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KVM: x86 emulator: Remove unused arg from read_descriptor()
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
6aa8b732 27
3eeb3288 28#include "x86.h"
38ba30ba 29#include "tss.h"
e99f0507 30
6aa8b732
AK		 31/*
32 * Opcode effective-address decode tables.
33 * Note that we only emulate instructions that have at least one memory
34 * operand (excluding implicit stack references). We assume that stack
35 * references and instruction fetches will never occur in special memory
36 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
37 * not be handled.
38 */
39
40/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 41#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 42/* Destination operand type. */
ab85b12b
AK		 43#define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
44#define DstReg (2<<1) /* Register operand. */
45#define DstMem (3<<1) /* Memory operand. */
46#define DstAcc (4<<1) /* Destination Accumulator */
47#define DstDI (5<<1) /* Destination is in ES:(E)DI */
48#define DstMem64 (6<<1) /* 64bit memory operand */
943858e2 49#define DstImmUByte (7<<1) /* 8-bit unsigned immediate operand */
ab85b12b 50#define DstMask (7<<1)
6aa8b732 51/* Source operand type. */
9c9fddd0 52#define SrcNone (0<<4) /* No source operand. */
9c9fddd0
GT		 53#define SrcReg (1<<4) /* Register operand. */
54#define SrcMem (2<<4) /* Memory operand. */
55#define SrcMem16 (3<<4) /* Memory operand (16-bit). */
56#define SrcMem32 (4<<4) /* Memory operand (32-bit). */
57#define SrcImm (5<<4) /* Immediate operand. */
58#define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
bfcadf83 59#define SrcOne (7<<4) /* Implied '1' */
341de7e3 60#define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */
c9eaf20f 61#define SrcImmU (9<<4) /* Immediate operand, unsigned */
a682e354 62#define SrcSI (0xa<<4) /* Source is in the DS:RSI */
414e6277
GN		 63#define SrcImmFAddr (0xb<<4) /* Source is immediate far address */
64#define SrcMemFAddr (0xc<<4) /* Source is far address in memory */
5d55f299 65#define SrcAcc (0xd<<4) /* Source Accumulator */
b250e605 66#define SrcImmU16 (0xe<<4) /* Immediate operand, unsigned, 16 bits */
341de7e3 67#define SrcMask (0xf<<4)
6aa8b732 68/* Generic ModRM decode. */
341de7e3 69#define ModRM (1<<8)
6aa8b732 70/* Destination is only written; never read. */
341de7e3
GN		 71#define Mov (1<<9)
72#define BitOp (1<<10)
73#define MemAbs (1<<11) /* Memory operand is absolute displacement */
9c9fddd0
GT		 74#define String (1<<12) /* String instruction (rep capable) */
75#define Stack (1<<13) /* Stack instruction (push/pop) */
46561646 76#define GroupMask (7<<14) /* Opcode uses one of the group mechanisms */
e09d082c 77#define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
46561646
AK		 78#define GroupDual (2<<14) /* Alternate decoding of mod == 3 */
79#define Prefix (3<<14) /* Instruction varies with 66/f2/f3 prefix */
80#define RMExt (4<<14) /* Opcode extension in ModRM r/m if mod == 3 */
1253791d 81#define Sse (1<<17) /* SSE Vector instruction */
d8769fed 82/* Misc flags */
8ea7d6ae 83#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
d867162c 84#define VendorSpecific (1<<22) /* Vendor specific instruction */
5a506b12 85#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 86#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 87#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 88#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 89#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 90#define No64 (1<<28)
0dc8d10f
GT		 91/* Source 2 operand type */
92#define Src2None (0<<29)
93#define Src2CL (1<<29)
94#define Src2ImmByte (2<<29)
95#define Src2One (3<<29)
7db41eb7 96#define Src2Imm (4<<29)
0dc8d10f 97#define Src2Mask (7<<29)
6aa8b732 98
d0e53325
AK		 99#define X2(x...) x, x
100#define X3(x...) X2(x), x
101#define X4(x...) X2(x), X2(x)
102#define X5(x...) X4(x), x
103#define X6(x...) X4(x), X2(x)
104#define X7(x...) X4(x), X3(x)
105#define X8(x...) X4(x), X4(x)
106#define X16(x...) X8(x), X8(x)
83babbca 107
d65b1dee
AK		 108struct opcode {
109 u32 flags;
c4f035c6 110 u8 intercept;
120df890 111 union {
ef65c889 112 int (*execute)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 113 struct opcode *group;
114 struct group_dual *gdual;
0d7cdee8 115 struct gprefix *gprefix;
120df890 116 } u;
d09beabd 117 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 118};
119
120struct group_dual {
121 struct opcode mod012[8];
122 struct opcode mod3[8];
d65b1dee
AK		 123};
124
0d7cdee8
AK		 125struct gprefix {
126 struct opcode pfx_no;
127 struct opcode pfx_66;
128 struct opcode pfx_f2;
129 struct opcode pfx_f3;
130};
131
6aa8b732 132/* EFLAGS bit definitions. */
d4c6a154
GN		 133#define EFLG_ID (1<<21)
134#define EFLG_VIP (1<<20)
135#define EFLG_VIF (1<<19)
136#define EFLG_AC (1<<18)
b1d86143
AP		 137#define EFLG_VM (1<<17)
138#define EFLG_RF (1<<16)
d4c6a154
GN		 139#define EFLG_IOPL (3<<12)
140#define EFLG_NT (1<<14)
6aa8b732
AK		 141#define EFLG_OF (1<<11)
142#define EFLG_DF (1<<10)
b1d86143 143#define EFLG_IF (1<<9)
d4c6a154 144#define EFLG_TF (1<<8)
6aa8b732
AK		 145#define EFLG_SF (1<<7)
146#define EFLG_ZF (1<<6)
147#define EFLG_AF (1<<4)
148#define EFLG_PF (1<<2)
149#define EFLG_CF (1<<0)
150
62bd430e
MG		 151#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
152#define EFLG_RESERVED_ONE_MASK 2
153
6aa8b732
AK		 154/*
155 * Instruction emulation:
156 * Most instructions are emulated directly via a fragment of inline assembly
157 * code. This allows us to save/restore EFLAGS and thus very easily pick up
158 * any modified flags.
159 */
160
05b3e0c2 161#if defined(CONFIG_X86_64)
6aa8b732
AK		 162#define _LO32 "k" /* force 32-bit operand */
163#define _STK "%%rsp" /* stack pointer */
164#elif defined(__i386__)
165#define _LO32 "" /* force 32-bit operand */
166#define _STK "%%esp" /* stack pointer */
167#endif
168
169/*
170 * These EFLAGS bits are restored from saved value during emulation, and
171 * any changes are written back to the saved value after emulation.
172 */
173#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
174
175/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 176#define _PRE_EFLAGS(_sav, _msk, _tmp) \
177 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
178 "movl %"_sav",%"_LO32 _tmp"; " \
179 "push %"_tmp"; " \
180 "push %"_tmp"; " \
181 "movl %"_msk",%"_LO32 _tmp"; " \
182 "andl %"_LO32 _tmp",("_STK"); " \
183 "pushf; " \
184 "notl %"_LO32 _tmp"; " \
185 "andl %"_LO32 _tmp",("_STK"); " \
186 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
187 "pop %"_tmp"; " \
188 "orl %"_LO32 _tmp",("_STK"); " \
189 "popf; " \
190 "pop %"_sav"; "
6aa8b732
AK		 191
192/* After executing instruction: write-back necessary bits in EFLAGS. */
193#define _POST_EFLAGS(_sav, _msk, _tmp) \
194 /* _sav |= EFLAGS & _msk; */ \
195 "pushf; " \
196 "pop %"_tmp"; " \
197 "andl %"_msk",%"_LO32 _tmp"; " \
198 "orl %"_LO32 _tmp",%"_sav"; "
199
dda96d8f
AK		 200#ifdef CONFIG_X86_64
201#define ON64(x) x
202#else
203#define ON64(x)
204#endif
205
b3b3d25a 206#define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix, _dsttype) \
6b7ad61f
AK		 207 do { \
208 __asm__ __volatile__ ( \
209 _PRE_EFLAGS("0", "4", "2") \
210 _op _suffix " %"_x"3,%1; " \
211 _POST_EFLAGS("0", "4", "2") \
fb2c2641 212 : "=m" (_eflags), "+q" (*(_dsttype*)&(_dst).val),\
6b7ad61f
AK		 213 "=&r" (_tmp) \
214 : _y ((_src).val), "i" (EFLAGS_MASK)); \
f3fd92fb 215 } while (0)
6b7ad61f
AK		 216
217
6aa8b732
AK		 218/* Raw emulation: instruction has two explicit operands. */
219#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 220 do { \
221 unsigned long _tmp; \
222 \
223 switch ((_dst).bytes) { \
224 case 2: \
b3b3d25a 225 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w",u16);\
6b7ad61f
AK		 226 break; \
227 case 4: \
b3b3d25a 228 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l",u32);\
6b7ad61f
AK		 229 break; \
230 case 8: \
b3b3d25a 231 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q",u64)); \
6b7ad61f
AK		 232 break; \
233 } \
6aa8b732
AK		 234 } while (0)
235
236#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
237 do { \
6b7ad61f 238 unsigned long _tmp; \
d77c26fc 239 switch ((_dst).bytes) { \
6aa8b732 240 case 1: \
b3b3d25a 241 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b",u8); \
6aa8b732
AK		 242 break; \
243 default: \
244 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
245 _wx, _wy, _lx, _ly, _qx, _qy); \
246 break; \
247 } \
248 } while (0)
249
250/* Source operand is byte-sized and may be restricted to just %cl. */
251#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
252 __emulate_2op(_op, _src, _dst, _eflags, \
253 "b", "c", "b", "c", "b", "c", "b", "c")
254
255/* Source operand is byte, word, long or quad sized. */
256#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
257 __emulate_2op(_op, _src, _dst, _eflags, \
258 "b", "q", "w", "r", _LO32, "r", "", "r")
259
260/* Source operand is word, long or quad sized. */
261#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
262 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
263 "w", "r", _LO32, "r", "", "r")
264
d175226a 265/* Instruction has three operands and one operand is stored in ECX register */
7295261c
AK		 266#define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
267 do { \
268 unsigned long _tmp; \
269 _type _clv = (_cl).val; \
270 _type _srcv = (_src).val; \
271 _type _dstv = (_dst).val; \
272 \
273 __asm__ __volatile__ ( \
274 _PRE_EFLAGS("0", "5", "2") \
275 _op _suffix " %4,%1 \n" \
276 _POST_EFLAGS("0", "5", "2") \
277 : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
278 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
279 ); \
280 \
281 (_cl).val = (unsigned long) _clv; \
282 (_src).val = (unsigned long) _srcv; \
283 (_dst).val = (unsigned long) _dstv; \
d175226a
GT		 284 } while (0)
285
7295261c
AK		 286#define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
287 do { \
288 switch ((_dst).bytes) { \
289 case 2: \
290 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
291 "w", unsigned short); \
292 break; \
293 case 4: \
294 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
295 "l", unsigned int); \
296 break; \
297 case 8: \
298 ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
299 "q", unsigned long)); \
300 break; \
301 } \
d175226a
GT		 302 } while (0)
303
dda96d8f 304#define __emulate_1op(_op, _dst, _eflags, _suffix) \
6aa8b732
AK		 305 do { \
306 unsigned long _tmp; \
307 \
dda96d8f
AK		 308 __asm__ __volatile__ ( \
309 _PRE_EFLAGS("0", "3", "2") \
310 _op _suffix " %1; " \
311 _POST_EFLAGS("0", "3", "2") \
312 : "=m" (_eflags), "+m" ((_dst).val), \
313 "=&r" (_tmp) \
314 : "i" (EFLAGS_MASK)); \
315 } while (0)
316
317/* Instruction has only one explicit operand (no source operand). */
318#define emulate_1op(_op, _dst, _eflags) \
319 do { \
d77c26fc 320 switch ((_dst).bytes) { \
dda96d8f
AK		 321 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
322 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
323 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
324 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
6aa8b732
AK		 325 } \
326 } while (0)
327
3f9f53b0
MG		 328#define __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, _suffix) \
329 do { \
330 unsigned long _tmp; \
331 \
332 __asm__ __volatile__ ( \
333 _PRE_EFLAGS("0", "4", "1") \
334 _op _suffix " %5; " \
335 _POST_EFLAGS("0", "4", "1") \
336 : "=m" (_eflags), "=&r" (_tmp), \
337 "+a" (_rax), "+d" (_rdx) \
338 : "i" (EFLAGS_MASK), "m" ((_src).val), \
339 "a" (_rax), "d" (_rdx)); \
340 } while (0)
341
f6b3597b
AK		 342#define __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, _eflags, _suffix, _ex) \
343 do { \
344 unsigned long _tmp; \
345 \
346 __asm__ __volatile__ ( \
347 _PRE_EFLAGS("0", "5", "1") \
348 "1: \n\t" \
349 _op _suffix " %6; " \
350 "2: \n\t" \
351 _POST_EFLAGS("0", "5", "1") \
352 ".pushsection .fixup,\"ax\" \n\t" \
353 "3: movb $1, %4 \n\t" \
354 "jmp 2b \n\t" \
355 ".popsection \n\t" \
356 _ASM_EXTABLE(1b, 3b) \
357 : "=m" (_eflags), "=&r" (_tmp), \
358 "+a" (_rax), "+d" (_rdx), "+qm"(_ex) \
359 : "i" (EFLAGS_MASK), "m" ((_src).val), \
360 "a" (_rax), "d" (_rdx)); \
361 } while (0)
362
3f9f53b0 363/* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
7295261c
AK		 364#define emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags) \
365 do { \
366 switch((_src).bytes) { \
367 case 1: \
368 __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, \
369 _eflags, "b"); \
370 break; \
371 case 2: \
372 __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, \
373 _eflags, "w"); \
374 break; \
375 case 4: \
376 __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, \
377 _eflags, "l"); \
378 break; \
379 case 8: \
380 ON64(__emulate_1op_rax_rdx(_op, _src, _rax, _rdx, \
381 _eflags, "q")); \
382 break; \
3f9f53b0
MG		 383 } \
384 } while (0)
385
f6b3597b
AK		 386#define emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, _eflags, _ex) \
387 do { \
388 switch((_src).bytes) { \
389 case 1: \
390 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
391 _eflags, "b", _ex); \
392 break; \
393 case 2: \
394 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
395 _eflags, "w", _ex); \
396 break; \
397 case 4: \
398 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
399 _eflags, "l", _ex); \
400 break; \
401 case 8: ON64( \
402 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
403 _eflags, "q", _ex)); \
404 break; \
405 } \
406 } while (0)
407
6aa8b732
AK		 408/* Fetch next part of the instruction being emulated. */
409#define insn_fetch(_type, _size, _eip) \
410({ unsigned long _x; \
62266869 411 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
af5b4f7f 412 if (rc != X86EMUL_CONTINUE) \
6aa8b732
AK		 413 goto done; \
414 (_eip) += (_size); \
415 (_type)_x; \
416})
417
7295261c 418#define insn_fetch_arr(_arr, _size, _eip) \
414e6277
GN		 419({ rc = do_insn_fetch(ctxt, ops, (_eip), _arr, (_size)); \
420 if (rc != X86EMUL_CONTINUE) \
421 goto done; \
422 (_eip) += (_size); \
423})
424
8a76d7f2
JR		 425static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
426 enum x86_intercept intercept,
427 enum x86_intercept_stage stage)
428{
429 struct x86_instruction_info info = {
430 .intercept = intercept,
431 .rep_prefix = ctxt->decode.rep_prefix,
432 .modrm_mod = ctxt->decode.modrm_mod,
433 .modrm_reg = ctxt->decode.modrm_reg,
434 .modrm_rm = ctxt->decode.modrm_rm,
435 .src_val = ctxt->decode.src.val64,
436 .src_bytes = ctxt->decode.src.bytes,
437 .dst_bytes = ctxt->decode.dst.bytes,
438 .ad_bytes = ctxt->decode.ad_bytes,
439 .next_rip = ctxt->eip,
440 };
441
2953538e 442 return ctxt->ops->intercept(ctxt, &info, stage);
8a76d7f2
JR		 443}
444
ddcb2885
HH		 445static inline unsigned long ad_mask(struct decode_cache *c)
446{
447 return (1UL << (c->ad_bytes << 3)) - 1;
448}
449
6aa8b732 450/* Access/update address held in a register, based on addressing mode. */
e4706772
HH		 451static inline unsigned long
452address_mask(struct decode_cache *c, unsigned long reg)
453{
454 if (c->ad_bytes == sizeof(unsigned long))
455 return reg;
456 else
457 return reg & ad_mask(c);
458}
459
460static inline unsigned long
90de84f5 461register_address(struct decode_cache *c, unsigned long reg)
e4706772 462{
90de84f5 463 return address_mask(c, reg);
e4706772
HH		 464}
465
7a957275
HH		 466static inline void
467register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
468{
469 if (c->ad_bytes == sizeof(unsigned long))
470 *reg += inc;
471 else
472 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
473}
6aa8b732 474
7a957275
HH		 475static inline void jmp_rel(struct decode_cache *c, int rel)
476{
477 register_address_increment(c, &c->eip, rel);
478}
098c937b 479
56697687
AK		 480static u32 desc_limit_scaled(struct desc_struct *desc)
481{
482 u32 limit = get_desc_limit(desc);
483
484 return desc->g ? (limit << 12) | 0xfff : limit;
485}
486
7a5b56df
AK		 487static void set_seg_override(struct decode_cache *c, int seg)
488{
489 c->has_seg_override = true;
490 c->seg_override = seg;
491}
492
79168fd1
GN		 493static unsigned long seg_base(struct x86_emulate_ctxt *ctxt,
494 struct x86_emulate_ops *ops, int seg)
7a5b56df
AK		 495{
496 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
497 return 0;
498
4bff1e86 499 return ops->get_cached_segment_base(ctxt, seg);
7a5b56df
AK		 500}
501
90de84f5 502static unsigned seg_override(struct x86_emulate_ctxt *ctxt,
90de84f5 503 struct decode_cache *c)
7a5b56df
AK		 504{
505 if (!c->has_seg_override)
506 return 0;
507
90de84f5 508 return c->seg_override;
7a5b56df
AK		 509}
510
35d3d4a1
AK		 511static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
512 u32 error, bool valid)
54b8486f 513{
da9cb575
AK		 514 ctxt->exception.vector = vec;
515 ctxt->exception.error_code = error;
516 ctxt->exception.error_code_valid = valid;
35d3d4a1 517 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 518}
519
3b88e41a
JR		 520static int emulate_db(struct x86_emulate_ctxt *ctxt)
521{
522 return emulate_exception(ctxt, DB_VECTOR, 0, false);
523}
524
35d3d4a1 525static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 526{
35d3d4a1 527 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 528}
529
618ff15d
AK		 530static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
531{
532 return emulate_exception(ctxt, SS_VECTOR, err, true);
533}
534
35d3d4a1 535static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 536{
35d3d4a1 537 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 538}
539
35d3d4a1 540static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 541{
35d3d4a1 542 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 543}
544
34d1f490
AK		 545static int emulate_de(struct x86_emulate_ctxt *ctxt)
546{
35d3d4a1 547 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 548}
549
1253791d
AK		 550static int emulate_nm(struct x86_emulate_ctxt *ctxt)
551{
552 return emulate_exception(ctxt, NM_VECTOR, 0, false);
553}
554
1aa36616
AK		 555static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
556{
557 u16 selector;
558 struct desc_struct desc;
559
560 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
561 return selector;
562}
563
564static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
565 unsigned seg)
566{
567 u16 dummy;
568 u32 base3;
569 struct desc_struct desc;
570
571 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
572 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
573}
574
3d9b938e 575static int __linearize(struct x86_emulate_ctxt *ctxt,
52fd8b44 576 struct segmented_address addr,
3d9b938e 577 unsigned size, bool write, bool fetch,
52fd8b44
AK		 578 ulong *linear)
579{
580 struct decode_cache *c = &ctxt->decode;
618ff15d
AK		 581 struct desc_struct desc;
582 bool usable;
52fd8b44 583 ulong la;
618ff15d 584 u32 lim;
1aa36616 585 u16 sel;
618ff15d 586 unsigned cpl, rpl;
52fd8b44
AK		 587
588 la = seg_base(ctxt, ctxt->ops, addr.seg) + addr.ea;
618ff15d
AK		 589 switch (ctxt->mode) {
590 case X86EMUL_MODE_REAL:
591 break;
592 case X86EMUL_MODE_PROT64:
593 if (((signed long)la << 16) >> 16 != la)
594 return emulate_gp(ctxt, 0);
595 break;
596 default:
1aa36616
AK		 597 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
598 addr.seg);
618ff15d
AK		 599 if (!usable)
600 goto bad;
601 /* code segment or read-only data segment */
602 if (((desc.type & 8) || !(desc.type & 2)) && write)
603 goto bad;
604 /* unreadable code segment */
3d9b938e 605 if (!fetch && (desc.type & 8) && !(desc.type & 2))
618ff15d
AK		 606 goto bad;
607 lim = desc_limit_scaled(&desc);
608 if ((desc.type & 8) || !(desc.type & 4)) {
609 /* expand-up segment */
610 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
611 goto bad;
612 } else {
613 /* exapand-down segment */
614 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
615 goto bad;
616 lim = desc.d ? 0xffffffff : 0xffff;
617 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
618 goto bad;
619 }
717746e3 620 cpl = ctxt->ops->cpl(ctxt);
1aa36616 621 rpl = sel & 3;
618ff15d
AK		 622 cpl = max(cpl, rpl);
623 if (!(desc.type & 8)) {
624 /* data segment */
625 if (cpl > desc.dpl)
626 goto bad;
627 } else if ((desc.type & 8) && !(desc.type & 4)) {
628 /* nonconforming code segment */
629 if (cpl != desc.dpl)
630 goto bad;
631 } else if ((desc.type & 8) && (desc.type & 4)) {
632 /* conforming code segment */
633 if (cpl < desc.dpl)
634 goto bad;
635 }
636 break;
637 }
3d9b938e 638 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : c->ad_bytes != 8)
52fd8b44
AK		 639 la &= (u32)-1;
640 *linear = la;
641 return X86EMUL_CONTINUE;
618ff15d
AK		 642bad:
643 if (addr.seg == VCPU_SREG_SS)
644 return emulate_ss(ctxt, addr.seg);
645 else
646 return emulate_gp(ctxt, addr.seg);
52fd8b44
AK		 647}
648
3d9b938e
NE		 649static int linearize(struct x86_emulate_ctxt *ctxt,
650 struct segmented_address addr,
651 unsigned size, bool write,
652 ulong *linear)
653{
654 return __linearize(ctxt, addr, size, write, false, linear);
655}
656
657
3ca3ac4d
AK		 658static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
659 struct segmented_address addr,
660 void *data,
661 unsigned size)
662{
9fa088f4
AK		 663 int rc;
664 ulong linear;
665
83b8795a 666 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 667 if (rc != X86EMUL_CONTINUE)
668 return rc;
0f65dd70 669 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
3ca3ac4d
AK		 670}
671
62266869
AK		 672static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
673 struct x86_emulate_ops *ops,
2fb53ad8 674 unsigned long eip, u8 *dest)
62266869
AK		 675{
676 struct fetch_cache *fc = &ctxt->decode.fetch;
677 int rc;
2fb53ad8 678 int size, cur_size;
62266869 679
2fb53ad8 680 if (eip == fc->end) {
3d9b938e
NE		 681 unsigned long linear;
682 struct segmented_address addr = { .seg=VCPU_SREG_CS, .ea=eip};
2fb53ad8
AK		 683 cur_size = fc->end - fc->start;
684 size = min(15UL - cur_size, PAGE_SIZE - offset_in_page(eip));
3d9b938e
NE		 685 rc = __linearize(ctxt, addr, size, false, true, &linear);
686 if (rc != X86EMUL_CONTINUE)
687 return rc;
0f65dd70
AK		 688 rc = ops->fetch(ctxt, linear, fc->data + cur_size,
689 size, &ctxt->exception);
3e2815e9 690 if (rc != X86EMUL_CONTINUE)
62266869 691 return rc;
2fb53ad8 692 fc->end += size;
62266869 693 }
2fb53ad8 694 *dest = fc->data[eip - fc->start];
3e2815e9 695 return X86EMUL_CONTINUE;
62266869
AK		 696}
697
698static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
699 struct x86_emulate_ops *ops,
700 unsigned long eip, void *dest, unsigned size)
701{
3e2815e9 702 int rc;
62266869 703
eb3c79e6 704 /* x86 instructions are limited to 15 bytes. */
063db061 705 if (eip + size - ctxt->eip > 15)
eb3c79e6 706 return X86EMUL_UNHANDLEABLE;
62266869
AK		 707 while (size--) {
708 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
3e2815e9 709 if (rc != X86EMUL_CONTINUE)
62266869
AK		 710 return rc;
711 }
3e2815e9 712 return X86EMUL_CONTINUE;
62266869
AK		 713}
714
1e3c5cb0
RR		 715/*
716 * Given the 'reg' portion of a ModRM byte, and a register block, return a
717 * pointer into the block that addresses the relevant register.
718 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
719 */
720static void *decode_register(u8 modrm_reg, unsigned long *regs,
721 int highbyte_regs)
6aa8b732
AK		 722{
723 void *p;
724
725 p = &regs[modrm_reg];
726 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
727 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
728 return p;
729}
730
731static int read_descriptor(struct x86_emulate_ctxt *ctxt,
90de84f5 732 struct segmented_address addr,
6aa8b732
AK		 733 u16 *size, unsigned long *address, int op_bytes)
734{
735 int rc;
736
737 if (op_bytes == 2)
738 op_bytes = 3;
739 *address = 0;
3ca3ac4d 740 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 741 if (rc != X86EMUL_CONTINUE)
6aa8b732 742 return rc;
30b31ab6 743 addr.ea += 2;
3ca3ac4d 744 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 745 return rc;
746}
747
bbe9abbd
NK		 748static int test_cc(unsigned int condition, unsigned int flags)
749{
750 int rc = 0;
751
752 switch ((condition & 15) >> 1) {
753 case 0: /* o */
754 rc |= (flags & EFLG_OF);
755 break;
756 case 1: /* b/c/nae */
757 rc |= (flags & EFLG_CF);
758 break;
759 case 2: /* z/e */
760 rc |= (flags & EFLG_ZF);
761 break;
762 case 3: /* be/na */
763 rc |= (flags & (EFLG_CF|EFLG_ZF));
764 break;
765 case 4: /* s */
766 rc |= (flags & EFLG_SF);
767 break;
768 case 5: /* p/pe */
769 rc |= (flags & EFLG_PF);
770 break;
771 case 7: /* le/ng */
772 rc |= (flags & EFLG_ZF);
773 /* fall through */
774 case 6: /* l/nge */
775 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
776 break;
777 }
778
779 /* Odd condition identifiers (lsb == 1) have inverted sense. */
780 return (!!rc ^ (condition & 1));
781}
782
91ff3cb4
AK		 783static void fetch_register_operand(struct operand *op)
784{
785 switch (op->bytes) {
786 case 1:
787 op->val = *(u8 *)op->addr.reg;
788 break;
789 case 2:
790 op->val = *(u16 *)op->addr.reg;
791 break;
792 case 4:
793 op->val = *(u32 *)op->addr.reg;
794 break;
795 case 8:
796 op->val = *(u64 *)op->addr.reg;
797 break;
798 }
799}
800
1253791d
AK		 801static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
802{
803 ctxt->ops->get_fpu(ctxt);
804 switch (reg) {
805 case 0: asm("movdqu %%xmm0, %0" : "=m"(*data)); break;
806 case 1: asm("movdqu %%xmm1, %0" : "=m"(*data)); break;
807 case 2: asm("movdqu %%xmm2, %0" : "=m"(*data)); break;
808 case 3: asm("movdqu %%xmm3, %0" : "=m"(*data)); break;
809 case 4: asm("movdqu %%xmm4, %0" : "=m"(*data)); break;
810 case 5: asm("movdqu %%xmm5, %0" : "=m"(*data)); break;
811 case 6: asm("movdqu %%xmm6, %0" : "=m"(*data)); break;
812 case 7: asm("movdqu %%xmm7, %0" : "=m"(*data)); break;
813#ifdef CONFIG_X86_64
814 case 8: asm("movdqu %%xmm8, %0" : "=m"(*data)); break;
815 case 9: asm("movdqu %%xmm9, %0" : "=m"(*data)); break;
816 case 10: asm("movdqu %%xmm10, %0" : "=m"(*data)); break;
817 case 11: asm("movdqu %%xmm11, %0" : "=m"(*data)); break;
818 case 12: asm("movdqu %%xmm12, %0" : "=m"(*data)); break;
819 case 13: asm("movdqu %%xmm13, %0" : "=m"(*data)); break;
820 case 14: asm("movdqu %%xmm14, %0" : "=m"(*data)); break;
821 case 15: asm("movdqu %%xmm15, %0" : "=m"(*data)); break;
822#endif
823 default: BUG();
824 }
825 ctxt->ops->put_fpu(ctxt);
826}
827
828static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
829 int reg)
830{
831 ctxt->ops->get_fpu(ctxt);
832 switch (reg) {
833 case 0: asm("movdqu %0, %%xmm0" : : "m"(*data)); break;
834 case 1: asm("movdqu %0, %%xmm1" : : "m"(*data)); break;
835 case 2: asm("movdqu %0, %%xmm2" : : "m"(*data)); break;
836 case 3: asm("movdqu %0, %%xmm3" : : "m"(*data)); break;
837 case 4: asm("movdqu %0, %%xmm4" : : "m"(*data)); break;
838 case 5: asm("movdqu %0, %%xmm5" : : "m"(*data)); break;
839 case 6: asm("movdqu %0, %%xmm6" : : "m"(*data)); break;
840 case 7: asm("movdqu %0, %%xmm7" : : "m"(*data)); break;
841#ifdef CONFIG_X86_64
842 case 8: asm("movdqu %0, %%xmm8" : : "m"(*data)); break;
843 case 9: asm("movdqu %0, %%xmm9" : : "m"(*data)); break;
844 case 10: asm("movdqu %0, %%xmm10" : : "m"(*data)); break;
845 case 11: asm("movdqu %0, %%xmm11" : : "m"(*data)); break;
846 case 12: asm("movdqu %0, %%xmm12" : : "m"(*data)); break;
847 case 13: asm("movdqu %0, %%xmm13" : : "m"(*data)); break;
848 case 14: asm("movdqu %0, %%xmm14" : : "m"(*data)); break;
849 case 15: asm("movdqu %0, %%xmm15" : : "m"(*data)); break;
850#endif
851 default: BUG();
852 }
853 ctxt->ops->put_fpu(ctxt);
854}
855
856static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
857 struct operand *op,
3c118e24 858 struct decode_cache *c,
3c118e24
AK		 859 int inhibit_bytereg)
860{
33615aa9 861 unsigned reg = c->modrm_reg;
9f1ef3f8 862 int highbyte_regs = c->rex_prefix == 0;
33615aa9
AK		 863
864 if (!(c->d & ModRM))
865 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
1253791d
AK		 866
867 if (c->d & Sse) {
868 op->type = OP_XMM;
869 op->bytes = 16;
870 op->addr.xmm = reg;
871 read_sse_reg(ctxt, &op->vec_val, reg);
872 return;
873 }
874
3c118e24
AK		 875 op->type = OP_REG;
876 if ((c->d & ByteOp) && !inhibit_bytereg) {
1a6440ae 877 op->addr.reg = decode_register(reg, c->regs, highbyte_regs);
3c118e24
AK		 878 op->bytes = 1;
879 } else {
1a6440ae 880 op->addr.reg = decode_register(reg, c->regs, 0);
3c118e24 881 op->bytes = c->op_bytes;
3c118e24 882 }
91ff3cb4 883 fetch_register_operand(op);
3c118e24
AK		 884 op->orig_val = op->val;
885}
886
1c73ef66 887static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7
AK		 888 struct x86_emulate_ops *ops,
889 struct operand *op)
1c73ef66
AK		 890{
891 struct decode_cache *c = &ctxt->decode;
892 u8 sib;
f5b4edcd 893 int index_reg = 0, base_reg = 0, scale;
3e2815e9 894 int rc = X86EMUL_CONTINUE;
2dbd0dd7 895 ulong modrm_ea = 0;
1c73ef66
AK		 896
897 if (c->rex_prefix) {
898 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
899 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
900 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
901 }
902
903 c->modrm = insn_fetch(u8, 1, c->eip);
904 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
905 c->modrm_reg |= (c->modrm & 0x38) >> 3;
906 c->modrm_rm |= (c->modrm & 0x07);
09ee57cd 907 c->modrm_seg = VCPU_SREG_DS;
1c73ef66
AK		 908
909 if (c->modrm_mod == 3) {
2dbd0dd7
AK		 910 op->type = OP_REG;
911 op->bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
912 op->addr.reg = decode_register(c->modrm_rm,
107d6d2e 913 c->regs, c->d & ByteOp);
1253791d
AK		 914 if (c->d & Sse) {
915 op->type = OP_XMM;
916 op->bytes = 16;
917 op->addr.xmm = c->modrm_rm;
918 read_sse_reg(ctxt, &op->vec_val, c->modrm_rm);
919 return rc;
920 }
2dbd0dd7 921 fetch_register_operand(op);
1c73ef66
AK		 922 return rc;
923 }
924
2dbd0dd7
AK		 925 op->type = OP_MEM;
926
1c73ef66
AK		 927 if (c->ad_bytes == 2) {
928 unsigned bx = c->regs[VCPU_REGS_RBX];
929 unsigned bp = c->regs[VCPU_REGS_RBP];
930 unsigned si = c->regs[VCPU_REGS_RSI];
931 unsigned di = c->regs[VCPU_REGS_RDI];
932
933 /* 16-bit ModR/M decode. */
934 switch (c->modrm_mod) {
935 case 0:
936 if (c->modrm_rm == 6)
2dbd0dd7 937 modrm_ea += insn_fetch(u16, 2, c->eip);
1c73ef66
AK		 938 break;
939 case 1:
2dbd0dd7 940 modrm_ea += insn_fetch(s8, 1, c->eip);
1c73ef66
AK		 941 break;
942 case 2:
2dbd0dd7 943 modrm_ea += insn_fetch(u16, 2, c->eip);
1c73ef66
AK		 944 break;
945 }
946 switch (c->modrm_rm) {
947 case 0:
2dbd0dd7 948 modrm_ea += bx + si;
1c73ef66
AK		 949 break;
950 case 1:
2dbd0dd7 951 modrm_ea += bx + di;
1c73ef66
AK		 952 break;
953 case 2:
2dbd0dd7 954 modrm_ea += bp + si;
1c73ef66
AK		 955 break;
956 case 3:
2dbd0dd7 957 modrm_ea += bp + di;
1c73ef66
AK		 958 break;
959 case 4:
2dbd0dd7 960 modrm_ea += si;
1c73ef66
AK		 961 break;
962 case 5:
2dbd0dd7 963 modrm_ea += di;
1c73ef66
AK		 964 break;
965 case 6:
966 if (c->modrm_mod != 0)
2dbd0dd7 967 modrm_ea += bp;
1c73ef66
AK		 968 break;
969 case 7:
2dbd0dd7 970 modrm_ea += bx;
1c73ef66
AK		 971 break;
972 }
973 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
974 (c->modrm_rm == 6 && c->modrm_mod != 0))
09ee57cd 975 c->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 976 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 977 } else {
978 /* 32/64-bit ModR/M decode. */
84411d85 979 if ((c->modrm_rm & 7) == 4) {
1c73ef66
AK		 980 sib = insn_fetch(u8, 1, c->eip);
981 index_reg |= (sib >> 3) & 7;
982 base_reg |= sib & 7;
983 scale = sib >> 6;
984
dc71d0f1 985 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
2dbd0dd7 986 modrm_ea += insn_fetch(s32, 4, c->eip);
dc71d0f1 987 else
2dbd0dd7 988 modrm_ea += c->regs[base_reg];
dc71d0f1 989 if (index_reg != 4)
2dbd0dd7 990 modrm_ea += c->regs[index_reg] << scale;
84411d85
AK		 991 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
992 if (ctxt->mode == X86EMUL_MODE_PROT64)
f5b4edcd 993 c->rip_relative = 1;
84411d85 994 } else
2dbd0dd7 995 modrm_ea += c->regs[c->modrm_rm];
1c73ef66
AK		 996 switch (c->modrm_mod) {
997 case 0:
998 if (c->modrm_rm == 5)
2dbd0dd7 999 modrm_ea += insn_fetch(s32, 4, c->eip);
1c73ef66
AK		 1000 break;
1001 case 1:
2dbd0dd7 1002 modrm_ea += insn_fetch(s8, 1, c->eip);
1c73ef66
AK		 1003 break;
1004 case 2:
2dbd0dd7 1005 modrm_ea += insn_fetch(s32, 4, c->eip);
1c73ef66
AK		 1006 break;
1007 }
1008 }
90de84f5 1009 op->addr.mem.ea = modrm_ea;
1c73ef66
AK		 1010done:
1011 return rc;
1012}
1013
1014static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7
AK		 1015 struct x86_emulate_ops *ops,
1016 struct operand *op)
1c73ef66
AK		 1017{
1018 struct decode_cache *c = &ctxt->decode;
3e2815e9 1019 int rc = X86EMUL_CONTINUE;
1c73ef66 1020
2dbd0dd7 1021 op->type = OP_MEM;
1c73ef66
AK		 1022 switch (c->ad_bytes) {
1023 case 2:
90de84f5 1024 op->addr.mem.ea = insn_fetch(u16, 2, c->eip);
1c73ef66
AK		 1025 break;
1026 case 4:
90de84f5 1027 op->addr.mem.ea = insn_fetch(u32, 4, c->eip);
1c73ef66
AK		 1028 break;
1029 case 8:
90de84f5 1030 op->addr.mem.ea = insn_fetch(u64, 8, c->eip);
1c73ef66
AK		 1031 break;
1032 }
1033done:
1034 return rc;
1035}
1036
35c843c4
WY		 1037static void fetch_bit_operand(struct decode_cache *c)
1038{
7129eeca 1039 long sv = 0, mask;
35c843c4 1040
3885f18f 1041 if (c->dst.type == OP_MEM && c->src.type == OP_REG) {
35c843c4
WY		 1042 mask = ~(c->dst.bytes * 8 - 1);
1043
1044 if (c->src.bytes == 2)
1045 sv = (s16)c->src.val & (s16)mask;
1046 else if (c->src.bytes == 4)
1047 sv = (s32)c->src.val & (s32)mask;
1048
90de84f5 1049 c->dst.addr.mem.ea += (sv >> 3);
35c843c4 1050 }
ba7ff2b7
WY		 1051
1052 /* only subword offset */
1053 c->src.val &= (c->dst.bytes << 3) - 1;
35c843c4
WY		 1054}
1055
dde7e6d1
AK		 1056static int read_emulated(struct x86_emulate_ctxt *ctxt,
1057 struct x86_emulate_ops *ops,
1058 unsigned long addr, void *dest, unsigned size)
6aa8b732 1059{
dde7e6d1
AK		 1060 int rc;
1061 struct read_cache *mc = &ctxt->decode.mem_read;
6aa8b732 1062
dde7e6d1
AK		 1063 while (size) {
1064 int n = min(size, 8u);
1065 size -= n;
1066 if (mc->pos < mc->end)
1067 goto read_cached;
5cd21917 1068
0f65dd70
AK		 1069 rc = ops->read_emulated(ctxt, addr, mc->data + mc->end, n,
1070 &ctxt->exception);
dde7e6d1
AK		 1071 if (rc != X86EMUL_CONTINUE)
1072 return rc;
1073 mc->end += n;
6aa8b732 1074
dde7e6d1
AK		 1075 read_cached:
1076 memcpy(dest, mc->data + mc->pos, n);
1077 mc->pos += n;
1078 dest += n;
1079 addr += n;
6aa8b732 1080 }
dde7e6d1
AK		 1081 return X86EMUL_CONTINUE;
1082}
6aa8b732 1083
3ca3ac4d
AK		 1084static int segmented_read(struct x86_emulate_ctxt *ctxt,
1085 struct segmented_address addr,
1086 void *data,
1087 unsigned size)
1088{
9fa088f4
AK		 1089 int rc;
1090 ulong linear;
1091
83b8795a 1092 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1093 if (rc != X86EMUL_CONTINUE)
1094 return rc;
1095 return read_emulated(ctxt, ctxt->ops, linear, data, size);
3ca3ac4d
AK		 1096}
1097
1098static int segmented_write(struct x86_emulate_ctxt *ctxt,
1099 struct segmented_address addr,
1100 const void *data,
1101 unsigned size)
1102{
9fa088f4
AK		 1103 int rc;
1104 ulong linear;
1105
83b8795a 1106 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1107 if (rc != X86EMUL_CONTINUE)
1108 return rc;
0f65dd70
AK		 1109 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1110 &ctxt->exception);
3ca3ac4d
AK		 1111}
1112
1113static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1114 struct segmented_address addr,
1115 const void *orig_data, const void *data,
1116 unsigned size)
1117{
9fa088f4
AK		 1118 int rc;
1119 ulong linear;
1120
83b8795a 1121 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1122 if (rc != X86EMUL_CONTINUE)
1123 return rc;
0f65dd70
AK		 1124 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1125 size, &ctxt->exception);
3ca3ac4d
AK		 1126}
1127
dde7e6d1
AK		 1128static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
1129 struct x86_emulate_ops *ops,
1130 unsigned int size, unsigned short port,
1131 void *dest)
1132{
1133 struct read_cache *rc = &ctxt->decode.io_read;
b4c6abfe 1134
dde7e6d1
AK		 1135 if (rc->pos == rc->end) { /* refill pio read ahead */
1136 struct decode_cache *c = &ctxt->decode;
1137 unsigned int in_page, n;
1138 unsigned int count = c->rep_prefix ?
1139 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1;
1140 in_page = (ctxt->eflags & EFLG_DF) ?
1141 offset_in_page(c->regs[VCPU_REGS_RDI]) :
1142 PAGE_SIZE - offset_in_page(c->regs[VCPU_REGS_RDI]);
1143 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1144 count);
1145 if (n == 0)
1146 n = 1;
1147 rc->pos = rc->end = 0;
ca1d4a9e 1148 if (!ops->pio_in_emulated(ctxt, size, port, rc->data, n))
dde7e6d1
AK		 1149 return 0;
1150 rc->end = n * size;
6aa8b732
AK		 1151 }
1152
dde7e6d1
AK		 1153 memcpy(dest, rc->data + rc->pos, size);
1154 rc->pos += size;
1155 return 1;
1156}
6aa8b732 1157
dde7e6d1
AK		 1158static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
1159 struct x86_emulate_ops *ops,
1160 u16 selector, struct desc_ptr *dt)
1161{
1162 if (selector & 1 << 2) {
1163 struct desc_struct desc;
1aa36616
AK		 1164 u16 sel;
1165
dde7e6d1 1166 memset (dt, 0, sizeof *dt);
1aa36616 1167 if (!ops->get_segment(ctxt, &sel, &desc, NULL, VCPU_SREG_LDTR))
dde7e6d1 1168 return;
e09d082c 1169
dde7e6d1
AK		 1170 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1171 dt->address = get_desc_base(&desc);
1172 } else
4bff1e86 1173 ops->get_gdt(ctxt, dt);
dde7e6d1 1174}
120df890 1175
dde7e6d1
AK		 1176/* allowed just for 8 bytes segments */
1177static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1178 struct x86_emulate_ops *ops,
1179 u16 selector, struct desc_struct *desc)
1180{
1181 struct desc_ptr dt;
1182 u16 index = selector >> 3;
1183 int ret;
dde7e6d1 1184 ulong addr;
120df890 1185
dde7e6d1 1186 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
120df890 1187
35d3d4a1
AK		 1188 if (dt.size < index * 8 + 7)
1189 return emulate_gp(ctxt, selector & 0xfffc);
dde7e6d1 1190 addr = dt.address + index * 8;
0f65dd70 1191 ret = ops->read_std(ctxt, addr, desc, sizeof *desc, &ctxt->exception);
e09d082c 1192
dde7e6d1
AK		 1193 return ret;
1194}
ef65c889 1195
dde7e6d1
AK		 1196/* allowed just for 8 bytes segments */
1197static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1198 struct x86_emulate_ops *ops,
1199 u16 selector, struct desc_struct *desc)
1200{
1201 struct desc_ptr dt;
1202 u16 index = selector >> 3;
dde7e6d1
AK		 1203 ulong addr;
1204 int ret;
6aa8b732 1205
dde7e6d1 1206 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
6e3d5dfb 1207
35d3d4a1
AK		 1208 if (dt.size < index * 8 + 7)
1209 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1210
dde7e6d1 1211 addr = dt.address + index * 8;
0f65dd70 1212 ret = ops->write_std(ctxt, addr, desc, sizeof *desc, &ctxt->exception);
c7e75a3d 1213
dde7e6d1
AK		 1214 return ret;
1215}
c7e75a3d 1216
5601d05b 1217/* Does not support long mode */
dde7e6d1
AK		 1218static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1219 struct x86_emulate_ops *ops,
1220 u16 selector, int seg)
1221{
1222 struct desc_struct seg_desc;
1223 u8 dpl, rpl, cpl;
1224 unsigned err_vec = GP_VECTOR;
1225 u32 err_code = 0;
1226 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
1227 int ret;
69f55cb1 1228
dde7e6d1 1229 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1230
dde7e6d1
AK		 1231 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
1232 || ctxt->mode == X86EMUL_MODE_REAL) {
1233 /* set real mode segment descriptor */
1234 set_desc_base(&seg_desc, selector << 4);
1235 set_desc_limit(&seg_desc, 0xffff);
1236 seg_desc.type = 3;
1237 seg_desc.p = 1;
1238 seg_desc.s = 1;
1239 goto load;
1240 }
1241
1242 /* NULL selector is not valid for TR, CS and SS */
1243 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
1244 && null_selector)
1245 goto exception;
1246
1247 /* TR should be in GDT only */
1248 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1249 goto exception;
1250
1251 if (null_selector) /* for NULL selector skip all following checks */
1252 goto load;
1253
1254 ret = read_segment_descriptor(ctxt, ops, selector, &seg_desc);
1255 if (ret != X86EMUL_CONTINUE)
1256 return ret;
1257
1258 err_code = selector & 0xfffc;
1259 err_vec = GP_VECTOR;
1260
1261 /* can't load system descriptor into segment selecor */
1262 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1263 goto exception;
1264
1265 if (!seg_desc.p) {
1266 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1267 goto exception;
1268 }
1269
1270 rpl = selector & 3;
1271 dpl = seg_desc.dpl;
717746e3 1272 cpl = ops->cpl(ctxt);
dde7e6d1
AK		 1273
1274 switch (seg) {
1275 case VCPU_SREG_SS:
1276 /*
1277 * segment is not a writable data segment or segment
1278 * selector's RPL != CPL or segment selector's RPL != CPL
1279 */
1280 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1281 goto exception;
6aa8b732 1282 break;
dde7e6d1
AK		 1283 case VCPU_SREG_CS:
1284 if (!(seg_desc.type & 8))
1285 goto exception;
1286
1287 if (seg_desc.type & 4) {
1288 /* conforming */
1289 if (dpl > cpl)
1290 goto exception;
1291 } else {
1292 /* nonconforming */
1293 if (rpl > cpl || dpl != cpl)
1294 goto exception;
1295 }
1296 /* CS(RPL) <- CPL */
1297 selector = (selector & 0xfffc) | cpl;
6aa8b732 1298 break;
dde7e6d1
AK		 1299 case VCPU_SREG_TR:
1300 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1301 goto exception;
1302 break;
1303 case VCPU_SREG_LDTR:
1304 if (seg_desc.s || seg_desc.type != 2)
1305 goto exception;
1306 break;
1307 default: /* DS, ES, FS, or GS */
4e62417b 1308 /*
dde7e6d1
AK		 1309 * segment is not a data or readable code segment or
1310 * ((segment is a data or nonconforming code segment)
1311 * and (both RPL and CPL > DPL))
4e62417b 1312 */
dde7e6d1
AK		 1313 if ((seg_desc.type & 0xa) == 0x8 ||
1314 (((seg_desc.type & 0xc) != 0xc) &&
1315 (rpl > dpl && cpl > dpl)))
1316 goto exception;
6aa8b732 1317 break;
dde7e6d1
AK		 1318 }
1319
1320 if (seg_desc.s) {
1321 /* mark segment as accessed */
1322 seg_desc.type |= 1;
1323 ret = write_segment_descriptor(ctxt, ops, selector, &seg_desc);
1324 if (ret != X86EMUL_CONTINUE)
1325 return ret;
1326 }
1327load:
1aa36616 1328 ops->set_segment(ctxt, selector, &seg_desc, 0, seg);
dde7e6d1
AK		 1329 return X86EMUL_CONTINUE;
1330exception:
1331 emulate_exception(ctxt, err_vec, err_code, true);
1332 return X86EMUL_PROPAGATE_FAULT;
1333}
1334
31be40b3
WY		 1335static void write_register_operand(struct operand *op)
1336{
1337 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1338 switch (op->bytes) {
1339 case 1:
1340 *(u8 *)op->addr.reg = (u8)op->val;
1341 break;
1342 case 2:
1343 *(u16 *)op->addr.reg = (u16)op->val;
1344 break;
1345 case 4:
1346 *op->addr.reg = (u32)op->val;
1347 break; /* 64b: zero-extend */
1348 case 8:
1349 *op->addr.reg = op->val;
1350 break;
1351 }
1352}
1353
dde7e6d1
AK		 1354static inline int writeback(struct x86_emulate_ctxt *ctxt,
1355 struct x86_emulate_ops *ops)
1356{
1357 int rc;
1358 struct decode_cache *c = &ctxt->decode;
dde7e6d1
AK		 1359
1360 switch (c->dst.type) {
1361 case OP_REG:
31be40b3 1362 write_register_operand(&c->dst);
6aa8b732 1363 break;
dde7e6d1
AK		 1364 case OP_MEM:
1365 if (c->lock_prefix)
3ca3ac4d
AK		 1366 rc = segmented_cmpxchg(ctxt,
1367 c->dst.addr.mem,
1368 &c->dst.orig_val,
1369 &c->dst.val,
1370 c->dst.bytes);
341de7e3 1371 else
3ca3ac4d
AK		 1372 rc = segmented_write(ctxt,
1373 c->dst.addr.mem,
1374 &c->dst.val,
1375 c->dst.bytes);
dde7e6d1
AK		 1376 if (rc != X86EMUL_CONTINUE)
1377 return rc;
a682e354 1378 break;
1253791d
AK		 1379 case OP_XMM:
1380 write_sse_reg(ctxt, &c->dst.vec_val, c->dst.addr.xmm);
1381 break;
dde7e6d1
AK		 1382 case OP_NONE:
1383 /* no writeback */
414e6277 1384 break;
dde7e6d1 1385 default:
414e6277 1386 break;
6aa8b732 1387 }
dde7e6d1
AK		 1388 return X86EMUL_CONTINUE;
1389}
6aa8b732 1390
4487b3b4 1391static int em_push(struct x86_emulate_ctxt *ctxt)
dde7e6d1
AK		 1392{
1393 struct decode_cache *c = &ctxt->decode;
4179bb02 1394 struct segmented_address addr;
0dc8d10f 1395
dde7e6d1 1396 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
4179bb02
TY		 1397 addr.ea = register_address(c, c->regs[VCPU_REGS_RSP]);
1398 addr.seg = VCPU_SREG_SS;
1399
1400 /* Disable writeback. */
1401 c->dst.type = OP_NONE;
1402 return segmented_write(ctxt, addr, &c->src.val, c->op_bytes);
dde7e6d1 1403}
69f55cb1 1404
dde7e6d1
AK		 1405static int emulate_pop(struct x86_emulate_ctxt *ctxt,
1406 struct x86_emulate_ops *ops,
1407 void *dest, int len)
1408{
1409 struct decode_cache *c = &ctxt->decode;
1410 int rc;
90de84f5 1411 struct segmented_address addr;
8b4caf66 1412
90de84f5
AK		 1413 addr.ea = register_address(c, c->regs[VCPU_REGS_RSP]);
1414 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1415 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1416 if (rc != X86EMUL_CONTINUE)
1417 return rc;
1418
1419 register_address_increment(c, &c->regs[VCPU_REGS_RSP], len);
1420 return rc;
8b4caf66
LV		 1421}
1422
c54fe504
TY		 1423static int em_pop(struct x86_emulate_ctxt *ctxt)
1424{
1425 struct decode_cache *c = &ctxt->decode;
1426
1427 return emulate_pop(ctxt, ctxt->ops, &c->dst.val, c->op_bytes);
1428}
1429
dde7e6d1
AK		 1430static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1431 struct x86_emulate_ops *ops,
1432 void *dest, int len)
9de41573
GN		 1433{
1434 int rc;
dde7e6d1
AK		 1435 unsigned long val, change_mask;
1436 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
717746e3 1437 int cpl = ops->cpl(ctxt);
9de41573 1438
dde7e6d1
AK		 1439 rc = emulate_pop(ctxt, ops, &val, len);
1440 if (rc != X86EMUL_CONTINUE)
1441 return rc;
9de41573 1442
dde7e6d1
AK		 1443 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1444 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
9de41573 1445
dde7e6d1
AK		 1446 switch(ctxt->mode) {
1447 case X86EMUL_MODE_PROT64:
1448 case X86EMUL_MODE_PROT32:
1449 case X86EMUL_MODE_PROT16:
1450 if (cpl == 0)
1451 change_mask |= EFLG_IOPL;
1452 if (cpl <= iopl)
1453 change_mask |= EFLG_IF;
1454 break;
1455 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1456 if (iopl < 3)
1457 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1458 change_mask |= EFLG_IF;
1459 break;
1460 default: /* real mode */
1461 change_mask |= (EFLG_IOPL | EFLG_IF);
1462 break;
9de41573 1463 }
dde7e6d1
AK		 1464
1465 *(unsigned long *)dest =
1466 (ctxt->eflags & ~change_mask) | (val & change_mask);
1467
1468 return rc;
9de41573
GN		 1469}
1470
62aaa2f0
TY		 1471static int em_popf(struct x86_emulate_ctxt *ctxt)
1472{
1473 struct decode_cache *c = &ctxt->decode;
1474
1475 c->dst.type = OP_REG;
1476 c->dst.addr.reg = &ctxt->eflags;
1477 c->dst.bytes = c->op_bytes;
1478 return emulate_popf(ctxt, ctxt->ops, &c->dst.val, c->op_bytes);
1479}
1480
4179bb02
TY		 1481static int emulate_push_sreg(struct x86_emulate_ctxt *ctxt,
1482 struct x86_emulate_ops *ops, int seg)
7b262e90 1483{
dde7e6d1 1484 struct decode_cache *c = &ctxt->decode;
7b262e90 1485
1aa36616 1486 c->src.val = get_segment_selector(ctxt, seg);
7b262e90 1487
4487b3b4 1488 return em_push(ctxt);
7b262e90
GN		 1489}
1490
dde7e6d1
AK		 1491static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt,
1492 struct x86_emulate_ops *ops, int seg)
38ba30ba 1493{
dde7e6d1
AK		 1494 struct decode_cache *c = &ctxt->decode;
1495 unsigned long selector;
1496 int rc;
38ba30ba 1497
dde7e6d1
AK		 1498 rc = emulate_pop(ctxt, ops, &selector, c->op_bytes);
1499 if (rc != X86EMUL_CONTINUE)
1500 return rc;
1501
1502 rc = load_segment_descriptor(ctxt, ops, (u16)selector, seg);
1503 return rc;
38ba30ba
GN		 1504}
1505
b96a7fad 1506static int em_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1507{
dde7e6d1
AK		 1508 struct decode_cache *c = &ctxt->decode;
1509 unsigned long old_esp = c->regs[VCPU_REGS_RSP];
1510 int rc = X86EMUL_CONTINUE;
1511 int reg = VCPU_REGS_RAX;
38ba30ba 1512
dde7e6d1
AK		 1513 while (reg <= VCPU_REGS_RDI) {
1514 (reg == VCPU_REGS_RSP) ?
1515 (c->src.val = old_esp) : (c->src.val = c->regs[reg]);
38ba30ba 1516
4487b3b4 1517 rc = em_push(ctxt);
dde7e6d1
AK		 1518 if (rc != X86EMUL_CONTINUE)
1519 return rc;
38ba30ba 1520
dde7e6d1 1521 ++reg;
38ba30ba 1522 }
38ba30ba 1523
dde7e6d1 1524 return rc;
38ba30ba
GN		 1525}
1526
62aaa2f0
TY		 1527static int em_pushf(struct x86_emulate_ctxt *ctxt)
1528{
1529 struct decode_cache *c = &ctxt->decode;
1530
1531 c->src.val = (unsigned long)ctxt->eflags;
1532 return em_push(ctxt);
1533}
1534
b96a7fad 1535static int em_popa(struct x86_emulate_ctxt *ctxt)
38ba30ba 1536{
dde7e6d1
AK		 1537 struct decode_cache *c = &ctxt->decode;
1538 int rc = X86EMUL_CONTINUE;
1539 int reg = VCPU_REGS_RDI;
38ba30ba 1540
dde7e6d1
AK		 1541 while (reg >= VCPU_REGS_RAX) {
1542 if (reg == VCPU_REGS_RSP) {
1543 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
1544 c->op_bytes);
1545 --reg;
1546 }
38ba30ba 1547
b96a7fad 1548 rc = emulate_pop(ctxt, ctxt->ops, &c->regs[reg], c->op_bytes);
dde7e6d1
AK		 1549 if (rc != X86EMUL_CONTINUE)
1550 break;
1551 --reg;
38ba30ba 1552 }
dde7e6d1 1553 return rc;
38ba30ba
GN		 1554}
1555
6e154e56
MG		 1556int emulate_int_real(struct x86_emulate_ctxt *ctxt,
1557 struct x86_emulate_ops *ops, int irq)
1558{
1559 struct decode_cache *c = &ctxt->decode;
5c56e1cf 1560 int rc;
6e154e56
MG		 1561 struct desc_ptr dt;
1562 gva_t cs_addr;
1563 gva_t eip_addr;
1564 u16 cs, eip;
6e154e56
MG		 1565
1566 /* TODO: Add limit checks */
1567 c->src.val = ctxt->eflags;
4487b3b4 1568 rc = em_push(ctxt);
5c56e1cf
AK		 1569 if (rc != X86EMUL_CONTINUE)
1570 return rc;
6e154e56
MG		 1571
1572 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1573
1aa36616 1574 c->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
4487b3b4 1575 rc = em_push(ctxt);
5c56e1cf
AK		 1576 if (rc != X86EMUL_CONTINUE)
1577 return rc;
6e154e56
MG		 1578
1579 c->src.val = c->eip;
4487b3b4 1580 rc = em_push(ctxt);
5c56e1cf
AK		 1581 if (rc != X86EMUL_CONTINUE)
1582 return rc;
1583
4bff1e86 1584 ops->get_idt(ctxt, &dt);
6e154e56
MG		 1585
1586 eip_addr = dt.address + (irq << 2);
1587 cs_addr = dt.address + (irq << 2) + 2;
1588
0f65dd70 1589 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
6e154e56
MG		 1590 if (rc != X86EMUL_CONTINUE)
1591 return rc;
1592
0f65dd70 1593 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
6e154e56
MG		 1594 if (rc != X86EMUL_CONTINUE)
1595 return rc;
1596
1597 rc = load_segment_descriptor(ctxt, ops, cs, VCPU_SREG_CS);
1598 if (rc != X86EMUL_CONTINUE)
1599 return rc;
1600
1601 c->eip = eip;
1602
1603 return rc;
1604}
1605
1606static int emulate_int(struct x86_emulate_ctxt *ctxt,
1607 struct x86_emulate_ops *ops, int irq)
1608{
1609 switch(ctxt->mode) {
1610 case X86EMUL_MODE_REAL:
1611 return emulate_int_real(ctxt, ops, irq);
1612 case X86EMUL_MODE_VM86:
1613 case X86EMUL_MODE_PROT16:
1614 case X86EMUL_MODE_PROT32:
1615 case X86EMUL_MODE_PROT64:
1616 default:
1617 /* Protected mode interrupts unimplemented yet */
1618 return X86EMUL_UNHANDLEABLE;
1619 }
1620}
1621
dde7e6d1
AK		 1622static int emulate_iret_real(struct x86_emulate_ctxt *ctxt,
1623 struct x86_emulate_ops *ops)
38ba30ba 1624{
dde7e6d1
AK		 1625 struct decode_cache *c = &ctxt->decode;
1626 int rc = X86EMUL_CONTINUE;
1627 unsigned long temp_eip = 0;
1628 unsigned long temp_eflags = 0;
1629 unsigned long cs = 0;
1630 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1631 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1632 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1633 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1634
dde7e6d1 1635 /* TODO: Add stack limit check */
38ba30ba 1636
dde7e6d1 1637 rc = emulate_pop(ctxt, ops, &temp_eip, c->op_bytes);
38ba30ba 1638
dde7e6d1
AK		 1639 if (rc != X86EMUL_CONTINUE)
1640 return rc;
38ba30ba 1641
35d3d4a1
AK		 1642 if (temp_eip & ~0xffff)
1643 return emulate_gp(ctxt, 0);
38ba30ba 1644
dde7e6d1 1645 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
38ba30ba 1646
dde7e6d1
AK		 1647 if (rc != X86EMUL_CONTINUE)
1648 return rc;
38ba30ba 1649
dde7e6d1 1650 rc = emulate_pop(ctxt, ops, &temp_eflags, c->op_bytes);
38ba30ba 1651
dde7e6d1
AK		 1652 if (rc != X86EMUL_CONTINUE)
1653 return rc;
38ba30ba 1654
dde7e6d1 1655 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
38ba30ba 1656
dde7e6d1
AK		 1657 if (rc != X86EMUL_CONTINUE)
1658 return rc;
38ba30ba 1659
dde7e6d1 1660 c->eip = temp_eip;
38ba30ba 1661
38ba30ba 1662
dde7e6d1
AK		 1663 if (c->op_bytes == 4)
1664 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
1665 else if (c->op_bytes == 2) {
1666 ctxt->eflags &= ~0xffff;
1667 ctxt->eflags |= temp_eflags;
38ba30ba 1668 }
dde7e6d1
AK		 1669
1670 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1671 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1672
1673 return rc;
38ba30ba
GN		 1674}
1675
dde7e6d1
AK		 1676static inline int emulate_iret(struct x86_emulate_ctxt *ctxt,
1677 struct x86_emulate_ops* ops)
c37eda13 1678{
dde7e6d1
AK		 1679 switch(ctxt->mode) {
1680 case X86EMUL_MODE_REAL:
1681 return emulate_iret_real(ctxt, ops);
1682 case X86EMUL_MODE_VM86:
1683 case X86EMUL_MODE_PROT16:
1684 case X86EMUL_MODE_PROT32:
1685 case X86EMUL_MODE_PROT64:
c37eda13 1686 default:
dde7e6d1
AK		 1687 /* iret from protected mode unimplemented yet */
1688 return X86EMUL_UNHANDLEABLE;
c37eda13 1689 }
c37eda13
WY		 1690}
1691
dde7e6d1 1692static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
79168fd1 1693 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1694{
1695 struct decode_cache *c = &ctxt->decode;
1696
dde7e6d1 1697 return emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes);
8cdbd2c9
LV		 1698}
1699
dde7e6d1 1700static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1701{
05f086f8 1702 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1703 switch (c->modrm_reg) {
1704 case 0: /* rol */
05f086f8 1705 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1706 break;
1707 case 1: /* ror */
05f086f8 1708 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1709 break;
1710 case 2: /* rcl */
05f086f8 1711 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1712 break;
1713 case 3: /* rcr */
05f086f8 1714 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1715 break;
1716 case 4: /* sal/shl */
1717 case 6: /* sal/shl */
05f086f8 1718 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1719 break;
1720 case 5: /* shr */
05f086f8 1721 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1722 break;
1723 case 7: /* sar */
05f086f8 1724 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1725 break;
1726 }
1727}
1728
1729static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
05f086f8 1730 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1731{
1732 struct decode_cache *c = &ctxt->decode;
3f9f53b0
MG		 1733 unsigned long *rax = &c->regs[VCPU_REGS_RAX];
1734 unsigned long *rdx = &c->regs[VCPU_REGS_RDX];
34d1f490 1735 u8 de = 0;
8cdbd2c9
LV		 1736
1737 switch (c->modrm_reg) {
1738 case 0 ... 1: /* test */
05f086f8 1739 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1740 break;
1741 case 2: /* not */
1742 c->dst.val = ~c->dst.val;
1743 break;
1744 case 3: /* neg */
05f086f8 1745 emulate_1op("neg", c->dst, ctxt->eflags);
8cdbd2c9 1746 break;
3f9f53b0
MG		 1747 case 4: /* mul */
1748 emulate_1op_rax_rdx("mul", c->src, *rax, *rdx, ctxt->eflags);
1749 break;
1750 case 5: /* imul */
1751 emulate_1op_rax_rdx("imul", c->src, *rax, *rdx, ctxt->eflags);
1752 break;
1753 case 6: /* div */
34d1f490
AK		 1754 emulate_1op_rax_rdx_ex("div", c->src, *rax, *rdx,
1755 ctxt->eflags, de);
3f9f53b0
MG		 1756 break;
1757 case 7: /* idiv */
34d1f490
AK		 1758 emulate_1op_rax_rdx_ex("idiv", c->src, *rax, *rdx,
1759 ctxt->eflags, de);
3f9f53b0 1760 break;
8cdbd2c9 1761 default:
8c5eee30 1762 return X86EMUL_UNHANDLEABLE;
8cdbd2c9 1763 }
34d1f490
AK		 1764 if (de)
1765 return emulate_de(ctxt);
8c5eee30 1766 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1767}
1768
4487b3b4 1769static int emulate_grp45(struct x86_emulate_ctxt *ctxt)
8cdbd2c9
LV		 1770{
1771 struct decode_cache *c = &ctxt->decode;
4179bb02 1772 int rc = X86EMUL_CONTINUE;
8cdbd2c9
LV		 1773
1774 switch (c->modrm_reg) {
1775 case 0: /* inc */
05f086f8 1776 emulate_1op("inc", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1777 break;
1778 case 1: /* dec */
05f086f8 1779 emulate_1op("dec", c->dst, ctxt->eflags);
8cdbd2c9 1780 break;
d19292e4
MG		 1781 case 2: /* call near abs */ {
1782 long int old_eip;
1783 old_eip = c->eip;
1784 c->eip = c->src.val;
1785 c->src.val = old_eip;
4487b3b4 1786 rc = em_push(ctxt);
d19292e4
MG		 1787 break;
1788 }
8cdbd2c9 1789 case 4: /* jmp abs */
fd60754e 1790 c->eip = c->src.val;
8cdbd2c9
LV		 1791 break;
1792 case 6: /* push */
4487b3b4 1793 rc = em_push(ctxt);
8cdbd2c9 1794 break;
8cdbd2c9 1795 }
4179bb02 1796 return rc;
8cdbd2c9
LV		 1797}
1798
1799static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
69f55cb1 1800 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1801{
1802 struct decode_cache *c = &ctxt->decode;
16518d5a 1803 u64 old = c->dst.orig_val64;
8cdbd2c9
LV		 1804
1805 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1806 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
8cdbd2c9
LV		 1807 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1808 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1809 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 1810 } else {
16518d5a
AK		 1811 c->dst.val64 = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1812 (u32) c->regs[VCPU_REGS_RBX];
8cdbd2c9 1813
05f086f8 1814 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 1815 }
1b30eaa8 1816 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1817}
1818
a77ab5ea
AK		 1819static int emulate_ret_far(struct x86_emulate_ctxt *ctxt,
1820 struct x86_emulate_ops *ops)
1821{
1822 struct decode_cache *c = &ctxt->decode;
1823 int rc;
1824 unsigned long cs;
1825
1826 rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes);
1b30eaa8 1827 if (rc != X86EMUL_CONTINUE)
a77ab5ea
AK		 1828 return rc;
1829 if (c->op_bytes == 4)
1830 c->eip = (u32)c->eip;
1831 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1b30eaa8 1832 if (rc != X86EMUL_CONTINUE)
a77ab5ea 1833 return rc;
2e873022 1834 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 1835 return rc;
1836}
1837
09b5f4d3
WY		 1838static int emulate_load_segment(struct x86_emulate_ctxt *ctxt,
1839 struct x86_emulate_ops *ops, int seg)
1840{
1841 struct decode_cache *c = &ctxt->decode;
1842 unsigned short sel;
1843 int rc;
1844
1845 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
1846
1847 rc = load_segment_descriptor(ctxt, ops, sel, seg);
1848 if (rc != X86EMUL_CONTINUE)
1849 return rc;
1850
1851 c->dst.val = c->src.val;
1852 return rc;
1853}
1854
e66bb2cc
AP		 1855static inline void
1856setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
79168fd1
GN		 1857 struct x86_emulate_ops *ops, struct desc_struct *cs,
1858 struct desc_struct *ss)
e66bb2cc 1859{
1aa36616
AK		 1860 u16 selector;
1861
79168fd1 1862 memset(cs, 0, sizeof(struct desc_struct));
1aa36616 1863 ops->get_segment(ctxt, &selector, cs, NULL, VCPU_SREG_CS);
79168fd1 1864 memset(ss, 0, sizeof(struct desc_struct));
e66bb2cc
AP		 1865
1866 cs->l = 0; /* will be adjusted later */
79168fd1 1867 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 1868 cs->g = 1; /* 4kb granularity */
79168fd1 1869 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1870 cs->type = 0x0b; /* Read, Execute, Accessed */
1871 cs->s = 1;
1872 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 1873 cs->p = 1;
1874 cs->d = 1;
e66bb2cc 1875
79168fd1
GN		 1876 set_desc_base(ss, 0); /* flat segment */
1877 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1878 ss->g = 1; /* 4kb granularity */
1879 ss->s = 1;
1880 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 1881 ss->d = 1; /* 32bit stack segment */
e66bb2cc 1882 ss->dpl = 0;
79168fd1 1883 ss->p = 1;
e66bb2cc
AP		 1884}
1885
1886static int
3fb1b5db 1887emulate_syscall(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
e66bb2cc
AP		 1888{
1889 struct decode_cache *c = &ctxt->decode;
79168fd1 1890 struct desc_struct cs, ss;
e66bb2cc 1891 u64 msr_data;
79168fd1 1892 u16 cs_sel, ss_sel;
c2ad2bb3 1893 u64 efer = 0;
e66bb2cc
AP		 1894
1895 /* syscall is not available in real mode */
2e901c4c 1896 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 1897 ctxt->mode == X86EMUL_MODE_VM86)
1898 return emulate_ud(ctxt);
e66bb2cc 1899
c2ad2bb3 1900 ops->get_msr(ctxt, MSR_EFER, &efer);
79168fd1 1901 setup_syscalls_segments(ctxt, ops, &cs, &ss);
e66bb2cc 1902
717746e3 1903 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc 1904 msr_data >>= 32;
79168fd1
GN		 1905 cs_sel = (u16)(msr_data & 0xfffc);
1906 ss_sel = (u16)(msr_data + 8);
e66bb2cc 1907
c2ad2bb3 1908 if (efer & EFER_LMA) {
79168fd1 1909 cs.d = 0;
e66bb2cc
AP		 1910 cs.l = 1;
1911 }
1aa36616
AK		 1912 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
1913 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
e66bb2cc
AP		 1914
1915 c->regs[VCPU_REGS_RCX] = c->eip;
c2ad2bb3 1916 if (efer & EFER_LMA) {
e66bb2cc
AP		 1917#ifdef CONFIG_X86_64
1918 c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
1919
717746e3 1920 ops->get_msr(ctxt,
3fb1b5db
GN		 1921 ctxt->mode == X86EMUL_MODE_PROT64 ?
1922 MSR_LSTAR : MSR_CSTAR, &msr_data);
e66bb2cc
AP		 1923 c->eip = msr_data;
1924
717746e3 1925 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 1926 ctxt->eflags &= ~(msr_data | EFLG_RF);
1927#endif
1928 } else {
1929 /* legacy mode */
717746e3 1930 ops->get_msr(ctxt, MSR_STAR, &msr_data);
e66bb2cc
AP		 1931 c->eip = (u32)msr_data;
1932
1933 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1934 }
1935
e54cfa97 1936 return X86EMUL_CONTINUE;
e66bb2cc
AP		 1937}
1938
8c604352 1939static int
3fb1b5db 1940emulate_sysenter(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8c604352
AP		 1941{
1942 struct decode_cache *c = &ctxt->decode;
79168fd1 1943 struct desc_struct cs, ss;
8c604352 1944 u64 msr_data;
79168fd1 1945 u16 cs_sel, ss_sel;
c2ad2bb3 1946 u64 efer = 0;
8c604352 1947
c2ad2bb3 1948 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
a0044755 1949 /* inject #GP if in real mode */
35d3d4a1
AK		 1950 if (ctxt->mode == X86EMUL_MODE_REAL)
1951 return emulate_gp(ctxt, 0);
8c604352
AP		 1952
1953 /* XXX sysenter/sysexit have not been tested in 64bit mode.
1954 * Therefore, we inject an #UD.
1955 */
35d3d4a1
AK		 1956 if (ctxt->mode == X86EMUL_MODE_PROT64)
1957 return emulate_ud(ctxt);
8c604352 1958
79168fd1 1959 setup_syscalls_segments(ctxt, ops, &cs, &ss);
8c604352 1960
717746e3 1961 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 1962 switch (ctxt->mode) {
1963 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 1964 if ((msr_data & 0xfffc) == 0x0)
1965 return emulate_gp(ctxt, 0);
8c604352
AP		 1966 break;
1967 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 1968 if (msr_data == 0x0)
1969 return emulate_gp(ctxt, 0);
8c604352
AP		 1970 break;
1971 }
1972
1973 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 1974 cs_sel = (u16)msr_data;
1975 cs_sel &= ~SELECTOR_RPL_MASK;
1976 ss_sel = cs_sel + 8;
1977 ss_sel &= ~SELECTOR_RPL_MASK;
c2ad2bb3 1978 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
79168fd1 1979 cs.d = 0;
8c604352
AP		 1980 cs.l = 1;
1981 }
1982
1aa36616
AK		 1983 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
1984 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
8c604352 1985
717746e3 1986 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
8c604352
AP		 1987 c->eip = msr_data;
1988
717746e3 1989 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
8c604352
AP		 1990 c->regs[VCPU_REGS_RSP] = msr_data;
1991
e54cfa97 1992 return X86EMUL_CONTINUE;
8c604352
AP		 1993}
1994
4668f050 1995static int
3fb1b5db 1996emulate_sysexit(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
4668f050
AP		 1997{
1998 struct decode_cache *c = &ctxt->decode;
79168fd1 1999 struct desc_struct cs, ss;
4668f050
AP		 2000 u64 msr_data;
2001 int usermode;
79168fd1 2002 u16 cs_sel, ss_sel;
4668f050 2003
a0044755
GN		 2004 /* inject #GP if in real mode or Virtual 8086 mode */
2005 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 2006 ctxt->mode == X86EMUL_MODE_VM86)
2007 return emulate_gp(ctxt, 0);
4668f050 2008
79168fd1 2009 setup_syscalls_segments(ctxt, ops, &cs, &ss);
4668f050
AP		 2010
2011 if ((c->rex_prefix & 0x8) != 0x0)
2012 usermode = X86EMUL_MODE_PROT64;
2013 else
2014 usermode = X86EMUL_MODE_PROT32;
2015
2016 cs.dpl = 3;
2017 ss.dpl = 3;
717746e3 2018 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 2019 switch (usermode) {
2020 case X86EMUL_MODE_PROT32:
79168fd1 2021 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 2022 if ((msr_data & 0xfffc) == 0x0)
2023 return emulate_gp(ctxt, 0);
79168fd1 2024 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 2025 break;
2026 case X86EMUL_MODE_PROT64:
79168fd1 2027 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 2028 if (msr_data == 0x0)
2029 return emulate_gp(ctxt, 0);
79168fd1
GN		 2030 ss_sel = cs_sel + 8;
2031 cs.d = 0;
4668f050
AP		 2032 cs.l = 1;
2033 break;
2034 }
79168fd1
GN		 2035 cs_sel |= SELECTOR_RPL_MASK;
2036 ss_sel |= SELECTOR_RPL_MASK;
4668f050 2037
1aa36616
AK		 2038 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2039 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
4668f050 2040
bdb475a3
GN		 2041 c->eip = c->regs[VCPU_REGS_RDX];
2042 c->regs[VCPU_REGS_RSP] = c->regs[VCPU_REGS_RCX];
4668f050 2043
e54cfa97 2044 return X86EMUL_CONTINUE;
4668f050
AP		 2045}
2046
9c537244
GN		 2047static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt,
2048 struct x86_emulate_ops *ops)
f850e2e6
GN		 2049{
2050 int iopl;
2051 if (ctxt->mode == X86EMUL_MODE_REAL)
2052 return false;
2053 if (ctxt->mode == X86EMUL_MODE_VM86)
2054 return true;
2055 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
717746e3 2056 return ops->cpl(ctxt) > iopl;
f850e2e6
GN		 2057}
2058
2059static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
2060 struct x86_emulate_ops *ops,
2061 u16 port, u16 len)
2062{
79168fd1 2063 struct desc_struct tr_seg;
5601d05b 2064 u32 base3;
f850e2e6 2065 int r;
1aa36616 2066 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2067 unsigned mask = (1 << len) - 1;
5601d05b 2068 unsigned long base;
f850e2e6 2069
1aa36616 2070 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
79168fd1 2071 if (!tr_seg.p)
f850e2e6 2072 return false;
79168fd1 2073 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2074 return false;
5601d05b
GN		 2075 base = get_desc_base(&tr_seg);
2076#ifdef CONFIG_X86_64
2077 base |= ((u64)base3) << 32;
2078#endif
0f65dd70 2079 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
f850e2e6
GN		 2080 if (r != X86EMUL_CONTINUE)
2081 return false;
79168fd1 2082 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2083 return false;
0f65dd70 2084 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
f850e2e6
GN		 2085 if (r != X86EMUL_CONTINUE)
2086 return false;
2087 if ((perm >> bit_idx) & mask)
2088 return false;
2089 return true;
2090}
2091
2092static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
2093 struct x86_emulate_ops *ops,
2094 u16 port, u16 len)
2095{
4fc40f07
GN		 2096 if (ctxt->perm_ok)
2097 return true;
2098
9c537244 2099 if (emulator_bad_iopl(ctxt, ops))
f850e2e6
GN		 2100 if (!emulator_io_port_access_allowed(ctxt, ops, port, len))
2101 return false;
4fc40f07
GN		 2102
2103 ctxt->perm_ok = true;
2104
f850e2e6
GN		 2105 return true;
2106}
2107
38ba30ba
GN		 2108static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
2109 struct x86_emulate_ops *ops,
2110 struct tss_segment_16 *tss)
2111{
2112 struct decode_cache *c = &ctxt->decode;
2113
2114 tss->ip = c->eip;
2115 tss->flag = ctxt->eflags;
2116 tss->ax = c->regs[VCPU_REGS_RAX];
2117 tss->cx = c->regs[VCPU_REGS_RCX];
2118 tss->dx = c->regs[VCPU_REGS_RDX];
2119 tss->bx = c->regs[VCPU_REGS_RBX];
2120 tss->sp = c->regs[VCPU_REGS_RSP];
2121 tss->bp = c->regs[VCPU_REGS_RBP];
2122 tss->si = c->regs[VCPU_REGS_RSI];
2123 tss->di = c->regs[VCPU_REGS_RDI];
2124
1aa36616
AK		 2125 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2126 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2127 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2128 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2129 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2130}
2131
2132static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
2133 struct x86_emulate_ops *ops,
2134 struct tss_segment_16 *tss)
2135{
2136 struct decode_cache *c = &ctxt->decode;
2137 int ret;
2138
2139 c->eip = tss->ip;
2140 ctxt->eflags = tss->flag | 2;
2141 c->regs[VCPU_REGS_RAX] = tss->ax;
2142 c->regs[VCPU_REGS_RCX] = tss->cx;
2143 c->regs[VCPU_REGS_RDX] = tss->dx;
2144 c->regs[VCPU_REGS_RBX] = tss->bx;
2145 c->regs[VCPU_REGS_RSP] = tss->sp;
2146 c->regs[VCPU_REGS_RBP] = tss->bp;
2147 c->regs[VCPU_REGS_RSI] = tss->si;
2148 c->regs[VCPU_REGS_RDI] = tss->di;
2149
2150 /*
2151 * SDM says that segment selectors are loaded before segment
2152 * descriptors
2153 */
1aa36616
AK		 2154 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2155 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2156 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2157 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2158 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
38ba30ba
GN		 2159
2160 /*
2161 * Now load segment descriptors. If fault happenes at this stage
2162 * it is handled in a context of new task
2163 */
2164 ret = load_segment_descriptor(ctxt, ops, tss->ldt, VCPU_SREG_LDTR);
2165 if (ret != X86EMUL_CONTINUE)
2166 return ret;
2167 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2168 if (ret != X86EMUL_CONTINUE)
2169 return ret;
2170 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2171 if (ret != X86EMUL_CONTINUE)
2172 return ret;
2173 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2174 if (ret != X86EMUL_CONTINUE)
2175 return ret;
2176 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2177 if (ret != X86EMUL_CONTINUE)
2178 return ret;
2179
2180 return X86EMUL_CONTINUE;
2181}
2182
2183static int task_switch_16(struct x86_emulate_ctxt *ctxt,
2184 struct x86_emulate_ops *ops,
2185 u16 tss_selector, u16 old_tss_sel,
2186 ulong old_tss_base, struct desc_struct *new_desc)
2187{
2188 struct tss_segment_16 tss_seg;
2189 int ret;
bcc55cba 2190 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2191
0f65dd70 2192 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2193 &ctxt->exception);
db297e3d 2194 if (ret != X86EMUL_CONTINUE)
38ba30ba 2195 /* FIXME: need to provide precise fault address */
38ba30ba 2196 return ret;
38ba30ba
GN		 2197
2198 save_state_to_tss16(ctxt, ops, &tss_seg);
2199
0f65dd70 2200 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2201 &ctxt->exception);
db297e3d 2202 if (ret != X86EMUL_CONTINUE)
38ba30ba 2203 /* FIXME: need to provide precise fault address */
38ba30ba 2204 return ret;
38ba30ba 2205
0f65dd70 2206 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2207 &ctxt->exception);
db297e3d 2208 if (ret != X86EMUL_CONTINUE)
38ba30ba 2209 /* FIXME: need to provide precise fault address */
38ba30ba 2210 return ret;
38ba30ba
GN		 2211
2212 if (old_tss_sel != 0xffff) {
2213 tss_seg.prev_task_link = old_tss_sel;
2214
0f65dd70 2215 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2216 &tss_seg.prev_task_link,
2217 sizeof tss_seg.prev_task_link,
0f65dd70 2218 &ctxt->exception);
db297e3d 2219 if (ret != X86EMUL_CONTINUE)
38ba30ba 2220 /* FIXME: need to provide precise fault address */
38ba30ba 2221 return ret;
38ba30ba
GN		 2222 }
2223
2224 return load_state_from_tss16(ctxt, ops, &tss_seg);
2225}
2226
2227static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
2228 struct x86_emulate_ops *ops,
2229 struct tss_segment_32 *tss)
2230{
2231 struct decode_cache *c = &ctxt->decode;
2232
717746e3 2233 tss->cr3 = ops->get_cr(ctxt, 3);
38ba30ba
GN		 2234 tss->eip = c->eip;
2235 tss->eflags = ctxt->eflags;
2236 tss->eax = c->regs[VCPU_REGS_RAX];
2237 tss->ecx = c->regs[VCPU_REGS_RCX];
2238 tss->edx = c->regs[VCPU_REGS_RDX];
2239 tss->ebx = c->regs[VCPU_REGS_RBX];
2240 tss->esp = c->regs[VCPU_REGS_RSP];
2241 tss->ebp = c->regs[VCPU_REGS_RBP];
2242 tss->esi = c->regs[VCPU_REGS_RSI];
2243 tss->edi = c->regs[VCPU_REGS_RDI];
2244
1aa36616
AK		 2245 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2246 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2247 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2248 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2249 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2250 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
2251 tss->ldt_selector = get_segment_selector(ctxt, VCPU_SREG_LDTR);
38ba30ba
GN		 2252}
2253
2254static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
2255 struct x86_emulate_ops *ops,
2256 struct tss_segment_32 *tss)
2257{
2258 struct decode_cache *c = &ctxt->decode;
2259 int ret;
2260
717746e3 2261 if (ops->set_cr(ctxt, 3, tss->cr3))
35d3d4a1 2262 return emulate_gp(ctxt, 0);
38ba30ba
GN		 2263 c->eip = tss->eip;
2264 ctxt->eflags = tss->eflags | 2;
2265 c->regs[VCPU_REGS_RAX] = tss->eax;
2266 c->regs[VCPU_REGS_RCX] = tss->ecx;
2267 c->regs[VCPU_REGS_RDX] = tss->edx;
2268 c->regs[VCPU_REGS_RBX] = tss->ebx;
2269 c->regs[VCPU_REGS_RSP] = tss->esp;
2270 c->regs[VCPU_REGS_RBP] = tss->ebp;
2271 c->regs[VCPU_REGS_RSI] = tss->esi;
2272 c->regs[VCPU_REGS_RDI] = tss->edi;
2273
2274 /*
2275 * SDM says that segment selectors are loaded before segment
2276 * descriptors
2277 */
1aa36616
AK		 2278 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2279 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2280 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2281 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2282 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2283 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2284 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
38ba30ba
GN		 2285
2286 /*
2287 * Now load segment descriptors. If fault happenes at this stage
2288 * it is handled in a context of new task
2289 */
2290 ret = load_segment_descriptor(ctxt, ops, tss->ldt_selector, VCPU_SREG_LDTR);
2291 if (ret != X86EMUL_CONTINUE)
2292 return ret;
2293 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2294 if (ret != X86EMUL_CONTINUE)
2295 return ret;
2296 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2297 if (ret != X86EMUL_CONTINUE)
2298 return ret;
2299 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2300 if (ret != X86EMUL_CONTINUE)
2301 return ret;
2302 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2303 if (ret != X86EMUL_CONTINUE)
2304 return ret;
2305 ret = load_segment_descriptor(ctxt, ops, tss->fs, VCPU_SREG_FS);
2306 if (ret != X86EMUL_CONTINUE)
2307 return ret;
2308 ret = load_segment_descriptor(ctxt, ops, tss->gs, VCPU_SREG_GS);
2309 if (ret != X86EMUL_CONTINUE)
2310 return ret;
2311
2312 return X86EMUL_CONTINUE;
2313}
2314
2315static int task_switch_32(struct x86_emulate_ctxt *ctxt,
2316 struct x86_emulate_ops *ops,
2317 u16 tss_selector, u16 old_tss_sel,
2318 ulong old_tss_base, struct desc_struct *new_desc)
2319{
2320 struct tss_segment_32 tss_seg;
2321 int ret;
bcc55cba 2322 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba 2323
0f65dd70 2324 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2325 &ctxt->exception);
db297e3d 2326 if (ret != X86EMUL_CONTINUE)
38ba30ba 2327 /* FIXME: need to provide precise fault address */
38ba30ba 2328 return ret;
38ba30ba
GN		 2329
2330 save_state_to_tss32(ctxt, ops, &tss_seg);
2331
0f65dd70 2332 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2333 &ctxt->exception);
db297e3d 2334 if (ret != X86EMUL_CONTINUE)
38ba30ba 2335 /* FIXME: need to provide precise fault address */
38ba30ba 2336 return ret;
38ba30ba 2337
0f65dd70 2338 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
bcc55cba 2339 &ctxt->exception);
db297e3d 2340 if (ret != X86EMUL_CONTINUE)
38ba30ba 2341 /* FIXME: need to provide precise fault address */
38ba30ba 2342 return ret;
38ba30ba
GN		 2343
2344 if (old_tss_sel != 0xffff) {
2345 tss_seg.prev_task_link = old_tss_sel;
2346
0f65dd70 2347 ret = ops->write_std(ctxt, new_tss_base,
38ba30ba
GN		 2348 &tss_seg.prev_task_link,
2349 sizeof tss_seg.prev_task_link,
0f65dd70 2350 &ctxt->exception);
db297e3d 2351 if (ret != X86EMUL_CONTINUE)
38ba30ba 2352 /* FIXME: need to provide precise fault address */
38ba30ba 2353 return ret;
38ba30ba
GN		 2354 }
2355
2356 return load_state_from_tss32(ctxt, ops, &tss_seg);
2357}
2358
2359static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 2360 struct x86_emulate_ops *ops,
2361 u16 tss_selector, int reason,
2362 bool has_error_code, u32 error_code)
38ba30ba
GN		 2363{
2364 struct desc_struct curr_tss_desc, next_tss_desc;
2365 int ret;
1aa36616 2366 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
38ba30ba 2367 ulong old_tss_base =
4bff1e86 2368 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
ceffb459 2369 u32 desc_limit;
38ba30ba
GN		 2370
2371 /* FIXME: old_tss_base == ~0 ? */
2372
2373 ret = read_segment_descriptor(ctxt, ops, tss_selector, &next_tss_desc);
2374 if (ret != X86EMUL_CONTINUE)
2375 return ret;
2376 ret = read_segment_descriptor(ctxt, ops, old_tss_sel, &curr_tss_desc);
2377 if (ret != X86EMUL_CONTINUE)
2378 return ret;
2379
2380 /* FIXME: check that next_tss_desc is tss */
2381
2382 if (reason != TASK_SWITCH_IRET) {
2383 if ((tss_selector & 3) > next_tss_desc.dpl ||
717746e3 2384 ops->cpl(ctxt) > next_tss_desc.dpl)
35d3d4a1 2385 return emulate_gp(ctxt, 0);
38ba30ba
GN		 2386 }
2387
ceffb459
GN		 2388 desc_limit = desc_limit_scaled(&next_tss_desc);
2389 if (!next_tss_desc.p ||
2390 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2391 desc_limit < 0x2b)) {
54b8486f 2392 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2393 return X86EMUL_PROPAGATE_FAULT;
2394 }
2395
2396 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2397 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
2398 write_segment_descriptor(ctxt, ops, old_tss_sel,
2399 &curr_tss_desc);
2400 }
2401
2402 if (reason == TASK_SWITCH_IRET)
2403 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2404
2405 /* set back link to prev task only if NT bit is set in eflags
2406 note that old_tss_sel is not used afetr this point */
2407 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2408 old_tss_sel = 0xffff;
2409
2410 if (next_tss_desc.type & 8)
2411 ret = task_switch_32(ctxt, ops, tss_selector, old_tss_sel,
2412 old_tss_base, &next_tss_desc);
2413 else
2414 ret = task_switch_16(ctxt, ops, tss_selector, old_tss_sel,
2415 old_tss_base, &next_tss_desc);
0760d448
JK		 2416 if (ret != X86EMUL_CONTINUE)
2417 return ret;
38ba30ba
GN		 2418
2419 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2420 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2421
2422 if (reason != TASK_SWITCH_IRET) {
2423 next_tss_desc.type |= (1 << 1); /* set busy flag */
2424 write_segment_descriptor(ctxt, ops, tss_selector,
2425 &next_tss_desc);
2426 }
2427
717746e3 2428 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
1aa36616 2429 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
38ba30ba 2430
e269fb21
JK		 2431 if (has_error_code) {
2432 struct decode_cache *c = &ctxt->decode;
2433
2434 c->op_bytes = c->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2435 c->lock_prefix = 0;
2436 c->src.val = (unsigned long) error_code;
4487b3b4 2437 ret = em_push(ctxt);
e269fb21
JK		 2438 }
2439
38ba30ba
GN		 2440 return ret;
2441}
2442
2443int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 2444 u16 tss_selector, int reason,
2445 bool has_error_code, u32 error_code)
38ba30ba 2446{
9aabc88f 2447 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2448 struct decode_cache *c = &ctxt->decode;
2449 int rc;
2450
38ba30ba 2451 c->eip = ctxt->eip;
e269fb21 2452 c->dst.type = OP_NONE;
38ba30ba 2453
e269fb21
JK		 2454 rc = emulator_do_task_switch(ctxt, ops, tss_selector, reason,
2455 has_error_code, error_code);
38ba30ba 2456
4179bb02
TY		 2457 if (rc == X86EMUL_CONTINUE)
2458 ctxt->eip = c->eip;
38ba30ba 2459
a0c0ab2f 2460 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2461}
2462
90de84f5 2463static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned seg,
d9271123 2464 int reg, struct operand *op)
a682e354
GN		 2465{
2466 struct decode_cache *c = &ctxt->decode;
2467 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
2468
d9271123 2469 register_address_increment(c, &c->regs[reg], df * op->bytes);
90de84f5
AK		 2470 op->addr.mem.ea = register_address(c, c->regs[reg]);
2471 op->addr.mem.seg = seg;
a682e354
GN		 2472}
2473
7af04fc0
AK		 2474static int em_das(struct x86_emulate_ctxt *ctxt)
2475{
2476 struct decode_cache *c = &ctxt->decode;
2477 u8 al, old_al;
2478 bool af, cf, old_cf;
2479
2480 cf = ctxt->eflags & X86_EFLAGS_CF;
2481 al = c->dst.val;
2482
2483 old_al = al;
2484 old_cf = cf;
2485 cf = false;
2486 af = ctxt->eflags & X86_EFLAGS_AF;
2487 if ((al & 0x0f) > 9 || af) {
2488 al -= 6;
2489 cf = old_cf | (al >= 250);
2490 af = true;
2491 } else {
2492 af = false;
2493 }
2494 if (old_al > 0x99 || old_cf) {
2495 al -= 0x60;
2496 cf = true;
2497 }
2498
2499 c->dst.val = al;
2500 /* Set PF, ZF, SF */
2501 c->src.type = OP_IMM;
2502 c->src.val = 0;
2503 c->src.bytes = 1;
2504 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
2505 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2506 if (cf)
2507 ctxt->eflags |= X86_EFLAGS_CF;
2508 if (af)
2509 ctxt->eflags |= X86_EFLAGS_AF;
2510 return X86EMUL_CONTINUE;
2511}
2512
0ef753b8
AK		 2513static int em_call_far(struct x86_emulate_ctxt *ctxt)
2514{
2515 struct decode_cache *c = &ctxt->decode;
2516 u16 sel, old_cs;
2517 ulong old_eip;
2518 int rc;
2519
1aa36616 2520 old_cs = get_segment_selector(ctxt, VCPU_SREG_CS);
0ef753b8
AK		 2521 old_eip = c->eip;
2522
2523 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
2524 if (load_segment_descriptor(ctxt, ctxt->ops, sel, VCPU_SREG_CS))
2525 return X86EMUL_CONTINUE;
2526
2527 c->eip = 0;
2528 memcpy(&c->eip, c->src.valptr, c->op_bytes);
2529
2530 c->src.val = old_cs;
4487b3b4 2531 rc = em_push(ctxt);
0ef753b8
AK		 2532 if (rc != X86EMUL_CONTINUE)
2533 return rc;
2534
2535 c->src.val = old_eip;
4487b3b4 2536 return em_push(ctxt);
0ef753b8
AK		 2537}
2538
40ece7c7
AK		 2539static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
2540{
2541 struct decode_cache *c = &ctxt->decode;
2542 int rc;
2543
2544 c->dst.type = OP_REG;
2545 c->dst.addr.reg = &c->eip;
2546 c->dst.bytes = c->op_bytes;
2547 rc = emulate_pop(ctxt, ctxt->ops, &c->dst.val, c->op_bytes);
2548 if (rc != X86EMUL_CONTINUE)
2549 return rc;
2550 register_address_increment(c, &c->regs[VCPU_REGS_RSP], c->src.val);
2551 return X86EMUL_CONTINUE;
2552}
2553
d67fc27a
TY		 2554static int em_add(struct x86_emulate_ctxt *ctxt)
2555{
2556 struct decode_cache *c = &ctxt->decode;
2557
2558 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
2559 return X86EMUL_CONTINUE;
2560}
2561
2562static int em_or(struct x86_emulate_ctxt *ctxt)
2563{
2564 struct decode_cache *c = &ctxt->decode;
2565
2566 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
2567 return X86EMUL_CONTINUE;
2568}
2569
2570static int em_adc(struct x86_emulate_ctxt *ctxt)
2571{
2572 struct decode_cache *c = &ctxt->decode;
2573
2574 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
2575 return X86EMUL_CONTINUE;
2576}
2577
2578static int em_sbb(struct x86_emulate_ctxt *ctxt)
2579{
2580 struct decode_cache *c = &ctxt->decode;
2581
2582 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
2583 return X86EMUL_CONTINUE;
2584}
2585
2586static int em_and(struct x86_emulate_ctxt *ctxt)
2587{
2588 struct decode_cache *c = &ctxt->decode;
2589
2590 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
2591 return X86EMUL_CONTINUE;
2592}
2593
2594static int em_sub(struct x86_emulate_ctxt *ctxt)
2595{
2596 struct decode_cache *c = &ctxt->decode;
2597
2598 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
2599 return X86EMUL_CONTINUE;
2600}
2601
2602static int em_xor(struct x86_emulate_ctxt *ctxt)
2603{
2604 struct decode_cache *c = &ctxt->decode;
2605
2606 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
2607 return X86EMUL_CONTINUE;
2608}
2609
2610static int em_cmp(struct x86_emulate_ctxt *ctxt)
2611{
2612 struct decode_cache *c = &ctxt->decode;
2613
2614 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
2615 /* Disable writeback. */
2616 c->dst.type = OP_NONE;
2617 return X86EMUL_CONTINUE;
2618}
2619
5c82aa29 2620static int em_imul(struct x86_emulate_ctxt *ctxt)
f3a1b9f4
AK		 2621{
2622 struct decode_cache *c = &ctxt->decode;
2623
f3a1b9f4
AK		 2624 emulate_2op_SrcV_nobyte("imul", c->src, c->dst, ctxt->eflags);
2625 return X86EMUL_CONTINUE;
2626}
2627
5c82aa29
AK		 2628static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
2629{
2630 struct decode_cache *c = &ctxt->decode;
2631
2632 c->dst.val = c->src2.val;
2633 return em_imul(ctxt);
2634}
2635
61429142
AK		 2636static int em_cwd(struct x86_emulate_ctxt *ctxt)
2637{
2638 struct decode_cache *c = &ctxt->decode;
2639
2640 c->dst.type = OP_REG;
2641 c->dst.bytes = c->src.bytes;
2642 c->dst.addr.reg = &c->regs[VCPU_REGS_RDX];
2643 c->dst.val = ~((c->src.val >> (c->src.bytes * 8 - 1)) - 1);
2644
2645 return X86EMUL_CONTINUE;
2646}
2647
48bb5d3c
AK		 2648static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
2649{
48bb5d3c
AK		 2650 struct decode_cache *c = &ctxt->decode;
2651 u64 tsc = 0;
2652
717746e3 2653 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
48bb5d3c
AK		 2654 c->regs[VCPU_REGS_RAX] = (u32)tsc;
2655 c->regs[VCPU_REGS_RDX] = tsc >> 32;
2656 return X86EMUL_CONTINUE;
2657}
2658
b9eac5f4
AK		 2659static int em_mov(struct x86_emulate_ctxt *ctxt)
2660{
2661 struct decode_cache *c = &ctxt->decode;
2662 c->dst.val = c->src.val;
2663 return X86EMUL_CONTINUE;
2664}
2665
aa97bb48
AK		 2666static int em_movdqu(struct x86_emulate_ctxt *ctxt)
2667{
2668 struct decode_cache *c = &ctxt->decode;
2669 memcpy(&c->dst.vec_val, &c->src.vec_val, c->op_bytes);
2670 return X86EMUL_CONTINUE;
2671}
2672
38503911
AK		 2673static int em_invlpg(struct x86_emulate_ctxt *ctxt)
2674{
2675 struct decode_cache *c = &ctxt->decode;
9fa088f4
AK		 2676 int rc;
2677 ulong linear;
2678
83b8795a 2679 rc = linearize(ctxt, c->src.addr.mem, 1, false, &linear);
9fa088f4 2680 if (rc == X86EMUL_CONTINUE)
3cb16fe7 2681 ctxt->ops->invlpg(ctxt, linear);
38503911
AK		 2682 /* Disable writeback. */
2683 c->dst.type = OP_NONE;
2684 return X86EMUL_CONTINUE;
2685}
2686
2d04a05b
AK		 2687static int em_clts(struct x86_emulate_ctxt *ctxt)
2688{
2689 ulong cr0;
2690
2691 cr0 = ctxt->ops->get_cr(ctxt, 0);
2692 cr0 &= ~X86_CR0_TS;
2693 ctxt->ops->set_cr(ctxt, 0, cr0);
2694 return X86EMUL_CONTINUE;
2695}
2696
26d05cc7
AK		 2697static int em_vmcall(struct x86_emulate_ctxt *ctxt)
2698{
2699 struct decode_cache *c = &ctxt->decode;
2700 int rc;
2701
2702 if (c->modrm_mod != 3 || c->modrm_rm != 1)
2703 return X86EMUL_UNHANDLEABLE;
2704
2705 rc = ctxt->ops->fix_hypercall(ctxt);
2706 if (rc != X86EMUL_CONTINUE)
2707 return rc;
2708
2709 /* Let the processor re-execute the fixed hypercall */
2710 c->eip = ctxt->eip;
2711 /* Disable writeback. */
2712 c->dst.type = OP_NONE;
2713 return X86EMUL_CONTINUE;
2714}
2715
2716static int em_lgdt(struct x86_emulate_ctxt *ctxt)
2717{
2718 struct decode_cache *c = &ctxt->decode;
2719 struct desc_ptr desc_ptr;
2720 int rc;
2721
509cf9fe 2722 rc = read_descriptor(ctxt, c->src.addr.mem,
26d05cc7
AK		 2723 &desc_ptr.size, &desc_ptr.address,
2724 c->op_bytes);
2725 if (rc != X86EMUL_CONTINUE)
2726 return rc;
2727 ctxt->ops->set_gdt(ctxt, &desc_ptr);
2728 /* Disable writeback. */
2729 c->dst.type = OP_NONE;
2730 return X86EMUL_CONTINUE;
2731}
2732
5ef39c71 2733static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
26d05cc7
AK		 2734{
2735 struct decode_cache *c = &ctxt->decode;
2736 int rc;
2737
5ef39c71
AK		 2738 rc = ctxt->ops->fix_hypercall(ctxt);
2739
26d05cc7
AK		 2740 /* Disable writeback. */
2741 c->dst.type = OP_NONE;
2742 return rc;
2743}
2744
2745static int em_lidt(struct x86_emulate_ctxt *ctxt)
2746{
2747 struct decode_cache *c = &ctxt->decode;
2748 struct desc_ptr desc_ptr;
2749 int rc;
2750
509cf9fe
TY		 2751 rc = read_descriptor(ctxt, c->src.addr.mem,
2752 &desc_ptr.size, &desc_ptr.address,
26d05cc7
AK		 2753 c->op_bytes);
2754 if (rc != X86EMUL_CONTINUE)
2755 return rc;
2756 ctxt->ops->set_idt(ctxt, &desc_ptr);
2757 /* Disable writeback. */
2758 c->dst.type = OP_NONE;
2759 return X86EMUL_CONTINUE;
2760}
2761
2762static int em_smsw(struct x86_emulate_ctxt *ctxt)
2763{
2764 struct decode_cache *c = &ctxt->decode;
2765
2766 c->dst.bytes = 2;
2767 c->dst.val = ctxt->ops->get_cr(ctxt, 0);
2768 return X86EMUL_CONTINUE;
2769}
2770
2771static int em_lmsw(struct x86_emulate_ctxt *ctxt)
2772{
2773 struct decode_cache *c = &ctxt->decode;
2774 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
2775 | (c->src.val & 0x0f));
2776 c->dst.type = OP_NONE;
2777 return X86EMUL_CONTINUE;
2778}
2779
cfec82cb
JR		 2780static bool valid_cr(int nr)
2781{
2782 switch (nr) {
2783 case 0:
2784 case 2 ... 4:
2785 case 8:
2786 return true;
2787 default:
2788 return false;
2789 }
2790}
2791
2792static int check_cr_read(struct x86_emulate_ctxt *ctxt)
2793{
2794 struct decode_cache *c = &ctxt->decode;
2795
2796 if (!valid_cr(c->modrm_reg))
2797 return emulate_ud(ctxt);
2798
2799 return X86EMUL_CONTINUE;
2800}
2801
2802static int check_cr_write(struct x86_emulate_ctxt *ctxt)
2803{
2804 struct decode_cache *c = &ctxt->decode;
2805 u64 new_val = c->src.val64;
2806 int cr = c->modrm_reg;
c2ad2bb3 2807 u64 efer = 0;
cfec82cb
JR		 2808
2809 static u64 cr_reserved_bits[] = {
2810 0xffffffff00000000ULL,
2811 0, 0, 0, /* CR3 checked later */
2812 CR4_RESERVED_BITS,
2813 0, 0, 0,
2814 CR8_RESERVED_BITS,
2815 };
2816
2817 if (!valid_cr(cr))
2818 return emulate_ud(ctxt);
2819
2820 if (new_val & cr_reserved_bits[cr])
2821 return emulate_gp(ctxt, 0);
2822
2823 switch (cr) {
2824 case 0: {
c2ad2bb3 2825 u64 cr4;
cfec82cb
JR		 2826 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
2827 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
2828 return emulate_gp(ctxt, 0);
2829
717746e3
AK		 2830 cr4 = ctxt->ops->get_cr(ctxt, 4);
2831 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 2832
2833 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
2834 !(cr4 & X86_CR4_PAE))
2835 return emulate_gp(ctxt, 0);
2836
2837 break;
2838 }
2839 case 3: {
2840 u64 rsvd = 0;
2841
c2ad2bb3
AK		 2842 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
2843 if (efer & EFER_LMA)
cfec82cb 2844 rsvd = CR3_L_MODE_RESERVED_BITS;
fd72c419 2845 else if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PAE)
cfec82cb 2846 rsvd = CR3_PAE_RESERVED_BITS;
fd72c419 2847 else if (ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PG)
cfec82cb
JR		 2848 rsvd = CR3_NONPAE_RESERVED_BITS;
2849
2850 if (new_val & rsvd)
2851 return emulate_gp(ctxt, 0);
2852
2853 break;
2854 }
2855 case 4: {
c2ad2bb3 2856 u64 cr4;
cfec82cb 2857
717746e3
AK		 2858 cr4 = ctxt->ops->get_cr(ctxt, 4);
2859 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
cfec82cb
JR		 2860
2861 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
2862 return emulate_gp(ctxt, 0);
2863
2864 break;
2865 }
2866 }
2867
2868 return X86EMUL_CONTINUE;
2869}
2870
3b88e41a
JR		 2871static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
2872{
2873 unsigned long dr7;
2874
717746e3 2875 ctxt->ops->get_dr(ctxt, 7, &dr7);
3b88e41a
JR		 2876
2877 /* Check if DR7.Global_Enable is set */
2878 return dr7 & (1 << 13);
2879}
2880
2881static int check_dr_read(struct x86_emulate_ctxt *ctxt)
2882{
2883 struct decode_cache *c = &ctxt->decode;
2884 int dr = c->modrm_reg;
2885 u64 cr4;
2886
2887 if (dr > 7)
2888 return emulate_ud(ctxt);
2889
717746e3 2890 cr4 = ctxt->ops->get_cr(ctxt, 4);
3b88e41a
JR		 2891 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
2892 return emulate_ud(ctxt);
2893
2894 if (check_dr7_gd(ctxt))
2895 return emulate_db(ctxt);
2896
2897 return X86EMUL_CONTINUE;
2898}
2899
2900static int check_dr_write(struct x86_emulate_ctxt *ctxt)
2901{
2902 struct decode_cache *c = &ctxt->decode;
2903 u64 new_val = c->src.val64;
2904 int dr = c->modrm_reg;
2905
2906 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
2907 return emulate_gp(ctxt, 0);
2908
2909 return check_dr_read(ctxt);
2910}
2911
01de8b09
JR		 2912static int check_svme(struct x86_emulate_ctxt *ctxt)
2913{
2914 u64 efer;
2915
717746e3 2916 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
01de8b09
JR		 2917
2918 if (!(efer & EFER_SVME))
2919 return emulate_ud(ctxt);
2920
2921 return X86EMUL_CONTINUE;
2922}
2923
2924static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
2925{
fe870ab9 2926 u64 rax = ctxt->decode.regs[VCPU_REGS_RAX];
01de8b09
JR		 2927
2928 /* Valid physical address? */
d4224449 2929 if (rax & 0xffff000000000000ULL)
01de8b09
JR		 2930 return emulate_gp(ctxt, 0);
2931
2932 return check_svme(ctxt);
2933}
2934
d7eb8203
JR		 2935static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
2936{
717746e3 2937 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
d7eb8203 2938
717746e3 2939 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
d7eb8203
JR		 2940 return emulate_ud(ctxt);
2941
2942 return X86EMUL_CONTINUE;
2943}
2944
8061252e
JR		 2945static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
2946{
717746e3 2947 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
fe870ab9 2948 u64 rcx = ctxt->decode.regs[VCPU_REGS_RCX];
8061252e 2949
717746e3 2950 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
8061252e
JR		 2951 (rcx > 3))
2952 return emulate_gp(ctxt, 0);
2953
2954 return X86EMUL_CONTINUE;
2955}
2956
f6511935
JR		 2957static int check_perm_in(struct x86_emulate_ctxt *ctxt)
2958{
2959 struct decode_cache *c = &ctxt->decode;
2960
2961 c->dst.bytes = min(c->dst.bytes, 4u);
2962 if (!emulator_io_permited(ctxt, ctxt->ops, c->src.val, c->dst.bytes))
2963 return emulate_gp(ctxt, 0);
2964
2965 return X86EMUL_CONTINUE;
2966}
2967
2968static int check_perm_out(struct x86_emulate_ctxt *ctxt)
2969{
2970 struct decode_cache *c = &ctxt->decode;
2971
2972 c->src.bytes = min(c->src.bytes, 4u);
2973 if (!emulator_io_permited(ctxt, ctxt->ops, c->dst.val, c->src.bytes))
2974 return emulate_gp(ctxt, 0);
2975
2976 return X86EMUL_CONTINUE;
2977}
2978
73fba5f4 2979#define D(_y) { .flags = (_y) }
c4f035c6 2980#define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i }
d09beabd
JR		 2981#define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \
2982 .check_perm = (_p) }
73fba5f4 2983#define N D(0)
01de8b09 2984#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
73fba5f4 2985#define G(_f, _g) { .flags = ((_f) | Group), .u.group = (_g) }
46561646 2986#define GD(_f, _g) { .flags = ((_f) | GroupDual), .u.gdual = (_g) }
73fba5f4 2987#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
c4f035c6
AK		 2988#define II(_f, _e, _i) \
2989 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd
JR		 2990#define IIP(_f, _e, _i, _p) \
2991 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \
2992 .check_perm = (_p) }
aa97bb48 2993#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 2994
8d8f4e9f 2995#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 2996#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f
AK		 2997#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
2998
d67fc27a
TY		 2999#define I6ALU(_f, _e) I2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3000 I2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3001 I2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
6230f7fc 3002
d7eb8203
JR		 3003static struct opcode group7_rm1[] = {
3004 DI(SrcNone | ModRM | Priv, monitor),
3005 DI(SrcNone | ModRM | Priv, mwait),
3006 N, N, N, N, N, N,
3007};
3008
01de8b09
JR		 3009static struct opcode group7_rm3[] = {
3010 DIP(SrcNone | ModRM | Prot | Priv, vmrun, check_svme_pa),
5ef39c71 3011 II(SrcNone | ModRM | Prot | VendorSpecific, em_vmmcall, vmmcall),
01de8b09
JR		 3012 DIP(SrcNone | ModRM | Prot | Priv, vmload, check_svme_pa),
3013 DIP(SrcNone | ModRM | Prot | Priv, vmsave, check_svme_pa),
3014 DIP(SrcNone | ModRM | Prot | Priv, stgi, check_svme),
3015 DIP(SrcNone | ModRM | Prot | Priv, clgi, check_svme),
3016 DIP(SrcNone | ModRM | Prot | Priv, skinit, check_svme),
3017 DIP(SrcNone | ModRM | Prot | Priv, invlpga, check_svme),
3018};
6230f7fc 3019
d7eb8203
JR		 3020static struct opcode group7_rm7[] = {
3021 N,
3022 DIP(SrcNone | ModRM, rdtscp, check_rdtsc),
3023 N, N, N, N, N, N,
3024};
d67fc27a 3025
73fba5f4 3026static struct opcode group1[] = {
d67fc27a
TY		 3027 I(Lock, em_add),
3028 I(Lock, em_or),
3029 I(Lock, em_adc),
3030 I(Lock, em_sbb),
3031 I(Lock, em_and),
3032 I(Lock, em_sub),
3033 I(Lock, em_xor),
3034 I(0, em_cmp),
73fba5f4
AK		 3035};
3036
3037static struct opcode group1A[] = {
3038 D(DstMem | SrcNone | ModRM | Mov | Stack), N, N, N, N, N, N, N,
3039};
3040
3041static struct opcode group3[] = {
3042 D(DstMem | SrcImm | ModRM), D(DstMem | SrcImm | ModRM),
3043 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
3f9f53b0 3044 X4(D(SrcMem | ModRM)),
73fba5f4
AK		 3045};
3046
3047static struct opcode group4[] = {
3048 D(ByteOp | DstMem | SrcNone | ModRM | Lock), D(ByteOp | DstMem | SrcNone | ModRM | Lock),
3049 N, N, N, N, N, N,
3050};
3051
3052static struct opcode group5[] = {
3053 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
0ef753b8
AK		 3054 D(SrcMem | ModRM | Stack),
3055 I(SrcMemFAddr | ModRM | ImplicitOps | Stack, em_call_far),
73fba5f4
AK		 3056 D(SrcMem | ModRM | Stack), D(SrcMemFAddr | ModRM | ImplicitOps),
3057 D(SrcMem | ModRM | Stack), N,
3058};
3059
dee6bb70
JR		 3060static struct opcode group6[] = {
3061 DI(ModRM | Prot, sldt),
3062 DI(ModRM | Prot, str),
3063 DI(ModRM | Prot | Priv, lldt),
3064 DI(ModRM | Prot | Priv, ltr),
3065 N, N, N, N,
3066};
3067
73fba5f4 3068static struct group_dual group7 = { {
dee6bb70
JR		 3069 DI(ModRM | Mov | DstMem | Priv, sgdt),
3070 DI(ModRM | Mov | DstMem | Priv, sidt),
5ef39c71
AK		 3071 II(ModRM | SrcMem | Priv, em_lgdt, lgdt),
3072 II(ModRM | SrcMem | Priv, em_lidt, lidt),
3073 II(SrcNone | ModRM | DstMem | Mov, em_smsw, smsw), N,
3074 II(SrcMem16 | ModRM | Mov | Priv, em_lmsw, lmsw),
3075 II(SrcMem | ModRM | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
73fba5f4 3076}, {
5ef39c71
AK		 3077 I(SrcNone | ModRM | Priv | VendorSpecific, em_vmcall),
3078 EXT(0, group7_rm1),
01de8b09 3079 N, EXT(0, group7_rm3),
5ef39c71
AK		 3080 II(SrcNone | ModRM | DstMem | Mov, em_smsw, smsw), N,
3081 II(SrcMem16 | ModRM | Mov | Priv, em_lmsw, lmsw), EXT(0, group7_rm7),
73fba5f4
AK		 3082} };
3083
3084static struct opcode group8[] = {
3085 N, N, N, N,
3086 D(DstMem | SrcImmByte | ModRM), D(DstMem | SrcImmByte | ModRM | Lock),
3087 D(DstMem | SrcImmByte | ModRM | Lock), D(DstMem | SrcImmByte | ModRM | Lock),
3088};
3089
3090static struct group_dual group9 = { {
3091 N, D(DstMem64 | ModRM | Lock), N, N, N, N, N, N,
3092}, {
3093 N, N, N, N, N, N, N, N,
3094} };
3095
a4d4a7c1
AK		 3096static struct opcode group11[] = {
3097 I(DstMem | SrcImm | ModRM | Mov, em_mov), X7(D(Undefined)),
3098};
3099
aa97bb48
AK		 3100static struct gprefix pfx_0f_6f_0f_7f = {
3101 N, N, N, I(Sse, em_movdqu),
3102};
3103
73fba5f4
AK		 3104static struct opcode opcode_table[256] = {
3105 /* 0x00 - 0x07 */
d67fc27a 3106 I6ALU(Lock, em_add),
73fba5f4
AK		 3107 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
3108 /* 0x08 - 0x0F */
d67fc27a 3109 I6ALU(Lock, em_or),
73fba5f4
AK		 3110 D(ImplicitOps | Stack | No64), N,
3111 /* 0x10 - 0x17 */
d67fc27a 3112 I6ALU(Lock, em_adc),
73fba5f4
AK		 3113 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
3114 /* 0x18 - 0x1F */
d67fc27a 3115 I6ALU(Lock, em_sbb),
73fba5f4
AK		 3116 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
3117 /* 0x20 - 0x27 */
d67fc27a 3118 I6ALU(Lock, em_and), N, N,
73fba5f4 3119 /* 0x28 - 0x2F */
d67fc27a 3120 I6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 3121 /* 0x30 - 0x37 */
d67fc27a 3122 I6ALU(Lock, em_xor), N, N,
73fba5f4 3123 /* 0x38 - 0x3F */
d67fc27a 3124 I6ALU(0, em_cmp), N, N,
73fba5f4
AK		 3125 /* 0x40 - 0x4F */
3126 X16(D(DstReg)),
3127 /* 0x50 - 0x57 */
63540382 3128 X8(I(SrcReg | Stack, em_push)),
73fba5f4 3129 /* 0x58 - 0x5F */
c54fe504 3130 X8(I(DstReg | Stack, em_pop)),
73fba5f4 3131 /* 0x60 - 0x67 */
b96a7fad
TY		 3132 I(ImplicitOps | Stack | No64, em_pusha),
3133 I(ImplicitOps | Stack | No64, em_popa),
73fba5f4
AK		 3134 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3135 N, N, N, N,
3136 /* 0x68 - 0x6F */
d46164db
AK		 3137 I(SrcImm | Mov | Stack, em_push),
3138 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 3139 I(SrcImmByte | Mov | Stack, em_push),
3140 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
f6511935
JR		 3141 D2bvIP(DstDI | Mov | String, ins, check_perm_in), /* insb, insw/insd */
3142 D2bvIP(SrcSI | ImplicitOps | String, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4
AK		 3143 /* 0x70 - 0x7F */
3144 X16(D(SrcImmByte)),
3145 /* 0x80 - 0x87 */
3146 G(ByteOp | DstMem | SrcImm | ModRM | Group, group1),
3147 G(DstMem | SrcImm | ModRM | Group, group1),
3148 G(ByteOp | DstMem | SrcImm | ModRM | No64 | Group, group1),
3149 G(DstMem | SrcImmByte | ModRM | Group, group1),
76e8e68d 3150 D2bv(DstMem | SrcReg | ModRM), D2bv(DstMem | SrcReg | ModRM | Lock),
73fba5f4 3151 /* 0x88 - 0x8F */
b9eac5f4
AK		 3152 I2bv(DstMem | SrcReg | ModRM | Mov, em_mov),
3153 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
342fc630 3154 D(DstMem | SrcNone | ModRM | Mov), D(ModRM | SrcMem | NoAccess | DstReg),
73fba5f4
AK		 3155 D(ImplicitOps | SrcMem16 | ModRM), G(0, group1A),
3156 /* 0x90 - 0x97 */
bf608f88 3157 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 3158 /* 0x98 - 0x9F */
61429142 3159 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 3160 I(SrcImmFAddr | No64, em_call_far), N,
62aaa2f0
TY		 3161 II(ImplicitOps | Stack, em_pushf, pushf),
3162 II(ImplicitOps | Stack, em_popf, popf), N, N,
73fba5f4 3163 /* 0xA0 - 0xA7 */
b9eac5f4
AK		 3164 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
3165 I2bv(DstMem | SrcAcc | Mov | MemAbs, em_mov),
3166 I2bv(SrcSI | DstDI | Mov | String, em_mov),
d67fc27a 3167 I2bv(SrcSI | DstDI | String, em_cmp),
73fba5f4 3168 /* 0xA8 - 0xAF */
50748613 3169 D2bv(DstAcc | SrcImm),
b9eac5f4
AK		 3170 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
3171 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
d67fc27a 3172 I2bv(SrcAcc | DstDI | String, em_cmp),
73fba5f4 3173 /* 0xB0 - 0xB7 */
b9eac5f4 3174 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3175 /* 0xB8 - 0xBF */
b9eac5f4 3176 X8(I(DstReg | SrcImm | Mov, em_mov)),
73fba5f4 3177 /* 0xC0 - 0xC7 */
d2c6c7ad 3178 D2bv(DstMem | SrcImmByte | ModRM),
40ece7c7
AK		 3179 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
3180 D(ImplicitOps | Stack),
09b5f4d3 3181 D(DstReg | SrcMemFAddr | ModRM | No64), D(DstReg | SrcMemFAddr | ModRM | No64),
a4d4a7c1 3182 G(ByteOp, group11), G(0, group11),
73fba5f4
AK		 3183 /* 0xC8 - 0xCF */
3184 N, N, N, D(ImplicitOps | Stack),
3c6e276f
AK		 3185 D(ImplicitOps), DI(SrcImmByte, intn),
3186 D(ImplicitOps | No64), DI(ImplicitOps, iret),
73fba5f4 3187 /* 0xD0 - 0xD7 */
d2c6c7ad 3188 D2bv(DstMem | SrcOne | ModRM), D2bv(DstMem | ModRM),
73fba5f4
AK		 3189 N, N, N, N,
3190 /* 0xD8 - 0xDF */
3191 N, N, N, N, N, N, N, N,
3192 /* 0xE0 - 0xE7 */
e4abac67 3193 X4(D(SrcImmByte)),
f6511935
JR		 3194 D2bvIP(SrcImmUByte | DstAcc, in, check_perm_in),
3195 D2bvIP(SrcAcc | DstImmUByte, out, check_perm_out),
73fba5f4
AK		 3196 /* 0xE8 - 0xEF */
3197 D(SrcImm | Stack), D(SrcImm | ImplicitOps),
3198 D(SrcImmFAddr | No64), D(SrcImmByte | ImplicitOps),
f6511935
JR		 3199 D2bvIP(SrcNone | DstAcc, in, check_perm_in),
3200 D2bvIP(SrcAcc | ImplicitOps, out, check_perm_out),
73fba5f4 3201 /* 0xF0 - 0xF7 */
bf608f88 3202 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 3203 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
3204 G(ByteOp, group3), G(0, group3),
73fba5f4 3205 /* 0xF8 - 0xFF */
8744aa9a 3206 D(ImplicitOps), D(ImplicitOps), D(ImplicitOps), D(ImplicitOps),
73fba5f4
AK		 3207 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
3208};
3209
3210static struct opcode twobyte_table[256] = {
3211 /* 0x00 - 0x0F */
dee6bb70 3212 G(0, group6), GD(0, &group7), N, N,
cfec82cb 3213 N, D(ImplicitOps | VendorSpecific), DI(ImplicitOps | Priv, clts), N,
3c6e276f 3214 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
73fba5f4
AK		 3215 N, D(ImplicitOps | ModRM), N, N,
3216 /* 0x10 - 0x1F */
3217 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
3218 /* 0x20 - 0x2F */
cfec82cb 3219 DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read),
3b88e41a 3220 DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read),
cfec82cb 3221 DIP(ModRM | SrcMem | Priv | Op3264, cr_write, check_cr_write),
3b88e41a 3222 DIP(ModRM | SrcMem | Priv | Op3264, dr_write, check_dr_write),
73fba5f4
AK		 3223 N, N, N, N,
3224 N, N, N, N, N, N, N, N,
3225 /* 0x30 - 0x3F */
8061252e
JR		 3226 DI(ImplicitOps | Priv, wrmsr),
3227 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
3228 DI(ImplicitOps | Priv, rdmsr),
3229 DIP(ImplicitOps | Priv, rdpmc, check_rdpmc),
d867162c
AK		 3230 D(ImplicitOps | VendorSpecific), D(ImplicitOps | Priv | VendorSpecific),
3231 N, N,
73fba5f4
AK		 3232 N, N, N, N, N, N, N, N,
3233 /* 0x40 - 0x4F */
3234 X16(D(DstReg | SrcMem | ModRM | Mov)),
3235 /* 0x50 - 0x5F */
3236 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3237 /* 0x60 - 0x6F */
aa97bb48
AK		 3238 N, N, N, N,
3239 N, N, N, N,
3240 N, N, N, N,
3241 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 3242 /* 0x70 - 0x7F */
aa97bb48
AK		 3243 N, N, N, N,
3244 N, N, N, N,
3245 N, N, N, N,
3246 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4
AK		 3247 /* 0x80 - 0x8F */
3248 X16(D(SrcImm)),
3249 /* 0x90 - 0x9F */
ee45b58e 3250 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4
AK		 3251 /* 0xA0 - 0xA7 */
3252 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
8061252e 3253 DI(ImplicitOps, cpuid), D(DstMem | SrcReg | ModRM | BitOp),
73fba5f4
AK		 3254 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3255 D(DstMem | SrcReg | Src2CL | ModRM), N, N,
3256 /* 0xA8 - 0xAF */
3257 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
8061252e 3258 DI(ImplicitOps, rsm), D(DstMem | SrcReg | ModRM | BitOp | Lock),
73fba5f4
AK		 3259 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3260 D(DstMem | SrcReg | Src2CL | ModRM),
5c82aa29 3261 D(ModRM), I(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 3262 /* 0xB0 - 0xB7 */
739ae406 3263 D2bv(DstMem | SrcReg | ModRM | Lock),
09b5f4d3
WY		 3264 D(DstReg | SrcMemFAddr | ModRM), D(DstMem | SrcReg | ModRM | BitOp | Lock),
3265 D(DstReg | SrcMemFAddr | ModRM), D(DstReg | SrcMemFAddr | ModRM),
3266 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 3267 /* 0xB8 - 0xBF */
3268 N, N,
ba7ff2b7 3269 G(BitOp, group8), D(DstMem | SrcReg | ModRM | BitOp | Lock),
d9574a25
WY		 3270 D(DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
3271 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4 3272 /* 0xC0 - 0xCF */
739ae406 3273 D2bv(DstMem | SrcReg | ModRM | Lock),
92f738a5 3274 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4
AK		 3275 N, N, N, GD(0, &group9),
3276 N, N, N, N, N, N, N, N,
3277 /* 0xD0 - 0xDF */
3278 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3279 /* 0xE0 - 0xEF */
3280 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3281 /* 0xF0 - 0xFF */
3282 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
3283};
3284
3285#undef D
3286#undef N
3287#undef G
3288#undef GD
3289#undef I
aa97bb48 3290#undef GP
01de8b09 3291#undef EXT
73fba5f4 3292
8d8f4e9f 3293#undef D2bv
f6511935 3294#undef D2bvIP
8d8f4e9f 3295#undef I2bv
d67fc27a 3296#undef I6ALU
8d8f4e9f 3297
39f21ee5
AK		 3298static unsigned imm_size(struct decode_cache *c)
3299{
3300 unsigned size;
3301
3302 size = (c->d & ByteOp) ? 1 : c->op_bytes;
3303 if (size == 8)
3304 size = 4;
3305 return size;
3306}
3307
3308static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
3309 unsigned size, bool sign_extension)
3310{
3311 struct decode_cache *c = &ctxt->decode;
3312 struct x86_emulate_ops *ops = ctxt->ops;
3313 int rc = X86EMUL_CONTINUE;
3314
3315 op->type = OP_IMM;
3316 op->bytes = size;
90de84f5 3317 op->addr.mem.ea = c->eip;
39f21ee5
AK		 3318 /* NB. Immediates are sign-extended as necessary. */
3319 switch (op->bytes) {
3320 case 1:
3321 op->val = insn_fetch(s8, 1, c->eip);
3322 break;
3323 case 2:
3324 op->val = insn_fetch(s16, 2, c->eip);
3325 break;
3326 case 4:
3327 op->val = insn_fetch(s32, 4, c->eip);
3328 break;
3329 }
3330 if (!sign_extension) {
3331 switch (op->bytes) {
3332 case 1:
3333 op->val &= 0xff;
3334 break;
3335 case 2:
3336 op->val &= 0xffff;
3337 break;
3338 case 4:
3339 op->val &= 0xffffffff;
3340 break;
3341 }
3342 }
3343done:
3344 return rc;
3345}
3346
dde7e6d1 3347int
dc25e89e 3348x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1
AK		 3349{
3350 struct x86_emulate_ops *ops = ctxt->ops;
3351 struct decode_cache *c = &ctxt->decode;
3352 int rc = X86EMUL_CONTINUE;
3353 int mode = ctxt->mode;
46561646 3354 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
0d7cdee8 3355 bool op_prefix = false;
46561646 3356 struct opcode opcode;
2dbd0dd7 3357 struct operand memop = { .type = OP_NONE };
dde7e6d1 3358
dde7e6d1 3359 c->eip = ctxt->eip;
dc25e89e
AP		 3360 c->fetch.start = c->eip;
3361 c->fetch.end = c->fetch.start + insn_len;
3362 if (insn_len > 0)
3363 memcpy(c->fetch.data, insn, insn_len);
dde7e6d1
AK		 3364
3365 switch (mode) {
3366 case X86EMUL_MODE_REAL:
3367 case X86EMUL_MODE_VM86:
3368 case X86EMUL_MODE_PROT16:
3369 def_op_bytes = def_ad_bytes = 2;
3370 break;
3371 case X86EMUL_MODE_PROT32:
3372 def_op_bytes = def_ad_bytes = 4;
3373 break;
3374#ifdef CONFIG_X86_64
3375 case X86EMUL_MODE_PROT64:
3376 def_op_bytes = 4;
3377 def_ad_bytes = 8;
3378 break;
3379#endif
3380 default:
3381 return -1;
3382 }
3383
3384 c->op_bytes = def_op_bytes;
3385 c->ad_bytes = def_ad_bytes;
3386
3387 /* Legacy prefixes. */
3388 for (;;) {
3389 switch (c->b = insn_fetch(u8, 1, c->eip)) {
3390 case 0x66: /* operand-size override */
0d7cdee8 3391 op_prefix = true;
dde7e6d1
AK		 3392 /* switch between 2/4 bytes */
3393 c->op_bytes = def_op_bytes ^ 6;
3394 break;
3395 case 0x67: /* address-size override */
3396 if (mode == X86EMUL_MODE_PROT64)
3397 /* switch between 4/8 bytes */
3398 c->ad_bytes = def_ad_bytes ^ 12;
3399 else
3400 /* switch between 2/4 bytes */
3401 c->ad_bytes = def_ad_bytes ^ 6;
3402 break;
3403 case 0x26: /* ES override */
3404 case 0x2e: /* CS override */
3405 case 0x36: /* SS override */
3406 case 0x3e: /* DS override */
3407 set_seg_override(c, (c->b >> 3) & 3);
3408 break;
3409 case 0x64: /* FS override */
3410 case 0x65: /* GS override */
3411 set_seg_override(c, c->b & 7);
3412 break;
3413 case 0x40 ... 0x4f: /* REX */
3414 if (mode != X86EMUL_MODE_PROT64)
3415 goto done_prefixes;
3416 c->rex_prefix = c->b;
3417 continue;
3418 case 0xf0: /* LOCK */
3419 c->lock_prefix = 1;
3420 break;
3421 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 3422 case 0xf3: /* REP/REPE/REPZ */
1d6b114f 3423 c->rep_prefix = c->b;
dde7e6d1
AK		 3424 break;
3425 default:
3426 goto done_prefixes;
3427 }
3428
3429 /* Any legacy prefix after a REX prefix nullifies its effect. */
3430
3431 c->rex_prefix = 0;
3432 }
3433
3434done_prefixes:
3435
3436 /* REX prefix. */
1e87e3ef
AK		 3437 if (c->rex_prefix & 8)
3438 c->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 3439
3440 /* Opcode byte(s). */
3441 opcode = opcode_table[c->b];
d3ad6243
WY		 3442 /* Two-byte opcode? */
3443 if (c->b == 0x0f) {
3444 c->twobyte = 1;
3445 c->b = insn_fetch(u8, 1, c->eip);
3446 opcode = twobyte_table[c->b];
dde7e6d1
AK		 3447 }
3448 c->d = opcode.flags;
3449
46561646
AK		 3450 while (c->d & GroupMask) {
3451 switch (c->d & GroupMask) {
3452 case Group:
3453 c->modrm = insn_fetch(u8, 1, c->eip);
3454 --c->eip;
3455 goffset = (c->modrm >> 3) & 7;
3456 opcode = opcode.u.group[goffset];
3457 break;
3458 case GroupDual:
3459 c->modrm = insn_fetch(u8, 1, c->eip);
3460 --c->eip;
3461 goffset = (c->modrm >> 3) & 7;
3462 if ((c->modrm >> 6) == 3)
3463 opcode = opcode.u.gdual->mod3[goffset];
3464 else
3465 opcode = opcode.u.gdual->mod012[goffset];
3466 break;
3467 case RMExt:
01de8b09
JR		 3468 goffset = c->modrm & 7;
3469 opcode = opcode.u.group[goffset];
46561646
AK		 3470 break;
3471 case Prefix:
3472 if (c->rep_prefix && op_prefix)
3473 return X86EMUL_UNHANDLEABLE;
3474 simd_prefix = op_prefix ? 0x66 : c->rep_prefix;
3475 switch (simd_prefix) {
3476 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
3477 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
3478 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
3479 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
3480 }
3481 break;
3482 default:
0d7cdee8 3483 return X86EMUL_UNHANDLEABLE;
0d7cdee8 3484 }
46561646
AK		 3485
3486 c->d &= ~GroupMask;
0d7cdee8
AK		 3487 c->d |= opcode.flags;
3488 }
3489
dde7e6d1 3490 c->execute = opcode.u.execute;
d09beabd 3491 c->check_perm = opcode.check_perm;
c4f035c6 3492 c->intercept = opcode.intercept;
dde7e6d1
AK		 3493
3494 /* Unrecognised? */
d53db5ef 3495 if (c->d == 0 || (c->d & Undefined))
dde7e6d1 3496 return -1;
dde7e6d1 3497
d867162c
AK		 3498 if (!(c->d & VendorSpecific) && ctxt->only_vendor_specific_insn)
3499 return -1;
3500
dde7e6d1
AK		 3501 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
3502 c->op_bytes = 8;
3503
7f9b4b75
AK		 3504 if (c->d & Op3264) {
3505 if (mode == X86EMUL_MODE_PROT64)
3506 c->op_bytes = 8;
3507 else
3508 c->op_bytes = 4;
3509 }
3510
1253791d
AK		 3511 if (c->d & Sse)
3512 c->op_bytes = 16;
3513
dde7e6d1 3514 /* ModRM and SIB bytes. */
09ee57cd 3515 if (c->d & ModRM) {
2dbd0dd7 3516 rc = decode_modrm(ctxt, ops, &memop);
09ee57cd
AK		 3517 if (!c->has_seg_override)
3518 set_seg_override(c, c->modrm_seg);
3519 } else if (c->d & MemAbs)
2dbd0dd7 3520 rc = decode_abs(ctxt, ops, &memop);
dde7e6d1
AK		 3521 if (rc != X86EMUL_CONTINUE)
3522 goto done;
3523
3524 if (!c->has_seg_override)
3525 set_seg_override(c, VCPU_SREG_DS);
3526
c1ed6dea 3527 memop.addr.mem.seg = seg_override(ctxt, c);
dde7e6d1 3528
2dbd0dd7 3529 if (memop.type == OP_MEM && c->ad_bytes != 8)
90de84f5 3530 memop.addr.mem.ea = (u32)memop.addr.mem.ea;
dde7e6d1 3531
2dbd0dd7 3532 if (memop.type == OP_MEM && c->rip_relative)
90de84f5 3533 memop.addr.mem.ea += c->eip;
dde7e6d1
AK		 3534
3535 /*
3536 * Decode and fetch the source operand: register, memory
3537 * or immediate.
3538 */
3539 switch (c->d & SrcMask) {
3540 case SrcNone:
3541 break;
3542 case SrcReg:
1253791d 3543 decode_register_operand(ctxt, &c->src, c, 0);
dde7e6d1
AK		 3544 break;
3545 case SrcMem16:
2dbd0dd7 3546 memop.bytes = 2;
dde7e6d1
AK		 3547 goto srcmem_common;
3548 case SrcMem32:
2dbd0dd7 3549 memop.bytes = 4;
dde7e6d1
AK		 3550 goto srcmem_common;
3551 case SrcMem:
2dbd0dd7 3552 memop.bytes = (c->d & ByteOp) ? 1 :
dde7e6d1 3553 c->op_bytes;
dde7e6d1 3554 srcmem_common:
2dbd0dd7 3555 c->src = memop;
dde7e6d1 3556 break;
b250e605 3557 case SrcImmU16:
39f21ee5
AK		 3558 rc = decode_imm(ctxt, &c->src, 2, false);
3559 break;
dde7e6d1 3560 case SrcImm:
39f21ee5
AK		 3561 rc = decode_imm(ctxt, &c->src, imm_size(c), true);
3562 break;
dde7e6d1 3563 case SrcImmU:
39f21ee5 3564 rc = decode_imm(ctxt, &c->src, imm_size(c), false);
dde7e6d1
AK		 3565 break;
3566 case SrcImmByte:
39f21ee5
AK		 3567 rc = decode_imm(ctxt, &c->src, 1, true);
3568 break;
dde7e6d1 3569 case SrcImmUByte:
39f21ee5 3570 rc = decode_imm(ctxt, &c->src, 1, false);
dde7e6d1
AK		 3571 break;
3572 case SrcAcc:
3573 c->src.type = OP_REG;
3574 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1a6440ae 3575 c->src.addr.reg = &c->regs[VCPU_REGS_RAX];
91ff3cb4 3576 fetch_register_operand(&c->src);
dde7e6d1
AK		 3577 break;
3578 case SrcOne:
3579 c->src.bytes = 1;
3580 c->src.val = 1;
3581 break;
3582 case SrcSI:
3583 c->src.type = OP_MEM;
3584 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
90de84f5
AK		 3585 c->src.addr.mem.ea =
3586 register_address(c, c->regs[VCPU_REGS_RSI]);
c1ed6dea 3587 c->src.addr.mem.seg = seg_override(ctxt, c);
dde7e6d1
AK		 3588 c->src.val = 0;
3589 break;
3590 case SrcImmFAddr:
3591 c->src.type = OP_IMM;
90de84f5 3592 c->src.addr.mem.ea = c->eip;
dde7e6d1
AK		 3593 c->src.bytes = c->op_bytes + 2;
3594 insn_fetch_arr(c->src.valptr, c->src.bytes, c->eip);
3595 break;
3596 case SrcMemFAddr:
2dbd0dd7
AK		 3597 memop.bytes = c->op_bytes + 2;
3598 goto srcmem_common;
dde7e6d1
AK		 3599 break;
3600 }
3601
39f21ee5
AK		 3602 if (rc != X86EMUL_CONTINUE)
3603 goto done;
3604
dde7e6d1
AK		 3605 /*
3606 * Decode and fetch the second source operand: register, memory
3607 * or immediate.
3608 */
3609 switch (c->d & Src2Mask) {
3610 case Src2None:
3611 break;
3612 case Src2CL:
3613 c->src2.bytes = 1;
3614 c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
3615 break;
3616 case Src2ImmByte:
39f21ee5 3617 rc = decode_imm(ctxt, &c->src2, 1, true);
dde7e6d1
AK		 3618 break;
3619 case Src2One:
3620 c->src2.bytes = 1;
3621 c->src2.val = 1;
3622 break;
7db41eb7
AK		 3623 case Src2Imm:
3624 rc = decode_imm(ctxt, &c->src2, imm_size(c), true);
3625 break;
dde7e6d1
AK		 3626 }
3627
39f21ee5
AK		 3628 if (rc != X86EMUL_CONTINUE)
3629 goto done;
3630
dde7e6d1
AK		 3631 /* Decode and fetch the destination operand: register or memory. */
3632 switch (c->d & DstMask) {
dde7e6d1 3633 case DstReg:
1253791d 3634 decode_register_operand(ctxt, &c->dst, c,
dde7e6d1
AK		 3635 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
3636 break;
943858e2
WY		 3637 case DstImmUByte:
3638 c->dst.type = OP_IMM;
90de84f5 3639 c->dst.addr.mem.ea = c->eip;
943858e2
WY		 3640 c->dst.bytes = 1;
3641 c->dst.val = insn_fetch(u8, 1, c->eip);
3642 break;
dde7e6d1
AK		 3643 case DstMem:
3644 case DstMem64:
2dbd0dd7 3645 c->dst = memop;
dde7e6d1
AK		 3646 if ((c->d & DstMask) == DstMem64)
3647 c->dst.bytes = 8;
3648 else
3649 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
35c843c4
WY		 3650 if (c->d & BitOp)
3651 fetch_bit_operand(c);
2dbd0dd7 3652 c->dst.orig_val = c->dst.val;
dde7e6d1
AK		 3653 break;
3654 case DstAcc:
3655 c->dst.type = OP_REG;
3656 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1a6440ae 3657 c->dst.addr.reg = &c->regs[VCPU_REGS_RAX];
91ff3cb4 3658 fetch_register_operand(&c->dst);
dde7e6d1
AK		 3659 c->dst.orig_val = c->dst.val;
3660 break;
3661 case DstDI:
3662 c->dst.type = OP_MEM;
3663 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
90de84f5
AK		 3664 c->dst.addr.mem.ea =
3665 register_address(c, c->regs[VCPU_REGS_RDI]);
3666 c->dst.addr.mem.seg = VCPU_SREG_ES;
dde7e6d1
AK		 3667 c->dst.val = 0;
3668 break;
36089fed
WY		 3669 case ImplicitOps:
3670 /* Special instructions do their own operand decoding. */
3671 default:
3672 c->dst.type = OP_NONE; /* Disable writeback. */
3673 return 0;
dde7e6d1
AK		 3674 }
3675
3676done:
a0c0ab2f 3677 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 3678}
3679
3e2f65d5
GN		 3680static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
3681{
3682 struct decode_cache *c = &ctxt->decode;
3683
3684 /* The second termination condition only applies for REPE
3685 * and REPNE. Test if the repeat string operation prefix is
3686 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
3687 * corresponding termination condition according to:
3688 * - if REPE/REPZ and ZF = 0 then done
3689 * - if REPNE/REPNZ and ZF = 1 then done
3690 */
3691 if (((c->b == 0xa6) || (c->b == 0xa7) ||
3692 (c->b == 0xae) || (c->b == 0xaf))
3693 && (((c->rep_prefix == REPE_PREFIX) &&
3694 ((ctxt->eflags & EFLG_ZF) == 0))
3695 || ((c->rep_prefix == REPNE_PREFIX) &&
3696 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
3697 return true;
3698
3699 return false;
3700}
3701
8b4caf66 3702int
9aabc88f 3703x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 3704{
9aabc88f 3705 struct x86_emulate_ops *ops = ctxt->ops;
8b4caf66 3706 u64 msr_data;
8b4caf66 3707 struct decode_cache *c = &ctxt->decode;
1b30eaa8 3708 int rc = X86EMUL_CONTINUE;
5cd21917 3709 int saved_dst_type = c->dst.type;
6e154e56 3710 int irq; /* Used for int 3, int, and into */
8b4caf66 3711
9de41573 3712 ctxt->decode.mem_read.pos = 0;
310b5d30 3713
1161624f 3714 if (ctxt->mode == X86EMUL_MODE_PROT64 && (c->d & No64)) {
35d3d4a1 3715 rc = emulate_ud(ctxt);
1161624f
GN		 3716 goto done;
3717 }
3718
d380a5e4 3719 /* LOCK prefix is allowed only with some instructions */
a41ffb75 3720 if (c->lock_prefix && (!(c->d & Lock) || c->dst.type != OP_MEM)) {
35d3d4a1 3721 rc = emulate_ud(ctxt);
d380a5e4
GN		 3722 goto done;
3723 }
3724
081bca0e 3725 if ((c->d & SrcMask) == SrcMemFAddr && c->src.type != OP_MEM) {
35d3d4a1 3726 rc = emulate_ud(ctxt);
081bca0e
AK		 3727 goto done;
3728 }
3729
1253791d 3730 if ((c->d & Sse)
717746e3
AK		 3731 && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)
3732 || !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
1253791d
AK		 3733 rc = emulate_ud(ctxt);
3734 goto done;
3735 }
3736
717746e3 3737 if ((c->d & Sse) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
1253791d
AK		 3738 rc = emulate_nm(ctxt);
3739 goto done;
3740 }
3741
c4f035c6 3742 if (unlikely(ctxt->guest_mode) && c->intercept) {
8a76d7f2
JR		 3743 rc = emulator_check_intercept(ctxt, c->intercept,
3744 X86_ICPT_PRE_EXCEPT);
c4f035c6
AK		 3745 if (rc != X86EMUL_CONTINUE)
3746 goto done;
3747 }
3748
e92805ac 3749 /* Privileged instruction can be executed only in CPL=0 */
717746e3 3750 if ((c->d & Priv) && ops->cpl(ctxt)) {
35d3d4a1 3751 rc = emulate_gp(ctxt, 0);
e92805ac
GN		 3752 goto done;
3753 }
3754
8ea7d6ae
JR		 3755 /* Instruction can only be executed in protected mode */
3756 if ((c->d & Prot) && !(ctxt->mode & X86EMUL_MODE_PROT)) {
3757 rc = emulate_ud(ctxt);
3758 goto done;
3759 }
3760
d09beabd
JR		 3761 /* Do instruction specific permission checks */
3762 if (c->check_perm) {
3763 rc = c->check_perm(ctxt);
3764 if (rc != X86EMUL_CONTINUE)
3765 goto done;
3766 }
3767
c4f035c6 3768 if (unlikely(ctxt->guest_mode) && c->intercept) {
8a76d7f2
JR		 3769 rc = emulator_check_intercept(ctxt, c->intercept,
3770 X86_ICPT_POST_EXCEPT);
c4f035c6
AK		 3771 if (rc != X86EMUL_CONTINUE)
3772 goto done;
3773 }
3774
b9fa9d6b
AK		 3775 if (c->rep_prefix && (c->d & String)) {
3776 /* All REP prefixes have the same first termination condition */
c73e197b 3777 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) {
95c55886 3778 ctxt->eip = c->eip;
b9fa9d6b
AK		 3779 goto done;
3780 }
b9fa9d6b
AK		 3781 }
3782
c483c02a 3783 if ((c->src.type == OP_MEM) && !(c->d & NoAccess)) {
3ca3ac4d
AK		 3784 rc = segmented_read(ctxt, c->src.addr.mem,
3785 c->src.valptr, c->src.bytes);
b60d513c 3786 if (rc != X86EMUL_CONTINUE)
8b4caf66 3787 goto done;
16518d5a 3788 c->src.orig_val64 = c->src.val64;
8b4caf66
LV		 3789 }
3790
e35b7b9c 3791 if (c->src2.type == OP_MEM) {
3ca3ac4d
AK		 3792 rc = segmented_read(ctxt, c->src2.addr.mem,
3793 &c->src2.val, c->src2.bytes);
e35b7b9c
GN		 3794 if (rc != X86EMUL_CONTINUE)
3795 goto done;
3796 }
3797
8b4caf66
LV		 3798 if ((c->d & DstMask) == ImplicitOps)
3799 goto special_insn;
3800
3801
69f55cb1
GN		 3802 if ((c->dst.type == OP_MEM) && !(c->d & Mov)) {
3803 /* optimisation - avoid slow emulated read if Mov */
3ca3ac4d 3804 rc = segmented_read(ctxt, c->dst.addr.mem,
9de41573 3805 &c->dst.val, c->dst.bytes);
69f55cb1
GN		 3806 if (rc != X86EMUL_CONTINUE)
3807 goto done;
038e51de 3808 }
e4e03ded 3809 c->dst.orig_val = c->dst.val;
038e51de 3810
018a98db
AK		 3811special_insn:
3812
c4f035c6 3813 if (unlikely(ctxt->guest_mode) && c->intercept) {
8a76d7f2
JR		 3814 rc = emulator_check_intercept(ctxt, c->intercept,
3815 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 3816 if (rc != X86EMUL_CONTINUE)
3817 goto done;
3818 }
3819
ef65c889
AK		 3820 if (c->execute) {
3821 rc = c->execute(ctxt);
3822 if (rc != X86EMUL_CONTINUE)
3823 goto done;
3824 goto writeback;
3825 }
3826
e4e03ded 3827 if (c->twobyte)
6aa8b732
AK		 3828 goto twobyte_insn;
3829
e4e03ded 3830 switch (c->b) {
0934ac9d 3831 case 0x06: /* push es */
4179bb02 3832 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_ES);
0934ac9d
MG		 3833 break;
3834 case 0x07: /* pop es */
0934ac9d 3835 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES);
0934ac9d 3836 break;
0934ac9d 3837 case 0x0e: /* push cs */
4179bb02 3838 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_CS);
0934ac9d 3839 break;
0934ac9d 3840 case 0x16: /* push ss */
4179bb02 3841 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_SS);
0934ac9d
MG		 3842 break;
3843 case 0x17: /* pop ss */
0934ac9d 3844 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS);
0934ac9d 3845 break;
0934ac9d 3846 case 0x1e: /* push ds */
4179bb02 3847 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_DS);
0934ac9d
MG		 3848 break;
3849 case 0x1f: /* pop ds */
0934ac9d 3850 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS);
0934ac9d 3851 break;
33615aa9
AK		 3852 case 0x40 ... 0x47: /* inc r16/r32 */
3853 emulate_1op("inc", c->dst, ctxt->eflags);
3854 break;
3855 case 0x48 ... 0x4f: /* dec r16/r32 */
3856 emulate_1op("dec", c->dst, ctxt->eflags);
3857 break;
6aa8b732 3858 case 0x63: /* movsxd */
8b4caf66 3859 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 3860 goto cannot_emulate;
e4e03ded 3861 c->dst.val = (s32) c->src.val;
6aa8b732 3862 break;
018a98db
AK		 3863 case 0x6c: /* insb */
3864 case 0x6d: /* insw/insd */
a13a63fa
WY		 3865 c->src.val = c->regs[VCPU_REGS_RDX];
3866 goto do_io_in;
018a98db
AK		 3867 case 0x6e: /* outsb */
3868 case 0x6f: /* outsw/outsd */
a13a63fa
WY		 3869 c->dst.val = c->regs[VCPU_REGS_RDX];
3870 goto do_io_out;
7972995b 3871 break;
b2833e3c 3872 case 0x70 ... 0x7f: /* jcc (short) */
018a98db 3873 if (test_cc(c->b, ctxt->eflags))
b2833e3c 3874 jmp_rel(c, c->src.val);
018a98db 3875 break;
6aa8b732 3876 case 0x84 ... 0x85:
dfb507c4 3877 test:
05f086f8 3878 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 3879 break;
3880 case 0x86 ... 0x87: /* xchg */
b13354f8 3881 xchg:
6aa8b732 3882 /* Write back the register source. */
31be40b3
WY		 3883 c->src.val = c->dst.val;
3884 write_register_operand(&c->src);
6aa8b732
AK		 3885 /*
3886 * Write back the memory destination with implicit LOCK
3887 * prefix.
3888 */
31be40b3 3889 c->dst.val = c->src.orig_val;
e4e03ded 3890 c->lock_prefix = 1;
6aa8b732 3891 break;
79168fd1
GN		 3892 case 0x8c: /* mov r/m, sreg */
3893 if (c->modrm_reg > VCPU_SREG_GS) {
35d3d4a1 3894 rc = emulate_ud(ctxt);
5e3ae6c5 3895 goto done;
38d5bc6d 3896 }
1aa36616 3897 c->dst.val = get_segment_selector(ctxt, c->modrm_reg);
38d5bc6d 3898 break;
7e0b54b1 3899 case 0x8d: /* lea r16/r32, m */
90de84f5 3900 c->dst.val = c->src.addr.mem.ea;
7e0b54b1 3901 break;
4257198a
GT		 3902 case 0x8e: { /* mov seg, r/m16 */
3903 uint16_t sel;
4257198a
GT		 3904
3905 sel = c->src.val;
8b9f4414 3906
c697518a
GN		 3907 if (c->modrm_reg == VCPU_SREG_CS ||
3908 c->modrm_reg > VCPU_SREG_GS) {
35d3d4a1 3909 rc = emulate_ud(ctxt);
8b9f4414
GN		 3910 goto done;
3911 }
3912
310b5d30 3913 if (c->modrm_reg == VCPU_SREG_SS)
95cb2295 3914 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
310b5d30 3915
2e873022 3916 rc = load_segment_descriptor(ctxt, ops, sel, c->modrm_reg);
4257198a
GT		 3917
3918 c->dst.type = OP_NONE; /* Disable writeback. */
3919 break;
3920 }
6aa8b732 3921 case 0x8f: /* pop (sole member of Grp1a) */
8cdbd2c9 3922 rc = emulate_grp1a(ctxt, ops);
6aa8b732 3923 break;
3d9e77df
AK		 3924 case 0x90 ... 0x97: /* nop / xchg reg, rax */
3925 if (c->dst.addr.reg == &c->regs[VCPU_REGS_RAX])
34698d8c 3926 break;
b13354f8 3927 goto xchg;
e8b6fa70
WY		 3928 case 0x98: /* cbw/cwde/cdqe */
3929 switch (c->op_bytes) {
3930 case 2: c->dst.val = (s8)c->dst.val; break;
3931 case 4: c->dst.val = (s16)c->dst.val; break;
3932 case 8: c->dst.val = (s32)c->dst.val; break;
3933 }
3934 break;
dfb507c4
MG		 3935 case 0xa8 ... 0xa9: /* test ax, imm */
3936 goto test;
018a98db
AK		 3937 case 0xc0 ... 0xc1:
3938 emulate_grp2(ctxt);
3939 break;
111de5d6 3940 case 0xc3: /* ret */
cf5de4f8 3941 c->dst.type = OP_REG;
1a6440ae 3942 c->dst.addr.reg = &c->eip;
cf5de4f8 3943 c->dst.bytes = c->op_bytes;
c54fe504
TY		 3944 rc = em_pop(ctxt);
3945 break;
09b5f4d3
WY		 3946 case 0xc4: /* les */
3947 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_ES);
09b5f4d3
WY		 3948 break;
3949 case 0xc5: /* lds */
3950 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_DS);
09b5f4d3 3951 break;
a77ab5ea
AK		 3952 case 0xcb: /* ret far */
3953 rc = emulate_ret_far(ctxt, ops);
62bd430e 3954 break;
6e154e56
MG		 3955 case 0xcc: /* int3 */
3956 irq = 3;
3957 goto do_interrupt;
3958 case 0xcd: /* int n */
3959 irq = c->src.val;
3960 do_interrupt:
3961 rc = emulate_int(ctxt, ops, irq);
6e154e56
MG		 3962 break;
3963 case 0xce: /* into */
3964 if (ctxt->eflags & EFLG_OF) {
3965 irq = 4;
3966 goto do_interrupt;
3967 }
3968 break;
62bd430e
MG		 3969 case 0xcf: /* iret */
3970 rc = emulate_iret(ctxt, ops);
a77ab5ea 3971 break;
018a98db 3972 case 0xd0 ... 0xd1: /* Grp2 */
018a98db
AK		 3973 emulate_grp2(ctxt);
3974 break;
3975 case 0xd2 ... 0xd3: /* Grp2 */
3976 c->src.val = c->regs[VCPU_REGS_RCX];
3977 emulate_grp2(ctxt);
3978 break;
f2f31845
WY		 3979 case 0xe0 ... 0xe2: /* loop/loopz/loopnz */
3980 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
3981 if (address_mask(c, c->regs[VCPU_REGS_RCX]) != 0 &&
3982 (c->b == 0xe2 || test_cc(c->b ^ 0x5, ctxt->eflags)))
3983 jmp_rel(c, c->src.val);
3984 break;
e4abac67
WY		 3985 case 0xe3: /* jcxz/jecxz/jrcxz */
3986 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0)
3987 jmp_rel(c, c->src.val);
3988 break;
a6a3034c
MG		 3989 case 0xe4: /* inb */
3990 case 0xe5: /* in */
cf8f70bf 3991 goto do_io_in;
a6a3034c
MG		 3992 case 0xe6: /* outb */
3993 case 0xe7: /* out */
cf8f70bf 3994 goto do_io_out;
1a52e051 3995 case 0xe8: /* call (near) */ {
d53c4777 3996 long int rel = c->src.val;
e4e03ded 3997 c->src.val = (unsigned long) c->eip;
7a957275 3998 jmp_rel(c, rel);
4487b3b4 3999 rc = em_push(ctxt);
8cdbd2c9 4000 break;
1a52e051
NK		 4001 }
4002 case 0xe9: /* jmp rel */
954cd36f 4003 goto jmp;
414e6277
GN		 4004 case 0xea: { /* jmp far */
4005 unsigned short sel;
ea79849d 4006 jump_far:
414e6277
GN		 4007 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
4008
4947e7cd
GN		 4009 rc = load_segment_descriptor(ctxt, ops, sel, VCPU_SREG_CS);
4010 if (rc != X86EMUL_CONTINUE)
c697518a 4011 goto done;
954cd36f 4012
414e6277
GN		 4013 c->eip = 0;
4014 memcpy(&c->eip, c->src.valptr, c->op_bytes);
954cd36f 4015 break;
414e6277 4016 }
954cd36f
GT		 4017 case 0xeb:
4018 jmp: /* jmp rel short */
7a957275 4019 jmp_rel(c, c->src.val);
a01af5ec 4020 c->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 4021 break;
a6a3034c
MG		 4022 case 0xec: /* in al,dx */
4023 case 0xed: /* in (e/r)ax,dx */
cf8f70bf
GN		 4024 c->src.val = c->regs[VCPU_REGS_RDX];
4025 do_io_in:
7b262e90
GN		 4026 if (!pio_in_emulated(ctxt, ops, c->dst.bytes, c->src.val,
4027 &c->dst.val))
cf8f70bf
GN		 4028 goto done; /* IO is needed */
4029 break;
ce7a0ad3
WY		 4030 case 0xee: /* out dx,al */
4031 case 0xef: /* out dx,(e/r)ax */
41167be5 4032 c->dst.val = c->regs[VCPU_REGS_RDX];
cf8f70bf 4033 do_io_out:
ca1d4a9e
AK		 4034 ops->pio_out_emulated(ctxt, c->src.bytes, c->dst.val,
4035 &c->src.val, 1);
cf8f70bf 4036 c->dst.type = OP_NONE; /* Disable writeback. */
e93f36bc 4037 break;
111de5d6 4038 case 0xf4: /* hlt */
6c3287f7 4039 ctxt->ops->halt(ctxt);
19fdfa0d 4040 break;
111de5d6
AK		 4041 case 0xf5: /* cmc */
4042 /* complement carry flag from eflags reg */
4043 ctxt->eflags ^= EFLG_CF;
111de5d6 4044 break;
018a98db 4045 case 0xf6 ... 0xf7: /* Grp3 */
34d1f490 4046 rc = emulate_grp3(ctxt, ops);
018a98db 4047 break;
111de5d6
AK		 4048 case 0xf8: /* clc */
4049 ctxt->eflags &= ~EFLG_CF;
111de5d6 4050 break;
8744aa9a
MG		 4051 case 0xf9: /* stc */
4052 ctxt->eflags |= EFLG_CF;
4053 break;
111de5d6 4054 case 0xfa: /* cli */
07cbc6c1 4055 if (emulator_bad_iopl(ctxt, ops)) {
35d3d4a1 4056 rc = emulate_gp(ctxt, 0);
07cbc6c1 4057 goto done;
36089fed 4058 } else
f850e2e6 4059 ctxt->eflags &= ~X86_EFLAGS_IF;
111de5d6
AK		 4060 break;
4061 case 0xfb: /* sti */
07cbc6c1 4062 if (emulator_bad_iopl(ctxt, ops)) {
35d3d4a1 4063 rc = emulate_gp(ctxt, 0);
07cbc6c1
WY		 4064 goto done;
4065 } else {
95cb2295 4066 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
f850e2e6 4067 ctxt->eflags |= X86_EFLAGS_IF;
f850e2e6 4068 }
111de5d6 4069 break;
fb4616f4
MG		 4070 case 0xfc: /* cld */
4071 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 4072 break;
4073 case 0xfd: /* std */
4074 ctxt->eflags |= EFLG_DF;
fb4616f4 4075 break;
ea79849d
GN		 4076 case 0xfe: /* Grp4 */
4077 grp45:
4487b3b4 4078 rc = emulate_grp45(ctxt);
018a98db 4079 break;
ea79849d
GN		 4080 case 0xff: /* Grp5 */
4081 if (c->modrm_reg == 5)
4082 goto jump_far;
4083 goto grp45;
91269b8f
AK		 4084 default:
4085 goto cannot_emulate;
6aa8b732 4086 }
018a98db 4087
7d9ddaed
AK		 4088 if (rc != X86EMUL_CONTINUE)
4089 goto done;
4090
018a98db
AK		 4091writeback:
4092 rc = writeback(ctxt, ops);
1b30eaa8 4093 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 4094 goto done;
4095
5cd21917
GN		 4096 /*
4097 * restore dst type in case the decoding will be reused
4098 * (happens for string instruction )
4099 */
4100 c->dst.type = saved_dst_type;
4101
a682e354 4102 if ((c->d & SrcMask) == SrcSI)
c1ed6dea 4103 string_addr_inc(ctxt, seg_override(ctxt, c),
79168fd1 4104 VCPU_REGS_RSI, &c->src);
a682e354
GN		 4105
4106 if ((c->d & DstMask) == DstDI)
90de84f5 4107 string_addr_inc(ctxt, VCPU_SREG_ES, VCPU_REGS_RDI,
79168fd1 4108 &c->dst);
d9271123 4109
5cd21917 4110 if (c->rep_prefix && (c->d & String)) {
6e2fb2ca 4111 struct read_cache *r = &ctxt->decode.io_read;
d9271123 4112 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
3e2f65d5 4113
d2ddd1c4
GN		 4114 if (!string_insn_completed(ctxt)) {
4115 /*
4116 * Re-enter guest when pio read ahead buffer is empty
4117 * or, if it is not used, after each 1024 iteration.
4118 */
4119 if ((r->end != 0 || c->regs[VCPU_REGS_RCX] & 0x3ff) &&
4120 (r->end == 0 || r->end != r->pos)) {
4121 /*
4122 * Reset read cache. Usually happens before
4123 * decode, but since instruction is restarted
4124 * we have to do it here.
4125 */
4126 ctxt->decode.mem_read.end = 0;
4127 return EMULATION_RESTART;
4128 }
4129 goto done; /* skip rip writeback */
0fa6ccbd 4130 }
5cd21917 4131 }
d2ddd1c4
GN		 4132
4133 ctxt->eip = c->eip;
018a98db
AK		 4134
4135done:
da9cb575
AK		 4136 if (rc == X86EMUL_PROPAGATE_FAULT)
4137 ctxt->have_exception = true;
775fde86
JR		 4138 if (rc == X86EMUL_INTERCEPTED)
4139 return EMULATION_INTERCEPTED;
4140
d2ddd1c4 4141 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 4142
4143twobyte_insn:
e4e03ded 4144 switch (c->b) {
e99f0507 4145 case 0x05: /* syscall */
3fb1b5db 4146 rc = emulate_syscall(ctxt, ops);
e99f0507 4147 break;
018a98db 4148 case 0x06:
2d04a05b 4149 rc = em_clts(ctxt);
018a98db 4150 break;
018a98db 4151 case 0x09: /* wbinvd */
cfb22375 4152 (ctxt->ops->wbinvd)(ctxt);
f5f48ee1
SY		 4153 break;
4154 case 0x08: /* invd */
018a98db
AK		 4155 case 0x0d: /* GrpP (prefetch) */
4156 case 0x18: /* Grp16 (prefetch/nop) */
018a98db
AK		 4157 break;
4158 case 0x20: /* mov cr, reg */
717746e3 4159 c->dst.val = ops->get_cr(ctxt, c->modrm_reg);
018a98db 4160 break;
6aa8b732 4161 case 0x21: /* mov from dr to reg */
717746e3 4162 ops->get_dr(ctxt, c->modrm_reg, &c->dst.val);
6aa8b732 4163 break;
018a98db 4164 case 0x22: /* mov reg, cr */
717746e3 4165 if (ops->set_cr(ctxt, c->modrm_reg, c->src.val)) {
54b8486f 4166 emulate_gp(ctxt, 0);
da9cb575 4167 rc = X86EMUL_PROPAGATE_FAULT;
0f12244f
GN		 4168 goto done;
4169 }
018a98db
AK		 4170 c->dst.type = OP_NONE;
4171 break;
6aa8b732 4172 case 0x23: /* mov from reg to dr */
717746e3 4173 if (ops->set_dr(ctxt, c->modrm_reg, c->src.val &
338dbc97 4174 ((ctxt->mode == X86EMUL_MODE_PROT64) ?
717746e3 4175 ~0ULL : ~0U)) < 0) {
338dbc97 4176 /* #UD condition is already handled by the code above */
54b8486f 4177 emulate_gp(ctxt, 0);
da9cb575 4178 rc = X86EMUL_PROPAGATE_FAULT;
338dbc97
GN		 4179 goto done;
4180 }
4181
a01af5ec 4182 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 4183 break;
018a98db
AK		 4184 case 0x30:
4185 /* wrmsr */
4186 msr_data = (u32)c->regs[VCPU_REGS_RAX]
4187 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
717746e3 4188 if (ops->set_msr(ctxt, c->regs[VCPU_REGS_RCX], msr_data)) {
54b8486f 4189 emulate_gp(ctxt, 0);
da9cb575 4190 rc = X86EMUL_PROPAGATE_FAULT;
fd525365 4191 goto done;
018a98db
AK		 4192 }
4193 rc = X86EMUL_CONTINUE;
018a98db
AK		 4194 break;
4195 case 0x32:
4196 /* rdmsr */
717746e3 4197 if (ops->get_msr(ctxt, c->regs[VCPU_REGS_RCX], &msr_data)) {
54b8486f 4198 emulate_gp(ctxt, 0);
da9cb575 4199 rc = X86EMUL_PROPAGATE_FAULT;
fd525365 4200 goto done;
018a98db
AK		 4201 } else {
4202 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
4203 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
4204 }
4205 rc = X86EMUL_CONTINUE;
018a98db 4206 break;
e99f0507 4207 case 0x34: /* sysenter */
3fb1b5db 4208 rc = emulate_sysenter(ctxt, ops);
e99f0507
AP		 4209 break;
4210 case 0x35: /* sysexit */
3fb1b5db 4211 rc = emulate_sysexit(ctxt, ops);
e99f0507 4212 break;
6aa8b732 4213 case 0x40 ... 0x4f: /* cmov */
e4e03ded 4214 c->dst.val = c->dst.orig_val = c->src.val;
a01af5ec
LV		 4215 if (!test_cc(c->b, ctxt->eflags))
4216 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 4217 break;
b2833e3c 4218 case 0x80 ... 0x8f: /* jnz rel, etc*/
018a98db 4219 if (test_cc(c->b, ctxt->eflags))
b2833e3c 4220 jmp_rel(c, c->src.val);
018a98db 4221 break;
ee45b58e
WY		 4222 case 0x90 ... 0x9f: /* setcc r/m8 */
4223 c->dst.val = test_cc(c->b, ctxt->eflags);
4224 break;
0934ac9d 4225 case 0xa0: /* push fs */
4179bb02 4226 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_FS);
0934ac9d
MG		 4227 break;
4228 case 0xa1: /* pop fs */
4229 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS);
0934ac9d 4230 break;
7de75248
NK		 4231 case 0xa3:
4232 bt: /* bt */
e4f8e039 4233 c->dst.type = OP_NONE;
e4e03ded
LV		 4234 /* only subword offset */
4235 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 4236 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
7de75248 4237 break;
9bf8ea42
GT		 4238 case 0xa4: /* shld imm8, r, r/m */
4239 case 0xa5: /* shld cl, r, r/m */
4240 emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
4241 break;
0934ac9d 4242 case 0xa8: /* push gs */
4179bb02 4243 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_GS);
0934ac9d
MG		 4244 break;
4245 case 0xa9: /* pop gs */
4246 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS);
0934ac9d 4247 break;
7de75248
NK		 4248 case 0xab:
4249 bts: /* bts */
05f086f8 4250 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
7de75248 4251 break;
9bf8ea42
GT		 4252 case 0xac: /* shrd imm8, r, r/m */
4253 case 0xad: /* shrd cl, r, r/m */
4254 emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags);
4255 break;
2a7c5b8b
GC		 4256 case 0xae: /* clflush */
4257 break;
6aa8b732
AK		 4258 case 0xb0 ... 0xb1: /* cmpxchg */
4259 /*
4260 * Save real source value, then compare EAX against
4261 * destination.
4262 */
e4e03ded
LV		 4263 c->src.orig_val = c->src.val;
4264 c->src.val = c->regs[VCPU_REGS_RAX];
05f086f8
LV		 4265 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
4266 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 4267 /* Success: write back to memory. */
e4e03ded 4268 c->dst.val = c->src.orig_val;
6aa8b732
AK		 4269 } else {
4270 /* Failure: write the value we saw to EAX. */
e4e03ded 4271 c->dst.type = OP_REG;
1a6440ae 4272 c->dst.addr.reg = (unsigned long *)&c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 4273 }
4274 break;
09b5f4d3
WY		 4275 case 0xb2: /* lss */
4276 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_SS);
09b5f4d3 4277 break;
6aa8b732
AK		 4278 case 0xb3:
4279 btr: /* btr */
05f086f8 4280 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
6aa8b732 4281 break;
09b5f4d3
WY		 4282 case 0xb4: /* lfs */
4283 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_FS);
09b5f4d3
WY		 4284 break;
4285 case 0xb5: /* lgs */
4286 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_GS);
09b5f4d3 4287 break;
6aa8b732 4288 case 0xb6 ... 0xb7: /* movzx */
e4e03ded
LV		 4289 c->dst.bytes = c->op_bytes;
4290 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
4291 : (u16) c->src.val;
6aa8b732 4292 break;
6aa8b732 4293 case 0xba: /* Grp8 */
e4e03ded 4294 switch (c->modrm_reg & 3) {
6aa8b732
AK		 4295 case 0:
4296 goto bt;
4297 case 1:
4298 goto bts;
4299 case 2:
4300 goto btr;
4301 case 3:
4302 goto btc;
4303 }
4304 break;
7de75248
NK		 4305 case 0xbb:
4306 btc: /* btc */
05f086f8 4307 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
7de75248 4308 break;
d9574a25
WY		 4309 case 0xbc: { /* bsf */
4310 u8 zf;
4311 __asm__ ("bsf %2, %0; setz %1"
4312 : "=r"(c->dst.val), "=q"(zf)
4313 : "r"(c->src.val));
4314 ctxt->eflags &= ~X86_EFLAGS_ZF;
4315 if (zf) {
4316 ctxt->eflags |= X86_EFLAGS_ZF;
4317 c->dst.type = OP_NONE; /* Disable writeback. */
4318 }
4319 break;
4320 }
4321 case 0xbd: { /* bsr */
4322 u8 zf;
4323 __asm__ ("bsr %2, %0; setz %1"
4324 : "=r"(c->dst.val), "=q"(zf)
4325 : "r"(c->src.val));
4326 ctxt->eflags &= ~X86_EFLAGS_ZF;
4327 if (zf) {
4328 ctxt->eflags |= X86_EFLAGS_ZF;
4329 c->dst.type = OP_NONE; /* Disable writeback. */
4330 }
4331 break;
4332 }
6aa8b732 4333 case 0xbe ... 0xbf: /* movsx */
e4e03ded
LV		 4334 c->dst.bytes = c->op_bytes;
4335 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
4336 (s16) c->src.val;
6aa8b732 4337 break;
92f738a5
WY		 4338 case 0xc0 ... 0xc1: /* xadd */
4339 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
4340 /* Write back the register source. */
4341 c->src.val = c->dst.orig_val;
4342 write_register_operand(&c->src);
4343 break;
a012e65a 4344 case 0xc3: /* movnti */
e4e03ded
LV		 4345 c->dst.bytes = c->op_bytes;
4346 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
4347 (u64) c->src.val;
a012e65a 4348 break;
6aa8b732 4349 case 0xc7: /* Grp9 (cmpxchg8b) */
69f55cb1 4350 rc = emulate_grp9(ctxt, ops);
8cdbd2c9 4351 break;
91269b8f
AK		 4352 default:
4353 goto cannot_emulate;
6aa8b732 4354 }
7d9ddaed
AK		 4355
4356 if (rc != X86EMUL_CONTINUE)
4357 goto done;
4358
6aa8b732
AK		 4359 goto writeback;
4360
4361cannot_emulate:
a0c0ab2f 4362 return EMULATION_FAILED;
6aa8b732 4363}
Linux kernel - Deliverables
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