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KVM: X86: Update last_guest_tsc in vcpu_put
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
6aa8b732 27
3eeb3288 28#include "x86.h"
38ba30ba 29#include "tss.h"
e99f0507 30
6aa8b732
AK		 31/*
32 * Opcode effective-address decode tables.
33 * Note that we only emulate instructions that have at least one memory
34 * operand (excluding implicit stack references). We assume that stack
35 * references and instruction fetches will never occur in special memory
36 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
37 * not be handled.
38 */
39
40/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 41#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 42/* Destination operand type. */
ab85b12b
AK		 43#define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
44#define DstReg (2<<1) /* Register operand. */
45#define DstMem (3<<1) /* Memory operand. */
46#define DstAcc (4<<1) /* Destination Accumulator */
47#define DstDI (5<<1) /* Destination is in ES:(E)DI */
48#define DstMem64 (6<<1) /* 64bit memory operand */
943858e2 49#define DstImmUByte (7<<1) /* 8-bit unsigned immediate operand */
ab85b12b 50#define DstMask (7<<1)
6aa8b732 51/* Source operand type. */
9c9fddd0 52#define SrcNone (0<<4) /* No source operand. */
9c9fddd0
GT		 53#define SrcReg (1<<4) /* Register operand. */
54#define SrcMem (2<<4) /* Memory operand. */
55#define SrcMem16 (3<<4) /* Memory operand (16-bit). */
56#define SrcMem32 (4<<4) /* Memory operand (32-bit). */
57#define SrcImm (5<<4) /* Immediate operand. */
58#define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
bfcadf83 59#define SrcOne (7<<4) /* Implied '1' */
341de7e3 60#define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */
c9eaf20f 61#define SrcImmU (9<<4) /* Immediate operand, unsigned */
a682e354 62#define SrcSI (0xa<<4) /* Source is in the DS:RSI */
414e6277
GN		 63#define SrcImmFAddr (0xb<<4) /* Source is immediate far address */
64#define SrcMemFAddr (0xc<<4) /* Source is far address in memory */
5d55f299 65#define SrcAcc (0xd<<4) /* Source Accumulator */
b250e605 66#define SrcImmU16 (0xe<<4) /* Immediate operand, unsigned, 16 bits */
341de7e3 67#define SrcMask (0xf<<4)
6aa8b732 68/* Generic ModRM decode. */
341de7e3 69#define ModRM (1<<8)
6aa8b732 70/* Destination is only written; never read. */
341de7e3
GN		 71#define Mov (1<<9)
72#define BitOp (1<<10)
73#define MemAbs (1<<11) /* Memory operand is absolute displacement */
9c9fddd0
GT		 74#define String (1<<12) /* String instruction (rep capable) */
75#define Stack (1<<13) /* Stack instruction (push/pop) */
e09d082c
AK		 76#define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
77#define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
0d7cdee8 78#define Prefix (1<<16) /* Instruction varies with 66/f2/f3 prefix */
1253791d 79#define Sse (1<<17) /* SSE Vector instruction */
01de8b09 80#define RMExt (1<<18) /* Opcode extension in ModRM r/m if mod == 3 */
d8769fed 81/* Misc flags */
8ea7d6ae 82#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
d867162c 83#define VendorSpecific (1<<22) /* Vendor specific instruction */
5a506b12 84#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 85#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 86#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 87#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 88#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 89#define No64 (1<<28)
0dc8d10f
GT		 90/* Source 2 operand type */
91#define Src2None (0<<29)
92#define Src2CL (1<<29)
93#define Src2ImmByte (2<<29)
94#define Src2One (3<<29)
7db41eb7 95#define Src2Imm (4<<29)
0dc8d10f 96#define Src2Mask (7<<29)
6aa8b732 97
d0e53325
AK		 98#define X2(x...) x, x
99#define X3(x...) X2(x), x
100#define X4(x...) X2(x), X2(x)
101#define X5(x...) X4(x), x
102#define X6(x...) X4(x), X2(x)
103#define X7(x...) X4(x), X3(x)
104#define X8(x...) X4(x), X4(x)
105#define X16(x...) X8(x), X8(x)
83babbca 106
d65b1dee
AK		 107struct opcode {
108 u32 flags;
c4f035c6 109 u8 intercept;
120df890 110 union {
ef65c889 111 int (*execute)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 112 struct opcode *group;
113 struct group_dual *gdual;
0d7cdee8 114 struct gprefix *gprefix;
120df890 115 } u;
d09beabd 116 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 117};
118
119struct group_dual {
120 struct opcode mod012[8];
121 struct opcode mod3[8];
d65b1dee
AK		 122};
123
0d7cdee8
AK		 124struct gprefix {
125 struct opcode pfx_no;
126 struct opcode pfx_66;
127 struct opcode pfx_f2;
128 struct opcode pfx_f3;
129};
130
6aa8b732 131/* EFLAGS bit definitions. */
d4c6a154
GN		 132#define EFLG_ID (1<<21)
133#define EFLG_VIP (1<<20)
134#define EFLG_VIF (1<<19)
135#define EFLG_AC (1<<18)
b1d86143
AP		 136#define EFLG_VM (1<<17)
137#define EFLG_RF (1<<16)
d4c6a154
GN		 138#define EFLG_IOPL (3<<12)
139#define EFLG_NT (1<<14)
6aa8b732
AK		 140#define EFLG_OF (1<<11)
141#define EFLG_DF (1<<10)
b1d86143 142#define EFLG_IF (1<<9)
d4c6a154 143#define EFLG_TF (1<<8)
6aa8b732
AK		 144#define EFLG_SF (1<<7)
145#define EFLG_ZF (1<<6)
146#define EFLG_AF (1<<4)
147#define EFLG_PF (1<<2)
148#define EFLG_CF (1<<0)
149
62bd430e
MG		 150#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
151#define EFLG_RESERVED_ONE_MASK 2
152
6aa8b732
AK		 153/*
154 * Instruction emulation:
155 * Most instructions are emulated directly via a fragment of inline assembly
156 * code. This allows us to save/restore EFLAGS and thus very easily pick up
157 * any modified flags.
158 */
159
05b3e0c2 160#if defined(CONFIG_X86_64)
6aa8b732
AK		 161#define _LO32 "k" /* force 32-bit operand */
162#define _STK "%%rsp" /* stack pointer */
163#elif defined(__i386__)
164#define _LO32 "" /* force 32-bit operand */
165#define _STK "%%esp" /* stack pointer */
166#endif
167
168/*
169 * These EFLAGS bits are restored from saved value during emulation, and
170 * any changes are written back to the saved value after emulation.
171 */
172#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
173
174/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 175#define _PRE_EFLAGS(_sav, _msk, _tmp) \
176 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
177 "movl %"_sav",%"_LO32 _tmp"; " \
178 "push %"_tmp"; " \
179 "push %"_tmp"; " \
180 "movl %"_msk",%"_LO32 _tmp"; " \
181 "andl %"_LO32 _tmp",("_STK"); " \
182 "pushf; " \
183 "notl %"_LO32 _tmp"; " \
184 "andl %"_LO32 _tmp",("_STK"); " \
185 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
186 "pop %"_tmp"; " \
187 "orl %"_LO32 _tmp",("_STK"); " \
188 "popf; " \
189 "pop %"_sav"; "
6aa8b732
AK		 190
191/* After executing instruction: write-back necessary bits in EFLAGS. */
192#define _POST_EFLAGS(_sav, _msk, _tmp) \
193 /* _sav |= EFLAGS & _msk; */ \
194 "pushf; " \
195 "pop %"_tmp"; " \
196 "andl %"_msk",%"_LO32 _tmp"; " \
197 "orl %"_LO32 _tmp",%"_sav"; "
198
dda96d8f
AK		 199#ifdef CONFIG_X86_64
200#define ON64(x) x
201#else
202#define ON64(x)
203#endif
204
b3b3d25a 205#define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix, _dsttype) \
6b7ad61f
AK		 206 do { \
207 __asm__ __volatile__ ( \
208 _PRE_EFLAGS("0", "4", "2") \
209 _op _suffix " %"_x"3,%1; " \
210 _POST_EFLAGS("0", "4", "2") \
fb2c2641 211 : "=m" (_eflags), "+q" (*(_dsttype*)&(_dst).val),\
6b7ad61f
AK		 212 "=&r" (_tmp) \
213 : _y ((_src).val), "i" (EFLAGS_MASK)); \
f3fd92fb 214 } while (0)
6b7ad61f
AK		 215
216
6aa8b732
AK		 217/* Raw emulation: instruction has two explicit operands. */
218#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 219 do { \
220 unsigned long _tmp; \
221 \
222 switch ((_dst).bytes) { \
223 case 2: \
b3b3d25a 224 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w",u16);\
6b7ad61f
AK		 225 break; \
226 case 4: \
b3b3d25a 227 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l",u32);\
6b7ad61f
AK		 228 break; \
229 case 8: \
b3b3d25a 230 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q",u64)); \
6b7ad61f
AK		 231 break; \
232 } \
6aa8b732
AK		 233 } while (0)
234
235#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
236 do { \
6b7ad61f 237 unsigned long _tmp; \
d77c26fc 238 switch ((_dst).bytes) { \
6aa8b732 239 case 1: \
b3b3d25a 240 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b",u8); \
6aa8b732
AK		 241 break; \
242 default: \
243 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
244 _wx, _wy, _lx, _ly, _qx, _qy); \
245 break; \
246 } \
247 } while (0)
248
249/* Source operand is byte-sized and may be restricted to just %cl. */
250#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
251 __emulate_2op(_op, _src, _dst, _eflags, \
252 "b", "c", "b", "c", "b", "c", "b", "c")
253
254/* Source operand is byte, word, long or quad sized. */
255#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
256 __emulate_2op(_op, _src, _dst, _eflags, \
257 "b", "q", "w", "r", _LO32, "r", "", "r")
258
259/* Source operand is word, long or quad sized. */
260#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
261 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
262 "w", "r", _LO32, "r", "", "r")
263
d175226a
GT		 264/* Instruction has three operands and one operand is stored in ECX register */
265#define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
266 do { \
267 unsigned long _tmp; \
268 _type _clv = (_cl).val; \
269 _type _srcv = (_src).val; \
270 _type _dstv = (_dst).val; \
271 \
272 __asm__ __volatile__ ( \
273 _PRE_EFLAGS("0", "5", "2") \
274 _op _suffix " %4,%1 \n" \
275 _POST_EFLAGS("0", "5", "2") \
276 : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
277 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
278 ); \
279 \
280 (_cl).val = (unsigned long) _clv; \
281 (_src).val = (unsigned long) _srcv; \
282 (_dst).val = (unsigned long) _dstv; \
283 } while (0)
284
285#define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
286 do { \
287 switch ((_dst).bytes) { \
288 case 2: \
289 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
290 "w", unsigned short); \
291 break; \
292 case 4: \
293 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
294 "l", unsigned int); \
295 break; \
296 case 8: \
297 ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
298 "q", unsigned long)); \
299 break; \
300 } \
301 } while (0)
302
dda96d8f 303#define __emulate_1op(_op, _dst, _eflags, _suffix) \
6aa8b732
AK		 304 do { \
305 unsigned long _tmp; \
306 \
dda96d8f
AK		 307 __asm__ __volatile__ ( \
308 _PRE_EFLAGS("0", "3", "2") \
309 _op _suffix " %1; " \
310 _POST_EFLAGS("0", "3", "2") \
311 : "=m" (_eflags), "+m" ((_dst).val), \
312 "=&r" (_tmp) \
313 : "i" (EFLAGS_MASK)); \
314 } while (0)
315
316/* Instruction has only one explicit operand (no source operand). */
317#define emulate_1op(_op, _dst, _eflags) \
318 do { \
d77c26fc 319 switch ((_dst).bytes) { \
dda96d8f
AK		 320 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
321 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
322 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
323 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
6aa8b732
AK		 324 } \
325 } while (0)
326
3f9f53b0
MG		 327#define __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, _suffix) \
328 do { \
329 unsigned long _tmp; \
330 \
331 __asm__ __volatile__ ( \
332 _PRE_EFLAGS("0", "4", "1") \
333 _op _suffix " %5; " \
334 _POST_EFLAGS("0", "4", "1") \
335 : "=m" (_eflags), "=&r" (_tmp), \
336 "+a" (_rax), "+d" (_rdx) \
337 : "i" (EFLAGS_MASK), "m" ((_src).val), \
338 "a" (_rax), "d" (_rdx)); \
339 } while (0)
340
f6b3597b
AK		 341#define __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, _eflags, _suffix, _ex) \
342 do { \
343 unsigned long _tmp; \
344 \
345 __asm__ __volatile__ ( \
346 _PRE_EFLAGS("0", "5", "1") \
347 "1: \n\t" \
348 _op _suffix " %6; " \
349 "2: \n\t" \
350 _POST_EFLAGS("0", "5", "1") \
351 ".pushsection .fixup,\"ax\" \n\t" \
352 "3: movb $1, %4 \n\t" \
353 "jmp 2b \n\t" \
354 ".popsection \n\t" \
355 _ASM_EXTABLE(1b, 3b) \
356 : "=m" (_eflags), "=&r" (_tmp), \
357 "+a" (_rax), "+d" (_rdx), "+qm"(_ex) \
358 : "i" (EFLAGS_MASK), "m" ((_src).val), \
359 "a" (_rax), "d" (_rdx)); \
360 } while (0)
361
3f9f53b0
MG		 362/* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
363#define emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags) \
364 do { \
365 switch((_src).bytes) { \
366 case 1: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "b"); break; \
367 case 2: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "w"); break; \
368 case 4: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "l"); break; \
369 case 8: ON64(__emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "q")); break; \
370 } \
371 } while (0)
372
f6b3597b
AK		 373#define emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, _eflags, _ex) \
374 do { \
375 switch((_src).bytes) { \
376 case 1: \
377 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
378 _eflags, "b", _ex); \
379 break; \
380 case 2: \
381 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
382 _eflags, "w", _ex); \
383 break; \
384 case 4: \
385 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
386 _eflags, "l", _ex); \
387 break; \
388 case 8: ON64( \
389 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
390 _eflags, "q", _ex)); \
391 break; \
392 } \
393 } while (0)
394
6aa8b732
AK		 395/* Fetch next part of the instruction being emulated. */
396#define insn_fetch(_type, _size, _eip) \
397({ unsigned long _x; \
62266869 398 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
af5b4f7f 399 if (rc != X86EMUL_CONTINUE) \
6aa8b732
AK		 400 goto done; \
401 (_eip) += (_size); \
402 (_type)_x; \
403})
404
414e6277
GN		 405#define insn_fetch_arr(_arr, _size, _eip) \
406({ rc = do_insn_fetch(ctxt, ops, (_eip), _arr, (_size)); \
407 if (rc != X86EMUL_CONTINUE) \
408 goto done; \
409 (_eip) += (_size); \
410})
411
8a76d7f2
JR		 412static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
413 enum x86_intercept intercept,
414 enum x86_intercept_stage stage)
415{
416 struct x86_instruction_info info = {
417 .intercept = intercept,
418 .rep_prefix = ctxt->decode.rep_prefix,
419 .modrm_mod = ctxt->decode.modrm_mod,
420 .modrm_reg = ctxt->decode.modrm_reg,
421 .modrm_rm = ctxt->decode.modrm_rm,
422 .src_val = ctxt->decode.src.val64,
423 .src_bytes = ctxt->decode.src.bytes,
424 .dst_bytes = ctxt->decode.dst.bytes,
425 .ad_bytes = ctxt->decode.ad_bytes,
426 .next_rip = ctxt->eip,
427 };
428
429 return ctxt->ops->intercept(ctxt->vcpu, &info, stage);
430}
431
ddcb2885
HH		 432static inline unsigned long ad_mask(struct decode_cache *c)
433{
434 return (1UL << (c->ad_bytes << 3)) - 1;
435}
436
6aa8b732 437/* Access/update address held in a register, based on addressing mode. */
e4706772
HH		 438static inline unsigned long
439address_mask(struct decode_cache *c, unsigned long reg)
440{
441 if (c->ad_bytes == sizeof(unsigned long))
442 return reg;
443 else
444 return reg & ad_mask(c);
445}
446
447static inline unsigned long
90de84f5 448register_address(struct decode_cache *c, unsigned long reg)
e4706772 449{
90de84f5 450 return address_mask(c, reg);
e4706772
HH		 451}
452
7a957275
HH		 453static inline void
454register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
455{
456 if (c->ad_bytes == sizeof(unsigned long))
457 *reg += inc;
458 else
459 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
460}
6aa8b732 461
7a957275
HH		 462static inline void jmp_rel(struct decode_cache *c, int rel)
463{
464 register_address_increment(c, &c->eip, rel);
465}
098c937b 466
56697687
AK		 467static u32 desc_limit_scaled(struct desc_struct *desc)
468{
469 u32 limit = get_desc_limit(desc);
470
471 return desc->g ? (limit << 12) | 0xfff : limit;
472}
473
7a5b56df
AK		 474static void set_seg_override(struct decode_cache *c, int seg)
475{
476 c->has_seg_override = true;
477 c->seg_override = seg;
478}
479
79168fd1
GN		 480static unsigned long seg_base(struct x86_emulate_ctxt *ctxt,
481 struct x86_emulate_ops *ops, int seg)
7a5b56df
AK		 482{
483 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
484 return 0;
485
79168fd1 486 return ops->get_cached_segment_base(seg, ctxt->vcpu);
7a5b56df
AK		 487}
488
90de84f5
AK		 489static unsigned seg_override(struct x86_emulate_ctxt *ctxt,
490 struct x86_emulate_ops *ops,
491 struct decode_cache *c)
7a5b56df
AK		 492{
493 if (!c->has_seg_override)
494 return 0;
495
90de84f5 496 return c->seg_override;
7a5b56df
AK		 497}
498
35d3d4a1
AK		 499static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
500 u32 error, bool valid)
54b8486f 501{
da9cb575
AK		 502 ctxt->exception.vector = vec;
503 ctxt->exception.error_code = error;
504 ctxt->exception.error_code_valid = valid;
35d3d4a1 505 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 506}
507
3b88e41a
JR		 508static int emulate_db(struct x86_emulate_ctxt *ctxt)
509{
510 return emulate_exception(ctxt, DB_VECTOR, 0, false);
511}
512
35d3d4a1 513static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 514{
35d3d4a1 515 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 516}
517
618ff15d
AK		 518static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
519{
520 return emulate_exception(ctxt, SS_VECTOR, err, true);
521}
522
35d3d4a1 523static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 524{
35d3d4a1 525 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 526}
527
35d3d4a1 528static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 529{
35d3d4a1 530 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 531}
532
34d1f490
AK		 533static int emulate_de(struct x86_emulate_ctxt *ctxt)
534{
35d3d4a1 535 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 536}
537
1253791d
AK		 538static int emulate_nm(struct x86_emulate_ctxt *ctxt)
539{
540 return emulate_exception(ctxt, NM_VECTOR, 0, false);
541}
542
52fd8b44
AK		 543static int linearize(struct x86_emulate_ctxt *ctxt,
544 struct segmented_address addr,
545 unsigned size, bool write,
546 ulong *linear)
547{
548 struct decode_cache *c = &ctxt->decode;
618ff15d
AK		 549 struct desc_struct desc;
550 bool usable;
52fd8b44 551 ulong la;
618ff15d
AK		 552 u32 lim;
553 unsigned cpl, rpl;
52fd8b44
AK		 554
555 la = seg_base(ctxt, ctxt->ops, addr.seg) + addr.ea;
618ff15d
AK		 556 switch (ctxt->mode) {
557 case X86EMUL_MODE_REAL:
558 break;
559 case X86EMUL_MODE_PROT64:
560 if (((signed long)la << 16) >> 16 != la)
561 return emulate_gp(ctxt, 0);
562 break;
563 default:
564 usable = ctxt->ops->get_cached_descriptor(&desc, NULL, addr.seg,
565 ctxt->vcpu);
566 if (!usable)
567 goto bad;
568 /* code segment or read-only data segment */
569 if (((desc.type & 8) || !(desc.type & 2)) && write)
570 goto bad;
571 /* unreadable code segment */
572 if ((desc.type & 8) && !(desc.type & 2))
573 goto bad;
574 lim = desc_limit_scaled(&desc);
575 if ((desc.type & 8) || !(desc.type & 4)) {
576 /* expand-up segment */
577 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
578 goto bad;
579 } else {
580 /* exapand-down segment */
581 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
582 goto bad;
583 lim = desc.d ? 0xffffffff : 0xffff;
584 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
585 goto bad;
586 }
587 cpl = ctxt->ops->cpl(ctxt->vcpu);
588 rpl = ctxt->ops->get_segment_selector(addr.seg, ctxt->vcpu) & 3;
589 cpl = max(cpl, rpl);
590 if (!(desc.type & 8)) {
591 /* data segment */
592 if (cpl > desc.dpl)
593 goto bad;
594 } else if ((desc.type & 8) && !(desc.type & 4)) {
595 /* nonconforming code segment */
596 if (cpl != desc.dpl)
597 goto bad;
598 } else if ((desc.type & 8) && (desc.type & 4)) {
599 /* conforming code segment */
600 if (cpl < desc.dpl)
601 goto bad;
602 }
603 break;
604 }
52fd8b44
AK		 605 if (c->ad_bytes != 8)
606 la &= (u32)-1;
607 *linear = la;
608 return X86EMUL_CONTINUE;
618ff15d
AK		 609bad:
610 if (addr.seg == VCPU_SREG_SS)
611 return emulate_ss(ctxt, addr.seg);
612 else
613 return emulate_gp(ctxt, addr.seg);
52fd8b44
AK		 614}
615
3ca3ac4d
AK		 616static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
617 struct segmented_address addr,
618 void *data,
619 unsigned size)
620{
9fa088f4
AK		 621 int rc;
622 ulong linear;
623
83b8795a 624 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 625 if (rc != X86EMUL_CONTINUE)
626 return rc;
627 return ctxt->ops->read_std(linear, data, size, ctxt->vcpu,
3ca3ac4d
AK		 628 &ctxt->exception);
629}
630
62266869
AK		 631static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
632 struct x86_emulate_ops *ops,
2fb53ad8 633 unsigned long eip, u8 *dest)
62266869
AK		 634{
635 struct fetch_cache *fc = &ctxt->decode.fetch;
636 int rc;
2fb53ad8 637 int size, cur_size;
62266869 638
2fb53ad8 639 if (eip == fc->end) {
0521e4c0
NE		 640 unsigned long linear = eip + ctxt->cs_base;
641 if (ctxt->mode != X86EMUL_MODE_PROT64)
642 linear &= (u32)-1;
2fb53ad8
AK		 643 cur_size = fc->end - fc->start;
644 size = min(15UL - cur_size, PAGE_SIZE - offset_in_page(eip));
0521e4c0 645 rc = ops->fetch(linear, fc->data + cur_size,
bcc55cba 646 size, ctxt->vcpu, &ctxt->exception);
3e2815e9 647 if (rc != X86EMUL_CONTINUE)
62266869 648 return rc;
2fb53ad8 649 fc->end += size;
62266869 650 }
2fb53ad8 651 *dest = fc->data[eip - fc->start];
3e2815e9 652 return X86EMUL_CONTINUE;
62266869
AK		 653}
654
655static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
656 struct x86_emulate_ops *ops,
657 unsigned long eip, void *dest, unsigned size)
658{
3e2815e9 659 int rc;
62266869 660
eb3c79e6 661 /* x86 instructions are limited to 15 bytes. */
063db061 662 if (eip + size - ctxt->eip > 15)
eb3c79e6 663 return X86EMUL_UNHANDLEABLE;
62266869
AK		 664 while (size--) {
665 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
3e2815e9 666 if (rc != X86EMUL_CONTINUE)
62266869
AK		 667 return rc;
668 }
3e2815e9 669 return X86EMUL_CONTINUE;
62266869
AK		 670}
671
1e3c5cb0
RR		 672/*
673 * Given the 'reg' portion of a ModRM byte, and a register block, return a
674 * pointer into the block that addresses the relevant register.
675 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
676 */
677static void *decode_register(u8 modrm_reg, unsigned long *regs,
678 int highbyte_regs)
6aa8b732
AK		 679{
680 void *p;
681
682 p = &regs[modrm_reg];
683 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
684 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
685 return p;
686}
687
688static int read_descriptor(struct x86_emulate_ctxt *ctxt,
689 struct x86_emulate_ops *ops,
90de84f5 690 struct segmented_address addr,
6aa8b732
AK		 691 u16 *size, unsigned long *address, int op_bytes)
692{
693 int rc;
694
695 if (op_bytes == 2)
696 op_bytes = 3;
697 *address = 0;
3ca3ac4d 698 rc = segmented_read_std(ctxt, addr, size, 2);
1b30eaa8 699 if (rc != X86EMUL_CONTINUE)
6aa8b732 700 return rc;
30b31ab6 701 addr.ea += 2;
3ca3ac4d 702 rc = segmented_read_std(ctxt, addr, address, op_bytes);
6aa8b732
AK		 703 return rc;
704}
705
bbe9abbd
NK		 706static int test_cc(unsigned int condition, unsigned int flags)
707{
708 int rc = 0;
709
710 switch ((condition & 15) >> 1) {
711 case 0: /* o */
712 rc |= (flags & EFLG_OF);
713 break;
714 case 1: /* b/c/nae */
715 rc |= (flags & EFLG_CF);
716 break;
717 case 2: /* z/e */
718 rc |= (flags & EFLG_ZF);
719 break;
720 case 3: /* be/na */
721 rc |= (flags & (EFLG_CF|EFLG_ZF));
722 break;
723 case 4: /* s */
724 rc |= (flags & EFLG_SF);
725 break;
726 case 5: /* p/pe */
727 rc |= (flags & EFLG_PF);
728 break;
729 case 7: /* le/ng */
730 rc |= (flags & EFLG_ZF);
731 /* fall through */
732 case 6: /* l/nge */
733 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
734 break;
735 }
736
737 /* Odd condition identifiers (lsb == 1) have inverted sense. */
738 return (!!rc ^ (condition & 1));
739}
740
91ff3cb4
AK		 741static void fetch_register_operand(struct operand *op)
742{
743 switch (op->bytes) {
744 case 1:
745 op->val = *(u8 *)op->addr.reg;
746 break;
747 case 2:
748 op->val = *(u16 *)op->addr.reg;
749 break;
750 case 4:
751 op->val = *(u32 *)op->addr.reg;
752 break;
753 case 8:
754 op->val = *(u64 *)op->addr.reg;
755 break;
756 }
757}
758
1253791d
AK		 759static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
760{
761 ctxt->ops->get_fpu(ctxt);
762 switch (reg) {
763 case 0: asm("movdqu %%xmm0, %0" : "=m"(*data)); break;
764 case 1: asm("movdqu %%xmm1, %0" : "=m"(*data)); break;
765 case 2: asm("movdqu %%xmm2, %0" : "=m"(*data)); break;
766 case 3: asm("movdqu %%xmm3, %0" : "=m"(*data)); break;
767 case 4: asm("movdqu %%xmm4, %0" : "=m"(*data)); break;
768 case 5: asm("movdqu %%xmm5, %0" : "=m"(*data)); break;
769 case 6: asm("movdqu %%xmm6, %0" : "=m"(*data)); break;
770 case 7: asm("movdqu %%xmm7, %0" : "=m"(*data)); break;
771#ifdef CONFIG_X86_64
772 case 8: asm("movdqu %%xmm8, %0" : "=m"(*data)); break;
773 case 9: asm("movdqu %%xmm9, %0" : "=m"(*data)); break;
774 case 10: asm("movdqu %%xmm10, %0" : "=m"(*data)); break;
775 case 11: asm("movdqu %%xmm11, %0" : "=m"(*data)); break;
776 case 12: asm("movdqu %%xmm12, %0" : "=m"(*data)); break;
777 case 13: asm("movdqu %%xmm13, %0" : "=m"(*data)); break;
778 case 14: asm("movdqu %%xmm14, %0" : "=m"(*data)); break;
779 case 15: asm("movdqu %%xmm15, %0" : "=m"(*data)); break;
780#endif
781 default: BUG();
782 }
783 ctxt->ops->put_fpu(ctxt);
784}
785
786static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
787 int reg)
788{
789 ctxt->ops->get_fpu(ctxt);
790 switch (reg) {
791 case 0: asm("movdqu %0, %%xmm0" : : "m"(*data)); break;
792 case 1: asm("movdqu %0, %%xmm1" : : "m"(*data)); break;
793 case 2: asm("movdqu %0, %%xmm2" : : "m"(*data)); break;
794 case 3: asm("movdqu %0, %%xmm3" : : "m"(*data)); break;
795 case 4: asm("movdqu %0, %%xmm4" : : "m"(*data)); break;
796 case 5: asm("movdqu %0, %%xmm5" : : "m"(*data)); break;
797 case 6: asm("movdqu %0, %%xmm6" : : "m"(*data)); break;
798 case 7: asm("movdqu %0, %%xmm7" : : "m"(*data)); break;
799#ifdef CONFIG_X86_64
800 case 8: asm("movdqu %0, %%xmm8" : : "m"(*data)); break;
801 case 9: asm("movdqu %0, %%xmm9" : : "m"(*data)); break;
802 case 10: asm("movdqu %0, %%xmm10" : : "m"(*data)); break;
803 case 11: asm("movdqu %0, %%xmm11" : : "m"(*data)); break;
804 case 12: asm("movdqu %0, %%xmm12" : : "m"(*data)); break;
805 case 13: asm("movdqu %0, %%xmm13" : : "m"(*data)); break;
806 case 14: asm("movdqu %0, %%xmm14" : : "m"(*data)); break;
807 case 15: asm("movdqu %0, %%xmm15" : : "m"(*data)); break;
808#endif
809 default: BUG();
810 }
811 ctxt->ops->put_fpu(ctxt);
812}
813
814static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
815 struct operand *op,
3c118e24 816 struct decode_cache *c,
3c118e24
AK		 817 int inhibit_bytereg)
818{
33615aa9 819 unsigned reg = c->modrm_reg;
9f1ef3f8 820 int highbyte_regs = c->rex_prefix == 0;
33615aa9
AK		 821
822 if (!(c->d & ModRM))
823 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
1253791d
AK		 824
825 if (c->d & Sse) {
826 op->type = OP_XMM;
827 op->bytes = 16;
828 op->addr.xmm = reg;
829 read_sse_reg(ctxt, &op->vec_val, reg);
830 return;
831 }
832
3c118e24
AK		 833 op->type = OP_REG;
834 if ((c->d & ByteOp) && !inhibit_bytereg) {
1a6440ae 835 op->addr.reg = decode_register(reg, c->regs, highbyte_regs);
3c118e24
AK		 836 op->bytes = 1;
837 } else {
1a6440ae 838 op->addr.reg = decode_register(reg, c->regs, 0);
3c118e24 839 op->bytes = c->op_bytes;
3c118e24 840 }
91ff3cb4 841 fetch_register_operand(op);
3c118e24
AK		 842 op->orig_val = op->val;
843}
844
1c73ef66 845static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7
AK		 846 struct x86_emulate_ops *ops,
847 struct operand *op)
1c73ef66
AK		 848{
849 struct decode_cache *c = &ctxt->decode;
850 u8 sib;
f5b4edcd 851 int index_reg = 0, base_reg = 0, scale;
3e2815e9 852 int rc = X86EMUL_CONTINUE;
2dbd0dd7 853 ulong modrm_ea = 0;
1c73ef66
AK		 854
855 if (c->rex_prefix) {
856 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
857 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
858 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
859 }
860
861 c->modrm = insn_fetch(u8, 1, c->eip);
862 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
863 c->modrm_reg |= (c->modrm & 0x38) >> 3;
864 c->modrm_rm |= (c->modrm & 0x07);
09ee57cd 865 c->modrm_seg = VCPU_SREG_DS;
1c73ef66
AK		 866
867 if (c->modrm_mod == 3) {
2dbd0dd7
AK		 868 op->type = OP_REG;
869 op->bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
870 op->addr.reg = decode_register(c->modrm_rm,
107d6d2e 871 c->regs, c->d & ByteOp);
1253791d
AK		 872 if (c->d & Sse) {
873 op->type = OP_XMM;
874 op->bytes = 16;
875 op->addr.xmm = c->modrm_rm;
876 read_sse_reg(ctxt, &op->vec_val, c->modrm_rm);
877 return rc;
878 }
2dbd0dd7 879 fetch_register_operand(op);
1c73ef66
AK		 880 return rc;
881 }
882
2dbd0dd7
AK		 883 op->type = OP_MEM;
884
1c73ef66
AK		 885 if (c->ad_bytes == 2) {
886 unsigned bx = c->regs[VCPU_REGS_RBX];
887 unsigned bp = c->regs[VCPU_REGS_RBP];
888 unsigned si = c->regs[VCPU_REGS_RSI];
889 unsigned di = c->regs[VCPU_REGS_RDI];
890
891 /* 16-bit ModR/M decode. */
892 switch (c->modrm_mod) {
893 case 0:
894 if (c->modrm_rm == 6)
2dbd0dd7 895 modrm_ea += insn_fetch(u16, 2, c->eip);
1c73ef66
AK		 896 break;
897 case 1:
2dbd0dd7 898 modrm_ea += insn_fetch(s8, 1, c->eip);
1c73ef66
AK		 899 break;
900 case 2:
2dbd0dd7 901 modrm_ea += insn_fetch(u16, 2, c->eip);
1c73ef66
AK		 902 break;
903 }
904 switch (c->modrm_rm) {
905 case 0:
2dbd0dd7 906 modrm_ea += bx + si;
1c73ef66
AK		 907 break;
908 case 1:
2dbd0dd7 909 modrm_ea += bx + di;
1c73ef66
AK		 910 break;
911 case 2:
2dbd0dd7 912 modrm_ea += bp + si;
1c73ef66
AK		 913 break;
914 case 3:
2dbd0dd7 915 modrm_ea += bp + di;
1c73ef66
AK		 916 break;
917 case 4:
2dbd0dd7 918 modrm_ea += si;
1c73ef66
AK		 919 break;
920 case 5:
2dbd0dd7 921 modrm_ea += di;
1c73ef66
AK		 922 break;
923 case 6:
924 if (c->modrm_mod != 0)
2dbd0dd7 925 modrm_ea += bp;
1c73ef66
AK		 926 break;
927 case 7:
2dbd0dd7 928 modrm_ea += bx;
1c73ef66
AK		 929 break;
930 }
931 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
932 (c->modrm_rm == 6 && c->modrm_mod != 0))
09ee57cd 933 c->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 934 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 935 } else {
936 /* 32/64-bit ModR/M decode. */
84411d85 937 if ((c->modrm_rm & 7) == 4) {
1c73ef66
AK		 938 sib = insn_fetch(u8, 1, c->eip);
939 index_reg |= (sib >> 3) & 7;
940 base_reg |= sib & 7;
941 scale = sib >> 6;
942
dc71d0f1 943 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
2dbd0dd7 944 modrm_ea += insn_fetch(s32, 4, c->eip);
dc71d0f1 945 else
2dbd0dd7 946 modrm_ea += c->regs[base_reg];
dc71d0f1 947 if (index_reg != 4)
2dbd0dd7 948 modrm_ea += c->regs[index_reg] << scale;
84411d85
AK		 949 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
950 if (ctxt->mode == X86EMUL_MODE_PROT64)
f5b4edcd 951 c->rip_relative = 1;
84411d85 952 } else
2dbd0dd7 953 modrm_ea += c->regs[c->modrm_rm];
1c73ef66
AK		 954 switch (c->modrm_mod) {
955 case 0:
956 if (c->modrm_rm == 5)
2dbd0dd7 957 modrm_ea += insn_fetch(s32, 4, c->eip);
1c73ef66
AK		 958 break;
959 case 1:
2dbd0dd7 960 modrm_ea += insn_fetch(s8, 1, c->eip);
1c73ef66
AK		 961 break;
962 case 2:
2dbd0dd7 963 modrm_ea += insn_fetch(s32, 4, c->eip);
1c73ef66
AK		 964 break;
965 }
966 }
90de84f5 967 op->addr.mem.ea = modrm_ea;
1c73ef66
AK		 968done:
969 return rc;
970}
971
972static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7
AK		 973 struct x86_emulate_ops *ops,
974 struct operand *op)
1c73ef66
AK		 975{
976 struct decode_cache *c = &ctxt->decode;
3e2815e9 977 int rc = X86EMUL_CONTINUE;
1c73ef66 978
2dbd0dd7 979 op->type = OP_MEM;
1c73ef66
AK		 980 switch (c->ad_bytes) {
981 case 2:
90de84f5 982 op->addr.mem.ea = insn_fetch(u16, 2, c->eip);
1c73ef66
AK		 983 break;
984 case 4:
90de84f5 985 op->addr.mem.ea = insn_fetch(u32, 4, c->eip);
1c73ef66
AK		 986 break;
987 case 8:
90de84f5 988 op->addr.mem.ea = insn_fetch(u64, 8, c->eip);
1c73ef66
AK		 989 break;
990 }
991done:
992 return rc;
993}
994
35c843c4
WY		 995static void fetch_bit_operand(struct decode_cache *c)
996{
7129eeca 997 long sv = 0, mask;
35c843c4 998
3885f18f 999 if (c->dst.type == OP_MEM && c->src.type == OP_REG) {
35c843c4
WY		 1000 mask = ~(c->dst.bytes * 8 - 1);
1001
1002 if (c->src.bytes == 2)
1003 sv = (s16)c->src.val & (s16)mask;
1004 else if (c->src.bytes == 4)
1005 sv = (s32)c->src.val & (s32)mask;
1006
90de84f5 1007 c->dst.addr.mem.ea += (sv >> 3);
35c843c4 1008 }
ba7ff2b7
WY		 1009
1010 /* only subword offset */
1011 c->src.val &= (c->dst.bytes << 3) - 1;
35c843c4
WY		 1012}
1013
dde7e6d1
AK		 1014static int read_emulated(struct x86_emulate_ctxt *ctxt,
1015 struct x86_emulate_ops *ops,
1016 unsigned long addr, void *dest, unsigned size)
6aa8b732 1017{
dde7e6d1
AK		 1018 int rc;
1019 struct read_cache *mc = &ctxt->decode.mem_read;
6aa8b732 1020
dde7e6d1
AK		 1021 while (size) {
1022 int n = min(size, 8u);
1023 size -= n;
1024 if (mc->pos < mc->end)
1025 goto read_cached;
5cd21917 1026
bcc55cba
AK		 1027 rc = ops->read_emulated(addr, mc->data + mc->end, n,
1028 &ctxt->exception, ctxt->vcpu);
dde7e6d1
AK		 1029 if (rc != X86EMUL_CONTINUE)
1030 return rc;
1031 mc->end += n;
6aa8b732 1032
dde7e6d1
AK		 1033 read_cached:
1034 memcpy(dest, mc->data + mc->pos, n);
1035 mc->pos += n;
1036 dest += n;
1037 addr += n;
6aa8b732 1038 }
dde7e6d1
AK		 1039 return X86EMUL_CONTINUE;
1040}
6aa8b732 1041
3ca3ac4d
AK		 1042static int segmented_read(struct x86_emulate_ctxt *ctxt,
1043 struct segmented_address addr,
1044 void *data,
1045 unsigned size)
1046{
9fa088f4
AK		 1047 int rc;
1048 ulong linear;
1049
83b8795a 1050 rc = linearize(ctxt, addr, size, false, &linear);
9fa088f4
AK		 1051 if (rc != X86EMUL_CONTINUE)
1052 return rc;
1053 return read_emulated(ctxt, ctxt->ops, linear, data, size);
3ca3ac4d
AK		 1054}
1055
1056static int segmented_write(struct x86_emulate_ctxt *ctxt,
1057 struct segmented_address addr,
1058 const void *data,
1059 unsigned size)
1060{
9fa088f4
AK		 1061 int rc;
1062 ulong linear;
1063
83b8795a 1064 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1065 if (rc != X86EMUL_CONTINUE)
1066 return rc;
1067 return ctxt->ops->write_emulated(linear, data, size,
3ca3ac4d
AK		 1068 &ctxt->exception, ctxt->vcpu);
1069}
1070
1071static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1072 struct segmented_address addr,
1073 const void *orig_data, const void *data,
1074 unsigned size)
1075{
9fa088f4
AK		 1076 int rc;
1077 ulong linear;
1078
83b8795a 1079 rc = linearize(ctxt, addr, size, true, &linear);
9fa088f4
AK		 1080 if (rc != X86EMUL_CONTINUE)
1081 return rc;
1082 return ctxt->ops->cmpxchg_emulated(linear, orig_data, data,
3ca3ac4d
AK		 1083 size, &ctxt->exception, ctxt->vcpu);
1084}
1085
dde7e6d1
AK		 1086static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
1087 struct x86_emulate_ops *ops,
1088 unsigned int size, unsigned short port,
1089 void *dest)
1090{
1091 struct read_cache *rc = &ctxt->decode.io_read;
b4c6abfe 1092
dde7e6d1
AK		 1093 if (rc->pos == rc->end) { /* refill pio read ahead */
1094 struct decode_cache *c = &ctxt->decode;
1095 unsigned int in_page, n;
1096 unsigned int count = c->rep_prefix ?
1097 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1;
1098 in_page = (ctxt->eflags & EFLG_DF) ?
1099 offset_in_page(c->regs[VCPU_REGS_RDI]) :
1100 PAGE_SIZE - offset_in_page(c->regs[VCPU_REGS_RDI]);
1101 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1102 count);
1103 if (n == 0)
1104 n = 1;
1105 rc->pos = rc->end = 0;
1106 if (!ops->pio_in_emulated(size, port, rc->data, n, ctxt->vcpu))
1107 return 0;
1108 rc->end = n * size;
6aa8b732
AK		 1109 }
1110
dde7e6d1
AK		 1111 memcpy(dest, rc->data + rc->pos, size);
1112 rc->pos += size;
1113 return 1;
1114}
6aa8b732 1115
dde7e6d1
AK		 1116static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
1117 struct x86_emulate_ops *ops,
1118 u16 selector, struct desc_ptr *dt)
1119{
1120 if (selector & 1 << 2) {
1121 struct desc_struct desc;
1122 memset (dt, 0, sizeof *dt);
5601d05b
GN		 1123 if (!ops->get_cached_descriptor(&desc, NULL, VCPU_SREG_LDTR,
1124 ctxt->vcpu))
dde7e6d1 1125 return;
e09d082c 1126
dde7e6d1
AK		 1127 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1128 dt->address = get_desc_base(&desc);
1129 } else
1130 ops->get_gdt(dt, ctxt->vcpu);
1131}
120df890 1132
dde7e6d1
AK		 1133/* allowed just for 8 bytes segments */
1134static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1135 struct x86_emulate_ops *ops,
1136 u16 selector, struct desc_struct *desc)
1137{
1138 struct desc_ptr dt;
1139 u16 index = selector >> 3;
1140 int ret;
dde7e6d1 1141 ulong addr;
120df890 1142
dde7e6d1 1143 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
120df890 1144
35d3d4a1
AK		 1145 if (dt.size < index * 8 + 7)
1146 return emulate_gp(ctxt, selector & 0xfffc);
dde7e6d1 1147 addr = dt.address + index * 8;
bcc55cba
AK		 1148 ret = ops->read_std(addr, desc, sizeof *desc, ctxt->vcpu,
1149 &ctxt->exception);
e09d082c 1150
dde7e6d1
AK		 1151 return ret;
1152}
ef65c889 1153
dde7e6d1
AK		 1154/* allowed just for 8 bytes segments */
1155static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1156 struct x86_emulate_ops *ops,
1157 u16 selector, struct desc_struct *desc)
1158{
1159 struct desc_ptr dt;
1160 u16 index = selector >> 3;
dde7e6d1
AK		 1161 ulong addr;
1162 int ret;
6aa8b732 1163
dde7e6d1 1164 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
6e3d5dfb 1165
35d3d4a1
AK		 1166 if (dt.size < index * 8 + 7)
1167 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1168
dde7e6d1 1169 addr = dt.address + index * 8;
bcc55cba
AK		 1170 ret = ops->write_std(addr, desc, sizeof *desc, ctxt->vcpu,
1171 &ctxt->exception);
c7e75a3d 1172
dde7e6d1
AK		 1173 return ret;
1174}
c7e75a3d 1175
5601d05b 1176/* Does not support long mode */
dde7e6d1
AK		 1177static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1178 struct x86_emulate_ops *ops,
1179 u16 selector, int seg)
1180{
1181 struct desc_struct seg_desc;
1182 u8 dpl, rpl, cpl;
1183 unsigned err_vec = GP_VECTOR;
1184 u32 err_code = 0;
1185 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
1186 int ret;
69f55cb1 1187
dde7e6d1 1188 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1189
dde7e6d1
AK		 1190 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
1191 || ctxt->mode == X86EMUL_MODE_REAL) {
1192 /* set real mode segment descriptor */
1193 set_desc_base(&seg_desc, selector << 4);
1194 set_desc_limit(&seg_desc, 0xffff);
1195 seg_desc.type = 3;
1196 seg_desc.p = 1;
1197 seg_desc.s = 1;
1198 goto load;
1199 }
1200
1201 /* NULL selector is not valid for TR, CS and SS */
1202 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
1203 && null_selector)
1204 goto exception;
1205
1206 /* TR should be in GDT only */
1207 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1208 goto exception;
1209
1210 if (null_selector) /* for NULL selector skip all following checks */
1211 goto load;
1212
1213 ret = read_segment_descriptor(ctxt, ops, selector, &seg_desc);
1214 if (ret != X86EMUL_CONTINUE)
1215 return ret;
1216
1217 err_code = selector & 0xfffc;
1218 err_vec = GP_VECTOR;
1219
1220 /* can't load system descriptor into segment selecor */
1221 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1222 goto exception;
1223
1224 if (!seg_desc.p) {
1225 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1226 goto exception;
1227 }
1228
1229 rpl = selector & 3;
1230 dpl = seg_desc.dpl;
1231 cpl = ops->cpl(ctxt->vcpu);
1232
1233 switch (seg) {
1234 case VCPU_SREG_SS:
1235 /*
1236 * segment is not a writable data segment or segment
1237 * selector's RPL != CPL or segment selector's RPL != CPL
1238 */
1239 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1240 goto exception;
6aa8b732 1241 break;
dde7e6d1
AK		 1242 case VCPU_SREG_CS:
1243 if (!(seg_desc.type & 8))
1244 goto exception;
1245
1246 if (seg_desc.type & 4) {
1247 /* conforming */
1248 if (dpl > cpl)
1249 goto exception;
1250 } else {
1251 /* nonconforming */
1252 if (rpl > cpl || dpl != cpl)
1253 goto exception;
1254 }
1255 /* CS(RPL) <- CPL */
1256 selector = (selector & 0xfffc) | cpl;
6aa8b732 1257 break;
dde7e6d1
AK		 1258 case VCPU_SREG_TR:
1259 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1260 goto exception;
1261 break;
1262 case VCPU_SREG_LDTR:
1263 if (seg_desc.s || seg_desc.type != 2)
1264 goto exception;
1265 break;
1266 default: /* DS, ES, FS, or GS */
4e62417b 1267 /*
dde7e6d1
AK		 1268 * segment is not a data or readable code segment or
1269 * ((segment is a data or nonconforming code segment)
1270 * and (both RPL and CPL > DPL))
4e62417b 1271 */
dde7e6d1
AK		 1272 if ((seg_desc.type & 0xa) == 0x8 ||
1273 (((seg_desc.type & 0xc) != 0xc) &&
1274 (rpl > dpl && cpl > dpl)))
1275 goto exception;
6aa8b732 1276 break;
dde7e6d1
AK		 1277 }
1278
1279 if (seg_desc.s) {
1280 /* mark segment as accessed */
1281 seg_desc.type |= 1;
1282 ret = write_segment_descriptor(ctxt, ops, selector, &seg_desc);
1283 if (ret != X86EMUL_CONTINUE)
1284 return ret;
1285 }
1286load:
1287 ops->set_segment_selector(selector, seg, ctxt->vcpu);
5601d05b 1288 ops->set_cached_descriptor(&seg_desc, 0, seg, ctxt->vcpu);
dde7e6d1
AK		 1289 return X86EMUL_CONTINUE;
1290exception:
1291 emulate_exception(ctxt, err_vec, err_code, true);
1292 return X86EMUL_PROPAGATE_FAULT;
1293}
1294
31be40b3
WY		 1295static void write_register_operand(struct operand *op)
1296{
1297 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1298 switch (op->bytes) {
1299 case 1:
1300 *(u8 *)op->addr.reg = (u8)op->val;
1301 break;
1302 case 2:
1303 *(u16 *)op->addr.reg = (u16)op->val;
1304 break;
1305 case 4:
1306 *op->addr.reg = (u32)op->val;
1307 break; /* 64b: zero-extend */
1308 case 8:
1309 *op->addr.reg = op->val;
1310 break;
1311 }
1312}
1313
dde7e6d1
AK		 1314static inline int writeback(struct x86_emulate_ctxt *ctxt,
1315 struct x86_emulate_ops *ops)
1316{
1317 int rc;
1318 struct decode_cache *c = &ctxt->decode;
dde7e6d1
AK		 1319
1320 switch (c->dst.type) {
1321 case OP_REG:
31be40b3 1322 write_register_operand(&c->dst);
6aa8b732 1323 break;
dde7e6d1
AK		 1324 case OP_MEM:
1325 if (c->lock_prefix)
3ca3ac4d
AK		 1326 rc = segmented_cmpxchg(ctxt,
1327 c->dst.addr.mem,
1328 &c->dst.orig_val,
1329 &c->dst.val,
1330 c->dst.bytes);
341de7e3 1331 else
3ca3ac4d
AK		 1332 rc = segmented_write(ctxt,
1333 c->dst.addr.mem,
1334 &c->dst.val,
1335 c->dst.bytes);
dde7e6d1
AK		 1336 if (rc != X86EMUL_CONTINUE)
1337 return rc;
a682e354 1338 break;
1253791d
AK		 1339 case OP_XMM:
1340 write_sse_reg(ctxt, &c->dst.vec_val, c->dst.addr.xmm);
1341 break;
dde7e6d1
AK		 1342 case OP_NONE:
1343 /* no writeback */
414e6277 1344 break;
dde7e6d1 1345 default:
414e6277 1346 break;
6aa8b732 1347 }
dde7e6d1
AK		 1348 return X86EMUL_CONTINUE;
1349}
6aa8b732 1350
4487b3b4 1351static int em_push(struct x86_emulate_ctxt *ctxt)
dde7e6d1
AK		 1352{
1353 struct decode_cache *c = &ctxt->decode;
4179bb02 1354 struct segmented_address addr;
0dc8d10f 1355
dde7e6d1 1356 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
4179bb02
TY		 1357 addr.ea = register_address(c, c->regs[VCPU_REGS_RSP]);
1358 addr.seg = VCPU_SREG_SS;
1359
1360 /* Disable writeback. */
1361 c->dst.type = OP_NONE;
1362 return segmented_write(ctxt, addr, &c->src.val, c->op_bytes);
dde7e6d1 1363}
69f55cb1 1364
dde7e6d1
AK		 1365static int emulate_pop(struct x86_emulate_ctxt *ctxt,
1366 struct x86_emulate_ops *ops,
1367 void *dest, int len)
1368{
1369 struct decode_cache *c = &ctxt->decode;
1370 int rc;
90de84f5 1371 struct segmented_address addr;
8b4caf66 1372
90de84f5
AK		 1373 addr.ea = register_address(c, c->regs[VCPU_REGS_RSP]);
1374 addr.seg = VCPU_SREG_SS;
3ca3ac4d 1375 rc = segmented_read(ctxt, addr, dest, len);
dde7e6d1
AK		 1376 if (rc != X86EMUL_CONTINUE)
1377 return rc;
1378
1379 register_address_increment(c, &c->regs[VCPU_REGS_RSP], len);
1380 return rc;
8b4caf66
LV		 1381}
1382
dde7e6d1
AK		 1383static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1384 struct x86_emulate_ops *ops,
1385 void *dest, int len)
9de41573
GN		 1386{
1387 int rc;
dde7e6d1
AK		 1388 unsigned long val, change_mask;
1389 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1390 int cpl = ops->cpl(ctxt->vcpu);
9de41573 1391
dde7e6d1
AK		 1392 rc = emulate_pop(ctxt, ops, &val, len);
1393 if (rc != X86EMUL_CONTINUE)
1394 return rc;
9de41573 1395
dde7e6d1
AK		 1396 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1397 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
9de41573 1398
dde7e6d1
AK		 1399 switch(ctxt->mode) {
1400 case X86EMUL_MODE_PROT64:
1401 case X86EMUL_MODE_PROT32:
1402 case X86EMUL_MODE_PROT16:
1403 if (cpl == 0)
1404 change_mask |= EFLG_IOPL;
1405 if (cpl <= iopl)
1406 change_mask |= EFLG_IF;
1407 break;
1408 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1409 if (iopl < 3)
1410 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1411 change_mask |= EFLG_IF;
1412 break;
1413 default: /* real mode */
1414 change_mask |= (EFLG_IOPL | EFLG_IF);
1415 break;
9de41573 1416 }
dde7e6d1
AK		 1417
1418 *(unsigned long *)dest =
1419 (ctxt->eflags & ~change_mask) | (val & change_mask);
1420
1421 return rc;
9de41573
GN		 1422}
1423
4179bb02
TY		 1424static int emulate_push_sreg(struct x86_emulate_ctxt *ctxt,
1425 struct x86_emulate_ops *ops, int seg)
7b262e90 1426{
dde7e6d1 1427 struct decode_cache *c = &ctxt->decode;
7b262e90 1428
dde7e6d1 1429 c->src.val = ops->get_segment_selector(seg, ctxt->vcpu);
7b262e90 1430
4487b3b4 1431 return em_push(ctxt);
7b262e90
GN		 1432}
1433
dde7e6d1
AK		 1434static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt,
1435 struct x86_emulate_ops *ops, int seg)
38ba30ba 1436{
dde7e6d1
AK		 1437 struct decode_cache *c = &ctxt->decode;
1438 unsigned long selector;
1439 int rc;
38ba30ba 1440
dde7e6d1
AK		 1441 rc = emulate_pop(ctxt, ops, &selector, c->op_bytes);
1442 if (rc != X86EMUL_CONTINUE)
1443 return rc;
1444
1445 rc = load_segment_descriptor(ctxt, ops, (u16)selector, seg);
1446 return rc;
38ba30ba
GN		 1447}
1448
4487b3b4 1449static int emulate_pusha(struct x86_emulate_ctxt *ctxt)
38ba30ba 1450{
dde7e6d1
AK		 1451 struct decode_cache *c = &ctxt->decode;
1452 unsigned long old_esp = c->regs[VCPU_REGS_RSP];
1453 int rc = X86EMUL_CONTINUE;
1454 int reg = VCPU_REGS_RAX;
38ba30ba 1455
dde7e6d1
AK		 1456 while (reg <= VCPU_REGS_RDI) {
1457 (reg == VCPU_REGS_RSP) ?
1458 (c->src.val = old_esp) : (c->src.val = c->regs[reg]);
38ba30ba 1459
4487b3b4 1460 rc = em_push(ctxt);
dde7e6d1
AK		 1461 if (rc != X86EMUL_CONTINUE)
1462 return rc;
38ba30ba 1463
dde7e6d1 1464 ++reg;
38ba30ba 1465 }
38ba30ba 1466
dde7e6d1 1467 return rc;
38ba30ba
GN		 1468}
1469
dde7e6d1
AK		 1470static int emulate_popa(struct x86_emulate_ctxt *ctxt,
1471 struct x86_emulate_ops *ops)
38ba30ba 1472{
dde7e6d1
AK		 1473 struct decode_cache *c = &ctxt->decode;
1474 int rc = X86EMUL_CONTINUE;
1475 int reg = VCPU_REGS_RDI;
38ba30ba 1476
dde7e6d1
AK		 1477 while (reg >= VCPU_REGS_RAX) {
1478 if (reg == VCPU_REGS_RSP) {
1479 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
1480 c->op_bytes);
1481 --reg;
1482 }
38ba30ba 1483
dde7e6d1
AK		 1484 rc = emulate_pop(ctxt, ops, &c->regs[reg], c->op_bytes);
1485 if (rc != X86EMUL_CONTINUE)
1486 break;
1487 --reg;
38ba30ba 1488 }
dde7e6d1 1489 return rc;
38ba30ba
GN		 1490}
1491
6e154e56
MG		 1492int emulate_int_real(struct x86_emulate_ctxt *ctxt,
1493 struct x86_emulate_ops *ops, int irq)
1494{
1495 struct decode_cache *c = &ctxt->decode;
5c56e1cf 1496 int rc;
6e154e56
MG		 1497 struct desc_ptr dt;
1498 gva_t cs_addr;
1499 gva_t eip_addr;
1500 u16 cs, eip;
6e154e56
MG		 1501
1502 /* TODO: Add limit checks */
1503 c->src.val = ctxt->eflags;
4487b3b4 1504 rc = em_push(ctxt);
5c56e1cf
AK		 1505 if (rc != X86EMUL_CONTINUE)
1506 return rc;
6e154e56
MG		 1507
1508 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1509
1510 c->src.val = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
4487b3b4 1511 rc = em_push(ctxt);
5c56e1cf
AK		 1512 if (rc != X86EMUL_CONTINUE)
1513 return rc;
6e154e56
MG		 1514
1515 c->src.val = c->eip;
4487b3b4 1516 rc = em_push(ctxt);
5c56e1cf
AK		 1517 if (rc != X86EMUL_CONTINUE)
1518 return rc;
1519
6e154e56
MG		 1520 ops->get_idt(&dt, ctxt->vcpu);
1521
1522 eip_addr = dt.address + (irq << 2);
1523 cs_addr = dt.address + (irq << 2) + 2;
1524
bcc55cba 1525 rc = ops->read_std(cs_addr, &cs, 2, ctxt->vcpu, &ctxt->exception);
6e154e56
MG		 1526 if (rc != X86EMUL_CONTINUE)
1527 return rc;
1528
bcc55cba 1529 rc = ops->read_std(eip_addr, &eip, 2, ctxt->vcpu, &ctxt->exception);
6e154e56
MG		 1530 if (rc != X86EMUL_CONTINUE)
1531 return rc;
1532
1533 rc = load_segment_descriptor(ctxt, ops, cs, VCPU_SREG_CS);
1534 if (rc != X86EMUL_CONTINUE)
1535 return rc;
1536
1537 c->eip = eip;
1538
1539 return rc;
1540}
1541
1542static int emulate_int(struct x86_emulate_ctxt *ctxt,
1543 struct x86_emulate_ops *ops, int irq)
1544{
1545 switch(ctxt->mode) {
1546 case X86EMUL_MODE_REAL:
1547 return emulate_int_real(ctxt, ops, irq);
1548 case X86EMUL_MODE_VM86:
1549 case X86EMUL_MODE_PROT16:
1550 case X86EMUL_MODE_PROT32:
1551 case X86EMUL_MODE_PROT64:
1552 default:
1553 /* Protected mode interrupts unimplemented yet */
1554 return X86EMUL_UNHANDLEABLE;
1555 }
1556}
1557
dde7e6d1
AK		 1558static int emulate_iret_real(struct x86_emulate_ctxt *ctxt,
1559 struct x86_emulate_ops *ops)
38ba30ba 1560{
dde7e6d1
AK		 1561 struct decode_cache *c = &ctxt->decode;
1562 int rc = X86EMUL_CONTINUE;
1563 unsigned long temp_eip = 0;
1564 unsigned long temp_eflags = 0;
1565 unsigned long cs = 0;
1566 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1567 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1568 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1569 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1570
dde7e6d1 1571 /* TODO: Add stack limit check */
38ba30ba 1572
dde7e6d1 1573 rc = emulate_pop(ctxt, ops, &temp_eip, c->op_bytes);
38ba30ba 1574
dde7e6d1
AK		 1575 if (rc != X86EMUL_CONTINUE)
1576 return rc;
38ba30ba 1577
35d3d4a1
AK		 1578 if (temp_eip & ~0xffff)
1579 return emulate_gp(ctxt, 0);
38ba30ba 1580
dde7e6d1 1581 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
38ba30ba 1582
dde7e6d1
AK		 1583 if (rc != X86EMUL_CONTINUE)
1584 return rc;
38ba30ba 1585
dde7e6d1 1586 rc = emulate_pop(ctxt, ops, &temp_eflags, c->op_bytes);
38ba30ba 1587
dde7e6d1
AK		 1588 if (rc != X86EMUL_CONTINUE)
1589 return rc;
38ba30ba 1590
dde7e6d1 1591 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
38ba30ba 1592
dde7e6d1
AK		 1593 if (rc != X86EMUL_CONTINUE)
1594 return rc;
38ba30ba 1595
dde7e6d1 1596 c->eip = temp_eip;
38ba30ba 1597
38ba30ba 1598
dde7e6d1
AK		 1599 if (c->op_bytes == 4)
1600 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
1601 else if (c->op_bytes == 2) {
1602 ctxt->eflags &= ~0xffff;
1603 ctxt->eflags |= temp_eflags;
38ba30ba 1604 }
dde7e6d1
AK		 1605
1606 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1607 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1608
1609 return rc;
38ba30ba
GN		 1610}
1611
dde7e6d1
AK		 1612static inline int emulate_iret(struct x86_emulate_ctxt *ctxt,
1613 struct x86_emulate_ops* ops)
c37eda13 1614{
dde7e6d1
AK		 1615 switch(ctxt->mode) {
1616 case X86EMUL_MODE_REAL:
1617 return emulate_iret_real(ctxt, ops);
1618 case X86EMUL_MODE_VM86:
1619 case X86EMUL_MODE_PROT16:
1620 case X86EMUL_MODE_PROT32:
1621 case X86EMUL_MODE_PROT64:
c37eda13 1622 default:
dde7e6d1
AK		 1623 /* iret from protected mode unimplemented yet */
1624 return X86EMUL_UNHANDLEABLE;
c37eda13 1625 }
c37eda13
WY		 1626}
1627
dde7e6d1 1628static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
79168fd1 1629 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1630{
1631 struct decode_cache *c = &ctxt->decode;
1632
dde7e6d1 1633 return emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes);
8cdbd2c9
LV		 1634}
1635
dde7e6d1 1636static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1637{
05f086f8 1638 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1639 switch (c->modrm_reg) {
1640 case 0: /* rol */
05f086f8 1641 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1642 break;
1643 case 1: /* ror */
05f086f8 1644 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1645 break;
1646 case 2: /* rcl */
05f086f8 1647 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1648 break;
1649 case 3: /* rcr */
05f086f8 1650 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1651 break;
1652 case 4: /* sal/shl */
1653 case 6: /* sal/shl */
05f086f8 1654 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1655 break;
1656 case 5: /* shr */
05f086f8 1657 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1658 break;
1659 case 7: /* sar */
05f086f8 1660 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1661 break;
1662 }
1663}
1664
1665static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
05f086f8 1666 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1667{
1668 struct decode_cache *c = &ctxt->decode;
3f9f53b0
MG		 1669 unsigned long *rax = &c->regs[VCPU_REGS_RAX];
1670 unsigned long *rdx = &c->regs[VCPU_REGS_RDX];
34d1f490 1671 u8 de = 0;
8cdbd2c9
LV		 1672
1673 switch (c->modrm_reg) {
1674 case 0 ... 1: /* test */
05f086f8 1675 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1676 break;
1677 case 2: /* not */
1678 c->dst.val = ~c->dst.val;
1679 break;
1680 case 3: /* neg */
05f086f8 1681 emulate_1op("neg", c->dst, ctxt->eflags);
8cdbd2c9 1682 break;
3f9f53b0
MG		 1683 case 4: /* mul */
1684 emulate_1op_rax_rdx("mul", c->src, *rax, *rdx, ctxt->eflags);
1685 break;
1686 case 5: /* imul */
1687 emulate_1op_rax_rdx("imul", c->src, *rax, *rdx, ctxt->eflags);
1688 break;
1689 case 6: /* div */
34d1f490
AK		 1690 emulate_1op_rax_rdx_ex("div", c->src, *rax, *rdx,
1691 ctxt->eflags, de);
3f9f53b0
MG		 1692 break;
1693 case 7: /* idiv */
34d1f490
AK		 1694 emulate_1op_rax_rdx_ex("idiv", c->src, *rax, *rdx,
1695 ctxt->eflags, de);
3f9f53b0 1696 break;
8cdbd2c9 1697 default:
8c5eee30 1698 return X86EMUL_UNHANDLEABLE;
8cdbd2c9 1699 }
34d1f490
AK		 1700 if (de)
1701 return emulate_de(ctxt);
8c5eee30 1702 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1703}
1704
4487b3b4 1705static int emulate_grp45(struct x86_emulate_ctxt *ctxt)
8cdbd2c9
LV		 1706{
1707 struct decode_cache *c = &ctxt->decode;
4179bb02 1708 int rc = X86EMUL_CONTINUE;
8cdbd2c9
LV		 1709
1710 switch (c->modrm_reg) {
1711 case 0: /* inc */
05f086f8 1712 emulate_1op("inc", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1713 break;
1714 case 1: /* dec */
05f086f8 1715 emulate_1op("dec", c->dst, ctxt->eflags);
8cdbd2c9 1716 break;
d19292e4
MG		 1717 case 2: /* call near abs */ {
1718 long int old_eip;
1719 old_eip = c->eip;
1720 c->eip = c->src.val;
1721 c->src.val = old_eip;
4487b3b4 1722 rc = em_push(ctxt);
d19292e4
MG		 1723 break;
1724 }
8cdbd2c9 1725 case 4: /* jmp abs */
fd60754e 1726 c->eip = c->src.val;
8cdbd2c9
LV		 1727 break;
1728 case 6: /* push */
4487b3b4 1729 rc = em_push(ctxt);
8cdbd2c9 1730 break;
8cdbd2c9 1731 }
4179bb02 1732 return rc;
8cdbd2c9
LV		 1733}
1734
1735static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
69f55cb1 1736 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1737{
1738 struct decode_cache *c = &ctxt->decode;
16518d5a 1739 u64 old = c->dst.orig_val64;
8cdbd2c9
LV		 1740
1741 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1742 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
8cdbd2c9
LV		 1743 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1744 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1745 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 1746 } else {
16518d5a
AK		 1747 c->dst.val64 = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1748 (u32) c->regs[VCPU_REGS_RBX];
8cdbd2c9 1749
05f086f8 1750 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 1751 }
1b30eaa8 1752 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1753}
1754
a77ab5ea
AK		 1755static int emulate_ret_far(struct x86_emulate_ctxt *ctxt,
1756 struct x86_emulate_ops *ops)
1757{
1758 struct decode_cache *c = &ctxt->decode;
1759 int rc;
1760 unsigned long cs;
1761
1762 rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes);
1b30eaa8 1763 if (rc != X86EMUL_CONTINUE)
a77ab5ea
AK		 1764 return rc;
1765 if (c->op_bytes == 4)
1766 c->eip = (u32)c->eip;
1767 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1b30eaa8 1768 if (rc != X86EMUL_CONTINUE)
a77ab5ea 1769 return rc;
2e873022 1770 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 1771 return rc;
1772}
1773
09b5f4d3
WY		 1774static int emulate_load_segment(struct x86_emulate_ctxt *ctxt,
1775 struct x86_emulate_ops *ops, int seg)
1776{
1777 struct decode_cache *c = &ctxt->decode;
1778 unsigned short sel;
1779 int rc;
1780
1781 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
1782
1783 rc = load_segment_descriptor(ctxt, ops, sel, seg);
1784 if (rc != X86EMUL_CONTINUE)
1785 return rc;
1786
1787 c->dst.val = c->src.val;
1788 return rc;
1789}
1790
e66bb2cc
AP		 1791static inline void
1792setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
79168fd1
GN		 1793 struct x86_emulate_ops *ops, struct desc_struct *cs,
1794 struct desc_struct *ss)
e66bb2cc 1795{
79168fd1 1796 memset(cs, 0, sizeof(struct desc_struct));
5601d05b 1797 ops->get_cached_descriptor(cs, NULL, VCPU_SREG_CS, ctxt->vcpu);
79168fd1 1798 memset(ss, 0, sizeof(struct desc_struct));
e66bb2cc
AP		 1799
1800 cs->l = 0; /* will be adjusted later */
79168fd1 1801 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 1802 cs->g = 1; /* 4kb granularity */
79168fd1 1803 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1804 cs->type = 0x0b; /* Read, Execute, Accessed */
1805 cs->s = 1;
1806 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 1807 cs->p = 1;
1808 cs->d = 1;
e66bb2cc 1809
79168fd1
GN		 1810 set_desc_base(ss, 0); /* flat segment */
1811 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1812 ss->g = 1; /* 4kb granularity */
1813 ss->s = 1;
1814 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 1815 ss->d = 1; /* 32bit stack segment */
e66bb2cc 1816 ss->dpl = 0;
79168fd1 1817 ss->p = 1;
e66bb2cc
AP		 1818}
1819
1820static int
3fb1b5db 1821emulate_syscall(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
e66bb2cc
AP		 1822{
1823 struct decode_cache *c = &ctxt->decode;
79168fd1 1824 struct desc_struct cs, ss;
e66bb2cc 1825 u64 msr_data;
79168fd1 1826 u16 cs_sel, ss_sel;
e66bb2cc
AP		 1827
1828 /* syscall is not available in real mode */
2e901c4c 1829 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 1830 ctxt->mode == X86EMUL_MODE_VM86)
1831 return emulate_ud(ctxt);
e66bb2cc 1832
79168fd1 1833 setup_syscalls_segments(ctxt, ops, &cs, &ss);
e66bb2cc 1834
3fb1b5db 1835 ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
e66bb2cc 1836 msr_data >>= 32;
79168fd1
GN		 1837 cs_sel = (u16)(msr_data & 0xfffc);
1838 ss_sel = (u16)(msr_data + 8);
e66bb2cc
AP		 1839
1840 if (is_long_mode(ctxt->vcpu)) {
79168fd1 1841 cs.d = 0;
e66bb2cc
AP		 1842 cs.l = 1;
1843 }
5601d05b 1844 ops->set_cached_descriptor(&cs, 0, VCPU_SREG_CS, ctxt->vcpu);
79168fd1 1845 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
5601d05b 1846 ops->set_cached_descriptor(&ss, 0, VCPU_SREG_SS, ctxt->vcpu);
79168fd1 1847 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
e66bb2cc
AP		 1848
1849 c->regs[VCPU_REGS_RCX] = c->eip;
1850 if (is_long_mode(ctxt->vcpu)) {
1851#ifdef CONFIG_X86_64
1852 c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
1853
3fb1b5db
GN		 1854 ops->get_msr(ctxt->vcpu,
1855 ctxt->mode == X86EMUL_MODE_PROT64 ?
1856 MSR_LSTAR : MSR_CSTAR, &msr_data);
e66bb2cc
AP		 1857 c->eip = msr_data;
1858
3fb1b5db 1859 ops->get_msr(ctxt->vcpu, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 1860 ctxt->eflags &= ~(msr_data | EFLG_RF);
1861#endif
1862 } else {
1863 /* legacy mode */
3fb1b5db 1864 ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
e66bb2cc
AP		 1865 c->eip = (u32)msr_data;
1866
1867 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1868 }
1869
e54cfa97 1870 return X86EMUL_CONTINUE;
e66bb2cc
AP		 1871}
1872
8c604352 1873static int
3fb1b5db 1874emulate_sysenter(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8c604352
AP		 1875{
1876 struct decode_cache *c = &ctxt->decode;
79168fd1 1877 struct desc_struct cs, ss;
8c604352 1878 u64 msr_data;
79168fd1 1879 u16 cs_sel, ss_sel;
8c604352 1880
a0044755 1881 /* inject #GP if in real mode */
35d3d4a1
AK		 1882 if (ctxt->mode == X86EMUL_MODE_REAL)
1883 return emulate_gp(ctxt, 0);
8c604352
AP		 1884
1885 /* XXX sysenter/sysexit have not been tested in 64bit mode.
1886 * Therefore, we inject an #UD.
1887 */
35d3d4a1
AK		 1888 if (ctxt->mode == X86EMUL_MODE_PROT64)
1889 return emulate_ud(ctxt);
8c604352 1890
79168fd1 1891 setup_syscalls_segments(ctxt, ops, &cs, &ss);
8c604352 1892
3fb1b5db 1893 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 1894 switch (ctxt->mode) {
1895 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 1896 if ((msr_data & 0xfffc) == 0x0)
1897 return emulate_gp(ctxt, 0);
8c604352
AP		 1898 break;
1899 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 1900 if (msr_data == 0x0)
1901 return emulate_gp(ctxt, 0);
8c604352
AP		 1902 break;
1903 }
1904
1905 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 1906 cs_sel = (u16)msr_data;
1907 cs_sel &= ~SELECTOR_RPL_MASK;
1908 ss_sel = cs_sel + 8;
1909 ss_sel &= ~SELECTOR_RPL_MASK;
8c604352
AP		 1910 if (ctxt->mode == X86EMUL_MODE_PROT64
1911 || is_long_mode(ctxt->vcpu)) {
79168fd1 1912 cs.d = 0;
8c604352
AP		 1913 cs.l = 1;
1914 }
1915
5601d05b 1916 ops->set_cached_descriptor(&cs, 0, VCPU_SREG_CS, ctxt->vcpu);
79168fd1 1917 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
5601d05b 1918 ops->set_cached_descriptor(&ss, 0, VCPU_SREG_SS, ctxt->vcpu);
79168fd1 1919 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
8c604352 1920
3fb1b5db 1921 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_EIP, &msr_data);
8c604352
AP		 1922 c->eip = msr_data;
1923
3fb1b5db 1924 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_ESP, &msr_data);
8c604352
AP		 1925 c->regs[VCPU_REGS_RSP] = msr_data;
1926
e54cfa97 1927 return X86EMUL_CONTINUE;
8c604352
AP		 1928}
1929
4668f050 1930static int
3fb1b5db 1931emulate_sysexit(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
4668f050
AP		 1932{
1933 struct decode_cache *c = &ctxt->decode;
79168fd1 1934 struct desc_struct cs, ss;
4668f050
AP		 1935 u64 msr_data;
1936 int usermode;
79168fd1 1937 u16 cs_sel, ss_sel;
4668f050 1938
a0044755
GN		 1939 /* inject #GP if in real mode or Virtual 8086 mode */
1940 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 1941 ctxt->mode == X86EMUL_MODE_VM86)
1942 return emulate_gp(ctxt, 0);
4668f050 1943
79168fd1 1944 setup_syscalls_segments(ctxt, ops, &cs, &ss);
4668f050
AP		 1945
1946 if ((c->rex_prefix & 0x8) != 0x0)
1947 usermode = X86EMUL_MODE_PROT64;
1948 else
1949 usermode = X86EMUL_MODE_PROT32;
1950
1951 cs.dpl = 3;
1952 ss.dpl = 3;
3fb1b5db 1953 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 1954 switch (usermode) {
1955 case X86EMUL_MODE_PROT32:
79168fd1 1956 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 1957 if ((msr_data & 0xfffc) == 0x0)
1958 return emulate_gp(ctxt, 0);
79168fd1 1959 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 1960 break;
1961 case X86EMUL_MODE_PROT64:
79168fd1 1962 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 1963 if (msr_data == 0x0)
1964 return emulate_gp(ctxt, 0);
79168fd1
GN		 1965 ss_sel = cs_sel + 8;
1966 cs.d = 0;
4668f050
AP		 1967 cs.l = 1;
1968 break;
1969 }
79168fd1
GN		 1970 cs_sel |= SELECTOR_RPL_MASK;
1971 ss_sel |= SELECTOR_RPL_MASK;
4668f050 1972
5601d05b 1973 ops->set_cached_descriptor(&cs, 0, VCPU_SREG_CS, ctxt->vcpu);
79168fd1 1974 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
5601d05b 1975 ops->set_cached_descriptor(&ss, 0, VCPU_SREG_SS, ctxt->vcpu);
79168fd1 1976 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
4668f050 1977
bdb475a3
GN		 1978 c->eip = c->regs[VCPU_REGS_RDX];
1979 c->regs[VCPU_REGS_RSP] = c->regs[VCPU_REGS_RCX];
4668f050 1980
e54cfa97 1981 return X86EMUL_CONTINUE;
4668f050
AP		 1982}
1983
9c537244
GN		 1984static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt,
1985 struct x86_emulate_ops *ops)
f850e2e6
GN		 1986{
1987 int iopl;
1988 if (ctxt->mode == X86EMUL_MODE_REAL)
1989 return false;
1990 if (ctxt->mode == X86EMUL_MODE_VM86)
1991 return true;
1992 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
9c537244 1993 return ops->cpl(ctxt->vcpu) > iopl;
f850e2e6
GN		 1994}
1995
1996static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
1997 struct x86_emulate_ops *ops,
1998 u16 port, u16 len)
1999{
79168fd1 2000 struct desc_struct tr_seg;
5601d05b 2001 u32 base3;
f850e2e6 2002 int r;
399a40c9 2003 u16 io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 2004 unsigned mask = (1 << len) - 1;
5601d05b 2005 unsigned long base;
f850e2e6 2006
5601d05b 2007 ops->get_cached_descriptor(&tr_seg, &base3, VCPU_SREG_TR, ctxt->vcpu);
79168fd1 2008 if (!tr_seg.p)
f850e2e6 2009 return false;
79168fd1 2010 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 2011 return false;
5601d05b
GN		 2012 base = get_desc_base(&tr_seg);
2013#ifdef CONFIG_X86_64
2014 base |= ((u64)base3) << 32;
2015#endif
2016 r = ops->read_std(base + 102, &io_bitmap_ptr, 2, ctxt->vcpu, NULL);
f850e2e6
GN		 2017 if (r != X86EMUL_CONTINUE)
2018 return false;
79168fd1 2019 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 2020 return false;
399a40c9 2021 r = ops->read_std(base + io_bitmap_ptr + port/8, &perm, 2, ctxt->vcpu,
5601d05b 2022 NULL);
f850e2e6
GN		 2023 if (r != X86EMUL_CONTINUE)
2024 return false;
2025 if ((perm >> bit_idx) & mask)
2026 return false;
2027 return true;
2028}
2029
2030static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
2031 struct x86_emulate_ops *ops,
2032 u16 port, u16 len)
2033{
4fc40f07
GN		 2034 if (ctxt->perm_ok)
2035 return true;
2036
9c537244 2037 if (emulator_bad_iopl(ctxt, ops))
f850e2e6
GN		 2038 if (!emulator_io_port_access_allowed(ctxt, ops, port, len))
2039 return false;
4fc40f07
GN		 2040
2041 ctxt->perm_ok = true;
2042
f850e2e6
GN		 2043 return true;
2044}
2045
38ba30ba
GN		 2046static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
2047 struct x86_emulate_ops *ops,
2048 struct tss_segment_16 *tss)
2049{
2050 struct decode_cache *c = &ctxt->decode;
2051
2052 tss->ip = c->eip;
2053 tss->flag = ctxt->eflags;
2054 tss->ax = c->regs[VCPU_REGS_RAX];
2055 tss->cx = c->regs[VCPU_REGS_RCX];
2056 tss->dx = c->regs[VCPU_REGS_RDX];
2057 tss->bx = c->regs[VCPU_REGS_RBX];
2058 tss->sp = c->regs[VCPU_REGS_RSP];
2059 tss->bp = c->regs[VCPU_REGS_RBP];
2060 tss->si = c->regs[VCPU_REGS_RSI];
2061 tss->di = c->regs[VCPU_REGS_RDI];
2062
2063 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
2064 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
2065 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
2066 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
2067 tss->ldt = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
2068}
2069
2070static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
2071 struct x86_emulate_ops *ops,
2072 struct tss_segment_16 *tss)
2073{
2074 struct decode_cache *c = &ctxt->decode;
2075 int ret;
2076
2077 c->eip = tss->ip;
2078 ctxt->eflags = tss->flag | 2;
2079 c->regs[VCPU_REGS_RAX] = tss->ax;
2080 c->regs[VCPU_REGS_RCX] = tss->cx;
2081 c->regs[VCPU_REGS_RDX] = tss->dx;
2082 c->regs[VCPU_REGS_RBX] = tss->bx;
2083 c->regs[VCPU_REGS_RSP] = tss->sp;
2084 c->regs[VCPU_REGS_RBP] = tss->bp;
2085 c->regs[VCPU_REGS_RSI] = tss->si;
2086 c->regs[VCPU_REGS_RDI] = tss->di;
2087
2088 /*
2089 * SDM says that segment selectors are loaded before segment
2090 * descriptors
2091 */
2092 ops->set_segment_selector(tss->ldt, VCPU_SREG_LDTR, ctxt->vcpu);
2093 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
2094 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
2095 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
2096 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
2097
2098 /*
2099 * Now load segment descriptors. If fault happenes at this stage
2100 * it is handled in a context of new task
2101 */
2102 ret = load_segment_descriptor(ctxt, ops, tss->ldt, VCPU_SREG_LDTR);
2103 if (ret != X86EMUL_CONTINUE)
2104 return ret;
2105 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2106 if (ret != X86EMUL_CONTINUE)
2107 return ret;
2108 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2109 if (ret != X86EMUL_CONTINUE)
2110 return ret;
2111 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2112 if (ret != X86EMUL_CONTINUE)
2113 return ret;
2114 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2115 if (ret != X86EMUL_CONTINUE)
2116 return ret;
2117
2118 return X86EMUL_CONTINUE;
2119}
2120
2121static int task_switch_16(struct x86_emulate_ctxt *ctxt,
2122 struct x86_emulate_ops *ops,
2123 u16 tss_selector, u16 old_tss_sel,
2124 ulong old_tss_base, struct desc_struct *new_desc)
2125{
2126 struct tss_segment_16 tss_seg;
2127 int ret;
bcc55cba 2128 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba
GN		 2129
2130 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
bcc55cba 2131 &ctxt->exception);
db297e3d 2132 if (ret != X86EMUL_CONTINUE)
38ba30ba 2133 /* FIXME: need to provide precise fault address */
38ba30ba 2134 return ret;
38ba30ba
GN		 2135
2136 save_state_to_tss16(ctxt, ops, &tss_seg);
2137
2138 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
bcc55cba 2139 &ctxt->exception);
db297e3d 2140 if (ret != X86EMUL_CONTINUE)
38ba30ba 2141 /* FIXME: need to provide precise fault address */
38ba30ba 2142 return ret;
38ba30ba
GN		 2143
2144 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
bcc55cba 2145 &ctxt->exception);
db297e3d 2146 if (ret != X86EMUL_CONTINUE)
38ba30ba 2147 /* FIXME: need to provide precise fault address */
38ba30ba 2148 return ret;
38ba30ba
GN		 2149
2150 if (old_tss_sel != 0xffff) {
2151 tss_seg.prev_task_link = old_tss_sel;
2152
2153 ret = ops->write_std(new_tss_base,
2154 &tss_seg.prev_task_link,
2155 sizeof tss_seg.prev_task_link,
bcc55cba 2156 ctxt->vcpu, &ctxt->exception);
db297e3d 2157 if (ret != X86EMUL_CONTINUE)
38ba30ba 2158 /* FIXME: need to provide precise fault address */
38ba30ba 2159 return ret;
38ba30ba
GN		 2160 }
2161
2162 return load_state_from_tss16(ctxt, ops, &tss_seg);
2163}
2164
2165static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
2166 struct x86_emulate_ops *ops,
2167 struct tss_segment_32 *tss)
2168{
2169 struct decode_cache *c = &ctxt->decode;
2170
2171 tss->cr3 = ops->get_cr(3, ctxt->vcpu);
2172 tss->eip = c->eip;
2173 tss->eflags = ctxt->eflags;
2174 tss->eax = c->regs[VCPU_REGS_RAX];
2175 tss->ecx = c->regs[VCPU_REGS_RCX];
2176 tss->edx = c->regs[VCPU_REGS_RDX];
2177 tss->ebx = c->regs[VCPU_REGS_RBX];
2178 tss->esp = c->regs[VCPU_REGS_RSP];
2179 tss->ebp = c->regs[VCPU_REGS_RBP];
2180 tss->esi = c->regs[VCPU_REGS_RSI];
2181 tss->edi = c->regs[VCPU_REGS_RDI];
2182
2183 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
2184 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
2185 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
2186 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
2187 tss->fs = ops->get_segment_selector(VCPU_SREG_FS, ctxt->vcpu);
2188 tss->gs = ops->get_segment_selector(VCPU_SREG_GS, ctxt->vcpu);
2189 tss->ldt_selector = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
2190}
2191
2192static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
2193 struct x86_emulate_ops *ops,
2194 struct tss_segment_32 *tss)
2195{
2196 struct decode_cache *c = &ctxt->decode;
2197 int ret;
2198
35d3d4a1
AK		 2199 if (ops->set_cr(3, tss->cr3, ctxt->vcpu))
2200 return emulate_gp(ctxt, 0);
38ba30ba
GN		 2201 c->eip = tss->eip;
2202 ctxt->eflags = tss->eflags | 2;
2203 c->regs[VCPU_REGS_RAX] = tss->eax;
2204 c->regs[VCPU_REGS_RCX] = tss->ecx;
2205 c->regs[VCPU_REGS_RDX] = tss->edx;
2206 c->regs[VCPU_REGS_RBX] = tss->ebx;
2207 c->regs[VCPU_REGS_RSP] = tss->esp;
2208 c->regs[VCPU_REGS_RBP] = tss->ebp;
2209 c->regs[VCPU_REGS_RSI] = tss->esi;
2210 c->regs[VCPU_REGS_RDI] = tss->edi;
2211
2212 /*
2213 * SDM says that segment selectors are loaded before segment
2214 * descriptors
2215 */
2216 ops->set_segment_selector(tss->ldt_selector, VCPU_SREG_LDTR, ctxt->vcpu);
2217 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
2218 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
2219 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
2220 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
2221 ops->set_segment_selector(tss->fs, VCPU_SREG_FS, ctxt->vcpu);
2222 ops->set_segment_selector(tss->gs, VCPU_SREG_GS, ctxt->vcpu);
2223
2224 /*
2225 * Now load segment descriptors. If fault happenes at this stage
2226 * it is handled in a context of new task
2227 */
2228 ret = load_segment_descriptor(ctxt, ops, tss->ldt_selector, VCPU_SREG_LDTR);
2229 if (ret != X86EMUL_CONTINUE)
2230 return ret;
2231 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2232 if (ret != X86EMUL_CONTINUE)
2233 return ret;
2234 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2235 if (ret != X86EMUL_CONTINUE)
2236 return ret;
2237 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2238 if (ret != X86EMUL_CONTINUE)
2239 return ret;
2240 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2241 if (ret != X86EMUL_CONTINUE)
2242 return ret;
2243 ret = load_segment_descriptor(ctxt, ops, tss->fs, VCPU_SREG_FS);
2244 if (ret != X86EMUL_CONTINUE)
2245 return ret;
2246 ret = load_segment_descriptor(ctxt, ops, tss->gs, VCPU_SREG_GS);
2247 if (ret != X86EMUL_CONTINUE)
2248 return ret;
2249
2250 return X86EMUL_CONTINUE;
2251}
2252
2253static int task_switch_32(struct x86_emulate_ctxt *ctxt,
2254 struct x86_emulate_ops *ops,
2255 u16 tss_selector, u16 old_tss_sel,
2256 ulong old_tss_base, struct desc_struct *new_desc)
2257{
2258 struct tss_segment_32 tss_seg;
2259 int ret;
bcc55cba 2260 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba
GN		 2261
2262 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
bcc55cba 2263 &ctxt->exception);
db297e3d 2264 if (ret != X86EMUL_CONTINUE)
38ba30ba 2265 /* FIXME: need to provide precise fault address */
38ba30ba 2266 return ret;
38ba30ba
GN		 2267
2268 save_state_to_tss32(ctxt, ops, &tss_seg);
2269
2270 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
bcc55cba 2271 &ctxt->exception);
db297e3d 2272 if (ret != X86EMUL_CONTINUE)
38ba30ba 2273 /* FIXME: need to provide precise fault address */
38ba30ba 2274 return ret;
38ba30ba
GN		 2275
2276 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
bcc55cba 2277 &ctxt->exception);
db297e3d 2278 if (ret != X86EMUL_CONTINUE)
38ba30ba 2279 /* FIXME: need to provide precise fault address */
38ba30ba 2280 return ret;
38ba30ba
GN		 2281
2282 if (old_tss_sel != 0xffff) {
2283 tss_seg.prev_task_link = old_tss_sel;
2284
2285 ret = ops->write_std(new_tss_base,
2286 &tss_seg.prev_task_link,
2287 sizeof tss_seg.prev_task_link,
bcc55cba 2288 ctxt->vcpu, &ctxt->exception);
db297e3d 2289 if (ret != X86EMUL_CONTINUE)
38ba30ba 2290 /* FIXME: need to provide precise fault address */
38ba30ba 2291 return ret;
38ba30ba
GN		 2292 }
2293
2294 return load_state_from_tss32(ctxt, ops, &tss_seg);
2295}
2296
2297static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 2298 struct x86_emulate_ops *ops,
2299 u16 tss_selector, int reason,
2300 bool has_error_code, u32 error_code)
38ba30ba
GN		 2301{
2302 struct desc_struct curr_tss_desc, next_tss_desc;
2303 int ret;
2304 u16 old_tss_sel = ops->get_segment_selector(VCPU_SREG_TR, ctxt->vcpu);
2305 ulong old_tss_base =
5951c442 2306 ops->get_cached_segment_base(VCPU_SREG_TR, ctxt->vcpu);
ceffb459 2307 u32 desc_limit;
38ba30ba
GN		 2308
2309 /* FIXME: old_tss_base == ~0 ? */
2310
2311 ret = read_segment_descriptor(ctxt, ops, tss_selector, &next_tss_desc);
2312 if (ret != X86EMUL_CONTINUE)
2313 return ret;
2314 ret = read_segment_descriptor(ctxt, ops, old_tss_sel, &curr_tss_desc);
2315 if (ret != X86EMUL_CONTINUE)
2316 return ret;
2317
2318 /* FIXME: check that next_tss_desc is tss */
2319
2320 if (reason != TASK_SWITCH_IRET) {
2321 if ((tss_selector & 3) > next_tss_desc.dpl ||
35d3d4a1
AK		 2322 ops->cpl(ctxt->vcpu) > next_tss_desc.dpl)
2323 return emulate_gp(ctxt, 0);
38ba30ba
GN		 2324 }
2325
ceffb459
GN		 2326 desc_limit = desc_limit_scaled(&next_tss_desc);
2327 if (!next_tss_desc.p ||
2328 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2329 desc_limit < 0x2b)) {
54b8486f 2330 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2331 return X86EMUL_PROPAGATE_FAULT;
2332 }
2333
2334 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2335 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
2336 write_segment_descriptor(ctxt, ops, old_tss_sel,
2337 &curr_tss_desc);
2338 }
2339
2340 if (reason == TASK_SWITCH_IRET)
2341 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2342
2343 /* set back link to prev task only if NT bit is set in eflags
2344 note that old_tss_sel is not used afetr this point */
2345 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2346 old_tss_sel = 0xffff;
2347
2348 if (next_tss_desc.type & 8)
2349 ret = task_switch_32(ctxt, ops, tss_selector, old_tss_sel,
2350 old_tss_base, &next_tss_desc);
2351 else
2352 ret = task_switch_16(ctxt, ops, tss_selector, old_tss_sel,
2353 old_tss_base, &next_tss_desc);
0760d448
JK		 2354 if (ret != X86EMUL_CONTINUE)
2355 return ret;
38ba30ba
GN		 2356
2357 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2358 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2359
2360 if (reason != TASK_SWITCH_IRET) {
2361 next_tss_desc.type |= (1 << 1); /* set busy flag */
2362 write_segment_descriptor(ctxt, ops, tss_selector,
2363 &next_tss_desc);
2364 }
2365
2366 ops->set_cr(0, ops->get_cr(0, ctxt->vcpu) | X86_CR0_TS, ctxt->vcpu);
5601d05b 2367 ops->set_cached_descriptor(&next_tss_desc, 0, VCPU_SREG_TR, ctxt->vcpu);
38ba30ba
GN		 2368 ops->set_segment_selector(tss_selector, VCPU_SREG_TR, ctxt->vcpu);
2369
e269fb21
JK		 2370 if (has_error_code) {
2371 struct decode_cache *c = &ctxt->decode;
2372
2373 c->op_bytes = c->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2374 c->lock_prefix = 0;
2375 c->src.val = (unsigned long) error_code;
4487b3b4 2376 ret = em_push(ctxt);
e269fb21
JK		 2377 }
2378
38ba30ba
GN		 2379 return ret;
2380}
2381
2382int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 2383 u16 tss_selector, int reason,
2384 bool has_error_code, u32 error_code)
38ba30ba 2385{
9aabc88f 2386 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2387 struct decode_cache *c = &ctxt->decode;
2388 int rc;
2389
38ba30ba 2390 c->eip = ctxt->eip;
e269fb21 2391 c->dst.type = OP_NONE;
38ba30ba 2392
e269fb21
JK		 2393 rc = emulator_do_task_switch(ctxt, ops, tss_selector, reason,
2394 has_error_code, error_code);
38ba30ba 2395
4179bb02
TY		 2396 if (rc == X86EMUL_CONTINUE)
2397 ctxt->eip = c->eip;
38ba30ba 2398
a0c0ab2f 2399 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
38ba30ba
GN		 2400}
2401
90de84f5 2402static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned seg,
d9271123 2403 int reg, struct operand *op)
a682e354
GN		 2404{
2405 struct decode_cache *c = &ctxt->decode;
2406 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
2407
d9271123 2408 register_address_increment(c, &c->regs[reg], df * op->bytes);
90de84f5
AK		 2409 op->addr.mem.ea = register_address(c, c->regs[reg]);
2410 op->addr.mem.seg = seg;
a682e354
GN		 2411}
2412
7af04fc0
AK		 2413static int em_das(struct x86_emulate_ctxt *ctxt)
2414{
2415 struct decode_cache *c = &ctxt->decode;
2416 u8 al, old_al;
2417 bool af, cf, old_cf;
2418
2419 cf = ctxt->eflags & X86_EFLAGS_CF;
2420 al = c->dst.val;
2421
2422 old_al = al;
2423 old_cf = cf;
2424 cf = false;
2425 af = ctxt->eflags & X86_EFLAGS_AF;
2426 if ((al & 0x0f) > 9 || af) {
2427 al -= 6;
2428 cf = old_cf | (al >= 250);
2429 af = true;
2430 } else {
2431 af = false;
2432 }
2433 if (old_al > 0x99 || old_cf) {
2434 al -= 0x60;
2435 cf = true;
2436 }
2437
2438 c->dst.val = al;
2439 /* Set PF, ZF, SF */
2440 c->src.type = OP_IMM;
2441 c->src.val = 0;
2442 c->src.bytes = 1;
2443 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
2444 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2445 if (cf)
2446 ctxt->eflags |= X86_EFLAGS_CF;
2447 if (af)
2448 ctxt->eflags |= X86_EFLAGS_AF;
2449 return X86EMUL_CONTINUE;
2450}
2451
0ef753b8
AK		 2452static int em_call_far(struct x86_emulate_ctxt *ctxt)
2453{
2454 struct decode_cache *c = &ctxt->decode;
2455 u16 sel, old_cs;
2456 ulong old_eip;
2457 int rc;
2458
2459 old_cs = ctxt->ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
2460 old_eip = c->eip;
2461
2462 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
2463 if (load_segment_descriptor(ctxt, ctxt->ops, sel, VCPU_SREG_CS))
2464 return X86EMUL_CONTINUE;
2465
2466 c->eip = 0;
2467 memcpy(&c->eip, c->src.valptr, c->op_bytes);
2468
2469 c->src.val = old_cs;
4487b3b4 2470 rc = em_push(ctxt);
0ef753b8
AK		 2471 if (rc != X86EMUL_CONTINUE)
2472 return rc;
2473
2474 c->src.val = old_eip;
4487b3b4 2475 return em_push(ctxt);
0ef753b8
AK		 2476}
2477
40ece7c7
AK		 2478static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
2479{
2480 struct decode_cache *c = &ctxt->decode;
2481 int rc;
2482
2483 c->dst.type = OP_REG;
2484 c->dst.addr.reg = &c->eip;
2485 c->dst.bytes = c->op_bytes;
2486 rc = emulate_pop(ctxt, ctxt->ops, &c->dst.val, c->op_bytes);
2487 if (rc != X86EMUL_CONTINUE)
2488 return rc;
2489 register_address_increment(c, &c->regs[VCPU_REGS_RSP], c->src.val);
2490 return X86EMUL_CONTINUE;
2491}
2492
5c82aa29 2493static int em_imul(struct x86_emulate_ctxt *ctxt)
f3a1b9f4
AK		 2494{
2495 struct decode_cache *c = &ctxt->decode;
2496
f3a1b9f4
AK		 2497 emulate_2op_SrcV_nobyte("imul", c->src, c->dst, ctxt->eflags);
2498 return X86EMUL_CONTINUE;
2499}
2500
5c82aa29
AK		 2501static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
2502{
2503 struct decode_cache *c = &ctxt->decode;
2504
2505 c->dst.val = c->src2.val;
2506 return em_imul(ctxt);
2507}
2508
61429142
AK		 2509static int em_cwd(struct x86_emulate_ctxt *ctxt)
2510{
2511 struct decode_cache *c = &ctxt->decode;
2512
2513 c->dst.type = OP_REG;
2514 c->dst.bytes = c->src.bytes;
2515 c->dst.addr.reg = &c->regs[VCPU_REGS_RDX];
2516 c->dst.val = ~((c->src.val >> (c->src.bytes * 8 - 1)) - 1);
2517
2518 return X86EMUL_CONTINUE;
2519}
2520
48bb5d3c
AK		 2521static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
2522{
48bb5d3c
AK		 2523 struct decode_cache *c = &ctxt->decode;
2524 u64 tsc = 0;
2525
48bb5d3c
AK		 2526 ctxt->ops->get_msr(ctxt->vcpu, MSR_IA32_TSC, &tsc);
2527 c->regs[VCPU_REGS_RAX] = (u32)tsc;
2528 c->regs[VCPU_REGS_RDX] = tsc >> 32;
2529 return X86EMUL_CONTINUE;
2530}
2531
b9eac5f4
AK		 2532static int em_mov(struct x86_emulate_ctxt *ctxt)
2533{
2534 struct decode_cache *c = &ctxt->decode;
2535 c->dst.val = c->src.val;
2536 return X86EMUL_CONTINUE;
2537}
2538
aa97bb48
AK		 2539static int em_movdqu(struct x86_emulate_ctxt *ctxt)
2540{
2541 struct decode_cache *c = &ctxt->decode;
2542 memcpy(&c->dst.vec_val, &c->src.vec_val, c->op_bytes);
2543 return X86EMUL_CONTINUE;
2544}
2545
38503911
AK		 2546static int em_invlpg(struct x86_emulate_ctxt *ctxt)
2547{
2548 struct decode_cache *c = &ctxt->decode;
9fa088f4
AK		 2549 int rc;
2550 ulong linear;
2551
83b8795a 2552 rc = linearize(ctxt, c->src.addr.mem, 1, false, &linear);
9fa088f4
AK		 2553 if (rc == X86EMUL_CONTINUE)
2554 emulate_invlpg(ctxt->vcpu, linear);
38503911
AK		 2555 /* Disable writeback. */
2556 c->dst.type = OP_NONE;
2557 return X86EMUL_CONTINUE;
2558}
2559
cfec82cb
JR		 2560static bool valid_cr(int nr)
2561{
2562 switch (nr) {
2563 case 0:
2564 case 2 ... 4:
2565 case 8:
2566 return true;
2567 default:
2568 return false;
2569 }
2570}
2571
2572static int check_cr_read(struct x86_emulate_ctxt *ctxt)
2573{
2574 struct decode_cache *c = &ctxt->decode;
2575
2576 if (!valid_cr(c->modrm_reg))
2577 return emulate_ud(ctxt);
2578
2579 return X86EMUL_CONTINUE;
2580}
2581
2582static int check_cr_write(struct x86_emulate_ctxt *ctxt)
2583{
2584 struct decode_cache *c = &ctxt->decode;
2585 u64 new_val = c->src.val64;
2586 int cr = c->modrm_reg;
2587
2588 static u64 cr_reserved_bits[] = {
2589 0xffffffff00000000ULL,
2590 0, 0, 0, /* CR3 checked later */
2591 CR4_RESERVED_BITS,
2592 0, 0, 0,
2593 CR8_RESERVED_BITS,
2594 };
2595
2596 if (!valid_cr(cr))
2597 return emulate_ud(ctxt);
2598
2599 if (new_val & cr_reserved_bits[cr])
2600 return emulate_gp(ctxt, 0);
2601
2602 switch (cr) {
2603 case 0: {
2604 u64 cr4, efer;
2605 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
2606 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
2607 return emulate_gp(ctxt, 0);
2608
2609 cr4 = ctxt->ops->get_cr(4, ctxt->vcpu);
2610 ctxt->ops->get_msr(ctxt->vcpu, MSR_EFER, &efer);
2611
2612 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
2613 !(cr4 & X86_CR4_PAE))
2614 return emulate_gp(ctxt, 0);
2615
2616 break;
2617 }
2618 case 3: {
2619 u64 rsvd = 0;
2620
2621 if (is_long_mode(ctxt->vcpu))
2622 rsvd = CR3_L_MODE_RESERVED_BITS;
2623 else if (is_pae(ctxt->vcpu))
2624 rsvd = CR3_PAE_RESERVED_BITS;
2625 else if (is_paging(ctxt->vcpu))
2626 rsvd = CR3_NONPAE_RESERVED_BITS;
2627
2628 if (new_val & rsvd)
2629 return emulate_gp(ctxt, 0);
2630
2631 break;
2632 }
2633 case 4: {
2634 u64 cr4, efer;
2635
2636 cr4 = ctxt->ops->get_cr(4, ctxt->vcpu);
2637 ctxt->ops->get_msr(ctxt->vcpu, MSR_EFER, &efer);
2638
2639 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
2640 return emulate_gp(ctxt, 0);
2641
2642 break;
2643 }
2644 }
2645
2646 return X86EMUL_CONTINUE;
2647}
2648
3b88e41a
JR		 2649static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
2650{
2651 unsigned long dr7;
2652
2653 ctxt->ops->get_dr(7, &dr7, ctxt->vcpu);
2654
2655 /* Check if DR7.Global_Enable is set */
2656 return dr7 & (1 << 13);
2657}
2658
2659static int check_dr_read(struct x86_emulate_ctxt *ctxt)
2660{
2661 struct decode_cache *c = &ctxt->decode;
2662 int dr = c->modrm_reg;
2663 u64 cr4;
2664
2665 if (dr > 7)
2666 return emulate_ud(ctxt);
2667
2668 cr4 = ctxt->ops->get_cr(4, ctxt->vcpu);
2669 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
2670 return emulate_ud(ctxt);
2671
2672 if (check_dr7_gd(ctxt))
2673 return emulate_db(ctxt);
2674
2675 return X86EMUL_CONTINUE;
2676}
2677
2678static int check_dr_write(struct x86_emulate_ctxt *ctxt)
2679{
2680 struct decode_cache *c = &ctxt->decode;
2681 u64 new_val = c->src.val64;
2682 int dr = c->modrm_reg;
2683
2684 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
2685 return emulate_gp(ctxt, 0);
2686
2687 return check_dr_read(ctxt);
2688}
2689
01de8b09
JR		 2690static int check_svme(struct x86_emulate_ctxt *ctxt)
2691{
2692 u64 efer;
2693
2694 ctxt->ops->get_msr(ctxt->vcpu, MSR_EFER, &efer);
2695
2696 if (!(efer & EFER_SVME))
2697 return emulate_ud(ctxt);
2698
2699 return X86EMUL_CONTINUE;
2700}
2701
2702static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
2703{
2704 u64 rax = kvm_register_read(ctxt->vcpu, VCPU_REGS_RAX);
2705
2706 /* Valid physical address? */
2707 if (rax & 0xffff000000000000)
2708 return emulate_gp(ctxt, 0);
2709
2710 return check_svme(ctxt);
2711}
2712
d7eb8203
JR		 2713static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
2714{
2715 u64 cr4 = ctxt->ops->get_cr(4, ctxt->vcpu);
2716
2717 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt->vcpu))
2718 return emulate_ud(ctxt);
2719
2720 return X86EMUL_CONTINUE;
2721}
2722
8061252e
JR		 2723static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
2724{
2725 u64 cr4 = ctxt->ops->get_cr(4, ctxt->vcpu);
2726 u64 rcx = kvm_register_read(ctxt->vcpu, VCPU_REGS_RCX);
2727
2728 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt->vcpu)) ||
2729 (rcx > 3))
2730 return emulate_gp(ctxt, 0);
2731
2732 return X86EMUL_CONTINUE;
2733}
2734
f6511935
JR		 2735static int check_perm_in(struct x86_emulate_ctxt *ctxt)
2736{
2737 struct decode_cache *c = &ctxt->decode;
2738
2739 c->dst.bytes = min(c->dst.bytes, 4u);
2740 if (!emulator_io_permited(ctxt, ctxt->ops, c->src.val, c->dst.bytes))
2741 return emulate_gp(ctxt, 0);
2742
2743 return X86EMUL_CONTINUE;
2744}
2745
2746static int check_perm_out(struct x86_emulate_ctxt *ctxt)
2747{
2748 struct decode_cache *c = &ctxt->decode;
2749
2750 c->src.bytes = min(c->src.bytes, 4u);
2751 if (!emulator_io_permited(ctxt, ctxt->ops, c->dst.val, c->src.bytes))
2752 return emulate_gp(ctxt, 0);
2753
2754 return X86EMUL_CONTINUE;
2755}
2756
73fba5f4 2757#define D(_y) { .flags = (_y) }
c4f035c6 2758#define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i }
d09beabd
JR		 2759#define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \
2760 .check_perm = (_p) }
73fba5f4 2761#define N D(0)
01de8b09 2762#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
73fba5f4
AK		 2763#define G(_f, _g) { .flags = ((_f) | Group), .u.group = (_g) }
2764#define GD(_f, _g) { .flags = ((_f) | Group | GroupDual), .u.gdual = (_g) }
2765#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
c4f035c6
AK		 2766#define II(_f, _e, _i) \
2767 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd
JR		 2768#define IIP(_f, _e, _i, _p) \
2769 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \
2770 .check_perm = (_p) }
aa97bb48 2771#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 2772
8d8f4e9f 2773#define D2bv(_f) D((_f) | ByteOp), D(_f)
f6511935 2774#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
8d8f4e9f
AK		 2775#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
2776
6230f7fc
AK		 2777#define D6ALU(_f) D2bv((_f) | DstMem | SrcReg | ModRM), \
2778 D2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock), \
2779 D2bv(((_f) & ~Lock) | DstAcc | SrcImm)
2780
d7eb8203
JR		 2781static struct opcode group7_rm1[] = {
2782 DI(SrcNone | ModRM | Priv, monitor),
2783 DI(SrcNone | ModRM | Priv, mwait),
2784 N, N, N, N, N, N,
2785};
2786
01de8b09
JR		 2787static struct opcode group7_rm3[] = {
2788 DIP(SrcNone | ModRM | Prot | Priv, vmrun, check_svme_pa),
bfeed29d 2789 DI(SrcNone | ModRM | Prot | VendorSpecific, vmmcall),
01de8b09
JR		 2790 DIP(SrcNone | ModRM | Prot | Priv, vmload, check_svme_pa),
2791 DIP(SrcNone | ModRM | Prot | Priv, vmsave, check_svme_pa),
2792 DIP(SrcNone | ModRM | Prot | Priv, stgi, check_svme),
2793 DIP(SrcNone | ModRM | Prot | Priv, clgi, check_svme),
2794 DIP(SrcNone | ModRM | Prot | Priv, skinit, check_svme),
2795 DIP(SrcNone | ModRM | Prot | Priv, invlpga, check_svme),
2796};
6230f7fc 2797
d7eb8203
JR		 2798static struct opcode group7_rm7[] = {
2799 N,
2800 DIP(SrcNone | ModRM, rdtscp, check_rdtsc),
2801 N, N, N, N, N, N,
2802};
73fba5f4
AK		 2803static struct opcode group1[] = {
2804 X7(D(Lock)), N
2805};
2806
2807static struct opcode group1A[] = {
2808 D(DstMem | SrcNone | ModRM | Mov | Stack), N, N, N, N, N, N, N,
2809};
2810
2811static struct opcode group3[] = {
2812 D(DstMem | SrcImm | ModRM), D(DstMem | SrcImm | ModRM),
2813 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
3f9f53b0 2814 X4(D(SrcMem | ModRM)),
73fba5f4
AK		 2815};
2816
2817static struct opcode group4[] = {
2818 D(ByteOp | DstMem | SrcNone | ModRM | Lock), D(ByteOp | DstMem | SrcNone | ModRM | Lock),
2819 N, N, N, N, N, N,
2820};
2821
2822static struct opcode group5[] = {
2823 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
0ef753b8
AK		 2824 D(SrcMem | ModRM | Stack),
2825 I(SrcMemFAddr | ModRM | ImplicitOps | Stack, em_call_far),
73fba5f4
AK		 2826 D(SrcMem | ModRM | Stack), D(SrcMemFAddr | ModRM | ImplicitOps),
2827 D(SrcMem | ModRM | Stack), N,
2828};
2829
dee6bb70
JR		 2830static struct opcode group6[] = {
2831 DI(ModRM | Prot, sldt),
2832 DI(ModRM | Prot, str),
2833 DI(ModRM | Prot | Priv, lldt),
2834 DI(ModRM | Prot | Priv, ltr),
2835 N, N, N, N,
2836};
2837
73fba5f4 2838static struct group_dual group7 = { {
dee6bb70
JR		 2839 DI(ModRM | Mov | DstMem | Priv, sgdt),
2840 DI(ModRM | Mov | DstMem | Priv, sidt),
2841 DI(ModRM | SrcMem | Priv, lgdt), DI(ModRM | SrcMem | Priv, lidt),
3c6e276f
AK		 2842 DI(SrcNone | ModRM | DstMem | Mov, smsw), N,
2843 DI(SrcMem16 | ModRM | Mov | Priv, lmsw),
2844 DI(SrcMem | ModRM | ByteOp | Priv | NoAccess, invlpg),
73fba5f4 2845}, {
d7eb8203 2846 D(SrcNone | ModRM | Priv | VendorSpecific), EXT(0, group7_rm1),
01de8b09 2847 N, EXT(0, group7_rm3),
3c6e276f 2848 DI(SrcNone | ModRM | DstMem | Mov, smsw), N,
d7eb8203 2849 DI(SrcMem16 | ModRM | Mov | Priv, lmsw), EXT(0, group7_rm7),
73fba5f4
AK		 2850} };
2851
2852static struct opcode group8[] = {
2853 N, N, N, N,
2854 D(DstMem | SrcImmByte | ModRM), D(DstMem | SrcImmByte | ModRM | Lock),
2855 D(DstMem | SrcImmByte | ModRM | Lock), D(DstMem | SrcImmByte | ModRM | Lock),
2856};
2857
2858static struct group_dual group9 = { {
2859 N, D(DstMem64 | ModRM | Lock), N, N, N, N, N, N,
2860}, {
2861 N, N, N, N, N, N, N, N,
2862} };
2863
a4d4a7c1
AK		 2864static struct opcode group11[] = {
2865 I(DstMem | SrcImm | ModRM | Mov, em_mov), X7(D(Undefined)),
2866};
2867
aa97bb48
AK		 2868static struct gprefix pfx_0f_6f_0f_7f = {
2869 N, N, N, I(Sse, em_movdqu),
2870};
2871
73fba5f4
AK		 2872static struct opcode opcode_table[256] = {
2873 /* 0x00 - 0x07 */
6230f7fc 2874 D6ALU(Lock),
73fba5f4
AK		 2875 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2876 /* 0x08 - 0x0F */
6230f7fc 2877 D6ALU(Lock),
73fba5f4
AK		 2878 D(ImplicitOps | Stack | No64), N,
2879 /* 0x10 - 0x17 */
6230f7fc 2880 D6ALU(Lock),
73fba5f4
AK		 2881 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2882 /* 0x18 - 0x1F */
6230f7fc 2883 D6ALU(Lock),
73fba5f4
AK		 2884 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2885 /* 0x20 - 0x27 */
6230f7fc 2886 D6ALU(Lock), N, N,
73fba5f4 2887 /* 0x28 - 0x2F */
6230f7fc 2888 D6ALU(Lock), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 2889 /* 0x30 - 0x37 */
6230f7fc 2890 D6ALU(Lock), N, N,
73fba5f4 2891 /* 0x38 - 0x3F */
6230f7fc 2892 D6ALU(0), N, N,
73fba5f4
AK		 2893 /* 0x40 - 0x4F */
2894 X16(D(DstReg)),
2895 /* 0x50 - 0x57 */
63540382 2896 X8(I(SrcReg | Stack, em_push)),
73fba5f4
AK		 2897 /* 0x58 - 0x5F */
2898 X8(D(DstReg | Stack)),
2899 /* 0x60 - 0x67 */
2900 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2901 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
2902 N, N, N, N,
2903 /* 0x68 - 0x6F */
d46164db
AK		 2904 I(SrcImm | Mov | Stack, em_push),
2905 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 2906 I(SrcImmByte | Mov | Stack, em_push),
2907 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
f6511935
JR		 2908 D2bvIP(DstDI | Mov | String, ins, check_perm_in), /* insb, insw/insd */
2909 D2bvIP(SrcSI | ImplicitOps | String, outs, check_perm_out), /* outsb, outsw/outsd */
73fba5f4
AK		 2910 /* 0x70 - 0x7F */
2911 X16(D(SrcImmByte)),
2912 /* 0x80 - 0x87 */
2913 G(ByteOp | DstMem | SrcImm | ModRM | Group, group1),
2914 G(DstMem | SrcImm | ModRM | Group, group1),
2915 G(ByteOp | DstMem | SrcImm | ModRM | No64 | Group, group1),
2916 G(DstMem | SrcImmByte | ModRM | Group, group1),
76e8e68d 2917 D2bv(DstMem | SrcReg | ModRM), D2bv(DstMem | SrcReg | ModRM | Lock),
73fba5f4 2918 /* 0x88 - 0x8F */
b9eac5f4
AK		 2919 I2bv(DstMem | SrcReg | ModRM | Mov, em_mov),
2920 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
342fc630 2921 D(DstMem | SrcNone | ModRM | Mov), D(ModRM | SrcMem | NoAccess | DstReg),
73fba5f4
AK		 2922 D(ImplicitOps | SrcMem16 | ModRM), G(0, group1A),
2923 /* 0x90 - 0x97 */
bf608f88 2924 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
73fba5f4 2925 /* 0x98 - 0x9F */
61429142 2926 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 2927 I(SrcImmFAddr | No64, em_call_far), N,
3c6e276f 2928 DI(ImplicitOps | Stack, pushf), DI(ImplicitOps | Stack, popf), N, N,
73fba5f4 2929 /* 0xA0 - 0xA7 */
b9eac5f4
AK		 2930 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
2931 I2bv(DstMem | SrcAcc | Mov | MemAbs, em_mov),
2932 I2bv(SrcSI | DstDI | Mov | String, em_mov),
2933 D2bv(SrcSI | DstDI | String),
73fba5f4 2934 /* 0xA8 - 0xAF */
50748613 2935 D2bv(DstAcc | SrcImm),
b9eac5f4
AK		 2936 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
2937 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
48fe67b5 2938 D2bv(SrcAcc | DstDI | String),
73fba5f4 2939 /* 0xB0 - 0xB7 */
b9eac5f4 2940 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 2941 /* 0xB8 - 0xBF */
b9eac5f4 2942 X8(I(DstReg | SrcImm | Mov, em_mov)),
73fba5f4 2943 /* 0xC0 - 0xC7 */
d2c6c7ad 2944 D2bv(DstMem | SrcImmByte | ModRM),
40ece7c7
AK		 2945 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
2946 D(ImplicitOps | Stack),
09b5f4d3 2947 D(DstReg | SrcMemFAddr | ModRM | No64), D(DstReg | SrcMemFAddr | ModRM | No64),
a4d4a7c1 2948 G(ByteOp, group11), G(0, group11),
73fba5f4
AK		 2949 /* 0xC8 - 0xCF */
2950 N, N, N, D(ImplicitOps | Stack),
3c6e276f
AK		 2951 D(ImplicitOps), DI(SrcImmByte, intn),
2952 D(ImplicitOps | No64), DI(ImplicitOps, iret),
73fba5f4 2953 /* 0xD0 - 0xD7 */
d2c6c7ad 2954 D2bv(DstMem | SrcOne | ModRM), D2bv(DstMem | ModRM),
73fba5f4
AK		 2955 N, N, N, N,
2956 /* 0xD8 - 0xDF */
2957 N, N, N, N, N, N, N, N,
2958 /* 0xE0 - 0xE7 */
e4abac67 2959 X4(D(SrcImmByte)),
f6511935
JR		 2960 D2bvIP(SrcImmUByte | DstAcc, in, check_perm_in),
2961 D2bvIP(SrcAcc | DstImmUByte, out, check_perm_out),
73fba5f4
AK		 2962 /* 0xE8 - 0xEF */
2963 D(SrcImm | Stack), D(SrcImm | ImplicitOps),
2964 D(SrcImmFAddr | No64), D(SrcImmByte | ImplicitOps),
f6511935
JR		 2965 D2bvIP(SrcNone | DstAcc, in, check_perm_in),
2966 D2bvIP(SrcAcc | ImplicitOps, out, check_perm_out),
73fba5f4 2967 /* 0xF0 - 0xF7 */
bf608f88 2968 N, DI(ImplicitOps, icebp), N, N,
3c6e276f
AK		 2969 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
2970 G(ByteOp, group3), G(0, group3),
73fba5f4 2971 /* 0xF8 - 0xFF */
8744aa9a 2972 D(ImplicitOps), D(ImplicitOps), D(ImplicitOps), D(ImplicitOps),
73fba5f4
AK		 2973 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
2974};
2975
2976static struct opcode twobyte_table[256] = {
2977 /* 0x00 - 0x0F */
dee6bb70 2978 G(0, group6), GD(0, &group7), N, N,
cfec82cb 2979 N, D(ImplicitOps | VendorSpecific), DI(ImplicitOps | Priv, clts), N,
3c6e276f 2980 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
73fba5f4
AK		 2981 N, D(ImplicitOps | ModRM), N, N,
2982 /* 0x10 - 0x1F */
2983 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
2984 /* 0x20 - 0x2F */
cfec82cb 2985 DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read),
3b88e41a 2986 DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read),
cfec82cb 2987 DIP(ModRM | SrcMem | Priv | Op3264, cr_write, check_cr_write),
3b88e41a 2988 DIP(ModRM | SrcMem | Priv | Op3264, dr_write, check_dr_write),
73fba5f4
AK		 2989 N, N, N, N,
2990 N, N, N, N, N, N, N, N,
2991 /* 0x30 - 0x3F */
8061252e
JR		 2992 DI(ImplicitOps | Priv, wrmsr),
2993 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
2994 DI(ImplicitOps | Priv, rdmsr),
2995 DIP(ImplicitOps | Priv, rdpmc, check_rdpmc),
d867162c
AK		 2996 D(ImplicitOps | VendorSpecific), D(ImplicitOps | Priv | VendorSpecific),
2997 N, N,
73fba5f4
AK		 2998 N, N, N, N, N, N, N, N,
2999 /* 0x40 - 0x4F */
3000 X16(D(DstReg | SrcMem | ModRM | Mov)),
3001 /* 0x50 - 0x5F */
3002 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3003 /* 0x60 - 0x6F */
aa97bb48
AK		 3004 N, N, N, N,
3005 N, N, N, N,
3006 N, N, N, N,
3007 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 3008 /* 0x70 - 0x7F */
aa97bb48
AK		 3009 N, N, N, N,
3010 N, N, N, N,
3011 N, N, N, N,
3012 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4
AK		 3013 /* 0x80 - 0x8F */
3014 X16(D(SrcImm)),
3015 /* 0x90 - 0x9F */
ee45b58e 3016 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4
AK		 3017 /* 0xA0 - 0xA7 */
3018 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
8061252e 3019 DI(ImplicitOps, cpuid), D(DstMem | SrcReg | ModRM | BitOp),
73fba5f4
AK		 3020 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3021 D(DstMem | SrcReg | Src2CL | ModRM), N, N,
3022 /* 0xA8 - 0xAF */
3023 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
8061252e 3024 DI(ImplicitOps, rsm), D(DstMem | SrcReg | ModRM | BitOp | Lock),
73fba5f4
AK		 3025 D(DstMem | SrcReg | Src2ImmByte | ModRM),
3026 D(DstMem | SrcReg | Src2CL | ModRM),
5c82aa29 3027 D(ModRM), I(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 3028 /* 0xB0 - 0xB7 */
739ae406 3029 D2bv(DstMem | SrcReg | ModRM | Lock),
09b5f4d3
WY		 3030 D(DstReg | SrcMemFAddr | ModRM), D(DstMem | SrcReg | ModRM | BitOp | Lock),
3031 D(DstReg | SrcMemFAddr | ModRM), D(DstReg | SrcMemFAddr | ModRM),
3032 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 3033 /* 0xB8 - 0xBF */
3034 N, N,
ba7ff2b7 3035 G(BitOp, group8), D(DstMem | SrcReg | ModRM | BitOp | Lock),
d9574a25
WY		 3036 D(DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
3037 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4 3038 /* 0xC0 - 0xCF */
739ae406 3039 D2bv(DstMem | SrcReg | ModRM | Lock),
92f738a5 3040 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4
AK		 3041 N, N, N, GD(0, &group9),
3042 N, N, N, N, N, N, N, N,
3043 /* 0xD0 - 0xDF */
3044 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3045 /* 0xE0 - 0xEF */
3046 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
3047 /* 0xF0 - 0xFF */
3048 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
3049};
3050
3051#undef D
3052#undef N
3053#undef G
3054#undef GD
3055#undef I
aa97bb48 3056#undef GP
01de8b09 3057#undef EXT
73fba5f4 3058
8d8f4e9f 3059#undef D2bv
f6511935 3060#undef D2bvIP
8d8f4e9f 3061#undef I2bv
6230f7fc 3062#undef D6ALU
8d8f4e9f 3063
39f21ee5
AK		 3064static unsigned imm_size(struct decode_cache *c)
3065{
3066 unsigned size;
3067
3068 size = (c->d & ByteOp) ? 1 : c->op_bytes;
3069 if (size == 8)
3070 size = 4;
3071 return size;
3072}
3073
3074static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
3075 unsigned size, bool sign_extension)
3076{
3077 struct decode_cache *c = &ctxt->decode;
3078 struct x86_emulate_ops *ops = ctxt->ops;
3079 int rc = X86EMUL_CONTINUE;
3080
3081 op->type = OP_IMM;
3082 op->bytes = size;
90de84f5 3083 op->addr.mem.ea = c->eip;
39f21ee5
AK		 3084 /* NB. Immediates are sign-extended as necessary. */
3085 switch (op->bytes) {
3086 case 1:
3087 op->val = insn_fetch(s8, 1, c->eip);
3088 break;
3089 case 2:
3090 op->val = insn_fetch(s16, 2, c->eip);
3091 break;
3092 case 4:
3093 op->val = insn_fetch(s32, 4, c->eip);
3094 break;
3095 }
3096 if (!sign_extension) {
3097 switch (op->bytes) {
3098 case 1:
3099 op->val &= 0xff;
3100 break;
3101 case 2:
3102 op->val &= 0xffff;
3103 break;
3104 case 4:
3105 op->val &= 0xffffffff;
3106 break;
3107 }
3108 }
3109done:
3110 return rc;
3111}
3112
dde7e6d1 3113int
dc25e89e 3114x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1
AK		 3115{
3116 struct x86_emulate_ops *ops = ctxt->ops;
3117 struct decode_cache *c = &ctxt->decode;
3118 int rc = X86EMUL_CONTINUE;
3119 int mode = ctxt->mode;
0d7cdee8
AK		 3120 int def_op_bytes, def_ad_bytes, dual, goffset, simd_prefix;
3121 bool op_prefix = false;
dde7e6d1 3122 struct opcode opcode, *g_mod012, *g_mod3;
2dbd0dd7 3123 struct operand memop = { .type = OP_NONE };
dde7e6d1 3124
dde7e6d1 3125 c->eip = ctxt->eip;
dc25e89e
AP		 3126 c->fetch.start = c->eip;
3127 c->fetch.end = c->fetch.start + insn_len;
3128 if (insn_len > 0)
3129 memcpy(c->fetch.data, insn, insn_len);
dde7e6d1
AK		 3130 ctxt->cs_base = seg_base(ctxt, ops, VCPU_SREG_CS);
3131
3132 switch (mode) {
3133 case X86EMUL_MODE_REAL:
3134 case X86EMUL_MODE_VM86:
3135 case X86EMUL_MODE_PROT16:
3136 def_op_bytes = def_ad_bytes = 2;
3137 break;
3138 case X86EMUL_MODE_PROT32:
3139 def_op_bytes = def_ad_bytes = 4;
3140 break;
3141#ifdef CONFIG_X86_64
3142 case X86EMUL_MODE_PROT64:
3143 def_op_bytes = 4;
3144 def_ad_bytes = 8;
3145 break;
3146#endif
3147 default:
3148 return -1;
3149 }
3150
3151 c->op_bytes = def_op_bytes;
3152 c->ad_bytes = def_ad_bytes;
3153
3154 /* Legacy prefixes. */
3155 for (;;) {
3156 switch (c->b = insn_fetch(u8, 1, c->eip)) {
3157 case 0x66: /* operand-size override */
0d7cdee8 3158 op_prefix = true;
dde7e6d1
AK		 3159 /* switch between 2/4 bytes */
3160 c->op_bytes = def_op_bytes ^ 6;
3161 break;
3162 case 0x67: /* address-size override */
3163 if (mode == X86EMUL_MODE_PROT64)
3164 /* switch between 4/8 bytes */
3165 c->ad_bytes = def_ad_bytes ^ 12;
3166 else
3167 /* switch between 2/4 bytes */
3168 c->ad_bytes = def_ad_bytes ^ 6;
3169 break;
3170 case 0x26: /* ES override */
3171 case 0x2e: /* CS override */
3172 case 0x36: /* SS override */
3173 case 0x3e: /* DS override */
3174 set_seg_override(c, (c->b >> 3) & 3);
3175 break;
3176 case 0x64: /* FS override */
3177 case 0x65: /* GS override */
3178 set_seg_override(c, c->b & 7);
3179 break;
3180 case 0x40 ... 0x4f: /* REX */
3181 if (mode != X86EMUL_MODE_PROT64)
3182 goto done_prefixes;
3183 c->rex_prefix = c->b;
3184 continue;
3185 case 0xf0: /* LOCK */
3186 c->lock_prefix = 1;
3187 break;
3188 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 3189 case 0xf3: /* REP/REPE/REPZ */
1d6b114f 3190 c->rep_prefix = c->b;
dde7e6d1
AK		 3191 break;
3192 default:
3193 goto done_prefixes;
3194 }
3195
3196 /* Any legacy prefix after a REX prefix nullifies its effect. */
3197
3198 c->rex_prefix = 0;
3199 }
3200
3201done_prefixes:
3202
3203 /* REX prefix. */
1e87e3ef
AK		 3204 if (c->rex_prefix & 8)
3205 c->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 3206
3207 /* Opcode byte(s). */
3208 opcode = opcode_table[c->b];
d3ad6243
WY		 3209 /* Two-byte opcode? */
3210 if (c->b == 0x0f) {
3211 c->twobyte = 1;
3212 c->b = insn_fetch(u8, 1, c->eip);
3213 opcode = twobyte_table[c->b];
dde7e6d1
AK		 3214 }
3215 c->d = opcode.flags;
3216
3217 if (c->d & Group) {
3218 dual = c->d & GroupDual;
3219 c->modrm = insn_fetch(u8, 1, c->eip);
3220 --c->eip;
3221
3222 if (c->d & GroupDual) {
3223 g_mod012 = opcode.u.gdual->mod012;
3224 g_mod3 = opcode.u.gdual->mod3;
3225 } else
3226 g_mod012 = g_mod3 = opcode.u.group;
3227
3228 c->d &= ~(Group | GroupDual);
3229
3230 goffset = (c->modrm >> 3) & 7;
3231
3232 if ((c->modrm >> 6) == 3)
3233 opcode = g_mod3[goffset];
3234 else
3235 opcode = g_mod012[goffset];
01de8b09
JR		 3236
3237 if (opcode.flags & RMExt) {
3238 goffset = c->modrm & 7;
3239 opcode = opcode.u.group[goffset];
3240 }
3241
dde7e6d1
AK		 3242 c->d |= opcode.flags;
3243 }
3244
0d7cdee8
AK		 3245 if (c->d & Prefix) {
3246 if (c->rep_prefix && op_prefix)
3247 return X86EMUL_UNHANDLEABLE;
3248 simd_prefix = op_prefix ? 0x66 : c->rep_prefix;
3249 switch (simd_prefix) {
3250 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
3251 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
3252 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
3253 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
3254 }
3255 c->d |= opcode.flags;
3256 }
3257
dde7e6d1 3258 c->execute = opcode.u.execute;
d09beabd 3259 c->check_perm = opcode.check_perm;
c4f035c6 3260 c->intercept = opcode.intercept;
dde7e6d1
AK		 3261
3262 /* Unrecognised? */
d53db5ef 3263 if (c->d == 0 || (c->d & Undefined))
dde7e6d1 3264 return -1;
dde7e6d1 3265
d867162c
AK		 3266 if (!(c->d & VendorSpecific) && ctxt->only_vendor_specific_insn)
3267 return -1;
3268
dde7e6d1
AK		 3269 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
3270 c->op_bytes = 8;
3271
7f9b4b75
AK		 3272 if (c->d & Op3264) {
3273 if (mode == X86EMUL_MODE_PROT64)
3274 c->op_bytes = 8;
3275 else
3276 c->op_bytes = 4;
3277 }
3278
1253791d
AK		 3279 if (c->d & Sse)
3280 c->op_bytes = 16;
3281
dde7e6d1 3282 /* ModRM and SIB bytes. */
09ee57cd 3283 if (c->d & ModRM) {
2dbd0dd7 3284 rc = decode_modrm(ctxt, ops, &memop);
09ee57cd
AK		 3285 if (!c->has_seg_override)
3286 set_seg_override(c, c->modrm_seg);
3287 } else if (c->d & MemAbs)
2dbd0dd7 3288 rc = decode_abs(ctxt, ops, &memop);
dde7e6d1
AK		 3289 if (rc != X86EMUL_CONTINUE)
3290 goto done;
3291
3292 if (!c->has_seg_override)
3293 set_seg_override(c, VCPU_SREG_DS);
3294
90de84f5 3295 memop.addr.mem.seg = seg_override(ctxt, ops, c);
dde7e6d1 3296
2dbd0dd7 3297 if (memop.type == OP_MEM && c->ad_bytes != 8)
90de84f5 3298 memop.addr.mem.ea = (u32)memop.addr.mem.ea;
dde7e6d1 3299
2dbd0dd7 3300 if (memop.type == OP_MEM && c->rip_relative)
90de84f5 3301 memop.addr.mem.ea += c->eip;
dde7e6d1
AK		 3302
3303 /*
3304 * Decode and fetch the source operand: register, memory
3305 * or immediate.
3306 */
3307 switch (c->d & SrcMask) {
3308 case SrcNone:
3309 break;
3310 case SrcReg:
1253791d 3311 decode_register_operand(ctxt, &c->src, c, 0);
dde7e6d1
AK		 3312 break;
3313 case SrcMem16:
2dbd0dd7 3314 memop.bytes = 2;
dde7e6d1
AK		 3315 goto srcmem_common;
3316 case SrcMem32:
2dbd0dd7 3317 memop.bytes = 4;
dde7e6d1
AK		 3318 goto srcmem_common;
3319 case SrcMem:
2dbd0dd7 3320 memop.bytes = (c->d & ByteOp) ? 1 :
dde7e6d1 3321 c->op_bytes;
dde7e6d1 3322 srcmem_common:
2dbd0dd7 3323 c->src = memop;
dde7e6d1 3324 break;
b250e605 3325 case SrcImmU16:
39f21ee5
AK		 3326 rc = decode_imm(ctxt, &c->src, 2, false);
3327 break;
dde7e6d1 3328 case SrcImm:
39f21ee5
AK		 3329 rc = decode_imm(ctxt, &c->src, imm_size(c), true);
3330 break;
dde7e6d1 3331 case SrcImmU:
39f21ee5 3332 rc = decode_imm(ctxt, &c->src, imm_size(c), false);
dde7e6d1
AK		 3333 break;
3334 case SrcImmByte:
39f21ee5
AK		 3335 rc = decode_imm(ctxt, &c->src, 1, true);
3336 break;
dde7e6d1 3337 case SrcImmUByte:
39f21ee5 3338 rc = decode_imm(ctxt, &c->src, 1, false);
dde7e6d1
AK		 3339 break;
3340 case SrcAcc:
3341 c->src.type = OP_REG;
3342 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1a6440ae 3343 c->src.addr.reg = &c->regs[VCPU_REGS_RAX];
91ff3cb4 3344 fetch_register_operand(&c->src);
dde7e6d1
AK		 3345 break;
3346 case SrcOne:
3347 c->src.bytes = 1;
3348 c->src.val = 1;
3349 break;
3350 case SrcSI:
3351 c->src.type = OP_MEM;
3352 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
90de84f5
AK		 3353 c->src.addr.mem.ea =
3354 register_address(c, c->regs[VCPU_REGS_RSI]);
3355 c->src.addr.mem.seg = seg_override(ctxt, ops, c),
dde7e6d1
AK		 3356 c->src.val = 0;
3357 break;
3358 case SrcImmFAddr:
3359 c->src.type = OP_IMM;
90de84f5 3360 c->src.addr.mem.ea = c->eip;
dde7e6d1
AK		 3361 c->src.bytes = c->op_bytes + 2;
3362 insn_fetch_arr(c->src.valptr, c->src.bytes, c->eip);
3363 break;
3364 case SrcMemFAddr:
2dbd0dd7
AK		 3365 memop.bytes = c->op_bytes + 2;
3366 goto srcmem_common;
dde7e6d1
AK		 3367 break;
3368 }
3369
39f21ee5
AK		 3370 if (rc != X86EMUL_CONTINUE)
3371 goto done;
3372
dde7e6d1
AK		 3373 /*
3374 * Decode and fetch the second source operand: register, memory
3375 * or immediate.
3376 */
3377 switch (c->d & Src2Mask) {
3378 case Src2None:
3379 break;
3380 case Src2CL:
3381 c->src2.bytes = 1;
3382 c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
3383 break;
3384 case Src2ImmByte:
39f21ee5 3385 rc = decode_imm(ctxt, &c->src2, 1, true);
dde7e6d1
AK		 3386 break;
3387 case Src2One:
3388 c->src2.bytes = 1;
3389 c->src2.val = 1;
3390 break;
7db41eb7
AK		 3391 case Src2Imm:
3392 rc = decode_imm(ctxt, &c->src2, imm_size(c), true);
3393 break;
dde7e6d1
AK		 3394 }
3395
39f21ee5
AK		 3396 if (rc != X86EMUL_CONTINUE)
3397 goto done;
3398
dde7e6d1
AK		 3399 /* Decode and fetch the destination operand: register or memory. */
3400 switch (c->d & DstMask) {
dde7e6d1 3401 case DstReg:
1253791d 3402 decode_register_operand(ctxt, &c->dst, c,
dde7e6d1
AK		 3403 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
3404 break;
943858e2
WY		 3405 case DstImmUByte:
3406 c->dst.type = OP_IMM;
90de84f5 3407 c->dst.addr.mem.ea = c->eip;
943858e2
WY		 3408 c->dst.bytes = 1;
3409 c->dst.val = insn_fetch(u8, 1, c->eip);
3410 break;
dde7e6d1
AK		 3411 case DstMem:
3412 case DstMem64:
2dbd0dd7 3413 c->dst = memop;
dde7e6d1
AK		 3414 if ((c->d & DstMask) == DstMem64)
3415 c->dst.bytes = 8;
3416 else
3417 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
35c843c4
WY		 3418 if (c->d & BitOp)
3419 fetch_bit_operand(c);
2dbd0dd7 3420 c->dst.orig_val = c->dst.val;
dde7e6d1
AK		 3421 break;
3422 case DstAcc:
3423 c->dst.type = OP_REG;
3424 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1a6440ae 3425 c->dst.addr.reg = &c->regs[VCPU_REGS_RAX];
91ff3cb4 3426 fetch_register_operand(&c->dst);
dde7e6d1
AK		 3427 c->dst.orig_val = c->dst.val;
3428 break;
3429 case DstDI:
3430 c->dst.type = OP_MEM;
3431 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
90de84f5
AK		 3432 c->dst.addr.mem.ea =
3433 register_address(c, c->regs[VCPU_REGS_RDI]);
3434 c->dst.addr.mem.seg = VCPU_SREG_ES;
dde7e6d1
AK		 3435 c->dst.val = 0;
3436 break;
36089fed
WY		 3437 case ImplicitOps:
3438 /* Special instructions do their own operand decoding. */
3439 default:
3440 c->dst.type = OP_NONE; /* Disable writeback. */
3441 return 0;
dde7e6d1
AK		 3442 }
3443
3444done:
a0c0ab2f 3445 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
dde7e6d1
AK		 3446}
3447
3e2f65d5
GN		 3448static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
3449{
3450 struct decode_cache *c = &ctxt->decode;
3451
3452 /* The second termination condition only applies for REPE
3453 * and REPNE. Test if the repeat string operation prefix is
3454 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
3455 * corresponding termination condition according to:
3456 * - if REPE/REPZ and ZF = 0 then done
3457 * - if REPNE/REPNZ and ZF = 1 then done
3458 */
3459 if (((c->b == 0xa6) || (c->b == 0xa7) ||
3460 (c->b == 0xae) || (c->b == 0xaf))
3461 && (((c->rep_prefix == REPE_PREFIX) &&
3462 ((ctxt->eflags & EFLG_ZF) == 0))
3463 || ((c->rep_prefix == REPNE_PREFIX) &&
3464 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
3465 return true;
3466
3467 return false;
3468}
3469
8b4caf66 3470int
9aabc88f 3471x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 3472{
9aabc88f 3473 struct x86_emulate_ops *ops = ctxt->ops;
8b4caf66 3474 u64 msr_data;
8b4caf66 3475 struct decode_cache *c = &ctxt->decode;
1b30eaa8 3476 int rc = X86EMUL_CONTINUE;
5cd21917 3477 int saved_dst_type = c->dst.type;
6e154e56 3478 int irq; /* Used for int 3, int, and into */
8b4caf66 3479
9de41573 3480 ctxt->decode.mem_read.pos = 0;
310b5d30 3481
1161624f 3482 if (ctxt->mode == X86EMUL_MODE_PROT64 && (c->d & No64)) {
35d3d4a1 3483 rc = emulate_ud(ctxt);
1161624f
GN		 3484 goto done;
3485 }
3486
d380a5e4 3487 /* LOCK prefix is allowed only with some instructions */
a41ffb75 3488 if (c->lock_prefix && (!(c->d & Lock) || c->dst.type != OP_MEM)) {
35d3d4a1 3489 rc = emulate_ud(ctxt);
d380a5e4
GN		 3490 goto done;
3491 }
3492
081bca0e 3493 if ((c->d & SrcMask) == SrcMemFAddr && c->src.type != OP_MEM) {
35d3d4a1 3494 rc = emulate_ud(ctxt);
081bca0e
AK		 3495 goto done;
3496 }
3497
1253791d
AK		 3498 if ((c->d & Sse)
3499 && ((ops->get_cr(0, ctxt->vcpu) & X86_CR0_EM)
3500 || !(ops->get_cr(4, ctxt->vcpu) & X86_CR4_OSFXSR))) {
3501 rc = emulate_ud(ctxt);
3502 goto done;
3503 }
3504
3505 if ((c->d & Sse) && (ops->get_cr(0, ctxt->vcpu) & X86_CR0_TS)) {
3506 rc = emulate_nm(ctxt);
3507 goto done;
3508 }
3509
c4f035c6 3510 if (unlikely(ctxt->guest_mode) && c->intercept) {
8a76d7f2
JR		 3511 rc = emulator_check_intercept(ctxt, c->intercept,
3512 X86_ICPT_PRE_EXCEPT);
c4f035c6
AK		 3513 if (rc != X86EMUL_CONTINUE)
3514 goto done;
3515 }
3516
e92805ac 3517 /* Privileged instruction can be executed only in CPL=0 */
9c537244 3518 if ((c->d & Priv) && ops->cpl(ctxt->vcpu)) {
35d3d4a1 3519 rc = emulate_gp(ctxt, 0);
e92805ac
GN		 3520 goto done;
3521 }
3522
8ea7d6ae
JR		 3523 /* Instruction can only be executed in protected mode */
3524 if ((c->d & Prot) && !(ctxt->mode & X86EMUL_MODE_PROT)) {
3525 rc = emulate_ud(ctxt);
3526 goto done;
3527 }
3528
d09beabd
JR		 3529 /* Do instruction specific permission checks */
3530 if (c->check_perm) {
3531 rc = c->check_perm(ctxt);
3532 if (rc != X86EMUL_CONTINUE)
3533 goto done;
3534 }
3535
c4f035c6 3536 if (unlikely(ctxt->guest_mode) && c->intercept) {
8a76d7f2
JR		 3537 rc = emulator_check_intercept(ctxt, c->intercept,
3538 X86_ICPT_POST_EXCEPT);
c4f035c6
AK		 3539 if (rc != X86EMUL_CONTINUE)
3540 goto done;
3541 }
3542
b9fa9d6b
AK		 3543 if (c->rep_prefix && (c->d & String)) {
3544 /* All REP prefixes have the same first termination condition */
c73e197b 3545 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) {
95c55886 3546 ctxt->eip = c->eip;
b9fa9d6b
AK		 3547 goto done;
3548 }
b9fa9d6b
AK		 3549 }
3550
c483c02a 3551 if ((c->src.type == OP_MEM) && !(c->d & NoAccess)) {
3ca3ac4d
AK		 3552 rc = segmented_read(ctxt, c->src.addr.mem,
3553 c->src.valptr, c->src.bytes);
b60d513c 3554 if (rc != X86EMUL_CONTINUE)
8b4caf66 3555 goto done;
16518d5a 3556 c->src.orig_val64 = c->src.val64;
8b4caf66
LV		 3557 }
3558
e35b7b9c 3559 if (c->src2.type == OP_MEM) {
3ca3ac4d
AK		 3560 rc = segmented_read(ctxt, c->src2.addr.mem,
3561 &c->src2.val, c->src2.bytes);
e35b7b9c
GN		 3562 if (rc != X86EMUL_CONTINUE)
3563 goto done;
3564 }
3565
8b4caf66
LV		 3566 if ((c->d & DstMask) == ImplicitOps)
3567 goto special_insn;
3568
3569
69f55cb1
GN		 3570 if ((c->dst.type == OP_MEM) && !(c->d & Mov)) {
3571 /* optimisation - avoid slow emulated read if Mov */
3ca3ac4d 3572 rc = segmented_read(ctxt, c->dst.addr.mem,
9de41573 3573 &c->dst.val, c->dst.bytes);
69f55cb1
GN		 3574 if (rc != X86EMUL_CONTINUE)
3575 goto done;
038e51de 3576 }
e4e03ded 3577 c->dst.orig_val = c->dst.val;
038e51de 3578
018a98db
AK		 3579special_insn:
3580
c4f035c6 3581 if (unlikely(ctxt->guest_mode) && c->intercept) {
8a76d7f2
JR		 3582 rc = emulator_check_intercept(ctxt, c->intercept,
3583 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 3584 if (rc != X86EMUL_CONTINUE)
3585 goto done;
3586 }
3587
ef65c889
AK		 3588 if (c->execute) {
3589 rc = c->execute(ctxt);
3590 if (rc != X86EMUL_CONTINUE)
3591 goto done;
3592 goto writeback;
3593 }
3594
e4e03ded 3595 if (c->twobyte)
6aa8b732
AK		 3596 goto twobyte_insn;
3597
e4e03ded 3598 switch (c->b) {
6aa8b732
AK		 3599 case 0x00 ... 0x05:
3600 add: /* add */
05f086f8 3601 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
6aa8b732 3602 break;
0934ac9d 3603 case 0x06: /* push es */
4179bb02 3604 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_ES);
0934ac9d
MG		 3605 break;
3606 case 0x07: /* pop es */
0934ac9d 3607 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES);
0934ac9d 3608 break;
6aa8b732
AK		 3609 case 0x08 ... 0x0d:
3610 or: /* or */
05f086f8 3611 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
6aa8b732 3612 break;
0934ac9d 3613 case 0x0e: /* push cs */
4179bb02 3614 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_CS);
0934ac9d 3615 break;
6aa8b732
AK		 3616 case 0x10 ... 0x15:
3617 adc: /* adc */
05f086f8 3618 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
6aa8b732 3619 break;
0934ac9d 3620 case 0x16: /* push ss */
4179bb02 3621 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_SS);
0934ac9d
MG		 3622 break;
3623 case 0x17: /* pop ss */
0934ac9d 3624 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS);
0934ac9d 3625 break;
6aa8b732
AK		 3626 case 0x18 ... 0x1d:
3627 sbb: /* sbb */
05f086f8 3628 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
6aa8b732 3629 break;
0934ac9d 3630 case 0x1e: /* push ds */
4179bb02 3631 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_DS);
0934ac9d
MG		 3632 break;
3633 case 0x1f: /* pop ds */
0934ac9d 3634 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS);
0934ac9d 3635 break;
aa3a816b 3636 case 0x20 ... 0x25:
6aa8b732 3637 and: /* and */
05f086f8 3638 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 3639 break;
3640 case 0x28 ... 0x2d:
3641 sub: /* sub */
05f086f8 3642 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 3643 break;
3644 case 0x30 ... 0x35:
3645 xor: /* xor */
05f086f8 3646 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 3647 break;
3648 case 0x38 ... 0x3d:
3649 cmp: /* cmp */
575e7c14 3650 c->dst.type = OP_NONE; /* Disable writeback. */
05f086f8 3651 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
6aa8b732 3652 break;
33615aa9
AK		 3653 case 0x40 ... 0x47: /* inc r16/r32 */
3654 emulate_1op("inc", c->dst, ctxt->eflags);
3655 break;
3656 case 0x48 ... 0x4f: /* dec r16/r32 */
3657 emulate_1op("dec", c->dst, ctxt->eflags);
3658 break;
33615aa9
AK		 3659 case 0x58 ... 0x5f: /* pop reg */
3660 pop_instruction:
350f69dc 3661 rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes);
33615aa9 3662 break;
abcf14b5 3663 case 0x60: /* pusha */
4487b3b4 3664 rc = emulate_pusha(ctxt);
abcf14b5
MG		 3665 break;
3666 case 0x61: /* popa */
3667 rc = emulate_popa(ctxt, ops);
abcf14b5 3668 break;
6aa8b732 3669 case 0x63: /* movsxd */
8b4caf66 3670 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 3671 goto cannot_emulate;
e4e03ded 3672 c->dst.val = (s32) c->src.val;
6aa8b732 3673 break;
018a98db
AK		 3674 case 0x6c: /* insb */
3675 case 0x6d: /* insw/insd */
a13a63fa
WY		 3676 c->src.val = c->regs[VCPU_REGS_RDX];
3677 goto do_io_in;
018a98db
AK		 3678 case 0x6e: /* outsb */
3679 case 0x6f: /* outsw/outsd */
a13a63fa
WY		 3680 c->dst.val = c->regs[VCPU_REGS_RDX];
3681 goto do_io_out;
7972995b 3682 break;
b2833e3c 3683 case 0x70 ... 0x7f: /* jcc (short) */
018a98db 3684 if (test_cc(c->b, ctxt->eflags))
b2833e3c 3685 jmp_rel(c, c->src.val);
018a98db 3686 break;
6aa8b732 3687 case 0x80 ... 0x83: /* Grp1 */
e4e03ded 3688 switch (c->modrm_reg) {
6aa8b732
AK		 3689 case 0:
3690 goto add;
3691 case 1:
3692 goto or;
3693 case 2:
3694 goto adc;
3695 case 3:
3696 goto sbb;
3697 case 4:
3698 goto and;
3699 case 5:
3700 goto sub;
3701 case 6:
3702 goto xor;
3703 case 7:
3704 goto cmp;
3705 }
3706 break;
3707 case 0x84 ... 0x85:
dfb507c4 3708 test:
05f086f8 3709 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 3710 break;
3711 case 0x86 ... 0x87: /* xchg */
b13354f8 3712 xchg:
6aa8b732 3713 /* Write back the register source. */
31be40b3
WY		 3714 c->src.val = c->dst.val;
3715 write_register_operand(&c->src);
6aa8b732
AK		 3716 /*
3717 * Write back the memory destination with implicit LOCK
3718 * prefix.
3719 */
31be40b3 3720 c->dst.val = c->src.orig_val;
e4e03ded 3721 c->lock_prefix = 1;
6aa8b732 3722 break;
79168fd1
GN		 3723 case 0x8c: /* mov r/m, sreg */
3724 if (c->modrm_reg > VCPU_SREG_GS) {
35d3d4a1 3725 rc = emulate_ud(ctxt);
5e3ae6c5 3726 goto done;
38d5bc6d 3727 }
79168fd1 3728 c->dst.val = ops->get_segment_selector(c->modrm_reg, ctxt->vcpu);
38d5bc6d 3729 break;
7e0b54b1 3730 case 0x8d: /* lea r16/r32, m */
90de84f5 3731 c->dst.val = c->src.addr.mem.ea;
7e0b54b1 3732 break;
4257198a
GT		 3733 case 0x8e: { /* mov seg, r/m16 */
3734 uint16_t sel;
4257198a
GT		 3735
3736 sel = c->src.val;
8b9f4414 3737
c697518a
GN		 3738 if (c->modrm_reg == VCPU_SREG_CS ||
3739 c->modrm_reg > VCPU_SREG_GS) {
35d3d4a1 3740 rc = emulate_ud(ctxt);
8b9f4414
GN		 3741 goto done;
3742 }
3743
310b5d30 3744 if (c->modrm_reg == VCPU_SREG_SS)
95cb2295 3745 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
310b5d30 3746
2e873022 3747 rc = load_segment_descriptor(ctxt, ops, sel, c->modrm_reg);
4257198a
GT		 3748
3749 c->dst.type = OP_NONE; /* Disable writeback. */
3750 break;
3751 }
6aa8b732 3752 case 0x8f: /* pop (sole member of Grp1a) */
8cdbd2c9 3753 rc = emulate_grp1a(ctxt, ops);
6aa8b732 3754 break;
3d9e77df
AK		 3755 case 0x90 ... 0x97: /* nop / xchg reg, rax */
3756 if (c->dst.addr.reg == &c->regs[VCPU_REGS_RAX])
34698d8c 3757 break;
b13354f8 3758 goto xchg;
e8b6fa70
WY		 3759 case 0x98: /* cbw/cwde/cdqe */
3760 switch (c->op_bytes) {
3761 case 2: c->dst.val = (s8)c->dst.val; break;
3762 case 4: c->dst.val = (s16)c->dst.val; break;
3763 case 8: c->dst.val = (s32)c->dst.val; break;
3764 }
3765 break;
fd2a7608 3766 case 0x9c: /* pushf */
05f086f8 3767 c->src.val = (unsigned long) ctxt->eflags;
4487b3b4 3768 rc = em_push(ctxt);
8cdbd2c9 3769 break;
535eabcf 3770 case 0x9d: /* popf */
2b48cc75 3771 c->dst.type = OP_REG;
1a6440ae 3772 c->dst.addr.reg = &ctxt->eflags;
2b48cc75 3773 c->dst.bytes = c->op_bytes;
d4c6a154 3774 rc = emulate_popf(ctxt, ops, &c->dst.val, c->op_bytes);
d4c6a154 3775 break;
6aa8b732 3776 case 0xa6 ... 0xa7: /* cmps */
a682e354 3777 goto cmp;
dfb507c4
MG		 3778 case 0xa8 ... 0xa9: /* test ax, imm */
3779 goto test;
6aa8b732 3780 case 0xae ... 0xaf: /* scas */
f6b33fc5 3781 goto cmp;
018a98db
AK		 3782 case 0xc0 ... 0xc1:
3783 emulate_grp2(ctxt);
3784 break;
111de5d6 3785 case 0xc3: /* ret */
cf5de4f8 3786 c->dst.type = OP_REG;
1a6440ae 3787 c->dst.addr.reg = &c->eip;
cf5de4f8 3788 c->dst.bytes = c->op_bytes;
111de5d6 3789 goto pop_instruction;
09b5f4d3
WY		 3790 case 0xc4: /* les */
3791 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_ES);
09b5f4d3
WY		 3792 break;
3793 case 0xc5: /* lds */
3794 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_DS);
09b5f4d3 3795 break;
a77ab5ea
AK		 3796 case 0xcb: /* ret far */
3797 rc = emulate_ret_far(ctxt, ops);
62bd430e 3798 break;
6e154e56
MG		 3799 case 0xcc: /* int3 */
3800 irq = 3;
3801 goto do_interrupt;
3802 case 0xcd: /* int n */
3803 irq = c->src.val;
3804 do_interrupt:
3805 rc = emulate_int(ctxt, ops, irq);
6e154e56
MG		 3806 break;
3807 case 0xce: /* into */
3808 if (ctxt->eflags & EFLG_OF) {
3809 irq = 4;
3810 goto do_interrupt;
3811 }
3812 break;
62bd430e
MG		 3813 case 0xcf: /* iret */
3814 rc = emulate_iret(ctxt, ops);
a77ab5ea 3815 break;
018a98db 3816 case 0xd0 ... 0xd1: /* Grp2 */
018a98db
AK		 3817 emulate_grp2(ctxt);
3818 break;
3819 case 0xd2 ... 0xd3: /* Grp2 */
3820 c->src.val = c->regs[VCPU_REGS_RCX];
3821 emulate_grp2(ctxt);
3822 break;
f2f31845
WY		 3823 case 0xe0 ... 0xe2: /* loop/loopz/loopnz */
3824 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
3825 if (address_mask(c, c->regs[VCPU_REGS_RCX]) != 0 &&
3826 (c->b == 0xe2 || test_cc(c->b ^ 0x5, ctxt->eflags)))
3827 jmp_rel(c, c->src.val);
3828 break;
e4abac67
WY		 3829 case 0xe3: /* jcxz/jecxz/jrcxz */
3830 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0)
3831 jmp_rel(c, c->src.val);
3832 break;
a6a3034c
MG		 3833 case 0xe4: /* inb */
3834 case 0xe5: /* in */
cf8f70bf 3835 goto do_io_in;
a6a3034c
MG		 3836 case 0xe6: /* outb */
3837 case 0xe7: /* out */
cf8f70bf 3838 goto do_io_out;
1a52e051 3839 case 0xe8: /* call (near) */ {
d53c4777 3840 long int rel = c->src.val;
e4e03ded 3841 c->src.val = (unsigned long) c->eip;
7a957275 3842 jmp_rel(c, rel);
4487b3b4 3843 rc = em_push(ctxt);
8cdbd2c9 3844 break;
1a52e051
NK		 3845 }
3846 case 0xe9: /* jmp rel */
954cd36f 3847 goto jmp;
414e6277
GN		 3848 case 0xea: { /* jmp far */
3849 unsigned short sel;
ea79849d 3850 jump_far:
414e6277
GN		 3851 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
3852
3853 if (load_segment_descriptor(ctxt, ops, sel, VCPU_SREG_CS))
c697518a 3854 goto done;
954cd36f 3855
414e6277
GN		 3856 c->eip = 0;
3857 memcpy(&c->eip, c->src.valptr, c->op_bytes);
954cd36f 3858 break;
414e6277 3859 }
954cd36f
GT		 3860 case 0xeb:
3861 jmp: /* jmp rel short */
7a957275 3862 jmp_rel(c, c->src.val);
a01af5ec 3863 c->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 3864 break;
a6a3034c
MG		 3865 case 0xec: /* in al,dx */
3866 case 0xed: /* in (e/r)ax,dx */
cf8f70bf
GN		 3867 c->src.val = c->regs[VCPU_REGS_RDX];
3868 do_io_in:
7b262e90
GN		 3869 if (!pio_in_emulated(ctxt, ops, c->dst.bytes, c->src.val,
3870 &c->dst.val))
cf8f70bf
GN		 3871 goto done; /* IO is needed */
3872 break;
ce7a0ad3
WY		 3873 case 0xee: /* out dx,al */
3874 case 0xef: /* out dx,(e/r)ax */
41167be5 3875 c->dst.val = c->regs[VCPU_REGS_RDX];
cf8f70bf 3876 do_io_out:
41167be5
WY		 3877 ops->pio_out_emulated(c->src.bytes, c->dst.val,
3878 &c->src.val, 1, ctxt->vcpu);
cf8f70bf 3879 c->dst.type = OP_NONE; /* Disable writeback. */
e93f36bc 3880 break;
111de5d6 3881 case 0xf4: /* hlt */
ad312c7c 3882 ctxt->vcpu->arch.halt_request = 1;
19fdfa0d 3883 break;
111de5d6
AK		 3884 case 0xf5: /* cmc */
3885 /* complement carry flag from eflags reg */
3886 ctxt->eflags ^= EFLG_CF;
111de5d6 3887 break;
018a98db 3888 case 0xf6 ... 0xf7: /* Grp3 */
34d1f490 3889 rc = emulate_grp3(ctxt, ops);
018a98db 3890 break;
111de5d6
AK		 3891 case 0xf8: /* clc */
3892 ctxt->eflags &= ~EFLG_CF;
111de5d6 3893 break;
8744aa9a
MG		 3894 case 0xf9: /* stc */
3895 ctxt->eflags |= EFLG_CF;
3896 break;
111de5d6 3897 case 0xfa: /* cli */
07cbc6c1 3898 if (emulator_bad_iopl(ctxt, ops)) {
35d3d4a1 3899 rc = emulate_gp(ctxt, 0);
07cbc6c1 3900 goto done;
36089fed 3901 } else
f850e2e6 3902 ctxt->eflags &= ~X86_EFLAGS_IF;
111de5d6
AK		 3903 break;
3904 case 0xfb: /* sti */
07cbc6c1 3905 if (emulator_bad_iopl(ctxt, ops)) {
35d3d4a1 3906 rc = emulate_gp(ctxt, 0);
07cbc6c1
WY		 3907 goto done;
3908 } else {
95cb2295 3909 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
f850e2e6 3910 ctxt->eflags |= X86_EFLAGS_IF;
f850e2e6 3911 }
111de5d6 3912 break;
fb4616f4
MG		 3913 case 0xfc: /* cld */
3914 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 3915 break;
3916 case 0xfd: /* std */
3917 ctxt->eflags |= EFLG_DF;
fb4616f4 3918 break;
ea79849d
GN		 3919 case 0xfe: /* Grp4 */
3920 grp45:
4487b3b4 3921 rc = emulate_grp45(ctxt);
018a98db 3922 break;
ea79849d
GN		 3923 case 0xff: /* Grp5 */
3924 if (c->modrm_reg == 5)
3925 goto jump_far;
3926 goto grp45;
91269b8f
AK		 3927 default:
3928 goto cannot_emulate;
6aa8b732 3929 }
018a98db 3930
7d9ddaed
AK		 3931 if (rc != X86EMUL_CONTINUE)
3932 goto done;
3933
018a98db
AK		 3934writeback:
3935 rc = writeback(ctxt, ops);
1b30eaa8 3936 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 3937 goto done;
3938
5cd21917
GN		 3939 /*
3940 * restore dst type in case the decoding will be reused
3941 * (happens for string instruction )
3942 */
3943 c->dst.type = saved_dst_type;
3944
a682e354 3945 if ((c->d & SrcMask) == SrcSI)
90de84f5 3946 string_addr_inc(ctxt, seg_override(ctxt, ops, c),
79168fd1 3947 VCPU_REGS_RSI, &c->src);
a682e354
GN		 3948
3949 if ((c->d & DstMask) == DstDI)
90de84f5 3950 string_addr_inc(ctxt, VCPU_SREG_ES, VCPU_REGS_RDI,
79168fd1 3951 &c->dst);
d9271123 3952
5cd21917 3953 if (c->rep_prefix && (c->d & String)) {
6e2fb2ca 3954 struct read_cache *r = &ctxt->decode.io_read;
d9271123 3955 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
3e2f65d5 3956
d2ddd1c4
GN		 3957 if (!string_insn_completed(ctxt)) {
3958 /*
3959 * Re-enter guest when pio read ahead buffer is empty
3960 * or, if it is not used, after each 1024 iteration.
3961 */
3962 if ((r->end != 0 || c->regs[VCPU_REGS_RCX] & 0x3ff) &&
3963 (r->end == 0 || r->end != r->pos)) {
3964 /*
3965 * Reset read cache. Usually happens before
3966 * decode, but since instruction is restarted
3967 * we have to do it here.
3968 */
3969 ctxt->decode.mem_read.end = 0;
3970 return EMULATION_RESTART;
3971 }
3972 goto done; /* skip rip writeback */
0fa6ccbd 3973 }
5cd21917 3974 }
d2ddd1c4
GN		 3975
3976 ctxt->eip = c->eip;
018a98db
AK		 3977
3978done:
da9cb575
AK		 3979 if (rc == X86EMUL_PROPAGATE_FAULT)
3980 ctxt->have_exception = true;
775fde86
JR		 3981 if (rc == X86EMUL_INTERCEPTED)
3982 return EMULATION_INTERCEPTED;
3983
d2ddd1c4 3984 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 3985
3986twobyte_insn:
e4e03ded 3987 switch (c->b) {
6aa8b732 3988 case 0x01: /* lgdt, lidt, lmsw */
e4e03ded 3989 switch (c->modrm_reg) {
6aa8b732
AK		 3990 u16 size;
3991 unsigned long address;
3992
aca7f966 3993 case 0: /* vmcall */
e4e03ded 3994 if (c->modrm_mod != 3 || c->modrm_rm != 1)
aca7f966
AL		 3995 goto cannot_emulate;
3996
7aa81cc0 3997 rc = kvm_fix_hypercall(ctxt->vcpu);
1b30eaa8 3998 if (rc != X86EMUL_CONTINUE)
7aa81cc0
AL		 3999 goto done;
4000
33e3885d 4001 /* Let the processor re-execute the fixed hypercall */
063db061 4002 c->eip = ctxt->eip;
16286d08
AK		 4003 /* Disable writeback. */
4004 c->dst.type = OP_NONE;
aca7f966 4005 break;
6aa8b732 4006 case 2: /* lgdt */
1a6440ae 4007 rc = read_descriptor(ctxt, ops, c->src.addr.mem,
e4e03ded 4008 &size, &address, c->op_bytes);
1b30eaa8 4009 if (rc != X86EMUL_CONTINUE)
6aa8b732
AK		 4010 goto done;
4011 realmode_lgdt(ctxt->vcpu, size, address);
16286d08
AK		 4012 /* Disable writeback. */
4013 c->dst.type = OP_NONE;
6aa8b732 4014 break;
aca7f966 4015 case 3: /* lidt/vmmcall */
2b3d2a20
AK		 4016 if (c->modrm_mod == 3) {
4017 switch (c->modrm_rm) {
4018 case 1:
4019 rc = kvm_fix_hypercall(ctxt->vcpu);
2b3d2a20
AK		 4020 break;
4021 default:
4022 goto cannot_emulate;
4023 }
aca7f966 4024 } else {
1a6440ae 4025 rc = read_descriptor(ctxt, ops, c->src.addr.mem,
aca7f966 4026 &size, &address,
e4e03ded 4027 c->op_bytes);
1b30eaa8 4028 if (rc != X86EMUL_CONTINUE)
aca7f966
AL		 4029 goto done;
4030 realmode_lidt(ctxt->vcpu, size, address);
4031 }
16286d08
AK		 4032 /* Disable writeback. */
4033 c->dst.type = OP_NONE;
6aa8b732
AK		 4034 break;
4035 case 4: /* smsw */
16286d08 4036 c->dst.bytes = 2;
52a46617 4037 c->dst.val = ops->get_cr(0, ctxt->vcpu);
6aa8b732
AK		 4038 break;
4039 case 6: /* lmsw */
9928ff60 4040 ops->set_cr(0, (ops->get_cr(0, ctxt->vcpu) & ~0x0eul) |
93a152be 4041 (c->src.val & 0x0f), ctxt->vcpu);
dc7457ea 4042 c->dst.type = OP_NONE;
6aa8b732 4043 break;
6e1e5ffe 4044 case 5: /* not defined */
54b8486f 4045 emulate_ud(ctxt);
da9cb575 4046 rc = X86EMUL_PROPAGATE_FAULT;
6e1e5ffe 4047 goto done;
6aa8b732 4048 case 7: /* invlpg*/
38503911 4049 rc = em_invlpg(ctxt);
6aa8b732
AK		 4050 break;
4051 default:
4052 goto cannot_emulate;
4053 }
4054 break;
e99f0507 4055 case 0x05: /* syscall */
3fb1b5db 4056 rc = emulate_syscall(ctxt, ops);
e99f0507 4057 break;
018a98db
AK		 4058 case 0x06:
4059 emulate_clts(ctxt->vcpu);
018a98db 4060 break;
018a98db 4061 case 0x09: /* wbinvd */
f5f48ee1 4062 kvm_emulate_wbinvd(ctxt->vcpu);
f5f48ee1
SY		 4063 break;
4064 case 0x08: /* invd */
018a98db
AK		 4065 case 0x0d: /* GrpP (prefetch) */
4066 case 0x18: /* Grp16 (prefetch/nop) */
018a98db
AK		 4067 break;
4068 case 0x20: /* mov cr, reg */
1a0c7d44 4069 c->dst.val = ops->get_cr(c->modrm_reg, ctxt->vcpu);
018a98db 4070 break;
6aa8b732 4071 case 0x21: /* mov from dr to reg */
b27f3856 4072 ops->get_dr(c->modrm_reg, &c->dst.val, ctxt->vcpu);
6aa8b732 4073 break;
018a98db 4074 case 0x22: /* mov reg, cr */
1a0c7d44 4075 if (ops->set_cr(c->modrm_reg, c->src.val, ctxt->vcpu)) {
54b8486f 4076 emulate_gp(ctxt, 0);
da9cb575 4077 rc = X86EMUL_PROPAGATE_FAULT;
0f12244f
GN		 4078 goto done;
4079 }
018a98db
AK		 4080 c->dst.type = OP_NONE;
4081 break;
6aa8b732 4082 case 0x23: /* mov from reg to dr */
b27f3856 4083 if (ops->set_dr(c->modrm_reg, c->src.val &
338dbc97
GN		 4084 ((ctxt->mode == X86EMUL_MODE_PROT64) ?
4085 ~0ULL : ~0U), ctxt->vcpu) < 0) {
4086 /* #UD condition is already handled by the code above */
54b8486f 4087 emulate_gp(ctxt, 0);
da9cb575 4088 rc = X86EMUL_PROPAGATE_FAULT;
338dbc97
GN		 4089 goto done;
4090 }
4091
a01af5ec 4092 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 4093 break;
018a98db
AK		 4094 case 0x30:
4095 /* wrmsr */
4096 msr_data = (u32)c->regs[VCPU_REGS_RAX]
4097 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
3fb1b5db 4098 if (ops->set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data)) {
54b8486f 4099 emulate_gp(ctxt, 0);
da9cb575 4100 rc = X86EMUL_PROPAGATE_FAULT;
fd525365 4101 goto done;
018a98db
AK		 4102 }
4103 rc = X86EMUL_CONTINUE;
018a98db
AK		 4104 break;
4105 case 0x32:
4106 /* rdmsr */
3fb1b5db 4107 if (ops->get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data)) {
54b8486f 4108 emulate_gp(ctxt, 0);
da9cb575 4109 rc = X86EMUL_PROPAGATE_FAULT;
fd525365 4110 goto done;
018a98db
AK		 4111 } else {
4112 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
4113 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
4114 }
4115 rc = X86EMUL_CONTINUE;
018a98db 4116 break;
e99f0507 4117 case 0x34: /* sysenter */
3fb1b5db 4118 rc = emulate_sysenter(ctxt, ops);
e99f0507
AP		 4119 break;
4120 case 0x35: /* sysexit */
3fb1b5db 4121 rc = emulate_sysexit(ctxt, ops);
e99f0507 4122 break;
6aa8b732 4123 case 0x40 ... 0x4f: /* cmov */
e4e03ded 4124 c->dst.val = c->dst.orig_val = c->src.val;
a01af5ec
LV		 4125 if (!test_cc(c->b, ctxt->eflags))
4126 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 4127 break;
b2833e3c 4128 case 0x80 ... 0x8f: /* jnz rel, etc*/
018a98db 4129 if (test_cc(c->b, ctxt->eflags))
b2833e3c 4130 jmp_rel(c, c->src.val);
018a98db 4131 break;
ee45b58e
WY		 4132 case 0x90 ... 0x9f: /* setcc r/m8 */
4133 c->dst.val = test_cc(c->b, ctxt->eflags);
4134 break;
0934ac9d 4135 case 0xa0: /* push fs */
4179bb02 4136 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_FS);
0934ac9d
MG		 4137 break;
4138 case 0xa1: /* pop fs */
4139 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS);
0934ac9d 4140 break;
7de75248
NK		 4141 case 0xa3:
4142 bt: /* bt */
e4f8e039 4143 c->dst.type = OP_NONE;
e4e03ded
LV		 4144 /* only subword offset */
4145 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 4146 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
7de75248 4147 break;
9bf8ea42
GT		 4148 case 0xa4: /* shld imm8, r, r/m */
4149 case 0xa5: /* shld cl, r, r/m */
4150 emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
4151 break;
0934ac9d 4152 case 0xa8: /* push gs */
4179bb02 4153 rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_GS);
0934ac9d
MG		 4154 break;
4155 case 0xa9: /* pop gs */
4156 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS);
0934ac9d 4157 break;
7de75248
NK		 4158 case 0xab:
4159 bts: /* bts */
05f086f8 4160 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
7de75248 4161 break;
9bf8ea42
GT		 4162 case 0xac: /* shrd imm8, r, r/m */
4163 case 0xad: /* shrd cl, r, r/m */
4164 emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags);
4165 break;
2a7c5b8b
GC		 4166 case 0xae: /* clflush */
4167 break;
6aa8b732
AK		 4168 case 0xb0 ... 0xb1: /* cmpxchg */
4169 /*
4170 * Save real source value, then compare EAX against
4171 * destination.
4172 */
e4e03ded
LV		 4173 c->src.orig_val = c->src.val;
4174 c->src.val = c->regs[VCPU_REGS_RAX];
05f086f8
LV		 4175 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
4176 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 4177 /* Success: write back to memory. */
e4e03ded 4178 c->dst.val = c->src.orig_val;
6aa8b732
AK		 4179 } else {
4180 /* Failure: write the value we saw to EAX. */
e4e03ded 4181 c->dst.type = OP_REG;
1a6440ae 4182 c->dst.addr.reg = (unsigned long *)&c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 4183 }
4184 break;
09b5f4d3
WY		 4185 case 0xb2: /* lss */
4186 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_SS);
09b5f4d3 4187 break;
6aa8b732
AK		 4188 case 0xb3:
4189 btr: /* btr */
05f086f8 4190 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
6aa8b732 4191 break;
09b5f4d3
WY		 4192 case 0xb4: /* lfs */
4193 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_FS);
09b5f4d3
WY		 4194 break;
4195 case 0xb5: /* lgs */
4196 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_GS);
09b5f4d3 4197 break;
6aa8b732 4198 case 0xb6 ... 0xb7: /* movzx */
e4e03ded
LV		 4199 c->dst.bytes = c->op_bytes;
4200 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
4201 : (u16) c->src.val;
6aa8b732 4202 break;
6aa8b732 4203 case 0xba: /* Grp8 */
e4e03ded 4204 switch (c->modrm_reg & 3) {
6aa8b732
AK		 4205 case 0:
4206 goto bt;
4207 case 1:
4208 goto bts;
4209 case 2:
4210 goto btr;
4211 case 3:
4212 goto btc;
4213 }
4214 break;
7de75248
NK		 4215 case 0xbb:
4216 btc: /* btc */
05f086f8 4217 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
7de75248 4218 break;
d9574a25
WY		 4219 case 0xbc: { /* bsf */
4220 u8 zf;
4221 __asm__ ("bsf %2, %0; setz %1"
4222 : "=r"(c->dst.val), "=q"(zf)
4223 : "r"(c->src.val));
4224 ctxt->eflags &= ~X86_EFLAGS_ZF;
4225 if (zf) {
4226 ctxt->eflags |= X86_EFLAGS_ZF;
4227 c->dst.type = OP_NONE; /* Disable writeback. */
4228 }
4229 break;
4230 }
4231 case 0xbd: { /* bsr */
4232 u8 zf;
4233 __asm__ ("bsr %2, %0; setz %1"
4234 : "=r"(c->dst.val), "=q"(zf)
4235 : "r"(c->src.val));
4236 ctxt->eflags &= ~X86_EFLAGS_ZF;
4237 if (zf) {
4238 ctxt->eflags |= X86_EFLAGS_ZF;
4239 c->dst.type = OP_NONE; /* Disable writeback. */
4240 }
4241 break;
4242 }
6aa8b732 4243 case 0xbe ... 0xbf: /* movsx */
e4e03ded
LV		 4244 c->dst.bytes = c->op_bytes;
4245 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
4246 (s16) c->src.val;
6aa8b732 4247 break;
92f738a5
WY		 4248 case 0xc0 ... 0xc1: /* xadd */
4249 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
4250 /* Write back the register source. */
4251 c->src.val = c->dst.orig_val;
4252 write_register_operand(&c->src);
4253 break;
a012e65a 4254 case 0xc3: /* movnti */
e4e03ded
LV		 4255 c->dst.bytes = c->op_bytes;
4256 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
4257 (u64) c->src.val;
a012e65a 4258 break;
6aa8b732 4259 case 0xc7: /* Grp9 (cmpxchg8b) */
69f55cb1 4260 rc = emulate_grp9(ctxt, ops);
8cdbd2c9 4261 break;
91269b8f
AK		 4262 default:
4263 goto cannot_emulate;
6aa8b732 4264 }
7d9ddaed
AK		 4265
4266 if (rc != X86EMUL_CONTINUE)
4267 goto done;
4268
6aa8b732
AK		 4269 goto writeback;
4270
4271cannot_emulate:
a0c0ab2f 4272 return EMULATION_FAILED;
6aa8b732 4273}
Linux kernel - Deliverables
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