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KVM: SVM: Add intercept checks for descriptor table accesses
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
9611c187 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
edf88417 23#include <linux/kvm_host.h>
5fdbf976 24#include "kvm_cache_regs.h"
6aa8b732 25#include <linux/module.h>
56e82318 26#include <asm/kvm_emulate.h>
6aa8b732 27
3eeb3288 28#include "x86.h"
38ba30ba 29#include "tss.h"
e99f0507 30
6aa8b732
AK		 31/*
32 * Opcode effective-address decode tables.
33 * Note that we only emulate instructions that have at least one memory
34 * operand (excluding implicit stack references). We assume that stack
35 * references and instruction fetches will never occur in special memory
36 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
37 * not be handled.
38 */
39
40/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 41#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 42/* Destination operand type. */
ab85b12b
AK		 43#define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
44#define DstReg (2<<1) /* Register operand. */
45#define DstMem (3<<1) /* Memory operand. */
46#define DstAcc (4<<1) /* Destination Accumulator */
47#define DstDI (5<<1) /* Destination is in ES:(E)DI */
48#define DstMem64 (6<<1) /* 64bit memory operand */
943858e2 49#define DstImmUByte (7<<1) /* 8-bit unsigned immediate operand */
ab85b12b 50#define DstMask (7<<1)
6aa8b732 51/* Source operand type. */
9c9fddd0 52#define SrcNone (0<<4) /* No source operand. */
9c9fddd0
GT		 53#define SrcReg (1<<4) /* Register operand. */
54#define SrcMem (2<<4) /* Memory operand. */
55#define SrcMem16 (3<<4) /* Memory operand (16-bit). */
56#define SrcMem32 (4<<4) /* Memory operand (32-bit). */
57#define SrcImm (5<<4) /* Immediate operand. */
58#define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
bfcadf83 59#define SrcOne (7<<4) /* Implied '1' */
341de7e3 60#define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */
c9eaf20f 61#define SrcImmU (9<<4) /* Immediate operand, unsigned */
a682e354 62#define SrcSI (0xa<<4) /* Source is in the DS:RSI */
414e6277
GN		 63#define SrcImmFAddr (0xb<<4) /* Source is immediate far address */
64#define SrcMemFAddr (0xc<<4) /* Source is far address in memory */
5d55f299 65#define SrcAcc (0xd<<4) /* Source Accumulator */
b250e605 66#define SrcImmU16 (0xe<<4) /* Immediate operand, unsigned, 16 bits */
341de7e3 67#define SrcMask (0xf<<4)
6aa8b732 68/* Generic ModRM decode. */
341de7e3 69#define ModRM (1<<8)
6aa8b732 70/* Destination is only written; never read. */
341de7e3
GN		 71#define Mov (1<<9)
72#define BitOp (1<<10)
73#define MemAbs (1<<11) /* Memory operand is absolute displacement */
9c9fddd0
GT		 74#define String (1<<12) /* String instruction (rep capable) */
75#define Stack (1<<13) /* Stack instruction (push/pop) */
e09d082c
AK		 76#define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
77#define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
0d7cdee8 78#define Prefix (1<<16) /* Instruction varies with 66/f2/f3 prefix */
1253791d 79#define Sse (1<<17) /* SSE Vector instruction */
d8769fed 80/* Misc flags */
8ea7d6ae 81#define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
d867162c 82#define VendorSpecific (1<<22) /* Vendor specific instruction */
5a506b12 83#define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
7f9b4b75 84#define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
047a4818 85#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 86#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 87#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 88#define No64 (1<<28)
0dc8d10f
GT		 89/* Source 2 operand type */
90#define Src2None (0<<29)
91#define Src2CL (1<<29)
92#define Src2ImmByte (2<<29)
93#define Src2One (3<<29)
7db41eb7 94#define Src2Imm (4<<29)
0dc8d10f 95#define Src2Mask (7<<29)
6aa8b732 96
d0e53325
AK		 97#define X2(x...) x, x
98#define X3(x...) X2(x), x
99#define X4(x...) X2(x), X2(x)
100#define X5(x...) X4(x), x
101#define X6(x...) X4(x), X2(x)
102#define X7(x...) X4(x), X3(x)
103#define X8(x...) X4(x), X4(x)
104#define X16(x...) X8(x), X8(x)
83babbca 105
d65b1dee
AK		 106struct opcode {
107 u32 flags;
c4f035c6 108 u8 intercept;
120df890 109 union {
ef65c889 110 int (*execute)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 111 struct opcode *group;
112 struct group_dual *gdual;
0d7cdee8 113 struct gprefix *gprefix;
120df890 114 } u;
d09beabd 115 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 116};
117
118struct group_dual {
119 struct opcode mod012[8];
120 struct opcode mod3[8];
d65b1dee
AK		 121};
122
0d7cdee8
AK		 123struct gprefix {
124 struct opcode pfx_no;
125 struct opcode pfx_66;
126 struct opcode pfx_f2;
127 struct opcode pfx_f3;
128};
129
6aa8b732 130/* EFLAGS bit definitions. */
d4c6a154
GN		 131#define EFLG_ID (1<<21)
132#define EFLG_VIP (1<<20)
133#define EFLG_VIF (1<<19)
134#define EFLG_AC (1<<18)
b1d86143
AP		 135#define EFLG_VM (1<<17)
136#define EFLG_RF (1<<16)
d4c6a154
GN		 137#define EFLG_IOPL (3<<12)
138#define EFLG_NT (1<<14)
6aa8b732
AK		 139#define EFLG_OF (1<<11)
140#define EFLG_DF (1<<10)
b1d86143 141#define EFLG_IF (1<<9)
d4c6a154 142#define EFLG_TF (1<<8)
6aa8b732
AK		 143#define EFLG_SF (1<<7)
144#define EFLG_ZF (1<<6)
145#define EFLG_AF (1<<4)
146#define EFLG_PF (1<<2)
147#define EFLG_CF (1<<0)
148
62bd430e
MG		 149#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
150#define EFLG_RESERVED_ONE_MASK 2
151
6aa8b732
AK		 152/*
153 * Instruction emulation:
154 * Most instructions are emulated directly via a fragment of inline assembly
155 * code. This allows us to save/restore EFLAGS and thus very easily pick up
156 * any modified flags.
157 */
158
05b3e0c2 159#if defined(CONFIG_X86_64)
6aa8b732
AK		 160#define _LO32 "k" /* force 32-bit operand */
161#define _STK "%%rsp" /* stack pointer */
162#elif defined(__i386__)
163#define _LO32 "" /* force 32-bit operand */
164#define _STK "%%esp" /* stack pointer */
165#endif
166
167/*
168 * These EFLAGS bits are restored from saved value during emulation, and
169 * any changes are written back to the saved value after emulation.
170 */
171#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
172
173/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 174#define _PRE_EFLAGS(_sav, _msk, _tmp) \
175 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
176 "movl %"_sav",%"_LO32 _tmp"; " \
177 "push %"_tmp"; " \
178 "push %"_tmp"; " \
179 "movl %"_msk",%"_LO32 _tmp"; " \
180 "andl %"_LO32 _tmp",("_STK"); " \
181 "pushf; " \
182 "notl %"_LO32 _tmp"; " \
183 "andl %"_LO32 _tmp",("_STK"); " \
184 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
185 "pop %"_tmp"; " \
186 "orl %"_LO32 _tmp",("_STK"); " \
187 "popf; " \
188 "pop %"_sav"; "
6aa8b732
AK		 189
190/* After executing instruction: write-back necessary bits in EFLAGS. */
191#define _POST_EFLAGS(_sav, _msk, _tmp) \
192 /* _sav |= EFLAGS & _msk; */ \
193 "pushf; " \
194 "pop %"_tmp"; " \
195 "andl %"_msk",%"_LO32 _tmp"; " \
196 "orl %"_LO32 _tmp",%"_sav"; "
197
dda96d8f
AK		 198#ifdef CONFIG_X86_64
199#define ON64(x) x
200#else
201#define ON64(x)
202#endif
203
b3b3d25a 204#define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix, _dsttype) \
6b7ad61f
AK		 205 do { \
206 __asm__ __volatile__ ( \
207 _PRE_EFLAGS("0", "4", "2") \
208 _op _suffix " %"_x"3,%1; " \
209 _POST_EFLAGS("0", "4", "2") \
fb2c2641 210 : "=m" (_eflags), "+q" (*(_dsttype*)&(_dst).val),\
6b7ad61f
AK		 211 "=&r" (_tmp) \
212 : _y ((_src).val), "i" (EFLAGS_MASK)); \
f3fd92fb 213 } while (0)
6b7ad61f
AK		 214
215
6aa8b732
AK		 216/* Raw emulation: instruction has two explicit operands. */
217#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 218 do { \
219 unsigned long _tmp; \
220 \
221 switch ((_dst).bytes) { \
222 case 2: \
b3b3d25a 223 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w",u16);\
6b7ad61f
AK		 224 break; \
225 case 4: \
b3b3d25a 226 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l",u32);\
6b7ad61f
AK		 227 break; \
228 case 8: \
b3b3d25a 229 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q",u64)); \
6b7ad61f
AK		 230 break; \
231 } \
6aa8b732
AK		 232 } while (0)
233
234#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
235 do { \
6b7ad61f 236 unsigned long _tmp; \
d77c26fc 237 switch ((_dst).bytes) { \
6aa8b732 238 case 1: \
b3b3d25a 239 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b",u8); \
6aa8b732
AK		 240 break; \
241 default: \
242 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
243 _wx, _wy, _lx, _ly, _qx, _qy); \
244 break; \
245 } \
246 } while (0)
247
248/* Source operand is byte-sized and may be restricted to just %cl. */
249#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
250 __emulate_2op(_op, _src, _dst, _eflags, \
251 "b", "c", "b", "c", "b", "c", "b", "c")
252
253/* Source operand is byte, word, long or quad sized. */
254#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
255 __emulate_2op(_op, _src, _dst, _eflags, \
256 "b", "q", "w", "r", _LO32, "r", "", "r")
257
258/* Source operand is word, long or quad sized. */
259#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
260 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
261 "w", "r", _LO32, "r", "", "r")
262
d175226a
GT		 263/* Instruction has three operands and one operand is stored in ECX register */
264#define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
265 do { \
266 unsigned long _tmp; \
267 _type _clv = (_cl).val; \
268 _type _srcv = (_src).val; \
269 _type _dstv = (_dst).val; \
270 \
271 __asm__ __volatile__ ( \
272 _PRE_EFLAGS("0", "5", "2") \
273 _op _suffix " %4,%1 \n" \
274 _POST_EFLAGS("0", "5", "2") \
275 : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
276 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
277 ); \
278 \
279 (_cl).val = (unsigned long) _clv; \
280 (_src).val = (unsigned long) _srcv; \
281 (_dst).val = (unsigned long) _dstv; \
282 } while (0)
283
284#define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
285 do { \
286 switch ((_dst).bytes) { \
287 case 2: \
288 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
289 "w", unsigned short); \
290 break; \
291 case 4: \
292 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
293 "l", unsigned int); \
294 break; \
295 case 8: \
296 ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
297 "q", unsigned long)); \
298 break; \
299 } \
300 } while (0)
301
dda96d8f 302#define __emulate_1op(_op, _dst, _eflags, _suffix) \
6aa8b732
AK		 303 do { \
304 unsigned long _tmp; \
305 \
dda96d8f
AK		 306 __asm__ __volatile__ ( \
307 _PRE_EFLAGS("0", "3", "2") \
308 _op _suffix " %1; " \
309 _POST_EFLAGS("0", "3", "2") \
310 : "=m" (_eflags), "+m" ((_dst).val), \
311 "=&r" (_tmp) \
312 : "i" (EFLAGS_MASK)); \
313 } while (0)
314
315/* Instruction has only one explicit operand (no source operand). */
316#define emulate_1op(_op, _dst, _eflags) \
317 do { \
d77c26fc 318 switch ((_dst).bytes) { \
dda96d8f
AK		 319 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
320 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
321 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
322 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
6aa8b732
AK		 323 } \
324 } while (0)
325
3f9f53b0
MG		 326#define __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, _suffix) \
327 do { \
328 unsigned long _tmp; \
329 \
330 __asm__ __volatile__ ( \
331 _PRE_EFLAGS("0", "4", "1") \
332 _op _suffix " %5; " \
333 _POST_EFLAGS("0", "4", "1") \
334 : "=m" (_eflags), "=&r" (_tmp), \
335 "+a" (_rax), "+d" (_rdx) \
336 : "i" (EFLAGS_MASK), "m" ((_src).val), \
337 "a" (_rax), "d" (_rdx)); \
338 } while (0)
339
f6b3597b
AK		 340#define __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, _eflags, _suffix, _ex) \
341 do { \
342 unsigned long _tmp; \
343 \
344 __asm__ __volatile__ ( \
345 _PRE_EFLAGS("0", "5", "1") \
346 "1: \n\t" \
347 _op _suffix " %6; " \
348 "2: \n\t" \
349 _POST_EFLAGS("0", "5", "1") \
350 ".pushsection .fixup,\"ax\" \n\t" \
351 "3: movb $1, %4 \n\t" \
352 "jmp 2b \n\t" \
353 ".popsection \n\t" \
354 _ASM_EXTABLE(1b, 3b) \
355 : "=m" (_eflags), "=&r" (_tmp), \
356 "+a" (_rax), "+d" (_rdx), "+qm"(_ex) \
357 : "i" (EFLAGS_MASK), "m" ((_src).val), \
358 "a" (_rax), "d" (_rdx)); \
359 } while (0)
360
3f9f53b0
MG		 361/* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
362#define emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags) \
363 do { \
364 switch((_src).bytes) { \
365 case 1: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "b"); break; \
366 case 2: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "w"); break; \
367 case 4: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "l"); break; \
368 case 8: ON64(__emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "q")); break; \
369 } \
370 } while (0)
371
f6b3597b
AK		 372#define emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, _eflags, _ex) \
373 do { \
374 switch((_src).bytes) { \
375 case 1: \
376 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
377 _eflags, "b", _ex); \
378 break; \
379 case 2: \
380 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
381 _eflags, "w", _ex); \
382 break; \
383 case 4: \
384 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
385 _eflags, "l", _ex); \
386 break; \
387 case 8: ON64( \
388 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
389 _eflags, "q", _ex)); \
390 break; \
391 } \
392 } while (0)
393
6aa8b732
AK		 394/* Fetch next part of the instruction being emulated. */
395#define insn_fetch(_type, _size, _eip) \
396({ unsigned long _x; \
62266869 397 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
af5b4f7f 398 if (rc != X86EMUL_CONTINUE) \
6aa8b732
AK		 399 goto done; \
400 (_eip) += (_size); \
401 (_type)_x; \
402})
403
414e6277
GN		 404#define insn_fetch_arr(_arr, _size, _eip) \
405({ rc = do_insn_fetch(ctxt, ops, (_eip), _arr, (_size)); \
406 if (rc != X86EMUL_CONTINUE) \
407 goto done; \
408 (_eip) += (_size); \
409})
410
8a76d7f2
JR		 411static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
412 enum x86_intercept intercept,
413 enum x86_intercept_stage stage)
414{
415 struct x86_instruction_info info = {
416 .intercept = intercept,
417 .rep_prefix = ctxt->decode.rep_prefix,
418 .modrm_mod = ctxt->decode.modrm_mod,
419 .modrm_reg = ctxt->decode.modrm_reg,
420 .modrm_rm = ctxt->decode.modrm_rm,
421 .src_val = ctxt->decode.src.val64,
422 .src_bytes = ctxt->decode.src.bytes,
423 .dst_bytes = ctxt->decode.dst.bytes,
424 .ad_bytes = ctxt->decode.ad_bytes,
425 .next_rip = ctxt->eip,
426 };
427
428 return ctxt->ops->intercept(ctxt->vcpu, &info, stage);
429}
430
ddcb2885
HH		 431static inline unsigned long ad_mask(struct decode_cache *c)
432{
433 return (1UL << (c->ad_bytes << 3)) - 1;
434}
435
6aa8b732 436/* Access/update address held in a register, based on addressing mode. */
e4706772
HH		 437static inline unsigned long
438address_mask(struct decode_cache *c, unsigned long reg)
439{
440 if (c->ad_bytes == sizeof(unsigned long))
441 return reg;
442 else
443 return reg & ad_mask(c);
444}
445
446static inline unsigned long
90de84f5 447register_address(struct decode_cache *c, unsigned long reg)
e4706772 448{
90de84f5 449 return address_mask(c, reg);
e4706772
HH		 450}
451
7a957275
HH		 452static inline void
453register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
454{
455 if (c->ad_bytes == sizeof(unsigned long))
456 *reg += inc;
457 else
458 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
459}
6aa8b732 460
7a957275
HH		 461static inline void jmp_rel(struct decode_cache *c, int rel)
462{
463 register_address_increment(c, &c->eip, rel);
464}
098c937b 465
7a5b56df
AK		 466static void set_seg_override(struct decode_cache *c, int seg)
467{
468 c->has_seg_override = true;
469 c->seg_override = seg;
470}
471
79168fd1
GN		 472static unsigned long seg_base(struct x86_emulate_ctxt *ctxt,
473 struct x86_emulate_ops *ops, int seg)
7a5b56df
AK		 474{
475 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
476 return 0;
477
79168fd1 478 return ops->get_cached_segment_base(seg, ctxt->vcpu);
7a5b56df
AK		 479}
480
90de84f5
AK		 481static unsigned seg_override(struct x86_emulate_ctxt *ctxt,
482 struct x86_emulate_ops *ops,
483 struct decode_cache *c)
7a5b56df
AK		 484{
485 if (!c->has_seg_override)
486 return 0;
487
90de84f5 488 return c->seg_override;
7a5b56df
AK		 489}
490
90de84f5
AK		 491static ulong linear(struct x86_emulate_ctxt *ctxt,
492 struct segmented_address addr)
7a5b56df 493{
90de84f5
AK		 494 struct decode_cache *c = &ctxt->decode;
495 ulong la;
7a5b56df 496
90de84f5
AK		 497 la = seg_base(ctxt, ctxt->ops, addr.seg) + addr.ea;
498 if (c->ad_bytes != 8)
499 la &= (u32)-1;
500 return la;
7a5b56df
AK		 501}
502
35d3d4a1
AK		 503static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
504 u32 error, bool valid)
54b8486f 505{
da9cb575
AK		 506 ctxt->exception.vector = vec;
507 ctxt->exception.error_code = error;
508 ctxt->exception.error_code_valid = valid;
35d3d4a1 509 return X86EMUL_PROPAGATE_FAULT;
54b8486f
GN		 510}
511
3b88e41a
JR		 512static int emulate_db(struct x86_emulate_ctxt *ctxt)
513{
514 return emulate_exception(ctxt, DB_VECTOR, 0, false);
515}
516
35d3d4a1 517static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 518{
35d3d4a1 519 return emulate_exception(ctxt, GP_VECTOR, err, true);
54b8486f
GN		 520}
521
35d3d4a1 522static int emulate_ud(struct x86_emulate_ctxt *ctxt)
54b8486f 523{
35d3d4a1 524 return emulate_exception(ctxt, UD_VECTOR, 0, false);
54b8486f
GN		 525}
526
35d3d4a1 527static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
54b8486f 528{
35d3d4a1 529 return emulate_exception(ctxt, TS_VECTOR, err, true);
54b8486f
GN		 530}
531
34d1f490
AK		 532static int emulate_de(struct x86_emulate_ctxt *ctxt)
533{
35d3d4a1 534 return emulate_exception(ctxt, DE_VECTOR, 0, false);
34d1f490
AK		 535}
536
1253791d
AK		 537static int emulate_nm(struct x86_emulate_ctxt *ctxt)
538{
539 return emulate_exception(ctxt, NM_VECTOR, 0, false);
540}
541
62266869
AK		 542static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
543 struct x86_emulate_ops *ops,
2fb53ad8 544 unsigned long eip, u8 *dest)
62266869
AK		 545{
546 struct fetch_cache *fc = &ctxt->decode.fetch;
547 int rc;
2fb53ad8 548 int size, cur_size;
62266869 549
2fb53ad8
AK		 550 if (eip == fc->end) {
551 cur_size = fc->end - fc->start;
552 size = min(15UL - cur_size, PAGE_SIZE - offset_in_page(eip));
553 rc = ops->fetch(ctxt->cs_base + eip, fc->data + cur_size,
bcc55cba 554 size, ctxt->vcpu, &ctxt->exception);
3e2815e9 555 if (rc != X86EMUL_CONTINUE)
62266869 556 return rc;
2fb53ad8 557 fc->end += size;
62266869 558 }
2fb53ad8 559 *dest = fc->data[eip - fc->start];
3e2815e9 560 return X86EMUL_CONTINUE;
62266869
AK		 561}
562
563static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
564 struct x86_emulate_ops *ops,
565 unsigned long eip, void *dest, unsigned size)
566{
3e2815e9 567 int rc;
62266869 568
eb3c79e6 569 /* x86 instructions are limited to 15 bytes. */
063db061 570 if (eip + size - ctxt->eip > 15)
eb3c79e6 571 return X86EMUL_UNHANDLEABLE;
62266869
AK		 572 while (size--) {
573 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
3e2815e9 574 if (rc != X86EMUL_CONTINUE)
62266869
AK		 575 return rc;
576 }
3e2815e9 577 return X86EMUL_CONTINUE;
62266869
AK		 578}
579
1e3c5cb0
RR		 580/*
581 * Given the 'reg' portion of a ModRM byte, and a register block, return a
582 * pointer into the block that addresses the relevant register.
583 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
584 */
585static void *decode_register(u8 modrm_reg, unsigned long *regs,
586 int highbyte_regs)
6aa8b732
AK		 587{
588 void *p;
589
590 p = &regs[modrm_reg];
591 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
592 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
593 return p;
594}
595
596static int read_descriptor(struct x86_emulate_ctxt *ctxt,
597 struct x86_emulate_ops *ops,
90de84f5 598 struct segmented_address addr,
6aa8b732
AK		 599 u16 *size, unsigned long *address, int op_bytes)
600{
601 int rc;
602
603 if (op_bytes == 2)
604 op_bytes = 3;
605 *address = 0;
90de84f5 606 rc = ops->read_std(linear(ctxt, addr), (unsigned long *)size, 2,
bcc55cba 607 ctxt->vcpu, &ctxt->exception);
1b30eaa8 608 if (rc != X86EMUL_CONTINUE)
6aa8b732 609 return rc;
30b31ab6
AK		 610 addr.ea += 2;
611 rc = ops->read_std(linear(ctxt, addr), address, op_bytes,
bcc55cba 612 ctxt->vcpu, &ctxt->exception);
6aa8b732
AK		 613 return rc;
614}
615
bbe9abbd
NK		 616static int test_cc(unsigned int condition, unsigned int flags)
617{
618 int rc = 0;
619
620 switch ((condition & 15) >> 1) {
621 case 0: /* o */
622 rc |= (flags & EFLG_OF);
623 break;
624 case 1: /* b/c/nae */
625 rc |= (flags & EFLG_CF);
626 break;
627 case 2: /* z/e */
628 rc |= (flags & EFLG_ZF);
629 break;
630 case 3: /* be/na */
631 rc |= (flags & (EFLG_CF|EFLG_ZF));
632 break;
633 case 4: /* s */
634 rc |= (flags & EFLG_SF);
635 break;
636 case 5: /* p/pe */
637 rc |= (flags & EFLG_PF);
638 break;
639 case 7: /* le/ng */
640 rc |= (flags & EFLG_ZF);
641 /* fall through */
642 case 6: /* l/nge */
643 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
644 break;
645 }
646
647 /* Odd condition identifiers (lsb == 1) have inverted sense. */
648 return (!!rc ^ (condition & 1));
649}
650
91ff3cb4
AK		 651static void fetch_register_operand(struct operand *op)
652{
653 switch (op->bytes) {
654 case 1:
655 op->val = *(u8 *)op->addr.reg;
656 break;
657 case 2:
658 op->val = *(u16 *)op->addr.reg;
659 break;
660 case 4:
661 op->val = *(u32 *)op->addr.reg;
662 break;
663 case 8:
664 op->val = *(u64 *)op->addr.reg;
665 break;
666 }
667}
668
1253791d
AK		 669static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
670{
671 ctxt->ops->get_fpu(ctxt);
672 switch (reg) {
673 case 0: asm("movdqu %%xmm0, %0" : "=m"(*data)); break;
674 case 1: asm("movdqu %%xmm1, %0" : "=m"(*data)); break;
675 case 2: asm("movdqu %%xmm2, %0" : "=m"(*data)); break;
676 case 3: asm("movdqu %%xmm3, %0" : "=m"(*data)); break;
677 case 4: asm("movdqu %%xmm4, %0" : "=m"(*data)); break;
678 case 5: asm("movdqu %%xmm5, %0" : "=m"(*data)); break;
679 case 6: asm("movdqu %%xmm6, %0" : "=m"(*data)); break;
680 case 7: asm("movdqu %%xmm7, %0" : "=m"(*data)); break;
681#ifdef CONFIG_X86_64
682 case 8: asm("movdqu %%xmm8, %0" : "=m"(*data)); break;
683 case 9: asm("movdqu %%xmm9, %0" : "=m"(*data)); break;
684 case 10: asm("movdqu %%xmm10, %0" : "=m"(*data)); break;
685 case 11: asm("movdqu %%xmm11, %0" : "=m"(*data)); break;
686 case 12: asm("movdqu %%xmm12, %0" : "=m"(*data)); break;
687 case 13: asm("movdqu %%xmm13, %0" : "=m"(*data)); break;
688 case 14: asm("movdqu %%xmm14, %0" : "=m"(*data)); break;
689 case 15: asm("movdqu %%xmm15, %0" : "=m"(*data)); break;
690#endif
691 default: BUG();
692 }
693 ctxt->ops->put_fpu(ctxt);
694}
695
696static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
697 int reg)
698{
699 ctxt->ops->get_fpu(ctxt);
700 switch (reg) {
701 case 0: asm("movdqu %0, %%xmm0" : : "m"(*data)); break;
702 case 1: asm("movdqu %0, %%xmm1" : : "m"(*data)); break;
703 case 2: asm("movdqu %0, %%xmm2" : : "m"(*data)); break;
704 case 3: asm("movdqu %0, %%xmm3" : : "m"(*data)); break;
705 case 4: asm("movdqu %0, %%xmm4" : : "m"(*data)); break;
706 case 5: asm("movdqu %0, %%xmm5" : : "m"(*data)); break;
707 case 6: asm("movdqu %0, %%xmm6" : : "m"(*data)); break;
708 case 7: asm("movdqu %0, %%xmm7" : : "m"(*data)); break;
709#ifdef CONFIG_X86_64
710 case 8: asm("movdqu %0, %%xmm8" : : "m"(*data)); break;
711 case 9: asm("movdqu %0, %%xmm9" : : "m"(*data)); break;
712 case 10: asm("movdqu %0, %%xmm10" : : "m"(*data)); break;
713 case 11: asm("movdqu %0, %%xmm11" : : "m"(*data)); break;
714 case 12: asm("movdqu %0, %%xmm12" : : "m"(*data)); break;
715 case 13: asm("movdqu %0, %%xmm13" : : "m"(*data)); break;
716 case 14: asm("movdqu %0, %%xmm14" : : "m"(*data)); break;
717 case 15: asm("movdqu %0, %%xmm15" : : "m"(*data)); break;
718#endif
719 default: BUG();
720 }
721 ctxt->ops->put_fpu(ctxt);
722}
723
724static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
725 struct operand *op,
3c118e24 726 struct decode_cache *c,
3c118e24
AK		 727 int inhibit_bytereg)
728{
33615aa9 729 unsigned reg = c->modrm_reg;
9f1ef3f8 730 int highbyte_regs = c->rex_prefix == 0;
33615aa9
AK		 731
732 if (!(c->d & ModRM))
733 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
1253791d
AK		 734
735 if (c->d & Sse) {
736 op->type = OP_XMM;
737 op->bytes = 16;
738 op->addr.xmm = reg;
739 read_sse_reg(ctxt, &op->vec_val, reg);
740 return;
741 }
742
3c118e24
AK		 743 op->type = OP_REG;
744 if ((c->d & ByteOp) && !inhibit_bytereg) {
1a6440ae 745 op->addr.reg = decode_register(reg, c->regs, highbyte_regs);
3c118e24
AK		 746 op->bytes = 1;
747 } else {
1a6440ae 748 op->addr.reg = decode_register(reg, c->regs, 0);
3c118e24 749 op->bytes = c->op_bytes;
3c118e24 750 }
91ff3cb4 751 fetch_register_operand(op);
3c118e24
AK		 752 op->orig_val = op->val;
753}
754
1c73ef66 755static int decode_modrm(struct x86_emulate_ctxt *ctxt,
2dbd0dd7
AK		 756 struct x86_emulate_ops *ops,
757 struct operand *op)
1c73ef66
AK		 758{
759 struct decode_cache *c = &ctxt->decode;
760 u8 sib;
f5b4edcd 761 int index_reg = 0, base_reg = 0, scale;
3e2815e9 762 int rc = X86EMUL_CONTINUE;
2dbd0dd7 763 ulong modrm_ea = 0;
1c73ef66
AK		 764
765 if (c->rex_prefix) {
766 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
767 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
768 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
769 }
770
771 c->modrm = insn_fetch(u8, 1, c->eip);
772 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
773 c->modrm_reg |= (c->modrm & 0x38) >> 3;
774 c->modrm_rm |= (c->modrm & 0x07);
09ee57cd 775 c->modrm_seg = VCPU_SREG_DS;
1c73ef66
AK		 776
777 if (c->modrm_mod == 3) {
2dbd0dd7
AK		 778 op->type = OP_REG;
779 op->bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
780 op->addr.reg = decode_register(c->modrm_rm,
107d6d2e 781 c->regs, c->d & ByteOp);
1253791d
AK		 782 if (c->d & Sse) {
783 op->type = OP_XMM;
784 op->bytes = 16;
785 op->addr.xmm = c->modrm_rm;
786 read_sse_reg(ctxt, &op->vec_val, c->modrm_rm);
787 return rc;
788 }
2dbd0dd7 789 fetch_register_operand(op);
1c73ef66
AK		 790 return rc;
791 }
792
2dbd0dd7
AK		 793 op->type = OP_MEM;
794
1c73ef66
AK		 795 if (c->ad_bytes == 2) {
796 unsigned bx = c->regs[VCPU_REGS_RBX];
797 unsigned bp = c->regs[VCPU_REGS_RBP];
798 unsigned si = c->regs[VCPU_REGS_RSI];
799 unsigned di = c->regs[VCPU_REGS_RDI];
800
801 /* 16-bit ModR/M decode. */
802 switch (c->modrm_mod) {
803 case 0:
804 if (c->modrm_rm == 6)
2dbd0dd7 805 modrm_ea += insn_fetch(u16, 2, c->eip);
1c73ef66
AK		 806 break;
807 case 1:
2dbd0dd7 808 modrm_ea += insn_fetch(s8, 1, c->eip);
1c73ef66
AK		 809 break;
810 case 2:
2dbd0dd7 811 modrm_ea += insn_fetch(u16, 2, c->eip);
1c73ef66
AK		 812 break;
813 }
814 switch (c->modrm_rm) {
815 case 0:
2dbd0dd7 816 modrm_ea += bx + si;
1c73ef66
AK		 817 break;
818 case 1:
2dbd0dd7 819 modrm_ea += bx + di;
1c73ef66
AK		 820 break;
821 case 2:
2dbd0dd7 822 modrm_ea += bp + si;
1c73ef66
AK		 823 break;
824 case 3:
2dbd0dd7 825 modrm_ea += bp + di;
1c73ef66
AK		 826 break;
827 case 4:
2dbd0dd7 828 modrm_ea += si;
1c73ef66
AK		 829 break;
830 case 5:
2dbd0dd7 831 modrm_ea += di;
1c73ef66
AK		 832 break;
833 case 6:
834 if (c->modrm_mod != 0)
2dbd0dd7 835 modrm_ea += bp;
1c73ef66
AK		 836 break;
837 case 7:
2dbd0dd7 838 modrm_ea += bx;
1c73ef66
AK		 839 break;
840 }
841 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
842 (c->modrm_rm == 6 && c->modrm_mod != 0))
09ee57cd 843 c->modrm_seg = VCPU_SREG_SS;
2dbd0dd7 844 modrm_ea = (u16)modrm_ea;
1c73ef66
AK		 845 } else {
846 /* 32/64-bit ModR/M decode. */
84411d85 847 if ((c->modrm_rm & 7) == 4) {
1c73ef66
AK		 848 sib = insn_fetch(u8, 1, c->eip);
849 index_reg |= (sib >> 3) & 7;
850 base_reg |= sib & 7;
851 scale = sib >> 6;
852
dc71d0f1 853 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
2dbd0dd7 854 modrm_ea += insn_fetch(s32, 4, c->eip);
dc71d0f1 855 else
2dbd0dd7 856 modrm_ea += c->regs[base_reg];
dc71d0f1 857 if (index_reg != 4)
2dbd0dd7 858 modrm_ea += c->regs[index_reg] << scale;
84411d85
AK		 859 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
860 if (ctxt->mode == X86EMUL_MODE_PROT64)
f5b4edcd 861 c->rip_relative = 1;
84411d85 862 } else
2dbd0dd7 863 modrm_ea += c->regs[c->modrm_rm];
1c73ef66
AK		 864 switch (c->modrm_mod) {
865 case 0:
866 if (c->modrm_rm == 5)
2dbd0dd7 867 modrm_ea += insn_fetch(s32, 4, c->eip);
1c73ef66
AK		 868 break;
869 case 1:
2dbd0dd7 870 modrm_ea += insn_fetch(s8, 1, c->eip);
1c73ef66
AK		 871 break;
872 case 2:
2dbd0dd7 873 modrm_ea += insn_fetch(s32, 4, c->eip);
1c73ef66
AK		 874 break;
875 }
876 }
90de84f5 877 op->addr.mem.ea = modrm_ea;
1c73ef66
AK		 878done:
879 return rc;
880}
881
882static int decode_abs(struct x86_emulate_ctxt *ctxt,
2dbd0dd7
AK		 883 struct x86_emulate_ops *ops,
884 struct operand *op)
1c73ef66
AK		 885{
886 struct decode_cache *c = &ctxt->decode;
3e2815e9 887 int rc = X86EMUL_CONTINUE;
1c73ef66 888
2dbd0dd7 889 op->type = OP_MEM;
1c73ef66
AK		 890 switch (c->ad_bytes) {
891 case 2:
90de84f5 892 op->addr.mem.ea = insn_fetch(u16, 2, c->eip);
1c73ef66
AK		 893 break;
894 case 4:
90de84f5 895 op->addr.mem.ea = insn_fetch(u32, 4, c->eip);
1c73ef66
AK		 896 break;
897 case 8:
90de84f5 898 op->addr.mem.ea = insn_fetch(u64, 8, c->eip);
1c73ef66
AK		 899 break;
900 }
901done:
902 return rc;
903}
904
35c843c4
WY		 905static void fetch_bit_operand(struct decode_cache *c)
906{
7129eeca 907 long sv = 0, mask;
35c843c4 908
3885f18f 909 if (c->dst.type == OP_MEM && c->src.type == OP_REG) {
35c843c4
WY		 910 mask = ~(c->dst.bytes * 8 - 1);
911
912 if (c->src.bytes == 2)
913 sv = (s16)c->src.val & (s16)mask;
914 else if (c->src.bytes == 4)
915 sv = (s32)c->src.val & (s32)mask;
916
90de84f5 917 c->dst.addr.mem.ea += (sv >> 3);
35c843c4 918 }
ba7ff2b7
WY		 919
920 /* only subword offset */
921 c->src.val &= (c->dst.bytes << 3) - 1;
35c843c4
WY		 922}
923
dde7e6d1
AK		 924static int read_emulated(struct x86_emulate_ctxt *ctxt,
925 struct x86_emulate_ops *ops,
926 unsigned long addr, void *dest, unsigned size)
6aa8b732 927{
dde7e6d1
AK		 928 int rc;
929 struct read_cache *mc = &ctxt->decode.mem_read;
6aa8b732 930
dde7e6d1
AK		 931 while (size) {
932 int n = min(size, 8u);
933 size -= n;
934 if (mc->pos < mc->end)
935 goto read_cached;
5cd21917 936
bcc55cba
AK		 937 rc = ops->read_emulated(addr, mc->data + mc->end, n,
938 &ctxt->exception, ctxt->vcpu);
dde7e6d1
AK		 939 if (rc != X86EMUL_CONTINUE)
940 return rc;
941 mc->end += n;
6aa8b732 942
dde7e6d1
AK		 943 read_cached:
944 memcpy(dest, mc->data + mc->pos, n);
945 mc->pos += n;
946 dest += n;
947 addr += n;
6aa8b732 948 }
dde7e6d1
AK		 949 return X86EMUL_CONTINUE;
950}
6aa8b732 951
dde7e6d1
AK		 952static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
953 struct x86_emulate_ops *ops,
954 unsigned int size, unsigned short port,
955 void *dest)
956{
957 struct read_cache *rc = &ctxt->decode.io_read;
b4c6abfe 958
dde7e6d1
AK		 959 if (rc->pos == rc->end) { /* refill pio read ahead */
960 struct decode_cache *c = &ctxt->decode;
961 unsigned int in_page, n;
962 unsigned int count = c->rep_prefix ?
963 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1;
964 in_page = (ctxt->eflags & EFLG_DF) ?
965 offset_in_page(c->regs[VCPU_REGS_RDI]) :
966 PAGE_SIZE - offset_in_page(c->regs[VCPU_REGS_RDI]);
967 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
968 count);
969 if (n == 0)
970 n = 1;
971 rc->pos = rc->end = 0;
972 if (!ops->pio_in_emulated(size, port, rc->data, n, ctxt->vcpu))
973 return 0;
974 rc->end = n * size;
6aa8b732
AK		 975 }
976
dde7e6d1
AK		 977 memcpy(dest, rc->data + rc->pos, size);
978 rc->pos += size;
979 return 1;
980}
6aa8b732 981
dde7e6d1
AK		 982static u32 desc_limit_scaled(struct desc_struct *desc)
983{
984 u32 limit = get_desc_limit(desc);
6aa8b732 985
dde7e6d1
AK		 986 return desc->g ? (limit << 12) | 0xfff : limit;
987}
6aa8b732 988
dde7e6d1
AK		 989static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
990 struct x86_emulate_ops *ops,
991 u16 selector, struct desc_ptr *dt)
992{
993 if (selector & 1 << 2) {
994 struct desc_struct desc;
995 memset (dt, 0, sizeof *dt);
5601d05b
GN		 996 if (!ops->get_cached_descriptor(&desc, NULL, VCPU_SREG_LDTR,
997 ctxt->vcpu))
dde7e6d1 998 return;
e09d082c 999
dde7e6d1
AK		 1000 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1001 dt->address = get_desc_base(&desc);
1002 } else
1003 ops->get_gdt(dt, ctxt->vcpu);
1004}
120df890 1005
dde7e6d1
AK		 1006/* allowed just for 8 bytes segments */
1007static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1008 struct x86_emulate_ops *ops,
1009 u16 selector, struct desc_struct *desc)
1010{
1011 struct desc_ptr dt;
1012 u16 index = selector >> 3;
1013 int ret;
dde7e6d1 1014 ulong addr;
120df890 1015
dde7e6d1 1016 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
120df890 1017
35d3d4a1
AK		 1018 if (dt.size < index * 8 + 7)
1019 return emulate_gp(ctxt, selector & 0xfffc);
dde7e6d1 1020 addr = dt.address + index * 8;
bcc55cba
AK		 1021 ret = ops->read_std(addr, desc, sizeof *desc, ctxt->vcpu,
1022 &ctxt->exception);
e09d082c 1023
dde7e6d1
AK		 1024 return ret;
1025}
ef65c889 1026
dde7e6d1
AK		 1027/* allowed just for 8 bytes segments */
1028static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1029 struct x86_emulate_ops *ops,
1030 u16 selector, struct desc_struct *desc)
1031{
1032 struct desc_ptr dt;
1033 u16 index = selector >> 3;
dde7e6d1
AK		 1034 ulong addr;
1035 int ret;
6aa8b732 1036
dde7e6d1 1037 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
6e3d5dfb 1038
35d3d4a1
AK		 1039 if (dt.size < index * 8 + 7)
1040 return emulate_gp(ctxt, selector & 0xfffc);
6aa8b732 1041
dde7e6d1 1042 addr = dt.address + index * 8;
bcc55cba
AK		 1043 ret = ops->write_std(addr, desc, sizeof *desc, ctxt->vcpu,
1044 &ctxt->exception);
c7e75a3d 1045
dde7e6d1
AK		 1046 return ret;
1047}
c7e75a3d 1048
5601d05b 1049/* Does not support long mode */
dde7e6d1
AK		 1050static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1051 struct x86_emulate_ops *ops,
1052 u16 selector, int seg)
1053{
1054 struct desc_struct seg_desc;
1055 u8 dpl, rpl, cpl;
1056 unsigned err_vec = GP_VECTOR;
1057 u32 err_code = 0;
1058 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
1059 int ret;
69f55cb1 1060
dde7e6d1 1061 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 1062
dde7e6d1
AK		 1063 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
1064 || ctxt->mode == X86EMUL_MODE_REAL) {
1065 /* set real mode segment descriptor */
1066 set_desc_base(&seg_desc, selector << 4);
1067 set_desc_limit(&seg_desc, 0xffff);
1068 seg_desc.type = 3;
1069 seg_desc.p = 1;
1070 seg_desc.s = 1;
1071 goto load;
1072 }
1073
1074 /* NULL selector is not valid for TR, CS and SS */
1075 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
1076 && null_selector)
1077 goto exception;
1078
1079 /* TR should be in GDT only */
1080 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1081 goto exception;
1082
1083 if (null_selector) /* for NULL selector skip all following checks */
1084 goto load;
1085
1086 ret = read_segment_descriptor(ctxt, ops, selector, &seg_desc);
1087 if (ret != X86EMUL_CONTINUE)
1088 return ret;
1089
1090 err_code = selector & 0xfffc;
1091 err_vec = GP_VECTOR;
1092
1093 /* can't load system descriptor into segment selecor */
1094 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1095 goto exception;
1096
1097 if (!seg_desc.p) {
1098 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1099 goto exception;
1100 }
1101
1102 rpl = selector & 3;
1103 dpl = seg_desc.dpl;
1104 cpl = ops->cpl(ctxt->vcpu);
1105
1106 switch (seg) {
1107 case VCPU_SREG_SS:
1108 /*
1109 * segment is not a writable data segment or segment
1110 * selector's RPL != CPL or segment selector's RPL != CPL
1111 */
1112 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1113 goto exception;
6aa8b732 1114 break;
dde7e6d1
AK		 1115 case VCPU_SREG_CS:
1116 if (!(seg_desc.type & 8))
1117 goto exception;
1118
1119 if (seg_desc.type & 4) {
1120 /* conforming */
1121 if (dpl > cpl)
1122 goto exception;
1123 } else {
1124 /* nonconforming */
1125 if (rpl > cpl || dpl != cpl)
1126 goto exception;
1127 }
1128 /* CS(RPL) <- CPL */
1129 selector = (selector & 0xfffc) | cpl;
6aa8b732 1130 break;
dde7e6d1
AK		 1131 case VCPU_SREG_TR:
1132 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1133 goto exception;
1134 break;
1135 case VCPU_SREG_LDTR:
1136 if (seg_desc.s || seg_desc.type != 2)
1137 goto exception;
1138 break;
1139 default: /* DS, ES, FS, or GS */
4e62417b 1140 /*
dde7e6d1
AK		 1141 * segment is not a data or readable code segment or
1142 * ((segment is a data or nonconforming code segment)
1143 * and (both RPL and CPL > DPL))
4e62417b 1144 */
dde7e6d1
AK		 1145 if ((seg_desc.type & 0xa) == 0x8 ||
1146 (((seg_desc.type & 0xc) != 0xc) &&
1147 (rpl > dpl && cpl > dpl)))
1148 goto exception;
6aa8b732 1149 break;
dde7e6d1
AK		 1150 }
1151
1152 if (seg_desc.s) {
1153 /* mark segment as accessed */
1154 seg_desc.type |= 1;
1155 ret = write_segment_descriptor(ctxt, ops, selector, &seg_desc);
1156 if (ret != X86EMUL_CONTINUE)
1157 return ret;
1158 }
1159load:
1160 ops->set_segment_selector(selector, seg, ctxt->vcpu);
5601d05b 1161 ops->set_cached_descriptor(&seg_desc, 0, seg, ctxt->vcpu);
dde7e6d1
AK		 1162 return X86EMUL_CONTINUE;
1163exception:
1164 emulate_exception(ctxt, err_vec, err_code, true);
1165 return X86EMUL_PROPAGATE_FAULT;
1166}
1167
31be40b3
WY		 1168static void write_register_operand(struct operand *op)
1169{
1170 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1171 switch (op->bytes) {
1172 case 1:
1173 *(u8 *)op->addr.reg = (u8)op->val;
1174 break;
1175 case 2:
1176 *(u16 *)op->addr.reg = (u16)op->val;
1177 break;
1178 case 4:
1179 *op->addr.reg = (u32)op->val;
1180 break; /* 64b: zero-extend */
1181 case 8:
1182 *op->addr.reg = op->val;
1183 break;
1184 }
1185}
1186
dde7e6d1
AK		 1187static inline int writeback(struct x86_emulate_ctxt *ctxt,
1188 struct x86_emulate_ops *ops)
1189{
1190 int rc;
1191 struct decode_cache *c = &ctxt->decode;
dde7e6d1
AK		 1192
1193 switch (c->dst.type) {
1194 case OP_REG:
31be40b3 1195 write_register_operand(&c->dst);
6aa8b732 1196 break;
dde7e6d1
AK		 1197 case OP_MEM:
1198 if (c->lock_prefix)
1199 rc = ops->cmpxchg_emulated(
90de84f5 1200 linear(ctxt, c->dst.addr.mem),
dde7e6d1
AK		 1201 &c->dst.orig_val,
1202 &c->dst.val,
1203 c->dst.bytes,
bcc55cba 1204 &ctxt->exception,
dde7e6d1 1205 ctxt->vcpu);
341de7e3 1206 else
dde7e6d1 1207 rc = ops->write_emulated(
90de84f5 1208 linear(ctxt, c->dst.addr.mem),
dde7e6d1
AK		 1209 &c->dst.val,
1210 c->dst.bytes,
bcc55cba 1211 &ctxt->exception,
dde7e6d1 1212 ctxt->vcpu);
dde7e6d1
AK		 1213 if (rc != X86EMUL_CONTINUE)
1214 return rc;
a682e354 1215 break;
1253791d
AK		 1216 case OP_XMM:
1217 write_sse_reg(ctxt, &c->dst.vec_val, c->dst.addr.xmm);
1218 break;
dde7e6d1
AK		 1219 case OP_NONE:
1220 /* no writeback */
414e6277 1221 break;
dde7e6d1 1222 default:
414e6277 1223 break;
6aa8b732 1224 }
dde7e6d1
AK		 1225 return X86EMUL_CONTINUE;
1226}
6aa8b732 1227
dde7e6d1
AK		 1228static inline void emulate_push(struct x86_emulate_ctxt *ctxt,
1229 struct x86_emulate_ops *ops)
1230{
1231 struct decode_cache *c = &ctxt->decode;
0dc8d10f 1232
dde7e6d1
AK		 1233 c->dst.type = OP_MEM;
1234 c->dst.bytes = c->op_bytes;
1235 c->dst.val = c->src.val;
1236 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
90de84f5
AK		 1237 c->dst.addr.mem.ea = register_address(c, c->regs[VCPU_REGS_RSP]);
1238 c->dst.addr.mem.seg = VCPU_SREG_SS;
dde7e6d1 1239}
69f55cb1 1240
dde7e6d1
AK		 1241static int emulate_pop(struct x86_emulate_ctxt *ctxt,
1242 struct x86_emulate_ops *ops,
1243 void *dest, int len)
1244{
1245 struct decode_cache *c = &ctxt->decode;
1246 int rc;
90de84f5 1247 struct segmented_address addr;
8b4caf66 1248
90de84f5
AK		 1249 addr.ea = register_address(c, c->regs[VCPU_REGS_RSP]);
1250 addr.seg = VCPU_SREG_SS;
1251 rc = read_emulated(ctxt, ops, linear(ctxt, addr), dest, len);
dde7e6d1
AK		 1252 if (rc != X86EMUL_CONTINUE)
1253 return rc;
1254
1255 register_address_increment(c, &c->regs[VCPU_REGS_RSP], len);
1256 return rc;
8b4caf66
LV		 1257}
1258
dde7e6d1
AK		 1259static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1260 struct x86_emulate_ops *ops,
1261 void *dest, int len)
9de41573
GN		 1262{
1263 int rc;
dde7e6d1
AK		 1264 unsigned long val, change_mask;
1265 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1266 int cpl = ops->cpl(ctxt->vcpu);
9de41573 1267
dde7e6d1
AK		 1268 rc = emulate_pop(ctxt, ops, &val, len);
1269 if (rc != X86EMUL_CONTINUE)
1270 return rc;
9de41573 1271
dde7e6d1
AK		 1272 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1273 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
9de41573 1274
dde7e6d1
AK		 1275 switch(ctxt->mode) {
1276 case X86EMUL_MODE_PROT64:
1277 case X86EMUL_MODE_PROT32:
1278 case X86EMUL_MODE_PROT16:
1279 if (cpl == 0)
1280 change_mask |= EFLG_IOPL;
1281 if (cpl <= iopl)
1282 change_mask |= EFLG_IF;
1283 break;
1284 case X86EMUL_MODE_VM86:
35d3d4a1
AK		 1285 if (iopl < 3)
1286 return emulate_gp(ctxt, 0);
dde7e6d1
AK		 1287 change_mask |= EFLG_IF;
1288 break;
1289 default: /* real mode */
1290 change_mask |= (EFLG_IOPL | EFLG_IF);
1291 break;
9de41573 1292 }
dde7e6d1
AK		 1293
1294 *(unsigned long *)dest =
1295 (ctxt->eflags & ~change_mask) | (val & change_mask);
1296
1297 return rc;
9de41573
GN		 1298}
1299
dde7e6d1
AK		 1300static void emulate_push_sreg(struct x86_emulate_ctxt *ctxt,
1301 struct x86_emulate_ops *ops, int seg)
7b262e90 1302{
dde7e6d1 1303 struct decode_cache *c = &ctxt->decode;
7b262e90 1304
dde7e6d1 1305 c->src.val = ops->get_segment_selector(seg, ctxt->vcpu);
7b262e90 1306
dde7e6d1 1307 emulate_push(ctxt, ops);
7b262e90
GN		 1308}
1309
dde7e6d1
AK		 1310static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt,
1311 struct x86_emulate_ops *ops, int seg)
38ba30ba 1312{
dde7e6d1
AK		 1313 struct decode_cache *c = &ctxt->decode;
1314 unsigned long selector;
1315 int rc;
38ba30ba 1316
dde7e6d1
AK		 1317 rc = emulate_pop(ctxt, ops, &selector, c->op_bytes);
1318 if (rc != X86EMUL_CONTINUE)
1319 return rc;
1320
1321 rc = load_segment_descriptor(ctxt, ops, (u16)selector, seg);
1322 return rc;
38ba30ba
GN		 1323}
1324
dde7e6d1
AK		 1325static int emulate_pusha(struct x86_emulate_ctxt *ctxt,
1326 struct x86_emulate_ops *ops)
38ba30ba 1327{
dde7e6d1
AK		 1328 struct decode_cache *c = &ctxt->decode;
1329 unsigned long old_esp = c->regs[VCPU_REGS_RSP];
1330 int rc = X86EMUL_CONTINUE;
1331 int reg = VCPU_REGS_RAX;
38ba30ba 1332
dde7e6d1
AK		 1333 while (reg <= VCPU_REGS_RDI) {
1334 (reg == VCPU_REGS_RSP) ?
1335 (c->src.val = old_esp) : (c->src.val = c->regs[reg]);
38ba30ba 1336
dde7e6d1 1337 emulate_push(ctxt, ops);
38ba30ba 1338
dde7e6d1
AK		 1339 rc = writeback(ctxt, ops);
1340 if (rc != X86EMUL_CONTINUE)
1341 return rc;
38ba30ba 1342
dde7e6d1 1343 ++reg;
38ba30ba 1344 }
38ba30ba 1345
dde7e6d1
AK		 1346 /* Disable writeback. */
1347 c->dst.type = OP_NONE;
1348
1349 return rc;
38ba30ba
GN		 1350}
1351
dde7e6d1
AK		 1352static int emulate_popa(struct x86_emulate_ctxt *ctxt,
1353 struct x86_emulate_ops *ops)
38ba30ba 1354{
dde7e6d1
AK		 1355 struct decode_cache *c = &ctxt->decode;
1356 int rc = X86EMUL_CONTINUE;
1357 int reg = VCPU_REGS_RDI;
38ba30ba 1358
dde7e6d1
AK		 1359 while (reg >= VCPU_REGS_RAX) {
1360 if (reg == VCPU_REGS_RSP) {
1361 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
1362 c->op_bytes);
1363 --reg;
1364 }
38ba30ba 1365
dde7e6d1
AK		 1366 rc = emulate_pop(ctxt, ops, &c->regs[reg], c->op_bytes);
1367 if (rc != X86EMUL_CONTINUE)
1368 break;
1369 --reg;
38ba30ba 1370 }
dde7e6d1 1371 return rc;
38ba30ba
GN		 1372}
1373
6e154e56
MG		 1374int emulate_int_real(struct x86_emulate_ctxt *ctxt,
1375 struct x86_emulate_ops *ops, int irq)
1376{
1377 struct decode_cache *c = &ctxt->decode;
5c56e1cf 1378 int rc;
6e154e56
MG		 1379 struct desc_ptr dt;
1380 gva_t cs_addr;
1381 gva_t eip_addr;
1382 u16 cs, eip;
6e154e56
MG		 1383
1384 /* TODO: Add limit checks */
1385 c->src.val = ctxt->eflags;
1386 emulate_push(ctxt, ops);
5c56e1cf
AK		 1387 rc = writeback(ctxt, ops);
1388 if (rc != X86EMUL_CONTINUE)
1389 return rc;
6e154e56
MG		 1390
1391 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1392
1393 c->src.val = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
1394 emulate_push(ctxt, ops);
5c56e1cf
AK		 1395 rc = writeback(ctxt, ops);
1396 if (rc != X86EMUL_CONTINUE)
1397 return rc;
6e154e56
MG		 1398
1399 c->src.val = c->eip;
1400 emulate_push(ctxt, ops);
5c56e1cf
AK		 1401 rc = writeback(ctxt, ops);
1402 if (rc != X86EMUL_CONTINUE)
1403 return rc;
1404
1405 c->dst.type = OP_NONE;
6e154e56
MG		 1406
1407 ops->get_idt(&dt, ctxt->vcpu);
1408
1409 eip_addr = dt.address + (irq << 2);
1410 cs_addr = dt.address + (irq << 2) + 2;
1411
bcc55cba 1412 rc = ops->read_std(cs_addr, &cs, 2, ctxt->vcpu, &ctxt->exception);
6e154e56
MG		 1413 if (rc != X86EMUL_CONTINUE)
1414 return rc;
1415
bcc55cba 1416 rc = ops->read_std(eip_addr, &eip, 2, ctxt->vcpu, &ctxt->exception);
6e154e56
MG		 1417 if (rc != X86EMUL_CONTINUE)
1418 return rc;
1419
1420 rc = load_segment_descriptor(ctxt, ops, cs, VCPU_SREG_CS);
1421 if (rc != X86EMUL_CONTINUE)
1422 return rc;
1423
1424 c->eip = eip;
1425
1426 return rc;
1427}
1428
1429static int emulate_int(struct x86_emulate_ctxt *ctxt,
1430 struct x86_emulate_ops *ops, int irq)
1431{
1432 switch(ctxt->mode) {
1433 case X86EMUL_MODE_REAL:
1434 return emulate_int_real(ctxt, ops, irq);
1435 case X86EMUL_MODE_VM86:
1436 case X86EMUL_MODE_PROT16:
1437 case X86EMUL_MODE_PROT32:
1438 case X86EMUL_MODE_PROT64:
1439 default:
1440 /* Protected mode interrupts unimplemented yet */
1441 return X86EMUL_UNHANDLEABLE;
1442 }
1443}
1444
dde7e6d1
AK		 1445static int emulate_iret_real(struct x86_emulate_ctxt *ctxt,
1446 struct x86_emulate_ops *ops)
38ba30ba 1447{
dde7e6d1
AK		 1448 struct decode_cache *c = &ctxt->decode;
1449 int rc = X86EMUL_CONTINUE;
1450 unsigned long temp_eip = 0;
1451 unsigned long temp_eflags = 0;
1452 unsigned long cs = 0;
1453 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1454 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1455 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1456 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1457
dde7e6d1 1458 /* TODO: Add stack limit check */
38ba30ba 1459
dde7e6d1 1460 rc = emulate_pop(ctxt, ops, &temp_eip, c->op_bytes);
38ba30ba 1461
dde7e6d1
AK		 1462 if (rc != X86EMUL_CONTINUE)
1463 return rc;
38ba30ba 1464
35d3d4a1
AK		 1465 if (temp_eip & ~0xffff)
1466 return emulate_gp(ctxt, 0);
38ba30ba 1467
dde7e6d1 1468 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
38ba30ba 1469
dde7e6d1
AK		 1470 if (rc != X86EMUL_CONTINUE)
1471 return rc;
38ba30ba 1472
dde7e6d1 1473 rc = emulate_pop(ctxt, ops, &temp_eflags, c->op_bytes);
38ba30ba 1474
dde7e6d1
AK		 1475 if (rc != X86EMUL_CONTINUE)
1476 return rc;
38ba30ba 1477
dde7e6d1 1478 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
38ba30ba 1479
dde7e6d1
AK		 1480 if (rc != X86EMUL_CONTINUE)
1481 return rc;
38ba30ba 1482
dde7e6d1 1483 c->eip = temp_eip;
38ba30ba 1484
38ba30ba 1485
dde7e6d1
AK		 1486 if (c->op_bytes == 4)
1487 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
1488 else if (c->op_bytes == 2) {
1489 ctxt->eflags &= ~0xffff;
1490 ctxt->eflags |= temp_eflags;
38ba30ba 1491 }
dde7e6d1
AK		 1492
1493 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1494 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1495
1496 return rc;
38ba30ba
GN		 1497}
1498
dde7e6d1
AK		 1499static inline int emulate_iret(struct x86_emulate_ctxt *ctxt,
1500 struct x86_emulate_ops* ops)
c37eda13 1501{
dde7e6d1
AK		 1502 switch(ctxt->mode) {
1503 case X86EMUL_MODE_REAL:
1504 return emulate_iret_real(ctxt, ops);
1505 case X86EMUL_MODE_VM86:
1506 case X86EMUL_MODE_PROT16:
1507 case X86EMUL_MODE_PROT32:
1508 case X86EMUL_MODE_PROT64:
c37eda13 1509 default:
dde7e6d1
AK		 1510 /* iret from protected mode unimplemented yet */
1511 return X86EMUL_UNHANDLEABLE;
c37eda13 1512 }
c37eda13
WY		 1513}
1514
dde7e6d1 1515static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
79168fd1 1516 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1517{
1518 struct decode_cache *c = &ctxt->decode;
1519
dde7e6d1 1520 return emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes);
8cdbd2c9
LV		 1521}
1522
dde7e6d1 1523static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1524{
05f086f8 1525 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1526 switch (c->modrm_reg) {
1527 case 0: /* rol */
05f086f8 1528 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1529 break;
1530 case 1: /* ror */
05f086f8 1531 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1532 break;
1533 case 2: /* rcl */
05f086f8 1534 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1535 break;
1536 case 3: /* rcr */
05f086f8 1537 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1538 break;
1539 case 4: /* sal/shl */
1540 case 6: /* sal/shl */
05f086f8 1541 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1542 break;
1543 case 5: /* shr */
05f086f8 1544 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1545 break;
1546 case 7: /* sar */
05f086f8 1547 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1548 break;
1549 }
1550}
1551
1552static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
05f086f8 1553 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1554{
1555 struct decode_cache *c = &ctxt->decode;
3f9f53b0
MG		 1556 unsigned long *rax = &c->regs[VCPU_REGS_RAX];
1557 unsigned long *rdx = &c->regs[VCPU_REGS_RDX];
34d1f490 1558 u8 de = 0;
8cdbd2c9
LV		 1559
1560 switch (c->modrm_reg) {
1561 case 0 ... 1: /* test */
05f086f8 1562 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1563 break;
1564 case 2: /* not */
1565 c->dst.val = ~c->dst.val;
1566 break;
1567 case 3: /* neg */
05f086f8 1568 emulate_1op("neg", c->dst, ctxt->eflags);
8cdbd2c9 1569 break;
3f9f53b0
MG		 1570 case 4: /* mul */
1571 emulate_1op_rax_rdx("mul", c->src, *rax, *rdx, ctxt->eflags);
1572 break;
1573 case 5: /* imul */
1574 emulate_1op_rax_rdx("imul", c->src, *rax, *rdx, ctxt->eflags);
1575 break;
1576 case 6: /* div */
34d1f490
AK		 1577 emulate_1op_rax_rdx_ex("div", c->src, *rax, *rdx,
1578 ctxt->eflags, de);
3f9f53b0
MG		 1579 break;
1580 case 7: /* idiv */
34d1f490
AK		 1581 emulate_1op_rax_rdx_ex("idiv", c->src, *rax, *rdx,
1582 ctxt->eflags, de);
3f9f53b0 1583 break;
8cdbd2c9 1584 default:
8c5eee30 1585 return X86EMUL_UNHANDLEABLE;
8cdbd2c9 1586 }
34d1f490
AK		 1587 if (de)
1588 return emulate_de(ctxt);
8c5eee30 1589 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1590}
1591
1592static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
a01af5ec 1593 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1594{
1595 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1596
1597 switch (c->modrm_reg) {
1598 case 0: /* inc */
05f086f8 1599 emulate_1op("inc", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1600 break;
1601 case 1: /* dec */
05f086f8 1602 emulate_1op("dec", c->dst, ctxt->eflags);
8cdbd2c9 1603 break;
d19292e4
MG		 1604 case 2: /* call near abs */ {
1605 long int old_eip;
1606 old_eip = c->eip;
1607 c->eip = c->src.val;
1608 c->src.val = old_eip;
79168fd1 1609 emulate_push(ctxt, ops);
d19292e4
MG		 1610 break;
1611 }
8cdbd2c9 1612 case 4: /* jmp abs */
fd60754e 1613 c->eip = c->src.val;
8cdbd2c9
LV		 1614 break;
1615 case 6: /* push */
79168fd1 1616 emulate_push(ctxt, ops);
8cdbd2c9 1617 break;
8cdbd2c9 1618 }
1b30eaa8 1619 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1620}
1621
1622static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
69f55cb1 1623 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1624{
1625 struct decode_cache *c = &ctxt->decode;
16518d5a 1626 u64 old = c->dst.orig_val64;
8cdbd2c9
LV		 1627
1628 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1629 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
8cdbd2c9
LV		 1630 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1631 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1632 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 1633 } else {
16518d5a
AK		 1634 c->dst.val64 = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1635 (u32) c->regs[VCPU_REGS_RBX];
8cdbd2c9 1636
05f086f8 1637 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 1638 }
1b30eaa8 1639 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1640}
1641
a77ab5ea
AK		 1642static int emulate_ret_far(struct x86_emulate_ctxt *ctxt,
1643 struct x86_emulate_ops *ops)
1644{
1645 struct decode_cache *c = &ctxt->decode;
1646 int rc;
1647 unsigned long cs;
1648
1649 rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes);
1b30eaa8 1650 if (rc != X86EMUL_CONTINUE)
a77ab5ea
AK		 1651 return rc;
1652 if (c->op_bytes == 4)
1653 c->eip = (u32)c->eip;
1654 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1b30eaa8 1655 if (rc != X86EMUL_CONTINUE)
a77ab5ea 1656 return rc;
2e873022 1657 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 1658 return rc;
1659}
1660
09b5f4d3
WY		 1661static int emulate_load_segment(struct x86_emulate_ctxt *ctxt,
1662 struct x86_emulate_ops *ops, int seg)
1663{
1664 struct decode_cache *c = &ctxt->decode;
1665 unsigned short sel;
1666 int rc;
1667
1668 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
1669
1670 rc = load_segment_descriptor(ctxt, ops, sel, seg);
1671 if (rc != X86EMUL_CONTINUE)
1672 return rc;
1673
1674 c->dst.val = c->src.val;
1675 return rc;
1676}
1677
e66bb2cc
AP		 1678static inline void
1679setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
79168fd1
GN		 1680 struct x86_emulate_ops *ops, struct desc_struct *cs,
1681 struct desc_struct *ss)
e66bb2cc 1682{
79168fd1 1683 memset(cs, 0, sizeof(struct desc_struct));
5601d05b 1684 ops->get_cached_descriptor(cs, NULL, VCPU_SREG_CS, ctxt->vcpu);
79168fd1 1685 memset(ss, 0, sizeof(struct desc_struct));
e66bb2cc
AP		 1686
1687 cs->l = 0; /* will be adjusted later */
79168fd1 1688 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 1689 cs->g = 1; /* 4kb granularity */
79168fd1 1690 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1691 cs->type = 0x0b; /* Read, Execute, Accessed */
1692 cs->s = 1;
1693 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 1694 cs->p = 1;
1695 cs->d = 1;
e66bb2cc 1696
79168fd1
GN		 1697 set_desc_base(ss, 0); /* flat segment */
1698 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1699 ss->g = 1; /* 4kb granularity */
1700 ss->s = 1;
1701 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 1702 ss->d = 1; /* 32bit stack segment */
e66bb2cc 1703 ss->dpl = 0;
79168fd1 1704 ss->p = 1;
e66bb2cc
AP		 1705}
1706
1707static int
3fb1b5db 1708emulate_syscall(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
e66bb2cc
AP		 1709{
1710 struct decode_cache *c = &ctxt->decode;
79168fd1 1711 struct desc_struct cs, ss;
e66bb2cc 1712 u64 msr_data;
79168fd1 1713 u16 cs_sel, ss_sel;
e66bb2cc
AP		 1714
1715 /* syscall is not available in real mode */
2e901c4c 1716 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 1717 ctxt->mode == X86EMUL_MODE_VM86)
1718 return emulate_ud(ctxt);
e66bb2cc 1719
79168fd1 1720 setup_syscalls_segments(ctxt, ops, &cs, &ss);
e66bb2cc 1721
3fb1b5db 1722 ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
e66bb2cc 1723 msr_data >>= 32;
79168fd1
GN		 1724 cs_sel = (u16)(msr_data & 0xfffc);
1725 ss_sel = (u16)(msr_data + 8);
e66bb2cc
AP		 1726
1727 if (is_long_mode(ctxt->vcpu)) {
79168fd1 1728 cs.d = 0;
e66bb2cc
AP		 1729 cs.l = 1;
1730 }
5601d05b 1731 ops->set_cached_descriptor(&cs, 0, VCPU_SREG_CS, ctxt->vcpu);
79168fd1 1732 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
5601d05b 1733 ops->set_cached_descriptor(&ss, 0, VCPU_SREG_SS, ctxt->vcpu);
79168fd1 1734 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
e66bb2cc
AP		 1735
1736 c->regs[VCPU_REGS_RCX] = c->eip;
1737 if (is_long_mode(ctxt->vcpu)) {
1738#ifdef CONFIG_X86_64
1739 c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
1740
3fb1b5db
GN		 1741 ops->get_msr(ctxt->vcpu,
1742 ctxt->mode == X86EMUL_MODE_PROT64 ?
1743 MSR_LSTAR : MSR_CSTAR, &msr_data);
e66bb2cc
AP		 1744 c->eip = msr_data;
1745
3fb1b5db 1746 ops->get_msr(ctxt->vcpu, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 1747 ctxt->eflags &= ~(msr_data | EFLG_RF);
1748#endif
1749 } else {
1750 /* legacy mode */
3fb1b5db 1751 ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
e66bb2cc
AP		 1752 c->eip = (u32)msr_data;
1753
1754 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1755 }
1756
e54cfa97 1757 return X86EMUL_CONTINUE;
e66bb2cc
AP		 1758}
1759
8c604352 1760static int
3fb1b5db 1761emulate_sysenter(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8c604352
AP		 1762{
1763 struct decode_cache *c = &ctxt->decode;
79168fd1 1764 struct desc_struct cs, ss;
8c604352 1765 u64 msr_data;
79168fd1 1766 u16 cs_sel, ss_sel;
8c604352 1767
a0044755 1768 /* inject #GP if in real mode */
35d3d4a1
AK		 1769 if (ctxt->mode == X86EMUL_MODE_REAL)
1770 return emulate_gp(ctxt, 0);
8c604352
AP		 1771
1772 /* XXX sysenter/sysexit have not been tested in 64bit mode.
1773 * Therefore, we inject an #UD.
1774 */
35d3d4a1
AK		 1775 if (ctxt->mode == X86EMUL_MODE_PROT64)
1776 return emulate_ud(ctxt);
8c604352 1777
79168fd1 1778 setup_syscalls_segments(ctxt, ops, &cs, &ss);
8c604352 1779
3fb1b5db 1780 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 1781 switch (ctxt->mode) {
1782 case X86EMUL_MODE_PROT32:
35d3d4a1
AK		 1783 if ((msr_data & 0xfffc) == 0x0)
1784 return emulate_gp(ctxt, 0);
8c604352
AP		 1785 break;
1786 case X86EMUL_MODE_PROT64:
35d3d4a1
AK		 1787 if (msr_data == 0x0)
1788 return emulate_gp(ctxt, 0);
8c604352
AP		 1789 break;
1790 }
1791
1792 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 1793 cs_sel = (u16)msr_data;
1794 cs_sel &= ~SELECTOR_RPL_MASK;
1795 ss_sel = cs_sel + 8;
1796 ss_sel &= ~SELECTOR_RPL_MASK;
8c604352
AP		 1797 if (ctxt->mode == X86EMUL_MODE_PROT64
1798 || is_long_mode(ctxt->vcpu)) {
79168fd1 1799 cs.d = 0;
8c604352
AP		 1800 cs.l = 1;
1801 }
1802
5601d05b 1803 ops->set_cached_descriptor(&cs, 0, VCPU_SREG_CS, ctxt->vcpu);
79168fd1 1804 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
5601d05b 1805 ops->set_cached_descriptor(&ss, 0, VCPU_SREG_SS, ctxt->vcpu);
79168fd1 1806 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
8c604352 1807
3fb1b5db 1808 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_EIP, &msr_data);
8c604352
AP		 1809 c->eip = msr_data;
1810
3fb1b5db 1811 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_ESP, &msr_data);
8c604352
AP		 1812 c->regs[VCPU_REGS_RSP] = msr_data;
1813
e54cfa97 1814 return X86EMUL_CONTINUE;
8c604352
AP		 1815}
1816
4668f050 1817static int
3fb1b5db 1818emulate_sysexit(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
4668f050
AP		 1819{
1820 struct decode_cache *c = &ctxt->decode;
79168fd1 1821 struct desc_struct cs, ss;
4668f050
AP		 1822 u64 msr_data;
1823 int usermode;
79168fd1 1824 u16 cs_sel, ss_sel;
4668f050 1825
a0044755
GN		 1826 /* inject #GP if in real mode or Virtual 8086 mode */
1827 if (ctxt->mode == X86EMUL_MODE_REAL ||
35d3d4a1
AK		 1828 ctxt->mode == X86EMUL_MODE_VM86)
1829 return emulate_gp(ctxt, 0);
4668f050 1830
79168fd1 1831 setup_syscalls_segments(ctxt, ops, &cs, &ss);
4668f050
AP		 1832
1833 if ((c->rex_prefix & 0x8) != 0x0)
1834 usermode = X86EMUL_MODE_PROT64;
1835 else
1836 usermode = X86EMUL_MODE_PROT32;
1837
1838 cs.dpl = 3;
1839 ss.dpl = 3;
3fb1b5db 1840 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 1841 switch (usermode) {
1842 case X86EMUL_MODE_PROT32:
79168fd1 1843 cs_sel = (u16)(msr_data + 16);
35d3d4a1
AK		 1844 if ((msr_data & 0xfffc) == 0x0)
1845 return emulate_gp(ctxt, 0);
79168fd1 1846 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 1847 break;
1848 case X86EMUL_MODE_PROT64:
79168fd1 1849 cs_sel = (u16)(msr_data + 32);
35d3d4a1
AK		 1850 if (msr_data == 0x0)
1851 return emulate_gp(ctxt, 0);
79168fd1
GN		 1852 ss_sel = cs_sel + 8;
1853 cs.d = 0;
4668f050
AP		 1854 cs.l = 1;
1855 break;
1856 }
79168fd1
GN		 1857 cs_sel |= SELECTOR_RPL_MASK;
1858 ss_sel |= SELECTOR_RPL_MASK;
4668f050 1859
5601d05b 1860 ops->set_cached_descriptor(&cs, 0, VCPU_SREG_CS, ctxt->vcpu);
79168fd1 1861 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
5601d05b 1862 ops->set_cached_descriptor(&ss, 0, VCPU_SREG_SS, ctxt->vcpu);
79168fd1 1863 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
4668f050 1864
bdb475a3
GN		 1865 c->eip = c->regs[VCPU_REGS_RDX];
1866 c->regs[VCPU_REGS_RSP] = c->regs[VCPU_REGS_RCX];
4668f050 1867
e54cfa97 1868 return X86EMUL_CONTINUE;
4668f050
AP		 1869}
1870
9c537244
GN		 1871static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt,
1872 struct x86_emulate_ops *ops)
f850e2e6
GN		 1873{
1874 int iopl;
1875 if (ctxt->mode == X86EMUL_MODE_REAL)
1876 return false;
1877 if (ctxt->mode == X86EMUL_MODE_VM86)
1878 return true;
1879 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
9c537244 1880 return ops->cpl(ctxt->vcpu) > iopl;
f850e2e6
GN		 1881}
1882
1883static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
1884 struct x86_emulate_ops *ops,
1885 u16 port, u16 len)
1886{
79168fd1 1887 struct desc_struct tr_seg;
5601d05b 1888 u32 base3;
f850e2e6 1889 int r;
399a40c9 1890 u16 io_bitmap_ptr, perm, bit_idx = port & 0x7;
f850e2e6 1891 unsigned mask = (1 << len) - 1;
5601d05b 1892 unsigned long base;
f850e2e6 1893
5601d05b 1894 ops->get_cached_descriptor(&tr_seg, &base3, VCPU_SREG_TR, ctxt->vcpu);
79168fd1 1895 if (!tr_seg.p)
f850e2e6 1896 return false;
79168fd1 1897 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 1898 return false;
5601d05b
GN		 1899 base = get_desc_base(&tr_seg);
1900#ifdef CONFIG_X86_64
1901 base |= ((u64)base3) << 32;
1902#endif
1903 r = ops->read_std(base + 102, &io_bitmap_ptr, 2, ctxt->vcpu, NULL);
f850e2e6
GN		 1904 if (r != X86EMUL_CONTINUE)
1905 return false;
79168fd1 1906 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 1907 return false;
399a40c9 1908 r = ops->read_std(base + io_bitmap_ptr + port/8, &perm, 2, ctxt->vcpu,
5601d05b 1909 NULL);
f850e2e6
GN		 1910 if (r != X86EMUL_CONTINUE)
1911 return false;
1912 if ((perm >> bit_idx) & mask)
1913 return false;
1914 return true;
1915}
1916
1917static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
1918 struct x86_emulate_ops *ops,
1919 u16 port, u16 len)
1920{
4fc40f07
GN		 1921 if (ctxt->perm_ok)
1922 return true;
1923
9c537244 1924 if (emulator_bad_iopl(ctxt, ops))
f850e2e6
GN		 1925 if (!emulator_io_port_access_allowed(ctxt, ops, port, len))
1926 return false;
4fc40f07
GN		 1927
1928 ctxt->perm_ok = true;
1929
f850e2e6
GN		 1930 return true;
1931}
1932
38ba30ba
GN		 1933static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
1934 struct x86_emulate_ops *ops,
1935 struct tss_segment_16 *tss)
1936{
1937 struct decode_cache *c = &ctxt->decode;
1938
1939 tss->ip = c->eip;
1940 tss->flag = ctxt->eflags;
1941 tss->ax = c->regs[VCPU_REGS_RAX];
1942 tss->cx = c->regs[VCPU_REGS_RCX];
1943 tss->dx = c->regs[VCPU_REGS_RDX];
1944 tss->bx = c->regs[VCPU_REGS_RBX];
1945 tss->sp = c->regs[VCPU_REGS_RSP];
1946 tss->bp = c->regs[VCPU_REGS_RBP];
1947 tss->si = c->regs[VCPU_REGS_RSI];
1948 tss->di = c->regs[VCPU_REGS_RDI];
1949
1950 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
1951 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
1952 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
1953 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
1954 tss->ldt = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
1955}
1956
1957static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
1958 struct x86_emulate_ops *ops,
1959 struct tss_segment_16 *tss)
1960{
1961 struct decode_cache *c = &ctxt->decode;
1962 int ret;
1963
1964 c->eip = tss->ip;
1965 ctxt->eflags = tss->flag | 2;
1966 c->regs[VCPU_REGS_RAX] = tss->ax;
1967 c->regs[VCPU_REGS_RCX] = tss->cx;
1968 c->regs[VCPU_REGS_RDX] = tss->dx;
1969 c->regs[VCPU_REGS_RBX] = tss->bx;
1970 c->regs[VCPU_REGS_RSP] = tss->sp;
1971 c->regs[VCPU_REGS_RBP] = tss->bp;
1972 c->regs[VCPU_REGS_RSI] = tss->si;
1973 c->regs[VCPU_REGS_RDI] = tss->di;
1974
1975 /*
1976 * SDM says that segment selectors are loaded before segment
1977 * descriptors
1978 */
1979 ops->set_segment_selector(tss->ldt, VCPU_SREG_LDTR, ctxt->vcpu);
1980 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
1981 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
1982 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
1983 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
1984
1985 /*
1986 * Now load segment descriptors. If fault happenes at this stage
1987 * it is handled in a context of new task
1988 */
1989 ret = load_segment_descriptor(ctxt, ops, tss->ldt, VCPU_SREG_LDTR);
1990 if (ret != X86EMUL_CONTINUE)
1991 return ret;
1992 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
1993 if (ret != X86EMUL_CONTINUE)
1994 return ret;
1995 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
1996 if (ret != X86EMUL_CONTINUE)
1997 return ret;
1998 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
1999 if (ret != X86EMUL_CONTINUE)
2000 return ret;
2001 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2002 if (ret != X86EMUL_CONTINUE)
2003 return ret;
2004
2005 return X86EMUL_CONTINUE;
2006}
2007
2008static int task_switch_16(struct x86_emulate_ctxt *ctxt,
2009 struct x86_emulate_ops *ops,
2010 u16 tss_selector, u16 old_tss_sel,
2011 ulong old_tss_base, struct desc_struct *new_desc)
2012{
2013 struct tss_segment_16 tss_seg;
2014 int ret;
bcc55cba 2015 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba
GN		 2016
2017 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
bcc55cba 2018 &ctxt->exception);
db297e3d 2019 if (ret != X86EMUL_CONTINUE)
38ba30ba 2020 /* FIXME: need to provide precise fault address */
38ba30ba 2021 return ret;
38ba30ba
GN		 2022
2023 save_state_to_tss16(ctxt, ops, &tss_seg);
2024
2025 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
bcc55cba 2026 &ctxt->exception);
db297e3d 2027 if (ret != X86EMUL_CONTINUE)
38ba30ba 2028 /* FIXME: need to provide precise fault address */
38ba30ba 2029 return ret;
38ba30ba
GN		 2030
2031 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
bcc55cba 2032 &ctxt->exception);
db297e3d 2033 if (ret != X86EMUL_CONTINUE)
38ba30ba 2034 /* FIXME: need to provide precise fault address */
38ba30ba 2035 return ret;
38ba30ba
GN		 2036
2037 if (old_tss_sel != 0xffff) {
2038 tss_seg.prev_task_link = old_tss_sel;
2039
2040 ret = ops->write_std(new_tss_base,
2041 &tss_seg.prev_task_link,
2042 sizeof tss_seg.prev_task_link,
bcc55cba 2043 ctxt->vcpu, &ctxt->exception);
db297e3d 2044 if (ret != X86EMUL_CONTINUE)
38ba30ba 2045 /* FIXME: need to provide precise fault address */
38ba30ba 2046 return ret;
38ba30ba
GN		 2047 }
2048
2049 return load_state_from_tss16(ctxt, ops, &tss_seg);
2050}
2051
2052static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
2053 struct x86_emulate_ops *ops,
2054 struct tss_segment_32 *tss)
2055{
2056 struct decode_cache *c = &ctxt->decode;
2057
2058 tss->cr3 = ops->get_cr(3, ctxt->vcpu);
2059 tss->eip = c->eip;
2060 tss->eflags = ctxt->eflags;
2061 tss->eax = c->regs[VCPU_REGS_RAX];
2062 tss->ecx = c->regs[VCPU_REGS_RCX];
2063 tss->edx = c->regs[VCPU_REGS_RDX];
2064 tss->ebx = c->regs[VCPU_REGS_RBX];
2065 tss->esp = c->regs[VCPU_REGS_RSP];
2066 tss->ebp = c->regs[VCPU_REGS_RBP];
2067 tss->esi = c->regs[VCPU_REGS_RSI];
2068 tss->edi = c->regs[VCPU_REGS_RDI];
2069
2070 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
2071 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
2072 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
2073 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
2074 tss->fs = ops->get_segment_selector(VCPU_SREG_FS, ctxt->vcpu);
2075 tss->gs = ops->get_segment_selector(VCPU_SREG_GS, ctxt->vcpu);
2076 tss->ldt_selector = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
2077}
2078
2079static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
2080 struct x86_emulate_ops *ops,
2081 struct tss_segment_32 *tss)
2082{
2083 struct decode_cache *c = &ctxt->decode;
2084 int ret;
2085
35d3d4a1
AK		 2086 if (ops->set_cr(3, tss->cr3, ctxt->vcpu))
2087 return emulate_gp(ctxt, 0);
38ba30ba
GN		 2088 c->eip = tss->eip;
2089 ctxt->eflags = tss->eflags | 2;
2090 c->regs[VCPU_REGS_RAX] = tss->eax;
2091 c->regs[VCPU_REGS_RCX] = tss->ecx;
2092 c->regs[VCPU_REGS_RDX] = tss->edx;
2093 c->regs[VCPU_REGS_RBX] = tss->ebx;
2094 c->regs[VCPU_REGS_RSP] = tss->esp;
2095 c->regs[VCPU_REGS_RBP] = tss->ebp;
2096 c->regs[VCPU_REGS_RSI] = tss->esi;
2097 c->regs[VCPU_REGS_RDI] = tss->edi;
2098
2099 /*
2100 * SDM says that segment selectors are loaded before segment
2101 * descriptors
2102 */
2103 ops->set_segment_selector(tss->ldt_selector, VCPU_SREG_LDTR, ctxt->vcpu);
2104 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
2105 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
2106 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
2107 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
2108 ops->set_segment_selector(tss->fs, VCPU_SREG_FS, ctxt->vcpu);
2109 ops->set_segment_selector(tss->gs, VCPU_SREG_GS, ctxt->vcpu);
2110
2111 /*
2112 * Now load segment descriptors. If fault happenes at this stage
2113 * it is handled in a context of new task
2114 */
2115 ret = load_segment_descriptor(ctxt, ops, tss->ldt_selector, VCPU_SREG_LDTR);
2116 if (ret != X86EMUL_CONTINUE)
2117 return ret;
2118 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2119 if (ret != X86EMUL_CONTINUE)
2120 return ret;
2121 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2122 if (ret != X86EMUL_CONTINUE)
2123 return ret;
2124 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2125 if (ret != X86EMUL_CONTINUE)
2126 return ret;
2127 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2128 if (ret != X86EMUL_CONTINUE)
2129 return ret;
2130 ret = load_segment_descriptor(ctxt, ops, tss->fs, VCPU_SREG_FS);
2131 if (ret != X86EMUL_CONTINUE)
2132 return ret;
2133 ret = load_segment_descriptor(ctxt, ops, tss->gs, VCPU_SREG_GS);
2134 if (ret != X86EMUL_CONTINUE)
2135 return ret;
2136
2137 return X86EMUL_CONTINUE;
2138}
2139
2140static int task_switch_32(struct x86_emulate_ctxt *ctxt,
2141 struct x86_emulate_ops *ops,
2142 u16 tss_selector, u16 old_tss_sel,
2143 ulong old_tss_base, struct desc_struct *new_desc)
2144{
2145 struct tss_segment_32 tss_seg;
2146 int ret;
bcc55cba 2147 u32 new_tss_base = get_desc_base(new_desc);
38ba30ba
GN		 2148
2149 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
bcc55cba 2150 &ctxt->exception);
db297e3d 2151 if (ret != X86EMUL_CONTINUE)
38ba30ba 2152 /* FIXME: need to provide precise fault address */
38ba30ba 2153 return ret;
38ba30ba
GN		 2154
2155 save_state_to_tss32(ctxt, ops, &tss_seg);
2156
2157 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
bcc55cba 2158 &ctxt->exception);
db297e3d 2159 if (ret != X86EMUL_CONTINUE)
38ba30ba 2160 /* FIXME: need to provide precise fault address */
38ba30ba 2161 return ret;
38ba30ba
GN		 2162
2163 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
bcc55cba 2164 &ctxt->exception);
db297e3d 2165 if (ret != X86EMUL_CONTINUE)
38ba30ba 2166 /* FIXME: need to provide precise fault address */
38ba30ba 2167 return ret;
38ba30ba
GN		 2168
2169 if (old_tss_sel != 0xffff) {
2170 tss_seg.prev_task_link = old_tss_sel;
2171
2172 ret = ops->write_std(new_tss_base,
2173 &tss_seg.prev_task_link,
2174 sizeof tss_seg.prev_task_link,
bcc55cba 2175 ctxt->vcpu, &ctxt->exception);
db297e3d 2176 if (ret != X86EMUL_CONTINUE)
38ba30ba 2177 /* FIXME: need to provide precise fault address */
38ba30ba 2178 return ret;
38ba30ba
GN		 2179 }
2180
2181 return load_state_from_tss32(ctxt, ops, &tss_seg);
2182}
2183
2184static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 2185 struct x86_emulate_ops *ops,
2186 u16 tss_selector, int reason,
2187 bool has_error_code, u32 error_code)
38ba30ba
GN		 2188{
2189 struct desc_struct curr_tss_desc, next_tss_desc;
2190 int ret;
2191 u16 old_tss_sel = ops->get_segment_selector(VCPU_SREG_TR, ctxt->vcpu);
2192 ulong old_tss_base =
5951c442 2193 ops->get_cached_segment_base(VCPU_SREG_TR, ctxt->vcpu);
ceffb459 2194 u32 desc_limit;
38ba30ba
GN		 2195
2196 /* FIXME: old_tss_base == ~0 ? */
2197
2198 ret = read_segment_descriptor(ctxt, ops, tss_selector, &next_tss_desc);
2199 if (ret != X86EMUL_CONTINUE)
2200 return ret;
2201 ret = read_segment_descriptor(ctxt, ops, old_tss_sel, &curr_tss_desc);
2202 if (ret != X86EMUL_CONTINUE)
2203 return ret;
2204
2205 /* FIXME: check that next_tss_desc is tss */
2206
2207 if (reason != TASK_SWITCH_IRET) {
2208 if ((tss_selector & 3) > next_tss_desc.dpl ||
35d3d4a1
AK		 2209 ops->cpl(ctxt->vcpu) > next_tss_desc.dpl)
2210 return emulate_gp(ctxt, 0);
38ba30ba
GN		 2211 }
2212
ceffb459
GN		 2213 desc_limit = desc_limit_scaled(&next_tss_desc);
2214 if (!next_tss_desc.p ||
2215 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2216 desc_limit < 0x2b)) {
54b8486f 2217 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 2218 return X86EMUL_PROPAGATE_FAULT;
2219 }
2220
2221 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2222 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
2223 write_segment_descriptor(ctxt, ops, old_tss_sel,
2224 &curr_tss_desc);
2225 }
2226
2227 if (reason == TASK_SWITCH_IRET)
2228 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2229
2230 /* set back link to prev task only if NT bit is set in eflags
2231 note that old_tss_sel is not used afetr this point */
2232 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2233 old_tss_sel = 0xffff;
2234
2235 if (next_tss_desc.type & 8)
2236 ret = task_switch_32(ctxt, ops, tss_selector, old_tss_sel,
2237 old_tss_base, &next_tss_desc);
2238 else
2239 ret = task_switch_16(ctxt, ops, tss_selector, old_tss_sel,
2240 old_tss_base, &next_tss_desc);
0760d448
JK		 2241 if (ret != X86EMUL_CONTINUE)
2242 return ret;
38ba30ba
GN		 2243
2244 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2245 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2246
2247 if (reason != TASK_SWITCH_IRET) {
2248 next_tss_desc.type |= (1 << 1); /* set busy flag */
2249 write_segment_descriptor(ctxt, ops, tss_selector,
2250 &next_tss_desc);
2251 }
2252
2253 ops->set_cr(0, ops->get_cr(0, ctxt->vcpu) | X86_CR0_TS, ctxt->vcpu);
5601d05b 2254 ops->set_cached_descriptor(&next_tss_desc, 0, VCPU_SREG_TR, ctxt->vcpu);
38ba30ba
GN		 2255 ops->set_segment_selector(tss_selector, VCPU_SREG_TR, ctxt->vcpu);
2256
e269fb21
JK		 2257 if (has_error_code) {
2258 struct decode_cache *c = &ctxt->decode;
2259
2260 c->op_bytes = c->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2261 c->lock_prefix = 0;
2262 c->src.val = (unsigned long) error_code;
79168fd1 2263 emulate_push(ctxt, ops);
e269fb21
JK		 2264 }
2265
38ba30ba
GN		 2266 return ret;
2267}
2268
2269int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 2270 u16 tss_selector, int reason,
2271 bool has_error_code, u32 error_code)
38ba30ba 2272{
9aabc88f 2273 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 2274 struct decode_cache *c = &ctxt->decode;
2275 int rc;
2276
38ba30ba 2277 c->eip = ctxt->eip;
e269fb21 2278 c->dst.type = OP_NONE;
38ba30ba 2279
e269fb21
JK		 2280 rc = emulator_do_task_switch(ctxt, ops, tss_selector, reason,
2281 has_error_code, error_code);
38ba30ba
GN		 2282
2283 if (rc == X86EMUL_CONTINUE) {
e269fb21 2284 rc = writeback(ctxt, ops);
95c55886
GN		 2285 if (rc == X86EMUL_CONTINUE)
2286 ctxt->eip = c->eip;
38ba30ba
GN		 2287 }
2288
19d04437 2289 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
38ba30ba
GN		 2290}
2291
90de84f5 2292static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned seg,
d9271123 2293 int reg, struct operand *op)
a682e354
GN		 2294{
2295 struct decode_cache *c = &ctxt->decode;
2296 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
2297
d9271123 2298 register_address_increment(c, &c->regs[reg], df * op->bytes);
90de84f5
AK		 2299 op->addr.mem.ea = register_address(c, c->regs[reg]);
2300 op->addr.mem.seg = seg;
a682e354
GN		 2301}
2302
63540382
AK		 2303static int em_push(struct x86_emulate_ctxt *ctxt)
2304{
2305 emulate_push(ctxt, ctxt->ops);
2306 return X86EMUL_CONTINUE;
2307}
2308
7af04fc0
AK		 2309static int em_das(struct x86_emulate_ctxt *ctxt)
2310{
2311 struct decode_cache *c = &ctxt->decode;
2312 u8 al, old_al;
2313 bool af, cf, old_cf;
2314
2315 cf = ctxt->eflags & X86_EFLAGS_CF;
2316 al = c->dst.val;
2317
2318 old_al = al;
2319 old_cf = cf;
2320 cf = false;
2321 af = ctxt->eflags & X86_EFLAGS_AF;
2322 if ((al & 0x0f) > 9 || af) {
2323 al -= 6;
2324 cf = old_cf | (al >= 250);
2325 af = true;
2326 } else {
2327 af = false;
2328 }
2329 if (old_al > 0x99 || old_cf) {
2330 al -= 0x60;
2331 cf = true;
2332 }
2333
2334 c->dst.val = al;
2335 /* Set PF, ZF, SF */
2336 c->src.type = OP_IMM;
2337 c->src.val = 0;
2338 c->src.bytes = 1;
2339 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
2340 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2341 if (cf)
2342 ctxt->eflags |= X86_EFLAGS_CF;
2343 if (af)
2344 ctxt->eflags |= X86_EFLAGS_AF;
2345 return X86EMUL_CONTINUE;
2346}
2347
0ef753b8
AK		 2348static int em_call_far(struct x86_emulate_ctxt *ctxt)
2349{
2350 struct decode_cache *c = &ctxt->decode;
2351 u16 sel, old_cs;
2352 ulong old_eip;
2353 int rc;
2354
2355 old_cs = ctxt->ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
2356 old_eip = c->eip;
2357
2358 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
2359 if (load_segment_descriptor(ctxt, ctxt->ops, sel, VCPU_SREG_CS))
2360 return X86EMUL_CONTINUE;
2361
2362 c->eip = 0;
2363 memcpy(&c->eip, c->src.valptr, c->op_bytes);
2364
2365 c->src.val = old_cs;
2366 emulate_push(ctxt, ctxt->ops);
2367 rc = writeback(ctxt, ctxt->ops);
2368 if (rc != X86EMUL_CONTINUE)
2369 return rc;
2370
2371 c->src.val = old_eip;
2372 emulate_push(ctxt, ctxt->ops);
2373 rc = writeback(ctxt, ctxt->ops);
2374 if (rc != X86EMUL_CONTINUE)
2375 return rc;
2376
2377 c->dst.type = OP_NONE;
2378
2379 return X86EMUL_CONTINUE;
2380}
2381
40ece7c7
AK		 2382static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
2383{
2384 struct decode_cache *c = &ctxt->decode;
2385 int rc;
2386
2387 c->dst.type = OP_REG;
2388 c->dst.addr.reg = &c->eip;
2389 c->dst.bytes = c->op_bytes;
2390 rc = emulate_pop(ctxt, ctxt->ops, &c->dst.val, c->op_bytes);
2391 if (rc != X86EMUL_CONTINUE)
2392 return rc;
2393 register_address_increment(c, &c->regs[VCPU_REGS_RSP], c->src.val);
2394 return X86EMUL_CONTINUE;
2395}
2396
5c82aa29 2397static int em_imul(struct x86_emulate_ctxt *ctxt)
f3a1b9f4
AK		 2398{
2399 struct decode_cache *c = &ctxt->decode;
2400
f3a1b9f4
AK		 2401 emulate_2op_SrcV_nobyte("imul", c->src, c->dst, ctxt->eflags);
2402 return X86EMUL_CONTINUE;
2403}
2404
5c82aa29
AK		 2405static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
2406{
2407 struct decode_cache *c = &ctxt->decode;
2408
2409 c->dst.val = c->src2.val;
2410 return em_imul(ctxt);
2411}
2412
61429142
AK		 2413static int em_cwd(struct x86_emulate_ctxt *ctxt)
2414{
2415 struct decode_cache *c = &ctxt->decode;
2416
2417 c->dst.type = OP_REG;
2418 c->dst.bytes = c->src.bytes;
2419 c->dst.addr.reg = &c->regs[VCPU_REGS_RDX];
2420 c->dst.val = ~((c->src.val >> (c->src.bytes * 8 - 1)) - 1);
2421
2422 return X86EMUL_CONTINUE;
2423}
2424
48bb5d3c
AK		 2425static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
2426{
2427 unsigned cpl = ctxt->ops->cpl(ctxt->vcpu);
2428 struct decode_cache *c = &ctxt->decode;
2429 u64 tsc = 0;
2430
35d3d4a1
AK		 2431 if (cpl > 0 && (ctxt->ops->get_cr(4, ctxt->vcpu) & X86_CR4_TSD))
2432 return emulate_gp(ctxt, 0);
48bb5d3c
AK		 2433 ctxt->ops->get_msr(ctxt->vcpu, MSR_IA32_TSC, &tsc);
2434 c->regs[VCPU_REGS_RAX] = (u32)tsc;
2435 c->regs[VCPU_REGS_RDX] = tsc >> 32;
2436 return X86EMUL_CONTINUE;
2437}
2438
b9eac5f4
AK		 2439static int em_mov(struct x86_emulate_ctxt *ctxt)
2440{
2441 struct decode_cache *c = &ctxt->decode;
2442 c->dst.val = c->src.val;
2443 return X86EMUL_CONTINUE;
2444}
2445
aa97bb48
AK		 2446static int em_movdqu(struct x86_emulate_ctxt *ctxt)
2447{
2448 struct decode_cache *c = &ctxt->decode;
2449 memcpy(&c->dst.vec_val, &c->src.vec_val, c->op_bytes);
2450 return X86EMUL_CONTINUE;
2451}
2452
cfec82cb
JR		 2453static bool valid_cr(int nr)
2454{
2455 switch (nr) {
2456 case 0:
2457 case 2 ... 4:
2458 case 8:
2459 return true;
2460 default:
2461 return false;
2462 }
2463}
2464
2465static int check_cr_read(struct x86_emulate_ctxt *ctxt)
2466{
2467 struct decode_cache *c = &ctxt->decode;
2468
2469 if (!valid_cr(c->modrm_reg))
2470 return emulate_ud(ctxt);
2471
2472 return X86EMUL_CONTINUE;
2473}
2474
2475static int check_cr_write(struct x86_emulate_ctxt *ctxt)
2476{
2477 struct decode_cache *c = &ctxt->decode;
2478 u64 new_val = c->src.val64;
2479 int cr = c->modrm_reg;
2480
2481 static u64 cr_reserved_bits[] = {
2482 0xffffffff00000000ULL,
2483 0, 0, 0, /* CR3 checked later */
2484 CR4_RESERVED_BITS,
2485 0, 0, 0,
2486 CR8_RESERVED_BITS,
2487 };
2488
2489 if (!valid_cr(cr))
2490 return emulate_ud(ctxt);
2491
2492 if (new_val & cr_reserved_bits[cr])
2493 return emulate_gp(ctxt, 0);
2494
2495 switch (cr) {
2496 case 0: {
2497 u64 cr4, efer;
2498 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
2499 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
2500 return emulate_gp(ctxt, 0);
2501
2502 cr4 = ctxt->ops->get_cr(4, ctxt->vcpu);
2503 ctxt->ops->get_msr(ctxt->vcpu, MSR_EFER, &efer);
2504
2505 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
2506 !(cr4 & X86_CR4_PAE))
2507 return emulate_gp(ctxt, 0);
2508
2509 break;
2510 }
2511 case 3: {
2512 u64 rsvd = 0;
2513
2514 if (is_long_mode(ctxt->vcpu))
2515 rsvd = CR3_L_MODE_RESERVED_BITS;
2516 else if (is_pae(ctxt->vcpu))
2517 rsvd = CR3_PAE_RESERVED_BITS;
2518 else if (is_paging(ctxt->vcpu))
2519 rsvd = CR3_NONPAE_RESERVED_BITS;
2520
2521 if (new_val & rsvd)
2522 return emulate_gp(ctxt, 0);
2523
2524 break;
2525 }
2526 case 4: {
2527 u64 cr4, efer;
2528
2529 cr4 = ctxt->ops->get_cr(4, ctxt->vcpu);
2530 ctxt->ops->get_msr(ctxt->vcpu, MSR_EFER, &efer);
2531
2532 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
2533 return emulate_gp(ctxt, 0);
2534
2535 break;
2536 }
2537 }
2538
2539 return X86EMUL_CONTINUE;
2540}
2541
3b88e41a
JR		 2542static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
2543{
2544 unsigned long dr7;
2545
2546 ctxt->ops->get_dr(7, &dr7, ctxt->vcpu);
2547
2548 /* Check if DR7.Global_Enable is set */
2549 return dr7 & (1 << 13);
2550}
2551
2552static int check_dr_read(struct x86_emulate_ctxt *ctxt)
2553{
2554 struct decode_cache *c = &ctxt->decode;
2555 int dr = c->modrm_reg;
2556 u64 cr4;
2557
2558 if (dr > 7)
2559 return emulate_ud(ctxt);
2560
2561 cr4 = ctxt->ops->get_cr(4, ctxt->vcpu);
2562 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
2563 return emulate_ud(ctxt);
2564
2565 if (check_dr7_gd(ctxt))
2566 return emulate_db(ctxt);
2567
2568 return X86EMUL_CONTINUE;
2569}
2570
2571static int check_dr_write(struct x86_emulate_ctxt *ctxt)
2572{
2573 struct decode_cache *c = &ctxt->decode;
2574 u64 new_val = c->src.val64;
2575 int dr = c->modrm_reg;
2576
2577 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
2578 return emulate_gp(ctxt, 0);
2579
2580 return check_dr_read(ctxt);
2581}
2582
73fba5f4 2583#define D(_y) { .flags = (_y) }
c4f035c6 2584#define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i }
d09beabd
JR		 2585#define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \
2586 .check_perm = (_p) }
73fba5f4
AK		 2587#define N D(0)
2588#define G(_f, _g) { .flags = ((_f) | Group), .u.group = (_g) }
2589#define GD(_f, _g) { .flags = ((_f) | Group | GroupDual), .u.gdual = (_g) }
2590#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
c4f035c6
AK		 2591#define II(_f, _e, _i) \
2592 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i }
d09beabd
JR		 2593#define IIP(_f, _e, _i, _p) \
2594 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \
2595 .check_perm = (_p) }
aa97bb48 2596#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
73fba5f4 2597
8d8f4e9f
AK		 2598#define D2bv(_f) D((_f) | ByteOp), D(_f)
2599#define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
2600
6230f7fc
AK		 2601#define D6ALU(_f) D2bv((_f) | DstMem | SrcReg | ModRM), \
2602 D2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock), \
2603 D2bv(((_f) & ~Lock) | DstAcc | SrcImm)
2604
2605
73fba5f4
AK		 2606static struct opcode group1[] = {
2607 X7(D(Lock)), N
2608};
2609
2610static struct opcode group1A[] = {
2611 D(DstMem | SrcNone | ModRM | Mov | Stack), N, N, N, N, N, N, N,
2612};
2613
2614static struct opcode group3[] = {
2615 D(DstMem | SrcImm | ModRM), D(DstMem | SrcImm | ModRM),
2616 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
3f9f53b0 2617 X4(D(SrcMem | ModRM)),
73fba5f4
AK		 2618};
2619
2620static struct opcode group4[] = {
2621 D(ByteOp | DstMem | SrcNone | ModRM | Lock), D(ByteOp | DstMem | SrcNone | ModRM | Lock),
2622 N, N, N, N, N, N,
2623};
2624
2625static struct opcode group5[] = {
2626 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
0ef753b8
AK		 2627 D(SrcMem | ModRM | Stack),
2628 I(SrcMemFAddr | ModRM | ImplicitOps | Stack, em_call_far),
73fba5f4
AK		 2629 D(SrcMem | ModRM | Stack), D(SrcMemFAddr | ModRM | ImplicitOps),
2630 D(SrcMem | ModRM | Stack), N,
2631};
2632
dee6bb70
JR		 2633static struct opcode group6[] = {
2634 DI(ModRM | Prot, sldt),
2635 DI(ModRM | Prot, str),
2636 DI(ModRM | Prot | Priv, lldt),
2637 DI(ModRM | Prot | Priv, ltr),
2638 N, N, N, N,
2639};
2640
73fba5f4 2641static struct group_dual group7 = { {
dee6bb70
JR		 2642 DI(ModRM | Mov | DstMem | Priv, sgdt),
2643 DI(ModRM | Mov | DstMem | Priv, sidt),
2644 DI(ModRM | SrcMem | Priv, lgdt), DI(ModRM | SrcMem | Priv, lidt),
3c6e276f
AK		 2645 DI(SrcNone | ModRM | DstMem | Mov, smsw), N,
2646 DI(SrcMem16 | ModRM | Mov | Priv, lmsw),
2647 DI(SrcMem | ModRM | ByteOp | Priv | NoAccess, invlpg),
73fba5f4 2648}, {
d867162c
AK		 2649 D(SrcNone | ModRM | Priv | VendorSpecific), N,
2650 N, D(SrcNone | ModRM | Priv | VendorSpecific),
3c6e276f
AK		 2651 DI(SrcNone | ModRM | DstMem | Mov, smsw), N,
2652 DI(SrcMem16 | ModRM | Mov | Priv, lmsw), N,
73fba5f4
AK		 2653} };
2654
2655static struct opcode group8[] = {
2656 N, N, N, N,
2657 D(DstMem | SrcImmByte | ModRM), D(DstMem | SrcImmByte | ModRM | Lock),
2658 D(DstMem | SrcImmByte | ModRM | Lock), D(DstMem | SrcImmByte | ModRM | Lock),
2659};
2660
2661static struct group_dual group9 = { {
2662 N, D(DstMem64 | ModRM | Lock), N, N, N, N, N, N,
2663}, {
2664 N, N, N, N, N, N, N, N,
2665} };
2666
a4d4a7c1
AK		 2667static struct opcode group11[] = {
2668 I(DstMem | SrcImm | ModRM | Mov, em_mov), X7(D(Undefined)),
2669};
2670
aa97bb48
AK		 2671static struct gprefix pfx_0f_6f_0f_7f = {
2672 N, N, N, I(Sse, em_movdqu),
2673};
2674
73fba5f4
AK		 2675static struct opcode opcode_table[256] = {
2676 /* 0x00 - 0x07 */
6230f7fc 2677 D6ALU(Lock),
73fba5f4
AK		 2678 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2679 /* 0x08 - 0x0F */
6230f7fc 2680 D6ALU(Lock),
73fba5f4
AK		 2681 D(ImplicitOps | Stack | No64), N,
2682 /* 0x10 - 0x17 */
6230f7fc 2683 D6ALU(Lock),
73fba5f4
AK		 2684 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2685 /* 0x18 - 0x1F */
6230f7fc 2686 D6ALU(Lock),
73fba5f4
AK		 2687 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2688 /* 0x20 - 0x27 */
6230f7fc 2689 D6ALU(Lock), N, N,
73fba5f4 2690 /* 0x28 - 0x2F */
6230f7fc 2691 D6ALU(Lock), N, I(ByteOp | DstAcc | No64, em_das),
73fba5f4 2692 /* 0x30 - 0x37 */
6230f7fc 2693 D6ALU(Lock), N, N,
73fba5f4 2694 /* 0x38 - 0x3F */
6230f7fc 2695 D6ALU(0), N, N,
73fba5f4
AK		 2696 /* 0x40 - 0x4F */
2697 X16(D(DstReg)),
2698 /* 0x50 - 0x57 */
63540382 2699 X8(I(SrcReg | Stack, em_push)),
73fba5f4
AK		 2700 /* 0x58 - 0x5F */
2701 X8(D(DstReg | Stack)),
2702 /* 0x60 - 0x67 */
2703 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2704 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
2705 N, N, N, N,
2706 /* 0x68 - 0x6F */
d46164db
AK		 2707 I(SrcImm | Mov | Stack, em_push),
2708 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
f3a1b9f4
AK		 2709 I(SrcImmByte | Mov | Stack, em_push),
2710 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
48fe67b5
AK		 2711 D2bv(DstDI | Mov | String), /* insb, insw/insd */
2712 D2bv(SrcSI | ImplicitOps | String), /* outsb, outsw/outsd */
73fba5f4
AK		 2713 /* 0x70 - 0x7F */
2714 X16(D(SrcImmByte)),
2715 /* 0x80 - 0x87 */
2716 G(ByteOp | DstMem | SrcImm | ModRM | Group, group1),
2717 G(DstMem | SrcImm | ModRM | Group, group1),
2718 G(ByteOp | DstMem | SrcImm | ModRM | No64 | Group, group1),
2719 G(DstMem | SrcImmByte | ModRM | Group, group1),
76e8e68d 2720 D2bv(DstMem | SrcReg | ModRM), D2bv(DstMem | SrcReg | ModRM | Lock),
73fba5f4 2721 /* 0x88 - 0x8F */
b9eac5f4
AK		 2722 I2bv(DstMem | SrcReg | ModRM | Mov, em_mov),
2723 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
342fc630 2724 D(DstMem | SrcNone | ModRM | Mov), D(ModRM | SrcMem | NoAccess | DstReg),
73fba5f4
AK		 2725 D(ImplicitOps | SrcMem16 | ModRM), G(0, group1A),
2726 /* 0x90 - 0x97 */
3d9e77df 2727 X8(D(SrcAcc | DstReg)),
73fba5f4 2728 /* 0x98 - 0x9F */
61429142 2729 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
cc4feed5 2730 I(SrcImmFAddr | No64, em_call_far), N,
3c6e276f 2731 DI(ImplicitOps | Stack, pushf), DI(ImplicitOps | Stack, popf), N, N,
73fba5f4 2732 /* 0xA0 - 0xA7 */
b9eac5f4
AK		 2733 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
2734 I2bv(DstMem | SrcAcc | Mov | MemAbs, em_mov),
2735 I2bv(SrcSI | DstDI | Mov | String, em_mov),
2736 D2bv(SrcSI | DstDI | String),
73fba5f4 2737 /* 0xA8 - 0xAF */
50748613 2738 D2bv(DstAcc | SrcImm),
b9eac5f4
AK		 2739 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
2740 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
48fe67b5 2741 D2bv(SrcAcc | DstDI | String),
73fba5f4 2742 /* 0xB0 - 0xB7 */
b9eac5f4 2743 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
73fba5f4 2744 /* 0xB8 - 0xBF */
b9eac5f4 2745 X8(I(DstReg | SrcImm | Mov, em_mov)),
73fba5f4 2746 /* 0xC0 - 0xC7 */
d2c6c7ad 2747 D2bv(DstMem | SrcImmByte | ModRM),
40ece7c7
AK		 2748 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
2749 D(ImplicitOps | Stack),
09b5f4d3 2750 D(DstReg | SrcMemFAddr | ModRM | No64), D(DstReg | SrcMemFAddr | ModRM | No64),
a4d4a7c1 2751 G(ByteOp, group11), G(0, group11),
73fba5f4
AK		 2752 /* 0xC8 - 0xCF */
2753 N, N, N, D(ImplicitOps | Stack),
3c6e276f
AK		 2754 D(ImplicitOps), DI(SrcImmByte, intn),
2755 D(ImplicitOps | No64), DI(ImplicitOps, iret),
73fba5f4 2756 /* 0xD0 - 0xD7 */
d2c6c7ad 2757 D2bv(DstMem | SrcOne | ModRM), D2bv(DstMem | ModRM),
73fba5f4
AK		 2758 N, N, N, N,
2759 /* 0xD8 - 0xDF */
2760 N, N, N, N, N, N, N, N,
2761 /* 0xE0 - 0xE7 */
e4abac67 2762 X4(D(SrcImmByte)),
d269e396 2763 D2bv(SrcImmUByte | DstAcc), D2bv(SrcAcc | DstImmUByte),
73fba5f4
AK		 2764 /* 0xE8 - 0xEF */
2765 D(SrcImm | Stack), D(SrcImm | ImplicitOps),
2766 D(SrcImmFAddr | No64), D(SrcImmByte | ImplicitOps),
d269e396 2767 D2bv(SrcNone | DstAcc), D2bv(SrcAcc | ImplicitOps),
73fba5f4
AK		 2768 /* 0xF0 - 0xF7 */
2769 N, N, N, N,
3c6e276f
AK		 2770 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
2771 G(ByteOp, group3), G(0, group3),
73fba5f4 2772 /* 0xF8 - 0xFF */
8744aa9a 2773 D(ImplicitOps), D(ImplicitOps), D(ImplicitOps), D(ImplicitOps),
73fba5f4
AK		 2774 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
2775};
2776
2777static struct opcode twobyte_table[256] = {
2778 /* 0x00 - 0x0F */
dee6bb70 2779 G(0, group6), GD(0, &group7), N, N,
cfec82cb 2780 N, D(ImplicitOps | VendorSpecific), DI(ImplicitOps | Priv, clts), N,
3c6e276f 2781 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
73fba5f4
AK		 2782 N, D(ImplicitOps | ModRM), N, N,
2783 /* 0x10 - 0x1F */
2784 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
2785 /* 0x20 - 0x2F */
cfec82cb 2786 DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read),
3b88e41a 2787 DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read),
cfec82cb 2788 DIP(ModRM | SrcMem | Priv | Op3264, cr_write, check_cr_write),
3b88e41a 2789 DIP(ModRM | SrcMem | Priv | Op3264, dr_write, check_dr_write),
73fba5f4
AK		 2790 N, N, N, N,
2791 N, N, N, N, N, N, N, N,
2792 /* 0x30 - 0x3F */
3c6e276f 2793 D(ImplicitOps | Priv), II(ImplicitOps, em_rdtsc, rdtsc),
48bb5d3c 2794 D(ImplicitOps | Priv), N,
d867162c
AK		 2795 D(ImplicitOps | VendorSpecific), D(ImplicitOps | Priv | VendorSpecific),
2796 N, N,
73fba5f4
AK		 2797 N, N, N, N, N, N, N, N,
2798 /* 0x40 - 0x4F */
2799 X16(D(DstReg | SrcMem | ModRM | Mov)),
2800 /* 0x50 - 0x5F */
2801 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2802 /* 0x60 - 0x6F */
aa97bb48
AK		 2803 N, N, N, N,
2804 N, N, N, N,
2805 N, N, N, N,
2806 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4 2807 /* 0x70 - 0x7F */
aa97bb48
AK		 2808 N, N, N, N,
2809 N, N, N, N,
2810 N, N, N, N,
2811 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
73fba5f4
AK		 2812 /* 0x80 - 0x8F */
2813 X16(D(SrcImm)),
2814 /* 0x90 - 0x9F */
ee45b58e 2815 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
73fba5f4
AK		 2816 /* 0xA0 - 0xA7 */
2817 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
2818 N, D(DstMem | SrcReg | ModRM | BitOp),
2819 D(DstMem | SrcReg | Src2ImmByte | ModRM),
2820 D(DstMem | SrcReg | Src2CL | ModRM), N, N,
2821 /* 0xA8 - 0xAF */
2822 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
2823 N, D(DstMem | SrcReg | ModRM | BitOp | Lock),
2824 D(DstMem | SrcReg | Src2ImmByte | ModRM),
2825 D(DstMem | SrcReg | Src2CL | ModRM),
5c82aa29 2826 D(ModRM), I(DstReg | SrcMem | ModRM, em_imul),
73fba5f4 2827 /* 0xB0 - 0xB7 */
739ae406 2828 D2bv(DstMem | SrcReg | ModRM | Lock),
09b5f4d3
WY		 2829 D(DstReg | SrcMemFAddr | ModRM), D(DstMem | SrcReg | ModRM | BitOp | Lock),
2830 D(DstReg | SrcMemFAddr | ModRM), D(DstReg | SrcMemFAddr | ModRM),
2831 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4
AK		 2832 /* 0xB8 - 0xBF */
2833 N, N,
ba7ff2b7 2834 G(BitOp, group8), D(DstMem | SrcReg | ModRM | BitOp | Lock),
d9574a25
WY		 2835 D(DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2836 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
73fba5f4 2837 /* 0xC0 - 0xCF */
739ae406 2838 D2bv(DstMem | SrcReg | ModRM | Lock),
92f738a5 2839 N, D(DstMem | SrcReg | ModRM | Mov),
73fba5f4
AK		 2840 N, N, N, GD(0, &group9),
2841 N, N, N, N, N, N, N, N,
2842 /* 0xD0 - 0xDF */
2843 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2844 /* 0xE0 - 0xEF */
2845 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2846 /* 0xF0 - 0xFF */
2847 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
2848};
2849
2850#undef D
2851#undef N
2852#undef G
2853#undef GD
2854#undef I
aa97bb48 2855#undef GP
73fba5f4 2856
8d8f4e9f
AK		 2857#undef D2bv
2858#undef I2bv
6230f7fc 2859#undef D6ALU
8d8f4e9f 2860
39f21ee5
AK		 2861static unsigned imm_size(struct decode_cache *c)
2862{
2863 unsigned size;
2864
2865 size = (c->d & ByteOp) ? 1 : c->op_bytes;
2866 if (size == 8)
2867 size = 4;
2868 return size;
2869}
2870
2871static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
2872 unsigned size, bool sign_extension)
2873{
2874 struct decode_cache *c = &ctxt->decode;
2875 struct x86_emulate_ops *ops = ctxt->ops;
2876 int rc = X86EMUL_CONTINUE;
2877
2878 op->type = OP_IMM;
2879 op->bytes = size;
90de84f5 2880 op->addr.mem.ea = c->eip;
39f21ee5
AK		 2881 /* NB. Immediates are sign-extended as necessary. */
2882 switch (op->bytes) {
2883 case 1:
2884 op->val = insn_fetch(s8, 1, c->eip);
2885 break;
2886 case 2:
2887 op->val = insn_fetch(s16, 2, c->eip);
2888 break;
2889 case 4:
2890 op->val = insn_fetch(s32, 4, c->eip);
2891 break;
2892 }
2893 if (!sign_extension) {
2894 switch (op->bytes) {
2895 case 1:
2896 op->val &= 0xff;
2897 break;
2898 case 2:
2899 op->val &= 0xffff;
2900 break;
2901 case 4:
2902 op->val &= 0xffffffff;
2903 break;
2904 }
2905 }
2906done:
2907 return rc;
2908}
2909
dde7e6d1 2910int
dc25e89e 2911x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
dde7e6d1
AK		 2912{
2913 struct x86_emulate_ops *ops = ctxt->ops;
2914 struct decode_cache *c = &ctxt->decode;
2915 int rc = X86EMUL_CONTINUE;
2916 int mode = ctxt->mode;
0d7cdee8
AK		 2917 int def_op_bytes, def_ad_bytes, dual, goffset, simd_prefix;
2918 bool op_prefix = false;
dde7e6d1 2919 struct opcode opcode, *g_mod012, *g_mod3;
2dbd0dd7 2920 struct operand memop = { .type = OP_NONE };
dde7e6d1 2921
dde7e6d1 2922 c->eip = ctxt->eip;
dc25e89e
AP		 2923 c->fetch.start = c->eip;
2924 c->fetch.end = c->fetch.start + insn_len;
2925 if (insn_len > 0)
2926 memcpy(c->fetch.data, insn, insn_len);
dde7e6d1
AK		 2927 ctxt->cs_base = seg_base(ctxt, ops, VCPU_SREG_CS);
2928
2929 switch (mode) {
2930 case X86EMUL_MODE_REAL:
2931 case X86EMUL_MODE_VM86:
2932 case X86EMUL_MODE_PROT16:
2933 def_op_bytes = def_ad_bytes = 2;
2934 break;
2935 case X86EMUL_MODE_PROT32:
2936 def_op_bytes = def_ad_bytes = 4;
2937 break;
2938#ifdef CONFIG_X86_64
2939 case X86EMUL_MODE_PROT64:
2940 def_op_bytes = 4;
2941 def_ad_bytes = 8;
2942 break;
2943#endif
2944 default:
2945 return -1;
2946 }
2947
2948 c->op_bytes = def_op_bytes;
2949 c->ad_bytes = def_ad_bytes;
2950
2951 /* Legacy prefixes. */
2952 for (;;) {
2953 switch (c->b = insn_fetch(u8, 1, c->eip)) {
2954 case 0x66: /* operand-size override */
0d7cdee8 2955 op_prefix = true;
dde7e6d1
AK		 2956 /* switch between 2/4 bytes */
2957 c->op_bytes = def_op_bytes ^ 6;
2958 break;
2959 case 0x67: /* address-size override */
2960 if (mode == X86EMUL_MODE_PROT64)
2961 /* switch between 4/8 bytes */
2962 c->ad_bytes = def_ad_bytes ^ 12;
2963 else
2964 /* switch between 2/4 bytes */
2965 c->ad_bytes = def_ad_bytes ^ 6;
2966 break;
2967 case 0x26: /* ES override */
2968 case 0x2e: /* CS override */
2969 case 0x36: /* SS override */
2970 case 0x3e: /* DS override */
2971 set_seg_override(c, (c->b >> 3) & 3);
2972 break;
2973 case 0x64: /* FS override */
2974 case 0x65: /* GS override */
2975 set_seg_override(c, c->b & 7);
2976 break;
2977 case 0x40 ... 0x4f: /* REX */
2978 if (mode != X86EMUL_MODE_PROT64)
2979 goto done_prefixes;
2980 c->rex_prefix = c->b;
2981 continue;
2982 case 0xf0: /* LOCK */
2983 c->lock_prefix = 1;
2984 break;
2985 case 0xf2: /* REPNE/REPNZ */
dde7e6d1 2986 case 0xf3: /* REP/REPE/REPZ */
1d6b114f 2987 c->rep_prefix = c->b;
dde7e6d1
AK		 2988 break;
2989 default:
2990 goto done_prefixes;
2991 }
2992
2993 /* Any legacy prefix after a REX prefix nullifies its effect. */
2994
2995 c->rex_prefix = 0;
2996 }
2997
2998done_prefixes:
2999
3000 /* REX prefix. */
1e87e3ef
AK		 3001 if (c->rex_prefix & 8)
3002 c->op_bytes = 8; /* REX.W */
dde7e6d1
AK		 3003
3004 /* Opcode byte(s). */
3005 opcode = opcode_table[c->b];
d3ad6243
WY		 3006 /* Two-byte opcode? */
3007 if (c->b == 0x0f) {
3008 c->twobyte = 1;
3009 c->b = insn_fetch(u8, 1, c->eip);
3010 opcode = twobyte_table[c->b];
dde7e6d1
AK		 3011 }
3012 c->d = opcode.flags;
3013
3014 if (c->d & Group) {
3015 dual = c->d & GroupDual;
3016 c->modrm = insn_fetch(u8, 1, c->eip);
3017 --c->eip;
3018
3019 if (c->d & GroupDual) {
3020 g_mod012 = opcode.u.gdual->mod012;
3021 g_mod3 = opcode.u.gdual->mod3;
3022 } else
3023 g_mod012 = g_mod3 = opcode.u.group;
3024
3025 c->d &= ~(Group | GroupDual);
3026
3027 goffset = (c->modrm >> 3) & 7;
3028
3029 if ((c->modrm >> 6) == 3)
3030 opcode = g_mod3[goffset];
3031 else
3032 opcode = g_mod012[goffset];
3033 c->d |= opcode.flags;
3034 }
3035
0d7cdee8
AK		 3036 if (c->d & Prefix) {
3037 if (c->rep_prefix && op_prefix)
3038 return X86EMUL_UNHANDLEABLE;
3039 simd_prefix = op_prefix ? 0x66 : c->rep_prefix;
3040 switch (simd_prefix) {
3041 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
3042 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
3043 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
3044 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
3045 }
3046 c->d |= opcode.flags;
3047 }
3048
dde7e6d1 3049 c->execute = opcode.u.execute;
d09beabd 3050 c->check_perm = opcode.check_perm;
c4f035c6 3051 c->intercept = opcode.intercept;
dde7e6d1
AK		 3052
3053 /* Unrecognised? */
d53db5ef 3054 if (c->d == 0 || (c->d & Undefined))
dde7e6d1 3055 return -1;
dde7e6d1 3056
d867162c
AK		 3057 if (!(c->d & VendorSpecific) && ctxt->only_vendor_specific_insn)
3058 return -1;
3059
dde7e6d1
AK		 3060 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
3061 c->op_bytes = 8;
3062
7f9b4b75
AK		 3063 if (c->d & Op3264) {
3064 if (mode == X86EMUL_MODE_PROT64)
3065 c->op_bytes = 8;
3066 else
3067 c->op_bytes = 4;
3068 }
3069
1253791d
AK		 3070 if (c->d & Sse)
3071 c->op_bytes = 16;
3072
dde7e6d1 3073 /* ModRM and SIB bytes. */
09ee57cd 3074 if (c->d & ModRM) {
2dbd0dd7 3075 rc = decode_modrm(ctxt, ops, &memop);
09ee57cd
AK		 3076 if (!c->has_seg_override)
3077 set_seg_override(c, c->modrm_seg);
3078 } else if (c->d & MemAbs)
2dbd0dd7 3079 rc = decode_abs(ctxt, ops, &memop);
dde7e6d1
AK		 3080 if (rc != X86EMUL_CONTINUE)
3081 goto done;
3082
3083 if (!c->has_seg_override)
3084 set_seg_override(c, VCPU_SREG_DS);
3085
90de84f5 3086 memop.addr.mem.seg = seg_override(ctxt, ops, c);
dde7e6d1 3087
2dbd0dd7 3088 if (memop.type == OP_MEM && c->ad_bytes != 8)
90de84f5 3089 memop.addr.mem.ea = (u32)memop.addr.mem.ea;
dde7e6d1 3090
2dbd0dd7 3091 if (memop.type == OP_MEM && c->rip_relative)
90de84f5 3092 memop.addr.mem.ea += c->eip;
dde7e6d1
AK		 3093
3094 /*
3095 * Decode and fetch the source operand: register, memory
3096 * or immediate.
3097 */
3098 switch (c->d & SrcMask) {
3099 case SrcNone:
3100 break;
3101 case SrcReg:
1253791d 3102 decode_register_operand(ctxt, &c->src, c, 0);
dde7e6d1
AK		 3103 break;
3104 case SrcMem16:
2dbd0dd7 3105 memop.bytes = 2;
dde7e6d1
AK		 3106 goto srcmem_common;
3107 case SrcMem32:
2dbd0dd7 3108 memop.bytes = 4;
dde7e6d1
AK		 3109 goto srcmem_common;
3110 case SrcMem:
2dbd0dd7 3111 memop.bytes = (c->d & ByteOp) ? 1 :
dde7e6d1 3112 c->op_bytes;
dde7e6d1 3113 srcmem_common:
2dbd0dd7 3114 c->src = memop;
dde7e6d1 3115 break;
b250e605 3116 case SrcImmU16:
39f21ee5
AK		 3117 rc = decode_imm(ctxt, &c->src, 2, false);
3118 break;
dde7e6d1 3119 case SrcImm:
39f21ee5
AK		 3120 rc = decode_imm(ctxt, &c->src, imm_size(c), true);
3121 break;
dde7e6d1 3122 case SrcImmU:
39f21ee5 3123 rc = decode_imm(ctxt, &c->src, imm_size(c), false);
dde7e6d1
AK		 3124 break;
3125 case SrcImmByte:
39f21ee5
AK		 3126 rc = decode_imm(ctxt, &c->src, 1, true);
3127 break;
dde7e6d1 3128 case SrcImmUByte:
39f21ee5 3129 rc = decode_imm(ctxt, &c->src, 1, false);
dde7e6d1
AK		 3130 break;
3131 case SrcAcc:
3132 c->src.type = OP_REG;
3133 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1a6440ae 3134 c->src.addr.reg = &c->regs[VCPU_REGS_RAX];
91ff3cb4 3135 fetch_register_operand(&c->src);
dde7e6d1
AK		 3136 break;
3137 case SrcOne:
3138 c->src.bytes = 1;
3139 c->src.val = 1;
3140 break;
3141 case SrcSI:
3142 c->src.type = OP_MEM;
3143 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
90de84f5
AK		 3144 c->src.addr.mem.ea =
3145 register_address(c, c->regs[VCPU_REGS_RSI]);
3146 c->src.addr.mem.seg = seg_override(ctxt, ops, c),
dde7e6d1
AK		 3147 c->src.val = 0;
3148 break;
3149 case SrcImmFAddr:
3150 c->src.type = OP_IMM;
90de84f5 3151 c->src.addr.mem.ea = c->eip;
dde7e6d1
AK		 3152 c->src.bytes = c->op_bytes + 2;
3153 insn_fetch_arr(c->src.valptr, c->src.bytes, c->eip);
3154 break;
3155 case SrcMemFAddr:
2dbd0dd7
AK		 3156 memop.bytes = c->op_bytes + 2;
3157 goto srcmem_common;
dde7e6d1
AK		 3158 break;
3159 }
3160
39f21ee5
AK		 3161 if (rc != X86EMUL_CONTINUE)
3162 goto done;
3163
dde7e6d1
AK		 3164 /*
3165 * Decode and fetch the second source operand: register, memory
3166 * or immediate.
3167 */
3168 switch (c->d & Src2Mask) {
3169 case Src2None:
3170 break;
3171 case Src2CL:
3172 c->src2.bytes = 1;
3173 c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
3174 break;
3175 case Src2ImmByte:
39f21ee5 3176 rc = decode_imm(ctxt, &c->src2, 1, true);
dde7e6d1
AK		 3177 break;
3178 case Src2One:
3179 c->src2.bytes = 1;
3180 c->src2.val = 1;
3181 break;
7db41eb7
AK		 3182 case Src2Imm:
3183 rc = decode_imm(ctxt, &c->src2, imm_size(c), true);
3184 break;
dde7e6d1
AK		 3185 }
3186
39f21ee5
AK		 3187 if (rc != X86EMUL_CONTINUE)
3188 goto done;
3189
dde7e6d1
AK		 3190 /* Decode and fetch the destination operand: register or memory. */
3191 switch (c->d & DstMask) {
dde7e6d1 3192 case DstReg:
1253791d 3193 decode_register_operand(ctxt, &c->dst, c,
dde7e6d1
AK		 3194 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
3195 break;
943858e2
WY		 3196 case DstImmUByte:
3197 c->dst.type = OP_IMM;
90de84f5 3198 c->dst.addr.mem.ea = c->eip;
943858e2
WY		 3199 c->dst.bytes = 1;
3200 c->dst.val = insn_fetch(u8, 1, c->eip);
3201 break;
dde7e6d1
AK		 3202 case DstMem:
3203 case DstMem64:
2dbd0dd7 3204 c->dst = memop;
dde7e6d1
AK		 3205 if ((c->d & DstMask) == DstMem64)
3206 c->dst.bytes = 8;
3207 else
3208 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
35c843c4
WY		 3209 if (c->d & BitOp)
3210 fetch_bit_operand(c);
2dbd0dd7 3211 c->dst.orig_val = c->dst.val;
dde7e6d1
AK		 3212 break;
3213 case DstAcc:
3214 c->dst.type = OP_REG;
3215 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1a6440ae 3216 c->dst.addr.reg = &c->regs[VCPU_REGS_RAX];
91ff3cb4 3217 fetch_register_operand(&c->dst);
dde7e6d1
AK		 3218 c->dst.orig_val = c->dst.val;
3219 break;
3220 case DstDI:
3221 c->dst.type = OP_MEM;
3222 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
90de84f5
AK		 3223 c->dst.addr.mem.ea =
3224 register_address(c, c->regs[VCPU_REGS_RDI]);
3225 c->dst.addr.mem.seg = VCPU_SREG_ES;
dde7e6d1
AK		 3226 c->dst.val = 0;
3227 break;
36089fed
WY		 3228 case ImplicitOps:
3229 /* Special instructions do their own operand decoding. */
3230 default:
3231 c->dst.type = OP_NONE; /* Disable writeback. */
3232 return 0;
dde7e6d1
AK		 3233 }
3234
3235done:
3236 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
3237}
3238
3e2f65d5
GN		 3239static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
3240{
3241 struct decode_cache *c = &ctxt->decode;
3242
3243 /* The second termination condition only applies for REPE
3244 * and REPNE. Test if the repeat string operation prefix is
3245 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
3246 * corresponding termination condition according to:
3247 * - if REPE/REPZ and ZF = 0 then done
3248 * - if REPNE/REPNZ and ZF = 1 then done
3249 */
3250 if (((c->b == 0xa6) || (c->b == 0xa7) ||
3251 (c->b == 0xae) || (c->b == 0xaf))
3252 && (((c->rep_prefix == REPE_PREFIX) &&
3253 ((ctxt->eflags & EFLG_ZF) == 0))
3254 || ((c->rep_prefix == REPNE_PREFIX) &&
3255 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
3256 return true;
3257
3258 return false;
3259}
3260
8b4caf66 3261int
9aabc88f 3262x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 3263{
9aabc88f 3264 struct x86_emulate_ops *ops = ctxt->ops;
8b4caf66 3265 u64 msr_data;
8b4caf66 3266 struct decode_cache *c = &ctxt->decode;
1b30eaa8 3267 int rc = X86EMUL_CONTINUE;
5cd21917 3268 int saved_dst_type = c->dst.type;
6e154e56 3269 int irq; /* Used for int 3, int, and into */
8b4caf66 3270
9de41573 3271 ctxt->decode.mem_read.pos = 0;
310b5d30 3272
1161624f 3273 if (ctxt->mode == X86EMUL_MODE_PROT64 && (c->d & No64)) {
35d3d4a1 3274 rc = emulate_ud(ctxt);
1161624f
GN		 3275 goto done;
3276 }
3277
d380a5e4 3278 /* LOCK prefix is allowed only with some instructions */
a41ffb75 3279 if (c->lock_prefix && (!(c->d & Lock) || c->dst.type != OP_MEM)) {
35d3d4a1 3280 rc = emulate_ud(ctxt);
d380a5e4
GN		 3281 goto done;
3282 }
3283
081bca0e 3284 if ((c->d & SrcMask) == SrcMemFAddr && c->src.type != OP_MEM) {
35d3d4a1 3285 rc = emulate_ud(ctxt);
081bca0e
AK		 3286 goto done;
3287 }
3288
1253791d
AK		 3289 if ((c->d & Sse)
3290 && ((ops->get_cr(0, ctxt->vcpu) & X86_CR0_EM)
3291 || !(ops->get_cr(4, ctxt->vcpu) & X86_CR4_OSFXSR))) {
3292 rc = emulate_ud(ctxt);
3293 goto done;
3294 }
3295
3296 if ((c->d & Sse) && (ops->get_cr(0, ctxt->vcpu) & X86_CR0_TS)) {
3297 rc = emulate_nm(ctxt);
3298 goto done;
3299 }
3300
c4f035c6 3301 if (unlikely(ctxt->guest_mode) && c->intercept) {
8a76d7f2
JR		 3302 rc = emulator_check_intercept(ctxt, c->intercept,
3303 X86_ICPT_PRE_EXCEPT);
c4f035c6
AK		 3304 if (rc != X86EMUL_CONTINUE)
3305 goto done;
3306 }
3307
e92805ac 3308 /* Privileged instruction can be executed only in CPL=0 */
9c537244 3309 if ((c->d & Priv) && ops->cpl(ctxt->vcpu)) {
35d3d4a1 3310 rc = emulate_gp(ctxt, 0);
e92805ac
GN		 3311 goto done;
3312 }
3313
8ea7d6ae
JR		 3314 /* Instruction can only be executed in protected mode */
3315 if ((c->d & Prot) && !(ctxt->mode & X86EMUL_MODE_PROT)) {
3316 rc = emulate_ud(ctxt);
3317 goto done;
3318 }
3319
d09beabd
JR		 3320 /* Do instruction specific permission checks */
3321 if (c->check_perm) {
3322 rc = c->check_perm(ctxt);
3323 if (rc != X86EMUL_CONTINUE)
3324 goto done;
3325 }
3326
c4f035c6 3327 if (unlikely(ctxt->guest_mode) && c->intercept) {
8a76d7f2
JR		 3328 rc = emulator_check_intercept(ctxt, c->intercept,
3329 X86_ICPT_POST_EXCEPT);
c4f035c6
AK		 3330 if (rc != X86EMUL_CONTINUE)
3331 goto done;
3332 }
3333
b9fa9d6b
AK		 3334 if (c->rep_prefix && (c->d & String)) {
3335 /* All REP prefixes have the same first termination condition */
c73e197b 3336 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) {
95c55886 3337 ctxt->eip = c->eip;
b9fa9d6b
AK		 3338 goto done;
3339 }
b9fa9d6b
AK		 3340 }
3341
c483c02a 3342 if ((c->src.type == OP_MEM) && !(c->d & NoAccess)) {
90de84f5 3343 rc = read_emulated(ctxt, ops, linear(ctxt, c->src.addr.mem),
414e6277 3344 c->src.valptr, c->src.bytes);
b60d513c 3345 if (rc != X86EMUL_CONTINUE)
8b4caf66 3346 goto done;
16518d5a 3347 c->src.orig_val64 = c->src.val64;
8b4caf66
LV		 3348 }
3349
e35b7b9c 3350 if (c->src2.type == OP_MEM) {
90de84f5 3351 rc = read_emulated(ctxt, ops, linear(ctxt, c->src2.addr.mem),
9de41573 3352 &c->src2.val, c->src2.bytes);
e35b7b9c
GN		 3353 if (rc != X86EMUL_CONTINUE)
3354 goto done;
3355 }
3356
8b4caf66
LV		 3357 if ((c->d & DstMask) == ImplicitOps)
3358 goto special_insn;
3359
3360
69f55cb1
GN		 3361 if ((c->dst.type == OP_MEM) && !(c->d & Mov)) {
3362 /* optimisation - avoid slow emulated read if Mov */
90de84f5 3363 rc = read_emulated(ctxt, ops, linear(ctxt, c->dst.addr.mem),
9de41573 3364 &c->dst.val, c->dst.bytes);
69f55cb1
GN		 3365 if (rc != X86EMUL_CONTINUE)
3366 goto done;
038e51de 3367 }
e4e03ded 3368 c->dst.orig_val = c->dst.val;
038e51de 3369
018a98db
AK		 3370special_insn:
3371
c4f035c6 3372 if (unlikely(ctxt->guest_mode) && c->intercept) {
8a76d7f2
JR		 3373 rc = emulator_check_intercept(ctxt, c->intercept,
3374 X86_ICPT_POST_MEMACCESS);
c4f035c6
AK		 3375 if (rc != X86EMUL_CONTINUE)
3376 goto done;
3377 }
3378
ef65c889
AK		 3379 if (c->execute) {
3380 rc = c->execute(ctxt);
3381 if (rc != X86EMUL_CONTINUE)
3382 goto done;
3383 goto writeback;
3384 }
3385
e4e03ded 3386 if (c->twobyte)
6aa8b732
AK		 3387 goto twobyte_insn;
3388
e4e03ded 3389 switch (c->b) {
6aa8b732
AK		 3390 case 0x00 ... 0x05:
3391 add: /* add */
05f086f8 3392 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
6aa8b732 3393 break;
0934ac9d 3394 case 0x06: /* push es */
79168fd1 3395 emulate_push_sreg(ctxt, ops, VCPU_SREG_ES);
0934ac9d
MG		 3396 break;
3397 case 0x07: /* pop es */
0934ac9d 3398 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES);
0934ac9d 3399 break;
6aa8b732
AK		 3400 case 0x08 ... 0x0d:
3401 or: /* or */
05f086f8 3402 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
6aa8b732 3403 break;
0934ac9d 3404 case 0x0e: /* push cs */
79168fd1 3405 emulate_push_sreg(ctxt, ops, VCPU_SREG_CS);
0934ac9d 3406 break;
6aa8b732
AK		 3407 case 0x10 ... 0x15:
3408 adc: /* adc */
05f086f8 3409 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
6aa8b732 3410 break;
0934ac9d 3411 case 0x16: /* push ss */
79168fd1 3412 emulate_push_sreg(ctxt, ops, VCPU_SREG_SS);
0934ac9d
MG		 3413 break;
3414 case 0x17: /* pop ss */
0934ac9d 3415 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS);
0934ac9d 3416 break;
6aa8b732
AK		 3417 case 0x18 ... 0x1d:
3418 sbb: /* sbb */
05f086f8 3419 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
6aa8b732 3420 break;
0934ac9d 3421 case 0x1e: /* push ds */
79168fd1 3422 emulate_push_sreg(ctxt, ops, VCPU_SREG_DS);
0934ac9d
MG		 3423 break;
3424 case 0x1f: /* pop ds */
0934ac9d 3425 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS);
0934ac9d 3426 break;
aa3a816b 3427 case 0x20 ... 0x25:
6aa8b732 3428 and: /* and */
05f086f8 3429 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 3430 break;
3431 case 0x28 ... 0x2d:
3432 sub: /* sub */
05f086f8 3433 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 3434 break;
3435 case 0x30 ... 0x35:
3436 xor: /* xor */
05f086f8 3437 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 3438 break;
3439 case 0x38 ... 0x3d:
3440 cmp: /* cmp */
05f086f8 3441 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
6aa8b732 3442 break;
33615aa9
AK		 3443 case 0x40 ... 0x47: /* inc r16/r32 */
3444 emulate_1op("inc", c->dst, ctxt->eflags);
3445 break;
3446 case 0x48 ... 0x4f: /* dec r16/r32 */
3447 emulate_1op("dec", c->dst, ctxt->eflags);
3448 break;
33615aa9
AK		 3449 case 0x58 ... 0x5f: /* pop reg */
3450 pop_instruction:
350f69dc 3451 rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes);
33615aa9 3452 break;
abcf14b5 3453 case 0x60: /* pusha */
c37eda13 3454 rc = emulate_pusha(ctxt, ops);
abcf14b5
MG		 3455 break;
3456 case 0x61: /* popa */
3457 rc = emulate_popa(ctxt, ops);
abcf14b5 3458 break;
6aa8b732 3459 case 0x63: /* movsxd */
8b4caf66 3460 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 3461 goto cannot_emulate;
e4e03ded 3462 c->dst.val = (s32) c->src.val;
6aa8b732 3463 break;
018a98db
AK		 3464 case 0x6c: /* insb */
3465 case 0x6d: /* insw/insd */
a13a63fa
WY		 3466 c->src.val = c->regs[VCPU_REGS_RDX];
3467 goto do_io_in;
018a98db
AK		 3468 case 0x6e: /* outsb */
3469 case 0x6f: /* outsw/outsd */
a13a63fa
WY		 3470 c->dst.val = c->regs[VCPU_REGS_RDX];
3471 goto do_io_out;
7972995b 3472 break;
b2833e3c 3473 case 0x70 ... 0x7f: /* jcc (short) */
018a98db 3474 if (test_cc(c->b, ctxt->eflags))
b2833e3c 3475 jmp_rel(c, c->src.val);
018a98db 3476 break;
6aa8b732 3477 case 0x80 ... 0x83: /* Grp1 */
e4e03ded 3478 switch (c->modrm_reg) {
6aa8b732
AK		 3479 case 0:
3480 goto add;
3481 case 1:
3482 goto or;
3483 case 2:
3484 goto adc;
3485 case 3:
3486 goto sbb;
3487 case 4:
3488 goto and;
3489 case 5:
3490 goto sub;
3491 case 6:
3492 goto xor;
3493 case 7:
3494 goto cmp;
3495 }
3496 break;
3497 case 0x84 ... 0x85:
dfb507c4 3498 test:
05f086f8 3499 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 3500 break;
3501 case 0x86 ... 0x87: /* xchg */
b13354f8 3502 xchg:
6aa8b732 3503 /* Write back the register source. */
31be40b3
WY		 3504 c->src.val = c->dst.val;
3505 write_register_operand(&c->src);
6aa8b732
AK		 3506 /*
3507 * Write back the memory destination with implicit LOCK
3508 * prefix.
3509 */
31be40b3 3510 c->dst.val = c->src.orig_val;
e4e03ded 3511 c->lock_prefix = 1;
6aa8b732 3512 break;
79168fd1
GN		 3513 case 0x8c: /* mov r/m, sreg */
3514 if (c->modrm_reg > VCPU_SREG_GS) {
35d3d4a1 3515 rc = emulate_ud(ctxt);
5e3ae6c5 3516 goto done;
38d5bc6d 3517 }
79168fd1 3518 c->dst.val = ops->get_segment_selector(c->modrm_reg, ctxt->vcpu);
38d5bc6d 3519 break;
7e0b54b1 3520 case 0x8d: /* lea r16/r32, m */
90de84f5 3521 c->dst.val = c->src.addr.mem.ea;
7e0b54b1 3522 break;
4257198a
GT		 3523 case 0x8e: { /* mov seg, r/m16 */
3524 uint16_t sel;
4257198a
GT		 3525
3526 sel = c->src.val;
8b9f4414 3527
c697518a
GN		 3528 if (c->modrm_reg == VCPU_SREG_CS ||
3529 c->modrm_reg > VCPU_SREG_GS) {
35d3d4a1 3530 rc = emulate_ud(ctxt);
8b9f4414
GN		 3531 goto done;
3532 }
3533
310b5d30 3534 if (c->modrm_reg == VCPU_SREG_SS)
95cb2295 3535 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
310b5d30 3536
2e873022 3537 rc = load_segment_descriptor(ctxt, ops, sel, c->modrm_reg);
4257198a
GT		 3538
3539 c->dst.type = OP_NONE; /* Disable writeback. */
3540 break;
3541 }
6aa8b732 3542 case 0x8f: /* pop (sole member of Grp1a) */
8cdbd2c9 3543 rc = emulate_grp1a(ctxt, ops);
6aa8b732 3544 break;
3d9e77df
AK		 3545 case 0x90 ... 0x97: /* nop / xchg reg, rax */
3546 if (c->dst.addr.reg == &c->regs[VCPU_REGS_RAX])
34698d8c 3547 break;
b13354f8 3548 goto xchg;
e8b6fa70
WY		 3549 case 0x98: /* cbw/cwde/cdqe */
3550 switch (c->op_bytes) {
3551 case 2: c->dst.val = (s8)c->dst.val; break;
3552 case 4: c->dst.val = (s16)c->dst.val; break;
3553 case 8: c->dst.val = (s32)c->dst.val; break;
3554 }
3555 break;
fd2a7608 3556 case 0x9c: /* pushf */
05f086f8 3557 c->src.val = (unsigned long) ctxt->eflags;
79168fd1 3558 emulate_push(ctxt, ops);
8cdbd2c9 3559 break;
535eabcf 3560 case 0x9d: /* popf */
2b48cc75 3561 c->dst.type = OP_REG;
1a6440ae 3562 c->dst.addr.reg = &ctxt->eflags;
2b48cc75 3563 c->dst.bytes = c->op_bytes;
d4c6a154 3564 rc = emulate_popf(ctxt, ops, &c->dst.val, c->op_bytes);
d4c6a154 3565 break;
6aa8b732 3566 case 0xa6 ... 0xa7: /* cmps */
d7e5117a 3567 c->dst.type = OP_NONE; /* Disable writeback. */
a682e354 3568 goto cmp;
dfb507c4
MG		 3569 case 0xa8 ... 0xa9: /* test ax, imm */
3570 goto test;
6aa8b732 3571 case 0xae ... 0xaf: /* scas */
f6b33fc5 3572 goto cmp;
018a98db
AK		 3573 case 0xc0 ... 0xc1:
3574 emulate_grp2(ctxt);
3575 break;
111de5d6 3576 case 0xc3: /* ret */
cf5de4f8 3577 c->dst.type = OP_REG;
1a6440ae 3578 c->dst.addr.reg = &c->eip;
cf5de4f8 3579 c->dst.bytes = c->op_bytes;
111de5d6 3580 goto pop_instruction;
09b5f4d3
WY		 3581 case 0xc4: /* les */
3582 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_ES);
09b5f4d3
WY		 3583 break;
3584 case 0xc5: /* lds */
3585 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_DS);
09b5f4d3 3586 break;
a77ab5ea
AK		 3587 case 0xcb: /* ret far */
3588 rc = emulate_ret_far(ctxt, ops);
62bd430e 3589 break;
6e154e56
MG		 3590 case 0xcc: /* int3 */
3591 irq = 3;
3592 goto do_interrupt;
3593 case 0xcd: /* int n */
3594 irq = c->src.val;
3595 do_interrupt:
3596 rc = emulate_int(ctxt, ops, irq);
6e154e56
MG		 3597 break;
3598 case 0xce: /* into */
3599 if (ctxt->eflags & EFLG_OF) {
3600 irq = 4;
3601 goto do_interrupt;
3602 }
3603 break;
62bd430e
MG		 3604 case 0xcf: /* iret */
3605 rc = emulate_iret(ctxt, ops);
a77ab5ea 3606 break;
018a98db 3607 case 0xd0 ... 0xd1: /* Grp2 */
018a98db
AK		 3608 emulate_grp2(ctxt);
3609 break;
3610 case 0xd2 ... 0xd3: /* Grp2 */
3611 c->src.val = c->regs[VCPU_REGS_RCX];
3612 emulate_grp2(ctxt);
3613 break;
f2f31845
WY		 3614 case 0xe0 ... 0xe2: /* loop/loopz/loopnz */
3615 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
3616 if (address_mask(c, c->regs[VCPU_REGS_RCX]) != 0 &&
3617 (c->b == 0xe2 || test_cc(c->b ^ 0x5, ctxt->eflags)))
3618 jmp_rel(c, c->src.val);
3619 break;
e4abac67
WY		 3620 case 0xe3: /* jcxz/jecxz/jrcxz */
3621 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0)
3622 jmp_rel(c, c->src.val);
3623 break;
a6a3034c
MG		 3624 case 0xe4: /* inb */
3625 case 0xe5: /* in */
cf8f70bf 3626 goto do_io_in;
a6a3034c
MG		 3627 case 0xe6: /* outb */
3628 case 0xe7: /* out */
cf8f70bf 3629 goto do_io_out;
1a52e051 3630 case 0xe8: /* call (near) */ {
d53c4777 3631 long int rel = c->src.val;
e4e03ded 3632 c->src.val = (unsigned long) c->eip;
7a957275 3633 jmp_rel(c, rel);
79168fd1 3634 emulate_push(ctxt, ops);
8cdbd2c9 3635 break;
1a52e051
NK		 3636 }
3637 case 0xe9: /* jmp rel */
954cd36f 3638 goto jmp;
414e6277
GN		 3639 case 0xea: { /* jmp far */
3640 unsigned short sel;
ea79849d 3641 jump_far:
414e6277
GN		 3642 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
3643
3644 if (load_segment_descriptor(ctxt, ops, sel, VCPU_SREG_CS))
c697518a 3645 goto done;
954cd36f 3646
414e6277
GN		 3647 c->eip = 0;
3648 memcpy(&c->eip, c->src.valptr, c->op_bytes);
954cd36f 3649 break;
414e6277 3650 }
954cd36f
GT		 3651 case 0xeb:
3652 jmp: /* jmp rel short */
7a957275 3653 jmp_rel(c, c->src.val);
a01af5ec 3654 c->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 3655 break;
a6a3034c
MG		 3656 case 0xec: /* in al,dx */
3657 case 0xed: /* in (e/r)ax,dx */
cf8f70bf
GN		 3658 c->src.val = c->regs[VCPU_REGS_RDX];
3659 do_io_in:
3660 c->dst.bytes = min(c->dst.bytes, 4u);
3661 if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) {
35d3d4a1 3662 rc = emulate_gp(ctxt, 0);
cf8f70bf
GN		 3663 goto done;
3664 }
7b262e90
GN		 3665 if (!pio_in_emulated(ctxt, ops, c->dst.bytes, c->src.val,
3666 &c->dst.val))
cf8f70bf
GN		 3667 goto done; /* IO is needed */
3668 break;
ce7a0ad3
WY		 3669 case 0xee: /* out dx,al */
3670 case 0xef: /* out dx,(e/r)ax */
41167be5 3671 c->dst.val = c->regs[VCPU_REGS_RDX];
cf8f70bf 3672 do_io_out:
41167be5
WY		 3673 c->src.bytes = min(c->src.bytes, 4u);
3674 if (!emulator_io_permited(ctxt, ops, c->dst.val,
3675 c->src.bytes)) {
35d3d4a1 3676 rc = emulate_gp(ctxt, 0);
f850e2e6
GN		 3677 goto done;
3678 }
41167be5
WY		 3679 ops->pio_out_emulated(c->src.bytes, c->dst.val,
3680 &c->src.val, 1, ctxt->vcpu);
cf8f70bf 3681 c->dst.type = OP_NONE; /* Disable writeback. */
e93f36bc 3682 break;
111de5d6 3683 case 0xf4: /* hlt */
ad312c7c 3684 ctxt->vcpu->arch.halt_request = 1;
19fdfa0d 3685 break;
111de5d6
AK		 3686 case 0xf5: /* cmc */
3687 /* complement carry flag from eflags reg */
3688 ctxt->eflags ^= EFLG_CF;
111de5d6 3689 break;
018a98db 3690 case 0xf6 ... 0xf7: /* Grp3 */
34d1f490 3691 rc = emulate_grp3(ctxt, ops);
018a98db 3692 break;
111de5d6
AK		 3693 case 0xf8: /* clc */
3694 ctxt->eflags &= ~EFLG_CF;
111de5d6 3695 break;
8744aa9a
MG		 3696 case 0xf9: /* stc */
3697 ctxt->eflags |= EFLG_CF;
3698 break;
111de5d6 3699 case 0xfa: /* cli */
07cbc6c1 3700 if (emulator_bad_iopl(ctxt, ops)) {
35d3d4a1 3701 rc = emulate_gp(ctxt, 0);
07cbc6c1 3702 goto done;
36089fed 3703 } else
f850e2e6 3704 ctxt->eflags &= ~X86_EFLAGS_IF;
111de5d6
AK		 3705 break;
3706 case 0xfb: /* sti */
07cbc6c1 3707 if (emulator_bad_iopl(ctxt, ops)) {
35d3d4a1 3708 rc = emulate_gp(ctxt, 0);
07cbc6c1
WY		 3709 goto done;
3710 } else {
95cb2295 3711 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
f850e2e6 3712 ctxt->eflags |= X86_EFLAGS_IF;
f850e2e6 3713 }
111de5d6 3714 break;
fb4616f4
MG		 3715 case 0xfc: /* cld */
3716 ctxt->eflags &= ~EFLG_DF;
fb4616f4
MG		 3717 break;
3718 case 0xfd: /* std */
3719 ctxt->eflags |= EFLG_DF;
fb4616f4 3720 break;
ea79849d
GN		 3721 case 0xfe: /* Grp4 */
3722 grp45:
018a98db 3723 rc = emulate_grp45(ctxt, ops);
018a98db 3724 break;
ea79849d
GN		 3725 case 0xff: /* Grp5 */
3726 if (c->modrm_reg == 5)
3727 goto jump_far;
3728 goto grp45;
91269b8f
AK		 3729 default:
3730 goto cannot_emulate;
6aa8b732 3731 }
018a98db 3732
7d9ddaed
AK		 3733 if (rc != X86EMUL_CONTINUE)
3734 goto done;
3735
018a98db
AK		 3736writeback:
3737 rc = writeback(ctxt, ops);
1b30eaa8 3738 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 3739 goto done;
3740
5cd21917
GN		 3741 /*
3742 * restore dst type in case the decoding will be reused
3743 * (happens for string instruction )
3744 */
3745 c->dst.type = saved_dst_type;
3746
a682e354 3747 if ((c->d & SrcMask) == SrcSI)
90de84f5 3748 string_addr_inc(ctxt, seg_override(ctxt, ops, c),
79168fd1 3749 VCPU_REGS_RSI, &c->src);
a682e354
GN		 3750
3751 if ((c->d & DstMask) == DstDI)
90de84f5 3752 string_addr_inc(ctxt, VCPU_SREG_ES, VCPU_REGS_RDI,
79168fd1 3753 &c->dst);
d9271123 3754
5cd21917 3755 if (c->rep_prefix && (c->d & String)) {
6e2fb2ca 3756 struct read_cache *r = &ctxt->decode.io_read;
d9271123 3757 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
3e2f65d5 3758
d2ddd1c4
GN		 3759 if (!string_insn_completed(ctxt)) {
3760 /*
3761 * Re-enter guest when pio read ahead buffer is empty
3762 * or, if it is not used, after each 1024 iteration.
3763 */
3764 if ((r->end != 0 || c->regs[VCPU_REGS_RCX] & 0x3ff) &&
3765 (r->end == 0 || r->end != r->pos)) {
3766 /*
3767 * Reset read cache. Usually happens before
3768 * decode, but since instruction is restarted
3769 * we have to do it here.
3770 */
3771 ctxt->decode.mem_read.end = 0;
3772 return EMULATION_RESTART;
3773 }
3774 goto done; /* skip rip writeback */
0fa6ccbd 3775 }
5cd21917 3776 }
d2ddd1c4
GN		 3777
3778 ctxt->eip = c->eip;
018a98db
AK		 3779
3780done:
da9cb575
AK		 3781 if (rc == X86EMUL_PROPAGATE_FAULT)
3782 ctxt->have_exception = true;
775fde86
JR		 3783 if (rc == X86EMUL_INTERCEPTED)
3784 return EMULATION_INTERCEPTED;
3785
d2ddd1c4 3786 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
6aa8b732
AK		 3787
3788twobyte_insn:
e4e03ded 3789 switch (c->b) {
6aa8b732 3790 case 0x01: /* lgdt, lidt, lmsw */
e4e03ded 3791 switch (c->modrm_reg) {
6aa8b732
AK		 3792 u16 size;
3793 unsigned long address;
3794
aca7f966 3795 case 0: /* vmcall */
e4e03ded 3796 if (c->modrm_mod != 3 || c->modrm_rm != 1)
aca7f966
AL		 3797 goto cannot_emulate;
3798
7aa81cc0 3799 rc = kvm_fix_hypercall(ctxt->vcpu);
1b30eaa8 3800 if (rc != X86EMUL_CONTINUE)
7aa81cc0
AL		 3801 goto done;
3802
33e3885d 3803 /* Let the processor re-execute the fixed hypercall */
063db061 3804 c->eip = ctxt->eip;
16286d08
AK		 3805 /* Disable writeback. */
3806 c->dst.type = OP_NONE;
aca7f966 3807 break;
6aa8b732 3808 case 2: /* lgdt */
1a6440ae 3809 rc = read_descriptor(ctxt, ops, c->src.addr.mem,
e4e03ded 3810 &size, &address, c->op_bytes);
1b30eaa8 3811 if (rc != X86EMUL_CONTINUE)
6aa8b732
AK		 3812 goto done;
3813 realmode_lgdt(ctxt->vcpu, size, address);
16286d08
AK		 3814 /* Disable writeback. */
3815 c->dst.type = OP_NONE;
6aa8b732 3816 break;
aca7f966 3817 case 3: /* lidt/vmmcall */
2b3d2a20
AK		 3818 if (c->modrm_mod == 3) {
3819 switch (c->modrm_rm) {
3820 case 1:
3821 rc = kvm_fix_hypercall(ctxt->vcpu);
2b3d2a20
AK		 3822 break;
3823 default:
3824 goto cannot_emulate;
3825 }
aca7f966 3826 } else {
1a6440ae 3827 rc = read_descriptor(ctxt, ops, c->src.addr.mem,
aca7f966 3828 &size, &address,
e4e03ded 3829 c->op_bytes);
1b30eaa8 3830 if (rc != X86EMUL_CONTINUE)
aca7f966
AL		 3831 goto done;
3832 realmode_lidt(ctxt->vcpu, size, address);
3833 }
16286d08
AK		 3834 /* Disable writeback. */
3835 c->dst.type = OP_NONE;
6aa8b732
AK		 3836 break;
3837 case 4: /* smsw */
16286d08 3838 c->dst.bytes = 2;
52a46617 3839 c->dst.val = ops->get_cr(0, ctxt->vcpu);
6aa8b732
AK		 3840 break;
3841 case 6: /* lmsw */
9928ff60 3842 ops->set_cr(0, (ops->get_cr(0, ctxt->vcpu) & ~0x0eul) |
93a152be 3843 (c->src.val & 0x0f), ctxt->vcpu);
dc7457ea 3844 c->dst.type = OP_NONE;
6aa8b732 3845 break;
6e1e5ffe 3846 case 5: /* not defined */
54b8486f 3847 emulate_ud(ctxt);
da9cb575 3848 rc = X86EMUL_PROPAGATE_FAULT;
6e1e5ffe 3849 goto done;
6aa8b732 3850 case 7: /* invlpg*/
90de84f5
AK		 3851 emulate_invlpg(ctxt->vcpu,
3852 linear(ctxt, c->src.addr.mem));
16286d08
AK		 3853 /* Disable writeback. */
3854 c->dst.type = OP_NONE;
6aa8b732
AK		 3855 break;
3856 default:
3857 goto cannot_emulate;
3858 }
3859 break;
e99f0507 3860 case 0x05: /* syscall */
3fb1b5db 3861 rc = emulate_syscall(ctxt, ops);
e99f0507 3862 break;
018a98db
AK		 3863 case 0x06:
3864 emulate_clts(ctxt->vcpu);
018a98db 3865 break;
018a98db 3866 case 0x09: /* wbinvd */
f5f48ee1 3867 kvm_emulate_wbinvd(ctxt->vcpu);
f5f48ee1
SY		 3868 break;
3869 case 0x08: /* invd */
018a98db
AK		 3870 case 0x0d: /* GrpP (prefetch) */
3871 case 0x18: /* Grp16 (prefetch/nop) */
018a98db
AK		 3872 break;
3873 case 0x20: /* mov cr, reg */
1a0c7d44 3874 c->dst.val = ops->get_cr(c->modrm_reg, ctxt->vcpu);
018a98db 3875 break;
6aa8b732 3876 case 0x21: /* mov from dr to reg */
b27f3856 3877 ops->get_dr(c->modrm_reg, &c->dst.val, ctxt->vcpu);
6aa8b732 3878 break;
018a98db 3879 case 0x22: /* mov reg, cr */
1a0c7d44 3880 if (ops->set_cr(c->modrm_reg, c->src.val, ctxt->vcpu)) {
54b8486f 3881 emulate_gp(ctxt, 0);
da9cb575 3882 rc = X86EMUL_PROPAGATE_FAULT;
0f12244f
GN		 3883 goto done;
3884 }
018a98db
AK		 3885 c->dst.type = OP_NONE;
3886 break;
6aa8b732 3887 case 0x23: /* mov from reg to dr */
b27f3856 3888 if (ops->set_dr(c->modrm_reg, c->src.val &
338dbc97
GN		 3889 ((ctxt->mode == X86EMUL_MODE_PROT64) ?
3890 ~0ULL : ~0U), ctxt->vcpu) < 0) {
3891 /* #UD condition is already handled by the code above */
54b8486f 3892 emulate_gp(ctxt, 0);
da9cb575 3893 rc = X86EMUL_PROPAGATE_FAULT;
338dbc97
GN		 3894 goto done;
3895 }
3896
a01af5ec 3897 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 3898 break;
018a98db
AK		 3899 case 0x30:
3900 /* wrmsr */
3901 msr_data = (u32)c->regs[VCPU_REGS_RAX]
3902 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
3fb1b5db 3903 if (ops->set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data)) {
54b8486f 3904 emulate_gp(ctxt, 0);
da9cb575 3905 rc = X86EMUL_PROPAGATE_FAULT;
fd525365 3906 goto done;
018a98db
AK		 3907 }
3908 rc = X86EMUL_CONTINUE;
018a98db
AK		 3909 break;
3910 case 0x32:
3911 /* rdmsr */
3fb1b5db 3912 if (ops->get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data)) {
54b8486f 3913 emulate_gp(ctxt, 0);
da9cb575 3914 rc = X86EMUL_PROPAGATE_FAULT;
fd525365 3915 goto done;
018a98db
AK		 3916 } else {
3917 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
3918 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
3919 }
3920 rc = X86EMUL_CONTINUE;
018a98db 3921 break;
e99f0507 3922 case 0x34: /* sysenter */
3fb1b5db 3923 rc = emulate_sysenter(ctxt, ops);
e99f0507
AP		 3924 break;
3925 case 0x35: /* sysexit */
3fb1b5db 3926 rc = emulate_sysexit(ctxt, ops);
e99f0507 3927 break;
6aa8b732 3928 case 0x40 ... 0x4f: /* cmov */
e4e03ded 3929 c->dst.val = c->dst.orig_val = c->src.val;
a01af5ec
LV		 3930 if (!test_cc(c->b, ctxt->eflags))
3931 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 3932 break;
b2833e3c 3933 case 0x80 ... 0x8f: /* jnz rel, etc*/
018a98db 3934 if (test_cc(c->b, ctxt->eflags))
b2833e3c 3935 jmp_rel(c, c->src.val);
018a98db 3936 break;
ee45b58e
WY		 3937 case 0x90 ... 0x9f: /* setcc r/m8 */
3938 c->dst.val = test_cc(c->b, ctxt->eflags);
3939 break;
0934ac9d 3940 case 0xa0: /* push fs */
79168fd1 3941 emulate_push_sreg(ctxt, ops, VCPU_SREG_FS);
0934ac9d
MG		 3942 break;
3943 case 0xa1: /* pop fs */
3944 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS);
0934ac9d 3945 break;
7de75248
NK		 3946 case 0xa3:
3947 bt: /* bt */
e4f8e039 3948 c->dst.type = OP_NONE;
e4e03ded
LV		 3949 /* only subword offset */
3950 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3951 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
7de75248 3952 break;
9bf8ea42
GT		 3953 case 0xa4: /* shld imm8, r, r/m */
3954 case 0xa5: /* shld cl, r, r/m */
3955 emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
3956 break;
0934ac9d 3957 case 0xa8: /* push gs */
79168fd1 3958 emulate_push_sreg(ctxt, ops, VCPU_SREG_GS);
0934ac9d
MG		 3959 break;
3960 case 0xa9: /* pop gs */
3961 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS);
0934ac9d 3962 break;
7de75248
NK		 3963 case 0xab:
3964 bts: /* bts */
05f086f8 3965 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
7de75248 3966 break;
9bf8ea42
GT		 3967 case 0xac: /* shrd imm8, r, r/m */
3968 case 0xad: /* shrd cl, r, r/m */
3969 emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags);
3970 break;
2a7c5b8b
GC		 3971 case 0xae: /* clflush */
3972 break;
6aa8b732
AK		 3973 case 0xb0 ... 0xb1: /* cmpxchg */
3974 /*
3975 * Save real source value, then compare EAX against
3976 * destination.
3977 */
e4e03ded
LV		 3978 c->src.orig_val = c->src.val;
3979 c->src.val = c->regs[VCPU_REGS_RAX];
05f086f8
LV		 3980 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
3981 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 3982 /* Success: write back to memory. */
e4e03ded 3983 c->dst.val = c->src.orig_val;
6aa8b732
AK		 3984 } else {
3985 /* Failure: write the value we saw to EAX. */
e4e03ded 3986 c->dst.type = OP_REG;
1a6440ae 3987 c->dst.addr.reg = (unsigned long *)&c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 3988 }
3989 break;
09b5f4d3
WY		 3990 case 0xb2: /* lss */
3991 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_SS);
09b5f4d3 3992 break;
6aa8b732
AK		 3993 case 0xb3:
3994 btr: /* btr */
05f086f8 3995 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
6aa8b732 3996 break;
09b5f4d3
WY		 3997 case 0xb4: /* lfs */
3998 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_FS);
09b5f4d3
WY		 3999 break;
4000 case 0xb5: /* lgs */
4001 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_GS);
09b5f4d3 4002 break;
6aa8b732 4003 case 0xb6 ... 0xb7: /* movzx */
e4e03ded
LV		 4004 c->dst.bytes = c->op_bytes;
4005 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
4006 : (u16) c->src.val;
6aa8b732 4007 break;
6aa8b732 4008 case 0xba: /* Grp8 */
e4e03ded 4009 switch (c->modrm_reg & 3) {
6aa8b732
AK		 4010 case 0:
4011 goto bt;
4012 case 1:
4013 goto bts;
4014 case 2:
4015 goto btr;
4016 case 3:
4017 goto btc;
4018 }
4019 break;
7de75248
NK		 4020 case 0xbb:
4021 btc: /* btc */
05f086f8 4022 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
7de75248 4023 break;
d9574a25
WY		 4024 case 0xbc: { /* bsf */
4025 u8 zf;
4026 __asm__ ("bsf %2, %0; setz %1"
4027 : "=r"(c->dst.val), "=q"(zf)
4028 : "r"(c->src.val));
4029 ctxt->eflags &= ~X86_EFLAGS_ZF;
4030 if (zf) {
4031 ctxt->eflags |= X86_EFLAGS_ZF;
4032 c->dst.type = OP_NONE; /* Disable writeback. */
4033 }
4034 break;
4035 }
4036 case 0xbd: { /* bsr */
4037 u8 zf;
4038 __asm__ ("bsr %2, %0; setz %1"
4039 : "=r"(c->dst.val), "=q"(zf)
4040 : "r"(c->src.val));
4041 ctxt->eflags &= ~X86_EFLAGS_ZF;
4042 if (zf) {
4043 ctxt->eflags |= X86_EFLAGS_ZF;
4044 c->dst.type = OP_NONE; /* Disable writeback. */
4045 }
4046 break;
4047 }
6aa8b732 4048 case 0xbe ... 0xbf: /* movsx */
e4e03ded
LV		 4049 c->dst.bytes = c->op_bytes;
4050 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
4051 (s16) c->src.val;
6aa8b732 4052 break;
92f738a5
WY		 4053 case 0xc0 ... 0xc1: /* xadd */
4054 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
4055 /* Write back the register source. */
4056 c->src.val = c->dst.orig_val;
4057 write_register_operand(&c->src);
4058 break;
a012e65a 4059 case 0xc3: /* movnti */
e4e03ded
LV		 4060 c->dst.bytes = c->op_bytes;
4061 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
4062 (u64) c->src.val;
a012e65a 4063 break;
6aa8b732 4064 case 0xc7: /* Grp9 (cmpxchg8b) */
69f55cb1 4065 rc = emulate_grp9(ctxt, ops);
8cdbd2c9 4066 break;
91269b8f
AK		 4067 default:
4068 goto cannot_emulate;
6aa8b732 4069 }
7d9ddaed
AK		 4070
4071 if (rc != X86EMUL_CONTINUE)
4072 goto done;
4073
6aa8b732
AK		 4074 goto writeback;
4075
4076cannot_emulate:
6aa8b732
AK		 4077 return -1;
4078}
Linux kernel - Deliverables
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