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KVM: x86 emulator: don't update vcpu state if instruction is restarted
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
CommitLineData
6aa8b732 1/******************************************************************************
56e82318 2 * emulate.c
6aa8b732
AK		 3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
221d059d 12 * Copyright 2010 Red Hat, Inc. and/or its affilates.
6aa8b732
AK		 13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
23#ifndef __KERNEL__
24#include <stdio.h>
25#include <stdint.h>
26#include <public/xen.h>
d77c26fc 27#define DPRINTF(_f, _a ...) printf(_f , ## _a)
6aa8b732 28#else
edf88417 29#include <linux/kvm_host.h>
5fdbf976 30#include "kvm_cache_regs.h"
6aa8b732
AK		 31#define DPRINTF(x...) do {} while (0)
32#endif
6aa8b732 33#include <linux/module.h>
56e82318 34#include <asm/kvm_emulate.h>
6aa8b732 35
3eeb3288 36#include "x86.h"
38ba30ba 37#include "tss.h"
e99f0507 38
6aa8b732
AK		 39/*
40 * Opcode effective-address decode tables.
41 * Note that we only emulate instructions that have at least one memory
42 * operand (excluding implicit stack references). We assume that stack
43 * references and instruction fetches will never occur in special memory
44 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
45 * not be handled.
46 */
47
48/* Operand sizes: 8-bit operands or specified/overridden size. */
ab85b12b 49#define ByteOp (1<<0) /* 8-bit operands. */
6aa8b732 50/* Destination operand type. */
ab85b12b
AK		 51#define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
52#define DstReg (2<<1) /* Register operand. */
53#define DstMem (3<<1) /* Memory operand. */
54#define DstAcc (4<<1) /* Destination Accumulator */
55#define DstDI (5<<1) /* Destination is in ES:(E)DI */
56#define DstMem64 (6<<1) /* 64bit memory operand */
57#define DstMask (7<<1)
6aa8b732 58/* Source operand type. */
9c9fddd0
GT		 59#define SrcNone (0<<4) /* No source operand. */
60#define SrcImplicit (0<<4) /* Source operand is implicit in the opcode. */
61#define SrcReg (1<<4) /* Register operand. */
62#define SrcMem (2<<4) /* Memory operand. */
63#define SrcMem16 (3<<4) /* Memory operand (16-bit). */
64#define SrcMem32 (4<<4) /* Memory operand (32-bit). */
65#define SrcImm (5<<4) /* Immediate operand. */
66#define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
bfcadf83 67#define SrcOne (7<<4) /* Implied '1' */
341de7e3 68#define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */
c9eaf20f 69#define SrcImmU (9<<4) /* Immediate operand, unsigned */
a682e354 70#define SrcSI (0xa<<4) /* Source is in the DS:RSI */
414e6277
GN		 71#define SrcImmFAddr (0xb<<4) /* Source is immediate far address */
72#define SrcMemFAddr (0xc<<4) /* Source is far address in memory */
5d55f299 73#define SrcAcc (0xd<<4) /* Source Accumulator */
341de7e3 74#define SrcMask (0xf<<4)
6aa8b732 75/* Generic ModRM decode. */
341de7e3 76#define ModRM (1<<8)
6aa8b732 77/* Destination is only written; never read. */
341de7e3
GN		 78#define Mov (1<<9)
79#define BitOp (1<<10)
80#define MemAbs (1<<11) /* Memory operand is absolute displacement */
9c9fddd0
GT		 81#define String (1<<12) /* String instruction (rep capable) */
82#define Stack (1<<13) /* Stack instruction (push/pop) */
e09d082c
AK		 83#define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
84#define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
d8769fed 85/* Misc flags */
047a4818 86#define Undefined (1<<25) /* No Such Instruction */
d380a5e4 87#define Lock (1<<26) /* lock prefix is allowed for the instruction */
e92805ac 88#define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
d8769fed 89#define No64 (1<<28)
0dc8d10f
GT		 90/* Source 2 operand type */
91#define Src2None (0<<29)
92#define Src2CL (1<<29)
93#define Src2ImmByte (2<<29)
94#define Src2One (3<<29)
95#define Src2Mask (7<<29)
6aa8b732 96
d0e53325
AK		 97#define X2(x...) x, x
98#define X3(x...) X2(x), x
99#define X4(x...) X2(x), X2(x)
100#define X5(x...) X4(x), x
101#define X6(x...) X4(x), X2(x)
102#define X7(x...) X4(x), X3(x)
103#define X8(x...) X4(x), X4(x)
104#define X16(x...) X8(x), X8(x)
83babbca 105
d65b1dee
AK		 106struct opcode {
107 u32 flags;
120df890 108 union {
ef65c889 109 int (*execute)(struct x86_emulate_ctxt *ctxt);
120df890
AK		 110 struct opcode *group;
111 struct group_dual *gdual;
112 } u;
113};
114
115struct group_dual {
116 struct opcode mod012[8];
117 struct opcode mod3[8];
d65b1dee
AK		 118};
119
6aa8b732 120/* EFLAGS bit definitions. */
d4c6a154
GN		 121#define EFLG_ID (1<<21)
122#define EFLG_VIP (1<<20)
123#define EFLG_VIF (1<<19)
124#define EFLG_AC (1<<18)
b1d86143
AP		 125#define EFLG_VM (1<<17)
126#define EFLG_RF (1<<16)
d4c6a154
GN		 127#define EFLG_IOPL (3<<12)
128#define EFLG_NT (1<<14)
6aa8b732
AK		 129#define EFLG_OF (1<<11)
130#define EFLG_DF (1<<10)
b1d86143 131#define EFLG_IF (1<<9)
d4c6a154 132#define EFLG_TF (1<<8)
6aa8b732
AK		 133#define EFLG_SF (1<<7)
134#define EFLG_ZF (1<<6)
135#define EFLG_AF (1<<4)
136#define EFLG_PF (1<<2)
137#define EFLG_CF (1<<0)
138
62bd430e
MG		 139#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
140#define EFLG_RESERVED_ONE_MASK 2
141
6aa8b732
AK		 142/*
143 * Instruction emulation:
144 * Most instructions are emulated directly via a fragment of inline assembly
145 * code. This allows us to save/restore EFLAGS and thus very easily pick up
146 * any modified flags.
147 */
148
05b3e0c2 149#if defined(CONFIG_X86_64)
6aa8b732
AK		 150#define _LO32 "k" /* force 32-bit operand */
151#define _STK "%%rsp" /* stack pointer */
152#elif defined(__i386__)
153#define _LO32 "" /* force 32-bit operand */
154#define _STK "%%esp" /* stack pointer */
155#endif
156
157/*
158 * These EFLAGS bits are restored from saved value during emulation, and
159 * any changes are written back to the saved value after emulation.
160 */
161#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
162
163/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 164#define _PRE_EFLAGS(_sav, _msk, _tmp) \
165 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
166 "movl %"_sav",%"_LO32 _tmp"; " \
167 "push %"_tmp"; " \
168 "push %"_tmp"; " \
169 "movl %"_msk",%"_LO32 _tmp"; " \
170 "andl %"_LO32 _tmp",("_STK"); " \
171 "pushf; " \
172 "notl %"_LO32 _tmp"; " \
173 "andl %"_LO32 _tmp",("_STK"); " \
174 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
175 "pop %"_tmp"; " \
176 "orl %"_LO32 _tmp",("_STK"); " \
177 "popf; " \
178 "pop %"_sav"; "
6aa8b732
AK		 179
180/* After executing instruction: write-back necessary bits in EFLAGS. */
181#define _POST_EFLAGS(_sav, _msk, _tmp) \
182 /* _sav |= EFLAGS & _msk; */ \
183 "pushf; " \
184 "pop %"_tmp"; " \
185 "andl %"_msk",%"_LO32 _tmp"; " \
186 "orl %"_LO32 _tmp",%"_sav"; "
187
dda96d8f
AK		 188#ifdef CONFIG_X86_64
189#define ON64(x) x
190#else
191#define ON64(x)
192#endif
193
6b7ad61f
AK		 194#define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix) \
195 do { \
196 __asm__ __volatile__ ( \
197 _PRE_EFLAGS("0", "4", "2") \
198 _op _suffix " %"_x"3,%1; " \
199 _POST_EFLAGS("0", "4", "2") \
200 : "=m" (_eflags), "=m" ((_dst).val), \
201 "=&r" (_tmp) \
202 : _y ((_src).val), "i" (EFLAGS_MASK)); \
f3fd92fb 203 } while (0)
6b7ad61f
AK		 204
205
6aa8b732
AK		 206/* Raw emulation: instruction has two explicit operands. */
207#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 208 do { \
209 unsigned long _tmp; \
210 \
211 switch ((_dst).bytes) { \
212 case 2: \
213 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w"); \
214 break; \
215 case 4: \
216 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l"); \
217 break; \
218 case 8: \
219 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q")); \
220 break; \
221 } \
6aa8b732
AK		 222 } while (0)
223
224#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
225 do { \
6b7ad61f 226 unsigned long _tmp; \
d77c26fc 227 switch ((_dst).bytes) { \
6aa8b732 228 case 1: \
6b7ad61f 229 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b"); \
6aa8b732
AK		 230 break; \
231 default: \
232 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
233 _wx, _wy, _lx, _ly, _qx, _qy); \
234 break; \
235 } \
236 } while (0)
237
238/* Source operand is byte-sized and may be restricted to just %cl. */
239#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
240 __emulate_2op(_op, _src, _dst, _eflags, \
241 "b", "c", "b", "c", "b", "c", "b", "c")
242
243/* Source operand is byte, word, long or quad sized. */
244#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
245 __emulate_2op(_op, _src, _dst, _eflags, \
246 "b", "q", "w", "r", _LO32, "r", "", "r")
247
248/* Source operand is word, long or quad sized. */
249#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
250 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
251 "w", "r", _LO32, "r", "", "r")
252
d175226a
GT		 253/* Instruction has three operands and one operand is stored in ECX register */
254#define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
255 do { \
256 unsigned long _tmp; \
257 _type _clv = (_cl).val; \
258 _type _srcv = (_src).val; \
259 _type _dstv = (_dst).val; \
260 \
261 __asm__ __volatile__ ( \
262 _PRE_EFLAGS("0", "5", "2") \
263 _op _suffix " %4,%1 \n" \
264 _POST_EFLAGS("0", "5", "2") \
265 : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
266 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
267 ); \
268 \
269 (_cl).val = (unsigned long) _clv; \
270 (_src).val = (unsigned long) _srcv; \
271 (_dst).val = (unsigned long) _dstv; \
272 } while (0)
273
274#define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
275 do { \
276 switch ((_dst).bytes) { \
277 case 2: \
278 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
279 "w", unsigned short); \
280 break; \
281 case 4: \
282 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
283 "l", unsigned int); \
284 break; \
285 case 8: \
286 ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
287 "q", unsigned long)); \
288 break; \
289 } \
290 } while (0)
291
dda96d8f 292#define __emulate_1op(_op, _dst, _eflags, _suffix) \
6aa8b732
AK		 293 do { \
294 unsigned long _tmp; \
295 \
dda96d8f
AK		 296 __asm__ __volatile__ ( \
297 _PRE_EFLAGS("0", "3", "2") \
298 _op _suffix " %1; " \
299 _POST_EFLAGS("0", "3", "2") \
300 : "=m" (_eflags), "+m" ((_dst).val), \
301 "=&r" (_tmp) \
302 : "i" (EFLAGS_MASK)); \
303 } while (0)
304
305/* Instruction has only one explicit operand (no source operand). */
306#define emulate_1op(_op, _dst, _eflags) \
307 do { \
d77c26fc 308 switch ((_dst).bytes) { \
dda96d8f
AK		 309 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
310 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
311 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
312 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
6aa8b732
AK		 313 } \
314 } while (0)
315
6aa8b732
AK		 316/* Fetch next part of the instruction being emulated. */
317#define insn_fetch(_type, _size, _eip) \
318({ unsigned long _x; \
62266869 319 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
af5b4f7f 320 if (rc != X86EMUL_CONTINUE) \
6aa8b732
AK		 321 goto done; \
322 (_eip) += (_size); \
323 (_type)_x; \
324})
325
414e6277
GN		 326#define insn_fetch_arr(_arr, _size, _eip) \
327({ rc = do_insn_fetch(ctxt, ops, (_eip), _arr, (_size)); \
328 if (rc != X86EMUL_CONTINUE) \
329 goto done; \
330 (_eip) += (_size); \
331})
332
ddcb2885
HH		 333static inline unsigned long ad_mask(struct decode_cache *c)
334{
335 return (1UL << (c->ad_bytes << 3)) - 1;
336}
337
6aa8b732 338/* Access/update address held in a register, based on addressing mode. */
e4706772
HH		 339static inline unsigned long
340address_mask(struct decode_cache *c, unsigned long reg)
341{
342 if (c->ad_bytes == sizeof(unsigned long))
343 return reg;
344 else
345 return reg & ad_mask(c);
346}
347
348static inline unsigned long
349register_address(struct decode_cache *c, unsigned long base, unsigned long reg)
350{
351 return base + address_mask(c, reg);
352}
353
7a957275
HH		 354static inline void
355register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
356{
357 if (c->ad_bytes == sizeof(unsigned long))
358 *reg += inc;
359 else
360 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
361}
6aa8b732 362
7a957275
HH		 363static inline void jmp_rel(struct decode_cache *c, int rel)
364{
365 register_address_increment(c, &c->eip, rel);
366}
098c937b 367
7a5b56df
AK		 368static void set_seg_override(struct decode_cache *c, int seg)
369{
370 c->has_seg_override = true;
371 c->seg_override = seg;
372}
373
79168fd1
GN		 374static unsigned long seg_base(struct x86_emulate_ctxt *ctxt,
375 struct x86_emulate_ops *ops, int seg)
7a5b56df
AK		 376{
377 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
378 return 0;
379
79168fd1 380 return ops->get_cached_segment_base(seg, ctxt->vcpu);
7a5b56df
AK		 381}
382
383static unsigned long seg_override_base(struct x86_emulate_ctxt *ctxt,
79168fd1 384 struct x86_emulate_ops *ops,
7a5b56df
AK		 385 struct decode_cache *c)
386{
387 if (!c->has_seg_override)
388 return 0;
389
79168fd1 390 return seg_base(ctxt, ops, c->seg_override);
7a5b56df
AK		 391}
392
79168fd1
GN		 393static unsigned long es_base(struct x86_emulate_ctxt *ctxt,
394 struct x86_emulate_ops *ops)
7a5b56df 395{
79168fd1 396 return seg_base(ctxt, ops, VCPU_SREG_ES);
7a5b56df
AK		 397}
398
79168fd1
GN		 399static unsigned long ss_base(struct x86_emulate_ctxt *ctxt,
400 struct x86_emulate_ops *ops)
7a5b56df 401{
79168fd1 402 return seg_base(ctxt, ops, VCPU_SREG_SS);
7a5b56df
AK		 403}
404
54b8486f
GN		 405static void emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
406 u32 error, bool valid)
407{
408 ctxt->exception = vec;
409 ctxt->error_code = error;
410 ctxt->error_code_valid = valid;
411 ctxt->restart = false;
412}
413
414static void emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
415{
416 emulate_exception(ctxt, GP_VECTOR, err, true);
417}
418
419static void emulate_pf(struct x86_emulate_ctxt *ctxt, unsigned long addr,
420 int err)
421{
422 ctxt->cr2 = addr;
423 emulate_exception(ctxt, PF_VECTOR, err, true);
424}
425
426static void emulate_ud(struct x86_emulate_ctxt *ctxt)
427{
428 emulate_exception(ctxt, UD_VECTOR, 0, false);
429}
430
431static void emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
432{
433 emulate_exception(ctxt, TS_VECTOR, err, true);
434}
435
62266869
AK		 436static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
437 struct x86_emulate_ops *ops,
2fb53ad8 438 unsigned long eip, u8 *dest)
62266869
AK		 439{
440 struct fetch_cache *fc = &ctxt->decode.fetch;
441 int rc;
2fb53ad8 442 int size, cur_size;
62266869 443
2fb53ad8
AK		 444 if (eip == fc->end) {
445 cur_size = fc->end - fc->start;
446 size = min(15UL - cur_size, PAGE_SIZE - offset_in_page(eip));
447 rc = ops->fetch(ctxt->cs_base + eip, fc->data + cur_size,
448 size, ctxt->vcpu, NULL);
3e2815e9 449 if (rc != X86EMUL_CONTINUE)
62266869 450 return rc;
2fb53ad8 451 fc->end += size;
62266869 452 }
2fb53ad8 453 *dest = fc->data[eip - fc->start];
3e2815e9 454 return X86EMUL_CONTINUE;
62266869
AK		 455}
456
457static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
458 struct x86_emulate_ops *ops,
459 unsigned long eip, void *dest, unsigned size)
460{
3e2815e9 461 int rc;
62266869 462
eb3c79e6 463 /* x86 instructions are limited to 15 bytes. */
063db061 464 if (eip + size - ctxt->eip > 15)
eb3c79e6 465 return X86EMUL_UNHANDLEABLE;
62266869
AK		 466 while (size--) {
467 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
3e2815e9 468 if (rc != X86EMUL_CONTINUE)
62266869
AK		 469 return rc;
470 }
3e2815e9 471 return X86EMUL_CONTINUE;
62266869
AK		 472}
473
1e3c5cb0
RR		 474/*
475 * Given the 'reg' portion of a ModRM byte, and a register block, return a
476 * pointer into the block that addresses the relevant register.
477 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
478 */
479static void *decode_register(u8 modrm_reg, unsigned long *regs,
480 int highbyte_regs)
6aa8b732
AK		 481{
482 void *p;
483
484 p = &regs[modrm_reg];
485 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
486 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
487 return p;
488}
489
490static int read_descriptor(struct x86_emulate_ctxt *ctxt,
491 struct x86_emulate_ops *ops,
492 void *ptr,
493 u16 *size, unsigned long *address, int op_bytes)
494{
495 int rc;
496
497 if (op_bytes == 2)
498 op_bytes = 3;
499 *address = 0;
cebff02b 500 rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2,
1871c602 501 ctxt->vcpu, NULL);
1b30eaa8 502 if (rc != X86EMUL_CONTINUE)
6aa8b732 503 return rc;
cebff02b 504 rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes,
1871c602 505 ctxt->vcpu, NULL);
6aa8b732
AK		 506 return rc;
507}
508
bbe9abbd
NK		 509static int test_cc(unsigned int condition, unsigned int flags)
510{
511 int rc = 0;
512
513 switch ((condition & 15) >> 1) {
514 case 0: /* o */
515 rc |= (flags & EFLG_OF);
516 break;
517 case 1: /* b/c/nae */
518 rc |= (flags & EFLG_CF);
519 break;
520 case 2: /* z/e */
521 rc |= (flags & EFLG_ZF);
522 break;
523 case 3: /* be/na */
524 rc |= (flags & (EFLG_CF|EFLG_ZF));
525 break;
526 case 4: /* s */
527 rc |= (flags & EFLG_SF);
528 break;
529 case 5: /* p/pe */
530 rc |= (flags & EFLG_PF);
531 break;
532 case 7: /* le/ng */
533 rc |= (flags & EFLG_ZF);
534 /* fall through */
535 case 6: /* l/nge */
536 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
537 break;
538 }
539
540 /* Odd condition identifiers (lsb == 1) have inverted sense. */
541 return (!!rc ^ (condition & 1));
542}
543
3c118e24
AK		 544static void decode_register_operand(struct operand *op,
545 struct decode_cache *c,
3c118e24
AK		 546 int inhibit_bytereg)
547{
33615aa9 548 unsigned reg = c->modrm_reg;
9f1ef3f8 549 int highbyte_regs = c->rex_prefix == 0;
33615aa9
AK		 550
551 if (!(c->d & ModRM))
552 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
3c118e24
AK		 553 op->type = OP_REG;
554 if ((c->d & ByteOp) && !inhibit_bytereg) {
33615aa9 555 op->ptr = decode_register(reg, c->regs, highbyte_regs);
3c118e24
AK		 556 op->val = *(u8 *)op->ptr;
557 op->bytes = 1;
558 } else {
33615aa9 559 op->ptr = decode_register(reg, c->regs, 0);
3c118e24
AK		 560 op->bytes = c->op_bytes;
561 switch (op->bytes) {
562 case 2:
563 op->val = *(u16 *)op->ptr;
564 break;
565 case 4:
566 op->val = *(u32 *)op->ptr;
567 break;
568 case 8:
569 op->val = *(u64 *) op->ptr;
570 break;
571 }
572 }
573 op->orig_val = op->val;
574}
575
1c73ef66
AK		 576static int decode_modrm(struct x86_emulate_ctxt *ctxt,
577 struct x86_emulate_ops *ops)
578{
579 struct decode_cache *c = &ctxt->decode;
580 u8 sib;
f5b4edcd 581 int index_reg = 0, base_reg = 0, scale;
3e2815e9 582 int rc = X86EMUL_CONTINUE;
1c73ef66
AK		 583
584 if (c->rex_prefix) {
585 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
586 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
587 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
588 }
589
590 c->modrm = insn_fetch(u8, 1, c->eip);
591 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
592 c->modrm_reg |= (c->modrm & 0x38) >> 3;
593 c->modrm_rm |= (c->modrm & 0x07);
594 c->modrm_ea = 0;
595 c->use_modrm_ea = 1;
596
597 if (c->modrm_mod == 3) {
107d6d2e
AK		 598 c->modrm_ptr = decode_register(c->modrm_rm,
599 c->regs, c->d & ByteOp);
600 c->modrm_val = *(unsigned long *)c->modrm_ptr;
1c73ef66
AK		 601 return rc;
602 }
603
604 if (c->ad_bytes == 2) {
605 unsigned bx = c->regs[VCPU_REGS_RBX];
606 unsigned bp = c->regs[VCPU_REGS_RBP];
607 unsigned si = c->regs[VCPU_REGS_RSI];
608 unsigned di = c->regs[VCPU_REGS_RDI];
609
610 /* 16-bit ModR/M decode. */
611 switch (c->modrm_mod) {
612 case 0:
613 if (c->modrm_rm == 6)
614 c->modrm_ea += insn_fetch(u16, 2, c->eip);
615 break;
616 case 1:
617 c->modrm_ea += insn_fetch(s8, 1, c->eip);
618 break;
619 case 2:
620 c->modrm_ea += insn_fetch(u16, 2, c->eip);
621 break;
622 }
623 switch (c->modrm_rm) {
624 case 0:
625 c->modrm_ea += bx + si;
626 break;
627 case 1:
628 c->modrm_ea += bx + di;
629 break;
630 case 2:
631 c->modrm_ea += bp + si;
632 break;
633 case 3:
634 c->modrm_ea += bp + di;
635 break;
636 case 4:
637 c->modrm_ea += si;
638 break;
639 case 5:
640 c->modrm_ea += di;
641 break;
642 case 6:
643 if (c->modrm_mod != 0)
644 c->modrm_ea += bp;
645 break;
646 case 7:
647 c->modrm_ea += bx;
648 break;
649 }
650 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
651 (c->modrm_rm == 6 && c->modrm_mod != 0))
7a5b56df
AK		 652 if (!c->has_seg_override)
653 set_seg_override(c, VCPU_SREG_SS);
1c73ef66
AK		 654 c->modrm_ea = (u16)c->modrm_ea;
655 } else {
656 /* 32/64-bit ModR/M decode. */
84411d85 657 if ((c->modrm_rm & 7) == 4) {
1c73ef66
AK		 658 sib = insn_fetch(u8, 1, c->eip);
659 index_reg |= (sib >> 3) & 7;
660 base_reg |= sib & 7;
661 scale = sib >> 6;
662
dc71d0f1
AK		 663 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
664 c->modrm_ea += insn_fetch(s32, 4, c->eip);
665 else
1c73ef66 666 c->modrm_ea += c->regs[base_reg];
dc71d0f1 667 if (index_reg != 4)
1c73ef66 668 c->modrm_ea += c->regs[index_reg] << scale;
84411d85
AK		 669 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
670 if (ctxt->mode == X86EMUL_MODE_PROT64)
f5b4edcd 671 c->rip_relative = 1;
84411d85 672 } else
1c73ef66 673 c->modrm_ea += c->regs[c->modrm_rm];
1c73ef66
AK		 674 switch (c->modrm_mod) {
675 case 0:
676 if (c->modrm_rm == 5)
677 c->modrm_ea += insn_fetch(s32, 4, c->eip);
678 break;
679 case 1:
680 c->modrm_ea += insn_fetch(s8, 1, c->eip);
681 break;
682 case 2:
683 c->modrm_ea += insn_fetch(s32, 4, c->eip);
684 break;
685 }
686 }
1c73ef66
AK		 687done:
688 return rc;
689}
690
691static int decode_abs(struct x86_emulate_ctxt *ctxt,
692 struct x86_emulate_ops *ops)
693{
694 struct decode_cache *c = &ctxt->decode;
3e2815e9 695 int rc = X86EMUL_CONTINUE;
1c73ef66
AK		 696
697 switch (c->ad_bytes) {
698 case 2:
699 c->modrm_ea = insn_fetch(u16, 2, c->eip);
700 break;
701 case 4:
702 c->modrm_ea = insn_fetch(u32, 4, c->eip);
703 break;
704 case 8:
705 c->modrm_ea = insn_fetch(u64, 8, c->eip);
706 break;
707 }
708done:
709 return rc;
710}
711
dde7e6d1
AK		 712static int read_emulated(struct x86_emulate_ctxt *ctxt,
713 struct x86_emulate_ops *ops,
714 unsigned long addr, void *dest, unsigned size)
6aa8b732 715{
dde7e6d1
AK		 716 int rc;
717 struct read_cache *mc = &ctxt->decode.mem_read;
718 u32 err;
6aa8b732 719
dde7e6d1
AK		 720 while (size) {
721 int n = min(size, 8u);
722 size -= n;
723 if (mc->pos < mc->end)
724 goto read_cached;
5cd21917 725
dde7e6d1
AK		 726 rc = ops->read_emulated(addr, mc->data + mc->end, n, &err,
727 ctxt->vcpu);
728 if (rc == X86EMUL_PROPAGATE_FAULT)
729 emulate_pf(ctxt, addr, err);
730 if (rc != X86EMUL_CONTINUE)
731 return rc;
732 mc->end += n;
6aa8b732 733
dde7e6d1
AK		 734 read_cached:
735 memcpy(dest, mc->data + mc->pos, n);
736 mc->pos += n;
737 dest += n;
738 addr += n;
6aa8b732 739 }
dde7e6d1
AK		 740 return X86EMUL_CONTINUE;
741}
6aa8b732 742
dde7e6d1
AK		 743static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
744 struct x86_emulate_ops *ops,
745 unsigned int size, unsigned short port,
746 void *dest)
747{
748 struct read_cache *rc = &ctxt->decode.io_read;
b4c6abfe 749
dde7e6d1
AK		 750 if (rc->pos == rc->end) { /* refill pio read ahead */
751 struct decode_cache *c = &ctxt->decode;
752 unsigned int in_page, n;
753 unsigned int count = c->rep_prefix ?
754 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1;
755 in_page = (ctxt->eflags & EFLG_DF) ?
756 offset_in_page(c->regs[VCPU_REGS_RDI]) :
757 PAGE_SIZE - offset_in_page(c->regs[VCPU_REGS_RDI]);
758 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
759 count);
760 if (n == 0)
761 n = 1;
762 rc->pos = rc->end = 0;
763 if (!ops->pio_in_emulated(size, port, rc->data, n, ctxt->vcpu))
764 return 0;
765 rc->end = n * size;
6aa8b732
AK		 766 }
767
dde7e6d1
AK		 768 memcpy(dest, rc->data + rc->pos, size);
769 rc->pos += size;
770 return 1;
771}
6aa8b732 772
dde7e6d1
AK		 773static u32 desc_limit_scaled(struct desc_struct *desc)
774{
775 u32 limit = get_desc_limit(desc);
6aa8b732 776
dde7e6d1
AK		 777 return desc->g ? (limit << 12) | 0xfff : limit;
778}
6aa8b732 779
dde7e6d1
AK		 780static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
781 struct x86_emulate_ops *ops,
782 u16 selector, struct desc_ptr *dt)
783{
784 if (selector & 1 << 2) {
785 struct desc_struct desc;
786 memset (dt, 0, sizeof *dt);
787 if (!ops->get_cached_descriptor(&desc, VCPU_SREG_LDTR, ctxt->vcpu))
788 return;
e09d082c 789
dde7e6d1
AK		 790 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
791 dt->address = get_desc_base(&desc);
792 } else
793 ops->get_gdt(dt, ctxt->vcpu);
794}
120df890 795
dde7e6d1
AK		 796/* allowed just for 8 bytes segments */
797static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
798 struct x86_emulate_ops *ops,
799 u16 selector, struct desc_struct *desc)
800{
801 struct desc_ptr dt;
802 u16 index = selector >> 3;
803 int ret;
804 u32 err;
805 ulong addr;
120df890 806
dde7e6d1 807 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
120df890 808
dde7e6d1
AK		 809 if (dt.size < index * 8 + 7) {
810 emulate_gp(ctxt, selector & 0xfffc);
811 return X86EMUL_PROPAGATE_FAULT;
e09d082c 812 }
dde7e6d1
AK		 813 addr = dt.address + index * 8;
814 ret = ops->read_std(addr, desc, sizeof *desc, ctxt->vcpu, &err);
815 if (ret == X86EMUL_PROPAGATE_FAULT)
816 emulate_pf(ctxt, addr, err);
e09d082c 817
dde7e6d1
AK		 818 return ret;
819}
ef65c889 820
dde7e6d1
AK		 821/* allowed just for 8 bytes segments */
822static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
823 struct x86_emulate_ops *ops,
824 u16 selector, struct desc_struct *desc)
825{
826 struct desc_ptr dt;
827 u16 index = selector >> 3;
828 u32 err;
829 ulong addr;
830 int ret;
6aa8b732 831
dde7e6d1 832 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
6e3d5dfb 833
dde7e6d1
AK		 834 if (dt.size < index * 8 + 7) {
835 emulate_gp(ctxt, selector & 0xfffc);
836 return X86EMUL_PROPAGATE_FAULT;
837 }
6aa8b732 838
dde7e6d1
AK		 839 addr = dt.address + index * 8;
840 ret = ops->write_std(addr, desc, sizeof *desc, ctxt->vcpu, &err);
841 if (ret == X86EMUL_PROPAGATE_FAULT)
842 emulate_pf(ctxt, addr, err);
c7e75a3d 843
dde7e6d1
AK		 844 return ret;
845}
c7e75a3d 846
dde7e6d1
AK		 847static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
848 struct x86_emulate_ops *ops,
849 u16 selector, int seg)
850{
851 struct desc_struct seg_desc;
852 u8 dpl, rpl, cpl;
853 unsigned err_vec = GP_VECTOR;
854 u32 err_code = 0;
855 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
856 int ret;
69f55cb1 857
dde7e6d1 858 memset(&seg_desc, 0, sizeof seg_desc);
69f55cb1 859
dde7e6d1
AK		 860 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
861 || ctxt->mode == X86EMUL_MODE_REAL) {
862 /* set real mode segment descriptor */
863 set_desc_base(&seg_desc, selector << 4);
864 set_desc_limit(&seg_desc, 0xffff);
865 seg_desc.type = 3;
866 seg_desc.p = 1;
867 seg_desc.s = 1;
868 goto load;
869 }
870
871 /* NULL selector is not valid for TR, CS and SS */
872 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
873 && null_selector)
874 goto exception;
875
876 /* TR should be in GDT only */
877 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
878 goto exception;
879
880 if (null_selector) /* for NULL selector skip all following checks */
881 goto load;
882
883 ret = read_segment_descriptor(ctxt, ops, selector, &seg_desc);
884 if (ret != X86EMUL_CONTINUE)
885 return ret;
886
887 err_code = selector & 0xfffc;
888 err_vec = GP_VECTOR;
889
890 /* can't load system descriptor into segment selecor */
891 if (seg <= VCPU_SREG_GS && !seg_desc.s)
892 goto exception;
893
894 if (!seg_desc.p) {
895 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
896 goto exception;
897 }
898
899 rpl = selector & 3;
900 dpl = seg_desc.dpl;
901 cpl = ops->cpl(ctxt->vcpu);
902
903 switch (seg) {
904 case VCPU_SREG_SS:
905 /*
906 * segment is not a writable data segment or segment
907 * selector's RPL != CPL or segment selector's RPL != CPL
908 */
909 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
910 goto exception;
6aa8b732 911 break;
dde7e6d1
AK		 912 case VCPU_SREG_CS:
913 if (!(seg_desc.type & 8))
914 goto exception;
915
916 if (seg_desc.type & 4) {
917 /* conforming */
918 if (dpl > cpl)
919 goto exception;
920 } else {
921 /* nonconforming */
922 if (rpl > cpl || dpl != cpl)
923 goto exception;
924 }
925 /* CS(RPL) <- CPL */
926 selector = (selector & 0xfffc) | cpl;
6aa8b732 927 break;
dde7e6d1
AK		 928 case VCPU_SREG_TR:
929 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
930 goto exception;
931 break;
932 case VCPU_SREG_LDTR:
933 if (seg_desc.s || seg_desc.type != 2)
934 goto exception;
935 break;
936 default: /* DS, ES, FS, or GS */
4e62417b 937 /*
dde7e6d1
AK		 938 * segment is not a data or readable code segment or
939 * ((segment is a data or nonconforming code segment)
940 * and (both RPL and CPL > DPL))
4e62417b 941 */
dde7e6d1
AK		 942 if ((seg_desc.type & 0xa) == 0x8 ||
943 (((seg_desc.type & 0xc) != 0xc) &&
944 (rpl > dpl && cpl > dpl)))
945 goto exception;
6aa8b732 946 break;
dde7e6d1
AK		 947 }
948
949 if (seg_desc.s) {
950 /* mark segment as accessed */
951 seg_desc.type |= 1;
952 ret = write_segment_descriptor(ctxt, ops, selector, &seg_desc);
953 if (ret != X86EMUL_CONTINUE)
954 return ret;
955 }
956load:
957 ops->set_segment_selector(selector, seg, ctxt->vcpu);
958 ops->set_cached_descriptor(&seg_desc, seg, ctxt->vcpu);
959 return X86EMUL_CONTINUE;
960exception:
961 emulate_exception(ctxt, err_vec, err_code, true);
962 return X86EMUL_PROPAGATE_FAULT;
963}
964
965static inline int writeback(struct x86_emulate_ctxt *ctxt,
966 struct x86_emulate_ops *ops)
967{
968 int rc;
969 struct decode_cache *c = &ctxt->decode;
970 u32 err;
971
972 switch (c->dst.type) {
973 case OP_REG:
974 /* The 4-byte case *is* correct:
975 * in 64-bit mode we zero-extend.
976 */
977 switch (c->dst.bytes) {
6aa8b732 978 case 1:
dde7e6d1 979 *(u8 *)c->dst.ptr = (u8)c->dst.val;
6aa8b732
AK		 980 break;
981 case 2:
dde7e6d1 982 *(u16 *)c->dst.ptr = (u16)c->dst.val;
6aa8b732
AK		 983 break;
984 case 4:
dde7e6d1
AK		 985 *c->dst.ptr = (u32)c->dst.val;
986 break; /* 64b: zero-ext */
987 case 8:
988 *c->dst.ptr = c->dst.val;
6aa8b732
AK		 989 break;
990 }
991 break;
dde7e6d1
AK		 992 case OP_MEM:
993 if (c->lock_prefix)
994 rc = ops->cmpxchg_emulated(
995 (unsigned long)c->dst.ptr,
996 &c->dst.orig_val,
997 &c->dst.val,
998 c->dst.bytes,
999 &err,
1000 ctxt->vcpu);
341de7e3 1001 else
dde7e6d1
AK		 1002 rc = ops->write_emulated(
1003 (unsigned long)c->dst.ptr,
1004 &c->dst.val,
1005 c->dst.bytes,
1006 &err,
1007 ctxt->vcpu);
1008 if (rc == X86EMUL_PROPAGATE_FAULT)
1009 emulate_pf(ctxt,
1010 (unsigned long)c->dst.ptr, err);
1011 if (rc != X86EMUL_CONTINUE)
1012 return rc;
a682e354 1013 break;
dde7e6d1
AK		 1014 case OP_NONE:
1015 /* no writeback */
414e6277 1016 break;
dde7e6d1 1017 default:
414e6277 1018 break;
6aa8b732 1019 }
dde7e6d1
AK		 1020 return X86EMUL_CONTINUE;
1021}
6aa8b732 1022
dde7e6d1
AK		 1023static inline void emulate_push(struct x86_emulate_ctxt *ctxt,
1024 struct x86_emulate_ops *ops)
1025{
1026 struct decode_cache *c = &ctxt->decode;
0dc8d10f 1027
dde7e6d1
AK		 1028 c->dst.type = OP_MEM;
1029 c->dst.bytes = c->op_bytes;
1030 c->dst.val = c->src.val;
1031 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
1032 c->dst.ptr = (void *) register_address(c, ss_base(ctxt, ops),
1033 c->regs[VCPU_REGS_RSP]);
1034}
69f55cb1 1035
dde7e6d1
AK		 1036static int emulate_pop(struct x86_emulate_ctxt *ctxt,
1037 struct x86_emulate_ops *ops,
1038 void *dest, int len)
1039{
1040 struct decode_cache *c = &ctxt->decode;
1041 int rc;
8b4caf66 1042
dde7e6d1
AK		 1043 rc = read_emulated(ctxt, ops, register_address(c, ss_base(ctxt, ops),
1044 c->regs[VCPU_REGS_RSP]),
1045 dest, len);
1046 if (rc != X86EMUL_CONTINUE)
1047 return rc;
1048
1049 register_address_increment(c, &c->regs[VCPU_REGS_RSP], len);
1050 return rc;
8b4caf66
LV		 1051}
1052
dde7e6d1
AK		 1053static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1054 struct x86_emulate_ops *ops,
1055 void *dest, int len)
9de41573
GN		 1056{
1057 int rc;
dde7e6d1
AK		 1058 unsigned long val, change_mask;
1059 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1060 int cpl = ops->cpl(ctxt->vcpu);
9de41573 1061
dde7e6d1
AK		 1062 rc = emulate_pop(ctxt, ops, &val, len);
1063 if (rc != X86EMUL_CONTINUE)
1064 return rc;
9de41573 1065
dde7e6d1
AK		 1066 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1067 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
9de41573 1068
dde7e6d1
AK		 1069 switch(ctxt->mode) {
1070 case X86EMUL_MODE_PROT64:
1071 case X86EMUL_MODE_PROT32:
1072 case X86EMUL_MODE_PROT16:
1073 if (cpl == 0)
1074 change_mask |= EFLG_IOPL;
1075 if (cpl <= iopl)
1076 change_mask |= EFLG_IF;
1077 break;
1078 case X86EMUL_MODE_VM86:
1079 if (iopl < 3) {
1080 emulate_gp(ctxt, 0);
1081 return X86EMUL_PROPAGATE_FAULT;
1082 }
1083 change_mask |= EFLG_IF;
1084 break;
1085 default: /* real mode */
1086 change_mask |= (EFLG_IOPL | EFLG_IF);
1087 break;
9de41573 1088 }
dde7e6d1
AK		 1089
1090 *(unsigned long *)dest =
1091 (ctxt->eflags & ~change_mask) | (val & change_mask);
1092
1093 return rc;
9de41573
GN		 1094}
1095
dde7e6d1
AK		 1096static void emulate_push_sreg(struct x86_emulate_ctxt *ctxt,
1097 struct x86_emulate_ops *ops, int seg)
7b262e90 1098{
dde7e6d1 1099 struct decode_cache *c = &ctxt->decode;
7b262e90 1100
dde7e6d1 1101 c->src.val = ops->get_segment_selector(seg, ctxt->vcpu);
7b262e90 1102
dde7e6d1 1103 emulate_push(ctxt, ops);
7b262e90
GN		 1104}
1105
dde7e6d1
AK		 1106static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt,
1107 struct x86_emulate_ops *ops, int seg)
38ba30ba 1108{
dde7e6d1
AK		 1109 struct decode_cache *c = &ctxt->decode;
1110 unsigned long selector;
1111 int rc;
38ba30ba 1112
dde7e6d1
AK		 1113 rc = emulate_pop(ctxt, ops, &selector, c->op_bytes);
1114 if (rc != X86EMUL_CONTINUE)
1115 return rc;
1116
1117 rc = load_segment_descriptor(ctxt, ops, (u16)selector, seg);
1118 return rc;
38ba30ba
GN		 1119}
1120
dde7e6d1
AK		 1121static int emulate_pusha(struct x86_emulate_ctxt *ctxt,
1122 struct x86_emulate_ops *ops)
38ba30ba 1123{
dde7e6d1
AK		 1124 struct decode_cache *c = &ctxt->decode;
1125 unsigned long old_esp = c->regs[VCPU_REGS_RSP];
1126 int rc = X86EMUL_CONTINUE;
1127 int reg = VCPU_REGS_RAX;
38ba30ba 1128
dde7e6d1
AK		 1129 while (reg <= VCPU_REGS_RDI) {
1130 (reg == VCPU_REGS_RSP) ?
1131 (c->src.val = old_esp) : (c->src.val = c->regs[reg]);
38ba30ba 1132
dde7e6d1 1133 emulate_push(ctxt, ops);
38ba30ba 1134
dde7e6d1
AK		 1135 rc = writeback(ctxt, ops);
1136 if (rc != X86EMUL_CONTINUE)
1137 return rc;
38ba30ba 1138
dde7e6d1 1139 ++reg;
38ba30ba 1140 }
38ba30ba 1141
dde7e6d1
AK		 1142 /* Disable writeback. */
1143 c->dst.type = OP_NONE;
1144
1145 return rc;
38ba30ba
GN		 1146}
1147
dde7e6d1
AK		 1148static int emulate_popa(struct x86_emulate_ctxt *ctxt,
1149 struct x86_emulate_ops *ops)
38ba30ba 1150{
dde7e6d1
AK		 1151 struct decode_cache *c = &ctxt->decode;
1152 int rc = X86EMUL_CONTINUE;
1153 int reg = VCPU_REGS_RDI;
38ba30ba 1154
dde7e6d1
AK		 1155 while (reg >= VCPU_REGS_RAX) {
1156 if (reg == VCPU_REGS_RSP) {
1157 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
1158 c->op_bytes);
1159 --reg;
1160 }
38ba30ba 1161
dde7e6d1
AK		 1162 rc = emulate_pop(ctxt, ops, &c->regs[reg], c->op_bytes);
1163 if (rc != X86EMUL_CONTINUE)
1164 break;
1165 --reg;
38ba30ba 1166 }
dde7e6d1 1167 return rc;
38ba30ba
GN		 1168}
1169
dde7e6d1
AK		 1170static int emulate_iret_real(struct x86_emulate_ctxt *ctxt,
1171 struct x86_emulate_ops *ops)
38ba30ba 1172{
dde7e6d1
AK		 1173 struct decode_cache *c = &ctxt->decode;
1174 int rc = X86EMUL_CONTINUE;
1175 unsigned long temp_eip = 0;
1176 unsigned long temp_eflags = 0;
1177 unsigned long cs = 0;
1178 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1179 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1180 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1181 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
38ba30ba 1182
dde7e6d1 1183 /* TODO: Add stack limit check */
38ba30ba 1184
dde7e6d1 1185 rc = emulate_pop(ctxt, ops, &temp_eip, c->op_bytes);
38ba30ba 1186
dde7e6d1
AK		 1187 if (rc != X86EMUL_CONTINUE)
1188 return rc;
38ba30ba 1189
dde7e6d1
AK		 1190 if (temp_eip & ~0xffff) {
1191 emulate_gp(ctxt, 0);
1192 return X86EMUL_PROPAGATE_FAULT;
1193 }
38ba30ba 1194
dde7e6d1 1195 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
38ba30ba 1196
dde7e6d1
AK		 1197 if (rc != X86EMUL_CONTINUE)
1198 return rc;
38ba30ba 1199
dde7e6d1 1200 rc = emulate_pop(ctxt, ops, &temp_eflags, c->op_bytes);
38ba30ba 1201
dde7e6d1
AK		 1202 if (rc != X86EMUL_CONTINUE)
1203 return rc;
38ba30ba 1204
dde7e6d1 1205 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
38ba30ba 1206
dde7e6d1
AK		 1207 if (rc != X86EMUL_CONTINUE)
1208 return rc;
38ba30ba 1209
dde7e6d1 1210 c->eip = temp_eip;
38ba30ba 1211
38ba30ba 1212
dde7e6d1
AK		 1213 if (c->op_bytes == 4)
1214 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
1215 else if (c->op_bytes == 2) {
1216 ctxt->eflags &= ~0xffff;
1217 ctxt->eflags |= temp_eflags;
38ba30ba 1218 }
dde7e6d1
AK		 1219
1220 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1221 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1222
1223 return rc;
38ba30ba
GN		 1224}
1225
dde7e6d1
AK		 1226static inline int emulate_iret(struct x86_emulate_ctxt *ctxt,
1227 struct x86_emulate_ops* ops)
c37eda13 1228{
dde7e6d1
AK		 1229 switch(ctxt->mode) {
1230 case X86EMUL_MODE_REAL:
1231 return emulate_iret_real(ctxt, ops);
1232 case X86EMUL_MODE_VM86:
1233 case X86EMUL_MODE_PROT16:
1234 case X86EMUL_MODE_PROT32:
1235 case X86EMUL_MODE_PROT64:
c37eda13 1236 default:
dde7e6d1
AK		 1237 /* iret from protected mode unimplemented yet */
1238 return X86EMUL_UNHANDLEABLE;
c37eda13 1239 }
c37eda13
WY		 1240}
1241
dde7e6d1 1242static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
79168fd1 1243 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1244{
1245 struct decode_cache *c = &ctxt->decode;
1246
dde7e6d1 1247 return emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes);
8cdbd2c9
LV		 1248}
1249
dde7e6d1 1250static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1251{
05f086f8 1252 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1253 switch (c->modrm_reg) {
1254 case 0: /* rol */
05f086f8 1255 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1256 break;
1257 case 1: /* ror */
05f086f8 1258 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1259 break;
1260 case 2: /* rcl */
05f086f8 1261 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1262 break;
1263 case 3: /* rcr */
05f086f8 1264 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1265 break;
1266 case 4: /* sal/shl */
1267 case 6: /* sal/shl */
05f086f8 1268 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1269 break;
1270 case 5: /* shr */
05f086f8 1271 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1272 break;
1273 case 7: /* sar */
05f086f8 1274 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1275 break;
1276 }
1277}
1278
1279static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
05f086f8 1280 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1281{
1282 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1283
1284 switch (c->modrm_reg) {
1285 case 0 ... 1: /* test */
05f086f8 1286 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1287 break;
1288 case 2: /* not */
1289 c->dst.val = ~c->dst.val;
1290 break;
1291 case 3: /* neg */
05f086f8 1292 emulate_1op("neg", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1293 break;
1294 default:
aca06a83 1295 return 0;
8cdbd2c9 1296 }
aca06a83 1297 return 1;
8cdbd2c9
LV		 1298}
1299
1300static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
a01af5ec 1301 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1302{
1303 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1304
1305 switch (c->modrm_reg) {
1306 case 0: /* inc */
05f086f8 1307 emulate_1op("inc", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1308 break;
1309 case 1: /* dec */
05f086f8 1310 emulate_1op("dec", c->dst, ctxt->eflags);
8cdbd2c9 1311 break;
d19292e4
MG		 1312 case 2: /* call near abs */ {
1313 long int old_eip;
1314 old_eip = c->eip;
1315 c->eip = c->src.val;
1316 c->src.val = old_eip;
79168fd1 1317 emulate_push(ctxt, ops);
d19292e4
MG		 1318 break;
1319 }
8cdbd2c9 1320 case 4: /* jmp abs */
fd60754e 1321 c->eip = c->src.val;
8cdbd2c9
LV		 1322 break;
1323 case 6: /* push */
79168fd1 1324 emulate_push(ctxt, ops);
8cdbd2c9 1325 break;
8cdbd2c9 1326 }
1b30eaa8 1327 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1328}
1329
1330static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
69f55cb1 1331 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1332{
1333 struct decode_cache *c = &ctxt->decode;
16518d5a 1334 u64 old = c->dst.orig_val64;
8cdbd2c9
LV		 1335
1336 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1337 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
8cdbd2c9
LV		 1338 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1339 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1340 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9 1341 } else {
16518d5a
AK		 1342 c->dst.val64 = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1343 (u32) c->regs[VCPU_REGS_RBX];
8cdbd2c9 1344
05f086f8 1345 ctxt->eflags |= EFLG_ZF;
8cdbd2c9 1346 }
1b30eaa8 1347 return X86EMUL_CONTINUE;
8cdbd2c9
LV		 1348}
1349
a77ab5ea
AK		 1350static int emulate_ret_far(struct x86_emulate_ctxt *ctxt,
1351 struct x86_emulate_ops *ops)
1352{
1353 struct decode_cache *c = &ctxt->decode;
1354 int rc;
1355 unsigned long cs;
1356
1357 rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes);
1b30eaa8 1358 if (rc != X86EMUL_CONTINUE)
a77ab5ea
AK		 1359 return rc;
1360 if (c->op_bytes == 4)
1361 c->eip = (u32)c->eip;
1362 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1b30eaa8 1363 if (rc != X86EMUL_CONTINUE)
a77ab5ea 1364 return rc;
2e873022 1365 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
a77ab5ea
AK		 1366 return rc;
1367}
1368
e66bb2cc
AP		 1369static inline void
1370setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
79168fd1
GN		 1371 struct x86_emulate_ops *ops, struct desc_struct *cs,
1372 struct desc_struct *ss)
e66bb2cc 1373{
79168fd1
GN		 1374 memset(cs, 0, sizeof(struct desc_struct));
1375 ops->get_cached_descriptor(cs, VCPU_SREG_CS, ctxt->vcpu);
1376 memset(ss, 0, sizeof(struct desc_struct));
e66bb2cc
AP		 1377
1378 cs->l = 0; /* will be adjusted later */
79168fd1 1379 set_desc_base(cs, 0); /* flat segment */
e66bb2cc 1380 cs->g = 1; /* 4kb granularity */
79168fd1 1381 set_desc_limit(cs, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1382 cs->type = 0x0b; /* Read, Execute, Accessed */
1383 cs->s = 1;
1384 cs->dpl = 0; /* will be adjusted later */
79168fd1
GN		 1385 cs->p = 1;
1386 cs->d = 1;
e66bb2cc 1387
79168fd1
GN		 1388 set_desc_base(ss, 0); /* flat segment */
1389 set_desc_limit(ss, 0xfffff); /* 4GB limit */
e66bb2cc
AP		 1390 ss->g = 1; /* 4kb granularity */
1391 ss->s = 1;
1392 ss->type = 0x03; /* Read/Write, Accessed */
79168fd1 1393 ss->d = 1; /* 32bit stack segment */
e66bb2cc 1394 ss->dpl = 0;
79168fd1 1395 ss->p = 1;
e66bb2cc
AP		 1396}
1397
1398static int
3fb1b5db 1399emulate_syscall(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
e66bb2cc
AP		 1400{
1401 struct decode_cache *c = &ctxt->decode;
79168fd1 1402 struct desc_struct cs, ss;
e66bb2cc 1403 u64 msr_data;
79168fd1 1404 u16 cs_sel, ss_sel;
e66bb2cc
AP		 1405
1406 /* syscall is not available in real mode */
2e901c4c
GN		 1407 if (ctxt->mode == X86EMUL_MODE_REAL ||
1408 ctxt->mode == X86EMUL_MODE_VM86) {
54b8486f 1409 emulate_ud(ctxt);
2e901c4c
GN		 1410 return X86EMUL_PROPAGATE_FAULT;
1411 }
e66bb2cc 1412
79168fd1 1413 setup_syscalls_segments(ctxt, ops, &cs, &ss);
e66bb2cc 1414
3fb1b5db 1415 ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
e66bb2cc 1416 msr_data >>= 32;
79168fd1
GN		 1417 cs_sel = (u16)(msr_data & 0xfffc);
1418 ss_sel = (u16)(msr_data + 8);
e66bb2cc
AP		 1419
1420 if (is_long_mode(ctxt->vcpu)) {
79168fd1 1421 cs.d = 0;
e66bb2cc
AP		 1422 cs.l = 1;
1423 }
79168fd1
GN		 1424 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
1425 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
1426 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
1427 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
e66bb2cc
AP		 1428
1429 c->regs[VCPU_REGS_RCX] = c->eip;
1430 if (is_long_mode(ctxt->vcpu)) {
1431#ifdef CONFIG_X86_64
1432 c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
1433
3fb1b5db
GN		 1434 ops->get_msr(ctxt->vcpu,
1435 ctxt->mode == X86EMUL_MODE_PROT64 ?
1436 MSR_LSTAR : MSR_CSTAR, &msr_data);
e66bb2cc
AP		 1437 c->eip = msr_data;
1438
3fb1b5db 1439 ops->get_msr(ctxt->vcpu, MSR_SYSCALL_MASK, &msr_data);
e66bb2cc
AP		 1440 ctxt->eflags &= ~(msr_data | EFLG_RF);
1441#endif
1442 } else {
1443 /* legacy mode */
3fb1b5db 1444 ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
e66bb2cc
AP		 1445 c->eip = (u32)msr_data;
1446
1447 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1448 }
1449
e54cfa97 1450 return X86EMUL_CONTINUE;
e66bb2cc
AP		 1451}
1452
8c604352 1453static int
3fb1b5db 1454emulate_sysenter(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8c604352
AP		 1455{
1456 struct decode_cache *c = &ctxt->decode;
79168fd1 1457 struct desc_struct cs, ss;
8c604352 1458 u64 msr_data;
79168fd1 1459 u16 cs_sel, ss_sel;
8c604352 1460
a0044755
GN		 1461 /* inject #GP if in real mode */
1462 if (ctxt->mode == X86EMUL_MODE_REAL) {
54b8486f 1463 emulate_gp(ctxt, 0);
2e901c4c 1464 return X86EMUL_PROPAGATE_FAULT;
8c604352
AP		 1465 }
1466
1467 /* XXX sysenter/sysexit have not been tested in 64bit mode.
1468 * Therefore, we inject an #UD.
1469 */
2e901c4c 1470 if (ctxt->mode == X86EMUL_MODE_PROT64) {
54b8486f 1471 emulate_ud(ctxt);
2e901c4c
GN		 1472 return X86EMUL_PROPAGATE_FAULT;
1473 }
8c604352 1474
79168fd1 1475 setup_syscalls_segments(ctxt, ops, &cs, &ss);
8c604352 1476
3fb1b5db 1477 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
8c604352
AP		 1478 switch (ctxt->mode) {
1479 case X86EMUL_MODE_PROT32:
1480 if ((msr_data & 0xfffc) == 0x0) {
54b8486f 1481 emulate_gp(ctxt, 0);
e54cfa97 1482 return X86EMUL_PROPAGATE_FAULT;
8c604352
AP		 1483 }
1484 break;
1485 case X86EMUL_MODE_PROT64:
1486 if (msr_data == 0x0) {
54b8486f 1487 emulate_gp(ctxt, 0);
e54cfa97 1488 return X86EMUL_PROPAGATE_FAULT;
8c604352
AP		 1489 }
1490 break;
1491 }
1492
1493 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
79168fd1
GN		 1494 cs_sel = (u16)msr_data;
1495 cs_sel &= ~SELECTOR_RPL_MASK;
1496 ss_sel = cs_sel + 8;
1497 ss_sel &= ~SELECTOR_RPL_MASK;
8c604352
AP		 1498 if (ctxt->mode == X86EMUL_MODE_PROT64
1499 || is_long_mode(ctxt->vcpu)) {
79168fd1 1500 cs.d = 0;
8c604352
AP		 1501 cs.l = 1;
1502 }
1503
79168fd1
GN		 1504 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
1505 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
1506 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
1507 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
8c604352 1508
3fb1b5db 1509 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_EIP, &msr_data);
8c604352
AP		 1510 c->eip = msr_data;
1511
3fb1b5db 1512 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_ESP, &msr_data);
8c604352
AP		 1513 c->regs[VCPU_REGS_RSP] = msr_data;
1514
e54cfa97 1515 return X86EMUL_CONTINUE;
8c604352
AP		 1516}
1517
4668f050 1518static int
3fb1b5db 1519emulate_sysexit(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
4668f050
AP		 1520{
1521 struct decode_cache *c = &ctxt->decode;
79168fd1 1522 struct desc_struct cs, ss;
4668f050
AP		 1523 u64 msr_data;
1524 int usermode;
79168fd1 1525 u16 cs_sel, ss_sel;
4668f050 1526
a0044755
GN		 1527 /* inject #GP if in real mode or Virtual 8086 mode */
1528 if (ctxt->mode == X86EMUL_MODE_REAL ||
1529 ctxt->mode == X86EMUL_MODE_VM86) {
54b8486f 1530 emulate_gp(ctxt, 0);
2e901c4c 1531 return X86EMUL_PROPAGATE_FAULT;
4668f050
AP		 1532 }
1533
79168fd1 1534 setup_syscalls_segments(ctxt, ops, &cs, &ss);
4668f050
AP		 1535
1536 if ((c->rex_prefix & 0x8) != 0x0)
1537 usermode = X86EMUL_MODE_PROT64;
1538 else
1539 usermode = X86EMUL_MODE_PROT32;
1540
1541 cs.dpl = 3;
1542 ss.dpl = 3;
3fb1b5db 1543 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
4668f050
AP		 1544 switch (usermode) {
1545 case X86EMUL_MODE_PROT32:
79168fd1 1546 cs_sel = (u16)(msr_data + 16);
4668f050 1547 if ((msr_data & 0xfffc) == 0x0) {
54b8486f 1548 emulate_gp(ctxt, 0);
e54cfa97 1549 return X86EMUL_PROPAGATE_FAULT;
4668f050 1550 }
79168fd1 1551 ss_sel = (u16)(msr_data + 24);
4668f050
AP		 1552 break;
1553 case X86EMUL_MODE_PROT64:
79168fd1 1554 cs_sel = (u16)(msr_data + 32);
4668f050 1555 if (msr_data == 0x0) {
54b8486f 1556 emulate_gp(ctxt, 0);
e54cfa97 1557 return X86EMUL_PROPAGATE_FAULT;
4668f050 1558 }
79168fd1
GN		 1559 ss_sel = cs_sel + 8;
1560 cs.d = 0;
4668f050
AP		 1561 cs.l = 1;
1562 break;
1563 }
79168fd1
GN		 1564 cs_sel |= SELECTOR_RPL_MASK;
1565 ss_sel |= SELECTOR_RPL_MASK;
4668f050 1566
79168fd1
GN		 1567 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
1568 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
1569 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
1570 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
4668f050 1571
bdb475a3
GN		 1572 c->eip = c->regs[VCPU_REGS_RDX];
1573 c->regs[VCPU_REGS_RSP] = c->regs[VCPU_REGS_RCX];
4668f050 1574
e54cfa97 1575 return X86EMUL_CONTINUE;
4668f050
AP		 1576}
1577
9c537244
GN		 1578static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt,
1579 struct x86_emulate_ops *ops)
f850e2e6
GN		 1580{
1581 int iopl;
1582 if (ctxt->mode == X86EMUL_MODE_REAL)
1583 return false;
1584 if (ctxt->mode == X86EMUL_MODE_VM86)
1585 return true;
1586 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
9c537244 1587 return ops->cpl(ctxt->vcpu) > iopl;
f850e2e6
GN		 1588}
1589
1590static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
1591 struct x86_emulate_ops *ops,
1592 u16 port, u16 len)
1593{
79168fd1 1594 struct desc_struct tr_seg;
f850e2e6
GN		 1595 int r;
1596 u16 io_bitmap_ptr;
1597 u8 perm, bit_idx = port & 0x7;
1598 unsigned mask = (1 << len) - 1;
1599
79168fd1
GN		 1600 ops->get_cached_descriptor(&tr_seg, VCPU_SREG_TR, ctxt->vcpu);
1601 if (!tr_seg.p)
f850e2e6 1602 return false;
79168fd1 1603 if (desc_limit_scaled(&tr_seg) < 103)
f850e2e6 1604 return false;
79168fd1
GN		 1605 r = ops->read_std(get_desc_base(&tr_seg) + 102, &io_bitmap_ptr, 2,
1606 ctxt->vcpu, NULL);
f850e2e6
GN		 1607 if (r != X86EMUL_CONTINUE)
1608 return false;
79168fd1 1609 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
f850e2e6 1610 return false;
79168fd1
GN		 1611 r = ops->read_std(get_desc_base(&tr_seg) + io_bitmap_ptr + port/8,
1612 &perm, 1, ctxt->vcpu, NULL);
f850e2e6
GN		 1613 if (r != X86EMUL_CONTINUE)
1614 return false;
1615 if ((perm >> bit_idx) & mask)
1616 return false;
1617 return true;
1618}
1619
1620static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
1621 struct x86_emulate_ops *ops,
1622 u16 port, u16 len)
1623{
9c537244 1624 if (emulator_bad_iopl(ctxt, ops))
f850e2e6
GN		 1625 if (!emulator_io_port_access_allowed(ctxt, ops, port, len))
1626 return false;
1627 return true;
1628}
1629
38ba30ba
GN		 1630static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
1631 struct x86_emulate_ops *ops,
1632 struct tss_segment_16 *tss)
1633{
1634 struct decode_cache *c = &ctxt->decode;
1635
1636 tss->ip = c->eip;
1637 tss->flag = ctxt->eflags;
1638 tss->ax = c->regs[VCPU_REGS_RAX];
1639 tss->cx = c->regs[VCPU_REGS_RCX];
1640 tss->dx = c->regs[VCPU_REGS_RDX];
1641 tss->bx = c->regs[VCPU_REGS_RBX];
1642 tss->sp = c->regs[VCPU_REGS_RSP];
1643 tss->bp = c->regs[VCPU_REGS_RBP];
1644 tss->si = c->regs[VCPU_REGS_RSI];
1645 tss->di = c->regs[VCPU_REGS_RDI];
1646
1647 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
1648 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
1649 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
1650 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
1651 tss->ldt = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
1652}
1653
1654static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
1655 struct x86_emulate_ops *ops,
1656 struct tss_segment_16 *tss)
1657{
1658 struct decode_cache *c = &ctxt->decode;
1659 int ret;
1660
1661 c->eip = tss->ip;
1662 ctxt->eflags = tss->flag | 2;
1663 c->regs[VCPU_REGS_RAX] = tss->ax;
1664 c->regs[VCPU_REGS_RCX] = tss->cx;
1665 c->regs[VCPU_REGS_RDX] = tss->dx;
1666 c->regs[VCPU_REGS_RBX] = tss->bx;
1667 c->regs[VCPU_REGS_RSP] = tss->sp;
1668 c->regs[VCPU_REGS_RBP] = tss->bp;
1669 c->regs[VCPU_REGS_RSI] = tss->si;
1670 c->regs[VCPU_REGS_RDI] = tss->di;
1671
1672 /*
1673 * SDM says that segment selectors are loaded before segment
1674 * descriptors
1675 */
1676 ops->set_segment_selector(tss->ldt, VCPU_SREG_LDTR, ctxt->vcpu);
1677 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
1678 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
1679 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
1680 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
1681
1682 /*
1683 * Now load segment descriptors. If fault happenes at this stage
1684 * it is handled in a context of new task
1685 */
1686 ret = load_segment_descriptor(ctxt, ops, tss->ldt, VCPU_SREG_LDTR);
1687 if (ret != X86EMUL_CONTINUE)
1688 return ret;
1689 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
1690 if (ret != X86EMUL_CONTINUE)
1691 return ret;
1692 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
1693 if (ret != X86EMUL_CONTINUE)
1694 return ret;
1695 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
1696 if (ret != X86EMUL_CONTINUE)
1697 return ret;
1698 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
1699 if (ret != X86EMUL_CONTINUE)
1700 return ret;
1701
1702 return X86EMUL_CONTINUE;
1703}
1704
1705static int task_switch_16(struct x86_emulate_ctxt *ctxt,
1706 struct x86_emulate_ops *ops,
1707 u16 tss_selector, u16 old_tss_sel,
1708 ulong old_tss_base, struct desc_struct *new_desc)
1709{
1710 struct tss_segment_16 tss_seg;
1711 int ret;
1712 u32 err, new_tss_base = get_desc_base(new_desc);
1713
1714 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
1715 &err);
1716 if (ret == X86EMUL_PROPAGATE_FAULT) {
1717 /* FIXME: need to provide precise fault address */
54b8486f 1718 emulate_pf(ctxt, old_tss_base, err);
38ba30ba
GN		 1719 return ret;
1720 }
1721
1722 save_state_to_tss16(ctxt, ops, &tss_seg);
1723
1724 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
1725 &err);
1726 if (ret == X86EMUL_PROPAGATE_FAULT) {
1727 /* FIXME: need to provide precise fault address */
54b8486f 1728 emulate_pf(ctxt, old_tss_base, err);
38ba30ba
GN		 1729 return ret;
1730 }
1731
1732 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
1733 &err);
1734 if (ret == X86EMUL_PROPAGATE_FAULT) {
1735 /* FIXME: need to provide precise fault address */
54b8486f 1736 emulate_pf(ctxt, new_tss_base, err);
38ba30ba
GN		 1737 return ret;
1738 }
1739
1740 if (old_tss_sel != 0xffff) {
1741 tss_seg.prev_task_link = old_tss_sel;
1742
1743 ret = ops->write_std(new_tss_base,
1744 &tss_seg.prev_task_link,
1745 sizeof tss_seg.prev_task_link,
1746 ctxt->vcpu, &err);
1747 if (ret == X86EMUL_PROPAGATE_FAULT) {
1748 /* FIXME: need to provide precise fault address */
54b8486f 1749 emulate_pf(ctxt, new_tss_base, err);
38ba30ba
GN		 1750 return ret;
1751 }
1752 }
1753
1754 return load_state_from_tss16(ctxt, ops, &tss_seg);
1755}
1756
1757static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
1758 struct x86_emulate_ops *ops,
1759 struct tss_segment_32 *tss)
1760{
1761 struct decode_cache *c = &ctxt->decode;
1762
1763 tss->cr3 = ops->get_cr(3, ctxt->vcpu);
1764 tss->eip = c->eip;
1765 tss->eflags = ctxt->eflags;
1766 tss->eax = c->regs[VCPU_REGS_RAX];
1767 tss->ecx = c->regs[VCPU_REGS_RCX];
1768 tss->edx = c->regs[VCPU_REGS_RDX];
1769 tss->ebx = c->regs[VCPU_REGS_RBX];
1770 tss->esp = c->regs[VCPU_REGS_RSP];
1771 tss->ebp = c->regs[VCPU_REGS_RBP];
1772 tss->esi = c->regs[VCPU_REGS_RSI];
1773 tss->edi = c->regs[VCPU_REGS_RDI];
1774
1775 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
1776 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
1777 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
1778 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
1779 tss->fs = ops->get_segment_selector(VCPU_SREG_FS, ctxt->vcpu);
1780 tss->gs = ops->get_segment_selector(VCPU_SREG_GS, ctxt->vcpu);
1781 tss->ldt_selector = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
1782}
1783
1784static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
1785 struct x86_emulate_ops *ops,
1786 struct tss_segment_32 *tss)
1787{
1788 struct decode_cache *c = &ctxt->decode;
1789 int ret;
1790
0f12244f 1791 if (ops->set_cr(3, tss->cr3, ctxt->vcpu)) {
54b8486f 1792 emulate_gp(ctxt, 0);
0f12244f
GN		 1793 return X86EMUL_PROPAGATE_FAULT;
1794 }
38ba30ba
GN		 1795 c->eip = tss->eip;
1796 ctxt->eflags = tss->eflags | 2;
1797 c->regs[VCPU_REGS_RAX] = tss->eax;
1798 c->regs[VCPU_REGS_RCX] = tss->ecx;
1799 c->regs[VCPU_REGS_RDX] = tss->edx;
1800 c->regs[VCPU_REGS_RBX] = tss->ebx;
1801 c->regs[VCPU_REGS_RSP] = tss->esp;
1802 c->regs[VCPU_REGS_RBP] = tss->ebp;
1803 c->regs[VCPU_REGS_RSI] = tss->esi;
1804 c->regs[VCPU_REGS_RDI] = tss->edi;
1805
1806 /*
1807 * SDM says that segment selectors are loaded before segment
1808 * descriptors
1809 */
1810 ops->set_segment_selector(tss->ldt_selector, VCPU_SREG_LDTR, ctxt->vcpu);
1811 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
1812 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
1813 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
1814 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
1815 ops->set_segment_selector(tss->fs, VCPU_SREG_FS, ctxt->vcpu);
1816 ops->set_segment_selector(tss->gs, VCPU_SREG_GS, ctxt->vcpu);
1817
1818 /*
1819 * Now load segment descriptors. If fault happenes at this stage
1820 * it is handled in a context of new task
1821 */
1822 ret = load_segment_descriptor(ctxt, ops, tss->ldt_selector, VCPU_SREG_LDTR);
1823 if (ret != X86EMUL_CONTINUE)
1824 return ret;
1825 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
1826 if (ret != X86EMUL_CONTINUE)
1827 return ret;
1828 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
1829 if (ret != X86EMUL_CONTINUE)
1830 return ret;
1831 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
1832 if (ret != X86EMUL_CONTINUE)
1833 return ret;
1834 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
1835 if (ret != X86EMUL_CONTINUE)
1836 return ret;
1837 ret = load_segment_descriptor(ctxt, ops, tss->fs, VCPU_SREG_FS);
1838 if (ret != X86EMUL_CONTINUE)
1839 return ret;
1840 ret = load_segment_descriptor(ctxt, ops, tss->gs, VCPU_SREG_GS);
1841 if (ret != X86EMUL_CONTINUE)
1842 return ret;
1843
1844 return X86EMUL_CONTINUE;
1845}
1846
1847static int task_switch_32(struct x86_emulate_ctxt *ctxt,
1848 struct x86_emulate_ops *ops,
1849 u16 tss_selector, u16 old_tss_sel,
1850 ulong old_tss_base, struct desc_struct *new_desc)
1851{
1852 struct tss_segment_32 tss_seg;
1853 int ret;
1854 u32 err, new_tss_base = get_desc_base(new_desc);
1855
1856 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
1857 &err);
1858 if (ret == X86EMUL_PROPAGATE_FAULT) {
1859 /* FIXME: need to provide precise fault address */
54b8486f 1860 emulate_pf(ctxt, old_tss_base, err);
38ba30ba
GN		 1861 return ret;
1862 }
1863
1864 save_state_to_tss32(ctxt, ops, &tss_seg);
1865
1866 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
1867 &err);
1868 if (ret == X86EMUL_PROPAGATE_FAULT) {
1869 /* FIXME: need to provide precise fault address */
54b8486f 1870 emulate_pf(ctxt, old_tss_base, err);
38ba30ba
GN		 1871 return ret;
1872 }
1873
1874 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
1875 &err);
1876 if (ret == X86EMUL_PROPAGATE_FAULT) {
1877 /* FIXME: need to provide precise fault address */
54b8486f 1878 emulate_pf(ctxt, new_tss_base, err);
38ba30ba
GN		 1879 return ret;
1880 }
1881
1882 if (old_tss_sel != 0xffff) {
1883 tss_seg.prev_task_link = old_tss_sel;
1884
1885 ret = ops->write_std(new_tss_base,
1886 &tss_seg.prev_task_link,
1887 sizeof tss_seg.prev_task_link,
1888 ctxt->vcpu, &err);
1889 if (ret == X86EMUL_PROPAGATE_FAULT) {
1890 /* FIXME: need to provide precise fault address */
54b8486f 1891 emulate_pf(ctxt, new_tss_base, err);
38ba30ba
GN		 1892 return ret;
1893 }
1894 }
1895
1896 return load_state_from_tss32(ctxt, ops, &tss_seg);
1897}
1898
1899static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 1900 struct x86_emulate_ops *ops,
1901 u16 tss_selector, int reason,
1902 bool has_error_code, u32 error_code)
38ba30ba
GN		 1903{
1904 struct desc_struct curr_tss_desc, next_tss_desc;
1905 int ret;
1906 u16 old_tss_sel = ops->get_segment_selector(VCPU_SREG_TR, ctxt->vcpu);
1907 ulong old_tss_base =
5951c442 1908 ops->get_cached_segment_base(VCPU_SREG_TR, ctxt->vcpu);
ceffb459 1909 u32 desc_limit;
38ba30ba
GN		 1910
1911 /* FIXME: old_tss_base == ~0 ? */
1912
1913 ret = read_segment_descriptor(ctxt, ops, tss_selector, &next_tss_desc);
1914 if (ret != X86EMUL_CONTINUE)
1915 return ret;
1916 ret = read_segment_descriptor(ctxt, ops, old_tss_sel, &curr_tss_desc);
1917 if (ret != X86EMUL_CONTINUE)
1918 return ret;
1919
1920 /* FIXME: check that next_tss_desc is tss */
1921
1922 if (reason != TASK_SWITCH_IRET) {
1923 if ((tss_selector & 3) > next_tss_desc.dpl ||
1924 ops->cpl(ctxt->vcpu) > next_tss_desc.dpl) {
54b8486f 1925 emulate_gp(ctxt, 0);
38ba30ba
GN		 1926 return X86EMUL_PROPAGATE_FAULT;
1927 }
1928 }
1929
ceffb459
GN		 1930 desc_limit = desc_limit_scaled(&next_tss_desc);
1931 if (!next_tss_desc.p ||
1932 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
1933 desc_limit < 0x2b)) {
54b8486f 1934 emulate_ts(ctxt, tss_selector & 0xfffc);
38ba30ba
GN		 1935 return X86EMUL_PROPAGATE_FAULT;
1936 }
1937
1938 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
1939 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
1940 write_segment_descriptor(ctxt, ops, old_tss_sel,
1941 &curr_tss_desc);
1942 }
1943
1944 if (reason == TASK_SWITCH_IRET)
1945 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
1946
1947 /* set back link to prev task only if NT bit is set in eflags
1948 note that old_tss_sel is not used afetr this point */
1949 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
1950 old_tss_sel = 0xffff;
1951
1952 if (next_tss_desc.type & 8)
1953 ret = task_switch_32(ctxt, ops, tss_selector, old_tss_sel,
1954 old_tss_base, &next_tss_desc);
1955 else
1956 ret = task_switch_16(ctxt, ops, tss_selector, old_tss_sel,
1957 old_tss_base, &next_tss_desc);
0760d448
JK		 1958 if (ret != X86EMUL_CONTINUE)
1959 return ret;
38ba30ba
GN		 1960
1961 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
1962 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
1963
1964 if (reason != TASK_SWITCH_IRET) {
1965 next_tss_desc.type |= (1 << 1); /* set busy flag */
1966 write_segment_descriptor(ctxt, ops, tss_selector,
1967 &next_tss_desc);
1968 }
1969
1970 ops->set_cr(0, ops->get_cr(0, ctxt->vcpu) | X86_CR0_TS, ctxt->vcpu);
1971 ops->set_cached_descriptor(&next_tss_desc, VCPU_SREG_TR, ctxt->vcpu);
1972 ops->set_segment_selector(tss_selector, VCPU_SREG_TR, ctxt->vcpu);
1973
e269fb21
JK		 1974 if (has_error_code) {
1975 struct decode_cache *c = &ctxt->decode;
1976
1977 c->op_bytes = c->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
1978 c->lock_prefix = 0;
1979 c->src.val = (unsigned long) error_code;
79168fd1 1980 emulate_push(ctxt, ops);
e269fb21
JK		 1981 }
1982
38ba30ba
GN		 1983 return ret;
1984}
1985
1986int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
e269fb21
JK		 1987 u16 tss_selector, int reason,
1988 bool has_error_code, u32 error_code)
38ba30ba 1989{
9aabc88f 1990 struct x86_emulate_ops *ops = ctxt->ops;
38ba30ba
GN		 1991 struct decode_cache *c = &ctxt->decode;
1992 int rc;
1993
38ba30ba 1994 c->eip = ctxt->eip;
e269fb21 1995 c->dst.type = OP_NONE;
38ba30ba 1996
e269fb21
JK		 1997 rc = emulator_do_task_switch(ctxt, ops, tss_selector, reason,
1998 has_error_code, error_code);
38ba30ba
GN		 1999
2000 if (rc == X86EMUL_CONTINUE) {
e269fb21 2001 rc = writeback(ctxt, ops);
95c55886
GN		 2002 if (rc == X86EMUL_CONTINUE)
2003 ctxt->eip = c->eip;
38ba30ba
GN		 2004 }
2005
19d04437 2006 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
38ba30ba
GN		 2007}
2008
a682e354 2009static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned long base,
d9271123 2010 int reg, struct operand *op)
a682e354
GN		 2011{
2012 struct decode_cache *c = &ctxt->decode;
2013 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
2014
d9271123
GN		 2015 register_address_increment(c, &c->regs[reg], df * op->bytes);
2016 op->ptr = (unsigned long *)register_address(c, base, c->regs[reg]);
a682e354
GN		 2017}
2018
63540382
AK		 2019static int em_push(struct x86_emulate_ctxt *ctxt)
2020{
2021 emulate_push(ctxt, ctxt->ops);
2022 return X86EMUL_CONTINUE;
2023}
2024
73fba5f4
AK		 2025#define D(_y) { .flags = (_y) }
2026#define N D(0)
2027#define G(_f, _g) { .flags = ((_f) | Group), .u.group = (_g) }
2028#define GD(_f, _g) { .flags = ((_f) | Group | GroupDual), .u.gdual = (_g) }
2029#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
2030
2031static struct opcode group1[] = {
2032 X7(D(Lock)), N
2033};
2034
2035static struct opcode group1A[] = {
2036 D(DstMem | SrcNone | ModRM | Mov | Stack), N, N, N, N, N, N, N,
2037};
2038
2039static struct opcode group3[] = {
2040 D(DstMem | SrcImm | ModRM), D(DstMem | SrcImm | ModRM),
2041 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
2042 X4(D(Undefined)),
2043};
2044
2045static struct opcode group4[] = {
2046 D(ByteOp | DstMem | SrcNone | ModRM | Lock), D(ByteOp | DstMem | SrcNone | ModRM | Lock),
2047 N, N, N, N, N, N,
2048};
2049
2050static struct opcode group5[] = {
2051 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
2052 D(SrcMem | ModRM | Stack), N,
2053 D(SrcMem | ModRM | Stack), D(SrcMemFAddr | ModRM | ImplicitOps),
2054 D(SrcMem | ModRM | Stack), N,
2055};
2056
2057static struct group_dual group7 = { {
2058 N, N, D(ModRM | SrcMem | Priv), D(ModRM | SrcMem | Priv),
2059 D(SrcNone | ModRM | DstMem | Mov), N,
2060 D(SrcMem16 | ModRM | Mov | Priv), D(SrcMem | ModRM | ByteOp | Priv),
2061}, {
2062 D(SrcNone | ModRM | Priv), N, N, D(SrcNone | ModRM | Priv),
2063 D(SrcNone | ModRM | DstMem | Mov), N,
2064 D(SrcMem16 | ModRM | Mov | Priv), N,
2065} };
2066
2067static struct opcode group8[] = {
2068 N, N, N, N,
2069 D(DstMem | SrcImmByte | ModRM), D(DstMem | SrcImmByte | ModRM | Lock),
2070 D(DstMem | SrcImmByte | ModRM | Lock), D(DstMem | SrcImmByte | ModRM | Lock),
2071};
2072
2073static struct group_dual group9 = { {
2074 N, D(DstMem64 | ModRM | Lock), N, N, N, N, N, N,
2075}, {
2076 N, N, N, N, N, N, N, N,
2077} };
2078
2079static struct opcode opcode_table[256] = {
2080 /* 0x00 - 0x07 */
2081 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2082 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2083 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
2084 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2085 /* 0x08 - 0x0F */
2086 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2087 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2088 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
2089 D(ImplicitOps | Stack | No64), N,
2090 /* 0x10 - 0x17 */
2091 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2092 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2093 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
2094 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2095 /* 0x18 - 0x1F */
2096 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2097 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2098 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
2099 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2100 /* 0x20 - 0x27 */
2101 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2102 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2103 D(ByteOp | DstAcc | SrcImmByte), D(DstAcc | SrcImm), N, N,
2104 /* 0x28 - 0x2F */
2105 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2106 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2107 D(ByteOp | DstAcc | SrcImmByte), D(DstAcc | SrcImm), N, N,
2108 /* 0x30 - 0x37 */
2109 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2110 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2111 D(ByteOp | DstAcc | SrcImmByte), D(DstAcc | SrcImm), N, N,
2112 /* 0x38 - 0x3F */
2113 D(ByteOp | DstMem | SrcReg | ModRM), D(DstMem | SrcReg | ModRM),
2114 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2115 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
2116 N, N,
2117 /* 0x40 - 0x4F */
2118 X16(D(DstReg)),
2119 /* 0x50 - 0x57 */
63540382 2120 X8(I(SrcReg | Stack, em_push)),
73fba5f4
AK		 2121 /* 0x58 - 0x5F */
2122 X8(D(DstReg | Stack)),
2123 /* 0x60 - 0x67 */
2124 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2125 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
2126 N, N, N, N,
2127 /* 0x68 - 0x6F */
63540382
AK		 2128 I(SrcImm | Mov | Stack, em_push), N,
2129 I(SrcImmByte | Mov | Stack, em_push), N,
73fba5f4
AK		 2130 D(DstDI | ByteOp | Mov | String), D(DstDI | Mov | String), /* insb, insw/insd */
2131 D(SrcSI | ByteOp | ImplicitOps | String), D(SrcSI | ImplicitOps | String), /* outsb, outsw/outsd */
2132 /* 0x70 - 0x7F */
2133 X16(D(SrcImmByte)),
2134 /* 0x80 - 0x87 */
2135 G(ByteOp | DstMem | SrcImm | ModRM | Group, group1),
2136 G(DstMem | SrcImm | ModRM | Group, group1),
2137 G(ByteOp | DstMem | SrcImm | ModRM | No64 | Group, group1),
2138 G(DstMem | SrcImmByte | ModRM | Group, group1),
2139 D(ByteOp | DstMem | SrcReg | ModRM), D(DstMem | SrcReg | ModRM),
2140 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2141 /* 0x88 - 0x8F */
2142 D(ByteOp | DstMem | SrcReg | ModRM | Mov), D(DstMem | SrcReg | ModRM | Mov),
2143 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem | ModRM | Mov),
2144 D(DstMem | SrcNone | ModRM | Mov), D(ModRM | DstReg),
2145 D(ImplicitOps | SrcMem16 | ModRM), G(0, group1A),
2146 /* 0x90 - 0x97 */
2147 D(DstReg), D(DstReg), D(DstReg), D(DstReg), D(DstReg), D(DstReg), D(DstReg), D(DstReg),
2148 /* 0x98 - 0x9F */
2149 N, N, D(SrcImmFAddr | No64), N,
2150 D(ImplicitOps | Stack), D(ImplicitOps | Stack), N, N,
2151 /* 0xA0 - 0xA7 */
2152 D(ByteOp | DstAcc | SrcMem | Mov | MemAbs), D(DstAcc | SrcMem | Mov | MemAbs),
2153 D(ByteOp | DstMem | SrcAcc | Mov | MemAbs), D(DstMem | SrcAcc | Mov | MemAbs),
2154 D(ByteOp | SrcSI | DstDI | Mov | String), D(SrcSI | DstDI | Mov | String),
2155 D(ByteOp | SrcSI | DstDI | String), D(SrcSI | DstDI | String),
2156 /* 0xA8 - 0xAF */
2157 D(DstAcc | SrcImmByte | ByteOp), D(DstAcc | SrcImm), D(ByteOp | DstDI | Mov | String), D(DstDI | Mov | String),
2158 D(ByteOp | SrcSI | DstAcc | Mov | String), D(SrcSI | DstAcc | Mov | String),
2159 D(ByteOp | DstDI | String), D(DstDI | String),
2160 /* 0xB0 - 0xB7 */
2161 X8(D(ByteOp | DstReg | SrcImm | Mov)),
2162 /* 0xB8 - 0xBF */
2163 X8(D(DstReg | SrcImm | Mov)),
2164 /* 0xC0 - 0xC7 */
2165 D(ByteOp | DstMem | SrcImm | ModRM), D(DstMem | SrcImmByte | ModRM),
2166 N, D(ImplicitOps | Stack), N, N,
2167 D(ByteOp | DstMem | SrcImm | ModRM | Mov), D(DstMem | SrcImm | ModRM | Mov),
2168 /* 0xC8 - 0xCF */
2169 N, N, N, D(ImplicitOps | Stack),
2170 D(ImplicitOps), D(SrcImmByte), D(ImplicitOps | No64), D(ImplicitOps),
2171 /* 0xD0 - 0xD7 */
2172 D(ByteOp | DstMem | SrcImplicit | ModRM), D(DstMem | SrcImplicit | ModRM),
2173 D(ByteOp | DstMem | SrcImplicit | ModRM), D(DstMem | SrcImplicit | ModRM),
2174 N, N, N, N,
2175 /* 0xD8 - 0xDF */
2176 N, N, N, N, N, N, N, N,
2177 /* 0xE0 - 0xE7 */
2178 N, N, N, N,
2179 D(ByteOp | SrcImmUByte | DstAcc), D(SrcImmUByte | DstAcc),
2180 D(ByteOp | SrcImmUByte | DstAcc), D(SrcImmUByte | DstAcc),
2181 /* 0xE8 - 0xEF */
2182 D(SrcImm | Stack), D(SrcImm | ImplicitOps),
2183 D(SrcImmFAddr | No64), D(SrcImmByte | ImplicitOps),
2184 D(SrcNone | ByteOp | DstAcc), D(SrcNone | DstAcc),
2185 D(SrcNone | ByteOp | DstAcc), D(SrcNone | DstAcc),
2186 /* 0xF0 - 0xF7 */
2187 N, N, N, N,
2188 D(ImplicitOps | Priv), D(ImplicitOps), G(ByteOp, group3), G(0, group3),
2189 /* 0xF8 - 0xFF */
2190 D(ImplicitOps), N, D(ImplicitOps), D(ImplicitOps),
2191 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
2192};
2193
2194static struct opcode twobyte_table[256] = {
2195 /* 0x00 - 0x0F */
2196 N, GD(0, &group7), N, N,
2197 N, D(ImplicitOps), D(ImplicitOps | Priv), N,
2198 D(ImplicitOps | Priv), D(ImplicitOps | Priv), N, N,
2199 N, D(ImplicitOps | ModRM), N, N,
2200 /* 0x10 - 0x1F */
2201 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
2202 /* 0x20 - 0x2F */
2203 D(ModRM | ImplicitOps | Priv), D(ModRM | Priv),
2204 D(ModRM | ImplicitOps | Priv), D(ModRM | Priv),
2205 N, N, N, N,
2206 N, N, N, N, N, N, N, N,
2207 /* 0x30 - 0x3F */
2208 D(ImplicitOps | Priv), N, D(ImplicitOps | Priv), N,
2209 D(ImplicitOps), D(ImplicitOps | Priv), N, N,
2210 N, N, N, N, N, N, N, N,
2211 /* 0x40 - 0x4F */
2212 X16(D(DstReg | SrcMem | ModRM | Mov)),
2213 /* 0x50 - 0x5F */
2214 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2215 /* 0x60 - 0x6F */
2216 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2217 /* 0x70 - 0x7F */
2218 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2219 /* 0x80 - 0x8F */
2220 X16(D(SrcImm)),
2221 /* 0x90 - 0x9F */
2222 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2223 /* 0xA0 - 0xA7 */
2224 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
2225 N, D(DstMem | SrcReg | ModRM | BitOp),
2226 D(DstMem | SrcReg | Src2ImmByte | ModRM),
2227 D(DstMem | SrcReg | Src2CL | ModRM), N, N,
2228 /* 0xA8 - 0xAF */
2229 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
2230 N, D(DstMem | SrcReg | ModRM | BitOp | Lock),
2231 D(DstMem | SrcReg | Src2ImmByte | ModRM),
2232 D(DstMem | SrcReg | Src2CL | ModRM),
2233 D(ModRM), N,
2234 /* 0xB0 - 0xB7 */
2235 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2236 N, D(DstMem | SrcReg | ModRM | BitOp | Lock),
2237 N, N, D(ByteOp | DstReg | SrcMem | ModRM | Mov),
2238 D(DstReg | SrcMem16 | ModRM | Mov),
2239 /* 0xB8 - 0xBF */
2240 N, N,
2241 G(0, group8), D(DstMem | SrcReg | ModRM | BitOp | Lock),
2242 N, N, D(ByteOp | DstReg | SrcMem | ModRM | Mov),
2243 D(DstReg | SrcMem16 | ModRM | Mov),
2244 /* 0xC0 - 0xCF */
2245 N, N, N, D(DstMem | SrcReg | ModRM | Mov),
2246 N, N, N, GD(0, &group9),
2247 N, N, N, N, N, N, N, N,
2248 /* 0xD0 - 0xDF */
2249 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2250 /* 0xE0 - 0xEF */
2251 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2252 /* 0xF0 - 0xFF */
2253 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
2254};
2255
2256#undef D
2257#undef N
2258#undef G
2259#undef GD
2260#undef I
2261
dde7e6d1
AK		 2262int
2263x86_decode_insn(struct x86_emulate_ctxt *ctxt)
2264{
2265 struct x86_emulate_ops *ops = ctxt->ops;
2266 struct decode_cache *c = &ctxt->decode;
2267 int rc = X86EMUL_CONTINUE;
2268 int mode = ctxt->mode;
2269 int def_op_bytes, def_ad_bytes, dual, goffset;
2270 struct opcode opcode, *g_mod012, *g_mod3;
2271
2272 /* we cannot decode insn before we complete previous rep insn */
2273 WARN_ON(ctxt->restart);
2274
2275 c->eip = ctxt->eip;
2276 c->fetch.start = c->fetch.end = c->eip;
2277 ctxt->cs_base = seg_base(ctxt, ops, VCPU_SREG_CS);
2278
2279 switch (mode) {
2280 case X86EMUL_MODE_REAL:
2281 case X86EMUL_MODE_VM86:
2282 case X86EMUL_MODE_PROT16:
2283 def_op_bytes = def_ad_bytes = 2;
2284 break;
2285 case X86EMUL_MODE_PROT32:
2286 def_op_bytes = def_ad_bytes = 4;
2287 break;
2288#ifdef CONFIG_X86_64
2289 case X86EMUL_MODE_PROT64:
2290 def_op_bytes = 4;
2291 def_ad_bytes = 8;
2292 break;
2293#endif
2294 default:
2295 return -1;
2296 }
2297
2298 c->op_bytes = def_op_bytes;
2299 c->ad_bytes = def_ad_bytes;
2300
2301 /* Legacy prefixes. */
2302 for (;;) {
2303 switch (c->b = insn_fetch(u8, 1, c->eip)) {
2304 case 0x66: /* operand-size override */
2305 /* switch between 2/4 bytes */
2306 c->op_bytes = def_op_bytes ^ 6;
2307 break;
2308 case 0x67: /* address-size override */
2309 if (mode == X86EMUL_MODE_PROT64)
2310 /* switch between 4/8 bytes */
2311 c->ad_bytes = def_ad_bytes ^ 12;
2312 else
2313 /* switch between 2/4 bytes */
2314 c->ad_bytes = def_ad_bytes ^ 6;
2315 break;
2316 case 0x26: /* ES override */
2317 case 0x2e: /* CS override */
2318 case 0x36: /* SS override */
2319 case 0x3e: /* DS override */
2320 set_seg_override(c, (c->b >> 3) & 3);
2321 break;
2322 case 0x64: /* FS override */
2323 case 0x65: /* GS override */
2324 set_seg_override(c, c->b & 7);
2325 break;
2326 case 0x40 ... 0x4f: /* REX */
2327 if (mode != X86EMUL_MODE_PROT64)
2328 goto done_prefixes;
2329 c->rex_prefix = c->b;
2330 continue;
2331 case 0xf0: /* LOCK */
2332 c->lock_prefix = 1;
2333 break;
2334 case 0xf2: /* REPNE/REPNZ */
2335 c->rep_prefix = REPNE_PREFIX;
2336 break;
2337 case 0xf3: /* REP/REPE/REPZ */
2338 c->rep_prefix = REPE_PREFIX;
2339 break;
2340 default:
2341 goto done_prefixes;
2342 }
2343
2344 /* Any legacy prefix after a REX prefix nullifies its effect. */
2345
2346 c->rex_prefix = 0;
2347 }
2348
2349done_prefixes:
2350
2351 /* REX prefix. */
2352 if (c->rex_prefix)
2353 if (c->rex_prefix & 8)
2354 c->op_bytes = 8; /* REX.W */
2355
2356 /* Opcode byte(s). */
2357 opcode = opcode_table[c->b];
2358 if (opcode.flags == 0) {
2359 /* Two-byte opcode? */
2360 if (c->b == 0x0f) {
2361 c->twobyte = 1;
2362 c->b = insn_fetch(u8, 1, c->eip);
2363 opcode = twobyte_table[c->b];
2364 }
2365 }
2366 c->d = opcode.flags;
2367
2368 if (c->d & Group) {
2369 dual = c->d & GroupDual;
2370 c->modrm = insn_fetch(u8, 1, c->eip);
2371 --c->eip;
2372
2373 if (c->d & GroupDual) {
2374 g_mod012 = opcode.u.gdual->mod012;
2375 g_mod3 = opcode.u.gdual->mod3;
2376 } else
2377 g_mod012 = g_mod3 = opcode.u.group;
2378
2379 c->d &= ~(Group | GroupDual);
2380
2381 goffset = (c->modrm >> 3) & 7;
2382
2383 if ((c->modrm >> 6) == 3)
2384 opcode = g_mod3[goffset];
2385 else
2386 opcode = g_mod012[goffset];
2387 c->d |= opcode.flags;
2388 }
2389
2390 c->execute = opcode.u.execute;
2391
2392 /* Unrecognised? */
2393 if (c->d == 0 || (c->d & Undefined)) {
2394 DPRINTF("Cannot emulate %02x\n", c->b);
2395 return -1;
2396 }
2397
2398 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
2399 c->op_bytes = 8;
2400
2401 /* ModRM and SIB bytes. */
2402 if (c->d & ModRM)
2403 rc = decode_modrm(ctxt, ops);
2404 else if (c->d & MemAbs)
2405 rc = decode_abs(ctxt, ops);
2406 if (rc != X86EMUL_CONTINUE)
2407 goto done;
2408
2409 if (!c->has_seg_override)
2410 set_seg_override(c, VCPU_SREG_DS);
2411
2412 if (!(!c->twobyte && c->b == 0x8d))
2413 c->modrm_ea += seg_override_base(ctxt, ops, c);
2414
2415 if (c->ad_bytes != 8)
2416 c->modrm_ea = (u32)c->modrm_ea;
2417
2418 if (c->rip_relative)
2419 c->modrm_ea += c->eip;
2420
2421 /*
2422 * Decode and fetch the source operand: register, memory
2423 * or immediate.
2424 */
2425 switch (c->d & SrcMask) {
2426 case SrcNone:
2427 break;
2428 case SrcReg:
2429 decode_register_operand(&c->src, c, 0);
2430 break;
2431 case SrcMem16:
2432 c->src.bytes = 2;
2433 goto srcmem_common;
2434 case SrcMem32:
2435 c->src.bytes = 4;
2436 goto srcmem_common;
2437 case SrcMem:
2438 c->src.bytes = (c->d & ByteOp) ? 1 :
2439 c->op_bytes;
2440 /* Don't fetch the address for invlpg: it could be unmapped. */
2441 if (c->twobyte && c->b == 0x01 && c->modrm_reg == 7)
2442 break;
2443 srcmem_common:
2444 /*
2445 * For instructions with a ModR/M byte, switch to register
2446 * access if Mod = 3.
2447 */
2448 if ((c->d & ModRM) && c->modrm_mod == 3) {
2449 c->src.type = OP_REG;
2450 c->src.val = c->modrm_val;
2451 c->src.ptr = c->modrm_ptr;
2452 break;
2453 }
2454 c->src.type = OP_MEM;
2455 c->src.ptr = (unsigned long *)c->modrm_ea;
2456 c->src.val = 0;
2457 break;
2458 case SrcImm:
2459 case SrcImmU:
2460 c->src.type = OP_IMM;
2461 c->src.ptr = (unsigned long *)c->eip;
2462 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
2463 if (c->src.bytes == 8)
2464 c->src.bytes = 4;
2465 /* NB. Immediates are sign-extended as necessary. */
2466 switch (c->src.bytes) {
2467 case 1:
2468 c->src.val = insn_fetch(s8, 1, c->eip);
2469 break;
2470 case 2:
2471 c->src.val = insn_fetch(s16, 2, c->eip);
2472 break;
2473 case 4:
2474 c->src.val = insn_fetch(s32, 4, c->eip);
2475 break;
2476 }
2477 if ((c->d & SrcMask) == SrcImmU) {
2478 switch (c->src.bytes) {
2479 case 1:
2480 c->src.val &= 0xff;
2481 break;
2482 case 2:
2483 c->src.val &= 0xffff;
2484 break;
2485 case 4:
2486 c->src.val &= 0xffffffff;
2487 break;
2488 }
2489 }
2490 break;
2491 case SrcImmByte:
2492 case SrcImmUByte:
2493 c->src.type = OP_IMM;
2494 c->src.ptr = (unsigned long *)c->eip;
2495 c->src.bytes = 1;
2496 if ((c->d & SrcMask) == SrcImmByte)
2497 c->src.val = insn_fetch(s8, 1, c->eip);
2498 else
2499 c->src.val = insn_fetch(u8, 1, c->eip);
2500 break;
2501 case SrcAcc:
2502 c->src.type = OP_REG;
2503 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
2504 c->src.ptr = &c->regs[VCPU_REGS_RAX];
2505 switch (c->src.bytes) {
2506 case 1:
2507 c->src.val = *(u8 *)c->src.ptr;
2508 break;
2509 case 2:
2510 c->src.val = *(u16 *)c->src.ptr;
2511 break;
2512 case 4:
2513 c->src.val = *(u32 *)c->src.ptr;
2514 break;
2515 case 8:
2516 c->src.val = *(u64 *)c->src.ptr;
2517 break;
2518 }
2519 break;
2520 case SrcOne:
2521 c->src.bytes = 1;
2522 c->src.val = 1;
2523 break;
2524 case SrcSI:
2525 c->src.type = OP_MEM;
2526 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
2527 c->src.ptr = (unsigned long *)
2528 register_address(c, seg_override_base(ctxt, ops, c),
2529 c->regs[VCPU_REGS_RSI]);
2530 c->src.val = 0;
2531 break;
2532 case SrcImmFAddr:
2533 c->src.type = OP_IMM;
2534 c->src.ptr = (unsigned long *)c->eip;
2535 c->src.bytes = c->op_bytes + 2;
2536 insn_fetch_arr(c->src.valptr, c->src.bytes, c->eip);
2537 break;
2538 case SrcMemFAddr:
2539 c->src.type = OP_MEM;
2540 c->src.ptr = (unsigned long *)c->modrm_ea;
2541 c->src.bytes = c->op_bytes + 2;
2542 break;
2543 }
2544
2545 /*
2546 * Decode and fetch the second source operand: register, memory
2547 * or immediate.
2548 */
2549 switch (c->d & Src2Mask) {
2550 case Src2None:
2551 break;
2552 case Src2CL:
2553 c->src2.bytes = 1;
2554 c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
2555 break;
2556 case Src2ImmByte:
2557 c->src2.type = OP_IMM;
2558 c->src2.ptr = (unsigned long *)c->eip;
2559 c->src2.bytes = 1;
2560 c->src2.val = insn_fetch(u8, 1, c->eip);
2561 break;
2562 case Src2One:
2563 c->src2.bytes = 1;
2564 c->src2.val = 1;
2565 break;
2566 }
2567
2568 /* Decode and fetch the destination operand: register or memory. */
2569 switch (c->d & DstMask) {
2570 case ImplicitOps:
2571 /* Special instructions do their own operand decoding. */
2572 return 0;
2573 case DstReg:
2574 decode_register_operand(&c->dst, c,
2575 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
2576 break;
2577 case DstMem:
2578 case DstMem64:
2579 if ((c->d & ModRM) && c->modrm_mod == 3) {
2580 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
2581 c->dst.type = OP_REG;
2582 c->dst.val = c->dst.orig_val = c->modrm_val;
2583 c->dst.ptr = c->modrm_ptr;
2584 break;
2585 }
2586 c->dst.type = OP_MEM;
2587 c->dst.ptr = (unsigned long *)c->modrm_ea;
2588 if ((c->d & DstMask) == DstMem64)
2589 c->dst.bytes = 8;
2590 else
2591 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
2592 c->dst.val = 0;
2593 if (c->d & BitOp) {
2594 unsigned long mask = ~(c->dst.bytes * 8 - 1);
2595
2596 c->dst.ptr = (void *)c->dst.ptr +
2597 (c->src.val & mask) / 8;
2598 }
2599 break;
2600 case DstAcc:
2601 c->dst.type = OP_REG;
2602 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
2603 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
2604 switch (c->dst.bytes) {
2605 case 1:
2606 c->dst.val = *(u8 *)c->dst.ptr;
2607 break;
2608 case 2:
2609 c->dst.val = *(u16 *)c->dst.ptr;
2610 break;
2611 case 4:
2612 c->dst.val = *(u32 *)c->dst.ptr;
2613 break;
2614 case 8:
2615 c->dst.val = *(u64 *)c->dst.ptr;
2616 break;
2617 }
2618 c->dst.orig_val = c->dst.val;
2619 break;
2620 case DstDI:
2621 c->dst.type = OP_MEM;
2622 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
2623 c->dst.ptr = (unsigned long *)
2624 register_address(c, es_base(ctxt, ops),
2625 c->regs[VCPU_REGS_RDI]);
2626 c->dst.val = 0;
2627 break;
2628 }
2629
2630done:
2631 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
2632}
2633
8b4caf66 2634int
9aabc88f 2635x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
8b4caf66 2636{
9aabc88f 2637 struct x86_emulate_ops *ops = ctxt->ops;
8b4caf66 2638 u64 msr_data;
8b4caf66 2639 struct decode_cache *c = &ctxt->decode;
1b30eaa8 2640 int rc = X86EMUL_CONTINUE;
5cd21917 2641 int saved_dst_type = c->dst.type;
8b4caf66 2642
9de41573 2643 ctxt->decode.mem_read.pos = 0;
310b5d30 2644
1161624f 2645 if (ctxt->mode == X86EMUL_MODE_PROT64 && (c->d & No64)) {
54b8486f 2646 emulate_ud(ctxt);
1161624f
GN		 2647 goto done;
2648 }
2649
d380a5e4 2650 /* LOCK prefix is allowed only with some instructions */
a41ffb75 2651 if (c->lock_prefix && (!(c->d & Lock) || c->dst.type != OP_MEM)) {
54b8486f 2652 emulate_ud(ctxt);
d380a5e4
GN		 2653 goto done;
2654 }
2655
e92805ac 2656 /* Privileged instruction can be executed only in CPL=0 */
9c537244 2657 if ((c->d & Priv) && ops->cpl(ctxt->vcpu)) {
54b8486f 2658 emulate_gp(ctxt, 0);
e92805ac
GN		 2659 goto done;
2660 }
2661
b9fa9d6b 2662 if (c->rep_prefix && (c->d & String)) {
5cd21917 2663 ctxt->restart = true;
b9fa9d6b 2664 /* All REP prefixes have the same first termination condition */
c73e197b 2665 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) {
5cd21917
GN		 2666 string_done:
2667 ctxt->restart = false;
95c55886 2668 ctxt->eip = c->eip;
b9fa9d6b
AK		 2669 goto done;
2670 }
2671 /* The second termination condition only applies for REPE
2672 * and REPNE. Test if the repeat string operation prefix is
2673 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
2674 * corresponding termination condition according to:
2675 * - if REPE/REPZ and ZF = 0 then done
2676 * - if REPNE/REPNZ and ZF = 1 then done
2677 */
2678 if ((c->b == 0xa6) || (c->b == 0xa7) ||
5cd21917 2679 (c->b == 0xae) || (c->b == 0xaf)) {
b9fa9d6b 2680 if ((c->rep_prefix == REPE_PREFIX) &&
5cd21917
GN		 2681 ((ctxt->eflags & EFLG_ZF) == 0))
2682 goto string_done;
b9fa9d6b 2683 if ((c->rep_prefix == REPNE_PREFIX) &&
5cd21917
GN		 2684 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))
2685 goto string_done;
b9fa9d6b 2686 }
063db061 2687 c->eip = ctxt->eip;
b9fa9d6b
AK		 2688 }
2689
8b4caf66 2690 if (c->src.type == OP_MEM) {
9de41573 2691 rc = read_emulated(ctxt, ops, (unsigned long)c->src.ptr,
414e6277 2692 c->src.valptr, c->src.bytes);
b60d513c 2693 if (rc != X86EMUL_CONTINUE)
8b4caf66 2694 goto done;
16518d5a 2695 c->src.orig_val64 = c->src.val64;
8b4caf66
LV		 2696 }
2697
e35b7b9c 2698 if (c->src2.type == OP_MEM) {
9de41573
GN		 2699 rc = read_emulated(ctxt, ops, (unsigned long)c->src2.ptr,
2700 &c->src2.val, c->src2.bytes);
e35b7b9c
GN		 2701 if (rc != X86EMUL_CONTINUE)
2702 goto done;
2703 }
2704
8b4caf66
LV		 2705 if ((c->d & DstMask) == ImplicitOps)
2706 goto special_insn;
2707
2708
69f55cb1
GN		 2709 if ((c->dst.type == OP_MEM) && !(c->d & Mov)) {
2710 /* optimisation - avoid slow emulated read if Mov */
9de41573
GN		 2711 rc = read_emulated(ctxt, ops, (unsigned long)c->dst.ptr,
2712 &c->dst.val, c->dst.bytes);
69f55cb1
GN		 2713 if (rc != X86EMUL_CONTINUE)
2714 goto done;
038e51de 2715 }
e4e03ded 2716 c->dst.orig_val = c->dst.val;
038e51de 2717
018a98db
AK		 2718special_insn:
2719
ef65c889
AK		 2720 if (c->execute) {
2721 rc = c->execute(ctxt);
2722 if (rc != X86EMUL_CONTINUE)
2723 goto done;
2724 goto writeback;
2725 }
2726
e4e03ded 2727 if (c->twobyte)
6aa8b732
AK		 2728 goto twobyte_insn;
2729
e4e03ded 2730 switch (c->b) {
6aa8b732
AK		 2731 case 0x00 ... 0x05:
2732 add: /* add */
05f086f8 2733 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
6aa8b732 2734 break;
0934ac9d 2735 case 0x06: /* push es */
79168fd1 2736 emulate_push_sreg(ctxt, ops, VCPU_SREG_ES);
0934ac9d
MG		 2737 break;
2738 case 0x07: /* pop es */
0934ac9d 2739 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES);
1b30eaa8 2740 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 2741 goto done;
2742 break;
6aa8b732
AK		 2743 case 0x08 ... 0x0d:
2744 or: /* or */
05f086f8 2745 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
6aa8b732 2746 break;
0934ac9d 2747 case 0x0e: /* push cs */
79168fd1 2748 emulate_push_sreg(ctxt, ops, VCPU_SREG_CS);
0934ac9d 2749 break;
6aa8b732
AK		 2750 case 0x10 ... 0x15:
2751 adc: /* adc */
05f086f8 2752 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
6aa8b732 2753 break;
0934ac9d 2754 case 0x16: /* push ss */
79168fd1 2755 emulate_push_sreg(ctxt, ops, VCPU_SREG_SS);
0934ac9d
MG		 2756 break;
2757 case 0x17: /* pop ss */
0934ac9d 2758 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS);
1b30eaa8 2759 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 2760 goto done;
2761 break;
6aa8b732
AK		 2762 case 0x18 ... 0x1d:
2763 sbb: /* sbb */
05f086f8 2764 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
6aa8b732 2765 break;
0934ac9d 2766 case 0x1e: /* push ds */
79168fd1 2767 emulate_push_sreg(ctxt, ops, VCPU_SREG_DS);
0934ac9d
MG		 2768 break;
2769 case 0x1f: /* pop ds */
0934ac9d 2770 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS);
1b30eaa8 2771 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 2772 goto done;
2773 break;
aa3a816b 2774 case 0x20 ... 0x25:
6aa8b732 2775 and: /* and */
05f086f8 2776 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2777 break;
2778 case 0x28 ... 0x2d:
2779 sub: /* sub */
05f086f8 2780 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2781 break;
2782 case 0x30 ... 0x35:
2783 xor: /* xor */
05f086f8 2784 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2785 break;
2786 case 0x38 ... 0x3d:
2787 cmp: /* cmp */
05f086f8 2788 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
6aa8b732 2789 break;
33615aa9
AK		 2790 case 0x40 ... 0x47: /* inc r16/r32 */
2791 emulate_1op("inc", c->dst, ctxt->eflags);
2792 break;
2793 case 0x48 ... 0x4f: /* dec r16/r32 */
2794 emulate_1op("dec", c->dst, ctxt->eflags);
2795 break;
33615aa9
AK		 2796 case 0x58 ... 0x5f: /* pop reg */
2797 pop_instruction:
350f69dc 2798 rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes);
1b30eaa8 2799 if (rc != X86EMUL_CONTINUE)
33615aa9 2800 goto done;
33615aa9 2801 break;
abcf14b5 2802 case 0x60: /* pusha */
c37eda13
WY		 2803 rc = emulate_pusha(ctxt, ops);
2804 if (rc != X86EMUL_CONTINUE)
2805 goto done;
abcf14b5
MG		 2806 break;
2807 case 0x61: /* popa */
2808 rc = emulate_popa(ctxt, ops);
1b30eaa8 2809 if (rc != X86EMUL_CONTINUE)
abcf14b5
MG		 2810 goto done;
2811 break;
6aa8b732 2812 case 0x63: /* movsxd */
8b4caf66 2813 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 2814 goto cannot_emulate;
e4e03ded 2815 c->dst.val = (s32) c->src.val;
6aa8b732 2816 break;
018a98db
AK		 2817 case 0x6c: /* insb */
2818 case 0x6d: /* insw/insd */
7972995b 2819 c->dst.bytes = min(c->dst.bytes, 4u);
f850e2e6 2820 if (!emulator_io_permited(ctxt, ops, c->regs[VCPU_REGS_RDX],
7972995b 2821 c->dst.bytes)) {
54b8486f 2822 emulate_gp(ctxt, 0);
f850e2e6
GN		 2823 goto done;
2824 }
7b262e90
GN		 2825 if (!pio_in_emulated(ctxt, ops, c->dst.bytes,
2826 c->regs[VCPU_REGS_RDX], &c->dst.val))
7972995b
GN		 2827 goto done; /* IO is needed, skip writeback */
2828 break;
018a98db
AK		 2829 case 0x6e: /* outsb */
2830 case 0x6f: /* outsw/outsd */
7972995b 2831 c->src.bytes = min(c->src.bytes, 4u);
f850e2e6 2832 if (!emulator_io_permited(ctxt, ops, c->regs[VCPU_REGS_RDX],
7972995b 2833 c->src.bytes)) {
54b8486f 2834 emulate_gp(ctxt, 0);
f850e2e6
GN		 2835 goto done;
2836 }
7972995b
GN		 2837 ops->pio_out_emulated(c->src.bytes, c->regs[VCPU_REGS_RDX],
2838 &c->src.val, 1, ctxt->vcpu);
2839
2840 c->dst.type = OP_NONE; /* nothing to writeback */
2841 break;
b2833e3c 2842 case 0x70 ... 0x7f: /* jcc (short) */
018a98db 2843 if (test_cc(c->b, ctxt->eflags))
b2833e3c 2844 jmp_rel(c, c->src.val);
018a98db 2845 break;
6aa8b732 2846 case 0x80 ... 0x83: /* Grp1 */
e4e03ded 2847 switch (c->modrm_reg) {
6aa8b732
AK		 2848 case 0:
2849 goto add;
2850 case 1:
2851 goto or;
2852 case 2:
2853 goto adc;
2854 case 3:
2855 goto sbb;
2856 case 4:
2857 goto and;
2858 case 5:
2859 goto sub;
2860 case 6:
2861 goto xor;
2862 case 7:
2863 goto cmp;
2864 }
2865 break;
2866 case 0x84 ... 0x85:
dfb507c4 2867 test:
05f086f8 2868 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 2869 break;
2870 case 0x86 ... 0x87: /* xchg */
b13354f8 2871 xchg:
6aa8b732 2872 /* Write back the register source. */
e4e03ded 2873 switch (c->dst.bytes) {
6aa8b732 2874 case 1:
e4e03ded 2875 *(u8 *) c->src.ptr = (u8) c->dst.val;
6aa8b732
AK		 2876 break;
2877 case 2:
e4e03ded 2878 *(u16 *) c->src.ptr = (u16) c->dst.val;
6aa8b732
AK		 2879 break;
2880 case 4:
e4e03ded 2881 *c->src.ptr = (u32) c->dst.val;
6aa8b732
AK		 2882 break; /* 64b reg: zero-extend */
2883 case 8:
e4e03ded 2884 *c->src.ptr = c->dst.val;
6aa8b732
AK		 2885 break;
2886 }
2887 /*
2888 * Write back the memory destination with implicit LOCK
2889 * prefix.
2890 */
e4e03ded
LV		 2891 c->dst.val = c->src.val;
2892 c->lock_prefix = 1;
6aa8b732 2893 break;
6aa8b732 2894 case 0x88 ... 0x8b: /* mov */
7de75248 2895 goto mov;
79168fd1
GN		 2896 case 0x8c: /* mov r/m, sreg */
2897 if (c->modrm_reg > VCPU_SREG_GS) {
54b8486f 2898 emulate_ud(ctxt);
5e3ae6c5 2899 goto done;
38d5bc6d 2900 }
79168fd1 2901 c->dst.val = ops->get_segment_selector(c->modrm_reg, ctxt->vcpu);
38d5bc6d 2902 break;
7e0b54b1 2903 case 0x8d: /* lea r16/r32, m */
f9b7aab3 2904 c->dst.val = c->modrm_ea;
7e0b54b1 2905 break;
4257198a
GT		 2906 case 0x8e: { /* mov seg, r/m16 */
2907 uint16_t sel;
4257198a
GT		 2908
2909 sel = c->src.val;
8b9f4414 2910
c697518a
GN		 2911 if (c->modrm_reg == VCPU_SREG_CS ||
2912 c->modrm_reg > VCPU_SREG_GS) {
54b8486f 2913 emulate_ud(ctxt);
8b9f4414
GN		 2914 goto done;
2915 }
2916
310b5d30 2917 if (c->modrm_reg == VCPU_SREG_SS)
95cb2295 2918 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
310b5d30 2919
2e873022 2920 rc = load_segment_descriptor(ctxt, ops, sel, c->modrm_reg);
4257198a
GT		 2921
2922 c->dst.type = OP_NONE; /* Disable writeback. */
2923 break;
2924 }
6aa8b732 2925 case 0x8f: /* pop (sole member of Grp1a) */
8cdbd2c9 2926 rc = emulate_grp1a(ctxt, ops);
1b30eaa8 2927 if (rc != X86EMUL_CONTINUE)
6aa8b732 2928 goto done;
6aa8b732 2929 break;
b13354f8 2930 case 0x90: /* nop / xchg r8,rax */
b8a98945
GN		 2931 if (c->dst.ptr == (unsigned long *)&c->regs[VCPU_REGS_RAX]) {
2932 c->dst.type = OP_NONE; /* nop */
b13354f8
MG		 2933 break;
2934 }
2935 case 0x91 ... 0x97: /* xchg reg,rax */
f0c13ef1
GN		 2936 c->src.type = OP_REG;
2937 c->src.bytes = c->op_bytes;
b13354f8
MG		 2938 c->src.ptr = (unsigned long *) &c->regs[VCPU_REGS_RAX];
2939 c->src.val = *(c->src.ptr);
2940 goto xchg;
fd2a7608 2941 case 0x9c: /* pushf */
05f086f8 2942 c->src.val = (unsigned long) ctxt->eflags;
79168fd1 2943 emulate_push(ctxt, ops);
8cdbd2c9 2944 break;
535eabcf 2945 case 0x9d: /* popf */
2b48cc75 2946 c->dst.type = OP_REG;
05f086f8 2947 c->dst.ptr = (unsigned long *) &ctxt->eflags;
2b48cc75 2948 c->dst.bytes = c->op_bytes;
d4c6a154
GN		 2949 rc = emulate_popf(ctxt, ops, &c->dst.val, c->op_bytes);
2950 if (rc != X86EMUL_CONTINUE)
2951 goto done;
2952 break;
5d55f299 2953 case 0xa0 ... 0xa3: /* mov */
6aa8b732 2954 case 0xa4 ... 0xa5: /* movs */
a682e354 2955 goto mov;
6aa8b732 2956 case 0xa6 ... 0xa7: /* cmps */
d7e5117a 2957 c->dst.type = OP_NONE; /* Disable writeback. */
d7e5117a 2958 DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.ptr, c->dst.ptr);
a682e354 2959 goto cmp;
dfb507c4
MG		 2960 case 0xa8 ... 0xa9: /* test ax, imm */
2961 goto test;
6aa8b732 2962 case 0xaa ... 0xab: /* stos */
e4e03ded 2963 c->dst.val = c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 2964 break;
2965 case 0xac ... 0xad: /* lods */
a682e354 2966 goto mov;
6aa8b732
AK		 2967 case 0xae ... 0xaf: /* scas */
2968 DPRINTF("Urk! I don't handle SCAS.\n");
2969 goto cannot_emulate;
a5e2e82b 2970 case 0xb0 ... 0xbf: /* mov r, imm */
615ac125 2971 goto mov;
018a98db
AK		 2972 case 0xc0 ... 0xc1:
2973 emulate_grp2(ctxt);
2974 break;
111de5d6 2975 case 0xc3: /* ret */
cf5de4f8 2976 c->dst.type = OP_REG;
111de5d6 2977 c->dst.ptr = &c->eip;
cf5de4f8 2978 c->dst.bytes = c->op_bytes;
111de5d6 2979 goto pop_instruction;
018a98db
AK		 2980 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
2981 mov:
2982 c->dst.val = c->src.val;
2983 break;
a77ab5ea
AK		 2984 case 0xcb: /* ret far */
2985 rc = emulate_ret_far(ctxt, ops);
62bd430e
MG		 2986 if (rc != X86EMUL_CONTINUE)
2987 goto done;
2988 break;
2989 case 0xcf: /* iret */
2990 rc = emulate_iret(ctxt, ops);
2991
1b30eaa8 2992 if (rc != X86EMUL_CONTINUE)
a77ab5ea
AK		 2993 goto done;
2994 break;
018a98db
AK		 2995 case 0xd0 ... 0xd1: /* Grp2 */
2996 c->src.val = 1;
2997 emulate_grp2(ctxt);
2998 break;
2999 case 0xd2 ... 0xd3: /* Grp2 */
3000 c->src.val = c->regs[VCPU_REGS_RCX];
3001 emulate_grp2(ctxt);
3002 break;
a6a3034c
MG		 3003 case 0xe4: /* inb */
3004 case 0xe5: /* in */
cf8f70bf 3005 goto do_io_in;
a6a3034c
MG		 3006 case 0xe6: /* outb */
3007 case 0xe7: /* out */
cf8f70bf 3008 goto do_io_out;
1a52e051 3009 case 0xe8: /* call (near) */ {
d53c4777 3010 long int rel = c->src.val;
e4e03ded 3011 c->src.val = (unsigned long) c->eip;
7a957275 3012 jmp_rel(c, rel);
79168fd1 3013 emulate_push(ctxt, ops);
8cdbd2c9 3014 break;
1a52e051
NK		 3015 }
3016 case 0xe9: /* jmp rel */
954cd36f 3017 goto jmp;
414e6277
GN		 3018 case 0xea: { /* jmp far */
3019 unsigned short sel;
ea79849d 3020 jump_far:
414e6277
GN		 3021 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
3022
3023 if (load_segment_descriptor(ctxt, ops, sel, VCPU_SREG_CS))
c697518a 3024 goto done;
954cd36f 3025
414e6277
GN		 3026 c->eip = 0;
3027 memcpy(&c->eip, c->src.valptr, c->op_bytes);
954cd36f 3028 break;
414e6277 3029 }
954cd36f
GT		 3030 case 0xeb:
3031 jmp: /* jmp rel short */
7a957275 3032 jmp_rel(c, c->src.val);
a01af5ec 3033 c->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 3034 break;
a6a3034c
MG		 3035 case 0xec: /* in al,dx */
3036 case 0xed: /* in (e/r)ax,dx */
cf8f70bf
GN		 3037 c->src.val = c->regs[VCPU_REGS_RDX];
3038 do_io_in:
3039 c->dst.bytes = min(c->dst.bytes, 4u);
3040 if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) {
54b8486f 3041 emulate_gp(ctxt, 0);
cf8f70bf
GN		 3042 goto done;
3043 }
7b262e90
GN		 3044 if (!pio_in_emulated(ctxt, ops, c->dst.bytes, c->src.val,
3045 &c->dst.val))
cf8f70bf
GN		 3046 goto done; /* IO is needed */
3047 break;
ce7a0ad3
WY		 3048 case 0xee: /* out dx,al */
3049 case 0xef: /* out dx,(e/r)ax */
cf8f70bf
GN		 3050 c->src.val = c->regs[VCPU_REGS_RDX];
3051 do_io_out:
3052 c->dst.bytes = min(c->dst.bytes, 4u);
3053 if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) {
54b8486f 3054 emulate_gp(ctxt, 0);
f850e2e6
GN		 3055 goto done;
3056 }
cf8f70bf
GN		 3057 ops->pio_out_emulated(c->dst.bytes, c->src.val, &c->dst.val, 1,
3058 ctxt->vcpu);
3059 c->dst.type = OP_NONE; /* Disable writeback. */
e93f36bc 3060 break;
111de5d6 3061 case 0xf4: /* hlt */
ad312c7c 3062 ctxt->vcpu->arch.halt_request = 1;
19fdfa0d 3063 break;
111de5d6
AK		 3064 case 0xf5: /* cmc */
3065 /* complement carry flag from eflags reg */
3066 ctxt->eflags ^= EFLG_CF;
3067 c->dst.type = OP_NONE; /* Disable writeback. */
3068 break;
018a98db 3069 case 0xf6 ... 0xf7: /* Grp3 */
aca06a83
GN		 3070 if (!emulate_grp3(ctxt, ops))
3071 goto cannot_emulate;
018a98db 3072 break;
111de5d6
AK		 3073 case 0xf8: /* clc */
3074 ctxt->eflags &= ~EFLG_CF;
3075 c->dst.type = OP_NONE; /* Disable writeback. */
3076 break;
3077 case 0xfa: /* cli */
07cbc6c1 3078 if (emulator_bad_iopl(ctxt, ops)) {
54b8486f 3079 emulate_gp(ctxt, 0);
07cbc6c1
WY		 3080 goto done;
3081 } else {
f850e2e6
GN		 3082 ctxt->eflags &= ~X86_EFLAGS_IF;
3083 c->dst.type = OP_NONE; /* Disable writeback. */
3084 }
111de5d6
AK		 3085 break;
3086 case 0xfb: /* sti */
07cbc6c1 3087 if (emulator_bad_iopl(ctxt, ops)) {
54b8486f 3088 emulate_gp(ctxt, 0);
07cbc6c1
WY		 3089 goto done;
3090 } else {
95cb2295 3091 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
f850e2e6
GN		 3092 ctxt->eflags |= X86_EFLAGS_IF;
3093 c->dst.type = OP_NONE; /* Disable writeback. */
3094 }
111de5d6 3095 break;
fb4616f4
MG		 3096 case 0xfc: /* cld */
3097 ctxt->eflags &= ~EFLG_DF;
3098 c->dst.type = OP_NONE; /* Disable writeback. */
3099 break;
3100 case 0xfd: /* std */
3101 ctxt->eflags |= EFLG_DF;
3102 c->dst.type = OP_NONE; /* Disable writeback. */
3103 break;
ea79849d
GN		 3104 case 0xfe: /* Grp4 */
3105 grp45:
018a98db 3106 rc = emulate_grp45(ctxt, ops);
1b30eaa8 3107 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 3108 goto done;
3109 break;
ea79849d
GN		 3110 case 0xff: /* Grp5 */
3111 if (c->modrm_reg == 5)
3112 goto jump_far;
3113 goto grp45;
91269b8f
AK		 3114 default:
3115 goto cannot_emulate;
6aa8b732 3116 }
018a98db
AK		 3117
3118writeback:
3119 rc = writeback(ctxt, ops);
1b30eaa8 3120 if (rc != X86EMUL_CONTINUE)
018a98db
AK		 3121 goto done;
3122
5cd21917
GN		 3123 /*
3124 * restore dst type in case the decoding will be reused
3125 * (happens for string instruction )
3126 */
3127 c->dst.type = saved_dst_type;
3128
a682e354 3129 if ((c->d & SrcMask) == SrcSI)
79168fd1
GN		 3130 string_addr_inc(ctxt, seg_override_base(ctxt, ops, c),
3131 VCPU_REGS_RSI, &c->src);
a682e354
GN		 3132
3133 if ((c->d & DstMask) == DstDI)
79168fd1
GN		 3134 string_addr_inc(ctxt, es_base(ctxt, ops), VCPU_REGS_RDI,
3135 &c->dst);
d9271123 3136
5cd21917 3137 if (c->rep_prefix && (c->d & String)) {
7b262e90 3138 struct read_cache *rc = &ctxt->decode.io_read;
d9271123 3139 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
7b262e90
GN		 3140 /*
3141 * Re-enter guest when pio read ahead buffer is empty or,
3142 * if it is not used, after each 1024 iteration.
3143 */
3144 if ((rc->end == 0 && !(c->regs[VCPU_REGS_RCX] & 0x3ff)) ||
3145 (rc->end != 0 && rc->end == rc->pos))
5cd21917
GN		 3146 ctxt->restart = false;
3147 }
9de41573
GN		 3148 /*
3149 * reset read cache here in case string instruction is restared
3150 * without decoding
3151 */
3152 ctxt->decode.mem_read.end = 0;
95c55886 3153 ctxt->eip = c->eip;
018a98db
AK		 3154
3155done:
cb404fe0 3156 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
6aa8b732
AK		 3157
3158twobyte_insn:
e4e03ded 3159 switch (c->b) {
6aa8b732 3160 case 0x01: /* lgdt, lidt, lmsw */
e4e03ded 3161 switch (c->modrm_reg) {
6aa8b732
AK		 3162 u16 size;
3163 unsigned long address;
3164
aca7f966 3165 case 0: /* vmcall */
e4e03ded 3166 if (c->modrm_mod != 3 || c->modrm_rm != 1)
aca7f966
AL		 3167 goto cannot_emulate;
3168
7aa81cc0 3169 rc = kvm_fix_hypercall(ctxt->vcpu);
1b30eaa8 3170 if (rc != X86EMUL_CONTINUE)
7aa81cc0
AL		 3171 goto done;
3172
33e3885d 3173 /* Let the processor re-execute the fixed hypercall */
063db061 3174 c->eip = ctxt->eip;
16286d08
AK		 3175 /* Disable writeback. */
3176 c->dst.type = OP_NONE;
aca7f966 3177 break;
6aa8b732 3178 case 2: /* lgdt */
e4e03ded
LV		 3179 rc = read_descriptor(ctxt, ops, c->src.ptr,
3180 &size, &address, c->op_bytes);
1b30eaa8 3181 if (rc != X86EMUL_CONTINUE)
6aa8b732
AK		 3182 goto done;
3183 realmode_lgdt(ctxt->vcpu, size, address);
16286d08
AK		 3184 /* Disable writeback. */
3185 c->dst.type = OP_NONE;
6aa8b732 3186 break;
aca7f966 3187 case 3: /* lidt/vmmcall */
2b3d2a20
AK		 3188 if (c->modrm_mod == 3) {
3189 switch (c->modrm_rm) {
3190 case 1:
3191 rc = kvm_fix_hypercall(ctxt->vcpu);
1b30eaa8 3192 if (rc != X86EMUL_CONTINUE)
2b3d2a20
AK		 3193 goto done;
3194 break;
3195 default:
3196 goto cannot_emulate;
3197 }
aca7f966 3198 } else {
e4e03ded 3199 rc = read_descriptor(ctxt, ops, c->src.ptr,
aca7f966 3200 &size, &address,
e4e03ded 3201 c->op_bytes);
1b30eaa8 3202 if (rc != X86EMUL_CONTINUE)
aca7f966
AL		 3203 goto done;
3204 realmode_lidt(ctxt->vcpu, size, address);
3205 }
16286d08
AK		 3206 /* Disable writeback. */
3207 c->dst.type = OP_NONE;
6aa8b732
AK		 3208 break;
3209 case 4: /* smsw */
16286d08 3210 c->dst.bytes = 2;
52a46617 3211 c->dst.val = ops->get_cr(0, ctxt->vcpu);
6aa8b732
AK		 3212 break;
3213 case 6: /* lmsw */
93a152be
GN		 3214 ops->set_cr(0, (ops->get_cr(0, ctxt->vcpu) & ~0x0ful) |
3215 (c->src.val & 0x0f), ctxt->vcpu);
dc7457ea 3216 c->dst.type = OP_NONE;
6aa8b732 3217 break;
6e1e5ffe 3218 case 5: /* not defined */
54b8486f 3219 emulate_ud(ctxt);
6e1e5ffe 3220 goto done;
6aa8b732 3221 case 7: /* invlpg*/
69f55cb1 3222 emulate_invlpg(ctxt->vcpu, c->modrm_ea);
16286d08
AK		 3223 /* Disable writeback. */
3224 c->dst.type = OP_NONE;
6aa8b732
AK		 3225 break;
3226 default:
3227 goto cannot_emulate;
3228 }
3229 break;
e99f0507 3230 case 0x05: /* syscall */
3fb1b5db 3231 rc = emulate_syscall(ctxt, ops);
e54cfa97
TY		 3232 if (rc != X86EMUL_CONTINUE)
3233 goto done;
e66bb2cc
AP		 3234 else
3235 goto writeback;
e99f0507 3236 break;
018a98db
AK		 3237 case 0x06:
3238 emulate_clts(ctxt->vcpu);
3239 c->dst.type = OP_NONE;
3240 break;
018a98db 3241 case 0x09: /* wbinvd */
f5f48ee1
SY		 3242 kvm_emulate_wbinvd(ctxt->vcpu);
3243 c->dst.type = OP_NONE;
3244 break;
3245 case 0x08: /* invd */
018a98db
AK		 3246 case 0x0d: /* GrpP (prefetch) */
3247 case 0x18: /* Grp16 (prefetch/nop) */
3248 c->dst.type = OP_NONE;
3249 break;
3250 case 0x20: /* mov cr, reg */
6aebfa6e
GN		 3251 switch (c->modrm_reg) {
3252 case 1:
3253 case 5 ... 7:
3254 case 9 ... 15:
54b8486f 3255 emulate_ud(ctxt);
6aebfa6e
GN		 3256 goto done;
3257 }
52a46617 3258 c->regs[c->modrm_rm] = ops->get_cr(c->modrm_reg, ctxt->vcpu);
018a98db
AK		 3259 c->dst.type = OP_NONE; /* no writeback */
3260 break;
6aa8b732 3261 case 0x21: /* mov from dr to reg */
1e470be5
GN		 3262 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
3263 (c->modrm_reg == 4 || c->modrm_reg == 5)) {
54b8486f 3264 emulate_ud(ctxt);
1e470be5
GN		 3265 goto done;
3266 }
35aa5375 3267 ops->get_dr(c->modrm_reg, &c->regs[c->modrm_rm], ctxt->vcpu);
a01af5ec 3268 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 3269 break;
018a98db 3270 case 0x22: /* mov reg, cr */
0f12244f 3271 if (ops->set_cr(c->modrm_reg, c->modrm_val, ctxt->vcpu)) {
54b8486f 3272 emulate_gp(ctxt, 0);
0f12244f
GN		 3273 goto done;
3274 }
018a98db
AK		 3275 c->dst.type = OP_NONE;
3276 break;
6aa8b732 3277 case 0x23: /* mov from reg to dr */
1e470be5
GN		 3278 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
3279 (c->modrm_reg == 4 || c->modrm_reg == 5)) {
54b8486f 3280 emulate_ud(ctxt);
1e470be5
GN		 3281 goto done;
3282 }
35aa5375 3283
338dbc97
GN		 3284 if (ops->set_dr(c->modrm_reg, c->regs[c->modrm_rm] &
3285 ((ctxt->mode == X86EMUL_MODE_PROT64) ?
3286 ~0ULL : ~0U), ctxt->vcpu) < 0) {
3287 /* #UD condition is already handled by the code above */
54b8486f 3288 emulate_gp(ctxt, 0);
338dbc97
GN		 3289 goto done;
3290 }
3291
a01af5ec 3292 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 3293 break;
018a98db
AK		 3294 case 0x30:
3295 /* wrmsr */
3296 msr_data = (u32)c->regs[VCPU_REGS_RAX]
3297 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
3fb1b5db 3298 if (ops->set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data)) {
54b8486f 3299 emulate_gp(ctxt, 0);
fd525365 3300 goto done;
018a98db
AK		 3301 }
3302 rc = X86EMUL_CONTINUE;
3303 c->dst.type = OP_NONE;
3304 break;
3305 case 0x32:
3306 /* rdmsr */
3fb1b5db 3307 if (ops->get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data)) {
54b8486f 3308 emulate_gp(ctxt, 0);
fd525365 3309 goto done;
018a98db
AK		 3310 } else {
3311 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
3312 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
3313 }
3314 rc = X86EMUL_CONTINUE;
3315 c->dst.type = OP_NONE;
3316 break;
e99f0507 3317 case 0x34: /* sysenter */
3fb1b5db 3318 rc = emulate_sysenter(ctxt, ops);
e54cfa97
TY		 3319 if (rc != X86EMUL_CONTINUE)
3320 goto done;
8c604352
AP		 3321 else
3322 goto writeback;
e99f0507
AP		 3323 break;
3324 case 0x35: /* sysexit */
3fb1b5db 3325 rc = emulate_sysexit(ctxt, ops);
e54cfa97
TY		 3326 if (rc != X86EMUL_CONTINUE)
3327 goto done;
4668f050
AP		 3328 else
3329 goto writeback;
e99f0507 3330 break;
6aa8b732 3331 case 0x40 ... 0x4f: /* cmov */
e4e03ded 3332 c->dst.val = c->dst.orig_val = c->src.val;
a01af5ec
LV		 3333 if (!test_cc(c->b, ctxt->eflags))
3334 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 3335 break;
b2833e3c 3336 case 0x80 ... 0x8f: /* jnz rel, etc*/
018a98db 3337 if (test_cc(c->b, ctxt->eflags))
b2833e3c 3338 jmp_rel(c, c->src.val);
018a98db
AK		 3339 c->dst.type = OP_NONE;
3340 break;
0934ac9d 3341 case 0xa0: /* push fs */
79168fd1 3342 emulate_push_sreg(ctxt, ops, VCPU_SREG_FS);
0934ac9d
MG		 3343 break;
3344 case 0xa1: /* pop fs */
3345 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS);
1b30eaa8 3346 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 3347 goto done;
3348 break;
7de75248
NK		 3349 case 0xa3:
3350 bt: /* bt */
e4f8e039 3351 c->dst.type = OP_NONE;
e4e03ded
LV		 3352 /* only subword offset */
3353 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3354 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
7de75248 3355 break;
9bf8ea42
GT		 3356 case 0xa4: /* shld imm8, r, r/m */
3357 case 0xa5: /* shld cl, r, r/m */
3358 emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
3359 break;
0934ac9d 3360 case 0xa8: /* push gs */
79168fd1 3361 emulate_push_sreg(ctxt, ops, VCPU_SREG_GS);
0934ac9d
MG		 3362 break;
3363 case 0xa9: /* pop gs */
3364 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS);
1b30eaa8 3365 if (rc != X86EMUL_CONTINUE)
0934ac9d
MG		 3366 goto done;
3367 break;
7de75248
NK		 3368 case 0xab:
3369 bts: /* bts */
e4e03ded
LV		 3370 /* only subword offset */
3371 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3372 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
7de75248 3373 break;
9bf8ea42
GT		 3374 case 0xac: /* shrd imm8, r, r/m */
3375 case 0xad: /* shrd cl, r, r/m */
3376 emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags);
3377 break;
2a7c5b8b
GC		 3378 case 0xae: /* clflush */
3379 break;
6aa8b732
AK		 3380 case 0xb0 ... 0xb1: /* cmpxchg */
3381 /*
3382 * Save real source value, then compare EAX against
3383 * destination.
3384 */
e4e03ded
LV		 3385 c->src.orig_val = c->src.val;
3386 c->src.val = c->regs[VCPU_REGS_RAX];
05f086f8
LV		 3387 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
3388 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 3389 /* Success: write back to memory. */
e4e03ded 3390 c->dst.val = c->src.orig_val;
6aa8b732
AK		 3391 } else {
3392 /* Failure: write the value we saw to EAX. */
e4e03ded
LV		 3393 c->dst.type = OP_REG;
3394 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 3395 }
3396 break;
6aa8b732
AK		 3397 case 0xb3:
3398 btr: /* btr */
e4e03ded
LV		 3399 /* only subword offset */
3400 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3401 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
6aa8b732 3402 break;
6aa8b732 3403 case 0xb6 ... 0xb7: /* movzx */
e4e03ded
LV		 3404 c->dst.bytes = c->op_bytes;
3405 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
3406 : (u16) c->src.val;
6aa8b732 3407 break;
6aa8b732 3408 case 0xba: /* Grp8 */
e4e03ded 3409 switch (c->modrm_reg & 3) {
6aa8b732
AK		 3410 case 0:
3411 goto bt;
3412 case 1:
3413 goto bts;
3414 case 2:
3415 goto btr;
3416 case 3:
3417 goto btc;
3418 }
3419 break;
7de75248
NK		 3420 case 0xbb:
3421 btc: /* btc */
e4e03ded
LV		 3422 /* only subword offset */
3423 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 3424 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
7de75248 3425 break;
6aa8b732 3426 case 0xbe ... 0xbf: /* movsx */
e4e03ded
LV		 3427 c->dst.bytes = c->op_bytes;
3428 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
3429 (s16) c->src.val;
6aa8b732 3430 break;
a012e65a 3431 case 0xc3: /* movnti */
e4e03ded
LV		 3432 c->dst.bytes = c->op_bytes;
3433 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
3434 (u64) c->src.val;
a012e65a 3435 break;
6aa8b732 3436 case 0xc7: /* Grp9 (cmpxchg8b) */
69f55cb1 3437 rc = emulate_grp9(ctxt, ops);
1b30eaa8 3438 if (rc != X86EMUL_CONTINUE)
8cdbd2c9
LV		 3439 goto done;
3440 break;
91269b8f
AK		 3441 default:
3442 goto cannot_emulate;
6aa8b732
AK		 3443 }
3444 goto writeback;
3445
3446cannot_emulate:
e4e03ded 3447 DPRINTF("Cannot emulate %02x\n", c->b);
6aa8b732
AK		 3448 return -1;
3449}
Linux kernel - Deliverables
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