Commit | Line | Data |
---|---|---|
7837699f SY |
1 | /* |
2 | * 8253/8254 interval timer emulation | |
3 | * | |
4 | * Copyright (c) 2003-2004 Fabrice Bellard | |
5 | * Copyright (c) 2006 Intel Corporation | |
6 | * Copyright (c) 2007 Keir Fraser, XenSource Inc | |
7 | * Copyright (c) 2008 Intel Corporation | |
8 | * | |
9 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
10 | * of this software and associated documentation files (the "Software"), to deal | |
11 | * in the Software without restriction, including without limitation the rights | |
12 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
13 | * copies of the Software, and to permit persons to whom the Software is | |
14 | * furnished to do so, subject to the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice shall be included in | |
17 | * all copies or substantial portions of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
20 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
21 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
22 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
23 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
24 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
25 | * THE SOFTWARE. | |
26 | * | |
27 | * Authors: | |
28 | * Sheng Yang <sheng.yang@intel.com> | |
29 | * Based on QEMU and Xen. | |
30 | */ | |
31 | ||
32 | #include <linux/kvm_host.h> | |
33 | ||
34 | #include "irq.h" | |
35 | #include "i8254.h" | |
36 | ||
37 | #ifndef CONFIG_X86_64 | |
6f6d6a1a | 38 | #define mod_64(x, y) ((x) - (y) * div64_u64(x, y)) |
7837699f SY |
39 | #else |
40 | #define mod_64(x, y) ((x) % (y)) | |
41 | #endif | |
42 | ||
43 | #define RW_STATE_LSB 1 | |
44 | #define RW_STATE_MSB 2 | |
45 | #define RW_STATE_WORD0 3 | |
46 | #define RW_STATE_WORD1 4 | |
47 | ||
48 | /* Compute with 96 bit intermediate result: (a*b)/c */ | |
49 | static u64 muldiv64(u64 a, u32 b, u32 c) | |
50 | { | |
51 | union { | |
52 | u64 ll; | |
53 | struct { | |
54 | u32 low, high; | |
55 | } l; | |
56 | } u, res; | |
57 | u64 rl, rh; | |
58 | ||
59 | u.ll = a; | |
60 | rl = (u64)u.l.low * (u64)b; | |
61 | rh = (u64)u.l.high * (u64)b; | |
62 | rh += (rl >> 32); | |
6f6d6a1a RZ |
63 | res.l.high = div64_u64(rh, c); |
64 | res.l.low = div64_u64(((mod_64(rh, c) << 32) + (rl & 0xffffffff)), c); | |
7837699f SY |
65 | return res.ll; |
66 | } | |
67 | ||
68 | static void pit_set_gate(struct kvm *kvm, int channel, u32 val) | |
69 | { | |
70 | struct kvm_kpit_channel_state *c = | |
71 | &kvm->arch.vpit->pit_state.channels[channel]; | |
72 | ||
73 | WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock)); | |
74 | ||
75 | switch (c->mode) { | |
76 | default: | |
77 | case 0: | |
78 | case 4: | |
79 | /* XXX: just disable/enable counting */ | |
80 | break; | |
81 | case 1: | |
82 | case 2: | |
83 | case 3: | |
84 | case 5: | |
85 | /* Restart counting on rising edge. */ | |
86 | if (c->gate < val) | |
87 | c->count_load_time = ktime_get(); | |
88 | break; | |
89 | } | |
90 | ||
91 | c->gate = val; | |
92 | } | |
93 | ||
8b2cf73c | 94 | static int pit_get_gate(struct kvm *kvm, int channel) |
7837699f SY |
95 | { |
96 | WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock)); | |
97 | ||
98 | return kvm->arch.vpit->pit_state.channels[channel].gate; | |
99 | } | |
100 | ||
fd668423 MT |
101 | static s64 __kpit_elapsed(struct kvm *kvm) |
102 | { | |
103 | s64 elapsed; | |
104 | ktime_t remaining; | |
105 | struct kvm_kpit_state *ps = &kvm->arch.vpit->pit_state; | |
106 | ||
0ff77873 MT |
107 | if (!ps->pit_timer.period) |
108 | return 0; | |
109 | ||
ede2ccc5 MT |
110 | /* |
111 | * The Counter does not stop when it reaches zero. In | |
112 | * Modes 0, 1, 4, and 5 the Counter ``wraps around'' to | |
113 | * the highest count, either FFFF hex for binary counting | |
114 | * or 9999 for BCD counting, and continues counting. | |
115 | * Modes 2 and 3 are periodic; the Counter reloads | |
116 | * itself with the initial count and continues counting | |
117 | * from there. | |
118 | */ | |
ace15464 | 119 | remaining = hrtimer_get_remaining(&ps->pit_timer.timer); |
ede2ccc5 MT |
120 | elapsed = ps->pit_timer.period - ktime_to_ns(remaining); |
121 | elapsed = mod_64(elapsed, ps->pit_timer.period); | |
fd668423 MT |
122 | |
123 | return elapsed; | |
124 | } | |
125 | ||
126 | static s64 kpit_elapsed(struct kvm *kvm, struct kvm_kpit_channel_state *c, | |
127 | int channel) | |
128 | { | |
129 | if (channel == 0) | |
130 | return __kpit_elapsed(kvm); | |
131 | ||
132 | return ktime_to_ns(ktime_sub(ktime_get(), c->count_load_time)); | |
133 | } | |
134 | ||
7837699f SY |
135 | static int pit_get_count(struct kvm *kvm, int channel) |
136 | { | |
137 | struct kvm_kpit_channel_state *c = | |
138 | &kvm->arch.vpit->pit_state.channels[channel]; | |
139 | s64 d, t; | |
140 | int counter; | |
141 | ||
142 | WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock)); | |
143 | ||
fd668423 | 144 | t = kpit_elapsed(kvm, c, channel); |
7837699f SY |
145 | d = muldiv64(t, KVM_PIT_FREQ, NSEC_PER_SEC); |
146 | ||
147 | switch (c->mode) { | |
148 | case 0: | |
149 | case 1: | |
150 | case 4: | |
151 | case 5: | |
152 | counter = (c->count - d) & 0xffff; | |
153 | break; | |
154 | case 3: | |
155 | /* XXX: may be incorrect for odd counts */ | |
156 | counter = c->count - (mod_64((2 * d), c->count)); | |
157 | break; | |
158 | default: | |
159 | counter = c->count - mod_64(d, c->count); | |
160 | break; | |
161 | } | |
162 | return counter; | |
163 | } | |
164 | ||
165 | static int pit_get_out(struct kvm *kvm, int channel) | |
166 | { | |
167 | struct kvm_kpit_channel_state *c = | |
168 | &kvm->arch.vpit->pit_state.channels[channel]; | |
169 | s64 d, t; | |
170 | int out; | |
171 | ||
172 | WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock)); | |
173 | ||
fd668423 | 174 | t = kpit_elapsed(kvm, c, channel); |
7837699f SY |
175 | d = muldiv64(t, KVM_PIT_FREQ, NSEC_PER_SEC); |
176 | ||
177 | switch (c->mode) { | |
178 | default: | |
179 | case 0: | |
180 | out = (d >= c->count); | |
181 | break; | |
182 | case 1: | |
183 | out = (d < c->count); | |
184 | break; | |
185 | case 2: | |
186 | out = ((mod_64(d, c->count) == 0) && (d != 0)); | |
187 | break; | |
188 | case 3: | |
189 | out = (mod_64(d, c->count) < ((c->count + 1) >> 1)); | |
190 | break; | |
191 | case 4: | |
192 | case 5: | |
193 | out = (d == c->count); | |
194 | break; | |
195 | } | |
196 | ||
197 | return out; | |
198 | } | |
199 | ||
200 | static void pit_latch_count(struct kvm *kvm, int channel) | |
201 | { | |
202 | struct kvm_kpit_channel_state *c = | |
203 | &kvm->arch.vpit->pit_state.channels[channel]; | |
204 | ||
205 | WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock)); | |
206 | ||
207 | if (!c->count_latched) { | |
208 | c->latched_count = pit_get_count(kvm, channel); | |
209 | c->count_latched = c->rw_mode; | |
210 | } | |
211 | } | |
212 | ||
213 | static void pit_latch_status(struct kvm *kvm, int channel) | |
214 | { | |
215 | struct kvm_kpit_channel_state *c = | |
216 | &kvm->arch.vpit->pit_state.channels[channel]; | |
217 | ||
218 | WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock)); | |
219 | ||
220 | if (!c->status_latched) { | |
221 | /* TODO: Return NULL COUNT (bit 6). */ | |
222 | c->status = ((pit_get_out(kvm, channel) << 7) | | |
223 | (c->rw_mode << 4) | | |
224 | (c->mode << 1) | | |
225 | c->bcd); | |
226 | c->status_latched = 1; | |
227 | } | |
228 | } | |
229 | ||
3d80840d MT |
230 | int pit_has_pending_timer(struct kvm_vcpu *vcpu) |
231 | { | |
232 | struct kvm_pit *pit = vcpu->kvm->arch.vpit; | |
233 | ||
c5af89b6 | 234 | if (pit && kvm_vcpu_is_bsp(vcpu) && pit->pit_state.irq_ack) |
3d80840d | 235 | return atomic_read(&pit->pit_state.pit_timer.pending); |
3d80840d MT |
236 | return 0; |
237 | } | |
238 | ||
ee032c99 | 239 | static void kvm_pit_ack_irq(struct kvm_irq_ack_notifier *kian) |
3cf57fed MT |
240 | { |
241 | struct kvm_kpit_state *ps = container_of(kian, struct kvm_kpit_state, | |
242 | irq_ack_notifier); | |
243 | spin_lock(&ps->inject_lock); | |
244 | if (atomic_dec_return(&ps->pit_timer.pending) < 0) | |
dc7404ce | 245 | atomic_inc(&ps->pit_timer.pending); |
3cf57fed MT |
246 | ps->irq_ack = 1; |
247 | spin_unlock(&ps->inject_lock); | |
248 | } | |
249 | ||
2f599714 MT |
250 | void __kvm_migrate_pit_timer(struct kvm_vcpu *vcpu) |
251 | { | |
252 | struct kvm_pit *pit = vcpu->kvm->arch.vpit; | |
253 | struct hrtimer *timer; | |
254 | ||
c5af89b6 | 255 | if (!kvm_vcpu_is_bsp(vcpu) || !pit) |
2f599714 MT |
256 | return; |
257 | ||
258 | timer = &pit->pit_state.pit_timer.timer; | |
259 | if (hrtimer_cancel(timer)) | |
beb20d52 | 260 | hrtimer_start_expires(timer, HRTIMER_MODE_ABS); |
2f599714 MT |
261 | } |
262 | ||
d3c7b77d | 263 | static void destroy_pit_timer(struct kvm_timer *pt) |
7837699f SY |
264 | { |
265 | pr_debug("pit: execute del timer!\n"); | |
266 | hrtimer_cancel(&pt->timer); | |
267 | } | |
268 | ||
d3c7b77d MT |
269 | static bool kpit_is_periodic(struct kvm_timer *ktimer) |
270 | { | |
271 | struct kvm_kpit_state *ps = container_of(ktimer, struct kvm_kpit_state, | |
272 | pit_timer); | |
273 | return ps->is_periodic; | |
274 | } | |
275 | ||
386eb6e8 | 276 | static struct kvm_timer_ops kpit_ops = { |
d3c7b77d MT |
277 | .is_periodic = kpit_is_periodic, |
278 | }; | |
279 | ||
3cf57fed | 280 | static void create_pit_timer(struct kvm_kpit_state *ps, u32 val, int is_period) |
7837699f | 281 | { |
d3c7b77d | 282 | struct kvm_timer *pt = &ps->pit_timer; |
7837699f SY |
283 | s64 interval; |
284 | ||
285 | interval = muldiv64(val, NSEC_PER_SEC, KVM_PIT_FREQ); | |
286 | ||
287 | pr_debug("pit: create pit timer, interval is %llu nsec\n", interval); | |
288 | ||
289 | /* TODO The new value only affected after the retriggered */ | |
290 | hrtimer_cancel(&pt->timer); | |
ede2ccc5 | 291 | pt->period = interval; |
d3c7b77d MT |
292 | ps->is_periodic = is_period; |
293 | ||
294 | pt->timer.function = kvm_timer_fn; | |
295 | pt->t_ops = &kpit_ops; | |
296 | pt->kvm = ps->pit->kvm; | |
1ed0ce00 | 297 | pt->vcpu = pt->kvm->bsp_vcpu; |
d3c7b77d | 298 | |
7837699f | 299 | atomic_set(&pt->pending, 0); |
3cf57fed | 300 | ps->irq_ack = 1; |
7837699f SY |
301 | |
302 | hrtimer_start(&pt->timer, ktime_add_ns(ktime_get(), interval), | |
303 | HRTIMER_MODE_ABS); | |
304 | } | |
305 | ||
306 | static void pit_load_count(struct kvm *kvm, int channel, u32 val) | |
307 | { | |
308 | struct kvm_kpit_state *ps = &kvm->arch.vpit->pit_state; | |
309 | ||
310 | WARN_ON(!mutex_is_locked(&ps->lock)); | |
311 | ||
312 | pr_debug("pit: load_count val is %d, channel is %d\n", val, channel); | |
313 | ||
314 | /* | |
ede2ccc5 MT |
315 | * The largest possible initial count is 0; this is equivalent |
316 | * to 216 for binary counting and 104 for BCD counting. | |
7837699f SY |
317 | */ |
318 | if (val == 0) | |
319 | val = 0x10000; | |
320 | ||
7837699f SY |
321 | ps->channels[channel].count = val; |
322 | ||
fd668423 MT |
323 | if (channel != 0) { |
324 | ps->channels[channel].count_load_time = ktime_get(); | |
7837699f | 325 | return; |
fd668423 | 326 | } |
7837699f SY |
327 | |
328 | /* Two types of timer | |
329 | * mode 1 is one shot, mode 2 is period, otherwise del timer */ | |
330 | switch (ps->channels[0].mode) { | |
ede2ccc5 | 331 | case 0: |
7837699f | 332 | case 1: |
ece15bab MT |
333 | /* FIXME: enhance mode 4 precision */ |
334 | case 4: | |
e9f42757 BK |
335 | if (!(ps->flags & KVM_PIT_FLAGS_HPET_LEGACY)) { |
336 | create_pit_timer(ps, val, 0); | |
337 | } | |
7837699f SY |
338 | break; |
339 | case 2: | |
f6975545 | 340 | case 3: |
e9f42757 BK |
341 | if (!(ps->flags & KVM_PIT_FLAGS_HPET_LEGACY)){ |
342 | create_pit_timer(ps, val, 1); | |
343 | } | |
7837699f SY |
344 | break; |
345 | default: | |
346 | destroy_pit_timer(&ps->pit_timer); | |
347 | } | |
348 | } | |
349 | ||
e9f42757 | 350 | void kvm_pit_load_count(struct kvm *kvm, int channel, u32 val, int hpet_legacy_start) |
e0f63cb9 | 351 | { |
e9f42757 BK |
352 | u8 saved_mode; |
353 | if (hpet_legacy_start) { | |
354 | /* save existing mode for later reenablement */ | |
355 | saved_mode = kvm->arch.vpit->pit_state.channels[0].mode; | |
356 | kvm->arch.vpit->pit_state.channels[0].mode = 0xff; /* disable timer */ | |
357 | pit_load_count(kvm, channel, val); | |
358 | kvm->arch.vpit->pit_state.channels[0].mode = saved_mode; | |
359 | } else { | |
360 | pit_load_count(kvm, channel, val); | |
361 | } | |
e0f63cb9 SY |
362 | } |
363 | ||
d76685c4 GH |
364 | static inline struct kvm_pit *dev_to_pit(struct kvm_io_device *dev) |
365 | { | |
366 | return container_of(dev, struct kvm_pit, dev); | |
367 | } | |
368 | ||
369 | static inline struct kvm_pit *speaker_to_pit(struct kvm_io_device *dev) | |
370 | { | |
371 | return container_of(dev, struct kvm_pit, speaker_dev); | |
372 | } | |
373 | ||
bda9020e MT |
374 | static inline int pit_in_range(gpa_t addr) |
375 | { | |
376 | return ((addr >= KVM_PIT_BASE_ADDRESS) && | |
377 | (addr < KVM_PIT_BASE_ADDRESS + KVM_PIT_MEM_LENGTH)); | |
378 | } | |
379 | ||
380 | static int pit_ioport_write(struct kvm_io_device *this, | |
381 | gpa_t addr, int len, const void *data) | |
7837699f | 382 | { |
d76685c4 | 383 | struct kvm_pit *pit = dev_to_pit(this); |
7837699f SY |
384 | struct kvm_kpit_state *pit_state = &pit->pit_state; |
385 | struct kvm *kvm = pit->kvm; | |
386 | int channel, access; | |
387 | struct kvm_kpit_channel_state *s; | |
388 | u32 val = *(u32 *) data; | |
bda9020e MT |
389 | if (!pit_in_range(addr)) |
390 | return -EOPNOTSUPP; | |
7837699f SY |
391 | |
392 | val &= 0xff; | |
393 | addr &= KVM_PIT_CHANNEL_MASK; | |
394 | ||
395 | mutex_lock(&pit_state->lock); | |
396 | ||
397 | if (val != 0) | |
398 | pr_debug("pit: write addr is 0x%x, len is %d, val is 0x%x\n", | |
399 | (unsigned int)addr, len, val); | |
400 | ||
401 | if (addr == 3) { | |
402 | channel = val >> 6; | |
403 | if (channel == 3) { | |
404 | /* Read-Back Command. */ | |
405 | for (channel = 0; channel < 3; channel++) { | |
406 | s = &pit_state->channels[channel]; | |
407 | if (val & (2 << channel)) { | |
408 | if (!(val & 0x20)) | |
409 | pit_latch_count(kvm, channel); | |
410 | if (!(val & 0x10)) | |
411 | pit_latch_status(kvm, channel); | |
412 | } | |
413 | } | |
414 | } else { | |
415 | /* Select Counter <channel>. */ | |
416 | s = &pit_state->channels[channel]; | |
417 | access = (val >> 4) & KVM_PIT_CHANNEL_MASK; | |
418 | if (access == 0) { | |
419 | pit_latch_count(kvm, channel); | |
420 | } else { | |
421 | s->rw_mode = access; | |
422 | s->read_state = access; | |
423 | s->write_state = access; | |
424 | s->mode = (val >> 1) & 7; | |
425 | if (s->mode > 5) | |
426 | s->mode -= 4; | |
427 | s->bcd = val & 1; | |
428 | } | |
429 | } | |
430 | } else { | |
431 | /* Write Count. */ | |
432 | s = &pit_state->channels[addr]; | |
433 | switch (s->write_state) { | |
434 | default: | |
435 | case RW_STATE_LSB: | |
436 | pit_load_count(kvm, addr, val); | |
437 | break; | |
438 | case RW_STATE_MSB: | |
439 | pit_load_count(kvm, addr, val << 8); | |
440 | break; | |
441 | case RW_STATE_WORD0: | |
442 | s->write_latch = val; | |
443 | s->write_state = RW_STATE_WORD1; | |
444 | break; | |
445 | case RW_STATE_WORD1: | |
446 | pit_load_count(kvm, addr, s->write_latch | (val << 8)); | |
447 | s->write_state = RW_STATE_WORD0; | |
448 | break; | |
449 | } | |
450 | } | |
451 | ||
452 | mutex_unlock(&pit_state->lock); | |
bda9020e | 453 | return 0; |
7837699f SY |
454 | } |
455 | ||
bda9020e MT |
456 | static int pit_ioport_read(struct kvm_io_device *this, |
457 | gpa_t addr, int len, void *data) | |
7837699f | 458 | { |
d76685c4 | 459 | struct kvm_pit *pit = dev_to_pit(this); |
7837699f SY |
460 | struct kvm_kpit_state *pit_state = &pit->pit_state; |
461 | struct kvm *kvm = pit->kvm; | |
462 | int ret, count; | |
463 | struct kvm_kpit_channel_state *s; | |
bda9020e MT |
464 | if (!pit_in_range(addr)) |
465 | return -EOPNOTSUPP; | |
7837699f SY |
466 | |
467 | addr &= KVM_PIT_CHANNEL_MASK; | |
468 | s = &pit_state->channels[addr]; | |
469 | ||
470 | mutex_lock(&pit_state->lock); | |
471 | ||
472 | if (s->status_latched) { | |
473 | s->status_latched = 0; | |
474 | ret = s->status; | |
475 | } else if (s->count_latched) { | |
476 | switch (s->count_latched) { | |
477 | default: | |
478 | case RW_STATE_LSB: | |
479 | ret = s->latched_count & 0xff; | |
480 | s->count_latched = 0; | |
481 | break; | |
482 | case RW_STATE_MSB: | |
483 | ret = s->latched_count >> 8; | |
484 | s->count_latched = 0; | |
485 | break; | |
486 | case RW_STATE_WORD0: | |
487 | ret = s->latched_count & 0xff; | |
488 | s->count_latched = RW_STATE_MSB; | |
489 | break; | |
490 | } | |
491 | } else { | |
492 | switch (s->read_state) { | |
493 | default: | |
494 | case RW_STATE_LSB: | |
495 | count = pit_get_count(kvm, addr); | |
496 | ret = count & 0xff; | |
497 | break; | |
498 | case RW_STATE_MSB: | |
499 | count = pit_get_count(kvm, addr); | |
500 | ret = (count >> 8) & 0xff; | |
501 | break; | |
502 | case RW_STATE_WORD0: | |
503 | count = pit_get_count(kvm, addr); | |
504 | ret = count & 0xff; | |
505 | s->read_state = RW_STATE_WORD1; | |
506 | break; | |
507 | case RW_STATE_WORD1: | |
508 | count = pit_get_count(kvm, addr); | |
509 | ret = (count >> 8) & 0xff; | |
510 | s->read_state = RW_STATE_WORD0; | |
511 | break; | |
512 | } | |
513 | } | |
514 | ||
515 | if (len > sizeof(ret)) | |
516 | len = sizeof(ret); | |
517 | memcpy(data, (char *)&ret, len); | |
518 | ||
519 | mutex_unlock(&pit_state->lock); | |
bda9020e | 520 | return 0; |
7837699f SY |
521 | } |
522 | ||
bda9020e MT |
523 | static int speaker_ioport_write(struct kvm_io_device *this, |
524 | gpa_t addr, int len, const void *data) | |
7837699f | 525 | { |
d76685c4 | 526 | struct kvm_pit *pit = speaker_to_pit(this); |
7837699f SY |
527 | struct kvm_kpit_state *pit_state = &pit->pit_state; |
528 | struct kvm *kvm = pit->kvm; | |
529 | u32 val = *(u32 *) data; | |
bda9020e MT |
530 | if (addr != KVM_SPEAKER_BASE_ADDRESS) |
531 | return -EOPNOTSUPP; | |
7837699f SY |
532 | |
533 | mutex_lock(&pit_state->lock); | |
534 | pit_state->speaker_data_on = (val >> 1) & 1; | |
535 | pit_set_gate(kvm, 2, val & 1); | |
536 | mutex_unlock(&pit_state->lock); | |
bda9020e | 537 | return 0; |
7837699f SY |
538 | } |
539 | ||
bda9020e MT |
540 | static int speaker_ioport_read(struct kvm_io_device *this, |
541 | gpa_t addr, int len, void *data) | |
7837699f | 542 | { |
d76685c4 | 543 | struct kvm_pit *pit = speaker_to_pit(this); |
7837699f SY |
544 | struct kvm_kpit_state *pit_state = &pit->pit_state; |
545 | struct kvm *kvm = pit->kvm; | |
546 | unsigned int refresh_clock; | |
547 | int ret; | |
bda9020e MT |
548 | if (addr != KVM_SPEAKER_BASE_ADDRESS) |
549 | return -EOPNOTSUPP; | |
7837699f SY |
550 | |
551 | /* Refresh clock toggles at about 15us. We approximate as 2^14ns. */ | |
552 | refresh_clock = ((unsigned int)ktime_to_ns(ktime_get()) >> 14) & 1; | |
553 | ||
554 | mutex_lock(&pit_state->lock); | |
555 | ret = ((pit_state->speaker_data_on << 1) | pit_get_gate(kvm, 2) | | |
556 | (pit_get_out(kvm, 2) << 5) | (refresh_clock << 4)); | |
557 | if (len > sizeof(ret)) | |
558 | len = sizeof(ret); | |
559 | memcpy(data, (char *)&ret, len); | |
560 | mutex_unlock(&pit_state->lock); | |
bda9020e | 561 | return 0; |
7837699f SY |
562 | } |
563 | ||
308b0f23 | 564 | void kvm_pit_reset(struct kvm_pit *pit) |
7837699f SY |
565 | { |
566 | int i; | |
308b0f23 SY |
567 | struct kvm_kpit_channel_state *c; |
568 | ||
569 | mutex_lock(&pit->pit_state.lock); | |
e9f42757 | 570 | pit->pit_state.flags = 0; |
308b0f23 SY |
571 | for (i = 0; i < 3; i++) { |
572 | c = &pit->pit_state.channels[i]; | |
573 | c->mode = 0xff; | |
574 | c->gate = (i != 2); | |
575 | pit_load_count(pit->kvm, i, 0); | |
576 | } | |
577 | mutex_unlock(&pit->pit_state.lock); | |
578 | ||
579 | atomic_set(&pit->pit_state.pit_timer.pending, 0); | |
3cf57fed | 580 | pit->pit_state.irq_ack = 1; |
308b0f23 SY |
581 | } |
582 | ||
4780c659 AK |
583 | static void pit_mask_notifer(struct kvm_irq_mask_notifier *kimn, bool mask) |
584 | { | |
585 | struct kvm_pit *pit = container_of(kimn, struct kvm_pit, mask_notifier); | |
586 | ||
587 | if (!mask) { | |
588 | atomic_set(&pit->pit_state.pit_timer.pending, 0); | |
589 | pit->pit_state.irq_ack = 1; | |
590 | } | |
591 | } | |
592 | ||
d76685c4 GH |
593 | static const struct kvm_io_device_ops pit_dev_ops = { |
594 | .read = pit_ioport_read, | |
595 | .write = pit_ioport_write, | |
d76685c4 GH |
596 | }; |
597 | ||
598 | static const struct kvm_io_device_ops speaker_dev_ops = { | |
599 | .read = speaker_ioport_read, | |
600 | .write = speaker_ioport_write, | |
d76685c4 GH |
601 | }; |
602 | ||
6c474694 | 603 | /* Caller must have writers lock on slots_lock */ |
c5ff41ce | 604 | struct kvm_pit *kvm_create_pit(struct kvm *kvm, u32 flags) |
308b0f23 | 605 | { |
7837699f SY |
606 | struct kvm_pit *pit; |
607 | struct kvm_kpit_state *pit_state; | |
090b7aff | 608 | int ret; |
7837699f SY |
609 | |
610 | pit = kzalloc(sizeof(struct kvm_pit), GFP_KERNEL); | |
611 | if (!pit) | |
612 | return NULL; | |
613 | ||
5550af4d | 614 | pit->irq_source_id = kvm_request_irq_source_id(kvm); |
e17d1dc0 AK |
615 | if (pit->irq_source_id < 0) { |
616 | kfree(pit); | |
5550af4d | 617 | return NULL; |
e17d1dc0 | 618 | } |
5550af4d | 619 | |
7837699f SY |
620 | mutex_init(&pit->pit_state.lock); |
621 | mutex_lock(&pit->pit_state.lock); | |
3cf57fed | 622 | spin_lock_init(&pit->pit_state.inject_lock); |
7837699f | 623 | |
7837699f SY |
624 | kvm->arch.vpit = pit; |
625 | pit->kvm = kvm; | |
626 | ||
627 | pit_state = &pit->pit_state; | |
628 | pit_state->pit = pit; | |
629 | hrtimer_init(&pit_state->pit_timer.timer, | |
630 | CLOCK_MONOTONIC, HRTIMER_MODE_ABS); | |
3cf57fed MT |
631 | pit_state->irq_ack_notifier.gsi = 0; |
632 | pit_state->irq_ack_notifier.irq_acked = kvm_pit_ack_irq; | |
633 | kvm_register_irq_ack_notifier(kvm, &pit_state->irq_ack_notifier); | |
52d939a0 | 634 | pit_state->pit_timer.reinject = true; |
7837699f SY |
635 | mutex_unlock(&pit->pit_state.lock); |
636 | ||
308b0f23 | 637 | kvm_pit_reset(pit); |
7837699f | 638 | |
4780c659 AK |
639 | pit->mask_notifier.func = pit_mask_notifer; |
640 | kvm_register_irq_mask_notifier(kvm, 0, &pit->mask_notifier); | |
641 | ||
6b66ac1a | 642 | kvm_iodevice_init(&pit->dev, &pit_dev_ops); |
090b7aff GH |
643 | ret = __kvm_io_bus_register_dev(&kvm->pio_bus, &pit->dev); |
644 | if (ret < 0) | |
645 | goto fail; | |
6b66ac1a GH |
646 | |
647 | if (flags & KVM_PIT_SPEAKER_DUMMY) { | |
648 | kvm_iodevice_init(&pit->speaker_dev, &speaker_dev_ops); | |
090b7aff GH |
649 | ret = __kvm_io_bus_register_dev(&kvm->pio_bus, |
650 | &pit->speaker_dev); | |
651 | if (ret < 0) | |
652 | goto fail_unregister; | |
6b66ac1a GH |
653 | } |
654 | ||
7837699f | 655 | return pit; |
090b7aff GH |
656 | |
657 | fail_unregister: | |
658 | __kvm_io_bus_unregister_dev(&kvm->pio_bus, &pit->dev); | |
659 | ||
660 | fail: | |
661 | if (pit->irq_source_id >= 0) | |
662 | kvm_free_irq_source_id(kvm, pit->irq_source_id); | |
663 | ||
664 | kfree(pit); | |
665 | return NULL; | |
7837699f SY |
666 | } |
667 | ||
668 | void kvm_free_pit(struct kvm *kvm) | |
669 | { | |
670 | struct hrtimer *timer; | |
671 | ||
672 | if (kvm->arch.vpit) { | |
4780c659 AK |
673 | kvm_unregister_irq_mask_notifier(kvm, 0, |
674 | &kvm->arch.vpit->mask_notifier); | |
84fde248 GN |
675 | kvm_unregister_irq_ack_notifier(kvm, |
676 | &kvm->arch.vpit->pit_state.irq_ack_notifier); | |
7837699f SY |
677 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
678 | timer = &kvm->arch.vpit->pit_state.pit_timer.timer; | |
679 | hrtimer_cancel(timer); | |
5550af4d | 680 | kvm_free_irq_source_id(kvm, kvm->arch.vpit->irq_source_id); |
7837699f SY |
681 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); |
682 | kfree(kvm->arch.vpit); | |
683 | } | |
684 | } | |
685 | ||
8b2cf73c | 686 | static void __inject_pit_timer_intr(struct kvm *kvm) |
7837699f | 687 | { |
23930f95 JK |
688 | struct kvm_vcpu *vcpu; |
689 | int i; | |
690 | ||
5550af4d SY |
691 | kvm_set_irq(kvm, kvm->arch.vpit->irq_source_id, 0, 1); |
692 | kvm_set_irq(kvm, kvm->arch.vpit->irq_source_id, 0, 0); | |
23930f95 JK |
693 | |
694 | /* | |
8fdb2351 JK |
695 | * Provides NMI watchdog support via Virtual Wire mode. |
696 | * The route is: PIT -> PIC -> LVT0 in NMI mode. | |
697 | * | |
698 | * Note: Our Virtual Wire implementation is simplified, only | |
699 | * propagating PIT interrupts to all VCPUs when they have set | |
700 | * LVT0 to NMI delivery. Other PIC interrupts are just sent to | |
701 | * VCPU0, and only if its LVT0 is in EXTINT mode. | |
23930f95 | 702 | */ |
cc6e462c | 703 | if (kvm->arch.vapics_in_nmi_mode > 0) |
988a2cae GN |
704 | kvm_for_each_vcpu(i, vcpu, kvm) |
705 | kvm_apic_nmi_wd_deliver(vcpu); | |
7837699f SY |
706 | } |
707 | ||
708 | void kvm_inject_pit_timer_irqs(struct kvm_vcpu *vcpu) | |
709 | { | |
710 | struct kvm_pit *pit = vcpu->kvm->arch.vpit; | |
711 | struct kvm *kvm = vcpu->kvm; | |
712 | struct kvm_kpit_state *ps; | |
713 | ||
95fb4eb6 | 714 | if (pit) { |
3cf57fed | 715 | int inject = 0; |
7837699f SY |
716 | ps = &pit->pit_state; |
717 | ||
3cf57fed MT |
718 | /* Try to inject pending interrupts when |
719 | * last one has been acked. | |
720 | */ | |
721 | spin_lock(&ps->inject_lock); | |
722 | if (atomic_read(&ps->pit_timer.pending) && ps->irq_ack) { | |
723 | ps->irq_ack = 0; | |
724 | inject = 1; | |
7837699f | 725 | } |
3cf57fed MT |
726 | spin_unlock(&ps->inject_lock); |
727 | if (inject) | |
728 | __inject_pit_timer_intr(kvm); | |
7837699f SY |
729 | } |
730 | } |