Commit | Line | Data |
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7837699f SY |
1 | /* |
2 | * 8253/8254 interval timer emulation | |
3 | * | |
4 | * Copyright (c) 2003-2004 Fabrice Bellard | |
5 | * Copyright (c) 2006 Intel Corporation | |
6 | * Copyright (c) 2007 Keir Fraser, XenSource Inc | |
7 | * Copyright (c) 2008 Intel Corporation | |
221d059d | 8 | * Copyright 2009 Red Hat, Inc. and/or its affilates. |
7837699f SY |
9 | * |
10 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
11 | * of this software and associated documentation files (the "Software"), to deal | |
12 | * in the Software without restriction, including without limitation the rights | |
13 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
14 | * copies of the Software, and to permit persons to whom the Software is | |
15 | * furnished to do so, subject to the following conditions: | |
16 | * | |
17 | * The above copyright notice and this permission notice shall be included in | |
18 | * all copies or substantial portions of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
21 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
22 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
23 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
24 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
25 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
26 | * THE SOFTWARE. | |
27 | * | |
28 | * Authors: | |
29 | * Sheng Yang <sheng.yang@intel.com> | |
30 | * Based on QEMU and Xen. | |
31 | */ | |
32 | ||
a78d9626 JP |
33 | #define pr_fmt(fmt) "pit: " fmt |
34 | ||
7837699f | 35 | #include <linux/kvm_host.h> |
5a0e3ad6 | 36 | #include <linux/slab.h> |
7837699f SY |
37 | |
38 | #include "irq.h" | |
39 | #include "i8254.h" | |
40 | ||
41 | #ifndef CONFIG_X86_64 | |
6f6d6a1a | 42 | #define mod_64(x, y) ((x) - (y) * div64_u64(x, y)) |
7837699f SY |
43 | #else |
44 | #define mod_64(x, y) ((x) % (y)) | |
45 | #endif | |
46 | ||
47 | #define RW_STATE_LSB 1 | |
48 | #define RW_STATE_MSB 2 | |
49 | #define RW_STATE_WORD0 3 | |
50 | #define RW_STATE_WORD1 4 | |
51 | ||
52 | /* Compute with 96 bit intermediate result: (a*b)/c */ | |
53 | static u64 muldiv64(u64 a, u32 b, u32 c) | |
54 | { | |
55 | union { | |
56 | u64 ll; | |
57 | struct { | |
58 | u32 low, high; | |
59 | } l; | |
60 | } u, res; | |
61 | u64 rl, rh; | |
62 | ||
63 | u.ll = a; | |
64 | rl = (u64)u.l.low * (u64)b; | |
65 | rh = (u64)u.l.high * (u64)b; | |
66 | rh += (rl >> 32); | |
6f6d6a1a RZ |
67 | res.l.high = div64_u64(rh, c); |
68 | res.l.low = div64_u64(((mod_64(rh, c) << 32) + (rl & 0xffffffff)), c); | |
7837699f SY |
69 | return res.ll; |
70 | } | |
71 | ||
72 | static void pit_set_gate(struct kvm *kvm, int channel, u32 val) | |
73 | { | |
74 | struct kvm_kpit_channel_state *c = | |
75 | &kvm->arch.vpit->pit_state.channels[channel]; | |
76 | ||
77 | WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock)); | |
78 | ||
79 | switch (c->mode) { | |
80 | default: | |
81 | case 0: | |
82 | case 4: | |
83 | /* XXX: just disable/enable counting */ | |
84 | break; | |
85 | case 1: | |
86 | case 2: | |
87 | case 3: | |
88 | case 5: | |
89 | /* Restart counting on rising edge. */ | |
90 | if (c->gate < val) | |
91 | c->count_load_time = ktime_get(); | |
92 | break; | |
93 | } | |
94 | ||
95 | c->gate = val; | |
96 | } | |
97 | ||
8b2cf73c | 98 | static int pit_get_gate(struct kvm *kvm, int channel) |
7837699f SY |
99 | { |
100 | WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock)); | |
101 | ||
102 | return kvm->arch.vpit->pit_state.channels[channel].gate; | |
103 | } | |
104 | ||
fd668423 MT |
105 | static s64 __kpit_elapsed(struct kvm *kvm) |
106 | { | |
107 | s64 elapsed; | |
108 | ktime_t remaining; | |
109 | struct kvm_kpit_state *ps = &kvm->arch.vpit->pit_state; | |
110 | ||
0ff77873 MT |
111 | if (!ps->pit_timer.period) |
112 | return 0; | |
113 | ||
ede2ccc5 MT |
114 | /* |
115 | * The Counter does not stop when it reaches zero. In | |
116 | * Modes 0, 1, 4, and 5 the Counter ``wraps around'' to | |
117 | * the highest count, either FFFF hex for binary counting | |
118 | * or 9999 for BCD counting, and continues counting. | |
119 | * Modes 2 and 3 are periodic; the Counter reloads | |
120 | * itself with the initial count and continues counting | |
121 | * from there. | |
122 | */ | |
ace15464 | 123 | remaining = hrtimer_get_remaining(&ps->pit_timer.timer); |
ede2ccc5 MT |
124 | elapsed = ps->pit_timer.period - ktime_to_ns(remaining); |
125 | elapsed = mod_64(elapsed, ps->pit_timer.period); | |
fd668423 MT |
126 | |
127 | return elapsed; | |
128 | } | |
129 | ||
130 | static s64 kpit_elapsed(struct kvm *kvm, struct kvm_kpit_channel_state *c, | |
131 | int channel) | |
132 | { | |
133 | if (channel == 0) | |
134 | return __kpit_elapsed(kvm); | |
135 | ||
136 | return ktime_to_ns(ktime_sub(ktime_get(), c->count_load_time)); | |
137 | } | |
138 | ||
7837699f SY |
139 | static int pit_get_count(struct kvm *kvm, int channel) |
140 | { | |
141 | struct kvm_kpit_channel_state *c = | |
142 | &kvm->arch.vpit->pit_state.channels[channel]; | |
143 | s64 d, t; | |
144 | int counter; | |
145 | ||
146 | WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock)); | |
147 | ||
fd668423 | 148 | t = kpit_elapsed(kvm, c, channel); |
7837699f SY |
149 | d = muldiv64(t, KVM_PIT_FREQ, NSEC_PER_SEC); |
150 | ||
151 | switch (c->mode) { | |
152 | case 0: | |
153 | case 1: | |
154 | case 4: | |
155 | case 5: | |
156 | counter = (c->count - d) & 0xffff; | |
157 | break; | |
158 | case 3: | |
159 | /* XXX: may be incorrect for odd counts */ | |
160 | counter = c->count - (mod_64((2 * d), c->count)); | |
161 | break; | |
162 | default: | |
163 | counter = c->count - mod_64(d, c->count); | |
164 | break; | |
165 | } | |
166 | return counter; | |
167 | } | |
168 | ||
169 | static int pit_get_out(struct kvm *kvm, int channel) | |
170 | { | |
171 | struct kvm_kpit_channel_state *c = | |
172 | &kvm->arch.vpit->pit_state.channels[channel]; | |
173 | s64 d, t; | |
174 | int out; | |
175 | ||
176 | WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock)); | |
177 | ||
fd668423 | 178 | t = kpit_elapsed(kvm, c, channel); |
7837699f SY |
179 | d = muldiv64(t, KVM_PIT_FREQ, NSEC_PER_SEC); |
180 | ||
181 | switch (c->mode) { | |
182 | default: | |
183 | case 0: | |
184 | out = (d >= c->count); | |
185 | break; | |
186 | case 1: | |
187 | out = (d < c->count); | |
188 | break; | |
189 | case 2: | |
190 | out = ((mod_64(d, c->count) == 0) && (d != 0)); | |
191 | break; | |
192 | case 3: | |
193 | out = (mod_64(d, c->count) < ((c->count + 1) >> 1)); | |
194 | break; | |
195 | case 4: | |
196 | case 5: | |
197 | out = (d == c->count); | |
198 | break; | |
199 | } | |
200 | ||
201 | return out; | |
202 | } | |
203 | ||
204 | static void pit_latch_count(struct kvm *kvm, int channel) | |
205 | { | |
206 | struct kvm_kpit_channel_state *c = | |
207 | &kvm->arch.vpit->pit_state.channels[channel]; | |
208 | ||
209 | WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock)); | |
210 | ||
211 | if (!c->count_latched) { | |
212 | c->latched_count = pit_get_count(kvm, channel); | |
213 | c->count_latched = c->rw_mode; | |
214 | } | |
215 | } | |
216 | ||
217 | static void pit_latch_status(struct kvm *kvm, int channel) | |
218 | { | |
219 | struct kvm_kpit_channel_state *c = | |
220 | &kvm->arch.vpit->pit_state.channels[channel]; | |
221 | ||
222 | WARN_ON(!mutex_is_locked(&kvm->arch.vpit->pit_state.lock)); | |
223 | ||
224 | if (!c->status_latched) { | |
225 | /* TODO: Return NULL COUNT (bit 6). */ | |
226 | c->status = ((pit_get_out(kvm, channel) << 7) | | |
227 | (c->rw_mode << 4) | | |
228 | (c->mode << 1) | | |
229 | c->bcd); | |
230 | c->status_latched = 1; | |
231 | } | |
232 | } | |
233 | ||
3d80840d MT |
234 | int pit_has_pending_timer(struct kvm_vcpu *vcpu) |
235 | { | |
236 | struct kvm_pit *pit = vcpu->kvm->arch.vpit; | |
237 | ||
c5af89b6 | 238 | if (pit && kvm_vcpu_is_bsp(vcpu) && pit->pit_state.irq_ack) |
3d80840d | 239 | return atomic_read(&pit->pit_state.pit_timer.pending); |
3d80840d MT |
240 | return 0; |
241 | } | |
242 | ||
ee032c99 | 243 | static void kvm_pit_ack_irq(struct kvm_irq_ack_notifier *kian) |
3cf57fed MT |
244 | { |
245 | struct kvm_kpit_state *ps = container_of(kian, struct kvm_kpit_state, | |
246 | irq_ack_notifier); | |
fa8273e9 | 247 | raw_spin_lock(&ps->inject_lock); |
3cf57fed | 248 | if (atomic_dec_return(&ps->pit_timer.pending) < 0) |
dc7404ce | 249 | atomic_inc(&ps->pit_timer.pending); |
3cf57fed | 250 | ps->irq_ack = 1; |
fa8273e9 | 251 | raw_spin_unlock(&ps->inject_lock); |
3cf57fed MT |
252 | } |
253 | ||
2f599714 MT |
254 | void __kvm_migrate_pit_timer(struct kvm_vcpu *vcpu) |
255 | { | |
256 | struct kvm_pit *pit = vcpu->kvm->arch.vpit; | |
257 | struct hrtimer *timer; | |
258 | ||
c5af89b6 | 259 | if (!kvm_vcpu_is_bsp(vcpu) || !pit) |
2f599714 MT |
260 | return; |
261 | ||
262 | timer = &pit->pit_state.pit_timer.timer; | |
263 | if (hrtimer_cancel(timer)) | |
beb20d52 | 264 | hrtimer_start_expires(timer, HRTIMER_MODE_ABS); |
2f599714 MT |
265 | } |
266 | ||
d3c7b77d | 267 | static void destroy_pit_timer(struct kvm_timer *pt) |
7837699f | 268 | { |
a78d9626 | 269 | pr_debug("execute del timer!\n"); |
7837699f SY |
270 | hrtimer_cancel(&pt->timer); |
271 | } | |
272 | ||
d3c7b77d MT |
273 | static bool kpit_is_periodic(struct kvm_timer *ktimer) |
274 | { | |
275 | struct kvm_kpit_state *ps = container_of(ktimer, struct kvm_kpit_state, | |
276 | pit_timer); | |
277 | return ps->is_periodic; | |
278 | } | |
279 | ||
386eb6e8 | 280 | static struct kvm_timer_ops kpit_ops = { |
d3c7b77d MT |
281 | .is_periodic = kpit_is_periodic, |
282 | }; | |
283 | ||
3cf57fed | 284 | static void create_pit_timer(struct kvm_kpit_state *ps, u32 val, int is_period) |
7837699f | 285 | { |
d3c7b77d | 286 | struct kvm_timer *pt = &ps->pit_timer; |
7837699f SY |
287 | s64 interval; |
288 | ||
289 | interval = muldiv64(val, NSEC_PER_SEC, KVM_PIT_FREQ); | |
290 | ||
a78d9626 | 291 | pr_debug("create pit timer, interval is %llu nsec\n", interval); |
7837699f SY |
292 | |
293 | /* TODO The new value only affected after the retriggered */ | |
294 | hrtimer_cancel(&pt->timer); | |
ede2ccc5 | 295 | pt->period = interval; |
d3c7b77d MT |
296 | ps->is_periodic = is_period; |
297 | ||
298 | pt->timer.function = kvm_timer_fn; | |
299 | pt->t_ops = &kpit_ops; | |
300 | pt->kvm = ps->pit->kvm; | |
1ed0ce00 | 301 | pt->vcpu = pt->kvm->bsp_vcpu; |
d3c7b77d | 302 | |
7837699f | 303 | atomic_set(&pt->pending, 0); |
3cf57fed | 304 | ps->irq_ack = 1; |
7837699f SY |
305 | |
306 | hrtimer_start(&pt->timer, ktime_add_ns(ktime_get(), interval), | |
307 | HRTIMER_MODE_ABS); | |
308 | } | |
309 | ||
310 | static void pit_load_count(struct kvm *kvm, int channel, u32 val) | |
311 | { | |
312 | struct kvm_kpit_state *ps = &kvm->arch.vpit->pit_state; | |
313 | ||
314 | WARN_ON(!mutex_is_locked(&ps->lock)); | |
315 | ||
a78d9626 | 316 | pr_debug("load_count val is %d, channel is %d\n", val, channel); |
7837699f SY |
317 | |
318 | /* | |
ede2ccc5 MT |
319 | * The largest possible initial count is 0; this is equivalent |
320 | * to 216 for binary counting and 104 for BCD counting. | |
7837699f SY |
321 | */ |
322 | if (val == 0) | |
323 | val = 0x10000; | |
324 | ||
7837699f SY |
325 | ps->channels[channel].count = val; |
326 | ||
fd668423 MT |
327 | if (channel != 0) { |
328 | ps->channels[channel].count_load_time = ktime_get(); | |
7837699f | 329 | return; |
fd668423 | 330 | } |
7837699f SY |
331 | |
332 | /* Two types of timer | |
333 | * mode 1 is one shot, mode 2 is period, otherwise del timer */ | |
334 | switch (ps->channels[0].mode) { | |
ede2ccc5 | 335 | case 0: |
7837699f | 336 | case 1: |
ece15bab MT |
337 | /* FIXME: enhance mode 4 precision */ |
338 | case 4: | |
e9f42757 BK |
339 | if (!(ps->flags & KVM_PIT_FLAGS_HPET_LEGACY)) { |
340 | create_pit_timer(ps, val, 0); | |
341 | } | |
7837699f SY |
342 | break; |
343 | case 2: | |
f6975545 | 344 | case 3: |
e9f42757 BK |
345 | if (!(ps->flags & KVM_PIT_FLAGS_HPET_LEGACY)){ |
346 | create_pit_timer(ps, val, 1); | |
347 | } | |
7837699f SY |
348 | break; |
349 | default: | |
350 | destroy_pit_timer(&ps->pit_timer); | |
351 | } | |
352 | } | |
353 | ||
e9f42757 | 354 | void kvm_pit_load_count(struct kvm *kvm, int channel, u32 val, int hpet_legacy_start) |
e0f63cb9 | 355 | { |
e9f42757 BK |
356 | u8 saved_mode; |
357 | if (hpet_legacy_start) { | |
358 | /* save existing mode for later reenablement */ | |
359 | saved_mode = kvm->arch.vpit->pit_state.channels[0].mode; | |
360 | kvm->arch.vpit->pit_state.channels[0].mode = 0xff; /* disable timer */ | |
361 | pit_load_count(kvm, channel, val); | |
362 | kvm->arch.vpit->pit_state.channels[0].mode = saved_mode; | |
363 | } else { | |
364 | pit_load_count(kvm, channel, val); | |
365 | } | |
e0f63cb9 SY |
366 | } |
367 | ||
d76685c4 GH |
368 | static inline struct kvm_pit *dev_to_pit(struct kvm_io_device *dev) |
369 | { | |
370 | return container_of(dev, struct kvm_pit, dev); | |
371 | } | |
372 | ||
373 | static inline struct kvm_pit *speaker_to_pit(struct kvm_io_device *dev) | |
374 | { | |
375 | return container_of(dev, struct kvm_pit, speaker_dev); | |
376 | } | |
377 | ||
bda9020e MT |
378 | static inline int pit_in_range(gpa_t addr) |
379 | { | |
380 | return ((addr >= KVM_PIT_BASE_ADDRESS) && | |
381 | (addr < KVM_PIT_BASE_ADDRESS + KVM_PIT_MEM_LENGTH)); | |
382 | } | |
383 | ||
384 | static int pit_ioport_write(struct kvm_io_device *this, | |
385 | gpa_t addr, int len, const void *data) | |
7837699f | 386 | { |
d76685c4 | 387 | struct kvm_pit *pit = dev_to_pit(this); |
7837699f SY |
388 | struct kvm_kpit_state *pit_state = &pit->pit_state; |
389 | struct kvm *kvm = pit->kvm; | |
390 | int channel, access; | |
391 | struct kvm_kpit_channel_state *s; | |
392 | u32 val = *(u32 *) data; | |
bda9020e MT |
393 | if (!pit_in_range(addr)) |
394 | return -EOPNOTSUPP; | |
7837699f SY |
395 | |
396 | val &= 0xff; | |
397 | addr &= KVM_PIT_CHANNEL_MASK; | |
398 | ||
399 | mutex_lock(&pit_state->lock); | |
400 | ||
401 | if (val != 0) | |
a78d9626 JP |
402 | pr_debug("write addr is 0x%x, len is %d, val is 0x%x\n", |
403 | (unsigned int)addr, len, val); | |
7837699f SY |
404 | |
405 | if (addr == 3) { | |
406 | channel = val >> 6; | |
407 | if (channel == 3) { | |
408 | /* Read-Back Command. */ | |
409 | for (channel = 0; channel < 3; channel++) { | |
410 | s = &pit_state->channels[channel]; | |
411 | if (val & (2 << channel)) { | |
412 | if (!(val & 0x20)) | |
413 | pit_latch_count(kvm, channel); | |
414 | if (!(val & 0x10)) | |
415 | pit_latch_status(kvm, channel); | |
416 | } | |
417 | } | |
418 | } else { | |
419 | /* Select Counter <channel>. */ | |
420 | s = &pit_state->channels[channel]; | |
421 | access = (val >> 4) & KVM_PIT_CHANNEL_MASK; | |
422 | if (access == 0) { | |
423 | pit_latch_count(kvm, channel); | |
424 | } else { | |
425 | s->rw_mode = access; | |
426 | s->read_state = access; | |
427 | s->write_state = access; | |
428 | s->mode = (val >> 1) & 7; | |
429 | if (s->mode > 5) | |
430 | s->mode -= 4; | |
431 | s->bcd = val & 1; | |
432 | } | |
433 | } | |
434 | } else { | |
435 | /* Write Count. */ | |
436 | s = &pit_state->channels[addr]; | |
437 | switch (s->write_state) { | |
438 | default: | |
439 | case RW_STATE_LSB: | |
440 | pit_load_count(kvm, addr, val); | |
441 | break; | |
442 | case RW_STATE_MSB: | |
443 | pit_load_count(kvm, addr, val << 8); | |
444 | break; | |
445 | case RW_STATE_WORD0: | |
446 | s->write_latch = val; | |
447 | s->write_state = RW_STATE_WORD1; | |
448 | break; | |
449 | case RW_STATE_WORD1: | |
450 | pit_load_count(kvm, addr, s->write_latch | (val << 8)); | |
451 | s->write_state = RW_STATE_WORD0; | |
452 | break; | |
453 | } | |
454 | } | |
455 | ||
456 | mutex_unlock(&pit_state->lock); | |
bda9020e | 457 | return 0; |
7837699f SY |
458 | } |
459 | ||
bda9020e MT |
460 | static int pit_ioport_read(struct kvm_io_device *this, |
461 | gpa_t addr, int len, void *data) | |
7837699f | 462 | { |
d76685c4 | 463 | struct kvm_pit *pit = dev_to_pit(this); |
7837699f SY |
464 | struct kvm_kpit_state *pit_state = &pit->pit_state; |
465 | struct kvm *kvm = pit->kvm; | |
466 | int ret, count; | |
467 | struct kvm_kpit_channel_state *s; | |
bda9020e MT |
468 | if (!pit_in_range(addr)) |
469 | return -EOPNOTSUPP; | |
7837699f SY |
470 | |
471 | addr &= KVM_PIT_CHANNEL_MASK; | |
ee73f656 MT |
472 | if (addr == 3) |
473 | return 0; | |
474 | ||
7837699f SY |
475 | s = &pit_state->channels[addr]; |
476 | ||
477 | mutex_lock(&pit_state->lock); | |
478 | ||
479 | if (s->status_latched) { | |
480 | s->status_latched = 0; | |
481 | ret = s->status; | |
482 | } else if (s->count_latched) { | |
483 | switch (s->count_latched) { | |
484 | default: | |
485 | case RW_STATE_LSB: | |
486 | ret = s->latched_count & 0xff; | |
487 | s->count_latched = 0; | |
488 | break; | |
489 | case RW_STATE_MSB: | |
490 | ret = s->latched_count >> 8; | |
491 | s->count_latched = 0; | |
492 | break; | |
493 | case RW_STATE_WORD0: | |
494 | ret = s->latched_count & 0xff; | |
495 | s->count_latched = RW_STATE_MSB; | |
496 | break; | |
497 | } | |
498 | } else { | |
499 | switch (s->read_state) { | |
500 | default: | |
501 | case RW_STATE_LSB: | |
502 | count = pit_get_count(kvm, addr); | |
503 | ret = count & 0xff; | |
504 | break; | |
505 | case RW_STATE_MSB: | |
506 | count = pit_get_count(kvm, addr); | |
507 | ret = (count >> 8) & 0xff; | |
508 | break; | |
509 | case RW_STATE_WORD0: | |
510 | count = pit_get_count(kvm, addr); | |
511 | ret = count & 0xff; | |
512 | s->read_state = RW_STATE_WORD1; | |
513 | break; | |
514 | case RW_STATE_WORD1: | |
515 | count = pit_get_count(kvm, addr); | |
516 | ret = (count >> 8) & 0xff; | |
517 | s->read_state = RW_STATE_WORD0; | |
518 | break; | |
519 | } | |
520 | } | |
521 | ||
522 | if (len > sizeof(ret)) | |
523 | len = sizeof(ret); | |
524 | memcpy(data, (char *)&ret, len); | |
525 | ||
526 | mutex_unlock(&pit_state->lock); | |
bda9020e | 527 | return 0; |
7837699f SY |
528 | } |
529 | ||
bda9020e MT |
530 | static int speaker_ioport_write(struct kvm_io_device *this, |
531 | gpa_t addr, int len, const void *data) | |
7837699f | 532 | { |
d76685c4 | 533 | struct kvm_pit *pit = speaker_to_pit(this); |
7837699f SY |
534 | struct kvm_kpit_state *pit_state = &pit->pit_state; |
535 | struct kvm *kvm = pit->kvm; | |
536 | u32 val = *(u32 *) data; | |
bda9020e MT |
537 | if (addr != KVM_SPEAKER_BASE_ADDRESS) |
538 | return -EOPNOTSUPP; | |
7837699f SY |
539 | |
540 | mutex_lock(&pit_state->lock); | |
541 | pit_state->speaker_data_on = (val >> 1) & 1; | |
542 | pit_set_gate(kvm, 2, val & 1); | |
543 | mutex_unlock(&pit_state->lock); | |
bda9020e | 544 | return 0; |
7837699f SY |
545 | } |
546 | ||
bda9020e MT |
547 | static int speaker_ioport_read(struct kvm_io_device *this, |
548 | gpa_t addr, int len, void *data) | |
7837699f | 549 | { |
d76685c4 | 550 | struct kvm_pit *pit = speaker_to_pit(this); |
7837699f SY |
551 | struct kvm_kpit_state *pit_state = &pit->pit_state; |
552 | struct kvm *kvm = pit->kvm; | |
553 | unsigned int refresh_clock; | |
554 | int ret; | |
bda9020e MT |
555 | if (addr != KVM_SPEAKER_BASE_ADDRESS) |
556 | return -EOPNOTSUPP; | |
7837699f SY |
557 | |
558 | /* Refresh clock toggles at about 15us. We approximate as 2^14ns. */ | |
559 | refresh_clock = ((unsigned int)ktime_to_ns(ktime_get()) >> 14) & 1; | |
560 | ||
561 | mutex_lock(&pit_state->lock); | |
562 | ret = ((pit_state->speaker_data_on << 1) | pit_get_gate(kvm, 2) | | |
563 | (pit_get_out(kvm, 2) << 5) | (refresh_clock << 4)); | |
564 | if (len > sizeof(ret)) | |
565 | len = sizeof(ret); | |
566 | memcpy(data, (char *)&ret, len); | |
567 | mutex_unlock(&pit_state->lock); | |
bda9020e | 568 | return 0; |
7837699f SY |
569 | } |
570 | ||
308b0f23 | 571 | void kvm_pit_reset(struct kvm_pit *pit) |
7837699f SY |
572 | { |
573 | int i; | |
308b0f23 SY |
574 | struct kvm_kpit_channel_state *c; |
575 | ||
576 | mutex_lock(&pit->pit_state.lock); | |
e9f42757 | 577 | pit->pit_state.flags = 0; |
308b0f23 SY |
578 | for (i = 0; i < 3; i++) { |
579 | c = &pit->pit_state.channels[i]; | |
580 | c->mode = 0xff; | |
581 | c->gate = (i != 2); | |
582 | pit_load_count(pit->kvm, i, 0); | |
583 | } | |
584 | mutex_unlock(&pit->pit_state.lock); | |
585 | ||
586 | atomic_set(&pit->pit_state.pit_timer.pending, 0); | |
3cf57fed | 587 | pit->pit_state.irq_ack = 1; |
308b0f23 SY |
588 | } |
589 | ||
4780c659 AK |
590 | static void pit_mask_notifer(struct kvm_irq_mask_notifier *kimn, bool mask) |
591 | { | |
592 | struct kvm_pit *pit = container_of(kimn, struct kvm_pit, mask_notifier); | |
593 | ||
594 | if (!mask) { | |
595 | atomic_set(&pit->pit_state.pit_timer.pending, 0); | |
596 | pit->pit_state.irq_ack = 1; | |
597 | } | |
598 | } | |
599 | ||
d76685c4 GH |
600 | static const struct kvm_io_device_ops pit_dev_ops = { |
601 | .read = pit_ioport_read, | |
602 | .write = pit_ioport_write, | |
d76685c4 GH |
603 | }; |
604 | ||
605 | static const struct kvm_io_device_ops speaker_dev_ops = { | |
606 | .read = speaker_ioport_read, | |
607 | .write = speaker_ioport_write, | |
d76685c4 GH |
608 | }; |
609 | ||
79fac95e | 610 | /* Caller must hold slots_lock */ |
c5ff41ce | 611 | struct kvm_pit *kvm_create_pit(struct kvm *kvm, u32 flags) |
308b0f23 | 612 | { |
7837699f SY |
613 | struct kvm_pit *pit; |
614 | struct kvm_kpit_state *pit_state; | |
090b7aff | 615 | int ret; |
7837699f SY |
616 | |
617 | pit = kzalloc(sizeof(struct kvm_pit), GFP_KERNEL); | |
618 | if (!pit) | |
619 | return NULL; | |
620 | ||
5550af4d | 621 | pit->irq_source_id = kvm_request_irq_source_id(kvm); |
e17d1dc0 AK |
622 | if (pit->irq_source_id < 0) { |
623 | kfree(pit); | |
5550af4d | 624 | return NULL; |
e17d1dc0 | 625 | } |
5550af4d | 626 | |
7837699f SY |
627 | mutex_init(&pit->pit_state.lock); |
628 | mutex_lock(&pit->pit_state.lock); | |
fa8273e9 | 629 | raw_spin_lock_init(&pit->pit_state.inject_lock); |
7837699f | 630 | |
7837699f SY |
631 | kvm->arch.vpit = pit; |
632 | pit->kvm = kvm; | |
633 | ||
634 | pit_state = &pit->pit_state; | |
635 | pit_state->pit = pit; | |
636 | hrtimer_init(&pit_state->pit_timer.timer, | |
637 | CLOCK_MONOTONIC, HRTIMER_MODE_ABS); | |
3cf57fed MT |
638 | pit_state->irq_ack_notifier.gsi = 0; |
639 | pit_state->irq_ack_notifier.irq_acked = kvm_pit_ack_irq; | |
640 | kvm_register_irq_ack_notifier(kvm, &pit_state->irq_ack_notifier); | |
52d939a0 | 641 | pit_state->pit_timer.reinject = true; |
7837699f SY |
642 | mutex_unlock(&pit->pit_state.lock); |
643 | ||
308b0f23 | 644 | kvm_pit_reset(pit); |
7837699f | 645 | |
4780c659 AK |
646 | pit->mask_notifier.func = pit_mask_notifer; |
647 | kvm_register_irq_mask_notifier(kvm, 0, &pit->mask_notifier); | |
648 | ||
6b66ac1a | 649 | kvm_iodevice_init(&pit->dev, &pit_dev_ops); |
e93f8a0f | 650 | ret = kvm_io_bus_register_dev(kvm, KVM_PIO_BUS, &pit->dev); |
090b7aff GH |
651 | if (ret < 0) |
652 | goto fail; | |
6b66ac1a GH |
653 | |
654 | if (flags & KVM_PIT_SPEAKER_DUMMY) { | |
655 | kvm_iodevice_init(&pit->speaker_dev, &speaker_dev_ops); | |
e93f8a0f | 656 | ret = kvm_io_bus_register_dev(kvm, KVM_PIO_BUS, |
090b7aff GH |
657 | &pit->speaker_dev); |
658 | if (ret < 0) | |
659 | goto fail_unregister; | |
6b66ac1a GH |
660 | } |
661 | ||
7837699f | 662 | return pit; |
090b7aff GH |
663 | |
664 | fail_unregister: | |
e93f8a0f | 665 | kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, &pit->dev); |
090b7aff GH |
666 | |
667 | fail: | |
d225f53b WY |
668 | kvm_unregister_irq_mask_notifier(kvm, 0, &pit->mask_notifier); |
669 | kvm_unregister_irq_ack_notifier(kvm, &pit_state->irq_ack_notifier); | |
670 | kvm_free_irq_source_id(kvm, pit->irq_source_id); | |
090b7aff GH |
671 | |
672 | kfree(pit); | |
673 | return NULL; | |
7837699f SY |
674 | } |
675 | ||
676 | void kvm_free_pit(struct kvm *kvm) | |
677 | { | |
678 | struct hrtimer *timer; | |
679 | ||
680 | if (kvm->arch.vpit) { | |
4780c659 AK |
681 | kvm_unregister_irq_mask_notifier(kvm, 0, |
682 | &kvm->arch.vpit->mask_notifier); | |
84fde248 GN |
683 | kvm_unregister_irq_ack_notifier(kvm, |
684 | &kvm->arch.vpit->pit_state.irq_ack_notifier); | |
7837699f SY |
685 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
686 | timer = &kvm->arch.vpit->pit_state.pit_timer.timer; | |
687 | hrtimer_cancel(timer); | |
5550af4d | 688 | kvm_free_irq_source_id(kvm, kvm->arch.vpit->irq_source_id); |
7837699f SY |
689 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); |
690 | kfree(kvm->arch.vpit); | |
691 | } | |
692 | } | |
693 | ||
8b2cf73c | 694 | static void __inject_pit_timer_intr(struct kvm *kvm) |
7837699f | 695 | { |
23930f95 JK |
696 | struct kvm_vcpu *vcpu; |
697 | int i; | |
698 | ||
5550af4d SY |
699 | kvm_set_irq(kvm, kvm->arch.vpit->irq_source_id, 0, 1); |
700 | kvm_set_irq(kvm, kvm->arch.vpit->irq_source_id, 0, 0); | |
23930f95 JK |
701 | |
702 | /* | |
8fdb2351 JK |
703 | * Provides NMI watchdog support via Virtual Wire mode. |
704 | * The route is: PIT -> PIC -> LVT0 in NMI mode. | |
705 | * | |
706 | * Note: Our Virtual Wire implementation is simplified, only | |
707 | * propagating PIT interrupts to all VCPUs when they have set | |
708 | * LVT0 to NMI delivery. Other PIC interrupts are just sent to | |
709 | * VCPU0, and only if its LVT0 is in EXTINT mode. | |
23930f95 | 710 | */ |
cc6e462c | 711 | if (kvm->arch.vapics_in_nmi_mode > 0) |
988a2cae GN |
712 | kvm_for_each_vcpu(i, vcpu, kvm) |
713 | kvm_apic_nmi_wd_deliver(vcpu); | |
7837699f SY |
714 | } |
715 | ||
716 | void kvm_inject_pit_timer_irqs(struct kvm_vcpu *vcpu) | |
717 | { | |
718 | struct kvm_pit *pit = vcpu->kvm->arch.vpit; | |
719 | struct kvm *kvm = vcpu->kvm; | |
720 | struct kvm_kpit_state *ps; | |
721 | ||
95fb4eb6 | 722 | if (pit) { |
3cf57fed | 723 | int inject = 0; |
7837699f SY |
724 | ps = &pit->pit_state; |
725 | ||
3cf57fed MT |
726 | /* Try to inject pending interrupts when |
727 | * last one has been acked. | |
728 | */ | |
fa8273e9 | 729 | raw_spin_lock(&ps->inject_lock); |
3cf57fed MT |
730 | if (atomic_read(&ps->pit_timer.pending) && ps->irq_ack) { |
731 | ps->irq_ack = 0; | |
732 | inject = 1; | |
7837699f | 733 | } |
fa8273e9 | 734 | raw_spin_unlock(&ps->inject_lock); |
3cf57fed MT |
735 | if (inject) |
736 | __inject_pit_timer_intr(kvm); | |
7837699f SY |
737 | } |
738 | } |