Commit | Line | Data |
---|---|---|
85f455f7 ED |
1 | /* |
2 | * irq.h: in kernel interrupt controller related definitions | |
3 | * Copyright (c) 2007, Intel Corporation. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., 59 Temple | |
16 | * Place - Suite 330, Boston, MA 02111-1307 USA. | |
17 | * Authors: | |
18 | * Yaozu (Eddie) Dong <Eddie.dong@intel.com> | |
19 | * | |
20 | */ | |
21 | ||
22 | #ifndef __IRQ_H | |
23 | #define __IRQ_H | |
24 | ||
e01a1b57 HB |
25 | #include <linux/mm_types.h> |
26 | #include <linux/hrtimer.h> | |
edf88417 | 27 | #include <linux/kvm_host.h> |
e2174021 | 28 | #include "iodev.h" |
85f455f7 | 29 | |
e01a1b57 HB |
30 | struct kvm; |
31 | struct kvm_vcpu; | |
32 | ||
85f455f7 ED |
33 | typedef void irq_request_func(void *opaque, int level); |
34 | ||
85f455f7 ED |
35 | struct kvm_kpic_state { |
36 | u8 last_irr; /* edge detection */ | |
37 | u8 irr; /* interrupt request register */ | |
38 | u8 imr; /* interrupt mask register */ | |
39 | u8 isr; /* interrupt service register */ | |
40 | u8 priority_add; /* highest irq priority */ | |
41 | u8 irq_base; | |
42 | u8 read_reg_select; | |
43 | u8 poll; | |
44 | u8 special_mask; | |
45 | u8 init_state; | |
46 | u8 auto_eoi; | |
47 | u8 rotate_on_auto_eoi; | |
48 | u8 special_fully_nested_mode; | |
49 | u8 init4; /* true if 4 byte init */ | |
50 | u8 elcr; /* PIIX edge/trigger selection */ | |
51 | u8 elcr_mask; | |
52 | struct kvm_pic *pics_state; | |
53 | }; | |
54 | ||
55 | struct kvm_pic { | |
56 | struct kvm_kpic_state pics[2]; /* 0 is master pic, 1 is slave pic */ | |
57 | irq_request_func *irq_request; | |
58 | void *irq_request_opaque; | |
59 | int output; /* intr from master PIC */ | |
60 | struct kvm_io_device dev; | |
61 | }; | |
62 | ||
63 | struct kvm_pic *kvm_create_pic(struct kvm *kvm); | |
64 | void kvm_pic_set_irq(void *opaque, int irq, int level); | |
65 | int kvm_pic_read_irq(struct kvm_pic *s); | |
6ceb9d79 | 66 | void kvm_pic_update_irq(struct kvm_pic *s); |
85f455f7 | 67 | |
6bf9e962 | 68 | #define IOAPIC_NUM_PINS KVM_IOAPIC_NUM_PINS |
1fd4f2a5 ED |
69 | #define IOAPIC_VERSION_ID 0x11 /* IOAPIC version */ |
70 | #define IOAPIC_EDGE_TRIG 0 | |
71 | #define IOAPIC_LEVEL_TRIG 1 | |
72 | ||
73 | #define IOAPIC_DEFAULT_BASE_ADDRESS 0xfec00000 | |
74 | #define IOAPIC_MEM_LENGTH 0x100 | |
75 | ||
76 | /* Direct registers. */ | |
77 | #define IOAPIC_REG_SELECT 0x00 | |
78 | #define IOAPIC_REG_WINDOW 0x10 | |
79 | #define IOAPIC_REG_EOI 0x40 /* IA64 IOSAPIC only */ | |
80 | ||
81 | /* Indirect registers. */ | |
82 | #define IOAPIC_REG_APIC_ID 0x00 /* x86 IOAPIC only */ | |
83 | #define IOAPIC_REG_VERSION 0x01 | |
84 | #define IOAPIC_REG_ARB_ID 0x02 /* x86 IOAPIC only */ | |
85 | ||
0c7ac28d ZX |
86 | /*ioapic delivery mode*/ |
87 | #define IOAPIC_FIXED 0x0 | |
88 | #define IOAPIC_LOWEST_PRIORITY 0x1 | |
89 | #define IOAPIC_PMI 0x2 | |
90 | #define IOAPIC_NMI 0x4 | |
91 | #define IOAPIC_INIT 0x5 | |
92 | #define IOAPIC_EXTINT 0x7 | |
93 | ||
1fd4f2a5 ED |
94 | struct kvm_ioapic { |
95 | u64 base_address; | |
96 | u32 ioregsel; | |
97 | u32 id; | |
98 | u32 irr; | |
99 | u32 pad; | |
100 | union ioapic_redir_entry { | |
101 | u64 bits; | |
102 | struct { | |
103 | u8 vector; | |
104 | u8 delivery_mode:3; | |
105 | u8 dest_mode:1; | |
106 | u8 delivery_status:1; | |
107 | u8 polarity:1; | |
108 | u8 remote_irr:1; | |
109 | u8 trig_mode:1; | |
110 | u8 mask:1; | |
111 | u8 reserve:7; | |
112 | u8 reserved[4]; | |
113 | u8 dest_id; | |
114 | } fields; | |
115 | } redirtbl[IOAPIC_NUM_PINS]; | |
116 | struct kvm_io_device dev; | |
117 | struct kvm *kvm; | |
118 | }; | |
119 | ||
97222cc8 ED |
120 | struct kvm_lapic { |
121 | unsigned long base_address; | |
122 | struct kvm_io_device dev; | |
123 | struct { | |
124 | atomic_t pending; | |
125 | s64 period; /* unit: ns */ | |
126 | u32 divide_count; | |
127 | ktime_t last_update; | |
128 | struct hrtimer dev; | |
129 | } timer; | |
130 | struct kvm_vcpu *vcpu; | |
131 | struct page *regs_page; | |
132 | void *regs; | |
133 | }; | |
134 | ||
135 | #ifdef DEBUG | |
136 | #define ASSERT(x) \ | |
137 | do { \ | |
138 | if (!(x)) { \ | |
139 | printk(KERN_EMERG "assertion failed %s: %d: %s\n", \ | |
140 | __FILE__, __LINE__, #x); \ | |
141 | BUG(); \ | |
142 | } \ | |
143 | } while (0) | |
144 | #else | |
145 | #define ASSERT(x) do { } while (0) | |
146 | #endif | |
147 | ||
682c59a3 ZX |
148 | static inline struct kvm_pic *pic_irqchip(struct kvm *kvm) |
149 | { | |
d7deeeb0 | 150 | return kvm->arch.vpic; |
682c59a3 ZX |
151 | } |
152 | ||
153 | static inline struct kvm_ioapic *ioapic_irqchip(struct kvm *kvm) | |
154 | { | |
d7deeeb0 | 155 | return kvm->arch.vioapic; |
682c59a3 ZX |
156 | } |
157 | ||
158 | static inline int irqchip_in_kernel(struct kvm *kvm) | |
159 | { | |
160 | return pic_irqchip(kvm) != NULL; | |
161 | } | |
162 | ||
97222cc8 ED |
163 | void kvm_vcpu_kick(struct kvm_vcpu *vcpu); |
164 | int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu); | |
40487c68 | 165 | int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu); |
97222cc8 ED |
166 | int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu); |
167 | int kvm_create_lapic(struct kvm_vcpu *vcpu); | |
c5ec1534 | 168 | void kvm_lapic_reset(struct kvm_vcpu *vcpu); |
2fcceae1 | 169 | void kvm_pic_reset(struct kvm_kpic_state *s); |
8c392696 | 170 | void kvm_ioapic_reset(struct kvm_ioapic *ioapic); |
d589444e | 171 | void kvm_free_lapic(struct kvm_vcpu *vcpu); |
97222cc8 ED |
172 | u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu); |
173 | void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8); | |
174 | void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value); | |
8be5453f ZX |
175 | |
176 | struct kvm_vcpu *kvm_get_lowest_prio_vcpu(struct kvm *kvm, u8 vector, | |
1fd4f2a5 | 177 | unsigned long bitmap); |
97222cc8 ED |
178 | u64 kvm_get_apic_base(struct kvm_vcpu *vcpu); |
179 | void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data); | |
1fd4f2a5 | 180 | int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest); |
97222cc8 | 181 | void kvm_ioapic_update_eoi(struct kvm *kvm, int vector); |
1fd4f2a5 | 182 | int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda); |
8be5453f | 183 | int kvm_apic_set_irq(struct kvm_vcpu *vcpu, u8 vec, u8 trig); |
96ad2cc6 | 184 | void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu); |
1fd4f2a5 ED |
185 | int kvm_ioapic_init(struct kvm *kvm); |
186 | void kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int level); | |
6e5d865c YS |
187 | int kvm_lapic_enabled(struct kvm_vcpu *vcpu); |
188 | int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu); | |
1b9778da ED |
189 | void kvm_apic_timer_intr_post(struct kvm_vcpu *vcpu, int vec); |
190 | void kvm_timer_intr_post(struct kvm_vcpu *vcpu, int vec); | |
191 | void kvm_inject_pending_timer_irqs(struct kvm_vcpu *vcpu); | |
192 | void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu); | |
a3d7f85f | 193 | void kvm_migrate_apic_timer(struct kvm_vcpu *vcpu); |
97222cc8 | 194 | |
85f455f7 | 195 | #endif |