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Merge tag 'md/4.1' of git://neil.brown.name/md
[deliverable/linux.git] / arch / x86 / kvm / lapic.c
CommitLineData
97222cc8
ED		 1
2/*
3 * Local APIC virtualization
4 *
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
9611c187 8 * Copyright 2009 Red Hat, Inc. and/or its affiliates.
97222cc8
ED		 9 *
10 * Authors:
11 * Dor Laor <dor.laor@qumranet.com>
12 * Gregory Haskins <ghaskins@novell.com>
13 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
14 *
15 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 */
20
edf88417 21#include <linux/kvm_host.h>
97222cc8
ED		 22#include <linux/kvm.h>
23#include <linux/mm.h>
24#include <linux/highmem.h>
25#include <linux/smp.h>
26#include <linux/hrtimer.h>
27#include <linux/io.h>
28#include <linux/module.h>
6f6d6a1a 29#include <linux/math64.h>
5a0e3ad6 30#include <linux/slab.h>
97222cc8
ED		 31#include <asm/processor.h>
32#include <asm/msr.h>
33#include <asm/page.h>
34#include <asm/current.h>
35#include <asm/apicdef.h>
d0659d94 36#include <asm/delay.h>
60063497 37#include <linux/atomic.h>
c5cc421b 38#include <linux/jump_label.h>
5fdbf976 39#include "kvm_cache_regs.h"
97222cc8 40#include "irq.h"
229456fc 41#include "trace.h"
fc61b800 42#include "x86.h"
00b27a3e 43#include "cpuid.h"
97222cc8 44
b682b814
MT		 45#ifndef CONFIG_X86_64
46#define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
47#else
48#define mod_64(x, y) ((x) % (y))
49#endif
50
97222cc8
ED		 51#define PRId64 "d"
52#define PRIx64 "llx"
53#define PRIu64 "u"
54#define PRIo64 "o"
55
56#define APIC_BUS_CYCLE_NS 1
57
58/* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
59#define apic_debug(fmt, arg...)
60
61#define APIC_LVT_NUM 6
62/* 14 is the version for Xeon and Pentium 8.4.8*/
63#define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16))
64#define LAPIC_MMIO_LENGTH (1 << 12)
65/* followed define is not in apicdef.h */
66#define APIC_SHORT_MASK 0xc0000
67#define APIC_DEST_NOSHORT 0x0
68#define APIC_DEST_MASK 0x800
69#define MAX_APIC_VECTOR 256
ecba9a52 70#define APIC_VECTORS_PER_REG 32
97222cc8 71
394457a9
NA		 72#define APIC_BROADCAST 0xFF
73#define X2APIC_BROADCAST 0xFFFFFFFFul
74
97222cc8
ED		 75#define VEC_POS(v) ((v) & (32 - 1))
76#define REG_POS(v) (((v) >> 5) << 4)
ad312c7c 77
97222cc8
ED		 78static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
79{
80 *((u32 *) (apic->regs + reg_off)) = val;
81}
82
a0c9a822
MT		 83static inline int apic_test_vector(int vec, void *bitmap)
84{
85 return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
86}
87
10606919
YZ		 88bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector)
89{
90 struct kvm_lapic *apic = vcpu->arch.apic;
91
92 return apic_test_vector(vector, apic->regs + APIC_ISR) ||
93 apic_test_vector(vector, apic->regs + APIC_IRR);
94}
95
97222cc8
ED		 96static inline void apic_set_vector(int vec, void *bitmap)
97{
98 set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
99}
100
101static inline void apic_clear_vector(int vec, void *bitmap)
102{
103 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
104}
105
8680b94b
MT		 106static inline int __apic_test_and_set_vector(int vec, void *bitmap)
107{
108 return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
109}
110
111static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
112{
113 return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
114}
115
c5cc421b 116struct static_key_deferred apic_hw_disabled __read_mostly;
f8c1ea10
GN		 117struct static_key_deferred apic_sw_disabled __read_mostly;
118
97222cc8
ED		 119static inline int apic_enabled(struct kvm_lapic *apic)
120{
c48f1496 121 return kvm_apic_sw_enabled(apic) && kvm_apic_hw_enabled(apic);
54e9818f
GN		 122}
123
97222cc8
ED		 124#define LVT_MASK \
125 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
126
127#define LINT_MASK \
128 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
129 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
130
131static inline int kvm_apic_id(struct kvm_lapic *apic)
132{
c48f1496 133 return (kvm_apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
97222cc8
ED		 134}
135
3548a259
RK		 136/* The logical map is definitely wrong if we have multiple
137 * modes at the same time. (Physical map is always right.)
138 */
139static inline bool kvm_apic_logical_map_valid(struct kvm_apic_map *map)
140{
141 return !(map->mode & (map->mode - 1));
142}
143
3b5a5ffa
RK		 144static inline void
145apic_logical_id(struct kvm_apic_map *map, u32 dest_id, u16 *cid, u16 *lid)
146{
147 unsigned lid_bits;
148
149 BUILD_BUG_ON(KVM_APIC_MODE_XAPIC_CLUSTER != 4);
150 BUILD_BUG_ON(KVM_APIC_MODE_XAPIC_FLAT != 8);
151 BUILD_BUG_ON(KVM_APIC_MODE_X2APIC != 16);
152 lid_bits = map->mode;
153
154 *cid = dest_id >> lid_bits;
155 *lid = dest_id & ((1 << lid_bits) - 1);
156}
157
1e08ec4a
GN		 158static void recalculate_apic_map(struct kvm *kvm)
159{
160 struct kvm_apic_map *new, *old = NULL;
161 struct kvm_vcpu *vcpu;
162 int i;
163
164 new = kzalloc(sizeof(struct kvm_apic_map), GFP_KERNEL);
165
166 mutex_lock(&kvm->arch.apic_map_lock);
167
168 if (!new)
169 goto out;
170
173beedc
NA		 171 kvm_for_each_vcpu(i, vcpu, kvm) {
172 struct kvm_lapic *apic = vcpu->arch.apic;
173 u16 cid, lid;
25995e5b 174 u32 ldr, aid;
1e08ec4a 175
df04d1d1
RK		 176 if (!kvm_apic_present(vcpu))
177 continue;
178
25995e5b 179 aid = kvm_apic_id(apic);
1e08ec4a 180 ldr = kvm_apic_get_reg(apic, APIC_LDR);
1e08ec4a 181
25995e5b
RK		 182 if (aid < ARRAY_SIZE(new->phys_map))
183 new->phys_map[aid] = apic;
3548a259 184
3b5a5ffa
RK		 185 if (apic_x2apic_mode(apic)) {
186 new->mode |= KVM_APIC_MODE_X2APIC;
187 } else if (ldr) {
188 ldr = GET_APIC_LOGICAL_ID(ldr);
189 if (kvm_apic_get_reg(apic, APIC_DFR) == APIC_DFR_FLAT)
190 new->mode |= KVM_APIC_MODE_XAPIC_FLAT;
191 else
192 new->mode |= KVM_APIC_MODE_XAPIC_CLUSTER;
193 }
194
195 if (!kvm_apic_logical_map_valid(new))
3548a259
RK		 196 continue;
197
3b5a5ffa
RK		 198 apic_logical_id(new, ldr, &cid, &lid);
199
25995e5b 200 if (lid && cid < ARRAY_SIZE(new->logical_map))
1e08ec4a
GN		 201 new->logical_map[cid][ffs(lid) - 1] = apic;
202 }
203out:
204 old = rcu_dereference_protected(kvm->arch.apic_map,
205 lockdep_is_held(&kvm->arch.apic_map_lock));
206 rcu_assign_pointer(kvm->arch.apic_map, new);
207 mutex_unlock(&kvm->arch.apic_map_lock);
208
209 if (old)
210 kfree_rcu(old, rcu);
c7c9c56c 211
3d81bc7e 212 kvm_vcpu_request_scan_ioapic(kvm);
1e08ec4a
GN		 213}
214
1e1b6c26
NA		 215static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
216{
e462755c 217 bool enabled = val & APIC_SPIV_APIC_ENABLED;
1e1b6c26
NA		 218
219 apic_set_reg(apic, APIC_SPIV, val);
e462755c
RK		 220
221 if (enabled != apic->sw_enabled) {
222 apic->sw_enabled = enabled;
223 if (enabled) {
1e1b6c26
NA		 224 static_key_slow_dec_deferred(&apic_sw_disabled);
225 recalculate_apic_map(apic->vcpu->kvm);
226 } else
227 static_key_slow_inc(&apic_sw_disabled.key);
228 }
229}
230
1e08ec4a
GN		 231static inline void kvm_apic_set_id(struct kvm_lapic *apic, u8 id)
232{
233 apic_set_reg(apic, APIC_ID, id << 24);
234 recalculate_apic_map(apic->vcpu->kvm);
235}
236
237static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
238{
239 apic_set_reg(apic, APIC_LDR, id);
240 recalculate_apic_map(apic->vcpu->kvm);
241}
242
97222cc8
ED		 243static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
244{
c48f1496 245 return !(kvm_apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
97222cc8
ED		 246}
247
248static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
249{
c48f1496 250 return kvm_apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
97222cc8
ED		 251}
252
a3e06bbe
LJ		 253static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
254{
f30ebc31 255 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT;
a3e06bbe
LJ		 256}
257
97222cc8
ED		 258static inline int apic_lvtt_period(struct kvm_lapic *apic)
259{
f30ebc31 260 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC;
a3e06bbe
LJ		 261}
262
263static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
264{
f30ebc31 265 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE;
97222cc8
ED		 266}
267
cc6e462c
JK		 268static inline int apic_lvt_nmi_mode(u32 lvt_val)
269{
270 return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
271}
272
fc61b800
GN		 273void kvm_apic_set_version(struct kvm_vcpu *vcpu)
274{
275 struct kvm_lapic *apic = vcpu->arch.apic;
276 struct kvm_cpuid_entry2 *feat;
277 u32 v = APIC_VERSION;
278
c48f1496 279 if (!kvm_vcpu_has_lapic(vcpu))
fc61b800
GN		 280 return;
281
282 feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
283 if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
284 v |= APIC_LVR_DIRECTED_EOI;
285 apic_set_reg(apic, APIC_LVR, v);
286}
287
f1d24831 288static const unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
a3e06bbe 289 LVT_MASK , /* part LVTT mask, timer mode mask added at runtime */
97222cc8
ED		 290 LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */
291 LVT_MASK | APIC_MODE_MASK, /* LVTPC */
292 LINT_MASK, LINT_MASK, /* LVT0-1 */
293 LVT_MASK /* LVTERR */
294};
295
296static int find_highest_vector(void *bitmap)
297{
ecba9a52
TY		 298 int vec;
299 u32 *reg;
97222cc8 300
ecba9a52
TY		 301 for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG;
302 vec >= 0; vec -= APIC_VECTORS_PER_REG) {
303 reg = bitmap + REG_POS(vec);
304 if (*reg)
305 return fls(*reg) - 1 + vec;
306 }
97222cc8 307
ecba9a52 308 return -1;
97222cc8
ED		 309}
310
8680b94b
MT		 311static u8 count_vectors(void *bitmap)
312{
ecba9a52
TY		 313 int vec;
314 u32 *reg;
8680b94b 315 u8 count = 0;
ecba9a52
TY		 316
317 for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) {
318 reg = bitmap + REG_POS(vec);
319 count += hweight32(*reg);
320 }
321
8680b94b
MT		 322 return count;
323}
324
705699a1 325void __kvm_apic_update_irr(u32 *pir, void *regs)
a20ed54d
YZ		 326{
327 u32 i, pir_val;
a20ed54d
YZ		 328
329 for (i = 0; i <= 7; i++) {
330 pir_val = xchg(&pir[i], 0);
331 if (pir_val)
705699a1 332 *((u32 *)(regs + APIC_IRR + i * 0x10)) |= pir_val;
a20ed54d
YZ		 333 }
334}
705699a1
WV		 335EXPORT_SYMBOL_GPL(__kvm_apic_update_irr);
336
337void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir)
338{
339 struct kvm_lapic *apic = vcpu->arch.apic;
340
341 __kvm_apic_update_irr(pir, apic->regs);
342}
a20ed54d
YZ		 343EXPORT_SYMBOL_GPL(kvm_apic_update_irr);
344
11f5cc05 345static inline void apic_set_irr(int vec, struct kvm_lapic *apic)
97222cc8 346{
11f5cc05 347 apic_set_vector(vec, apic->regs + APIC_IRR);
f210f757
NA		 348 /*
349 * irr_pending must be true if any interrupt is pending; set it after
350 * APIC_IRR to avoid race with apic_clear_irr
351 */
352 apic->irr_pending = true;
97222cc8
ED		 353}
354
33e4c686 355static inline int apic_search_irr(struct kvm_lapic *apic)
97222cc8 356{
33e4c686 357 return find_highest_vector(apic->regs + APIC_IRR);
97222cc8
ED		 358}
359
360static inline int apic_find_highest_irr(struct kvm_lapic *apic)
361{
362 int result;
363
c7c9c56c
YZ		 364 /*
365 * Note that irr_pending is just a hint. It will be always
366 * true with virtual interrupt delivery enabled.
367 */
33e4c686
GN		 368 if (!apic->irr_pending)
369 return -1;
370
5a71785d 371 kvm_x86_ops->sync_pir_to_irr(apic->vcpu);
33e4c686 372 result = apic_search_irr(apic);
97222cc8
ED		 373 ASSERT(result == -1 || result >= 16);
374
375 return result;
376}
377
33e4c686
GN		 378static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
379{
56cc2406
WL		 380 struct kvm_vcpu *vcpu;
381
382 vcpu = apic->vcpu;
383
f210f757 384 if (unlikely(kvm_apic_vid_enabled(vcpu->kvm))) {
56cc2406 385 /* try to update RVI */
f210f757 386 apic_clear_vector(vec, apic->regs + APIC_IRR);
56cc2406 387 kvm_make_request(KVM_REQ_EVENT, vcpu);
f210f757
NA		 388 } else {
389 apic->irr_pending = false;
390 apic_clear_vector(vec, apic->regs + APIC_IRR);
391 if (apic_search_irr(apic) != -1)
392 apic->irr_pending = true;
56cc2406 393 }
33e4c686
GN		 394}
395
8680b94b
MT		 396static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
397{
56cc2406
WL		 398 struct kvm_vcpu *vcpu;
399
400 if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
401 return;
402
403 vcpu = apic->vcpu;
fc57ac2c 404
8680b94b 405 /*
56cc2406
WL		 406 * With APIC virtualization enabled, all caching is disabled
407 * because the processor can modify ISR under the hood. Instead
408 * just set SVI.
8680b94b 409 */
b4eef9b3 410 if (unlikely(kvm_x86_ops->hwapic_isr_update))
56cc2406
WL		 411 kvm_x86_ops->hwapic_isr_update(vcpu->kvm, vec);
412 else {
413 ++apic->isr_count;
414 BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
415 /*
416 * ISR (in service register) bit is set when injecting an interrupt.
417 * The highest vector is injected. Thus the latest bit set matches
418 * the highest bit in ISR.
419 */
420 apic->highest_isr_cache = vec;
421 }
8680b94b
MT		 422}
423
fc57ac2c
PB		 424static inline int apic_find_highest_isr(struct kvm_lapic *apic)
425{
426 int result;
427
428 /*
429 * Note that isr_count is always 1, and highest_isr_cache
430 * is always -1, with APIC virtualization enabled.
431 */
432 if (!apic->isr_count)
433 return -1;
434 if (likely(apic->highest_isr_cache != -1))
435 return apic->highest_isr_cache;
436
437 result = find_highest_vector(apic->regs + APIC_ISR);
438 ASSERT(result == -1 || result >= 16);
439
440 return result;
441}
442
8680b94b
MT		 443static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
444{
fc57ac2c
PB		 445 struct kvm_vcpu *vcpu;
446 if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
447 return;
448
449 vcpu = apic->vcpu;
450
451 /*
452 * We do get here for APIC virtualization enabled if the guest
453 * uses the Hyper-V APIC enlightenment. In this case we may need
454 * to trigger a new interrupt delivery by writing the SVI field;
455 * on the other hand isr_count and highest_isr_cache are unused
456 * and must be left alone.
457 */
b4eef9b3 458 if (unlikely(kvm_x86_ops->hwapic_isr_update))
fc57ac2c
PB		 459 kvm_x86_ops->hwapic_isr_update(vcpu->kvm,
460 apic_find_highest_isr(apic));
461 else {
8680b94b 462 --apic->isr_count;
fc57ac2c
PB		 463 BUG_ON(apic->isr_count < 0);
464 apic->highest_isr_cache = -1;
465 }
8680b94b
MT		 466}
467
6e5d865c
YS		 468int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
469{
6e5d865c
YS		 470 int highest_irr;
471
33e4c686
GN		 472 /* This may race with setting of irr in __apic_accept_irq() and
473 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
474 * will cause vmexit immediately and the value will be recalculated
475 * on the next vmentry.
476 */
c48f1496 477 if (!kvm_vcpu_has_lapic(vcpu))
6e5d865c 478 return 0;
54e9818f 479 highest_irr = apic_find_highest_irr(vcpu->arch.apic);
6e5d865c
YS		 480
481 return highest_irr;
482}
6e5d865c 483
6da7e3f6 484static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
b4f2225c
YZ		 485 int vector, int level, int trig_mode,
486 unsigned long *dest_map);
6da7e3f6 487
b4f2225c
YZ		 488int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
489 unsigned long *dest_map)
97222cc8 490{
ad312c7c 491 struct kvm_lapic *apic = vcpu->arch.apic;
8be5453f 492
58c2dde1 493 return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
b4f2225c 494 irq->level, irq->trig_mode, dest_map);
97222cc8
ED		 495}
496
ae7a2a3f
MT		 497static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
498{
499
500 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
501 sizeof(val));
502}
503
504static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
505{
506
507 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
508 sizeof(*val));
509}
510
511static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
512{
513 return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
514}
515
516static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
517{
518 u8 val;
519 if (pv_eoi_get_user(vcpu, &val) < 0)
520 apic_debug("Can't read EOI MSR value: 0x%llx\n",
96893977 521 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
ae7a2a3f
MT		 522 return val & 0x1;
523}
524
525static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
526{
527 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
528 apic_debug("Can't set EOI MSR value: 0x%llx\n",
96893977 529 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
ae7a2a3f
MT		 530 return;
531 }
532 __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
533}
534
535static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
536{
537 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
538 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
96893977 539 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
ae7a2a3f
MT		 540 return;
541 }
542 __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
543}
544
cf9e65b7
YZ		 545void kvm_apic_update_tmr(struct kvm_vcpu *vcpu, u32 *tmr)
546{
547 struct kvm_lapic *apic = vcpu->arch.apic;
548 int i;
549
550 for (i = 0; i < 8; i++)
551 apic_set_reg(apic, APIC_TMR + 0x10 * i, tmr[i]);
552}
553
97222cc8
ED		 554static void apic_update_ppr(struct kvm_lapic *apic)
555{
3842d135 556 u32 tpr, isrv, ppr, old_ppr;
97222cc8
ED		 557 int isr;
558
c48f1496
GN		 559 old_ppr = kvm_apic_get_reg(apic, APIC_PROCPRI);
560 tpr = kvm_apic_get_reg(apic, APIC_TASKPRI);
97222cc8
ED		 561 isr = apic_find_highest_isr(apic);
562 isrv = (isr != -1) ? isr : 0;
563
564 if ((tpr & 0xf0) >= (isrv & 0xf0))
565 ppr = tpr & 0xff;
566 else
567 ppr = isrv & 0xf0;
568
569 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
570 apic, ppr, isr, isrv);
571
3842d135
AK		 572 if (old_ppr != ppr) {
573 apic_set_reg(apic, APIC_PROCPRI, ppr);
83bcacb1
AK		 574 if (ppr < old_ppr)
575 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
3842d135 576 }
97222cc8
ED		 577}
578
579static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
580{
581 apic_set_reg(apic, APIC_TASKPRI, tpr);
582 apic_update_ppr(apic);
583}
584
03d2249e 585static bool kvm_apic_broadcast(struct kvm_lapic *apic, u32 mda)
394457a9 586{
03d2249e
RK		 587 if (apic_x2apic_mode(apic))
588 return mda == X2APIC_BROADCAST;
589
590 return GET_APIC_DEST_FIELD(mda) == APIC_BROADCAST;
394457a9
NA		 591}
592
03d2249e 593static bool kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 mda)
97222cc8 594{
03d2249e
RK		 595 if (kvm_apic_broadcast(apic, mda))
596 return true;
597
598 if (apic_x2apic_mode(apic))
599 return mda == kvm_apic_id(apic);
600
601 return mda == SET_APIC_DEST_FIELD(kvm_apic_id(apic));
97222cc8
ED		 602}
603
52c233a4 604static bool kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda)
97222cc8 605{
0105d1a5
GN		 606 u32 logical_id;
607
394457a9 608 if (kvm_apic_broadcast(apic, mda))
9368b567 609 return true;
394457a9 610
9368b567 611 logical_id = kvm_apic_get_reg(apic, APIC_LDR);
97222cc8 612
9368b567 613 if (apic_x2apic_mode(apic))
8a395363
RK		 614 return ((logical_id >> 16) == (mda >> 16))
615 && (logical_id & mda & 0xffff) != 0;
97222cc8 616
9368b567 617 logical_id = GET_APIC_LOGICAL_ID(logical_id);
03d2249e 618 mda = GET_APIC_DEST_FIELD(mda);
97222cc8 619
c48f1496 620 switch (kvm_apic_get_reg(apic, APIC_DFR)) {
97222cc8 621 case APIC_DFR_FLAT:
9368b567 622 return (logical_id & mda) != 0;
97222cc8 623 case APIC_DFR_CLUSTER:
9368b567
RK		 624 return ((logical_id >> 4) == (mda >> 4))
625 && (logical_id & mda & 0xf) != 0;
97222cc8 626 default:
7712de87 627 apic_debug("Bad DFR vcpu %d: %08x\n",
c48f1496 628 apic->vcpu->vcpu_id, kvm_apic_get_reg(apic, APIC_DFR));
9368b567 629 return false;
97222cc8 630 }
97222cc8
ED		 631}
632
03d2249e
RK		 633/* KVM APIC implementation has two quirks
634 * - dest always begins at 0 while xAPIC MDA has offset 24,
635 * - IOxAPIC messages have to be delivered (directly) to x2APIC.
636 */
637static u32 kvm_apic_mda(unsigned int dest_id, struct kvm_lapic *source,
638 struct kvm_lapic *target)
639{
640 bool ipi = source != NULL;
641 bool x2apic_mda = apic_x2apic_mode(ipi ? source : target);
642
643 if (!ipi && dest_id == APIC_BROADCAST && x2apic_mda)
644 return X2APIC_BROADCAST;
645
646 return x2apic_mda ? dest_id : SET_APIC_DEST_FIELD(dest_id);
647}
648
52c233a4 649bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
394457a9 650 int short_hand, unsigned int dest, int dest_mode)
97222cc8 651{
ad312c7c 652 struct kvm_lapic *target = vcpu->arch.apic;
03d2249e 653 u32 mda = kvm_apic_mda(dest, source, target);
97222cc8
ED		 654
655 apic_debug("target %p, source %p, dest 0x%x, "
343f94fe 656 "dest_mode 0x%x, short_hand 0x%x\n",
97222cc8
ED		 657 target, source, dest, dest_mode, short_hand);
658
bd371396 659 ASSERT(target);
97222cc8
ED		 660 switch (short_hand) {
661 case APIC_DEST_NOSHORT:
3697f302 662 if (dest_mode == APIC_DEST_PHYSICAL)
03d2249e 663 return kvm_apic_match_physical_addr(target, mda);
343f94fe 664 else
03d2249e 665 return kvm_apic_match_logical_addr(target, mda);
97222cc8 666 case APIC_DEST_SELF:
9368b567 667 return target == source;
97222cc8 668 case APIC_DEST_ALLINC:
9368b567 669 return true;
97222cc8 670 case APIC_DEST_ALLBUT:
9368b567 671 return target != source;
97222cc8 672 default:
7712de87
JK		 673 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
674 short_hand);
9368b567 675 return false;
97222cc8 676 }
97222cc8
ED		 677}
678
1e08ec4a 679bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
b4f2225c 680 struct kvm_lapic_irq *irq, int *r, unsigned long *dest_map)
1e08ec4a
GN		 681{
682 struct kvm_apic_map *map;
683 unsigned long bitmap = 1;
684 struct kvm_lapic **dst;
685 int i;
686 bool ret = false;
9ea369b0 687 bool x2apic_ipi = src && apic_x2apic_mode(src);
1e08ec4a
GN		 688
689 *r = -1;
690
691 if (irq->shorthand == APIC_DEST_SELF) {
b4f2225c 692 *r = kvm_apic_set_irq(src->vcpu, irq, dest_map);
1e08ec4a
GN		 693 return true;
694 }
695
696 if (irq->shorthand)
697 return false;
698
9ea369b0
RK		 699 if (irq->dest_id == (x2apic_ipi ? X2APIC_BROADCAST : APIC_BROADCAST))
700 return false;
701
1e08ec4a
GN		 702 rcu_read_lock();
703 map = rcu_dereference(kvm->arch.apic_map);
704
705 if (!map)
706 goto out;
707
698f9755
RK		 708 ret = true;
709
3697f302 710 if (irq->dest_mode == APIC_DEST_PHYSICAL) {
fa834e91
RK		 711 if (irq->dest_id >= ARRAY_SIZE(map->phys_map))
712 goto out;
713
714 dst = &map->phys_map[irq->dest_id];
1e08ec4a 715 } else {
3548a259
RK		 716 u16 cid;
717
718 if (!kvm_apic_logical_map_valid(map)) {
719 ret = false;
720 goto out;
721 }
722
3b5a5ffa 723 apic_logical_id(map, irq->dest_id, &cid, (u16 *)&bitmap);
45c3094a
RK		 724
725 if (cid >= ARRAY_SIZE(map->logical_map))
726 goto out;
1e08ec4a 727
45c3094a 728 dst = map->logical_map[cid];
1e08ec4a 729
1e08ec4a
GN		 730 if (irq->delivery_mode == APIC_DM_LOWEST) {
731 int l = -1;
732 for_each_set_bit(i, &bitmap, 16) {
733 if (!dst[i])
734 continue;
735 if (l < 0)
736 l = i;
737 else if (kvm_apic_compare_prio(dst[i]->vcpu, dst[l]->vcpu) < 0)
738 l = i;
739 }
740
741 bitmap = (l >= 0) ? 1 << l : 0;
742 }
743 }
744
745 for_each_set_bit(i, &bitmap, 16) {
746 if (!dst[i])
747 continue;
748 if (*r < 0)
749 *r = 0;
b4f2225c 750 *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map);
1e08ec4a 751 }
1e08ec4a
GN		 752out:
753 rcu_read_unlock();
754 return ret;
755}
756
97222cc8
ED		 757/*
758 * Add a pending IRQ into lapic.
759 * Return 1 if successfully added and 0 if discarded.
760 */
761static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
b4f2225c
YZ		 762 int vector, int level, int trig_mode,
763 unsigned long *dest_map)
97222cc8 764{
6da7e3f6 765 int result = 0;
c5ec1534 766 struct kvm_vcpu *vcpu = apic->vcpu;
97222cc8 767
a183b638
PB		 768 trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
769 trig_mode, vector);
97222cc8 770 switch (delivery_mode) {
97222cc8 771 case APIC_DM_LOWEST:
e1035715
GN		 772 vcpu->arch.apic_arb_prio++;
773 case APIC_DM_FIXED:
97222cc8
ED		 774 /* FIXME add logic for vcpu on reset */
775 if (unlikely(!apic_enabled(apic)))
776 break;
777
11f5cc05
JK		 778 result = 1;
779
b4f2225c
YZ		 780 if (dest_map)
781 __set_bit(vcpu->vcpu_id, dest_map);
a5d36f82 782
11f5cc05 783 if (kvm_x86_ops->deliver_posted_interrupt)
5a71785d 784 kvm_x86_ops->deliver_posted_interrupt(vcpu, vector);
11f5cc05
JK		 785 else {
786 apic_set_irr(vector, apic);
5a71785d
YZ		 787
788 kvm_make_request(KVM_REQ_EVENT, vcpu);
789 kvm_vcpu_kick(vcpu);
790 }
97222cc8
ED		 791 break;
792
793 case APIC_DM_REMRD:
24d2166b
R		 794 result = 1;
795 vcpu->arch.pv.pv_unhalted = 1;
796 kvm_make_request(KVM_REQ_EVENT, vcpu);
797 kvm_vcpu_kick(vcpu);
97222cc8
ED		 798 break;
799
800 case APIC_DM_SMI:
7712de87 801 apic_debug("Ignoring guest SMI\n");
97222cc8 802 break;
3419ffc8 803
97222cc8 804 case APIC_DM_NMI:
6da7e3f6 805 result = 1;
3419ffc8 806 kvm_inject_nmi(vcpu);
26df99c6 807 kvm_vcpu_kick(vcpu);
97222cc8
ED		 808 break;
809
810 case APIC_DM_INIT:
a52315e1 811 if (!trig_mode || level) {
6da7e3f6 812 result = 1;
66450a21
JK		 813 /* assumes that there are only KVM_APIC_INIT/SIPI */
814 apic->pending_events = (1UL << KVM_APIC_INIT);
815 /* make sure pending_events is visible before sending
816 * the request */
817 smp_wmb();
3842d135 818 kvm_make_request(KVM_REQ_EVENT, vcpu);
c5ec1534
HQ		 819 kvm_vcpu_kick(vcpu);
820 } else {
1b10bf31
JK		 821 apic_debug("Ignoring de-assert INIT to vcpu %d\n",
822 vcpu->vcpu_id);
c5ec1534 823 }
97222cc8
ED		 824 break;
825
826 case APIC_DM_STARTUP:
1b10bf31
JK		 827 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
828 vcpu->vcpu_id, vector);
66450a21
JK		 829 result = 1;
830 apic->sipi_vector = vector;
831 /* make sure sipi_vector is visible for the receiver */
832 smp_wmb();
833 set_bit(KVM_APIC_SIPI, &apic->pending_events);
834 kvm_make_request(KVM_REQ_EVENT, vcpu);
835 kvm_vcpu_kick(vcpu);
97222cc8
ED		 836 break;
837
23930f95
JK		 838 case APIC_DM_EXTINT:
839 /*
840 * Should only be called by kvm_apic_local_deliver() with LVT0,
841 * before NMI watchdog was enabled. Already handled by
842 * kvm_apic_accept_pic_intr().
843 */
844 break;
845
97222cc8
ED		 846 default:
847 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
848 delivery_mode);
849 break;
850 }
851 return result;
852}
853
e1035715 854int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
8be5453f 855{
e1035715 856 return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
8be5453f
ZX		 857}
858
c7c9c56c
YZ		 859static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)
860{
c806a6ad 861 if (kvm_ioapic_handles_vector(apic->vcpu->kvm, vector)) {
c7c9c56c
YZ		 862 int trigger_mode;
863 if (apic_test_vector(vector, apic->regs + APIC_TMR))
864 trigger_mode = IOAPIC_LEVEL_TRIG;
865 else
866 trigger_mode = IOAPIC_EDGE_TRIG;
1fcc7890 867 kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode);
c7c9c56c
YZ		 868 }
869}
870
ae7a2a3f 871static int apic_set_eoi(struct kvm_lapic *apic)
97222cc8
ED		 872{
873 int vector = apic_find_highest_isr(apic);
ae7a2a3f
MT		 874
875 trace_kvm_eoi(apic, vector);
876
97222cc8
ED		 877 /*
878 * Not every write EOI will has corresponding ISR,
879 * one example is when Kernel check timer on setup_IO_APIC
880 */
881 if (vector == -1)
ae7a2a3f 882 return vector;
97222cc8 883
8680b94b 884 apic_clear_isr(vector, apic);
97222cc8
ED		 885 apic_update_ppr(apic);
886
c7c9c56c 887 kvm_ioapic_send_eoi(apic, vector);
3842d135 888 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
ae7a2a3f 889 return vector;
97222cc8
ED		 890}
891
c7c9c56c
YZ		 892/*
893 * this interface assumes a trap-like exit, which has already finished
894 * desired side effect including vISR and vPPR update.
895 */
896void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector)
897{
898 struct kvm_lapic *apic = vcpu->arch.apic;
899
900 trace_kvm_eoi(apic, vector);
901
902 kvm_ioapic_send_eoi(apic, vector);
903 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
904}
905EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated);
906
97222cc8
ED		 907static void apic_send_ipi(struct kvm_lapic *apic)
908{
c48f1496
GN		 909 u32 icr_low = kvm_apic_get_reg(apic, APIC_ICR);
910 u32 icr_high = kvm_apic_get_reg(apic, APIC_ICR2);
58c2dde1 911 struct kvm_lapic_irq irq;
97222cc8 912
58c2dde1
GN		 913 irq.vector = icr_low & APIC_VECTOR_MASK;
914 irq.delivery_mode = icr_low & APIC_MODE_MASK;
915 irq.dest_mode = icr_low & APIC_DEST_MASK;
916 irq.level = icr_low & APIC_INT_ASSERT;
917 irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
918 irq.shorthand = icr_low & APIC_SHORT_MASK;
0105d1a5
GN		 919 if (apic_x2apic_mode(apic))
920 irq.dest_id = icr_high;
921 else
922 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
97222cc8 923
1000ff8d
GN		 924 trace_kvm_apic_ipi(icr_low, irq.dest_id);
925
97222cc8
ED		 926 apic_debug("icr_high 0x%x, icr_low 0x%x, "
927 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
928 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
9b5843dd 929 icr_high, icr_low, irq.shorthand, irq.dest_id,
58c2dde1
GN		 930 irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
931 irq.vector);
932
b4f2225c 933 kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL);
97222cc8
ED		 934}
935
936static u32 apic_get_tmcct(struct kvm_lapic *apic)
937{
b682b814
MT		 938 ktime_t remaining;
939 s64 ns;
9da8f4e8 940 u32 tmcct;
97222cc8
ED		 941
942 ASSERT(apic != NULL);
943
9da8f4e8 944 /* if initial count is 0, current count should also be 0 */
b963a22e
AH		 945 if (kvm_apic_get_reg(apic, APIC_TMICT) == 0 ||
946 apic->lapic_timer.period == 0)
9da8f4e8
KP		 947 return 0;
948
ace15464 949 remaining = hrtimer_get_remaining(&apic->lapic_timer.timer);
b682b814
MT		 950 if (ktime_to_ns(remaining) < 0)
951 remaining = ktime_set(0, 0);
952
d3c7b77d
MT		 953 ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
954 tmcct = div64_u64(ns,
955 (APIC_BUS_CYCLE_NS * apic->divide_count));
97222cc8
ED		 956
957 return tmcct;
958}
959
b209749f
AK		 960static void __report_tpr_access(struct kvm_lapic *apic, bool write)
961{
962 struct kvm_vcpu *vcpu = apic->vcpu;
963 struct kvm_run *run = vcpu->run;
964
a8eeb04a 965 kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
5fdbf976 966 run->tpr_access.rip = kvm_rip_read(vcpu);
b209749f
AK		 967 run->tpr_access.is_write = write;
968}
969
970static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
971{
972 if (apic->vcpu->arch.tpr_access_reporting)
973 __report_tpr_access(apic, write);
974}
975
97222cc8
ED		 976static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
977{
978 u32 val = 0;
979
980 if (offset >= LAPIC_MMIO_LENGTH)
981 return 0;
982
983 switch (offset) {
0105d1a5
GN		 984 case APIC_ID:
985 if (apic_x2apic_mode(apic))
986 val = kvm_apic_id(apic);
987 else
988 val = kvm_apic_id(apic) << 24;
989 break;
97222cc8 990 case APIC_ARBPRI:
7712de87 991 apic_debug("Access APIC ARBPRI register which is for P6\n");
97222cc8
ED		 992 break;
993
994 case APIC_TMCCT: /* Timer CCR */
a3e06bbe
LJ		 995 if (apic_lvtt_tscdeadline(apic))
996 return 0;
997
97222cc8
ED		 998 val = apic_get_tmcct(apic);
999 break;
4a4541a4
AK		 1000 case APIC_PROCPRI:
1001 apic_update_ppr(apic);
c48f1496 1002 val = kvm_apic_get_reg(apic, offset);
4a4541a4 1003 break;
b209749f
AK		 1004 case APIC_TASKPRI:
1005 report_tpr_access(apic, false);
1006 /* fall thru */
97222cc8 1007 default:
c48f1496 1008 val = kvm_apic_get_reg(apic, offset);
97222cc8
ED		 1009 break;
1010 }
1011
1012 return val;
1013}
1014
d76685c4
GH		 1015static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
1016{
1017 return container_of(dev, struct kvm_lapic, dev);
1018}
1019
0105d1a5
GN		 1020static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
1021 void *data)
97222cc8 1022{
97222cc8
ED		 1023 unsigned char alignment = offset & 0xf;
1024 u32 result;
d5b0b5b1 1025 /* this bitmask has a bit cleared for each reserved register */
0105d1a5 1026 static const u64 rmask = 0x43ff01ffffffe70cULL;
97222cc8
ED		 1027
1028 if ((alignment + len) > 4) {
4088bb3c
GN		 1029 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
1030 offset, len);
0105d1a5 1031 return 1;
97222cc8 1032 }
0105d1a5
GN		 1033
1034 if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
4088bb3c
GN		 1035 apic_debug("KVM_APIC_READ: read reserved register %x\n",
1036 offset);
0105d1a5
GN		 1037 return 1;
1038 }
1039
97222cc8
ED		 1040 result = __apic_read(apic, offset & ~0xf);
1041
229456fc
MT		 1042 trace_kvm_apic_read(offset, result);
1043
97222cc8
ED		 1044 switch (len) {
1045 case 1:
1046 case 2:
1047 case 4:
1048 memcpy(data, (char *)&result + alignment, len);
1049 break;
1050 default:
1051 printk(KERN_ERR "Local APIC read with len = %x, "
1052 "should be 1,2, or 4 instead\n", len);
1053 break;
1054 }
bda9020e 1055 return 0;
97222cc8
ED		 1056}
1057
0105d1a5
GN		 1058static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
1059{
c48f1496 1060 return kvm_apic_hw_enabled(apic) &&
0105d1a5
GN		 1061 addr >= apic->base_address &&
1062 addr < apic->base_address + LAPIC_MMIO_LENGTH;
1063}
1064
e32edf4f 1065static int apic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
0105d1a5
GN		 1066 gpa_t address, int len, void *data)
1067{
1068 struct kvm_lapic *apic = to_lapic(this);
1069 u32 offset = address - apic->base_address;
1070
1071 if (!apic_mmio_in_range(apic, address))
1072 return -EOPNOTSUPP;
1073
1074 apic_reg_read(apic, offset, len, data);
1075
1076 return 0;
1077}
1078
97222cc8
ED		 1079static void update_divide_count(struct kvm_lapic *apic)
1080{
1081 u32 tmp1, tmp2, tdcr;
1082
c48f1496 1083 tdcr = kvm_apic_get_reg(apic, APIC_TDCR);
97222cc8
ED		 1084 tmp1 = tdcr & 0xf;
1085 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
d3c7b77d 1086 apic->divide_count = 0x1 << (tmp2 & 0x7);
97222cc8
ED		 1087
1088 apic_debug("timer divide count is 0x%x\n",
9b5843dd 1089 apic->divide_count);
97222cc8
ED		 1090}
1091
5d87db71
RK		 1092static void apic_timer_expired(struct kvm_lapic *apic)
1093{
1094 struct kvm_vcpu *vcpu = apic->vcpu;
1095 wait_queue_head_t *q = &vcpu->wq;
d0659d94 1096 struct kvm_timer *ktimer = &apic->lapic_timer;
5d87db71 1097
5d87db71
RK		 1098 if (atomic_read(&apic->lapic_timer.pending))
1099 return;
1100
1101 atomic_inc(&apic->lapic_timer.pending);
bab5bb39 1102 kvm_set_pending_timer(vcpu);
5d87db71
RK		 1103
1104 if (waitqueue_active(q))
1105 wake_up_interruptible(q);
d0659d94
MT		 1106
1107 if (apic_lvtt_tscdeadline(apic))
1108 ktimer->expired_tscdeadline = ktimer->tscdeadline;
1109}
1110
1111/*
1112 * On APICv, this test will cause a busy wait
1113 * during a higher-priority task.
1114 */
1115
1116static bool lapic_timer_int_injected(struct kvm_vcpu *vcpu)
1117{
1118 struct kvm_lapic *apic = vcpu->arch.apic;
1119 u32 reg = kvm_apic_get_reg(apic, APIC_LVTT);
1120
1121 if (kvm_apic_hw_enabled(apic)) {
1122 int vec = reg & APIC_VECTOR_MASK;
f9339860 1123 void *bitmap = apic->regs + APIC_ISR;
d0659d94 1124
f9339860
MT		 1125 if (kvm_x86_ops->deliver_posted_interrupt)
1126 bitmap = apic->regs + APIC_IRR;
1127
1128 if (apic_test_vector(vec, bitmap))
1129 return true;
d0659d94
MT		 1130 }
1131 return false;
1132}
1133
1134void wait_lapic_expire(struct kvm_vcpu *vcpu)
1135{
1136 struct kvm_lapic *apic = vcpu->arch.apic;
1137 u64 guest_tsc, tsc_deadline;
1138
1139 if (!kvm_vcpu_has_lapic(vcpu))
1140 return;
1141
1142 if (apic->lapic_timer.expired_tscdeadline == 0)
1143 return;
1144
1145 if (!lapic_timer_int_injected(vcpu))
1146 return;
1147
1148 tsc_deadline = apic->lapic_timer.expired_tscdeadline;
1149 apic->lapic_timer.expired_tscdeadline = 0;
1150 guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, native_read_tsc());
6c19b753 1151 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, guest_tsc - tsc_deadline);
d0659d94
MT		 1152
1153 /* __delay is delay_tsc whenever the hardware has TSC, thus always. */
1154 if (guest_tsc < tsc_deadline)
1155 __delay(tsc_deadline - guest_tsc);
5d87db71
RK		 1156}
1157
97222cc8
ED		 1158static void start_apic_timer(struct kvm_lapic *apic)
1159{
a3e06bbe 1160 ktime_t now;
d0659d94 1161
d3c7b77d 1162 atomic_set(&apic->lapic_timer.pending, 0);
0b975a3c 1163
a3e06bbe 1164 if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) {
d5b0b5b1 1165 /* lapic timer in oneshot or periodic mode */
a3e06bbe 1166 now = apic->lapic_timer.timer.base->get_time();
c48f1496 1167 apic->lapic_timer.period = (u64)kvm_apic_get_reg(apic, APIC_TMICT)
a3e06bbe
LJ		 1168 * APIC_BUS_CYCLE_NS * apic->divide_count;
1169
1170 if (!apic->lapic_timer.period)
1171 return;
1172 /*
1173 * Do not allow the guest to program periodic timers with small
1174 * interval, since the hrtimers are not throttled by the host
1175 * scheduler.
1176 */
1177 if (apic_lvtt_period(apic)) {
1178 s64 min_period = min_timer_period_us * 1000LL;
1179
1180 if (apic->lapic_timer.period < min_period) {
1181 pr_info_ratelimited(
1182 "kvm: vcpu %i: requested %lld ns "
1183 "lapic timer period limited to %lld ns\n",
1184 apic->vcpu->vcpu_id,
1185 apic->lapic_timer.period, min_period);
1186 apic->lapic_timer.period = min_period;
1187 }
9bc5791d 1188 }
0b975a3c 1189
a3e06bbe
LJ		 1190 hrtimer_start(&apic->lapic_timer.timer,
1191 ktime_add_ns(now, apic->lapic_timer.period),
1192 HRTIMER_MODE_ABS);
97222cc8 1193
a3e06bbe 1194 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
97222cc8
ED		 1195 PRIx64 ", "
1196 "timer initial count 0x%x, period %lldns, "
b8688d51 1197 "expire @ 0x%016" PRIx64 ".\n", __func__,
97222cc8 1198 APIC_BUS_CYCLE_NS, ktime_to_ns(now),
c48f1496 1199 kvm_apic_get_reg(apic, APIC_TMICT),
d3c7b77d 1200 apic->lapic_timer.period,
97222cc8 1201 ktime_to_ns(ktime_add_ns(now,
d3c7b77d 1202 apic->lapic_timer.period)));
a3e06bbe
LJ		 1203 } else if (apic_lvtt_tscdeadline(apic)) {
1204 /* lapic timer in tsc deadline mode */
1205 u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline;
1206 u64 ns = 0;
d0659d94 1207 ktime_t expire;
a3e06bbe 1208 struct kvm_vcpu *vcpu = apic->vcpu;
cc578287 1209 unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
a3e06bbe
LJ		 1210 unsigned long flags;
1211
1212 if (unlikely(!tscdeadline || !this_tsc_khz))
1213 return;
1214
1215 local_irq_save(flags);
1216
1217 now = apic->lapic_timer.timer.base->get_time();
886b470c 1218 guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, native_read_tsc());
a3e06bbe
LJ		 1219 if (likely(tscdeadline > guest_tsc)) {
1220 ns = (tscdeadline - guest_tsc) * 1000000ULL;
1221 do_div(ns, this_tsc_khz);
d0659d94
MT		 1222 expire = ktime_add_ns(now, ns);
1223 expire = ktime_sub_ns(expire, lapic_timer_advance_ns);
1e0ad70c 1224 hrtimer_start(&apic->lapic_timer.timer,
d0659d94 1225 expire, HRTIMER_MODE_ABS);
1e0ad70c
RK		 1226 } else
1227 apic_timer_expired(apic);
a3e06bbe
LJ		 1228
1229 local_irq_restore(flags);
1230 }
97222cc8
ED		 1231}
1232
cc6e462c
JK		 1233static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
1234{
c48f1496 1235 int nmi_wd_enabled = apic_lvt_nmi_mode(kvm_apic_get_reg(apic, APIC_LVT0));
cc6e462c
JK		 1236
1237 if (apic_lvt_nmi_mode(lvt0_val)) {
1238 if (!nmi_wd_enabled) {
1239 apic_debug("Receive NMI setting on APIC_LVT0 "
1240 "for cpu %d\n", apic->vcpu->vcpu_id);
1241 apic->vcpu->kvm->arch.vapics_in_nmi_mode++;
1242 }
1243 } else if (nmi_wd_enabled)
1244 apic->vcpu->kvm->arch.vapics_in_nmi_mode--;
1245}
1246
0105d1a5 1247static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
97222cc8 1248{
0105d1a5 1249 int ret = 0;
97222cc8 1250
0105d1a5 1251 trace_kvm_apic_write(reg, val);
97222cc8 1252
0105d1a5 1253 switch (reg) {
97222cc8 1254 case APIC_ID: /* Local APIC ID */
0105d1a5 1255 if (!apic_x2apic_mode(apic))
1e08ec4a 1256 kvm_apic_set_id(apic, val >> 24);
0105d1a5
GN		 1257 else
1258 ret = 1;
97222cc8
ED		 1259 break;
1260
1261 case APIC_TASKPRI:
b209749f 1262 report_tpr_access(apic, true);
97222cc8
ED		 1263 apic_set_tpr(apic, val & 0xff);
1264 break;
1265
1266 case APIC_EOI:
1267 apic_set_eoi(apic);
1268 break;
1269
1270 case APIC_LDR:
0105d1a5 1271 if (!apic_x2apic_mode(apic))
1e08ec4a 1272 kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);
0105d1a5
GN		 1273 else
1274 ret = 1;
97222cc8
ED		 1275 break;
1276
1277 case APIC_DFR:
1e08ec4a 1278 if (!apic_x2apic_mode(apic)) {
0105d1a5 1279 apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
1e08ec4a
GN		 1280 recalculate_apic_map(apic->vcpu->kvm);
1281 } else
0105d1a5 1282 ret = 1;
97222cc8
ED		 1283 break;
1284
fc61b800
GN		 1285 case APIC_SPIV: {
1286 u32 mask = 0x3ff;
c48f1496 1287 if (kvm_apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
fc61b800 1288 mask |= APIC_SPIV_DIRECTED_EOI;
f8c1ea10 1289 apic_set_spiv(apic, val & mask);
97222cc8
ED		 1290 if (!(val & APIC_SPIV_APIC_ENABLED)) {
1291 int i;
1292 u32 lvt_val;
1293
1294 for (i = 0; i < APIC_LVT_NUM; i++) {
c48f1496 1295 lvt_val = kvm_apic_get_reg(apic,
97222cc8
ED		 1296 APIC_LVTT + 0x10 * i);
1297 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
1298 lvt_val | APIC_LVT_MASKED);
1299 }
d3c7b77d 1300 atomic_set(&apic->lapic_timer.pending, 0);
97222cc8
ED		 1301
1302 }
1303 break;
fc61b800 1304 }
97222cc8
ED		 1305 case APIC_ICR:
1306 /* No delay here, so we always clear the pending bit */
1307 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
1308 apic_send_ipi(apic);
1309 break;
1310
1311 case APIC_ICR2:
0105d1a5
GN		 1312 if (!apic_x2apic_mode(apic))
1313 val &= 0xff000000;
1314 apic_set_reg(apic, APIC_ICR2, val);
97222cc8
ED		 1315 break;
1316
23930f95 1317 case APIC_LVT0:
cc6e462c 1318 apic_manage_nmi_watchdog(apic, val);
97222cc8
ED		 1319 case APIC_LVTTHMR:
1320 case APIC_LVTPC:
97222cc8
ED		 1321 case APIC_LVT1:
1322 case APIC_LVTERR:
1323 /* TODO: Check vector */
c48f1496 1324 if (!kvm_apic_sw_enabled(apic))
97222cc8
ED		 1325 val |= APIC_LVT_MASKED;
1326
0105d1a5
GN		 1327 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
1328 apic_set_reg(apic, reg, val);
97222cc8
ED		 1329
1330 break;
1331
a323b409
RK		 1332 case APIC_LVTT: {
1333 u32 timer_mode = val & apic->lapic_timer.timer_mode_mask;
1334
1335 if (apic->lapic_timer.timer_mode != timer_mode) {
1336 apic->lapic_timer.timer_mode = timer_mode;
a3e06bbe 1337 hrtimer_cancel(&apic->lapic_timer.timer);
a323b409 1338 }
a3e06bbe 1339
c48f1496 1340 if (!kvm_apic_sw_enabled(apic))
a3e06bbe
LJ		 1341 val |= APIC_LVT_MASKED;
1342 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
1343 apic_set_reg(apic, APIC_LVTT, val);
1344 break;
a323b409 1345 }
a3e06bbe 1346
97222cc8 1347 case APIC_TMICT:
a3e06bbe
LJ		 1348 if (apic_lvtt_tscdeadline(apic))
1349 break;
1350
d3c7b77d 1351 hrtimer_cancel(&apic->lapic_timer.timer);
97222cc8
ED		 1352 apic_set_reg(apic, APIC_TMICT, val);
1353 start_apic_timer(apic);
0105d1a5 1354 break;
97222cc8
ED		 1355
1356 case APIC_TDCR:
1357 if (val & 4)
7712de87 1358 apic_debug("KVM_WRITE:TDCR %x\n", val);
97222cc8
ED		 1359 apic_set_reg(apic, APIC_TDCR, val);
1360 update_divide_count(apic);
1361 break;
1362
0105d1a5
GN		 1363 case APIC_ESR:
1364 if (apic_x2apic_mode(apic) && val != 0) {
7712de87 1365 apic_debug("KVM_WRITE:ESR not zero %x\n", val);
0105d1a5
GN		 1366 ret = 1;
1367 }
1368 break;
1369
1370 case APIC_SELF_IPI:
1371 if (apic_x2apic_mode(apic)) {
1372 apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
1373 } else
1374 ret = 1;
1375 break;
97222cc8 1376 default:
0105d1a5 1377 ret = 1;
97222cc8
ED		 1378 break;
1379 }
0105d1a5
GN		 1380 if (ret)
1381 apic_debug("Local APIC Write to read-only register %x\n", reg);
1382 return ret;
1383}
1384
e32edf4f 1385static int apic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
0105d1a5
GN		 1386 gpa_t address, int len, const void *data)
1387{
1388 struct kvm_lapic *apic = to_lapic(this);
1389 unsigned int offset = address - apic->base_address;
1390 u32 val;
1391
1392 if (!apic_mmio_in_range(apic, address))
1393 return -EOPNOTSUPP;
1394
1395 /*
1396 * APIC register must be aligned on 128-bits boundary.
1397 * 32/64/128 bits registers must be accessed thru 32 bits.
1398 * Refer SDM 8.4.1
1399 */
1400 if (len != 4 || (offset & 0xf)) {
1401 /* Don't shout loud, $infamous_os would cause only noise. */
1402 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
756975bb 1403 return 0;
0105d1a5
GN		 1404 }
1405
1406 val = *(u32*)data;
1407
1408 /* too common printing */
1409 if (offset != APIC_EOI)
1410 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
1411 "0x%x\n", __func__, offset, len, val);
1412
1413 apic_reg_write(apic, offset & 0xff0, val);
1414
bda9020e 1415 return 0;
97222cc8
ED		 1416}
1417
58fbbf26
KT		 1418void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
1419{
c48f1496 1420 if (kvm_vcpu_has_lapic(vcpu))
58fbbf26
KT		 1421 apic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
1422}
1423EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
1424
83d4c286
YZ		 1425/* emulate APIC access in a trap manner */
1426void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
1427{
1428 u32 val = 0;
1429
1430 /* hw has done the conditional check and inst decode */
1431 offset &= 0xff0;
1432
1433 apic_reg_read(vcpu->arch.apic, offset, 4, &val);
1434
1435 /* TODO: optimize to just emulate side effect w/o one more write */
1436 apic_reg_write(vcpu->arch.apic, offset, val);
1437}
1438EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
1439
d589444e 1440void kvm_free_lapic(struct kvm_vcpu *vcpu)
97222cc8 1441{
f8c1ea10
GN		 1442 struct kvm_lapic *apic = vcpu->arch.apic;
1443
ad312c7c 1444 if (!vcpu->arch.apic)
97222cc8
ED		 1445 return;
1446
f8c1ea10 1447 hrtimer_cancel(&apic->lapic_timer.timer);
97222cc8 1448
c5cc421b
GN		 1449 if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
1450 static_key_slow_dec_deferred(&apic_hw_disabled);
1451
e462755c 1452 if (!apic->sw_enabled)
f8c1ea10 1453 static_key_slow_dec_deferred(&apic_sw_disabled);
97222cc8 1454
f8c1ea10
GN		 1455 if (apic->regs)
1456 free_page((unsigned long)apic->regs);
1457
1458 kfree(apic);
97222cc8
ED		 1459}
1460
1461/*
1462 *----------------------------------------------------------------------
1463 * LAPIC interface
1464 *----------------------------------------------------------------------
1465 */
1466
a3e06bbe
LJ		 1467u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
1468{
1469 struct kvm_lapic *apic = vcpu->arch.apic;
a3e06bbe 1470
c48f1496 1471 if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
54e9818f 1472 apic_lvtt_period(apic))
a3e06bbe
LJ		 1473 return 0;
1474
1475 return apic->lapic_timer.tscdeadline;
1476}
1477
1478void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
1479{
1480 struct kvm_lapic *apic = vcpu->arch.apic;
a3e06bbe 1481
c48f1496 1482 if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
54e9818f 1483 apic_lvtt_period(apic))
a3e06bbe
LJ		 1484 return;
1485
1486 hrtimer_cancel(&apic->lapic_timer.timer);
1487 apic->lapic_timer.tscdeadline = data;
1488 start_apic_timer(apic);
1489}
1490
97222cc8
ED		 1491void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
1492{
ad312c7c 1493 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8 1494
c48f1496 1495 if (!kvm_vcpu_has_lapic(vcpu))
97222cc8 1496 return;
54e9818f 1497
b93463aa 1498 apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
c48f1496 1499 | (kvm_apic_get_reg(apic, APIC_TASKPRI) & 4));
97222cc8
ED		 1500}
1501
1502u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
1503{
97222cc8
ED		 1504 u64 tpr;
1505
c48f1496 1506 if (!kvm_vcpu_has_lapic(vcpu))
97222cc8 1507 return 0;
54e9818f 1508
c48f1496 1509 tpr = (u64) kvm_apic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
97222cc8
ED		 1510
1511 return (tpr & 0xf0) >> 4;
1512}
1513
1514void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
1515{
8d14695f 1516 u64 old_value = vcpu->arch.apic_base;
ad312c7c 1517 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 1518
1519 if (!apic) {
1520 value |= MSR_IA32_APICBASE_BSP;
ad312c7c 1521 vcpu->arch.apic_base = value;
97222cc8
ED		 1522 return;
1523 }
c5af89b6 1524
e66d2ae7
JK		 1525 vcpu->arch.apic_base = value;
1526
c5cc421b 1527 /* update jump label if enable bit changes */
0dce7cd6 1528 if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) {
c5cc421b
GN		 1529 if (value & MSR_IA32_APICBASE_ENABLE)
1530 static_key_slow_dec_deferred(&apic_hw_disabled);
1531 else
1532 static_key_slow_inc(&apic_hw_disabled.key);
1e08ec4a 1533 recalculate_apic_map(vcpu->kvm);
c5cc421b
GN		 1534 }
1535
8d14695f
YZ		 1536 if ((old_value ^ value) & X2APIC_ENABLE) {
1537 if (value & X2APIC_ENABLE) {
1538 u32 id = kvm_apic_id(apic);
1539 u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf));
1540 kvm_apic_set_ldr(apic, ldr);
1541 kvm_x86_ops->set_virtual_x2apic_mode(vcpu, true);
1542 } else
1543 kvm_x86_ops->set_virtual_x2apic_mode(vcpu, false);
0105d1a5 1544 }
8d14695f 1545
ad312c7c 1546 apic->base_address = apic->vcpu->arch.apic_base &
97222cc8
ED		 1547 MSR_IA32_APICBASE_BASE;
1548
db324fe6
NA		 1549 if ((value & MSR_IA32_APICBASE_ENABLE) &&
1550 apic->base_address != APIC_DEFAULT_PHYS_BASE)
1551 pr_warn_once("APIC base relocation is unsupported by KVM");
1552
97222cc8
ED		 1553 /* with FSB delivery interrupt, we can restart APIC functionality */
1554 apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
ad312c7c 1555 "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
97222cc8
ED		 1556
1557}
1558
c5ec1534 1559void kvm_lapic_reset(struct kvm_vcpu *vcpu)
97222cc8
ED		 1560{
1561 struct kvm_lapic *apic;
1562 int i;
1563
b8688d51 1564 apic_debug("%s\n", __func__);
97222cc8
ED		 1565
1566 ASSERT(vcpu);
ad312c7c 1567 apic = vcpu->arch.apic;
97222cc8
ED		 1568 ASSERT(apic != NULL);
1569
1570 /* Stop the timer in case it's a reset to an active apic */
d3c7b77d 1571 hrtimer_cancel(&apic->lapic_timer.timer);
97222cc8 1572
1e08ec4a 1573 kvm_apic_set_id(apic, vcpu->vcpu_id);
fc61b800 1574 kvm_apic_set_version(apic->vcpu);
97222cc8
ED		 1575
1576 for (i = 0; i < APIC_LVT_NUM; i++)
1577 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
a323b409 1578 apic->lapic_timer.timer_mode = 0;
40487c68
QH		 1579 apic_set_reg(apic, APIC_LVT0,
1580 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
97222cc8
ED		 1581
1582 apic_set_reg(apic, APIC_DFR, 0xffffffffU);
f8c1ea10 1583 apic_set_spiv(apic, 0xff);
97222cc8 1584 apic_set_reg(apic, APIC_TASKPRI, 0);
1e08ec4a 1585 kvm_apic_set_ldr(apic, 0);
97222cc8
ED		 1586 apic_set_reg(apic, APIC_ESR, 0);
1587 apic_set_reg(apic, APIC_ICR, 0);
1588 apic_set_reg(apic, APIC_ICR2, 0);
1589 apic_set_reg(apic, APIC_TDCR, 0);
1590 apic_set_reg(apic, APIC_TMICT, 0);
1591 for (i = 0; i < 8; i++) {
1592 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
1593 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
1594 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
1595 }
c7c9c56c 1596 apic->irr_pending = kvm_apic_vid_enabled(vcpu->kvm);
f563db4b 1597 apic->isr_count = kvm_x86_ops->hwapic_isr_update ? 1 : 0;
8680b94b 1598 apic->highest_isr_cache = -1;
b33ac88b 1599 update_divide_count(apic);
d3c7b77d 1600 atomic_set(&apic->lapic_timer.pending, 0);
c5af89b6 1601 if (kvm_vcpu_is_bsp(vcpu))
5dbc8f3f
GN		 1602 kvm_lapic_set_base(vcpu,
1603 vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP);
ae7a2a3f 1604 vcpu->arch.pv_eoi.msr_val = 0;
97222cc8
ED		 1605 apic_update_ppr(apic);
1606
e1035715 1607 vcpu->arch.apic_arb_prio = 0;
41383771 1608 vcpu->arch.apic_attention = 0;
e1035715 1609
98eff52a 1610 apic_debug("%s: vcpu=%p, id=%d, base_msr="
b8688d51 1611 "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
97222cc8 1612 vcpu, kvm_apic_id(apic),
ad312c7c 1613 vcpu->arch.apic_base, apic->base_address);
97222cc8
ED		 1614}
1615
97222cc8
ED		 1616/*
1617 *----------------------------------------------------------------------
1618 * timer interface
1619 *----------------------------------------------------------------------
1620 */
1b9778da 1621
2a6eac96 1622static bool lapic_is_periodic(struct kvm_lapic *apic)
97222cc8 1623{
d3c7b77d 1624 return apic_lvtt_period(apic);
97222cc8
ED		 1625}
1626
3d80840d
MT		 1627int apic_has_pending_timer(struct kvm_vcpu *vcpu)
1628{
54e9818f 1629 struct kvm_lapic *apic = vcpu->arch.apic;
3d80840d 1630
c48f1496 1631 if (kvm_vcpu_has_lapic(vcpu) && apic_enabled(apic) &&
54e9818f
GN		 1632 apic_lvt_enabled(apic, APIC_LVTT))
1633 return atomic_read(&apic->lapic_timer.pending);
3d80840d
MT		 1634
1635 return 0;
1636}
1637
89342082 1638int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1b9778da 1639{
c48f1496 1640 u32 reg = kvm_apic_get_reg(apic, lvt_type);
23930f95 1641 int vector, mode, trig_mode;
23930f95 1642
c48f1496 1643 if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
23930f95
JK		 1644 vector = reg & APIC_VECTOR_MASK;
1645 mode = reg & APIC_MODE_MASK;
1646 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
b4f2225c
YZ		 1647 return __apic_accept_irq(apic, mode, vector, 1, trig_mode,
1648 NULL);
23930f95
JK		 1649 }
1650 return 0;
1651}
1b9778da 1652
8fdb2351 1653void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
23930f95 1654{
8fdb2351
JK		 1655 struct kvm_lapic *apic = vcpu->arch.apic;
1656
1657 if (apic)
1658 kvm_apic_local_deliver(apic, APIC_LVT0);
1b9778da
ED		 1659}
1660
d76685c4
GH		 1661static const struct kvm_io_device_ops apic_mmio_ops = {
1662 .read = apic_mmio_read,
1663 .write = apic_mmio_write,
d76685c4
GH		 1664};
1665
e9d90d47
AK		 1666static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
1667{
1668 struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
2a6eac96 1669 struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
e9d90d47 1670
5d87db71 1671 apic_timer_expired(apic);
e9d90d47 1672
2a6eac96 1673 if (lapic_is_periodic(apic)) {
e9d90d47
AK		 1674 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
1675 return HRTIMER_RESTART;
1676 } else
1677 return HRTIMER_NORESTART;
1678}
1679
97222cc8
ED		 1680int kvm_create_lapic(struct kvm_vcpu *vcpu)
1681{
1682 struct kvm_lapic *apic;
1683
1684 ASSERT(vcpu != NULL);
1685 apic_debug("apic_init %d\n", vcpu->vcpu_id);
1686
1687 apic = kzalloc(sizeof(*apic), GFP_KERNEL);
1688 if (!apic)
1689 goto nomem;
1690
ad312c7c 1691 vcpu->arch.apic = apic;
97222cc8 1692
afc20184
TY		 1693 apic->regs = (void *)get_zeroed_page(GFP_KERNEL);
1694 if (!apic->regs) {
97222cc8
ED		 1695 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
1696 vcpu->vcpu_id);
d589444e 1697 goto nomem_free_apic;
97222cc8 1698 }
97222cc8
ED		 1699 apic->vcpu = vcpu;
1700
d3c7b77d
MT		 1701 hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
1702 HRTIMER_MODE_ABS);
e9d90d47 1703 apic->lapic_timer.timer.function = apic_timer_fn;
d3c7b77d 1704
c5cc421b
GN		 1705 /*
1706 * APIC is created enabled. This will prevent kvm_lapic_set_base from
1707 * thinking that APIC satet has changed.
1708 */
1709 vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
6aed64a8
GN		 1710 kvm_lapic_set_base(vcpu,
1711 APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE);
97222cc8 1712
f8c1ea10 1713 static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */
c5ec1534 1714 kvm_lapic_reset(vcpu);
d76685c4 1715 kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
97222cc8
ED		 1716
1717 return 0;
d589444e
RR		 1718nomem_free_apic:
1719 kfree(apic);
97222cc8 1720nomem:
97222cc8
ED		 1721 return -ENOMEM;
1722}
97222cc8
ED		 1723
1724int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1725{
ad312c7c 1726 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 1727 int highest_irr;
1728
c48f1496 1729 if (!kvm_vcpu_has_lapic(vcpu) || !apic_enabled(apic))
97222cc8
ED		 1730 return -1;
1731
6e5d865c 1732 apic_update_ppr(apic);
97222cc8
ED		 1733 highest_irr = apic_find_highest_irr(apic);
1734 if ((highest_irr == -1) ||
c48f1496 1735 ((highest_irr & 0xF0) <= kvm_apic_get_reg(apic, APIC_PROCPRI)))
97222cc8
ED		 1736 return -1;
1737 return highest_irr;
1738}
1739
40487c68
QH		 1740int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1741{
c48f1496 1742 u32 lvt0 = kvm_apic_get_reg(vcpu->arch.apic, APIC_LVT0);
40487c68
QH		 1743 int r = 0;
1744
c48f1496 1745 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
e7dca5c0
CL		 1746 r = 1;
1747 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1748 GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1749 r = 1;
40487c68
QH		 1750 return r;
1751}
1752
1b9778da
ED		 1753void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1754{
ad312c7c 1755 struct kvm_lapic *apic = vcpu->arch.apic;
1b9778da 1756
c48f1496 1757 if (!kvm_vcpu_has_lapic(vcpu))
54e9818f
GN		 1758 return;
1759
1760 if (atomic_read(&apic->lapic_timer.pending) > 0) {
f1ed0450 1761 kvm_apic_local_deliver(apic, APIC_LVTT);
fae0ba21
NA		 1762 if (apic_lvtt_tscdeadline(apic))
1763 apic->lapic_timer.tscdeadline = 0;
f1ed0450 1764 atomic_set(&apic->lapic_timer.pending, 0);
1b9778da
ED		 1765 }
1766}
1767
97222cc8
ED		 1768int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1769{
1770 int vector = kvm_apic_has_interrupt(vcpu);
ad312c7c 1771 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 1772
1773 if (vector == -1)
1774 return -1;
1775
56cc2406
WL		 1776 /*
1777 * We get here even with APIC virtualization enabled, if doing
1778 * nested virtualization and L1 runs with the "acknowledge interrupt
1779 * on exit" mode. Then we cannot inject the interrupt via RVI,
1780 * because the process would deliver it through the IDT.
1781 */
1782
8680b94b 1783 apic_set_isr(vector, apic);
97222cc8
ED		 1784 apic_update_ppr(apic);
1785 apic_clear_irr(vector, apic);
1786 return vector;
1787}
96ad2cc6 1788
64eb0620
GN		 1789void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu,
1790 struct kvm_lapic_state *s)
96ad2cc6 1791{
ad312c7c 1792 struct kvm_lapic *apic = vcpu->arch.apic;
96ad2cc6 1793
5dbc8f3f 1794 kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
64eb0620
GN		 1795 /* set SPIV separately to get count of SW disabled APICs right */
1796 apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
1797 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
1e08ec4a
GN		 1798 /* call kvm_apic_set_id() to put apic into apic_map */
1799 kvm_apic_set_id(apic, kvm_apic_id(apic));
fc61b800
GN		 1800 kvm_apic_set_version(vcpu);
1801
96ad2cc6 1802 apic_update_ppr(apic);
d3c7b77d 1803 hrtimer_cancel(&apic->lapic_timer.timer);
96ad2cc6
ED		 1804 update_divide_count(apic);
1805 start_apic_timer(apic);
6e24a6ef 1806 apic->irr_pending = true;
f563db4b 1807 apic->isr_count = kvm_x86_ops->hwapic_isr_update ?
c7c9c56c 1808 1 : count_vectors(apic->regs + APIC_ISR);
8680b94b 1809 apic->highest_isr_cache = -1;
4114c27d
WW		 1810 if (kvm_x86_ops->hwapic_irr_update)
1811 kvm_x86_ops->hwapic_irr_update(vcpu,
1812 apic_find_highest_irr(apic));
b4eef9b3
TC		 1813 if (unlikely(kvm_x86_ops->hwapic_isr_update))
1814 kvm_x86_ops->hwapic_isr_update(vcpu->kvm,
1815 apic_find_highest_isr(apic));
3842d135 1816 kvm_make_request(KVM_REQ_EVENT, vcpu);
10606919 1817 kvm_rtc_eoi_tracking_restore_one(vcpu);
96ad2cc6 1818}
a3d7f85f 1819
2f52d58c 1820void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
a3d7f85f 1821{
a3d7f85f
ED		 1822 struct hrtimer *timer;
1823
c48f1496 1824 if (!kvm_vcpu_has_lapic(vcpu))
a3d7f85f
ED		 1825 return;
1826
54e9818f 1827 timer = &vcpu->arch.apic->lapic_timer.timer;
a3d7f85f 1828 if (hrtimer_cancel(timer))
beb20d52 1829 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
a3d7f85f 1830}
b93463aa 1831
ae7a2a3f
MT		 1832/*
1833 * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
1834 *
1835 * Detect whether guest triggered PV EOI since the
1836 * last entry. If yes, set EOI on guests's behalf.
1837 * Clear PV EOI in guest memory in any case.
1838 */
1839static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
1840 struct kvm_lapic *apic)
1841{
1842 bool pending;
1843 int vector;
1844 /*
1845 * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
1846 * and KVM_PV_EOI_ENABLED in guest memory as follows:
1847 *
1848 * KVM_APIC_PV_EOI_PENDING is unset:
1849 * -> host disabled PV EOI.
1850 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
1851 * -> host enabled PV EOI, guest did not execute EOI yet.
1852 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
1853 * -> host enabled PV EOI, guest executed EOI.
1854 */
1855 BUG_ON(!pv_eoi_enabled(vcpu));
1856 pending = pv_eoi_get_pending(vcpu);
1857 /*
1858 * Clear pending bit in any case: it will be set again on vmentry.
1859 * While this might not be ideal from performance point of view,
1860 * this makes sure pv eoi is only enabled when we know it's safe.
1861 */
1862 pv_eoi_clr_pending(vcpu);
1863 if (pending)
1864 return;
1865 vector = apic_set_eoi(apic);
1866 trace_kvm_pv_eoi(apic, vector);
1867}
1868
b93463aa
AK		 1869void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1870{
1871 u32 data;
b93463aa 1872
ae7a2a3f
MT		 1873 if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
1874 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
1875
41383771 1876 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
b93463aa
AK		 1877 return;
1878
fda4e2e8
AH		 1879 kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
1880 sizeof(u32));
b93463aa
AK		 1881
1882 apic_set_tpr(vcpu->arch.apic, data & 0xff);
1883}
1884
ae7a2a3f
MT		 1885/*
1886 * apic_sync_pv_eoi_to_guest - called before vmentry
1887 *
1888 * Detect whether it's safe to enable PV EOI and
1889 * if yes do so.
1890 */
1891static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
1892 struct kvm_lapic *apic)
1893{
1894 if (!pv_eoi_enabled(vcpu) ||
1895 /* IRR set or many bits in ISR: could be nested. */
1896 apic->irr_pending ||
1897 /* Cache not set: could be safe but we don't bother. */
1898 apic->highest_isr_cache == -1 ||
1899 /* Need EOI to update ioapic. */
1900 kvm_ioapic_handles_vector(vcpu->kvm, apic->highest_isr_cache)) {
1901 /*
1902 * PV EOI was disabled by apic_sync_pv_eoi_from_guest
1903 * so we need not do anything here.
1904 */
1905 return;
1906 }
1907
1908 pv_eoi_set_pending(apic->vcpu);
1909}
1910
b93463aa
AK		 1911void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1912{
1913 u32 data, tpr;
1914 int max_irr, max_isr;
ae7a2a3f 1915 struct kvm_lapic *apic = vcpu->arch.apic;
b93463aa 1916
ae7a2a3f
MT		 1917 apic_sync_pv_eoi_to_guest(vcpu, apic);
1918
41383771 1919 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
b93463aa
AK		 1920 return;
1921
c48f1496 1922 tpr = kvm_apic_get_reg(apic, APIC_TASKPRI) & 0xff;
b93463aa
AK		 1923 max_irr = apic_find_highest_irr(apic);
1924 if (max_irr < 0)
1925 max_irr = 0;
1926 max_isr = apic_find_highest_isr(apic);
1927 if (max_isr < 0)
1928 max_isr = 0;
1929 data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1930
fda4e2e8
AH		 1931 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
1932 sizeof(u32));
b93463aa
AK		 1933}
1934
fda4e2e8 1935int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
b93463aa 1936{
fda4e2e8
AH		 1937 if (vapic_addr) {
1938 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
1939 &vcpu->arch.apic->vapic_cache,
1940 vapic_addr, sizeof(u32)))
1941 return -EINVAL;
41383771 1942 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
fda4e2e8 1943 } else {
41383771 1944 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
fda4e2e8
AH		 1945 }
1946
1947 vcpu->arch.apic->vapic_addr = vapic_addr;
1948 return 0;
b93463aa 1949}
0105d1a5
GN		 1950
1951int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1952{
1953 struct kvm_lapic *apic = vcpu->arch.apic;
1954 u32 reg = (msr - APIC_BASE_MSR) << 4;
1955
1956 if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1957 return 1;
1958
c69d3d9b
NA		 1959 if (reg == APIC_ICR2)
1960 return 1;
1961
0105d1a5 1962 /* if this is ICR write vector before command */
decdc283 1963 if (reg == APIC_ICR)
0105d1a5
GN		 1964 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1965 return apic_reg_write(apic, reg, (u32)data);
1966}
1967
1968int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
1969{
1970 struct kvm_lapic *apic = vcpu->arch.apic;
1971 u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
1972
1973 if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1974 return 1;
1975
c69d3d9b
NA		 1976 if (reg == APIC_DFR || reg == APIC_ICR2) {
1977 apic_debug("KVM_APIC_READ: read x2apic reserved register %x\n",
1978 reg);
1979 return 1;
1980 }
1981
0105d1a5
GN		 1982 if (apic_reg_read(apic, reg, 4, &low))
1983 return 1;
decdc283 1984 if (reg == APIC_ICR)
0105d1a5
GN		 1985 apic_reg_read(apic, APIC_ICR2, 4, &high);
1986
1987 *data = (((u64)high) << 32) | low;
1988
1989 return 0;
1990}
10388a07
GN		 1991
1992int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
1993{
1994 struct kvm_lapic *apic = vcpu->arch.apic;
1995
c48f1496 1996 if (!kvm_vcpu_has_lapic(vcpu))
10388a07
GN		 1997 return 1;
1998
1999 /* if this is ICR write vector before command */
2000 if (reg == APIC_ICR)
2001 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2002 return apic_reg_write(apic, reg, (u32)data);
2003}
2004
2005int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
2006{
2007 struct kvm_lapic *apic = vcpu->arch.apic;
2008 u32 low, high = 0;
2009
c48f1496 2010 if (!kvm_vcpu_has_lapic(vcpu))
10388a07
GN		 2011 return 1;
2012
2013 if (apic_reg_read(apic, reg, 4, &low))
2014 return 1;
2015 if (reg == APIC_ICR)
2016 apic_reg_read(apic, APIC_ICR2, 4, &high);
2017
2018 *data = (((u64)high) << 32) | low;
2019
2020 return 0;
2021}
ae7a2a3f
MT		 2022
2023int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data)
2024{
2025 u64 addr = data & ~KVM_MSR_ENABLED;
2026 if (!IS_ALIGNED(addr, 4))
2027 return 1;
2028
2029 vcpu->arch.pv_eoi.msr_val = data;
2030 if (!pv_eoi_enabled(vcpu))
2031 return 0;
2032 return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data,
8f964525 2033 addr, sizeof(u8));
ae7a2a3f 2034}
c5cc421b 2035
66450a21
JK		 2036void kvm_apic_accept_events(struct kvm_vcpu *vcpu)
2037{
2038 struct kvm_lapic *apic = vcpu->arch.apic;
2b4a273b 2039 u8 sipi_vector;
299018f4 2040 unsigned long pe;
66450a21 2041
299018f4 2042 if (!kvm_vcpu_has_lapic(vcpu) || !apic->pending_events)
66450a21
JK		 2043 return;
2044
299018f4
GN		 2045 pe = xchg(&apic->pending_events, 0);
2046
2047 if (test_bit(KVM_APIC_INIT, &pe)) {
66450a21
JK		 2048 kvm_lapic_reset(vcpu);
2049 kvm_vcpu_reset(vcpu);
2050 if (kvm_vcpu_is_bsp(apic->vcpu))
2051 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2052 else
2053 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
2054 }
299018f4 2055 if (test_bit(KVM_APIC_SIPI, &pe) &&
66450a21
JK		 2056 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
2057 /* evaluate pending_events before reading the vector */
2058 smp_rmb();
2059 sipi_vector = apic->sipi_vector;
98eff52a 2060 apic_debug("vcpu %d received sipi with vector # %x\n",
66450a21
JK		 2061 vcpu->vcpu_id, sipi_vector);
2062 kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector);
2063 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2064 }
2065}
2066
c5cc421b
GN		 2067void kvm_lapic_init(void)
2068{
2069 /* do not patch jump label more than once per second */
2070 jump_label_rate_limit(&apic_hw_disabled, HZ);
f8c1ea10 2071 jump_label_rate_limit(&apic_sw_disabled, HZ);
c5cc421b 2072}
Linux kernel - Deliverables
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