KVM: Route irq 0 to vcpu 0 exclusively
[deliverable/linux.git] / arch / x86 / kvm / mmu.c
CommitLineData
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1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * MMU support
8 *
9 * Copyright (C) 2006 Qumranet, Inc.
10 *
11 * Authors:
12 * Yaniv Kamay <yaniv@qumranet.com>
13 * Avi Kivity <avi@qumranet.com>
14 *
15 * This work is licensed under the terms of the GNU GPL, version 2. See
16 * the COPYING file in the top-level directory.
17 *
18 */
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19
20#include "vmx.h"
1d737c8a 21#include "mmu.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
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24#include <linux/types.h>
25#include <linux/string.h>
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26#include <linux/mm.h>
27#include <linux/highmem.h>
28#include <linux/module.h>
448353ca 29#include <linux/swap.h>
6aa8b732 30
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31#include <asm/page.h>
32#include <asm/cmpxchg.h>
4e542370 33#include <asm/io.h>
6aa8b732 34
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35#undef MMU_DEBUG
36
37#undef AUDIT
38
39#ifdef AUDIT
40static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg);
41#else
42static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg) {}
43#endif
44
45#ifdef MMU_DEBUG
46
47#define pgprintk(x...) do { if (dbg) printk(x); } while (0)
48#define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
49
50#else
51
52#define pgprintk(x...) do { } while (0)
53#define rmap_printk(x...) do { } while (0)
54
55#endif
56
57#if defined(MMU_DEBUG) || defined(AUDIT)
58static int dbg = 1;
59#endif
6aa8b732 60
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61#ifndef MMU_DEBUG
62#define ASSERT(x) do { } while (0)
63#else
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64#define ASSERT(x) \
65 if (!(x)) { \
66 printk(KERN_WARNING "assertion failed %s:%d: %s\n", \
67 __FILE__, __LINE__, #x); \
68 }
d6c69ee9 69#endif
6aa8b732 70
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71#define PT64_PT_BITS 9
72#define PT64_ENT_PER_PAGE (1 << PT64_PT_BITS)
73#define PT32_PT_BITS 10
74#define PT32_ENT_PER_PAGE (1 << PT32_PT_BITS)
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75
76#define PT_WRITABLE_SHIFT 1
77
78#define PT_PRESENT_MASK (1ULL << 0)
79#define PT_WRITABLE_MASK (1ULL << PT_WRITABLE_SHIFT)
80#define PT_USER_MASK (1ULL << 2)
81#define PT_PWT_MASK (1ULL << 3)
82#define PT_PCD_MASK (1ULL << 4)
83#define PT_ACCESSED_MASK (1ULL << 5)
84#define PT_DIRTY_MASK (1ULL << 6)
85#define PT_PAGE_SIZE_MASK (1ULL << 7)
86#define PT_PAT_MASK (1ULL << 7)
87#define PT_GLOBAL_MASK (1ULL << 8)
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88#define PT64_NX_SHIFT 63
89#define PT64_NX_MASK (1ULL << PT64_NX_SHIFT)
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90
91#define PT_PAT_SHIFT 7
92#define PT_DIR_PAT_SHIFT 12
93#define PT_DIR_PAT_MASK (1ULL << PT_DIR_PAT_SHIFT)
94
95#define PT32_DIR_PSE36_SIZE 4
96#define PT32_DIR_PSE36_SHIFT 13
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97#define PT32_DIR_PSE36_MASK \
98 (((1ULL << PT32_DIR_PSE36_SIZE) - 1) << PT32_DIR_PSE36_SHIFT)
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99
100
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101#define PT_FIRST_AVAIL_BITS_SHIFT 9
102#define PT64_SECOND_AVAIL_BITS_SHIFT 52
103
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104#define PT_SHADOW_IO_MARK (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
105
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106#define VALID_PAGE(x) ((x) != INVALID_PAGE)
107
108#define PT64_LEVEL_BITS 9
109
110#define PT64_LEVEL_SHIFT(level) \
d77c26fc 111 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
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112
113#define PT64_LEVEL_MASK(level) \
114 (((1ULL << PT64_LEVEL_BITS) - 1) << PT64_LEVEL_SHIFT(level))
115
116#define PT64_INDEX(address, level)\
117 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
118
119
120#define PT32_LEVEL_BITS 10
121
122#define PT32_LEVEL_SHIFT(level) \
d77c26fc 123 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
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124
125#define PT32_LEVEL_MASK(level) \
126 (((1ULL << PT32_LEVEL_BITS) - 1) << PT32_LEVEL_SHIFT(level))
127
128#define PT32_INDEX(address, level)\
129 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
130
131
27aba766 132#define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
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133#define PT64_DIR_BASE_ADDR_MASK \
134 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
135
136#define PT32_BASE_ADDR_MASK PAGE_MASK
137#define PT32_DIR_BASE_ADDR_MASK \
138 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
139
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140#define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \
141 | PT64_NX_MASK)
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142
143#define PFERR_PRESENT_MASK (1U << 0)
144#define PFERR_WRITE_MASK (1U << 1)
145#define PFERR_USER_MASK (1U << 2)
73b1087e 146#define PFERR_FETCH_MASK (1U << 4)
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147
148#define PT64_ROOT_LEVEL 4
149#define PT32_ROOT_LEVEL 2
150#define PT32E_ROOT_LEVEL 3
151
152#define PT_DIRECTORY_LEVEL 2
153#define PT_PAGE_TABLE_LEVEL 1
154
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155#define RMAP_EXT 4
156
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157#define ACC_EXEC_MASK 1
158#define ACC_WRITE_MASK PT_WRITABLE_MASK
159#define ACC_USER_MASK PT_USER_MASK
160#define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
161
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162struct kvm_rmap_desc {
163 u64 *shadow_ptes[RMAP_EXT];
164 struct kvm_rmap_desc *more;
165};
166
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167static struct kmem_cache *pte_chain_cache;
168static struct kmem_cache *rmap_desc_cache;
d3d25b04 169static struct kmem_cache *mmu_page_header_cache;
b5a33a75 170
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171static u64 __read_mostly shadow_trap_nonpresent_pte;
172static u64 __read_mostly shadow_notrap_nonpresent_pte;
173
174void kvm_mmu_set_nonpresent_ptes(u64 trap_pte, u64 notrap_pte)
175{
176 shadow_trap_nonpresent_pte = trap_pte;
177 shadow_notrap_nonpresent_pte = notrap_pte;
178}
179EXPORT_SYMBOL_GPL(kvm_mmu_set_nonpresent_ptes);
180
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181static int is_write_protection(struct kvm_vcpu *vcpu)
182{
ad312c7c 183 return vcpu->arch.cr0 & X86_CR0_WP;
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184}
185
186static int is_cpuid_PSE36(void)
187{
188 return 1;
189}
190
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191static int is_nx(struct kvm_vcpu *vcpu)
192{
ad312c7c 193 return vcpu->arch.shadow_efer & EFER_NX;
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194}
195
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196static int is_present_pte(unsigned long pte)
197{
198 return pte & PT_PRESENT_MASK;
199}
200
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201static int is_shadow_present_pte(u64 pte)
202{
203 pte &= ~PT_SHADOW_IO_MARK;
204 return pte != shadow_trap_nonpresent_pte
205 && pte != shadow_notrap_nonpresent_pte;
206}
207
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208static int is_writeble_pte(unsigned long pte)
209{
210 return pte & PT_WRITABLE_MASK;
211}
212
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213static int is_dirty_pte(unsigned long pte)
214{
215 return pte & PT_DIRTY_MASK;
216}
217
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218static int is_io_pte(unsigned long pte)
219{
220 return pte & PT_SHADOW_IO_MARK;
221}
222
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223static int is_rmap_pte(u64 pte)
224{
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225 return pte != shadow_trap_nonpresent_pte
226 && pte != shadow_notrap_nonpresent_pte;
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227}
228
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229static gfn_t pse36_gfn_delta(u32 gpte)
230{
231 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
232
233 return (gpte & PT32_DIR_PSE36_MASK) << shift;
234}
235
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236static void set_shadow_pte(u64 *sptep, u64 spte)
237{
238#ifdef CONFIG_X86_64
239 set_64bit((unsigned long *)sptep, spte);
240#else
241 set_64bit((unsigned long long *)sptep, spte);
242#endif
243}
244
e2dec939 245static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
2e3e5882 246 struct kmem_cache *base_cache, int min)
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247{
248 void *obj;
249
250 if (cache->nobjs >= min)
e2dec939 251 return 0;
714b93da 252 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
2e3e5882 253 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL);
714b93da 254 if (!obj)
e2dec939 255 return -ENOMEM;
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256 cache->objects[cache->nobjs++] = obj;
257 }
e2dec939 258 return 0;
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259}
260
261static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc)
262{
263 while (mc->nobjs)
264 kfree(mc->objects[--mc->nobjs]);
265}
266
c1158e63 267static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
2e3e5882 268 int min)
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269{
270 struct page *page;
271
272 if (cache->nobjs >= min)
273 return 0;
274 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
2e3e5882 275 page = alloc_page(GFP_KERNEL);
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276 if (!page)
277 return -ENOMEM;
278 set_page_private(page, 0);
279 cache->objects[cache->nobjs++] = page_address(page);
280 }
281 return 0;
282}
283
284static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
285{
286 while (mc->nobjs)
c4d198d5 287 free_page((unsigned long)mc->objects[--mc->nobjs]);
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288}
289
2e3e5882 290static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
714b93da 291{
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292 int r;
293
ad312c7c 294 r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_chain_cache,
2e3e5882 295 pte_chain_cache, 4);
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296 if (r)
297 goto out;
ad312c7c 298 r = mmu_topup_memory_cache(&vcpu->arch.mmu_rmap_desc_cache,
2e3e5882 299 rmap_desc_cache, 1);
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300 if (r)
301 goto out;
ad312c7c 302 r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
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303 if (r)
304 goto out;
ad312c7c 305 r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
2e3e5882 306 mmu_page_header_cache, 4);
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307out:
308 return r;
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309}
310
311static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
312{
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313 mmu_free_memory_cache(&vcpu->arch.mmu_pte_chain_cache);
314 mmu_free_memory_cache(&vcpu->arch.mmu_rmap_desc_cache);
315 mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
316 mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache);
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317}
318
319static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc,
320 size_t size)
321{
322 void *p;
323
324 BUG_ON(!mc->nobjs);
325 p = mc->objects[--mc->nobjs];
326 memset(p, 0, size);
327 return p;
328}
329
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330static struct kvm_pte_chain *mmu_alloc_pte_chain(struct kvm_vcpu *vcpu)
331{
ad312c7c 332 return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_chain_cache,
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333 sizeof(struct kvm_pte_chain));
334}
335
90cb0529 336static void mmu_free_pte_chain(struct kvm_pte_chain *pc)
714b93da 337{
90cb0529 338 kfree(pc);
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339}
340
341static struct kvm_rmap_desc *mmu_alloc_rmap_desc(struct kvm_vcpu *vcpu)
342{
ad312c7c 343 return mmu_memory_cache_alloc(&vcpu->arch.mmu_rmap_desc_cache,
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344 sizeof(struct kvm_rmap_desc));
345}
346
90cb0529 347static void mmu_free_rmap_desc(struct kvm_rmap_desc *rd)
714b93da 348{
90cb0529 349 kfree(rd);
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350}
351
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352/*
353 * Take gfn and return the reverse mapping to it.
354 * Note: gfn must be unaliased before this function get called
355 */
356
357static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn)
358{
359 struct kvm_memory_slot *slot;
360
361 slot = gfn_to_memslot(kvm, gfn);
362 return &slot->rmap[gfn - slot->base_gfn];
363}
364
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365/*
366 * Reverse mapping data structures:
367 *
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368 * If rmapp bit zero is zero, then rmapp point to the shadw page table entry
369 * that points to page_address(page).
cd4a4e53 370 *
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371 * If rmapp bit zero is one, (then rmap & ~1) points to a struct kvm_rmap_desc
372 * containing more mappings.
cd4a4e53 373 */
290fc38d 374static void rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
cd4a4e53 375{
4db35314 376 struct kvm_mmu_page *sp;
cd4a4e53 377 struct kvm_rmap_desc *desc;
290fc38d 378 unsigned long *rmapp;
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379 int i;
380
381 if (!is_rmap_pte(*spte))
382 return;
290fc38d 383 gfn = unalias_gfn(vcpu->kvm, gfn);
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384 sp = page_header(__pa(spte));
385 sp->gfns[spte - sp->spt] = gfn;
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386 rmapp = gfn_to_rmap(vcpu->kvm, gfn);
387 if (!*rmapp) {
cd4a4e53 388 rmap_printk("rmap_add: %p %llx 0->1\n", spte, *spte);
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389 *rmapp = (unsigned long)spte;
390 } else if (!(*rmapp & 1)) {
cd4a4e53 391 rmap_printk("rmap_add: %p %llx 1->many\n", spte, *spte);
714b93da 392 desc = mmu_alloc_rmap_desc(vcpu);
290fc38d 393 desc->shadow_ptes[0] = (u64 *)*rmapp;
cd4a4e53 394 desc->shadow_ptes[1] = spte;
290fc38d 395 *rmapp = (unsigned long)desc | 1;
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396 } else {
397 rmap_printk("rmap_add: %p %llx many->many\n", spte, *spte);
290fc38d 398 desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
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399 while (desc->shadow_ptes[RMAP_EXT-1] && desc->more)
400 desc = desc->more;
401 if (desc->shadow_ptes[RMAP_EXT-1]) {
714b93da 402 desc->more = mmu_alloc_rmap_desc(vcpu);
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403 desc = desc->more;
404 }
405 for (i = 0; desc->shadow_ptes[i]; ++i)
406 ;
407 desc->shadow_ptes[i] = spte;
408 }
409}
410
290fc38d 411static void rmap_desc_remove_entry(unsigned long *rmapp,
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412 struct kvm_rmap_desc *desc,
413 int i,
414 struct kvm_rmap_desc *prev_desc)
415{
416 int j;
417
418 for (j = RMAP_EXT - 1; !desc->shadow_ptes[j] && j > i; --j)
419 ;
420 desc->shadow_ptes[i] = desc->shadow_ptes[j];
11718b4d 421 desc->shadow_ptes[j] = NULL;
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422 if (j != 0)
423 return;
424 if (!prev_desc && !desc->more)
290fc38d 425 *rmapp = (unsigned long)desc->shadow_ptes[0];
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426 else
427 if (prev_desc)
428 prev_desc->more = desc->more;
429 else
290fc38d 430 *rmapp = (unsigned long)desc->more | 1;
90cb0529 431 mmu_free_rmap_desc(desc);
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432}
433
290fc38d 434static void rmap_remove(struct kvm *kvm, u64 *spte)
cd4a4e53 435{
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436 struct kvm_rmap_desc *desc;
437 struct kvm_rmap_desc *prev_desc;
4db35314 438 struct kvm_mmu_page *sp;
76c35c6e 439 struct page *page;
290fc38d 440 unsigned long *rmapp;
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441 int i;
442
443 if (!is_rmap_pte(*spte))
444 return;
4db35314 445 sp = page_header(__pa(spte));
76c35c6e 446 page = pfn_to_page((*spte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT);
448353ca 447 mark_page_accessed(page);
b4231d61 448 if (is_writeble_pte(*spte))
76c35c6e 449 kvm_release_page_dirty(page);
b4231d61 450 else
76c35c6e 451 kvm_release_page_clean(page);
4db35314 452 rmapp = gfn_to_rmap(kvm, sp->gfns[spte - sp->spt]);
290fc38d 453 if (!*rmapp) {
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454 printk(KERN_ERR "rmap_remove: %p %llx 0->BUG\n", spte, *spte);
455 BUG();
290fc38d 456 } else if (!(*rmapp & 1)) {
cd4a4e53 457 rmap_printk("rmap_remove: %p %llx 1->0\n", spte, *spte);
290fc38d 458 if ((u64 *)*rmapp != spte) {
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459 printk(KERN_ERR "rmap_remove: %p %llx 1->BUG\n",
460 spte, *spte);
461 BUG();
462 }
290fc38d 463 *rmapp = 0;
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464 } else {
465 rmap_printk("rmap_remove: %p %llx many->many\n", spte, *spte);
290fc38d 466 desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
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467 prev_desc = NULL;
468 while (desc) {
469 for (i = 0; i < RMAP_EXT && desc->shadow_ptes[i]; ++i)
470 if (desc->shadow_ptes[i] == spte) {
290fc38d 471 rmap_desc_remove_entry(rmapp,
714b93da 472 desc, i,
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473 prev_desc);
474 return;
475 }
476 prev_desc = desc;
477 desc = desc->more;
478 }
479 BUG();
480 }
481}
482
98348e95 483static u64 *rmap_next(struct kvm *kvm, unsigned long *rmapp, u64 *spte)
374cbac0 484{
374cbac0 485 struct kvm_rmap_desc *desc;
98348e95
IE
486 struct kvm_rmap_desc *prev_desc;
487 u64 *prev_spte;
488 int i;
489
490 if (!*rmapp)
491 return NULL;
492 else if (!(*rmapp & 1)) {
493 if (!spte)
494 return (u64 *)*rmapp;
495 return NULL;
496 }
497 desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
498 prev_desc = NULL;
499 prev_spte = NULL;
500 while (desc) {
501 for (i = 0; i < RMAP_EXT && desc->shadow_ptes[i]; ++i) {
502 if (prev_spte == spte)
503 return desc->shadow_ptes[i];
504 prev_spte = desc->shadow_ptes[i];
505 }
506 desc = desc->more;
507 }
508 return NULL;
509}
510
511static void rmap_write_protect(struct kvm *kvm, u64 gfn)
512{
290fc38d 513 unsigned long *rmapp;
374cbac0 514 u64 *spte;
caa5b8a5 515 int write_protected = 0;
374cbac0 516
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517 gfn = unalias_gfn(kvm, gfn);
518 rmapp = gfn_to_rmap(kvm, gfn);
374cbac0 519
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520 spte = rmap_next(kvm, rmapp, NULL);
521 while (spte) {
374cbac0 522 BUG_ON(!spte);
374cbac0 523 BUG_ON(!(*spte & PT_PRESENT_MASK));
374cbac0 524 rmap_printk("rmap_write_protect: spte %p %llx\n", spte, *spte);
caa5b8a5 525 if (is_writeble_pte(*spte)) {
9647c14c 526 set_shadow_pte(spte, *spte & ~PT_WRITABLE_MASK);
caa5b8a5
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527 write_protected = 1;
528 }
9647c14c 529 spte = rmap_next(kvm, rmapp, spte);
374cbac0 530 }
caa5b8a5
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531 if (write_protected)
532 kvm_flush_remote_tlbs(kvm);
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533}
534
d6c69ee9 535#ifdef MMU_DEBUG
47ad8e68 536static int is_empty_shadow_page(u64 *spt)
6aa8b732 537{
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538 u64 *pos;
539 u64 *end;
540
47ad8e68 541 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
c7addb90 542 if ((*pos & ~PT_SHADOW_IO_MARK) != shadow_trap_nonpresent_pte) {
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543 printk(KERN_ERR "%s: %p %llx\n", __FUNCTION__,
544 pos, *pos);
6aa8b732 545 return 0;
139bdb2d 546 }
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547 return 1;
548}
d6c69ee9 549#endif
6aa8b732 550
4db35314 551static void kvm_mmu_free_page(struct kvm *kvm, struct kvm_mmu_page *sp)
260746c0 552{
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553 ASSERT(is_empty_shadow_page(sp->spt));
554 list_del(&sp->link);
555 __free_page(virt_to_page(sp->spt));
556 __free_page(virt_to_page(sp->gfns));
557 kfree(sp);
f05e70ac 558 ++kvm->arch.n_free_mmu_pages;
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559}
560
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561static unsigned kvm_page_table_hashfn(gfn_t gfn)
562{
563 return gfn;
564}
565
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566static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu,
567 u64 *parent_pte)
6aa8b732 568{
4db35314 569 struct kvm_mmu_page *sp;
6aa8b732 570
ad312c7c
ZX
571 sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache, sizeof *sp);
572 sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE);
573 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE);
4db35314 574 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
f05e70ac 575 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
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576 ASSERT(is_empty_shadow_page(sp->spt));
577 sp->slot_bitmap = 0;
578 sp->multimapped = 0;
579 sp->parent_pte = parent_pte;
f05e70ac 580 --vcpu->kvm->arch.n_free_mmu_pages;
4db35314 581 return sp;
6aa8b732
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582}
583
714b93da 584static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
4db35314 585 struct kvm_mmu_page *sp, u64 *parent_pte)
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586{
587 struct kvm_pte_chain *pte_chain;
588 struct hlist_node *node;
589 int i;
590
591 if (!parent_pte)
592 return;
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593 if (!sp->multimapped) {
594 u64 *old = sp->parent_pte;
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595
596 if (!old) {
4db35314 597 sp->parent_pte = parent_pte;
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598 return;
599 }
4db35314 600 sp->multimapped = 1;
714b93da 601 pte_chain = mmu_alloc_pte_chain(vcpu);
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602 INIT_HLIST_HEAD(&sp->parent_ptes);
603 hlist_add_head(&pte_chain->link, &sp->parent_ptes);
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604 pte_chain->parent_ptes[0] = old;
605 }
4db35314 606 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link) {
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607 if (pte_chain->parent_ptes[NR_PTE_CHAIN_ENTRIES-1])
608 continue;
609 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i)
610 if (!pte_chain->parent_ptes[i]) {
611 pte_chain->parent_ptes[i] = parent_pte;
612 return;
613 }
614 }
714b93da 615 pte_chain = mmu_alloc_pte_chain(vcpu);
cea0f0e7 616 BUG_ON(!pte_chain);
4db35314 617 hlist_add_head(&pte_chain->link, &sp->parent_ptes);
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618 pte_chain->parent_ptes[0] = parent_pte;
619}
620
4db35314 621static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
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622 u64 *parent_pte)
623{
624 struct kvm_pte_chain *pte_chain;
625 struct hlist_node *node;
626 int i;
627
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628 if (!sp->multimapped) {
629 BUG_ON(sp->parent_pte != parent_pte);
630 sp->parent_pte = NULL;
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631 return;
632 }
4db35314 633 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link)
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634 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) {
635 if (!pte_chain->parent_ptes[i])
636 break;
637 if (pte_chain->parent_ptes[i] != parent_pte)
638 continue;
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639 while (i + 1 < NR_PTE_CHAIN_ENTRIES
640 && pte_chain->parent_ptes[i + 1]) {
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641 pte_chain->parent_ptes[i]
642 = pte_chain->parent_ptes[i + 1];
643 ++i;
644 }
645 pte_chain->parent_ptes[i] = NULL;
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646 if (i == 0) {
647 hlist_del(&pte_chain->link);
90cb0529 648 mmu_free_pte_chain(pte_chain);
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649 if (hlist_empty(&sp->parent_ptes)) {
650 sp->multimapped = 0;
651 sp->parent_pte = NULL;
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652 }
653 }
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654 return;
655 }
656 BUG();
657}
658
4db35314 659static struct kvm_mmu_page *kvm_mmu_lookup_page(struct kvm *kvm, gfn_t gfn)
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660{
661 unsigned index;
662 struct hlist_head *bucket;
4db35314 663 struct kvm_mmu_page *sp;
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664 struct hlist_node *node;
665
666 pgprintk("%s: looking for gfn %lx\n", __FUNCTION__, gfn);
667 index = kvm_page_table_hashfn(gfn) % KVM_NUM_MMU_PAGES;
f05e70ac 668 bucket = &kvm->arch.mmu_page_hash[index];
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669 hlist_for_each_entry(sp, node, bucket, hash_link)
670 if (sp->gfn == gfn && !sp->role.metaphysical) {
cea0f0e7 671 pgprintk("%s: found role %x\n",
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672 __FUNCTION__, sp->role.word);
673 return sp;
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674 }
675 return NULL;
676}
677
678static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
679 gfn_t gfn,
680 gva_t gaddr,
681 unsigned level,
682 int metaphysical,
41074d07 683 unsigned access,
7819026e
MT
684 u64 *parent_pte,
685 bool *new_page)
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686{
687 union kvm_mmu_page_role role;
688 unsigned index;
689 unsigned quadrant;
690 struct hlist_head *bucket;
4db35314 691 struct kvm_mmu_page *sp;
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692 struct hlist_node *node;
693
694 role.word = 0;
ad312c7c 695 role.glevels = vcpu->arch.mmu.root_level;
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696 role.level = level;
697 role.metaphysical = metaphysical;
41074d07 698 role.access = access;
ad312c7c 699 if (vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) {
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700 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
701 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
702 role.quadrant = quadrant;
703 }
704 pgprintk("%s: looking gfn %lx role %x\n", __FUNCTION__,
705 gfn, role.word);
706 index = kvm_page_table_hashfn(gfn) % KVM_NUM_MMU_PAGES;
f05e70ac 707 bucket = &vcpu->kvm->arch.mmu_page_hash[index];
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708 hlist_for_each_entry(sp, node, bucket, hash_link)
709 if (sp->gfn == gfn && sp->role.word == role.word) {
710 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
cea0f0e7 711 pgprintk("%s: found\n", __FUNCTION__);
4db35314 712 return sp;
cea0f0e7 713 }
dfc5aa00 714 ++vcpu->kvm->stat.mmu_cache_miss;
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715 sp = kvm_mmu_alloc_page(vcpu, parent_pte);
716 if (!sp)
717 return sp;
cea0f0e7 718 pgprintk("%s: adding gfn %lx role %x\n", __FUNCTION__, gfn, role.word);
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719 sp->gfn = gfn;
720 sp->role = role;
721 hlist_add_head(&sp->hash_link, bucket);
ad312c7c 722 vcpu->arch.mmu.prefetch_page(vcpu, sp);
374cbac0 723 if (!metaphysical)
4a4c9924 724 rmap_write_protect(vcpu->kvm, gfn);
7819026e
MT
725 if (new_page)
726 *new_page = 1;
4db35314 727 return sp;
cea0f0e7
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728}
729
90cb0529 730static void kvm_mmu_page_unlink_children(struct kvm *kvm,
4db35314 731 struct kvm_mmu_page *sp)
a436036b 732{
697fe2e2
AK
733 unsigned i;
734 u64 *pt;
735 u64 ent;
736
4db35314 737 pt = sp->spt;
697fe2e2 738
4db35314 739 if (sp->role.level == PT_PAGE_TABLE_LEVEL) {
697fe2e2 740 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
c7addb90 741 if (is_shadow_present_pte(pt[i]))
290fc38d 742 rmap_remove(kvm, &pt[i]);
c7addb90 743 pt[i] = shadow_trap_nonpresent_pte;
697fe2e2 744 }
90cb0529 745 kvm_flush_remote_tlbs(kvm);
697fe2e2
AK
746 return;
747 }
748
749 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
750 ent = pt[i];
751
c7addb90
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752 pt[i] = shadow_trap_nonpresent_pte;
753 if (!is_shadow_present_pte(ent))
697fe2e2
AK
754 continue;
755 ent &= PT64_BASE_ADDR_MASK;
90cb0529 756 mmu_page_remove_parent_pte(page_header(ent), &pt[i]);
697fe2e2 757 }
90cb0529 758 kvm_flush_remote_tlbs(kvm);
a436036b
AK
759}
760
4db35314 761static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte)
cea0f0e7 762{
4db35314 763 mmu_page_remove_parent_pte(sp, parent_pte);
a436036b
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764}
765
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766static void kvm_mmu_reset_last_pte_updated(struct kvm *kvm)
767{
768 int i;
769
770 for (i = 0; i < KVM_MAX_VCPUS; ++i)
771 if (kvm->vcpus[i])
ad312c7c 772 kvm->vcpus[i]->arch.last_pte_updated = NULL;
12b7d28f
AK
773}
774
4db35314 775static void kvm_mmu_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp)
a436036b
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776{
777 u64 *parent_pte;
778
4cee5764 779 ++kvm->stat.mmu_shadow_zapped;
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780 while (sp->multimapped || sp->parent_pte) {
781 if (!sp->multimapped)
782 parent_pte = sp->parent_pte;
a436036b
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783 else {
784 struct kvm_pte_chain *chain;
785
4db35314 786 chain = container_of(sp->parent_ptes.first,
a436036b
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787 struct kvm_pte_chain, link);
788 parent_pte = chain->parent_ptes[0];
789 }
697fe2e2 790 BUG_ON(!parent_pte);
4db35314 791 kvm_mmu_put_page(sp, parent_pte);
c7addb90 792 set_shadow_pte(parent_pte, shadow_trap_nonpresent_pte);
a436036b 793 }
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794 kvm_mmu_page_unlink_children(kvm, sp);
795 if (!sp->root_count) {
796 hlist_del(&sp->hash_link);
797 kvm_mmu_free_page(kvm, sp);
36868f7b 798 } else
f05e70ac 799 list_move(&sp->link, &kvm->arch.active_mmu_pages);
12b7d28f 800 kvm_mmu_reset_last_pte_updated(kvm);
a436036b
AK
801}
802
82ce2c96
IE
803/*
804 * Changing the number of mmu pages allocated to the vm
805 * Note: if kvm_nr_mmu_pages is too small, you will get dead lock
806 */
807void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int kvm_nr_mmu_pages)
808{
809 /*
810 * If we set the number of mmu pages to be smaller be than the
811 * number of actived pages , we must to free some mmu pages before we
812 * change the value
813 */
814
f05e70ac 815 if ((kvm->arch.n_alloc_mmu_pages - kvm->arch.n_free_mmu_pages) >
82ce2c96 816 kvm_nr_mmu_pages) {
f05e70ac
ZX
817 int n_used_mmu_pages = kvm->arch.n_alloc_mmu_pages
818 - kvm->arch.n_free_mmu_pages;
82ce2c96
IE
819
820 while (n_used_mmu_pages > kvm_nr_mmu_pages) {
821 struct kvm_mmu_page *page;
822
f05e70ac 823 page = container_of(kvm->arch.active_mmu_pages.prev,
82ce2c96
IE
824 struct kvm_mmu_page, link);
825 kvm_mmu_zap_page(kvm, page);
826 n_used_mmu_pages--;
827 }
f05e70ac 828 kvm->arch.n_free_mmu_pages = 0;
82ce2c96
IE
829 }
830 else
f05e70ac
ZX
831 kvm->arch.n_free_mmu_pages += kvm_nr_mmu_pages
832 - kvm->arch.n_alloc_mmu_pages;
82ce2c96 833
f05e70ac 834 kvm->arch.n_alloc_mmu_pages = kvm_nr_mmu_pages;
82ce2c96
IE
835}
836
f67a46f4 837static int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
a436036b
AK
838{
839 unsigned index;
840 struct hlist_head *bucket;
4db35314 841 struct kvm_mmu_page *sp;
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842 struct hlist_node *node, *n;
843 int r;
844
845 pgprintk("%s: looking for gfn %lx\n", __FUNCTION__, gfn);
846 r = 0;
847 index = kvm_page_table_hashfn(gfn) % KVM_NUM_MMU_PAGES;
f05e70ac 848 bucket = &kvm->arch.mmu_page_hash[index];
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849 hlist_for_each_entry_safe(sp, node, n, bucket, hash_link)
850 if (sp->gfn == gfn && !sp->role.metaphysical) {
697fe2e2 851 pgprintk("%s: gfn %lx role %x\n", __FUNCTION__, gfn,
4db35314
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852 sp->role.word);
853 kvm_mmu_zap_page(kvm, sp);
a436036b
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854 r = 1;
855 }
856 return r;
cea0f0e7
AK
857}
858
f67a46f4 859static void mmu_unshadow(struct kvm *kvm, gfn_t gfn)
97a0a01e 860{
4db35314 861 struct kvm_mmu_page *sp;
97a0a01e 862
4db35314
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863 while ((sp = kvm_mmu_lookup_page(kvm, gfn)) != NULL) {
864 pgprintk("%s: zap %lx %x\n", __FUNCTION__, gfn, sp->role.word);
865 kvm_mmu_zap_page(kvm, sp);
97a0a01e
AK
866 }
867}
868
38c335f1 869static void page_header_update_slot(struct kvm *kvm, void *pte, gfn_t gfn)
6aa8b732 870{
38c335f1 871 int slot = memslot_id(kvm, gfn_to_memslot(kvm, gfn));
4db35314 872 struct kvm_mmu_page *sp = page_header(__pa(pte));
6aa8b732 873
4db35314 874 __set_bit(slot, &sp->slot_bitmap);
6aa8b732
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875}
876
039576c0
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877struct page *gva_to_page(struct kvm_vcpu *vcpu, gva_t gva)
878{
72dc67a6
IE
879 struct page *page;
880
ad312c7c 881 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gva);
039576c0
AK
882
883 if (gpa == UNMAPPED_GVA)
884 return NULL;
72dc67a6
IE
885
886 down_read(&current->mm->mmap_sem);
887 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
888 up_read(&current->mm->mmap_sem);
889
890 return page;
039576c0
AK
891}
892
1c4f1fd6
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893static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *shadow_pte,
894 unsigned pt_access, unsigned pte_access,
895 int user_fault, int write_fault, int dirty,
d7824fff 896 int *ptwrite, gfn_t gfn, struct page *page)
1c4f1fd6
AK
897{
898 u64 spte;
899 int was_rmapped = is_rmap_pte(*shadow_pte);
75e68e60 900 int was_writeble = is_writeble_pte(*shadow_pte);
1c4f1fd6 901
bc750ba8 902 pgprintk("%s: spte %llx access %x write_fault %d"
1c4f1fd6 903 " user_fault %d gfn %lx\n",
bc750ba8 904 __FUNCTION__, *shadow_pte, pt_access,
1c4f1fd6
AK
905 write_fault, user_fault, gfn);
906
907 /*
908 * We don't set the accessed bit, since we sometimes want to see
909 * whether the guest actually used the pte (in order to detect
910 * demand paging).
911 */
912 spte = PT_PRESENT_MASK | PT_DIRTY_MASK;
913 if (!dirty)
914 pte_access &= ~ACC_WRITE_MASK;
915 if (!(pte_access & ACC_EXEC_MASK))
916 spte |= PT64_NX_MASK;
917
1c4f1fd6
AK
918 spte |= PT_PRESENT_MASK;
919 if (pte_access & ACC_USER_MASK)
920 spte |= PT_USER_MASK;
921
922 if (is_error_page(page)) {
923 set_shadow_pte(shadow_pte,
924 shadow_trap_nonpresent_pte | PT_SHADOW_IO_MARK);
925 kvm_release_page_clean(page);
926 return;
927 }
928
929 spte |= page_to_phys(page);
930
931 if ((pte_access & ACC_WRITE_MASK)
932 || (write_fault && !is_write_protection(vcpu) && !user_fault)) {
933 struct kvm_mmu_page *shadow;
934
935 spte |= PT_WRITABLE_MASK;
936 if (user_fault) {
937 mmu_unshadow(vcpu->kvm, gfn);
938 goto unshadowed;
939 }
940
941 shadow = kvm_mmu_lookup_page(vcpu->kvm, gfn);
942 if (shadow) {
943 pgprintk("%s: found shadow page for %lx, marking ro\n",
944 __FUNCTION__, gfn);
945 pte_access &= ~ACC_WRITE_MASK;
946 if (is_writeble_pte(spte)) {
947 spte &= ~PT_WRITABLE_MASK;
948 kvm_x86_ops->tlb_flush(vcpu);
949 }
950 if (write_fault)
951 *ptwrite = 1;
952 }
953 }
954
955unshadowed:
956
957 if (pte_access & ACC_WRITE_MASK)
958 mark_page_dirty(vcpu->kvm, gfn);
959
960 pgprintk("%s: setting spte %llx\n", __FUNCTION__, spte);
961 set_shadow_pte(shadow_pte, spte);
962 page_header_update_slot(vcpu->kvm, shadow_pte, gfn);
963 if (!was_rmapped) {
964 rmap_add(vcpu, shadow_pte, gfn);
965 if (!is_rmap_pte(*shadow_pte))
966 kvm_release_page_clean(page);
75e68e60
IE
967 } else {
968 if (was_writeble)
969 kvm_release_page_dirty(page);
970 else
971 kvm_release_page_clean(page);
1c4f1fd6 972 }
1c4f1fd6 973 if (!ptwrite || !*ptwrite)
ad312c7c 974 vcpu->arch.last_pte_updated = shadow_pte;
1c4f1fd6
AK
975}
976
6aa8b732
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977static void nonpaging_new_cr3(struct kvm_vcpu *vcpu)
978{
979}
980
aaee2c94
MT
981static int __nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write,
982 gfn_t gfn, struct page *page)
6aa8b732
AK
983{
984 int level = PT32E_ROOT_LEVEL;
ad312c7c 985 hpa_t table_addr = vcpu->arch.mmu.root_hpa;
e833240f 986 int pt_write = 0;
6aa8b732
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987
988 for (; ; level--) {
989 u32 index = PT64_INDEX(v, level);
990 u64 *table;
991
992 ASSERT(VALID_PAGE(table_addr));
993 table = __va(table_addr);
994
995 if (level == 1) {
e833240f 996 mmu_set_spte(vcpu, &table[index], ACC_ALL, ACC_ALL,
d7824fff 997 0, write, 1, &pt_write, gfn, page);
e833240f 998 return pt_write || is_io_pte(table[index]);
6aa8b732
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999 }
1000
c7addb90 1001 if (table[index] == shadow_trap_nonpresent_pte) {
25c0de2c 1002 struct kvm_mmu_page *new_table;
cea0f0e7 1003 gfn_t pseudo_gfn;
6aa8b732 1004
cea0f0e7
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1005 pseudo_gfn = (v & PT64_DIR_BASE_ADDR_MASK)
1006 >> PAGE_SHIFT;
1007 new_table = kvm_mmu_get_page(vcpu, pseudo_gfn,
1008 v, level - 1,
7819026e
MT
1009 1, ACC_ALL, &table[index],
1010 NULL);
25c0de2c 1011 if (!new_table) {
6aa8b732 1012 pgprintk("nonpaging_map: ENOMEM\n");
d7824fff 1013 kvm_release_page_clean(page);
6aa8b732
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1014 return -ENOMEM;
1015 }
1016
47ad8e68 1017 table[index] = __pa(new_table->spt) | PT_PRESENT_MASK
25c0de2c 1018 | PT_WRITABLE_MASK | PT_USER_MASK;
6aa8b732
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1019 }
1020 table_addr = table[index] & PT64_BASE_ADDR_MASK;
1021 }
1022}
1023
10589a46
MT
1024static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write, gfn_t gfn)
1025{
1026 int r;
1027
aaee2c94
MT
1028 struct page *page;
1029
72dc67a6
IE
1030 down_read(&vcpu->kvm->slots_lock);
1031
aaee2c94
MT
1032 down_read(&current->mm->mmap_sem);
1033 page = gfn_to_page(vcpu->kvm, gfn);
72dc67a6 1034 up_read(&current->mm->mmap_sem);
aaee2c94
MT
1035
1036 spin_lock(&vcpu->kvm->mmu_lock);
eb787d10 1037 kvm_mmu_free_some_pages(vcpu);
aaee2c94
MT
1038 r = __nonpaging_map(vcpu, v, write, gfn, page);
1039 spin_unlock(&vcpu->kvm->mmu_lock);
1040
72dc67a6 1041 up_read(&vcpu->kvm->slots_lock);
aaee2c94 1042
10589a46
MT
1043 return r;
1044}
1045
1046
c7addb90
AK
1047static void nonpaging_prefetch_page(struct kvm_vcpu *vcpu,
1048 struct kvm_mmu_page *sp)
1049{
1050 int i;
1051
1052 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
1053 sp->spt[i] = shadow_trap_nonpresent_pte;
1054}
1055
17ac10ad
AK
1056static void mmu_free_roots(struct kvm_vcpu *vcpu)
1057{
1058 int i;
4db35314 1059 struct kvm_mmu_page *sp;
17ac10ad 1060
ad312c7c 1061 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
7b53aa56 1062 return;
aaee2c94 1063 spin_lock(&vcpu->kvm->mmu_lock);
17ac10ad 1064#ifdef CONFIG_X86_64
ad312c7c
ZX
1065 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
1066 hpa_t root = vcpu->arch.mmu.root_hpa;
17ac10ad 1067
4db35314
AK
1068 sp = page_header(root);
1069 --sp->root_count;
ad312c7c 1070 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
aaee2c94 1071 spin_unlock(&vcpu->kvm->mmu_lock);
17ac10ad
AK
1072 return;
1073 }
1074#endif
1075 for (i = 0; i < 4; ++i) {
ad312c7c 1076 hpa_t root = vcpu->arch.mmu.pae_root[i];
17ac10ad 1077
417726a3 1078 if (root) {
417726a3 1079 root &= PT64_BASE_ADDR_MASK;
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AK
1080 sp = page_header(root);
1081 --sp->root_count;
417726a3 1082 }
ad312c7c 1083 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
17ac10ad 1084 }
aaee2c94 1085 spin_unlock(&vcpu->kvm->mmu_lock);
ad312c7c 1086 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
17ac10ad
AK
1087}
1088
1089static void mmu_alloc_roots(struct kvm_vcpu *vcpu)
1090{
1091 int i;
cea0f0e7 1092 gfn_t root_gfn;
4db35314 1093 struct kvm_mmu_page *sp;
3bb65a22 1094
ad312c7c 1095 root_gfn = vcpu->arch.cr3 >> PAGE_SHIFT;
17ac10ad
AK
1096
1097#ifdef CONFIG_X86_64
ad312c7c
ZX
1098 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
1099 hpa_t root = vcpu->arch.mmu.root_hpa;
17ac10ad
AK
1100
1101 ASSERT(!VALID_PAGE(root));
4db35314 1102 sp = kvm_mmu_get_page(vcpu, root_gfn, 0,
7819026e 1103 PT64_ROOT_LEVEL, 0, ACC_ALL, NULL, NULL);
4db35314
AK
1104 root = __pa(sp->spt);
1105 ++sp->root_count;
ad312c7c 1106 vcpu->arch.mmu.root_hpa = root;
17ac10ad
AK
1107 return;
1108 }
1109#endif
1110 for (i = 0; i < 4; ++i) {
ad312c7c 1111 hpa_t root = vcpu->arch.mmu.pae_root[i];
17ac10ad
AK
1112
1113 ASSERT(!VALID_PAGE(root));
ad312c7c
ZX
1114 if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
1115 if (!is_present_pte(vcpu->arch.pdptrs[i])) {
1116 vcpu->arch.mmu.pae_root[i] = 0;
417726a3
AK
1117 continue;
1118 }
ad312c7c
ZX
1119 root_gfn = vcpu->arch.pdptrs[i] >> PAGE_SHIFT;
1120 } else if (vcpu->arch.mmu.root_level == 0)
cea0f0e7 1121 root_gfn = 0;
4db35314
AK
1122 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30,
1123 PT32_ROOT_LEVEL, !is_paging(vcpu),
7819026e 1124 ACC_ALL, NULL, NULL);
4db35314
AK
1125 root = __pa(sp->spt);
1126 ++sp->root_count;
ad312c7c 1127 vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK;
17ac10ad 1128 }
ad312c7c 1129 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
17ac10ad
AK
1130}
1131
6aa8b732
AK
1132static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr)
1133{
1134 return vaddr;
1135}
1136
1137static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
3f3e7124 1138 u32 error_code)
6aa8b732 1139{
e833240f 1140 gfn_t gfn;
e2dec939 1141 int r;
6aa8b732 1142
e833240f 1143 pgprintk("%s: gva %lx error %x\n", __FUNCTION__, gva, error_code);
e2dec939
AK
1144 r = mmu_topup_memory_caches(vcpu);
1145 if (r)
1146 return r;
714b93da 1147
6aa8b732 1148 ASSERT(vcpu);
ad312c7c 1149 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
6aa8b732 1150
e833240f 1151 gfn = gva >> PAGE_SHIFT;
6aa8b732 1152
e833240f
AK
1153 return nonpaging_map(vcpu, gva & PAGE_MASK,
1154 error_code & PFERR_WRITE_MASK, gfn);
6aa8b732
AK
1155}
1156
6aa8b732
AK
1157static void nonpaging_free(struct kvm_vcpu *vcpu)
1158{
17ac10ad 1159 mmu_free_roots(vcpu);
6aa8b732
AK
1160}
1161
1162static int nonpaging_init_context(struct kvm_vcpu *vcpu)
1163{
ad312c7c 1164 struct kvm_mmu *context = &vcpu->arch.mmu;
6aa8b732
AK
1165
1166 context->new_cr3 = nonpaging_new_cr3;
1167 context->page_fault = nonpaging_page_fault;
6aa8b732
AK
1168 context->gva_to_gpa = nonpaging_gva_to_gpa;
1169 context->free = nonpaging_free;
c7addb90 1170 context->prefetch_page = nonpaging_prefetch_page;
cea0f0e7 1171 context->root_level = 0;
6aa8b732 1172 context->shadow_root_level = PT32E_ROOT_LEVEL;
17c3ba9d 1173 context->root_hpa = INVALID_PAGE;
6aa8b732
AK
1174 return 0;
1175}
1176
d835dfec 1177void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu)
6aa8b732 1178{
1165f5fe 1179 ++vcpu->stat.tlb_flush;
cbdd1bea 1180 kvm_x86_ops->tlb_flush(vcpu);
6aa8b732
AK
1181}
1182
1183static void paging_new_cr3(struct kvm_vcpu *vcpu)
1184{
24993d53 1185 pgprintk("%s: cr3 %lx\n", __FUNCTION__, vcpu->arch.cr3);
cea0f0e7 1186 mmu_free_roots(vcpu);
6aa8b732
AK
1187}
1188
6aa8b732
AK
1189static void inject_page_fault(struct kvm_vcpu *vcpu,
1190 u64 addr,
1191 u32 err_code)
1192{
c3c91fee 1193 kvm_inject_page_fault(vcpu, addr, err_code);
6aa8b732
AK
1194}
1195
6aa8b732
AK
1196static void paging_free(struct kvm_vcpu *vcpu)
1197{
1198 nonpaging_free(vcpu);
1199}
1200
1201#define PTTYPE 64
1202#include "paging_tmpl.h"
1203#undef PTTYPE
1204
1205#define PTTYPE 32
1206#include "paging_tmpl.h"
1207#undef PTTYPE
1208
17ac10ad 1209static int paging64_init_context_common(struct kvm_vcpu *vcpu, int level)
6aa8b732 1210{
ad312c7c 1211 struct kvm_mmu *context = &vcpu->arch.mmu;
6aa8b732
AK
1212
1213 ASSERT(is_pae(vcpu));
1214 context->new_cr3 = paging_new_cr3;
1215 context->page_fault = paging64_page_fault;
6aa8b732 1216 context->gva_to_gpa = paging64_gva_to_gpa;
c7addb90 1217 context->prefetch_page = paging64_prefetch_page;
6aa8b732 1218 context->free = paging_free;
17ac10ad
AK
1219 context->root_level = level;
1220 context->shadow_root_level = level;
17c3ba9d 1221 context->root_hpa = INVALID_PAGE;
6aa8b732
AK
1222 return 0;
1223}
1224
17ac10ad
AK
1225static int paging64_init_context(struct kvm_vcpu *vcpu)
1226{
1227 return paging64_init_context_common(vcpu, PT64_ROOT_LEVEL);
1228}
1229
6aa8b732
AK
1230static int paging32_init_context(struct kvm_vcpu *vcpu)
1231{
ad312c7c 1232 struct kvm_mmu *context = &vcpu->arch.mmu;
6aa8b732
AK
1233
1234 context->new_cr3 = paging_new_cr3;
1235 context->page_fault = paging32_page_fault;
6aa8b732
AK
1236 context->gva_to_gpa = paging32_gva_to_gpa;
1237 context->free = paging_free;
c7addb90 1238 context->prefetch_page = paging32_prefetch_page;
6aa8b732
AK
1239 context->root_level = PT32_ROOT_LEVEL;
1240 context->shadow_root_level = PT32E_ROOT_LEVEL;
17c3ba9d 1241 context->root_hpa = INVALID_PAGE;
6aa8b732
AK
1242 return 0;
1243}
1244
1245static int paging32E_init_context(struct kvm_vcpu *vcpu)
1246{
17ac10ad 1247 return paging64_init_context_common(vcpu, PT32E_ROOT_LEVEL);
6aa8b732
AK
1248}
1249
1250static int init_kvm_mmu(struct kvm_vcpu *vcpu)
1251{
1252 ASSERT(vcpu);
ad312c7c 1253 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
6aa8b732
AK
1254
1255 if (!is_paging(vcpu))
1256 return nonpaging_init_context(vcpu);
a9058ecd 1257 else if (is_long_mode(vcpu))
6aa8b732
AK
1258 return paging64_init_context(vcpu);
1259 else if (is_pae(vcpu))
1260 return paging32E_init_context(vcpu);
1261 else
1262 return paging32_init_context(vcpu);
1263}
1264
1265static void destroy_kvm_mmu(struct kvm_vcpu *vcpu)
1266{
1267 ASSERT(vcpu);
ad312c7c
ZX
1268 if (VALID_PAGE(vcpu->arch.mmu.root_hpa)) {
1269 vcpu->arch.mmu.free(vcpu);
1270 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
6aa8b732
AK
1271 }
1272}
1273
1274int kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
17c3ba9d
AK
1275{
1276 destroy_kvm_mmu(vcpu);
1277 return init_kvm_mmu(vcpu);
1278}
8668a3c4 1279EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
17c3ba9d
AK
1280
1281int kvm_mmu_load(struct kvm_vcpu *vcpu)
6aa8b732 1282{
714b93da
AK
1283 int r;
1284
e2dec939 1285 r = mmu_topup_memory_caches(vcpu);
17c3ba9d
AK
1286 if (r)
1287 goto out;
aaee2c94 1288 spin_lock(&vcpu->kvm->mmu_lock);
eb787d10 1289 kvm_mmu_free_some_pages(vcpu);
17c3ba9d 1290 mmu_alloc_roots(vcpu);
aaee2c94 1291 spin_unlock(&vcpu->kvm->mmu_lock);
ad312c7c 1292 kvm_x86_ops->set_cr3(vcpu, vcpu->arch.mmu.root_hpa);
17c3ba9d 1293 kvm_mmu_flush_tlb(vcpu);
714b93da
AK
1294out:
1295 return r;
6aa8b732 1296}
17c3ba9d
AK
1297EXPORT_SYMBOL_GPL(kvm_mmu_load);
1298
1299void kvm_mmu_unload(struct kvm_vcpu *vcpu)
1300{
1301 mmu_free_roots(vcpu);
1302}
6aa8b732 1303
09072daf 1304static void mmu_pte_write_zap_pte(struct kvm_vcpu *vcpu,
4db35314 1305 struct kvm_mmu_page *sp,
ac1b714e
AK
1306 u64 *spte)
1307{
1308 u64 pte;
1309 struct kvm_mmu_page *child;
1310
1311 pte = *spte;
c7addb90 1312 if (is_shadow_present_pte(pte)) {
4db35314 1313 if (sp->role.level == PT_PAGE_TABLE_LEVEL)
290fc38d 1314 rmap_remove(vcpu->kvm, spte);
ac1b714e
AK
1315 else {
1316 child = page_header(pte & PT64_BASE_ADDR_MASK);
90cb0529 1317 mmu_page_remove_parent_pte(child, spte);
ac1b714e
AK
1318 }
1319 }
c7addb90 1320 set_shadow_pte(spte, shadow_trap_nonpresent_pte);
ac1b714e
AK
1321}
1322
0028425f 1323static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
4db35314 1324 struct kvm_mmu_page *sp,
0028425f 1325 u64 *spte,
c7addb90
AK
1326 const void *new, int bytes,
1327 int offset_in_pte)
0028425f 1328{
4db35314 1329 if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
4cee5764 1330 ++vcpu->kvm->stat.mmu_pde_zapped;
0028425f 1331 return;
4cee5764 1332 }
0028425f 1333
4cee5764 1334 ++vcpu->kvm->stat.mmu_pte_updated;
4db35314
AK
1335 if (sp->role.glevels == PT32_ROOT_LEVEL)
1336 paging32_update_pte(vcpu, sp, spte, new, bytes, offset_in_pte);
0028425f 1337 else
4db35314 1338 paging64_update_pte(vcpu, sp, spte, new, bytes, offset_in_pte);
0028425f
AK
1339}
1340
79539cec
AK
1341static bool need_remote_flush(u64 old, u64 new)
1342{
1343 if (!is_shadow_present_pte(old))
1344 return false;
1345 if (!is_shadow_present_pte(new))
1346 return true;
1347 if ((old ^ new) & PT64_BASE_ADDR_MASK)
1348 return true;
1349 old ^= PT64_NX_MASK;
1350 new ^= PT64_NX_MASK;
1351 return (old & ~new & PT64_PERM_MASK) != 0;
1352}
1353
1354static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, u64 old, u64 new)
1355{
1356 if (need_remote_flush(old, new))
1357 kvm_flush_remote_tlbs(vcpu->kvm);
1358 else
1359 kvm_mmu_flush_tlb(vcpu);
1360}
1361
12b7d28f
AK
1362static bool last_updated_pte_accessed(struct kvm_vcpu *vcpu)
1363{
ad312c7c 1364 u64 *spte = vcpu->arch.last_pte_updated;
12b7d28f
AK
1365
1366 return !!(spte && (*spte & PT_ACCESSED_MASK));
1367}
1368
d7824fff
AK
1369static void mmu_guess_page_from_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
1370 const u8 *new, int bytes)
1371{
1372 gfn_t gfn;
1373 int r;
1374 u64 gpte = 0;
72dc67a6 1375 struct page *page;
d7824fff
AK
1376
1377 if (bytes != 4 && bytes != 8)
1378 return;
1379
1380 /*
1381 * Assume that the pte write on a page table of the same type
1382 * as the current vcpu paging mode. This is nearly always true
1383 * (might be false while changing modes). Note it is verified later
1384 * by update_pte().
1385 */
1386 if (is_pae(vcpu)) {
1387 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
1388 if ((bytes == 4) && (gpa % 4 == 0)) {
1389 r = kvm_read_guest(vcpu->kvm, gpa & ~(u64)7, &gpte, 8);
1390 if (r)
1391 return;
1392 memcpy((void *)&gpte + (gpa % 8), new, 4);
1393 } else if ((bytes == 8) && (gpa % 8 == 0)) {
1394 memcpy((void *)&gpte, new, 8);
1395 }
1396 } else {
1397 if ((bytes == 4) && (gpa % 4 == 0))
1398 memcpy((void *)&gpte, new, 4);
1399 }
1400 if (!is_present_pte(gpte))
1401 return;
1402 gfn = (gpte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
72dc67a6
IE
1403
1404 down_read(&current->mm->mmap_sem);
1405 page = gfn_to_page(vcpu->kvm, gfn);
1406 up_read(&current->mm->mmap_sem);
1407
d7824fff
AK
1408 vcpu->arch.update_pte.gfn = gfn;
1409 vcpu->arch.update_pte.page = gfn_to_page(vcpu->kvm, gfn);
1410}
1411
09072daf 1412void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
fe551881 1413 const u8 *new, int bytes)
da4a00f0 1414{
9b7a0325 1415 gfn_t gfn = gpa >> PAGE_SHIFT;
4db35314 1416 struct kvm_mmu_page *sp;
0e7bc4b9 1417 struct hlist_node *node, *n;
9b7a0325
AK
1418 struct hlist_head *bucket;
1419 unsigned index;
79539cec 1420 u64 entry;
9b7a0325 1421 u64 *spte;
9b7a0325 1422 unsigned offset = offset_in_page(gpa);
0e7bc4b9 1423 unsigned pte_size;
9b7a0325 1424 unsigned page_offset;
0e7bc4b9 1425 unsigned misaligned;
fce0657f 1426 unsigned quadrant;
9b7a0325 1427 int level;
86a5ba02 1428 int flooded = 0;
ac1b714e 1429 int npte;
9b7a0325 1430
da4a00f0 1431 pgprintk("%s: gpa %llx bytes %d\n", __FUNCTION__, gpa, bytes);
d7824fff 1432 mmu_guess_page_from_pte_write(vcpu, gpa, new, bytes);
aaee2c94 1433 spin_lock(&vcpu->kvm->mmu_lock);
eb787d10 1434 kvm_mmu_free_some_pages(vcpu);
4cee5764 1435 ++vcpu->kvm->stat.mmu_pte_write;
c7addb90 1436 kvm_mmu_audit(vcpu, "pre pte write");
ad312c7c 1437 if (gfn == vcpu->arch.last_pt_write_gfn
12b7d28f 1438 && !last_updated_pte_accessed(vcpu)) {
ad312c7c
ZX
1439 ++vcpu->arch.last_pt_write_count;
1440 if (vcpu->arch.last_pt_write_count >= 3)
86a5ba02
AK
1441 flooded = 1;
1442 } else {
ad312c7c
ZX
1443 vcpu->arch.last_pt_write_gfn = gfn;
1444 vcpu->arch.last_pt_write_count = 1;
1445 vcpu->arch.last_pte_updated = NULL;
86a5ba02 1446 }
9b7a0325 1447 index = kvm_page_table_hashfn(gfn) % KVM_NUM_MMU_PAGES;
f05e70ac 1448 bucket = &vcpu->kvm->arch.mmu_page_hash[index];
4db35314
AK
1449 hlist_for_each_entry_safe(sp, node, n, bucket, hash_link) {
1450 if (sp->gfn != gfn || sp->role.metaphysical)
9b7a0325 1451 continue;
4db35314 1452 pte_size = sp->role.glevels == PT32_ROOT_LEVEL ? 4 : 8;
0e7bc4b9 1453 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
e925c5ba 1454 misaligned |= bytes < 4;
86a5ba02 1455 if (misaligned || flooded) {
0e7bc4b9
AK
1456 /*
1457 * Misaligned accesses are too much trouble to fix
1458 * up; also, they usually indicate a page is not used
1459 * as a page table.
86a5ba02
AK
1460 *
1461 * If we're seeing too many writes to a page,
1462 * it may no longer be a page table, or we may be
1463 * forking, in which case it is better to unmap the
1464 * page.
0e7bc4b9
AK
1465 */
1466 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
4db35314
AK
1467 gpa, bytes, sp->role.word);
1468 kvm_mmu_zap_page(vcpu->kvm, sp);
4cee5764 1469 ++vcpu->kvm->stat.mmu_flooded;
0e7bc4b9
AK
1470 continue;
1471 }
9b7a0325 1472 page_offset = offset;
4db35314 1473 level = sp->role.level;
ac1b714e 1474 npte = 1;
4db35314 1475 if (sp->role.glevels == PT32_ROOT_LEVEL) {
ac1b714e
AK
1476 page_offset <<= 1; /* 32->64 */
1477 /*
1478 * A 32-bit pde maps 4MB while the shadow pdes map
1479 * only 2MB. So we need to double the offset again
1480 * and zap two pdes instead of one.
1481 */
1482 if (level == PT32_ROOT_LEVEL) {
6b8d0f9b 1483 page_offset &= ~7; /* kill rounding error */
ac1b714e
AK
1484 page_offset <<= 1;
1485 npte = 2;
1486 }
fce0657f 1487 quadrant = page_offset >> PAGE_SHIFT;
9b7a0325 1488 page_offset &= ~PAGE_MASK;
4db35314 1489 if (quadrant != sp->role.quadrant)
fce0657f 1490 continue;
9b7a0325 1491 }
4db35314 1492 spte = &sp->spt[page_offset / sizeof(*spte)];
ac1b714e 1493 while (npte--) {
79539cec 1494 entry = *spte;
4db35314
AK
1495 mmu_pte_write_zap_pte(vcpu, sp, spte);
1496 mmu_pte_write_new_pte(vcpu, sp, spte, new, bytes,
c7addb90 1497 page_offset & (pte_size - 1));
79539cec 1498 mmu_pte_write_flush_tlb(vcpu, entry, *spte);
ac1b714e 1499 ++spte;
9b7a0325 1500 }
9b7a0325 1501 }
c7addb90 1502 kvm_mmu_audit(vcpu, "post pte write");
aaee2c94 1503 spin_unlock(&vcpu->kvm->mmu_lock);
d7824fff
AK
1504 if (vcpu->arch.update_pte.page) {
1505 kvm_release_page_clean(vcpu->arch.update_pte.page);
1506 vcpu->arch.update_pte.page = NULL;
1507 }
da4a00f0
AK
1508}
1509
a436036b
AK
1510int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
1511{
10589a46
MT
1512 gpa_t gpa;
1513 int r;
a436036b 1514
72dc67a6 1515 down_read(&vcpu->kvm->slots_lock);
10589a46 1516 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gva);
72dc67a6 1517 up_read(&vcpu->kvm->slots_lock);
10589a46 1518
aaee2c94 1519 spin_lock(&vcpu->kvm->mmu_lock);
10589a46 1520 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
aaee2c94 1521 spin_unlock(&vcpu->kvm->mmu_lock);
10589a46 1522 return r;
a436036b
AK
1523}
1524
22d95b12 1525void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu)
ebeace86 1526{
f05e70ac 1527 while (vcpu->kvm->arch.n_free_mmu_pages < KVM_REFILL_PAGES) {
4db35314 1528 struct kvm_mmu_page *sp;
ebeace86 1529
f05e70ac 1530 sp = container_of(vcpu->kvm->arch.active_mmu_pages.prev,
4db35314
AK
1531 struct kvm_mmu_page, link);
1532 kvm_mmu_zap_page(vcpu->kvm, sp);
4cee5764 1533 ++vcpu->kvm->stat.mmu_recycled;
ebeace86
AK
1534 }
1535}
ebeace86 1536
3067714c
AK
1537int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code)
1538{
1539 int r;
1540 enum emulation_result er;
1541
ad312c7c 1542 r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code);
3067714c
AK
1543 if (r < 0)
1544 goto out;
1545
1546 if (!r) {
1547 r = 1;
1548 goto out;
1549 }
1550
b733bfb5
AK
1551 r = mmu_topup_memory_caches(vcpu);
1552 if (r)
1553 goto out;
1554
3067714c 1555 er = emulate_instruction(vcpu, vcpu->run, cr2, error_code, 0);
3067714c
AK
1556
1557 switch (er) {
1558 case EMULATE_DONE:
1559 return 1;
1560 case EMULATE_DO_MMIO:
1561 ++vcpu->stat.mmio_exits;
1562 return 0;
1563 case EMULATE_FAIL:
1564 kvm_report_emulation_failure(vcpu, "pagetable");
1565 return 1;
1566 default:
1567 BUG();
1568 }
1569out:
3067714c
AK
1570 return r;
1571}
1572EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
1573
6aa8b732
AK
1574static void free_mmu_pages(struct kvm_vcpu *vcpu)
1575{
4db35314 1576 struct kvm_mmu_page *sp;
6aa8b732 1577
f05e70ac
ZX
1578 while (!list_empty(&vcpu->kvm->arch.active_mmu_pages)) {
1579 sp = container_of(vcpu->kvm->arch.active_mmu_pages.next,
4db35314
AK
1580 struct kvm_mmu_page, link);
1581 kvm_mmu_zap_page(vcpu->kvm, sp);
f51234c2 1582 }
ad312c7c 1583 free_page((unsigned long)vcpu->arch.mmu.pae_root);
6aa8b732
AK
1584}
1585
1586static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
1587{
17ac10ad 1588 struct page *page;
6aa8b732
AK
1589 int i;
1590
1591 ASSERT(vcpu);
1592
f05e70ac
ZX
1593 if (vcpu->kvm->arch.n_requested_mmu_pages)
1594 vcpu->kvm->arch.n_free_mmu_pages =
1595 vcpu->kvm->arch.n_requested_mmu_pages;
82ce2c96 1596 else
f05e70ac
ZX
1597 vcpu->kvm->arch.n_free_mmu_pages =
1598 vcpu->kvm->arch.n_alloc_mmu_pages;
17ac10ad
AK
1599 /*
1600 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
1601 * Therefore we need to allocate shadow page tables in the first
1602 * 4GB of memory, which happens to fit the DMA32 zone.
1603 */
1604 page = alloc_page(GFP_KERNEL | __GFP_DMA32);
1605 if (!page)
1606 goto error_1;
ad312c7c 1607 vcpu->arch.mmu.pae_root = page_address(page);
17ac10ad 1608 for (i = 0; i < 4; ++i)
ad312c7c 1609 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
17ac10ad 1610
6aa8b732
AK
1611 return 0;
1612
1613error_1:
1614 free_mmu_pages(vcpu);
1615 return -ENOMEM;
1616}
1617
8018c27b 1618int kvm_mmu_create(struct kvm_vcpu *vcpu)
6aa8b732 1619{
6aa8b732 1620 ASSERT(vcpu);
ad312c7c 1621 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
6aa8b732 1622
8018c27b
IM
1623 return alloc_mmu_pages(vcpu);
1624}
6aa8b732 1625
8018c27b
IM
1626int kvm_mmu_setup(struct kvm_vcpu *vcpu)
1627{
1628 ASSERT(vcpu);
ad312c7c 1629 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
2c264957 1630
8018c27b 1631 return init_kvm_mmu(vcpu);
6aa8b732
AK
1632}
1633
1634void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
1635{
1636 ASSERT(vcpu);
1637
1638 destroy_kvm_mmu(vcpu);
1639 free_mmu_pages(vcpu);
714b93da 1640 mmu_free_memory_caches(vcpu);
6aa8b732
AK
1641}
1642
90cb0529 1643void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot)
6aa8b732 1644{
4db35314 1645 struct kvm_mmu_page *sp;
6aa8b732 1646
f05e70ac 1647 list_for_each_entry(sp, &kvm->arch.active_mmu_pages, link) {
6aa8b732
AK
1648 int i;
1649 u64 *pt;
1650
4db35314 1651 if (!test_bit(slot, &sp->slot_bitmap))
6aa8b732
AK
1652 continue;
1653
4db35314 1654 pt = sp->spt;
6aa8b732
AK
1655 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
1656 /* avoid RMW */
9647c14c 1657 if (pt[i] & PT_WRITABLE_MASK)
6aa8b732 1658 pt[i] &= ~PT_WRITABLE_MASK;
6aa8b732
AK
1659 }
1660}
37a7d8b0 1661
90cb0529 1662void kvm_mmu_zap_all(struct kvm *kvm)
e0fa826f 1663{
4db35314 1664 struct kvm_mmu_page *sp, *node;
e0fa826f 1665
aaee2c94 1666 spin_lock(&kvm->mmu_lock);
f05e70ac 1667 list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link)
4db35314 1668 kvm_mmu_zap_page(kvm, sp);
aaee2c94 1669 spin_unlock(&kvm->mmu_lock);
e0fa826f 1670
90cb0529 1671 kvm_flush_remote_tlbs(kvm);
e0fa826f
DL
1672}
1673
b5a33a75
AK
1674void kvm_mmu_module_exit(void)
1675{
1676 if (pte_chain_cache)
1677 kmem_cache_destroy(pte_chain_cache);
1678 if (rmap_desc_cache)
1679 kmem_cache_destroy(rmap_desc_cache);
d3d25b04
AK
1680 if (mmu_page_header_cache)
1681 kmem_cache_destroy(mmu_page_header_cache);
b5a33a75
AK
1682}
1683
1684int kvm_mmu_module_init(void)
1685{
1686 pte_chain_cache = kmem_cache_create("kvm_pte_chain",
1687 sizeof(struct kvm_pte_chain),
20c2df83 1688 0, 0, NULL);
b5a33a75
AK
1689 if (!pte_chain_cache)
1690 goto nomem;
1691 rmap_desc_cache = kmem_cache_create("kvm_rmap_desc",
1692 sizeof(struct kvm_rmap_desc),
20c2df83 1693 0, 0, NULL);
b5a33a75
AK
1694 if (!rmap_desc_cache)
1695 goto nomem;
1696
d3d25b04
AK
1697 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
1698 sizeof(struct kvm_mmu_page),
20c2df83 1699 0, 0, NULL);
d3d25b04
AK
1700 if (!mmu_page_header_cache)
1701 goto nomem;
1702
b5a33a75
AK
1703 return 0;
1704
1705nomem:
1706 kvm_mmu_module_exit();
1707 return -ENOMEM;
1708}
1709
3ad82a7e
ZX
1710/*
1711 * Caculate mmu pages needed for kvm.
1712 */
1713unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
1714{
1715 int i;
1716 unsigned int nr_mmu_pages;
1717 unsigned int nr_pages = 0;
1718
1719 for (i = 0; i < kvm->nmemslots; i++)
1720 nr_pages += kvm->memslots[i].npages;
1721
1722 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
1723 nr_mmu_pages = max(nr_mmu_pages,
1724 (unsigned int) KVM_MIN_ALLOC_MMU_PAGES);
1725
1726 return nr_mmu_pages;
1727}
1728
37a7d8b0
AK
1729#ifdef AUDIT
1730
1731static const char *audit_msg;
1732
1733static gva_t canonicalize(gva_t gva)
1734{
1735#ifdef CONFIG_X86_64
1736 gva = (long long)(gva << 16) >> 16;
1737#endif
1738 return gva;
1739}
1740
1741static void audit_mappings_page(struct kvm_vcpu *vcpu, u64 page_pte,
1742 gva_t va, int level)
1743{
1744 u64 *pt = __va(page_pte & PT64_BASE_ADDR_MASK);
1745 int i;
1746 gva_t va_delta = 1ul << (PAGE_SHIFT + 9 * (level - 1));
1747
1748 for (i = 0; i < PT64_ENT_PER_PAGE; ++i, va += va_delta) {
1749 u64 ent = pt[i];
1750
c7addb90 1751 if (ent == shadow_trap_nonpresent_pte)
37a7d8b0
AK
1752 continue;
1753
1754 va = canonicalize(va);
c7addb90
AK
1755 if (level > 1) {
1756 if (ent == shadow_notrap_nonpresent_pte)
1757 printk(KERN_ERR "audit: (%s) nontrapping pte"
1758 " in nonleaf level: levels %d gva %lx"
1759 " level %d pte %llx\n", audit_msg,
ad312c7c 1760 vcpu->arch.mmu.root_level, va, level, ent);
c7addb90 1761
37a7d8b0 1762 audit_mappings_page(vcpu, ent, va, level - 1);
c7addb90 1763 } else {
ad312c7c 1764 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, va);
1d28f5f4
AK
1765 struct page *page = gpa_to_page(vcpu, gpa);
1766 hpa_t hpa = page_to_phys(page);
37a7d8b0 1767
c7addb90 1768 if (is_shadow_present_pte(ent)
37a7d8b0 1769 && (ent & PT64_BASE_ADDR_MASK) != hpa)
c7addb90
AK
1770 printk(KERN_ERR "xx audit error: (%s) levels %d"
1771 " gva %lx gpa %llx hpa %llx ent %llx %d\n",
ad312c7c 1772 audit_msg, vcpu->arch.mmu.root_level,
d77c26fc
MD
1773 va, gpa, hpa, ent,
1774 is_shadow_present_pte(ent));
c7addb90
AK
1775 else if (ent == shadow_notrap_nonpresent_pte
1776 && !is_error_hpa(hpa))
1777 printk(KERN_ERR "audit: (%s) notrap shadow,"
1778 " valid guest gva %lx\n", audit_msg, va);
b4231d61 1779 kvm_release_page_clean(page);
c7addb90 1780
37a7d8b0
AK
1781 }
1782 }
1783}
1784
1785static void audit_mappings(struct kvm_vcpu *vcpu)
1786{
1ea252af 1787 unsigned i;
37a7d8b0 1788
ad312c7c
ZX
1789 if (vcpu->arch.mmu.root_level == 4)
1790 audit_mappings_page(vcpu, vcpu->arch.mmu.root_hpa, 0, 4);
37a7d8b0
AK
1791 else
1792 for (i = 0; i < 4; ++i)
ad312c7c 1793 if (vcpu->arch.mmu.pae_root[i] & PT_PRESENT_MASK)
37a7d8b0 1794 audit_mappings_page(vcpu,
ad312c7c 1795 vcpu->arch.mmu.pae_root[i],
37a7d8b0
AK
1796 i << 30,
1797 2);
1798}
1799
1800static int count_rmaps(struct kvm_vcpu *vcpu)
1801{
1802 int nmaps = 0;
1803 int i, j, k;
1804
1805 for (i = 0; i < KVM_MEMORY_SLOTS; ++i) {
1806 struct kvm_memory_slot *m = &vcpu->kvm->memslots[i];
1807 struct kvm_rmap_desc *d;
1808
1809 for (j = 0; j < m->npages; ++j) {
290fc38d 1810 unsigned long *rmapp = &m->rmap[j];
37a7d8b0 1811
290fc38d 1812 if (!*rmapp)
37a7d8b0 1813 continue;
290fc38d 1814 if (!(*rmapp & 1)) {
37a7d8b0
AK
1815 ++nmaps;
1816 continue;
1817 }
290fc38d 1818 d = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
37a7d8b0
AK
1819 while (d) {
1820 for (k = 0; k < RMAP_EXT; ++k)
1821 if (d->shadow_ptes[k])
1822 ++nmaps;
1823 else
1824 break;
1825 d = d->more;
1826 }
1827 }
1828 }
1829 return nmaps;
1830}
1831
1832static int count_writable_mappings(struct kvm_vcpu *vcpu)
1833{
1834 int nmaps = 0;
4db35314 1835 struct kvm_mmu_page *sp;
37a7d8b0
AK
1836 int i;
1837
f05e70ac 1838 list_for_each_entry(sp, &vcpu->kvm->arch.active_mmu_pages, link) {
4db35314 1839 u64 *pt = sp->spt;
37a7d8b0 1840
4db35314 1841 if (sp->role.level != PT_PAGE_TABLE_LEVEL)
37a7d8b0
AK
1842 continue;
1843
1844 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
1845 u64 ent = pt[i];
1846
1847 if (!(ent & PT_PRESENT_MASK))
1848 continue;
1849 if (!(ent & PT_WRITABLE_MASK))
1850 continue;
1851 ++nmaps;
1852 }
1853 }
1854 return nmaps;
1855}
1856
1857static void audit_rmap(struct kvm_vcpu *vcpu)
1858{
1859 int n_rmap = count_rmaps(vcpu);
1860 int n_actual = count_writable_mappings(vcpu);
1861
1862 if (n_rmap != n_actual)
1863 printk(KERN_ERR "%s: (%s) rmap %d actual %d\n",
1864 __FUNCTION__, audit_msg, n_rmap, n_actual);
1865}
1866
1867static void audit_write_protection(struct kvm_vcpu *vcpu)
1868{
4db35314 1869 struct kvm_mmu_page *sp;
290fc38d
IE
1870 struct kvm_memory_slot *slot;
1871 unsigned long *rmapp;
1872 gfn_t gfn;
37a7d8b0 1873
f05e70ac 1874 list_for_each_entry(sp, &vcpu->kvm->arch.active_mmu_pages, link) {
4db35314 1875 if (sp->role.metaphysical)
37a7d8b0
AK
1876 continue;
1877
4db35314
AK
1878 slot = gfn_to_memslot(vcpu->kvm, sp->gfn);
1879 gfn = unalias_gfn(vcpu->kvm, sp->gfn);
290fc38d
IE
1880 rmapp = &slot->rmap[gfn - slot->base_gfn];
1881 if (*rmapp)
37a7d8b0
AK
1882 printk(KERN_ERR "%s: (%s) shadow page has writable"
1883 " mappings: gfn %lx role %x\n",
4db35314
AK
1884 __FUNCTION__, audit_msg, sp->gfn,
1885 sp->role.word);
37a7d8b0
AK
1886 }
1887}
1888
1889static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg)
1890{
1891 int olddbg = dbg;
1892
1893 dbg = 0;
1894 audit_msg = msg;
1895 audit_rmap(vcpu);
1896 audit_write_protection(vcpu);
1897 audit_mappings(vcpu);
1898 dbg = olddbg;
1899}
1900
1901#endif
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