Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * MMU support | |
8 | * | |
9 | * Copyright (C) 2006 Qumranet, Inc. | |
221d059d | 10 | * Copyright 2010 Red Hat, Inc. and/or its affilates. |
6aa8b732 AK |
11 | * |
12 | * Authors: | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * | |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | * | |
19 | */ | |
20 | ||
21 | /* | |
22 | * We need the mmu code to access both 32-bit and 64-bit guest ptes, | |
23 | * so the code in this file is compiled twice, once per pte size. | |
24 | */ | |
25 | ||
26 | #if PTTYPE == 64 | |
27 | #define pt_element_t u64 | |
28 | #define guest_walker guest_walker64 | |
29 | #define FNAME(name) paging##64_##name | |
30 | #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK | |
e04da980 JR |
31 | #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl) |
32 | #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl) | |
6aa8b732 | 33 | #define PT_INDEX(addr, level) PT64_INDEX(addr, level) |
6aa8b732 | 34 | #define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level) |
c7addb90 | 35 | #define PT_LEVEL_BITS PT64_LEVEL_BITS |
cea0f0e7 AK |
36 | #ifdef CONFIG_X86_64 |
37 | #define PT_MAX_FULL_LEVELS 4 | |
b3e4e63f | 38 | #define CMPXCHG cmpxchg |
cea0f0e7 | 39 | #else |
b3e4e63f | 40 | #define CMPXCHG cmpxchg64 |
cea0f0e7 AK |
41 | #define PT_MAX_FULL_LEVELS 2 |
42 | #endif | |
6aa8b732 AK |
43 | #elif PTTYPE == 32 |
44 | #define pt_element_t u32 | |
45 | #define guest_walker guest_walker32 | |
46 | #define FNAME(name) paging##32_##name | |
47 | #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK | |
e04da980 JR |
48 | #define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl) |
49 | #define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl) | |
6aa8b732 | 50 | #define PT_INDEX(addr, level) PT32_INDEX(addr, level) |
6aa8b732 | 51 | #define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level) |
c7addb90 | 52 | #define PT_LEVEL_BITS PT32_LEVEL_BITS |
cea0f0e7 | 53 | #define PT_MAX_FULL_LEVELS 2 |
b3e4e63f | 54 | #define CMPXCHG cmpxchg |
6aa8b732 AK |
55 | #else |
56 | #error Invalid PTTYPE value | |
57 | #endif | |
58 | ||
e04da980 JR |
59 | #define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl) |
60 | #define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PT_PAGE_TABLE_LEVEL) | |
5fb07ddb | 61 | |
6aa8b732 AK |
62 | /* |
63 | * The guest_walker structure emulates the behavior of the hardware page | |
64 | * table walker. | |
65 | */ | |
66 | struct guest_walker { | |
67 | int level; | |
cea0f0e7 | 68 | gfn_t table_gfn[PT_MAX_FULL_LEVELS]; |
7819026e MT |
69 | pt_element_t ptes[PT_MAX_FULL_LEVELS]; |
70 | gpa_t pte_gpa[PT_MAX_FULL_LEVELS]; | |
fe135d2c AK |
71 | unsigned pt_access; |
72 | unsigned pte_access; | |
815af8d4 | 73 | gfn_t gfn; |
7993ba43 | 74 | u32 error_code; |
6aa8b732 AK |
75 | }; |
76 | ||
e04da980 | 77 | static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl) |
5fb07ddb | 78 | { |
e04da980 | 79 | return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT; |
5fb07ddb AK |
80 | } |
81 | ||
b3e4e63f MT |
82 | static bool FNAME(cmpxchg_gpte)(struct kvm *kvm, |
83 | gfn_t table_gfn, unsigned index, | |
84 | pt_element_t orig_pte, pt_element_t new_pte) | |
85 | { | |
86 | pt_element_t ret; | |
87 | pt_element_t *table; | |
88 | struct page *page; | |
89 | ||
90 | page = gfn_to_page(kvm, table_gfn); | |
72dc67a6 | 91 | |
b3e4e63f | 92 | table = kmap_atomic(page, KM_USER0); |
b3e4e63f | 93 | ret = CMPXCHG(&table[index], orig_pte, new_pte); |
b3e4e63f MT |
94 | kunmap_atomic(table, KM_USER0); |
95 | ||
96 | kvm_release_page_dirty(page); | |
97 | ||
98 | return (ret != orig_pte); | |
99 | } | |
100 | ||
bedbe4ee AK |
101 | static unsigned FNAME(gpte_access)(struct kvm_vcpu *vcpu, pt_element_t gpte) |
102 | { | |
103 | unsigned access; | |
104 | ||
105 | access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK; | |
106 | #if PTTYPE == 64 | |
107 | if (is_nx(vcpu)) | |
108 | access &= ~(gpte >> PT64_NX_SHIFT); | |
109 | #endif | |
110 | return access; | |
111 | } | |
112 | ||
ac79c978 AK |
113 | /* |
114 | * Fetch a guest pte for a guest virtual address | |
115 | */ | |
7993ba43 AK |
116 | static int FNAME(walk_addr)(struct guest_walker *walker, |
117 | struct kvm_vcpu *vcpu, gva_t addr, | |
73b1087e | 118 | int write_fault, int user_fault, int fetch_fault) |
6aa8b732 | 119 | { |
42bf3f0a | 120 | pt_element_t pte; |
cea0f0e7 | 121 | gfn_t table_gfn; |
f59c1d2d | 122 | unsigned index, pt_access, uninitialized_var(pte_access); |
42bf3f0a | 123 | gpa_t pte_gpa; |
f59c1d2d | 124 | bool eperm, present, rsvd_fault; |
6aa8b732 | 125 | |
07420171 AK |
126 | trace_kvm_mmu_pagetable_walk(addr, write_fault, user_fault, |
127 | fetch_fault); | |
b3e4e63f | 128 | walk: |
f59c1d2d AK |
129 | present = true; |
130 | eperm = rsvd_fault = false; | |
ad312c7c ZX |
131 | walker->level = vcpu->arch.mmu.root_level; |
132 | pte = vcpu->arch.cr3; | |
1b0973bd AK |
133 | #if PTTYPE == 64 |
134 | if (!is_long_mode(vcpu)) { | |
6de4f3ad | 135 | pte = kvm_pdptr_read(vcpu, (addr >> 30) & 3); |
07420171 | 136 | trace_kvm_mmu_paging_element(pte, walker->level); |
f59c1d2d AK |
137 | if (!is_present_gpte(pte)) { |
138 | present = false; | |
139 | goto error; | |
140 | } | |
1b0973bd AK |
141 | --walker->level; |
142 | } | |
143 | #endif | |
a9058ecd | 144 | ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) || |
24993d53 | 145 | (vcpu->arch.cr3 & CR3_NONPAE_RESERVED_BITS) == 0); |
6aa8b732 | 146 | |
fe135d2c | 147 | pt_access = ACC_ALL; |
ac79c978 AK |
148 | |
149 | for (;;) { | |
42bf3f0a | 150 | index = PT_INDEX(addr, walker->level); |
ac79c978 | 151 | |
5fb07ddb | 152 | table_gfn = gpte_to_gfn(pte); |
1755fbcc | 153 | pte_gpa = gfn_to_gpa(table_gfn); |
ec8d4eae | 154 | pte_gpa += index * sizeof(pt_element_t); |
42bf3f0a | 155 | walker->table_gfn[walker->level - 1] = table_gfn; |
7819026e | 156 | walker->pte_gpa[walker->level - 1] = pte_gpa; |
42bf3f0a | 157 | |
f59c1d2d AK |
158 | if (kvm_read_guest(vcpu->kvm, pte_gpa, &pte, sizeof(pte))) { |
159 | present = false; | |
160 | break; | |
161 | } | |
a6085fba | 162 | |
07420171 | 163 | trace_kvm_mmu_paging_element(pte, walker->level); |
42bf3f0a | 164 | |
f59c1d2d AK |
165 | if (!is_present_gpte(pte)) { |
166 | present = false; | |
167 | break; | |
168 | } | |
7993ba43 | 169 | |
f59c1d2d AK |
170 | if (is_rsvd_bits_set(vcpu, pte, walker->level)) { |
171 | rsvd_fault = true; | |
172 | break; | |
173 | } | |
82725b20 | 174 | |
8dae4445 | 175 | if (write_fault && !is_writable_pte(pte)) |
7993ba43 | 176 | if (user_fault || is_write_protection(vcpu)) |
f59c1d2d | 177 | eperm = true; |
7993ba43 | 178 | |
42bf3f0a | 179 | if (user_fault && !(pte & PT_USER_MASK)) |
f59c1d2d | 180 | eperm = true; |
7993ba43 | 181 | |
73b1087e | 182 | #if PTTYPE == 64 |
24222c2f | 183 | if (fetch_fault && (pte & PT64_NX_MASK)) |
f59c1d2d | 184 | eperm = true; |
73b1087e AK |
185 | #endif |
186 | ||
f59c1d2d | 187 | if (!eperm && !rsvd_fault && !(pte & PT_ACCESSED_MASK)) { |
07420171 AK |
188 | trace_kvm_mmu_set_accessed_bit(table_gfn, index, |
189 | sizeof(pte)); | |
b3e4e63f MT |
190 | if (FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn, |
191 | index, pte, pte|PT_ACCESSED_MASK)) | |
192 | goto walk; | |
f3b8c964 | 193 | mark_page_dirty(vcpu->kvm, table_gfn); |
42bf3f0a | 194 | pte |= PT_ACCESSED_MASK; |
bf3f8e86 | 195 | } |
815af8d4 | 196 | |
bedbe4ee | 197 | pte_access = pt_access & FNAME(gpte_access)(vcpu, pte); |
fe135d2c | 198 | |
7819026e MT |
199 | walker->ptes[walker->level - 1] = pte; |
200 | ||
e04da980 JR |
201 | if ((walker->level == PT_PAGE_TABLE_LEVEL) || |
202 | ((walker->level == PT_DIRECTORY_LEVEL) && | |
814a59d2 | 203 | is_large_pte(pte) && |
e04da980 JR |
204 | (PTTYPE == 64 || is_pse(vcpu))) || |
205 | ((walker->level == PT_PDPE_LEVEL) && | |
814a59d2 | 206 | is_large_pte(pte) && |
e04da980 JR |
207 | is_long_mode(vcpu))) { |
208 | int lvl = walker->level; | |
209 | ||
210 | walker->gfn = gpte_to_gfn_lvl(pte, lvl); | |
211 | walker->gfn += (addr & PT_LVL_OFFSET_MASK(lvl)) | |
212 | >> PAGE_SHIFT; | |
213 | ||
214 | if (PTTYPE == 32 && | |
215 | walker->level == PT_DIRECTORY_LEVEL && | |
216 | is_cpuid_PSE36()) | |
da928521 | 217 | walker->gfn += pse36_gfn_delta(pte); |
e04da980 | 218 | |
ac79c978 | 219 | break; |
815af8d4 | 220 | } |
ac79c978 | 221 | |
fe135d2c | 222 | pt_access = pte_access; |
ac79c978 AK |
223 | --walker->level; |
224 | } | |
42bf3f0a | 225 | |
f59c1d2d AK |
226 | if (!present || eperm || rsvd_fault) |
227 | goto error; | |
228 | ||
43a3795a | 229 | if (write_fault && !is_dirty_gpte(pte)) { |
b3e4e63f MT |
230 | bool ret; |
231 | ||
07420171 | 232 | trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte)); |
b3e4e63f MT |
233 | ret = FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn, index, pte, |
234 | pte|PT_DIRTY_MASK); | |
235 | if (ret) | |
236 | goto walk; | |
f3b8c964 | 237 | mark_page_dirty(vcpu->kvm, table_gfn); |
42bf3f0a | 238 | pte |= PT_DIRTY_MASK; |
7819026e | 239 | walker->ptes[walker->level - 1] = pte; |
42bf3f0a AK |
240 | } |
241 | ||
fe135d2c AK |
242 | walker->pt_access = pt_access; |
243 | walker->pte_access = pte_access; | |
244 | pgprintk("%s: pte %llx pte_access %x pt_access %x\n", | |
518c5a05 | 245 | __func__, (u64)pte, pte_access, pt_access); |
7993ba43 AK |
246 | return 1; |
247 | ||
f59c1d2d | 248 | error: |
7993ba43 | 249 | walker->error_code = 0; |
f59c1d2d AK |
250 | if (present) |
251 | walker->error_code |= PFERR_PRESENT_MASK; | |
7993ba43 AK |
252 | if (write_fault) |
253 | walker->error_code |= PFERR_WRITE_MASK; | |
254 | if (user_fault) | |
255 | walker->error_code |= PFERR_USER_MASK; | |
b0eeec29 | 256 | if (fetch_fault && is_nx(vcpu)) |
73b1087e | 257 | walker->error_code |= PFERR_FETCH_MASK; |
82725b20 DE |
258 | if (rsvd_fault) |
259 | walker->error_code |= PFERR_RSVD_MASK; | |
07420171 | 260 | trace_kvm_mmu_walker_error(walker->error_code); |
fe551881 | 261 | return 0; |
6aa8b732 AK |
262 | } |
263 | ||
ac3cd03c | 264 | static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
489f1d65 | 265 | u64 *spte, const void *pte) |
0028425f AK |
266 | { |
267 | pt_element_t gpte; | |
41074d07 | 268 | unsigned pte_access; |
35149e21 | 269 | pfn_t pfn; |
fbc5d139 | 270 | u64 new_spte; |
0028425f | 271 | |
0028425f | 272 | gpte = *(const pt_element_t *)pte; |
c7addb90 | 273 | if (~gpte & (PT_PRESENT_MASK | PT_ACCESSED_MASK)) { |
fbc5d139 | 274 | if (!is_present_gpte(gpte)) { |
ac3cd03c | 275 | if (sp->unsync) |
fbc5d139 AK |
276 | new_spte = shadow_trap_nonpresent_pte; |
277 | else | |
278 | new_spte = shadow_notrap_nonpresent_pte; | |
279 | __set_spte(spte, new_spte); | |
280 | } | |
c7addb90 AK |
281 | return; |
282 | } | |
b8688d51 | 283 | pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte); |
ac3cd03c | 284 | pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte); |
d7824fff AK |
285 | if (gpte_to_gfn(gpte) != vcpu->arch.update_pte.gfn) |
286 | return; | |
35149e21 AL |
287 | pfn = vcpu->arch.update_pte.pfn; |
288 | if (is_error_pfn(pfn)) | |
d7824fff | 289 | return; |
e930bffe AA |
290 | if (mmu_notifier_retry(vcpu, vcpu->arch.update_pte.mmu_seq)) |
291 | return; | |
35149e21 | 292 | kvm_get_pfn(pfn); |
1403283a IE |
293 | /* |
294 | * we call mmu_set_spte() with reset_host_protection = true beacuse that | |
295 | * vcpu->arch.update_pte.pfn was fetched from get_user_pages(write = 1). | |
296 | */ | |
ac3cd03c | 297 | mmu_set_spte(vcpu, spte, sp->role.access, pte_access, 0, 0, |
cb83cad2 | 298 | is_dirty_gpte(gpte), NULL, PT_PAGE_TABLE_LEVEL, |
1403283a | 299 | gpte_to_gfn(gpte), pfn, true, true); |
0028425f AK |
300 | } |
301 | ||
39c8c672 AK |
302 | static bool FNAME(gpte_changed)(struct kvm_vcpu *vcpu, |
303 | struct guest_walker *gw, int level) | |
304 | { | |
305 | int r; | |
306 | pt_element_t curr_pte; | |
307 | ||
308 | r = kvm_read_guest_atomic(vcpu->kvm, gw->pte_gpa[level - 1], | |
309 | &curr_pte, sizeof(curr_pte)); | |
310 | return r || curr_pte != gw->ptes[level - 1]; | |
311 | } | |
312 | ||
957ed9ef XG |
313 | static void FNAME(pte_prefetch)(struct kvm_vcpu *vcpu, u64 *sptep) |
314 | { | |
315 | struct kvm_mmu_page *sp; | |
316 | pt_element_t gptep[PTE_PREFETCH_NUM]; | |
317 | gpa_t first_pte_gpa; | |
318 | int offset = 0, i; | |
319 | u64 *spte; | |
320 | ||
321 | sp = page_header(__pa(sptep)); | |
322 | ||
323 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) | |
324 | return; | |
325 | ||
326 | if (sp->role.direct) | |
327 | return __direct_pte_prefetch(vcpu, sp, sptep); | |
328 | ||
329 | i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1); | |
330 | ||
331 | if (PTTYPE == 32) | |
332 | offset = sp->role.quadrant << PT64_LEVEL_BITS; | |
333 | ||
334 | first_pte_gpa = gfn_to_gpa(sp->gfn) + | |
335 | (offset + i) * sizeof(pt_element_t); | |
336 | ||
337 | if (kvm_read_guest_atomic(vcpu->kvm, first_pte_gpa, gptep, | |
338 | sizeof(gptep)) < 0) | |
339 | return; | |
340 | ||
341 | spte = sp->spt + i; | |
342 | ||
343 | for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) { | |
344 | pt_element_t gpte; | |
345 | unsigned pte_access; | |
346 | gfn_t gfn; | |
347 | pfn_t pfn; | |
348 | bool dirty; | |
349 | ||
350 | if (spte == sptep) | |
351 | continue; | |
352 | ||
353 | if (*spte != shadow_trap_nonpresent_pte) | |
354 | continue; | |
355 | ||
356 | gpte = gptep[i]; | |
357 | ||
358 | if (!is_present_gpte(gpte) || | |
359 | is_rsvd_bits_set(vcpu, gpte, PT_PAGE_TABLE_LEVEL)) { | |
360 | if (!sp->unsync) | |
361 | __set_spte(spte, shadow_notrap_nonpresent_pte); | |
362 | continue; | |
363 | } | |
364 | ||
365 | if (!(gpte & PT_ACCESSED_MASK)) | |
366 | continue; | |
367 | ||
368 | pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte); | |
369 | gfn = gpte_to_gfn(gpte); | |
370 | dirty = is_dirty_gpte(gpte); | |
371 | pfn = pte_prefetch_gfn_to_pfn(vcpu, gfn, | |
372 | (pte_access & ACC_WRITE_MASK) && dirty); | |
373 | if (is_error_pfn(pfn)) { | |
374 | kvm_release_pfn_clean(pfn); | |
375 | break; | |
376 | } | |
377 | ||
378 | mmu_set_spte(vcpu, spte, sp->role.access, pte_access, 0, 0, | |
379 | dirty, NULL, PT_PAGE_TABLE_LEVEL, gfn, | |
380 | pfn, true, true); | |
381 | } | |
382 | } | |
383 | ||
6aa8b732 AK |
384 | /* |
385 | * Fetch a shadow pte for a specific level in the paging hierarchy. | |
386 | */ | |
e7a04c99 AK |
387 | static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr, |
388 | struct guest_walker *gw, | |
7e4e4056 | 389 | int user_fault, int write_fault, int hlevel, |
e7a04c99 | 390 | int *ptwrite, pfn_t pfn) |
6aa8b732 | 391 | { |
abb9e0b8 | 392 | unsigned access = gw->pt_access; |
5991b332 | 393 | struct kvm_mmu_page *sp = NULL; |
84754cd8 | 394 | bool dirty = is_dirty_gpte(gw->ptes[gw->level - 1]); |
5991b332 | 395 | int top_level; |
84754cd8 | 396 | unsigned direct_access; |
24157aaf | 397 | struct kvm_shadow_walk_iterator it; |
abb9e0b8 | 398 | |
43a3795a | 399 | if (!is_present_gpte(gw->ptes[gw->level - 1])) |
e7a04c99 | 400 | return NULL; |
6aa8b732 | 401 | |
84754cd8 XG |
402 | direct_access = gw->pt_access & gw->pte_access; |
403 | if (!dirty) | |
404 | direct_access &= ~ACC_WRITE_MASK; | |
405 | ||
5991b332 AK |
406 | top_level = vcpu->arch.mmu.root_level; |
407 | if (top_level == PT32E_ROOT_LEVEL) | |
408 | top_level = PT32_ROOT_LEVEL; | |
409 | /* | |
410 | * Verify that the top-level gpte is still there. Since the page | |
411 | * is a root page, it is either write protected (and cannot be | |
412 | * changed from now on) or it is invalid (in which case, we don't | |
413 | * really care if it changes underneath us after this point). | |
414 | */ | |
415 | if (FNAME(gpte_changed)(vcpu, gw, top_level)) | |
416 | goto out_gpte_changed; | |
417 | ||
24157aaf AK |
418 | for (shadow_walk_init(&it, vcpu, addr); |
419 | shadow_walk_okay(&it) && it.level > gw->level; | |
420 | shadow_walk_next(&it)) { | |
0b3c9333 AK |
421 | gfn_t table_gfn; |
422 | ||
24157aaf | 423 | drop_large_spte(vcpu, it.sptep); |
ef0197e8 | 424 | |
5991b332 | 425 | sp = NULL; |
24157aaf AK |
426 | if (!is_shadow_present_pte(*it.sptep)) { |
427 | table_gfn = gw->table_gfn[it.level - 2]; | |
428 | sp = kvm_mmu_get_page(vcpu, table_gfn, addr, it.level-1, | |
429 | false, access, it.sptep); | |
5991b332 | 430 | } |
0b3c9333 AK |
431 | |
432 | /* | |
433 | * Verify that the gpte in the page we've just write | |
434 | * protected is still there. | |
435 | */ | |
24157aaf | 436 | if (FNAME(gpte_changed)(vcpu, gw, it.level - 1)) |
0b3c9333 | 437 | goto out_gpte_changed; |
abb9e0b8 | 438 | |
5991b332 | 439 | if (sp) |
24157aaf | 440 | link_shadow_page(it.sptep, sp); |
e7a04c99 | 441 | } |
050e6499 | 442 | |
0b3c9333 | 443 | for (; |
24157aaf AK |
444 | shadow_walk_okay(&it) && it.level > hlevel; |
445 | shadow_walk_next(&it)) { | |
0b3c9333 AK |
446 | gfn_t direct_gfn; |
447 | ||
24157aaf | 448 | validate_direct_spte(vcpu, it.sptep, direct_access); |
0b3c9333 | 449 | |
24157aaf | 450 | drop_large_spte(vcpu, it.sptep); |
0b3c9333 | 451 | |
24157aaf | 452 | if (is_shadow_present_pte(*it.sptep)) |
0b3c9333 AK |
453 | continue; |
454 | ||
24157aaf | 455 | direct_gfn = gw->gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1); |
0b3c9333 | 456 | |
24157aaf AK |
457 | sp = kvm_mmu_get_page(vcpu, direct_gfn, addr, it.level-1, |
458 | true, direct_access, it.sptep); | |
459 | link_shadow_page(it.sptep, sp); | |
0b3c9333 AK |
460 | } |
461 | ||
24157aaf AK |
462 | mmu_set_spte(vcpu, it.sptep, access, gw->pte_access & access, |
463 | user_fault, write_fault, dirty, ptwrite, it.level, | |
0b3c9333 | 464 | gw->gfn, pfn, false, true); |
957ed9ef | 465 | FNAME(pte_prefetch)(vcpu, it.sptep); |
0b3c9333 | 466 | |
24157aaf | 467 | return it.sptep; |
0b3c9333 AK |
468 | |
469 | out_gpte_changed: | |
5991b332 | 470 | if (sp) |
24157aaf | 471 | kvm_mmu_put_page(sp, it.sptep); |
0b3c9333 AK |
472 | kvm_release_pfn_clean(pfn); |
473 | return NULL; | |
6aa8b732 AK |
474 | } |
475 | ||
6aa8b732 AK |
476 | /* |
477 | * Page fault handler. There are several causes for a page fault: | |
478 | * - there is no shadow pte for the guest pte | |
479 | * - write access through a shadow pte marked read only so that we can set | |
480 | * the dirty bit | |
481 | * - write access to a shadow pte marked read only so we can update the page | |
482 | * dirty bitmap, when userspace requests it | |
483 | * - mmio access; in this case we will never install a present shadow pte | |
484 | * - normal guest page fault due to the guest pte marked not present, not | |
485 | * writable, or not executable | |
486 | * | |
e2dec939 AK |
487 | * Returns: 1 if we need to emulate the instruction, 0 otherwise, or |
488 | * a negative value on error. | |
6aa8b732 AK |
489 | */ |
490 | static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr, | |
491 | u32 error_code) | |
492 | { | |
493 | int write_fault = error_code & PFERR_WRITE_MASK; | |
6aa8b732 | 494 | int user_fault = error_code & PFERR_USER_MASK; |
73b1087e | 495 | int fetch_fault = error_code & PFERR_FETCH_MASK; |
6aa8b732 | 496 | struct guest_walker walker; |
d555c333 | 497 | u64 *sptep; |
cea0f0e7 | 498 | int write_pt = 0; |
e2dec939 | 499 | int r; |
35149e21 | 500 | pfn_t pfn; |
7e4e4056 | 501 | int level = PT_PAGE_TABLE_LEVEL; |
e930bffe | 502 | unsigned long mmu_seq; |
6aa8b732 | 503 | |
b8688d51 | 504 | pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code); |
37a7d8b0 | 505 | kvm_mmu_audit(vcpu, "pre page fault"); |
714b93da | 506 | |
e2dec939 AK |
507 | r = mmu_topup_memory_caches(vcpu); |
508 | if (r) | |
509 | return r; | |
714b93da | 510 | |
6aa8b732 | 511 | /* |
a8b876b1 | 512 | * Look up the guest pte for the faulting address. |
6aa8b732 | 513 | */ |
73b1087e AK |
514 | r = FNAME(walk_addr)(&walker, vcpu, addr, write_fault, user_fault, |
515 | fetch_fault); | |
6aa8b732 AK |
516 | |
517 | /* | |
518 | * The page is not mapped by the guest. Let the guest handle it. | |
519 | */ | |
7993ba43 | 520 | if (!r) { |
b8688d51 | 521 | pgprintk("%s: guest page fault\n", __func__); |
7993ba43 | 522 | inject_page_fault(vcpu, addr, walker.error_code); |
ad312c7c | 523 | vcpu->arch.last_pt_write_count = 0; /* reset fork detector */ |
6aa8b732 AK |
524 | return 0; |
525 | } | |
526 | ||
7e4e4056 JR |
527 | if (walker.level >= PT_DIRECTORY_LEVEL) { |
528 | level = min(walker.level, mapping_level(vcpu, walker.gfn)); | |
529 | walker.gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1); | |
05da4558 | 530 | } |
7e4e4056 | 531 | |
e930bffe | 532 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 533 | smp_rmb(); |
35149e21 | 534 | pfn = gfn_to_pfn(vcpu->kvm, walker.gfn); |
d7824fff | 535 | |
d196e343 | 536 | /* mmio */ |
bf998156 HY |
537 | if (is_error_pfn(pfn)) |
538 | return kvm_handle_bad_page(vcpu->kvm, walker.gfn, pfn); | |
d196e343 | 539 | |
aaee2c94 | 540 | spin_lock(&vcpu->kvm->mmu_lock); |
e930bffe AA |
541 | if (mmu_notifier_retry(vcpu, mmu_seq)) |
542 | goto out_unlock; | |
eb787d10 | 543 | kvm_mmu_free_some_pages(vcpu); |
d555c333 | 544 | sptep = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault, |
7e4e4056 | 545 | level, &write_pt, pfn); |
a24e8099 | 546 | (void)sptep; |
b8688d51 | 547 | pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __func__, |
d555c333 | 548 | sptep, *sptep, write_pt); |
cea0f0e7 | 549 | |
a25f7e1f | 550 | if (!write_pt) |
ad312c7c | 551 | vcpu->arch.last_pt_write_count = 0; /* reset fork detector */ |
a25f7e1f | 552 | |
1165f5fe | 553 | ++vcpu->stat.pf_fixed; |
37a7d8b0 | 554 | kvm_mmu_audit(vcpu, "post page fault (fixed)"); |
aaee2c94 | 555 | spin_unlock(&vcpu->kvm->mmu_lock); |
6aa8b732 | 556 | |
cea0f0e7 | 557 | return write_pt; |
e930bffe AA |
558 | |
559 | out_unlock: | |
560 | spin_unlock(&vcpu->kvm->mmu_lock); | |
561 | kvm_release_pfn_clean(pfn); | |
562 | return 0; | |
6aa8b732 AK |
563 | } |
564 | ||
a461930b | 565 | static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva) |
a7052897 | 566 | { |
a461930b | 567 | struct kvm_shadow_walk_iterator iterator; |
f78978aa | 568 | struct kvm_mmu_page *sp; |
08e850c6 | 569 | gpa_t pte_gpa = -1; |
a461930b AK |
570 | int level; |
571 | u64 *sptep; | |
4539b358 | 572 | int need_flush = 0; |
a461930b AK |
573 | |
574 | spin_lock(&vcpu->kvm->mmu_lock); | |
a7052897 | 575 | |
a461930b AK |
576 | for_each_shadow_entry(vcpu, gva, iterator) { |
577 | level = iterator.level; | |
578 | sptep = iterator.sptep; | |
ad218f85 | 579 | |
f78978aa | 580 | sp = page_header(__pa(sptep)); |
884a0ff0 | 581 | if (is_last_spte(*sptep, level)) { |
22c9b2d1 | 582 | int offset, shift; |
08e850c6 | 583 | |
f78978aa XG |
584 | if (!sp->unsync) |
585 | break; | |
586 | ||
22c9b2d1 XG |
587 | shift = PAGE_SHIFT - |
588 | (PT_LEVEL_BITS - PT64_LEVEL_BITS) * level; | |
589 | offset = sp->role.quadrant << shift; | |
590 | ||
591 | pte_gpa = (sp->gfn << PAGE_SHIFT) + offset; | |
08e850c6 | 592 | pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t); |
a461930b AK |
593 | |
594 | if (is_shadow_present_pte(*sptep)) { | |
a461930b AK |
595 | if (is_large_pte(*sptep)) |
596 | --vcpu->kvm->stat.lpages; | |
be38d276 AK |
597 | drop_spte(vcpu->kvm, sptep, |
598 | shadow_trap_nonpresent_pte); | |
4539b358 | 599 | need_flush = 1; |
be38d276 AK |
600 | } else |
601 | __set_spte(sptep, shadow_trap_nonpresent_pte); | |
a461930b | 602 | break; |
87917239 | 603 | } |
a7052897 | 604 | |
f78978aa | 605 | if (!is_shadow_present_pte(*sptep) || !sp->unsync_children) |
a461930b AK |
606 | break; |
607 | } | |
a7052897 | 608 | |
4539b358 AA |
609 | if (need_flush) |
610 | kvm_flush_remote_tlbs(vcpu->kvm); | |
08e850c6 AK |
611 | |
612 | atomic_inc(&vcpu->kvm->arch.invlpg_counter); | |
613 | ||
ad218f85 | 614 | spin_unlock(&vcpu->kvm->mmu_lock); |
08e850c6 AK |
615 | |
616 | if (pte_gpa == -1) | |
617 | return; | |
618 | ||
619 | if (mmu_topup_memory_caches(vcpu)) | |
620 | return; | |
621 | kvm_mmu_pte_write(vcpu, pte_gpa, NULL, sizeof(pt_element_t), 0); | |
a7052897 MT |
622 | } |
623 | ||
1871c602 GN |
624 | static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr, u32 access, |
625 | u32 *error) | |
6aa8b732 AK |
626 | { |
627 | struct guest_walker walker; | |
e119d117 AK |
628 | gpa_t gpa = UNMAPPED_GVA; |
629 | int r; | |
6aa8b732 | 630 | |
1871c602 GN |
631 | r = FNAME(walk_addr)(&walker, vcpu, vaddr, |
632 | !!(access & PFERR_WRITE_MASK), | |
633 | !!(access & PFERR_USER_MASK), | |
634 | !!(access & PFERR_FETCH_MASK)); | |
6aa8b732 | 635 | |
e119d117 | 636 | if (r) { |
1755fbcc | 637 | gpa = gfn_to_gpa(walker.gfn); |
e119d117 | 638 | gpa |= vaddr & ~PAGE_MASK; |
1871c602 GN |
639 | } else if (error) |
640 | *error = walker.error_code; | |
6aa8b732 AK |
641 | |
642 | return gpa; | |
643 | } | |
644 | ||
c7addb90 AK |
645 | static void FNAME(prefetch_page)(struct kvm_vcpu *vcpu, |
646 | struct kvm_mmu_page *sp) | |
647 | { | |
eab9f71f AK |
648 | int i, j, offset, r; |
649 | pt_element_t pt[256 / sizeof(pt_element_t)]; | |
650 | gpa_t pte_gpa; | |
c7addb90 | 651 | |
f6e2c02b | 652 | if (sp->role.direct |
e5a4c8ca | 653 | || (PTTYPE == 32 && sp->role.level > PT_PAGE_TABLE_LEVEL)) { |
c7addb90 AK |
654 | nonpaging_prefetch_page(vcpu, sp); |
655 | return; | |
656 | } | |
657 | ||
eab9f71f AK |
658 | pte_gpa = gfn_to_gpa(sp->gfn); |
659 | if (PTTYPE == 32) { | |
e5a4c8ca | 660 | offset = sp->role.quadrant << PT64_LEVEL_BITS; |
eab9f71f AK |
661 | pte_gpa += offset * sizeof(pt_element_t); |
662 | } | |
7ec54588 | 663 | |
eab9f71f AK |
664 | for (i = 0; i < PT64_ENT_PER_PAGE; i += ARRAY_SIZE(pt)) { |
665 | r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa, pt, sizeof pt); | |
666 | pte_gpa += ARRAY_SIZE(pt) * sizeof(pt_element_t); | |
667 | for (j = 0; j < ARRAY_SIZE(pt); ++j) | |
43a3795a | 668 | if (r || is_present_gpte(pt[j])) |
eab9f71f AK |
669 | sp->spt[i+j] = shadow_trap_nonpresent_pte; |
670 | else | |
671 | sp->spt[i+j] = shadow_notrap_nonpresent_pte; | |
7ec54588 | 672 | } |
c7addb90 AK |
673 | } |
674 | ||
e8bc217a MT |
675 | /* |
676 | * Using the cached information from sp->gfns is safe because: | |
677 | * - The spte has a reference to the struct page, so the pfn for a given gfn | |
678 | * can't change unless all sptes pointing to it are nuked first. | |
e8bc217a | 679 | */ |
be71e061 XG |
680 | static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
681 | bool clear_unsync) | |
e8bc217a MT |
682 | { |
683 | int i, offset, nr_present; | |
1403283a | 684 | bool reset_host_protection; |
51fb60d8 | 685 | gpa_t first_pte_gpa; |
e8bc217a MT |
686 | |
687 | offset = nr_present = 0; | |
688 | ||
2032a93d LJ |
689 | /* direct kvm_mmu_page can not be unsync. */ |
690 | BUG_ON(sp->role.direct); | |
691 | ||
e8bc217a MT |
692 | if (PTTYPE == 32) |
693 | offset = sp->role.quadrant << PT64_LEVEL_BITS; | |
694 | ||
51fb60d8 GJ |
695 | first_pte_gpa = gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t); |
696 | ||
e8bc217a MT |
697 | for (i = 0; i < PT64_ENT_PER_PAGE; i++) { |
698 | unsigned pte_access; | |
699 | pt_element_t gpte; | |
700 | gpa_t pte_gpa; | |
f55c3f41 | 701 | gfn_t gfn; |
e8bc217a MT |
702 | |
703 | if (!is_shadow_present_pte(sp->spt[i])) | |
704 | continue; | |
705 | ||
51fb60d8 | 706 | pte_gpa = first_pte_gpa + i * sizeof(pt_element_t); |
e8bc217a MT |
707 | |
708 | if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte, | |
709 | sizeof(pt_element_t))) | |
710 | return -EINVAL; | |
711 | ||
f55c3f41 | 712 | gfn = gpte_to_gfn(gpte); |
fa1de2bf XG |
713 | if (is_rsvd_bits_set(vcpu, gpte, PT_PAGE_TABLE_LEVEL) |
714 | || gfn != sp->gfns[i] || !is_present_gpte(gpte) | |
715 | || !(gpte & PT_ACCESSED_MASK)) { | |
e8bc217a MT |
716 | u64 nonpresent; |
717 | ||
be71e061 | 718 | if (is_present_gpte(gpte) || !clear_unsync) |
e8bc217a MT |
719 | nonpresent = shadow_trap_nonpresent_pte; |
720 | else | |
721 | nonpresent = shadow_notrap_nonpresent_pte; | |
be38d276 | 722 | drop_spte(vcpu->kvm, &sp->spt[i], nonpresent); |
e8bc217a MT |
723 | continue; |
724 | } | |
725 | ||
726 | nr_present++; | |
727 | pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte); | |
1403283a IE |
728 | if (!(sp->spt[i] & SPTE_HOST_WRITEABLE)) { |
729 | pte_access &= ~ACC_WRITE_MASK; | |
730 | reset_host_protection = 0; | |
731 | } else { | |
732 | reset_host_protection = 1; | |
733 | } | |
e8bc217a | 734 | set_spte(vcpu, &sp->spt[i], pte_access, 0, 0, |
7e4e4056 | 735 | is_dirty_gpte(gpte), PT_PAGE_TABLE_LEVEL, gfn, |
1403283a IE |
736 | spte_to_pfn(sp->spt[i]), true, false, |
737 | reset_host_protection); | |
e8bc217a MT |
738 | } |
739 | ||
740 | return !nr_present; | |
741 | } | |
742 | ||
6aa8b732 AK |
743 | #undef pt_element_t |
744 | #undef guest_walker | |
745 | #undef FNAME | |
746 | #undef PT_BASE_ADDR_MASK | |
747 | #undef PT_INDEX | |
6aa8b732 | 748 | #undef PT_LEVEL_MASK |
e04da980 JR |
749 | #undef PT_LVL_ADDR_MASK |
750 | #undef PT_LVL_OFFSET_MASK | |
c7addb90 | 751 | #undef PT_LEVEL_BITS |
cea0f0e7 | 752 | #undef PT_MAX_FULL_LEVELS |
5fb07ddb | 753 | #undef gpte_to_gfn |
e04da980 | 754 | #undef gpte_to_gfn_lvl |
b3e4e63f | 755 | #undef CMPXCHG |