Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * MMU support | |
8 | * | |
9 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 10 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
11 | * |
12 | * Authors: | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * | |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | * | |
19 | */ | |
20 | ||
21 | /* | |
22 | * We need the mmu code to access both 32-bit and 64-bit guest ptes, | |
23 | * so the code in this file is compiled twice, once per pte size. | |
24 | */ | |
25 | ||
26 | #if PTTYPE == 64 | |
27 | #define pt_element_t u64 | |
28 | #define guest_walker guest_walker64 | |
29 | #define FNAME(name) paging##64_##name | |
30 | #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK | |
e04da980 JR |
31 | #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl) |
32 | #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl) | |
6aa8b732 | 33 | #define PT_INDEX(addr, level) PT64_INDEX(addr, level) |
c7addb90 | 34 | #define PT_LEVEL_BITS PT64_LEVEL_BITS |
cea0f0e7 AK |
35 | #ifdef CONFIG_X86_64 |
36 | #define PT_MAX_FULL_LEVELS 4 | |
b3e4e63f | 37 | #define CMPXCHG cmpxchg |
cea0f0e7 | 38 | #else |
b3e4e63f | 39 | #define CMPXCHG cmpxchg64 |
cea0f0e7 AK |
40 | #define PT_MAX_FULL_LEVELS 2 |
41 | #endif | |
6aa8b732 AK |
42 | #elif PTTYPE == 32 |
43 | #define pt_element_t u32 | |
44 | #define guest_walker guest_walker32 | |
45 | #define FNAME(name) paging##32_##name | |
46 | #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK | |
e04da980 JR |
47 | #define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl) |
48 | #define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl) | |
6aa8b732 | 49 | #define PT_INDEX(addr, level) PT32_INDEX(addr, level) |
c7addb90 | 50 | #define PT_LEVEL_BITS PT32_LEVEL_BITS |
cea0f0e7 | 51 | #define PT_MAX_FULL_LEVELS 2 |
b3e4e63f | 52 | #define CMPXCHG cmpxchg |
6aa8b732 AK |
53 | #else |
54 | #error Invalid PTTYPE value | |
55 | #endif | |
56 | ||
e04da980 JR |
57 | #define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl) |
58 | #define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PT_PAGE_TABLE_LEVEL) | |
5fb07ddb | 59 | |
6aa8b732 AK |
60 | /* |
61 | * The guest_walker structure emulates the behavior of the hardware page | |
62 | * table walker. | |
63 | */ | |
64 | struct guest_walker { | |
65 | int level; | |
8cbc7069 | 66 | unsigned max_level; |
cea0f0e7 | 67 | gfn_t table_gfn[PT_MAX_FULL_LEVELS]; |
7819026e | 68 | pt_element_t ptes[PT_MAX_FULL_LEVELS]; |
189be38d | 69 | pt_element_t prefetch_ptes[PTE_PREFETCH_NUM]; |
7819026e | 70 | gpa_t pte_gpa[PT_MAX_FULL_LEVELS]; |
8cbc7069 | 71 | pt_element_t __user *ptep_user[PT_MAX_FULL_LEVELS]; |
fe135d2c AK |
72 | unsigned pt_access; |
73 | unsigned pte_access; | |
815af8d4 | 74 | gfn_t gfn; |
8c28d031 | 75 | struct x86_exception fault; |
6aa8b732 AK |
76 | }; |
77 | ||
e04da980 | 78 | static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl) |
5fb07ddb | 79 | { |
e04da980 | 80 | return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT; |
5fb07ddb AK |
81 | } |
82 | ||
a78484c6 | 83 | static int FNAME(cmpxchg_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, |
c8cfbb55 TY |
84 | pt_element_t __user *ptep_user, unsigned index, |
85 | pt_element_t orig_pte, pt_element_t new_pte) | |
b3e4e63f | 86 | { |
c8cfbb55 | 87 | int npages; |
b3e4e63f MT |
88 | pt_element_t ret; |
89 | pt_element_t *table; | |
90 | struct page *page; | |
91 | ||
c8cfbb55 TY |
92 | npages = get_user_pages_fast((unsigned long)ptep_user, 1, 1, &page); |
93 | /* Check if the user is doing something meaningless. */ | |
94 | if (unlikely(npages != 1)) | |
a78484c6 RJ |
95 | return -EFAULT; |
96 | ||
8fd75e12 | 97 | table = kmap_atomic(page); |
b3e4e63f | 98 | ret = CMPXCHG(&table[index], orig_pte, new_pte); |
8fd75e12 | 99 | kunmap_atomic(table); |
b3e4e63f MT |
100 | |
101 | kvm_release_page_dirty(page); | |
102 | ||
103 | return (ret != orig_pte); | |
104 | } | |
105 | ||
8cbc7069 AK |
106 | static int FNAME(update_accessed_dirty_bits)(struct kvm_vcpu *vcpu, |
107 | struct kvm_mmu *mmu, | |
108 | struct guest_walker *walker, | |
109 | int write_fault) | |
110 | { | |
111 | unsigned level, index; | |
112 | pt_element_t pte, orig_pte; | |
113 | pt_element_t __user *ptep_user; | |
114 | gfn_t table_gfn; | |
115 | int ret; | |
116 | ||
117 | for (level = walker->max_level; level >= walker->level; --level) { | |
118 | pte = orig_pte = walker->ptes[level - 1]; | |
119 | table_gfn = walker->table_gfn[level - 1]; | |
120 | ptep_user = walker->ptep_user[level - 1]; | |
121 | index = offset_in_page(ptep_user) / sizeof(pt_element_t); | |
122 | if (!(pte & PT_ACCESSED_MASK)) { | |
123 | trace_kvm_mmu_set_accessed_bit(table_gfn, index, sizeof(pte)); | |
124 | pte |= PT_ACCESSED_MASK; | |
125 | } | |
126 | if (level == walker->level && write_fault && !is_dirty_gpte(pte)) { | |
127 | trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte)); | |
128 | pte |= PT_DIRTY_MASK; | |
129 | } | |
130 | if (pte == orig_pte) | |
131 | continue; | |
132 | ||
133 | ret = FNAME(cmpxchg_gpte)(vcpu, mmu, ptep_user, index, orig_pte, pte); | |
134 | if (ret) | |
135 | return ret; | |
136 | ||
137 | mark_page_dirty(vcpu->kvm, table_gfn); | |
138 | walker->ptes[level] = pte; | |
139 | } | |
140 | return 0; | |
141 | } | |
142 | ||
ac79c978 AK |
143 | /* |
144 | * Fetch a guest pte for a guest virtual address | |
145 | */ | |
1e301feb JR |
146 | static int FNAME(walk_addr_generic)(struct guest_walker *walker, |
147 | struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
33770780 | 148 | gva_t addr, u32 access) |
6aa8b732 | 149 | { |
8cbc7069 | 150 | int ret; |
42bf3f0a | 151 | pt_element_t pte; |
b7233635 | 152 | pt_element_t __user *uninitialized_var(ptep_user); |
cea0f0e7 | 153 | gfn_t table_gfn; |
b514c30f | 154 | unsigned index, pt_access, pte_access, accessed_dirty, shift; |
42bf3f0a | 155 | gpa_t pte_gpa; |
134291bf TY |
156 | int offset; |
157 | const int write_fault = access & PFERR_WRITE_MASK; | |
158 | const int user_fault = access & PFERR_USER_MASK; | |
159 | const int fetch_fault = access & PFERR_FETCH_MASK; | |
160 | u16 errcode = 0; | |
13d22b6a AK |
161 | gpa_t real_gpa; |
162 | gfn_t gfn; | |
163 | u32 ac; | |
6aa8b732 | 164 | |
6fbc2770 | 165 | trace_kvm_mmu_pagetable_walk(addr, access); |
92c1c1e8 | 166 | retry_walk: |
1e301feb JR |
167 | walker->level = mmu->root_level; |
168 | pte = mmu->get_cr3(vcpu); | |
169 | ||
1b0973bd | 170 | #if PTTYPE == 64 |
1e301feb | 171 | if (walker->level == PT32E_ROOT_LEVEL) { |
e4e517b4 | 172 | pte = mmu->get_pdptr(vcpu, (addr >> 30) & 3); |
07420171 | 173 | trace_kvm_mmu_paging_element(pte, walker->level); |
134291bf | 174 | if (!is_present_gpte(pte)) |
f59c1d2d | 175 | goto error; |
1b0973bd AK |
176 | --walker->level; |
177 | } | |
178 | #endif | |
8cbc7069 | 179 | walker->max_level = walker->level; |
a9058ecd | 180 | ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) || |
1e301feb | 181 | (mmu->get_cr3(vcpu) & CR3_NONPAE_RESERVED_BITS) == 0); |
6aa8b732 | 182 | |
b514c30f | 183 | accessed_dirty = PT_ACCESSED_MASK; |
13d22b6a AK |
184 | pt_access = pte_access = ACC_ALL; |
185 | ++walker->level; | |
ac79c978 | 186 | |
13d22b6a | 187 | do { |
6e2ca7d1 TY |
188 | gfn_t real_gfn; |
189 | unsigned long host_addr; | |
190 | ||
13d22b6a AK |
191 | pt_access &= pte_access; |
192 | --walker->level; | |
193 | ||
42bf3f0a | 194 | index = PT_INDEX(addr, walker->level); |
ac79c978 | 195 | |
5fb07ddb | 196 | table_gfn = gpte_to_gfn(pte); |
2329d46d JR |
197 | offset = index * sizeof(pt_element_t); |
198 | pte_gpa = gfn_to_gpa(table_gfn) + offset; | |
42bf3f0a | 199 | walker->table_gfn[walker->level - 1] = table_gfn; |
7819026e | 200 | walker->pte_gpa[walker->level - 1] = pte_gpa; |
42bf3f0a | 201 | |
6e2ca7d1 TY |
202 | real_gfn = mmu->translate_gpa(vcpu, gfn_to_gpa(table_gfn), |
203 | PFERR_USER_MASK|PFERR_WRITE_MASK); | |
134291bf TY |
204 | if (unlikely(real_gfn == UNMAPPED_GVA)) |
205 | goto error; | |
6e2ca7d1 TY |
206 | real_gfn = gpa_to_gfn(real_gfn); |
207 | ||
208 | host_addr = gfn_to_hva(vcpu->kvm, real_gfn); | |
134291bf TY |
209 | if (unlikely(kvm_is_error_hva(host_addr))) |
210 | goto error; | |
6e2ca7d1 TY |
211 | |
212 | ptep_user = (pt_element_t __user *)((void *)host_addr + offset); | |
134291bf TY |
213 | if (unlikely(__copy_from_user(&pte, ptep_user, sizeof(pte)))) |
214 | goto error; | |
8cbc7069 | 215 | walker->ptep_user[walker->level - 1] = ptep_user; |
a6085fba | 216 | |
07420171 | 217 | trace_kvm_mmu_paging_element(pte, walker->level); |
42bf3f0a | 218 | |
134291bf TY |
219 | if (unlikely(!is_present_gpte(pte))) |
220 | goto error; | |
7993ba43 | 221 | |
781e0743 AK |
222 | if (unlikely(is_rsvd_bits_set(&vcpu->arch.mmu, pte, |
223 | walker->level))) { | |
134291bf TY |
224 | errcode |= PFERR_RSVD_MASK | PFERR_PRESENT_MASK; |
225 | goto error; | |
f59c1d2d | 226 | } |
82725b20 | 227 | |
b514c30f | 228 | accessed_dirty &= pte; |
97d64b78 | 229 | pte_access = pt_access & gpte_access(vcpu, pte); |
73b1087e | 230 | |
7819026e | 231 | walker->ptes[walker->level - 1] = pte; |
6fd01b71 | 232 | } while (!is_last_gpte(mmu, walker->level, pte)); |
42bf3f0a | 233 | |
71331a1d | 234 | if (unlikely(permission_fault(mmu, pte_access, access))) { |
134291bf | 235 | errcode |= PFERR_PRESENT_MASK; |
f59c1d2d | 236 | goto error; |
134291bf | 237 | } |
f59c1d2d | 238 | |
13d22b6a AK |
239 | gfn = gpte_to_gfn_lvl(pte, walker->level); |
240 | gfn += (addr & PT_LVL_OFFSET_MASK(walker->level)) >> PAGE_SHIFT; | |
241 | ||
242 | if (PTTYPE == 32 && walker->level == PT_DIRECTORY_LEVEL && is_cpuid_PSE36()) | |
243 | gfn += pse36_gfn_delta(pte); | |
244 | ||
245 | ac = write_fault | fetch_fault | user_fault; | |
246 | ||
247 | real_gpa = mmu->translate_gpa(vcpu, gfn_to_gpa(gfn), ac); | |
248 | if (real_gpa == UNMAPPED_GVA) | |
249 | return 0; | |
250 | ||
251 | walker->gfn = real_gpa >> PAGE_SHIFT; | |
252 | ||
8ea667f2 AK |
253 | if (!write_fault) |
254 | protect_clean_gpte(&pte_access, pte); | |
a78484c6 | 255 | |
b514c30f AK |
256 | /* |
257 | * On a write fault, fold the dirty bit into accessed_dirty by shifting it one | |
258 | * place right. | |
259 | * | |
260 | * On a read fault, do nothing. | |
261 | */ | |
262 | shift = write_fault >> ilog2(PFERR_WRITE_MASK); | |
263 | shift *= PT_DIRTY_SHIFT - PT_ACCESSED_SHIFT; | |
264 | accessed_dirty &= pte >> shift; | |
265 | ||
266 | if (unlikely(!accessed_dirty)) { | |
267 | ret = FNAME(update_accessed_dirty_bits)(vcpu, mmu, walker, write_fault); | |
268 | if (unlikely(ret < 0)) | |
269 | goto error; | |
270 | else if (ret) | |
271 | goto retry_walk; | |
272 | } | |
42bf3f0a | 273 | |
fe135d2c AK |
274 | walker->pt_access = pt_access; |
275 | walker->pte_access = pte_access; | |
276 | pgprintk("%s: pte %llx pte_access %x pt_access %x\n", | |
518c5a05 | 277 | __func__, (u64)pte, pte_access, pt_access); |
7993ba43 AK |
278 | return 1; |
279 | ||
f59c1d2d | 280 | error: |
134291bf | 281 | errcode |= write_fault | user_fault; |
e57d4a35 YW |
282 | if (fetch_fault && (mmu->nx || |
283 | kvm_read_cr4_bits(vcpu, X86_CR4_SMEP))) | |
134291bf | 284 | errcode |= PFERR_FETCH_MASK; |
8df25a32 | 285 | |
134291bf TY |
286 | walker->fault.vector = PF_VECTOR; |
287 | walker->fault.error_code_valid = true; | |
288 | walker->fault.error_code = errcode; | |
6389ee94 AK |
289 | walker->fault.address = addr; |
290 | walker->fault.nested_page_fault = mmu != vcpu->arch.walk_mmu; | |
8df25a32 | 291 | |
8c28d031 | 292 | trace_kvm_mmu_walker_error(walker->fault.error_code); |
fe551881 | 293 | return 0; |
6aa8b732 AK |
294 | } |
295 | ||
1e301feb | 296 | static int FNAME(walk_addr)(struct guest_walker *walker, |
33770780 | 297 | struct kvm_vcpu *vcpu, gva_t addr, u32 access) |
1e301feb JR |
298 | { |
299 | return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.mmu, addr, | |
33770780 | 300 | access); |
1e301feb JR |
301 | } |
302 | ||
6539e738 JR |
303 | static int FNAME(walk_addr_nested)(struct guest_walker *walker, |
304 | struct kvm_vcpu *vcpu, gva_t addr, | |
33770780 | 305 | u32 access) |
6539e738 JR |
306 | { |
307 | return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.nested_mmu, | |
33770780 | 308 | addr, access); |
6539e738 JR |
309 | } |
310 | ||
407c61c6 XG |
311 | static bool FNAME(prefetch_invalid_gpte)(struct kvm_vcpu *vcpu, |
312 | struct kvm_mmu_page *sp, u64 *spte, | |
313 | pt_element_t gpte) | |
314 | { | |
407c61c6 XG |
315 | if (is_rsvd_bits_set(&vcpu->arch.mmu, gpte, PT_PAGE_TABLE_LEVEL)) |
316 | goto no_present; | |
317 | ||
c3707958 | 318 | if (!is_present_gpte(gpte)) |
407c61c6 | 319 | goto no_present; |
407c61c6 XG |
320 | |
321 | if (!(gpte & PT_ACCESSED_MASK)) | |
322 | goto no_present; | |
323 | ||
324 | return false; | |
325 | ||
326 | no_present: | |
c3707958 | 327 | drop_spte(vcpu->kvm, spte); |
407c61c6 XG |
328 | return true; |
329 | } | |
330 | ||
ac3cd03c | 331 | static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
7c562522 | 332 | u64 *spte, const void *pte) |
0028425f AK |
333 | { |
334 | pt_element_t gpte; | |
41074d07 | 335 | unsigned pte_access; |
35149e21 | 336 | pfn_t pfn; |
0028425f | 337 | |
0028425f | 338 | gpte = *(const pt_element_t *)pte; |
407c61c6 | 339 | if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte)) |
c7addb90 | 340 | return; |
407c61c6 | 341 | |
b8688d51 | 342 | pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte); |
3d34adec | 343 | pte_access = sp->role.access & gpte_access(vcpu, gpte); |
8ea667f2 | 344 | protect_clean_gpte(&pte_access, gpte); |
0f53b5b1 | 345 | pfn = gfn_to_pfn_atomic(vcpu->kvm, gpte_to_gfn(gpte)); |
cb9aaa30 | 346 | if (mmu_invalid_pfn(pfn)) |
d7824fff | 347 | return; |
0f53b5b1 | 348 | |
1403283a | 349 | /* |
0d2eb44f | 350 | * we call mmu_set_spte() with host_writable = true because that |
1403283a IE |
351 | * vcpu->arch.update_pte.pfn was fetched from get_user_pages(write = 1). |
352 | */ | |
ac3cd03c | 353 | mmu_set_spte(vcpu, spte, sp->role.access, pte_access, 0, 0, |
640d9b0d | 354 | NULL, PT_PAGE_TABLE_LEVEL, |
1403283a | 355 | gpte_to_gfn(gpte), pfn, true, true); |
0028425f AK |
356 | } |
357 | ||
39c8c672 AK |
358 | static bool FNAME(gpte_changed)(struct kvm_vcpu *vcpu, |
359 | struct guest_walker *gw, int level) | |
360 | { | |
39c8c672 | 361 | pt_element_t curr_pte; |
189be38d XG |
362 | gpa_t base_gpa, pte_gpa = gw->pte_gpa[level - 1]; |
363 | u64 mask; | |
364 | int r, index; | |
365 | ||
366 | if (level == PT_PAGE_TABLE_LEVEL) { | |
367 | mask = PTE_PREFETCH_NUM * sizeof(pt_element_t) - 1; | |
368 | base_gpa = pte_gpa & ~mask; | |
369 | index = (pte_gpa - base_gpa) / sizeof(pt_element_t); | |
370 | ||
371 | r = kvm_read_guest_atomic(vcpu->kvm, base_gpa, | |
372 | gw->prefetch_ptes, sizeof(gw->prefetch_ptes)); | |
373 | curr_pte = gw->prefetch_ptes[index]; | |
374 | } else | |
375 | r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa, | |
39c8c672 | 376 | &curr_pte, sizeof(curr_pte)); |
189be38d | 377 | |
39c8c672 AK |
378 | return r || curr_pte != gw->ptes[level - 1]; |
379 | } | |
380 | ||
189be38d XG |
381 | static void FNAME(pte_prefetch)(struct kvm_vcpu *vcpu, struct guest_walker *gw, |
382 | u64 *sptep) | |
957ed9ef XG |
383 | { |
384 | struct kvm_mmu_page *sp; | |
189be38d | 385 | pt_element_t *gptep = gw->prefetch_ptes; |
957ed9ef | 386 | u64 *spte; |
189be38d | 387 | int i; |
957ed9ef XG |
388 | |
389 | sp = page_header(__pa(sptep)); | |
390 | ||
391 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) | |
392 | return; | |
393 | ||
394 | if (sp->role.direct) | |
395 | return __direct_pte_prefetch(vcpu, sp, sptep); | |
396 | ||
397 | i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1); | |
957ed9ef XG |
398 | spte = sp->spt + i; |
399 | ||
400 | for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) { | |
401 | pt_element_t gpte; | |
402 | unsigned pte_access; | |
403 | gfn_t gfn; | |
404 | pfn_t pfn; | |
957ed9ef XG |
405 | |
406 | if (spte == sptep) | |
407 | continue; | |
408 | ||
c3707958 | 409 | if (is_shadow_present_pte(*spte)) |
957ed9ef XG |
410 | continue; |
411 | ||
412 | gpte = gptep[i]; | |
413 | ||
407c61c6 | 414 | if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte)) |
957ed9ef XG |
415 | continue; |
416 | ||
3d34adec | 417 | pte_access = sp->role.access & gpte_access(vcpu, gpte); |
8ea667f2 | 418 | protect_clean_gpte(&pte_access, gpte); |
957ed9ef | 419 | gfn = gpte_to_gfn(gpte); |
957ed9ef | 420 | pfn = pte_prefetch_gfn_to_pfn(vcpu, gfn, |
640d9b0d | 421 | pte_access & ACC_WRITE_MASK); |
cb9aaa30 | 422 | if (mmu_invalid_pfn(pfn)) |
957ed9ef | 423 | break; |
957ed9ef XG |
424 | |
425 | mmu_set_spte(vcpu, spte, sp->role.access, pte_access, 0, 0, | |
640d9b0d | 426 | NULL, PT_PAGE_TABLE_LEVEL, gfn, |
957ed9ef XG |
427 | pfn, true, true); |
428 | } | |
429 | } | |
430 | ||
6aa8b732 AK |
431 | /* |
432 | * Fetch a shadow pte for a specific level in the paging hierarchy. | |
433 | */ | |
e7a04c99 AK |
434 | static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr, |
435 | struct guest_walker *gw, | |
7e4e4056 | 436 | int user_fault, int write_fault, int hlevel, |
b90a0e6c | 437 | int *emulate, pfn_t pfn, bool map_writable, |
fb67e14f | 438 | bool prefault) |
6aa8b732 | 439 | { |
abb9e0b8 | 440 | unsigned access = gw->pt_access; |
5991b332 | 441 | struct kvm_mmu_page *sp = NULL; |
5991b332 | 442 | int top_level; |
84754cd8 | 443 | unsigned direct_access; |
24157aaf | 444 | struct kvm_shadow_walk_iterator it; |
abb9e0b8 | 445 | |
43a3795a | 446 | if (!is_present_gpte(gw->ptes[gw->level - 1])) |
e7a04c99 | 447 | return NULL; |
6aa8b732 | 448 | |
b36c7a7c | 449 | direct_access = gw->pte_access; |
84754cd8 | 450 | |
5991b332 AK |
451 | top_level = vcpu->arch.mmu.root_level; |
452 | if (top_level == PT32E_ROOT_LEVEL) | |
453 | top_level = PT32_ROOT_LEVEL; | |
454 | /* | |
455 | * Verify that the top-level gpte is still there. Since the page | |
456 | * is a root page, it is either write protected (and cannot be | |
457 | * changed from now on) or it is invalid (in which case, we don't | |
458 | * really care if it changes underneath us after this point). | |
459 | */ | |
460 | if (FNAME(gpte_changed)(vcpu, gw, top_level)) | |
461 | goto out_gpte_changed; | |
462 | ||
24157aaf AK |
463 | for (shadow_walk_init(&it, vcpu, addr); |
464 | shadow_walk_okay(&it) && it.level > gw->level; | |
465 | shadow_walk_next(&it)) { | |
0b3c9333 AK |
466 | gfn_t table_gfn; |
467 | ||
a30f47cb | 468 | clear_sp_write_flooding_count(it.sptep); |
24157aaf | 469 | drop_large_spte(vcpu, it.sptep); |
ef0197e8 | 470 | |
5991b332 | 471 | sp = NULL; |
24157aaf AK |
472 | if (!is_shadow_present_pte(*it.sptep)) { |
473 | table_gfn = gw->table_gfn[it.level - 2]; | |
474 | sp = kvm_mmu_get_page(vcpu, table_gfn, addr, it.level-1, | |
475 | false, access, it.sptep); | |
5991b332 | 476 | } |
0b3c9333 AK |
477 | |
478 | /* | |
479 | * Verify that the gpte in the page we've just write | |
480 | * protected is still there. | |
481 | */ | |
24157aaf | 482 | if (FNAME(gpte_changed)(vcpu, gw, it.level - 1)) |
0b3c9333 | 483 | goto out_gpte_changed; |
abb9e0b8 | 484 | |
5991b332 | 485 | if (sp) |
24157aaf | 486 | link_shadow_page(it.sptep, sp); |
e7a04c99 | 487 | } |
050e6499 | 488 | |
0b3c9333 | 489 | for (; |
24157aaf AK |
490 | shadow_walk_okay(&it) && it.level > hlevel; |
491 | shadow_walk_next(&it)) { | |
0b3c9333 AK |
492 | gfn_t direct_gfn; |
493 | ||
a30f47cb | 494 | clear_sp_write_flooding_count(it.sptep); |
24157aaf | 495 | validate_direct_spte(vcpu, it.sptep, direct_access); |
0b3c9333 | 496 | |
24157aaf | 497 | drop_large_spte(vcpu, it.sptep); |
0b3c9333 | 498 | |
24157aaf | 499 | if (is_shadow_present_pte(*it.sptep)) |
0b3c9333 AK |
500 | continue; |
501 | ||
24157aaf | 502 | direct_gfn = gw->gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1); |
0b3c9333 | 503 | |
24157aaf AK |
504 | sp = kvm_mmu_get_page(vcpu, direct_gfn, addr, it.level-1, |
505 | true, direct_access, it.sptep); | |
506 | link_shadow_page(it.sptep, sp); | |
0b3c9333 AK |
507 | } |
508 | ||
a30f47cb | 509 | clear_sp_write_flooding_count(it.sptep); |
b36c7a7c | 510 | mmu_set_spte(vcpu, it.sptep, access, gw->pte_access, |
b90a0e6c | 511 | user_fault, write_fault, emulate, it.level, |
fb67e14f | 512 | gw->gfn, pfn, prefault, map_writable); |
189be38d | 513 | FNAME(pte_prefetch)(vcpu, gw, it.sptep); |
0b3c9333 | 514 | |
24157aaf | 515 | return it.sptep; |
0b3c9333 AK |
516 | |
517 | out_gpte_changed: | |
5991b332 | 518 | if (sp) |
24157aaf | 519 | kvm_mmu_put_page(sp, it.sptep); |
0b3c9333 AK |
520 | kvm_release_pfn_clean(pfn); |
521 | return NULL; | |
6aa8b732 AK |
522 | } |
523 | ||
6aa8b732 AK |
524 | /* |
525 | * Page fault handler. There are several causes for a page fault: | |
526 | * - there is no shadow pte for the guest pte | |
527 | * - write access through a shadow pte marked read only so that we can set | |
528 | * the dirty bit | |
529 | * - write access to a shadow pte marked read only so we can update the page | |
530 | * dirty bitmap, when userspace requests it | |
531 | * - mmio access; in this case we will never install a present shadow pte | |
532 | * - normal guest page fault due to the guest pte marked not present, not | |
533 | * writable, or not executable | |
534 | * | |
e2dec939 AK |
535 | * Returns: 1 if we need to emulate the instruction, 0 otherwise, or |
536 | * a negative value on error. | |
6aa8b732 | 537 | */ |
56028d08 | 538 | static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr, u32 error_code, |
78b2c54a | 539 | bool prefault) |
6aa8b732 AK |
540 | { |
541 | int write_fault = error_code & PFERR_WRITE_MASK; | |
6aa8b732 AK |
542 | int user_fault = error_code & PFERR_USER_MASK; |
543 | struct guest_walker walker; | |
d555c333 | 544 | u64 *sptep; |
b90a0e6c | 545 | int emulate = 0; |
e2dec939 | 546 | int r; |
35149e21 | 547 | pfn_t pfn; |
7e4e4056 | 548 | int level = PT_PAGE_TABLE_LEVEL; |
936a5fe6 | 549 | int force_pt_level; |
e930bffe | 550 | unsigned long mmu_seq; |
612819c3 | 551 | bool map_writable; |
6aa8b732 | 552 | |
b8688d51 | 553 | pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code); |
714b93da | 554 | |
ce88decf XG |
555 | if (unlikely(error_code & PFERR_RSVD_MASK)) |
556 | return handle_mmio_page_fault(vcpu, addr, error_code, | |
557 | mmu_is_nested(vcpu)); | |
558 | ||
e2dec939 AK |
559 | r = mmu_topup_memory_caches(vcpu); |
560 | if (r) | |
561 | return r; | |
714b93da | 562 | |
6aa8b732 | 563 | /* |
a8b876b1 | 564 | * Look up the guest pte for the faulting address. |
6aa8b732 | 565 | */ |
33770780 | 566 | r = FNAME(walk_addr)(&walker, vcpu, addr, error_code); |
6aa8b732 AK |
567 | |
568 | /* | |
569 | * The page is not mapped by the guest. Let the guest handle it. | |
570 | */ | |
7993ba43 | 571 | if (!r) { |
b8688d51 | 572 | pgprintk("%s: guest page fault\n", __func__); |
a30f47cb | 573 | if (!prefault) |
fb67e14f | 574 | inject_page_fault(vcpu, &walker.fault); |
a30f47cb | 575 | |
6aa8b732 AK |
576 | return 0; |
577 | } | |
578 | ||
936a5fe6 AA |
579 | if (walker.level >= PT_DIRECTORY_LEVEL) |
580 | force_pt_level = mapping_level_dirty_bitmap(vcpu, walker.gfn); | |
581 | else | |
582 | force_pt_level = 1; | |
583 | if (!force_pt_level) { | |
7e4e4056 JR |
584 | level = min(walker.level, mapping_level(vcpu, walker.gfn)); |
585 | walker.gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1); | |
05da4558 | 586 | } |
7e4e4056 | 587 | |
e930bffe | 588 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 589 | smp_rmb(); |
af585b92 | 590 | |
78b2c54a | 591 | if (try_async_pf(vcpu, prefault, walker.gfn, addr, &pfn, write_fault, |
612819c3 | 592 | &map_writable)) |
af585b92 | 593 | return 0; |
d7824fff | 594 | |
d7c55201 XG |
595 | if (handle_abnormal_pfn(vcpu, mmu_is_nested(vcpu) ? 0 : addr, |
596 | walker.gfn, pfn, walker.pte_access, &r)) | |
597 | return r; | |
598 | ||
aaee2c94 | 599 | spin_lock(&vcpu->kvm->mmu_lock); |
e930bffe AA |
600 | if (mmu_notifier_retry(vcpu, mmu_seq)) |
601 | goto out_unlock; | |
bc32ce21 | 602 | |
0375f7fa | 603 | kvm_mmu_audit(vcpu, AUDIT_PRE_PAGE_FAULT); |
eb787d10 | 604 | kvm_mmu_free_some_pages(vcpu); |
936a5fe6 AA |
605 | if (!force_pt_level) |
606 | transparent_hugepage_adjust(vcpu, &walker.gfn, &pfn, &level); | |
d555c333 | 607 | sptep = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault, |
b90a0e6c | 608 | level, &emulate, pfn, map_writable, prefault); |
a24e8099 | 609 | (void)sptep; |
b90a0e6c XG |
610 | pgprintk("%s: shadow pte %p %llx emulate %d\n", __func__, |
611 | sptep, *sptep, emulate); | |
cea0f0e7 | 612 | |
1165f5fe | 613 | ++vcpu->stat.pf_fixed; |
0375f7fa | 614 | kvm_mmu_audit(vcpu, AUDIT_POST_PAGE_FAULT); |
aaee2c94 | 615 | spin_unlock(&vcpu->kvm->mmu_lock); |
6aa8b732 | 616 | |
b90a0e6c | 617 | return emulate; |
e930bffe AA |
618 | |
619 | out_unlock: | |
620 | spin_unlock(&vcpu->kvm->mmu_lock); | |
621 | kvm_release_pfn_clean(pfn); | |
622 | return 0; | |
6aa8b732 AK |
623 | } |
624 | ||
505aef8f XG |
625 | static gpa_t FNAME(get_level1_sp_gpa)(struct kvm_mmu_page *sp) |
626 | { | |
627 | int offset = 0; | |
628 | ||
f71fa31f | 629 | WARN_ON(sp->role.level != PT_PAGE_TABLE_LEVEL); |
505aef8f XG |
630 | |
631 | if (PTTYPE == 32) | |
632 | offset = sp->role.quadrant << PT64_LEVEL_BITS; | |
633 | ||
634 | return gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t); | |
635 | } | |
636 | ||
a461930b | 637 | static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva) |
a7052897 | 638 | { |
a461930b | 639 | struct kvm_shadow_walk_iterator iterator; |
f78978aa | 640 | struct kvm_mmu_page *sp; |
a461930b AK |
641 | int level; |
642 | u64 *sptep; | |
643 | ||
bebb106a XG |
644 | vcpu_clear_mmio_info(vcpu, gva); |
645 | ||
f57f2ef5 XG |
646 | /* |
647 | * No need to check return value here, rmap_can_add() can | |
648 | * help us to skip pte prefetch later. | |
649 | */ | |
650 | mmu_topup_memory_caches(vcpu); | |
a7052897 | 651 | |
f57f2ef5 | 652 | spin_lock(&vcpu->kvm->mmu_lock); |
a461930b AK |
653 | for_each_shadow_entry(vcpu, gva, iterator) { |
654 | level = iterator.level; | |
655 | sptep = iterator.sptep; | |
ad218f85 | 656 | |
f78978aa | 657 | sp = page_header(__pa(sptep)); |
884a0ff0 | 658 | if (is_last_spte(*sptep, level)) { |
f57f2ef5 XG |
659 | pt_element_t gpte; |
660 | gpa_t pte_gpa; | |
661 | ||
f78978aa XG |
662 | if (!sp->unsync) |
663 | break; | |
664 | ||
505aef8f | 665 | pte_gpa = FNAME(get_level1_sp_gpa)(sp); |
08e850c6 | 666 | pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t); |
a461930b | 667 | |
505aef8f XG |
668 | if (mmu_page_zap_pte(vcpu->kvm, sp, sptep)) |
669 | kvm_flush_remote_tlbs(vcpu->kvm); | |
f57f2ef5 XG |
670 | |
671 | if (!rmap_can_add(vcpu)) | |
672 | break; | |
673 | ||
674 | if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte, | |
675 | sizeof(pt_element_t))) | |
676 | break; | |
677 | ||
678 | FNAME(update_pte)(vcpu, sp, sptep, &gpte); | |
87917239 | 679 | } |
a7052897 | 680 | |
f78978aa | 681 | if (!is_shadow_present_pte(*sptep) || !sp->unsync_children) |
a461930b AK |
682 | break; |
683 | } | |
ad218f85 | 684 | spin_unlock(&vcpu->kvm->mmu_lock); |
a7052897 MT |
685 | } |
686 | ||
1871c602 | 687 | static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr, u32 access, |
ab9ae313 | 688 | struct x86_exception *exception) |
6aa8b732 AK |
689 | { |
690 | struct guest_walker walker; | |
e119d117 AK |
691 | gpa_t gpa = UNMAPPED_GVA; |
692 | int r; | |
6aa8b732 | 693 | |
33770780 | 694 | r = FNAME(walk_addr)(&walker, vcpu, vaddr, access); |
6aa8b732 | 695 | |
e119d117 | 696 | if (r) { |
1755fbcc | 697 | gpa = gfn_to_gpa(walker.gfn); |
e119d117 | 698 | gpa |= vaddr & ~PAGE_MASK; |
8c28d031 AK |
699 | } else if (exception) |
700 | *exception = walker.fault; | |
6aa8b732 AK |
701 | |
702 | return gpa; | |
703 | } | |
704 | ||
6539e738 | 705 | static gpa_t FNAME(gva_to_gpa_nested)(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 AK |
706 | u32 access, |
707 | struct x86_exception *exception) | |
6539e738 JR |
708 | { |
709 | struct guest_walker walker; | |
710 | gpa_t gpa = UNMAPPED_GVA; | |
711 | int r; | |
712 | ||
33770780 | 713 | r = FNAME(walk_addr_nested)(&walker, vcpu, vaddr, access); |
6539e738 JR |
714 | |
715 | if (r) { | |
716 | gpa = gfn_to_gpa(walker.gfn); | |
717 | gpa |= vaddr & ~PAGE_MASK; | |
8c28d031 AK |
718 | } else if (exception) |
719 | *exception = walker.fault; | |
6539e738 JR |
720 | |
721 | return gpa; | |
722 | } | |
723 | ||
e8bc217a MT |
724 | /* |
725 | * Using the cached information from sp->gfns is safe because: | |
726 | * - The spte has a reference to the struct page, so the pfn for a given gfn | |
727 | * can't change unless all sptes pointing to it are nuked first. | |
a4ee1ca4 XG |
728 | * |
729 | * Note: | |
730 | * We should flush all tlbs if spte is dropped even though guest is | |
731 | * responsible for it. Since if we don't, kvm_mmu_notifier_invalidate_page | |
732 | * and kvm_mmu_notifier_invalidate_range_start detect the mapping page isn't | |
733 | * used by guest then tlbs are not flushed, so guest is allowed to access the | |
734 | * freed pages. | |
735 | * And we increase kvm->tlbs_dirty to delay tlbs flush in this case. | |
e8bc217a | 736 | */ |
a4a8e6f7 | 737 | static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) |
e8bc217a | 738 | { |
505aef8f | 739 | int i, nr_present = 0; |
9bdbba13 | 740 | bool host_writable; |
51fb60d8 | 741 | gpa_t first_pte_gpa; |
e8bc217a | 742 | |
2032a93d LJ |
743 | /* direct kvm_mmu_page can not be unsync. */ |
744 | BUG_ON(sp->role.direct); | |
745 | ||
505aef8f | 746 | first_pte_gpa = FNAME(get_level1_sp_gpa)(sp); |
51fb60d8 | 747 | |
e8bc217a MT |
748 | for (i = 0; i < PT64_ENT_PER_PAGE; i++) { |
749 | unsigned pte_access; | |
750 | pt_element_t gpte; | |
751 | gpa_t pte_gpa; | |
f55c3f41 | 752 | gfn_t gfn; |
e8bc217a | 753 | |
ce88decf | 754 | if (!sp->spt[i]) |
e8bc217a MT |
755 | continue; |
756 | ||
51fb60d8 | 757 | pte_gpa = first_pte_gpa + i * sizeof(pt_element_t); |
e8bc217a MT |
758 | |
759 | if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte, | |
760 | sizeof(pt_element_t))) | |
761 | return -EINVAL; | |
762 | ||
407c61c6 | 763 | if (FNAME(prefetch_invalid_gpte)(vcpu, sp, &sp->spt[i], gpte)) { |
a4ee1ca4 | 764 | vcpu->kvm->tlbs_dirty++; |
407c61c6 XG |
765 | continue; |
766 | } | |
767 | ||
ce88decf XG |
768 | gfn = gpte_to_gfn(gpte); |
769 | pte_access = sp->role.access; | |
3d34adec | 770 | pte_access &= gpte_access(vcpu, gpte); |
8ea667f2 | 771 | protect_clean_gpte(&pte_access, gpte); |
ce88decf XG |
772 | |
773 | if (sync_mmio_spte(&sp->spt[i], gfn, pte_access, &nr_present)) | |
774 | continue; | |
775 | ||
407c61c6 | 776 | if (gfn != sp->gfns[i]) { |
c3707958 | 777 | drop_spte(vcpu->kvm, &sp->spt[i]); |
a4ee1ca4 | 778 | vcpu->kvm->tlbs_dirty++; |
e8bc217a MT |
779 | continue; |
780 | } | |
781 | ||
782 | nr_present++; | |
ce88decf | 783 | |
f8e453b0 XG |
784 | host_writable = sp->spt[i] & SPTE_HOST_WRITEABLE; |
785 | ||
e8bc217a | 786 | set_spte(vcpu, &sp->spt[i], pte_access, 0, 0, |
640d9b0d | 787 | PT_PAGE_TABLE_LEVEL, gfn, |
1403283a | 788 | spte_to_pfn(sp->spt[i]), true, false, |
9bdbba13 | 789 | host_writable); |
e8bc217a MT |
790 | } |
791 | ||
792 | return !nr_present; | |
793 | } | |
794 | ||
6aa8b732 AK |
795 | #undef pt_element_t |
796 | #undef guest_walker | |
797 | #undef FNAME | |
798 | #undef PT_BASE_ADDR_MASK | |
799 | #undef PT_INDEX | |
e04da980 JR |
800 | #undef PT_LVL_ADDR_MASK |
801 | #undef PT_LVL_OFFSET_MASK | |
c7addb90 | 802 | #undef PT_LEVEL_BITS |
cea0f0e7 | 803 | #undef PT_MAX_FULL_LEVELS |
5fb07ddb | 804 | #undef gpte_to_gfn |
e04da980 | 805 | #undef gpte_to_gfn_lvl |
b3e4e63f | 806 | #undef CMPXCHG |