Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * AMD SVM support | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
7 | * | |
8 | * Authors: | |
9 | * Yaniv Kamay <yaniv@qumranet.com> | |
10 | * Avi Kivity <avi@qumranet.com> | |
11 | * | |
12 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
13 | * the COPYING file in the top-level directory. | |
14 | * | |
15 | */ | |
edf88417 AK |
16 | #include <linux/kvm_host.h> |
17 | ||
85f455f7 | 18 | #include "irq.h" |
1d737c8a | 19 | #include "mmu.h" |
5fdbf976 | 20 | #include "kvm_cache_regs.h" |
fe4c7b19 | 21 | #include "x86.h" |
e495606d | 22 | |
6aa8b732 | 23 | #include <linux/module.h> |
9d8f549d | 24 | #include <linux/kernel.h> |
6aa8b732 AK |
25 | #include <linux/vmalloc.h> |
26 | #include <linux/highmem.h> | |
e8edc6e0 | 27 | #include <linux/sched.h> |
229456fc | 28 | #include <linux/ftrace_event.h> |
6aa8b732 | 29 | |
e495606d | 30 | #include <asm/desc.h> |
6aa8b732 | 31 | |
63d1142f | 32 | #include <asm/virtext.h> |
229456fc | 33 | #include "trace.h" |
63d1142f | 34 | |
4ecac3fd AK |
35 | #define __ex(x) __kvm_handle_fault_on_reboot(x) |
36 | ||
6aa8b732 AK |
37 | MODULE_AUTHOR("Qumranet"); |
38 | MODULE_LICENSE("GPL"); | |
39 | ||
40 | #define IOPM_ALLOC_ORDER 2 | |
41 | #define MSRPM_ALLOC_ORDER 1 | |
42 | ||
6aa8b732 AK |
43 | #define SEG_TYPE_LDT 2 |
44 | #define SEG_TYPE_BUSY_TSS16 3 | |
45 | ||
80b7706e JR |
46 | #define SVM_FEATURE_NPT (1 << 0) |
47 | #define SVM_FEATURE_LBRV (1 << 1) | |
94c935a1 | 48 | #define SVM_FEATURE_SVML (1 << 2) |
80b7706e | 49 | |
410e4d57 JR |
50 | #define NESTED_EXIT_HOST 0 /* Exit handled on host level */ |
51 | #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */ | |
52 | #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */ | |
53 | ||
24e09cbf JR |
54 | #define DEBUGCTL_RESERVED_BITS (~(0x3fULL)) |
55 | ||
c0725420 AG |
56 | /* Turn on to get debugging output*/ |
57 | /* #define NESTED_DEBUG */ | |
58 | ||
59 | #ifdef NESTED_DEBUG | |
60 | #define nsvm_printk(fmt, args...) printk(KERN_INFO fmt, ## args) | |
61 | #else | |
62 | #define nsvm_printk(fmt, args...) do {} while(0) | |
63 | #endif | |
64 | ||
6c8166a7 AK |
65 | static const u32 host_save_user_msrs[] = { |
66 | #ifdef CONFIG_X86_64 | |
67 | MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE, | |
68 | MSR_FS_BASE, | |
69 | #endif | |
70 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, | |
71 | }; | |
72 | ||
73 | #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs) | |
74 | ||
75 | struct kvm_vcpu; | |
76 | ||
e6aa9abd JR |
77 | struct nested_state { |
78 | struct vmcb *hsave; | |
79 | u64 hsave_msr; | |
80 | u64 vmcb; | |
81 | ||
82 | /* These are the merged vectors */ | |
83 | u32 *msrpm; | |
84 | ||
85 | /* gpa pointers to the real vectors */ | |
86 | u64 vmcb_msrpm; | |
aad42c64 JR |
87 | |
88 | /* cache for intercepts of the guest */ | |
89 | u16 intercept_cr_read; | |
90 | u16 intercept_cr_write; | |
91 | u16 intercept_dr_read; | |
92 | u16 intercept_dr_write; | |
93 | u32 intercept_exceptions; | |
94 | u64 intercept; | |
95 | ||
e6aa9abd JR |
96 | }; |
97 | ||
6c8166a7 AK |
98 | struct vcpu_svm { |
99 | struct kvm_vcpu vcpu; | |
100 | struct vmcb *vmcb; | |
101 | unsigned long vmcb_pa; | |
102 | struct svm_cpu_data *svm_data; | |
103 | uint64_t asid_generation; | |
104 | uint64_t sysenter_esp; | |
105 | uint64_t sysenter_eip; | |
106 | ||
107 | u64 next_rip; | |
108 | ||
109 | u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS]; | |
110 | u64 host_gs_base; | |
6c8166a7 AK |
111 | |
112 | u32 *msrpm; | |
6c8166a7 | 113 | |
e6aa9abd | 114 | struct nested_state nested; |
6c8166a7 AK |
115 | }; |
116 | ||
709ddebf JR |
117 | /* enable NPT for AMD64 and X86 with PAE */ |
118 | #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE) | |
119 | static bool npt_enabled = true; | |
120 | #else | |
e3da3acd | 121 | static bool npt_enabled = false; |
709ddebf | 122 | #endif |
6c7dac72 JR |
123 | static int npt = 1; |
124 | ||
125 | module_param(npt, int, S_IRUGO); | |
e3da3acd | 126 | |
4b6e4dca | 127 | static int nested = 1; |
236de055 AG |
128 | module_param(nested, int, S_IRUGO); |
129 | ||
44874f84 | 130 | static void svm_flush_tlb(struct kvm_vcpu *vcpu); |
a5c3832d | 131 | static void svm_complete_interrupts(struct vcpu_svm *svm); |
04d2cc77 | 132 | |
410e4d57 | 133 | static int nested_svm_exit_handled(struct vcpu_svm *svm); |
cf74a78b | 134 | static int nested_svm_vmexit(struct vcpu_svm *svm); |
cf74a78b AG |
135 | static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, |
136 | bool has_error_code, u32 error_code); | |
137 | ||
a2fa3e9f GH |
138 | static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu) |
139 | { | |
fb3f0f51 | 140 | return container_of(vcpu, struct vcpu_svm, vcpu); |
a2fa3e9f GH |
141 | } |
142 | ||
3d6368ef AG |
143 | static inline bool is_nested(struct vcpu_svm *svm) |
144 | { | |
e6aa9abd | 145 | return svm->nested.vmcb; |
3d6368ef AG |
146 | } |
147 | ||
2af9194d JR |
148 | static inline void enable_gif(struct vcpu_svm *svm) |
149 | { | |
150 | svm->vcpu.arch.hflags |= HF_GIF_MASK; | |
151 | } | |
152 | ||
153 | static inline void disable_gif(struct vcpu_svm *svm) | |
154 | { | |
155 | svm->vcpu.arch.hflags &= ~HF_GIF_MASK; | |
156 | } | |
157 | ||
158 | static inline bool gif_set(struct vcpu_svm *svm) | |
159 | { | |
160 | return !!(svm->vcpu.arch.hflags & HF_GIF_MASK); | |
161 | } | |
162 | ||
4866d5e3 | 163 | static unsigned long iopm_base; |
6aa8b732 AK |
164 | |
165 | struct kvm_ldttss_desc { | |
166 | u16 limit0; | |
167 | u16 base0; | |
168 | unsigned base1 : 8, type : 5, dpl : 2, p : 1; | |
169 | unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8; | |
170 | u32 base3; | |
171 | u32 zero1; | |
172 | } __attribute__((packed)); | |
173 | ||
174 | struct svm_cpu_data { | |
175 | int cpu; | |
176 | ||
5008fdf5 AK |
177 | u64 asid_generation; |
178 | u32 max_asid; | |
179 | u32 next_asid; | |
6aa8b732 AK |
180 | struct kvm_ldttss_desc *tss_desc; |
181 | ||
182 | struct page *save_area; | |
183 | }; | |
184 | ||
185 | static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data); | |
80b7706e | 186 | static uint32_t svm_features; |
6aa8b732 AK |
187 | |
188 | struct svm_init_data { | |
189 | int cpu; | |
190 | int r; | |
191 | }; | |
192 | ||
193 | static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000}; | |
194 | ||
9d8f549d | 195 | #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges) |
6aa8b732 AK |
196 | #define MSRS_RANGE_SIZE 2048 |
197 | #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2) | |
198 | ||
199 | #define MAX_INST_SIZE 15 | |
200 | ||
80b7706e JR |
201 | static inline u32 svm_has(u32 feat) |
202 | { | |
203 | return svm_features & feat; | |
204 | } | |
205 | ||
6aa8b732 AK |
206 | static inline void clgi(void) |
207 | { | |
4ecac3fd | 208 | asm volatile (__ex(SVM_CLGI)); |
6aa8b732 AK |
209 | } |
210 | ||
211 | static inline void stgi(void) | |
212 | { | |
4ecac3fd | 213 | asm volatile (__ex(SVM_STGI)); |
6aa8b732 AK |
214 | } |
215 | ||
216 | static inline void invlpga(unsigned long addr, u32 asid) | |
217 | { | |
4ecac3fd | 218 | asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid)); |
6aa8b732 AK |
219 | } |
220 | ||
6aa8b732 AK |
221 | static inline void force_new_asid(struct kvm_vcpu *vcpu) |
222 | { | |
a2fa3e9f | 223 | to_svm(vcpu)->asid_generation--; |
6aa8b732 AK |
224 | } |
225 | ||
226 | static inline void flush_guest_tlb(struct kvm_vcpu *vcpu) | |
227 | { | |
228 | force_new_asid(vcpu); | |
229 | } | |
230 | ||
231 | static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer) | |
232 | { | |
709ddebf | 233 | if (!npt_enabled && !(efer & EFER_LMA)) |
2b5203ee | 234 | efer &= ~EFER_LME; |
6aa8b732 | 235 | |
9962d032 | 236 | to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME; |
ad312c7c | 237 | vcpu->arch.shadow_efer = efer; |
6aa8b732 AK |
238 | } |
239 | ||
298101da AK |
240 | static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr, |
241 | bool has_error_code, u32 error_code) | |
242 | { | |
243 | struct vcpu_svm *svm = to_svm(vcpu); | |
244 | ||
cf74a78b AG |
245 | /* If we are within a nested VM we'd better #VMEXIT and let the |
246 | guest handle the exception */ | |
247 | if (nested_svm_check_exception(svm, nr, has_error_code, error_code)) | |
248 | return; | |
249 | ||
298101da AK |
250 | svm->vmcb->control.event_inj = nr |
251 | | SVM_EVTINJ_VALID | |
252 | | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0) | |
253 | | SVM_EVTINJ_TYPE_EXEPT; | |
254 | svm->vmcb->control.event_inj_err = error_code; | |
255 | } | |
256 | ||
6aa8b732 AK |
257 | static int is_external_interrupt(u32 info) |
258 | { | |
259 | info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID; | |
260 | return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR); | |
261 | } | |
262 | ||
2809f5d2 GC |
263 | static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) |
264 | { | |
265 | struct vcpu_svm *svm = to_svm(vcpu); | |
266 | u32 ret = 0; | |
267 | ||
268 | if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) | |
269 | ret |= X86_SHADOW_INT_STI | X86_SHADOW_INT_MOV_SS; | |
270 | return ret & mask; | |
271 | } | |
272 | ||
273 | static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) | |
274 | { | |
275 | struct vcpu_svm *svm = to_svm(vcpu); | |
276 | ||
277 | if (mask == 0) | |
278 | svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK; | |
279 | else | |
280 | svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK; | |
281 | ||
282 | } | |
283 | ||
6aa8b732 AK |
284 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) |
285 | { | |
a2fa3e9f GH |
286 | struct vcpu_svm *svm = to_svm(vcpu); |
287 | ||
288 | if (!svm->next_rip) { | |
851ba692 | 289 | if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) != |
f629cf84 GN |
290 | EMULATE_DONE) |
291 | printk(KERN_DEBUG "%s: NOP\n", __func__); | |
6aa8b732 AK |
292 | return; |
293 | } | |
5fdbf976 MT |
294 | if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE) |
295 | printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n", | |
296 | __func__, kvm_rip_read(vcpu), svm->next_rip); | |
6aa8b732 | 297 | |
5fdbf976 | 298 | kvm_rip_write(vcpu, svm->next_rip); |
2809f5d2 | 299 | svm_set_interrupt_shadow(vcpu, 0); |
6aa8b732 AK |
300 | } |
301 | ||
302 | static int has_svm(void) | |
303 | { | |
63d1142f | 304 | const char *msg; |
6aa8b732 | 305 | |
63d1142f | 306 | if (!cpu_has_svm(&msg)) { |
ff81ff10 | 307 | printk(KERN_INFO "has_svm: %s\n", msg); |
6aa8b732 AK |
308 | return 0; |
309 | } | |
310 | ||
6aa8b732 AK |
311 | return 1; |
312 | } | |
313 | ||
314 | static void svm_hardware_disable(void *garbage) | |
315 | { | |
2c8dceeb | 316 | cpu_svm_disable(); |
6aa8b732 AK |
317 | } |
318 | ||
10474ae8 | 319 | static int svm_hardware_enable(void *garbage) |
6aa8b732 AK |
320 | { |
321 | ||
322 | struct svm_cpu_data *svm_data; | |
323 | uint64_t efer; | |
b792c344 | 324 | struct descriptor_table gdt_descr; |
6aa8b732 AK |
325 | struct desc_struct *gdt; |
326 | int me = raw_smp_processor_id(); | |
327 | ||
10474ae8 AG |
328 | rdmsrl(MSR_EFER, efer); |
329 | if (efer & EFER_SVME) | |
330 | return -EBUSY; | |
331 | ||
6aa8b732 AK |
332 | if (!has_svm()) { |
333 | printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me); | |
10474ae8 | 334 | return -EINVAL; |
6aa8b732 AK |
335 | } |
336 | svm_data = per_cpu(svm_data, me); | |
337 | ||
338 | if (!svm_data) { | |
339 | printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n", | |
340 | me); | |
10474ae8 | 341 | return -EINVAL; |
6aa8b732 AK |
342 | } |
343 | ||
344 | svm_data->asid_generation = 1; | |
345 | svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1; | |
346 | svm_data->next_asid = svm_data->max_asid + 1; | |
347 | ||
b792c344 AM |
348 | kvm_get_gdt(&gdt_descr); |
349 | gdt = (struct desc_struct *)gdt_descr.base; | |
6aa8b732 AK |
350 | svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS); |
351 | ||
9962d032 | 352 | wrmsrl(MSR_EFER, efer | EFER_SVME); |
6aa8b732 AK |
353 | |
354 | wrmsrl(MSR_VM_HSAVE_PA, | |
355 | page_to_pfn(svm_data->save_area) << PAGE_SHIFT); | |
10474ae8 AG |
356 | |
357 | return 0; | |
6aa8b732 AK |
358 | } |
359 | ||
0da1db75 JR |
360 | static void svm_cpu_uninit(int cpu) |
361 | { | |
362 | struct svm_cpu_data *svm_data | |
363 | = per_cpu(svm_data, raw_smp_processor_id()); | |
364 | ||
365 | if (!svm_data) | |
366 | return; | |
367 | ||
368 | per_cpu(svm_data, raw_smp_processor_id()) = NULL; | |
369 | __free_page(svm_data->save_area); | |
370 | kfree(svm_data); | |
371 | } | |
372 | ||
6aa8b732 AK |
373 | static int svm_cpu_init(int cpu) |
374 | { | |
375 | struct svm_cpu_data *svm_data; | |
376 | int r; | |
377 | ||
378 | svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL); | |
379 | if (!svm_data) | |
380 | return -ENOMEM; | |
381 | svm_data->cpu = cpu; | |
382 | svm_data->save_area = alloc_page(GFP_KERNEL); | |
383 | r = -ENOMEM; | |
384 | if (!svm_data->save_area) | |
385 | goto err_1; | |
386 | ||
387 | per_cpu(svm_data, cpu) = svm_data; | |
388 | ||
389 | return 0; | |
390 | ||
391 | err_1: | |
392 | kfree(svm_data); | |
393 | return r; | |
394 | ||
395 | } | |
396 | ||
bfc733a7 RR |
397 | static void set_msr_interception(u32 *msrpm, unsigned msr, |
398 | int read, int write) | |
6aa8b732 AK |
399 | { |
400 | int i; | |
401 | ||
402 | for (i = 0; i < NUM_MSR_MAPS; i++) { | |
403 | if (msr >= msrpm_ranges[i] && | |
404 | msr < msrpm_ranges[i] + MSRS_IN_RANGE) { | |
405 | u32 msr_offset = (i * MSRS_IN_RANGE + msr - | |
406 | msrpm_ranges[i]) * 2; | |
407 | ||
408 | u32 *base = msrpm + (msr_offset / 32); | |
409 | u32 msr_shift = msr_offset % 32; | |
410 | u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1); | |
411 | *base = (*base & ~(0x3 << msr_shift)) | | |
412 | (mask << msr_shift); | |
bfc733a7 | 413 | return; |
6aa8b732 AK |
414 | } |
415 | } | |
bfc733a7 | 416 | BUG(); |
6aa8b732 AK |
417 | } |
418 | ||
f65c229c JR |
419 | static void svm_vcpu_init_msrpm(u32 *msrpm) |
420 | { | |
421 | memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER)); | |
422 | ||
423 | #ifdef CONFIG_X86_64 | |
424 | set_msr_interception(msrpm, MSR_GS_BASE, 1, 1); | |
425 | set_msr_interception(msrpm, MSR_FS_BASE, 1, 1); | |
426 | set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1); | |
427 | set_msr_interception(msrpm, MSR_LSTAR, 1, 1); | |
428 | set_msr_interception(msrpm, MSR_CSTAR, 1, 1); | |
429 | set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1); | |
430 | #endif | |
431 | set_msr_interception(msrpm, MSR_K6_STAR, 1, 1); | |
432 | set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1); | |
f65c229c JR |
433 | } |
434 | ||
24e09cbf JR |
435 | static void svm_enable_lbrv(struct vcpu_svm *svm) |
436 | { | |
437 | u32 *msrpm = svm->msrpm; | |
438 | ||
439 | svm->vmcb->control.lbr_ctl = 1; | |
440 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1); | |
441 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1); | |
442 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1); | |
443 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1); | |
444 | } | |
445 | ||
446 | static void svm_disable_lbrv(struct vcpu_svm *svm) | |
447 | { | |
448 | u32 *msrpm = svm->msrpm; | |
449 | ||
450 | svm->vmcb->control.lbr_ctl = 0; | |
451 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0); | |
452 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0); | |
453 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0); | |
454 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0); | |
455 | } | |
456 | ||
6aa8b732 AK |
457 | static __init int svm_hardware_setup(void) |
458 | { | |
459 | int cpu; | |
460 | struct page *iopm_pages; | |
f65c229c | 461 | void *iopm_va; |
6aa8b732 AK |
462 | int r; |
463 | ||
6aa8b732 AK |
464 | iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER); |
465 | ||
466 | if (!iopm_pages) | |
467 | return -ENOMEM; | |
c8681339 AL |
468 | |
469 | iopm_va = page_address(iopm_pages); | |
470 | memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER)); | |
6aa8b732 AK |
471 | iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT; |
472 | ||
50a37eb4 JR |
473 | if (boot_cpu_has(X86_FEATURE_NX)) |
474 | kvm_enable_efer_bits(EFER_NX); | |
475 | ||
1b2fd70c AG |
476 | if (boot_cpu_has(X86_FEATURE_FXSR_OPT)) |
477 | kvm_enable_efer_bits(EFER_FFXSR); | |
478 | ||
236de055 AG |
479 | if (nested) { |
480 | printk(KERN_INFO "kvm: Nested Virtualization enabled\n"); | |
481 | kvm_enable_efer_bits(EFER_SVME); | |
482 | } | |
483 | ||
6aa8b732 AK |
484 | for_each_online_cpu(cpu) { |
485 | r = svm_cpu_init(cpu); | |
486 | if (r) | |
f65c229c | 487 | goto err; |
6aa8b732 | 488 | } |
33bd6a0b JR |
489 | |
490 | svm_features = cpuid_edx(SVM_CPUID_FUNC); | |
491 | ||
e3da3acd JR |
492 | if (!svm_has(SVM_FEATURE_NPT)) |
493 | npt_enabled = false; | |
494 | ||
6c7dac72 JR |
495 | if (npt_enabled && !npt) { |
496 | printk(KERN_INFO "kvm: Nested Paging disabled\n"); | |
497 | npt_enabled = false; | |
498 | } | |
499 | ||
18552672 | 500 | if (npt_enabled) { |
e3da3acd | 501 | printk(KERN_INFO "kvm: Nested Paging enabled\n"); |
18552672 | 502 | kvm_enable_tdp(); |
5f4cb662 JR |
503 | } else |
504 | kvm_disable_tdp(); | |
e3da3acd | 505 | |
6aa8b732 AK |
506 | return 0; |
507 | ||
f65c229c | 508 | err: |
6aa8b732 AK |
509 | __free_pages(iopm_pages, IOPM_ALLOC_ORDER); |
510 | iopm_base = 0; | |
511 | return r; | |
512 | } | |
513 | ||
514 | static __exit void svm_hardware_unsetup(void) | |
515 | { | |
0da1db75 JR |
516 | int cpu; |
517 | ||
518 | for_each_online_cpu(cpu) | |
519 | svm_cpu_uninit(cpu); | |
520 | ||
6aa8b732 | 521 | __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER); |
f65c229c | 522 | iopm_base = 0; |
6aa8b732 AK |
523 | } |
524 | ||
525 | static void init_seg(struct vmcb_seg *seg) | |
526 | { | |
527 | seg->selector = 0; | |
528 | seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK | | |
529 | SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */ | |
530 | seg->limit = 0xffff; | |
531 | seg->base = 0; | |
532 | } | |
533 | ||
534 | static void init_sys_seg(struct vmcb_seg *seg, uint32_t type) | |
535 | { | |
536 | seg->selector = 0; | |
537 | seg->attrib = SVM_SELECTOR_P_MASK | type; | |
538 | seg->limit = 0xffff; | |
539 | seg->base = 0; | |
540 | } | |
541 | ||
e6101a96 | 542 | static void init_vmcb(struct vcpu_svm *svm) |
6aa8b732 | 543 | { |
e6101a96 JR |
544 | struct vmcb_control_area *control = &svm->vmcb->control; |
545 | struct vmcb_save_area *save = &svm->vmcb->save; | |
6aa8b732 AK |
546 | |
547 | control->intercept_cr_read = INTERCEPT_CR0_MASK | | |
548 | INTERCEPT_CR3_MASK | | |
649d6864 | 549 | INTERCEPT_CR4_MASK; |
6aa8b732 AK |
550 | |
551 | control->intercept_cr_write = INTERCEPT_CR0_MASK | | |
552 | INTERCEPT_CR3_MASK | | |
80a8119c AK |
553 | INTERCEPT_CR4_MASK | |
554 | INTERCEPT_CR8_MASK; | |
6aa8b732 AK |
555 | |
556 | control->intercept_dr_read = INTERCEPT_DR0_MASK | | |
557 | INTERCEPT_DR1_MASK | | |
558 | INTERCEPT_DR2_MASK | | |
559 | INTERCEPT_DR3_MASK; | |
560 | ||
561 | control->intercept_dr_write = INTERCEPT_DR0_MASK | | |
562 | INTERCEPT_DR1_MASK | | |
563 | INTERCEPT_DR2_MASK | | |
564 | INTERCEPT_DR3_MASK | | |
565 | INTERCEPT_DR5_MASK | | |
566 | INTERCEPT_DR7_MASK; | |
567 | ||
7aa81cc0 | 568 | control->intercept_exceptions = (1 << PF_VECTOR) | |
53371b50 JR |
569 | (1 << UD_VECTOR) | |
570 | (1 << MC_VECTOR); | |
6aa8b732 AK |
571 | |
572 | ||
573 | control->intercept = (1ULL << INTERCEPT_INTR) | | |
574 | (1ULL << INTERCEPT_NMI) | | |
0152527b | 575 | (1ULL << INTERCEPT_SMI) | |
6aa8b732 | 576 | (1ULL << INTERCEPT_CPUID) | |
cf5a94d1 | 577 | (1ULL << INTERCEPT_INVD) | |
6aa8b732 | 578 | (1ULL << INTERCEPT_HLT) | |
a7052897 | 579 | (1ULL << INTERCEPT_INVLPG) | |
6aa8b732 AK |
580 | (1ULL << INTERCEPT_INVLPGA) | |
581 | (1ULL << INTERCEPT_IOIO_PROT) | | |
582 | (1ULL << INTERCEPT_MSR_PROT) | | |
583 | (1ULL << INTERCEPT_TASK_SWITCH) | | |
46fe4ddd | 584 | (1ULL << INTERCEPT_SHUTDOWN) | |
6aa8b732 AK |
585 | (1ULL << INTERCEPT_VMRUN) | |
586 | (1ULL << INTERCEPT_VMMCALL) | | |
587 | (1ULL << INTERCEPT_VMLOAD) | | |
588 | (1ULL << INTERCEPT_VMSAVE) | | |
589 | (1ULL << INTERCEPT_STGI) | | |
590 | (1ULL << INTERCEPT_CLGI) | | |
916ce236 | 591 | (1ULL << INTERCEPT_SKINIT) | |
cf5a94d1 | 592 | (1ULL << INTERCEPT_WBINVD) | |
916ce236 JR |
593 | (1ULL << INTERCEPT_MONITOR) | |
594 | (1ULL << INTERCEPT_MWAIT); | |
6aa8b732 AK |
595 | |
596 | control->iopm_base_pa = iopm_base; | |
f65c229c | 597 | control->msrpm_base_pa = __pa(svm->msrpm); |
0cc5064d | 598 | control->tsc_offset = 0; |
6aa8b732 AK |
599 | control->int_ctl = V_INTR_MASKING_MASK; |
600 | ||
601 | init_seg(&save->es); | |
602 | init_seg(&save->ss); | |
603 | init_seg(&save->ds); | |
604 | init_seg(&save->fs); | |
605 | init_seg(&save->gs); | |
606 | ||
607 | save->cs.selector = 0xf000; | |
608 | /* Executable/Readable Code Segment */ | |
609 | save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK | | |
610 | SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK; | |
611 | save->cs.limit = 0xffff; | |
d92899a0 AK |
612 | /* |
613 | * cs.base should really be 0xffff0000, but vmx can't handle that, so | |
614 | * be consistent with it. | |
615 | * | |
616 | * Replace when we have real mode working for vmx. | |
617 | */ | |
618 | save->cs.base = 0xf0000; | |
6aa8b732 AK |
619 | |
620 | save->gdtr.limit = 0xffff; | |
621 | save->idtr.limit = 0xffff; | |
622 | ||
623 | init_sys_seg(&save->ldtr, SEG_TYPE_LDT); | |
624 | init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16); | |
625 | ||
9962d032 | 626 | save->efer = EFER_SVME; |
d77c26fc | 627 | save->dr6 = 0xffff0ff0; |
6aa8b732 AK |
628 | save->dr7 = 0x400; |
629 | save->rflags = 2; | |
630 | save->rip = 0x0000fff0; | |
5fdbf976 | 631 | svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip; |
6aa8b732 AK |
632 | |
633 | /* | |
634 | * cr0 val on cpu init should be 0x60000010, we enable cpu | |
635 | * cache by default. the orderly way is to enable cache in bios. | |
636 | */ | |
707d92fa | 637 | save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP; |
66aee91a | 638 | save->cr4 = X86_CR4_PAE; |
6aa8b732 | 639 | /* rdx = ?? */ |
709ddebf JR |
640 | |
641 | if (npt_enabled) { | |
642 | /* Setup VMCB for Nested Paging */ | |
643 | control->nested_ctl = 1; | |
a7052897 MT |
644 | control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) | |
645 | (1ULL << INTERCEPT_INVLPG)); | |
709ddebf JR |
646 | control->intercept_exceptions &= ~(1 << PF_VECTOR); |
647 | control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK| | |
648 | INTERCEPT_CR3_MASK); | |
649 | control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK| | |
650 | INTERCEPT_CR3_MASK); | |
651 | save->g_pat = 0x0007040600070406ULL; | |
652 | /* enable caching because the QEMU Bios doesn't enable it */ | |
653 | save->cr0 = X86_CR0_ET; | |
654 | save->cr3 = 0; | |
655 | save->cr4 = 0; | |
656 | } | |
a79d2f18 | 657 | force_new_asid(&svm->vcpu); |
1371d904 | 658 | |
e6aa9abd | 659 | svm->nested.vmcb = 0; |
2af9194d JR |
660 | svm->vcpu.arch.hflags = 0; |
661 | ||
662 | enable_gif(svm); | |
6aa8b732 AK |
663 | } |
664 | ||
e00c8cf2 | 665 | static int svm_vcpu_reset(struct kvm_vcpu *vcpu) |
04d2cc77 AK |
666 | { |
667 | struct vcpu_svm *svm = to_svm(vcpu); | |
668 | ||
e6101a96 | 669 | init_vmcb(svm); |
70433389 | 670 | |
c5af89b6 | 671 | if (!kvm_vcpu_is_bsp(vcpu)) { |
5fdbf976 | 672 | kvm_rip_write(vcpu, 0); |
ad312c7c ZX |
673 | svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12; |
674 | svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8; | |
70433389 | 675 | } |
5fdbf976 MT |
676 | vcpu->arch.regs_avail = ~0; |
677 | vcpu->arch.regs_dirty = ~0; | |
e00c8cf2 AK |
678 | |
679 | return 0; | |
04d2cc77 AK |
680 | } |
681 | ||
fb3f0f51 | 682 | static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 683 | { |
a2fa3e9f | 684 | struct vcpu_svm *svm; |
6aa8b732 | 685 | struct page *page; |
f65c229c | 686 | struct page *msrpm_pages; |
b286d5d8 | 687 | struct page *hsave_page; |
3d6368ef | 688 | struct page *nested_msrpm_pages; |
fb3f0f51 | 689 | int err; |
6aa8b732 | 690 | |
c16f862d | 691 | svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); |
fb3f0f51 RR |
692 | if (!svm) { |
693 | err = -ENOMEM; | |
694 | goto out; | |
695 | } | |
696 | ||
697 | err = kvm_vcpu_init(&svm->vcpu, kvm, id); | |
698 | if (err) | |
699 | goto free_svm; | |
700 | ||
6aa8b732 | 701 | page = alloc_page(GFP_KERNEL); |
fb3f0f51 RR |
702 | if (!page) { |
703 | err = -ENOMEM; | |
704 | goto uninit; | |
705 | } | |
6aa8b732 | 706 | |
f65c229c JR |
707 | err = -ENOMEM; |
708 | msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); | |
709 | if (!msrpm_pages) | |
710 | goto uninit; | |
3d6368ef AG |
711 | |
712 | nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); | |
713 | if (!nested_msrpm_pages) | |
714 | goto uninit; | |
715 | ||
f65c229c JR |
716 | svm->msrpm = page_address(msrpm_pages); |
717 | svm_vcpu_init_msrpm(svm->msrpm); | |
718 | ||
b286d5d8 AG |
719 | hsave_page = alloc_page(GFP_KERNEL); |
720 | if (!hsave_page) | |
721 | goto uninit; | |
e6aa9abd | 722 | svm->nested.hsave = page_address(hsave_page); |
b286d5d8 | 723 | |
e6aa9abd | 724 | svm->nested.msrpm = page_address(nested_msrpm_pages); |
3d6368ef | 725 | |
a2fa3e9f GH |
726 | svm->vmcb = page_address(page); |
727 | clear_page(svm->vmcb); | |
728 | svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT; | |
729 | svm->asid_generation = 0; | |
e6101a96 | 730 | init_vmcb(svm); |
a2fa3e9f | 731 | |
fb3f0f51 RR |
732 | fx_init(&svm->vcpu); |
733 | svm->vcpu.fpu_active = 1; | |
ad312c7c | 734 | svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE; |
c5af89b6 | 735 | if (kvm_vcpu_is_bsp(&svm->vcpu)) |
ad312c7c | 736 | svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP; |
6aa8b732 | 737 | |
fb3f0f51 | 738 | return &svm->vcpu; |
36241b8c | 739 | |
fb3f0f51 RR |
740 | uninit: |
741 | kvm_vcpu_uninit(&svm->vcpu); | |
742 | free_svm: | |
a4770347 | 743 | kmem_cache_free(kvm_vcpu_cache, svm); |
fb3f0f51 RR |
744 | out: |
745 | return ERR_PTR(err); | |
6aa8b732 AK |
746 | } |
747 | ||
748 | static void svm_free_vcpu(struct kvm_vcpu *vcpu) | |
749 | { | |
a2fa3e9f GH |
750 | struct vcpu_svm *svm = to_svm(vcpu); |
751 | ||
fb3f0f51 | 752 | __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT)); |
f65c229c | 753 | __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER); |
e6aa9abd JR |
754 | __free_page(virt_to_page(svm->nested.hsave)); |
755 | __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER); | |
fb3f0f51 | 756 | kvm_vcpu_uninit(vcpu); |
a4770347 | 757 | kmem_cache_free(kvm_vcpu_cache, svm); |
6aa8b732 AK |
758 | } |
759 | ||
15ad7146 | 760 | static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 761 | { |
a2fa3e9f | 762 | struct vcpu_svm *svm = to_svm(vcpu); |
15ad7146 | 763 | int i; |
0cc5064d | 764 | |
0cc5064d | 765 | if (unlikely(cpu != vcpu->cpu)) { |
e935d48e | 766 | u64 delta; |
0cc5064d AK |
767 | |
768 | /* | |
769 | * Make sure that the guest sees a monotonically | |
770 | * increasing TSC. | |
771 | */ | |
e935d48e | 772 | delta = vcpu->arch.host_tsc - native_read_tsc(); |
a2fa3e9f | 773 | svm->vmcb->control.tsc_offset += delta; |
77b1ab17 JR |
774 | if (is_nested(svm)) |
775 | svm->nested.hsave->control.tsc_offset += delta; | |
0cc5064d | 776 | vcpu->cpu = cpu; |
2f599714 | 777 | kvm_migrate_timers(vcpu); |
4b656b12 | 778 | svm->asid_generation = 0; |
0cc5064d | 779 | } |
94dfbdb3 AL |
780 | |
781 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) | |
a2fa3e9f | 782 | rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
6aa8b732 AK |
783 | } |
784 | ||
785 | static void svm_vcpu_put(struct kvm_vcpu *vcpu) | |
786 | { | |
a2fa3e9f | 787 | struct vcpu_svm *svm = to_svm(vcpu); |
94dfbdb3 AL |
788 | int i; |
789 | ||
e1beb1d3 | 790 | ++vcpu->stat.host_state_reload; |
94dfbdb3 | 791 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) |
a2fa3e9f | 792 | wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
94dfbdb3 | 793 | |
e935d48e | 794 | vcpu->arch.host_tsc = native_read_tsc(); |
6aa8b732 AK |
795 | } |
796 | ||
6aa8b732 AK |
797 | static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu) |
798 | { | |
a2fa3e9f | 799 | return to_svm(vcpu)->vmcb->save.rflags; |
6aa8b732 AK |
800 | } |
801 | ||
802 | static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
803 | { | |
a2fa3e9f | 804 | to_svm(vcpu)->vmcb->save.rflags = rflags; |
6aa8b732 AK |
805 | } |
806 | ||
6de4f3ad AK |
807 | static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) |
808 | { | |
809 | switch (reg) { | |
810 | case VCPU_EXREG_PDPTR: | |
811 | BUG_ON(!npt_enabled); | |
812 | load_pdptrs(vcpu, vcpu->arch.cr3); | |
813 | break; | |
814 | default: | |
815 | BUG(); | |
816 | } | |
817 | } | |
818 | ||
f0b85051 AG |
819 | static void svm_set_vintr(struct vcpu_svm *svm) |
820 | { | |
821 | svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR; | |
822 | } | |
823 | ||
824 | static void svm_clear_vintr(struct vcpu_svm *svm) | |
825 | { | |
826 | svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR); | |
827 | } | |
828 | ||
6aa8b732 AK |
829 | static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg) |
830 | { | |
a2fa3e9f | 831 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; |
6aa8b732 AK |
832 | |
833 | switch (seg) { | |
834 | case VCPU_SREG_CS: return &save->cs; | |
835 | case VCPU_SREG_DS: return &save->ds; | |
836 | case VCPU_SREG_ES: return &save->es; | |
837 | case VCPU_SREG_FS: return &save->fs; | |
838 | case VCPU_SREG_GS: return &save->gs; | |
839 | case VCPU_SREG_SS: return &save->ss; | |
840 | case VCPU_SREG_TR: return &save->tr; | |
841 | case VCPU_SREG_LDTR: return &save->ldtr; | |
842 | } | |
843 | BUG(); | |
8b6d44c7 | 844 | return NULL; |
6aa8b732 AK |
845 | } |
846 | ||
847 | static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg) | |
848 | { | |
849 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
850 | ||
851 | return s->base; | |
852 | } | |
853 | ||
854 | static void svm_get_segment(struct kvm_vcpu *vcpu, | |
855 | struct kvm_segment *var, int seg) | |
856 | { | |
857 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
858 | ||
859 | var->base = s->base; | |
860 | var->limit = s->limit; | |
861 | var->selector = s->selector; | |
862 | var->type = s->attrib & SVM_SELECTOR_TYPE_MASK; | |
863 | var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1; | |
864 | var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3; | |
865 | var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1; | |
866 | var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1; | |
867 | var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1; | |
868 | var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1; | |
869 | var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1; | |
25022acc | 870 | |
19bca6ab AP |
871 | /* AMD's VMCB does not have an explicit unusable field, so emulate it |
872 | * for cross vendor migration purposes by "not present" | |
873 | */ | |
874 | var->unusable = !var->present || (var->type == 0); | |
875 | ||
1fbdc7a5 AP |
876 | switch (seg) { |
877 | case VCPU_SREG_CS: | |
878 | /* | |
879 | * SVM always stores 0 for the 'G' bit in the CS selector in | |
880 | * the VMCB on a VMEXIT. This hurts cross-vendor migration: | |
881 | * Intel's VMENTRY has a check on the 'G' bit. | |
882 | */ | |
25022acc | 883 | var->g = s->limit > 0xfffff; |
1fbdc7a5 AP |
884 | break; |
885 | case VCPU_SREG_TR: | |
886 | /* | |
887 | * Work around a bug where the busy flag in the tr selector | |
888 | * isn't exposed | |
889 | */ | |
c0d09828 | 890 | var->type |= 0x2; |
1fbdc7a5 AP |
891 | break; |
892 | case VCPU_SREG_DS: | |
893 | case VCPU_SREG_ES: | |
894 | case VCPU_SREG_FS: | |
895 | case VCPU_SREG_GS: | |
896 | /* | |
897 | * The accessed bit must always be set in the segment | |
898 | * descriptor cache, although it can be cleared in the | |
899 | * descriptor, the cached bit always remains at 1. Since | |
900 | * Intel has a check on this, set it here to support | |
901 | * cross-vendor migration. | |
902 | */ | |
903 | if (!var->unusable) | |
904 | var->type |= 0x1; | |
905 | break; | |
b586eb02 AP |
906 | case VCPU_SREG_SS: |
907 | /* On AMD CPUs sometimes the DB bit in the segment | |
908 | * descriptor is left as 1, although the whole segment has | |
909 | * been made unusable. Clear it here to pass an Intel VMX | |
910 | * entry check when cross vendor migrating. | |
911 | */ | |
912 | if (var->unusable) | |
913 | var->db = 0; | |
914 | break; | |
1fbdc7a5 | 915 | } |
6aa8b732 AK |
916 | } |
917 | ||
2e4d2653 IE |
918 | static int svm_get_cpl(struct kvm_vcpu *vcpu) |
919 | { | |
920 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; | |
921 | ||
922 | return save->cpl; | |
923 | } | |
924 | ||
6aa8b732 AK |
925 | static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) |
926 | { | |
a2fa3e9f GH |
927 | struct vcpu_svm *svm = to_svm(vcpu); |
928 | ||
929 | dt->limit = svm->vmcb->save.idtr.limit; | |
930 | dt->base = svm->vmcb->save.idtr.base; | |
6aa8b732 AK |
931 | } |
932 | ||
933 | static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
934 | { | |
a2fa3e9f GH |
935 | struct vcpu_svm *svm = to_svm(vcpu); |
936 | ||
937 | svm->vmcb->save.idtr.limit = dt->limit; | |
938 | svm->vmcb->save.idtr.base = dt->base ; | |
6aa8b732 AK |
939 | } |
940 | ||
941 | static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
942 | { | |
a2fa3e9f GH |
943 | struct vcpu_svm *svm = to_svm(vcpu); |
944 | ||
945 | dt->limit = svm->vmcb->save.gdtr.limit; | |
946 | dt->base = svm->vmcb->save.gdtr.base; | |
6aa8b732 AK |
947 | } |
948 | ||
949 | static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
950 | { | |
a2fa3e9f GH |
951 | struct vcpu_svm *svm = to_svm(vcpu); |
952 | ||
953 | svm->vmcb->save.gdtr.limit = dt->limit; | |
954 | svm->vmcb->save.gdtr.base = dt->base ; | |
6aa8b732 AK |
955 | } |
956 | ||
25c4c276 | 957 | static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 AK |
958 | { |
959 | } | |
960 | ||
6aa8b732 AK |
961 | static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
962 | { | |
a2fa3e9f GH |
963 | struct vcpu_svm *svm = to_svm(vcpu); |
964 | ||
05b3e0c2 | 965 | #ifdef CONFIG_X86_64 |
ad312c7c | 966 | if (vcpu->arch.shadow_efer & EFER_LME) { |
707d92fa | 967 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { |
ad312c7c | 968 | vcpu->arch.shadow_efer |= EFER_LMA; |
2b5203ee | 969 | svm->vmcb->save.efer |= EFER_LMA | EFER_LME; |
6aa8b732 AK |
970 | } |
971 | ||
d77c26fc | 972 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) { |
ad312c7c | 973 | vcpu->arch.shadow_efer &= ~EFER_LMA; |
2b5203ee | 974 | svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME); |
6aa8b732 AK |
975 | } |
976 | } | |
977 | #endif | |
709ddebf JR |
978 | if (npt_enabled) |
979 | goto set; | |
980 | ||
ad312c7c | 981 | if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) { |
a2fa3e9f | 982 | svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR); |
7807fa6c AL |
983 | vcpu->fpu_active = 1; |
984 | } | |
985 | ||
ad312c7c | 986 | vcpu->arch.cr0 = cr0; |
707d92fa | 987 | cr0 |= X86_CR0_PG | X86_CR0_WP; |
6b390b63 JR |
988 | if (!vcpu->fpu_active) { |
989 | svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR); | |
334df50a | 990 | cr0 |= X86_CR0_TS; |
6b390b63 | 991 | } |
709ddebf JR |
992 | set: |
993 | /* | |
994 | * re-enable caching here because the QEMU bios | |
995 | * does not do it - this results in some delay at | |
996 | * reboot | |
997 | */ | |
998 | cr0 &= ~(X86_CR0_CD | X86_CR0_NW); | |
a2fa3e9f | 999 | svm->vmcb->save.cr0 = cr0; |
6aa8b732 AK |
1000 | } |
1001 | ||
1002 | static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) | |
1003 | { | |
6394b649 | 1004 | unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE; |
e5eab0ce JR |
1005 | unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4; |
1006 | ||
1007 | if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE)) | |
1008 | force_new_asid(vcpu); | |
6394b649 | 1009 | |
ec077263 JR |
1010 | vcpu->arch.cr4 = cr4; |
1011 | if (!npt_enabled) | |
1012 | cr4 |= X86_CR4_PAE; | |
6394b649 | 1013 | cr4 |= host_cr4_mce; |
ec077263 | 1014 | to_svm(vcpu)->vmcb->save.cr4 = cr4; |
6aa8b732 AK |
1015 | } |
1016 | ||
1017 | static void svm_set_segment(struct kvm_vcpu *vcpu, | |
1018 | struct kvm_segment *var, int seg) | |
1019 | { | |
a2fa3e9f | 1020 | struct vcpu_svm *svm = to_svm(vcpu); |
6aa8b732 AK |
1021 | struct vmcb_seg *s = svm_seg(vcpu, seg); |
1022 | ||
1023 | s->base = var->base; | |
1024 | s->limit = var->limit; | |
1025 | s->selector = var->selector; | |
1026 | if (var->unusable) | |
1027 | s->attrib = 0; | |
1028 | else { | |
1029 | s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK); | |
1030 | s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT; | |
1031 | s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT; | |
1032 | s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT; | |
1033 | s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT; | |
1034 | s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT; | |
1035 | s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT; | |
1036 | s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT; | |
1037 | } | |
1038 | if (seg == VCPU_SREG_CS) | |
a2fa3e9f GH |
1039 | svm->vmcb->save.cpl |
1040 | = (svm->vmcb->save.cs.attrib | |
6aa8b732 AK |
1041 | >> SVM_SELECTOR_DPL_SHIFT) & 3; |
1042 | ||
1043 | } | |
1044 | ||
44c11430 | 1045 | static void update_db_intercept(struct kvm_vcpu *vcpu) |
6aa8b732 | 1046 | { |
d0bfb940 JK |
1047 | struct vcpu_svm *svm = to_svm(vcpu); |
1048 | ||
d0bfb940 JK |
1049 | svm->vmcb->control.intercept_exceptions &= |
1050 | ~((1 << DB_VECTOR) | (1 << BP_VECTOR)); | |
44c11430 GN |
1051 | |
1052 | if (vcpu->arch.singlestep) | |
1053 | svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR); | |
1054 | ||
d0bfb940 JK |
1055 | if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) { |
1056 | if (vcpu->guest_debug & | |
1057 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) | |
1058 | svm->vmcb->control.intercept_exceptions |= | |
1059 | 1 << DB_VECTOR; | |
1060 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) | |
1061 | svm->vmcb->control.intercept_exceptions |= | |
1062 | 1 << BP_VECTOR; | |
1063 | } else | |
1064 | vcpu->guest_debug = 0; | |
44c11430 GN |
1065 | } |
1066 | ||
1067 | static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg) | |
1068 | { | |
1069 | int old_debug = vcpu->guest_debug; | |
1070 | struct vcpu_svm *svm = to_svm(vcpu); | |
1071 | ||
1072 | vcpu->guest_debug = dbg->control; | |
1073 | ||
1074 | update_db_intercept(vcpu); | |
d0bfb940 | 1075 | |
ae675ef0 JK |
1076 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) |
1077 | svm->vmcb->save.dr7 = dbg->arch.debugreg[7]; | |
1078 | else | |
1079 | svm->vmcb->save.dr7 = vcpu->arch.dr7; | |
1080 | ||
d0bfb940 JK |
1081 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) |
1082 | svm->vmcb->save.rflags |= X86_EFLAGS_TF | X86_EFLAGS_RF; | |
1083 | else if (old_debug & KVM_GUESTDBG_SINGLESTEP) | |
1084 | svm->vmcb->save.rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF); | |
1085 | ||
1086 | return 0; | |
6aa8b732 AK |
1087 | } |
1088 | ||
1089 | static void load_host_msrs(struct kvm_vcpu *vcpu) | |
1090 | { | |
94dfbdb3 | 1091 | #ifdef CONFIG_X86_64 |
a2fa3e9f | 1092 | wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base); |
94dfbdb3 | 1093 | #endif |
6aa8b732 AK |
1094 | } |
1095 | ||
1096 | static void save_host_msrs(struct kvm_vcpu *vcpu) | |
1097 | { | |
94dfbdb3 | 1098 | #ifdef CONFIG_X86_64 |
a2fa3e9f | 1099 | rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base); |
94dfbdb3 | 1100 | #endif |
6aa8b732 AK |
1101 | } |
1102 | ||
e756fc62 | 1103 | static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data) |
6aa8b732 AK |
1104 | { |
1105 | if (svm_data->next_asid > svm_data->max_asid) { | |
1106 | ++svm_data->asid_generation; | |
1107 | svm_data->next_asid = 1; | |
a2fa3e9f | 1108 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID; |
6aa8b732 AK |
1109 | } |
1110 | ||
a2fa3e9f GH |
1111 | svm->asid_generation = svm_data->asid_generation; |
1112 | svm->vmcb->control.asid = svm_data->next_asid++; | |
6aa8b732 AK |
1113 | } |
1114 | ||
6aa8b732 AK |
1115 | static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr) |
1116 | { | |
42dbaa5a JK |
1117 | struct vcpu_svm *svm = to_svm(vcpu); |
1118 | unsigned long val; | |
1119 | ||
1120 | switch (dr) { | |
1121 | case 0 ... 3: | |
1122 | val = vcpu->arch.db[dr]; | |
1123 | break; | |
1124 | case 6: | |
1125 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) | |
1126 | val = vcpu->arch.dr6; | |
1127 | else | |
1128 | val = svm->vmcb->save.dr6; | |
1129 | break; | |
1130 | case 7: | |
1131 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) | |
1132 | val = vcpu->arch.dr7; | |
1133 | else | |
1134 | val = svm->vmcb->save.dr7; | |
1135 | break; | |
1136 | default: | |
1137 | val = 0; | |
1138 | } | |
1139 | ||
af9ca2d7 | 1140 | return val; |
6aa8b732 AK |
1141 | } |
1142 | ||
1143 | static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value, | |
1144 | int *exception) | |
1145 | { | |
a2fa3e9f GH |
1146 | struct vcpu_svm *svm = to_svm(vcpu); |
1147 | ||
42dbaa5a | 1148 | *exception = 0; |
6aa8b732 AK |
1149 | |
1150 | switch (dr) { | |
1151 | case 0 ... 3: | |
42dbaa5a JK |
1152 | vcpu->arch.db[dr] = value; |
1153 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) | |
1154 | vcpu->arch.eff_db[dr] = value; | |
6aa8b732 AK |
1155 | return; |
1156 | case 4 ... 5: | |
42dbaa5a | 1157 | if (vcpu->arch.cr4 & X86_CR4_DE) |
6aa8b732 | 1158 | *exception = UD_VECTOR; |
42dbaa5a JK |
1159 | return; |
1160 | case 6: | |
1161 | if (value & 0xffffffff00000000ULL) { | |
1162 | *exception = GP_VECTOR; | |
6aa8b732 AK |
1163 | return; |
1164 | } | |
42dbaa5a JK |
1165 | vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1; |
1166 | return; | |
1167 | case 7: | |
1168 | if (value & 0xffffffff00000000ULL) { | |
6aa8b732 AK |
1169 | *exception = GP_VECTOR; |
1170 | return; | |
1171 | } | |
42dbaa5a JK |
1172 | vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1; |
1173 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { | |
1174 | svm->vmcb->save.dr7 = vcpu->arch.dr7; | |
1175 | vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK); | |
1176 | } | |
6aa8b732 | 1177 | return; |
6aa8b732 | 1178 | default: |
42dbaa5a | 1179 | /* FIXME: Possible case? */ |
6aa8b732 | 1180 | printk(KERN_DEBUG "%s: unexpected dr %u\n", |
b8688d51 | 1181 | __func__, dr); |
6aa8b732 AK |
1182 | *exception = UD_VECTOR; |
1183 | return; | |
1184 | } | |
1185 | } | |
1186 | ||
851ba692 | 1187 | static int pf_interception(struct vcpu_svm *svm) |
6aa8b732 | 1188 | { |
6aa8b732 AK |
1189 | u64 fault_address; |
1190 | u32 error_code; | |
6aa8b732 | 1191 | |
a2fa3e9f GH |
1192 | fault_address = svm->vmcb->control.exit_info_2; |
1193 | error_code = svm->vmcb->control.exit_info_1; | |
af9ca2d7 | 1194 | |
229456fc | 1195 | trace_kvm_page_fault(fault_address, error_code); |
52c7847d AK |
1196 | if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu)) |
1197 | kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address); | |
3067714c | 1198 | return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code); |
6aa8b732 AK |
1199 | } |
1200 | ||
851ba692 | 1201 | static int db_interception(struct vcpu_svm *svm) |
d0bfb940 | 1202 | { |
851ba692 AK |
1203 | struct kvm_run *kvm_run = svm->vcpu.run; |
1204 | ||
d0bfb940 | 1205 | if (!(svm->vcpu.guest_debug & |
44c11430 GN |
1206 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) && |
1207 | !svm->vcpu.arch.singlestep) { | |
d0bfb940 JK |
1208 | kvm_queue_exception(&svm->vcpu, DB_VECTOR); |
1209 | return 1; | |
1210 | } | |
44c11430 GN |
1211 | |
1212 | if (svm->vcpu.arch.singlestep) { | |
1213 | svm->vcpu.arch.singlestep = false; | |
1214 | if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) | |
1215 | svm->vmcb->save.rflags &= | |
1216 | ~(X86_EFLAGS_TF | X86_EFLAGS_RF); | |
1217 | update_db_intercept(&svm->vcpu); | |
1218 | } | |
1219 | ||
1220 | if (svm->vcpu.guest_debug & | |
1221 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)){ | |
1222 | kvm_run->exit_reason = KVM_EXIT_DEBUG; | |
1223 | kvm_run->debug.arch.pc = | |
1224 | svm->vmcb->save.cs.base + svm->vmcb->save.rip; | |
1225 | kvm_run->debug.arch.exception = DB_VECTOR; | |
1226 | return 0; | |
1227 | } | |
1228 | ||
1229 | return 1; | |
d0bfb940 JK |
1230 | } |
1231 | ||
851ba692 | 1232 | static int bp_interception(struct vcpu_svm *svm) |
d0bfb940 | 1233 | { |
851ba692 AK |
1234 | struct kvm_run *kvm_run = svm->vcpu.run; |
1235 | ||
d0bfb940 JK |
1236 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
1237 | kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip; | |
1238 | kvm_run->debug.arch.exception = BP_VECTOR; | |
1239 | return 0; | |
1240 | } | |
1241 | ||
851ba692 | 1242 | static int ud_interception(struct vcpu_svm *svm) |
7aa81cc0 AL |
1243 | { |
1244 | int er; | |
1245 | ||
851ba692 | 1246 | er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD); |
7aa81cc0 | 1247 | if (er != EMULATE_DONE) |
7ee5d940 | 1248 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
7aa81cc0 AL |
1249 | return 1; |
1250 | } | |
1251 | ||
851ba692 | 1252 | static int nm_interception(struct vcpu_svm *svm) |
7807fa6c | 1253 | { |
a2fa3e9f | 1254 | svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR); |
ad312c7c | 1255 | if (!(svm->vcpu.arch.cr0 & X86_CR0_TS)) |
a2fa3e9f | 1256 | svm->vmcb->save.cr0 &= ~X86_CR0_TS; |
e756fc62 | 1257 | svm->vcpu.fpu_active = 1; |
a2fa3e9f GH |
1258 | |
1259 | return 1; | |
7807fa6c AL |
1260 | } |
1261 | ||
851ba692 | 1262 | static int mc_interception(struct vcpu_svm *svm) |
53371b50 JR |
1263 | { |
1264 | /* | |
1265 | * On an #MC intercept the MCE handler is not called automatically in | |
1266 | * the host. So do it by hand here. | |
1267 | */ | |
1268 | asm volatile ( | |
1269 | "int $0x12\n"); | |
1270 | /* not sure if we ever come back to this point */ | |
1271 | ||
1272 | return 1; | |
1273 | } | |
1274 | ||
851ba692 | 1275 | static int shutdown_interception(struct vcpu_svm *svm) |
46fe4ddd | 1276 | { |
851ba692 AK |
1277 | struct kvm_run *kvm_run = svm->vcpu.run; |
1278 | ||
46fe4ddd JR |
1279 | /* |
1280 | * VMCB is undefined after a SHUTDOWN intercept | |
1281 | * so reinitialize it. | |
1282 | */ | |
a2fa3e9f | 1283 | clear_page(svm->vmcb); |
e6101a96 | 1284 | init_vmcb(svm); |
46fe4ddd JR |
1285 | |
1286 | kvm_run->exit_reason = KVM_EXIT_SHUTDOWN; | |
1287 | return 0; | |
1288 | } | |
1289 | ||
851ba692 | 1290 | static int io_interception(struct vcpu_svm *svm) |
6aa8b732 | 1291 | { |
d77c26fc | 1292 | u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */ |
34c33d16 | 1293 | int size, in, string; |
039576c0 | 1294 | unsigned port; |
6aa8b732 | 1295 | |
e756fc62 | 1296 | ++svm->vcpu.stat.io_exits; |
6aa8b732 | 1297 | |
a2fa3e9f | 1298 | svm->next_rip = svm->vmcb->control.exit_info_2; |
6aa8b732 | 1299 | |
e70669ab LV |
1300 | string = (io_info & SVM_IOIO_STR_MASK) != 0; |
1301 | ||
1302 | if (string) { | |
3427318f | 1303 | if (emulate_instruction(&svm->vcpu, |
851ba692 | 1304 | 0, 0, 0) == EMULATE_DO_MMIO) |
e70669ab LV |
1305 | return 0; |
1306 | return 1; | |
1307 | } | |
1308 | ||
039576c0 AK |
1309 | in = (io_info & SVM_IOIO_TYPE_MASK) != 0; |
1310 | port = io_info >> 16; | |
1311 | size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT; | |
6aa8b732 | 1312 | |
e93f36bc | 1313 | skip_emulated_instruction(&svm->vcpu); |
851ba692 | 1314 | return kvm_emulate_pio(&svm->vcpu, in, size, port); |
6aa8b732 AK |
1315 | } |
1316 | ||
851ba692 | 1317 | static int nmi_interception(struct vcpu_svm *svm) |
c47f098d JR |
1318 | { |
1319 | return 1; | |
1320 | } | |
1321 | ||
851ba692 | 1322 | static int intr_interception(struct vcpu_svm *svm) |
a0698055 JR |
1323 | { |
1324 | ++svm->vcpu.stat.irq_exits; | |
1325 | return 1; | |
1326 | } | |
1327 | ||
851ba692 | 1328 | static int nop_on_interception(struct vcpu_svm *svm) |
6aa8b732 AK |
1329 | { |
1330 | return 1; | |
1331 | } | |
1332 | ||
851ba692 | 1333 | static int halt_interception(struct vcpu_svm *svm) |
6aa8b732 | 1334 | { |
5fdbf976 | 1335 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 1; |
e756fc62 RR |
1336 | skip_emulated_instruction(&svm->vcpu); |
1337 | return kvm_emulate_halt(&svm->vcpu); | |
6aa8b732 AK |
1338 | } |
1339 | ||
851ba692 | 1340 | static int vmmcall_interception(struct vcpu_svm *svm) |
02e235bc | 1341 | { |
5fdbf976 | 1342 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; |
e756fc62 | 1343 | skip_emulated_instruction(&svm->vcpu); |
7aa81cc0 AL |
1344 | kvm_emulate_hypercall(&svm->vcpu); |
1345 | return 1; | |
02e235bc AK |
1346 | } |
1347 | ||
c0725420 AG |
1348 | static int nested_svm_check_permissions(struct vcpu_svm *svm) |
1349 | { | |
1350 | if (!(svm->vcpu.arch.shadow_efer & EFER_SVME) | |
1351 | || !is_paging(&svm->vcpu)) { | |
1352 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
1353 | return 1; | |
1354 | } | |
1355 | ||
1356 | if (svm->vmcb->save.cpl) { | |
1357 | kvm_inject_gp(&svm->vcpu, 0); | |
1358 | return 1; | |
1359 | } | |
1360 | ||
1361 | return 0; | |
1362 | } | |
1363 | ||
cf74a78b AG |
1364 | static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, |
1365 | bool has_error_code, u32 error_code) | |
1366 | { | |
0295ad7d JR |
1367 | if (!is_nested(svm)) |
1368 | return 0; | |
cf74a78b | 1369 | |
0295ad7d JR |
1370 | svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr; |
1371 | svm->vmcb->control.exit_code_hi = 0; | |
1372 | svm->vmcb->control.exit_info_1 = error_code; | |
1373 | svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2; | |
1374 | ||
410e4d57 | 1375 | return nested_svm_exit_handled(svm); |
cf74a78b AG |
1376 | } |
1377 | ||
1378 | static inline int nested_svm_intr(struct vcpu_svm *svm) | |
1379 | { | |
26666957 JR |
1380 | if (!is_nested(svm)) |
1381 | return 0; | |
cf74a78b | 1382 | |
26666957 JR |
1383 | if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK)) |
1384 | return 0; | |
cf74a78b | 1385 | |
26666957 JR |
1386 | if (!(svm->vcpu.arch.hflags & HF_HIF_MASK)) |
1387 | return 0; | |
cf74a78b | 1388 | |
26666957 JR |
1389 | svm->vmcb->control.exit_code = SVM_EXIT_INTR; |
1390 | ||
1391 | if (nested_svm_exit_handled(svm)) { | |
1392 | nsvm_printk("VMexit -> INTR\n"); | |
1393 | return 1; | |
cf74a78b AG |
1394 | } |
1395 | ||
1396 | return 0; | |
1397 | } | |
1398 | ||
34f80cfa JR |
1399 | static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, enum km_type idx) |
1400 | { | |
1401 | struct page *page; | |
1402 | ||
34f80cfa | 1403 | page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT); |
34f80cfa JR |
1404 | if (is_error_page(page)) |
1405 | goto error; | |
1406 | ||
1407 | return kmap_atomic(page, idx); | |
1408 | ||
1409 | error: | |
1410 | kvm_release_page_clean(page); | |
1411 | kvm_inject_gp(&svm->vcpu, 0); | |
1412 | ||
1413 | return NULL; | |
1414 | } | |
1415 | ||
1416 | static void nested_svm_unmap(void *addr, enum km_type idx) | |
1417 | { | |
1418 | struct page *page; | |
1419 | ||
1420 | if (!addr) | |
1421 | return; | |
1422 | ||
1423 | page = kmap_atomic_to_page(addr); | |
1424 | ||
1425 | kunmap_atomic(addr, idx); | |
1426 | kvm_release_page_dirty(page); | |
1427 | } | |
1428 | ||
3d62d9aa | 1429 | static bool nested_svm_exit_handled_msr(struct vcpu_svm *svm) |
4c2161ae | 1430 | { |
4c2161ae | 1431 | u32 param = svm->vmcb->control.exit_info_1 & 1; |
3d62d9aa JR |
1432 | u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
1433 | bool ret = false; | |
1434 | u32 t0, t1; | |
1435 | u8 *msrpm; | |
4c2161ae | 1436 | |
3d62d9aa JR |
1437 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT))) |
1438 | return false; | |
1439 | ||
1440 | msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, KM_USER0); | |
1441 | ||
1442 | if (!msrpm) | |
1443 | goto out; | |
4c2161ae JR |
1444 | |
1445 | switch (msr) { | |
1446 | case 0 ... 0x1fff: | |
1447 | t0 = (msr * 2) % 8; | |
1448 | t1 = msr / 8; | |
1449 | break; | |
1450 | case 0xc0000000 ... 0xc0001fff: | |
1451 | t0 = (8192 + msr - 0xc0000000) * 2; | |
1452 | t1 = (t0 / 8); | |
1453 | t0 %= 8; | |
1454 | break; | |
1455 | case 0xc0010000 ... 0xc0011fff: | |
1456 | t0 = (16384 + msr - 0xc0010000) * 2; | |
1457 | t1 = (t0 / 8); | |
1458 | t0 %= 8; | |
1459 | break; | |
1460 | default: | |
3d62d9aa JR |
1461 | ret = true; |
1462 | goto out; | |
4c2161ae | 1463 | } |
4c2161ae | 1464 | |
3d62d9aa JR |
1465 | ret = msrpm[t1] & ((1 << param) << t0); |
1466 | ||
1467 | out: | |
1468 | nested_svm_unmap(msrpm, KM_USER0); | |
1469 | ||
1470 | return ret; | |
4c2161ae JR |
1471 | } |
1472 | ||
410e4d57 | 1473 | static int nested_svm_exit_special(struct vcpu_svm *svm) |
cf74a78b | 1474 | { |
cf74a78b | 1475 | u32 exit_code = svm->vmcb->control.exit_code; |
4c2161ae | 1476 | |
410e4d57 JR |
1477 | switch (exit_code) { |
1478 | case SVM_EXIT_INTR: | |
1479 | case SVM_EXIT_NMI: | |
1480 | return NESTED_EXIT_HOST; | |
cf74a78b | 1481 | /* For now we are always handling NPFs when using them */ |
410e4d57 JR |
1482 | case SVM_EXIT_NPF: |
1483 | if (npt_enabled) | |
1484 | return NESTED_EXIT_HOST; | |
1485 | break; | |
1486 | /* When we're shadowing, trap PFs */ | |
1487 | case SVM_EXIT_EXCP_BASE + PF_VECTOR: | |
1488 | if (!npt_enabled) | |
1489 | return NESTED_EXIT_HOST; | |
1490 | break; | |
1491 | default: | |
1492 | break; | |
cf74a78b AG |
1493 | } |
1494 | ||
410e4d57 JR |
1495 | return NESTED_EXIT_CONTINUE; |
1496 | } | |
1497 | ||
1498 | /* | |
1499 | * If this function returns true, this #vmexit was already handled | |
1500 | */ | |
1501 | static int nested_svm_exit_handled(struct vcpu_svm *svm) | |
1502 | { | |
1503 | u32 exit_code = svm->vmcb->control.exit_code; | |
1504 | int vmexit = NESTED_EXIT_HOST; | |
1505 | ||
cf74a78b | 1506 | switch (exit_code) { |
9c4e40b9 | 1507 | case SVM_EXIT_MSR: |
3d62d9aa | 1508 | vmexit = nested_svm_exit_handled_msr(svm); |
9c4e40b9 | 1509 | break; |
cf74a78b AG |
1510 | case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: { |
1511 | u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0); | |
aad42c64 | 1512 | if (svm->nested.intercept_cr_read & cr_bits) |
410e4d57 | 1513 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
1514 | break; |
1515 | } | |
1516 | case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: { | |
1517 | u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0); | |
aad42c64 | 1518 | if (svm->nested.intercept_cr_write & cr_bits) |
410e4d57 | 1519 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
1520 | break; |
1521 | } | |
1522 | case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: { | |
1523 | u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0); | |
aad42c64 | 1524 | if (svm->nested.intercept_dr_read & dr_bits) |
410e4d57 | 1525 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
1526 | break; |
1527 | } | |
1528 | case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: { | |
1529 | u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0); | |
aad42c64 | 1530 | if (svm->nested.intercept_dr_write & dr_bits) |
410e4d57 | 1531 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
1532 | break; |
1533 | } | |
1534 | case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: { | |
1535 | u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE); | |
aad42c64 | 1536 | if (svm->nested.intercept_exceptions & excp_bits) |
410e4d57 | 1537 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
1538 | break; |
1539 | } | |
1540 | default: { | |
1541 | u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR); | |
1542 | nsvm_printk("exit code: 0x%x\n", exit_code); | |
aad42c64 | 1543 | if (svm->nested.intercept & exit_bits) |
410e4d57 | 1544 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
1545 | } |
1546 | } | |
1547 | ||
410e4d57 | 1548 | if (vmexit == NESTED_EXIT_DONE) { |
9c4e40b9 JR |
1549 | nsvm_printk("#VMEXIT reason=%04x\n", exit_code); |
1550 | nested_svm_vmexit(svm); | |
1551 | } | |
1552 | ||
1553 | return vmexit; | |
cf74a78b AG |
1554 | } |
1555 | ||
0460a979 JR |
1556 | static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb) |
1557 | { | |
1558 | struct vmcb_control_area *dst = &dst_vmcb->control; | |
1559 | struct vmcb_control_area *from = &from_vmcb->control; | |
1560 | ||
1561 | dst->intercept_cr_read = from->intercept_cr_read; | |
1562 | dst->intercept_cr_write = from->intercept_cr_write; | |
1563 | dst->intercept_dr_read = from->intercept_dr_read; | |
1564 | dst->intercept_dr_write = from->intercept_dr_write; | |
1565 | dst->intercept_exceptions = from->intercept_exceptions; | |
1566 | dst->intercept = from->intercept; | |
1567 | dst->iopm_base_pa = from->iopm_base_pa; | |
1568 | dst->msrpm_base_pa = from->msrpm_base_pa; | |
1569 | dst->tsc_offset = from->tsc_offset; | |
1570 | dst->asid = from->asid; | |
1571 | dst->tlb_ctl = from->tlb_ctl; | |
1572 | dst->int_ctl = from->int_ctl; | |
1573 | dst->int_vector = from->int_vector; | |
1574 | dst->int_state = from->int_state; | |
1575 | dst->exit_code = from->exit_code; | |
1576 | dst->exit_code_hi = from->exit_code_hi; | |
1577 | dst->exit_info_1 = from->exit_info_1; | |
1578 | dst->exit_info_2 = from->exit_info_2; | |
1579 | dst->exit_int_info = from->exit_int_info; | |
1580 | dst->exit_int_info_err = from->exit_int_info_err; | |
1581 | dst->nested_ctl = from->nested_ctl; | |
1582 | dst->event_inj = from->event_inj; | |
1583 | dst->event_inj_err = from->event_inj_err; | |
1584 | dst->nested_cr3 = from->nested_cr3; | |
1585 | dst->lbr_ctl = from->lbr_ctl; | |
1586 | } | |
1587 | ||
34f80cfa | 1588 | static int nested_svm_vmexit(struct vcpu_svm *svm) |
cf74a78b | 1589 | { |
34f80cfa | 1590 | struct vmcb *nested_vmcb; |
e6aa9abd | 1591 | struct vmcb *hsave = svm->nested.hsave; |
33740e40 | 1592 | struct vmcb *vmcb = svm->vmcb; |
cf74a78b | 1593 | |
34f80cfa JR |
1594 | nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, KM_USER0); |
1595 | if (!nested_vmcb) | |
1596 | return 1; | |
1597 | ||
cf74a78b | 1598 | /* Give the current vmcb to the guest */ |
33740e40 JR |
1599 | disable_gif(svm); |
1600 | ||
1601 | nested_vmcb->save.es = vmcb->save.es; | |
1602 | nested_vmcb->save.cs = vmcb->save.cs; | |
1603 | nested_vmcb->save.ss = vmcb->save.ss; | |
1604 | nested_vmcb->save.ds = vmcb->save.ds; | |
1605 | nested_vmcb->save.gdtr = vmcb->save.gdtr; | |
1606 | nested_vmcb->save.idtr = vmcb->save.idtr; | |
1607 | if (npt_enabled) | |
1608 | nested_vmcb->save.cr3 = vmcb->save.cr3; | |
1609 | nested_vmcb->save.cr2 = vmcb->save.cr2; | |
1610 | nested_vmcb->save.rflags = vmcb->save.rflags; | |
1611 | nested_vmcb->save.rip = vmcb->save.rip; | |
1612 | nested_vmcb->save.rsp = vmcb->save.rsp; | |
1613 | nested_vmcb->save.rax = vmcb->save.rax; | |
1614 | nested_vmcb->save.dr7 = vmcb->save.dr7; | |
1615 | nested_vmcb->save.dr6 = vmcb->save.dr6; | |
1616 | nested_vmcb->save.cpl = vmcb->save.cpl; | |
1617 | ||
1618 | nested_vmcb->control.int_ctl = vmcb->control.int_ctl; | |
1619 | nested_vmcb->control.int_vector = vmcb->control.int_vector; | |
1620 | nested_vmcb->control.int_state = vmcb->control.int_state; | |
1621 | nested_vmcb->control.exit_code = vmcb->control.exit_code; | |
1622 | nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi; | |
1623 | nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1; | |
1624 | nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2; | |
1625 | nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info; | |
1626 | nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err; | |
1627 | nested_vmcb->control.tlb_ctl = 0; | |
1628 | nested_vmcb->control.event_inj = 0; | |
1629 | nested_vmcb->control.event_inj_err = 0; | |
cf74a78b AG |
1630 | |
1631 | /* We always set V_INTR_MASKING and remember the old value in hflags */ | |
1632 | if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK)) | |
1633 | nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK; | |
1634 | ||
cf74a78b | 1635 | /* Restore the original control entries */ |
0460a979 | 1636 | copy_vmcb_control_area(vmcb, hsave); |
cf74a78b AG |
1637 | |
1638 | /* Kill any pending exceptions */ | |
1639 | if (svm->vcpu.arch.exception.pending == true) | |
1640 | nsvm_printk("WARNING: Pending Exception\n"); | |
33740e40 | 1641 | |
219b65dc AG |
1642 | kvm_clear_exception_queue(&svm->vcpu); |
1643 | kvm_clear_interrupt_queue(&svm->vcpu); | |
cf74a78b AG |
1644 | |
1645 | /* Restore selected save entries */ | |
1646 | svm->vmcb->save.es = hsave->save.es; | |
1647 | svm->vmcb->save.cs = hsave->save.cs; | |
1648 | svm->vmcb->save.ss = hsave->save.ss; | |
1649 | svm->vmcb->save.ds = hsave->save.ds; | |
1650 | svm->vmcb->save.gdtr = hsave->save.gdtr; | |
1651 | svm->vmcb->save.idtr = hsave->save.idtr; | |
1652 | svm->vmcb->save.rflags = hsave->save.rflags; | |
1653 | svm_set_efer(&svm->vcpu, hsave->save.efer); | |
1654 | svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE); | |
1655 | svm_set_cr4(&svm->vcpu, hsave->save.cr4); | |
1656 | if (npt_enabled) { | |
1657 | svm->vmcb->save.cr3 = hsave->save.cr3; | |
1658 | svm->vcpu.arch.cr3 = hsave->save.cr3; | |
1659 | } else { | |
1660 | kvm_set_cr3(&svm->vcpu, hsave->save.cr3); | |
1661 | } | |
1662 | kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax); | |
1663 | kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp); | |
1664 | kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip); | |
1665 | svm->vmcb->save.dr7 = 0; | |
1666 | svm->vmcb->save.cpl = 0; | |
1667 | svm->vmcb->control.exit_int_info = 0; | |
1668 | ||
cf74a78b | 1669 | /* Exit nested SVM mode */ |
e6aa9abd | 1670 | svm->nested.vmcb = 0; |
cf74a78b | 1671 | |
34f80cfa | 1672 | nested_svm_unmap(nested_vmcb, KM_USER0); |
cf74a78b AG |
1673 | |
1674 | kvm_mmu_reset_context(&svm->vcpu); | |
1675 | kvm_mmu_load(&svm->vcpu); | |
1676 | ||
1677 | return 0; | |
1678 | } | |
3d6368ef | 1679 | |
9738b2c9 | 1680 | static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm) |
3d6368ef | 1681 | { |
9738b2c9 | 1682 | u32 *nested_msrpm; |
3d6368ef | 1683 | int i; |
9738b2c9 JR |
1684 | |
1685 | nested_msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, KM_USER0); | |
1686 | if (!nested_msrpm) | |
1687 | return false; | |
1688 | ||
3d6368ef | 1689 | for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++) |
e6aa9abd | 1690 | svm->nested.msrpm[i] = svm->msrpm[i] | nested_msrpm[i]; |
9738b2c9 | 1691 | |
e6aa9abd | 1692 | svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm); |
3d6368ef | 1693 | |
9738b2c9 JR |
1694 | nested_svm_unmap(nested_msrpm, KM_USER0); |
1695 | ||
1696 | return true; | |
3d6368ef AG |
1697 | } |
1698 | ||
9738b2c9 | 1699 | static bool nested_svm_vmrun(struct vcpu_svm *svm) |
3d6368ef | 1700 | { |
9738b2c9 | 1701 | struct vmcb *nested_vmcb; |
e6aa9abd | 1702 | struct vmcb *hsave = svm->nested.hsave; |
defbba56 | 1703 | struct vmcb *vmcb = svm->vmcb; |
3d6368ef | 1704 | |
9738b2c9 JR |
1705 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0); |
1706 | if (!nested_vmcb) | |
1707 | return false; | |
1708 | ||
3d6368ef | 1709 | /* nested_vmcb is our indicator if nested SVM is activated */ |
e6aa9abd | 1710 | svm->nested.vmcb = svm->vmcb->save.rax; |
3d6368ef AG |
1711 | |
1712 | /* Clear internal status */ | |
219b65dc AG |
1713 | kvm_clear_exception_queue(&svm->vcpu); |
1714 | kvm_clear_interrupt_queue(&svm->vcpu); | |
3d6368ef AG |
1715 | |
1716 | /* Save the old vmcb, so we don't need to pick what we save, but | |
1717 | can restore everything when a VMEXIT occurs */ | |
defbba56 JR |
1718 | hsave->save.es = vmcb->save.es; |
1719 | hsave->save.cs = vmcb->save.cs; | |
1720 | hsave->save.ss = vmcb->save.ss; | |
1721 | hsave->save.ds = vmcb->save.ds; | |
1722 | hsave->save.gdtr = vmcb->save.gdtr; | |
1723 | hsave->save.idtr = vmcb->save.idtr; | |
1724 | hsave->save.efer = svm->vcpu.arch.shadow_efer; | |
1725 | hsave->save.cr0 = svm->vcpu.arch.cr0; | |
1726 | hsave->save.cr4 = svm->vcpu.arch.cr4; | |
1727 | hsave->save.rflags = vmcb->save.rflags; | |
1728 | hsave->save.rip = svm->next_rip; | |
1729 | hsave->save.rsp = vmcb->save.rsp; | |
1730 | hsave->save.rax = vmcb->save.rax; | |
1731 | if (npt_enabled) | |
1732 | hsave->save.cr3 = vmcb->save.cr3; | |
1733 | else | |
1734 | hsave->save.cr3 = svm->vcpu.arch.cr3; | |
1735 | ||
0460a979 | 1736 | copy_vmcb_control_area(hsave, vmcb); |
3d6368ef AG |
1737 | |
1738 | if (svm->vmcb->save.rflags & X86_EFLAGS_IF) | |
1739 | svm->vcpu.arch.hflags |= HF_HIF_MASK; | |
1740 | else | |
1741 | svm->vcpu.arch.hflags &= ~HF_HIF_MASK; | |
1742 | ||
1743 | /* Load the nested guest state */ | |
1744 | svm->vmcb->save.es = nested_vmcb->save.es; | |
1745 | svm->vmcb->save.cs = nested_vmcb->save.cs; | |
1746 | svm->vmcb->save.ss = nested_vmcb->save.ss; | |
1747 | svm->vmcb->save.ds = nested_vmcb->save.ds; | |
1748 | svm->vmcb->save.gdtr = nested_vmcb->save.gdtr; | |
1749 | svm->vmcb->save.idtr = nested_vmcb->save.idtr; | |
1750 | svm->vmcb->save.rflags = nested_vmcb->save.rflags; | |
1751 | svm_set_efer(&svm->vcpu, nested_vmcb->save.efer); | |
1752 | svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0); | |
1753 | svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4); | |
1754 | if (npt_enabled) { | |
1755 | svm->vmcb->save.cr3 = nested_vmcb->save.cr3; | |
1756 | svm->vcpu.arch.cr3 = nested_vmcb->save.cr3; | |
1757 | } else { | |
1758 | kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3); | |
1759 | kvm_mmu_reset_context(&svm->vcpu); | |
1760 | } | |
defbba56 | 1761 | svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2; |
3d6368ef AG |
1762 | kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax); |
1763 | kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp); | |
1764 | kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip); | |
1765 | /* In case we don't even reach vcpu_run, the fields are not updated */ | |
1766 | svm->vmcb->save.rax = nested_vmcb->save.rax; | |
1767 | svm->vmcb->save.rsp = nested_vmcb->save.rsp; | |
1768 | svm->vmcb->save.rip = nested_vmcb->save.rip; | |
1769 | svm->vmcb->save.dr7 = nested_vmcb->save.dr7; | |
1770 | svm->vmcb->save.dr6 = nested_vmcb->save.dr6; | |
1771 | svm->vmcb->save.cpl = nested_vmcb->save.cpl; | |
1772 | ||
1773 | /* We don't want a nested guest to be more powerful than the guest, | |
1774 | so all intercepts are ORed */ | |
1775 | svm->vmcb->control.intercept_cr_read |= | |
1776 | nested_vmcb->control.intercept_cr_read; | |
1777 | svm->vmcb->control.intercept_cr_write |= | |
1778 | nested_vmcb->control.intercept_cr_write; | |
1779 | svm->vmcb->control.intercept_dr_read |= | |
1780 | nested_vmcb->control.intercept_dr_read; | |
1781 | svm->vmcb->control.intercept_dr_write |= | |
1782 | nested_vmcb->control.intercept_dr_write; | |
1783 | svm->vmcb->control.intercept_exceptions |= | |
1784 | nested_vmcb->control.intercept_exceptions; | |
1785 | ||
1786 | svm->vmcb->control.intercept |= nested_vmcb->control.intercept; | |
1787 | ||
e6aa9abd | 1788 | svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa; |
3d6368ef | 1789 | |
aad42c64 JR |
1790 | /* cache intercepts */ |
1791 | svm->nested.intercept_cr_read = nested_vmcb->control.intercept_cr_read; | |
1792 | svm->nested.intercept_cr_write = nested_vmcb->control.intercept_cr_write; | |
1793 | svm->nested.intercept_dr_read = nested_vmcb->control.intercept_dr_read; | |
1794 | svm->nested.intercept_dr_write = nested_vmcb->control.intercept_dr_write; | |
1795 | svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions; | |
1796 | svm->nested.intercept = nested_vmcb->control.intercept; | |
1797 | ||
3d6368ef | 1798 | force_new_asid(&svm->vcpu); |
3d6368ef AG |
1799 | svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK; |
1800 | if (nested_vmcb->control.int_ctl & V_IRQ_MASK) { | |
1801 | nsvm_printk("nSVM Injecting Interrupt: 0x%x\n", | |
1802 | nested_vmcb->control.int_ctl); | |
1803 | } | |
1804 | if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK) | |
1805 | svm->vcpu.arch.hflags |= HF_VINTR_MASK; | |
1806 | else | |
1807 | svm->vcpu.arch.hflags &= ~HF_VINTR_MASK; | |
1808 | ||
1809 | nsvm_printk("nSVM exit_int_info: 0x%x | int_state: 0x%x\n", | |
1810 | nested_vmcb->control.exit_int_info, | |
1811 | nested_vmcb->control.int_state); | |
1812 | ||
1813 | svm->vmcb->control.int_vector = nested_vmcb->control.int_vector; | |
1814 | svm->vmcb->control.int_state = nested_vmcb->control.int_state; | |
1815 | svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset; | |
1816 | if (nested_vmcb->control.event_inj & SVM_EVTINJ_VALID) | |
1817 | nsvm_printk("Injecting Event: 0x%x\n", | |
1818 | nested_vmcb->control.event_inj); | |
1819 | svm->vmcb->control.event_inj = nested_vmcb->control.event_inj; | |
1820 | svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err; | |
1821 | ||
9738b2c9 JR |
1822 | nested_svm_unmap(nested_vmcb, KM_USER0); |
1823 | ||
2af9194d | 1824 | enable_gif(svm); |
3d6368ef | 1825 | |
9738b2c9 | 1826 | return true; |
3d6368ef AG |
1827 | } |
1828 | ||
9966bf68 | 1829 | static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb) |
5542675b AG |
1830 | { |
1831 | to_vmcb->save.fs = from_vmcb->save.fs; | |
1832 | to_vmcb->save.gs = from_vmcb->save.gs; | |
1833 | to_vmcb->save.tr = from_vmcb->save.tr; | |
1834 | to_vmcb->save.ldtr = from_vmcb->save.ldtr; | |
1835 | to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base; | |
1836 | to_vmcb->save.star = from_vmcb->save.star; | |
1837 | to_vmcb->save.lstar = from_vmcb->save.lstar; | |
1838 | to_vmcb->save.cstar = from_vmcb->save.cstar; | |
1839 | to_vmcb->save.sfmask = from_vmcb->save.sfmask; | |
1840 | to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs; | |
1841 | to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp; | |
1842 | to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip; | |
5542675b AG |
1843 | } |
1844 | ||
851ba692 | 1845 | static int vmload_interception(struct vcpu_svm *svm) |
5542675b | 1846 | { |
9966bf68 JR |
1847 | struct vmcb *nested_vmcb; |
1848 | ||
5542675b AG |
1849 | if (nested_svm_check_permissions(svm)) |
1850 | return 1; | |
1851 | ||
1852 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
1853 | skip_emulated_instruction(&svm->vcpu); | |
1854 | ||
9966bf68 JR |
1855 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0); |
1856 | if (!nested_vmcb) | |
1857 | return 1; | |
1858 | ||
1859 | nested_svm_vmloadsave(nested_vmcb, svm->vmcb); | |
1860 | nested_svm_unmap(nested_vmcb, KM_USER0); | |
5542675b AG |
1861 | |
1862 | return 1; | |
1863 | } | |
1864 | ||
851ba692 | 1865 | static int vmsave_interception(struct vcpu_svm *svm) |
5542675b | 1866 | { |
9966bf68 JR |
1867 | struct vmcb *nested_vmcb; |
1868 | ||
5542675b AG |
1869 | if (nested_svm_check_permissions(svm)) |
1870 | return 1; | |
1871 | ||
1872 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
1873 | skip_emulated_instruction(&svm->vcpu); | |
1874 | ||
9966bf68 JR |
1875 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0); |
1876 | if (!nested_vmcb) | |
1877 | return 1; | |
1878 | ||
1879 | nested_svm_vmloadsave(svm->vmcb, nested_vmcb); | |
1880 | nested_svm_unmap(nested_vmcb, KM_USER0); | |
5542675b AG |
1881 | |
1882 | return 1; | |
1883 | } | |
1884 | ||
851ba692 | 1885 | static int vmrun_interception(struct vcpu_svm *svm) |
3d6368ef AG |
1886 | { |
1887 | nsvm_printk("VMrun\n"); | |
1f8da478 | 1888 | |
3d6368ef AG |
1889 | if (nested_svm_check_permissions(svm)) |
1890 | return 1; | |
1891 | ||
1892 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
1893 | skip_emulated_instruction(&svm->vcpu); | |
1894 | ||
9738b2c9 | 1895 | if (!nested_svm_vmrun(svm)) |
3d6368ef AG |
1896 | return 1; |
1897 | ||
9738b2c9 | 1898 | if (!nested_svm_vmrun_msrpm(svm)) |
1f8da478 JR |
1899 | goto failed; |
1900 | ||
1901 | return 1; | |
1902 | ||
1903 | failed: | |
1904 | ||
1905 | svm->vmcb->control.exit_code = SVM_EXIT_ERR; | |
1906 | svm->vmcb->control.exit_code_hi = 0; | |
1907 | svm->vmcb->control.exit_info_1 = 0; | |
1908 | svm->vmcb->control.exit_info_2 = 0; | |
1909 | ||
1910 | nested_svm_vmexit(svm); | |
3d6368ef AG |
1911 | |
1912 | return 1; | |
1913 | } | |
1914 | ||
851ba692 | 1915 | static int stgi_interception(struct vcpu_svm *svm) |
1371d904 AG |
1916 | { |
1917 | if (nested_svm_check_permissions(svm)) | |
1918 | return 1; | |
1919 | ||
1920 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
1921 | skip_emulated_instruction(&svm->vcpu); | |
1922 | ||
2af9194d | 1923 | enable_gif(svm); |
1371d904 AG |
1924 | |
1925 | return 1; | |
1926 | } | |
1927 | ||
851ba692 | 1928 | static int clgi_interception(struct vcpu_svm *svm) |
1371d904 AG |
1929 | { |
1930 | if (nested_svm_check_permissions(svm)) | |
1931 | return 1; | |
1932 | ||
1933 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
1934 | skip_emulated_instruction(&svm->vcpu); | |
1935 | ||
2af9194d | 1936 | disable_gif(svm); |
1371d904 AG |
1937 | |
1938 | /* After a CLGI no interrupts should come */ | |
1939 | svm_clear_vintr(svm); | |
1940 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; | |
1941 | ||
1942 | return 1; | |
1943 | } | |
1944 | ||
851ba692 | 1945 | static int invlpga_interception(struct vcpu_svm *svm) |
ff092385 AG |
1946 | { |
1947 | struct kvm_vcpu *vcpu = &svm->vcpu; | |
1948 | nsvm_printk("INVLPGA\n"); | |
1949 | ||
1950 | /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */ | |
1951 | kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]); | |
1952 | ||
1953 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
1954 | skip_emulated_instruction(&svm->vcpu); | |
1955 | return 1; | |
1956 | } | |
1957 | ||
851ba692 | 1958 | static int invalid_op_interception(struct vcpu_svm *svm) |
6aa8b732 | 1959 | { |
7ee5d940 | 1960 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
6aa8b732 AK |
1961 | return 1; |
1962 | } | |
1963 | ||
851ba692 | 1964 | static int task_switch_interception(struct vcpu_svm *svm) |
6aa8b732 | 1965 | { |
37817f29 | 1966 | u16 tss_selector; |
64a7ec06 GN |
1967 | int reason; |
1968 | int int_type = svm->vmcb->control.exit_int_info & | |
1969 | SVM_EXITINTINFO_TYPE_MASK; | |
8317c298 | 1970 | int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK; |
fe8e7f83 GN |
1971 | uint32_t type = |
1972 | svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK; | |
1973 | uint32_t idt_v = | |
1974 | svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID; | |
37817f29 IE |
1975 | |
1976 | tss_selector = (u16)svm->vmcb->control.exit_info_1; | |
64a7ec06 | 1977 | |
37817f29 IE |
1978 | if (svm->vmcb->control.exit_info_2 & |
1979 | (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET)) | |
64a7ec06 GN |
1980 | reason = TASK_SWITCH_IRET; |
1981 | else if (svm->vmcb->control.exit_info_2 & | |
1982 | (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP)) | |
1983 | reason = TASK_SWITCH_JMP; | |
fe8e7f83 | 1984 | else if (idt_v) |
64a7ec06 GN |
1985 | reason = TASK_SWITCH_GATE; |
1986 | else | |
1987 | reason = TASK_SWITCH_CALL; | |
1988 | ||
fe8e7f83 GN |
1989 | if (reason == TASK_SWITCH_GATE) { |
1990 | switch (type) { | |
1991 | case SVM_EXITINTINFO_TYPE_NMI: | |
1992 | svm->vcpu.arch.nmi_injected = false; | |
1993 | break; | |
1994 | case SVM_EXITINTINFO_TYPE_EXEPT: | |
1995 | kvm_clear_exception_queue(&svm->vcpu); | |
1996 | break; | |
1997 | case SVM_EXITINTINFO_TYPE_INTR: | |
1998 | kvm_clear_interrupt_queue(&svm->vcpu); | |
1999 | break; | |
2000 | default: | |
2001 | break; | |
2002 | } | |
2003 | } | |
64a7ec06 | 2004 | |
8317c298 GN |
2005 | if (reason != TASK_SWITCH_GATE || |
2006 | int_type == SVM_EXITINTINFO_TYPE_SOFT || | |
2007 | (int_type == SVM_EXITINTINFO_TYPE_EXEPT && | |
f629cf84 GN |
2008 | (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) |
2009 | skip_emulated_instruction(&svm->vcpu); | |
64a7ec06 GN |
2010 | |
2011 | return kvm_task_switch(&svm->vcpu, tss_selector, reason); | |
6aa8b732 AK |
2012 | } |
2013 | ||
851ba692 | 2014 | static int cpuid_interception(struct vcpu_svm *svm) |
6aa8b732 | 2015 | { |
5fdbf976 | 2016 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
e756fc62 | 2017 | kvm_emulate_cpuid(&svm->vcpu); |
06465c5a | 2018 | return 1; |
6aa8b732 AK |
2019 | } |
2020 | ||
851ba692 | 2021 | static int iret_interception(struct vcpu_svm *svm) |
95ba8273 GN |
2022 | { |
2023 | ++svm->vcpu.stat.nmi_window_exits; | |
2024 | svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET); | |
44c11430 | 2025 | svm->vcpu.arch.hflags |= HF_IRET_MASK; |
95ba8273 GN |
2026 | return 1; |
2027 | } | |
2028 | ||
851ba692 | 2029 | static int invlpg_interception(struct vcpu_svm *svm) |
a7052897 | 2030 | { |
851ba692 | 2031 | if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE) |
a7052897 MT |
2032 | pr_unimpl(&svm->vcpu, "%s: failed\n", __func__); |
2033 | return 1; | |
2034 | } | |
2035 | ||
851ba692 | 2036 | static int emulate_on_interception(struct vcpu_svm *svm) |
6aa8b732 | 2037 | { |
851ba692 | 2038 | if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE) |
b8688d51 | 2039 | pr_unimpl(&svm->vcpu, "%s: failed\n", __func__); |
6aa8b732 AK |
2040 | return 1; |
2041 | } | |
2042 | ||
851ba692 | 2043 | static int cr8_write_interception(struct vcpu_svm *svm) |
1d075434 | 2044 | { |
851ba692 AK |
2045 | struct kvm_run *kvm_run = svm->vcpu.run; |
2046 | ||
0a5fff19 GN |
2047 | u8 cr8_prev = kvm_get_cr8(&svm->vcpu); |
2048 | /* instruction emulation calls kvm_set_cr8() */ | |
851ba692 | 2049 | emulate_instruction(&svm->vcpu, 0, 0, 0); |
95ba8273 GN |
2050 | if (irqchip_in_kernel(svm->vcpu.kvm)) { |
2051 | svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK; | |
1d075434 | 2052 | return 1; |
95ba8273 | 2053 | } |
0a5fff19 GN |
2054 | if (cr8_prev <= kvm_get_cr8(&svm->vcpu)) |
2055 | return 1; | |
1d075434 JR |
2056 | kvm_run->exit_reason = KVM_EXIT_SET_TPR; |
2057 | return 0; | |
2058 | } | |
2059 | ||
6aa8b732 AK |
2060 | static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data) |
2061 | { | |
a2fa3e9f GH |
2062 | struct vcpu_svm *svm = to_svm(vcpu); |
2063 | ||
6aa8b732 | 2064 | switch (ecx) { |
af24a4e4 | 2065 | case MSR_IA32_TSC: { |
20824f30 | 2066 | u64 tsc_offset; |
6aa8b732 | 2067 | |
20824f30 JR |
2068 | if (is_nested(svm)) |
2069 | tsc_offset = svm->nested.hsave->control.tsc_offset; | |
2070 | else | |
2071 | tsc_offset = svm->vmcb->control.tsc_offset; | |
2072 | ||
2073 | *data = tsc_offset + native_read_tsc(); | |
6aa8b732 AK |
2074 | break; |
2075 | } | |
0e859cac | 2076 | case MSR_K6_STAR: |
a2fa3e9f | 2077 | *data = svm->vmcb->save.star; |
6aa8b732 | 2078 | break; |
0e859cac | 2079 | #ifdef CONFIG_X86_64 |
6aa8b732 | 2080 | case MSR_LSTAR: |
a2fa3e9f | 2081 | *data = svm->vmcb->save.lstar; |
6aa8b732 AK |
2082 | break; |
2083 | case MSR_CSTAR: | |
a2fa3e9f | 2084 | *data = svm->vmcb->save.cstar; |
6aa8b732 AK |
2085 | break; |
2086 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 2087 | *data = svm->vmcb->save.kernel_gs_base; |
6aa8b732 AK |
2088 | break; |
2089 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 2090 | *data = svm->vmcb->save.sfmask; |
6aa8b732 AK |
2091 | break; |
2092 | #endif | |
2093 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 2094 | *data = svm->vmcb->save.sysenter_cs; |
6aa8b732 AK |
2095 | break; |
2096 | case MSR_IA32_SYSENTER_EIP: | |
017cb99e | 2097 | *data = svm->sysenter_eip; |
6aa8b732 AK |
2098 | break; |
2099 | case MSR_IA32_SYSENTER_ESP: | |
017cb99e | 2100 | *data = svm->sysenter_esp; |
6aa8b732 | 2101 | break; |
a2938c80 JR |
2102 | /* Nobody will change the following 5 values in the VMCB so |
2103 | we can safely return them on rdmsr. They will always be 0 | |
2104 | until LBRV is implemented. */ | |
2105 | case MSR_IA32_DEBUGCTLMSR: | |
2106 | *data = svm->vmcb->save.dbgctl; | |
2107 | break; | |
2108 | case MSR_IA32_LASTBRANCHFROMIP: | |
2109 | *data = svm->vmcb->save.br_from; | |
2110 | break; | |
2111 | case MSR_IA32_LASTBRANCHTOIP: | |
2112 | *data = svm->vmcb->save.br_to; | |
2113 | break; | |
2114 | case MSR_IA32_LASTINTFROMIP: | |
2115 | *data = svm->vmcb->save.last_excp_from; | |
2116 | break; | |
2117 | case MSR_IA32_LASTINTTOIP: | |
2118 | *data = svm->vmcb->save.last_excp_to; | |
2119 | break; | |
b286d5d8 | 2120 | case MSR_VM_HSAVE_PA: |
e6aa9abd | 2121 | *data = svm->nested.hsave_msr; |
b286d5d8 | 2122 | break; |
eb6f302e JR |
2123 | case MSR_VM_CR: |
2124 | *data = 0; | |
2125 | break; | |
c8a73f18 AG |
2126 | case MSR_IA32_UCODE_REV: |
2127 | *data = 0x01000065; | |
2128 | break; | |
6aa8b732 | 2129 | default: |
3bab1f5d | 2130 | return kvm_get_msr_common(vcpu, ecx, data); |
6aa8b732 AK |
2131 | } |
2132 | return 0; | |
2133 | } | |
2134 | ||
851ba692 | 2135 | static int rdmsr_interception(struct vcpu_svm *svm) |
6aa8b732 | 2136 | { |
ad312c7c | 2137 | u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
6aa8b732 AK |
2138 | u64 data; |
2139 | ||
e756fc62 | 2140 | if (svm_get_msr(&svm->vcpu, ecx, &data)) |
c1a5d4f9 | 2141 | kvm_inject_gp(&svm->vcpu, 0); |
6aa8b732 | 2142 | else { |
229456fc | 2143 | trace_kvm_msr_read(ecx, data); |
af9ca2d7 | 2144 | |
5fdbf976 | 2145 | svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff; |
ad312c7c | 2146 | svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32; |
5fdbf976 | 2147 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
e756fc62 | 2148 | skip_emulated_instruction(&svm->vcpu); |
6aa8b732 AK |
2149 | } |
2150 | return 1; | |
2151 | } | |
2152 | ||
2153 | static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data) | |
2154 | { | |
a2fa3e9f GH |
2155 | struct vcpu_svm *svm = to_svm(vcpu); |
2156 | ||
6aa8b732 | 2157 | switch (ecx) { |
af24a4e4 | 2158 | case MSR_IA32_TSC: { |
20824f30 JR |
2159 | u64 tsc_offset = data - native_read_tsc(); |
2160 | u64 g_tsc_offset = 0; | |
2161 | ||
2162 | if (is_nested(svm)) { | |
2163 | g_tsc_offset = svm->vmcb->control.tsc_offset - | |
2164 | svm->nested.hsave->control.tsc_offset; | |
2165 | svm->nested.hsave->control.tsc_offset = tsc_offset; | |
2166 | } | |
2167 | ||
2168 | svm->vmcb->control.tsc_offset = tsc_offset + g_tsc_offset; | |
6aa8b732 | 2169 | |
6aa8b732 AK |
2170 | break; |
2171 | } | |
0e859cac | 2172 | case MSR_K6_STAR: |
a2fa3e9f | 2173 | svm->vmcb->save.star = data; |
6aa8b732 | 2174 | break; |
49b14f24 | 2175 | #ifdef CONFIG_X86_64 |
6aa8b732 | 2176 | case MSR_LSTAR: |
a2fa3e9f | 2177 | svm->vmcb->save.lstar = data; |
6aa8b732 AK |
2178 | break; |
2179 | case MSR_CSTAR: | |
a2fa3e9f | 2180 | svm->vmcb->save.cstar = data; |
6aa8b732 AK |
2181 | break; |
2182 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 2183 | svm->vmcb->save.kernel_gs_base = data; |
6aa8b732 AK |
2184 | break; |
2185 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 2186 | svm->vmcb->save.sfmask = data; |
6aa8b732 AK |
2187 | break; |
2188 | #endif | |
2189 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 2190 | svm->vmcb->save.sysenter_cs = data; |
6aa8b732 AK |
2191 | break; |
2192 | case MSR_IA32_SYSENTER_EIP: | |
017cb99e | 2193 | svm->sysenter_eip = data; |
a2fa3e9f | 2194 | svm->vmcb->save.sysenter_eip = data; |
6aa8b732 AK |
2195 | break; |
2196 | case MSR_IA32_SYSENTER_ESP: | |
017cb99e | 2197 | svm->sysenter_esp = data; |
a2fa3e9f | 2198 | svm->vmcb->save.sysenter_esp = data; |
6aa8b732 | 2199 | break; |
a2938c80 | 2200 | case MSR_IA32_DEBUGCTLMSR: |
24e09cbf JR |
2201 | if (!svm_has(SVM_FEATURE_LBRV)) { |
2202 | pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n", | |
b8688d51 | 2203 | __func__, data); |
24e09cbf JR |
2204 | break; |
2205 | } | |
2206 | if (data & DEBUGCTL_RESERVED_BITS) | |
2207 | return 1; | |
2208 | ||
2209 | svm->vmcb->save.dbgctl = data; | |
2210 | if (data & (1ULL<<0)) | |
2211 | svm_enable_lbrv(svm); | |
2212 | else | |
2213 | svm_disable_lbrv(svm); | |
a2938c80 | 2214 | break; |
b286d5d8 | 2215 | case MSR_VM_HSAVE_PA: |
e6aa9abd | 2216 | svm->nested.hsave_msr = data; |
62b9abaa | 2217 | break; |
3c5d0a44 AG |
2218 | case MSR_VM_CR: |
2219 | case MSR_VM_IGNNE: | |
3c5d0a44 AG |
2220 | pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data); |
2221 | break; | |
6aa8b732 | 2222 | default: |
3bab1f5d | 2223 | return kvm_set_msr_common(vcpu, ecx, data); |
6aa8b732 AK |
2224 | } |
2225 | return 0; | |
2226 | } | |
2227 | ||
851ba692 | 2228 | static int wrmsr_interception(struct vcpu_svm *svm) |
6aa8b732 | 2229 | { |
ad312c7c | 2230 | u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
5fdbf976 | 2231 | u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u) |
ad312c7c | 2232 | | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32); |
af9ca2d7 | 2233 | |
229456fc | 2234 | trace_kvm_msr_write(ecx, data); |
af9ca2d7 | 2235 | |
5fdbf976 | 2236 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
e756fc62 | 2237 | if (svm_set_msr(&svm->vcpu, ecx, data)) |
c1a5d4f9 | 2238 | kvm_inject_gp(&svm->vcpu, 0); |
6aa8b732 | 2239 | else |
e756fc62 | 2240 | skip_emulated_instruction(&svm->vcpu); |
6aa8b732 AK |
2241 | return 1; |
2242 | } | |
2243 | ||
851ba692 | 2244 | static int msr_interception(struct vcpu_svm *svm) |
6aa8b732 | 2245 | { |
e756fc62 | 2246 | if (svm->vmcb->control.exit_info_1) |
851ba692 | 2247 | return wrmsr_interception(svm); |
6aa8b732 | 2248 | else |
851ba692 | 2249 | return rdmsr_interception(svm); |
6aa8b732 AK |
2250 | } |
2251 | ||
851ba692 | 2252 | static int interrupt_window_interception(struct vcpu_svm *svm) |
c1150d8c | 2253 | { |
851ba692 AK |
2254 | struct kvm_run *kvm_run = svm->vcpu.run; |
2255 | ||
f0b85051 | 2256 | svm_clear_vintr(svm); |
85f455f7 | 2257 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; |
c1150d8c DL |
2258 | /* |
2259 | * If the user space waits to inject interrupts, exit as soon as | |
2260 | * possible | |
2261 | */ | |
8061823a GN |
2262 | if (!irqchip_in_kernel(svm->vcpu.kvm) && |
2263 | kvm_run->request_interrupt_window && | |
2264 | !kvm_cpu_has_interrupt(&svm->vcpu)) { | |
e756fc62 | 2265 | ++svm->vcpu.stat.irq_window_exits; |
c1150d8c DL |
2266 | kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; |
2267 | return 0; | |
2268 | } | |
2269 | ||
2270 | return 1; | |
2271 | } | |
2272 | ||
851ba692 | 2273 | static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = { |
6aa8b732 AK |
2274 | [SVM_EXIT_READ_CR0] = emulate_on_interception, |
2275 | [SVM_EXIT_READ_CR3] = emulate_on_interception, | |
2276 | [SVM_EXIT_READ_CR4] = emulate_on_interception, | |
80a8119c | 2277 | [SVM_EXIT_READ_CR8] = emulate_on_interception, |
6aa8b732 AK |
2278 | /* for now: */ |
2279 | [SVM_EXIT_WRITE_CR0] = emulate_on_interception, | |
2280 | [SVM_EXIT_WRITE_CR3] = emulate_on_interception, | |
2281 | [SVM_EXIT_WRITE_CR4] = emulate_on_interception, | |
1d075434 | 2282 | [SVM_EXIT_WRITE_CR8] = cr8_write_interception, |
6aa8b732 AK |
2283 | [SVM_EXIT_READ_DR0] = emulate_on_interception, |
2284 | [SVM_EXIT_READ_DR1] = emulate_on_interception, | |
2285 | [SVM_EXIT_READ_DR2] = emulate_on_interception, | |
2286 | [SVM_EXIT_READ_DR3] = emulate_on_interception, | |
2287 | [SVM_EXIT_WRITE_DR0] = emulate_on_interception, | |
2288 | [SVM_EXIT_WRITE_DR1] = emulate_on_interception, | |
2289 | [SVM_EXIT_WRITE_DR2] = emulate_on_interception, | |
2290 | [SVM_EXIT_WRITE_DR3] = emulate_on_interception, | |
2291 | [SVM_EXIT_WRITE_DR5] = emulate_on_interception, | |
2292 | [SVM_EXIT_WRITE_DR7] = emulate_on_interception, | |
d0bfb940 JK |
2293 | [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception, |
2294 | [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception, | |
7aa81cc0 | 2295 | [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception, |
6aa8b732 | 2296 | [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception, |
7807fa6c | 2297 | [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception, |
53371b50 | 2298 | [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception, |
a0698055 | 2299 | [SVM_EXIT_INTR] = intr_interception, |
c47f098d | 2300 | [SVM_EXIT_NMI] = nmi_interception, |
6aa8b732 AK |
2301 | [SVM_EXIT_SMI] = nop_on_interception, |
2302 | [SVM_EXIT_INIT] = nop_on_interception, | |
c1150d8c | 2303 | [SVM_EXIT_VINTR] = interrupt_window_interception, |
6aa8b732 AK |
2304 | /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */ |
2305 | [SVM_EXIT_CPUID] = cpuid_interception, | |
95ba8273 | 2306 | [SVM_EXIT_IRET] = iret_interception, |
cf5a94d1 | 2307 | [SVM_EXIT_INVD] = emulate_on_interception, |
6aa8b732 | 2308 | [SVM_EXIT_HLT] = halt_interception, |
a7052897 | 2309 | [SVM_EXIT_INVLPG] = invlpg_interception, |
ff092385 | 2310 | [SVM_EXIT_INVLPGA] = invlpga_interception, |
6aa8b732 AK |
2311 | [SVM_EXIT_IOIO] = io_interception, |
2312 | [SVM_EXIT_MSR] = msr_interception, | |
2313 | [SVM_EXIT_TASK_SWITCH] = task_switch_interception, | |
46fe4ddd | 2314 | [SVM_EXIT_SHUTDOWN] = shutdown_interception, |
3d6368ef | 2315 | [SVM_EXIT_VMRUN] = vmrun_interception, |
02e235bc | 2316 | [SVM_EXIT_VMMCALL] = vmmcall_interception, |
5542675b AG |
2317 | [SVM_EXIT_VMLOAD] = vmload_interception, |
2318 | [SVM_EXIT_VMSAVE] = vmsave_interception, | |
1371d904 AG |
2319 | [SVM_EXIT_STGI] = stgi_interception, |
2320 | [SVM_EXIT_CLGI] = clgi_interception, | |
6aa8b732 | 2321 | [SVM_EXIT_SKINIT] = invalid_op_interception, |
cf5a94d1 | 2322 | [SVM_EXIT_WBINVD] = emulate_on_interception, |
916ce236 JR |
2323 | [SVM_EXIT_MONITOR] = invalid_op_interception, |
2324 | [SVM_EXIT_MWAIT] = invalid_op_interception, | |
709ddebf | 2325 | [SVM_EXIT_NPF] = pf_interception, |
6aa8b732 AK |
2326 | }; |
2327 | ||
851ba692 | 2328 | static int handle_exit(struct kvm_vcpu *vcpu) |
6aa8b732 | 2329 | { |
04d2cc77 | 2330 | struct vcpu_svm *svm = to_svm(vcpu); |
851ba692 | 2331 | struct kvm_run *kvm_run = vcpu->run; |
a2fa3e9f | 2332 | u32 exit_code = svm->vmcb->control.exit_code; |
6aa8b732 | 2333 | |
229456fc | 2334 | trace_kvm_exit(exit_code, svm->vmcb->save.rip); |
af9ca2d7 | 2335 | |
cf74a78b | 2336 | if (is_nested(svm)) { |
410e4d57 JR |
2337 | int vmexit; |
2338 | ||
cf74a78b AG |
2339 | nsvm_printk("nested handle_exit: 0x%x | 0x%lx | 0x%lx | 0x%lx\n", |
2340 | exit_code, svm->vmcb->control.exit_info_1, | |
2341 | svm->vmcb->control.exit_info_2, svm->vmcb->save.rip); | |
410e4d57 JR |
2342 | |
2343 | vmexit = nested_svm_exit_special(svm); | |
2344 | ||
2345 | if (vmexit == NESTED_EXIT_CONTINUE) | |
2346 | vmexit = nested_svm_exit_handled(svm); | |
2347 | ||
2348 | if (vmexit == NESTED_EXIT_DONE) | |
cf74a78b | 2349 | return 1; |
cf74a78b AG |
2350 | } |
2351 | ||
a5c3832d JR |
2352 | svm_complete_interrupts(svm); |
2353 | ||
709ddebf JR |
2354 | if (npt_enabled) { |
2355 | int mmu_reload = 0; | |
2356 | if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) { | |
2357 | svm_set_cr0(vcpu, svm->vmcb->save.cr0); | |
2358 | mmu_reload = 1; | |
2359 | } | |
2360 | vcpu->arch.cr0 = svm->vmcb->save.cr0; | |
2361 | vcpu->arch.cr3 = svm->vmcb->save.cr3; | |
709ddebf JR |
2362 | if (mmu_reload) { |
2363 | kvm_mmu_reset_context(vcpu); | |
2364 | kvm_mmu_load(vcpu); | |
2365 | } | |
2366 | } | |
2367 | ||
04d2cc77 AK |
2368 | |
2369 | if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) { | |
2370 | kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY; | |
2371 | kvm_run->fail_entry.hardware_entry_failure_reason | |
2372 | = svm->vmcb->control.exit_code; | |
2373 | return 0; | |
2374 | } | |
2375 | ||
a2fa3e9f | 2376 | if (is_external_interrupt(svm->vmcb->control.exit_int_info) && |
709ddebf | 2377 | exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR && |
fe8e7f83 | 2378 | exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH) |
6aa8b732 AK |
2379 | printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x " |
2380 | "exit_code 0x%x\n", | |
b8688d51 | 2381 | __func__, svm->vmcb->control.exit_int_info, |
6aa8b732 AK |
2382 | exit_code); |
2383 | ||
9d8f549d | 2384 | if (exit_code >= ARRAY_SIZE(svm_exit_handlers) |
56919c5c | 2385 | || !svm_exit_handlers[exit_code]) { |
6aa8b732 | 2386 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; |
364b625b | 2387 | kvm_run->hw.hardware_exit_reason = exit_code; |
6aa8b732 AK |
2388 | return 0; |
2389 | } | |
2390 | ||
851ba692 | 2391 | return svm_exit_handlers[exit_code](svm); |
6aa8b732 AK |
2392 | } |
2393 | ||
2394 | static void reload_tss(struct kvm_vcpu *vcpu) | |
2395 | { | |
2396 | int cpu = raw_smp_processor_id(); | |
2397 | ||
2398 | struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu); | |
d77c26fc | 2399 | svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */ |
6aa8b732 AK |
2400 | load_TR_desc(); |
2401 | } | |
2402 | ||
e756fc62 | 2403 | static void pre_svm_run(struct vcpu_svm *svm) |
6aa8b732 AK |
2404 | { |
2405 | int cpu = raw_smp_processor_id(); | |
2406 | ||
2407 | struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu); | |
2408 | ||
a2fa3e9f | 2409 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING; |
4b656b12 MT |
2410 | /* FIXME: handle wraparound of asid_generation */ |
2411 | if (svm->asid_generation != svm_data->asid_generation) | |
e756fc62 | 2412 | new_asid(svm, svm_data); |
6aa8b732 AK |
2413 | } |
2414 | ||
95ba8273 GN |
2415 | static void svm_inject_nmi(struct kvm_vcpu *vcpu) |
2416 | { | |
2417 | struct vcpu_svm *svm = to_svm(vcpu); | |
2418 | ||
2419 | svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI; | |
2420 | vcpu->arch.hflags |= HF_NMI_MASK; | |
2421 | svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET); | |
2422 | ++vcpu->stat.nmi_injections; | |
2423 | } | |
6aa8b732 | 2424 | |
85f455f7 | 2425 | static inline void svm_inject_irq(struct vcpu_svm *svm, int irq) |
6aa8b732 AK |
2426 | { |
2427 | struct vmcb_control_area *control; | |
2428 | ||
229456fc | 2429 | trace_kvm_inj_virq(irq); |
af9ca2d7 | 2430 | |
fa89a817 | 2431 | ++svm->vcpu.stat.irq_injections; |
e756fc62 | 2432 | control = &svm->vmcb->control; |
85f455f7 | 2433 | control->int_vector = irq; |
6aa8b732 AK |
2434 | control->int_ctl &= ~V_INTR_PRIO_MASK; |
2435 | control->int_ctl |= V_IRQ_MASK | | |
2436 | ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT); | |
2437 | } | |
2438 | ||
66fd3f7f | 2439 | static void svm_set_irq(struct kvm_vcpu *vcpu) |
2a8067f1 ED |
2440 | { |
2441 | struct vcpu_svm *svm = to_svm(vcpu); | |
2442 | ||
2af9194d | 2443 | BUG_ON(!(gif_set(svm))); |
cf74a78b | 2444 | |
219b65dc AG |
2445 | svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr | |
2446 | SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR; | |
2a8067f1 ED |
2447 | } |
2448 | ||
95ba8273 | 2449 | static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr) |
aaacfc9a JR |
2450 | { |
2451 | struct vcpu_svm *svm = to_svm(vcpu); | |
aaacfc9a | 2452 | |
95ba8273 | 2453 | if (irr == -1) |
aaacfc9a JR |
2454 | return; |
2455 | ||
95ba8273 GN |
2456 | if (tpr >= irr) |
2457 | svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK; | |
2458 | } | |
aaacfc9a | 2459 | |
95ba8273 GN |
2460 | static int svm_nmi_allowed(struct kvm_vcpu *vcpu) |
2461 | { | |
2462 | struct vcpu_svm *svm = to_svm(vcpu); | |
2463 | struct vmcb *vmcb = svm->vmcb; | |
2464 | return !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) && | |
2465 | !(svm->vcpu.arch.hflags & HF_NMI_MASK); | |
aaacfc9a JR |
2466 | } |
2467 | ||
78646121 GN |
2468 | static int svm_interrupt_allowed(struct kvm_vcpu *vcpu) |
2469 | { | |
2470 | struct vcpu_svm *svm = to_svm(vcpu); | |
2471 | struct vmcb *vmcb = svm->vmcb; | |
7fcdb510 JR |
2472 | int ret; |
2473 | ||
2474 | if (!gif_set(svm) || | |
2475 | (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)) | |
2476 | return 0; | |
2477 | ||
2478 | ret = !!(vmcb->save.rflags & X86_EFLAGS_IF); | |
2479 | ||
2480 | if (is_nested(svm)) | |
2481 | return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK); | |
2482 | ||
2483 | return ret; | |
78646121 GN |
2484 | } |
2485 | ||
9222be18 | 2486 | static void enable_irq_window(struct kvm_vcpu *vcpu) |
6aa8b732 | 2487 | { |
219b65dc AG |
2488 | struct vcpu_svm *svm = to_svm(vcpu); |
2489 | nsvm_printk("Trying to open IRQ window\n"); | |
2490 | ||
2491 | nested_svm_intr(svm); | |
2492 | ||
2493 | /* In case GIF=0 we can't rely on the CPU to tell us when | |
2494 | * GIF becomes 1, because that's a separate STGI/VMRUN intercept. | |
2495 | * The next time we get that intercept, this function will be | |
2496 | * called again though and we'll get the vintr intercept. */ | |
2af9194d | 2497 | if (gif_set(svm)) { |
219b65dc AG |
2498 | svm_set_vintr(svm); |
2499 | svm_inject_irq(svm, 0x0); | |
2500 | } | |
85f455f7 ED |
2501 | } |
2502 | ||
95ba8273 | 2503 | static void enable_nmi_window(struct kvm_vcpu *vcpu) |
c1150d8c | 2504 | { |
04d2cc77 | 2505 | struct vcpu_svm *svm = to_svm(vcpu); |
c1150d8c | 2506 | |
44c11430 GN |
2507 | if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK)) |
2508 | == HF_NMI_MASK) | |
2509 | return; /* IRET will cause a vm exit */ | |
2510 | ||
2511 | /* Something prevents NMI from been injected. Single step over | |
2512 | possible problem (IRET or exception injection or interrupt | |
2513 | shadow) */ | |
2514 | vcpu->arch.singlestep = true; | |
2515 | svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF); | |
2516 | update_db_intercept(vcpu); | |
c1150d8c DL |
2517 | } |
2518 | ||
cbc94022 IE |
2519 | static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr) |
2520 | { | |
2521 | return 0; | |
2522 | } | |
2523 | ||
d9e368d6 AK |
2524 | static void svm_flush_tlb(struct kvm_vcpu *vcpu) |
2525 | { | |
2526 | force_new_asid(vcpu); | |
2527 | } | |
2528 | ||
04d2cc77 AK |
2529 | static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu) |
2530 | { | |
2531 | } | |
2532 | ||
d7bf8221 JR |
2533 | static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu) |
2534 | { | |
2535 | struct vcpu_svm *svm = to_svm(vcpu); | |
2536 | ||
2537 | if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) { | |
2538 | int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK; | |
615d5193 | 2539 | kvm_set_cr8(vcpu, cr8); |
d7bf8221 JR |
2540 | } |
2541 | } | |
2542 | ||
649d6864 JR |
2543 | static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu) |
2544 | { | |
2545 | struct vcpu_svm *svm = to_svm(vcpu); | |
2546 | u64 cr8; | |
2547 | ||
649d6864 JR |
2548 | cr8 = kvm_get_cr8(vcpu); |
2549 | svm->vmcb->control.int_ctl &= ~V_TPR_MASK; | |
2550 | svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK; | |
2551 | } | |
2552 | ||
9222be18 GN |
2553 | static void svm_complete_interrupts(struct vcpu_svm *svm) |
2554 | { | |
2555 | u8 vector; | |
2556 | int type; | |
2557 | u32 exitintinfo = svm->vmcb->control.exit_int_info; | |
2558 | ||
44c11430 GN |
2559 | if (svm->vcpu.arch.hflags & HF_IRET_MASK) |
2560 | svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK); | |
2561 | ||
9222be18 GN |
2562 | svm->vcpu.arch.nmi_injected = false; |
2563 | kvm_clear_exception_queue(&svm->vcpu); | |
2564 | kvm_clear_interrupt_queue(&svm->vcpu); | |
2565 | ||
2566 | if (!(exitintinfo & SVM_EXITINTINFO_VALID)) | |
2567 | return; | |
2568 | ||
2569 | vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK; | |
2570 | type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK; | |
2571 | ||
2572 | switch (type) { | |
2573 | case SVM_EXITINTINFO_TYPE_NMI: | |
2574 | svm->vcpu.arch.nmi_injected = true; | |
2575 | break; | |
2576 | case SVM_EXITINTINFO_TYPE_EXEPT: | |
2577 | /* In case of software exception do not reinject an exception | |
2578 | vector, but re-execute and instruction instead */ | |
219b65dc AG |
2579 | if (is_nested(svm)) |
2580 | break; | |
66fd3f7f | 2581 | if (kvm_exception_is_soft(vector)) |
9222be18 GN |
2582 | break; |
2583 | if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) { | |
2584 | u32 err = svm->vmcb->control.exit_int_info_err; | |
2585 | kvm_queue_exception_e(&svm->vcpu, vector, err); | |
2586 | ||
2587 | } else | |
2588 | kvm_queue_exception(&svm->vcpu, vector); | |
2589 | break; | |
2590 | case SVM_EXITINTINFO_TYPE_INTR: | |
66fd3f7f | 2591 | kvm_queue_interrupt(&svm->vcpu, vector, false); |
9222be18 GN |
2592 | break; |
2593 | default: | |
2594 | break; | |
2595 | } | |
2596 | } | |
2597 | ||
80e31d4f AK |
2598 | #ifdef CONFIG_X86_64 |
2599 | #define R "r" | |
2600 | #else | |
2601 | #define R "e" | |
2602 | #endif | |
2603 | ||
851ba692 | 2604 | static void svm_vcpu_run(struct kvm_vcpu *vcpu) |
6aa8b732 | 2605 | { |
a2fa3e9f | 2606 | struct vcpu_svm *svm = to_svm(vcpu); |
6aa8b732 AK |
2607 | u16 fs_selector; |
2608 | u16 gs_selector; | |
2609 | u16 ldt_selector; | |
d9e368d6 | 2610 | |
5fdbf976 MT |
2611 | svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX]; |
2612 | svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP]; | |
2613 | svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP]; | |
2614 | ||
e756fc62 | 2615 | pre_svm_run(svm); |
6aa8b732 | 2616 | |
649d6864 JR |
2617 | sync_lapic_to_cr8(vcpu); |
2618 | ||
6aa8b732 | 2619 | save_host_msrs(vcpu); |
d6e88aec AK |
2620 | fs_selector = kvm_read_fs(); |
2621 | gs_selector = kvm_read_gs(); | |
2622 | ldt_selector = kvm_read_ldt(); | |
cda0ffdd | 2623 | svm->vmcb->save.cr2 = vcpu->arch.cr2; |
709ddebf JR |
2624 | /* required for live migration with NPT */ |
2625 | if (npt_enabled) | |
2626 | svm->vmcb->save.cr3 = vcpu->arch.cr3; | |
6aa8b732 | 2627 | |
04d2cc77 AK |
2628 | clgi(); |
2629 | ||
2630 | local_irq_enable(); | |
36241b8c | 2631 | |
6aa8b732 | 2632 | asm volatile ( |
80e31d4f AK |
2633 | "push %%"R"bp; \n\t" |
2634 | "mov %c[rbx](%[svm]), %%"R"bx \n\t" | |
2635 | "mov %c[rcx](%[svm]), %%"R"cx \n\t" | |
2636 | "mov %c[rdx](%[svm]), %%"R"dx \n\t" | |
2637 | "mov %c[rsi](%[svm]), %%"R"si \n\t" | |
2638 | "mov %c[rdi](%[svm]), %%"R"di \n\t" | |
2639 | "mov %c[rbp](%[svm]), %%"R"bp \n\t" | |
05b3e0c2 | 2640 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
2641 | "mov %c[r8](%[svm]), %%r8 \n\t" |
2642 | "mov %c[r9](%[svm]), %%r9 \n\t" | |
2643 | "mov %c[r10](%[svm]), %%r10 \n\t" | |
2644 | "mov %c[r11](%[svm]), %%r11 \n\t" | |
2645 | "mov %c[r12](%[svm]), %%r12 \n\t" | |
2646 | "mov %c[r13](%[svm]), %%r13 \n\t" | |
2647 | "mov %c[r14](%[svm]), %%r14 \n\t" | |
2648 | "mov %c[r15](%[svm]), %%r15 \n\t" | |
6aa8b732 AK |
2649 | #endif |
2650 | ||
6aa8b732 | 2651 | /* Enter guest mode */ |
80e31d4f AK |
2652 | "push %%"R"ax \n\t" |
2653 | "mov %c[vmcb](%[svm]), %%"R"ax \n\t" | |
4ecac3fd AK |
2654 | __ex(SVM_VMLOAD) "\n\t" |
2655 | __ex(SVM_VMRUN) "\n\t" | |
2656 | __ex(SVM_VMSAVE) "\n\t" | |
80e31d4f | 2657 | "pop %%"R"ax \n\t" |
6aa8b732 AK |
2658 | |
2659 | /* Save guest registers, load host registers */ | |
80e31d4f AK |
2660 | "mov %%"R"bx, %c[rbx](%[svm]) \n\t" |
2661 | "mov %%"R"cx, %c[rcx](%[svm]) \n\t" | |
2662 | "mov %%"R"dx, %c[rdx](%[svm]) \n\t" | |
2663 | "mov %%"R"si, %c[rsi](%[svm]) \n\t" | |
2664 | "mov %%"R"di, %c[rdi](%[svm]) \n\t" | |
2665 | "mov %%"R"bp, %c[rbp](%[svm]) \n\t" | |
05b3e0c2 | 2666 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
2667 | "mov %%r8, %c[r8](%[svm]) \n\t" |
2668 | "mov %%r9, %c[r9](%[svm]) \n\t" | |
2669 | "mov %%r10, %c[r10](%[svm]) \n\t" | |
2670 | "mov %%r11, %c[r11](%[svm]) \n\t" | |
2671 | "mov %%r12, %c[r12](%[svm]) \n\t" | |
2672 | "mov %%r13, %c[r13](%[svm]) \n\t" | |
2673 | "mov %%r14, %c[r14](%[svm]) \n\t" | |
2674 | "mov %%r15, %c[r15](%[svm]) \n\t" | |
6aa8b732 | 2675 | #endif |
80e31d4f | 2676 | "pop %%"R"bp" |
6aa8b732 | 2677 | : |
fb3f0f51 | 2678 | : [svm]"a"(svm), |
6aa8b732 | 2679 | [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)), |
ad312c7c ZX |
2680 | [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])), |
2681 | [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])), | |
2682 | [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])), | |
2683 | [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])), | |
2684 | [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])), | |
2685 | [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP])) | |
05b3e0c2 | 2686 | #ifdef CONFIG_X86_64 |
ad312c7c ZX |
2687 | , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])), |
2688 | [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])), | |
2689 | [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])), | |
2690 | [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])), | |
2691 | [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])), | |
2692 | [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])), | |
2693 | [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])), | |
2694 | [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15])) | |
6aa8b732 | 2695 | #endif |
54a08c04 | 2696 | : "cc", "memory" |
80e31d4f | 2697 | , R"bx", R"cx", R"dx", R"si", R"di" |
54a08c04 | 2698 | #ifdef CONFIG_X86_64 |
54a08c04 LV |
2699 | , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15" |
2700 | #endif | |
2701 | ); | |
6aa8b732 | 2702 | |
ad312c7c | 2703 | vcpu->arch.cr2 = svm->vmcb->save.cr2; |
5fdbf976 MT |
2704 | vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax; |
2705 | vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp; | |
2706 | vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip; | |
6aa8b732 | 2707 | |
d6e88aec AK |
2708 | kvm_load_fs(fs_selector); |
2709 | kvm_load_gs(gs_selector); | |
2710 | kvm_load_ldt(ldt_selector); | |
6aa8b732 AK |
2711 | load_host_msrs(vcpu); |
2712 | ||
2713 | reload_tss(vcpu); | |
2714 | ||
56ba47dd AK |
2715 | local_irq_disable(); |
2716 | ||
2717 | stgi(); | |
2718 | ||
d7bf8221 JR |
2719 | sync_cr8_to_lapic(vcpu); |
2720 | ||
a2fa3e9f | 2721 | svm->next_rip = 0; |
9222be18 | 2722 | |
6de4f3ad AK |
2723 | if (npt_enabled) { |
2724 | vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR); | |
2725 | vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR); | |
2726 | } | |
6aa8b732 AK |
2727 | } |
2728 | ||
80e31d4f AK |
2729 | #undef R |
2730 | ||
6aa8b732 AK |
2731 | static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root) |
2732 | { | |
a2fa3e9f GH |
2733 | struct vcpu_svm *svm = to_svm(vcpu); |
2734 | ||
709ddebf JR |
2735 | if (npt_enabled) { |
2736 | svm->vmcb->control.nested_cr3 = root; | |
2737 | force_new_asid(vcpu); | |
2738 | return; | |
2739 | } | |
2740 | ||
a2fa3e9f | 2741 | svm->vmcb->save.cr3 = root; |
6aa8b732 | 2742 | force_new_asid(vcpu); |
7807fa6c AL |
2743 | |
2744 | if (vcpu->fpu_active) { | |
a2fa3e9f GH |
2745 | svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR); |
2746 | svm->vmcb->save.cr0 |= X86_CR0_TS; | |
7807fa6c AL |
2747 | vcpu->fpu_active = 0; |
2748 | } | |
6aa8b732 AK |
2749 | } |
2750 | ||
6aa8b732 AK |
2751 | static int is_disabled(void) |
2752 | { | |
6031a61c JR |
2753 | u64 vm_cr; |
2754 | ||
2755 | rdmsrl(MSR_VM_CR, vm_cr); | |
2756 | if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE)) | |
2757 | return 1; | |
2758 | ||
6aa8b732 AK |
2759 | return 0; |
2760 | } | |
2761 | ||
102d8325 IM |
2762 | static void |
2763 | svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
2764 | { | |
2765 | /* | |
2766 | * Patch in the VMMCALL instruction: | |
2767 | */ | |
2768 | hypercall[0] = 0x0f; | |
2769 | hypercall[1] = 0x01; | |
2770 | hypercall[2] = 0xd9; | |
102d8325 IM |
2771 | } |
2772 | ||
002c7f7c YS |
2773 | static void svm_check_processor_compat(void *rtn) |
2774 | { | |
2775 | *(int *)rtn = 0; | |
2776 | } | |
2777 | ||
774ead3a AK |
2778 | static bool svm_cpu_has_accelerated_tpr(void) |
2779 | { | |
2780 | return false; | |
2781 | } | |
2782 | ||
67253af5 SY |
2783 | static int get_npt_level(void) |
2784 | { | |
2785 | #ifdef CONFIG_X86_64 | |
2786 | return PT64_ROOT_LEVEL; | |
2787 | #else | |
2788 | return PT32E_ROOT_LEVEL; | |
2789 | #endif | |
2790 | } | |
2791 | ||
4b12f0de | 2792 | static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio) |
64d4d521 SY |
2793 | { |
2794 | return 0; | |
2795 | } | |
2796 | ||
229456fc MT |
2797 | static const struct trace_print_flags svm_exit_reasons_str[] = { |
2798 | { SVM_EXIT_READ_CR0, "read_cr0" }, | |
2799 | { SVM_EXIT_READ_CR3, "read_cr3" }, | |
2800 | { SVM_EXIT_READ_CR4, "read_cr4" }, | |
2801 | { SVM_EXIT_READ_CR8, "read_cr8" }, | |
2802 | { SVM_EXIT_WRITE_CR0, "write_cr0" }, | |
2803 | { SVM_EXIT_WRITE_CR3, "write_cr3" }, | |
2804 | { SVM_EXIT_WRITE_CR4, "write_cr4" }, | |
2805 | { SVM_EXIT_WRITE_CR8, "write_cr8" }, | |
2806 | { SVM_EXIT_READ_DR0, "read_dr0" }, | |
2807 | { SVM_EXIT_READ_DR1, "read_dr1" }, | |
2808 | { SVM_EXIT_READ_DR2, "read_dr2" }, | |
2809 | { SVM_EXIT_READ_DR3, "read_dr3" }, | |
2810 | { SVM_EXIT_WRITE_DR0, "write_dr0" }, | |
2811 | { SVM_EXIT_WRITE_DR1, "write_dr1" }, | |
2812 | { SVM_EXIT_WRITE_DR2, "write_dr2" }, | |
2813 | { SVM_EXIT_WRITE_DR3, "write_dr3" }, | |
2814 | { SVM_EXIT_WRITE_DR5, "write_dr5" }, | |
2815 | { SVM_EXIT_WRITE_DR7, "write_dr7" }, | |
2816 | { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" }, | |
2817 | { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" }, | |
2818 | { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" }, | |
2819 | { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" }, | |
2820 | { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" }, | |
2821 | { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" }, | |
2822 | { SVM_EXIT_INTR, "interrupt" }, | |
2823 | { SVM_EXIT_NMI, "nmi" }, | |
2824 | { SVM_EXIT_SMI, "smi" }, | |
2825 | { SVM_EXIT_INIT, "init" }, | |
2826 | { SVM_EXIT_VINTR, "vintr" }, | |
2827 | { SVM_EXIT_CPUID, "cpuid" }, | |
2828 | { SVM_EXIT_INVD, "invd" }, | |
2829 | { SVM_EXIT_HLT, "hlt" }, | |
2830 | { SVM_EXIT_INVLPG, "invlpg" }, | |
2831 | { SVM_EXIT_INVLPGA, "invlpga" }, | |
2832 | { SVM_EXIT_IOIO, "io" }, | |
2833 | { SVM_EXIT_MSR, "msr" }, | |
2834 | { SVM_EXIT_TASK_SWITCH, "task_switch" }, | |
2835 | { SVM_EXIT_SHUTDOWN, "shutdown" }, | |
2836 | { SVM_EXIT_VMRUN, "vmrun" }, | |
2837 | { SVM_EXIT_VMMCALL, "hypercall" }, | |
2838 | { SVM_EXIT_VMLOAD, "vmload" }, | |
2839 | { SVM_EXIT_VMSAVE, "vmsave" }, | |
2840 | { SVM_EXIT_STGI, "stgi" }, | |
2841 | { SVM_EXIT_CLGI, "clgi" }, | |
2842 | { SVM_EXIT_SKINIT, "skinit" }, | |
2843 | { SVM_EXIT_WBINVD, "wbinvd" }, | |
2844 | { SVM_EXIT_MONITOR, "monitor" }, | |
2845 | { SVM_EXIT_MWAIT, "mwait" }, | |
2846 | { SVM_EXIT_NPF, "npf" }, | |
2847 | { -1, NULL } | |
2848 | }; | |
2849 | ||
344f414f JR |
2850 | static bool svm_gb_page_enable(void) |
2851 | { | |
2852 | return true; | |
2853 | } | |
2854 | ||
cbdd1bea | 2855 | static struct kvm_x86_ops svm_x86_ops = { |
6aa8b732 AK |
2856 | .cpu_has_kvm_support = has_svm, |
2857 | .disabled_by_bios = is_disabled, | |
2858 | .hardware_setup = svm_hardware_setup, | |
2859 | .hardware_unsetup = svm_hardware_unsetup, | |
002c7f7c | 2860 | .check_processor_compatibility = svm_check_processor_compat, |
6aa8b732 AK |
2861 | .hardware_enable = svm_hardware_enable, |
2862 | .hardware_disable = svm_hardware_disable, | |
774ead3a | 2863 | .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr, |
6aa8b732 AK |
2864 | |
2865 | .vcpu_create = svm_create_vcpu, | |
2866 | .vcpu_free = svm_free_vcpu, | |
04d2cc77 | 2867 | .vcpu_reset = svm_vcpu_reset, |
6aa8b732 | 2868 | |
04d2cc77 | 2869 | .prepare_guest_switch = svm_prepare_guest_switch, |
6aa8b732 AK |
2870 | .vcpu_load = svm_vcpu_load, |
2871 | .vcpu_put = svm_vcpu_put, | |
2872 | ||
2873 | .set_guest_debug = svm_guest_debug, | |
2874 | .get_msr = svm_get_msr, | |
2875 | .set_msr = svm_set_msr, | |
2876 | .get_segment_base = svm_get_segment_base, | |
2877 | .get_segment = svm_get_segment, | |
2878 | .set_segment = svm_set_segment, | |
2e4d2653 | 2879 | .get_cpl = svm_get_cpl, |
1747fb71 | 2880 | .get_cs_db_l_bits = kvm_get_cs_db_l_bits, |
25c4c276 | 2881 | .decache_cr4_guest_bits = svm_decache_cr4_guest_bits, |
6aa8b732 | 2882 | .set_cr0 = svm_set_cr0, |
6aa8b732 AK |
2883 | .set_cr3 = svm_set_cr3, |
2884 | .set_cr4 = svm_set_cr4, | |
2885 | .set_efer = svm_set_efer, | |
2886 | .get_idt = svm_get_idt, | |
2887 | .set_idt = svm_set_idt, | |
2888 | .get_gdt = svm_get_gdt, | |
2889 | .set_gdt = svm_set_gdt, | |
2890 | .get_dr = svm_get_dr, | |
2891 | .set_dr = svm_set_dr, | |
6de4f3ad | 2892 | .cache_reg = svm_cache_reg, |
6aa8b732 AK |
2893 | .get_rflags = svm_get_rflags, |
2894 | .set_rflags = svm_set_rflags, | |
2895 | ||
6aa8b732 | 2896 | .tlb_flush = svm_flush_tlb, |
6aa8b732 | 2897 | |
6aa8b732 | 2898 | .run = svm_vcpu_run, |
04d2cc77 | 2899 | .handle_exit = handle_exit, |
6aa8b732 | 2900 | .skip_emulated_instruction = skip_emulated_instruction, |
2809f5d2 GC |
2901 | .set_interrupt_shadow = svm_set_interrupt_shadow, |
2902 | .get_interrupt_shadow = svm_get_interrupt_shadow, | |
102d8325 | 2903 | .patch_hypercall = svm_patch_hypercall, |
2a8067f1 | 2904 | .set_irq = svm_set_irq, |
95ba8273 | 2905 | .set_nmi = svm_inject_nmi, |
298101da | 2906 | .queue_exception = svm_queue_exception, |
78646121 | 2907 | .interrupt_allowed = svm_interrupt_allowed, |
95ba8273 GN |
2908 | .nmi_allowed = svm_nmi_allowed, |
2909 | .enable_nmi_window = enable_nmi_window, | |
2910 | .enable_irq_window = enable_irq_window, | |
2911 | .update_cr8_intercept = update_cr8_intercept, | |
cbc94022 IE |
2912 | |
2913 | .set_tss_addr = svm_set_tss_addr, | |
67253af5 | 2914 | .get_tdp_level = get_npt_level, |
4b12f0de | 2915 | .get_mt_mask = svm_get_mt_mask, |
229456fc MT |
2916 | |
2917 | .exit_reasons_str = svm_exit_reasons_str, | |
344f414f | 2918 | .gb_page_enable = svm_gb_page_enable, |
6aa8b732 AK |
2919 | }; |
2920 | ||
2921 | static int __init svm_init(void) | |
2922 | { | |
cb498ea2 | 2923 | return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm), |
c16f862d | 2924 | THIS_MODULE); |
6aa8b732 AK |
2925 | } |
2926 | ||
2927 | static void __exit svm_exit(void) | |
2928 | { | |
cb498ea2 | 2929 | kvm_exit(); |
6aa8b732 AK |
2930 | } |
2931 | ||
2932 | module_init(svm_init) | |
2933 | module_exit(svm_exit) |