Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * AMD SVM support | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
7 | * | |
8 | * Authors: | |
9 | * Yaniv Kamay <yaniv@qumranet.com> | |
10 | * Avi Kivity <avi@qumranet.com> | |
11 | * | |
12 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
13 | * the COPYING file in the top-level directory. | |
14 | * | |
15 | */ | |
edf88417 AK |
16 | #include <linux/kvm_host.h> |
17 | ||
e495606d | 18 | #include "kvm_svm.h" |
85f455f7 | 19 | #include "irq.h" |
1d737c8a | 20 | #include "mmu.h" |
e495606d | 21 | |
6aa8b732 | 22 | #include <linux/module.h> |
9d8f549d | 23 | #include <linux/kernel.h> |
6aa8b732 AK |
24 | #include <linux/vmalloc.h> |
25 | #include <linux/highmem.h> | |
e8edc6e0 | 26 | #include <linux/sched.h> |
6aa8b732 | 27 | |
e495606d | 28 | #include <asm/desc.h> |
6aa8b732 | 29 | |
4ecac3fd AK |
30 | #define __ex(x) __kvm_handle_fault_on_reboot(x) |
31 | ||
6aa8b732 AK |
32 | MODULE_AUTHOR("Qumranet"); |
33 | MODULE_LICENSE("GPL"); | |
34 | ||
35 | #define IOPM_ALLOC_ORDER 2 | |
36 | #define MSRPM_ALLOC_ORDER 1 | |
37 | ||
38 | #define DB_VECTOR 1 | |
39 | #define UD_VECTOR 6 | |
40 | #define GP_VECTOR 13 | |
41 | ||
42 | #define DR7_GD_MASK (1 << 13) | |
43 | #define DR6_BD_MASK (1 << 13) | |
6aa8b732 AK |
44 | |
45 | #define SEG_TYPE_LDT 2 | |
46 | #define SEG_TYPE_BUSY_TSS16 3 | |
47 | ||
80b7706e JR |
48 | #define SVM_FEATURE_NPT (1 << 0) |
49 | #define SVM_FEATURE_LBRV (1 << 1) | |
50 | #define SVM_DEATURE_SVML (1 << 2) | |
51 | ||
24e09cbf JR |
52 | #define DEBUGCTL_RESERVED_BITS (~(0x3fULL)) |
53 | ||
709ddebf JR |
54 | /* enable NPT for AMD64 and X86 with PAE */ |
55 | #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE) | |
56 | static bool npt_enabled = true; | |
57 | #else | |
e3da3acd | 58 | static bool npt_enabled = false; |
709ddebf | 59 | #endif |
6c7dac72 JR |
60 | static int npt = 1; |
61 | ||
62 | module_param(npt, int, S_IRUGO); | |
e3da3acd | 63 | |
04d2cc77 | 64 | static void kvm_reput_irq(struct vcpu_svm *svm); |
44874f84 | 65 | static void svm_flush_tlb(struct kvm_vcpu *vcpu); |
04d2cc77 | 66 | |
a2fa3e9f GH |
67 | static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu) |
68 | { | |
fb3f0f51 | 69 | return container_of(vcpu, struct vcpu_svm, vcpu); |
a2fa3e9f GH |
70 | } |
71 | ||
4866d5e3 | 72 | static unsigned long iopm_base; |
6aa8b732 AK |
73 | |
74 | struct kvm_ldttss_desc { | |
75 | u16 limit0; | |
76 | u16 base0; | |
77 | unsigned base1 : 8, type : 5, dpl : 2, p : 1; | |
78 | unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8; | |
79 | u32 base3; | |
80 | u32 zero1; | |
81 | } __attribute__((packed)); | |
82 | ||
83 | struct svm_cpu_data { | |
84 | int cpu; | |
85 | ||
5008fdf5 AK |
86 | u64 asid_generation; |
87 | u32 max_asid; | |
88 | u32 next_asid; | |
6aa8b732 AK |
89 | struct kvm_ldttss_desc *tss_desc; |
90 | ||
91 | struct page *save_area; | |
92 | }; | |
93 | ||
94 | static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data); | |
80b7706e | 95 | static uint32_t svm_features; |
6aa8b732 AK |
96 | |
97 | struct svm_init_data { | |
98 | int cpu; | |
99 | int r; | |
100 | }; | |
101 | ||
102 | static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000}; | |
103 | ||
9d8f549d | 104 | #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges) |
6aa8b732 AK |
105 | #define MSRS_RANGE_SIZE 2048 |
106 | #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2) | |
107 | ||
108 | #define MAX_INST_SIZE 15 | |
109 | ||
80b7706e JR |
110 | static inline u32 svm_has(u32 feat) |
111 | { | |
112 | return svm_features & feat; | |
113 | } | |
114 | ||
6aa8b732 AK |
115 | static inline u8 pop_irq(struct kvm_vcpu *vcpu) |
116 | { | |
ad312c7c ZX |
117 | int word_index = __ffs(vcpu->arch.irq_summary); |
118 | int bit_index = __ffs(vcpu->arch.irq_pending[word_index]); | |
6aa8b732 AK |
119 | int irq = word_index * BITS_PER_LONG + bit_index; |
120 | ||
ad312c7c ZX |
121 | clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]); |
122 | if (!vcpu->arch.irq_pending[word_index]) | |
123 | clear_bit(word_index, &vcpu->arch.irq_summary); | |
6aa8b732 AK |
124 | return irq; |
125 | } | |
126 | ||
127 | static inline void push_irq(struct kvm_vcpu *vcpu, u8 irq) | |
128 | { | |
ad312c7c ZX |
129 | set_bit(irq, vcpu->arch.irq_pending); |
130 | set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary); | |
6aa8b732 AK |
131 | } |
132 | ||
133 | static inline void clgi(void) | |
134 | { | |
4ecac3fd | 135 | asm volatile (__ex(SVM_CLGI)); |
6aa8b732 AK |
136 | } |
137 | ||
138 | static inline void stgi(void) | |
139 | { | |
4ecac3fd | 140 | asm volatile (__ex(SVM_STGI)); |
6aa8b732 AK |
141 | } |
142 | ||
143 | static inline void invlpga(unsigned long addr, u32 asid) | |
144 | { | |
4ecac3fd | 145 | asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid)); |
6aa8b732 AK |
146 | } |
147 | ||
148 | static inline unsigned long kvm_read_cr2(void) | |
149 | { | |
150 | unsigned long cr2; | |
151 | ||
152 | asm volatile ("mov %%cr2, %0" : "=r" (cr2)); | |
153 | return cr2; | |
154 | } | |
155 | ||
156 | static inline void kvm_write_cr2(unsigned long val) | |
157 | { | |
158 | asm volatile ("mov %0, %%cr2" :: "r" (val)); | |
159 | } | |
160 | ||
161 | static inline unsigned long read_dr6(void) | |
162 | { | |
163 | unsigned long dr6; | |
164 | ||
165 | asm volatile ("mov %%dr6, %0" : "=r" (dr6)); | |
166 | return dr6; | |
167 | } | |
168 | ||
169 | static inline void write_dr6(unsigned long val) | |
170 | { | |
171 | asm volatile ("mov %0, %%dr6" :: "r" (val)); | |
172 | } | |
173 | ||
174 | static inline unsigned long read_dr7(void) | |
175 | { | |
176 | unsigned long dr7; | |
177 | ||
178 | asm volatile ("mov %%dr7, %0" : "=r" (dr7)); | |
179 | return dr7; | |
180 | } | |
181 | ||
182 | static inline void write_dr7(unsigned long val) | |
183 | { | |
184 | asm volatile ("mov %0, %%dr7" :: "r" (val)); | |
185 | } | |
186 | ||
6aa8b732 AK |
187 | static inline void force_new_asid(struct kvm_vcpu *vcpu) |
188 | { | |
a2fa3e9f | 189 | to_svm(vcpu)->asid_generation--; |
6aa8b732 AK |
190 | } |
191 | ||
192 | static inline void flush_guest_tlb(struct kvm_vcpu *vcpu) | |
193 | { | |
194 | force_new_asid(vcpu); | |
195 | } | |
196 | ||
197 | static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer) | |
198 | { | |
709ddebf | 199 | if (!npt_enabled && !(efer & EFER_LMA)) |
2b5203ee | 200 | efer &= ~EFER_LME; |
6aa8b732 | 201 | |
a2fa3e9f | 202 | to_svm(vcpu)->vmcb->save.efer = efer | MSR_EFER_SVME_MASK; |
ad312c7c | 203 | vcpu->arch.shadow_efer = efer; |
6aa8b732 AK |
204 | } |
205 | ||
298101da AK |
206 | static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr, |
207 | bool has_error_code, u32 error_code) | |
208 | { | |
209 | struct vcpu_svm *svm = to_svm(vcpu); | |
210 | ||
211 | svm->vmcb->control.event_inj = nr | |
212 | | SVM_EVTINJ_VALID | |
213 | | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0) | |
214 | | SVM_EVTINJ_TYPE_EXEPT; | |
215 | svm->vmcb->control.event_inj_err = error_code; | |
216 | } | |
217 | ||
218 | static bool svm_exception_injected(struct kvm_vcpu *vcpu) | |
219 | { | |
220 | struct vcpu_svm *svm = to_svm(vcpu); | |
221 | ||
222 | return !(svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID); | |
223 | } | |
224 | ||
6aa8b732 AK |
225 | static int is_external_interrupt(u32 info) |
226 | { | |
227 | info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID; | |
228 | return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR); | |
229 | } | |
230 | ||
231 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) | |
232 | { | |
a2fa3e9f GH |
233 | struct vcpu_svm *svm = to_svm(vcpu); |
234 | ||
235 | if (!svm->next_rip) { | |
b8688d51 | 236 | printk(KERN_DEBUG "%s: NOP\n", __func__); |
6aa8b732 AK |
237 | return; |
238 | } | |
d77c26fc | 239 | if (svm->next_rip - svm->vmcb->save.rip > MAX_INST_SIZE) |
6aa8b732 | 240 | printk(KERN_ERR "%s: ip 0x%llx next 0x%llx\n", |
b8688d51 | 241 | __func__, |
a2fa3e9f GH |
242 | svm->vmcb->save.rip, |
243 | svm->next_rip); | |
6aa8b732 | 244 | |
ad312c7c | 245 | vcpu->arch.rip = svm->vmcb->save.rip = svm->next_rip; |
a2fa3e9f | 246 | svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK; |
c1150d8c | 247 | |
ad312c7c | 248 | vcpu->arch.interrupt_window_open = 1; |
6aa8b732 AK |
249 | } |
250 | ||
251 | static int has_svm(void) | |
252 | { | |
253 | uint32_t eax, ebx, ecx, edx; | |
254 | ||
1e885461 | 255 | if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) { |
6aa8b732 AK |
256 | printk(KERN_INFO "has_svm: not amd\n"); |
257 | return 0; | |
258 | } | |
259 | ||
260 | cpuid(0x80000000, &eax, &ebx, &ecx, &edx); | |
261 | if (eax < SVM_CPUID_FUNC) { | |
262 | printk(KERN_INFO "has_svm: can't execute cpuid_8000000a\n"); | |
263 | return 0; | |
264 | } | |
265 | ||
266 | cpuid(0x80000001, &eax, &ebx, &ecx, &edx); | |
267 | if (!(ecx & (1 << SVM_CPUID_FEATURE_SHIFT))) { | |
268 | printk(KERN_DEBUG "has_svm: svm not available\n"); | |
269 | return 0; | |
270 | } | |
271 | return 1; | |
272 | } | |
273 | ||
274 | static void svm_hardware_disable(void *garbage) | |
275 | { | |
0da1db75 | 276 | uint64_t efer; |
6aa8b732 | 277 | |
0da1db75 JR |
278 | wrmsrl(MSR_VM_HSAVE_PA, 0); |
279 | rdmsrl(MSR_EFER, efer); | |
280 | wrmsrl(MSR_EFER, efer & ~MSR_EFER_SVME_MASK); | |
6aa8b732 AK |
281 | } |
282 | ||
283 | static void svm_hardware_enable(void *garbage) | |
284 | { | |
285 | ||
286 | struct svm_cpu_data *svm_data; | |
287 | uint64_t efer; | |
6aa8b732 | 288 | struct desc_ptr gdt_descr; |
6aa8b732 AK |
289 | struct desc_struct *gdt; |
290 | int me = raw_smp_processor_id(); | |
291 | ||
292 | if (!has_svm()) { | |
293 | printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me); | |
294 | return; | |
295 | } | |
296 | svm_data = per_cpu(svm_data, me); | |
297 | ||
298 | if (!svm_data) { | |
299 | printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n", | |
300 | me); | |
301 | return; | |
302 | } | |
303 | ||
304 | svm_data->asid_generation = 1; | |
305 | svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1; | |
306 | svm_data->next_asid = svm_data->max_asid + 1; | |
307 | ||
d77c26fc | 308 | asm volatile ("sgdt %0" : "=m"(gdt_descr)); |
6aa8b732 AK |
309 | gdt = (struct desc_struct *)gdt_descr.address; |
310 | svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS); | |
311 | ||
312 | rdmsrl(MSR_EFER, efer); | |
313 | wrmsrl(MSR_EFER, efer | MSR_EFER_SVME_MASK); | |
314 | ||
315 | wrmsrl(MSR_VM_HSAVE_PA, | |
316 | page_to_pfn(svm_data->save_area) << PAGE_SHIFT); | |
317 | } | |
318 | ||
0da1db75 JR |
319 | static void svm_cpu_uninit(int cpu) |
320 | { | |
321 | struct svm_cpu_data *svm_data | |
322 | = per_cpu(svm_data, raw_smp_processor_id()); | |
323 | ||
324 | if (!svm_data) | |
325 | return; | |
326 | ||
327 | per_cpu(svm_data, raw_smp_processor_id()) = NULL; | |
328 | __free_page(svm_data->save_area); | |
329 | kfree(svm_data); | |
330 | } | |
331 | ||
6aa8b732 AK |
332 | static int svm_cpu_init(int cpu) |
333 | { | |
334 | struct svm_cpu_data *svm_data; | |
335 | int r; | |
336 | ||
337 | svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL); | |
338 | if (!svm_data) | |
339 | return -ENOMEM; | |
340 | svm_data->cpu = cpu; | |
341 | svm_data->save_area = alloc_page(GFP_KERNEL); | |
342 | r = -ENOMEM; | |
343 | if (!svm_data->save_area) | |
344 | goto err_1; | |
345 | ||
346 | per_cpu(svm_data, cpu) = svm_data; | |
347 | ||
348 | return 0; | |
349 | ||
350 | err_1: | |
351 | kfree(svm_data); | |
352 | return r; | |
353 | ||
354 | } | |
355 | ||
bfc733a7 RR |
356 | static void set_msr_interception(u32 *msrpm, unsigned msr, |
357 | int read, int write) | |
6aa8b732 AK |
358 | { |
359 | int i; | |
360 | ||
361 | for (i = 0; i < NUM_MSR_MAPS; i++) { | |
362 | if (msr >= msrpm_ranges[i] && | |
363 | msr < msrpm_ranges[i] + MSRS_IN_RANGE) { | |
364 | u32 msr_offset = (i * MSRS_IN_RANGE + msr - | |
365 | msrpm_ranges[i]) * 2; | |
366 | ||
367 | u32 *base = msrpm + (msr_offset / 32); | |
368 | u32 msr_shift = msr_offset % 32; | |
369 | u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1); | |
370 | *base = (*base & ~(0x3 << msr_shift)) | | |
371 | (mask << msr_shift); | |
bfc733a7 | 372 | return; |
6aa8b732 AK |
373 | } |
374 | } | |
bfc733a7 | 375 | BUG(); |
6aa8b732 AK |
376 | } |
377 | ||
f65c229c JR |
378 | static void svm_vcpu_init_msrpm(u32 *msrpm) |
379 | { | |
380 | memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER)); | |
381 | ||
382 | #ifdef CONFIG_X86_64 | |
383 | set_msr_interception(msrpm, MSR_GS_BASE, 1, 1); | |
384 | set_msr_interception(msrpm, MSR_FS_BASE, 1, 1); | |
385 | set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1); | |
386 | set_msr_interception(msrpm, MSR_LSTAR, 1, 1); | |
387 | set_msr_interception(msrpm, MSR_CSTAR, 1, 1); | |
388 | set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1); | |
389 | #endif | |
390 | set_msr_interception(msrpm, MSR_K6_STAR, 1, 1); | |
391 | set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1); | |
392 | set_msr_interception(msrpm, MSR_IA32_SYSENTER_ESP, 1, 1); | |
393 | set_msr_interception(msrpm, MSR_IA32_SYSENTER_EIP, 1, 1); | |
394 | } | |
395 | ||
24e09cbf JR |
396 | static void svm_enable_lbrv(struct vcpu_svm *svm) |
397 | { | |
398 | u32 *msrpm = svm->msrpm; | |
399 | ||
400 | svm->vmcb->control.lbr_ctl = 1; | |
401 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1); | |
402 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1); | |
403 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1); | |
404 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1); | |
405 | } | |
406 | ||
407 | static void svm_disable_lbrv(struct vcpu_svm *svm) | |
408 | { | |
409 | u32 *msrpm = svm->msrpm; | |
410 | ||
411 | svm->vmcb->control.lbr_ctl = 0; | |
412 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0); | |
413 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0); | |
414 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0); | |
415 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0); | |
416 | } | |
417 | ||
6aa8b732 AK |
418 | static __init int svm_hardware_setup(void) |
419 | { | |
420 | int cpu; | |
421 | struct page *iopm_pages; | |
f65c229c | 422 | void *iopm_va; |
6aa8b732 AK |
423 | int r; |
424 | ||
6aa8b732 AK |
425 | iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER); |
426 | ||
427 | if (!iopm_pages) | |
428 | return -ENOMEM; | |
c8681339 AL |
429 | |
430 | iopm_va = page_address(iopm_pages); | |
431 | memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER)); | |
432 | clear_bit(0x80, iopm_va); /* allow direct access to PC debug port */ | |
6aa8b732 AK |
433 | iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT; |
434 | ||
50a37eb4 JR |
435 | if (boot_cpu_has(X86_FEATURE_NX)) |
436 | kvm_enable_efer_bits(EFER_NX); | |
437 | ||
6aa8b732 AK |
438 | for_each_online_cpu(cpu) { |
439 | r = svm_cpu_init(cpu); | |
440 | if (r) | |
f65c229c | 441 | goto err; |
6aa8b732 | 442 | } |
33bd6a0b JR |
443 | |
444 | svm_features = cpuid_edx(SVM_CPUID_FUNC); | |
445 | ||
e3da3acd JR |
446 | if (!svm_has(SVM_FEATURE_NPT)) |
447 | npt_enabled = false; | |
448 | ||
6c7dac72 JR |
449 | if (npt_enabled && !npt) { |
450 | printk(KERN_INFO "kvm: Nested Paging disabled\n"); | |
451 | npt_enabled = false; | |
452 | } | |
453 | ||
18552672 | 454 | if (npt_enabled) { |
e3da3acd | 455 | printk(KERN_INFO "kvm: Nested Paging enabled\n"); |
18552672 | 456 | kvm_enable_tdp(); |
5f4cb662 JR |
457 | } else |
458 | kvm_disable_tdp(); | |
e3da3acd | 459 | |
6aa8b732 AK |
460 | return 0; |
461 | ||
f65c229c | 462 | err: |
6aa8b732 AK |
463 | __free_pages(iopm_pages, IOPM_ALLOC_ORDER); |
464 | iopm_base = 0; | |
465 | return r; | |
466 | } | |
467 | ||
468 | static __exit void svm_hardware_unsetup(void) | |
469 | { | |
0da1db75 JR |
470 | int cpu; |
471 | ||
472 | for_each_online_cpu(cpu) | |
473 | svm_cpu_uninit(cpu); | |
474 | ||
6aa8b732 | 475 | __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER); |
f65c229c | 476 | iopm_base = 0; |
6aa8b732 AK |
477 | } |
478 | ||
479 | static void init_seg(struct vmcb_seg *seg) | |
480 | { | |
481 | seg->selector = 0; | |
482 | seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK | | |
483 | SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */ | |
484 | seg->limit = 0xffff; | |
485 | seg->base = 0; | |
486 | } | |
487 | ||
488 | static void init_sys_seg(struct vmcb_seg *seg, uint32_t type) | |
489 | { | |
490 | seg->selector = 0; | |
491 | seg->attrib = SVM_SELECTOR_P_MASK | type; | |
492 | seg->limit = 0xffff; | |
493 | seg->base = 0; | |
494 | } | |
495 | ||
e6101a96 | 496 | static void init_vmcb(struct vcpu_svm *svm) |
6aa8b732 | 497 | { |
e6101a96 JR |
498 | struct vmcb_control_area *control = &svm->vmcb->control; |
499 | struct vmcb_save_area *save = &svm->vmcb->save; | |
6aa8b732 AK |
500 | |
501 | control->intercept_cr_read = INTERCEPT_CR0_MASK | | |
502 | INTERCEPT_CR3_MASK | | |
649d6864 | 503 | INTERCEPT_CR4_MASK; |
6aa8b732 AK |
504 | |
505 | control->intercept_cr_write = INTERCEPT_CR0_MASK | | |
506 | INTERCEPT_CR3_MASK | | |
80a8119c AK |
507 | INTERCEPT_CR4_MASK | |
508 | INTERCEPT_CR8_MASK; | |
6aa8b732 AK |
509 | |
510 | control->intercept_dr_read = INTERCEPT_DR0_MASK | | |
511 | INTERCEPT_DR1_MASK | | |
512 | INTERCEPT_DR2_MASK | | |
513 | INTERCEPT_DR3_MASK; | |
514 | ||
515 | control->intercept_dr_write = INTERCEPT_DR0_MASK | | |
516 | INTERCEPT_DR1_MASK | | |
517 | INTERCEPT_DR2_MASK | | |
518 | INTERCEPT_DR3_MASK | | |
519 | INTERCEPT_DR5_MASK | | |
520 | INTERCEPT_DR7_MASK; | |
521 | ||
7aa81cc0 | 522 | control->intercept_exceptions = (1 << PF_VECTOR) | |
53371b50 JR |
523 | (1 << UD_VECTOR) | |
524 | (1 << MC_VECTOR); | |
6aa8b732 AK |
525 | |
526 | ||
527 | control->intercept = (1ULL << INTERCEPT_INTR) | | |
528 | (1ULL << INTERCEPT_NMI) | | |
0152527b | 529 | (1ULL << INTERCEPT_SMI) | |
6aa8b732 | 530 | (1ULL << INTERCEPT_CPUID) | |
cf5a94d1 | 531 | (1ULL << INTERCEPT_INVD) | |
6aa8b732 | 532 | (1ULL << INTERCEPT_HLT) | |
6aa8b732 AK |
533 | (1ULL << INTERCEPT_INVLPGA) | |
534 | (1ULL << INTERCEPT_IOIO_PROT) | | |
535 | (1ULL << INTERCEPT_MSR_PROT) | | |
536 | (1ULL << INTERCEPT_TASK_SWITCH) | | |
46fe4ddd | 537 | (1ULL << INTERCEPT_SHUTDOWN) | |
6aa8b732 AK |
538 | (1ULL << INTERCEPT_VMRUN) | |
539 | (1ULL << INTERCEPT_VMMCALL) | | |
540 | (1ULL << INTERCEPT_VMLOAD) | | |
541 | (1ULL << INTERCEPT_VMSAVE) | | |
542 | (1ULL << INTERCEPT_STGI) | | |
543 | (1ULL << INTERCEPT_CLGI) | | |
916ce236 | 544 | (1ULL << INTERCEPT_SKINIT) | |
cf5a94d1 | 545 | (1ULL << INTERCEPT_WBINVD) | |
916ce236 JR |
546 | (1ULL << INTERCEPT_MONITOR) | |
547 | (1ULL << INTERCEPT_MWAIT); | |
6aa8b732 AK |
548 | |
549 | control->iopm_base_pa = iopm_base; | |
f65c229c | 550 | control->msrpm_base_pa = __pa(svm->msrpm); |
0cc5064d | 551 | control->tsc_offset = 0; |
6aa8b732 AK |
552 | control->int_ctl = V_INTR_MASKING_MASK; |
553 | ||
554 | init_seg(&save->es); | |
555 | init_seg(&save->ss); | |
556 | init_seg(&save->ds); | |
557 | init_seg(&save->fs); | |
558 | init_seg(&save->gs); | |
559 | ||
560 | save->cs.selector = 0xf000; | |
561 | /* Executable/Readable Code Segment */ | |
562 | save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK | | |
563 | SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK; | |
564 | save->cs.limit = 0xffff; | |
d92899a0 AK |
565 | /* |
566 | * cs.base should really be 0xffff0000, but vmx can't handle that, so | |
567 | * be consistent with it. | |
568 | * | |
569 | * Replace when we have real mode working for vmx. | |
570 | */ | |
571 | save->cs.base = 0xf0000; | |
6aa8b732 AK |
572 | |
573 | save->gdtr.limit = 0xffff; | |
574 | save->idtr.limit = 0xffff; | |
575 | ||
576 | init_sys_seg(&save->ldtr, SEG_TYPE_LDT); | |
577 | init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16); | |
578 | ||
579 | save->efer = MSR_EFER_SVME_MASK; | |
d77c26fc | 580 | save->dr6 = 0xffff0ff0; |
6aa8b732 AK |
581 | save->dr7 = 0x400; |
582 | save->rflags = 2; | |
583 | save->rip = 0x0000fff0; | |
584 | ||
585 | /* | |
586 | * cr0 val on cpu init should be 0x60000010, we enable cpu | |
587 | * cache by default. the orderly way is to enable cache in bios. | |
588 | */ | |
707d92fa | 589 | save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP; |
66aee91a | 590 | save->cr4 = X86_CR4_PAE; |
6aa8b732 | 591 | /* rdx = ?? */ |
709ddebf JR |
592 | |
593 | if (npt_enabled) { | |
594 | /* Setup VMCB for Nested Paging */ | |
595 | control->nested_ctl = 1; | |
3564990a | 596 | control->intercept &= ~(1ULL << INTERCEPT_TASK_SWITCH); |
709ddebf JR |
597 | control->intercept_exceptions &= ~(1 << PF_VECTOR); |
598 | control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK| | |
599 | INTERCEPT_CR3_MASK); | |
600 | control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK| | |
601 | INTERCEPT_CR3_MASK); | |
602 | save->g_pat = 0x0007040600070406ULL; | |
603 | /* enable caching because the QEMU Bios doesn't enable it */ | |
604 | save->cr0 = X86_CR0_ET; | |
605 | save->cr3 = 0; | |
606 | save->cr4 = 0; | |
607 | } | |
a79d2f18 | 608 | force_new_asid(&svm->vcpu); |
6aa8b732 AK |
609 | } |
610 | ||
e00c8cf2 | 611 | static int svm_vcpu_reset(struct kvm_vcpu *vcpu) |
04d2cc77 AK |
612 | { |
613 | struct vcpu_svm *svm = to_svm(vcpu); | |
614 | ||
e6101a96 | 615 | init_vmcb(svm); |
70433389 AK |
616 | |
617 | if (vcpu->vcpu_id != 0) { | |
618 | svm->vmcb->save.rip = 0; | |
ad312c7c ZX |
619 | svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12; |
620 | svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8; | |
70433389 | 621 | } |
e00c8cf2 AK |
622 | |
623 | return 0; | |
04d2cc77 AK |
624 | } |
625 | ||
fb3f0f51 | 626 | static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 627 | { |
a2fa3e9f | 628 | struct vcpu_svm *svm; |
6aa8b732 | 629 | struct page *page; |
f65c229c | 630 | struct page *msrpm_pages; |
fb3f0f51 | 631 | int err; |
6aa8b732 | 632 | |
c16f862d | 633 | svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); |
fb3f0f51 RR |
634 | if (!svm) { |
635 | err = -ENOMEM; | |
636 | goto out; | |
637 | } | |
638 | ||
639 | err = kvm_vcpu_init(&svm->vcpu, kvm, id); | |
640 | if (err) | |
641 | goto free_svm; | |
642 | ||
6aa8b732 | 643 | page = alloc_page(GFP_KERNEL); |
fb3f0f51 RR |
644 | if (!page) { |
645 | err = -ENOMEM; | |
646 | goto uninit; | |
647 | } | |
6aa8b732 | 648 | |
f65c229c JR |
649 | err = -ENOMEM; |
650 | msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); | |
651 | if (!msrpm_pages) | |
652 | goto uninit; | |
653 | svm->msrpm = page_address(msrpm_pages); | |
654 | svm_vcpu_init_msrpm(svm->msrpm); | |
655 | ||
a2fa3e9f GH |
656 | svm->vmcb = page_address(page); |
657 | clear_page(svm->vmcb); | |
658 | svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT; | |
659 | svm->asid_generation = 0; | |
660 | memset(svm->db_regs, 0, sizeof(svm->db_regs)); | |
e6101a96 | 661 | init_vmcb(svm); |
a2fa3e9f | 662 | |
fb3f0f51 RR |
663 | fx_init(&svm->vcpu); |
664 | svm->vcpu.fpu_active = 1; | |
ad312c7c | 665 | svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE; |
fb3f0f51 | 666 | if (svm->vcpu.vcpu_id == 0) |
ad312c7c | 667 | svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP; |
6aa8b732 | 668 | |
fb3f0f51 | 669 | return &svm->vcpu; |
36241b8c | 670 | |
fb3f0f51 RR |
671 | uninit: |
672 | kvm_vcpu_uninit(&svm->vcpu); | |
673 | free_svm: | |
a4770347 | 674 | kmem_cache_free(kvm_vcpu_cache, svm); |
fb3f0f51 RR |
675 | out: |
676 | return ERR_PTR(err); | |
6aa8b732 AK |
677 | } |
678 | ||
679 | static void svm_free_vcpu(struct kvm_vcpu *vcpu) | |
680 | { | |
a2fa3e9f GH |
681 | struct vcpu_svm *svm = to_svm(vcpu); |
682 | ||
fb3f0f51 | 683 | __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT)); |
f65c229c | 684 | __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER); |
fb3f0f51 | 685 | kvm_vcpu_uninit(vcpu); |
a4770347 | 686 | kmem_cache_free(kvm_vcpu_cache, svm); |
6aa8b732 AK |
687 | } |
688 | ||
15ad7146 | 689 | static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 690 | { |
a2fa3e9f | 691 | struct vcpu_svm *svm = to_svm(vcpu); |
15ad7146 | 692 | int i; |
0cc5064d | 693 | |
0cc5064d AK |
694 | if (unlikely(cpu != vcpu->cpu)) { |
695 | u64 tsc_this, delta; | |
696 | ||
697 | /* | |
698 | * Make sure that the guest sees a monotonically | |
699 | * increasing TSC. | |
700 | */ | |
701 | rdtscll(tsc_this); | |
ad312c7c | 702 | delta = vcpu->arch.host_tsc - tsc_this; |
a2fa3e9f | 703 | svm->vmcb->control.tsc_offset += delta; |
0cc5064d | 704 | vcpu->cpu = cpu; |
2f599714 | 705 | kvm_migrate_timers(vcpu); |
0cc5064d | 706 | } |
94dfbdb3 AL |
707 | |
708 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) | |
a2fa3e9f | 709 | rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
6aa8b732 AK |
710 | } |
711 | ||
712 | static void svm_vcpu_put(struct kvm_vcpu *vcpu) | |
713 | { | |
a2fa3e9f | 714 | struct vcpu_svm *svm = to_svm(vcpu); |
94dfbdb3 AL |
715 | int i; |
716 | ||
e1beb1d3 | 717 | ++vcpu->stat.host_state_reload; |
94dfbdb3 | 718 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) |
a2fa3e9f | 719 | wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
94dfbdb3 | 720 | |
ad312c7c | 721 | rdtscll(vcpu->arch.host_tsc); |
6aa8b732 AK |
722 | } |
723 | ||
724 | static void svm_cache_regs(struct kvm_vcpu *vcpu) | |
725 | { | |
a2fa3e9f GH |
726 | struct vcpu_svm *svm = to_svm(vcpu); |
727 | ||
ad312c7c ZX |
728 | vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax; |
729 | vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp; | |
730 | vcpu->arch.rip = svm->vmcb->save.rip; | |
6aa8b732 AK |
731 | } |
732 | ||
733 | static void svm_decache_regs(struct kvm_vcpu *vcpu) | |
734 | { | |
a2fa3e9f | 735 | struct vcpu_svm *svm = to_svm(vcpu); |
ad312c7c ZX |
736 | svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX]; |
737 | svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP]; | |
738 | svm->vmcb->save.rip = vcpu->arch.rip; | |
6aa8b732 AK |
739 | } |
740 | ||
741 | static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu) | |
742 | { | |
a2fa3e9f | 743 | return to_svm(vcpu)->vmcb->save.rflags; |
6aa8b732 AK |
744 | } |
745 | ||
746 | static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
747 | { | |
a2fa3e9f | 748 | to_svm(vcpu)->vmcb->save.rflags = rflags; |
6aa8b732 AK |
749 | } |
750 | ||
751 | static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg) | |
752 | { | |
a2fa3e9f | 753 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; |
6aa8b732 AK |
754 | |
755 | switch (seg) { | |
756 | case VCPU_SREG_CS: return &save->cs; | |
757 | case VCPU_SREG_DS: return &save->ds; | |
758 | case VCPU_SREG_ES: return &save->es; | |
759 | case VCPU_SREG_FS: return &save->fs; | |
760 | case VCPU_SREG_GS: return &save->gs; | |
761 | case VCPU_SREG_SS: return &save->ss; | |
762 | case VCPU_SREG_TR: return &save->tr; | |
763 | case VCPU_SREG_LDTR: return &save->ldtr; | |
764 | } | |
765 | BUG(); | |
8b6d44c7 | 766 | return NULL; |
6aa8b732 AK |
767 | } |
768 | ||
769 | static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg) | |
770 | { | |
771 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
772 | ||
773 | return s->base; | |
774 | } | |
775 | ||
776 | static void svm_get_segment(struct kvm_vcpu *vcpu, | |
777 | struct kvm_segment *var, int seg) | |
778 | { | |
779 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
780 | ||
781 | var->base = s->base; | |
782 | var->limit = s->limit; | |
783 | var->selector = s->selector; | |
784 | var->type = s->attrib & SVM_SELECTOR_TYPE_MASK; | |
785 | var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1; | |
786 | var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3; | |
787 | var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1; | |
788 | var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1; | |
789 | var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1; | |
790 | var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1; | |
791 | var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1; | |
792 | var->unusable = !var->present; | |
793 | } | |
794 | ||
2e4d2653 IE |
795 | static int svm_get_cpl(struct kvm_vcpu *vcpu) |
796 | { | |
797 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; | |
798 | ||
799 | return save->cpl; | |
800 | } | |
801 | ||
6aa8b732 AK |
802 | static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) |
803 | { | |
a2fa3e9f GH |
804 | struct vcpu_svm *svm = to_svm(vcpu); |
805 | ||
806 | dt->limit = svm->vmcb->save.idtr.limit; | |
807 | dt->base = svm->vmcb->save.idtr.base; | |
6aa8b732 AK |
808 | } |
809 | ||
810 | static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
811 | { | |
a2fa3e9f GH |
812 | struct vcpu_svm *svm = to_svm(vcpu); |
813 | ||
814 | svm->vmcb->save.idtr.limit = dt->limit; | |
815 | svm->vmcb->save.idtr.base = dt->base ; | |
6aa8b732 AK |
816 | } |
817 | ||
818 | static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
819 | { | |
a2fa3e9f GH |
820 | struct vcpu_svm *svm = to_svm(vcpu); |
821 | ||
822 | dt->limit = svm->vmcb->save.gdtr.limit; | |
823 | dt->base = svm->vmcb->save.gdtr.base; | |
6aa8b732 AK |
824 | } |
825 | ||
826 | static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
827 | { | |
a2fa3e9f GH |
828 | struct vcpu_svm *svm = to_svm(vcpu); |
829 | ||
830 | svm->vmcb->save.gdtr.limit = dt->limit; | |
831 | svm->vmcb->save.gdtr.base = dt->base ; | |
6aa8b732 AK |
832 | } |
833 | ||
25c4c276 | 834 | static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 AK |
835 | { |
836 | } | |
837 | ||
6aa8b732 AK |
838 | static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
839 | { | |
a2fa3e9f GH |
840 | struct vcpu_svm *svm = to_svm(vcpu); |
841 | ||
05b3e0c2 | 842 | #ifdef CONFIG_X86_64 |
ad312c7c | 843 | if (vcpu->arch.shadow_efer & EFER_LME) { |
707d92fa | 844 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { |
ad312c7c | 845 | vcpu->arch.shadow_efer |= EFER_LMA; |
2b5203ee | 846 | svm->vmcb->save.efer |= EFER_LMA | EFER_LME; |
6aa8b732 AK |
847 | } |
848 | ||
d77c26fc | 849 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) { |
ad312c7c | 850 | vcpu->arch.shadow_efer &= ~EFER_LMA; |
2b5203ee | 851 | svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME); |
6aa8b732 AK |
852 | } |
853 | } | |
854 | #endif | |
709ddebf JR |
855 | if (npt_enabled) |
856 | goto set; | |
857 | ||
ad312c7c | 858 | if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) { |
a2fa3e9f | 859 | svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR); |
7807fa6c AL |
860 | vcpu->fpu_active = 1; |
861 | } | |
862 | ||
ad312c7c | 863 | vcpu->arch.cr0 = cr0; |
707d92fa | 864 | cr0 |= X86_CR0_PG | X86_CR0_WP; |
6b390b63 JR |
865 | if (!vcpu->fpu_active) { |
866 | svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR); | |
334df50a | 867 | cr0 |= X86_CR0_TS; |
6b390b63 | 868 | } |
709ddebf JR |
869 | set: |
870 | /* | |
871 | * re-enable caching here because the QEMU bios | |
872 | * does not do it - this results in some delay at | |
873 | * reboot | |
874 | */ | |
875 | cr0 &= ~(X86_CR0_CD | X86_CR0_NW); | |
a2fa3e9f | 876 | svm->vmcb->save.cr0 = cr0; |
6aa8b732 AK |
877 | } |
878 | ||
879 | static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) | |
880 | { | |
6394b649 JR |
881 | unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE; |
882 | ||
ec077263 JR |
883 | vcpu->arch.cr4 = cr4; |
884 | if (!npt_enabled) | |
885 | cr4 |= X86_CR4_PAE; | |
6394b649 | 886 | cr4 |= host_cr4_mce; |
ec077263 | 887 | to_svm(vcpu)->vmcb->save.cr4 = cr4; |
6aa8b732 AK |
888 | } |
889 | ||
890 | static void svm_set_segment(struct kvm_vcpu *vcpu, | |
891 | struct kvm_segment *var, int seg) | |
892 | { | |
a2fa3e9f | 893 | struct vcpu_svm *svm = to_svm(vcpu); |
6aa8b732 AK |
894 | struct vmcb_seg *s = svm_seg(vcpu, seg); |
895 | ||
896 | s->base = var->base; | |
897 | s->limit = var->limit; | |
898 | s->selector = var->selector; | |
899 | if (var->unusable) | |
900 | s->attrib = 0; | |
901 | else { | |
902 | s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK); | |
903 | s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT; | |
904 | s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT; | |
905 | s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT; | |
906 | s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT; | |
907 | s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT; | |
908 | s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT; | |
909 | s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT; | |
910 | } | |
911 | if (seg == VCPU_SREG_CS) | |
a2fa3e9f GH |
912 | svm->vmcb->save.cpl |
913 | = (svm->vmcb->save.cs.attrib | |
6aa8b732 AK |
914 | >> SVM_SELECTOR_DPL_SHIFT) & 3; |
915 | ||
916 | } | |
917 | ||
6aa8b732 AK |
918 | static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg) |
919 | { | |
920 | return -EOPNOTSUPP; | |
921 | } | |
922 | ||
2a8067f1 ED |
923 | static int svm_get_irq(struct kvm_vcpu *vcpu) |
924 | { | |
925 | struct vcpu_svm *svm = to_svm(vcpu); | |
926 | u32 exit_int_info = svm->vmcb->control.exit_int_info; | |
927 | ||
928 | if (is_external_interrupt(exit_int_info)) | |
929 | return exit_int_info & SVM_EVTINJ_VEC_MASK; | |
930 | return -1; | |
931 | } | |
932 | ||
6aa8b732 AK |
933 | static void load_host_msrs(struct kvm_vcpu *vcpu) |
934 | { | |
94dfbdb3 | 935 | #ifdef CONFIG_X86_64 |
a2fa3e9f | 936 | wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base); |
94dfbdb3 | 937 | #endif |
6aa8b732 AK |
938 | } |
939 | ||
940 | static void save_host_msrs(struct kvm_vcpu *vcpu) | |
941 | { | |
94dfbdb3 | 942 | #ifdef CONFIG_X86_64 |
a2fa3e9f | 943 | rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base); |
94dfbdb3 | 944 | #endif |
6aa8b732 AK |
945 | } |
946 | ||
e756fc62 | 947 | static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data) |
6aa8b732 AK |
948 | { |
949 | if (svm_data->next_asid > svm_data->max_asid) { | |
950 | ++svm_data->asid_generation; | |
951 | svm_data->next_asid = 1; | |
a2fa3e9f | 952 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID; |
6aa8b732 AK |
953 | } |
954 | ||
e756fc62 | 955 | svm->vcpu.cpu = svm_data->cpu; |
a2fa3e9f GH |
956 | svm->asid_generation = svm_data->asid_generation; |
957 | svm->vmcb->control.asid = svm_data->next_asid++; | |
6aa8b732 AK |
958 | } |
959 | ||
6aa8b732 AK |
960 | static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr) |
961 | { | |
af9ca2d7 JR |
962 | unsigned long val = to_svm(vcpu)->db_regs[dr]; |
963 | KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler); | |
964 | return val; | |
6aa8b732 AK |
965 | } |
966 | ||
967 | static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value, | |
968 | int *exception) | |
969 | { | |
a2fa3e9f GH |
970 | struct vcpu_svm *svm = to_svm(vcpu); |
971 | ||
6aa8b732 AK |
972 | *exception = 0; |
973 | ||
a2fa3e9f GH |
974 | if (svm->vmcb->save.dr7 & DR7_GD_MASK) { |
975 | svm->vmcb->save.dr7 &= ~DR7_GD_MASK; | |
976 | svm->vmcb->save.dr6 |= DR6_BD_MASK; | |
6aa8b732 AK |
977 | *exception = DB_VECTOR; |
978 | return; | |
979 | } | |
980 | ||
981 | switch (dr) { | |
982 | case 0 ... 3: | |
a2fa3e9f | 983 | svm->db_regs[dr] = value; |
6aa8b732 AK |
984 | return; |
985 | case 4 ... 5: | |
ad312c7c | 986 | if (vcpu->arch.cr4 & X86_CR4_DE) { |
6aa8b732 AK |
987 | *exception = UD_VECTOR; |
988 | return; | |
989 | } | |
990 | case 7: { | |
991 | if (value & ~((1ULL << 32) - 1)) { | |
992 | *exception = GP_VECTOR; | |
993 | return; | |
994 | } | |
a2fa3e9f | 995 | svm->vmcb->save.dr7 = value; |
6aa8b732 AK |
996 | return; |
997 | } | |
998 | default: | |
999 | printk(KERN_DEBUG "%s: unexpected dr %u\n", | |
b8688d51 | 1000 | __func__, dr); |
6aa8b732 AK |
1001 | *exception = UD_VECTOR; |
1002 | return; | |
1003 | } | |
1004 | } | |
1005 | ||
e756fc62 | 1006 | static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1007 | { |
a2fa3e9f | 1008 | u32 exit_int_info = svm->vmcb->control.exit_int_info; |
e756fc62 | 1009 | struct kvm *kvm = svm->vcpu.kvm; |
6aa8b732 AK |
1010 | u64 fault_address; |
1011 | u32 error_code; | |
577bdc49 | 1012 | bool event_injection = false; |
6aa8b732 | 1013 | |
85f455f7 | 1014 | if (!irqchip_in_kernel(kvm) && |
577bdc49 AK |
1015 | is_external_interrupt(exit_int_info)) { |
1016 | event_injection = true; | |
e756fc62 | 1017 | push_irq(&svm->vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK); |
577bdc49 | 1018 | } |
6aa8b732 | 1019 | |
a2fa3e9f GH |
1020 | fault_address = svm->vmcb->control.exit_info_2; |
1021 | error_code = svm->vmcb->control.exit_info_1; | |
af9ca2d7 JR |
1022 | |
1023 | if (!npt_enabled) | |
1024 | KVMTRACE_3D(PAGE_FAULT, &svm->vcpu, error_code, | |
1025 | (u32)fault_address, (u32)(fault_address >> 32), | |
1026 | handler); | |
d2ebb410 JR |
1027 | else |
1028 | KVMTRACE_3D(TDP_FAULT, &svm->vcpu, error_code, | |
1029 | (u32)fault_address, (u32)(fault_address >> 32), | |
1030 | handler); | |
44874f84 JR |
1031 | /* |
1032 | * FIXME: Tis shouldn't be necessary here, but there is a flush | |
1033 | * missing in the MMU code. Until we find this bug, flush the | |
1034 | * complete TLB here on an NPF | |
1035 | */ | |
1036 | if (npt_enabled) | |
1037 | svm_flush_tlb(&svm->vcpu); | |
af9ca2d7 | 1038 | |
577bdc49 AK |
1039 | if (event_injection) |
1040 | kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address); | |
3067714c | 1041 | return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code); |
6aa8b732 AK |
1042 | } |
1043 | ||
7aa81cc0 AL |
1044 | static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
1045 | { | |
1046 | int er; | |
1047 | ||
571008da | 1048 | er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD); |
7aa81cc0 | 1049 | if (er != EMULATE_DONE) |
7ee5d940 | 1050 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
7aa81cc0 AL |
1051 | return 1; |
1052 | } | |
1053 | ||
e756fc62 | 1054 | static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
7807fa6c | 1055 | { |
a2fa3e9f | 1056 | svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR); |
ad312c7c | 1057 | if (!(svm->vcpu.arch.cr0 & X86_CR0_TS)) |
a2fa3e9f | 1058 | svm->vmcb->save.cr0 &= ~X86_CR0_TS; |
e756fc62 | 1059 | svm->vcpu.fpu_active = 1; |
a2fa3e9f GH |
1060 | |
1061 | return 1; | |
7807fa6c AL |
1062 | } |
1063 | ||
53371b50 JR |
1064 | static int mc_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
1065 | { | |
1066 | /* | |
1067 | * On an #MC intercept the MCE handler is not called automatically in | |
1068 | * the host. So do it by hand here. | |
1069 | */ | |
1070 | asm volatile ( | |
1071 | "int $0x12\n"); | |
1072 | /* not sure if we ever come back to this point */ | |
1073 | ||
1074 | return 1; | |
1075 | } | |
1076 | ||
e756fc62 | 1077 | static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
46fe4ddd JR |
1078 | { |
1079 | /* | |
1080 | * VMCB is undefined after a SHUTDOWN intercept | |
1081 | * so reinitialize it. | |
1082 | */ | |
a2fa3e9f | 1083 | clear_page(svm->vmcb); |
e6101a96 | 1084 | init_vmcb(svm); |
46fe4ddd JR |
1085 | |
1086 | kvm_run->exit_reason = KVM_EXIT_SHUTDOWN; | |
1087 | return 0; | |
1088 | } | |
1089 | ||
e756fc62 | 1090 | static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1091 | { |
d77c26fc | 1092 | u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */ |
039576c0 AK |
1093 | int size, down, in, string, rep; |
1094 | unsigned port; | |
6aa8b732 | 1095 | |
e756fc62 | 1096 | ++svm->vcpu.stat.io_exits; |
6aa8b732 | 1097 | |
a2fa3e9f | 1098 | svm->next_rip = svm->vmcb->control.exit_info_2; |
6aa8b732 | 1099 | |
e70669ab LV |
1100 | string = (io_info & SVM_IOIO_STR_MASK) != 0; |
1101 | ||
1102 | if (string) { | |
3427318f LV |
1103 | if (emulate_instruction(&svm->vcpu, |
1104 | kvm_run, 0, 0, 0) == EMULATE_DO_MMIO) | |
e70669ab LV |
1105 | return 0; |
1106 | return 1; | |
1107 | } | |
1108 | ||
039576c0 AK |
1109 | in = (io_info & SVM_IOIO_TYPE_MASK) != 0; |
1110 | port = io_info >> 16; | |
1111 | size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT; | |
039576c0 | 1112 | rep = (io_info & SVM_IOIO_REP_MASK) != 0; |
a2fa3e9f | 1113 | down = (svm->vmcb->save.rflags & X86_EFLAGS_DF) != 0; |
6aa8b732 | 1114 | |
3090dd73 | 1115 | return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port); |
6aa8b732 AK |
1116 | } |
1117 | ||
c47f098d JR |
1118 | static int nmi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
1119 | { | |
af9ca2d7 | 1120 | KVMTRACE_0D(NMI, &svm->vcpu, handler); |
c47f098d JR |
1121 | return 1; |
1122 | } | |
1123 | ||
a0698055 JR |
1124 | static int intr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
1125 | { | |
1126 | ++svm->vcpu.stat.irq_exits; | |
af9ca2d7 | 1127 | KVMTRACE_0D(INTR, &svm->vcpu, handler); |
a0698055 JR |
1128 | return 1; |
1129 | } | |
1130 | ||
e756fc62 | 1131 | static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 AK |
1132 | { |
1133 | return 1; | |
1134 | } | |
1135 | ||
e756fc62 | 1136 | static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1137 | { |
a2fa3e9f | 1138 | svm->next_rip = svm->vmcb->save.rip + 1; |
e756fc62 RR |
1139 | skip_emulated_instruction(&svm->vcpu); |
1140 | return kvm_emulate_halt(&svm->vcpu); | |
6aa8b732 AK |
1141 | } |
1142 | ||
e756fc62 | 1143 | static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
02e235bc | 1144 | { |
a2fa3e9f | 1145 | svm->next_rip = svm->vmcb->save.rip + 3; |
e756fc62 | 1146 | skip_emulated_instruction(&svm->vcpu); |
7aa81cc0 AL |
1147 | kvm_emulate_hypercall(&svm->vcpu); |
1148 | return 1; | |
02e235bc AK |
1149 | } |
1150 | ||
e756fc62 RR |
1151 | static int invalid_op_interception(struct vcpu_svm *svm, |
1152 | struct kvm_run *kvm_run) | |
6aa8b732 | 1153 | { |
7ee5d940 | 1154 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
6aa8b732 AK |
1155 | return 1; |
1156 | } | |
1157 | ||
e756fc62 RR |
1158 | static int task_switch_interception(struct vcpu_svm *svm, |
1159 | struct kvm_run *kvm_run) | |
6aa8b732 | 1160 | { |
37817f29 IE |
1161 | u16 tss_selector; |
1162 | ||
1163 | tss_selector = (u16)svm->vmcb->control.exit_info_1; | |
1164 | if (svm->vmcb->control.exit_info_2 & | |
1165 | (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET)) | |
1166 | return kvm_task_switch(&svm->vcpu, tss_selector, | |
1167 | TASK_SWITCH_IRET); | |
1168 | if (svm->vmcb->control.exit_info_2 & | |
1169 | (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP)) | |
1170 | return kvm_task_switch(&svm->vcpu, tss_selector, | |
1171 | TASK_SWITCH_JMP); | |
1172 | return kvm_task_switch(&svm->vcpu, tss_selector, TASK_SWITCH_CALL); | |
6aa8b732 AK |
1173 | } |
1174 | ||
e756fc62 | 1175 | static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1176 | { |
a2fa3e9f | 1177 | svm->next_rip = svm->vmcb->save.rip + 2; |
e756fc62 | 1178 | kvm_emulate_cpuid(&svm->vcpu); |
06465c5a | 1179 | return 1; |
6aa8b732 AK |
1180 | } |
1181 | ||
e756fc62 RR |
1182 | static int emulate_on_interception(struct vcpu_svm *svm, |
1183 | struct kvm_run *kvm_run) | |
6aa8b732 | 1184 | { |
3427318f | 1185 | if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE) |
b8688d51 | 1186 | pr_unimpl(&svm->vcpu, "%s: failed\n", __func__); |
6aa8b732 AK |
1187 | return 1; |
1188 | } | |
1189 | ||
1d075434 JR |
1190 | static int cr8_write_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
1191 | { | |
1192 | emulate_instruction(&svm->vcpu, NULL, 0, 0, 0); | |
1193 | if (irqchip_in_kernel(svm->vcpu.kvm)) | |
1194 | return 1; | |
1195 | kvm_run->exit_reason = KVM_EXIT_SET_TPR; | |
1196 | return 0; | |
1197 | } | |
1198 | ||
6aa8b732 AK |
1199 | static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data) |
1200 | { | |
a2fa3e9f GH |
1201 | struct vcpu_svm *svm = to_svm(vcpu); |
1202 | ||
6aa8b732 | 1203 | switch (ecx) { |
6aa8b732 AK |
1204 | case MSR_IA32_TIME_STAMP_COUNTER: { |
1205 | u64 tsc; | |
1206 | ||
1207 | rdtscll(tsc); | |
a2fa3e9f | 1208 | *data = svm->vmcb->control.tsc_offset + tsc; |
6aa8b732 AK |
1209 | break; |
1210 | } | |
0e859cac | 1211 | case MSR_K6_STAR: |
a2fa3e9f | 1212 | *data = svm->vmcb->save.star; |
6aa8b732 | 1213 | break; |
0e859cac | 1214 | #ifdef CONFIG_X86_64 |
6aa8b732 | 1215 | case MSR_LSTAR: |
a2fa3e9f | 1216 | *data = svm->vmcb->save.lstar; |
6aa8b732 AK |
1217 | break; |
1218 | case MSR_CSTAR: | |
a2fa3e9f | 1219 | *data = svm->vmcb->save.cstar; |
6aa8b732 AK |
1220 | break; |
1221 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 1222 | *data = svm->vmcb->save.kernel_gs_base; |
6aa8b732 AK |
1223 | break; |
1224 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 1225 | *data = svm->vmcb->save.sfmask; |
6aa8b732 AK |
1226 | break; |
1227 | #endif | |
1228 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 1229 | *data = svm->vmcb->save.sysenter_cs; |
6aa8b732 AK |
1230 | break; |
1231 | case MSR_IA32_SYSENTER_EIP: | |
a2fa3e9f | 1232 | *data = svm->vmcb->save.sysenter_eip; |
6aa8b732 AK |
1233 | break; |
1234 | case MSR_IA32_SYSENTER_ESP: | |
a2fa3e9f | 1235 | *data = svm->vmcb->save.sysenter_esp; |
6aa8b732 | 1236 | break; |
a2938c80 JR |
1237 | /* Nobody will change the following 5 values in the VMCB so |
1238 | we can safely return them on rdmsr. They will always be 0 | |
1239 | until LBRV is implemented. */ | |
1240 | case MSR_IA32_DEBUGCTLMSR: | |
1241 | *data = svm->vmcb->save.dbgctl; | |
1242 | break; | |
1243 | case MSR_IA32_LASTBRANCHFROMIP: | |
1244 | *data = svm->vmcb->save.br_from; | |
1245 | break; | |
1246 | case MSR_IA32_LASTBRANCHTOIP: | |
1247 | *data = svm->vmcb->save.br_to; | |
1248 | break; | |
1249 | case MSR_IA32_LASTINTFROMIP: | |
1250 | *data = svm->vmcb->save.last_excp_from; | |
1251 | break; | |
1252 | case MSR_IA32_LASTINTTOIP: | |
1253 | *data = svm->vmcb->save.last_excp_to; | |
1254 | break; | |
6aa8b732 | 1255 | default: |
3bab1f5d | 1256 | return kvm_get_msr_common(vcpu, ecx, data); |
6aa8b732 AK |
1257 | } |
1258 | return 0; | |
1259 | } | |
1260 | ||
e756fc62 | 1261 | static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1262 | { |
ad312c7c | 1263 | u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
6aa8b732 AK |
1264 | u64 data; |
1265 | ||
e756fc62 | 1266 | if (svm_get_msr(&svm->vcpu, ecx, &data)) |
c1a5d4f9 | 1267 | kvm_inject_gp(&svm->vcpu, 0); |
6aa8b732 | 1268 | else { |
af9ca2d7 JR |
1269 | KVMTRACE_3D(MSR_READ, &svm->vcpu, ecx, (u32)data, |
1270 | (u32)(data >> 32), handler); | |
1271 | ||
a2fa3e9f | 1272 | svm->vmcb->save.rax = data & 0xffffffff; |
ad312c7c | 1273 | svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32; |
a2fa3e9f | 1274 | svm->next_rip = svm->vmcb->save.rip + 2; |
e756fc62 | 1275 | skip_emulated_instruction(&svm->vcpu); |
6aa8b732 AK |
1276 | } |
1277 | return 1; | |
1278 | } | |
1279 | ||
1280 | static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data) | |
1281 | { | |
a2fa3e9f GH |
1282 | struct vcpu_svm *svm = to_svm(vcpu); |
1283 | ||
6aa8b732 | 1284 | switch (ecx) { |
6aa8b732 AK |
1285 | case MSR_IA32_TIME_STAMP_COUNTER: { |
1286 | u64 tsc; | |
1287 | ||
1288 | rdtscll(tsc); | |
a2fa3e9f | 1289 | svm->vmcb->control.tsc_offset = data - tsc; |
6aa8b732 AK |
1290 | break; |
1291 | } | |
0e859cac | 1292 | case MSR_K6_STAR: |
a2fa3e9f | 1293 | svm->vmcb->save.star = data; |
6aa8b732 | 1294 | break; |
49b14f24 | 1295 | #ifdef CONFIG_X86_64 |
6aa8b732 | 1296 | case MSR_LSTAR: |
a2fa3e9f | 1297 | svm->vmcb->save.lstar = data; |
6aa8b732 AK |
1298 | break; |
1299 | case MSR_CSTAR: | |
a2fa3e9f | 1300 | svm->vmcb->save.cstar = data; |
6aa8b732 AK |
1301 | break; |
1302 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 1303 | svm->vmcb->save.kernel_gs_base = data; |
6aa8b732 AK |
1304 | break; |
1305 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 1306 | svm->vmcb->save.sfmask = data; |
6aa8b732 AK |
1307 | break; |
1308 | #endif | |
1309 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 1310 | svm->vmcb->save.sysenter_cs = data; |
6aa8b732 AK |
1311 | break; |
1312 | case MSR_IA32_SYSENTER_EIP: | |
a2fa3e9f | 1313 | svm->vmcb->save.sysenter_eip = data; |
6aa8b732 AK |
1314 | break; |
1315 | case MSR_IA32_SYSENTER_ESP: | |
a2fa3e9f | 1316 | svm->vmcb->save.sysenter_esp = data; |
6aa8b732 | 1317 | break; |
a2938c80 | 1318 | case MSR_IA32_DEBUGCTLMSR: |
24e09cbf JR |
1319 | if (!svm_has(SVM_FEATURE_LBRV)) { |
1320 | pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n", | |
b8688d51 | 1321 | __func__, data); |
24e09cbf JR |
1322 | break; |
1323 | } | |
1324 | if (data & DEBUGCTL_RESERVED_BITS) | |
1325 | return 1; | |
1326 | ||
1327 | svm->vmcb->save.dbgctl = data; | |
1328 | if (data & (1ULL<<0)) | |
1329 | svm_enable_lbrv(svm); | |
1330 | else | |
1331 | svm_disable_lbrv(svm); | |
a2938c80 | 1332 | break; |
62b9abaa JR |
1333 | case MSR_K7_EVNTSEL0: |
1334 | case MSR_K7_EVNTSEL1: | |
1335 | case MSR_K7_EVNTSEL2: | |
1336 | case MSR_K7_EVNTSEL3: | |
14ae51b6 CL |
1337 | case MSR_K7_PERFCTR0: |
1338 | case MSR_K7_PERFCTR1: | |
1339 | case MSR_K7_PERFCTR2: | |
1340 | case MSR_K7_PERFCTR3: | |
62b9abaa | 1341 | /* |
14ae51b6 CL |
1342 | * Just discard all writes to the performance counters; this |
1343 | * should keep both older linux and windows 64-bit guests | |
1344 | * happy | |
62b9abaa | 1345 | */ |
14ae51b6 CL |
1346 | pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", ecx, data); |
1347 | ||
62b9abaa | 1348 | break; |
6aa8b732 | 1349 | default: |
3bab1f5d | 1350 | return kvm_set_msr_common(vcpu, ecx, data); |
6aa8b732 AK |
1351 | } |
1352 | return 0; | |
1353 | } | |
1354 | ||
e756fc62 | 1355 | static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1356 | { |
ad312c7c | 1357 | u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
a2fa3e9f | 1358 | u64 data = (svm->vmcb->save.rax & -1u) |
ad312c7c | 1359 | | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32); |
af9ca2d7 JR |
1360 | |
1361 | KVMTRACE_3D(MSR_WRITE, &svm->vcpu, ecx, (u32)data, (u32)(data >> 32), | |
1362 | handler); | |
1363 | ||
a2fa3e9f | 1364 | svm->next_rip = svm->vmcb->save.rip + 2; |
e756fc62 | 1365 | if (svm_set_msr(&svm->vcpu, ecx, data)) |
c1a5d4f9 | 1366 | kvm_inject_gp(&svm->vcpu, 0); |
6aa8b732 | 1367 | else |
e756fc62 | 1368 | skip_emulated_instruction(&svm->vcpu); |
6aa8b732 AK |
1369 | return 1; |
1370 | } | |
1371 | ||
e756fc62 | 1372 | static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1373 | { |
e756fc62 RR |
1374 | if (svm->vmcb->control.exit_info_1) |
1375 | return wrmsr_interception(svm, kvm_run); | |
6aa8b732 | 1376 | else |
e756fc62 | 1377 | return rdmsr_interception(svm, kvm_run); |
6aa8b732 AK |
1378 | } |
1379 | ||
e756fc62 | 1380 | static int interrupt_window_interception(struct vcpu_svm *svm, |
c1150d8c DL |
1381 | struct kvm_run *kvm_run) |
1382 | { | |
af9ca2d7 JR |
1383 | KVMTRACE_0D(PEND_INTR, &svm->vcpu, handler); |
1384 | ||
85f455f7 ED |
1385 | svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR); |
1386 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; | |
c1150d8c DL |
1387 | /* |
1388 | * If the user space waits to inject interrupts, exit as soon as | |
1389 | * possible | |
1390 | */ | |
1391 | if (kvm_run->request_interrupt_window && | |
ad312c7c | 1392 | !svm->vcpu.arch.irq_summary) { |
e756fc62 | 1393 | ++svm->vcpu.stat.irq_window_exits; |
c1150d8c DL |
1394 | kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; |
1395 | return 0; | |
1396 | } | |
1397 | ||
1398 | return 1; | |
1399 | } | |
1400 | ||
e756fc62 | 1401 | static int (*svm_exit_handlers[])(struct vcpu_svm *svm, |
6aa8b732 AK |
1402 | struct kvm_run *kvm_run) = { |
1403 | [SVM_EXIT_READ_CR0] = emulate_on_interception, | |
1404 | [SVM_EXIT_READ_CR3] = emulate_on_interception, | |
1405 | [SVM_EXIT_READ_CR4] = emulate_on_interception, | |
80a8119c | 1406 | [SVM_EXIT_READ_CR8] = emulate_on_interception, |
6aa8b732 AK |
1407 | /* for now: */ |
1408 | [SVM_EXIT_WRITE_CR0] = emulate_on_interception, | |
1409 | [SVM_EXIT_WRITE_CR3] = emulate_on_interception, | |
1410 | [SVM_EXIT_WRITE_CR4] = emulate_on_interception, | |
1d075434 | 1411 | [SVM_EXIT_WRITE_CR8] = cr8_write_interception, |
6aa8b732 AK |
1412 | [SVM_EXIT_READ_DR0] = emulate_on_interception, |
1413 | [SVM_EXIT_READ_DR1] = emulate_on_interception, | |
1414 | [SVM_EXIT_READ_DR2] = emulate_on_interception, | |
1415 | [SVM_EXIT_READ_DR3] = emulate_on_interception, | |
1416 | [SVM_EXIT_WRITE_DR0] = emulate_on_interception, | |
1417 | [SVM_EXIT_WRITE_DR1] = emulate_on_interception, | |
1418 | [SVM_EXIT_WRITE_DR2] = emulate_on_interception, | |
1419 | [SVM_EXIT_WRITE_DR3] = emulate_on_interception, | |
1420 | [SVM_EXIT_WRITE_DR5] = emulate_on_interception, | |
1421 | [SVM_EXIT_WRITE_DR7] = emulate_on_interception, | |
7aa81cc0 | 1422 | [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception, |
6aa8b732 | 1423 | [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception, |
7807fa6c | 1424 | [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception, |
53371b50 | 1425 | [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception, |
a0698055 | 1426 | [SVM_EXIT_INTR] = intr_interception, |
c47f098d | 1427 | [SVM_EXIT_NMI] = nmi_interception, |
6aa8b732 AK |
1428 | [SVM_EXIT_SMI] = nop_on_interception, |
1429 | [SVM_EXIT_INIT] = nop_on_interception, | |
c1150d8c | 1430 | [SVM_EXIT_VINTR] = interrupt_window_interception, |
6aa8b732 AK |
1431 | /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */ |
1432 | [SVM_EXIT_CPUID] = cpuid_interception, | |
cf5a94d1 | 1433 | [SVM_EXIT_INVD] = emulate_on_interception, |
6aa8b732 AK |
1434 | [SVM_EXIT_HLT] = halt_interception, |
1435 | [SVM_EXIT_INVLPG] = emulate_on_interception, | |
1436 | [SVM_EXIT_INVLPGA] = invalid_op_interception, | |
1437 | [SVM_EXIT_IOIO] = io_interception, | |
1438 | [SVM_EXIT_MSR] = msr_interception, | |
1439 | [SVM_EXIT_TASK_SWITCH] = task_switch_interception, | |
46fe4ddd | 1440 | [SVM_EXIT_SHUTDOWN] = shutdown_interception, |
6aa8b732 | 1441 | [SVM_EXIT_VMRUN] = invalid_op_interception, |
02e235bc | 1442 | [SVM_EXIT_VMMCALL] = vmmcall_interception, |
6aa8b732 AK |
1443 | [SVM_EXIT_VMLOAD] = invalid_op_interception, |
1444 | [SVM_EXIT_VMSAVE] = invalid_op_interception, | |
1445 | [SVM_EXIT_STGI] = invalid_op_interception, | |
1446 | [SVM_EXIT_CLGI] = invalid_op_interception, | |
1447 | [SVM_EXIT_SKINIT] = invalid_op_interception, | |
cf5a94d1 | 1448 | [SVM_EXIT_WBINVD] = emulate_on_interception, |
916ce236 JR |
1449 | [SVM_EXIT_MONITOR] = invalid_op_interception, |
1450 | [SVM_EXIT_MWAIT] = invalid_op_interception, | |
709ddebf | 1451 | [SVM_EXIT_NPF] = pf_interception, |
6aa8b732 AK |
1452 | }; |
1453 | ||
04d2cc77 | 1454 | static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu) |
6aa8b732 | 1455 | { |
04d2cc77 | 1456 | struct vcpu_svm *svm = to_svm(vcpu); |
a2fa3e9f | 1457 | u32 exit_code = svm->vmcb->control.exit_code; |
6aa8b732 | 1458 | |
af9ca2d7 JR |
1459 | KVMTRACE_3D(VMEXIT, vcpu, exit_code, (u32)svm->vmcb->save.rip, |
1460 | (u32)((u64)svm->vmcb->save.rip >> 32), entryexit); | |
1461 | ||
709ddebf JR |
1462 | if (npt_enabled) { |
1463 | int mmu_reload = 0; | |
1464 | if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) { | |
1465 | svm_set_cr0(vcpu, svm->vmcb->save.cr0); | |
1466 | mmu_reload = 1; | |
1467 | } | |
1468 | vcpu->arch.cr0 = svm->vmcb->save.cr0; | |
1469 | vcpu->arch.cr3 = svm->vmcb->save.cr3; | |
1470 | if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) { | |
1471 | if (!load_pdptrs(vcpu, vcpu->arch.cr3)) { | |
1472 | kvm_inject_gp(vcpu, 0); | |
1473 | return 1; | |
1474 | } | |
1475 | } | |
1476 | if (mmu_reload) { | |
1477 | kvm_mmu_reset_context(vcpu); | |
1478 | kvm_mmu_load(vcpu); | |
1479 | } | |
1480 | } | |
1481 | ||
04d2cc77 AK |
1482 | kvm_reput_irq(svm); |
1483 | ||
1484 | if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) { | |
1485 | kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY; | |
1486 | kvm_run->fail_entry.hardware_entry_failure_reason | |
1487 | = svm->vmcb->control.exit_code; | |
1488 | return 0; | |
1489 | } | |
1490 | ||
a2fa3e9f | 1491 | if (is_external_interrupt(svm->vmcb->control.exit_int_info) && |
709ddebf JR |
1492 | exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR && |
1493 | exit_code != SVM_EXIT_NPF) | |
6aa8b732 AK |
1494 | printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x " |
1495 | "exit_code 0x%x\n", | |
b8688d51 | 1496 | __func__, svm->vmcb->control.exit_int_info, |
6aa8b732 AK |
1497 | exit_code); |
1498 | ||
9d8f549d | 1499 | if (exit_code >= ARRAY_SIZE(svm_exit_handlers) |
56919c5c | 1500 | || !svm_exit_handlers[exit_code]) { |
6aa8b732 | 1501 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; |
364b625b | 1502 | kvm_run->hw.hardware_exit_reason = exit_code; |
6aa8b732 AK |
1503 | return 0; |
1504 | } | |
1505 | ||
e756fc62 | 1506 | return svm_exit_handlers[exit_code](svm, kvm_run); |
6aa8b732 AK |
1507 | } |
1508 | ||
1509 | static void reload_tss(struct kvm_vcpu *vcpu) | |
1510 | { | |
1511 | int cpu = raw_smp_processor_id(); | |
1512 | ||
1513 | struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu); | |
d77c26fc | 1514 | svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */ |
6aa8b732 AK |
1515 | load_TR_desc(); |
1516 | } | |
1517 | ||
e756fc62 | 1518 | static void pre_svm_run(struct vcpu_svm *svm) |
6aa8b732 AK |
1519 | { |
1520 | int cpu = raw_smp_processor_id(); | |
1521 | ||
1522 | struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu); | |
1523 | ||
a2fa3e9f | 1524 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING; |
e756fc62 | 1525 | if (svm->vcpu.cpu != cpu || |
a2fa3e9f | 1526 | svm->asid_generation != svm_data->asid_generation) |
e756fc62 | 1527 | new_asid(svm, svm_data); |
6aa8b732 AK |
1528 | } |
1529 | ||
1530 | ||
85f455f7 | 1531 | static inline void svm_inject_irq(struct vcpu_svm *svm, int irq) |
6aa8b732 AK |
1532 | { |
1533 | struct vmcb_control_area *control; | |
1534 | ||
af9ca2d7 JR |
1535 | KVMTRACE_1D(INJ_VIRQ, &svm->vcpu, (u32)irq, handler); |
1536 | ||
e756fc62 | 1537 | control = &svm->vmcb->control; |
85f455f7 | 1538 | control->int_vector = irq; |
6aa8b732 AK |
1539 | control->int_ctl &= ~V_INTR_PRIO_MASK; |
1540 | control->int_ctl |= V_IRQ_MASK | | |
1541 | ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT); | |
1542 | } | |
1543 | ||
2a8067f1 ED |
1544 | static void svm_set_irq(struct kvm_vcpu *vcpu, int irq) |
1545 | { | |
1546 | struct vcpu_svm *svm = to_svm(vcpu); | |
1547 | ||
1548 | svm_inject_irq(svm, irq); | |
1549 | } | |
1550 | ||
aaacfc9a JR |
1551 | static void update_cr8_intercept(struct kvm_vcpu *vcpu) |
1552 | { | |
1553 | struct vcpu_svm *svm = to_svm(vcpu); | |
1554 | struct vmcb *vmcb = svm->vmcb; | |
1555 | int max_irr, tpr; | |
1556 | ||
1557 | if (!irqchip_in_kernel(vcpu->kvm) || vcpu->arch.apic->vapic_addr) | |
1558 | return; | |
1559 | ||
1560 | vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK; | |
1561 | ||
1562 | max_irr = kvm_lapic_find_highest_irr(vcpu); | |
1563 | if (max_irr == -1) | |
1564 | return; | |
1565 | ||
1566 | tpr = kvm_lapic_get_cr8(vcpu) << 4; | |
1567 | ||
1568 | if (tpr >= (max_irr & 0xf0)) | |
1569 | vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK; | |
1570 | } | |
1571 | ||
04d2cc77 | 1572 | static void svm_intr_assist(struct kvm_vcpu *vcpu) |
6aa8b732 | 1573 | { |
04d2cc77 | 1574 | struct vcpu_svm *svm = to_svm(vcpu); |
85f455f7 ED |
1575 | struct vmcb *vmcb = svm->vmcb; |
1576 | int intr_vector = -1; | |
1577 | ||
1578 | if ((vmcb->control.exit_int_info & SVM_EVTINJ_VALID) && | |
1579 | ((vmcb->control.exit_int_info & SVM_EVTINJ_TYPE_MASK) == 0)) { | |
1580 | intr_vector = vmcb->control.exit_int_info & | |
1581 | SVM_EVTINJ_VEC_MASK; | |
1582 | vmcb->control.exit_int_info = 0; | |
1583 | svm_inject_irq(svm, intr_vector); | |
aaacfc9a | 1584 | goto out; |
85f455f7 ED |
1585 | } |
1586 | ||
1587 | if (vmcb->control.int_ctl & V_IRQ_MASK) | |
aaacfc9a | 1588 | goto out; |
85f455f7 | 1589 | |
1b9778da | 1590 | if (!kvm_cpu_has_interrupt(vcpu)) |
aaacfc9a | 1591 | goto out; |
85f455f7 ED |
1592 | |
1593 | if (!(vmcb->save.rflags & X86_EFLAGS_IF) || | |
1594 | (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) || | |
1595 | (vmcb->control.event_inj & SVM_EVTINJ_VALID)) { | |
1596 | /* unable to deliver irq, set pending irq */ | |
1597 | vmcb->control.intercept |= (1ULL << INTERCEPT_VINTR); | |
1598 | svm_inject_irq(svm, 0x0); | |
aaacfc9a | 1599 | goto out; |
85f455f7 ED |
1600 | } |
1601 | /* Okay, we can deliver the interrupt: grab it and update PIC state. */ | |
1b9778da | 1602 | intr_vector = kvm_cpu_get_interrupt(vcpu); |
85f455f7 | 1603 | svm_inject_irq(svm, intr_vector); |
1b9778da | 1604 | kvm_timer_intr_post(vcpu, intr_vector); |
aaacfc9a JR |
1605 | out: |
1606 | update_cr8_intercept(vcpu); | |
85f455f7 ED |
1607 | } |
1608 | ||
1609 | static void kvm_reput_irq(struct vcpu_svm *svm) | |
1610 | { | |
e756fc62 | 1611 | struct vmcb_control_area *control = &svm->vmcb->control; |
6aa8b732 | 1612 | |
7017fc3d ED |
1613 | if ((control->int_ctl & V_IRQ_MASK) |
1614 | && !irqchip_in_kernel(svm->vcpu.kvm)) { | |
6aa8b732 | 1615 | control->int_ctl &= ~V_IRQ_MASK; |
e756fc62 | 1616 | push_irq(&svm->vcpu, control->int_vector); |
6aa8b732 | 1617 | } |
c1150d8c | 1618 | |
ad312c7c | 1619 | svm->vcpu.arch.interrupt_window_open = |
c1150d8c DL |
1620 | !(control->int_state & SVM_INTERRUPT_SHADOW_MASK); |
1621 | } | |
1622 | ||
85f455f7 ED |
1623 | static void svm_do_inject_vector(struct vcpu_svm *svm) |
1624 | { | |
1625 | struct kvm_vcpu *vcpu = &svm->vcpu; | |
ad312c7c ZX |
1626 | int word_index = __ffs(vcpu->arch.irq_summary); |
1627 | int bit_index = __ffs(vcpu->arch.irq_pending[word_index]); | |
85f455f7 ED |
1628 | int irq = word_index * BITS_PER_LONG + bit_index; |
1629 | ||
ad312c7c ZX |
1630 | clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]); |
1631 | if (!vcpu->arch.irq_pending[word_index]) | |
1632 | clear_bit(word_index, &vcpu->arch.irq_summary); | |
85f455f7 ED |
1633 | svm_inject_irq(svm, irq); |
1634 | } | |
1635 | ||
04d2cc77 | 1636 | static void do_interrupt_requests(struct kvm_vcpu *vcpu, |
c1150d8c DL |
1637 | struct kvm_run *kvm_run) |
1638 | { | |
04d2cc77 | 1639 | struct vcpu_svm *svm = to_svm(vcpu); |
a2fa3e9f | 1640 | struct vmcb_control_area *control = &svm->vmcb->control; |
c1150d8c | 1641 | |
ad312c7c | 1642 | svm->vcpu.arch.interrupt_window_open = |
c1150d8c | 1643 | (!(control->int_state & SVM_INTERRUPT_SHADOW_MASK) && |
a2fa3e9f | 1644 | (svm->vmcb->save.rflags & X86_EFLAGS_IF)); |
c1150d8c | 1645 | |
ad312c7c | 1646 | if (svm->vcpu.arch.interrupt_window_open && svm->vcpu.arch.irq_summary) |
c1150d8c DL |
1647 | /* |
1648 | * If interrupts enabled, and not blocked by sti or mov ss. Good. | |
1649 | */ | |
85f455f7 | 1650 | svm_do_inject_vector(svm); |
c1150d8c DL |
1651 | |
1652 | /* | |
1653 | * Interrupts blocked. Wait for unblock. | |
1654 | */ | |
ad312c7c ZX |
1655 | if (!svm->vcpu.arch.interrupt_window_open && |
1656 | (svm->vcpu.arch.irq_summary || kvm_run->request_interrupt_window)) | |
c1150d8c | 1657 | control->intercept |= 1ULL << INTERCEPT_VINTR; |
d77c26fc | 1658 | else |
c1150d8c DL |
1659 | control->intercept &= ~(1ULL << INTERCEPT_VINTR); |
1660 | } | |
1661 | ||
cbc94022 IE |
1662 | static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr) |
1663 | { | |
1664 | return 0; | |
1665 | } | |
1666 | ||
6aa8b732 AK |
1667 | static void save_db_regs(unsigned long *db_regs) |
1668 | { | |
5aff458e AK |
1669 | asm volatile ("mov %%dr0, %0" : "=r"(db_regs[0])); |
1670 | asm volatile ("mov %%dr1, %0" : "=r"(db_regs[1])); | |
1671 | asm volatile ("mov %%dr2, %0" : "=r"(db_regs[2])); | |
1672 | asm volatile ("mov %%dr3, %0" : "=r"(db_regs[3])); | |
6aa8b732 AK |
1673 | } |
1674 | ||
1675 | static void load_db_regs(unsigned long *db_regs) | |
1676 | { | |
5aff458e AK |
1677 | asm volatile ("mov %0, %%dr0" : : "r"(db_regs[0])); |
1678 | asm volatile ("mov %0, %%dr1" : : "r"(db_regs[1])); | |
1679 | asm volatile ("mov %0, %%dr2" : : "r"(db_regs[2])); | |
1680 | asm volatile ("mov %0, %%dr3" : : "r"(db_regs[3])); | |
6aa8b732 AK |
1681 | } |
1682 | ||
d9e368d6 AK |
1683 | static void svm_flush_tlb(struct kvm_vcpu *vcpu) |
1684 | { | |
1685 | force_new_asid(vcpu); | |
1686 | } | |
1687 | ||
04d2cc77 AK |
1688 | static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu) |
1689 | { | |
1690 | } | |
1691 | ||
d7bf8221 JR |
1692 | static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu) |
1693 | { | |
1694 | struct vcpu_svm *svm = to_svm(vcpu); | |
1695 | ||
1696 | if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) { | |
1697 | int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK; | |
1698 | kvm_lapic_set_tpr(vcpu, cr8); | |
1699 | } | |
1700 | } | |
1701 | ||
649d6864 JR |
1702 | static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu) |
1703 | { | |
1704 | struct vcpu_svm *svm = to_svm(vcpu); | |
1705 | u64 cr8; | |
1706 | ||
1707 | if (!irqchip_in_kernel(vcpu->kvm)) | |
1708 | return; | |
1709 | ||
1710 | cr8 = kvm_get_cr8(vcpu); | |
1711 | svm->vmcb->control.int_ctl &= ~V_TPR_MASK; | |
1712 | svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK; | |
1713 | } | |
1714 | ||
04d2cc77 | 1715 | static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
6aa8b732 | 1716 | { |
a2fa3e9f | 1717 | struct vcpu_svm *svm = to_svm(vcpu); |
6aa8b732 AK |
1718 | u16 fs_selector; |
1719 | u16 gs_selector; | |
1720 | u16 ldt_selector; | |
d9e368d6 | 1721 | |
e756fc62 | 1722 | pre_svm_run(svm); |
6aa8b732 | 1723 | |
649d6864 JR |
1724 | sync_lapic_to_cr8(vcpu); |
1725 | ||
6aa8b732 | 1726 | save_host_msrs(vcpu); |
d6e88aec AK |
1727 | fs_selector = kvm_read_fs(); |
1728 | gs_selector = kvm_read_gs(); | |
1729 | ldt_selector = kvm_read_ldt(); | |
a2fa3e9f GH |
1730 | svm->host_cr2 = kvm_read_cr2(); |
1731 | svm->host_dr6 = read_dr6(); | |
1732 | svm->host_dr7 = read_dr7(); | |
ad312c7c | 1733 | svm->vmcb->save.cr2 = vcpu->arch.cr2; |
709ddebf JR |
1734 | /* required for live migration with NPT */ |
1735 | if (npt_enabled) | |
1736 | svm->vmcb->save.cr3 = vcpu->arch.cr3; | |
6aa8b732 | 1737 | |
a2fa3e9f | 1738 | if (svm->vmcb->save.dr7 & 0xff) { |
6aa8b732 | 1739 | write_dr7(0); |
a2fa3e9f GH |
1740 | save_db_regs(svm->host_db_regs); |
1741 | load_db_regs(svm->db_regs); | |
6aa8b732 | 1742 | } |
36241b8c | 1743 | |
04d2cc77 AK |
1744 | clgi(); |
1745 | ||
1746 | local_irq_enable(); | |
36241b8c | 1747 | |
6aa8b732 | 1748 | asm volatile ( |
05b3e0c2 | 1749 | #ifdef CONFIG_X86_64 |
54a08c04 | 1750 | "push %%rbp; \n\t" |
6aa8b732 | 1751 | #else |
fe7935d4 | 1752 | "push %%ebp; \n\t" |
6aa8b732 AK |
1753 | #endif |
1754 | ||
05b3e0c2 | 1755 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
1756 | "mov %c[rbx](%[svm]), %%rbx \n\t" |
1757 | "mov %c[rcx](%[svm]), %%rcx \n\t" | |
1758 | "mov %c[rdx](%[svm]), %%rdx \n\t" | |
1759 | "mov %c[rsi](%[svm]), %%rsi \n\t" | |
1760 | "mov %c[rdi](%[svm]), %%rdi \n\t" | |
1761 | "mov %c[rbp](%[svm]), %%rbp \n\t" | |
1762 | "mov %c[r8](%[svm]), %%r8 \n\t" | |
1763 | "mov %c[r9](%[svm]), %%r9 \n\t" | |
1764 | "mov %c[r10](%[svm]), %%r10 \n\t" | |
1765 | "mov %c[r11](%[svm]), %%r11 \n\t" | |
1766 | "mov %c[r12](%[svm]), %%r12 \n\t" | |
1767 | "mov %c[r13](%[svm]), %%r13 \n\t" | |
1768 | "mov %c[r14](%[svm]), %%r14 \n\t" | |
1769 | "mov %c[r15](%[svm]), %%r15 \n\t" | |
6aa8b732 | 1770 | #else |
fb3f0f51 RR |
1771 | "mov %c[rbx](%[svm]), %%ebx \n\t" |
1772 | "mov %c[rcx](%[svm]), %%ecx \n\t" | |
1773 | "mov %c[rdx](%[svm]), %%edx \n\t" | |
1774 | "mov %c[rsi](%[svm]), %%esi \n\t" | |
1775 | "mov %c[rdi](%[svm]), %%edi \n\t" | |
1776 | "mov %c[rbp](%[svm]), %%ebp \n\t" | |
6aa8b732 AK |
1777 | #endif |
1778 | ||
05b3e0c2 | 1779 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
1780 | /* Enter guest mode */ |
1781 | "push %%rax \n\t" | |
fb3f0f51 | 1782 | "mov %c[vmcb](%[svm]), %%rax \n\t" |
4ecac3fd AK |
1783 | __ex(SVM_VMLOAD) "\n\t" |
1784 | __ex(SVM_VMRUN) "\n\t" | |
1785 | __ex(SVM_VMSAVE) "\n\t" | |
6aa8b732 AK |
1786 | "pop %%rax \n\t" |
1787 | #else | |
1788 | /* Enter guest mode */ | |
1789 | "push %%eax \n\t" | |
fb3f0f51 | 1790 | "mov %c[vmcb](%[svm]), %%eax \n\t" |
4ecac3fd AK |
1791 | __ex(SVM_VMLOAD) "\n\t" |
1792 | __ex(SVM_VMRUN) "\n\t" | |
1793 | __ex(SVM_VMSAVE) "\n\t" | |
6aa8b732 AK |
1794 | "pop %%eax \n\t" |
1795 | #endif | |
1796 | ||
1797 | /* Save guest registers, load host registers */ | |
05b3e0c2 | 1798 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
1799 | "mov %%rbx, %c[rbx](%[svm]) \n\t" |
1800 | "mov %%rcx, %c[rcx](%[svm]) \n\t" | |
1801 | "mov %%rdx, %c[rdx](%[svm]) \n\t" | |
1802 | "mov %%rsi, %c[rsi](%[svm]) \n\t" | |
1803 | "mov %%rdi, %c[rdi](%[svm]) \n\t" | |
1804 | "mov %%rbp, %c[rbp](%[svm]) \n\t" | |
1805 | "mov %%r8, %c[r8](%[svm]) \n\t" | |
1806 | "mov %%r9, %c[r9](%[svm]) \n\t" | |
1807 | "mov %%r10, %c[r10](%[svm]) \n\t" | |
1808 | "mov %%r11, %c[r11](%[svm]) \n\t" | |
1809 | "mov %%r12, %c[r12](%[svm]) \n\t" | |
1810 | "mov %%r13, %c[r13](%[svm]) \n\t" | |
1811 | "mov %%r14, %c[r14](%[svm]) \n\t" | |
1812 | "mov %%r15, %c[r15](%[svm]) \n\t" | |
6aa8b732 | 1813 | |
54a08c04 | 1814 | "pop %%rbp; \n\t" |
6aa8b732 | 1815 | #else |
fb3f0f51 RR |
1816 | "mov %%ebx, %c[rbx](%[svm]) \n\t" |
1817 | "mov %%ecx, %c[rcx](%[svm]) \n\t" | |
1818 | "mov %%edx, %c[rdx](%[svm]) \n\t" | |
1819 | "mov %%esi, %c[rsi](%[svm]) \n\t" | |
1820 | "mov %%edi, %c[rdi](%[svm]) \n\t" | |
1821 | "mov %%ebp, %c[rbp](%[svm]) \n\t" | |
6aa8b732 | 1822 | |
fe7935d4 | 1823 | "pop %%ebp; \n\t" |
6aa8b732 AK |
1824 | #endif |
1825 | : | |
fb3f0f51 | 1826 | : [svm]"a"(svm), |
6aa8b732 | 1827 | [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)), |
ad312c7c ZX |
1828 | [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])), |
1829 | [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])), | |
1830 | [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])), | |
1831 | [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])), | |
1832 | [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])), | |
1833 | [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP])) | |
05b3e0c2 | 1834 | #ifdef CONFIG_X86_64 |
ad312c7c ZX |
1835 | , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])), |
1836 | [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])), | |
1837 | [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])), | |
1838 | [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])), | |
1839 | [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])), | |
1840 | [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])), | |
1841 | [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])), | |
1842 | [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15])) | |
6aa8b732 | 1843 | #endif |
54a08c04 LV |
1844 | : "cc", "memory" |
1845 | #ifdef CONFIG_X86_64 | |
1846 | , "rbx", "rcx", "rdx", "rsi", "rdi" | |
1847 | , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15" | |
fe7935d4 LV |
1848 | #else |
1849 | , "ebx", "ecx", "edx" , "esi", "edi" | |
54a08c04 LV |
1850 | #endif |
1851 | ); | |
6aa8b732 | 1852 | |
a2fa3e9f GH |
1853 | if ((svm->vmcb->save.dr7 & 0xff)) |
1854 | load_db_regs(svm->host_db_regs); | |
6aa8b732 | 1855 | |
ad312c7c | 1856 | vcpu->arch.cr2 = svm->vmcb->save.cr2; |
6aa8b732 | 1857 | |
a2fa3e9f GH |
1858 | write_dr6(svm->host_dr6); |
1859 | write_dr7(svm->host_dr7); | |
1860 | kvm_write_cr2(svm->host_cr2); | |
6aa8b732 | 1861 | |
d6e88aec AK |
1862 | kvm_load_fs(fs_selector); |
1863 | kvm_load_gs(gs_selector); | |
1864 | kvm_load_ldt(ldt_selector); | |
6aa8b732 AK |
1865 | load_host_msrs(vcpu); |
1866 | ||
1867 | reload_tss(vcpu); | |
1868 | ||
56ba47dd AK |
1869 | local_irq_disable(); |
1870 | ||
1871 | stgi(); | |
1872 | ||
d7bf8221 JR |
1873 | sync_cr8_to_lapic(vcpu); |
1874 | ||
a2fa3e9f | 1875 | svm->next_rip = 0; |
6aa8b732 AK |
1876 | } |
1877 | ||
6aa8b732 AK |
1878 | static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root) |
1879 | { | |
a2fa3e9f GH |
1880 | struct vcpu_svm *svm = to_svm(vcpu); |
1881 | ||
709ddebf JR |
1882 | if (npt_enabled) { |
1883 | svm->vmcb->control.nested_cr3 = root; | |
1884 | force_new_asid(vcpu); | |
1885 | return; | |
1886 | } | |
1887 | ||
a2fa3e9f | 1888 | svm->vmcb->save.cr3 = root; |
6aa8b732 | 1889 | force_new_asid(vcpu); |
7807fa6c AL |
1890 | |
1891 | if (vcpu->fpu_active) { | |
a2fa3e9f GH |
1892 | svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR); |
1893 | svm->vmcb->save.cr0 |= X86_CR0_TS; | |
7807fa6c AL |
1894 | vcpu->fpu_active = 0; |
1895 | } | |
6aa8b732 AK |
1896 | } |
1897 | ||
6aa8b732 AK |
1898 | static int is_disabled(void) |
1899 | { | |
6031a61c JR |
1900 | u64 vm_cr; |
1901 | ||
1902 | rdmsrl(MSR_VM_CR, vm_cr); | |
1903 | if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE)) | |
1904 | return 1; | |
1905 | ||
6aa8b732 AK |
1906 | return 0; |
1907 | } | |
1908 | ||
102d8325 IM |
1909 | static void |
1910 | svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
1911 | { | |
1912 | /* | |
1913 | * Patch in the VMMCALL instruction: | |
1914 | */ | |
1915 | hypercall[0] = 0x0f; | |
1916 | hypercall[1] = 0x01; | |
1917 | hypercall[2] = 0xd9; | |
102d8325 IM |
1918 | } |
1919 | ||
002c7f7c YS |
1920 | static void svm_check_processor_compat(void *rtn) |
1921 | { | |
1922 | *(int *)rtn = 0; | |
1923 | } | |
1924 | ||
774ead3a AK |
1925 | static bool svm_cpu_has_accelerated_tpr(void) |
1926 | { | |
1927 | return false; | |
1928 | } | |
1929 | ||
67253af5 SY |
1930 | static int get_npt_level(void) |
1931 | { | |
1932 | #ifdef CONFIG_X86_64 | |
1933 | return PT64_ROOT_LEVEL; | |
1934 | #else | |
1935 | return PT32E_ROOT_LEVEL; | |
1936 | #endif | |
1937 | } | |
1938 | ||
cbdd1bea | 1939 | static struct kvm_x86_ops svm_x86_ops = { |
6aa8b732 AK |
1940 | .cpu_has_kvm_support = has_svm, |
1941 | .disabled_by_bios = is_disabled, | |
1942 | .hardware_setup = svm_hardware_setup, | |
1943 | .hardware_unsetup = svm_hardware_unsetup, | |
002c7f7c | 1944 | .check_processor_compatibility = svm_check_processor_compat, |
6aa8b732 AK |
1945 | .hardware_enable = svm_hardware_enable, |
1946 | .hardware_disable = svm_hardware_disable, | |
774ead3a | 1947 | .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr, |
6aa8b732 AK |
1948 | |
1949 | .vcpu_create = svm_create_vcpu, | |
1950 | .vcpu_free = svm_free_vcpu, | |
04d2cc77 | 1951 | .vcpu_reset = svm_vcpu_reset, |
6aa8b732 | 1952 | |
04d2cc77 | 1953 | .prepare_guest_switch = svm_prepare_guest_switch, |
6aa8b732 AK |
1954 | .vcpu_load = svm_vcpu_load, |
1955 | .vcpu_put = svm_vcpu_put, | |
1956 | ||
1957 | .set_guest_debug = svm_guest_debug, | |
1958 | .get_msr = svm_get_msr, | |
1959 | .set_msr = svm_set_msr, | |
1960 | .get_segment_base = svm_get_segment_base, | |
1961 | .get_segment = svm_get_segment, | |
1962 | .set_segment = svm_set_segment, | |
2e4d2653 | 1963 | .get_cpl = svm_get_cpl, |
1747fb71 | 1964 | .get_cs_db_l_bits = kvm_get_cs_db_l_bits, |
25c4c276 | 1965 | .decache_cr4_guest_bits = svm_decache_cr4_guest_bits, |
6aa8b732 | 1966 | .set_cr0 = svm_set_cr0, |
6aa8b732 AK |
1967 | .set_cr3 = svm_set_cr3, |
1968 | .set_cr4 = svm_set_cr4, | |
1969 | .set_efer = svm_set_efer, | |
1970 | .get_idt = svm_get_idt, | |
1971 | .set_idt = svm_set_idt, | |
1972 | .get_gdt = svm_get_gdt, | |
1973 | .set_gdt = svm_set_gdt, | |
1974 | .get_dr = svm_get_dr, | |
1975 | .set_dr = svm_set_dr, | |
1976 | .cache_regs = svm_cache_regs, | |
1977 | .decache_regs = svm_decache_regs, | |
1978 | .get_rflags = svm_get_rflags, | |
1979 | .set_rflags = svm_set_rflags, | |
1980 | ||
6aa8b732 | 1981 | .tlb_flush = svm_flush_tlb, |
6aa8b732 | 1982 | |
6aa8b732 | 1983 | .run = svm_vcpu_run, |
04d2cc77 | 1984 | .handle_exit = handle_exit, |
6aa8b732 | 1985 | .skip_emulated_instruction = skip_emulated_instruction, |
102d8325 | 1986 | .patch_hypercall = svm_patch_hypercall, |
2a8067f1 ED |
1987 | .get_irq = svm_get_irq, |
1988 | .set_irq = svm_set_irq, | |
298101da AK |
1989 | .queue_exception = svm_queue_exception, |
1990 | .exception_injected = svm_exception_injected, | |
04d2cc77 AK |
1991 | .inject_pending_irq = svm_intr_assist, |
1992 | .inject_pending_vectors = do_interrupt_requests, | |
cbc94022 IE |
1993 | |
1994 | .set_tss_addr = svm_set_tss_addr, | |
67253af5 | 1995 | .get_tdp_level = get_npt_level, |
6aa8b732 AK |
1996 | }; |
1997 | ||
1998 | static int __init svm_init(void) | |
1999 | { | |
cb498ea2 | 2000 | return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm), |
c16f862d | 2001 | THIS_MODULE); |
6aa8b732 AK |
2002 | } |
2003 | ||
2004 | static void __exit svm_exit(void) | |
2005 | { | |
cb498ea2 | 2006 | kvm_exit(); |
6aa8b732 AK |
2007 | } |
2008 | ||
2009 | module_init(svm_init) | |
2010 | module_exit(svm_exit) |