Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * AMD SVM support | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
7 | * | |
8 | * Authors: | |
9 | * Yaniv Kamay <yaniv@qumranet.com> | |
10 | * Avi Kivity <avi@qumranet.com> | |
11 | * | |
12 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
13 | * the COPYING file in the top-level directory. | |
14 | * | |
15 | */ | |
edf88417 AK |
16 | #include <linux/kvm_host.h> |
17 | ||
e495606d | 18 | #include "kvm_svm.h" |
85f455f7 | 19 | #include "irq.h" |
1d737c8a | 20 | #include "mmu.h" |
e495606d | 21 | |
6aa8b732 | 22 | #include <linux/module.h> |
9d8f549d | 23 | #include <linux/kernel.h> |
6aa8b732 AK |
24 | #include <linux/vmalloc.h> |
25 | #include <linux/highmem.h> | |
e8edc6e0 | 26 | #include <linux/sched.h> |
6aa8b732 | 27 | |
e495606d | 28 | #include <asm/desc.h> |
6aa8b732 AK |
29 | |
30 | MODULE_AUTHOR("Qumranet"); | |
31 | MODULE_LICENSE("GPL"); | |
32 | ||
33 | #define IOPM_ALLOC_ORDER 2 | |
34 | #define MSRPM_ALLOC_ORDER 1 | |
35 | ||
36 | #define DB_VECTOR 1 | |
37 | #define UD_VECTOR 6 | |
38 | #define GP_VECTOR 13 | |
39 | ||
40 | #define DR7_GD_MASK (1 << 13) | |
41 | #define DR6_BD_MASK (1 << 13) | |
6aa8b732 AK |
42 | |
43 | #define SEG_TYPE_LDT 2 | |
44 | #define SEG_TYPE_BUSY_TSS16 3 | |
45 | ||
80b7706e JR |
46 | #define SVM_FEATURE_NPT (1 << 0) |
47 | #define SVM_FEATURE_LBRV (1 << 1) | |
48 | #define SVM_DEATURE_SVML (1 << 2) | |
49 | ||
24e09cbf JR |
50 | #define DEBUGCTL_RESERVED_BITS (~(0x3fULL)) |
51 | ||
709ddebf JR |
52 | /* enable NPT for AMD64 and X86 with PAE */ |
53 | #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE) | |
54 | static bool npt_enabled = true; | |
55 | #else | |
e3da3acd | 56 | static bool npt_enabled = false; |
709ddebf | 57 | #endif |
6c7dac72 JR |
58 | static int npt = 1; |
59 | ||
60 | module_param(npt, int, S_IRUGO); | |
e3da3acd | 61 | |
04d2cc77 AK |
62 | static void kvm_reput_irq(struct vcpu_svm *svm); |
63 | ||
a2fa3e9f GH |
64 | static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu) |
65 | { | |
fb3f0f51 | 66 | return container_of(vcpu, struct vcpu_svm, vcpu); |
a2fa3e9f GH |
67 | } |
68 | ||
4866d5e3 | 69 | static unsigned long iopm_base; |
6aa8b732 AK |
70 | |
71 | struct kvm_ldttss_desc { | |
72 | u16 limit0; | |
73 | u16 base0; | |
74 | unsigned base1 : 8, type : 5, dpl : 2, p : 1; | |
75 | unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8; | |
76 | u32 base3; | |
77 | u32 zero1; | |
78 | } __attribute__((packed)); | |
79 | ||
80 | struct svm_cpu_data { | |
81 | int cpu; | |
82 | ||
5008fdf5 AK |
83 | u64 asid_generation; |
84 | u32 max_asid; | |
85 | u32 next_asid; | |
6aa8b732 AK |
86 | struct kvm_ldttss_desc *tss_desc; |
87 | ||
88 | struct page *save_area; | |
89 | }; | |
90 | ||
91 | static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data); | |
80b7706e | 92 | static uint32_t svm_features; |
6aa8b732 AK |
93 | |
94 | struct svm_init_data { | |
95 | int cpu; | |
96 | int r; | |
97 | }; | |
98 | ||
99 | static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000}; | |
100 | ||
9d8f549d | 101 | #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges) |
6aa8b732 AK |
102 | #define MSRS_RANGE_SIZE 2048 |
103 | #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2) | |
104 | ||
105 | #define MAX_INST_SIZE 15 | |
106 | ||
80b7706e JR |
107 | static inline u32 svm_has(u32 feat) |
108 | { | |
109 | return svm_features & feat; | |
110 | } | |
111 | ||
6aa8b732 AK |
112 | static inline u8 pop_irq(struct kvm_vcpu *vcpu) |
113 | { | |
ad312c7c ZX |
114 | int word_index = __ffs(vcpu->arch.irq_summary); |
115 | int bit_index = __ffs(vcpu->arch.irq_pending[word_index]); | |
6aa8b732 AK |
116 | int irq = word_index * BITS_PER_LONG + bit_index; |
117 | ||
ad312c7c ZX |
118 | clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]); |
119 | if (!vcpu->arch.irq_pending[word_index]) | |
120 | clear_bit(word_index, &vcpu->arch.irq_summary); | |
6aa8b732 AK |
121 | return irq; |
122 | } | |
123 | ||
124 | static inline void push_irq(struct kvm_vcpu *vcpu, u8 irq) | |
125 | { | |
ad312c7c ZX |
126 | set_bit(irq, vcpu->arch.irq_pending); |
127 | set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary); | |
6aa8b732 AK |
128 | } |
129 | ||
130 | static inline void clgi(void) | |
131 | { | |
132 | asm volatile (SVM_CLGI); | |
133 | } | |
134 | ||
135 | static inline void stgi(void) | |
136 | { | |
137 | asm volatile (SVM_STGI); | |
138 | } | |
139 | ||
140 | static inline void invlpga(unsigned long addr, u32 asid) | |
141 | { | |
142 | asm volatile (SVM_INVLPGA :: "a"(addr), "c"(asid)); | |
143 | } | |
144 | ||
145 | static inline unsigned long kvm_read_cr2(void) | |
146 | { | |
147 | unsigned long cr2; | |
148 | ||
149 | asm volatile ("mov %%cr2, %0" : "=r" (cr2)); | |
150 | return cr2; | |
151 | } | |
152 | ||
153 | static inline void kvm_write_cr2(unsigned long val) | |
154 | { | |
155 | asm volatile ("mov %0, %%cr2" :: "r" (val)); | |
156 | } | |
157 | ||
158 | static inline unsigned long read_dr6(void) | |
159 | { | |
160 | unsigned long dr6; | |
161 | ||
162 | asm volatile ("mov %%dr6, %0" : "=r" (dr6)); | |
163 | return dr6; | |
164 | } | |
165 | ||
166 | static inline void write_dr6(unsigned long val) | |
167 | { | |
168 | asm volatile ("mov %0, %%dr6" :: "r" (val)); | |
169 | } | |
170 | ||
171 | static inline unsigned long read_dr7(void) | |
172 | { | |
173 | unsigned long dr7; | |
174 | ||
175 | asm volatile ("mov %%dr7, %0" : "=r" (dr7)); | |
176 | return dr7; | |
177 | } | |
178 | ||
179 | static inline void write_dr7(unsigned long val) | |
180 | { | |
181 | asm volatile ("mov %0, %%dr7" :: "r" (val)); | |
182 | } | |
183 | ||
6aa8b732 AK |
184 | static inline void force_new_asid(struct kvm_vcpu *vcpu) |
185 | { | |
a2fa3e9f | 186 | to_svm(vcpu)->asid_generation--; |
6aa8b732 AK |
187 | } |
188 | ||
189 | static inline void flush_guest_tlb(struct kvm_vcpu *vcpu) | |
190 | { | |
191 | force_new_asid(vcpu); | |
192 | } | |
193 | ||
194 | static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer) | |
195 | { | |
709ddebf | 196 | if (!npt_enabled && !(efer & EFER_LMA)) |
2b5203ee | 197 | efer &= ~EFER_LME; |
6aa8b732 | 198 | |
a2fa3e9f | 199 | to_svm(vcpu)->vmcb->save.efer = efer | MSR_EFER_SVME_MASK; |
ad312c7c | 200 | vcpu->arch.shadow_efer = efer; |
6aa8b732 AK |
201 | } |
202 | ||
298101da AK |
203 | static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr, |
204 | bool has_error_code, u32 error_code) | |
205 | { | |
206 | struct vcpu_svm *svm = to_svm(vcpu); | |
207 | ||
208 | svm->vmcb->control.event_inj = nr | |
209 | | SVM_EVTINJ_VALID | |
210 | | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0) | |
211 | | SVM_EVTINJ_TYPE_EXEPT; | |
212 | svm->vmcb->control.event_inj_err = error_code; | |
213 | } | |
214 | ||
215 | static bool svm_exception_injected(struct kvm_vcpu *vcpu) | |
216 | { | |
217 | struct vcpu_svm *svm = to_svm(vcpu); | |
218 | ||
219 | return !(svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID); | |
220 | } | |
221 | ||
6aa8b732 AK |
222 | static int is_external_interrupt(u32 info) |
223 | { | |
224 | info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID; | |
225 | return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR); | |
226 | } | |
227 | ||
228 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) | |
229 | { | |
a2fa3e9f GH |
230 | struct vcpu_svm *svm = to_svm(vcpu); |
231 | ||
232 | if (!svm->next_rip) { | |
b8688d51 | 233 | printk(KERN_DEBUG "%s: NOP\n", __func__); |
6aa8b732 AK |
234 | return; |
235 | } | |
d77c26fc | 236 | if (svm->next_rip - svm->vmcb->save.rip > MAX_INST_SIZE) |
6aa8b732 | 237 | printk(KERN_ERR "%s: ip 0x%llx next 0x%llx\n", |
b8688d51 | 238 | __func__, |
a2fa3e9f GH |
239 | svm->vmcb->save.rip, |
240 | svm->next_rip); | |
6aa8b732 | 241 | |
ad312c7c | 242 | vcpu->arch.rip = svm->vmcb->save.rip = svm->next_rip; |
a2fa3e9f | 243 | svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK; |
c1150d8c | 244 | |
ad312c7c | 245 | vcpu->arch.interrupt_window_open = 1; |
6aa8b732 AK |
246 | } |
247 | ||
248 | static int has_svm(void) | |
249 | { | |
250 | uint32_t eax, ebx, ecx, edx; | |
251 | ||
1e885461 | 252 | if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) { |
6aa8b732 AK |
253 | printk(KERN_INFO "has_svm: not amd\n"); |
254 | return 0; | |
255 | } | |
256 | ||
257 | cpuid(0x80000000, &eax, &ebx, &ecx, &edx); | |
258 | if (eax < SVM_CPUID_FUNC) { | |
259 | printk(KERN_INFO "has_svm: can't execute cpuid_8000000a\n"); | |
260 | return 0; | |
261 | } | |
262 | ||
263 | cpuid(0x80000001, &eax, &ebx, &ecx, &edx); | |
264 | if (!(ecx & (1 << SVM_CPUID_FEATURE_SHIFT))) { | |
265 | printk(KERN_DEBUG "has_svm: svm not available\n"); | |
266 | return 0; | |
267 | } | |
268 | return 1; | |
269 | } | |
270 | ||
271 | static void svm_hardware_disable(void *garbage) | |
272 | { | |
273 | struct svm_cpu_data *svm_data | |
274 | = per_cpu(svm_data, raw_smp_processor_id()); | |
275 | ||
276 | if (svm_data) { | |
277 | uint64_t efer; | |
278 | ||
279 | wrmsrl(MSR_VM_HSAVE_PA, 0); | |
280 | rdmsrl(MSR_EFER, efer); | |
281 | wrmsrl(MSR_EFER, efer & ~MSR_EFER_SVME_MASK); | |
8b6d44c7 | 282 | per_cpu(svm_data, raw_smp_processor_id()) = NULL; |
6aa8b732 AK |
283 | __free_page(svm_data->save_area); |
284 | kfree(svm_data); | |
285 | } | |
286 | } | |
287 | ||
288 | static void svm_hardware_enable(void *garbage) | |
289 | { | |
290 | ||
291 | struct svm_cpu_data *svm_data; | |
292 | uint64_t efer; | |
6aa8b732 | 293 | struct desc_ptr gdt_descr; |
6aa8b732 AK |
294 | struct desc_struct *gdt; |
295 | int me = raw_smp_processor_id(); | |
296 | ||
297 | if (!has_svm()) { | |
298 | printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me); | |
299 | return; | |
300 | } | |
301 | svm_data = per_cpu(svm_data, me); | |
302 | ||
303 | if (!svm_data) { | |
304 | printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n", | |
305 | me); | |
306 | return; | |
307 | } | |
308 | ||
309 | svm_data->asid_generation = 1; | |
310 | svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1; | |
311 | svm_data->next_asid = svm_data->max_asid + 1; | |
312 | ||
d77c26fc | 313 | asm volatile ("sgdt %0" : "=m"(gdt_descr)); |
6aa8b732 AK |
314 | gdt = (struct desc_struct *)gdt_descr.address; |
315 | svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS); | |
316 | ||
317 | rdmsrl(MSR_EFER, efer); | |
318 | wrmsrl(MSR_EFER, efer | MSR_EFER_SVME_MASK); | |
319 | ||
320 | wrmsrl(MSR_VM_HSAVE_PA, | |
321 | page_to_pfn(svm_data->save_area) << PAGE_SHIFT); | |
322 | } | |
323 | ||
324 | static int svm_cpu_init(int cpu) | |
325 | { | |
326 | struct svm_cpu_data *svm_data; | |
327 | int r; | |
328 | ||
329 | svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL); | |
330 | if (!svm_data) | |
331 | return -ENOMEM; | |
332 | svm_data->cpu = cpu; | |
333 | svm_data->save_area = alloc_page(GFP_KERNEL); | |
334 | r = -ENOMEM; | |
335 | if (!svm_data->save_area) | |
336 | goto err_1; | |
337 | ||
338 | per_cpu(svm_data, cpu) = svm_data; | |
339 | ||
340 | return 0; | |
341 | ||
342 | err_1: | |
343 | kfree(svm_data); | |
344 | return r; | |
345 | ||
346 | } | |
347 | ||
bfc733a7 RR |
348 | static void set_msr_interception(u32 *msrpm, unsigned msr, |
349 | int read, int write) | |
6aa8b732 AK |
350 | { |
351 | int i; | |
352 | ||
353 | for (i = 0; i < NUM_MSR_MAPS; i++) { | |
354 | if (msr >= msrpm_ranges[i] && | |
355 | msr < msrpm_ranges[i] + MSRS_IN_RANGE) { | |
356 | u32 msr_offset = (i * MSRS_IN_RANGE + msr - | |
357 | msrpm_ranges[i]) * 2; | |
358 | ||
359 | u32 *base = msrpm + (msr_offset / 32); | |
360 | u32 msr_shift = msr_offset % 32; | |
361 | u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1); | |
362 | *base = (*base & ~(0x3 << msr_shift)) | | |
363 | (mask << msr_shift); | |
bfc733a7 | 364 | return; |
6aa8b732 AK |
365 | } |
366 | } | |
bfc733a7 | 367 | BUG(); |
6aa8b732 AK |
368 | } |
369 | ||
f65c229c JR |
370 | static void svm_vcpu_init_msrpm(u32 *msrpm) |
371 | { | |
372 | memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER)); | |
373 | ||
374 | #ifdef CONFIG_X86_64 | |
375 | set_msr_interception(msrpm, MSR_GS_BASE, 1, 1); | |
376 | set_msr_interception(msrpm, MSR_FS_BASE, 1, 1); | |
377 | set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1); | |
378 | set_msr_interception(msrpm, MSR_LSTAR, 1, 1); | |
379 | set_msr_interception(msrpm, MSR_CSTAR, 1, 1); | |
380 | set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1); | |
381 | #endif | |
382 | set_msr_interception(msrpm, MSR_K6_STAR, 1, 1); | |
383 | set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1); | |
384 | set_msr_interception(msrpm, MSR_IA32_SYSENTER_ESP, 1, 1); | |
385 | set_msr_interception(msrpm, MSR_IA32_SYSENTER_EIP, 1, 1); | |
386 | } | |
387 | ||
24e09cbf JR |
388 | static void svm_enable_lbrv(struct vcpu_svm *svm) |
389 | { | |
390 | u32 *msrpm = svm->msrpm; | |
391 | ||
392 | svm->vmcb->control.lbr_ctl = 1; | |
393 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1); | |
394 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1); | |
395 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1); | |
396 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1); | |
397 | } | |
398 | ||
399 | static void svm_disable_lbrv(struct vcpu_svm *svm) | |
400 | { | |
401 | u32 *msrpm = svm->msrpm; | |
402 | ||
403 | svm->vmcb->control.lbr_ctl = 0; | |
404 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0); | |
405 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0); | |
406 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0); | |
407 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0); | |
408 | } | |
409 | ||
6aa8b732 AK |
410 | static __init int svm_hardware_setup(void) |
411 | { | |
412 | int cpu; | |
413 | struct page *iopm_pages; | |
f65c229c | 414 | void *iopm_va; |
6aa8b732 AK |
415 | int r; |
416 | ||
6aa8b732 AK |
417 | iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER); |
418 | ||
419 | if (!iopm_pages) | |
420 | return -ENOMEM; | |
c8681339 AL |
421 | |
422 | iopm_va = page_address(iopm_pages); | |
423 | memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER)); | |
424 | clear_bit(0x80, iopm_va); /* allow direct access to PC debug port */ | |
6aa8b732 AK |
425 | iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT; |
426 | ||
50a37eb4 JR |
427 | if (boot_cpu_has(X86_FEATURE_NX)) |
428 | kvm_enable_efer_bits(EFER_NX); | |
429 | ||
6aa8b732 AK |
430 | for_each_online_cpu(cpu) { |
431 | r = svm_cpu_init(cpu); | |
432 | if (r) | |
f65c229c | 433 | goto err; |
6aa8b732 | 434 | } |
33bd6a0b JR |
435 | |
436 | svm_features = cpuid_edx(SVM_CPUID_FUNC); | |
437 | ||
e3da3acd JR |
438 | if (!svm_has(SVM_FEATURE_NPT)) |
439 | npt_enabled = false; | |
440 | ||
6c7dac72 JR |
441 | if (npt_enabled && !npt) { |
442 | printk(KERN_INFO "kvm: Nested Paging disabled\n"); | |
443 | npt_enabled = false; | |
444 | } | |
445 | ||
18552672 | 446 | if (npt_enabled) { |
e3da3acd | 447 | printk(KERN_INFO "kvm: Nested Paging enabled\n"); |
18552672 JR |
448 | kvm_enable_tdp(); |
449 | } | |
e3da3acd | 450 | |
6aa8b732 AK |
451 | return 0; |
452 | ||
f65c229c | 453 | err: |
6aa8b732 AK |
454 | __free_pages(iopm_pages, IOPM_ALLOC_ORDER); |
455 | iopm_base = 0; | |
456 | return r; | |
457 | } | |
458 | ||
459 | static __exit void svm_hardware_unsetup(void) | |
460 | { | |
6aa8b732 | 461 | __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER); |
f65c229c | 462 | iopm_base = 0; |
6aa8b732 AK |
463 | } |
464 | ||
465 | static void init_seg(struct vmcb_seg *seg) | |
466 | { | |
467 | seg->selector = 0; | |
468 | seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK | | |
469 | SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */ | |
470 | seg->limit = 0xffff; | |
471 | seg->base = 0; | |
472 | } | |
473 | ||
474 | static void init_sys_seg(struct vmcb_seg *seg, uint32_t type) | |
475 | { | |
476 | seg->selector = 0; | |
477 | seg->attrib = SVM_SELECTOR_P_MASK | type; | |
478 | seg->limit = 0xffff; | |
479 | seg->base = 0; | |
480 | } | |
481 | ||
e6101a96 | 482 | static void init_vmcb(struct vcpu_svm *svm) |
6aa8b732 | 483 | { |
e6101a96 JR |
484 | struct vmcb_control_area *control = &svm->vmcb->control; |
485 | struct vmcb_save_area *save = &svm->vmcb->save; | |
6aa8b732 AK |
486 | |
487 | control->intercept_cr_read = INTERCEPT_CR0_MASK | | |
488 | INTERCEPT_CR3_MASK | | |
80a8119c AK |
489 | INTERCEPT_CR4_MASK | |
490 | INTERCEPT_CR8_MASK; | |
6aa8b732 AK |
491 | |
492 | control->intercept_cr_write = INTERCEPT_CR0_MASK | | |
493 | INTERCEPT_CR3_MASK | | |
80a8119c AK |
494 | INTERCEPT_CR4_MASK | |
495 | INTERCEPT_CR8_MASK; | |
6aa8b732 AK |
496 | |
497 | control->intercept_dr_read = INTERCEPT_DR0_MASK | | |
498 | INTERCEPT_DR1_MASK | | |
499 | INTERCEPT_DR2_MASK | | |
500 | INTERCEPT_DR3_MASK; | |
501 | ||
502 | control->intercept_dr_write = INTERCEPT_DR0_MASK | | |
503 | INTERCEPT_DR1_MASK | | |
504 | INTERCEPT_DR2_MASK | | |
505 | INTERCEPT_DR3_MASK | | |
506 | INTERCEPT_DR5_MASK | | |
507 | INTERCEPT_DR7_MASK; | |
508 | ||
7aa81cc0 AL |
509 | control->intercept_exceptions = (1 << PF_VECTOR) | |
510 | (1 << UD_VECTOR); | |
6aa8b732 AK |
511 | |
512 | ||
513 | control->intercept = (1ULL << INTERCEPT_INTR) | | |
514 | (1ULL << INTERCEPT_NMI) | | |
0152527b | 515 | (1ULL << INTERCEPT_SMI) | |
6aa8b732 AK |
516 | /* |
517 | * selective cr0 intercept bug? | |
518 | * 0: 0f 22 d8 mov %eax,%cr3 | |
519 | * 3: 0f 20 c0 mov %cr0,%eax | |
520 | * 6: 0d 00 00 00 80 or $0x80000000,%eax | |
521 | * b: 0f 22 c0 mov %eax,%cr0 | |
522 | * set cr3 ->interception | |
523 | * get cr0 ->interception | |
524 | * set cr0 -> no interception | |
525 | */ | |
526 | /* (1ULL << INTERCEPT_SELECTIVE_CR0) | */ | |
527 | (1ULL << INTERCEPT_CPUID) | | |
cf5a94d1 | 528 | (1ULL << INTERCEPT_INVD) | |
6aa8b732 | 529 | (1ULL << INTERCEPT_HLT) | |
6aa8b732 AK |
530 | (1ULL << INTERCEPT_INVLPGA) | |
531 | (1ULL << INTERCEPT_IOIO_PROT) | | |
532 | (1ULL << INTERCEPT_MSR_PROT) | | |
533 | (1ULL << INTERCEPT_TASK_SWITCH) | | |
46fe4ddd | 534 | (1ULL << INTERCEPT_SHUTDOWN) | |
6aa8b732 AK |
535 | (1ULL << INTERCEPT_VMRUN) | |
536 | (1ULL << INTERCEPT_VMMCALL) | | |
537 | (1ULL << INTERCEPT_VMLOAD) | | |
538 | (1ULL << INTERCEPT_VMSAVE) | | |
539 | (1ULL << INTERCEPT_STGI) | | |
540 | (1ULL << INTERCEPT_CLGI) | | |
916ce236 | 541 | (1ULL << INTERCEPT_SKINIT) | |
cf5a94d1 | 542 | (1ULL << INTERCEPT_WBINVD) | |
916ce236 JR |
543 | (1ULL << INTERCEPT_MONITOR) | |
544 | (1ULL << INTERCEPT_MWAIT); | |
6aa8b732 AK |
545 | |
546 | control->iopm_base_pa = iopm_base; | |
f65c229c | 547 | control->msrpm_base_pa = __pa(svm->msrpm); |
0cc5064d | 548 | control->tsc_offset = 0; |
6aa8b732 AK |
549 | control->int_ctl = V_INTR_MASKING_MASK; |
550 | ||
551 | init_seg(&save->es); | |
552 | init_seg(&save->ss); | |
553 | init_seg(&save->ds); | |
554 | init_seg(&save->fs); | |
555 | init_seg(&save->gs); | |
556 | ||
557 | save->cs.selector = 0xf000; | |
558 | /* Executable/Readable Code Segment */ | |
559 | save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK | | |
560 | SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK; | |
561 | save->cs.limit = 0xffff; | |
d92899a0 AK |
562 | /* |
563 | * cs.base should really be 0xffff0000, but vmx can't handle that, so | |
564 | * be consistent with it. | |
565 | * | |
566 | * Replace when we have real mode working for vmx. | |
567 | */ | |
568 | save->cs.base = 0xf0000; | |
6aa8b732 AK |
569 | |
570 | save->gdtr.limit = 0xffff; | |
571 | save->idtr.limit = 0xffff; | |
572 | ||
573 | init_sys_seg(&save->ldtr, SEG_TYPE_LDT); | |
574 | init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16); | |
575 | ||
576 | save->efer = MSR_EFER_SVME_MASK; | |
d77c26fc | 577 | save->dr6 = 0xffff0ff0; |
6aa8b732 AK |
578 | save->dr7 = 0x400; |
579 | save->rflags = 2; | |
580 | save->rip = 0x0000fff0; | |
581 | ||
582 | /* | |
583 | * cr0 val on cpu init should be 0x60000010, we enable cpu | |
584 | * cache by default. the orderly way is to enable cache in bios. | |
585 | */ | |
707d92fa | 586 | save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP; |
66aee91a | 587 | save->cr4 = X86_CR4_PAE; |
6aa8b732 | 588 | /* rdx = ?? */ |
709ddebf JR |
589 | |
590 | if (npt_enabled) { | |
591 | /* Setup VMCB for Nested Paging */ | |
592 | control->nested_ctl = 1; | |
593 | control->intercept_exceptions &= ~(1 << PF_VECTOR); | |
594 | control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK| | |
595 | INTERCEPT_CR3_MASK); | |
596 | control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK| | |
597 | INTERCEPT_CR3_MASK); | |
598 | save->g_pat = 0x0007040600070406ULL; | |
599 | /* enable caching because the QEMU Bios doesn't enable it */ | |
600 | save->cr0 = X86_CR0_ET; | |
601 | save->cr3 = 0; | |
602 | save->cr4 = 0; | |
603 | } | |
604 | ||
6aa8b732 AK |
605 | } |
606 | ||
e00c8cf2 | 607 | static int svm_vcpu_reset(struct kvm_vcpu *vcpu) |
04d2cc77 AK |
608 | { |
609 | struct vcpu_svm *svm = to_svm(vcpu); | |
610 | ||
e6101a96 | 611 | init_vmcb(svm); |
70433389 AK |
612 | |
613 | if (vcpu->vcpu_id != 0) { | |
614 | svm->vmcb->save.rip = 0; | |
ad312c7c ZX |
615 | svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12; |
616 | svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8; | |
70433389 | 617 | } |
e00c8cf2 AK |
618 | |
619 | return 0; | |
04d2cc77 AK |
620 | } |
621 | ||
fb3f0f51 | 622 | static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 623 | { |
a2fa3e9f | 624 | struct vcpu_svm *svm; |
6aa8b732 | 625 | struct page *page; |
f65c229c | 626 | struct page *msrpm_pages; |
fb3f0f51 | 627 | int err; |
6aa8b732 | 628 | |
c16f862d | 629 | svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); |
fb3f0f51 RR |
630 | if (!svm) { |
631 | err = -ENOMEM; | |
632 | goto out; | |
633 | } | |
634 | ||
635 | err = kvm_vcpu_init(&svm->vcpu, kvm, id); | |
636 | if (err) | |
637 | goto free_svm; | |
638 | ||
6aa8b732 | 639 | page = alloc_page(GFP_KERNEL); |
fb3f0f51 RR |
640 | if (!page) { |
641 | err = -ENOMEM; | |
642 | goto uninit; | |
643 | } | |
6aa8b732 | 644 | |
f65c229c JR |
645 | err = -ENOMEM; |
646 | msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); | |
647 | if (!msrpm_pages) | |
648 | goto uninit; | |
649 | svm->msrpm = page_address(msrpm_pages); | |
650 | svm_vcpu_init_msrpm(svm->msrpm); | |
651 | ||
a2fa3e9f GH |
652 | svm->vmcb = page_address(page); |
653 | clear_page(svm->vmcb); | |
654 | svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT; | |
655 | svm->asid_generation = 0; | |
656 | memset(svm->db_regs, 0, sizeof(svm->db_regs)); | |
e6101a96 | 657 | init_vmcb(svm); |
a2fa3e9f | 658 | |
fb3f0f51 RR |
659 | fx_init(&svm->vcpu); |
660 | svm->vcpu.fpu_active = 1; | |
ad312c7c | 661 | svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE; |
fb3f0f51 | 662 | if (svm->vcpu.vcpu_id == 0) |
ad312c7c | 663 | svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP; |
6aa8b732 | 664 | |
fb3f0f51 | 665 | return &svm->vcpu; |
36241b8c | 666 | |
fb3f0f51 RR |
667 | uninit: |
668 | kvm_vcpu_uninit(&svm->vcpu); | |
669 | free_svm: | |
a4770347 | 670 | kmem_cache_free(kvm_vcpu_cache, svm); |
fb3f0f51 RR |
671 | out: |
672 | return ERR_PTR(err); | |
6aa8b732 AK |
673 | } |
674 | ||
675 | static void svm_free_vcpu(struct kvm_vcpu *vcpu) | |
676 | { | |
a2fa3e9f GH |
677 | struct vcpu_svm *svm = to_svm(vcpu); |
678 | ||
fb3f0f51 | 679 | __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT)); |
f65c229c | 680 | __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER); |
fb3f0f51 | 681 | kvm_vcpu_uninit(vcpu); |
a4770347 | 682 | kmem_cache_free(kvm_vcpu_cache, svm); |
6aa8b732 AK |
683 | } |
684 | ||
15ad7146 | 685 | static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 686 | { |
a2fa3e9f | 687 | struct vcpu_svm *svm = to_svm(vcpu); |
15ad7146 | 688 | int i; |
0cc5064d | 689 | |
0cc5064d AK |
690 | if (unlikely(cpu != vcpu->cpu)) { |
691 | u64 tsc_this, delta; | |
692 | ||
693 | /* | |
694 | * Make sure that the guest sees a monotonically | |
695 | * increasing TSC. | |
696 | */ | |
697 | rdtscll(tsc_this); | |
ad312c7c | 698 | delta = vcpu->arch.host_tsc - tsc_this; |
a2fa3e9f | 699 | svm->vmcb->control.tsc_offset += delta; |
0cc5064d | 700 | vcpu->cpu = cpu; |
a3d7f85f | 701 | kvm_migrate_apic_timer(vcpu); |
0cc5064d | 702 | } |
94dfbdb3 AL |
703 | |
704 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) | |
a2fa3e9f | 705 | rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
6aa8b732 AK |
706 | } |
707 | ||
708 | static void svm_vcpu_put(struct kvm_vcpu *vcpu) | |
709 | { | |
a2fa3e9f | 710 | struct vcpu_svm *svm = to_svm(vcpu); |
94dfbdb3 AL |
711 | int i; |
712 | ||
e1beb1d3 | 713 | ++vcpu->stat.host_state_reload; |
94dfbdb3 | 714 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) |
a2fa3e9f | 715 | wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
94dfbdb3 | 716 | |
ad312c7c | 717 | rdtscll(vcpu->arch.host_tsc); |
6aa8b732 AK |
718 | } |
719 | ||
774c47f1 AK |
720 | static void svm_vcpu_decache(struct kvm_vcpu *vcpu) |
721 | { | |
722 | } | |
723 | ||
6aa8b732 AK |
724 | static void svm_cache_regs(struct kvm_vcpu *vcpu) |
725 | { | |
a2fa3e9f GH |
726 | struct vcpu_svm *svm = to_svm(vcpu); |
727 | ||
ad312c7c ZX |
728 | vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax; |
729 | vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp; | |
730 | vcpu->arch.rip = svm->vmcb->save.rip; | |
6aa8b732 AK |
731 | } |
732 | ||
733 | static void svm_decache_regs(struct kvm_vcpu *vcpu) | |
734 | { | |
a2fa3e9f | 735 | struct vcpu_svm *svm = to_svm(vcpu); |
ad312c7c ZX |
736 | svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX]; |
737 | svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP]; | |
738 | svm->vmcb->save.rip = vcpu->arch.rip; | |
6aa8b732 AK |
739 | } |
740 | ||
741 | static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu) | |
742 | { | |
a2fa3e9f | 743 | return to_svm(vcpu)->vmcb->save.rflags; |
6aa8b732 AK |
744 | } |
745 | ||
746 | static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
747 | { | |
a2fa3e9f | 748 | to_svm(vcpu)->vmcb->save.rflags = rflags; |
6aa8b732 AK |
749 | } |
750 | ||
751 | static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg) | |
752 | { | |
a2fa3e9f | 753 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; |
6aa8b732 AK |
754 | |
755 | switch (seg) { | |
756 | case VCPU_SREG_CS: return &save->cs; | |
757 | case VCPU_SREG_DS: return &save->ds; | |
758 | case VCPU_SREG_ES: return &save->es; | |
759 | case VCPU_SREG_FS: return &save->fs; | |
760 | case VCPU_SREG_GS: return &save->gs; | |
761 | case VCPU_SREG_SS: return &save->ss; | |
762 | case VCPU_SREG_TR: return &save->tr; | |
763 | case VCPU_SREG_LDTR: return &save->ldtr; | |
764 | } | |
765 | BUG(); | |
8b6d44c7 | 766 | return NULL; |
6aa8b732 AK |
767 | } |
768 | ||
769 | static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg) | |
770 | { | |
771 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
772 | ||
773 | return s->base; | |
774 | } | |
775 | ||
776 | static void svm_get_segment(struct kvm_vcpu *vcpu, | |
777 | struct kvm_segment *var, int seg) | |
778 | { | |
779 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
780 | ||
781 | var->base = s->base; | |
782 | var->limit = s->limit; | |
783 | var->selector = s->selector; | |
784 | var->type = s->attrib & SVM_SELECTOR_TYPE_MASK; | |
785 | var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1; | |
786 | var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3; | |
787 | var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1; | |
788 | var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1; | |
789 | var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1; | |
790 | var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1; | |
791 | var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1; | |
792 | var->unusable = !var->present; | |
793 | } | |
794 | ||
6aa8b732 AK |
795 | static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) |
796 | { | |
a2fa3e9f GH |
797 | struct vcpu_svm *svm = to_svm(vcpu); |
798 | ||
799 | dt->limit = svm->vmcb->save.idtr.limit; | |
800 | dt->base = svm->vmcb->save.idtr.base; | |
6aa8b732 AK |
801 | } |
802 | ||
803 | static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
804 | { | |
a2fa3e9f GH |
805 | struct vcpu_svm *svm = to_svm(vcpu); |
806 | ||
807 | svm->vmcb->save.idtr.limit = dt->limit; | |
808 | svm->vmcb->save.idtr.base = dt->base ; | |
6aa8b732 AK |
809 | } |
810 | ||
811 | static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
812 | { | |
a2fa3e9f GH |
813 | struct vcpu_svm *svm = to_svm(vcpu); |
814 | ||
815 | dt->limit = svm->vmcb->save.gdtr.limit; | |
816 | dt->base = svm->vmcb->save.gdtr.base; | |
6aa8b732 AK |
817 | } |
818 | ||
819 | static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
820 | { | |
a2fa3e9f GH |
821 | struct vcpu_svm *svm = to_svm(vcpu); |
822 | ||
823 | svm->vmcb->save.gdtr.limit = dt->limit; | |
824 | svm->vmcb->save.gdtr.base = dt->base ; | |
6aa8b732 AK |
825 | } |
826 | ||
25c4c276 | 827 | static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 AK |
828 | { |
829 | } | |
830 | ||
6aa8b732 AK |
831 | static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
832 | { | |
a2fa3e9f GH |
833 | struct vcpu_svm *svm = to_svm(vcpu); |
834 | ||
05b3e0c2 | 835 | #ifdef CONFIG_X86_64 |
ad312c7c | 836 | if (vcpu->arch.shadow_efer & EFER_LME) { |
707d92fa | 837 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { |
ad312c7c | 838 | vcpu->arch.shadow_efer |= EFER_LMA; |
2b5203ee | 839 | svm->vmcb->save.efer |= EFER_LMA | EFER_LME; |
6aa8b732 AK |
840 | } |
841 | ||
d77c26fc | 842 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) { |
ad312c7c | 843 | vcpu->arch.shadow_efer &= ~EFER_LMA; |
2b5203ee | 844 | svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME); |
6aa8b732 AK |
845 | } |
846 | } | |
847 | #endif | |
709ddebf JR |
848 | if (npt_enabled) |
849 | goto set; | |
850 | ||
ad312c7c | 851 | if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) { |
a2fa3e9f | 852 | svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR); |
7807fa6c AL |
853 | vcpu->fpu_active = 1; |
854 | } | |
855 | ||
ad312c7c | 856 | vcpu->arch.cr0 = cr0; |
707d92fa | 857 | cr0 |= X86_CR0_PG | X86_CR0_WP; |
6b390b63 JR |
858 | if (!vcpu->fpu_active) { |
859 | svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR); | |
334df50a | 860 | cr0 |= X86_CR0_TS; |
6b390b63 | 861 | } |
709ddebf JR |
862 | set: |
863 | /* | |
864 | * re-enable caching here because the QEMU bios | |
865 | * does not do it - this results in some delay at | |
866 | * reboot | |
867 | */ | |
868 | cr0 &= ~(X86_CR0_CD | X86_CR0_NW); | |
a2fa3e9f | 869 | svm->vmcb->save.cr0 = cr0; |
6aa8b732 AK |
870 | } |
871 | ||
872 | static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) | |
873 | { | |
ad312c7c | 874 | vcpu->arch.cr4 = cr4; |
709ddebf JR |
875 | if (!npt_enabled) |
876 | cr4 |= X86_CR4_PAE; | |
877 | to_svm(vcpu)->vmcb->save.cr4 = cr4; | |
6aa8b732 AK |
878 | } |
879 | ||
880 | static void svm_set_segment(struct kvm_vcpu *vcpu, | |
881 | struct kvm_segment *var, int seg) | |
882 | { | |
a2fa3e9f | 883 | struct vcpu_svm *svm = to_svm(vcpu); |
6aa8b732 AK |
884 | struct vmcb_seg *s = svm_seg(vcpu, seg); |
885 | ||
886 | s->base = var->base; | |
887 | s->limit = var->limit; | |
888 | s->selector = var->selector; | |
889 | if (var->unusable) | |
890 | s->attrib = 0; | |
891 | else { | |
892 | s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK); | |
893 | s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT; | |
894 | s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT; | |
895 | s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT; | |
896 | s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT; | |
897 | s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT; | |
898 | s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT; | |
899 | s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT; | |
900 | } | |
901 | if (seg == VCPU_SREG_CS) | |
a2fa3e9f GH |
902 | svm->vmcb->save.cpl |
903 | = (svm->vmcb->save.cs.attrib | |
6aa8b732 AK |
904 | >> SVM_SELECTOR_DPL_SHIFT) & 3; |
905 | ||
906 | } | |
907 | ||
908 | /* FIXME: | |
909 | ||
a2fa3e9f GH |
910 | svm(vcpu)->vmcb->control.int_ctl &= ~V_TPR_MASK; |
911 | svm(vcpu)->vmcb->control.int_ctl |= (sregs->cr8 & V_TPR_MASK); | |
6aa8b732 AK |
912 | |
913 | */ | |
914 | ||
915 | static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg) | |
916 | { | |
917 | return -EOPNOTSUPP; | |
918 | } | |
919 | ||
2a8067f1 ED |
920 | static int svm_get_irq(struct kvm_vcpu *vcpu) |
921 | { | |
922 | struct vcpu_svm *svm = to_svm(vcpu); | |
923 | u32 exit_int_info = svm->vmcb->control.exit_int_info; | |
924 | ||
925 | if (is_external_interrupt(exit_int_info)) | |
926 | return exit_int_info & SVM_EVTINJ_VEC_MASK; | |
927 | return -1; | |
928 | } | |
929 | ||
6aa8b732 AK |
930 | static void load_host_msrs(struct kvm_vcpu *vcpu) |
931 | { | |
94dfbdb3 | 932 | #ifdef CONFIG_X86_64 |
a2fa3e9f | 933 | wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base); |
94dfbdb3 | 934 | #endif |
6aa8b732 AK |
935 | } |
936 | ||
937 | static void save_host_msrs(struct kvm_vcpu *vcpu) | |
938 | { | |
94dfbdb3 | 939 | #ifdef CONFIG_X86_64 |
a2fa3e9f | 940 | rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base); |
94dfbdb3 | 941 | #endif |
6aa8b732 AK |
942 | } |
943 | ||
e756fc62 | 944 | static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data) |
6aa8b732 AK |
945 | { |
946 | if (svm_data->next_asid > svm_data->max_asid) { | |
947 | ++svm_data->asid_generation; | |
948 | svm_data->next_asid = 1; | |
a2fa3e9f | 949 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID; |
6aa8b732 AK |
950 | } |
951 | ||
e756fc62 | 952 | svm->vcpu.cpu = svm_data->cpu; |
a2fa3e9f GH |
953 | svm->asid_generation = svm_data->asid_generation; |
954 | svm->vmcb->control.asid = svm_data->next_asid++; | |
6aa8b732 AK |
955 | } |
956 | ||
6aa8b732 AK |
957 | static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr) |
958 | { | |
a2fa3e9f | 959 | return to_svm(vcpu)->db_regs[dr]; |
6aa8b732 AK |
960 | } |
961 | ||
962 | static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value, | |
963 | int *exception) | |
964 | { | |
a2fa3e9f GH |
965 | struct vcpu_svm *svm = to_svm(vcpu); |
966 | ||
6aa8b732 AK |
967 | *exception = 0; |
968 | ||
a2fa3e9f GH |
969 | if (svm->vmcb->save.dr7 & DR7_GD_MASK) { |
970 | svm->vmcb->save.dr7 &= ~DR7_GD_MASK; | |
971 | svm->vmcb->save.dr6 |= DR6_BD_MASK; | |
6aa8b732 AK |
972 | *exception = DB_VECTOR; |
973 | return; | |
974 | } | |
975 | ||
976 | switch (dr) { | |
977 | case 0 ... 3: | |
a2fa3e9f | 978 | svm->db_regs[dr] = value; |
6aa8b732 AK |
979 | return; |
980 | case 4 ... 5: | |
ad312c7c | 981 | if (vcpu->arch.cr4 & X86_CR4_DE) { |
6aa8b732 AK |
982 | *exception = UD_VECTOR; |
983 | return; | |
984 | } | |
985 | case 7: { | |
986 | if (value & ~((1ULL << 32) - 1)) { | |
987 | *exception = GP_VECTOR; | |
988 | return; | |
989 | } | |
a2fa3e9f | 990 | svm->vmcb->save.dr7 = value; |
6aa8b732 AK |
991 | return; |
992 | } | |
993 | default: | |
994 | printk(KERN_DEBUG "%s: unexpected dr %u\n", | |
b8688d51 | 995 | __func__, dr); |
6aa8b732 AK |
996 | *exception = UD_VECTOR; |
997 | return; | |
998 | } | |
999 | } | |
1000 | ||
e756fc62 | 1001 | static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1002 | { |
a2fa3e9f | 1003 | u32 exit_int_info = svm->vmcb->control.exit_int_info; |
e756fc62 | 1004 | struct kvm *kvm = svm->vcpu.kvm; |
6aa8b732 AK |
1005 | u64 fault_address; |
1006 | u32 error_code; | |
6aa8b732 | 1007 | |
85f455f7 ED |
1008 | if (!irqchip_in_kernel(kvm) && |
1009 | is_external_interrupt(exit_int_info)) | |
e756fc62 | 1010 | push_irq(&svm->vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK); |
6aa8b732 | 1011 | |
a2fa3e9f GH |
1012 | fault_address = svm->vmcb->control.exit_info_2; |
1013 | error_code = svm->vmcb->control.exit_info_1; | |
3067714c | 1014 | return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code); |
6aa8b732 AK |
1015 | } |
1016 | ||
7aa81cc0 AL |
1017 | static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
1018 | { | |
1019 | int er; | |
1020 | ||
571008da | 1021 | er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD); |
7aa81cc0 | 1022 | if (er != EMULATE_DONE) |
7ee5d940 | 1023 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
7aa81cc0 AL |
1024 | return 1; |
1025 | } | |
1026 | ||
e756fc62 | 1027 | static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
7807fa6c | 1028 | { |
a2fa3e9f | 1029 | svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR); |
ad312c7c | 1030 | if (!(svm->vcpu.arch.cr0 & X86_CR0_TS)) |
a2fa3e9f | 1031 | svm->vmcb->save.cr0 &= ~X86_CR0_TS; |
e756fc62 | 1032 | svm->vcpu.fpu_active = 1; |
a2fa3e9f GH |
1033 | |
1034 | return 1; | |
7807fa6c AL |
1035 | } |
1036 | ||
e756fc62 | 1037 | static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
46fe4ddd JR |
1038 | { |
1039 | /* | |
1040 | * VMCB is undefined after a SHUTDOWN intercept | |
1041 | * so reinitialize it. | |
1042 | */ | |
a2fa3e9f | 1043 | clear_page(svm->vmcb); |
e6101a96 | 1044 | init_vmcb(svm); |
46fe4ddd JR |
1045 | |
1046 | kvm_run->exit_reason = KVM_EXIT_SHUTDOWN; | |
1047 | return 0; | |
1048 | } | |
1049 | ||
e756fc62 | 1050 | static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1051 | { |
d77c26fc | 1052 | u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */ |
039576c0 AK |
1053 | int size, down, in, string, rep; |
1054 | unsigned port; | |
6aa8b732 | 1055 | |
e756fc62 | 1056 | ++svm->vcpu.stat.io_exits; |
6aa8b732 | 1057 | |
a2fa3e9f | 1058 | svm->next_rip = svm->vmcb->control.exit_info_2; |
6aa8b732 | 1059 | |
e70669ab LV |
1060 | string = (io_info & SVM_IOIO_STR_MASK) != 0; |
1061 | ||
1062 | if (string) { | |
3427318f LV |
1063 | if (emulate_instruction(&svm->vcpu, |
1064 | kvm_run, 0, 0, 0) == EMULATE_DO_MMIO) | |
e70669ab LV |
1065 | return 0; |
1066 | return 1; | |
1067 | } | |
1068 | ||
039576c0 AK |
1069 | in = (io_info & SVM_IOIO_TYPE_MASK) != 0; |
1070 | port = io_info >> 16; | |
1071 | size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT; | |
039576c0 | 1072 | rep = (io_info & SVM_IOIO_REP_MASK) != 0; |
a2fa3e9f | 1073 | down = (svm->vmcb->save.rflags & X86_EFLAGS_DF) != 0; |
6aa8b732 | 1074 | |
3090dd73 | 1075 | return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port); |
6aa8b732 AK |
1076 | } |
1077 | ||
e756fc62 | 1078 | static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 AK |
1079 | { |
1080 | return 1; | |
1081 | } | |
1082 | ||
e756fc62 | 1083 | static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1084 | { |
a2fa3e9f | 1085 | svm->next_rip = svm->vmcb->save.rip + 1; |
e756fc62 RR |
1086 | skip_emulated_instruction(&svm->vcpu); |
1087 | return kvm_emulate_halt(&svm->vcpu); | |
6aa8b732 AK |
1088 | } |
1089 | ||
e756fc62 | 1090 | static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
02e235bc | 1091 | { |
a2fa3e9f | 1092 | svm->next_rip = svm->vmcb->save.rip + 3; |
e756fc62 | 1093 | skip_emulated_instruction(&svm->vcpu); |
7aa81cc0 AL |
1094 | kvm_emulate_hypercall(&svm->vcpu); |
1095 | return 1; | |
02e235bc AK |
1096 | } |
1097 | ||
e756fc62 RR |
1098 | static int invalid_op_interception(struct vcpu_svm *svm, |
1099 | struct kvm_run *kvm_run) | |
6aa8b732 | 1100 | { |
7ee5d940 | 1101 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
6aa8b732 AK |
1102 | return 1; |
1103 | } | |
1104 | ||
e756fc62 RR |
1105 | static int task_switch_interception(struct vcpu_svm *svm, |
1106 | struct kvm_run *kvm_run) | |
6aa8b732 | 1107 | { |
b8688d51 | 1108 | pr_unimpl(&svm->vcpu, "%s: task switch is unsupported\n", __func__); |
6aa8b732 AK |
1109 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; |
1110 | return 0; | |
1111 | } | |
1112 | ||
e756fc62 | 1113 | static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1114 | { |
a2fa3e9f | 1115 | svm->next_rip = svm->vmcb->save.rip + 2; |
e756fc62 | 1116 | kvm_emulate_cpuid(&svm->vcpu); |
06465c5a | 1117 | return 1; |
6aa8b732 AK |
1118 | } |
1119 | ||
e756fc62 RR |
1120 | static int emulate_on_interception(struct vcpu_svm *svm, |
1121 | struct kvm_run *kvm_run) | |
6aa8b732 | 1122 | { |
3427318f | 1123 | if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE) |
b8688d51 | 1124 | pr_unimpl(&svm->vcpu, "%s: failed\n", __func__); |
6aa8b732 AK |
1125 | return 1; |
1126 | } | |
1127 | ||
1d075434 JR |
1128 | static int cr8_write_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
1129 | { | |
1130 | emulate_instruction(&svm->vcpu, NULL, 0, 0, 0); | |
1131 | if (irqchip_in_kernel(svm->vcpu.kvm)) | |
1132 | return 1; | |
1133 | kvm_run->exit_reason = KVM_EXIT_SET_TPR; | |
1134 | return 0; | |
1135 | } | |
1136 | ||
6aa8b732 AK |
1137 | static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data) |
1138 | { | |
a2fa3e9f GH |
1139 | struct vcpu_svm *svm = to_svm(vcpu); |
1140 | ||
6aa8b732 | 1141 | switch (ecx) { |
6aa8b732 AK |
1142 | case MSR_IA32_TIME_STAMP_COUNTER: { |
1143 | u64 tsc; | |
1144 | ||
1145 | rdtscll(tsc); | |
a2fa3e9f | 1146 | *data = svm->vmcb->control.tsc_offset + tsc; |
6aa8b732 AK |
1147 | break; |
1148 | } | |
0e859cac | 1149 | case MSR_K6_STAR: |
a2fa3e9f | 1150 | *data = svm->vmcb->save.star; |
6aa8b732 | 1151 | break; |
0e859cac | 1152 | #ifdef CONFIG_X86_64 |
6aa8b732 | 1153 | case MSR_LSTAR: |
a2fa3e9f | 1154 | *data = svm->vmcb->save.lstar; |
6aa8b732 AK |
1155 | break; |
1156 | case MSR_CSTAR: | |
a2fa3e9f | 1157 | *data = svm->vmcb->save.cstar; |
6aa8b732 AK |
1158 | break; |
1159 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 1160 | *data = svm->vmcb->save.kernel_gs_base; |
6aa8b732 AK |
1161 | break; |
1162 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 1163 | *data = svm->vmcb->save.sfmask; |
6aa8b732 AK |
1164 | break; |
1165 | #endif | |
1166 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 1167 | *data = svm->vmcb->save.sysenter_cs; |
6aa8b732 AK |
1168 | break; |
1169 | case MSR_IA32_SYSENTER_EIP: | |
a2fa3e9f | 1170 | *data = svm->vmcb->save.sysenter_eip; |
6aa8b732 AK |
1171 | break; |
1172 | case MSR_IA32_SYSENTER_ESP: | |
a2fa3e9f | 1173 | *data = svm->vmcb->save.sysenter_esp; |
6aa8b732 | 1174 | break; |
a2938c80 JR |
1175 | /* Nobody will change the following 5 values in the VMCB so |
1176 | we can safely return them on rdmsr. They will always be 0 | |
1177 | until LBRV is implemented. */ | |
1178 | case MSR_IA32_DEBUGCTLMSR: | |
1179 | *data = svm->vmcb->save.dbgctl; | |
1180 | break; | |
1181 | case MSR_IA32_LASTBRANCHFROMIP: | |
1182 | *data = svm->vmcb->save.br_from; | |
1183 | break; | |
1184 | case MSR_IA32_LASTBRANCHTOIP: | |
1185 | *data = svm->vmcb->save.br_to; | |
1186 | break; | |
1187 | case MSR_IA32_LASTINTFROMIP: | |
1188 | *data = svm->vmcb->save.last_excp_from; | |
1189 | break; | |
1190 | case MSR_IA32_LASTINTTOIP: | |
1191 | *data = svm->vmcb->save.last_excp_to; | |
1192 | break; | |
6aa8b732 | 1193 | default: |
3bab1f5d | 1194 | return kvm_get_msr_common(vcpu, ecx, data); |
6aa8b732 AK |
1195 | } |
1196 | return 0; | |
1197 | } | |
1198 | ||
e756fc62 | 1199 | static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1200 | { |
ad312c7c | 1201 | u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
6aa8b732 AK |
1202 | u64 data; |
1203 | ||
e756fc62 | 1204 | if (svm_get_msr(&svm->vcpu, ecx, &data)) |
c1a5d4f9 | 1205 | kvm_inject_gp(&svm->vcpu, 0); |
6aa8b732 | 1206 | else { |
a2fa3e9f | 1207 | svm->vmcb->save.rax = data & 0xffffffff; |
ad312c7c | 1208 | svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32; |
a2fa3e9f | 1209 | svm->next_rip = svm->vmcb->save.rip + 2; |
e756fc62 | 1210 | skip_emulated_instruction(&svm->vcpu); |
6aa8b732 AK |
1211 | } |
1212 | return 1; | |
1213 | } | |
1214 | ||
1215 | static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data) | |
1216 | { | |
a2fa3e9f GH |
1217 | struct vcpu_svm *svm = to_svm(vcpu); |
1218 | ||
6aa8b732 | 1219 | switch (ecx) { |
6aa8b732 AK |
1220 | case MSR_IA32_TIME_STAMP_COUNTER: { |
1221 | u64 tsc; | |
1222 | ||
1223 | rdtscll(tsc); | |
a2fa3e9f | 1224 | svm->vmcb->control.tsc_offset = data - tsc; |
6aa8b732 AK |
1225 | break; |
1226 | } | |
0e859cac | 1227 | case MSR_K6_STAR: |
a2fa3e9f | 1228 | svm->vmcb->save.star = data; |
6aa8b732 | 1229 | break; |
49b14f24 | 1230 | #ifdef CONFIG_X86_64 |
6aa8b732 | 1231 | case MSR_LSTAR: |
a2fa3e9f | 1232 | svm->vmcb->save.lstar = data; |
6aa8b732 AK |
1233 | break; |
1234 | case MSR_CSTAR: | |
a2fa3e9f | 1235 | svm->vmcb->save.cstar = data; |
6aa8b732 AK |
1236 | break; |
1237 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 1238 | svm->vmcb->save.kernel_gs_base = data; |
6aa8b732 AK |
1239 | break; |
1240 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 1241 | svm->vmcb->save.sfmask = data; |
6aa8b732 AK |
1242 | break; |
1243 | #endif | |
1244 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 1245 | svm->vmcb->save.sysenter_cs = data; |
6aa8b732 AK |
1246 | break; |
1247 | case MSR_IA32_SYSENTER_EIP: | |
a2fa3e9f | 1248 | svm->vmcb->save.sysenter_eip = data; |
6aa8b732 AK |
1249 | break; |
1250 | case MSR_IA32_SYSENTER_ESP: | |
a2fa3e9f | 1251 | svm->vmcb->save.sysenter_esp = data; |
6aa8b732 | 1252 | break; |
a2938c80 | 1253 | case MSR_IA32_DEBUGCTLMSR: |
24e09cbf JR |
1254 | if (!svm_has(SVM_FEATURE_LBRV)) { |
1255 | pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n", | |
b8688d51 | 1256 | __func__, data); |
24e09cbf JR |
1257 | break; |
1258 | } | |
1259 | if (data & DEBUGCTL_RESERVED_BITS) | |
1260 | return 1; | |
1261 | ||
1262 | svm->vmcb->save.dbgctl = data; | |
1263 | if (data & (1ULL<<0)) | |
1264 | svm_enable_lbrv(svm); | |
1265 | else | |
1266 | svm_disable_lbrv(svm); | |
a2938c80 | 1267 | break; |
62b9abaa JR |
1268 | case MSR_K7_EVNTSEL0: |
1269 | case MSR_K7_EVNTSEL1: | |
1270 | case MSR_K7_EVNTSEL2: | |
1271 | case MSR_K7_EVNTSEL3: | |
1272 | /* | |
1273 | * only support writing 0 to the performance counters for now | |
1274 | * to make Windows happy. Should be replaced by a real | |
1275 | * performance counter emulation later. | |
1276 | */ | |
1277 | if (data != 0) | |
1278 | goto unhandled; | |
1279 | break; | |
6aa8b732 | 1280 | default: |
62b9abaa | 1281 | unhandled: |
3bab1f5d | 1282 | return kvm_set_msr_common(vcpu, ecx, data); |
6aa8b732 AK |
1283 | } |
1284 | return 0; | |
1285 | } | |
1286 | ||
e756fc62 | 1287 | static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1288 | { |
ad312c7c | 1289 | u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
a2fa3e9f | 1290 | u64 data = (svm->vmcb->save.rax & -1u) |
ad312c7c | 1291 | | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32); |
a2fa3e9f | 1292 | svm->next_rip = svm->vmcb->save.rip + 2; |
e756fc62 | 1293 | if (svm_set_msr(&svm->vcpu, ecx, data)) |
c1a5d4f9 | 1294 | kvm_inject_gp(&svm->vcpu, 0); |
6aa8b732 | 1295 | else |
e756fc62 | 1296 | skip_emulated_instruction(&svm->vcpu); |
6aa8b732 AK |
1297 | return 1; |
1298 | } | |
1299 | ||
e756fc62 | 1300 | static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1301 | { |
e756fc62 RR |
1302 | if (svm->vmcb->control.exit_info_1) |
1303 | return wrmsr_interception(svm, kvm_run); | |
6aa8b732 | 1304 | else |
e756fc62 | 1305 | return rdmsr_interception(svm, kvm_run); |
6aa8b732 AK |
1306 | } |
1307 | ||
e756fc62 | 1308 | static int interrupt_window_interception(struct vcpu_svm *svm, |
c1150d8c DL |
1309 | struct kvm_run *kvm_run) |
1310 | { | |
85f455f7 ED |
1311 | svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR); |
1312 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; | |
c1150d8c DL |
1313 | /* |
1314 | * If the user space waits to inject interrupts, exit as soon as | |
1315 | * possible | |
1316 | */ | |
1317 | if (kvm_run->request_interrupt_window && | |
ad312c7c | 1318 | !svm->vcpu.arch.irq_summary) { |
e756fc62 | 1319 | ++svm->vcpu.stat.irq_window_exits; |
c1150d8c DL |
1320 | kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; |
1321 | return 0; | |
1322 | } | |
1323 | ||
1324 | return 1; | |
1325 | } | |
1326 | ||
e756fc62 | 1327 | static int (*svm_exit_handlers[])(struct vcpu_svm *svm, |
6aa8b732 AK |
1328 | struct kvm_run *kvm_run) = { |
1329 | [SVM_EXIT_READ_CR0] = emulate_on_interception, | |
1330 | [SVM_EXIT_READ_CR3] = emulate_on_interception, | |
1331 | [SVM_EXIT_READ_CR4] = emulate_on_interception, | |
80a8119c | 1332 | [SVM_EXIT_READ_CR8] = emulate_on_interception, |
6aa8b732 AK |
1333 | /* for now: */ |
1334 | [SVM_EXIT_WRITE_CR0] = emulate_on_interception, | |
1335 | [SVM_EXIT_WRITE_CR3] = emulate_on_interception, | |
1336 | [SVM_EXIT_WRITE_CR4] = emulate_on_interception, | |
1d075434 | 1337 | [SVM_EXIT_WRITE_CR8] = cr8_write_interception, |
6aa8b732 AK |
1338 | [SVM_EXIT_READ_DR0] = emulate_on_interception, |
1339 | [SVM_EXIT_READ_DR1] = emulate_on_interception, | |
1340 | [SVM_EXIT_READ_DR2] = emulate_on_interception, | |
1341 | [SVM_EXIT_READ_DR3] = emulate_on_interception, | |
1342 | [SVM_EXIT_WRITE_DR0] = emulate_on_interception, | |
1343 | [SVM_EXIT_WRITE_DR1] = emulate_on_interception, | |
1344 | [SVM_EXIT_WRITE_DR2] = emulate_on_interception, | |
1345 | [SVM_EXIT_WRITE_DR3] = emulate_on_interception, | |
1346 | [SVM_EXIT_WRITE_DR5] = emulate_on_interception, | |
1347 | [SVM_EXIT_WRITE_DR7] = emulate_on_interception, | |
7aa81cc0 | 1348 | [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception, |
6aa8b732 | 1349 | [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception, |
7807fa6c | 1350 | [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception, |
6aa8b732 AK |
1351 | [SVM_EXIT_INTR] = nop_on_interception, |
1352 | [SVM_EXIT_NMI] = nop_on_interception, | |
1353 | [SVM_EXIT_SMI] = nop_on_interception, | |
1354 | [SVM_EXIT_INIT] = nop_on_interception, | |
c1150d8c | 1355 | [SVM_EXIT_VINTR] = interrupt_window_interception, |
6aa8b732 AK |
1356 | /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */ |
1357 | [SVM_EXIT_CPUID] = cpuid_interception, | |
cf5a94d1 | 1358 | [SVM_EXIT_INVD] = emulate_on_interception, |
6aa8b732 AK |
1359 | [SVM_EXIT_HLT] = halt_interception, |
1360 | [SVM_EXIT_INVLPG] = emulate_on_interception, | |
1361 | [SVM_EXIT_INVLPGA] = invalid_op_interception, | |
1362 | [SVM_EXIT_IOIO] = io_interception, | |
1363 | [SVM_EXIT_MSR] = msr_interception, | |
1364 | [SVM_EXIT_TASK_SWITCH] = task_switch_interception, | |
46fe4ddd | 1365 | [SVM_EXIT_SHUTDOWN] = shutdown_interception, |
6aa8b732 | 1366 | [SVM_EXIT_VMRUN] = invalid_op_interception, |
02e235bc | 1367 | [SVM_EXIT_VMMCALL] = vmmcall_interception, |
6aa8b732 AK |
1368 | [SVM_EXIT_VMLOAD] = invalid_op_interception, |
1369 | [SVM_EXIT_VMSAVE] = invalid_op_interception, | |
1370 | [SVM_EXIT_STGI] = invalid_op_interception, | |
1371 | [SVM_EXIT_CLGI] = invalid_op_interception, | |
1372 | [SVM_EXIT_SKINIT] = invalid_op_interception, | |
cf5a94d1 | 1373 | [SVM_EXIT_WBINVD] = emulate_on_interception, |
916ce236 JR |
1374 | [SVM_EXIT_MONITOR] = invalid_op_interception, |
1375 | [SVM_EXIT_MWAIT] = invalid_op_interception, | |
709ddebf | 1376 | [SVM_EXIT_NPF] = pf_interception, |
6aa8b732 AK |
1377 | }; |
1378 | ||
04d2cc77 | 1379 | static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu) |
6aa8b732 | 1380 | { |
04d2cc77 | 1381 | struct vcpu_svm *svm = to_svm(vcpu); |
a2fa3e9f | 1382 | u32 exit_code = svm->vmcb->control.exit_code; |
6aa8b732 | 1383 | |
709ddebf JR |
1384 | if (npt_enabled) { |
1385 | int mmu_reload = 0; | |
1386 | if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) { | |
1387 | svm_set_cr0(vcpu, svm->vmcb->save.cr0); | |
1388 | mmu_reload = 1; | |
1389 | } | |
1390 | vcpu->arch.cr0 = svm->vmcb->save.cr0; | |
1391 | vcpu->arch.cr3 = svm->vmcb->save.cr3; | |
1392 | if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) { | |
1393 | if (!load_pdptrs(vcpu, vcpu->arch.cr3)) { | |
1394 | kvm_inject_gp(vcpu, 0); | |
1395 | return 1; | |
1396 | } | |
1397 | } | |
1398 | if (mmu_reload) { | |
1399 | kvm_mmu_reset_context(vcpu); | |
1400 | kvm_mmu_load(vcpu); | |
1401 | } | |
1402 | } | |
1403 | ||
04d2cc77 AK |
1404 | kvm_reput_irq(svm); |
1405 | ||
1406 | if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) { | |
1407 | kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY; | |
1408 | kvm_run->fail_entry.hardware_entry_failure_reason | |
1409 | = svm->vmcb->control.exit_code; | |
1410 | return 0; | |
1411 | } | |
1412 | ||
a2fa3e9f | 1413 | if (is_external_interrupt(svm->vmcb->control.exit_int_info) && |
709ddebf JR |
1414 | exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR && |
1415 | exit_code != SVM_EXIT_NPF) | |
6aa8b732 AK |
1416 | printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x " |
1417 | "exit_code 0x%x\n", | |
b8688d51 | 1418 | __func__, svm->vmcb->control.exit_int_info, |
6aa8b732 AK |
1419 | exit_code); |
1420 | ||
9d8f549d | 1421 | if (exit_code >= ARRAY_SIZE(svm_exit_handlers) |
56919c5c | 1422 | || !svm_exit_handlers[exit_code]) { |
6aa8b732 | 1423 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; |
364b625b | 1424 | kvm_run->hw.hardware_exit_reason = exit_code; |
6aa8b732 AK |
1425 | return 0; |
1426 | } | |
1427 | ||
e756fc62 | 1428 | return svm_exit_handlers[exit_code](svm, kvm_run); |
6aa8b732 AK |
1429 | } |
1430 | ||
1431 | static void reload_tss(struct kvm_vcpu *vcpu) | |
1432 | { | |
1433 | int cpu = raw_smp_processor_id(); | |
1434 | ||
1435 | struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu); | |
d77c26fc | 1436 | svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */ |
6aa8b732 AK |
1437 | load_TR_desc(); |
1438 | } | |
1439 | ||
e756fc62 | 1440 | static void pre_svm_run(struct vcpu_svm *svm) |
6aa8b732 AK |
1441 | { |
1442 | int cpu = raw_smp_processor_id(); | |
1443 | ||
1444 | struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu); | |
1445 | ||
a2fa3e9f | 1446 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING; |
e756fc62 | 1447 | if (svm->vcpu.cpu != cpu || |
a2fa3e9f | 1448 | svm->asid_generation != svm_data->asid_generation) |
e756fc62 | 1449 | new_asid(svm, svm_data); |
6aa8b732 AK |
1450 | } |
1451 | ||
1452 | ||
85f455f7 | 1453 | static inline void svm_inject_irq(struct vcpu_svm *svm, int irq) |
6aa8b732 AK |
1454 | { |
1455 | struct vmcb_control_area *control; | |
1456 | ||
e756fc62 | 1457 | control = &svm->vmcb->control; |
85f455f7 | 1458 | control->int_vector = irq; |
6aa8b732 AK |
1459 | control->int_ctl &= ~V_INTR_PRIO_MASK; |
1460 | control->int_ctl |= V_IRQ_MASK | | |
1461 | ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT); | |
1462 | } | |
1463 | ||
2a8067f1 ED |
1464 | static void svm_set_irq(struct kvm_vcpu *vcpu, int irq) |
1465 | { | |
1466 | struct vcpu_svm *svm = to_svm(vcpu); | |
1467 | ||
1468 | svm_inject_irq(svm, irq); | |
1469 | } | |
1470 | ||
04d2cc77 | 1471 | static void svm_intr_assist(struct kvm_vcpu *vcpu) |
6aa8b732 | 1472 | { |
04d2cc77 | 1473 | struct vcpu_svm *svm = to_svm(vcpu); |
85f455f7 ED |
1474 | struct vmcb *vmcb = svm->vmcb; |
1475 | int intr_vector = -1; | |
1476 | ||
1477 | if ((vmcb->control.exit_int_info & SVM_EVTINJ_VALID) && | |
1478 | ((vmcb->control.exit_int_info & SVM_EVTINJ_TYPE_MASK) == 0)) { | |
1479 | intr_vector = vmcb->control.exit_int_info & | |
1480 | SVM_EVTINJ_VEC_MASK; | |
1481 | vmcb->control.exit_int_info = 0; | |
1482 | svm_inject_irq(svm, intr_vector); | |
1483 | return; | |
1484 | } | |
1485 | ||
1486 | if (vmcb->control.int_ctl & V_IRQ_MASK) | |
1487 | return; | |
1488 | ||
1b9778da | 1489 | if (!kvm_cpu_has_interrupt(vcpu)) |
85f455f7 ED |
1490 | return; |
1491 | ||
1492 | if (!(vmcb->save.rflags & X86_EFLAGS_IF) || | |
1493 | (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) || | |
1494 | (vmcb->control.event_inj & SVM_EVTINJ_VALID)) { | |
1495 | /* unable to deliver irq, set pending irq */ | |
1496 | vmcb->control.intercept |= (1ULL << INTERCEPT_VINTR); | |
1497 | svm_inject_irq(svm, 0x0); | |
1498 | return; | |
1499 | } | |
1500 | /* Okay, we can deliver the interrupt: grab it and update PIC state. */ | |
1b9778da | 1501 | intr_vector = kvm_cpu_get_interrupt(vcpu); |
85f455f7 | 1502 | svm_inject_irq(svm, intr_vector); |
1b9778da | 1503 | kvm_timer_intr_post(vcpu, intr_vector); |
85f455f7 ED |
1504 | } |
1505 | ||
1506 | static void kvm_reput_irq(struct vcpu_svm *svm) | |
1507 | { | |
e756fc62 | 1508 | struct vmcb_control_area *control = &svm->vmcb->control; |
6aa8b732 | 1509 | |
7017fc3d ED |
1510 | if ((control->int_ctl & V_IRQ_MASK) |
1511 | && !irqchip_in_kernel(svm->vcpu.kvm)) { | |
6aa8b732 | 1512 | control->int_ctl &= ~V_IRQ_MASK; |
e756fc62 | 1513 | push_irq(&svm->vcpu, control->int_vector); |
6aa8b732 | 1514 | } |
c1150d8c | 1515 | |
ad312c7c | 1516 | svm->vcpu.arch.interrupt_window_open = |
c1150d8c DL |
1517 | !(control->int_state & SVM_INTERRUPT_SHADOW_MASK); |
1518 | } | |
1519 | ||
85f455f7 ED |
1520 | static void svm_do_inject_vector(struct vcpu_svm *svm) |
1521 | { | |
1522 | struct kvm_vcpu *vcpu = &svm->vcpu; | |
ad312c7c ZX |
1523 | int word_index = __ffs(vcpu->arch.irq_summary); |
1524 | int bit_index = __ffs(vcpu->arch.irq_pending[word_index]); | |
85f455f7 ED |
1525 | int irq = word_index * BITS_PER_LONG + bit_index; |
1526 | ||
ad312c7c ZX |
1527 | clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]); |
1528 | if (!vcpu->arch.irq_pending[word_index]) | |
1529 | clear_bit(word_index, &vcpu->arch.irq_summary); | |
85f455f7 ED |
1530 | svm_inject_irq(svm, irq); |
1531 | } | |
1532 | ||
04d2cc77 | 1533 | static void do_interrupt_requests(struct kvm_vcpu *vcpu, |
c1150d8c DL |
1534 | struct kvm_run *kvm_run) |
1535 | { | |
04d2cc77 | 1536 | struct vcpu_svm *svm = to_svm(vcpu); |
a2fa3e9f | 1537 | struct vmcb_control_area *control = &svm->vmcb->control; |
c1150d8c | 1538 | |
ad312c7c | 1539 | svm->vcpu.arch.interrupt_window_open = |
c1150d8c | 1540 | (!(control->int_state & SVM_INTERRUPT_SHADOW_MASK) && |
a2fa3e9f | 1541 | (svm->vmcb->save.rflags & X86_EFLAGS_IF)); |
c1150d8c | 1542 | |
ad312c7c | 1543 | if (svm->vcpu.arch.interrupt_window_open && svm->vcpu.arch.irq_summary) |
c1150d8c DL |
1544 | /* |
1545 | * If interrupts enabled, and not blocked by sti or mov ss. Good. | |
1546 | */ | |
85f455f7 | 1547 | svm_do_inject_vector(svm); |
c1150d8c DL |
1548 | |
1549 | /* | |
1550 | * Interrupts blocked. Wait for unblock. | |
1551 | */ | |
ad312c7c ZX |
1552 | if (!svm->vcpu.arch.interrupt_window_open && |
1553 | (svm->vcpu.arch.irq_summary || kvm_run->request_interrupt_window)) | |
c1150d8c | 1554 | control->intercept |= 1ULL << INTERCEPT_VINTR; |
d77c26fc | 1555 | else |
c1150d8c DL |
1556 | control->intercept &= ~(1ULL << INTERCEPT_VINTR); |
1557 | } | |
1558 | ||
cbc94022 IE |
1559 | static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr) |
1560 | { | |
1561 | return 0; | |
1562 | } | |
1563 | ||
6aa8b732 AK |
1564 | static void save_db_regs(unsigned long *db_regs) |
1565 | { | |
5aff458e AK |
1566 | asm volatile ("mov %%dr0, %0" : "=r"(db_regs[0])); |
1567 | asm volatile ("mov %%dr1, %0" : "=r"(db_regs[1])); | |
1568 | asm volatile ("mov %%dr2, %0" : "=r"(db_regs[2])); | |
1569 | asm volatile ("mov %%dr3, %0" : "=r"(db_regs[3])); | |
6aa8b732 AK |
1570 | } |
1571 | ||
1572 | static void load_db_regs(unsigned long *db_regs) | |
1573 | { | |
5aff458e AK |
1574 | asm volatile ("mov %0, %%dr0" : : "r"(db_regs[0])); |
1575 | asm volatile ("mov %0, %%dr1" : : "r"(db_regs[1])); | |
1576 | asm volatile ("mov %0, %%dr2" : : "r"(db_regs[2])); | |
1577 | asm volatile ("mov %0, %%dr3" : : "r"(db_regs[3])); | |
6aa8b732 AK |
1578 | } |
1579 | ||
d9e368d6 AK |
1580 | static void svm_flush_tlb(struct kvm_vcpu *vcpu) |
1581 | { | |
1582 | force_new_asid(vcpu); | |
1583 | } | |
1584 | ||
04d2cc77 AK |
1585 | static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu) |
1586 | { | |
1587 | } | |
1588 | ||
1589 | static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
6aa8b732 | 1590 | { |
a2fa3e9f | 1591 | struct vcpu_svm *svm = to_svm(vcpu); |
6aa8b732 AK |
1592 | u16 fs_selector; |
1593 | u16 gs_selector; | |
1594 | u16 ldt_selector; | |
d9e368d6 | 1595 | |
e756fc62 | 1596 | pre_svm_run(svm); |
6aa8b732 AK |
1597 | |
1598 | save_host_msrs(vcpu); | |
1599 | fs_selector = read_fs(); | |
1600 | gs_selector = read_gs(); | |
1601 | ldt_selector = read_ldt(); | |
a2fa3e9f GH |
1602 | svm->host_cr2 = kvm_read_cr2(); |
1603 | svm->host_dr6 = read_dr6(); | |
1604 | svm->host_dr7 = read_dr7(); | |
ad312c7c | 1605 | svm->vmcb->save.cr2 = vcpu->arch.cr2; |
709ddebf JR |
1606 | /* required for live migration with NPT */ |
1607 | if (npt_enabled) | |
1608 | svm->vmcb->save.cr3 = vcpu->arch.cr3; | |
6aa8b732 | 1609 | |
a2fa3e9f | 1610 | if (svm->vmcb->save.dr7 & 0xff) { |
6aa8b732 | 1611 | write_dr7(0); |
a2fa3e9f GH |
1612 | save_db_regs(svm->host_db_regs); |
1613 | load_db_regs(svm->db_regs); | |
6aa8b732 | 1614 | } |
36241b8c | 1615 | |
04d2cc77 AK |
1616 | clgi(); |
1617 | ||
1618 | local_irq_enable(); | |
36241b8c | 1619 | |
6aa8b732 | 1620 | asm volatile ( |
05b3e0c2 | 1621 | #ifdef CONFIG_X86_64 |
54a08c04 | 1622 | "push %%rbp; \n\t" |
6aa8b732 | 1623 | #else |
fe7935d4 | 1624 | "push %%ebp; \n\t" |
6aa8b732 AK |
1625 | #endif |
1626 | ||
05b3e0c2 | 1627 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
1628 | "mov %c[rbx](%[svm]), %%rbx \n\t" |
1629 | "mov %c[rcx](%[svm]), %%rcx \n\t" | |
1630 | "mov %c[rdx](%[svm]), %%rdx \n\t" | |
1631 | "mov %c[rsi](%[svm]), %%rsi \n\t" | |
1632 | "mov %c[rdi](%[svm]), %%rdi \n\t" | |
1633 | "mov %c[rbp](%[svm]), %%rbp \n\t" | |
1634 | "mov %c[r8](%[svm]), %%r8 \n\t" | |
1635 | "mov %c[r9](%[svm]), %%r9 \n\t" | |
1636 | "mov %c[r10](%[svm]), %%r10 \n\t" | |
1637 | "mov %c[r11](%[svm]), %%r11 \n\t" | |
1638 | "mov %c[r12](%[svm]), %%r12 \n\t" | |
1639 | "mov %c[r13](%[svm]), %%r13 \n\t" | |
1640 | "mov %c[r14](%[svm]), %%r14 \n\t" | |
1641 | "mov %c[r15](%[svm]), %%r15 \n\t" | |
6aa8b732 | 1642 | #else |
fb3f0f51 RR |
1643 | "mov %c[rbx](%[svm]), %%ebx \n\t" |
1644 | "mov %c[rcx](%[svm]), %%ecx \n\t" | |
1645 | "mov %c[rdx](%[svm]), %%edx \n\t" | |
1646 | "mov %c[rsi](%[svm]), %%esi \n\t" | |
1647 | "mov %c[rdi](%[svm]), %%edi \n\t" | |
1648 | "mov %c[rbp](%[svm]), %%ebp \n\t" | |
6aa8b732 AK |
1649 | #endif |
1650 | ||
05b3e0c2 | 1651 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
1652 | /* Enter guest mode */ |
1653 | "push %%rax \n\t" | |
fb3f0f51 | 1654 | "mov %c[vmcb](%[svm]), %%rax \n\t" |
6aa8b732 AK |
1655 | SVM_VMLOAD "\n\t" |
1656 | SVM_VMRUN "\n\t" | |
1657 | SVM_VMSAVE "\n\t" | |
1658 | "pop %%rax \n\t" | |
1659 | #else | |
1660 | /* Enter guest mode */ | |
1661 | "push %%eax \n\t" | |
fb3f0f51 | 1662 | "mov %c[vmcb](%[svm]), %%eax \n\t" |
6aa8b732 AK |
1663 | SVM_VMLOAD "\n\t" |
1664 | SVM_VMRUN "\n\t" | |
1665 | SVM_VMSAVE "\n\t" | |
1666 | "pop %%eax \n\t" | |
1667 | #endif | |
1668 | ||
1669 | /* Save guest registers, load host registers */ | |
05b3e0c2 | 1670 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
1671 | "mov %%rbx, %c[rbx](%[svm]) \n\t" |
1672 | "mov %%rcx, %c[rcx](%[svm]) \n\t" | |
1673 | "mov %%rdx, %c[rdx](%[svm]) \n\t" | |
1674 | "mov %%rsi, %c[rsi](%[svm]) \n\t" | |
1675 | "mov %%rdi, %c[rdi](%[svm]) \n\t" | |
1676 | "mov %%rbp, %c[rbp](%[svm]) \n\t" | |
1677 | "mov %%r8, %c[r8](%[svm]) \n\t" | |
1678 | "mov %%r9, %c[r9](%[svm]) \n\t" | |
1679 | "mov %%r10, %c[r10](%[svm]) \n\t" | |
1680 | "mov %%r11, %c[r11](%[svm]) \n\t" | |
1681 | "mov %%r12, %c[r12](%[svm]) \n\t" | |
1682 | "mov %%r13, %c[r13](%[svm]) \n\t" | |
1683 | "mov %%r14, %c[r14](%[svm]) \n\t" | |
1684 | "mov %%r15, %c[r15](%[svm]) \n\t" | |
6aa8b732 | 1685 | |
54a08c04 | 1686 | "pop %%rbp; \n\t" |
6aa8b732 | 1687 | #else |
fb3f0f51 RR |
1688 | "mov %%ebx, %c[rbx](%[svm]) \n\t" |
1689 | "mov %%ecx, %c[rcx](%[svm]) \n\t" | |
1690 | "mov %%edx, %c[rdx](%[svm]) \n\t" | |
1691 | "mov %%esi, %c[rsi](%[svm]) \n\t" | |
1692 | "mov %%edi, %c[rdi](%[svm]) \n\t" | |
1693 | "mov %%ebp, %c[rbp](%[svm]) \n\t" | |
6aa8b732 | 1694 | |
fe7935d4 | 1695 | "pop %%ebp; \n\t" |
6aa8b732 AK |
1696 | #endif |
1697 | : | |
fb3f0f51 | 1698 | : [svm]"a"(svm), |
6aa8b732 | 1699 | [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)), |
ad312c7c ZX |
1700 | [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])), |
1701 | [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])), | |
1702 | [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])), | |
1703 | [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])), | |
1704 | [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])), | |
1705 | [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP])) | |
05b3e0c2 | 1706 | #ifdef CONFIG_X86_64 |
ad312c7c ZX |
1707 | , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])), |
1708 | [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])), | |
1709 | [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])), | |
1710 | [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])), | |
1711 | [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])), | |
1712 | [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])), | |
1713 | [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])), | |
1714 | [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15])) | |
6aa8b732 | 1715 | #endif |
54a08c04 LV |
1716 | : "cc", "memory" |
1717 | #ifdef CONFIG_X86_64 | |
1718 | , "rbx", "rcx", "rdx", "rsi", "rdi" | |
1719 | , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15" | |
fe7935d4 LV |
1720 | #else |
1721 | , "ebx", "ecx", "edx" , "esi", "edi" | |
54a08c04 LV |
1722 | #endif |
1723 | ); | |
6aa8b732 | 1724 | |
a2fa3e9f GH |
1725 | if ((svm->vmcb->save.dr7 & 0xff)) |
1726 | load_db_regs(svm->host_db_regs); | |
6aa8b732 | 1727 | |
ad312c7c | 1728 | vcpu->arch.cr2 = svm->vmcb->save.cr2; |
6aa8b732 | 1729 | |
a2fa3e9f GH |
1730 | write_dr6(svm->host_dr6); |
1731 | write_dr7(svm->host_dr7); | |
1732 | kvm_write_cr2(svm->host_cr2); | |
6aa8b732 AK |
1733 | |
1734 | load_fs(fs_selector); | |
1735 | load_gs(gs_selector); | |
1736 | load_ldt(ldt_selector); | |
1737 | load_host_msrs(vcpu); | |
1738 | ||
1739 | reload_tss(vcpu); | |
1740 | ||
56ba47dd AK |
1741 | local_irq_disable(); |
1742 | ||
1743 | stgi(); | |
1744 | ||
a2fa3e9f | 1745 | svm->next_rip = 0; |
6aa8b732 AK |
1746 | } |
1747 | ||
6aa8b732 AK |
1748 | static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root) |
1749 | { | |
a2fa3e9f GH |
1750 | struct vcpu_svm *svm = to_svm(vcpu); |
1751 | ||
709ddebf JR |
1752 | if (npt_enabled) { |
1753 | svm->vmcb->control.nested_cr3 = root; | |
1754 | force_new_asid(vcpu); | |
1755 | return; | |
1756 | } | |
1757 | ||
a2fa3e9f | 1758 | svm->vmcb->save.cr3 = root; |
6aa8b732 | 1759 | force_new_asid(vcpu); |
7807fa6c AL |
1760 | |
1761 | if (vcpu->fpu_active) { | |
a2fa3e9f GH |
1762 | svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR); |
1763 | svm->vmcb->save.cr0 |= X86_CR0_TS; | |
7807fa6c AL |
1764 | vcpu->fpu_active = 0; |
1765 | } | |
6aa8b732 AK |
1766 | } |
1767 | ||
6aa8b732 AK |
1768 | static int is_disabled(void) |
1769 | { | |
6031a61c JR |
1770 | u64 vm_cr; |
1771 | ||
1772 | rdmsrl(MSR_VM_CR, vm_cr); | |
1773 | if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE)) | |
1774 | return 1; | |
1775 | ||
6aa8b732 AK |
1776 | return 0; |
1777 | } | |
1778 | ||
102d8325 IM |
1779 | static void |
1780 | svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
1781 | { | |
1782 | /* | |
1783 | * Patch in the VMMCALL instruction: | |
1784 | */ | |
1785 | hypercall[0] = 0x0f; | |
1786 | hypercall[1] = 0x01; | |
1787 | hypercall[2] = 0xd9; | |
102d8325 IM |
1788 | } |
1789 | ||
002c7f7c YS |
1790 | static void svm_check_processor_compat(void *rtn) |
1791 | { | |
1792 | *(int *)rtn = 0; | |
1793 | } | |
1794 | ||
774ead3a AK |
1795 | static bool svm_cpu_has_accelerated_tpr(void) |
1796 | { | |
1797 | return false; | |
1798 | } | |
1799 | ||
cbdd1bea | 1800 | static struct kvm_x86_ops svm_x86_ops = { |
6aa8b732 AK |
1801 | .cpu_has_kvm_support = has_svm, |
1802 | .disabled_by_bios = is_disabled, | |
1803 | .hardware_setup = svm_hardware_setup, | |
1804 | .hardware_unsetup = svm_hardware_unsetup, | |
002c7f7c | 1805 | .check_processor_compatibility = svm_check_processor_compat, |
6aa8b732 AK |
1806 | .hardware_enable = svm_hardware_enable, |
1807 | .hardware_disable = svm_hardware_disable, | |
774ead3a | 1808 | .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr, |
6aa8b732 AK |
1809 | |
1810 | .vcpu_create = svm_create_vcpu, | |
1811 | .vcpu_free = svm_free_vcpu, | |
04d2cc77 | 1812 | .vcpu_reset = svm_vcpu_reset, |
6aa8b732 | 1813 | |
04d2cc77 | 1814 | .prepare_guest_switch = svm_prepare_guest_switch, |
6aa8b732 AK |
1815 | .vcpu_load = svm_vcpu_load, |
1816 | .vcpu_put = svm_vcpu_put, | |
774c47f1 | 1817 | .vcpu_decache = svm_vcpu_decache, |
6aa8b732 AK |
1818 | |
1819 | .set_guest_debug = svm_guest_debug, | |
1820 | .get_msr = svm_get_msr, | |
1821 | .set_msr = svm_set_msr, | |
1822 | .get_segment_base = svm_get_segment_base, | |
1823 | .get_segment = svm_get_segment, | |
1824 | .set_segment = svm_set_segment, | |
1747fb71 | 1825 | .get_cs_db_l_bits = kvm_get_cs_db_l_bits, |
25c4c276 | 1826 | .decache_cr4_guest_bits = svm_decache_cr4_guest_bits, |
6aa8b732 | 1827 | .set_cr0 = svm_set_cr0, |
6aa8b732 AK |
1828 | .set_cr3 = svm_set_cr3, |
1829 | .set_cr4 = svm_set_cr4, | |
1830 | .set_efer = svm_set_efer, | |
1831 | .get_idt = svm_get_idt, | |
1832 | .set_idt = svm_set_idt, | |
1833 | .get_gdt = svm_get_gdt, | |
1834 | .set_gdt = svm_set_gdt, | |
1835 | .get_dr = svm_get_dr, | |
1836 | .set_dr = svm_set_dr, | |
1837 | .cache_regs = svm_cache_regs, | |
1838 | .decache_regs = svm_decache_regs, | |
1839 | .get_rflags = svm_get_rflags, | |
1840 | .set_rflags = svm_set_rflags, | |
1841 | ||
6aa8b732 | 1842 | .tlb_flush = svm_flush_tlb, |
6aa8b732 | 1843 | |
6aa8b732 | 1844 | .run = svm_vcpu_run, |
04d2cc77 | 1845 | .handle_exit = handle_exit, |
6aa8b732 | 1846 | .skip_emulated_instruction = skip_emulated_instruction, |
102d8325 | 1847 | .patch_hypercall = svm_patch_hypercall, |
2a8067f1 ED |
1848 | .get_irq = svm_get_irq, |
1849 | .set_irq = svm_set_irq, | |
298101da AK |
1850 | .queue_exception = svm_queue_exception, |
1851 | .exception_injected = svm_exception_injected, | |
04d2cc77 AK |
1852 | .inject_pending_irq = svm_intr_assist, |
1853 | .inject_pending_vectors = do_interrupt_requests, | |
cbc94022 IE |
1854 | |
1855 | .set_tss_addr = svm_set_tss_addr, | |
6aa8b732 AK |
1856 | }; |
1857 | ||
1858 | static int __init svm_init(void) | |
1859 | { | |
cb498ea2 | 1860 | return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm), |
c16f862d | 1861 | THIS_MODULE); |
6aa8b732 AK |
1862 | } |
1863 | ||
1864 | static void __exit svm_exit(void) | |
1865 | { | |
cb498ea2 | 1866 | kvm_exit(); |
6aa8b732 AK |
1867 | } |
1868 | ||
1869 | module_init(svm_init) | |
1870 | module_exit(svm_exit) |