Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * AMD SVM support | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
7 | * | |
8 | * Authors: | |
9 | * Yaniv Kamay <yaniv@qumranet.com> | |
10 | * Avi Kivity <avi@qumranet.com> | |
11 | * | |
12 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
13 | * the COPYING file in the top-level directory. | |
14 | * | |
15 | */ | |
edf88417 AK |
16 | #include <linux/kvm_host.h> |
17 | ||
e495606d | 18 | #include "kvm_svm.h" |
85f455f7 | 19 | #include "irq.h" |
1d737c8a | 20 | #include "mmu.h" |
e495606d | 21 | |
6aa8b732 | 22 | #include <linux/module.h> |
9d8f549d | 23 | #include <linux/kernel.h> |
6aa8b732 AK |
24 | #include <linux/vmalloc.h> |
25 | #include <linux/highmem.h> | |
e8edc6e0 | 26 | #include <linux/sched.h> |
6aa8b732 | 27 | |
e495606d | 28 | #include <asm/desc.h> |
6aa8b732 AK |
29 | |
30 | MODULE_AUTHOR("Qumranet"); | |
31 | MODULE_LICENSE("GPL"); | |
32 | ||
33 | #define IOPM_ALLOC_ORDER 2 | |
34 | #define MSRPM_ALLOC_ORDER 1 | |
35 | ||
36 | #define DB_VECTOR 1 | |
37 | #define UD_VECTOR 6 | |
38 | #define GP_VECTOR 13 | |
39 | ||
40 | #define DR7_GD_MASK (1 << 13) | |
41 | #define DR6_BD_MASK (1 << 13) | |
6aa8b732 AK |
42 | |
43 | #define SEG_TYPE_LDT 2 | |
44 | #define SEG_TYPE_BUSY_TSS16 3 | |
45 | ||
80b7706e JR |
46 | #define SVM_FEATURE_NPT (1 << 0) |
47 | #define SVM_FEATURE_LBRV (1 << 1) | |
48 | #define SVM_DEATURE_SVML (1 << 2) | |
49 | ||
04d2cc77 AK |
50 | static void kvm_reput_irq(struct vcpu_svm *svm); |
51 | ||
a2fa3e9f GH |
52 | static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu) |
53 | { | |
fb3f0f51 | 54 | return container_of(vcpu, struct vcpu_svm, vcpu); |
a2fa3e9f GH |
55 | } |
56 | ||
6aa8b732 AK |
57 | unsigned long iopm_base; |
58 | unsigned long msrpm_base; | |
59 | ||
60 | struct kvm_ldttss_desc { | |
61 | u16 limit0; | |
62 | u16 base0; | |
63 | unsigned base1 : 8, type : 5, dpl : 2, p : 1; | |
64 | unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8; | |
65 | u32 base3; | |
66 | u32 zero1; | |
67 | } __attribute__((packed)); | |
68 | ||
69 | struct svm_cpu_data { | |
70 | int cpu; | |
71 | ||
5008fdf5 AK |
72 | u64 asid_generation; |
73 | u32 max_asid; | |
74 | u32 next_asid; | |
6aa8b732 AK |
75 | struct kvm_ldttss_desc *tss_desc; |
76 | ||
77 | struct page *save_area; | |
78 | }; | |
79 | ||
80 | static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data); | |
80b7706e | 81 | static uint32_t svm_features; |
6aa8b732 AK |
82 | |
83 | struct svm_init_data { | |
84 | int cpu; | |
85 | int r; | |
86 | }; | |
87 | ||
88 | static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000}; | |
89 | ||
9d8f549d | 90 | #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges) |
6aa8b732 AK |
91 | #define MSRS_RANGE_SIZE 2048 |
92 | #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2) | |
93 | ||
94 | #define MAX_INST_SIZE 15 | |
95 | ||
80b7706e JR |
96 | static inline u32 svm_has(u32 feat) |
97 | { | |
98 | return svm_features & feat; | |
99 | } | |
100 | ||
6aa8b732 AK |
101 | static inline u8 pop_irq(struct kvm_vcpu *vcpu) |
102 | { | |
ad312c7c ZX |
103 | int word_index = __ffs(vcpu->arch.irq_summary); |
104 | int bit_index = __ffs(vcpu->arch.irq_pending[word_index]); | |
6aa8b732 AK |
105 | int irq = word_index * BITS_PER_LONG + bit_index; |
106 | ||
ad312c7c ZX |
107 | clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]); |
108 | if (!vcpu->arch.irq_pending[word_index]) | |
109 | clear_bit(word_index, &vcpu->arch.irq_summary); | |
6aa8b732 AK |
110 | return irq; |
111 | } | |
112 | ||
113 | static inline void push_irq(struct kvm_vcpu *vcpu, u8 irq) | |
114 | { | |
ad312c7c ZX |
115 | set_bit(irq, vcpu->arch.irq_pending); |
116 | set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary); | |
6aa8b732 AK |
117 | } |
118 | ||
119 | static inline void clgi(void) | |
120 | { | |
121 | asm volatile (SVM_CLGI); | |
122 | } | |
123 | ||
124 | static inline void stgi(void) | |
125 | { | |
126 | asm volatile (SVM_STGI); | |
127 | } | |
128 | ||
129 | static inline void invlpga(unsigned long addr, u32 asid) | |
130 | { | |
131 | asm volatile (SVM_INVLPGA :: "a"(addr), "c"(asid)); | |
132 | } | |
133 | ||
134 | static inline unsigned long kvm_read_cr2(void) | |
135 | { | |
136 | unsigned long cr2; | |
137 | ||
138 | asm volatile ("mov %%cr2, %0" : "=r" (cr2)); | |
139 | return cr2; | |
140 | } | |
141 | ||
142 | static inline void kvm_write_cr2(unsigned long val) | |
143 | { | |
144 | asm volatile ("mov %0, %%cr2" :: "r" (val)); | |
145 | } | |
146 | ||
147 | static inline unsigned long read_dr6(void) | |
148 | { | |
149 | unsigned long dr6; | |
150 | ||
151 | asm volatile ("mov %%dr6, %0" : "=r" (dr6)); | |
152 | return dr6; | |
153 | } | |
154 | ||
155 | static inline void write_dr6(unsigned long val) | |
156 | { | |
157 | asm volatile ("mov %0, %%dr6" :: "r" (val)); | |
158 | } | |
159 | ||
160 | static inline unsigned long read_dr7(void) | |
161 | { | |
162 | unsigned long dr7; | |
163 | ||
164 | asm volatile ("mov %%dr7, %0" : "=r" (dr7)); | |
165 | return dr7; | |
166 | } | |
167 | ||
168 | static inline void write_dr7(unsigned long val) | |
169 | { | |
170 | asm volatile ("mov %0, %%dr7" :: "r" (val)); | |
171 | } | |
172 | ||
6aa8b732 AK |
173 | static inline void force_new_asid(struct kvm_vcpu *vcpu) |
174 | { | |
a2fa3e9f | 175 | to_svm(vcpu)->asid_generation--; |
6aa8b732 AK |
176 | } |
177 | ||
178 | static inline void flush_guest_tlb(struct kvm_vcpu *vcpu) | |
179 | { | |
180 | force_new_asid(vcpu); | |
181 | } | |
182 | ||
183 | static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer) | |
184 | { | |
2b5203ee CMAB |
185 | if (!(efer & EFER_LMA)) |
186 | efer &= ~EFER_LME; | |
6aa8b732 | 187 | |
a2fa3e9f | 188 | to_svm(vcpu)->vmcb->save.efer = efer | MSR_EFER_SVME_MASK; |
ad312c7c | 189 | vcpu->arch.shadow_efer = efer; |
6aa8b732 AK |
190 | } |
191 | ||
298101da AK |
192 | static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr, |
193 | bool has_error_code, u32 error_code) | |
194 | { | |
195 | struct vcpu_svm *svm = to_svm(vcpu); | |
196 | ||
197 | svm->vmcb->control.event_inj = nr | |
198 | | SVM_EVTINJ_VALID | |
199 | | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0) | |
200 | | SVM_EVTINJ_TYPE_EXEPT; | |
201 | svm->vmcb->control.event_inj_err = error_code; | |
202 | } | |
203 | ||
204 | static bool svm_exception_injected(struct kvm_vcpu *vcpu) | |
205 | { | |
206 | struct vcpu_svm *svm = to_svm(vcpu); | |
207 | ||
208 | return !(svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID); | |
209 | } | |
210 | ||
6aa8b732 AK |
211 | static int is_external_interrupt(u32 info) |
212 | { | |
213 | info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID; | |
214 | return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR); | |
215 | } | |
216 | ||
217 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) | |
218 | { | |
a2fa3e9f GH |
219 | struct vcpu_svm *svm = to_svm(vcpu); |
220 | ||
221 | if (!svm->next_rip) { | |
6aa8b732 AK |
222 | printk(KERN_DEBUG "%s: NOP\n", __FUNCTION__); |
223 | return; | |
224 | } | |
d77c26fc | 225 | if (svm->next_rip - svm->vmcb->save.rip > MAX_INST_SIZE) |
6aa8b732 AK |
226 | printk(KERN_ERR "%s: ip 0x%llx next 0x%llx\n", |
227 | __FUNCTION__, | |
a2fa3e9f GH |
228 | svm->vmcb->save.rip, |
229 | svm->next_rip); | |
6aa8b732 | 230 | |
ad312c7c | 231 | vcpu->arch.rip = svm->vmcb->save.rip = svm->next_rip; |
a2fa3e9f | 232 | svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK; |
c1150d8c | 233 | |
ad312c7c | 234 | vcpu->arch.interrupt_window_open = 1; |
6aa8b732 AK |
235 | } |
236 | ||
237 | static int has_svm(void) | |
238 | { | |
239 | uint32_t eax, ebx, ecx, edx; | |
240 | ||
1e885461 | 241 | if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) { |
6aa8b732 AK |
242 | printk(KERN_INFO "has_svm: not amd\n"); |
243 | return 0; | |
244 | } | |
245 | ||
246 | cpuid(0x80000000, &eax, &ebx, &ecx, &edx); | |
247 | if (eax < SVM_CPUID_FUNC) { | |
248 | printk(KERN_INFO "has_svm: can't execute cpuid_8000000a\n"); | |
249 | return 0; | |
250 | } | |
251 | ||
252 | cpuid(0x80000001, &eax, &ebx, &ecx, &edx); | |
253 | if (!(ecx & (1 << SVM_CPUID_FEATURE_SHIFT))) { | |
254 | printk(KERN_DEBUG "has_svm: svm not available\n"); | |
255 | return 0; | |
256 | } | |
257 | return 1; | |
258 | } | |
259 | ||
260 | static void svm_hardware_disable(void *garbage) | |
261 | { | |
262 | struct svm_cpu_data *svm_data | |
263 | = per_cpu(svm_data, raw_smp_processor_id()); | |
264 | ||
265 | if (svm_data) { | |
266 | uint64_t efer; | |
267 | ||
268 | wrmsrl(MSR_VM_HSAVE_PA, 0); | |
269 | rdmsrl(MSR_EFER, efer); | |
270 | wrmsrl(MSR_EFER, efer & ~MSR_EFER_SVME_MASK); | |
8b6d44c7 | 271 | per_cpu(svm_data, raw_smp_processor_id()) = NULL; |
6aa8b732 AK |
272 | __free_page(svm_data->save_area); |
273 | kfree(svm_data); | |
274 | } | |
275 | } | |
276 | ||
277 | static void svm_hardware_enable(void *garbage) | |
278 | { | |
279 | ||
280 | struct svm_cpu_data *svm_data; | |
281 | uint64_t efer; | |
05b3e0c2 | 282 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
283 | struct desc_ptr gdt_descr; |
284 | #else | |
6b68f01b | 285 | struct desc_ptr gdt_descr; |
6aa8b732 AK |
286 | #endif |
287 | struct desc_struct *gdt; | |
288 | int me = raw_smp_processor_id(); | |
289 | ||
290 | if (!has_svm()) { | |
291 | printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me); | |
292 | return; | |
293 | } | |
294 | svm_data = per_cpu(svm_data, me); | |
295 | ||
296 | if (!svm_data) { | |
297 | printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n", | |
298 | me); | |
299 | return; | |
300 | } | |
301 | ||
302 | svm_data->asid_generation = 1; | |
303 | svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1; | |
304 | svm_data->next_asid = svm_data->max_asid + 1; | |
80b7706e | 305 | svm_features = cpuid_edx(SVM_CPUID_FUNC); |
6aa8b732 | 306 | |
d77c26fc | 307 | asm volatile ("sgdt %0" : "=m"(gdt_descr)); |
6aa8b732 AK |
308 | gdt = (struct desc_struct *)gdt_descr.address; |
309 | svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS); | |
310 | ||
311 | rdmsrl(MSR_EFER, efer); | |
312 | wrmsrl(MSR_EFER, efer | MSR_EFER_SVME_MASK); | |
313 | ||
314 | wrmsrl(MSR_VM_HSAVE_PA, | |
315 | page_to_pfn(svm_data->save_area) << PAGE_SHIFT); | |
316 | } | |
317 | ||
318 | static int svm_cpu_init(int cpu) | |
319 | { | |
320 | struct svm_cpu_data *svm_data; | |
321 | int r; | |
322 | ||
323 | svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL); | |
324 | if (!svm_data) | |
325 | return -ENOMEM; | |
326 | svm_data->cpu = cpu; | |
327 | svm_data->save_area = alloc_page(GFP_KERNEL); | |
328 | r = -ENOMEM; | |
329 | if (!svm_data->save_area) | |
330 | goto err_1; | |
331 | ||
332 | per_cpu(svm_data, cpu) = svm_data; | |
333 | ||
334 | return 0; | |
335 | ||
336 | err_1: | |
337 | kfree(svm_data); | |
338 | return r; | |
339 | ||
340 | } | |
341 | ||
bfc733a7 RR |
342 | static void set_msr_interception(u32 *msrpm, unsigned msr, |
343 | int read, int write) | |
6aa8b732 AK |
344 | { |
345 | int i; | |
346 | ||
347 | for (i = 0; i < NUM_MSR_MAPS; i++) { | |
348 | if (msr >= msrpm_ranges[i] && | |
349 | msr < msrpm_ranges[i] + MSRS_IN_RANGE) { | |
350 | u32 msr_offset = (i * MSRS_IN_RANGE + msr - | |
351 | msrpm_ranges[i]) * 2; | |
352 | ||
353 | u32 *base = msrpm + (msr_offset / 32); | |
354 | u32 msr_shift = msr_offset % 32; | |
355 | u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1); | |
356 | *base = (*base & ~(0x3 << msr_shift)) | | |
357 | (mask << msr_shift); | |
bfc733a7 | 358 | return; |
6aa8b732 AK |
359 | } |
360 | } | |
bfc733a7 | 361 | BUG(); |
6aa8b732 AK |
362 | } |
363 | ||
364 | static __init int svm_hardware_setup(void) | |
365 | { | |
366 | int cpu; | |
367 | struct page *iopm_pages; | |
368 | struct page *msrpm_pages; | |
c8681339 | 369 | void *iopm_va, *msrpm_va; |
6aa8b732 AK |
370 | int r; |
371 | ||
6aa8b732 AK |
372 | iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER); |
373 | ||
374 | if (!iopm_pages) | |
375 | return -ENOMEM; | |
c8681339 AL |
376 | |
377 | iopm_va = page_address(iopm_pages); | |
378 | memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER)); | |
379 | clear_bit(0x80, iopm_va); /* allow direct access to PC debug port */ | |
6aa8b732 AK |
380 | iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT; |
381 | ||
382 | ||
383 | msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); | |
384 | ||
385 | r = -ENOMEM; | |
386 | if (!msrpm_pages) | |
387 | goto err_1; | |
388 | ||
389 | msrpm_va = page_address(msrpm_pages); | |
390 | memset(msrpm_va, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER)); | |
391 | msrpm_base = page_to_pfn(msrpm_pages) << PAGE_SHIFT; | |
392 | ||
05b3e0c2 | 393 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
394 | set_msr_interception(msrpm_va, MSR_GS_BASE, 1, 1); |
395 | set_msr_interception(msrpm_va, MSR_FS_BASE, 1, 1); | |
396 | set_msr_interception(msrpm_va, MSR_KERNEL_GS_BASE, 1, 1); | |
6aa8b732 AK |
397 | set_msr_interception(msrpm_va, MSR_LSTAR, 1, 1); |
398 | set_msr_interception(msrpm_va, MSR_CSTAR, 1, 1); | |
399 | set_msr_interception(msrpm_va, MSR_SYSCALL_MASK, 1, 1); | |
400 | #endif | |
0e859cac | 401 | set_msr_interception(msrpm_va, MSR_K6_STAR, 1, 1); |
6aa8b732 AK |
402 | set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_CS, 1, 1); |
403 | set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_ESP, 1, 1); | |
404 | set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_EIP, 1, 1); | |
405 | ||
406 | for_each_online_cpu(cpu) { | |
407 | r = svm_cpu_init(cpu); | |
408 | if (r) | |
409 | goto err_2; | |
410 | } | |
411 | return 0; | |
412 | ||
413 | err_2: | |
414 | __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER); | |
415 | msrpm_base = 0; | |
416 | err_1: | |
417 | __free_pages(iopm_pages, IOPM_ALLOC_ORDER); | |
418 | iopm_base = 0; | |
419 | return r; | |
420 | } | |
421 | ||
422 | static __exit void svm_hardware_unsetup(void) | |
423 | { | |
424 | __free_pages(pfn_to_page(msrpm_base >> PAGE_SHIFT), MSRPM_ALLOC_ORDER); | |
425 | __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER); | |
426 | iopm_base = msrpm_base = 0; | |
427 | } | |
428 | ||
429 | static void init_seg(struct vmcb_seg *seg) | |
430 | { | |
431 | seg->selector = 0; | |
432 | seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK | | |
433 | SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */ | |
434 | seg->limit = 0xffff; | |
435 | seg->base = 0; | |
436 | } | |
437 | ||
438 | static void init_sys_seg(struct vmcb_seg *seg, uint32_t type) | |
439 | { | |
440 | seg->selector = 0; | |
441 | seg->attrib = SVM_SELECTOR_P_MASK | type; | |
442 | seg->limit = 0xffff; | |
443 | seg->base = 0; | |
444 | } | |
445 | ||
6aa8b732 AK |
446 | static void init_vmcb(struct vmcb *vmcb) |
447 | { | |
448 | struct vmcb_control_area *control = &vmcb->control; | |
449 | struct vmcb_save_area *save = &vmcb->save; | |
6aa8b732 AK |
450 | |
451 | control->intercept_cr_read = INTERCEPT_CR0_MASK | | |
452 | INTERCEPT_CR3_MASK | | |
80a8119c AK |
453 | INTERCEPT_CR4_MASK | |
454 | INTERCEPT_CR8_MASK; | |
6aa8b732 AK |
455 | |
456 | control->intercept_cr_write = INTERCEPT_CR0_MASK | | |
457 | INTERCEPT_CR3_MASK | | |
80a8119c AK |
458 | INTERCEPT_CR4_MASK | |
459 | INTERCEPT_CR8_MASK; | |
6aa8b732 AK |
460 | |
461 | control->intercept_dr_read = INTERCEPT_DR0_MASK | | |
462 | INTERCEPT_DR1_MASK | | |
463 | INTERCEPT_DR2_MASK | | |
464 | INTERCEPT_DR3_MASK; | |
465 | ||
466 | control->intercept_dr_write = INTERCEPT_DR0_MASK | | |
467 | INTERCEPT_DR1_MASK | | |
468 | INTERCEPT_DR2_MASK | | |
469 | INTERCEPT_DR3_MASK | | |
470 | INTERCEPT_DR5_MASK | | |
471 | INTERCEPT_DR7_MASK; | |
472 | ||
7aa81cc0 AL |
473 | control->intercept_exceptions = (1 << PF_VECTOR) | |
474 | (1 << UD_VECTOR); | |
6aa8b732 AK |
475 | |
476 | ||
477 | control->intercept = (1ULL << INTERCEPT_INTR) | | |
478 | (1ULL << INTERCEPT_NMI) | | |
0152527b | 479 | (1ULL << INTERCEPT_SMI) | |
6aa8b732 AK |
480 | /* |
481 | * selective cr0 intercept bug? | |
482 | * 0: 0f 22 d8 mov %eax,%cr3 | |
483 | * 3: 0f 20 c0 mov %cr0,%eax | |
484 | * 6: 0d 00 00 00 80 or $0x80000000,%eax | |
485 | * b: 0f 22 c0 mov %eax,%cr0 | |
486 | * set cr3 ->interception | |
487 | * get cr0 ->interception | |
488 | * set cr0 -> no interception | |
489 | */ | |
490 | /* (1ULL << INTERCEPT_SELECTIVE_CR0) | */ | |
491 | (1ULL << INTERCEPT_CPUID) | | |
cf5a94d1 | 492 | (1ULL << INTERCEPT_INVD) | |
6aa8b732 | 493 | (1ULL << INTERCEPT_HLT) | |
6aa8b732 AK |
494 | (1ULL << INTERCEPT_INVLPGA) | |
495 | (1ULL << INTERCEPT_IOIO_PROT) | | |
496 | (1ULL << INTERCEPT_MSR_PROT) | | |
497 | (1ULL << INTERCEPT_TASK_SWITCH) | | |
46fe4ddd | 498 | (1ULL << INTERCEPT_SHUTDOWN) | |
6aa8b732 AK |
499 | (1ULL << INTERCEPT_VMRUN) | |
500 | (1ULL << INTERCEPT_VMMCALL) | | |
501 | (1ULL << INTERCEPT_VMLOAD) | | |
502 | (1ULL << INTERCEPT_VMSAVE) | | |
503 | (1ULL << INTERCEPT_STGI) | | |
504 | (1ULL << INTERCEPT_CLGI) | | |
916ce236 | 505 | (1ULL << INTERCEPT_SKINIT) | |
cf5a94d1 | 506 | (1ULL << INTERCEPT_WBINVD) | |
916ce236 JR |
507 | (1ULL << INTERCEPT_MONITOR) | |
508 | (1ULL << INTERCEPT_MWAIT); | |
6aa8b732 AK |
509 | |
510 | control->iopm_base_pa = iopm_base; | |
511 | control->msrpm_base_pa = msrpm_base; | |
0cc5064d | 512 | control->tsc_offset = 0; |
6aa8b732 AK |
513 | control->int_ctl = V_INTR_MASKING_MASK; |
514 | ||
515 | init_seg(&save->es); | |
516 | init_seg(&save->ss); | |
517 | init_seg(&save->ds); | |
518 | init_seg(&save->fs); | |
519 | init_seg(&save->gs); | |
520 | ||
521 | save->cs.selector = 0xf000; | |
522 | /* Executable/Readable Code Segment */ | |
523 | save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK | | |
524 | SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK; | |
525 | save->cs.limit = 0xffff; | |
d92899a0 AK |
526 | /* |
527 | * cs.base should really be 0xffff0000, but vmx can't handle that, so | |
528 | * be consistent with it. | |
529 | * | |
530 | * Replace when we have real mode working for vmx. | |
531 | */ | |
532 | save->cs.base = 0xf0000; | |
6aa8b732 AK |
533 | |
534 | save->gdtr.limit = 0xffff; | |
535 | save->idtr.limit = 0xffff; | |
536 | ||
537 | init_sys_seg(&save->ldtr, SEG_TYPE_LDT); | |
538 | init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16); | |
539 | ||
540 | save->efer = MSR_EFER_SVME_MASK; | |
d77c26fc | 541 | save->dr6 = 0xffff0ff0; |
6aa8b732 AK |
542 | save->dr7 = 0x400; |
543 | save->rflags = 2; | |
544 | save->rip = 0x0000fff0; | |
545 | ||
546 | /* | |
547 | * cr0 val on cpu init should be 0x60000010, we enable cpu | |
548 | * cache by default. the orderly way is to enable cache in bios. | |
549 | */ | |
707d92fa | 550 | save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP; |
66aee91a | 551 | save->cr4 = X86_CR4_PAE; |
6aa8b732 AK |
552 | /* rdx = ?? */ |
553 | } | |
554 | ||
e00c8cf2 | 555 | static int svm_vcpu_reset(struct kvm_vcpu *vcpu) |
04d2cc77 AK |
556 | { |
557 | struct vcpu_svm *svm = to_svm(vcpu); | |
558 | ||
559 | init_vmcb(svm->vmcb); | |
70433389 AK |
560 | |
561 | if (vcpu->vcpu_id != 0) { | |
562 | svm->vmcb->save.rip = 0; | |
ad312c7c ZX |
563 | svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12; |
564 | svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8; | |
70433389 | 565 | } |
e00c8cf2 AK |
566 | |
567 | return 0; | |
04d2cc77 AK |
568 | } |
569 | ||
fb3f0f51 | 570 | static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 571 | { |
a2fa3e9f | 572 | struct vcpu_svm *svm; |
6aa8b732 | 573 | struct page *page; |
fb3f0f51 | 574 | int err; |
6aa8b732 | 575 | |
c16f862d | 576 | svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); |
fb3f0f51 RR |
577 | if (!svm) { |
578 | err = -ENOMEM; | |
579 | goto out; | |
580 | } | |
581 | ||
582 | err = kvm_vcpu_init(&svm->vcpu, kvm, id); | |
583 | if (err) | |
584 | goto free_svm; | |
585 | ||
6aa8b732 | 586 | page = alloc_page(GFP_KERNEL); |
fb3f0f51 RR |
587 | if (!page) { |
588 | err = -ENOMEM; | |
589 | goto uninit; | |
590 | } | |
6aa8b732 | 591 | |
a2fa3e9f GH |
592 | svm->vmcb = page_address(page); |
593 | clear_page(svm->vmcb); | |
594 | svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT; | |
595 | svm->asid_generation = 0; | |
596 | memset(svm->db_regs, 0, sizeof(svm->db_regs)); | |
597 | init_vmcb(svm->vmcb); | |
598 | ||
fb3f0f51 RR |
599 | fx_init(&svm->vcpu); |
600 | svm->vcpu.fpu_active = 1; | |
ad312c7c | 601 | svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE; |
fb3f0f51 | 602 | if (svm->vcpu.vcpu_id == 0) |
ad312c7c | 603 | svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP; |
6aa8b732 | 604 | |
fb3f0f51 | 605 | return &svm->vcpu; |
36241b8c | 606 | |
fb3f0f51 RR |
607 | uninit: |
608 | kvm_vcpu_uninit(&svm->vcpu); | |
609 | free_svm: | |
a4770347 | 610 | kmem_cache_free(kvm_vcpu_cache, svm); |
fb3f0f51 RR |
611 | out: |
612 | return ERR_PTR(err); | |
6aa8b732 AK |
613 | } |
614 | ||
615 | static void svm_free_vcpu(struct kvm_vcpu *vcpu) | |
616 | { | |
a2fa3e9f GH |
617 | struct vcpu_svm *svm = to_svm(vcpu); |
618 | ||
fb3f0f51 RR |
619 | __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT)); |
620 | kvm_vcpu_uninit(vcpu); | |
a4770347 | 621 | kmem_cache_free(kvm_vcpu_cache, svm); |
6aa8b732 AK |
622 | } |
623 | ||
15ad7146 | 624 | static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 625 | { |
a2fa3e9f | 626 | struct vcpu_svm *svm = to_svm(vcpu); |
15ad7146 | 627 | int i; |
0cc5064d | 628 | |
0cc5064d AK |
629 | if (unlikely(cpu != vcpu->cpu)) { |
630 | u64 tsc_this, delta; | |
631 | ||
632 | /* | |
633 | * Make sure that the guest sees a monotonically | |
634 | * increasing TSC. | |
635 | */ | |
636 | rdtscll(tsc_this); | |
ad312c7c | 637 | delta = vcpu->arch.host_tsc - tsc_this; |
a2fa3e9f | 638 | svm->vmcb->control.tsc_offset += delta; |
0cc5064d | 639 | vcpu->cpu = cpu; |
a3d7f85f | 640 | kvm_migrate_apic_timer(vcpu); |
0cc5064d | 641 | } |
94dfbdb3 AL |
642 | |
643 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) | |
a2fa3e9f | 644 | rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
6aa8b732 AK |
645 | } |
646 | ||
647 | static void svm_vcpu_put(struct kvm_vcpu *vcpu) | |
648 | { | |
a2fa3e9f | 649 | struct vcpu_svm *svm = to_svm(vcpu); |
94dfbdb3 AL |
650 | int i; |
651 | ||
e1beb1d3 | 652 | ++vcpu->stat.host_state_reload; |
94dfbdb3 | 653 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) |
a2fa3e9f | 654 | wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
94dfbdb3 | 655 | |
ad312c7c | 656 | rdtscll(vcpu->arch.host_tsc); |
6aa8b732 AK |
657 | } |
658 | ||
774c47f1 AK |
659 | static void svm_vcpu_decache(struct kvm_vcpu *vcpu) |
660 | { | |
661 | } | |
662 | ||
6aa8b732 AK |
663 | static void svm_cache_regs(struct kvm_vcpu *vcpu) |
664 | { | |
a2fa3e9f GH |
665 | struct vcpu_svm *svm = to_svm(vcpu); |
666 | ||
ad312c7c ZX |
667 | vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax; |
668 | vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp; | |
669 | vcpu->arch.rip = svm->vmcb->save.rip; | |
6aa8b732 AK |
670 | } |
671 | ||
672 | static void svm_decache_regs(struct kvm_vcpu *vcpu) | |
673 | { | |
a2fa3e9f | 674 | struct vcpu_svm *svm = to_svm(vcpu); |
ad312c7c ZX |
675 | svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX]; |
676 | svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP]; | |
677 | svm->vmcb->save.rip = vcpu->arch.rip; | |
6aa8b732 AK |
678 | } |
679 | ||
680 | static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu) | |
681 | { | |
a2fa3e9f | 682 | return to_svm(vcpu)->vmcb->save.rflags; |
6aa8b732 AK |
683 | } |
684 | ||
685 | static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
686 | { | |
a2fa3e9f | 687 | to_svm(vcpu)->vmcb->save.rflags = rflags; |
6aa8b732 AK |
688 | } |
689 | ||
690 | static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg) | |
691 | { | |
a2fa3e9f | 692 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; |
6aa8b732 AK |
693 | |
694 | switch (seg) { | |
695 | case VCPU_SREG_CS: return &save->cs; | |
696 | case VCPU_SREG_DS: return &save->ds; | |
697 | case VCPU_SREG_ES: return &save->es; | |
698 | case VCPU_SREG_FS: return &save->fs; | |
699 | case VCPU_SREG_GS: return &save->gs; | |
700 | case VCPU_SREG_SS: return &save->ss; | |
701 | case VCPU_SREG_TR: return &save->tr; | |
702 | case VCPU_SREG_LDTR: return &save->ldtr; | |
703 | } | |
704 | BUG(); | |
8b6d44c7 | 705 | return NULL; |
6aa8b732 AK |
706 | } |
707 | ||
708 | static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg) | |
709 | { | |
710 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
711 | ||
712 | return s->base; | |
713 | } | |
714 | ||
715 | static void svm_get_segment(struct kvm_vcpu *vcpu, | |
716 | struct kvm_segment *var, int seg) | |
717 | { | |
718 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
719 | ||
720 | var->base = s->base; | |
721 | var->limit = s->limit; | |
722 | var->selector = s->selector; | |
723 | var->type = s->attrib & SVM_SELECTOR_TYPE_MASK; | |
724 | var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1; | |
725 | var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3; | |
726 | var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1; | |
727 | var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1; | |
728 | var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1; | |
729 | var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1; | |
730 | var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1; | |
731 | var->unusable = !var->present; | |
732 | } | |
733 | ||
6aa8b732 AK |
734 | static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) |
735 | { | |
a2fa3e9f GH |
736 | struct vcpu_svm *svm = to_svm(vcpu); |
737 | ||
738 | dt->limit = svm->vmcb->save.idtr.limit; | |
739 | dt->base = svm->vmcb->save.idtr.base; | |
6aa8b732 AK |
740 | } |
741 | ||
742 | static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
743 | { | |
a2fa3e9f GH |
744 | struct vcpu_svm *svm = to_svm(vcpu); |
745 | ||
746 | svm->vmcb->save.idtr.limit = dt->limit; | |
747 | svm->vmcb->save.idtr.base = dt->base ; | |
6aa8b732 AK |
748 | } |
749 | ||
750 | static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
751 | { | |
a2fa3e9f GH |
752 | struct vcpu_svm *svm = to_svm(vcpu); |
753 | ||
754 | dt->limit = svm->vmcb->save.gdtr.limit; | |
755 | dt->base = svm->vmcb->save.gdtr.base; | |
6aa8b732 AK |
756 | } |
757 | ||
758 | static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
759 | { | |
a2fa3e9f GH |
760 | struct vcpu_svm *svm = to_svm(vcpu); |
761 | ||
762 | svm->vmcb->save.gdtr.limit = dt->limit; | |
763 | svm->vmcb->save.gdtr.base = dt->base ; | |
6aa8b732 AK |
764 | } |
765 | ||
25c4c276 | 766 | static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 AK |
767 | { |
768 | } | |
769 | ||
6aa8b732 AK |
770 | static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
771 | { | |
a2fa3e9f GH |
772 | struct vcpu_svm *svm = to_svm(vcpu); |
773 | ||
05b3e0c2 | 774 | #ifdef CONFIG_X86_64 |
ad312c7c | 775 | if (vcpu->arch.shadow_efer & EFER_LME) { |
707d92fa | 776 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { |
ad312c7c | 777 | vcpu->arch.shadow_efer |= EFER_LMA; |
2b5203ee | 778 | svm->vmcb->save.efer |= EFER_LMA | EFER_LME; |
6aa8b732 AK |
779 | } |
780 | ||
d77c26fc | 781 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) { |
ad312c7c | 782 | vcpu->arch.shadow_efer &= ~EFER_LMA; |
2b5203ee | 783 | svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME); |
6aa8b732 AK |
784 | } |
785 | } | |
786 | #endif | |
ad312c7c | 787 | if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) { |
a2fa3e9f | 788 | svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR); |
7807fa6c AL |
789 | vcpu->fpu_active = 1; |
790 | } | |
791 | ||
ad312c7c | 792 | vcpu->arch.cr0 = cr0; |
707d92fa RR |
793 | cr0 |= X86_CR0_PG | X86_CR0_WP; |
794 | cr0 &= ~(X86_CR0_CD | X86_CR0_NW); | |
6b390b63 JR |
795 | if (!vcpu->fpu_active) { |
796 | svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR); | |
334df50a | 797 | cr0 |= X86_CR0_TS; |
6b390b63 | 798 | } |
a2fa3e9f | 799 | svm->vmcb->save.cr0 = cr0; |
6aa8b732 AK |
800 | } |
801 | ||
802 | static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) | |
803 | { | |
ad312c7c | 804 | vcpu->arch.cr4 = cr4; |
a2fa3e9f | 805 | to_svm(vcpu)->vmcb->save.cr4 = cr4 | X86_CR4_PAE; |
6aa8b732 AK |
806 | } |
807 | ||
808 | static void svm_set_segment(struct kvm_vcpu *vcpu, | |
809 | struct kvm_segment *var, int seg) | |
810 | { | |
a2fa3e9f | 811 | struct vcpu_svm *svm = to_svm(vcpu); |
6aa8b732 AK |
812 | struct vmcb_seg *s = svm_seg(vcpu, seg); |
813 | ||
814 | s->base = var->base; | |
815 | s->limit = var->limit; | |
816 | s->selector = var->selector; | |
817 | if (var->unusable) | |
818 | s->attrib = 0; | |
819 | else { | |
820 | s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK); | |
821 | s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT; | |
822 | s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT; | |
823 | s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT; | |
824 | s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT; | |
825 | s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT; | |
826 | s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT; | |
827 | s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT; | |
828 | } | |
829 | if (seg == VCPU_SREG_CS) | |
a2fa3e9f GH |
830 | svm->vmcb->save.cpl |
831 | = (svm->vmcb->save.cs.attrib | |
6aa8b732 AK |
832 | >> SVM_SELECTOR_DPL_SHIFT) & 3; |
833 | ||
834 | } | |
835 | ||
836 | /* FIXME: | |
837 | ||
a2fa3e9f GH |
838 | svm(vcpu)->vmcb->control.int_ctl &= ~V_TPR_MASK; |
839 | svm(vcpu)->vmcb->control.int_ctl |= (sregs->cr8 & V_TPR_MASK); | |
6aa8b732 AK |
840 | |
841 | */ | |
842 | ||
843 | static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg) | |
844 | { | |
845 | return -EOPNOTSUPP; | |
846 | } | |
847 | ||
2a8067f1 ED |
848 | static int svm_get_irq(struct kvm_vcpu *vcpu) |
849 | { | |
850 | struct vcpu_svm *svm = to_svm(vcpu); | |
851 | u32 exit_int_info = svm->vmcb->control.exit_int_info; | |
852 | ||
853 | if (is_external_interrupt(exit_int_info)) | |
854 | return exit_int_info & SVM_EVTINJ_VEC_MASK; | |
855 | return -1; | |
856 | } | |
857 | ||
6aa8b732 AK |
858 | static void load_host_msrs(struct kvm_vcpu *vcpu) |
859 | { | |
94dfbdb3 | 860 | #ifdef CONFIG_X86_64 |
a2fa3e9f | 861 | wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base); |
94dfbdb3 | 862 | #endif |
6aa8b732 AK |
863 | } |
864 | ||
865 | static void save_host_msrs(struct kvm_vcpu *vcpu) | |
866 | { | |
94dfbdb3 | 867 | #ifdef CONFIG_X86_64 |
a2fa3e9f | 868 | rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base); |
94dfbdb3 | 869 | #endif |
6aa8b732 AK |
870 | } |
871 | ||
e756fc62 | 872 | static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data) |
6aa8b732 AK |
873 | { |
874 | if (svm_data->next_asid > svm_data->max_asid) { | |
875 | ++svm_data->asid_generation; | |
876 | svm_data->next_asid = 1; | |
a2fa3e9f | 877 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID; |
6aa8b732 AK |
878 | } |
879 | ||
e756fc62 | 880 | svm->vcpu.cpu = svm_data->cpu; |
a2fa3e9f GH |
881 | svm->asid_generation = svm_data->asid_generation; |
882 | svm->vmcb->control.asid = svm_data->next_asid++; | |
6aa8b732 AK |
883 | } |
884 | ||
6aa8b732 AK |
885 | static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr) |
886 | { | |
a2fa3e9f | 887 | return to_svm(vcpu)->db_regs[dr]; |
6aa8b732 AK |
888 | } |
889 | ||
890 | static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value, | |
891 | int *exception) | |
892 | { | |
a2fa3e9f GH |
893 | struct vcpu_svm *svm = to_svm(vcpu); |
894 | ||
6aa8b732 AK |
895 | *exception = 0; |
896 | ||
a2fa3e9f GH |
897 | if (svm->vmcb->save.dr7 & DR7_GD_MASK) { |
898 | svm->vmcb->save.dr7 &= ~DR7_GD_MASK; | |
899 | svm->vmcb->save.dr6 |= DR6_BD_MASK; | |
6aa8b732 AK |
900 | *exception = DB_VECTOR; |
901 | return; | |
902 | } | |
903 | ||
904 | switch (dr) { | |
905 | case 0 ... 3: | |
a2fa3e9f | 906 | svm->db_regs[dr] = value; |
6aa8b732 AK |
907 | return; |
908 | case 4 ... 5: | |
ad312c7c | 909 | if (vcpu->arch.cr4 & X86_CR4_DE) { |
6aa8b732 AK |
910 | *exception = UD_VECTOR; |
911 | return; | |
912 | } | |
913 | case 7: { | |
914 | if (value & ~((1ULL << 32) - 1)) { | |
915 | *exception = GP_VECTOR; | |
916 | return; | |
917 | } | |
a2fa3e9f | 918 | svm->vmcb->save.dr7 = value; |
6aa8b732 AK |
919 | return; |
920 | } | |
921 | default: | |
922 | printk(KERN_DEBUG "%s: unexpected dr %u\n", | |
923 | __FUNCTION__, dr); | |
924 | *exception = UD_VECTOR; | |
925 | return; | |
926 | } | |
927 | } | |
928 | ||
e756fc62 | 929 | static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 930 | { |
a2fa3e9f | 931 | u32 exit_int_info = svm->vmcb->control.exit_int_info; |
e756fc62 | 932 | struct kvm *kvm = svm->vcpu.kvm; |
6aa8b732 AK |
933 | u64 fault_address; |
934 | u32 error_code; | |
6aa8b732 | 935 | |
85f455f7 ED |
936 | if (!irqchip_in_kernel(kvm) && |
937 | is_external_interrupt(exit_int_info)) | |
e756fc62 | 938 | push_irq(&svm->vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK); |
6aa8b732 | 939 | |
a2fa3e9f GH |
940 | fault_address = svm->vmcb->control.exit_info_2; |
941 | error_code = svm->vmcb->control.exit_info_1; | |
3067714c | 942 | return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code); |
6aa8b732 AK |
943 | } |
944 | ||
7aa81cc0 AL |
945 | static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
946 | { | |
947 | int er; | |
948 | ||
571008da | 949 | er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD); |
7aa81cc0 | 950 | if (er != EMULATE_DONE) |
7ee5d940 | 951 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
7aa81cc0 AL |
952 | return 1; |
953 | } | |
954 | ||
e756fc62 | 955 | static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
7807fa6c | 956 | { |
a2fa3e9f | 957 | svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR); |
ad312c7c | 958 | if (!(svm->vcpu.arch.cr0 & X86_CR0_TS)) |
a2fa3e9f | 959 | svm->vmcb->save.cr0 &= ~X86_CR0_TS; |
e756fc62 | 960 | svm->vcpu.fpu_active = 1; |
a2fa3e9f GH |
961 | |
962 | return 1; | |
7807fa6c AL |
963 | } |
964 | ||
e756fc62 | 965 | static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
46fe4ddd JR |
966 | { |
967 | /* | |
968 | * VMCB is undefined after a SHUTDOWN intercept | |
969 | * so reinitialize it. | |
970 | */ | |
a2fa3e9f GH |
971 | clear_page(svm->vmcb); |
972 | init_vmcb(svm->vmcb); | |
46fe4ddd JR |
973 | |
974 | kvm_run->exit_reason = KVM_EXIT_SHUTDOWN; | |
975 | return 0; | |
976 | } | |
977 | ||
e756fc62 | 978 | static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 979 | { |
d77c26fc | 980 | u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */ |
039576c0 AK |
981 | int size, down, in, string, rep; |
982 | unsigned port; | |
6aa8b732 | 983 | |
e756fc62 | 984 | ++svm->vcpu.stat.io_exits; |
6aa8b732 | 985 | |
a2fa3e9f | 986 | svm->next_rip = svm->vmcb->control.exit_info_2; |
6aa8b732 | 987 | |
e70669ab LV |
988 | string = (io_info & SVM_IOIO_STR_MASK) != 0; |
989 | ||
990 | if (string) { | |
3427318f LV |
991 | if (emulate_instruction(&svm->vcpu, |
992 | kvm_run, 0, 0, 0) == EMULATE_DO_MMIO) | |
e70669ab LV |
993 | return 0; |
994 | return 1; | |
995 | } | |
996 | ||
039576c0 AK |
997 | in = (io_info & SVM_IOIO_TYPE_MASK) != 0; |
998 | port = io_info >> 16; | |
999 | size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT; | |
039576c0 | 1000 | rep = (io_info & SVM_IOIO_REP_MASK) != 0; |
a2fa3e9f | 1001 | down = (svm->vmcb->save.rflags & X86_EFLAGS_DF) != 0; |
6aa8b732 | 1002 | |
3090dd73 | 1003 | return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port); |
6aa8b732 AK |
1004 | } |
1005 | ||
e756fc62 | 1006 | static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 AK |
1007 | { |
1008 | return 1; | |
1009 | } | |
1010 | ||
e756fc62 | 1011 | static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1012 | { |
a2fa3e9f | 1013 | svm->next_rip = svm->vmcb->save.rip + 1; |
e756fc62 RR |
1014 | skip_emulated_instruction(&svm->vcpu); |
1015 | return kvm_emulate_halt(&svm->vcpu); | |
6aa8b732 AK |
1016 | } |
1017 | ||
e756fc62 | 1018 | static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
02e235bc | 1019 | { |
a2fa3e9f | 1020 | svm->next_rip = svm->vmcb->save.rip + 3; |
e756fc62 | 1021 | skip_emulated_instruction(&svm->vcpu); |
7aa81cc0 AL |
1022 | kvm_emulate_hypercall(&svm->vcpu); |
1023 | return 1; | |
02e235bc AK |
1024 | } |
1025 | ||
e756fc62 RR |
1026 | static int invalid_op_interception(struct vcpu_svm *svm, |
1027 | struct kvm_run *kvm_run) | |
6aa8b732 | 1028 | { |
7ee5d940 | 1029 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
6aa8b732 AK |
1030 | return 1; |
1031 | } | |
1032 | ||
e756fc62 RR |
1033 | static int task_switch_interception(struct vcpu_svm *svm, |
1034 | struct kvm_run *kvm_run) | |
6aa8b732 | 1035 | { |
f0242478 | 1036 | pr_unimpl(&svm->vcpu, "%s: task switch is unsupported\n", __FUNCTION__); |
6aa8b732 AK |
1037 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; |
1038 | return 0; | |
1039 | } | |
1040 | ||
e756fc62 | 1041 | static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1042 | { |
a2fa3e9f | 1043 | svm->next_rip = svm->vmcb->save.rip + 2; |
e756fc62 | 1044 | kvm_emulate_cpuid(&svm->vcpu); |
06465c5a | 1045 | return 1; |
6aa8b732 AK |
1046 | } |
1047 | ||
e756fc62 RR |
1048 | static int emulate_on_interception(struct vcpu_svm *svm, |
1049 | struct kvm_run *kvm_run) | |
6aa8b732 | 1050 | { |
3427318f | 1051 | if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE) |
f0242478 | 1052 | pr_unimpl(&svm->vcpu, "%s: failed\n", __FUNCTION__); |
6aa8b732 AK |
1053 | return 1; |
1054 | } | |
1055 | ||
1d075434 JR |
1056 | static int cr8_write_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
1057 | { | |
1058 | emulate_instruction(&svm->vcpu, NULL, 0, 0, 0); | |
1059 | if (irqchip_in_kernel(svm->vcpu.kvm)) | |
1060 | return 1; | |
1061 | kvm_run->exit_reason = KVM_EXIT_SET_TPR; | |
1062 | return 0; | |
1063 | } | |
1064 | ||
6aa8b732 AK |
1065 | static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data) |
1066 | { | |
a2fa3e9f GH |
1067 | struct vcpu_svm *svm = to_svm(vcpu); |
1068 | ||
6aa8b732 | 1069 | switch (ecx) { |
6aa8b732 AK |
1070 | case MSR_IA32_TIME_STAMP_COUNTER: { |
1071 | u64 tsc; | |
1072 | ||
1073 | rdtscll(tsc); | |
a2fa3e9f | 1074 | *data = svm->vmcb->control.tsc_offset + tsc; |
6aa8b732 AK |
1075 | break; |
1076 | } | |
0e859cac | 1077 | case MSR_K6_STAR: |
a2fa3e9f | 1078 | *data = svm->vmcb->save.star; |
6aa8b732 | 1079 | break; |
0e859cac | 1080 | #ifdef CONFIG_X86_64 |
6aa8b732 | 1081 | case MSR_LSTAR: |
a2fa3e9f | 1082 | *data = svm->vmcb->save.lstar; |
6aa8b732 AK |
1083 | break; |
1084 | case MSR_CSTAR: | |
a2fa3e9f | 1085 | *data = svm->vmcb->save.cstar; |
6aa8b732 AK |
1086 | break; |
1087 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 1088 | *data = svm->vmcb->save.kernel_gs_base; |
6aa8b732 AK |
1089 | break; |
1090 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 1091 | *data = svm->vmcb->save.sfmask; |
6aa8b732 AK |
1092 | break; |
1093 | #endif | |
1094 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 1095 | *data = svm->vmcb->save.sysenter_cs; |
6aa8b732 AK |
1096 | break; |
1097 | case MSR_IA32_SYSENTER_EIP: | |
a2fa3e9f | 1098 | *data = svm->vmcb->save.sysenter_eip; |
6aa8b732 AK |
1099 | break; |
1100 | case MSR_IA32_SYSENTER_ESP: | |
a2fa3e9f | 1101 | *data = svm->vmcb->save.sysenter_esp; |
6aa8b732 AK |
1102 | break; |
1103 | default: | |
3bab1f5d | 1104 | return kvm_get_msr_common(vcpu, ecx, data); |
6aa8b732 AK |
1105 | } |
1106 | return 0; | |
1107 | } | |
1108 | ||
e756fc62 | 1109 | static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1110 | { |
ad312c7c | 1111 | u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
6aa8b732 AK |
1112 | u64 data; |
1113 | ||
e756fc62 | 1114 | if (svm_get_msr(&svm->vcpu, ecx, &data)) |
c1a5d4f9 | 1115 | kvm_inject_gp(&svm->vcpu, 0); |
6aa8b732 | 1116 | else { |
a2fa3e9f | 1117 | svm->vmcb->save.rax = data & 0xffffffff; |
ad312c7c | 1118 | svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32; |
a2fa3e9f | 1119 | svm->next_rip = svm->vmcb->save.rip + 2; |
e756fc62 | 1120 | skip_emulated_instruction(&svm->vcpu); |
6aa8b732 AK |
1121 | } |
1122 | return 1; | |
1123 | } | |
1124 | ||
1125 | static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data) | |
1126 | { | |
a2fa3e9f GH |
1127 | struct vcpu_svm *svm = to_svm(vcpu); |
1128 | ||
6aa8b732 | 1129 | switch (ecx) { |
6aa8b732 AK |
1130 | case MSR_IA32_TIME_STAMP_COUNTER: { |
1131 | u64 tsc; | |
1132 | ||
1133 | rdtscll(tsc); | |
a2fa3e9f | 1134 | svm->vmcb->control.tsc_offset = data - tsc; |
6aa8b732 AK |
1135 | break; |
1136 | } | |
0e859cac | 1137 | case MSR_K6_STAR: |
a2fa3e9f | 1138 | svm->vmcb->save.star = data; |
6aa8b732 | 1139 | break; |
49b14f24 | 1140 | #ifdef CONFIG_X86_64 |
6aa8b732 | 1141 | case MSR_LSTAR: |
a2fa3e9f | 1142 | svm->vmcb->save.lstar = data; |
6aa8b732 AK |
1143 | break; |
1144 | case MSR_CSTAR: | |
a2fa3e9f | 1145 | svm->vmcb->save.cstar = data; |
6aa8b732 AK |
1146 | break; |
1147 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 1148 | svm->vmcb->save.kernel_gs_base = data; |
6aa8b732 AK |
1149 | break; |
1150 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 1151 | svm->vmcb->save.sfmask = data; |
6aa8b732 AK |
1152 | break; |
1153 | #endif | |
1154 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 1155 | svm->vmcb->save.sysenter_cs = data; |
6aa8b732 AK |
1156 | break; |
1157 | case MSR_IA32_SYSENTER_EIP: | |
a2fa3e9f | 1158 | svm->vmcb->save.sysenter_eip = data; |
6aa8b732 AK |
1159 | break; |
1160 | case MSR_IA32_SYSENTER_ESP: | |
a2fa3e9f | 1161 | svm->vmcb->save.sysenter_esp = data; |
6aa8b732 | 1162 | break; |
62b9abaa JR |
1163 | case MSR_K7_EVNTSEL0: |
1164 | case MSR_K7_EVNTSEL1: | |
1165 | case MSR_K7_EVNTSEL2: | |
1166 | case MSR_K7_EVNTSEL3: | |
1167 | /* | |
1168 | * only support writing 0 to the performance counters for now | |
1169 | * to make Windows happy. Should be replaced by a real | |
1170 | * performance counter emulation later. | |
1171 | */ | |
1172 | if (data != 0) | |
1173 | goto unhandled; | |
1174 | break; | |
6aa8b732 | 1175 | default: |
62b9abaa | 1176 | unhandled: |
3bab1f5d | 1177 | return kvm_set_msr_common(vcpu, ecx, data); |
6aa8b732 AK |
1178 | } |
1179 | return 0; | |
1180 | } | |
1181 | ||
e756fc62 | 1182 | static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1183 | { |
ad312c7c | 1184 | u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
a2fa3e9f | 1185 | u64 data = (svm->vmcb->save.rax & -1u) |
ad312c7c | 1186 | | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32); |
a2fa3e9f | 1187 | svm->next_rip = svm->vmcb->save.rip + 2; |
e756fc62 | 1188 | if (svm_set_msr(&svm->vcpu, ecx, data)) |
c1a5d4f9 | 1189 | kvm_inject_gp(&svm->vcpu, 0); |
6aa8b732 | 1190 | else |
e756fc62 | 1191 | skip_emulated_instruction(&svm->vcpu); |
6aa8b732 AK |
1192 | return 1; |
1193 | } | |
1194 | ||
e756fc62 | 1195 | static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1196 | { |
e756fc62 RR |
1197 | if (svm->vmcb->control.exit_info_1) |
1198 | return wrmsr_interception(svm, kvm_run); | |
6aa8b732 | 1199 | else |
e756fc62 | 1200 | return rdmsr_interception(svm, kvm_run); |
6aa8b732 AK |
1201 | } |
1202 | ||
e756fc62 | 1203 | static int interrupt_window_interception(struct vcpu_svm *svm, |
c1150d8c DL |
1204 | struct kvm_run *kvm_run) |
1205 | { | |
85f455f7 ED |
1206 | svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR); |
1207 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; | |
c1150d8c DL |
1208 | /* |
1209 | * If the user space waits to inject interrupts, exit as soon as | |
1210 | * possible | |
1211 | */ | |
1212 | if (kvm_run->request_interrupt_window && | |
ad312c7c | 1213 | !svm->vcpu.arch.irq_summary) { |
e756fc62 | 1214 | ++svm->vcpu.stat.irq_window_exits; |
c1150d8c DL |
1215 | kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; |
1216 | return 0; | |
1217 | } | |
1218 | ||
1219 | return 1; | |
1220 | } | |
1221 | ||
e756fc62 | 1222 | static int (*svm_exit_handlers[])(struct vcpu_svm *svm, |
6aa8b732 AK |
1223 | struct kvm_run *kvm_run) = { |
1224 | [SVM_EXIT_READ_CR0] = emulate_on_interception, | |
1225 | [SVM_EXIT_READ_CR3] = emulate_on_interception, | |
1226 | [SVM_EXIT_READ_CR4] = emulate_on_interception, | |
80a8119c | 1227 | [SVM_EXIT_READ_CR8] = emulate_on_interception, |
6aa8b732 AK |
1228 | /* for now: */ |
1229 | [SVM_EXIT_WRITE_CR0] = emulate_on_interception, | |
1230 | [SVM_EXIT_WRITE_CR3] = emulate_on_interception, | |
1231 | [SVM_EXIT_WRITE_CR4] = emulate_on_interception, | |
1d075434 | 1232 | [SVM_EXIT_WRITE_CR8] = cr8_write_interception, |
6aa8b732 AK |
1233 | [SVM_EXIT_READ_DR0] = emulate_on_interception, |
1234 | [SVM_EXIT_READ_DR1] = emulate_on_interception, | |
1235 | [SVM_EXIT_READ_DR2] = emulate_on_interception, | |
1236 | [SVM_EXIT_READ_DR3] = emulate_on_interception, | |
1237 | [SVM_EXIT_WRITE_DR0] = emulate_on_interception, | |
1238 | [SVM_EXIT_WRITE_DR1] = emulate_on_interception, | |
1239 | [SVM_EXIT_WRITE_DR2] = emulate_on_interception, | |
1240 | [SVM_EXIT_WRITE_DR3] = emulate_on_interception, | |
1241 | [SVM_EXIT_WRITE_DR5] = emulate_on_interception, | |
1242 | [SVM_EXIT_WRITE_DR7] = emulate_on_interception, | |
7aa81cc0 | 1243 | [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception, |
6aa8b732 | 1244 | [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception, |
7807fa6c | 1245 | [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception, |
6aa8b732 AK |
1246 | [SVM_EXIT_INTR] = nop_on_interception, |
1247 | [SVM_EXIT_NMI] = nop_on_interception, | |
1248 | [SVM_EXIT_SMI] = nop_on_interception, | |
1249 | [SVM_EXIT_INIT] = nop_on_interception, | |
c1150d8c | 1250 | [SVM_EXIT_VINTR] = interrupt_window_interception, |
6aa8b732 AK |
1251 | /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */ |
1252 | [SVM_EXIT_CPUID] = cpuid_interception, | |
cf5a94d1 | 1253 | [SVM_EXIT_INVD] = emulate_on_interception, |
6aa8b732 AK |
1254 | [SVM_EXIT_HLT] = halt_interception, |
1255 | [SVM_EXIT_INVLPG] = emulate_on_interception, | |
1256 | [SVM_EXIT_INVLPGA] = invalid_op_interception, | |
1257 | [SVM_EXIT_IOIO] = io_interception, | |
1258 | [SVM_EXIT_MSR] = msr_interception, | |
1259 | [SVM_EXIT_TASK_SWITCH] = task_switch_interception, | |
46fe4ddd | 1260 | [SVM_EXIT_SHUTDOWN] = shutdown_interception, |
6aa8b732 | 1261 | [SVM_EXIT_VMRUN] = invalid_op_interception, |
02e235bc | 1262 | [SVM_EXIT_VMMCALL] = vmmcall_interception, |
6aa8b732 AK |
1263 | [SVM_EXIT_VMLOAD] = invalid_op_interception, |
1264 | [SVM_EXIT_VMSAVE] = invalid_op_interception, | |
1265 | [SVM_EXIT_STGI] = invalid_op_interception, | |
1266 | [SVM_EXIT_CLGI] = invalid_op_interception, | |
1267 | [SVM_EXIT_SKINIT] = invalid_op_interception, | |
cf5a94d1 | 1268 | [SVM_EXIT_WBINVD] = emulate_on_interception, |
916ce236 JR |
1269 | [SVM_EXIT_MONITOR] = invalid_op_interception, |
1270 | [SVM_EXIT_MWAIT] = invalid_op_interception, | |
6aa8b732 AK |
1271 | }; |
1272 | ||
1273 | ||
04d2cc77 | 1274 | static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu) |
6aa8b732 | 1275 | { |
04d2cc77 | 1276 | struct vcpu_svm *svm = to_svm(vcpu); |
a2fa3e9f | 1277 | u32 exit_code = svm->vmcb->control.exit_code; |
6aa8b732 | 1278 | |
04d2cc77 AK |
1279 | kvm_reput_irq(svm); |
1280 | ||
1281 | if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) { | |
1282 | kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY; | |
1283 | kvm_run->fail_entry.hardware_entry_failure_reason | |
1284 | = svm->vmcb->control.exit_code; | |
1285 | return 0; | |
1286 | } | |
1287 | ||
a2fa3e9f | 1288 | if (is_external_interrupt(svm->vmcb->control.exit_int_info) && |
6aa8b732 AK |
1289 | exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR) |
1290 | printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x " | |
1291 | "exit_code 0x%x\n", | |
a2fa3e9f | 1292 | __FUNCTION__, svm->vmcb->control.exit_int_info, |
6aa8b732 AK |
1293 | exit_code); |
1294 | ||
9d8f549d | 1295 | if (exit_code >= ARRAY_SIZE(svm_exit_handlers) |
56919c5c | 1296 | || !svm_exit_handlers[exit_code]) { |
6aa8b732 | 1297 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; |
364b625b | 1298 | kvm_run->hw.hardware_exit_reason = exit_code; |
6aa8b732 AK |
1299 | return 0; |
1300 | } | |
1301 | ||
e756fc62 | 1302 | return svm_exit_handlers[exit_code](svm, kvm_run); |
6aa8b732 AK |
1303 | } |
1304 | ||
1305 | static void reload_tss(struct kvm_vcpu *vcpu) | |
1306 | { | |
1307 | int cpu = raw_smp_processor_id(); | |
1308 | ||
1309 | struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu); | |
d77c26fc | 1310 | svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */ |
6aa8b732 AK |
1311 | load_TR_desc(); |
1312 | } | |
1313 | ||
e756fc62 | 1314 | static void pre_svm_run(struct vcpu_svm *svm) |
6aa8b732 AK |
1315 | { |
1316 | int cpu = raw_smp_processor_id(); | |
1317 | ||
1318 | struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu); | |
1319 | ||
a2fa3e9f | 1320 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING; |
e756fc62 | 1321 | if (svm->vcpu.cpu != cpu || |
a2fa3e9f | 1322 | svm->asid_generation != svm_data->asid_generation) |
e756fc62 | 1323 | new_asid(svm, svm_data); |
6aa8b732 AK |
1324 | } |
1325 | ||
1326 | ||
85f455f7 | 1327 | static inline void svm_inject_irq(struct vcpu_svm *svm, int irq) |
6aa8b732 AK |
1328 | { |
1329 | struct vmcb_control_area *control; | |
1330 | ||
e756fc62 | 1331 | control = &svm->vmcb->control; |
85f455f7 | 1332 | control->int_vector = irq; |
6aa8b732 AK |
1333 | control->int_ctl &= ~V_INTR_PRIO_MASK; |
1334 | control->int_ctl |= V_IRQ_MASK | | |
1335 | ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT); | |
1336 | } | |
1337 | ||
2a8067f1 ED |
1338 | static void svm_set_irq(struct kvm_vcpu *vcpu, int irq) |
1339 | { | |
1340 | struct vcpu_svm *svm = to_svm(vcpu); | |
1341 | ||
1342 | svm_inject_irq(svm, irq); | |
1343 | } | |
1344 | ||
04d2cc77 | 1345 | static void svm_intr_assist(struct kvm_vcpu *vcpu) |
6aa8b732 | 1346 | { |
04d2cc77 | 1347 | struct vcpu_svm *svm = to_svm(vcpu); |
85f455f7 ED |
1348 | struct vmcb *vmcb = svm->vmcb; |
1349 | int intr_vector = -1; | |
1350 | ||
1351 | if ((vmcb->control.exit_int_info & SVM_EVTINJ_VALID) && | |
1352 | ((vmcb->control.exit_int_info & SVM_EVTINJ_TYPE_MASK) == 0)) { | |
1353 | intr_vector = vmcb->control.exit_int_info & | |
1354 | SVM_EVTINJ_VEC_MASK; | |
1355 | vmcb->control.exit_int_info = 0; | |
1356 | svm_inject_irq(svm, intr_vector); | |
1357 | return; | |
1358 | } | |
1359 | ||
1360 | if (vmcb->control.int_ctl & V_IRQ_MASK) | |
1361 | return; | |
1362 | ||
1b9778da | 1363 | if (!kvm_cpu_has_interrupt(vcpu)) |
85f455f7 ED |
1364 | return; |
1365 | ||
1366 | if (!(vmcb->save.rflags & X86_EFLAGS_IF) || | |
1367 | (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) || | |
1368 | (vmcb->control.event_inj & SVM_EVTINJ_VALID)) { | |
1369 | /* unable to deliver irq, set pending irq */ | |
1370 | vmcb->control.intercept |= (1ULL << INTERCEPT_VINTR); | |
1371 | svm_inject_irq(svm, 0x0); | |
1372 | return; | |
1373 | } | |
1374 | /* Okay, we can deliver the interrupt: grab it and update PIC state. */ | |
1b9778da | 1375 | intr_vector = kvm_cpu_get_interrupt(vcpu); |
85f455f7 | 1376 | svm_inject_irq(svm, intr_vector); |
1b9778da | 1377 | kvm_timer_intr_post(vcpu, intr_vector); |
85f455f7 ED |
1378 | } |
1379 | ||
1380 | static void kvm_reput_irq(struct vcpu_svm *svm) | |
1381 | { | |
e756fc62 | 1382 | struct vmcb_control_area *control = &svm->vmcb->control; |
6aa8b732 | 1383 | |
7017fc3d ED |
1384 | if ((control->int_ctl & V_IRQ_MASK) |
1385 | && !irqchip_in_kernel(svm->vcpu.kvm)) { | |
6aa8b732 | 1386 | control->int_ctl &= ~V_IRQ_MASK; |
e756fc62 | 1387 | push_irq(&svm->vcpu, control->int_vector); |
6aa8b732 | 1388 | } |
c1150d8c | 1389 | |
ad312c7c | 1390 | svm->vcpu.arch.interrupt_window_open = |
c1150d8c DL |
1391 | !(control->int_state & SVM_INTERRUPT_SHADOW_MASK); |
1392 | } | |
1393 | ||
85f455f7 ED |
1394 | static void svm_do_inject_vector(struct vcpu_svm *svm) |
1395 | { | |
1396 | struct kvm_vcpu *vcpu = &svm->vcpu; | |
ad312c7c ZX |
1397 | int word_index = __ffs(vcpu->arch.irq_summary); |
1398 | int bit_index = __ffs(vcpu->arch.irq_pending[word_index]); | |
85f455f7 ED |
1399 | int irq = word_index * BITS_PER_LONG + bit_index; |
1400 | ||
ad312c7c ZX |
1401 | clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]); |
1402 | if (!vcpu->arch.irq_pending[word_index]) | |
1403 | clear_bit(word_index, &vcpu->arch.irq_summary); | |
85f455f7 ED |
1404 | svm_inject_irq(svm, irq); |
1405 | } | |
1406 | ||
04d2cc77 | 1407 | static void do_interrupt_requests(struct kvm_vcpu *vcpu, |
c1150d8c DL |
1408 | struct kvm_run *kvm_run) |
1409 | { | |
04d2cc77 | 1410 | struct vcpu_svm *svm = to_svm(vcpu); |
a2fa3e9f | 1411 | struct vmcb_control_area *control = &svm->vmcb->control; |
c1150d8c | 1412 | |
ad312c7c | 1413 | svm->vcpu.arch.interrupt_window_open = |
c1150d8c | 1414 | (!(control->int_state & SVM_INTERRUPT_SHADOW_MASK) && |
a2fa3e9f | 1415 | (svm->vmcb->save.rflags & X86_EFLAGS_IF)); |
c1150d8c | 1416 | |
ad312c7c | 1417 | if (svm->vcpu.arch.interrupt_window_open && svm->vcpu.arch.irq_summary) |
c1150d8c DL |
1418 | /* |
1419 | * If interrupts enabled, and not blocked by sti or mov ss. Good. | |
1420 | */ | |
85f455f7 | 1421 | svm_do_inject_vector(svm); |
c1150d8c DL |
1422 | |
1423 | /* | |
1424 | * Interrupts blocked. Wait for unblock. | |
1425 | */ | |
ad312c7c ZX |
1426 | if (!svm->vcpu.arch.interrupt_window_open && |
1427 | (svm->vcpu.arch.irq_summary || kvm_run->request_interrupt_window)) | |
c1150d8c | 1428 | control->intercept |= 1ULL << INTERCEPT_VINTR; |
d77c26fc | 1429 | else |
c1150d8c DL |
1430 | control->intercept &= ~(1ULL << INTERCEPT_VINTR); |
1431 | } | |
1432 | ||
cbc94022 IE |
1433 | static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr) |
1434 | { | |
1435 | return 0; | |
1436 | } | |
1437 | ||
6aa8b732 AK |
1438 | static void save_db_regs(unsigned long *db_regs) |
1439 | { | |
5aff458e AK |
1440 | asm volatile ("mov %%dr0, %0" : "=r"(db_regs[0])); |
1441 | asm volatile ("mov %%dr1, %0" : "=r"(db_regs[1])); | |
1442 | asm volatile ("mov %%dr2, %0" : "=r"(db_regs[2])); | |
1443 | asm volatile ("mov %%dr3, %0" : "=r"(db_regs[3])); | |
6aa8b732 AK |
1444 | } |
1445 | ||
1446 | static void load_db_regs(unsigned long *db_regs) | |
1447 | { | |
5aff458e AK |
1448 | asm volatile ("mov %0, %%dr0" : : "r"(db_regs[0])); |
1449 | asm volatile ("mov %0, %%dr1" : : "r"(db_regs[1])); | |
1450 | asm volatile ("mov %0, %%dr2" : : "r"(db_regs[2])); | |
1451 | asm volatile ("mov %0, %%dr3" : : "r"(db_regs[3])); | |
6aa8b732 AK |
1452 | } |
1453 | ||
d9e368d6 AK |
1454 | static void svm_flush_tlb(struct kvm_vcpu *vcpu) |
1455 | { | |
1456 | force_new_asid(vcpu); | |
1457 | } | |
1458 | ||
04d2cc77 AK |
1459 | static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu) |
1460 | { | |
1461 | } | |
1462 | ||
1463 | static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
6aa8b732 | 1464 | { |
a2fa3e9f | 1465 | struct vcpu_svm *svm = to_svm(vcpu); |
6aa8b732 AK |
1466 | u16 fs_selector; |
1467 | u16 gs_selector; | |
1468 | u16 ldt_selector; | |
d9e368d6 | 1469 | |
e756fc62 | 1470 | pre_svm_run(svm); |
6aa8b732 AK |
1471 | |
1472 | save_host_msrs(vcpu); | |
1473 | fs_selector = read_fs(); | |
1474 | gs_selector = read_gs(); | |
1475 | ldt_selector = read_ldt(); | |
a2fa3e9f GH |
1476 | svm->host_cr2 = kvm_read_cr2(); |
1477 | svm->host_dr6 = read_dr6(); | |
1478 | svm->host_dr7 = read_dr7(); | |
ad312c7c | 1479 | svm->vmcb->save.cr2 = vcpu->arch.cr2; |
6aa8b732 | 1480 | |
a2fa3e9f | 1481 | if (svm->vmcb->save.dr7 & 0xff) { |
6aa8b732 | 1482 | write_dr7(0); |
a2fa3e9f GH |
1483 | save_db_regs(svm->host_db_regs); |
1484 | load_db_regs(svm->db_regs); | |
6aa8b732 | 1485 | } |
36241b8c | 1486 | |
04d2cc77 AK |
1487 | clgi(); |
1488 | ||
1489 | local_irq_enable(); | |
36241b8c | 1490 | |
6aa8b732 | 1491 | asm volatile ( |
05b3e0c2 | 1492 | #ifdef CONFIG_X86_64 |
54a08c04 | 1493 | "push %%rbp; \n\t" |
6aa8b732 | 1494 | #else |
fe7935d4 | 1495 | "push %%ebp; \n\t" |
6aa8b732 AK |
1496 | #endif |
1497 | ||
05b3e0c2 | 1498 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
1499 | "mov %c[rbx](%[svm]), %%rbx \n\t" |
1500 | "mov %c[rcx](%[svm]), %%rcx \n\t" | |
1501 | "mov %c[rdx](%[svm]), %%rdx \n\t" | |
1502 | "mov %c[rsi](%[svm]), %%rsi \n\t" | |
1503 | "mov %c[rdi](%[svm]), %%rdi \n\t" | |
1504 | "mov %c[rbp](%[svm]), %%rbp \n\t" | |
1505 | "mov %c[r8](%[svm]), %%r8 \n\t" | |
1506 | "mov %c[r9](%[svm]), %%r9 \n\t" | |
1507 | "mov %c[r10](%[svm]), %%r10 \n\t" | |
1508 | "mov %c[r11](%[svm]), %%r11 \n\t" | |
1509 | "mov %c[r12](%[svm]), %%r12 \n\t" | |
1510 | "mov %c[r13](%[svm]), %%r13 \n\t" | |
1511 | "mov %c[r14](%[svm]), %%r14 \n\t" | |
1512 | "mov %c[r15](%[svm]), %%r15 \n\t" | |
6aa8b732 | 1513 | #else |
fb3f0f51 RR |
1514 | "mov %c[rbx](%[svm]), %%ebx \n\t" |
1515 | "mov %c[rcx](%[svm]), %%ecx \n\t" | |
1516 | "mov %c[rdx](%[svm]), %%edx \n\t" | |
1517 | "mov %c[rsi](%[svm]), %%esi \n\t" | |
1518 | "mov %c[rdi](%[svm]), %%edi \n\t" | |
1519 | "mov %c[rbp](%[svm]), %%ebp \n\t" | |
6aa8b732 AK |
1520 | #endif |
1521 | ||
05b3e0c2 | 1522 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
1523 | /* Enter guest mode */ |
1524 | "push %%rax \n\t" | |
fb3f0f51 | 1525 | "mov %c[vmcb](%[svm]), %%rax \n\t" |
6aa8b732 AK |
1526 | SVM_VMLOAD "\n\t" |
1527 | SVM_VMRUN "\n\t" | |
1528 | SVM_VMSAVE "\n\t" | |
1529 | "pop %%rax \n\t" | |
1530 | #else | |
1531 | /* Enter guest mode */ | |
1532 | "push %%eax \n\t" | |
fb3f0f51 | 1533 | "mov %c[vmcb](%[svm]), %%eax \n\t" |
6aa8b732 AK |
1534 | SVM_VMLOAD "\n\t" |
1535 | SVM_VMRUN "\n\t" | |
1536 | SVM_VMSAVE "\n\t" | |
1537 | "pop %%eax \n\t" | |
1538 | #endif | |
1539 | ||
1540 | /* Save guest registers, load host registers */ | |
05b3e0c2 | 1541 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
1542 | "mov %%rbx, %c[rbx](%[svm]) \n\t" |
1543 | "mov %%rcx, %c[rcx](%[svm]) \n\t" | |
1544 | "mov %%rdx, %c[rdx](%[svm]) \n\t" | |
1545 | "mov %%rsi, %c[rsi](%[svm]) \n\t" | |
1546 | "mov %%rdi, %c[rdi](%[svm]) \n\t" | |
1547 | "mov %%rbp, %c[rbp](%[svm]) \n\t" | |
1548 | "mov %%r8, %c[r8](%[svm]) \n\t" | |
1549 | "mov %%r9, %c[r9](%[svm]) \n\t" | |
1550 | "mov %%r10, %c[r10](%[svm]) \n\t" | |
1551 | "mov %%r11, %c[r11](%[svm]) \n\t" | |
1552 | "mov %%r12, %c[r12](%[svm]) \n\t" | |
1553 | "mov %%r13, %c[r13](%[svm]) \n\t" | |
1554 | "mov %%r14, %c[r14](%[svm]) \n\t" | |
1555 | "mov %%r15, %c[r15](%[svm]) \n\t" | |
6aa8b732 | 1556 | |
54a08c04 | 1557 | "pop %%rbp; \n\t" |
6aa8b732 | 1558 | #else |
fb3f0f51 RR |
1559 | "mov %%ebx, %c[rbx](%[svm]) \n\t" |
1560 | "mov %%ecx, %c[rcx](%[svm]) \n\t" | |
1561 | "mov %%edx, %c[rdx](%[svm]) \n\t" | |
1562 | "mov %%esi, %c[rsi](%[svm]) \n\t" | |
1563 | "mov %%edi, %c[rdi](%[svm]) \n\t" | |
1564 | "mov %%ebp, %c[rbp](%[svm]) \n\t" | |
6aa8b732 | 1565 | |
fe7935d4 | 1566 | "pop %%ebp; \n\t" |
6aa8b732 AK |
1567 | #endif |
1568 | : | |
fb3f0f51 | 1569 | : [svm]"a"(svm), |
6aa8b732 | 1570 | [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)), |
ad312c7c ZX |
1571 | [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])), |
1572 | [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])), | |
1573 | [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])), | |
1574 | [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])), | |
1575 | [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])), | |
1576 | [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP])) | |
05b3e0c2 | 1577 | #ifdef CONFIG_X86_64 |
ad312c7c ZX |
1578 | , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])), |
1579 | [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])), | |
1580 | [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])), | |
1581 | [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])), | |
1582 | [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])), | |
1583 | [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])), | |
1584 | [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])), | |
1585 | [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15])) | |
6aa8b732 | 1586 | #endif |
54a08c04 LV |
1587 | : "cc", "memory" |
1588 | #ifdef CONFIG_X86_64 | |
1589 | , "rbx", "rcx", "rdx", "rsi", "rdi" | |
1590 | , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15" | |
fe7935d4 LV |
1591 | #else |
1592 | , "ebx", "ecx", "edx" , "esi", "edi" | |
54a08c04 LV |
1593 | #endif |
1594 | ); | |
6aa8b732 | 1595 | |
a2fa3e9f GH |
1596 | if ((svm->vmcb->save.dr7 & 0xff)) |
1597 | load_db_regs(svm->host_db_regs); | |
6aa8b732 | 1598 | |
ad312c7c | 1599 | vcpu->arch.cr2 = svm->vmcb->save.cr2; |
6aa8b732 | 1600 | |
a2fa3e9f GH |
1601 | write_dr6(svm->host_dr6); |
1602 | write_dr7(svm->host_dr7); | |
1603 | kvm_write_cr2(svm->host_cr2); | |
6aa8b732 AK |
1604 | |
1605 | load_fs(fs_selector); | |
1606 | load_gs(gs_selector); | |
1607 | load_ldt(ldt_selector); | |
1608 | load_host_msrs(vcpu); | |
1609 | ||
1610 | reload_tss(vcpu); | |
1611 | ||
56ba47dd AK |
1612 | local_irq_disable(); |
1613 | ||
1614 | stgi(); | |
1615 | ||
a2fa3e9f | 1616 | svm->next_rip = 0; |
6aa8b732 AK |
1617 | } |
1618 | ||
6aa8b732 AK |
1619 | static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root) |
1620 | { | |
a2fa3e9f GH |
1621 | struct vcpu_svm *svm = to_svm(vcpu); |
1622 | ||
1623 | svm->vmcb->save.cr3 = root; | |
6aa8b732 | 1624 | force_new_asid(vcpu); |
7807fa6c AL |
1625 | |
1626 | if (vcpu->fpu_active) { | |
a2fa3e9f GH |
1627 | svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR); |
1628 | svm->vmcb->save.cr0 |= X86_CR0_TS; | |
7807fa6c AL |
1629 | vcpu->fpu_active = 0; |
1630 | } | |
6aa8b732 AK |
1631 | } |
1632 | ||
6aa8b732 AK |
1633 | static int is_disabled(void) |
1634 | { | |
6031a61c JR |
1635 | u64 vm_cr; |
1636 | ||
1637 | rdmsrl(MSR_VM_CR, vm_cr); | |
1638 | if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE)) | |
1639 | return 1; | |
1640 | ||
6aa8b732 AK |
1641 | return 0; |
1642 | } | |
1643 | ||
102d8325 IM |
1644 | static void |
1645 | svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
1646 | { | |
1647 | /* | |
1648 | * Patch in the VMMCALL instruction: | |
1649 | */ | |
1650 | hypercall[0] = 0x0f; | |
1651 | hypercall[1] = 0x01; | |
1652 | hypercall[2] = 0xd9; | |
102d8325 IM |
1653 | } |
1654 | ||
002c7f7c YS |
1655 | static void svm_check_processor_compat(void *rtn) |
1656 | { | |
1657 | *(int *)rtn = 0; | |
1658 | } | |
1659 | ||
774ead3a AK |
1660 | static bool svm_cpu_has_accelerated_tpr(void) |
1661 | { | |
1662 | return false; | |
1663 | } | |
1664 | ||
cbdd1bea | 1665 | static struct kvm_x86_ops svm_x86_ops = { |
6aa8b732 AK |
1666 | .cpu_has_kvm_support = has_svm, |
1667 | .disabled_by_bios = is_disabled, | |
1668 | .hardware_setup = svm_hardware_setup, | |
1669 | .hardware_unsetup = svm_hardware_unsetup, | |
002c7f7c | 1670 | .check_processor_compatibility = svm_check_processor_compat, |
6aa8b732 AK |
1671 | .hardware_enable = svm_hardware_enable, |
1672 | .hardware_disable = svm_hardware_disable, | |
774ead3a | 1673 | .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr, |
6aa8b732 AK |
1674 | |
1675 | .vcpu_create = svm_create_vcpu, | |
1676 | .vcpu_free = svm_free_vcpu, | |
04d2cc77 | 1677 | .vcpu_reset = svm_vcpu_reset, |
6aa8b732 | 1678 | |
04d2cc77 | 1679 | .prepare_guest_switch = svm_prepare_guest_switch, |
6aa8b732 AK |
1680 | .vcpu_load = svm_vcpu_load, |
1681 | .vcpu_put = svm_vcpu_put, | |
774c47f1 | 1682 | .vcpu_decache = svm_vcpu_decache, |
6aa8b732 AK |
1683 | |
1684 | .set_guest_debug = svm_guest_debug, | |
1685 | .get_msr = svm_get_msr, | |
1686 | .set_msr = svm_set_msr, | |
1687 | .get_segment_base = svm_get_segment_base, | |
1688 | .get_segment = svm_get_segment, | |
1689 | .set_segment = svm_set_segment, | |
1747fb71 | 1690 | .get_cs_db_l_bits = kvm_get_cs_db_l_bits, |
25c4c276 | 1691 | .decache_cr4_guest_bits = svm_decache_cr4_guest_bits, |
6aa8b732 | 1692 | .set_cr0 = svm_set_cr0, |
6aa8b732 AK |
1693 | .set_cr3 = svm_set_cr3, |
1694 | .set_cr4 = svm_set_cr4, | |
1695 | .set_efer = svm_set_efer, | |
1696 | .get_idt = svm_get_idt, | |
1697 | .set_idt = svm_set_idt, | |
1698 | .get_gdt = svm_get_gdt, | |
1699 | .set_gdt = svm_set_gdt, | |
1700 | .get_dr = svm_get_dr, | |
1701 | .set_dr = svm_set_dr, | |
1702 | .cache_regs = svm_cache_regs, | |
1703 | .decache_regs = svm_decache_regs, | |
1704 | .get_rflags = svm_get_rflags, | |
1705 | .set_rflags = svm_set_rflags, | |
1706 | ||
6aa8b732 | 1707 | .tlb_flush = svm_flush_tlb, |
6aa8b732 | 1708 | |
6aa8b732 | 1709 | .run = svm_vcpu_run, |
04d2cc77 | 1710 | .handle_exit = handle_exit, |
6aa8b732 | 1711 | .skip_emulated_instruction = skip_emulated_instruction, |
102d8325 | 1712 | .patch_hypercall = svm_patch_hypercall, |
2a8067f1 ED |
1713 | .get_irq = svm_get_irq, |
1714 | .set_irq = svm_set_irq, | |
298101da AK |
1715 | .queue_exception = svm_queue_exception, |
1716 | .exception_injected = svm_exception_injected, | |
04d2cc77 AK |
1717 | .inject_pending_irq = svm_intr_assist, |
1718 | .inject_pending_vectors = do_interrupt_requests, | |
cbc94022 IE |
1719 | |
1720 | .set_tss_addr = svm_set_tss_addr, | |
6aa8b732 AK |
1721 | }; |
1722 | ||
1723 | static int __init svm_init(void) | |
1724 | { | |
cb498ea2 | 1725 | return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm), |
c16f862d | 1726 | THIS_MODULE); |
6aa8b732 AK |
1727 | } |
1728 | ||
1729 | static void __exit svm_exit(void) | |
1730 | { | |
cb498ea2 | 1731 | kvm_exit(); |
6aa8b732 AK |
1732 | } |
1733 | ||
1734 | module_init(svm_init) | |
1735 | module_exit(svm_exit) |