Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * AMD SVM support | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
7 | * | |
8 | * Authors: | |
9 | * Yaniv Kamay <yaniv@qumranet.com> | |
10 | * Avi Kivity <avi@qumranet.com> | |
11 | * | |
12 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
13 | * the COPYING file in the top-level directory. | |
14 | * | |
15 | */ | |
edf88417 AK |
16 | #include <linux/kvm_host.h> |
17 | ||
85f455f7 | 18 | #include "irq.h" |
1d737c8a | 19 | #include "mmu.h" |
5fdbf976 | 20 | #include "kvm_cache_regs.h" |
fe4c7b19 | 21 | #include "x86.h" |
e495606d | 22 | |
6aa8b732 | 23 | #include <linux/module.h> |
9d8f549d | 24 | #include <linux/kernel.h> |
6aa8b732 AK |
25 | #include <linux/vmalloc.h> |
26 | #include <linux/highmem.h> | |
e8edc6e0 | 27 | #include <linux/sched.h> |
229456fc | 28 | #include <linux/ftrace_event.h> |
6aa8b732 | 29 | |
e495606d | 30 | #include <asm/desc.h> |
6aa8b732 | 31 | |
63d1142f | 32 | #include <asm/virtext.h> |
229456fc | 33 | #include "trace.h" |
63d1142f | 34 | |
4ecac3fd AK |
35 | #define __ex(x) __kvm_handle_fault_on_reboot(x) |
36 | ||
6aa8b732 AK |
37 | MODULE_AUTHOR("Qumranet"); |
38 | MODULE_LICENSE("GPL"); | |
39 | ||
40 | #define IOPM_ALLOC_ORDER 2 | |
41 | #define MSRPM_ALLOC_ORDER 1 | |
42 | ||
6aa8b732 AK |
43 | #define SEG_TYPE_LDT 2 |
44 | #define SEG_TYPE_BUSY_TSS16 3 | |
45 | ||
80b7706e JR |
46 | #define SVM_FEATURE_NPT (1 << 0) |
47 | #define SVM_FEATURE_LBRV (1 << 1) | |
94c935a1 | 48 | #define SVM_FEATURE_SVML (1 << 2) |
80b7706e | 49 | |
410e4d57 JR |
50 | #define NESTED_EXIT_HOST 0 /* Exit handled on host level */ |
51 | #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */ | |
52 | #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */ | |
53 | ||
24e09cbf JR |
54 | #define DEBUGCTL_RESERVED_BITS (~(0x3fULL)) |
55 | ||
c0725420 AG |
56 | /* Turn on to get debugging output*/ |
57 | /* #define NESTED_DEBUG */ | |
58 | ||
59 | #ifdef NESTED_DEBUG | |
60 | #define nsvm_printk(fmt, args...) printk(KERN_INFO fmt, ## args) | |
61 | #else | |
62 | #define nsvm_printk(fmt, args...) do {} while(0) | |
63 | #endif | |
64 | ||
6c8166a7 AK |
65 | static const u32 host_save_user_msrs[] = { |
66 | #ifdef CONFIG_X86_64 | |
67 | MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE, | |
68 | MSR_FS_BASE, | |
69 | #endif | |
70 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, | |
71 | }; | |
72 | ||
73 | #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs) | |
74 | ||
75 | struct kvm_vcpu; | |
76 | ||
e6aa9abd JR |
77 | struct nested_state { |
78 | struct vmcb *hsave; | |
79 | u64 hsave_msr; | |
80 | u64 vmcb; | |
81 | ||
82 | /* These are the merged vectors */ | |
83 | u32 *msrpm; | |
84 | ||
85 | /* gpa pointers to the real vectors */ | |
86 | u64 vmcb_msrpm; | |
aad42c64 | 87 | |
cd3ff653 JR |
88 | /* A VMEXIT is required but not yet emulated */ |
89 | bool exit_required; | |
90 | ||
aad42c64 JR |
91 | /* cache for intercepts of the guest */ |
92 | u16 intercept_cr_read; | |
93 | u16 intercept_cr_write; | |
94 | u16 intercept_dr_read; | |
95 | u16 intercept_dr_write; | |
96 | u32 intercept_exceptions; | |
97 | u64 intercept; | |
98 | ||
e6aa9abd JR |
99 | }; |
100 | ||
6c8166a7 AK |
101 | struct vcpu_svm { |
102 | struct kvm_vcpu vcpu; | |
103 | struct vmcb *vmcb; | |
104 | unsigned long vmcb_pa; | |
105 | struct svm_cpu_data *svm_data; | |
106 | uint64_t asid_generation; | |
107 | uint64_t sysenter_esp; | |
108 | uint64_t sysenter_eip; | |
109 | ||
110 | u64 next_rip; | |
111 | ||
112 | u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS]; | |
113 | u64 host_gs_base; | |
6c8166a7 AK |
114 | |
115 | u32 *msrpm; | |
6c8166a7 | 116 | |
e6aa9abd | 117 | struct nested_state nested; |
6c8166a7 AK |
118 | }; |
119 | ||
709ddebf JR |
120 | /* enable NPT for AMD64 and X86 with PAE */ |
121 | #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE) | |
122 | static bool npt_enabled = true; | |
123 | #else | |
e3da3acd | 124 | static bool npt_enabled = false; |
709ddebf | 125 | #endif |
6c7dac72 JR |
126 | static int npt = 1; |
127 | ||
128 | module_param(npt, int, S_IRUGO); | |
e3da3acd | 129 | |
4b6e4dca | 130 | static int nested = 1; |
236de055 AG |
131 | module_param(nested, int, S_IRUGO); |
132 | ||
44874f84 | 133 | static void svm_flush_tlb(struct kvm_vcpu *vcpu); |
a5c3832d | 134 | static void svm_complete_interrupts(struct vcpu_svm *svm); |
04d2cc77 | 135 | |
410e4d57 | 136 | static int nested_svm_exit_handled(struct vcpu_svm *svm); |
cf74a78b | 137 | static int nested_svm_vmexit(struct vcpu_svm *svm); |
cf74a78b AG |
138 | static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, |
139 | bool has_error_code, u32 error_code); | |
140 | ||
a2fa3e9f GH |
141 | static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu) |
142 | { | |
fb3f0f51 | 143 | return container_of(vcpu, struct vcpu_svm, vcpu); |
a2fa3e9f GH |
144 | } |
145 | ||
3d6368ef AG |
146 | static inline bool is_nested(struct vcpu_svm *svm) |
147 | { | |
e6aa9abd | 148 | return svm->nested.vmcb; |
3d6368ef AG |
149 | } |
150 | ||
2af9194d JR |
151 | static inline void enable_gif(struct vcpu_svm *svm) |
152 | { | |
153 | svm->vcpu.arch.hflags |= HF_GIF_MASK; | |
154 | } | |
155 | ||
156 | static inline void disable_gif(struct vcpu_svm *svm) | |
157 | { | |
158 | svm->vcpu.arch.hflags &= ~HF_GIF_MASK; | |
159 | } | |
160 | ||
161 | static inline bool gif_set(struct vcpu_svm *svm) | |
162 | { | |
163 | return !!(svm->vcpu.arch.hflags & HF_GIF_MASK); | |
164 | } | |
165 | ||
4866d5e3 | 166 | static unsigned long iopm_base; |
6aa8b732 AK |
167 | |
168 | struct kvm_ldttss_desc { | |
169 | u16 limit0; | |
170 | u16 base0; | |
171 | unsigned base1 : 8, type : 5, dpl : 2, p : 1; | |
172 | unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8; | |
173 | u32 base3; | |
174 | u32 zero1; | |
175 | } __attribute__((packed)); | |
176 | ||
177 | struct svm_cpu_data { | |
178 | int cpu; | |
179 | ||
5008fdf5 AK |
180 | u64 asid_generation; |
181 | u32 max_asid; | |
182 | u32 next_asid; | |
6aa8b732 AK |
183 | struct kvm_ldttss_desc *tss_desc; |
184 | ||
185 | struct page *save_area; | |
186 | }; | |
187 | ||
188 | static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data); | |
80b7706e | 189 | static uint32_t svm_features; |
6aa8b732 AK |
190 | |
191 | struct svm_init_data { | |
192 | int cpu; | |
193 | int r; | |
194 | }; | |
195 | ||
196 | static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000}; | |
197 | ||
9d8f549d | 198 | #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges) |
6aa8b732 AK |
199 | #define MSRS_RANGE_SIZE 2048 |
200 | #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2) | |
201 | ||
202 | #define MAX_INST_SIZE 15 | |
203 | ||
80b7706e JR |
204 | static inline u32 svm_has(u32 feat) |
205 | { | |
206 | return svm_features & feat; | |
207 | } | |
208 | ||
6aa8b732 AK |
209 | static inline void clgi(void) |
210 | { | |
4ecac3fd | 211 | asm volatile (__ex(SVM_CLGI)); |
6aa8b732 AK |
212 | } |
213 | ||
214 | static inline void stgi(void) | |
215 | { | |
4ecac3fd | 216 | asm volatile (__ex(SVM_STGI)); |
6aa8b732 AK |
217 | } |
218 | ||
219 | static inline void invlpga(unsigned long addr, u32 asid) | |
220 | { | |
4ecac3fd | 221 | asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid)); |
6aa8b732 AK |
222 | } |
223 | ||
6aa8b732 AK |
224 | static inline void force_new_asid(struct kvm_vcpu *vcpu) |
225 | { | |
a2fa3e9f | 226 | to_svm(vcpu)->asid_generation--; |
6aa8b732 AK |
227 | } |
228 | ||
229 | static inline void flush_guest_tlb(struct kvm_vcpu *vcpu) | |
230 | { | |
231 | force_new_asid(vcpu); | |
232 | } | |
233 | ||
234 | static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer) | |
235 | { | |
709ddebf | 236 | if (!npt_enabled && !(efer & EFER_LMA)) |
2b5203ee | 237 | efer &= ~EFER_LME; |
6aa8b732 | 238 | |
9962d032 | 239 | to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME; |
ad312c7c | 240 | vcpu->arch.shadow_efer = efer; |
6aa8b732 AK |
241 | } |
242 | ||
298101da AK |
243 | static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr, |
244 | bool has_error_code, u32 error_code) | |
245 | { | |
246 | struct vcpu_svm *svm = to_svm(vcpu); | |
247 | ||
cf74a78b AG |
248 | /* If we are within a nested VM we'd better #VMEXIT and let the |
249 | guest handle the exception */ | |
250 | if (nested_svm_check_exception(svm, nr, has_error_code, error_code)) | |
251 | return; | |
252 | ||
298101da AK |
253 | svm->vmcb->control.event_inj = nr |
254 | | SVM_EVTINJ_VALID | |
255 | | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0) | |
256 | | SVM_EVTINJ_TYPE_EXEPT; | |
257 | svm->vmcb->control.event_inj_err = error_code; | |
258 | } | |
259 | ||
6aa8b732 AK |
260 | static int is_external_interrupt(u32 info) |
261 | { | |
262 | info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID; | |
263 | return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR); | |
264 | } | |
265 | ||
2809f5d2 GC |
266 | static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) |
267 | { | |
268 | struct vcpu_svm *svm = to_svm(vcpu); | |
269 | u32 ret = 0; | |
270 | ||
271 | if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) | |
272 | ret |= X86_SHADOW_INT_STI | X86_SHADOW_INT_MOV_SS; | |
273 | return ret & mask; | |
274 | } | |
275 | ||
276 | static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) | |
277 | { | |
278 | struct vcpu_svm *svm = to_svm(vcpu); | |
279 | ||
280 | if (mask == 0) | |
281 | svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK; | |
282 | else | |
283 | svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK; | |
284 | ||
285 | } | |
286 | ||
6aa8b732 AK |
287 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) |
288 | { | |
a2fa3e9f GH |
289 | struct vcpu_svm *svm = to_svm(vcpu); |
290 | ||
291 | if (!svm->next_rip) { | |
851ba692 | 292 | if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) != |
f629cf84 GN |
293 | EMULATE_DONE) |
294 | printk(KERN_DEBUG "%s: NOP\n", __func__); | |
6aa8b732 AK |
295 | return; |
296 | } | |
5fdbf976 MT |
297 | if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE) |
298 | printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n", | |
299 | __func__, kvm_rip_read(vcpu), svm->next_rip); | |
6aa8b732 | 300 | |
5fdbf976 | 301 | kvm_rip_write(vcpu, svm->next_rip); |
2809f5d2 | 302 | svm_set_interrupt_shadow(vcpu, 0); |
6aa8b732 AK |
303 | } |
304 | ||
305 | static int has_svm(void) | |
306 | { | |
63d1142f | 307 | const char *msg; |
6aa8b732 | 308 | |
63d1142f | 309 | if (!cpu_has_svm(&msg)) { |
ff81ff10 | 310 | printk(KERN_INFO "has_svm: %s\n", msg); |
6aa8b732 AK |
311 | return 0; |
312 | } | |
313 | ||
6aa8b732 AK |
314 | return 1; |
315 | } | |
316 | ||
317 | static void svm_hardware_disable(void *garbage) | |
318 | { | |
2c8dceeb | 319 | cpu_svm_disable(); |
6aa8b732 AK |
320 | } |
321 | ||
10474ae8 | 322 | static int svm_hardware_enable(void *garbage) |
6aa8b732 AK |
323 | { |
324 | ||
325 | struct svm_cpu_data *svm_data; | |
326 | uint64_t efer; | |
b792c344 | 327 | struct descriptor_table gdt_descr; |
6aa8b732 AK |
328 | struct desc_struct *gdt; |
329 | int me = raw_smp_processor_id(); | |
330 | ||
10474ae8 AG |
331 | rdmsrl(MSR_EFER, efer); |
332 | if (efer & EFER_SVME) | |
333 | return -EBUSY; | |
334 | ||
6aa8b732 | 335 | if (!has_svm()) { |
e6732a5a ZA |
336 | printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n", |
337 | me); | |
10474ae8 | 338 | return -EINVAL; |
6aa8b732 AK |
339 | } |
340 | svm_data = per_cpu(svm_data, me); | |
341 | ||
342 | if (!svm_data) { | |
e6732a5a | 343 | printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n", |
6aa8b732 | 344 | me); |
10474ae8 | 345 | return -EINVAL; |
6aa8b732 AK |
346 | } |
347 | ||
348 | svm_data->asid_generation = 1; | |
349 | svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1; | |
350 | svm_data->next_asid = svm_data->max_asid + 1; | |
351 | ||
b792c344 AM |
352 | kvm_get_gdt(&gdt_descr); |
353 | gdt = (struct desc_struct *)gdt_descr.base; | |
6aa8b732 AK |
354 | svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS); |
355 | ||
9962d032 | 356 | wrmsrl(MSR_EFER, efer | EFER_SVME); |
6aa8b732 AK |
357 | |
358 | wrmsrl(MSR_VM_HSAVE_PA, | |
359 | page_to_pfn(svm_data->save_area) << PAGE_SHIFT); | |
10474ae8 AG |
360 | |
361 | return 0; | |
6aa8b732 AK |
362 | } |
363 | ||
0da1db75 JR |
364 | static void svm_cpu_uninit(int cpu) |
365 | { | |
366 | struct svm_cpu_data *svm_data | |
367 | = per_cpu(svm_data, raw_smp_processor_id()); | |
368 | ||
369 | if (!svm_data) | |
370 | return; | |
371 | ||
372 | per_cpu(svm_data, raw_smp_processor_id()) = NULL; | |
373 | __free_page(svm_data->save_area); | |
374 | kfree(svm_data); | |
375 | } | |
376 | ||
6aa8b732 AK |
377 | static int svm_cpu_init(int cpu) |
378 | { | |
379 | struct svm_cpu_data *svm_data; | |
380 | int r; | |
381 | ||
382 | svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL); | |
383 | if (!svm_data) | |
384 | return -ENOMEM; | |
385 | svm_data->cpu = cpu; | |
386 | svm_data->save_area = alloc_page(GFP_KERNEL); | |
387 | r = -ENOMEM; | |
388 | if (!svm_data->save_area) | |
389 | goto err_1; | |
390 | ||
391 | per_cpu(svm_data, cpu) = svm_data; | |
392 | ||
393 | return 0; | |
394 | ||
395 | err_1: | |
396 | kfree(svm_data); | |
397 | return r; | |
398 | ||
399 | } | |
400 | ||
bfc733a7 RR |
401 | static void set_msr_interception(u32 *msrpm, unsigned msr, |
402 | int read, int write) | |
6aa8b732 AK |
403 | { |
404 | int i; | |
405 | ||
406 | for (i = 0; i < NUM_MSR_MAPS; i++) { | |
407 | if (msr >= msrpm_ranges[i] && | |
408 | msr < msrpm_ranges[i] + MSRS_IN_RANGE) { | |
409 | u32 msr_offset = (i * MSRS_IN_RANGE + msr - | |
410 | msrpm_ranges[i]) * 2; | |
411 | ||
412 | u32 *base = msrpm + (msr_offset / 32); | |
413 | u32 msr_shift = msr_offset % 32; | |
414 | u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1); | |
415 | *base = (*base & ~(0x3 << msr_shift)) | | |
416 | (mask << msr_shift); | |
bfc733a7 | 417 | return; |
6aa8b732 AK |
418 | } |
419 | } | |
bfc733a7 | 420 | BUG(); |
6aa8b732 AK |
421 | } |
422 | ||
f65c229c JR |
423 | static void svm_vcpu_init_msrpm(u32 *msrpm) |
424 | { | |
425 | memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER)); | |
426 | ||
427 | #ifdef CONFIG_X86_64 | |
428 | set_msr_interception(msrpm, MSR_GS_BASE, 1, 1); | |
429 | set_msr_interception(msrpm, MSR_FS_BASE, 1, 1); | |
430 | set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1); | |
431 | set_msr_interception(msrpm, MSR_LSTAR, 1, 1); | |
432 | set_msr_interception(msrpm, MSR_CSTAR, 1, 1); | |
433 | set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1); | |
434 | #endif | |
435 | set_msr_interception(msrpm, MSR_K6_STAR, 1, 1); | |
436 | set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1); | |
f65c229c JR |
437 | } |
438 | ||
24e09cbf JR |
439 | static void svm_enable_lbrv(struct vcpu_svm *svm) |
440 | { | |
441 | u32 *msrpm = svm->msrpm; | |
442 | ||
443 | svm->vmcb->control.lbr_ctl = 1; | |
444 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1); | |
445 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1); | |
446 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1); | |
447 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1); | |
448 | } | |
449 | ||
450 | static void svm_disable_lbrv(struct vcpu_svm *svm) | |
451 | { | |
452 | u32 *msrpm = svm->msrpm; | |
453 | ||
454 | svm->vmcb->control.lbr_ctl = 0; | |
455 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0); | |
456 | set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0); | |
457 | set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0); | |
458 | set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0); | |
459 | } | |
460 | ||
6aa8b732 AK |
461 | static __init int svm_hardware_setup(void) |
462 | { | |
463 | int cpu; | |
464 | struct page *iopm_pages; | |
f65c229c | 465 | void *iopm_va; |
6aa8b732 AK |
466 | int r; |
467 | ||
6aa8b732 AK |
468 | iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER); |
469 | ||
470 | if (!iopm_pages) | |
471 | return -ENOMEM; | |
c8681339 AL |
472 | |
473 | iopm_va = page_address(iopm_pages); | |
474 | memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER)); | |
6aa8b732 AK |
475 | iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT; |
476 | ||
50a37eb4 JR |
477 | if (boot_cpu_has(X86_FEATURE_NX)) |
478 | kvm_enable_efer_bits(EFER_NX); | |
479 | ||
1b2fd70c AG |
480 | if (boot_cpu_has(X86_FEATURE_FXSR_OPT)) |
481 | kvm_enable_efer_bits(EFER_FFXSR); | |
482 | ||
236de055 AG |
483 | if (nested) { |
484 | printk(KERN_INFO "kvm: Nested Virtualization enabled\n"); | |
485 | kvm_enable_efer_bits(EFER_SVME); | |
486 | } | |
487 | ||
3230bb47 | 488 | for_each_possible_cpu(cpu) { |
6aa8b732 AK |
489 | r = svm_cpu_init(cpu); |
490 | if (r) | |
f65c229c | 491 | goto err; |
6aa8b732 | 492 | } |
33bd6a0b JR |
493 | |
494 | svm_features = cpuid_edx(SVM_CPUID_FUNC); | |
495 | ||
e3da3acd JR |
496 | if (!svm_has(SVM_FEATURE_NPT)) |
497 | npt_enabled = false; | |
498 | ||
6c7dac72 JR |
499 | if (npt_enabled && !npt) { |
500 | printk(KERN_INFO "kvm: Nested Paging disabled\n"); | |
501 | npt_enabled = false; | |
502 | } | |
503 | ||
18552672 | 504 | if (npt_enabled) { |
e3da3acd | 505 | printk(KERN_INFO "kvm: Nested Paging enabled\n"); |
18552672 | 506 | kvm_enable_tdp(); |
5f4cb662 JR |
507 | } else |
508 | kvm_disable_tdp(); | |
e3da3acd | 509 | |
6aa8b732 AK |
510 | return 0; |
511 | ||
f65c229c | 512 | err: |
6aa8b732 AK |
513 | __free_pages(iopm_pages, IOPM_ALLOC_ORDER); |
514 | iopm_base = 0; | |
515 | return r; | |
516 | } | |
517 | ||
518 | static __exit void svm_hardware_unsetup(void) | |
519 | { | |
0da1db75 JR |
520 | int cpu; |
521 | ||
3230bb47 | 522 | for_each_possible_cpu(cpu) |
0da1db75 JR |
523 | svm_cpu_uninit(cpu); |
524 | ||
6aa8b732 | 525 | __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER); |
f65c229c | 526 | iopm_base = 0; |
6aa8b732 AK |
527 | } |
528 | ||
529 | static void init_seg(struct vmcb_seg *seg) | |
530 | { | |
531 | seg->selector = 0; | |
532 | seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK | | |
533 | SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */ | |
534 | seg->limit = 0xffff; | |
535 | seg->base = 0; | |
536 | } | |
537 | ||
538 | static void init_sys_seg(struct vmcb_seg *seg, uint32_t type) | |
539 | { | |
540 | seg->selector = 0; | |
541 | seg->attrib = SVM_SELECTOR_P_MASK | type; | |
542 | seg->limit = 0xffff; | |
543 | seg->base = 0; | |
544 | } | |
545 | ||
e6101a96 | 546 | static void init_vmcb(struct vcpu_svm *svm) |
6aa8b732 | 547 | { |
e6101a96 JR |
548 | struct vmcb_control_area *control = &svm->vmcb->control; |
549 | struct vmcb_save_area *save = &svm->vmcb->save; | |
6aa8b732 AK |
550 | |
551 | control->intercept_cr_read = INTERCEPT_CR0_MASK | | |
552 | INTERCEPT_CR3_MASK | | |
649d6864 | 553 | INTERCEPT_CR4_MASK; |
6aa8b732 AK |
554 | |
555 | control->intercept_cr_write = INTERCEPT_CR0_MASK | | |
556 | INTERCEPT_CR3_MASK | | |
80a8119c AK |
557 | INTERCEPT_CR4_MASK | |
558 | INTERCEPT_CR8_MASK; | |
6aa8b732 AK |
559 | |
560 | control->intercept_dr_read = INTERCEPT_DR0_MASK | | |
561 | INTERCEPT_DR1_MASK | | |
562 | INTERCEPT_DR2_MASK | | |
563 | INTERCEPT_DR3_MASK; | |
564 | ||
565 | control->intercept_dr_write = INTERCEPT_DR0_MASK | | |
566 | INTERCEPT_DR1_MASK | | |
567 | INTERCEPT_DR2_MASK | | |
568 | INTERCEPT_DR3_MASK | | |
569 | INTERCEPT_DR5_MASK | | |
570 | INTERCEPT_DR7_MASK; | |
571 | ||
7aa81cc0 | 572 | control->intercept_exceptions = (1 << PF_VECTOR) | |
53371b50 JR |
573 | (1 << UD_VECTOR) | |
574 | (1 << MC_VECTOR); | |
6aa8b732 AK |
575 | |
576 | ||
577 | control->intercept = (1ULL << INTERCEPT_INTR) | | |
578 | (1ULL << INTERCEPT_NMI) | | |
0152527b | 579 | (1ULL << INTERCEPT_SMI) | |
6aa8b732 | 580 | (1ULL << INTERCEPT_CPUID) | |
cf5a94d1 | 581 | (1ULL << INTERCEPT_INVD) | |
6aa8b732 | 582 | (1ULL << INTERCEPT_HLT) | |
a7052897 | 583 | (1ULL << INTERCEPT_INVLPG) | |
6aa8b732 AK |
584 | (1ULL << INTERCEPT_INVLPGA) | |
585 | (1ULL << INTERCEPT_IOIO_PROT) | | |
586 | (1ULL << INTERCEPT_MSR_PROT) | | |
587 | (1ULL << INTERCEPT_TASK_SWITCH) | | |
46fe4ddd | 588 | (1ULL << INTERCEPT_SHUTDOWN) | |
6aa8b732 AK |
589 | (1ULL << INTERCEPT_VMRUN) | |
590 | (1ULL << INTERCEPT_VMMCALL) | | |
591 | (1ULL << INTERCEPT_VMLOAD) | | |
592 | (1ULL << INTERCEPT_VMSAVE) | | |
593 | (1ULL << INTERCEPT_STGI) | | |
594 | (1ULL << INTERCEPT_CLGI) | | |
916ce236 | 595 | (1ULL << INTERCEPT_SKINIT) | |
cf5a94d1 | 596 | (1ULL << INTERCEPT_WBINVD) | |
916ce236 JR |
597 | (1ULL << INTERCEPT_MONITOR) | |
598 | (1ULL << INTERCEPT_MWAIT); | |
6aa8b732 AK |
599 | |
600 | control->iopm_base_pa = iopm_base; | |
f65c229c | 601 | control->msrpm_base_pa = __pa(svm->msrpm); |
0cc5064d | 602 | control->tsc_offset = 0; |
6aa8b732 AK |
603 | control->int_ctl = V_INTR_MASKING_MASK; |
604 | ||
605 | init_seg(&save->es); | |
606 | init_seg(&save->ss); | |
607 | init_seg(&save->ds); | |
608 | init_seg(&save->fs); | |
609 | init_seg(&save->gs); | |
610 | ||
611 | save->cs.selector = 0xf000; | |
612 | /* Executable/Readable Code Segment */ | |
613 | save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK | | |
614 | SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK; | |
615 | save->cs.limit = 0xffff; | |
d92899a0 AK |
616 | /* |
617 | * cs.base should really be 0xffff0000, but vmx can't handle that, so | |
618 | * be consistent with it. | |
619 | * | |
620 | * Replace when we have real mode working for vmx. | |
621 | */ | |
622 | save->cs.base = 0xf0000; | |
6aa8b732 AK |
623 | |
624 | save->gdtr.limit = 0xffff; | |
625 | save->idtr.limit = 0xffff; | |
626 | ||
627 | init_sys_seg(&save->ldtr, SEG_TYPE_LDT); | |
628 | init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16); | |
629 | ||
9962d032 | 630 | save->efer = EFER_SVME; |
d77c26fc | 631 | save->dr6 = 0xffff0ff0; |
6aa8b732 AK |
632 | save->dr7 = 0x400; |
633 | save->rflags = 2; | |
634 | save->rip = 0x0000fff0; | |
5fdbf976 | 635 | svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip; |
6aa8b732 AK |
636 | |
637 | /* | |
638 | * cr0 val on cpu init should be 0x60000010, we enable cpu | |
639 | * cache by default. the orderly way is to enable cache in bios. | |
640 | */ | |
707d92fa | 641 | save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP; |
66aee91a | 642 | save->cr4 = X86_CR4_PAE; |
6aa8b732 | 643 | /* rdx = ?? */ |
709ddebf JR |
644 | |
645 | if (npt_enabled) { | |
646 | /* Setup VMCB for Nested Paging */ | |
647 | control->nested_ctl = 1; | |
a7052897 MT |
648 | control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) | |
649 | (1ULL << INTERCEPT_INVLPG)); | |
709ddebf JR |
650 | control->intercept_exceptions &= ~(1 << PF_VECTOR); |
651 | control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK| | |
652 | INTERCEPT_CR3_MASK); | |
653 | control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK| | |
654 | INTERCEPT_CR3_MASK); | |
655 | save->g_pat = 0x0007040600070406ULL; | |
656 | /* enable caching because the QEMU Bios doesn't enable it */ | |
657 | save->cr0 = X86_CR0_ET; | |
658 | save->cr3 = 0; | |
659 | save->cr4 = 0; | |
660 | } | |
a79d2f18 | 661 | force_new_asid(&svm->vcpu); |
1371d904 | 662 | |
e6aa9abd | 663 | svm->nested.vmcb = 0; |
2af9194d JR |
664 | svm->vcpu.arch.hflags = 0; |
665 | ||
666 | enable_gif(svm); | |
6aa8b732 AK |
667 | } |
668 | ||
e00c8cf2 | 669 | static int svm_vcpu_reset(struct kvm_vcpu *vcpu) |
04d2cc77 AK |
670 | { |
671 | struct vcpu_svm *svm = to_svm(vcpu); | |
672 | ||
e6101a96 | 673 | init_vmcb(svm); |
70433389 | 674 | |
c5af89b6 | 675 | if (!kvm_vcpu_is_bsp(vcpu)) { |
5fdbf976 | 676 | kvm_rip_write(vcpu, 0); |
ad312c7c ZX |
677 | svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12; |
678 | svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8; | |
70433389 | 679 | } |
5fdbf976 MT |
680 | vcpu->arch.regs_avail = ~0; |
681 | vcpu->arch.regs_dirty = ~0; | |
e00c8cf2 AK |
682 | |
683 | return 0; | |
04d2cc77 AK |
684 | } |
685 | ||
fb3f0f51 | 686 | static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 687 | { |
a2fa3e9f | 688 | struct vcpu_svm *svm; |
6aa8b732 | 689 | struct page *page; |
f65c229c | 690 | struct page *msrpm_pages; |
b286d5d8 | 691 | struct page *hsave_page; |
3d6368ef | 692 | struct page *nested_msrpm_pages; |
fb3f0f51 | 693 | int err; |
6aa8b732 | 694 | |
c16f862d | 695 | svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); |
fb3f0f51 RR |
696 | if (!svm) { |
697 | err = -ENOMEM; | |
698 | goto out; | |
699 | } | |
700 | ||
701 | err = kvm_vcpu_init(&svm->vcpu, kvm, id); | |
702 | if (err) | |
703 | goto free_svm; | |
704 | ||
6aa8b732 | 705 | page = alloc_page(GFP_KERNEL); |
fb3f0f51 RR |
706 | if (!page) { |
707 | err = -ENOMEM; | |
708 | goto uninit; | |
709 | } | |
6aa8b732 | 710 | |
f65c229c JR |
711 | err = -ENOMEM; |
712 | msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); | |
713 | if (!msrpm_pages) | |
714 | goto uninit; | |
3d6368ef AG |
715 | |
716 | nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); | |
717 | if (!nested_msrpm_pages) | |
718 | goto uninit; | |
719 | ||
f65c229c JR |
720 | svm->msrpm = page_address(msrpm_pages); |
721 | svm_vcpu_init_msrpm(svm->msrpm); | |
722 | ||
b286d5d8 AG |
723 | hsave_page = alloc_page(GFP_KERNEL); |
724 | if (!hsave_page) | |
725 | goto uninit; | |
e6aa9abd | 726 | svm->nested.hsave = page_address(hsave_page); |
b286d5d8 | 727 | |
e6aa9abd | 728 | svm->nested.msrpm = page_address(nested_msrpm_pages); |
3d6368ef | 729 | |
a2fa3e9f GH |
730 | svm->vmcb = page_address(page); |
731 | clear_page(svm->vmcb); | |
732 | svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT; | |
733 | svm->asid_generation = 0; | |
e6101a96 | 734 | init_vmcb(svm); |
a2fa3e9f | 735 | |
fb3f0f51 RR |
736 | fx_init(&svm->vcpu); |
737 | svm->vcpu.fpu_active = 1; | |
ad312c7c | 738 | svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE; |
c5af89b6 | 739 | if (kvm_vcpu_is_bsp(&svm->vcpu)) |
ad312c7c | 740 | svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP; |
6aa8b732 | 741 | |
fb3f0f51 | 742 | return &svm->vcpu; |
36241b8c | 743 | |
fb3f0f51 RR |
744 | uninit: |
745 | kvm_vcpu_uninit(&svm->vcpu); | |
746 | free_svm: | |
a4770347 | 747 | kmem_cache_free(kvm_vcpu_cache, svm); |
fb3f0f51 RR |
748 | out: |
749 | return ERR_PTR(err); | |
6aa8b732 AK |
750 | } |
751 | ||
752 | static void svm_free_vcpu(struct kvm_vcpu *vcpu) | |
753 | { | |
a2fa3e9f GH |
754 | struct vcpu_svm *svm = to_svm(vcpu); |
755 | ||
fb3f0f51 | 756 | __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT)); |
f65c229c | 757 | __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER); |
e6aa9abd JR |
758 | __free_page(virt_to_page(svm->nested.hsave)); |
759 | __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER); | |
fb3f0f51 | 760 | kvm_vcpu_uninit(vcpu); |
a4770347 | 761 | kmem_cache_free(kvm_vcpu_cache, svm); |
6aa8b732 AK |
762 | } |
763 | ||
15ad7146 | 764 | static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 765 | { |
a2fa3e9f | 766 | struct vcpu_svm *svm = to_svm(vcpu); |
15ad7146 | 767 | int i; |
0cc5064d | 768 | |
0cc5064d | 769 | if (unlikely(cpu != vcpu->cpu)) { |
e935d48e | 770 | u64 delta; |
0cc5064d AK |
771 | |
772 | /* | |
773 | * Make sure that the guest sees a monotonically | |
774 | * increasing TSC. | |
775 | */ | |
e935d48e | 776 | delta = vcpu->arch.host_tsc - native_read_tsc(); |
a2fa3e9f | 777 | svm->vmcb->control.tsc_offset += delta; |
77b1ab17 JR |
778 | if (is_nested(svm)) |
779 | svm->nested.hsave->control.tsc_offset += delta; | |
0cc5064d | 780 | vcpu->cpu = cpu; |
2f599714 | 781 | kvm_migrate_timers(vcpu); |
4b656b12 | 782 | svm->asid_generation = 0; |
0cc5064d | 783 | } |
94dfbdb3 AL |
784 | |
785 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) | |
a2fa3e9f | 786 | rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
6aa8b732 AK |
787 | } |
788 | ||
789 | static void svm_vcpu_put(struct kvm_vcpu *vcpu) | |
790 | { | |
a2fa3e9f | 791 | struct vcpu_svm *svm = to_svm(vcpu); |
94dfbdb3 AL |
792 | int i; |
793 | ||
e1beb1d3 | 794 | ++vcpu->stat.host_state_reload; |
94dfbdb3 | 795 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) |
a2fa3e9f | 796 | wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
94dfbdb3 | 797 | |
e935d48e | 798 | vcpu->arch.host_tsc = native_read_tsc(); |
6aa8b732 AK |
799 | } |
800 | ||
6aa8b732 AK |
801 | static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu) |
802 | { | |
a2fa3e9f | 803 | return to_svm(vcpu)->vmcb->save.rflags; |
6aa8b732 AK |
804 | } |
805 | ||
806 | static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
807 | { | |
a2fa3e9f | 808 | to_svm(vcpu)->vmcb->save.rflags = rflags; |
6aa8b732 AK |
809 | } |
810 | ||
6de4f3ad AK |
811 | static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) |
812 | { | |
813 | switch (reg) { | |
814 | case VCPU_EXREG_PDPTR: | |
815 | BUG_ON(!npt_enabled); | |
816 | load_pdptrs(vcpu, vcpu->arch.cr3); | |
817 | break; | |
818 | default: | |
819 | BUG(); | |
820 | } | |
821 | } | |
822 | ||
f0b85051 AG |
823 | static void svm_set_vintr(struct vcpu_svm *svm) |
824 | { | |
825 | svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR; | |
826 | } | |
827 | ||
828 | static void svm_clear_vintr(struct vcpu_svm *svm) | |
829 | { | |
830 | svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR); | |
831 | } | |
832 | ||
6aa8b732 AK |
833 | static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg) |
834 | { | |
a2fa3e9f | 835 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; |
6aa8b732 AK |
836 | |
837 | switch (seg) { | |
838 | case VCPU_SREG_CS: return &save->cs; | |
839 | case VCPU_SREG_DS: return &save->ds; | |
840 | case VCPU_SREG_ES: return &save->es; | |
841 | case VCPU_SREG_FS: return &save->fs; | |
842 | case VCPU_SREG_GS: return &save->gs; | |
843 | case VCPU_SREG_SS: return &save->ss; | |
844 | case VCPU_SREG_TR: return &save->tr; | |
845 | case VCPU_SREG_LDTR: return &save->ldtr; | |
846 | } | |
847 | BUG(); | |
8b6d44c7 | 848 | return NULL; |
6aa8b732 AK |
849 | } |
850 | ||
851 | static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg) | |
852 | { | |
853 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
854 | ||
855 | return s->base; | |
856 | } | |
857 | ||
858 | static void svm_get_segment(struct kvm_vcpu *vcpu, | |
859 | struct kvm_segment *var, int seg) | |
860 | { | |
861 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
862 | ||
863 | var->base = s->base; | |
864 | var->limit = s->limit; | |
865 | var->selector = s->selector; | |
866 | var->type = s->attrib & SVM_SELECTOR_TYPE_MASK; | |
867 | var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1; | |
868 | var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3; | |
869 | var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1; | |
870 | var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1; | |
871 | var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1; | |
872 | var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1; | |
873 | var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1; | |
25022acc | 874 | |
19bca6ab AP |
875 | /* AMD's VMCB does not have an explicit unusable field, so emulate it |
876 | * for cross vendor migration purposes by "not present" | |
877 | */ | |
878 | var->unusable = !var->present || (var->type == 0); | |
879 | ||
1fbdc7a5 AP |
880 | switch (seg) { |
881 | case VCPU_SREG_CS: | |
882 | /* | |
883 | * SVM always stores 0 for the 'G' bit in the CS selector in | |
884 | * the VMCB on a VMEXIT. This hurts cross-vendor migration: | |
885 | * Intel's VMENTRY has a check on the 'G' bit. | |
886 | */ | |
25022acc | 887 | var->g = s->limit > 0xfffff; |
1fbdc7a5 AP |
888 | break; |
889 | case VCPU_SREG_TR: | |
890 | /* | |
891 | * Work around a bug where the busy flag in the tr selector | |
892 | * isn't exposed | |
893 | */ | |
c0d09828 | 894 | var->type |= 0x2; |
1fbdc7a5 AP |
895 | break; |
896 | case VCPU_SREG_DS: | |
897 | case VCPU_SREG_ES: | |
898 | case VCPU_SREG_FS: | |
899 | case VCPU_SREG_GS: | |
900 | /* | |
901 | * The accessed bit must always be set in the segment | |
902 | * descriptor cache, although it can be cleared in the | |
903 | * descriptor, the cached bit always remains at 1. Since | |
904 | * Intel has a check on this, set it here to support | |
905 | * cross-vendor migration. | |
906 | */ | |
907 | if (!var->unusable) | |
908 | var->type |= 0x1; | |
909 | break; | |
b586eb02 AP |
910 | case VCPU_SREG_SS: |
911 | /* On AMD CPUs sometimes the DB bit in the segment | |
912 | * descriptor is left as 1, although the whole segment has | |
913 | * been made unusable. Clear it here to pass an Intel VMX | |
914 | * entry check when cross vendor migrating. | |
915 | */ | |
916 | if (var->unusable) | |
917 | var->db = 0; | |
918 | break; | |
1fbdc7a5 | 919 | } |
6aa8b732 AK |
920 | } |
921 | ||
2e4d2653 IE |
922 | static int svm_get_cpl(struct kvm_vcpu *vcpu) |
923 | { | |
924 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; | |
925 | ||
926 | return save->cpl; | |
927 | } | |
928 | ||
6aa8b732 AK |
929 | static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) |
930 | { | |
a2fa3e9f GH |
931 | struct vcpu_svm *svm = to_svm(vcpu); |
932 | ||
933 | dt->limit = svm->vmcb->save.idtr.limit; | |
934 | dt->base = svm->vmcb->save.idtr.base; | |
6aa8b732 AK |
935 | } |
936 | ||
937 | static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
938 | { | |
a2fa3e9f GH |
939 | struct vcpu_svm *svm = to_svm(vcpu); |
940 | ||
941 | svm->vmcb->save.idtr.limit = dt->limit; | |
942 | svm->vmcb->save.idtr.base = dt->base ; | |
6aa8b732 AK |
943 | } |
944 | ||
945 | static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
946 | { | |
a2fa3e9f GH |
947 | struct vcpu_svm *svm = to_svm(vcpu); |
948 | ||
949 | dt->limit = svm->vmcb->save.gdtr.limit; | |
950 | dt->base = svm->vmcb->save.gdtr.base; | |
6aa8b732 AK |
951 | } |
952 | ||
953 | static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
954 | { | |
a2fa3e9f GH |
955 | struct vcpu_svm *svm = to_svm(vcpu); |
956 | ||
957 | svm->vmcb->save.gdtr.limit = dt->limit; | |
958 | svm->vmcb->save.gdtr.base = dt->base ; | |
6aa8b732 AK |
959 | } |
960 | ||
25c4c276 | 961 | static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 AK |
962 | { |
963 | } | |
964 | ||
6aa8b732 AK |
965 | static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
966 | { | |
a2fa3e9f GH |
967 | struct vcpu_svm *svm = to_svm(vcpu); |
968 | ||
05b3e0c2 | 969 | #ifdef CONFIG_X86_64 |
ad312c7c | 970 | if (vcpu->arch.shadow_efer & EFER_LME) { |
707d92fa | 971 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { |
ad312c7c | 972 | vcpu->arch.shadow_efer |= EFER_LMA; |
2b5203ee | 973 | svm->vmcb->save.efer |= EFER_LMA | EFER_LME; |
6aa8b732 AK |
974 | } |
975 | ||
d77c26fc | 976 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) { |
ad312c7c | 977 | vcpu->arch.shadow_efer &= ~EFER_LMA; |
2b5203ee | 978 | svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME); |
6aa8b732 AK |
979 | } |
980 | } | |
981 | #endif | |
709ddebf JR |
982 | if (npt_enabled) |
983 | goto set; | |
984 | ||
ad312c7c | 985 | if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) { |
a2fa3e9f | 986 | svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR); |
7807fa6c AL |
987 | vcpu->fpu_active = 1; |
988 | } | |
989 | ||
ad312c7c | 990 | vcpu->arch.cr0 = cr0; |
707d92fa | 991 | cr0 |= X86_CR0_PG | X86_CR0_WP; |
6b390b63 JR |
992 | if (!vcpu->fpu_active) { |
993 | svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR); | |
334df50a | 994 | cr0 |= X86_CR0_TS; |
6b390b63 | 995 | } |
709ddebf JR |
996 | set: |
997 | /* | |
998 | * re-enable caching here because the QEMU bios | |
999 | * does not do it - this results in some delay at | |
1000 | * reboot | |
1001 | */ | |
1002 | cr0 &= ~(X86_CR0_CD | X86_CR0_NW); | |
a2fa3e9f | 1003 | svm->vmcb->save.cr0 = cr0; |
6aa8b732 AK |
1004 | } |
1005 | ||
1006 | static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) | |
1007 | { | |
6394b649 | 1008 | unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE; |
e5eab0ce JR |
1009 | unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4; |
1010 | ||
1011 | if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE)) | |
1012 | force_new_asid(vcpu); | |
6394b649 | 1013 | |
ec077263 JR |
1014 | vcpu->arch.cr4 = cr4; |
1015 | if (!npt_enabled) | |
1016 | cr4 |= X86_CR4_PAE; | |
6394b649 | 1017 | cr4 |= host_cr4_mce; |
ec077263 | 1018 | to_svm(vcpu)->vmcb->save.cr4 = cr4; |
6aa8b732 AK |
1019 | } |
1020 | ||
1021 | static void svm_set_segment(struct kvm_vcpu *vcpu, | |
1022 | struct kvm_segment *var, int seg) | |
1023 | { | |
a2fa3e9f | 1024 | struct vcpu_svm *svm = to_svm(vcpu); |
6aa8b732 AK |
1025 | struct vmcb_seg *s = svm_seg(vcpu, seg); |
1026 | ||
1027 | s->base = var->base; | |
1028 | s->limit = var->limit; | |
1029 | s->selector = var->selector; | |
1030 | if (var->unusable) | |
1031 | s->attrib = 0; | |
1032 | else { | |
1033 | s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK); | |
1034 | s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT; | |
1035 | s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT; | |
1036 | s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT; | |
1037 | s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT; | |
1038 | s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT; | |
1039 | s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT; | |
1040 | s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT; | |
1041 | } | |
1042 | if (seg == VCPU_SREG_CS) | |
a2fa3e9f GH |
1043 | svm->vmcb->save.cpl |
1044 | = (svm->vmcb->save.cs.attrib | |
6aa8b732 AK |
1045 | >> SVM_SELECTOR_DPL_SHIFT) & 3; |
1046 | ||
1047 | } | |
1048 | ||
44c11430 | 1049 | static void update_db_intercept(struct kvm_vcpu *vcpu) |
6aa8b732 | 1050 | { |
d0bfb940 JK |
1051 | struct vcpu_svm *svm = to_svm(vcpu); |
1052 | ||
d0bfb940 JK |
1053 | svm->vmcb->control.intercept_exceptions &= |
1054 | ~((1 << DB_VECTOR) | (1 << BP_VECTOR)); | |
44c11430 GN |
1055 | |
1056 | if (vcpu->arch.singlestep) | |
1057 | svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR); | |
1058 | ||
d0bfb940 JK |
1059 | if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) { |
1060 | if (vcpu->guest_debug & | |
1061 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) | |
1062 | svm->vmcb->control.intercept_exceptions |= | |
1063 | 1 << DB_VECTOR; | |
1064 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) | |
1065 | svm->vmcb->control.intercept_exceptions |= | |
1066 | 1 << BP_VECTOR; | |
1067 | } else | |
1068 | vcpu->guest_debug = 0; | |
44c11430 GN |
1069 | } |
1070 | ||
355be0b9 | 1071 | static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg) |
44c11430 | 1072 | { |
44c11430 GN |
1073 | struct vcpu_svm *svm = to_svm(vcpu); |
1074 | ||
ae675ef0 JK |
1075 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) |
1076 | svm->vmcb->save.dr7 = dbg->arch.debugreg[7]; | |
1077 | else | |
1078 | svm->vmcb->save.dr7 = vcpu->arch.dr7; | |
1079 | ||
355be0b9 | 1080 | update_db_intercept(vcpu); |
6aa8b732 AK |
1081 | } |
1082 | ||
1083 | static void load_host_msrs(struct kvm_vcpu *vcpu) | |
1084 | { | |
94dfbdb3 | 1085 | #ifdef CONFIG_X86_64 |
a2fa3e9f | 1086 | wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base); |
94dfbdb3 | 1087 | #endif |
6aa8b732 AK |
1088 | } |
1089 | ||
1090 | static void save_host_msrs(struct kvm_vcpu *vcpu) | |
1091 | { | |
94dfbdb3 | 1092 | #ifdef CONFIG_X86_64 |
a2fa3e9f | 1093 | rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base); |
94dfbdb3 | 1094 | #endif |
6aa8b732 AK |
1095 | } |
1096 | ||
e756fc62 | 1097 | static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data) |
6aa8b732 AK |
1098 | { |
1099 | if (svm_data->next_asid > svm_data->max_asid) { | |
1100 | ++svm_data->asid_generation; | |
1101 | svm_data->next_asid = 1; | |
a2fa3e9f | 1102 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID; |
6aa8b732 AK |
1103 | } |
1104 | ||
a2fa3e9f GH |
1105 | svm->asid_generation = svm_data->asid_generation; |
1106 | svm->vmcb->control.asid = svm_data->next_asid++; | |
6aa8b732 AK |
1107 | } |
1108 | ||
6aa8b732 AK |
1109 | static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr) |
1110 | { | |
42dbaa5a JK |
1111 | struct vcpu_svm *svm = to_svm(vcpu); |
1112 | unsigned long val; | |
1113 | ||
1114 | switch (dr) { | |
1115 | case 0 ... 3: | |
1116 | val = vcpu->arch.db[dr]; | |
1117 | break; | |
1118 | case 6: | |
1119 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) | |
1120 | val = vcpu->arch.dr6; | |
1121 | else | |
1122 | val = svm->vmcb->save.dr6; | |
1123 | break; | |
1124 | case 7: | |
1125 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) | |
1126 | val = vcpu->arch.dr7; | |
1127 | else | |
1128 | val = svm->vmcb->save.dr7; | |
1129 | break; | |
1130 | default: | |
1131 | val = 0; | |
1132 | } | |
1133 | ||
af9ca2d7 | 1134 | return val; |
6aa8b732 AK |
1135 | } |
1136 | ||
1137 | static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value, | |
1138 | int *exception) | |
1139 | { | |
a2fa3e9f GH |
1140 | struct vcpu_svm *svm = to_svm(vcpu); |
1141 | ||
42dbaa5a | 1142 | *exception = 0; |
6aa8b732 AK |
1143 | |
1144 | switch (dr) { | |
1145 | case 0 ... 3: | |
42dbaa5a JK |
1146 | vcpu->arch.db[dr] = value; |
1147 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) | |
1148 | vcpu->arch.eff_db[dr] = value; | |
6aa8b732 AK |
1149 | return; |
1150 | case 4 ... 5: | |
42dbaa5a | 1151 | if (vcpu->arch.cr4 & X86_CR4_DE) |
6aa8b732 | 1152 | *exception = UD_VECTOR; |
42dbaa5a JK |
1153 | return; |
1154 | case 6: | |
1155 | if (value & 0xffffffff00000000ULL) { | |
1156 | *exception = GP_VECTOR; | |
6aa8b732 AK |
1157 | return; |
1158 | } | |
42dbaa5a JK |
1159 | vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1; |
1160 | return; | |
1161 | case 7: | |
1162 | if (value & 0xffffffff00000000ULL) { | |
6aa8b732 AK |
1163 | *exception = GP_VECTOR; |
1164 | return; | |
1165 | } | |
42dbaa5a JK |
1166 | vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1; |
1167 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { | |
1168 | svm->vmcb->save.dr7 = vcpu->arch.dr7; | |
1169 | vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK); | |
1170 | } | |
6aa8b732 | 1171 | return; |
6aa8b732 | 1172 | default: |
42dbaa5a | 1173 | /* FIXME: Possible case? */ |
6aa8b732 | 1174 | printk(KERN_DEBUG "%s: unexpected dr %u\n", |
b8688d51 | 1175 | __func__, dr); |
6aa8b732 AK |
1176 | *exception = UD_VECTOR; |
1177 | return; | |
1178 | } | |
1179 | } | |
1180 | ||
851ba692 | 1181 | static int pf_interception(struct vcpu_svm *svm) |
6aa8b732 | 1182 | { |
6aa8b732 AK |
1183 | u64 fault_address; |
1184 | u32 error_code; | |
6aa8b732 | 1185 | |
a2fa3e9f GH |
1186 | fault_address = svm->vmcb->control.exit_info_2; |
1187 | error_code = svm->vmcb->control.exit_info_1; | |
af9ca2d7 | 1188 | |
229456fc | 1189 | trace_kvm_page_fault(fault_address, error_code); |
52c7847d AK |
1190 | if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu)) |
1191 | kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address); | |
3067714c | 1192 | return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code); |
6aa8b732 AK |
1193 | } |
1194 | ||
851ba692 | 1195 | static int db_interception(struct vcpu_svm *svm) |
d0bfb940 | 1196 | { |
851ba692 AK |
1197 | struct kvm_run *kvm_run = svm->vcpu.run; |
1198 | ||
d0bfb940 | 1199 | if (!(svm->vcpu.guest_debug & |
44c11430 GN |
1200 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) && |
1201 | !svm->vcpu.arch.singlestep) { | |
d0bfb940 JK |
1202 | kvm_queue_exception(&svm->vcpu, DB_VECTOR); |
1203 | return 1; | |
1204 | } | |
44c11430 GN |
1205 | |
1206 | if (svm->vcpu.arch.singlestep) { | |
1207 | svm->vcpu.arch.singlestep = false; | |
1208 | if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) | |
1209 | svm->vmcb->save.rflags &= | |
1210 | ~(X86_EFLAGS_TF | X86_EFLAGS_RF); | |
1211 | update_db_intercept(&svm->vcpu); | |
1212 | } | |
1213 | ||
1214 | if (svm->vcpu.guest_debug & | |
1215 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)){ | |
1216 | kvm_run->exit_reason = KVM_EXIT_DEBUG; | |
1217 | kvm_run->debug.arch.pc = | |
1218 | svm->vmcb->save.cs.base + svm->vmcb->save.rip; | |
1219 | kvm_run->debug.arch.exception = DB_VECTOR; | |
1220 | return 0; | |
1221 | } | |
1222 | ||
1223 | return 1; | |
d0bfb940 JK |
1224 | } |
1225 | ||
851ba692 | 1226 | static int bp_interception(struct vcpu_svm *svm) |
d0bfb940 | 1227 | { |
851ba692 AK |
1228 | struct kvm_run *kvm_run = svm->vcpu.run; |
1229 | ||
d0bfb940 JK |
1230 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
1231 | kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip; | |
1232 | kvm_run->debug.arch.exception = BP_VECTOR; | |
1233 | return 0; | |
1234 | } | |
1235 | ||
851ba692 | 1236 | static int ud_interception(struct vcpu_svm *svm) |
7aa81cc0 AL |
1237 | { |
1238 | int er; | |
1239 | ||
851ba692 | 1240 | er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD); |
7aa81cc0 | 1241 | if (er != EMULATE_DONE) |
7ee5d940 | 1242 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
7aa81cc0 AL |
1243 | return 1; |
1244 | } | |
1245 | ||
851ba692 | 1246 | static int nm_interception(struct vcpu_svm *svm) |
7807fa6c | 1247 | { |
a2fa3e9f | 1248 | svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR); |
ad312c7c | 1249 | if (!(svm->vcpu.arch.cr0 & X86_CR0_TS)) |
a2fa3e9f | 1250 | svm->vmcb->save.cr0 &= ~X86_CR0_TS; |
e756fc62 | 1251 | svm->vcpu.fpu_active = 1; |
a2fa3e9f GH |
1252 | |
1253 | return 1; | |
7807fa6c AL |
1254 | } |
1255 | ||
851ba692 | 1256 | static int mc_interception(struct vcpu_svm *svm) |
53371b50 JR |
1257 | { |
1258 | /* | |
1259 | * On an #MC intercept the MCE handler is not called automatically in | |
1260 | * the host. So do it by hand here. | |
1261 | */ | |
1262 | asm volatile ( | |
1263 | "int $0x12\n"); | |
1264 | /* not sure if we ever come back to this point */ | |
1265 | ||
1266 | return 1; | |
1267 | } | |
1268 | ||
851ba692 | 1269 | static int shutdown_interception(struct vcpu_svm *svm) |
46fe4ddd | 1270 | { |
851ba692 AK |
1271 | struct kvm_run *kvm_run = svm->vcpu.run; |
1272 | ||
46fe4ddd JR |
1273 | /* |
1274 | * VMCB is undefined after a SHUTDOWN intercept | |
1275 | * so reinitialize it. | |
1276 | */ | |
a2fa3e9f | 1277 | clear_page(svm->vmcb); |
e6101a96 | 1278 | init_vmcb(svm); |
46fe4ddd JR |
1279 | |
1280 | kvm_run->exit_reason = KVM_EXIT_SHUTDOWN; | |
1281 | return 0; | |
1282 | } | |
1283 | ||
851ba692 | 1284 | static int io_interception(struct vcpu_svm *svm) |
6aa8b732 | 1285 | { |
d77c26fc | 1286 | u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */ |
34c33d16 | 1287 | int size, in, string; |
039576c0 | 1288 | unsigned port; |
6aa8b732 | 1289 | |
e756fc62 | 1290 | ++svm->vcpu.stat.io_exits; |
6aa8b732 | 1291 | |
a2fa3e9f | 1292 | svm->next_rip = svm->vmcb->control.exit_info_2; |
6aa8b732 | 1293 | |
e70669ab LV |
1294 | string = (io_info & SVM_IOIO_STR_MASK) != 0; |
1295 | ||
1296 | if (string) { | |
3427318f | 1297 | if (emulate_instruction(&svm->vcpu, |
851ba692 | 1298 | 0, 0, 0) == EMULATE_DO_MMIO) |
e70669ab LV |
1299 | return 0; |
1300 | return 1; | |
1301 | } | |
1302 | ||
039576c0 AK |
1303 | in = (io_info & SVM_IOIO_TYPE_MASK) != 0; |
1304 | port = io_info >> 16; | |
1305 | size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT; | |
6aa8b732 | 1306 | |
e93f36bc | 1307 | skip_emulated_instruction(&svm->vcpu); |
851ba692 | 1308 | return kvm_emulate_pio(&svm->vcpu, in, size, port); |
6aa8b732 AK |
1309 | } |
1310 | ||
851ba692 | 1311 | static int nmi_interception(struct vcpu_svm *svm) |
c47f098d JR |
1312 | { |
1313 | return 1; | |
1314 | } | |
1315 | ||
851ba692 | 1316 | static int intr_interception(struct vcpu_svm *svm) |
a0698055 JR |
1317 | { |
1318 | ++svm->vcpu.stat.irq_exits; | |
1319 | return 1; | |
1320 | } | |
1321 | ||
851ba692 | 1322 | static int nop_on_interception(struct vcpu_svm *svm) |
6aa8b732 AK |
1323 | { |
1324 | return 1; | |
1325 | } | |
1326 | ||
851ba692 | 1327 | static int halt_interception(struct vcpu_svm *svm) |
6aa8b732 | 1328 | { |
5fdbf976 | 1329 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 1; |
e756fc62 RR |
1330 | skip_emulated_instruction(&svm->vcpu); |
1331 | return kvm_emulate_halt(&svm->vcpu); | |
6aa8b732 AK |
1332 | } |
1333 | ||
851ba692 | 1334 | static int vmmcall_interception(struct vcpu_svm *svm) |
02e235bc | 1335 | { |
5fdbf976 | 1336 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; |
e756fc62 | 1337 | skip_emulated_instruction(&svm->vcpu); |
7aa81cc0 AL |
1338 | kvm_emulate_hypercall(&svm->vcpu); |
1339 | return 1; | |
02e235bc AK |
1340 | } |
1341 | ||
c0725420 AG |
1342 | static int nested_svm_check_permissions(struct vcpu_svm *svm) |
1343 | { | |
1344 | if (!(svm->vcpu.arch.shadow_efer & EFER_SVME) | |
1345 | || !is_paging(&svm->vcpu)) { | |
1346 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); | |
1347 | return 1; | |
1348 | } | |
1349 | ||
1350 | if (svm->vmcb->save.cpl) { | |
1351 | kvm_inject_gp(&svm->vcpu, 0); | |
1352 | return 1; | |
1353 | } | |
1354 | ||
1355 | return 0; | |
1356 | } | |
1357 | ||
cf74a78b AG |
1358 | static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, |
1359 | bool has_error_code, u32 error_code) | |
1360 | { | |
0295ad7d JR |
1361 | if (!is_nested(svm)) |
1362 | return 0; | |
cf74a78b | 1363 | |
0295ad7d JR |
1364 | svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr; |
1365 | svm->vmcb->control.exit_code_hi = 0; | |
1366 | svm->vmcb->control.exit_info_1 = error_code; | |
1367 | svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2; | |
1368 | ||
410e4d57 | 1369 | return nested_svm_exit_handled(svm); |
cf74a78b AG |
1370 | } |
1371 | ||
1372 | static inline int nested_svm_intr(struct vcpu_svm *svm) | |
1373 | { | |
26666957 JR |
1374 | if (!is_nested(svm)) |
1375 | return 0; | |
cf74a78b | 1376 | |
26666957 JR |
1377 | if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK)) |
1378 | return 0; | |
cf74a78b | 1379 | |
26666957 JR |
1380 | if (!(svm->vcpu.arch.hflags & HF_HIF_MASK)) |
1381 | return 0; | |
cf74a78b | 1382 | |
26666957 JR |
1383 | svm->vmcb->control.exit_code = SVM_EXIT_INTR; |
1384 | ||
cd3ff653 JR |
1385 | if (svm->nested.intercept & 1ULL) { |
1386 | /* | |
1387 | * The #vmexit can't be emulated here directly because this | |
1388 | * code path runs with irqs and preemtion disabled. A | |
1389 | * #vmexit emulation might sleep. Only signal request for | |
1390 | * the #vmexit here. | |
1391 | */ | |
1392 | svm->nested.exit_required = true; | |
236649de | 1393 | trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip); |
26666957 | 1394 | return 1; |
cf74a78b AG |
1395 | } |
1396 | ||
1397 | return 0; | |
1398 | } | |
1399 | ||
34f80cfa JR |
1400 | static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, enum km_type idx) |
1401 | { | |
1402 | struct page *page; | |
1403 | ||
34f80cfa | 1404 | page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT); |
34f80cfa JR |
1405 | if (is_error_page(page)) |
1406 | goto error; | |
1407 | ||
1408 | return kmap_atomic(page, idx); | |
1409 | ||
1410 | error: | |
1411 | kvm_release_page_clean(page); | |
1412 | kvm_inject_gp(&svm->vcpu, 0); | |
1413 | ||
1414 | return NULL; | |
1415 | } | |
1416 | ||
1417 | static void nested_svm_unmap(void *addr, enum km_type idx) | |
1418 | { | |
1419 | struct page *page; | |
1420 | ||
1421 | if (!addr) | |
1422 | return; | |
1423 | ||
1424 | page = kmap_atomic_to_page(addr); | |
1425 | ||
1426 | kunmap_atomic(addr, idx); | |
1427 | kvm_release_page_dirty(page); | |
1428 | } | |
1429 | ||
3d62d9aa | 1430 | static bool nested_svm_exit_handled_msr(struct vcpu_svm *svm) |
4c2161ae | 1431 | { |
4c2161ae | 1432 | u32 param = svm->vmcb->control.exit_info_1 & 1; |
3d62d9aa JR |
1433 | u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
1434 | bool ret = false; | |
1435 | u32 t0, t1; | |
1436 | u8 *msrpm; | |
4c2161ae | 1437 | |
3d62d9aa JR |
1438 | if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT))) |
1439 | return false; | |
1440 | ||
1441 | msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, KM_USER0); | |
1442 | ||
1443 | if (!msrpm) | |
1444 | goto out; | |
4c2161ae JR |
1445 | |
1446 | switch (msr) { | |
1447 | case 0 ... 0x1fff: | |
1448 | t0 = (msr * 2) % 8; | |
1449 | t1 = msr / 8; | |
1450 | break; | |
1451 | case 0xc0000000 ... 0xc0001fff: | |
1452 | t0 = (8192 + msr - 0xc0000000) * 2; | |
1453 | t1 = (t0 / 8); | |
1454 | t0 %= 8; | |
1455 | break; | |
1456 | case 0xc0010000 ... 0xc0011fff: | |
1457 | t0 = (16384 + msr - 0xc0010000) * 2; | |
1458 | t1 = (t0 / 8); | |
1459 | t0 %= 8; | |
1460 | break; | |
1461 | default: | |
3d62d9aa JR |
1462 | ret = true; |
1463 | goto out; | |
4c2161ae | 1464 | } |
4c2161ae | 1465 | |
3d62d9aa JR |
1466 | ret = msrpm[t1] & ((1 << param) << t0); |
1467 | ||
1468 | out: | |
1469 | nested_svm_unmap(msrpm, KM_USER0); | |
1470 | ||
1471 | return ret; | |
4c2161ae JR |
1472 | } |
1473 | ||
410e4d57 | 1474 | static int nested_svm_exit_special(struct vcpu_svm *svm) |
cf74a78b | 1475 | { |
cf74a78b | 1476 | u32 exit_code = svm->vmcb->control.exit_code; |
4c2161ae | 1477 | |
410e4d57 JR |
1478 | switch (exit_code) { |
1479 | case SVM_EXIT_INTR: | |
1480 | case SVM_EXIT_NMI: | |
1481 | return NESTED_EXIT_HOST; | |
cf74a78b | 1482 | /* For now we are always handling NPFs when using them */ |
410e4d57 JR |
1483 | case SVM_EXIT_NPF: |
1484 | if (npt_enabled) | |
1485 | return NESTED_EXIT_HOST; | |
1486 | break; | |
1487 | /* When we're shadowing, trap PFs */ | |
1488 | case SVM_EXIT_EXCP_BASE + PF_VECTOR: | |
1489 | if (!npt_enabled) | |
1490 | return NESTED_EXIT_HOST; | |
1491 | break; | |
1492 | default: | |
1493 | break; | |
cf74a78b AG |
1494 | } |
1495 | ||
410e4d57 JR |
1496 | return NESTED_EXIT_CONTINUE; |
1497 | } | |
1498 | ||
1499 | /* | |
1500 | * If this function returns true, this #vmexit was already handled | |
1501 | */ | |
1502 | static int nested_svm_exit_handled(struct vcpu_svm *svm) | |
1503 | { | |
1504 | u32 exit_code = svm->vmcb->control.exit_code; | |
1505 | int vmexit = NESTED_EXIT_HOST; | |
1506 | ||
cf74a78b | 1507 | switch (exit_code) { |
9c4e40b9 | 1508 | case SVM_EXIT_MSR: |
3d62d9aa | 1509 | vmexit = nested_svm_exit_handled_msr(svm); |
9c4e40b9 | 1510 | break; |
cf74a78b AG |
1511 | case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: { |
1512 | u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0); | |
aad42c64 | 1513 | if (svm->nested.intercept_cr_read & cr_bits) |
410e4d57 | 1514 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
1515 | break; |
1516 | } | |
1517 | case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: { | |
1518 | u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0); | |
aad42c64 | 1519 | if (svm->nested.intercept_cr_write & cr_bits) |
410e4d57 | 1520 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
1521 | break; |
1522 | } | |
1523 | case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: { | |
1524 | u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0); | |
aad42c64 | 1525 | if (svm->nested.intercept_dr_read & dr_bits) |
410e4d57 | 1526 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
1527 | break; |
1528 | } | |
1529 | case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: { | |
1530 | u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0); | |
aad42c64 | 1531 | if (svm->nested.intercept_dr_write & dr_bits) |
410e4d57 | 1532 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
1533 | break; |
1534 | } | |
1535 | case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: { | |
1536 | u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE); | |
aad42c64 | 1537 | if (svm->nested.intercept_exceptions & excp_bits) |
410e4d57 | 1538 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
1539 | break; |
1540 | } | |
1541 | default: { | |
1542 | u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR); | |
1543 | nsvm_printk("exit code: 0x%x\n", exit_code); | |
aad42c64 | 1544 | if (svm->nested.intercept & exit_bits) |
410e4d57 | 1545 | vmexit = NESTED_EXIT_DONE; |
cf74a78b AG |
1546 | } |
1547 | } | |
1548 | ||
410e4d57 | 1549 | if (vmexit == NESTED_EXIT_DONE) { |
9c4e40b9 JR |
1550 | nsvm_printk("#VMEXIT reason=%04x\n", exit_code); |
1551 | nested_svm_vmexit(svm); | |
1552 | } | |
1553 | ||
1554 | return vmexit; | |
cf74a78b AG |
1555 | } |
1556 | ||
0460a979 JR |
1557 | static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb) |
1558 | { | |
1559 | struct vmcb_control_area *dst = &dst_vmcb->control; | |
1560 | struct vmcb_control_area *from = &from_vmcb->control; | |
1561 | ||
1562 | dst->intercept_cr_read = from->intercept_cr_read; | |
1563 | dst->intercept_cr_write = from->intercept_cr_write; | |
1564 | dst->intercept_dr_read = from->intercept_dr_read; | |
1565 | dst->intercept_dr_write = from->intercept_dr_write; | |
1566 | dst->intercept_exceptions = from->intercept_exceptions; | |
1567 | dst->intercept = from->intercept; | |
1568 | dst->iopm_base_pa = from->iopm_base_pa; | |
1569 | dst->msrpm_base_pa = from->msrpm_base_pa; | |
1570 | dst->tsc_offset = from->tsc_offset; | |
1571 | dst->asid = from->asid; | |
1572 | dst->tlb_ctl = from->tlb_ctl; | |
1573 | dst->int_ctl = from->int_ctl; | |
1574 | dst->int_vector = from->int_vector; | |
1575 | dst->int_state = from->int_state; | |
1576 | dst->exit_code = from->exit_code; | |
1577 | dst->exit_code_hi = from->exit_code_hi; | |
1578 | dst->exit_info_1 = from->exit_info_1; | |
1579 | dst->exit_info_2 = from->exit_info_2; | |
1580 | dst->exit_int_info = from->exit_int_info; | |
1581 | dst->exit_int_info_err = from->exit_int_info_err; | |
1582 | dst->nested_ctl = from->nested_ctl; | |
1583 | dst->event_inj = from->event_inj; | |
1584 | dst->event_inj_err = from->event_inj_err; | |
1585 | dst->nested_cr3 = from->nested_cr3; | |
1586 | dst->lbr_ctl = from->lbr_ctl; | |
1587 | } | |
1588 | ||
34f80cfa | 1589 | static int nested_svm_vmexit(struct vcpu_svm *svm) |
cf74a78b | 1590 | { |
34f80cfa | 1591 | struct vmcb *nested_vmcb; |
e6aa9abd | 1592 | struct vmcb *hsave = svm->nested.hsave; |
33740e40 | 1593 | struct vmcb *vmcb = svm->vmcb; |
cf74a78b | 1594 | |
17897f36 JR |
1595 | trace_kvm_nested_vmexit_inject(vmcb->control.exit_code, |
1596 | vmcb->control.exit_info_1, | |
1597 | vmcb->control.exit_info_2, | |
1598 | vmcb->control.exit_int_info, | |
1599 | vmcb->control.exit_int_info_err); | |
1600 | ||
34f80cfa JR |
1601 | nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, KM_USER0); |
1602 | if (!nested_vmcb) | |
1603 | return 1; | |
1604 | ||
cf74a78b | 1605 | /* Give the current vmcb to the guest */ |
33740e40 JR |
1606 | disable_gif(svm); |
1607 | ||
1608 | nested_vmcb->save.es = vmcb->save.es; | |
1609 | nested_vmcb->save.cs = vmcb->save.cs; | |
1610 | nested_vmcb->save.ss = vmcb->save.ss; | |
1611 | nested_vmcb->save.ds = vmcb->save.ds; | |
1612 | nested_vmcb->save.gdtr = vmcb->save.gdtr; | |
1613 | nested_vmcb->save.idtr = vmcb->save.idtr; | |
1614 | if (npt_enabled) | |
1615 | nested_vmcb->save.cr3 = vmcb->save.cr3; | |
1616 | nested_vmcb->save.cr2 = vmcb->save.cr2; | |
1617 | nested_vmcb->save.rflags = vmcb->save.rflags; | |
1618 | nested_vmcb->save.rip = vmcb->save.rip; | |
1619 | nested_vmcb->save.rsp = vmcb->save.rsp; | |
1620 | nested_vmcb->save.rax = vmcb->save.rax; | |
1621 | nested_vmcb->save.dr7 = vmcb->save.dr7; | |
1622 | nested_vmcb->save.dr6 = vmcb->save.dr6; | |
1623 | nested_vmcb->save.cpl = vmcb->save.cpl; | |
1624 | ||
1625 | nested_vmcb->control.int_ctl = vmcb->control.int_ctl; | |
1626 | nested_vmcb->control.int_vector = vmcb->control.int_vector; | |
1627 | nested_vmcb->control.int_state = vmcb->control.int_state; | |
1628 | nested_vmcb->control.exit_code = vmcb->control.exit_code; | |
1629 | nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi; | |
1630 | nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1; | |
1631 | nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2; | |
1632 | nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info; | |
1633 | nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err; | |
8d23c466 AG |
1634 | |
1635 | /* | |
1636 | * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have | |
1637 | * to make sure that we do not lose injected events. So check event_inj | |
1638 | * here and copy it to exit_int_info if it is valid. | |
1639 | * Exit_int_info and event_inj can't be both valid because the case | |
1640 | * below only happens on a VMRUN instruction intercept which has | |
1641 | * no valid exit_int_info set. | |
1642 | */ | |
1643 | if (vmcb->control.event_inj & SVM_EVTINJ_VALID) { | |
1644 | struct vmcb_control_area *nc = &nested_vmcb->control; | |
1645 | ||
1646 | nc->exit_int_info = vmcb->control.event_inj; | |
1647 | nc->exit_int_info_err = vmcb->control.event_inj_err; | |
1648 | } | |
1649 | ||
33740e40 JR |
1650 | nested_vmcb->control.tlb_ctl = 0; |
1651 | nested_vmcb->control.event_inj = 0; | |
1652 | nested_vmcb->control.event_inj_err = 0; | |
cf74a78b AG |
1653 | |
1654 | /* We always set V_INTR_MASKING and remember the old value in hflags */ | |
1655 | if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK)) | |
1656 | nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK; | |
1657 | ||
cf74a78b | 1658 | /* Restore the original control entries */ |
0460a979 | 1659 | copy_vmcb_control_area(vmcb, hsave); |
cf74a78b AG |
1660 | |
1661 | /* Kill any pending exceptions */ | |
1662 | if (svm->vcpu.arch.exception.pending == true) | |
1663 | nsvm_printk("WARNING: Pending Exception\n"); | |
33740e40 | 1664 | |
219b65dc AG |
1665 | kvm_clear_exception_queue(&svm->vcpu); |
1666 | kvm_clear_interrupt_queue(&svm->vcpu); | |
cf74a78b AG |
1667 | |
1668 | /* Restore selected save entries */ | |
1669 | svm->vmcb->save.es = hsave->save.es; | |
1670 | svm->vmcb->save.cs = hsave->save.cs; | |
1671 | svm->vmcb->save.ss = hsave->save.ss; | |
1672 | svm->vmcb->save.ds = hsave->save.ds; | |
1673 | svm->vmcb->save.gdtr = hsave->save.gdtr; | |
1674 | svm->vmcb->save.idtr = hsave->save.idtr; | |
1675 | svm->vmcb->save.rflags = hsave->save.rflags; | |
1676 | svm_set_efer(&svm->vcpu, hsave->save.efer); | |
1677 | svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE); | |
1678 | svm_set_cr4(&svm->vcpu, hsave->save.cr4); | |
1679 | if (npt_enabled) { | |
1680 | svm->vmcb->save.cr3 = hsave->save.cr3; | |
1681 | svm->vcpu.arch.cr3 = hsave->save.cr3; | |
1682 | } else { | |
1683 | kvm_set_cr3(&svm->vcpu, hsave->save.cr3); | |
1684 | } | |
1685 | kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax); | |
1686 | kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp); | |
1687 | kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip); | |
1688 | svm->vmcb->save.dr7 = 0; | |
1689 | svm->vmcb->save.cpl = 0; | |
1690 | svm->vmcb->control.exit_int_info = 0; | |
1691 | ||
cf74a78b | 1692 | /* Exit nested SVM mode */ |
e6aa9abd | 1693 | svm->nested.vmcb = 0; |
cf74a78b | 1694 | |
34f80cfa | 1695 | nested_svm_unmap(nested_vmcb, KM_USER0); |
cf74a78b AG |
1696 | |
1697 | kvm_mmu_reset_context(&svm->vcpu); | |
1698 | kvm_mmu_load(&svm->vcpu); | |
1699 | ||
1700 | return 0; | |
1701 | } | |
3d6368ef | 1702 | |
9738b2c9 | 1703 | static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm) |
3d6368ef | 1704 | { |
9738b2c9 | 1705 | u32 *nested_msrpm; |
3d6368ef | 1706 | int i; |
9738b2c9 JR |
1707 | |
1708 | nested_msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, KM_USER0); | |
1709 | if (!nested_msrpm) | |
1710 | return false; | |
1711 | ||
3d6368ef | 1712 | for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++) |
e6aa9abd | 1713 | svm->nested.msrpm[i] = svm->msrpm[i] | nested_msrpm[i]; |
9738b2c9 | 1714 | |
e6aa9abd | 1715 | svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm); |
3d6368ef | 1716 | |
9738b2c9 JR |
1717 | nested_svm_unmap(nested_msrpm, KM_USER0); |
1718 | ||
1719 | return true; | |
3d6368ef AG |
1720 | } |
1721 | ||
9738b2c9 | 1722 | static bool nested_svm_vmrun(struct vcpu_svm *svm) |
3d6368ef | 1723 | { |
9738b2c9 | 1724 | struct vmcb *nested_vmcb; |
e6aa9abd | 1725 | struct vmcb *hsave = svm->nested.hsave; |
defbba56 | 1726 | struct vmcb *vmcb = svm->vmcb; |
3d6368ef | 1727 | |
9738b2c9 JR |
1728 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0); |
1729 | if (!nested_vmcb) | |
1730 | return false; | |
1731 | ||
3d6368ef | 1732 | /* nested_vmcb is our indicator if nested SVM is activated */ |
e6aa9abd | 1733 | svm->nested.vmcb = svm->vmcb->save.rax; |
3d6368ef | 1734 | |
0ac406de JR |
1735 | trace_kvm_nested_vmrun(svm->vmcb->save.rip - 3, svm->nested.vmcb, |
1736 | nested_vmcb->save.rip, | |
1737 | nested_vmcb->control.int_ctl, | |
1738 | nested_vmcb->control.event_inj, | |
1739 | nested_vmcb->control.nested_ctl); | |
1740 | ||
3d6368ef | 1741 | /* Clear internal status */ |
219b65dc AG |
1742 | kvm_clear_exception_queue(&svm->vcpu); |
1743 | kvm_clear_interrupt_queue(&svm->vcpu); | |
3d6368ef AG |
1744 | |
1745 | /* Save the old vmcb, so we don't need to pick what we save, but | |
1746 | can restore everything when a VMEXIT occurs */ | |
defbba56 JR |
1747 | hsave->save.es = vmcb->save.es; |
1748 | hsave->save.cs = vmcb->save.cs; | |
1749 | hsave->save.ss = vmcb->save.ss; | |
1750 | hsave->save.ds = vmcb->save.ds; | |
1751 | hsave->save.gdtr = vmcb->save.gdtr; | |
1752 | hsave->save.idtr = vmcb->save.idtr; | |
1753 | hsave->save.efer = svm->vcpu.arch.shadow_efer; | |
1754 | hsave->save.cr0 = svm->vcpu.arch.cr0; | |
1755 | hsave->save.cr4 = svm->vcpu.arch.cr4; | |
1756 | hsave->save.rflags = vmcb->save.rflags; | |
1757 | hsave->save.rip = svm->next_rip; | |
1758 | hsave->save.rsp = vmcb->save.rsp; | |
1759 | hsave->save.rax = vmcb->save.rax; | |
1760 | if (npt_enabled) | |
1761 | hsave->save.cr3 = vmcb->save.cr3; | |
1762 | else | |
1763 | hsave->save.cr3 = svm->vcpu.arch.cr3; | |
1764 | ||
0460a979 | 1765 | copy_vmcb_control_area(hsave, vmcb); |
3d6368ef AG |
1766 | |
1767 | if (svm->vmcb->save.rflags & X86_EFLAGS_IF) | |
1768 | svm->vcpu.arch.hflags |= HF_HIF_MASK; | |
1769 | else | |
1770 | svm->vcpu.arch.hflags &= ~HF_HIF_MASK; | |
1771 | ||
1772 | /* Load the nested guest state */ | |
1773 | svm->vmcb->save.es = nested_vmcb->save.es; | |
1774 | svm->vmcb->save.cs = nested_vmcb->save.cs; | |
1775 | svm->vmcb->save.ss = nested_vmcb->save.ss; | |
1776 | svm->vmcb->save.ds = nested_vmcb->save.ds; | |
1777 | svm->vmcb->save.gdtr = nested_vmcb->save.gdtr; | |
1778 | svm->vmcb->save.idtr = nested_vmcb->save.idtr; | |
1779 | svm->vmcb->save.rflags = nested_vmcb->save.rflags; | |
1780 | svm_set_efer(&svm->vcpu, nested_vmcb->save.efer); | |
1781 | svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0); | |
1782 | svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4); | |
1783 | if (npt_enabled) { | |
1784 | svm->vmcb->save.cr3 = nested_vmcb->save.cr3; | |
1785 | svm->vcpu.arch.cr3 = nested_vmcb->save.cr3; | |
1786 | } else { | |
1787 | kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3); | |
1788 | kvm_mmu_reset_context(&svm->vcpu); | |
1789 | } | |
defbba56 | 1790 | svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2; |
3d6368ef AG |
1791 | kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax); |
1792 | kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp); | |
1793 | kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip); | |
1794 | /* In case we don't even reach vcpu_run, the fields are not updated */ | |
1795 | svm->vmcb->save.rax = nested_vmcb->save.rax; | |
1796 | svm->vmcb->save.rsp = nested_vmcb->save.rsp; | |
1797 | svm->vmcb->save.rip = nested_vmcb->save.rip; | |
1798 | svm->vmcb->save.dr7 = nested_vmcb->save.dr7; | |
1799 | svm->vmcb->save.dr6 = nested_vmcb->save.dr6; | |
1800 | svm->vmcb->save.cpl = nested_vmcb->save.cpl; | |
1801 | ||
1802 | /* We don't want a nested guest to be more powerful than the guest, | |
1803 | so all intercepts are ORed */ | |
1804 | svm->vmcb->control.intercept_cr_read |= | |
1805 | nested_vmcb->control.intercept_cr_read; | |
1806 | svm->vmcb->control.intercept_cr_write |= | |
1807 | nested_vmcb->control.intercept_cr_write; | |
1808 | svm->vmcb->control.intercept_dr_read |= | |
1809 | nested_vmcb->control.intercept_dr_read; | |
1810 | svm->vmcb->control.intercept_dr_write |= | |
1811 | nested_vmcb->control.intercept_dr_write; | |
1812 | svm->vmcb->control.intercept_exceptions |= | |
1813 | nested_vmcb->control.intercept_exceptions; | |
1814 | ||
1815 | svm->vmcb->control.intercept |= nested_vmcb->control.intercept; | |
1816 | ||
e6aa9abd | 1817 | svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa; |
3d6368ef | 1818 | |
aad42c64 JR |
1819 | /* cache intercepts */ |
1820 | svm->nested.intercept_cr_read = nested_vmcb->control.intercept_cr_read; | |
1821 | svm->nested.intercept_cr_write = nested_vmcb->control.intercept_cr_write; | |
1822 | svm->nested.intercept_dr_read = nested_vmcb->control.intercept_dr_read; | |
1823 | svm->nested.intercept_dr_write = nested_vmcb->control.intercept_dr_write; | |
1824 | svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions; | |
1825 | svm->nested.intercept = nested_vmcb->control.intercept; | |
1826 | ||
3d6368ef | 1827 | force_new_asid(&svm->vcpu); |
3d6368ef AG |
1828 | svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK; |
1829 | if (nested_vmcb->control.int_ctl & V_IRQ_MASK) { | |
1830 | nsvm_printk("nSVM Injecting Interrupt: 0x%x\n", | |
1831 | nested_vmcb->control.int_ctl); | |
1832 | } | |
1833 | if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK) | |
1834 | svm->vcpu.arch.hflags |= HF_VINTR_MASK; | |
1835 | else | |
1836 | svm->vcpu.arch.hflags &= ~HF_VINTR_MASK; | |
1837 | ||
1838 | nsvm_printk("nSVM exit_int_info: 0x%x | int_state: 0x%x\n", | |
1839 | nested_vmcb->control.exit_int_info, | |
1840 | nested_vmcb->control.int_state); | |
1841 | ||
1842 | svm->vmcb->control.int_vector = nested_vmcb->control.int_vector; | |
1843 | svm->vmcb->control.int_state = nested_vmcb->control.int_state; | |
1844 | svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset; | |
1845 | if (nested_vmcb->control.event_inj & SVM_EVTINJ_VALID) | |
1846 | nsvm_printk("Injecting Event: 0x%x\n", | |
1847 | nested_vmcb->control.event_inj); | |
1848 | svm->vmcb->control.event_inj = nested_vmcb->control.event_inj; | |
1849 | svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err; | |
1850 | ||
9738b2c9 JR |
1851 | nested_svm_unmap(nested_vmcb, KM_USER0); |
1852 | ||
2af9194d | 1853 | enable_gif(svm); |
3d6368ef | 1854 | |
9738b2c9 | 1855 | return true; |
3d6368ef AG |
1856 | } |
1857 | ||
9966bf68 | 1858 | static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb) |
5542675b AG |
1859 | { |
1860 | to_vmcb->save.fs = from_vmcb->save.fs; | |
1861 | to_vmcb->save.gs = from_vmcb->save.gs; | |
1862 | to_vmcb->save.tr = from_vmcb->save.tr; | |
1863 | to_vmcb->save.ldtr = from_vmcb->save.ldtr; | |
1864 | to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base; | |
1865 | to_vmcb->save.star = from_vmcb->save.star; | |
1866 | to_vmcb->save.lstar = from_vmcb->save.lstar; | |
1867 | to_vmcb->save.cstar = from_vmcb->save.cstar; | |
1868 | to_vmcb->save.sfmask = from_vmcb->save.sfmask; | |
1869 | to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs; | |
1870 | to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp; | |
1871 | to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip; | |
5542675b AG |
1872 | } |
1873 | ||
851ba692 | 1874 | static int vmload_interception(struct vcpu_svm *svm) |
5542675b | 1875 | { |
9966bf68 JR |
1876 | struct vmcb *nested_vmcb; |
1877 | ||
5542675b AG |
1878 | if (nested_svm_check_permissions(svm)) |
1879 | return 1; | |
1880 | ||
1881 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
1882 | skip_emulated_instruction(&svm->vcpu); | |
1883 | ||
9966bf68 JR |
1884 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0); |
1885 | if (!nested_vmcb) | |
1886 | return 1; | |
1887 | ||
1888 | nested_svm_vmloadsave(nested_vmcb, svm->vmcb); | |
1889 | nested_svm_unmap(nested_vmcb, KM_USER0); | |
5542675b AG |
1890 | |
1891 | return 1; | |
1892 | } | |
1893 | ||
851ba692 | 1894 | static int vmsave_interception(struct vcpu_svm *svm) |
5542675b | 1895 | { |
9966bf68 JR |
1896 | struct vmcb *nested_vmcb; |
1897 | ||
5542675b AG |
1898 | if (nested_svm_check_permissions(svm)) |
1899 | return 1; | |
1900 | ||
1901 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
1902 | skip_emulated_instruction(&svm->vcpu); | |
1903 | ||
9966bf68 JR |
1904 | nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0); |
1905 | if (!nested_vmcb) | |
1906 | return 1; | |
1907 | ||
1908 | nested_svm_vmloadsave(svm->vmcb, nested_vmcb); | |
1909 | nested_svm_unmap(nested_vmcb, KM_USER0); | |
5542675b AG |
1910 | |
1911 | return 1; | |
1912 | } | |
1913 | ||
851ba692 | 1914 | static int vmrun_interception(struct vcpu_svm *svm) |
3d6368ef AG |
1915 | { |
1916 | nsvm_printk("VMrun\n"); | |
1f8da478 | 1917 | |
3d6368ef AG |
1918 | if (nested_svm_check_permissions(svm)) |
1919 | return 1; | |
1920 | ||
1921 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
1922 | skip_emulated_instruction(&svm->vcpu); | |
1923 | ||
9738b2c9 | 1924 | if (!nested_svm_vmrun(svm)) |
3d6368ef AG |
1925 | return 1; |
1926 | ||
9738b2c9 | 1927 | if (!nested_svm_vmrun_msrpm(svm)) |
1f8da478 JR |
1928 | goto failed; |
1929 | ||
1930 | return 1; | |
1931 | ||
1932 | failed: | |
1933 | ||
1934 | svm->vmcb->control.exit_code = SVM_EXIT_ERR; | |
1935 | svm->vmcb->control.exit_code_hi = 0; | |
1936 | svm->vmcb->control.exit_info_1 = 0; | |
1937 | svm->vmcb->control.exit_info_2 = 0; | |
1938 | ||
1939 | nested_svm_vmexit(svm); | |
3d6368ef AG |
1940 | |
1941 | return 1; | |
1942 | } | |
1943 | ||
851ba692 | 1944 | static int stgi_interception(struct vcpu_svm *svm) |
1371d904 AG |
1945 | { |
1946 | if (nested_svm_check_permissions(svm)) | |
1947 | return 1; | |
1948 | ||
1949 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
1950 | skip_emulated_instruction(&svm->vcpu); | |
1951 | ||
2af9194d | 1952 | enable_gif(svm); |
1371d904 AG |
1953 | |
1954 | return 1; | |
1955 | } | |
1956 | ||
851ba692 | 1957 | static int clgi_interception(struct vcpu_svm *svm) |
1371d904 AG |
1958 | { |
1959 | if (nested_svm_check_permissions(svm)) | |
1960 | return 1; | |
1961 | ||
1962 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
1963 | skip_emulated_instruction(&svm->vcpu); | |
1964 | ||
2af9194d | 1965 | disable_gif(svm); |
1371d904 AG |
1966 | |
1967 | /* After a CLGI no interrupts should come */ | |
1968 | svm_clear_vintr(svm); | |
1969 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; | |
1970 | ||
1971 | return 1; | |
1972 | } | |
1973 | ||
851ba692 | 1974 | static int invlpga_interception(struct vcpu_svm *svm) |
ff092385 AG |
1975 | { |
1976 | struct kvm_vcpu *vcpu = &svm->vcpu; | |
1977 | nsvm_printk("INVLPGA\n"); | |
1978 | ||
ec1ff790 JR |
1979 | trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX], |
1980 | vcpu->arch.regs[VCPU_REGS_RAX]); | |
1981 | ||
ff092385 AG |
1982 | /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */ |
1983 | kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]); | |
1984 | ||
1985 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 3; | |
1986 | skip_emulated_instruction(&svm->vcpu); | |
1987 | return 1; | |
1988 | } | |
1989 | ||
851ba692 | 1990 | static int invalid_op_interception(struct vcpu_svm *svm) |
6aa8b732 | 1991 | { |
7ee5d940 | 1992 | kvm_queue_exception(&svm->vcpu, UD_VECTOR); |
6aa8b732 AK |
1993 | return 1; |
1994 | } | |
1995 | ||
851ba692 | 1996 | static int task_switch_interception(struct vcpu_svm *svm) |
6aa8b732 | 1997 | { |
37817f29 | 1998 | u16 tss_selector; |
64a7ec06 GN |
1999 | int reason; |
2000 | int int_type = svm->vmcb->control.exit_int_info & | |
2001 | SVM_EXITINTINFO_TYPE_MASK; | |
8317c298 | 2002 | int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK; |
fe8e7f83 GN |
2003 | uint32_t type = |
2004 | svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK; | |
2005 | uint32_t idt_v = | |
2006 | svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID; | |
37817f29 IE |
2007 | |
2008 | tss_selector = (u16)svm->vmcb->control.exit_info_1; | |
64a7ec06 | 2009 | |
37817f29 IE |
2010 | if (svm->vmcb->control.exit_info_2 & |
2011 | (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET)) | |
64a7ec06 GN |
2012 | reason = TASK_SWITCH_IRET; |
2013 | else if (svm->vmcb->control.exit_info_2 & | |
2014 | (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP)) | |
2015 | reason = TASK_SWITCH_JMP; | |
fe8e7f83 | 2016 | else if (idt_v) |
64a7ec06 GN |
2017 | reason = TASK_SWITCH_GATE; |
2018 | else | |
2019 | reason = TASK_SWITCH_CALL; | |
2020 | ||
fe8e7f83 GN |
2021 | if (reason == TASK_SWITCH_GATE) { |
2022 | switch (type) { | |
2023 | case SVM_EXITINTINFO_TYPE_NMI: | |
2024 | svm->vcpu.arch.nmi_injected = false; | |
2025 | break; | |
2026 | case SVM_EXITINTINFO_TYPE_EXEPT: | |
2027 | kvm_clear_exception_queue(&svm->vcpu); | |
2028 | break; | |
2029 | case SVM_EXITINTINFO_TYPE_INTR: | |
2030 | kvm_clear_interrupt_queue(&svm->vcpu); | |
2031 | break; | |
2032 | default: | |
2033 | break; | |
2034 | } | |
2035 | } | |
64a7ec06 | 2036 | |
8317c298 GN |
2037 | if (reason != TASK_SWITCH_GATE || |
2038 | int_type == SVM_EXITINTINFO_TYPE_SOFT || | |
2039 | (int_type == SVM_EXITINTINFO_TYPE_EXEPT && | |
f629cf84 GN |
2040 | (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) |
2041 | skip_emulated_instruction(&svm->vcpu); | |
64a7ec06 GN |
2042 | |
2043 | return kvm_task_switch(&svm->vcpu, tss_selector, reason); | |
6aa8b732 AK |
2044 | } |
2045 | ||
851ba692 | 2046 | static int cpuid_interception(struct vcpu_svm *svm) |
6aa8b732 | 2047 | { |
5fdbf976 | 2048 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
e756fc62 | 2049 | kvm_emulate_cpuid(&svm->vcpu); |
06465c5a | 2050 | return 1; |
6aa8b732 AK |
2051 | } |
2052 | ||
851ba692 | 2053 | static int iret_interception(struct vcpu_svm *svm) |
95ba8273 GN |
2054 | { |
2055 | ++svm->vcpu.stat.nmi_window_exits; | |
2056 | svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET); | |
44c11430 | 2057 | svm->vcpu.arch.hflags |= HF_IRET_MASK; |
95ba8273 GN |
2058 | return 1; |
2059 | } | |
2060 | ||
851ba692 | 2061 | static int invlpg_interception(struct vcpu_svm *svm) |
a7052897 | 2062 | { |
851ba692 | 2063 | if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE) |
a7052897 MT |
2064 | pr_unimpl(&svm->vcpu, "%s: failed\n", __func__); |
2065 | return 1; | |
2066 | } | |
2067 | ||
851ba692 | 2068 | static int emulate_on_interception(struct vcpu_svm *svm) |
6aa8b732 | 2069 | { |
851ba692 | 2070 | if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE) |
b8688d51 | 2071 | pr_unimpl(&svm->vcpu, "%s: failed\n", __func__); |
6aa8b732 AK |
2072 | return 1; |
2073 | } | |
2074 | ||
851ba692 | 2075 | static int cr8_write_interception(struct vcpu_svm *svm) |
1d075434 | 2076 | { |
851ba692 AK |
2077 | struct kvm_run *kvm_run = svm->vcpu.run; |
2078 | ||
0a5fff19 GN |
2079 | u8 cr8_prev = kvm_get_cr8(&svm->vcpu); |
2080 | /* instruction emulation calls kvm_set_cr8() */ | |
851ba692 | 2081 | emulate_instruction(&svm->vcpu, 0, 0, 0); |
95ba8273 GN |
2082 | if (irqchip_in_kernel(svm->vcpu.kvm)) { |
2083 | svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK; | |
1d075434 | 2084 | return 1; |
95ba8273 | 2085 | } |
0a5fff19 GN |
2086 | if (cr8_prev <= kvm_get_cr8(&svm->vcpu)) |
2087 | return 1; | |
1d075434 JR |
2088 | kvm_run->exit_reason = KVM_EXIT_SET_TPR; |
2089 | return 0; | |
2090 | } | |
2091 | ||
6aa8b732 AK |
2092 | static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data) |
2093 | { | |
a2fa3e9f GH |
2094 | struct vcpu_svm *svm = to_svm(vcpu); |
2095 | ||
6aa8b732 | 2096 | switch (ecx) { |
af24a4e4 | 2097 | case MSR_IA32_TSC: { |
20824f30 | 2098 | u64 tsc_offset; |
6aa8b732 | 2099 | |
20824f30 JR |
2100 | if (is_nested(svm)) |
2101 | tsc_offset = svm->nested.hsave->control.tsc_offset; | |
2102 | else | |
2103 | tsc_offset = svm->vmcb->control.tsc_offset; | |
2104 | ||
2105 | *data = tsc_offset + native_read_tsc(); | |
6aa8b732 AK |
2106 | break; |
2107 | } | |
0e859cac | 2108 | case MSR_K6_STAR: |
a2fa3e9f | 2109 | *data = svm->vmcb->save.star; |
6aa8b732 | 2110 | break; |
0e859cac | 2111 | #ifdef CONFIG_X86_64 |
6aa8b732 | 2112 | case MSR_LSTAR: |
a2fa3e9f | 2113 | *data = svm->vmcb->save.lstar; |
6aa8b732 AK |
2114 | break; |
2115 | case MSR_CSTAR: | |
a2fa3e9f | 2116 | *data = svm->vmcb->save.cstar; |
6aa8b732 AK |
2117 | break; |
2118 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 2119 | *data = svm->vmcb->save.kernel_gs_base; |
6aa8b732 AK |
2120 | break; |
2121 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 2122 | *data = svm->vmcb->save.sfmask; |
6aa8b732 AK |
2123 | break; |
2124 | #endif | |
2125 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 2126 | *data = svm->vmcb->save.sysenter_cs; |
6aa8b732 AK |
2127 | break; |
2128 | case MSR_IA32_SYSENTER_EIP: | |
017cb99e | 2129 | *data = svm->sysenter_eip; |
6aa8b732 AK |
2130 | break; |
2131 | case MSR_IA32_SYSENTER_ESP: | |
017cb99e | 2132 | *data = svm->sysenter_esp; |
6aa8b732 | 2133 | break; |
a2938c80 JR |
2134 | /* Nobody will change the following 5 values in the VMCB so |
2135 | we can safely return them on rdmsr. They will always be 0 | |
2136 | until LBRV is implemented. */ | |
2137 | case MSR_IA32_DEBUGCTLMSR: | |
2138 | *data = svm->vmcb->save.dbgctl; | |
2139 | break; | |
2140 | case MSR_IA32_LASTBRANCHFROMIP: | |
2141 | *data = svm->vmcb->save.br_from; | |
2142 | break; | |
2143 | case MSR_IA32_LASTBRANCHTOIP: | |
2144 | *data = svm->vmcb->save.br_to; | |
2145 | break; | |
2146 | case MSR_IA32_LASTINTFROMIP: | |
2147 | *data = svm->vmcb->save.last_excp_from; | |
2148 | break; | |
2149 | case MSR_IA32_LASTINTTOIP: | |
2150 | *data = svm->vmcb->save.last_excp_to; | |
2151 | break; | |
b286d5d8 | 2152 | case MSR_VM_HSAVE_PA: |
e6aa9abd | 2153 | *data = svm->nested.hsave_msr; |
b286d5d8 | 2154 | break; |
eb6f302e JR |
2155 | case MSR_VM_CR: |
2156 | *data = 0; | |
2157 | break; | |
c8a73f18 AG |
2158 | case MSR_IA32_UCODE_REV: |
2159 | *data = 0x01000065; | |
2160 | break; | |
6aa8b732 | 2161 | default: |
3bab1f5d | 2162 | return kvm_get_msr_common(vcpu, ecx, data); |
6aa8b732 AK |
2163 | } |
2164 | return 0; | |
2165 | } | |
2166 | ||
851ba692 | 2167 | static int rdmsr_interception(struct vcpu_svm *svm) |
6aa8b732 | 2168 | { |
ad312c7c | 2169 | u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
6aa8b732 AK |
2170 | u64 data; |
2171 | ||
e756fc62 | 2172 | if (svm_get_msr(&svm->vcpu, ecx, &data)) |
c1a5d4f9 | 2173 | kvm_inject_gp(&svm->vcpu, 0); |
6aa8b732 | 2174 | else { |
229456fc | 2175 | trace_kvm_msr_read(ecx, data); |
af9ca2d7 | 2176 | |
5fdbf976 | 2177 | svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff; |
ad312c7c | 2178 | svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32; |
5fdbf976 | 2179 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
e756fc62 | 2180 | skip_emulated_instruction(&svm->vcpu); |
6aa8b732 AK |
2181 | } |
2182 | return 1; | |
2183 | } | |
2184 | ||
2185 | static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data) | |
2186 | { | |
a2fa3e9f GH |
2187 | struct vcpu_svm *svm = to_svm(vcpu); |
2188 | ||
6aa8b732 | 2189 | switch (ecx) { |
af24a4e4 | 2190 | case MSR_IA32_TSC: { |
20824f30 JR |
2191 | u64 tsc_offset = data - native_read_tsc(); |
2192 | u64 g_tsc_offset = 0; | |
2193 | ||
2194 | if (is_nested(svm)) { | |
2195 | g_tsc_offset = svm->vmcb->control.tsc_offset - | |
2196 | svm->nested.hsave->control.tsc_offset; | |
2197 | svm->nested.hsave->control.tsc_offset = tsc_offset; | |
2198 | } | |
2199 | ||
2200 | svm->vmcb->control.tsc_offset = tsc_offset + g_tsc_offset; | |
6aa8b732 | 2201 | |
6aa8b732 AK |
2202 | break; |
2203 | } | |
0e859cac | 2204 | case MSR_K6_STAR: |
a2fa3e9f | 2205 | svm->vmcb->save.star = data; |
6aa8b732 | 2206 | break; |
49b14f24 | 2207 | #ifdef CONFIG_X86_64 |
6aa8b732 | 2208 | case MSR_LSTAR: |
a2fa3e9f | 2209 | svm->vmcb->save.lstar = data; |
6aa8b732 AK |
2210 | break; |
2211 | case MSR_CSTAR: | |
a2fa3e9f | 2212 | svm->vmcb->save.cstar = data; |
6aa8b732 AK |
2213 | break; |
2214 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 2215 | svm->vmcb->save.kernel_gs_base = data; |
6aa8b732 AK |
2216 | break; |
2217 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 2218 | svm->vmcb->save.sfmask = data; |
6aa8b732 AK |
2219 | break; |
2220 | #endif | |
2221 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 2222 | svm->vmcb->save.sysenter_cs = data; |
6aa8b732 AK |
2223 | break; |
2224 | case MSR_IA32_SYSENTER_EIP: | |
017cb99e | 2225 | svm->sysenter_eip = data; |
a2fa3e9f | 2226 | svm->vmcb->save.sysenter_eip = data; |
6aa8b732 AK |
2227 | break; |
2228 | case MSR_IA32_SYSENTER_ESP: | |
017cb99e | 2229 | svm->sysenter_esp = data; |
a2fa3e9f | 2230 | svm->vmcb->save.sysenter_esp = data; |
6aa8b732 | 2231 | break; |
a2938c80 | 2232 | case MSR_IA32_DEBUGCTLMSR: |
24e09cbf JR |
2233 | if (!svm_has(SVM_FEATURE_LBRV)) { |
2234 | pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n", | |
b8688d51 | 2235 | __func__, data); |
24e09cbf JR |
2236 | break; |
2237 | } | |
2238 | if (data & DEBUGCTL_RESERVED_BITS) | |
2239 | return 1; | |
2240 | ||
2241 | svm->vmcb->save.dbgctl = data; | |
2242 | if (data & (1ULL<<0)) | |
2243 | svm_enable_lbrv(svm); | |
2244 | else | |
2245 | svm_disable_lbrv(svm); | |
a2938c80 | 2246 | break; |
b286d5d8 | 2247 | case MSR_VM_HSAVE_PA: |
e6aa9abd | 2248 | svm->nested.hsave_msr = data; |
62b9abaa | 2249 | break; |
3c5d0a44 AG |
2250 | case MSR_VM_CR: |
2251 | case MSR_VM_IGNNE: | |
3c5d0a44 AG |
2252 | pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data); |
2253 | break; | |
6aa8b732 | 2254 | default: |
3bab1f5d | 2255 | return kvm_set_msr_common(vcpu, ecx, data); |
6aa8b732 AK |
2256 | } |
2257 | return 0; | |
2258 | } | |
2259 | ||
851ba692 | 2260 | static int wrmsr_interception(struct vcpu_svm *svm) |
6aa8b732 | 2261 | { |
ad312c7c | 2262 | u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX]; |
5fdbf976 | 2263 | u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u) |
ad312c7c | 2264 | | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32); |
af9ca2d7 | 2265 | |
229456fc | 2266 | trace_kvm_msr_write(ecx, data); |
af9ca2d7 | 2267 | |
5fdbf976 | 2268 | svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; |
e756fc62 | 2269 | if (svm_set_msr(&svm->vcpu, ecx, data)) |
c1a5d4f9 | 2270 | kvm_inject_gp(&svm->vcpu, 0); |
6aa8b732 | 2271 | else |
e756fc62 | 2272 | skip_emulated_instruction(&svm->vcpu); |
6aa8b732 AK |
2273 | return 1; |
2274 | } | |
2275 | ||
851ba692 | 2276 | static int msr_interception(struct vcpu_svm *svm) |
6aa8b732 | 2277 | { |
e756fc62 | 2278 | if (svm->vmcb->control.exit_info_1) |
851ba692 | 2279 | return wrmsr_interception(svm); |
6aa8b732 | 2280 | else |
851ba692 | 2281 | return rdmsr_interception(svm); |
6aa8b732 AK |
2282 | } |
2283 | ||
851ba692 | 2284 | static int interrupt_window_interception(struct vcpu_svm *svm) |
c1150d8c | 2285 | { |
851ba692 AK |
2286 | struct kvm_run *kvm_run = svm->vcpu.run; |
2287 | ||
f0b85051 | 2288 | svm_clear_vintr(svm); |
85f455f7 | 2289 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; |
c1150d8c DL |
2290 | /* |
2291 | * If the user space waits to inject interrupts, exit as soon as | |
2292 | * possible | |
2293 | */ | |
8061823a GN |
2294 | if (!irqchip_in_kernel(svm->vcpu.kvm) && |
2295 | kvm_run->request_interrupt_window && | |
2296 | !kvm_cpu_has_interrupt(&svm->vcpu)) { | |
e756fc62 | 2297 | ++svm->vcpu.stat.irq_window_exits; |
c1150d8c DL |
2298 | kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; |
2299 | return 0; | |
2300 | } | |
2301 | ||
2302 | return 1; | |
2303 | } | |
2304 | ||
851ba692 | 2305 | static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = { |
6aa8b732 AK |
2306 | [SVM_EXIT_READ_CR0] = emulate_on_interception, |
2307 | [SVM_EXIT_READ_CR3] = emulate_on_interception, | |
2308 | [SVM_EXIT_READ_CR4] = emulate_on_interception, | |
80a8119c | 2309 | [SVM_EXIT_READ_CR8] = emulate_on_interception, |
6aa8b732 AK |
2310 | /* for now: */ |
2311 | [SVM_EXIT_WRITE_CR0] = emulate_on_interception, | |
2312 | [SVM_EXIT_WRITE_CR3] = emulate_on_interception, | |
2313 | [SVM_EXIT_WRITE_CR4] = emulate_on_interception, | |
1d075434 | 2314 | [SVM_EXIT_WRITE_CR8] = cr8_write_interception, |
6aa8b732 AK |
2315 | [SVM_EXIT_READ_DR0] = emulate_on_interception, |
2316 | [SVM_EXIT_READ_DR1] = emulate_on_interception, | |
2317 | [SVM_EXIT_READ_DR2] = emulate_on_interception, | |
2318 | [SVM_EXIT_READ_DR3] = emulate_on_interception, | |
2319 | [SVM_EXIT_WRITE_DR0] = emulate_on_interception, | |
2320 | [SVM_EXIT_WRITE_DR1] = emulate_on_interception, | |
2321 | [SVM_EXIT_WRITE_DR2] = emulate_on_interception, | |
2322 | [SVM_EXIT_WRITE_DR3] = emulate_on_interception, | |
2323 | [SVM_EXIT_WRITE_DR5] = emulate_on_interception, | |
2324 | [SVM_EXIT_WRITE_DR7] = emulate_on_interception, | |
d0bfb940 JK |
2325 | [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception, |
2326 | [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception, | |
7aa81cc0 | 2327 | [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception, |
6aa8b732 | 2328 | [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception, |
7807fa6c | 2329 | [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception, |
53371b50 | 2330 | [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception, |
a0698055 | 2331 | [SVM_EXIT_INTR] = intr_interception, |
c47f098d | 2332 | [SVM_EXIT_NMI] = nmi_interception, |
6aa8b732 AK |
2333 | [SVM_EXIT_SMI] = nop_on_interception, |
2334 | [SVM_EXIT_INIT] = nop_on_interception, | |
c1150d8c | 2335 | [SVM_EXIT_VINTR] = interrupt_window_interception, |
6aa8b732 AK |
2336 | /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */ |
2337 | [SVM_EXIT_CPUID] = cpuid_interception, | |
95ba8273 | 2338 | [SVM_EXIT_IRET] = iret_interception, |
cf5a94d1 | 2339 | [SVM_EXIT_INVD] = emulate_on_interception, |
6aa8b732 | 2340 | [SVM_EXIT_HLT] = halt_interception, |
a7052897 | 2341 | [SVM_EXIT_INVLPG] = invlpg_interception, |
ff092385 | 2342 | [SVM_EXIT_INVLPGA] = invlpga_interception, |
6aa8b732 AK |
2343 | [SVM_EXIT_IOIO] = io_interception, |
2344 | [SVM_EXIT_MSR] = msr_interception, | |
2345 | [SVM_EXIT_TASK_SWITCH] = task_switch_interception, | |
46fe4ddd | 2346 | [SVM_EXIT_SHUTDOWN] = shutdown_interception, |
3d6368ef | 2347 | [SVM_EXIT_VMRUN] = vmrun_interception, |
02e235bc | 2348 | [SVM_EXIT_VMMCALL] = vmmcall_interception, |
5542675b AG |
2349 | [SVM_EXIT_VMLOAD] = vmload_interception, |
2350 | [SVM_EXIT_VMSAVE] = vmsave_interception, | |
1371d904 AG |
2351 | [SVM_EXIT_STGI] = stgi_interception, |
2352 | [SVM_EXIT_CLGI] = clgi_interception, | |
6aa8b732 | 2353 | [SVM_EXIT_SKINIT] = invalid_op_interception, |
cf5a94d1 | 2354 | [SVM_EXIT_WBINVD] = emulate_on_interception, |
916ce236 JR |
2355 | [SVM_EXIT_MONITOR] = invalid_op_interception, |
2356 | [SVM_EXIT_MWAIT] = invalid_op_interception, | |
709ddebf | 2357 | [SVM_EXIT_NPF] = pf_interception, |
6aa8b732 AK |
2358 | }; |
2359 | ||
851ba692 | 2360 | static int handle_exit(struct kvm_vcpu *vcpu) |
6aa8b732 | 2361 | { |
04d2cc77 | 2362 | struct vcpu_svm *svm = to_svm(vcpu); |
851ba692 | 2363 | struct kvm_run *kvm_run = vcpu->run; |
a2fa3e9f | 2364 | u32 exit_code = svm->vmcb->control.exit_code; |
6aa8b732 | 2365 | |
229456fc | 2366 | trace_kvm_exit(exit_code, svm->vmcb->save.rip); |
af9ca2d7 | 2367 | |
cd3ff653 JR |
2368 | if (unlikely(svm->nested.exit_required)) { |
2369 | nested_svm_vmexit(svm); | |
2370 | svm->nested.exit_required = false; | |
2371 | ||
2372 | return 1; | |
2373 | } | |
2374 | ||
cf74a78b | 2375 | if (is_nested(svm)) { |
410e4d57 JR |
2376 | int vmexit; |
2377 | ||
d8cabddf JR |
2378 | trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code, |
2379 | svm->vmcb->control.exit_info_1, | |
2380 | svm->vmcb->control.exit_info_2, | |
2381 | svm->vmcb->control.exit_int_info, | |
2382 | svm->vmcb->control.exit_int_info_err); | |
2383 | ||
cf74a78b AG |
2384 | nsvm_printk("nested handle_exit: 0x%x | 0x%lx | 0x%lx | 0x%lx\n", |
2385 | exit_code, svm->vmcb->control.exit_info_1, | |
2386 | svm->vmcb->control.exit_info_2, svm->vmcb->save.rip); | |
410e4d57 JR |
2387 | |
2388 | vmexit = nested_svm_exit_special(svm); | |
2389 | ||
2390 | if (vmexit == NESTED_EXIT_CONTINUE) | |
2391 | vmexit = nested_svm_exit_handled(svm); | |
2392 | ||
2393 | if (vmexit == NESTED_EXIT_DONE) | |
cf74a78b | 2394 | return 1; |
cf74a78b AG |
2395 | } |
2396 | ||
a5c3832d JR |
2397 | svm_complete_interrupts(svm); |
2398 | ||
709ddebf JR |
2399 | if (npt_enabled) { |
2400 | int mmu_reload = 0; | |
2401 | if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) { | |
2402 | svm_set_cr0(vcpu, svm->vmcb->save.cr0); | |
2403 | mmu_reload = 1; | |
2404 | } | |
2405 | vcpu->arch.cr0 = svm->vmcb->save.cr0; | |
2406 | vcpu->arch.cr3 = svm->vmcb->save.cr3; | |
709ddebf JR |
2407 | if (mmu_reload) { |
2408 | kvm_mmu_reset_context(vcpu); | |
2409 | kvm_mmu_load(vcpu); | |
2410 | } | |
2411 | } | |
2412 | ||
04d2cc77 AK |
2413 | |
2414 | if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) { | |
2415 | kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY; | |
2416 | kvm_run->fail_entry.hardware_entry_failure_reason | |
2417 | = svm->vmcb->control.exit_code; | |
2418 | return 0; | |
2419 | } | |
2420 | ||
a2fa3e9f | 2421 | if (is_external_interrupt(svm->vmcb->control.exit_int_info) && |
709ddebf | 2422 | exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR && |
fe8e7f83 | 2423 | exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH) |
6aa8b732 AK |
2424 | printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x " |
2425 | "exit_code 0x%x\n", | |
b8688d51 | 2426 | __func__, svm->vmcb->control.exit_int_info, |
6aa8b732 AK |
2427 | exit_code); |
2428 | ||
9d8f549d | 2429 | if (exit_code >= ARRAY_SIZE(svm_exit_handlers) |
56919c5c | 2430 | || !svm_exit_handlers[exit_code]) { |
6aa8b732 | 2431 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; |
364b625b | 2432 | kvm_run->hw.hardware_exit_reason = exit_code; |
6aa8b732 AK |
2433 | return 0; |
2434 | } | |
2435 | ||
851ba692 | 2436 | return svm_exit_handlers[exit_code](svm); |
6aa8b732 AK |
2437 | } |
2438 | ||
2439 | static void reload_tss(struct kvm_vcpu *vcpu) | |
2440 | { | |
2441 | int cpu = raw_smp_processor_id(); | |
2442 | ||
2443 | struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu); | |
d77c26fc | 2444 | svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */ |
6aa8b732 AK |
2445 | load_TR_desc(); |
2446 | } | |
2447 | ||
e756fc62 | 2448 | static void pre_svm_run(struct vcpu_svm *svm) |
6aa8b732 AK |
2449 | { |
2450 | int cpu = raw_smp_processor_id(); | |
2451 | ||
2452 | struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu); | |
2453 | ||
a2fa3e9f | 2454 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING; |
4b656b12 MT |
2455 | /* FIXME: handle wraparound of asid_generation */ |
2456 | if (svm->asid_generation != svm_data->asid_generation) | |
e756fc62 | 2457 | new_asid(svm, svm_data); |
6aa8b732 AK |
2458 | } |
2459 | ||
95ba8273 GN |
2460 | static void svm_inject_nmi(struct kvm_vcpu *vcpu) |
2461 | { | |
2462 | struct vcpu_svm *svm = to_svm(vcpu); | |
2463 | ||
2464 | svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI; | |
2465 | vcpu->arch.hflags |= HF_NMI_MASK; | |
2466 | svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET); | |
2467 | ++vcpu->stat.nmi_injections; | |
2468 | } | |
6aa8b732 | 2469 | |
85f455f7 | 2470 | static inline void svm_inject_irq(struct vcpu_svm *svm, int irq) |
6aa8b732 AK |
2471 | { |
2472 | struct vmcb_control_area *control; | |
2473 | ||
229456fc | 2474 | trace_kvm_inj_virq(irq); |
af9ca2d7 | 2475 | |
fa89a817 | 2476 | ++svm->vcpu.stat.irq_injections; |
e756fc62 | 2477 | control = &svm->vmcb->control; |
85f455f7 | 2478 | control->int_vector = irq; |
6aa8b732 AK |
2479 | control->int_ctl &= ~V_INTR_PRIO_MASK; |
2480 | control->int_ctl |= V_IRQ_MASK | | |
2481 | ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT); | |
2482 | } | |
2483 | ||
66fd3f7f | 2484 | static void svm_set_irq(struct kvm_vcpu *vcpu) |
2a8067f1 ED |
2485 | { |
2486 | struct vcpu_svm *svm = to_svm(vcpu); | |
2487 | ||
2af9194d | 2488 | BUG_ON(!(gif_set(svm))); |
cf74a78b | 2489 | |
219b65dc AG |
2490 | svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr | |
2491 | SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR; | |
2a8067f1 ED |
2492 | } |
2493 | ||
95ba8273 | 2494 | static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr) |
aaacfc9a JR |
2495 | { |
2496 | struct vcpu_svm *svm = to_svm(vcpu); | |
aaacfc9a | 2497 | |
95ba8273 | 2498 | if (irr == -1) |
aaacfc9a JR |
2499 | return; |
2500 | ||
95ba8273 GN |
2501 | if (tpr >= irr) |
2502 | svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK; | |
2503 | } | |
aaacfc9a | 2504 | |
95ba8273 GN |
2505 | static int svm_nmi_allowed(struct kvm_vcpu *vcpu) |
2506 | { | |
2507 | struct vcpu_svm *svm = to_svm(vcpu); | |
2508 | struct vmcb *vmcb = svm->vmcb; | |
2509 | return !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) && | |
2510 | !(svm->vcpu.arch.hflags & HF_NMI_MASK); | |
aaacfc9a JR |
2511 | } |
2512 | ||
78646121 GN |
2513 | static int svm_interrupt_allowed(struct kvm_vcpu *vcpu) |
2514 | { | |
2515 | struct vcpu_svm *svm = to_svm(vcpu); | |
2516 | struct vmcb *vmcb = svm->vmcb; | |
7fcdb510 JR |
2517 | int ret; |
2518 | ||
2519 | if (!gif_set(svm) || | |
2520 | (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)) | |
2521 | return 0; | |
2522 | ||
2523 | ret = !!(vmcb->save.rflags & X86_EFLAGS_IF); | |
2524 | ||
2525 | if (is_nested(svm)) | |
2526 | return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK); | |
2527 | ||
2528 | return ret; | |
78646121 GN |
2529 | } |
2530 | ||
9222be18 | 2531 | static void enable_irq_window(struct kvm_vcpu *vcpu) |
6aa8b732 | 2532 | { |
219b65dc AG |
2533 | struct vcpu_svm *svm = to_svm(vcpu); |
2534 | nsvm_printk("Trying to open IRQ window\n"); | |
2535 | ||
2536 | nested_svm_intr(svm); | |
2537 | ||
2538 | /* In case GIF=0 we can't rely on the CPU to tell us when | |
2539 | * GIF becomes 1, because that's a separate STGI/VMRUN intercept. | |
2540 | * The next time we get that intercept, this function will be | |
2541 | * called again though and we'll get the vintr intercept. */ | |
2af9194d | 2542 | if (gif_set(svm)) { |
219b65dc AG |
2543 | svm_set_vintr(svm); |
2544 | svm_inject_irq(svm, 0x0); | |
2545 | } | |
85f455f7 ED |
2546 | } |
2547 | ||
95ba8273 | 2548 | static void enable_nmi_window(struct kvm_vcpu *vcpu) |
c1150d8c | 2549 | { |
04d2cc77 | 2550 | struct vcpu_svm *svm = to_svm(vcpu); |
c1150d8c | 2551 | |
44c11430 GN |
2552 | if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK)) |
2553 | == HF_NMI_MASK) | |
2554 | return; /* IRET will cause a vm exit */ | |
2555 | ||
2556 | /* Something prevents NMI from been injected. Single step over | |
2557 | possible problem (IRET or exception injection or interrupt | |
2558 | shadow) */ | |
2559 | vcpu->arch.singlestep = true; | |
2560 | svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF); | |
2561 | update_db_intercept(vcpu); | |
c1150d8c DL |
2562 | } |
2563 | ||
cbc94022 IE |
2564 | static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr) |
2565 | { | |
2566 | return 0; | |
2567 | } | |
2568 | ||
d9e368d6 AK |
2569 | static void svm_flush_tlb(struct kvm_vcpu *vcpu) |
2570 | { | |
2571 | force_new_asid(vcpu); | |
2572 | } | |
2573 | ||
04d2cc77 AK |
2574 | static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu) |
2575 | { | |
2576 | } | |
2577 | ||
d7bf8221 JR |
2578 | static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu) |
2579 | { | |
2580 | struct vcpu_svm *svm = to_svm(vcpu); | |
2581 | ||
2582 | if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) { | |
2583 | int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK; | |
615d5193 | 2584 | kvm_set_cr8(vcpu, cr8); |
d7bf8221 JR |
2585 | } |
2586 | } | |
2587 | ||
649d6864 JR |
2588 | static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu) |
2589 | { | |
2590 | struct vcpu_svm *svm = to_svm(vcpu); | |
2591 | u64 cr8; | |
2592 | ||
649d6864 JR |
2593 | cr8 = kvm_get_cr8(vcpu); |
2594 | svm->vmcb->control.int_ctl &= ~V_TPR_MASK; | |
2595 | svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK; | |
2596 | } | |
2597 | ||
9222be18 GN |
2598 | static void svm_complete_interrupts(struct vcpu_svm *svm) |
2599 | { | |
2600 | u8 vector; | |
2601 | int type; | |
2602 | u32 exitintinfo = svm->vmcb->control.exit_int_info; | |
2603 | ||
44c11430 GN |
2604 | if (svm->vcpu.arch.hflags & HF_IRET_MASK) |
2605 | svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK); | |
2606 | ||
9222be18 GN |
2607 | svm->vcpu.arch.nmi_injected = false; |
2608 | kvm_clear_exception_queue(&svm->vcpu); | |
2609 | kvm_clear_interrupt_queue(&svm->vcpu); | |
2610 | ||
2611 | if (!(exitintinfo & SVM_EXITINTINFO_VALID)) | |
2612 | return; | |
2613 | ||
2614 | vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK; | |
2615 | type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK; | |
2616 | ||
2617 | switch (type) { | |
2618 | case SVM_EXITINTINFO_TYPE_NMI: | |
2619 | svm->vcpu.arch.nmi_injected = true; | |
2620 | break; | |
2621 | case SVM_EXITINTINFO_TYPE_EXEPT: | |
2622 | /* In case of software exception do not reinject an exception | |
2623 | vector, but re-execute and instruction instead */ | |
219b65dc AG |
2624 | if (is_nested(svm)) |
2625 | break; | |
66fd3f7f | 2626 | if (kvm_exception_is_soft(vector)) |
9222be18 GN |
2627 | break; |
2628 | if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) { | |
2629 | u32 err = svm->vmcb->control.exit_int_info_err; | |
2630 | kvm_queue_exception_e(&svm->vcpu, vector, err); | |
2631 | ||
2632 | } else | |
2633 | kvm_queue_exception(&svm->vcpu, vector); | |
2634 | break; | |
2635 | case SVM_EXITINTINFO_TYPE_INTR: | |
66fd3f7f | 2636 | kvm_queue_interrupt(&svm->vcpu, vector, false); |
9222be18 GN |
2637 | break; |
2638 | default: | |
2639 | break; | |
2640 | } | |
2641 | } | |
2642 | ||
80e31d4f AK |
2643 | #ifdef CONFIG_X86_64 |
2644 | #define R "r" | |
2645 | #else | |
2646 | #define R "e" | |
2647 | #endif | |
2648 | ||
851ba692 | 2649 | static void svm_vcpu_run(struct kvm_vcpu *vcpu) |
6aa8b732 | 2650 | { |
a2fa3e9f | 2651 | struct vcpu_svm *svm = to_svm(vcpu); |
6aa8b732 AK |
2652 | u16 fs_selector; |
2653 | u16 gs_selector; | |
2654 | u16 ldt_selector; | |
d9e368d6 | 2655 | |
cd3ff653 JR |
2656 | /* |
2657 | * A vmexit emulation is required before the vcpu can be executed | |
2658 | * again. | |
2659 | */ | |
2660 | if (unlikely(svm->nested.exit_required)) | |
2661 | return; | |
2662 | ||
5fdbf976 MT |
2663 | svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX]; |
2664 | svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP]; | |
2665 | svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP]; | |
2666 | ||
e756fc62 | 2667 | pre_svm_run(svm); |
6aa8b732 | 2668 | |
649d6864 JR |
2669 | sync_lapic_to_cr8(vcpu); |
2670 | ||
6aa8b732 | 2671 | save_host_msrs(vcpu); |
d6e88aec AK |
2672 | fs_selector = kvm_read_fs(); |
2673 | gs_selector = kvm_read_gs(); | |
2674 | ldt_selector = kvm_read_ldt(); | |
cda0ffdd | 2675 | svm->vmcb->save.cr2 = vcpu->arch.cr2; |
709ddebf JR |
2676 | /* required for live migration with NPT */ |
2677 | if (npt_enabled) | |
2678 | svm->vmcb->save.cr3 = vcpu->arch.cr3; | |
6aa8b732 | 2679 | |
04d2cc77 AK |
2680 | clgi(); |
2681 | ||
2682 | local_irq_enable(); | |
36241b8c | 2683 | |
6aa8b732 | 2684 | asm volatile ( |
80e31d4f AK |
2685 | "push %%"R"bp; \n\t" |
2686 | "mov %c[rbx](%[svm]), %%"R"bx \n\t" | |
2687 | "mov %c[rcx](%[svm]), %%"R"cx \n\t" | |
2688 | "mov %c[rdx](%[svm]), %%"R"dx \n\t" | |
2689 | "mov %c[rsi](%[svm]), %%"R"si \n\t" | |
2690 | "mov %c[rdi](%[svm]), %%"R"di \n\t" | |
2691 | "mov %c[rbp](%[svm]), %%"R"bp \n\t" | |
05b3e0c2 | 2692 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
2693 | "mov %c[r8](%[svm]), %%r8 \n\t" |
2694 | "mov %c[r9](%[svm]), %%r9 \n\t" | |
2695 | "mov %c[r10](%[svm]), %%r10 \n\t" | |
2696 | "mov %c[r11](%[svm]), %%r11 \n\t" | |
2697 | "mov %c[r12](%[svm]), %%r12 \n\t" | |
2698 | "mov %c[r13](%[svm]), %%r13 \n\t" | |
2699 | "mov %c[r14](%[svm]), %%r14 \n\t" | |
2700 | "mov %c[r15](%[svm]), %%r15 \n\t" | |
6aa8b732 AK |
2701 | #endif |
2702 | ||
6aa8b732 | 2703 | /* Enter guest mode */ |
80e31d4f AK |
2704 | "push %%"R"ax \n\t" |
2705 | "mov %c[vmcb](%[svm]), %%"R"ax \n\t" | |
4ecac3fd AK |
2706 | __ex(SVM_VMLOAD) "\n\t" |
2707 | __ex(SVM_VMRUN) "\n\t" | |
2708 | __ex(SVM_VMSAVE) "\n\t" | |
80e31d4f | 2709 | "pop %%"R"ax \n\t" |
6aa8b732 AK |
2710 | |
2711 | /* Save guest registers, load host registers */ | |
80e31d4f AK |
2712 | "mov %%"R"bx, %c[rbx](%[svm]) \n\t" |
2713 | "mov %%"R"cx, %c[rcx](%[svm]) \n\t" | |
2714 | "mov %%"R"dx, %c[rdx](%[svm]) \n\t" | |
2715 | "mov %%"R"si, %c[rsi](%[svm]) \n\t" | |
2716 | "mov %%"R"di, %c[rdi](%[svm]) \n\t" | |
2717 | "mov %%"R"bp, %c[rbp](%[svm]) \n\t" | |
05b3e0c2 | 2718 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
2719 | "mov %%r8, %c[r8](%[svm]) \n\t" |
2720 | "mov %%r9, %c[r9](%[svm]) \n\t" | |
2721 | "mov %%r10, %c[r10](%[svm]) \n\t" | |
2722 | "mov %%r11, %c[r11](%[svm]) \n\t" | |
2723 | "mov %%r12, %c[r12](%[svm]) \n\t" | |
2724 | "mov %%r13, %c[r13](%[svm]) \n\t" | |
2725 | "mov %%r14, %c[r14](%[svm]) \n\t" | |
2726 | "mov %%r15, %c[r15](%[svm]) \n\t" | |
6aa8b732 | 2727 | #endif |
80e31d4f | 2728 | "pop %%"R"bp" |
6aa8b732 | 2729 | : |
fb3f0f51 | 2730 | : [svm]"a"(svm), |
6aa8b732 | 2731 | [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)), |
ad312c7c ZX |
2732 | [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])), |
2733 | [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])), | |
2734 | [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])), | |
2735 | [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])), | |
2736 | [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])), | |
2737 | [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP])) | |
05b3e0c2 | 2738 | #ifdef CONFIG_X86_64 |
ad312c7c ZX |
2739 | , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])), |
2740 | [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])), | |
2741 | [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])), | |
2742 | [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])), | |
2743 | [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])), | |
2744 | [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])), | |
2745 | [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])), | |
2746 | [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15])) | |
6aa8b732 | 2747 | #endif |
54a08c04 | 2748 | : "cc", "memory" |
80e31d4f | 2749 | , R"bx", R"cx", R"dx", R"si", R"di" |
54a08c04 | 2750 | #ifdef CONFIG_X86_64 |
54a08c04 LV |
2751 | , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15" |
2752 | #endif | |
2753 | ); | |
6aa8b732 | 2754 | |
ad312c7c | 2755 | vcpu->arch.cr2 = svm->vmcb->save.cr2; |
5fdbf976 MT |
2756 | vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax; |
2757 | vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp; | |
2758 | vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip; | |
6aa8b732 | 2759 | |
d6e88aec AK |
2760 | kvm_load_fs(fs_selector); |
2761 | kvm_load_gs(gs_selector); | |
2762 | kvm_load_ldt(ldt_selector); | |
6aa8b732 AK |
2763 | load_host_msrs(vcpu); |
2764 | ||
2765 | reload_tss(vcpu); | |
2766 | ||
56ba47dd AK |
2767 | local_irq_disable(); |
2768 | ||
2769 | stgi(); | |
2770 | ||
d7bf8221 JR |
2771 | sync_cr8_to_lapic(vcpu); |
2772 | ||
a2fa3e9f | 2773 | svm->next_rip = 0; |
9222be18 | 2774 | |
6de4f3ad AK |
2775 | if (npt_enabled) { |
2776 | vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR); | |
2777 | vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR); | |
2778 | } | |
6aa8b732 AK |
2779 | } |
2780 | ||
80e31d4f AK |
2781 | #undef R |
2782 | ||
6aa8b732 AK |
2783 | static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root) |
2784 | { | |
a2fa3e9f GH |
2785 | struct vcpu_svm *svm = to_svm(vcpu); |
2786 | ||
709ddebf JR |
2787 | if (npt_enabled) { |
2788 | svm->vmcb->control.nested_cr3 = root; | |
2789 | force_new_asid(vcpu); | |
2790 | return; | |
2791 | } | |
2792 | ||
a2fa3e9f | 2793 | svm->vmcb->save.cr3 = root; |
6aa8b732 | 2794 | force_new_asid(vcpu); |
7807fa6c AL |
2795 | |
2796 | if (vcpu->fpu_active) { | |
a2fa3e9f GH |
2797 | svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR); |
2798 | svm->vmcb->save.cr0 |= X86_CR0_TS; | |
7807fa6c AL |
2799 | vcpu->fpu_active = 0; |
2800 | } | |
6aa8b732 AK |
2801 | } |
2802 | ||
6aa8b732 AK |
2803 | static int is_disabled(void) |
2804 | { | |
6031a61c JR |
2805 | u64 vm_cr; |
2806 | ||
2807 | rdmsrl(MSR_VM_CR, vm_cr); | |
2808 | if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE)) | |
2809 | return 1; | |
2810 | ||
6aa8b732 AK |
2811 | return 0; |
2812 | } | |
2813 | ||
102d8325 IM |
2814 | static void |
2815 | svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
2816 | { | |
2817 | /* | |
2818 | * Patch in the VMMCALL instruction: | |
2819 | */ | |
2820 | hypercall[0] = 0x0f; | |
2821 | hypercall[1] = 0x01; | |
2822 | hypercall[2] = 0xd9; | |
102d8325 IM |
2823 | } |
2824 | ||
002c7f7c YS |
2825 | static void svm_check_processor_compat(void *rtn) |
2826 | { | |
2827 | *(int *)rtn = 0; | |
2828 | } | |
2829 | ||
774ead3a AK |
2830 | static bool svm_cpu_has_accelerated_tpr(void) |
2831 | { | |
2832 | return false; | |
2833 | } | |
2834 | ||
67253af5 SY |
2835 | static int get_npt_level(void) |
2836 | { | |
2837 | #ifdef CONFIG_X86_64 | |
2838 | return PT64_ROOT_LEVEL; | |
2839 | #else | |
2840 | return PT32E_ROOT_LEVEL; | |
2841 | #endif | |
2842 | } | |
2843 | ||
4b12f0de | 2844 | static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio) |
64d4d521 SY |
2845 | { |
2846 | return 0; | |
2847 | } | |
2848 | ||
229456fc MT |
2849 | static const struct trace_print_flags svm_exit_reasons_str[] = { |
2850 | { SVM_EXIT_READ_CR0, "read_cr0" }, | |
2851 | { SVM_EXIT_READ_CR3, "read_cr3" }, | |
2852 | { SVM_EXIT_READ_CR4, "read_cr4" }, | |
2853 | { SVM_EXIT_READ_CR8, "read_cr8" }, | |
2854 | { SVM_EXIT_WRITE_CR0, "write_cr0" }, | |
2855 | { SVM_EXIT_WRITE_CR3, "write_cr3" }, | |
2856 | { SVM_EXIT_WRITE_CR4, "write_cr4" }, | |
2857 | { SVM_EXIT_WRITE_CR8, "write_cr8" }, | |
2858 | { SVM_EXIT_READ_DR0, "read_dr0" }, | |
2859 | { SVM_EXIT_READ_DR1, "read_dr1" }, | |
2860 | { SVM_EXIT_READ_DR2, "read_dr2" }, | |
2861 | { SVM_EXIT_READ_DR3, "read_dr3" }, | |
2862 | { SVM_EXIT_WRITE_DR0, "write_dr0" }, | |
2863 | { SVM_EXIT_WRITE_DR1, "write_dr1" }, | |
2864 | { SVM_EXIT_WRITE_DR2, "write_dr2" }, | |
2865 | { SVM_EXIT_WRITE_DR3, "write_dr3" }, | |
2866 | { SVM_EXIT_WRITE_DR5, "write_dr5" }, | |
2867 | { SVM_EXIT_WRITE_DR7, "write_dr7" }, | |
2868 | { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" }, | |
2869 | { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" }, | |
2870 | { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" }, | |
2871 | { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" }, | |
2872 | { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" }, | |
2873 | { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" }, | |
2874 | { SVM_EXIT_INTR, "interrupt" }, | |
2875 | { SVM_EXIT_NMI, "nmi" }, | |
2876 | { SVM_EXIT_SMI, "smi" }, | |
2877 | { SVM_EXIT_INIT, "init" }, | |
2878 | { SVM_EXIT_VINTR, "vintr" }, | |
2879 | { SVM_EXIT_CPUID, "cpuid" }, | |
2880 | { SVM_EXIT_INVD, "invd" }, | |
2881 | { SVM_EXIT_HLT, "hlt" }, | |
2882 | { SVM_EXIT_INVLPG, "invlpg" }, | |
2883 | { SVM_EXIT_INVLPGA, "invlpga" }, | |
2884 | { SVM_EXIT_IOIO, "io" }, | |
2885 | { SVM_EXIT_MSR, "msr" }, | |
2886 | { SVM_EXIT_TASK_SWITCH, "task_switch" }, | |
2887 | { SVM_EXIT_SHUTDOWN, "shutdown" }, | |
2888 | { SVM_EXIT_VMRUN, "vmrun" }, | |
2889 | { SVM_EXIT_VMMCALL, "hypercall" }, | |
2890 | { SVM_EXIT_VMLOAD, "vmload" }, | |
2891 | { SVM_EXIT_VMSAVE, "vmsave" }, | |
2892 | { SVM_EXIT_STGI, "stgi" }, | |
2893 | { SVM_EXIT_CLGI, "clgi" }, | |
2894 | { SVM_EXIT_SKINIT, "skinit" }, | |
2895 | { SVM_EXIT_WBINVD, "wbinvd" }, | |
2896 | { SVM_EXIT_MONITOR, "monitor" }, | |
2897 | { SVM_EXIT_MWAIT, "mwait" }, | |
2898 | { SVM_EXIT_NPF, "npf" }, | |
2899 | { -1, NULL } | |
2900 | }; | |
2901 | ||
344f414f JR |
2902 | static bool svm_gb_page_enable(void) |
2903 | { | |
2904 | return true; | |
2905 | } | |
2906 | ||
cbdd1bea | 2907 | static struct kvm_x86_ops svm_x86_ops = { |
6aa8b732 AK |
2908 | .cpu_has_kvm_support = has_svm, |
2909 | .disabled_by_bios = is_disabled, | |
2910 | .hardware_setup = svm_hardware_setup, | |
2911 | .hardware_unsetup = svm_hardware_unsetup, | |
002c7f7c | 2912 | .check_processor_compatibility = svm_check_processor_compat, |
6aa8b732 AK |
2913 | .hardware_enable = svm_hardware_enable, |
2914 | .hardware_disable = svm_hardware_disable, | |
774ead3a | 2915 | .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr, |
6aa8b732 AK |
2916 | |
2917 | .vcpu_create = svm_create_vcpu, | |
2918 | .vcpu_free = svm_free_vcpu, | |
04d2cc77 | 2919 | .vcpu_reset = svm_vcpu_reset, |
6aa8b732 | 2920 | |
04d2cc77 | 2921 | .prepare_guest_switch = svm_prepare_guest_switch, |
6aa8b732 AK |
2922 | .vcpu_load = svm_vcpu_load, |
2923 | .vcpu_put = svm_vcpu_put, | |
2924 | ||
2925 | .set_guest_debug = svm_guest_debug, | |
2926 | .get_msr = svm_get_msr, | |
2927 | .set_msr = svm_set_msr, | |
2928 | .get_segment_base = svm_get_segment_base, | |
2929 | .get_segment = svm_get_segment, | |
2930 | .set_segment = svm_set_segment, | |
2e4d2653 | 2931 | .get_cpl = svm_get_cpl, |
1747fb71 | 2932 | .get_cs_db_l_bits = kvm_get_cs_db_l_bits, |
25c4c276 | 2933 | .decache_cr4_guest_bits = svm_decache_cr4_guest_bits, |
6aa8b732 | 2934 | .set_cr0 = svm_set_cr0, |
6aa8b732 AK |
2935 | .set_cr3 = svm_set_cr3, |
2936 | .set_cr4 = svm_set_cr4, | |
2937 | .set_efer = svm_set_efer, | |
2938 | .get_idt = svm_get_idt, | |
2939 | .set_idt = svm_set_idt, | |
2940 | .get_gdt = svm_get_gdt, | |
2941 | .set_gdt = svm_set_gdt, | |
2942 | .get_dr = svm_get_dr, | |
2943 | .set_dr = svm_set_dr, | |
6de4f3ad | 2944 | .cache_reg = svm_cache_reg, |
6aa8b732 AK |
2945 | .get_rflags = svm_get_rflags, |
2946 | .set_rflags = svm_set_rflags, | |
2947 | ||
6aa8b732 | 2948 | .tlb_flush = svm_flush_tlb, |
6aa8b732 | 2949 | |
6aa8b732 | 2950 | .run = svm_vcpu_run, |
04d2cc77 | 2951 | .handle_exit = handle_exit, |
6aa8b732 | 2952 | .skip_emulated_instruction = skip_emulated_instruction, |
2809f5d2 GC |
2953 | .set_interrupt_shadow = svm_set_interrupt_shadow, |
2954 | .get_interrupt_shadow = svm_get_interrupt_shadow, | |
102d8325 | 2955 | .patch_hypercall = svm_patch_hypercall, |
2a8067f1 | 2956 | .set_irq = svm_set_irq, |
95ba8273 | 2957 | .set_nmi = svm_inject_nmi, |
298101da | 2958 | .queue_exception = svm_queue_exception, |
78646121 | 2959 | .interrupt_allowed = svm_interrupt_allowed, |
95ba8273 GN |
2960 | .nmi_allowed = svm_nmi_allowed, |
2961 | .enable_nmi_window = enable_nmi_window, | |
2962 | .enable_irq_window = enable_irq_window, | |
2963 | .update_cr8_intercept = update_cr8_intercept, | |
cbc94022 IE |
2964 | |
2965 | .set_tss_addr = svm_set_tss_addr, | |
67253af5 | 2966 | .get_tdp_level = get_npt_level, |
4b12f0de | 2967 | .get_mt_mask = svm_get_mt_mask, |
229456fc MT |
2968 | |
2969 | .exit_reasons_str = svm_exit_reasons_str, | |
344f414f | 2970 | .gb_page_enable = svm_gb_page_enable, |
6aa8b732 AK |
2971 | }; |
2972 | ||
2973 | static int __init svm_init(void) | |
2974 | { | |
cb498ea2 | 2975 | return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm), |
c16f862d | 2976 | THIS_MODULE); |
6aa8b732 AK |
2977 | } |
2978 | ||
2979 | static void __exit svm_exit(void) | |
2980 | { | |
cb498ea2 | 2981 | kvm_exit(); |
6aa8b732 AK |
2982 | } |
2983 | ||
2984 | module_init(svm_init) | |
2985 | module_exit(svm_exit) |