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KVM: i8259: simplify pic_irq_request() calling sequence
[deliverable/linux.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
221d059d 8 * Copyright 2010 Red Hat, Inc. and/or its affilates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
e495606d 21
edf88417 22#include <linux/kvm_host.h>
6aa8b732 23#include <linux/module.h>
9d8f549d 24#include <linux/kernel.h>
6aa8b732
AK		 25#include <linux/mm.h>
26#include <linux/highmem.h>
e8edc6e0 27#include <linux/sched.h>
c7addb90 28#include <linux/moduleparam.h>
229456fc 29#include <linux/ftrace_event.h>
5a0e3ad6 30#include <linux/slab.h>
cafd6659 31#include <linux/tboot.h>
5fdbf976 32#include "kvm_cache_regs.h"
35920a35 33#include "x86.h"
e495606d 34
6aa8b732 35#include <asm/io.h>
3b3be0d1 36#include <asm/desc.h>
13673a90 37#include <asm/vmx.h>
6210e37b 38#include <asm/virtext.h>
a0861c02 39#include <asm/mce.h>
2acf923e
DC		 40#include <asm/i387.h>
41#include <asm/xcr.h>
6aa8b732 42
229456fc
MT		 43#include "trace.h"
44
4ecac3fd
AK		 45#define __ex(x) __kvm_handle_fault_on_reboot(x)
46
6aa8b732
AK		 47MODULE_AUTHOR("Qumranet");
48MODULE_LICENSE("GPL");
49
4462d21a 50static int __read_mostly bypass_guest_pf = 1;
c1f8bc04 51module_param(bypass_guest_pf, bool, S_IRUGO);
c7addb90 52
4462d21a 53static int __read_mostly enable_vpid = 1;
736caefe 54module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 55
4462d21a 56static int __read_mostly flexpriority_enabled = 1;
736caefe 57module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 58
4462d21a 59static int __read_mostly enable_ept = 1;
736caefe 60module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 61
3a624e29
NK		 62static int __read_mostly enable_unrestricted_guest = 1;
63module_param_named(unrestricted_guest,
64 enable_unrestricted_guest, bool, S_IRUGO);
65
4462d21a 66static int __read_mostly emulate_invalid_guest_state = 0;
c1f8bc04 67module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 68
b923e62e
DX		 69static int __read_mostly vmm_exclusive = 1;
70module_param(vmm_exclusive, bool, S_IRUGO);
71
cdc0e244
AK		 72#define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
73 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
74#define KVM_GUEST_CR0_MASK \
75 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
76#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
81231c69 77 (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 78#define KVM_VM_CR0_ALWAYS_ON \
79 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 80#define KVM_CR4_GUEST_OWNED_BITS \
81 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
82 | X86_CR4_OSXMMEXCPT)
83
cdc0e244
AK		 84#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
85#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
86
78ac8b47
AK		 87#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
88
4b8d54f9
ZE		 89/*
90 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
91 * ple_gap: upper bound on the amount of time between two successive
92 * executions of PAUSE in a loop. Also indicate if ple enabled.
93 * According to test, this time is usually small than 41 cycles.
94 * ple_window: upper bound on the amount of time a guest is allowed to execute
95 * in a PAUSE loop. Tests indicate that most spinlocks are held for
96 * less than 2^12 cycles
97 * Time is measured based on a counter that runs at the same rate as the TSC,
98 * refer SDM volume 3b section 21.6.13 & 22.1.3.
99 */
100#define KVM_VMX_DEFAULT_PLE_GAP 41
101#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
102static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
103module_param(ple_gap, int, S_IRUGO);
104
105static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
106module_param(ple_window, int, S_IRUGO);
107
61d2ef2c
AK		 108#define NR_AUTOLOAD_MSRS 1
109
a2fa3e9f
GH		 110struct vmcs {
111 u32 revision_id;
112 u32 abort;
113 char data[0];
114};
115
26bb0981
AK		 116struct shared_msr_entry {
117 unsigned index;
118 u64 data;
d5696725 119 u64 mask;
26bb0981
AK		 120};
121
a2fa3e9f 122struct vcpu_vmx {
fb3f0f51 123 struct kvm_vcpu vcpu;
543e4243 124 struct list_head local_vcpus_link;
313dbd49 125 unsigned long host_rsp;
a2fa3e9f 126 int launched;
29bd8a78 127 u8 fail;
1155f76a 128 u32 idt_vectoring_info;
26bb0981 129 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 130 int nmsrs;
131 int save_nmsrs;
a2fa3e9f 132#ifdef CONFIG_X86_64
44ea2b17
AK		 133 u64 msr_host_kernel_gs_base;
134 u64 msr_guest_kernel_gs_base;
a2fa3e9f
GH		 135#endif
136 struct vmcs *vmcs;
61d2ef2c
AK		 137 struct msr_autoload {
138 unsigned nr;
139 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
140 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
141 } msr_autoload;
a2fa3e9f
GH		 142 struct {
143 int loaded;
144 u16 fs_sel, gs_sel, ldt_sel;
152d3f2f
LV		 145 int gs_ldt_reload_needed;
146 int fs_reload_needed;
d77c26fc 147 } host_state;
9c8cba37 148 struct {
7ffd92c5 149 int vm86_active;
78ac8b47 150 ulong save_rflags;
7ffd92c5
AK		 151 struct kvm_save_segment {
152 u16 selector;
153 unsigned long base;
154 u32 limit;
155 u32 ar;
156 } tr, es, ds, fs, gs;
9c8cba37
AK		 157 struct {
158 bool pending;
159 u8 vector;
160 unsigned rip;
161 } irq;
162 } rmode;
2384d2b3 163 int vpid;
04fa4d32 164 bool emulation_required;
3b86cd99
JK		 165
166 /* Support for vnmi-less CPUs */
167 int soft_vnmi_blocked;
168 ktime_t entry_time;
169 s64 vnmi_blocked_time;
a0861c02 170 u32 exit_reason;
4e47c7a6
SY		 171
172 bool rdtscp_enabled;
a2fa3e9f
GH		 173};
174
175static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
176{
fb3f0f51 177 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 178}
179
b7ebfb05 180static int init_rmode(struct kvm *kvm);
4e1096d2 181static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 182static void kvm_cpu_vmxon(u64 addr);
183static void kvm_cpu_vmxoff(void);
75880a01 184
6aa8b732
AK		 185static DEFINE_PER_CPU(struct vmcs *, vmxarea);
186static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
543e4243 187static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
6aa8b732 188
3e7c73e9
AK		 189static unsigned long *vmx_io_bitmap_a;
190static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 191static unsigned long *vmx_msr_bitmap_legacy;
192static unsigned long *vmx_msr_bitmap_longmode;
fdef3ad1 193
2384d2b3
SY		 194static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
195static DEFINE_SPINLOCK(vmx_vpid_lock);
196
1c3d14fe 197static struct vmcs_config {
6aa8b732
AK		 198 int size;
199 int order;
200 u32 revision_id;
1c3d14fe
YS		 201 u32 pin_based_exec_ctrl;
202 u32 cpu_based_exec_ctrl;
f78e0e2e 203 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 204 u32 vmexit_ctrl;
205 u32 vmentry_ctrl;
206} vmcs_config;
6aa8b732 207
efff9e53 208static struct vmx_capability {
d56f546d
SY		 209 u32 ept;
210 u32 vpid;
211} vmx_capability;
212
6aa8b732
AK		 213#define VMX_SEGMENT_FIELD(seg) \
214 [VCPU_SREG_##seg] = { \
215 .selector = GUEST_##seg##_SELECTOR, \
216 .base = GUEST_##seg##_BASE, \
217 .limit = GUEST_##seg##_LIMIT, \
218 .ar_bytes = GUEST_##seg##_AR_BYTES, \
219 }
220
221static struct kvm_vmx_segment_field {
222 unsigned selector;
223 unsigned base;
224 unsigned limit;
225 unsigned ar_bytes;
226} kvm_vmx_segment_fields[] = {
227 VMX_SEGMENT_FIELD(CS),
228 VMX_SEGMENT_FIELD(DS),
229 VMX_SEGMENT_FIELD(ES),
230 VMX_SEGMENT_FIELD(FS),
231 VMX_SEGMENT_FIELD(GS),
232 VMX_SEGMENT_FIELD(SS),
233 VMX_SEGMENT_FIELD(TR),
234 VMX_SEGMENT_FIELD(LDTR),
235};
236
26bb0981
AK		 237static u64 host_efer;
238
6de4f3ad
AK		 239static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
240
4d56c8a7
AK		 241/*
242 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
243 * away by decrementing the array size.
244 */
6aa8b732 245static const u32 vmx_msr_index[] = {
05b3e0c2 246#ifdef CONFIG_X86_64
44ea2b17 247 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 248#endif
4e47c7a6 249 MSR_EFER, MSR_TSC_AUX, MSR_K6_STAR,
6aa8b732 250};
9d8f549d 251#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 252
31299944 253static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 254{
255 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
256 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 257 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 258}
259
31299944 260static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 261{
262 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
263 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 264 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 265}
266
31299944 267static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 268{
269 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
270 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 271 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 272}
273
31299944 274static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 275{
276 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
277 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
278}
279
31299944 280static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 281{
282 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
283 INTR_INFO_VALID_MASK)) ==
284 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
285}
286
31299944 287static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 288{
04547156 289 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 290}
291
31299944 292static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 293{
04547156 294 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 295}
296
31299944 297static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 298{
04547156 299 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 300}
301
31299944 302static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 303{
04547156
SY		 304 return vmcs_config.cpu_based_exec_ctrl &
305 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 306}
307
774ead3a 308static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 309{
04547156
SY		 310 return vmcs_config.cpu_based_2nd_exec_ctrl &
311 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
312}
313
314static inline bool cpu_has_vmx_flexpriority(void)
315{
316 return cpu_has_vmx_tpr_shadow() &&
317 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 318}
319
e799794e
MT		 320static inline bool cpu_has_vmx_ept_execute_only(void)
321{
31299944 322 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 323}
324
325static inline bool cpu_has_vmx_eptp_uncacheable(void)
326{
31299944 327 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 328}
329
330static inline bool cpu_has_vmx_eptp_writeback(void)
331{
31299944 332 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 333}
334
335static inline bool cpu_has_vmx_ept_2m_page(void)
336{
31299944 337 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 338}
339
878403b7
SY		 340static inline bool cpu_has_vmx_ept_1g_page(void)
341{
31299944 342 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 343}
344
4bc9b982
SY		 345static inline bool cpu_has_vmx_ept_4levels(void)
346{
347 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
348}
349
31299944 350static inline bool cpu_has_vmx_invept_individual_addr(void)
d56f546d 351{
31299944 352 return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
d56f546d
SY		 353}
354
31299944 355static inline bool cpu_has_vmx_invept_context(void)
d56f546d 356{
31299944 357 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 358}
359
31299944 360static inline bool cpu_has_vmx_invept_global(void)
d56f546d 361{
31299944 362 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 363}
364
518c8aee
GJ		 365static inline bool cpu_has_vmx_invvpid_single(void)
366{
367 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
368}
369
b9d762fa
GJ		 370static inline bool cpu_has_vmx_invvpid_global(void)
371{
372 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
373}
374
31299944 375static inline bool cpu_has_vmx_ept(void)
d56f546d 376{
04547156
SY		 377 return vmcs_config.cpu_based_2nd_exec_ctrl &
378 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 379}
380
31299944 381static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 382{
383 return vmcs_config.cpu_based_2nd_exec_ctrl &
384 SECONDARY_EXEC_UNRESTRICTED_GUEST;
385}
386
31299944 387static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 388{
389 return vmcs_config.cpu_based_2nd_exec_ctrl &
390 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
391}
392
31299944 393static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 394{
6d3e435e 395 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 396}
397
31299944 398static inline bool cpu_has_vmx_vpid(void)
2384d2b3 399{
04547156
SY		 400 return vmcs_config.cpu_based_2nd_exec_ctrl &
401 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 402}
403
31299944 404static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 405{
406 return vmcs_config.cpu_based_2nd_exec_ctrl &
407 SECONDARY_EXEC_RDTSCP;
408}
409
31299944 410static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 411{
412 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
413}
414
04547156
SY		 415static inline bool report_flexpriority(void)
416{
417 return flexpriority_enabled;
418}
419
8b9cf98c 420static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 421{
422 int i;
423
a2fa3e9f 424 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 425 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 426 return i;
427 return -1;
428}
429
2384d2b3
SY		 430static inline void __invvpid(int ext, u16 vpid, gva_t gva)
431{
432 struct {
433 u64 vpid : 16;
434 u64 rsvd : 48;
435 u64 gva;
436 } operand = { vpid, 0, gva };
437
4ecac3fd 438 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 439 /* CF==1 or ZF==1 --> rc = -1 */
440 "; ja 1f ; ud2 ; 1:"
441 : : "a"(&operand), "c"(ext) : "cc", "memory");
442}
443
1439442c
SY		 444static inline void __invept(int ext, u64 eptp, gpa_t gpa)
445{
446 struct {
447 u64 eptp, gpa;
448 } operand = {eptp, gpa};
449
4ecac3fd 450 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 451 /* CF==1 or ZF==1 --> rc = -1 */
452 "; ja 1f ; ud2 ; 1:\n"
453 : : "a" (&operand), "c" (ext) : "cc", "memory");
454}
455
26bb0981 456static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 457{
458 int i;
459
8b9cf98c 460 i = __find_msr_index(vmx, msr);
a75beee6 461 if (i >= 0)
a2fa3e9f 462 return &vmx->guest_msrs[i];
8b6d44c7 463 return NULL;
7725f0ba
AK		 464}
465
6aa8b732
AK		 466static void vmcs_clear(struct vmcs *vmcs)
467{
468 u64 phys_addr = __pa(vmcs);
469 u8 error;
470
4ecac3fd 471 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
6aa8b732
AK		 472 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
473 : "cc", "memory");
474 if (error)
475 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
476 vmcs, phys_addr);
477}
478
7725b894
DX		 479static void vmcs_load(struct vmcs *vmcs)
480{
481 u64 phys_addr = __pa(vmcs);
482 u8 error;
483
484 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
485 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
486 : "cc", "memory");
487 if (error)
488 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
489 vmcs, phys_addr);
490}
491
6aa8b732
AK		 492static void __vcpu_clear(void *arg)
493{
8b9cf98c 494 struct vcpu_vmx *vmx = arg;
d3b2c338 495 int cpu = raw_smp_processor_id();
6aa8b732 496
8b9cf98c 497 if (vmx->vcpu.cpu == cpu)
a2fa3e9f
GH		 498 vmcs_clear(vmx->vmcs);
499 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
6aa8b732 500 per_cpu(current_vmcs, cpu) = NULL;
ad312c7c 501 rdtscll(vmx->vcpu.arch.host_tsc);
543e4243
AK		 502 list_del(&vmx->local_vcpus_link);
503 vmx->vcpu.cpu = -1;
504 vmx->launched = 0;
6aa8b732
AK		 505}
506
8b9cf98c 507static void vcpu_clear(struct vcpu_vmx *vmx)
8d0be2b3 508{
eae5ecb5
AK		 509 if (vmx->vcpu.cpu == -1)
510 return;
8691e5a8 511 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
8d0be2b3
AK		 512}
513
1760dd49 514static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 515{
516 if (vmx->vpid == 0)
517 return;
518
518c8aee
GJ		 519 if (cpu_has_vmx_invvpid_single())
520 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 521}
522
b9d762fa
GJ		 523static inline void vpid_sync_vcpu_global(void)
524{
525 if (cpu_has_vmx_invvpid_global())
526 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
527}
528
529static inline void vpid_sync_context(struct vcpu_vmx *vmx)
530{
531 if (cpu_has_vmx_invvpid_single())
1760dd49 532 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 533 else
534 vpid_sync_vcpu_global();
535}
536
1439442c
SY		 537static inline void ept_sync_global(void)
538{
539 if (cpu_has_vmx_invept_global())
540 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
541}
542
543static inline void ept_sync_context(u64 eptp)
544{
089d034e 545 if (enable_ept) {
1439442c
SY		 546 if (cpu_has_vmx_invept_context())
547 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
548 else
549 ept_sync_global();
550 }
551}
552
553static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
554{
089d034e 555 if (enable_ept) {
1439442c
SY		 556 if (cpu_has_vmx_invept_individual_addr())
557 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
558 eptp, gpa);
559 else
560 ept_sync_context(eptp);
561 }
562}
563
6aa8b732
AK		 564static unsigned long vmcs_readl(unsigned long field)
565{
566 unsigned long value;
567
4ecac3fd 568 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
6aa8b732
AK		 569 : "=a"(value) : "d"(field) : "cc");
570 return value;
571}
572
573static u16 vmcs_read16(unsigned long field)
574{
575 return vmcs_readl(field);
576}
577
578static u32 vmcs_read32(unsigned long field)
579{
580 return vmcs_readl(field);
581}
582
583static u64 vmcs_read64(unsigned long field)
584{
05b3e0c2 585#ifdef CONFIG_X86_64
6aa8b732
AK		 586 return vmcs_readl(field);
587#else
588 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
589#endif
590}
591
e52de1b8
AK		 592static noinline void vmwrite_error(unsigned long field, unsigned long value)
593{
594 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
595 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
596 dump_stack();
597}
598
6aa8b732
AK		 599static void vmcs_writel(unsigned long field, unsigned long value)
600{
601 u8 error;
602
4ecac3fd 603 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 604 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 605 if (unlikely(error))
606 vmwrite_error(field, value);
6aa8b732
AK		 607}
608
609static void vmcs_write16(unsigned long field, u16 value)
610{
611 vmcs_writel(field, value);
612}
613
614static void vmcs_write32(unsigned long field, u32 value)
615{
616 vmcs_writel(field, value);
617}
618
619static void vmcs_write64(unsigned long field, u64 value)
620{
6aa8b732 621 vmcs_writel(field, value);
7682f2d0 622#ifndef CONFIG_X86_64
6aa8b732
AK		 623 asm volatile ("");
624 vmcs_writel(field+1, value >> 32);
625#endif
626}
627
2ab455cc
AL		 628static void vmcs_clear_bits(unsigned long field, u32 mask)
629{
630 vmcs_writel(field, vmcs_readl(field) & ~mask);
631}
632
633static void vmcs_set_bits(unsigned long field, u32 mask)
634{
635 vmcs_writel(field, vmcs_readl(field) | mask);
636}
637
abd3f2d6
AK		 638static void update_exception_bitmap(struct kvm_vcpu *vcpu)
639{
640 u32 eb;
641
fd7373cc
JK		 642 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
643 (1u << NM_VECTOR) | (1u << DB_VECTOR);
644 if ((vcpu->guest_debug &
645 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
646 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
647 eb |= 1u << BP_VECTOR;
7ffd92c5 648 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 649 eb = ~0;
089d034e 650 if (enable_ept)
1439442c 651 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 652 if (vcpu->fpu_active)
653 eb &= ~(1u << NM_VECTOR);
abd3f2d6
AK		 654 vmcs_write32(EXCEPTION_BITMAP, eb);
655}
656
61d2ef2c
AK		 657static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
658{
659 unsigned i;
660 struct msr_autoload *m = &vmx->msr_autoload;
661
662 for (i = 0; i < m->nr; ++i)
663 if (m->guest[i].index == msr)
664 break;
665
666 if (i == m->nr)
667 return;
668 --m->nr;
669 m->guest[i] = m->guest[m->nr];
670 m->host[i] = m->host[m->nr];
671 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
672 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
673}
674
675static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
676 u64 guest_val, u64 host_val)
677{
678 unsigned i;
679 struct msr_autoload *m = &vmx->msr_autoload;
680
681 for (i = 0; i < m->nr; ++i)
682 if (m->guest[i].index == msr)
683 break;
684
685 if (i == m->nr) {
686 ++m->nr;
687 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
688 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
689 }
690
691 m->guest[i].index = msr;
692 m->guest[i].value = guest_val;
693 m->host[i].index = msr;
694 m->host[i].value = host_val;
695}
696
33ed6329
AK		 697static void reload_tss(void)
698{
33ed6329
AK		 699 /*
700 * VT restores TR but not its size. Useless.
701 */
89a27f4d 702 struct desc_ptr gdt;
a5f61300 703 struct desc_struct *descs;
33ed6329 704
d6ab1ed4 705 native_store_gdt(&gdt);
89a27f4d 706 descs = (void *)gdt.address;
33ed6329
AK		 707 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
708 load_TR_desc();
33ed6329
AK		 709}
710
92c0d900 711static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 712{
3a34a881 713 u64 guest_efer;
51c6cf66
AK		 714 u64 ignore_bits;
715
f6801dff 716 guest_efer = vmx->vcpu.arch.efer;
3a34a881 717
51c6cf66
AK		 718 /*
719 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
720 * outside long mode
721 */
722 ignore_bits = EFER_NX | EFER_SCE;
723#ifdef CONFIG_X86_64
724 ignore_bits |= EFER_LMA | EFER_LME;
725 /* SCE is meaningful only in long mode on Intel */
726 if (guest_efer & EFER_LMA)
727 ignore_bits &= ~(u64)EFER_SCE;
728#endif
51c6cf66
AK		 729 guest_efer &= ~ignore_bits;
730 guest_efer |= host_efer & ignore_bits;
26bb0981 731 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 732 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 733
734 clear_atomic_switch_msr(vmx, MSR_EFER);
735 /* On ept, can't emulate nx, and must switch nx atomically */
736 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
737 guest_efer = vmx->vcpu.arch.efer;
738 if (!(guest_efer & EFER_LMA))
739 guest_efer &= ~EFER_LME;
740 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
741 return false;
742 }
743
26bb0981 744 return true;
51c6cf66
AK		 745}
746
2d49ec72
GN		 747static unsigned long segment_base(u16 selector)
748{
749 struct desc_ptr gdt;
750 struct desc_struct *d;
751 unsigned long table_base;
752 unsigned long v;
753
754 if (!(selector & ~3))
755 return 0;
756
757 native_store_gdt(&gdt);
758 table_base = gdt.address;
759
760 if (selector & 4) { /* from ldt */
761 u16 ldt_selector = kvm_read_ldt();
762
763 if (!(ldt_selector & ~3))
764 return 0;
765
766 table_base = segment_base(ldt_selector);
767 }
768 d = (struct desc_struct *)(table_base + (selector & ~7));
769 v = get_desc_base(d);
770#ifdef CONFIG_X86_64
771 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
772 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
773#endif
774 return v;
775}
776
777static inline unsigned long kvm_read_tr_base(void)
778{
779 u16 tr;
780 asm("str %0" : "=g"(tr));
781 return segment_base(tr);
782}
783
04d2cc77 784static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 785{
04d2cc77 786 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 787 int i;
04d2cc77 788
a2fa3e9f 789 if (vmx->host_state.loaded)
33ed6329
AK		 790 return;
791
a2fa3e9f 792 vmx->host_state.loaded = 1;
33ed6329
AK		 793 /*
794 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
795 * allow segment selectors with cpl > 0 or ti == 1.
796 */
d6e88aec 797 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 798 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
d6e88aec 799 vmx->host_state.fs_sel = kvm_read_fs();
152d3f2f 800 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 801 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 802 vmx->host_state.fs_reload_needed = 0;
803 } else {
33ed6329 804 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 805 vmx->host_state.fs_reload_needed = 1;
33ed6329 806 }
d6e88aec 807 vmx->host_state.gs_sel = kvm_read_gs();
a2fa3e9f
GH		 808 if (!(vmx->host_state.gs_sel & 7))
809 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 810 else {
811 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 812 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 813 }
814
815#ifdef CONFIG_X86_64
816 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
817 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
818#else
a2fa3e9f
GH		 819 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
820 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 821#endif
707c0874
AK		 822
823#ifdef CONFIG_X86_64
44ea2b17
AK		 824 if (is_long_mode(&vmx->vcpu)) {
825 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
826 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
827 }
707c0874 828#endif
26bb0981
AK		 829 for (i = 0; i < vmx->save_nmsrs; ++i)
830 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 831 vmx->guest_msrs[i].data,
832 vmx->guest_msrs[i].mask);
33ed6329
AK		 833}
834
a9b21b62 835static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 836{
15ad7146 837 unsigned long flags;
33ed6329 838
a2fa3e9f 839 if (!vmx->host_state.loaded)
33ed6329
AK		 840 return;
841
e1beb1d3 842 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 843 vmx->host_state.loaded = 0;
152d3f2f 844 if (vmx->host_state.fs_reload_needed)
d6e88aec 845 kvm_load_fs(vmx->host_state.fs_sel);
152d3f2f 846 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 847 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329
AK		 848 /*
849 * If we have to reload gs, we must take care to
850 * preserve our gs base.
851 */
15ad7146 852 local_irq_save(flags);
d6e88aec 853 kvm_load_gs(vmx->host_state.gs_sel);
33ed6329
AK		 854#ifdef CONFIG_X86_64
855 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
856#endif
15ad7146 857 local_irq_restore(flags);
33ed6329 858 }
152d3f2f 859 reload_tss();
44ea2b17
AK		 860#ifdef CONFIG_X86_64
861 if (is_long_mode(&vmx->vcpu)) {
862 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
863 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
864 }
865#endif
1c11e713
AK		 866 if (current_thread_info()->status & TS_USEDFPU)
867 clts();
33ed6329
AK		 868}
869
a9b21b62
AK		 870static void vmx_load_host_state(struct vcpu_vmx *vmx)
871{
872 preempt_disable();
873 __vmx_load_host_state(vmx);
874 preempt_enable();
875}
876
6aa8b732
AK		 877/*
878 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
879 * vcpu mutex is already taken.
880 */
15ad7146 881static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 882{
a2fa3e9f 883 struct vcpu_vmx *vmx = to_vmx(vcpu);
019960ae 884 u64 tsc_this, delta, new_offset;
4610c9cc 885 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 886
4610c9cc
DX		 887 if (!vmm_exclusive)
888 kvm_cpu_vmxon(phys_addr);
889 else if (vcpu->cpu != cpu)
8b9cf98c 890 vcpu_clear(vmx);
6aa8b732 891
a2fa3e9f 892 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
a2fa3e9f 893 per_cpu(current_vmcs, cpu) = vmx->vmcs;
7725b894 894 vmcs_load(vmx->vmcs);
6aa8b732
AK		 895 }
896
897 if (vcpu->cpu != cpu) {
89a27f4d 898 struct desc_ptr dt;
6aa8b732
AK		 899 unsigned long sysenter_esp;
900
92fe13be
DX		 901 kvm_migrate_timers(vcpu);
902 set_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests);
903 local_irq_disable();
904 list_add(&vmx->local_vcpus_link,
905 &per_cpu(vcpus_on_cpu, cpu));
906 local_irq_enable();
907
6aa8b732
AK		 908 vcpu->cpu = cpu;
909 /*
910 * Linux uses per-cpu TSS and GDT, so set these when switching
911 * processors.
912 */
d6e88aec 913 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d6ab1ed4 914 native_store_gdt(&dt);
89a27f4d 915 vmcs_writel(HOST_GDTR_BASE, dt.address); /* 22.2.4 */
6aa8b732
AK		 916
917 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
918 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
7700270e
AK		 919
920 /*
921 * Make sure the time stamp counter is monotonous.
922 */
923 rdtscll(tsc_this);
019960ae
AK		 924 if (tsc_this < vcpu->arch.host_tsc) {
925 delta = vcpu->arch.host_tsc - tsc_this;
926 new_offset = vmcs_read64(TSC_OFFSET) + delta;
927 vmcs_write64(TSC_OFFSET, new_offset);
928 }
6aa8b732 929 }
6aa8b732
AK		 930}
931
932static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
933{
a9b21b62 934 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 935 if (!vmm_exclusive) {
b923e62e 936 __vcpu_clear(to_vmx(vcpu));
4610c9cc
DX		 937 kvm_cpu_vmxoff();
938 }
6aa8b732
AK		 939}
940
5fd86fcf
AK		 941static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
942{
81231c69
AK		 943 ulong cr0;
944
5fd86fcf
AK		 945 if (vcpu->fpu_active)
946 return;
947 vcpu->fpu_active = 1;
81231c69
AK		 948 cr0 = vmcs_readl(GUEST_CR0);
949 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
950 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
951 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 952 update_exception_bitmap(vcpu);
edcafe3c
AK		 953 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
954 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 955}
956
edcafe3c
AK		 957static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
958
5fd86fcf
AK		 959static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
960{
edcafe3c 961 vmx_decache_cr0_guest_bits(vcpu);
81231c69 962 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 963 update_exception_bitmap(vcpu);
edcafe3c
AK		 964 vcpu->arch.cr0_guest_owned_bits = 0;
965 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
966 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 967}
968
6aa8b732
AK		 969static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
970{
78ac8b47 971 unsigned long rflags, save_rflags;
345dcaa8
AK		 972
973 rflags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 974 if (to_vmx(vcpu)->rmode.vm86_active) {
975 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
976 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
977 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
978 }
345dcaa8 979 return rflags;
6aa8b732
AK		 980}
981
982static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
983{
78ac8b47
AK		 984 if (to_vmx(vcpu)->rmode.vm86_active) {
985 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 986 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 987 }
6aa8b732
AK		 988 vmcs_writel(GUEST_RFLAGS, rflags);
989}
990
2809f5d2
GC		 991static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
992{
993 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
994 int ret = 0;
995
996 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 997 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 998 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 999 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 1000
1001 return ret & mask;
1002}
1003
1004static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1005{
1006 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1007 u32 interruptibility = interruptibility_old;
1008
1009 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1010
48005f64 1011 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1012 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1013 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1014 interruptibility |= GUEST_INTR_STATE_STI;
1015
1016 if ((interruptibility != interruptibility_old))
1017 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1018}
1019
6aa8b732
AK		 1020static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1021{
1022 unsigned long rip;
6aa8b732 1023
5fdbf976 1024 rip = kvm_rip_read(vcpu);
6aa8b732 1025 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1026 kvm_rip_write(vcpu, rip);
6aa8b732 1027
2809f5d2
GC		 1028 /* skipping an emulated instruction also counts */
1029 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1030}
1031
298101da 1032static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 1033 bool has_error_code, u32 error_code,
1034 bool reinject)
298101da 1035{
77ab6db0 1036 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 1037 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1038
8ab2d2e2 1039 if (has_error_code) {
77ab6db0 1040 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1041 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1042 }
77ab6db0 1043
7ffd92c5 1044 if (vmx->rmode.vm86_active) {
77ab6db0
JK		 1045 vmx->rmode.irq.pending = true;
1046 vmx->rmode.irq.vector = nr;
1047 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
ae0bb3e0
GN		 1048 if (kvm_exception_is_soft(nr))
1049 vmx->rmode.irq.rip +=
1050 vmx->vcpu.arch.event_exit_inst_len;
8ab2d2e2
JK		 1051 intr_info |= INTR_TYPE_SOFT_INTR;
1052 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
77ab6db0
JK		 1053 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
1054 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
1055 return;
1056 }
1057
66fd3f7f
GN		 1058 if (kvm_exception_is_soft(nr)) {
1059 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1060 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1061 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1062 } else
1063 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1064
1065 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 1066}
1067
4e47c7a6
SY		 1068static bool vmx_rdtscp_supported(void)
1069{
1070 return cpu_has_vmx_rdtscp();
1071}
1072
a75beee6
ED		 1073/*
1074 * Swap MSR entry in host/guest MSR entry array.
1075 */
8b9cf98c 1076static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1077{
26bb0981 1078 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1079
1080 tmp = vmx->guest_msrs[to];
1081 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1082 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1083}
1084
e38aea3e
AK		 1085/*
1086 * Set up the vmcs to automatically save and restore system
1087 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1088 * mode, as fiddling with msrs is very expensive.
1089 */
8b9cf98c 1090static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1091{
26bb0981 1092 int save_nmsrs, index;
5897297b 1093 unsigned long *msr_bitmap;
e38aea3e 1094
33f9c505 1095 vmx_load_host_state(vmx);
a75beee6
ED		 1096 save_nmsrs = 0;
1097#ifdef CONFIG_X86_64
8b9cf98c 1098 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 1099 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 1100 if (index >= 0)
8b9cf98c
RR		 1101 move_msr_up(vmx, index, save_nmsrs++);
1102 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 1103 if (index >= 0)
8b9cf98c
RR		 1104 move_msr_up(vmx, index, save_nmsrs++);
1105 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 1106 if (index >= 0)
8b9cf98c 1107 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 1108 index = __find_msr_index(vmx, MSR_TSC_AUX);
1109 if (index >= 0 && vmx->rdtscp_enabled)
1110 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 1111 /*
1112 * MSR_K6_STAR is only needed on long mode guests, and only
1113 * if efer.sce is enabled.
1114 */
8b9cf98c 1115 index = __find_msr_index(vmx, MSR_K6_STAR);
f6801dff 1116 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 1117 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 1118 }
1119#endif
92c0d900
AK		 1120 index = __find_msr_index(vmx, MSR_EFER);
1121 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 1122 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 1123
26bb0981 1124 vmx->save_nmsrs = save_nmsrs;
5897297b
AK		 1125
1126 if (cpu_has_vmx_msr_bitmap()) {
1127 if (is_long_mode(&vmx->vcpu))
1128 msr_bitmap = vmx_msr_bitmap_longmode;
1129 else
1130 msr_bitmap = vmx_msr_bitmap_legacy;
1131
1132 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1133 }
e38aea3e
AK		 1134}
1135
6aa8b732
AK		 1136/*
1137 * reads and returns guest's timestamp counter "register"
1138 * guest_tsc = host_tsc + tsc_offset -- 21.3
1139 */
1140static u64 guest_read_tsc(void)
1141{
1142 u64 host_tsc, tsc_offset;
1143
1144 rdtscll(host_tsc);
1145 tsc_offset = vmcs_read64(TSC_OFFSET);
1146 return host_tsc + tsc_offset;
1147}
1148
1149/*
1150 * writes 'guest_tsc' into guest's timestamp counter "register"
1151 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
1152 */
53f658b3 1153static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
6aa8b732 1154{
6aa8b732
AK		 1155 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
1156}
1157
6aa8b732
AK		 1158/*
1159 * Reads an msr value (of 'msr_index') into 'pdata'.
1160 * Returns 0 on success, non-0 otherwise.
1161 * Assumes vcpu_load() was already called.
1162 */
1163static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1164{
1165 u64 data;
26bb0981 1166 struct shared_msr_entry *msr;
6aa8b732
AK		 1167
1168 if (!pdata) {
1169 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1170 return -EINVAL;
1171 }
1172
1173 switch (msr_index) {
05b3e0c2 1174#ifdef CONFIG_X86_64
6aa8b732
AK		 1175 case MSR_FS_BASE:
1176 data = vmcs_readl(GUEST_FS_BASE);
1177 break;
1178 case MSR_GS_BASE:
1179 data = vmcs_readl(GUEST_GS_BASE);
1180 break;
44ea2b17
AK		 1181 case MSR_KERNEL_GS_BASE:
1182 vmx_load_host_state(to_vmx(vcpu));
1183 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1184 break;
26bb0981 1185#endif
6aa8b732 1186 case MSR_EFER:
3bab1f5d 1187 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 1188 case MSR_IA32_TSC:
6aa8b732
AK		 1189 data = guest_read_tsc();
1190 break;
1191 case MSR_IA32_SYSENTER_CS:
1192 data = vmcs_read32(GUEST_SYSENTER_CS);
1193 break;
1194 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1195 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 1196 break;
1197 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1198 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 1199 break;
4e47c7a6
SY		 1200 case MSR_TSC_AUX:
1201 if (!to_vmx(vcpu)->rdtscp_enabled)
1202 return 1;
1203 /* Otherwise falls through */
6aa8b732 1204 default:
26bb0981 1205 vmx_load_host_state(to_vmx(vcpu));
8b9cf98c 1206 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d 1207 if (msr) {
542423b0 1208 vmx_load_host_state(to_vmx(vcpu));
3bab1f5d
AK		 1209 data = msr->data;
1210 break;
6aa8b732 1211 }
3bab1f5d 1212 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 1213 }
1214
1215 *pdata = data;
1216 return 0;
1217}
1218
1219/*
1220 * Writes msr value into into the appropriate "register".
1221 * Returns 0 on success, non-0 otherwise.
1222 * Assumes vcpu_load() was already called.
1223 */
1224static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1225{
a2fa3e9f 1226 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1227 struct shared_msr_entry *msr;
53f658b3 1228 u64 host_tsc;
2cc51560
ED		 1229 int ret = 0;
1230
6aa8b732 1231 switch (msr_index) {
3bab1f5d 1232 case MSR_EFER:
a9b21b62 1233 vmx_load_host_state(vmx);
2cc51560 1234 ret = kvm_set_msr_common(vcpu, msr_index, data);
2cc51560 1235 break;
16175a79 1236#ifdef CONFIG_X86_64
6aa8b732
AK		 1237 case MSR_FS_BASE:
1238 vmcs_writel(GUEST_FS_BASE, data);
1239 break;
1240 case MSR_GS_BASE:
1241 vmcs_writel(GUEST_GS_BASE, data);
1242 break;
44ea2b17
AK		 1243 case MSR_KERNEL_GS_BASE:
1244 vmx_load_host_state(vmx);
1245 vmx->msr_guest_kernel_gs_base = data;
1246 break;
6aa8b732
AK		 1247#endif
1248 case MSR_IA32_SYSENTER_CS:
1249 vmcs_write32(GUEST_SYSENTER_CS, data);
1250 break;
1251 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1252 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 1253 break;
1254 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1255 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 1256 break;
af24a4e4 1257 case MSR_IA32_TSC:
53f658b3
MT		 1258 rdtscll(host_tsc);
1259 guest_write_tsc(data, host_tsc);
6aa8b732 1260 break;
468d472f
SY		 1261 case MSR_IA32_CR_PAT:
1262 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1263 vmcs_write64(GUEST_IA32_PAT, data);
1264 vcpu->arch.pat = data;
1265 break;
1266 }
4e47c7a6
SY		 1267 ret = kvm_set_msr_common(vcpu, msr_index, data);
1268 break;
1269 case MSR_TSC_AUX:
1270 if (!vmx->rdtscp_enabled)
1271 return 1;
1272 /* Check reserved bit, higher 32 bits should be zero */
1273 if ((data >> 32) != 0)
1274 return 1;
1275 /* Otherwise falls through */
6aa8b732 1276 default:
8b9cf98c 1277 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 1278 if (msr) {
542423b0 1279 vmx_load_host_state(vmx);
3bab1f5d
AK		 1280 msr->data = data;
1281 break;
6aa8b732 1282 }
2cc51560 1283 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 1284 }
1285
2cc51560 1286 return ret;
6aa8b732
AK		 1287}
1288
5fdbf976 1289static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 1290{
5fdbf976
MT		 1291 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1292 switch (reg) {
1293 case VCPU_REGS_RSP:
1294 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1295 break;
1296 case VCPU_REGS_RIP:
1297 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1298 break;
6de4f3ad
AK		 1299 case VCPU_EXREG_PDPTR:
1300 if (enable_ept)
1301 ept_save_pdptrs(vcpu);
1302 break;
5fdbf976
MT		 1303 default:
1304 break;
1305 }
6aa8b732
AK		 1306}
1307
355be0b9 1308static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
6aa8b732 1309{
ae675ef0
JK		 1310 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1311 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1312 else
1313 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1314
abd3f2d6 1315 update_exception_bitmap(vcpu);
6aa8b732
AK		 1316}
1317
1318static __init int cpu_has_kvm_support(void)
1319{
6210e37b 1320 return cpu_has_vmx();
6aa8b732
AK		 1321}
1322
1323static __init int vmx_disabled_by_bios(void)
1324{
1325 u64 msr;
1326
1327 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659
SW		 1328 if (msr & FEATURE_CONTROL_LOCKED) {
1329 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
1330 && tboot_enabled())
1331 return 1;
1332 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
1333 && !tboot_enabled())
1334 return 1;
1335 }
1336
1337 return 0;
62b3ffb8 1338 /* locked but not enabled */
6aa8b732
AK		 1339}
1340
7725b894
DX		 1341static void kvm_cpu_vmxon(u64 addr)
1342{
1343 asm volatile (ASM_VMX_VMXON_RAX
1344 : : "a"(&addr), "m"(addr)
1345 : "memory", "cc");
1346}
1347
10474ae8 1348static int hardware_enable(void *garbage)
6aa8b732
AK		 1349{
1350 int cpu = raw_smp_processor_id();
1351 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 1352 u64 old, test_bits;
6aa8b732 1353
10474ae8
AG		 1354 if (read_cr4() & X86_CR4_VMXE)
1355 return -EBUSY;
1356
543e4243 1357 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
6aa8b732 1358 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 1359
1360 test_bits = FEATURE_CONTROL_LOCKED;
1361 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
1362 if (tboot_enabled())
1363 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
1364
1365 if ((old & test_bits) != test_bits) {
6aa8b732 1366 /* enable and lock */
cafd6659
SW		 1367 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
1368 }
66aee91a 1369 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 1370
4610c9cc
DX		 1371 if (vmm_exclusive) {
1372 kvm_cpu_vmxon(phys_addr);
1373 ept_sync_global();
1374 }
10474ae8
AG		 1375
1376 return 0;
6aa8b732
AK		 1377}
1378
543e4243
AK		 1379static void vmclear_local_vcpus(void)
1380{
1381 int cpu = raw_smp_processor_id();
1382 struct vcpu_vmx *vmx, *n;
1383
1384 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1385 local_vcpus_link)
1386 __vcpu_clear(vmx);
1387}
1388
710ff4a8
EH		 1389
1390/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1391 * tricks.
1392 */
1393static void kvm_cpu_vmxoff(void)
6aa8b732 1394{
4ecac3fd 1395 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 1396}
1397
710ff4a8
EH		 1398static void hardware_disable(void *garbage)
1399{
4610c9cc
DX		 1400 if (vmm_exclusive) {
1401 vmclear_local_vcpus();
1402 kvm_cpu_vmxoff();
1403 }
7725b894 1404 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 1405}
1406
1c3d14fe 1407static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 1408 u32 msr, u32 *result)
1c3d14fe
YS		 1409{
1410 u32 vmx_msr_low, vmx_msr_high;
1411 u32 ctl = ctl_min | ctl_opt;
1412
1413 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1414
1415 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1416 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1417
1418 /* Ensure minimum (required) set of control bits are supported. */
1419 if (ctl_min & ~ctl)
002c7f7c 1420 return -EIO;
1c3d14fe
YS		 1421
1422 *result = ctl;
1423 return 0;
1424}
1425
002c7f7c 1426static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 1427{
1428 u32 vmx_msr_low, vmx_msr_high;
d56f546d 1429 u32 min, opt, min2, opt2;
1c3d14fe
YS		 1430 u32 _pin_based_exec_control = 0;
1431 u32 _cpu_based_exec_control = 0;
f78e0e2e 1432 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 1433 u32 _vmexit_control = 0;
1434 u32 _vmentry_control = 0;
1435
1436 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 1437 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 1438 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1439 &_pin_based_exec_control) < 0)
002c7f7c 1440 return -EIO;
1c3d14fe
YS		 1441
1442 min = CPU_BASED_HLT_EXITING |
1443#ifdef CONFIG_X86_64
1444 CPU_BASED_CR8_LOAD_EXITING |
1445 CPU_BASED_CR8_STORE_EXITING |
1446#endif
d56f546d
SY		 1447 CPU_BASED_CR3_LOAD_EXITING |
1448 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 1449 CPU_BASED_USE_IO_BITMAPS |
1450 CPU_BASED_MOV_DR_EXITING |
a7052897 1451 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 1452 CPU_BASED_MWAIT_EXITING |
1453 CPU_BASED_MONITOR_EXITING |
a7052897 1454 CPU_BASED_INVLPG_EXITING;
f78e0e2e 1455 opt = CPU_BASED_TPR_SHADOW |
25c5f225 1456 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 1457 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 1458 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1459 &_cpu_based_exec_control) < 0)
002c7f7c 1460 return -EIO;
6e5d865c
YS		 1461#ifdef CONFIG_X86_64
1462 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1463 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1464 ~CPU_BASED_CR8_STORE_EXITING;
1465#endif
f78e0e2e 1466 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 1467 min2 = 0;
1468 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 1469 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 1470 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 1471 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 1472 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6
SY		 1473 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
1474 SECONDARY_EXEC_RDTSCP;
d56f546d
SY		 1475 if (adjust_vmx_controls(min2, opt2,
1476 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 1477 &_cpu_based_2nd_exec_control) < 0)
1478 return -EIO;
1479 }
1480#ifndef CONFIG_X86_64
1481 if (!(_cpu_based_2nd_exec_control &
1482 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1483 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1484#endif
d56f546d 1485 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 1486 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1487 enabled */
5fff7d27
GN		 1488 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1489 CPU_BASED_CR3_STORE_EXITING |
1490 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 1491 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1492 vmx_capability.ept, vmx_capability.vpid);
1493 }
1c3d14fe
YS		 1494
1495 min = 0;
1496#ifdef CONFIG_X86_64
1497 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1498#endif
468d472f 1499 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1c3d14fe
YS		 1500 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1501 &_vmexit_control) < 0)
002c7f7c 1502 return -EIO;
1c3d14fe 1503
468d472f
SY		 1504 min = 0;
1505 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 1506 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1507 &_vmentry_control) < 0)
002c7f7c 1508 return -EIO;
6aa8b732 1509
c68876fd 1510 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 1511
1512 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1513 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 1514 return -EIO;
1c3d14fe
YS		 1515
1516#ifdef CONFIG_X86_64
1517 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1518 if (vmx_msr_high & (1u<<16))
002c7f7c 1519 return -EIO;
1c3d14fe
YS		 1520#endif
1521
1522 /* Require Write-Back (WB) memory type for VMCS accesses. */
1523 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 1524 return -EIO;
1c3d14fe 1525
002c7f7c
YS		 1526 vmcs_conf->size = vmx_msr_high & 0x1fff;
1527 vmcs_conf->order = get_order(vmcs_config.size);
1528 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 1529
002c7f7c
YS		 1530 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1531 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 1532 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 1533 vmcs_conf->vmexit_ctrl = _vmexit_control;
1534 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe
YS		 1535
1536 return 0;
c68876fd 1537}
6aa8b732
AK		 1538
1539static struct vmcs *alloc_vmcs_cpu(int cpu)
1540{
1541 int node = cpu_to_node(cpu);
1542 struct page *pages;
1543 struct vmcs *vmcs;
1544
6484eb3e 1545 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 1546 if (!pages)
1547 return NULL;
1548 vmcs = page_address(pages);
1c3d14fe
YS		 1549 memset(vmcs, 0, vmcs_config.size);
1550 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 1551 return vmcs;
1552}
1553
1554static struct vmcs *alloc_vmcs(void)
1555{
d3b2c338 1556 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 1557}
1558
1559static void free_vmcs(struct vmcs *vmcs)
1560{
1c3d14fe 1561 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 1562}
1563
39959588 1564static void free_kvm_area(void)
6aa8b732
AK		 1565{
1566 int cpu;
1567
3230bb47 1568 for_each_possible_cpu(cpu) {
6aa8b732 1569 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 1570 per_cpu(vmxarea, cpu) = NULL;
1571 }
6aa8b732
AK		 1572}
1573
6aa8b732
AK		 1574static __init int alloc_kvm_area(void)
1575{
1576 int cpu;
1577
3230bb47 1578 for_each_possible_cpu(cpu) {
6aa8b732
AK		 1579 struct vmcs *vmcs;
1580
1581 vmcs = alloc_vmcs_cpu(cpu);
1582 if (!vmcs) {
1583 free_kvm_area();
1584 return -ENOMEM;
1585 }
1586
1587 per_cpu(vmxarea, cpu) = vmcs;
1588 }
1589 return 0;
1590}
1591
1592static __init int hardware_setup(void)
1593{
002c7f7c
YS		 1594 if (setup_vmcs_config(&vmcs_config) < 0)
1595 return -EIO;
50a37eb4
JR		 1596
1597 if (boot_cpu_has(X86_FEATURE_NX))
1598 kvm_enable_efer_bits(EFER_NX);
1599
93ba03c2
SY		 1600 if (!cpu_has_vmx_vpid())
1601 enable_vpid = 0;
1602
4bc9b982
SY		 1603 if (!cpu_has_vmx_ept() ||
1604 !cpu_has_vmx_ept_4levels()) {
93ba03c2 1605 enable_ept = 0;
3a624e29
NK		 1606 enable_unrestricted_guest = 0;
1607 }
1608
1609 if (!cpu_has_vmx_unrestricted_guest())
1610 enable_unrestricted_guest = 0;
93ba03c2
SY		 1611
1612 if (!cpu_has_vmx_flexpriority())
1613 flexpriority_enabled = 0;
1614
95ba8273
GN		 1615 if (!cpu_has_vmx_tpr_shadow())
1616 kvm_x86_ops->update_cr8_intercept = NULL;
1617
54dee993
MT		 1618 if (enable_ept && !cpu_has_vmx_ept_2m_page())
1619 kvm_disable_largepages();
1620
4b8d54f9
ZE		 1621 if (!cpu_has_vmx_ple())
1622 ple_gap = 0;
1623
6aa8b732
AK		 1624 return alloc_kvm_area();
1625}
1626
1627static __exit void hardware_unsetup(void)
1628{
1629 free_kvm_area();
1630}
1631
6aa8b732
AK		 1632static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1633{
1634 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1635
6af11b9e 1636 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 1637 vmcs_write16(sf->selector, save->selector);
1638 vmcs_writel(sf->base, save->base);
1639 vmcs_write32(sf->limit, save->limit);
1640 vmcs_write32(sf->ar_bytes, save->ar);
1641 } else {
1642 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1643 << AR_DPL_SHIFT;
1644 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1645 }
1646}
1647
1648static void enter_pmode(struct kvm_vcpu *vcpu)
1649{
1650 unsigned long flags;
a89a8fb9 1651 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1652
a89a8fb9 1653 vmx->emulation_required = 1;
7ffd92c5 1654 vmx->rmode.vm86_active = 0;
6aa8b732 1655
7ffd92c5
AK		 1656 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1657 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1658 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
6aa8b732
AK		 1659
1660 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 1661 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1662 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 1663 vmcs_writel(GUEST_RFLAGS, flags);
1664
66aee91a
RR		 1665 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1666 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 1667
1668 update_exception_bitmap(vcpu);
1669
a89a8fb9
MG		 1670 if (emulate_invalid_guest_state)
1671 return;
1672
7ffd92c5
AK		 1673 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1674 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1675 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1676 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
6aa8b732
AK		 1677
1678 vmcs_write16(GUEST_SS_SELECTOR, 0);
1679 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1680
1681 vmcs_write16(GUEST_CS_SELECTOR,
1682 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1683 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1684}
1685
d77c26fc 1686static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 1687{
bfc6d222 1688 if (!kvm->arch.tss_addr) {
bc6678a3
MT		 1689 struct kvm_memslots *slots;
1690 gfn_t base_gfn;
1691
90d83dc3 1692 slots = kvm_memslots(kvm);
f495c6e5 1693 base_gfn = slots->memslots[0].base_gfn +
46a26bf5 1694 kvm->memslots->memslots[0].npages - 3;
cbc94022
IE		 1695 return base_gfn << PAGE_SHIFT;
1696 }
bfc6d222 1697 return kvm->arch.tss_addr;
6aa8b732
AK		 1698}
1699
1700static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1701{
1702 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1703
1704 save->selector = vmcs_read16(sf->selector);
1705 save->base = vmcs_readl(sf->base);
1706 save->limit = vmcs_read32(sf->limit);
1707 save->ar = vmcs_read32(sf->ar_bytes);
15b00f32
JK		 1708 vmcs_write16(sf->selector, save->base >> 4);
1709 vmcs_write32(sf->base, save->base & 0xfffff);
6aa8b732
AK		 1710 vmcs_write32(sf->limit, 0xffff);
1711 vmcs_write32(sf->ar_bytes, 0xf3);
1712}
1713
1714static void enter_rmode(struct kvm_vcpu *vcpu)
1715{
1716 unsigned long flags;
a89a8fb9 1717 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1718
3a624e29
NK		 1719 if (enable_unrestricted_guest)
1720 return;
1721
a89a8fb9 1722 vmx->emulation_required = 1;
7ffd92c5 1723 vmx->rmode.vm86_active = 1;
6aa8b732 1724
7ffd92c5 1725 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
6aa8b732
AK		 1726 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1727
7ffd92c5 1728 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
6aa8b732
AK		 1729 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1730
7ffd92c5 1731 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
6aa8b732
AK		 1732 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1733
1734 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 1735 vmx->rmode.save_rflags = flags;
6aa8b732 1736
053de044 1737 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 1738
1739 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 1740 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 1741 update_exception_bitmap(vcpu);
1742
a89a8fb9
MG		 1743 if (emulate_invalid_guest_state)
1744 goto continue_rmode;
1745
6aa8b732
AK		 1746 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1747 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1748 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1749
1750 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 1751 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 1752 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1753 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 1754 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1755
7ffd92c5
AK		 1756 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1757 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1758 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1759 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
75880a01 1760
a89a8fb9 1761continue_rmode:
8668a3c4 1762 kvm_mmu_reset_context(vcpu);
b7ebfb05 1763 init_rmode(vcpu->kvm);
6aa8b732
AK		 1764}
1765
401d10de
AS		 1766static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1767{
1768 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 1769 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1770
1771 if (!msr)
1772 return;
401d10de 1773
44ea2b17
AK		 1774 /*
1775 * Force kernel_gs_base reloading before EFER changes, as control
1776 * of this msr depends on is_long_mode().
1777 */
1778 vmx_load_host_state(to_vmx(vcpu));
f6801dff 1779 vcpu->arch.efer = efer;
401d10de
AS		 1780 if (efer & EFER_LMA) {
1781 vmcs_write32(VM_ENTRY_CONTROLS,
1782 vmcs_read32(VM_ENTRY_CONTROLS) |
1783 VM_ENTRY_IA32E_MODE);
1784 msr->data = efer;
1785 } else {
1786 vmcs_write32(VM_ENTRY_CONTROLS,
1787 vmcs_read32(VM_ENTRY_CONTROLS) &
1788 ~VM_ENTRY_IA32E_MODE);
1789
1790 msr->data = efer & ~EFER_LME;
1791 }
1792 setup_msrs(vmx);
1793}
1794
05b3e0c2 1795#ifdef CONFIG_X86_64
6aa8b732
AK		 1796
1797static void enter_lmode(struct kvm_vcpu *vcpu)
1798{
1799 u32 guest_tr_ar;
1800
1801 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1802 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1803 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
b8688d51 1804 __func__);
6aa8b732
AK		 1805 vmcs_write32(GUEST_TR_AR_BYTES,
1806 (guest_tr_ar & ~AR_TYPE_MASK)
1807 | AR_TYPE_BUSY_64_TSS);
1808 }
da38f438 1809 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 1810}
1811
1812static void exit_lmode(struct kvm_vcpu *vcpu)
1813{
6aa8b732
AK		 1814 vmcs_write32(VM_ENTRY_CONTROLS,
1815 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1816 & ~VM_ENTRY_IA32E_MODE);
da38f438 1817 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 1818}
1819
1820#endif
1821
2384d2b3
SY		 1822static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1823{
b9d762fa 1824 vpid_sync_context(to_vmx(vcpu));
089d034e 1825 if (enable_ept)
4e1096d2 1826 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2384d2b3
SY		 1827}
1828
e8467fda
AK		 1829static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1830{
1831 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
1832
1833 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
1834 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
1835}
1836
25c4c276 1837static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 1838{
fc78f519
AK		 1839 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
1840
1841 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
1842 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 1843}
1844
1439442c
SY		 1845static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1846{
6de4f3ad
AK		 1847 if (!test_bit(VCPU_EXREG_PDPTR,
1848 (unsigned long *)&vcpu->arch.regs_dirty))
1849 return;
1850
1439442c 1851 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1439442c
SY		 1852 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1853 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1854 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1855 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1856 }
1857}
1858
8f5d549f
AK		 1859static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1860{
1861 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1862 vcpu->arch.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1863 vcpu->arch.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1864 vcpu->arch.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1865 vcpu->arch.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1866 }
6de4f3ad
AK		 1867
1868 __set_bit(VCPU_EXREG_PDPTR,
1869 (unsigned long *)&vcpu->arch.regs_avail);
1870 __set_bit(VCPU_EXREG_PDPTR,
1871 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 1872}
1873
1439442c
SY		 1874static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1875
1876static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1877 unsigned long cr0,
1878 struct kvm_vcpu *vcpu)
1879{
1880 if (!(cr0 & X86_CR0_PG)) {
1881 /* From paging/starting to nonpaging */
1882 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1883 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 1884 (CPU_BASED_CR3_LOAD_EXITING |
1885 CPU_BASED_CR3_STORE_EXITING));
1886 vcpu->arch.cr0 = cr0;
fc78f519 1887 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 1888 } else if (!is_paging(vcpu)) {
1889 /* From nonpaging to paging */
1890 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1891 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 1892 ~(CPU_BASED_CR3_LOAD_EXITING |
1893 CPU_BASED_CR3_STORE_EXITING));
1894 vcpu->arch.cr0 = cr0;
fc78f519 1895 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 1896 }
95eb84a7
SY		 1897
1898 if (!(cr0 & X86_CR0_WP))
1899 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 1900}
1901
6aa8b732
AK		 1902static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1903{
7ffd92c5 1904 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 1905 unsigned long hw_cr0;
1906
1907 if (enable_unrestricted_guest)
1908 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1909 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1910 else
1911 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1439442c 1912
7ffd92c5 1913 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 1914 enter_pmode(vcpu);
1915
7ffd92c5 1916 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 1917 enter_rmode(vcpu);
1918
05b3e0c2 1919#ifdef CONFIG_X86_64
f6801dff 1920 if (vcpu->arch.efer & EFER_LME) {
707d92fa 1921 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 1922 enter_lmode(vcpu);
707d92fa 1923 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 1924 exit_lmode(vcpu);
1925 }
1926#endif
1927
089d034e 1928 if (enable_ept)
1439442c
SY		 1929 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1930
02daab21 1931 if (!vcpu->fpu_active)
81231c69 1932 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 1933
6aa8b732 1934 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 1935 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 1936 vcpu->arch.cr0 = cr0;
6aa8b732
AK		 1937}
1938
1439442c
SY		 1939static u64 construct_eptp(unsigned long root_hpa)
1940{
1941 u64 eptp;
1942
1943 /* TODO write the value reading from MSR */
1944 eptp = VMX_EPT_DEFAULT_MT |
1945 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1946 eptp |= (root_hpa & PAGE_MASK);
1947
1948 return eptp;
1949}
1950
6aa8b732
AK		 1951static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1952{
1439442c
SY		 1953 unsigned long guest_cr3;
1954 u64 eptp;
1955
1956 guest_cr3 = cr3;
089d034e 1957 if (enable_ept) {
1439442c
SY		 1958 eptp = construct_eptp(cr3);
1959 vmcs_write64(EPT_POINTER, eptp);
1439442c 1960 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
b927a3ce 1961 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 1962 ept_load_pdptrs(vcpu);
1439442c
SY		 1963 }
1964
2384d2b3 1965 vmx_flush_tlb(vcpu);
1439442c 1966 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 1967}
1968
1969static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1970{
7ffd92c5 1971 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 1972 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1973
ad312c7c 1974 vcpu->arch.cr4 = cr4;
bc23008b
AK		 1975 if (enable_ept) {
1976 if (!is_paging(vcpu)) {
1977 hw_cr4 &= ~X86_CR4_PAE;
1978 hw_cr4 |= X86_CR4_PSE;
1979 } else if (!(cr4 & X86_CR4_PAE)) {
1980 hw_cr4 &= ~X86_CR4_PAE;
1981 }
1982 }
1439442c
SY		 1983
1984 vmcs_writel(CR4_READ_SHADOW, cr4);
1985 vmcs_writel(GUEST_CR4, hw_cr4);
6aa8b732
AK		 1986}
1987
6aa8b732
AK		 1988static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1989{
1990 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1991
1992 return vmcs_readl(sf->base);
1993}
1994
1995static void vmx_get_segment(struct kvm_vcpu *vcpu,
1996 struct kvm_segment *var, int seg)
1997{
1998 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1999 u32 ar;
2000
2001 var->base = vmcs_readl(sf->base);
2002 var->limit = vmcs_read32(sf->limit);
2003 var->selector = vmcs_read16(sf->selector);
2004 ar = vmcs_read32(sf->ar_bytes);
9fd4a3b7 2005 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
6aa8b732
AK		 2006 ar = 0;
2007 var->type = ar & 15;
2008 var->s = (ar >> 4) & 1;
2009 var->dpl = (ar >> 5) & 3;
2010 var->present = (ar >> 7) & 1;
2011 var->avl = (ar >> 12) & 1;
2012 var->l = (ar >> 13) & 1;
2013 var->db = (ar >> 14) & 1;
2014 var->g = (ar >> 15) & 1;
2015 var->unusable = (ar >> 16) & 1;
2016}
2017
2e4d2653
IE		 2018static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2019{
3eeb3288 2020 if (!is_protmode(vcpu))
2e4d2653
IE		 2021 return 0;
2022
2023 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
2024 return 3;
2025
eab4b8aa 2026 return vmcs_read16(GUEST_CS_SELECTOR) & 3;
2e4d2653
IE		 2027}
2028
653e3108 2029static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 2030{
6aa8b732
AK		 2031 u32 ar;
2032
653e3108 2033 if (var->unusable)
6aa8b732
AK		 2034 ar = 1 << 16;
2035 else {
2036 ar = var->type & 15;
2037 ar |= (var->s & 1) << 4;
2038 ar |= (var->dpl & 3) << 5;
2039 ar |= (var->present & 1) << 7;
2040 ar |= (var->avl & 1) << 12;
2041 ar |= (var->l & 1) << 13;
2042 ar |= (var->db & 1) << 14;
2043 ar |= (var->g & 1) << 15;
2044 }
f7fbf1fd
UL		 2045 if (ar == 0) /* a 0 value means unusable */
2046 ar = AR_UNUSABLE_MASK;
653e3108
AK		 2047
2048 return ar;
2049}
2050
2051static void vmx_set_segment(struct kvm_vcpu *vcpu,
2052 struct kvm_segment *var, int seg)
2053{
7ffd92c5 2054 struct vcpu_vmx *vmx = to_vmx(vcpu);
653e3108
AK		 2055 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2056 u32 ar;
2057
7ffd92c5
AK		 2058 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
2059 vmx->rmode.tr.selector = var->selector;
2060 vmx->rmode.tr.base = var->base;
2061 vmx->rmode.tr.limit = var->limit;
2062 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
653e3108
AK		 2063 return;
2064 }
2065 vmcs_writel(sf->base, var->base);
2066 vmcs_write32(sf->limit, var->limit);
2067 vmcs_write16(sf->selector, var->selector);
7ffd92c5 2068 if (vmx->rmode.vm86_active && var->s) {
653e3108
AK		 2069 /*
2070 * Hack real-mode segments into vm86 compatibility.
2071 */
2072 if (var->base == 0xffff0000 && var->selector == 0xf000)
2073 vmcs_writel(sf->base, 0xf0000);
2074 ar = 0xf3;
2075 } else
2076 ar = vmx_segment_access_rights(var);
3a624e29
NK		 2077
2078 /*
2079 * Fix the "Accessed" bit in AR field of segment registers for older
2080 * qemu binaries.
2081 * IA32 arch specifies that at the time of processor reset the
2082 * "Accessed" bit in the AR field of segment registers is 1. And qemu
2083 * is setting it to 0 in the usedland code. This causes invalid guest
2084 * state vmexit when "unrestricted guest" mode is turned on.
2085 * Fix for this setup issue in cpu_reset is being pushed in the qemu
2086 * tree. Newer qemu binaries with that qemu fix would not need this
2087 * kvm hack.
2088 */
2089 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
2090 ar |= 0x1; /* Accessed */
2091
6aa8b732
AK		 2092 vmcs_write32(sf->ar_bytes, ar);
2093}
2094
6aa8b732
AK		 2095static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
2096{
2097 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
2098
2099 *db = (ar >> 14) & 1;
2100 *l = (ar >> 13) & 1;
2101}
2102
89a27f4d 2103static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2104{
89a27f4d
GN		 2105 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
2106 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 2107}
2108
89a27f4d 2109static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2110{
89a27f4d
GN		 2111 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
2112 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 2113}
2114
89a27f4d 2115static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2116{
89a27f4d
GN		 2117 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
2118 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 2119}
2120
89a27f4d 2121static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2122{
89a27f4d
GN		 2123 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
2124 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 2125}
2126
648dfaa7
MG		 2127static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
2128{
2129 struct kvm_segment var;
2130 u32 ar;
2131
2132 vmx_get_segment(vcpu, &var, seg);
2133 ar = vmx_segment_access_rights(&var);
2134
2135 if (var.base != (var.selector << 4))
2136 return false;
2137 if (var.limit != 0xffff)
2138 return false;
2139 if (ar != 0xf3)
2140 return false;
2141
2142 return true;
2143}
2144
2145static bool code_segment_valid(struct kvm_vcpu *vcpu)
2146{
2147 struct kvm_segment cs;
2148 unsigned int cs_rpl;
2149
2150 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2151 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
2152
1872a3f4
AK		 2153 if (cs.unusable)
2154 return false;
648dfaa7
MG		 2155 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
2156 return false;
2157 if (!cs.s)
2158 return false;
1872a3f4 2159 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 2160 if (cs.dpl > cs_rpl)
2161 return false;
1872a3f4 2162 } else {
648dfaa7
MG		 2163 if (cs.dpl != cs_rpl)
2164 return false;
2165 }
2166 if (!cs.present)
2167 return false;
2168
2169 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
2170 return true;
2171}
2172
2173static bool stack_segment_valid(struct kvm_vcpu *vcpu)
2174{
2175 struct kvm_segment ss;
2176 unsigned int ss_rpl;
2177
2178 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2179 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
2180
1872a3f4
AK		 2181 if (ss.unusable)
2182 return true;
2183 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 2184 return false;
2185 if (!ss.s)
2186 return false;
2187 if (ss.dpl != ss_rpl) /* DPL != RPL */
2188 return false;
2189 if (!ss.present)
2190 return false;
2191
2192 return true;
2193}
2194
2195static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
2196{
2197 struct kvm_segment var;
2198 unsigned int rpl;
2199
2200 vmx_get_segment(vcpu, &var, seg);
2201 rpl = var.selector & SELECTOR_RPL_MASK;
2202
1872a3f4
AK		 2203 if (var.unusable)
2204 return true;
648dfaa7
MG		 2205 if (!var.s)
2206 return false;
2207 if (!var.present)
2208 return false;
2209 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
2210 if (var.dpl < rpl) /* DPL < RPL */
2211 return false;
2212 }
2213
2214 /* TODO: Add other members to kvm_segment_field to allow checking for other access
2215 * rights flags
2216 */
2217 return true;
2218}
2219
2220static bool tr_valid(struct kvm_vcpu *vcpu)
2221{
2222 struct kvm_segment tr;
2223
2224 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2225
1872a3f4
AK		 2226 if (tr.unusable)
2227 return false;
648dfaa7
MG		 2228 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2229 return false;
1872a3f4 2230 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 2231 return false;
2232 if (!tr.present)
2233 return false;
2234
2235 return true;
2236}
2237
2238static bool ldtr_valid(struct kvm_vcpu *vcpu)
2239{
2240 struct kvm_segment ldtr;
2241
2242 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2243
1872a3f4
AK		 2244 if (ldtr.unusable)
2245 return true;
648dfaa7
MG		 2246 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2247 return false;
2248 if (ldtr.type != 2)
2249 return false;
2250 if (!ldtr.present)
2251 return false;
2252
2253 return true;
2254}
2255
2256static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2257{
2258 struct kvm_segment cs, ss;
2259
2260 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2261 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2262
2263 return ((cs.selector & SELECTOR_RPL_MASK) ==
2264 (ss.selector & SELECTOR_RPL_MASK));
2265}
2266
2267/*
2268 * Check if guest state is valid. Returns true if valid, false if
2269 * not.
2270 * We assume that registers are always usable
2271 */
2272static bool guest_state_valid(struct kvm_vcpu *vcpu)
2273{
2274 /* real mode guest state checks */
3eeb3288 2275 if (!is_protmode(vcpu)) {
648dfaa7
MG		 2276 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2277 return false;
2278 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2279 return false;
2280 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2281 return false;
2282 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2283 return false;
2284 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2285 return false;
2286 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2287 return false;
2288 } else {
2289 /* protected mode guest state checks */
2290 if (!cs_ss_rpl_check(vcpu))
2291 return false;
2292 if (!code_segment_valid(vcpu))
2293 return false;
2294 if (!stack_segment_valid(vcpu))
2295 return false;
2296 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2297 return false;
2298 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2299 return false;
2300 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2301 return false;
2302 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2303 return false;
2304 if (!tr_valid(vcpu))
2305 return false;
2306 if (!ldtr_valid(vcpu))
2307 return false;
2308 }
2309 /* TODO:
2310 * - Add checks on RIP
2311 * - Add checks on RFLAGS
2312 */
2313
2314 return true;
2315}
2316
d77c26fc 2317static int init_rmode_tss(struct kvm *kvm)
6aa8b732 2318{
6aa8b732 2319 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde 2320 u16 data = 0;
10589a46 2321 int ret = 0;
195aefde 2322 int r;
6aa8b732 2323
195aefde
IE		 2324 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2325 if (r < 0)
10589a46 2326 goto out;
195aefde 2327 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 2328 r = kvm_write_guest_page(kvm, fn++, &data,
2329 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 2330 if (r < 0)
10589a46 2331 goto out;
195aefde
IE		 2332 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2333 if (r < 0)
10589a46 2334 goto out;
195aefde
IE		 2335 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2336 if (r < 0)
10589a46 2337 goto out;
195aefde 2338 data = ~0;
10589a46
MT		 2339 r = kvm_write_guest_page(kvm, fn, &data,
2340 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2341 sizeof(u8));
195aefde 2342 if (r < 0)
10589a46
MT		 2343 goto out;
2344
2345 ret = 1;
2346out:
10589a46 2347 return ret;
6aa8b732
AK		 2348}
2349
b7ebfb05
SY		 2350static int init_rmode_identity_map(struct kvm *kvm)
2351{
2352 int i, r, ret;
2353 pfn_t identity_map_pfn;
2354 u32 tmp;
2355
089d034e 2356 if (!enable_ept)
b7ebfb05
SY		 2357 return 1;
2358 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2359 printk(KERN_ERR "EPT: identity-mapping pagetable "
2360 "haven't been allocated!\n");
2361 return 0;
2362 }
2363 if (likely(kvm->arch.ept_identity_pagetable_done))
2364 return 1;
2365 ret = 0;
b927a3ce 2366 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
b7ebfb05
SY		 2367 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2368 if (r < 0)
2369 goto out;
2370 /* Set up identity-mapping pagetable for EPT in real mode */
2371 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2372 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2373 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2374 r = kvm_write_guest_page(kvm, identity_map_pfn,
2375 &tmp, i * sizeof(tmp), sizeof(tmp));
2376 if (r < 0)
2377 goto out;
2378 }
2379 kvm->arch.ept_identity_pagetable_done = true;
2380 ret = 1;
2381out:
2382 return ret;
2383}
2384
6aa8b732
AK		 2385static void seg_setup(int seg)
2386{
2387 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 2388 unsigned int ar;
6aa8b732
AK		 2389
2390 vmcs_write16(sf->selector, 0);
2391 vmcs_writel(sf->base, 0);
2392 vmcs_write32(sf->limit, 0xffff);
3a624e29
NK		 2393 if (enable_unrestricted_guest) {
2394 ar = 0x93;
2395 if (seg == VCPU_SREG_CS)
2396 ar |= 0x08; /* code segment */
2397 } else
2398 ar = 0xf3;
2399
2400 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 2401}
2402
f78e0e2e
SY		 2403static int alloc_apic_access_page(struct kvm *kvm)
2404{
2405 struct kvm_userspace_memory_region kvm_userspace_mem;
2406 int r = 0;
2407
79fac95e 2408 mutex_lock(&kvm->slots_lock);
bfc6d222 2409 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 2410 goto out;
2411 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2412 kvm_userspace_mem.flags = 0;
2413 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2414 kvm_userspace_mem.memory_size = PAGE_SIZE;
2415 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2416 if (r)
2417 goto out;
72dc67a6 2418
bfc6d222 2419 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
f78e0e2e 2420out:
79fac95e 2421 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 2422 return r;
2423}
2424
b7ebfb05
SY		 2425static int alloc_identity_pagetable(struct kvm *kvm)
2426{
2427 struct kvm_userspace_memory_region kvm_userspace_mem;
2428 int r = 0;
2429
79fac95e 2430 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 2431 if (kvm->arch.ept_identity_pagetable)
2432 goto out;
2433 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2434 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 2435 kvm_userspace_mem.guest_phys_addr =
2436 kvm->arch.ept_identity_map_addr;
b7ebfb05
SY		 2437 kvm_userspace_mem.memory_size = PAGE_SIZE;
2438 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2439 if (r)
2440 goto out;
2441
b7ebfb05 2442 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
b927a3ce 2443 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
b7ebfb05 2444out:
79fac95e 2445 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 2446 return r;
2447}
2448
2384d2b3
SY		 2449static void allocate_vpid(struct vcpu_vmx *vmx)
2450{
2451 int vpid;
2452
2453 vmx->vpid = 0;
919818ab 2454 if (!enable_vpid)
2384d2b3
SY		 2455 return;
2456 spin_lock(&vmx_vpid_lock);
2457 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2458 if (vpid < VMX_NR_VPIDS) {
2459 vmx->vpid = vpid;
2460 __set_bit(vpid, vmx_vpid_bitmap);
2461 }
2462 spin_unlock(&vmx_vpid_lock);
2463}
2464
cdbecfc3
LJ		 2465static void free_vpid(struct vcpu_vmx *vmx)
2466{
2467 if (!enable_vpid)
2468 return;
2469 spin_lock(&vmx_vpid_lock);
2470 if (vmx->vpid != 0)
2471 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
2472 spin_unlock(&vmx_vpid_lock);
2473}
2474
5897297b 2475static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
25c5f225 2476{
3e7c73e9 2477 int f = sizeof(unsigned long);
25c5f225
SY		 2478
2479 if (!cpu_has_vmx_msr_bitmap())
2480 return;
2481
2482 /*
2483 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2484 * have the write-low and read-high bitmap offsets the wrong way round.
2485 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2486 */
25c5f225 2487 if (msr <= 0x1fff) {
3e7c73e9
AK		 2488 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2489 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
25c5f225
SY		 2490 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2491 msr &= 0x1fff;
3e7c73e9
AK		 2492 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2493 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
25c5f225 2494 }
25c5f225
SY		 2495}
2496
5897297b
AK		 2497static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2498{
2499 if (!longmode_only)
2500 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2501 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2502}
2503
6aa8b732
AK		 2504/*
2505 * Sets up the vmcs for emulated real mode.
2506 */
8b9cf98c 2507static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 2508{
468d472f 2509 u32 host_sysenter_cs, msr_low, msr_high;
6aa8b732 2510 u32 junk;
53f658b3 2511 u64 host_pat, tsc_this, tsc_base;
6aa8b732 2512 unsigned long a;
89a27f4d 2513 struct desc_ptr dt;
6aa8b732 2514 int i;
cd2276a7 2515 unsigned long kvm_vmx_return;
6e5d865c 2516 u32 exec_control;
6aa8b732 2517
6aa8b732 2518 /* I/O */
3e7c73e9
AK		 2519 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2520 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 2521
25c5f225 2522 if (cpu_has_vmx_msr_bitmap())
5897297b 2523 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 2524
6aa8b732
AK		 2525 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2526
6aa8b732 2527 /* Control */
1c3d14fe
YS		 2528 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2529 vmcs_config.pin_based_exec_ctrl);
6e5d865c
YS		 2530
2531 exec_control = vmcs_config.cpu_based_exec_ctrl;
2532 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2533 exec_control &= ~CPU_BASED_TPR_SHADOW;
2534#ifdef CONFIG_X86_64
2535 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2536 CPU_BASED_CR8_LOAD_EXITING;
2537#endif
2538 }
089d034e 2539 if (!enable_ept)
d56f546d 2540 exec_control |= CPU_BASED_CR3_STORE_EXITING |
83dbc83a
MT		 2541 CPU_BASED_CR3_LOAD_EXITING |
2542 CPU_BASED_INVLPG_EXITING;
6e5d865c 2543 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6aa8b732 2544
83ff3b9d
SY		 2545 if (cpu_has_secondary_exec_ctrls()) {
2546 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2547 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2548 exec_control &=
2549 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2384d2b3
SY		 2550 if (vmx->vpid == 0)
2551 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
046d8710 2552 if (!enable_ept) {
d56f546d 2553 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
046d8710
SY		 2554 enable_unrestricted_guest = 0;
2555 }
3a624e29
NK		 2556 if (!enable_unrestricted_guest)
2557 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4b8d54f9
ZE		 2558 if (!ple_gap)
2559 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
83ff3b9d
SY		 2560 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2561 }
f78e0e2e 2562
4b8d54f9
ZE		 2563 if (ple_gap) {
2564 vmcs_write32(PLE_GAP, ple_gap);
2565 vmcs_write32(PLE_WINDOW, ple_window);
2566 }
2567
c7addb90
AK		 2568 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2569 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
6aa8b732
AK		 2570 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2571
1c11e713 2572 vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS); /* 22.2.3 */
6aa8b732
AK		 2573 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2574 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2575
2576 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2577 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2578 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
d6e88aec
AK		 2579 vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs()); /* 22.2.4 */
2580 vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs()); /* 22.2.4 */
6aa8b732 2581 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
05b3e0c2 2582#ifdef CONFIG_X86_64
6aa8b732
AK		 2583 rdmsrl(MSR_FS_BASE, a);
2584 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2585 rdmsrl(MSR_GS_BASE, a);
2586 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2587#else
2588 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2589 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2590#endif
2591
2592 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2593
ec68798c 2594 native_store_idt(&dt);
89a27f4d 2595 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
6aa8b732 2596
d77c26fc 2597 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
cd2276a7 2598 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2cc51560
ED		 2599 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2600 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 2601 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 2602 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 2603 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732
AK		 2604
2605 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2606 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2607 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2608 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2609 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2610 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2611
468d472f
SY		 2612 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2613 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2614 host_pat = msr_low | ((u64) msr_high << 32);
2615 vmcs_write64(HOST_IA32_PAT, host_pat);
2616 }
2617 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2618 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2619 host_pat = msr_low | ((u64) msr_high << 32);
2620 /* Write the default value follow host pat */
2621 vmcs_write64(GUEST_IA32_PAT, host_pat);
2622 /* Keep arch.pat sync with GUEST_IA32_PAT */
2623 vmx->vcpu.arch.pat = host_pat;
2624 }
2625
6aa8b732
AK		 2626 for (i = 0; i < NR_VMX_MSR; ++i) {
2627 u32 index = vmx_msr_index[i];
2628 u32 data_low, data_high;
a2fa3e9f 2629 int j = vmx->nmsrs;
6aa8b732
AK		 2630
2631 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2632 continue;
432bd6cb
AK		 2633 if (wrmsr_safe(index, data_low, data_high) < 0)
2634 continue;
26bb0981
AK		 2635 vmx->guest_msrs[j].index = i;
2636 vmx->guest_msrs[j].data = 0;
d5696725 2637 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 2638 ++vmx->nmsrs;
6aa8b732 2639 }
6aa8b732 2640
1c3d14fe 2641 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 2642
2643 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 2644 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2645
e00c8cf2 2646 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4c38609a 2647 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
ce03e4f2
AK		 2648 if (enable_ept)
2649 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4c38609a 2650 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
e00c8cf2 2651
53f658b3
MT		 2652 tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2653 rdtscll(tsc_this);
2654 if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2655 tsc_base = tsc_this;
2656
2657 guest_write_tsc(0, tsc_base);
f78e0e2e 2658
e00c8cf2
AK		 2659 return 0;
2660}
2661
b7ebfb05
SY		 2662static int init_rmode(struct kvm *kvm)
2663{
4b9d3a04
XG		 2664 int idx, ret = 0;
2665
2666 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05 2667 if (!init_rmode_tss(kvm))
4b9d3a04 2668 goto exit;
b7ebfb05 2669 if (!init_rmode_identity_map(kvm))
4b9d3a04
XG		 2670 goto exit;
2671
2672 ret = 1;
2673exit:
2674 srcu_read_unlock(&kvm->srcu, idx);
2675 return ret;
b7ebfb05
SY		 2676}
2677
e00c8cf2
AK		 2678static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2679{
2680 struct vcpu_vmx *vmx = to_vmx(vcpu);
2681 u64 msr;
4b9d3a04 2682 int ret;
e00c8cf2 2683
5fdbf976 2684 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
b7ebfb05 2685 if (!init_rmode(vmx->vcpu.kvm)) {
e00c8cf2
AK		 2686 ret = -ENOMEM;
2687 goto out;
2688 }
2689
7ffd92c5 2690 vmx->rmode.vm86_active = 0;
e00c8cf2 2691
3b86cd99
JK		 2692 vmx->soft_vnmi_blocked = 0;
2693
ad312c7c 2694 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 2695 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 2696 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 2697 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 2698 msr |= MSR_IA32_APICBASE_BSP;
2699 kvm_set_apic_base(&vmx->vcpu, msr);
2700
10ab25cd
JK		 2701 ret = fx_init(&vmx->vcpu);
2702 if (ret != 0)
2703 goto out;
e00c8cf2 2704
5706be0d 2705 seg_setup(VCPU_SREG_CS);
e00c8cf2
AK		 2706 /*
2707 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2708 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2709 */
c5af89b6 2710 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
e00c8cf2
AK		 2711 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2712 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2713 } else {
ad312c7c
ZX		 2714 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2715 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2 2716 }
e00c8cf2
AK		 2717
2718 seg_setup(VCPU_SREG_DS);
2719 seg_setup(VCPU_SREG_ES);
2720 seg_setup(VCPU_SREG_FS);
2721 seg_setup(VCPU_SREG_GS);
2722 seg_setup(VCPU_SREG_SS);
2723
2724 vmcs_write16(GUEST_TR_SELECTOR, 0);
2725 vmcs_writel(GUEST_TR_BASE, 0);
2726 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2727 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2728
2729 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2730 vmcs_writel(GUEST_LDTR_BASE, 0);
2731 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2732 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2733
2734 vmcs_write32(GUEST_SYSENTER_CS, 0);
2735 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2736 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2737
2738 vmcs_writel(GUEST_RFLAGS, 0x02);
c5af89b6 2739 if (kvm_vcpu_is_bsp(&vmx->vcpu))
5fdbf976 2740 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 2741 else
5fdbf976
MT		 2742 kvm_rip_write(vcpu, 0);
2743 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
e00c8cf2 2744
e00c8cf2
AK		 2745 vmcs_writel(GUEST_DR7, 0x400);
2746
2747 vmcs_writel(GUEST_GDTR_BASE, 0);
2748 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2749
2750 vmcs_writel(GUEST_IDTR_BASE, 0);
2751 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2752
2753 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2754 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2755 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2756
e00c8cf2
AK		 2757 /* Special registers */
2758 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2759
2760 setup_msrs(vmx);
2761
6aa8b732
AK		 2762 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2763
f78e0e2e
SY		 2764 if (cpu_has_vmx_tpr_shadow()) {
2765 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2766 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2767 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
ad312c7c 2768 page_to_phys(vmx->vcpu.arch.apic->regs_page));
f78e0e2e
SY		 2769 vmcs_write32(TPR_THRESHOLD, 0);
2770 }
2771
2772 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2773 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 2774 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 2775
2384d2b3
SY		 2776 if (vmx->vpid != 0)
2777 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2778
fa40052c 2779 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 2780 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 2781 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 2782 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 2783 vmx_fpu_activate(&vmx->vcpu);
2784 update_exception_bitmap(&vmx->vcpu);
6aa8b732 2785
b9d762fa 2786 vpid_sync_context(vmx);
2384d2b3 2787
3200f405 2788 ret = 0;
6aa8b732 2789
a89a8fb9
MG		 2790 /* HACK: Don't enable emulation on guest boot/reset */
2791 vmx->emulation_required = 0;
2792
6aa8b732
AK		 2793out:
2794 return ret;
2795}
2796
3b86cd99
JK		 2797static void enable_irq_window(struct kvm_vcpu *vcpu)
2798{
2799 u32 cpu_based_vm_exec_control;
2800
2801 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2802 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2803 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2804}
2805
2806static void enable_nmi_window(struct kvm_vcpu *vcpu)
2807{
2808 u32 cpu_based_vm_exec_control;
2809
2810 if (!cpu_has_virtual_nmis()) {
2811 enable_irq_window(vcpu);
2812 return;
2813 }
2814
2815 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2816 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2817 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2818}
2819
66fd3f7f 2820static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 2821{
9c8cba37 2822 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 2823 uint32_t intr;
2824 int irq = vcpu->arch.interrupt.nr;
9c8cba37 2825
229456fc 2826 trace_kvm_inj_virq(irq);
2714d1d3 2827
fa89a817 2828 ++vcpu->stat.irq_injections;
7ffd92c5 2829 if (vmx->rmode.vm86_active) {
9c8cba37
AK		 2830 vmx->rmode.irq.pending = true;
2831 vmx->rmode.irq.vector = irq;
5fdbf976 2832 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
ae0bb3e0
GN		 2833 if (vcpu->arch.interrupt.soft)
2834 vmx->rmode.irq.rip +=
2835 vmx->vcpu.arch.event_exit_inst_len;
9c5623e3
AK		 2836 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2837 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2838 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
5fdbf976 2839 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
85f455f7
ED		 2840 return;
2841 }
66fd3f7f
GN		 2842 intr = irq | INTR_INFO_VALID_MASK;
2843 if (vcpu->arch.interrupt.soft) {
2844 intr |= INTR_TYPE_SOFT_INTR;
2845 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2846 vmx->vcpu.arch.event_exit_inst_len);
2847 } else
2848 intr |= INTR_TYPE_EXT_INTR;
2849 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 2850}
2851
f08864b4
SY		 2852static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2853{
66a5a347
JK		 2854 struct vcpu_vmx *vmx = to_vmx(vcpu);
2855
3b86cd99
JK		 2856 if (!cpu_has_virtual_nmis()) {
2857 /*
2858 * Tracking the NMI-blocked state in software is built upon
2859 * finding the next open IRQ window. This, in turn, depends on
2860 * well-behaving guests: They have to keep IRQs disabled at
2861 * least as long as the NMI handler runs. Otherwise we may
2862 * cause NMI nesting, maybe breaking the guest. But as this is
2863 * highly unlikely, we can live with the residual risk.
2864 */
2865 vmx->soft_vnmi_blocked = 1;
2866 vmx->vnmi_blocked_time = 0;
2867 }
2868
487b391d 2869 ++vcpu->stat.nmi_injections;
7ffd92c5 2870 if (vmx->rmode.vm86_active) {
66a5a347
JK		 2871 vmx->rmode.irq.pending = true;
2872 vmx->rmode.irq.vector = NMI_VECTOR;
2873 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2874 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2875 NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2876 INTR_INFO_VALID_MASK);
2877 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2878 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2879 return;
2880 }
f08864b4
SY		 2881 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2882 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 2883}
2884
c4282df9 2885static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
33f089ca 2886{
3b86cd99 2887 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
c4282df9 2888 return 0;
33f089ca 2889
c4282df9 2890 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
f8c5fae1 2891 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_NMI));
33f089ca
JK		 2892}
2893
3cfc3092
JK		 2894static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
2895{
2896 if (!cpu_has_virtual_nmis())
2897 return to_vmx(vcpu)->soft_vnmi_blocked;
c332c83a 2898 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 2899}
2900
2901static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2902{
2903 struct vcpu_vmx *vmx = to_vmx(vcpu);
2904
2905 if (!cpu_has_virtual_nmis()) {
2906 if (vmx->soft_vnmi_blocked != masked) {
2907 vmx->soft_vnmi_blocked = masked;
2908 vmx->vnmi_blocked_time = 0;
2909 }
2910 } else {
2911 if (masked)
2912 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2913 GUEST_INTR_STATE_NMI);
2914 else
2915 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2916 GUEST_INTR_STATE_NMI);
2917 }
2918}
2919
78646121
GN		 2920static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2921{
c4282df9
GN		 2922 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2923 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2924 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 2925}
2926
cbc94022
IE		 2927static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2928{
2929 int ret;
2930 struct kvm_userspace_memory_region tss_mem = {
6fe63979 2931 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 2932 .guest_phys_addr = addr,
2933 .memory_size = PAGE_SIZE * 3,
2934 .flags = 0,
2935 };
2936
2937 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2938 if (ret)
2939 return ret;
bfc6d222 2940 kvm->arch.tss_addr = addr;
cbc94022
IE		 2941 return 0;
2942}
2943
6aa8b732
AK		 2944static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2945 int vec, u32 err_code)
2946{
b3f37707
NK		 2947 /*
2948 * Instruction with address size override prefix opcode 0x67
2949 * Cause the #SS fault with 0 error code in VM86 mode.
2950 */
2951 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
851ba692 2952 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE)
6aa8b732 2953 return 1;
77ab6db0
JK		 2954 /*
2955 * Forward all other exceptions that are valid in real mode.
2956 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2957 * the required debugging infrastructure rework.
2958 */
2959 switch (vec) {
77ab6db0 2960 case DB_VECTOR:
d0bfb940
JK		 2961 if (vcpu->guest_debug &
2962 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2963 return 0;
2964 kvm_queue_exception(vcpu, vec);
2965 return 1;
77ab6db0 2966 case BP_VECTOR:
c573cd22
JK		 2967 /*
2968 * Update instruction length as we may reinject the exception
2969 * from user space while in guest debugging mode.
2970 */
2971 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
2972 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940
JK		 2973 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2974 return 0;
2975 /* fall through */
2976 case DE_VECTOR:
77ab6db0
JK		 2977 case OF_VECTOR:
2978 case BR_VECTOR:
2979 case UD_VECTOR:
2980 case DF_VECTOR:
2981 case SS_VECTOR:
2982 case GP_VECTOR:
2983 case MF_VECTOR:
2984 kvm_queue_exception(vcpu, vec);
2985 return 1;
2986 }
6aa8b732
AK		 2987 return 0;
2988}
2989
a0861c02
AK		 2990/*
2991 * Trigger machine check on the host. We assume all the MSRs are already set up
2992 * by the CPU and that we still run on the same CPU as the MCE occurred on.
2993 * We pass a fake environment to the machine check handler because we want
2994 * the guest to be always treated like user space, no matter what context
2995 * it used internally.
2996 */
2997static void kvm_machine_check(void)
2998{
2999#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
3000 struct pt_regs regs = {
3001 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
3002 .flags = X86_EFLAGS_IF,
3003 };
3004
3005 do_machine_check(&regs, 0);
3006#endif
3007}
3008
851ba692 3009static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 3010{
3011 /* already handled by vcpu_run */
3012 return 1;
3013}
3014
851ba692 3015static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 3016{
1155f76a 3017 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 3018 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 3019 u32 intr_info, ex_no, error_code;
42dbaa5a 3020 unsigned long cr2, rip, dr6;
6aa8b732
AK		 3021 u32 vect_info;
3022 enum emulation_result er;
3023
1155f76a 3024 vect_info = vmx->idt_vectoring_info;
6aa8b732
AK		 3025 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3026
a0861c02 3027 if (is_machine_check(intr_info))
851ba692 3028 return handle_machine_check(vcpu);
a0861c02 3029
6aa8b732 3030 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
65ac7264
AK		 3031 !is_page_fault(intr_info)) {
3032 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3033 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
3034 vcpu->run->internal.ndata = 2;
3035 vcpu->run->internal.data[0] = vect_info;
3036 vcpu->run->internal.data[1] = intr_info;
3037 return 0;
3038 }
6aa8b732 3039
e4a41889 3040 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 3041 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 3042
3043 if (is_no_device(intr_info)) {
5fd86fcf 3044 vmx_fpu_activate(vcpu);
2ab455cc
AL		 3045 return 1;
3046 }
3047
7aa81cc0 3048 if (is_invalid_opcode(intr_info)) {
851ba692 3049 er = emulate_instruction(vcpu, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 3050 if (er != EMULATE_DONE)
7ee5d940 3051 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 3052 return 1;
3053 }
3054
6aa8b732 3055 error_code = 0;
5fdbf976 3056 rip = kvm_rip_read(vcpu);
2e11384c 3057 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732
AK		 3058 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
3059 if (is_page_fault(intr_info)) {
1439442c 3060 /* EPT won't cause page fault directly */
089d034e 3061 if (enable_ept)
1439442c 3062 BUG();
6aa8b732 3063 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 3064 trace_kvm_page_fault(cr2, error_code);
3065
3298b75c 3066 if (kvm_event_needs_reinjection(vcpu))
577bdc49 3067 kvm_mmu_unprotect_page_virt(vcpu, cr2);
3067714c 3068 return kvm_mmu_page_fault(vcpu, cr2, error_code);
6aa8b732
AK		 3069 }
3070
7ffd92c5 3071 if (vmx->rmode.vm86_active &&
6aa8b732 3072 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 3073 error_code)) {
ad312c7c
ZX		 3074 if (vcpu->arch.halt_request) {
3075 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 3076 return kvm_emulate_halt(vcpu);
3077 }
6aa8b732 3078 return 1;
72d6e5a0 3079 }
6aa8b732 3080
d0bfb940 3081 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
42dbaa5a
JK		 3082 switch (ex_no) {
3083 case DB_VECTOR:
3084 dr6 = vmcs_readl(EXIT_QUALIFICATION);
3085 if (!(vcpu->guest_debug &
3086 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
3087 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
3088 kvm_queue_exception(vcpu, DB_VECTOR);
3089 return 1;
3090 }
3091 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
3092 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
3093 /* fall through */
3094 case BP_VECTOR:
c573cd22
JK		 3095 /*
3096 * Update instruction length as we may reinject #BP from
3097 * user space while in guest debugging mode. Reading it for
3098 * #DB as well causes no harm, it is not used in that case.
3099 */
3100 vmx->vcpu.arch.event_exit_inst_len =
3101 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 3102 kvm_run->exit_reason = KVM_EXIT_DEBUG;
d0bfb940
JK		 3103 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
3104 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 3105 break;
3106 default:
d0bfb940
JK		 3107 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
3108 kvm_run->ex.exception = ex_no;
3109 kvm_run->ex.error_code = error_code;
42dbaa5a 3110 break;
6aa8b732 3111 }
6aa8b732
AK		 3112 return 0;
3113}
3114
851ba692 3115static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 3116{
1165f5fe 3117 ++vcpu->stat.irq_exits;
6aa8b732
AK		 3118 return 1;
3119}
3120
851ba692 3121static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 3122{
851ba692 3123 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 3124 return 0;
3125}
6aa8b732 3126
851ba692 3127static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 3128{
bfdaab09 3129 unsigned long exit_qualification;
34c33d16 3130 int size, in, string;
039576c0 3131 unsigned port;
6aa8b732 3132
bfdaab09 3133 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 3134 string = (exit_qualification & 16) != 0;
cf8f70bf 3135 in = (exit_qualification & 8) != 0;
e70669ab 3136
cf8f70bf 3137 ++vcpu->stat.io_exits;
e70669ab 3138
cf8f70bf 3139 if (string || in)
6d77dbfc 3140 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
e70669ab 3141
cf8f70bf
GN		 3142 port = exit_qualification >> 16;
3143 size = (exit_qualification & 7) + 1;
e93f36bc 3144 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 3145
3146 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 3147}
3148
102d8325
IM		 3149static void
3150vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3151{
3152 /*
3153 * Patch in the VMCALL instruction:
3154 */
3155 hypercall[0] = 0x0f;
3156 hypercall[1] = 0x01;
3157 hypercall[2] = 0xc1;
102d8325
IM		 3158}
3159
49a9b07e
AK		 3160static void complete_insn_gp(struct kvm_vcpu *vcpu, int err)
3161{
3162 if (err)
3163 kvm_inject_gp(vcpu, 0);
3164 else
3165 skip_emulated_instruction(vcpu);
3166}
3167
851ba692 3168static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 3169{
229456fc 3170 unsigned long exit_qualification, val;
6aa8b732
AK		 3171 int cr;
3172 int reg;
49a9b07e 3173 int err;
6aa8b732 3174
bfdaab09 3175 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 3176 cr = exit_qualification & 15;
3177 reg = (exit_qualification >> 8) & 15;
3178 switch ((exit_qualification >> 4) & 3) {
3179 case 0: /* mov to cr */
229456fc
MT		 3180 val = kvm_register_read(vcpu, reg);
3181 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 3182 switch (cr) {
3183 case 0:
49a9b07e
AK		 3184 err = kvm_set_cr0(vcpu, val);
3185 complete_insn_gp(vcpu, err);
6aa8b732
AK		 3186 return 1;
3187 case 3:
2390218b
AK		 3188 err = kvm_set_cr3(vcpu, val);
3189 complete_insn_gp(vcpu, err);
6aa8b732
AK		 3190 return 1;
3191 case 4:
a83b29c6
AK		 3192 err = kvm_set_cr4(vcpu, val);
3193 complete_insn_gp(vcpu, err);
6aa8b732 3194 return 1;
0a5fff19
GN		 3195 case 8: {
3196 u8 cr8_prev = kvm_get_cr8(vcpu);
3197 u8 cr8 = kvm_register_read(vcpu, reg);
3198 kvm_set_cr8(vcpu, cr8);
3199 skip_emulated_instruction(vcpu);
3200 if (irqchip_in_kernel(vcpu->kvm))
3201 return 1;
3202 if (cr8_prev <= cr8)
3203 return 1;
851ba692 3204 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 3205 return 0;
3206 }
6aa8b732
AK		 3207 };
3208 break;
25c4c276 3209 case 2: /* clts */
edcafe3c 3210 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4d4ec087 3211 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 3212 skip_emulated_instruction(vcpu);
6b52d186 3213 vmx_fpu_activate(vcpu);
25c4c276 3214 return 1;
6aa8b732
AK		 3215 case 1: /*mov from cr*/
3216 switch (cr) {
3217 case 3:
5fdbf976 3218 kvm_register_write(vcpu, reg, vcpu->arch.cr3);
229456fc 3219 trace_kvm_cr_read(cr, vcpu->arch.cr3);
6aa8b732
AK		 3220 skip_emulated_instruction(vcpu);
3221 return 1;
3222 case 8:
229456fc
MT		 3223 val = kvm_get_cr8(vcpu);
3224 kvm_register_write(vcpu, reg, val);
3225 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 3226 skip_emulated_instruction(vcpu);
3227 return 1;
3228 }
3229 break;
3230 case 3: /* lmsw */
a1f83a74 3231 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 3232 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 3233 kvm_lmsw(vcpu, val);
6aa8b732
AK		 3234
3235 skip_emulated_instruction(vcpu);
3236 return 1;
3237 default:
3238 break;
3239 }
851ba692 3240 vcpu->run->exit_reason = 0;
f0242478 3241 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 3242 (int)(exit_qualification >> 4) & 3, cr);
3243 return 0;
3244}
3245
851ba692 3246static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 3247{
bfdaab09 3248 unsigned long exit_qualification;
6aa8b732
AK		 3249 int dr, reg;
3250
f2483415 3251 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 3252 if (!kvm_require_cpl(vcpu, 0))
3253 return 1;
42dbaa5a
JK		 3254 dr = vmcs_readl(GUEST_DR7);
3255 if (dr & DR7_GD) {
3256 /*
3257 * As the vm-exit takes precedence over the debug trap, we
3258 * need to emulate the latter, either for the host or the
3259 * guest debugging itself.
3260 */
3261 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 3262 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3263 vcpu->run->debug.arch.dr7 = dr;
3264 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 3265 vmcs_readl(GUEST_CS_BASE) +
3266 vmcs_readl(GUEST_RIP);
851ba692
AK		 3267 vcpu->run->debug.arch.exception = DB_VECTOR;
3268 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 3269 return 0;
3270 } else {
3271 vcpu->arch.dr7 &= ~DR7_GD;
3272 vcpu->arch.dr6 |= DR6_BD;
3273 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3274 kvm_queue_exception(vcpu, DB_VECTOR);
3275 return 1;
3276 }
3277 }
3278
bfdaab09 3279 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 3280 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3281 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3282 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079
GN		 3283 unsigned long val;
3284 if (!kvm_get_dr(vcpu, dr, &val))
3285 kvm_register_write(vcpu, reg, val);
3286 } else
3287 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
6aa8b732
AK		 3288 skip_emulated_instruction(vcpu);
3289 return 1;
3290}
3291
020df079
GN		 3292static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
3293{
3294 vmcs_writel(GUEST_DR7, val);
3295}
3296
851ba692 3297static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 3298{
06465c5a
AK		 3299 kvm_emulate_cpuid(vcpu);
3300 return 1;
6aa8b732
AK		 3301}
3302
851ba692 3303static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 3304{
ad312c7c 3305 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 3306 u64 data;
3307
3308 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 3309 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 3310 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 3311 return 1;
3312 }
3313
229456fc 3314 trace_kvm_msr_read(ecx, data);
2714d1d3 3315
6aa8b732 3316 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 3317 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3318 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 3319 skip_emulated_instruction(vcpu);
3320 return 1;
3321}
3322
851ba692 3323static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 3324{
ad312c7c
ZX		 3325 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3326 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3327 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732
AK		 3328
3329 if (vmx_set_msr(vcpu, ecx, data) != 0) {
59200273 3330 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 3331 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 3332 return 1;
3333 }
3334
59200273 3335 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 3336 skip_emulated_instruction(vcpu);
3337 return 1;
3338}
3339
851ba692 3340static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c
YS		 3341{
3342 return 1;
3343}
3344
851ba692 3345static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 3346{
85f455f7
ED		 3347 u32 cpu_based_vm_exec_control;
3348
3349 /* clear pending irq */
3350 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3351 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3352 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 3353
a26bf12a 3354 ++vcpu->stat.irq_window_exits;
2714d1d3 3355
c1150d8c
DL		 3356 /*
3357 * If the user space waits to inject interrupts, exit as soon as
3358 * possible
3359 */
8061823a 3360 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 3361 vcpu->run->request_interrupt_window &&
8061823a 3362 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 3363 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 3364 return 0;
3365 }
6aa8b732
AK		 3366 return 1;
3367}
3368
851ba692 3369static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 3370{
3371 skip_emulated_instruction(vcpu);
d3bef15f 3372 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 3373}
3374
851ba692 3375static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 3376{
510043da 3377 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 3378 kvm_emulate_hypercall(vcpu);
3379 return 1;
c21415e8
IM		 3380}
3381
851ba692 3382static int handle_vmx_insn(struct kvm_vcpu *vcpu)
e3c7cb6a
AK		 3383{
3384 kvm_queue_exception(vcpu, UD_VECTOR);
3385 return 1;
3386}
3387
851ba692 3388static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 3389{
f9c617f6 3390 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 3391
3392 kvm_mmu_invlpg(vcpu, exit_qualification);
3393 skip_emulated_instruction(vcpu);
3394 return 1;
3395}
3396
851ba692 3397static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 3398{
3399 skip_emulated_instruction(vcpu);
3400 /* TODO: Add support for VT-d/pass-through device */
3401 return 1;
3402}
3403
2acf923e
DC		 3404static int handle_xsetbv(struct kvm_vcpu *vcpu)
3405{
3406 u64 new_bv = kvm_read_edx_eax(vcpu);
3407 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3408
3409 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
3410 skip_emulated_instruction(vcpu);
3411 return 1;
3412}
3413
851ba692 3414static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 3415{
6d77dbfc 3416 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
f78e0e2e
SY		 3417}
3418
851ba692 3419static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 3420{
60637aac 3421 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 3422 unsigned long exit_qualification;
e269fb21
JK		 3423 bool has_error_code = false;
3424 u32 error_code = 0;
37817f29 3425 u16 tss_selector;
64a7ec06
GN		 3426 int reason, type, idt_v;
3427
3428 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3429 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 3430
3431 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3432
3433 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 3434 if (reason == TASK_SWITCH_GATE && idt_v) {
3435 switch (type) {
3436 case INTR_TYPE_NMI_INTR:
3437 vcpu->arch.nmi_injected = false;
3438 if (cpu_has_virtual_nmis())
3439 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3440 GUEST_INTR_STATE_NMI);
3441 break;
3442 case INTR_TYPE_EXT_INTR:
66fd3f7f 3443 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 3444 kvm_clear_interrupt_queue(vcpu);
3445 break;
3446 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 3447 if (vmx->idt_vectoring_info &
3448 VECTORING_INFO_DELIVER_CODE_MASK) {
3449 has_error_code = true;
3450 error_code =
3451 vmcs_read32(IDT_VECTORING_ERROR_CODE);
3452 }
3453 /* fall through */
64a7ec06
GN		 3454 case INTR_TYPE_SOFT_EXCEPTION:
3455 kvm_clear_exception_queue(vcpu);
3456 break;
3457 default:
3458 break;
3459 }
60637aac 3460 }
37817f29
IE		 3461 tss_selector = exit_qualification;
3462
64a7ec06
GN		 3463 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3464 type != INTR_TYPE_EXT_INTR &&
3465 type != INTR_TYPE_NMI_INTR))
3466 skip_emulated_instruction(vcpu);
3467
acb54517
GN		 3468 if (kvm_task_switch(vcpu, tss_selector, reason,
3469 has_error_code, error_code) == EMULATE_FAIL) {
3470 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3471 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3472 vcpu->run->internal.ndata = 0;
42dbaa5a 3473 return 0;
acb54517 3474 }
42dbaa5a
JK		 3475
3476 /* clear all local breakpoint enable flags */
3477 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3478
3479 /*
3480 * TODO: What about debug traps on tss switch?
3481 * Are we supposed to inject them and update dr6?
3482 */
3483
3484 return 1;
37817f29
IE		 3485}
3486
851ba692 3487static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 3488{
f9c617f6 3489 unsigned long exit_qualification;
1439442c 3490 gpa_t gpa;
1439442c 3491 int gla_validity;
1439442c 3492
f9c617f6 3493 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c
SY		 3494
3495 if (exit_qualification & (1 << 6)) {
3496 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
7f582ab6 3497 return -EINVAL;
1439442c
SY		 3498 }
3499
3500 gla_validity = (exit_qualification >> 7) & 0x3;
3501 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3502 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3503 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3504 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 3505 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 3506 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3507 (long unsigned int)exit_qualification);
851ba692
AK		 3508 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3509 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 3510 return 0;
1439442c
SY		 3511 }
3512
3513 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 3514 trace_kvm_page_fault(gpa, exit_qualification);
49cd7d22 3515 return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
1439442c
SY		 3516}
3517
68f89400
MT		 3518static u64 ept_rsvd_mask(u64 spte, int level)
3519{
3520 int i;
3521 u64 mask = 0;
3522
3523 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3524 mask |= (1ULL << i);
3525
3526 if (level > 2)
3527 /* bits 7:3 reserved */
3528 mask |= 0xf8;
3529 else if (level == 2) {
3530 if (spte & (1ULL << 7))
3531 /* 2MB ref, bits 20:12 reserved */
3532 mask |= 0x1ff000;
3533 else
3534 /* bits 6:3 reserved */
3535 mask |= 0x78;
3536 }
3537
3538 return mask;
3539}
3540
3541static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3542 int level)
3543{
3544 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3545
3546 /* 010b (write-only) */
3547 WARN_ON((spte & 0x7) == 0x2);
3548
3549 /* 110b (write/execute) */
3550 WARN_ON((spte & 0x7) == 0x6);
3551
3552 /* 100b (execute-only) and value not supported by logical processor */
3553 if (!cpu_has_vmx_ept_execute_only())
3554 WARN_ON((spte & 0x7) == 0x4);
3555
3556 /* not 000b */
3557 if ((spte & 0x7)) {
3558 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3559
3560 if (rsvd_bits != 0) {
3561 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3562 __func__, rsvd_bits);
3563 WARN_ON(1);
3564 }
3565
3566 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3567 u64 ept_mem_type = (spte & 0x38) >> 3;
3568
3569 if (ept_mem_type == 2 || ept_mem_type == 3 ||
3570 ept_mem_type == 7) {
3571 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3572 __func__, ept_mem_type);
3573 WARN_ON(1);
3574 }
3575 }
3576 }
3577}
3578
851ba692 3579static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 3580{
3581 u64 sptes[4];
3582 int nr_sptes, i;
3583 gpa_t gpa;
3584
3585 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3586
3587 printk(KERN_ERR "EPT: Misconfiguration.\n");
3588 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3589
3590 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3591
3592 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3593 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3594
851ba692
AK		 3595 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3596 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 3597
3598 return 0;
3599}
3600
851ba692 3601static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 3602{
3603 u32 cpu_based_vm_exec_control;
3604
3605 /* clear pending NMI */
3606 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3607 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3608 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3609 ++vcpu->stat.nmi_window_exits;
3610
3611 return 1;
3612}
3613
80ced186 3614static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 3615{
8b3079a5
AK		 3616 struct vcpu_vmx *vmx = to_vmx(vcpu);
3617 enum emulation_result err = EMULATE_DONE;
80ced186 3618 int ret = 1;
ea953ef0
MG		 3619
3620 while (!guest_state_valid(vcpu)) {
851ba692 3621 err = emulate_instruction(vcpu, 0, 0, 0);
ea953ef0 3622
80ced186
MG		 3623 if (err == EMULATE_DO_MMIO) {
3624 ret = 0;
3625 goto out;
3626 }
1d5a4d9b 3627
6d77dbfc
GN		 3628 if (err != EMULATE_DONE)
3629 return 0;
ea953ef0
MG		 3630
3631 if (signal_pending(current))
80ced186 3632 goto out;
ea953ef0
MG		 3633 if (need_resched())
3634 schedule();
3635 }
3636
80ced186
MG		 3637 vmx->emulation_required = 0;
3638out:
3639 return ret;
ea953ef0
MG		 3640}
3641
4b8d54f9
ZE		 3642/*
3643 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3644 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3645 */
9fb41ba8 3646static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 3647{
3648 skip_emulated_instruction(vcpu);
3649 kvm_vcpu_on_spin(vcpu);
3650
3651 return 1;
3652}
3653
59708670
SY		 3654static int handle_invalid_op(struct kvm_vcpu *vcpu)
3655{
3656 kvm_queue_exception(vcpu, UD_VECTOR);
3657 return 1;
3658}
3659
6aa8b732
AK		 3660/*
3661 * The exit handlers return 1 if the exit was handled fully and guest execution
3662 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3663 * to be done to userspace and return 0.
3664 */
851ba692 3665static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 3666 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3667 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 3668 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 3669 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 3670 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 3671 [EXIT_REASON_CR_ACCESS] = handle_cr,
3672 [EXIT_REASON_DR_ACCESS] = handle_dr,
3673 [EXIT_REASON_CPUID] = handle_cpuid,
3674 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3675 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3676 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3677 [EXIT_REASON_HLT] = handle_halt,
a7052897 3678 [EXIT_REASON_INVLPG] = handle_invlpg,
c21415e8 3679 [EXIT_REASON_VMCALL] = handle_vmcall,
e3c7cb6a
AK		 3680 [EXIT_REASON_VMCLEAR] = handle_vmx_insn,
3681 [EXIT_REASON_VMLAUNCH] = handle_vmx_insn,
3682 [EXIT_REASON_VMPTRLD] = handle_vmx_insn,
3683 [EXIT_REASON_VMPTRST] = handle_vmx_insn,
3684 [EXIT_REASON_VMREAD] = handle_vmx_insn,
3685 [EXIT_REASON_VMRESUME] = handle_vmx_insn,
3686 [EXIT_REASON_VMWRITE] = handle_vmx_insn,
3687 [EXIT_REASON_VMOFF] = handle_vmx_insn,
3688 [EXIT_REASON_VMON] = handle_vmx_insn,
f78e0e2e
SY		 3689 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3690 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 3691 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 3692 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 3693 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 3694 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 3695 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
3696 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 3697 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 3698 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
3699 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
6aa8b732
AK		 3700};
3701
3702static const int kvm_vmx_max_exit_handlers =
50a3485c 3703 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732
AK		 3704
3705/*
3706 * The guest has exited. See if we can fix it or if we need userspace
3707 * assistance.
3708 */
851ba692 3709static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 3710{
29bd8a78 3711 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 3712 u32 exit_reason = vmx->exit_reason;
1155f76a 3713 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 3714
5bfd8b54 3715 trace_kvm_exit(exit_reason, vcpu);
2714d1d3 3716
80ced186
MG		 3717 /* If guest state is invalid, start emulating */
3718 if (vmx->emulation_required && emulate_invalid_guest_state)
3719 return handle_invalid_guest_state(vcpu);
1d5a4d9b 3720
1439442c
SY		 3721 /* Access CR3 don't cause VMExit in paging mode, so we need
3722 * to sync with guest real CR3. */
6de4f3ad 3723 if (enable_ept && is_paging(vcpu))
1439442c 3724 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
1439442c 3725
5120702e
MG		 3726 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
3727 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3728 vcpu->run->fail_entry.hardware_entry_failure_reason
3729 = exit_reason;
3730 return 0;
3731 }
3732
29bd8a78 3733 if (unlikely(vmx->fail)) {
851ba692
AK		 3734 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3735 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 3736 = vmcs_read32(VM_INSTRUCTION_ERROR);
3737 return 0;
3738 }
6aa8b732 3739
d77c26fc 3740 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 3741 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac
JK		 3742 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3743 exit_reason != EXIT_REASON_TASK_SWITCH))
3744 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3745 "(0x%x) and exit reason is 0x%x\n",
3746 __func__, vectoring_info, exit_reason);
3b86cd99
JK		 3747
3748 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
c4282df9 3749 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 3750 vmx->soft_vnmi_blocked = 0;
3b86cd99 3751 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 3752 vcpu->arch.nmi_pending) {
3b86cd99
JK		 3753 /*
3754 * This CPU don't support us in finding the end of an
3755 * NMI-blocked window if the guest runs with IRQs
3756 * disabled. So we pull the trigger after 1 s of
3757 * futile waiting, but inform the user about this.
3758 */
3759 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3760 "state on VCPU %d after 1 s timeout\n",
3761 __func__, vcpu->vcpu_id);
3762 vmx->soft_vnmi_blocked = 0;
3b86cd99 3763 }
3b86cd99
JK		 3764 }
3765
6aa8b732
AK		 3766 if (exit_reason < kvm_vmx_max_exit_handlers
3767 && kvm_vmx_exit_handlers[exit_reason])
851ba692 3768 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 3769 else {
851ba692
AK		 3770 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3771 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 3772 }
3773 return 0;
3774}
3775
95ba8273 3776static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 3777{
95ba8273 3778 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 3779 vmcs_write32(TPR_THRESHOLD, 0);
3780 return;
3781 }
3782
95ba8273 3783 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 3784}
3785
cf393f75
AK		 3786static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3787{
3788 u32 exit_intr_info;
7b4a25cb 3789 u32 idt_vectoring_info = vmx->idt_vectoring_info;
cf393f75
AK		 3790 bool unblock_nmi;
3791 u8 vector;
668f612f
AK		 3792 int type;
3793 bool idtv_info_valid;
cf393f75
AK		 3794
3795 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
20f65983 3796
a0861c02
AK		 3797 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
3798
3799 /* Handle machine checks before interrupts are enabled */
3800 if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3801 || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3802 && is_machine_check(exit_intr_info)))
3803 kvm_machine_check();
3804
20f65983
GN		 3805 /* We need to handle NMIs before interrupts are enabled */
3806 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 3807 (exit_intr_info & INTR_INFO_VALID_MASK)) {
3808 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 3809 asm("int $2");
ff9d07a0
ZY		 3810 kvm_after_handle_nmi(&vmx->vcpu);
3811 }
20f65983
GN		 3812
3813 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3814
cf393f75
AK		 3815 if (cpu_has_virtual_nmis()) {
3816 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3817 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3818 /*
7b4a25cb 3819 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 3820 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3821 * a guest IRET fault.
7b4a25cb
GN		 3822 * SDM 3: 23.2.2 (September 2008)
3823 * Bit 12 is undefined in any of the following cases:
3824 * If the VM exit sets the valid bit in the IDT-vectoring
3825 * information field.
3826 * If the VM exit is due to a double fault.
cf393f75 3827 */
7b4a25cb
GN		 3828 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3829 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 3830 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3831 GUEST_INTR_STATE_NMI);
3b86cd99
JK		 3832 } else if (unlikely(vmx->soft_vnmi_blocked))
3833 vmx->vnmi_blocked_time +=
3834 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
668f612f 3835
37b96e98
GN		 3836 vmx->vcpu.arch.nmi_injected = false;
3837 kvm_clear_exception_queue(&vmx->vcpu);
3838 kvm_clear_interrupt_queue(&vmx->vcpu);
3839
3840 if (!idtv_info_valid)
3841 return;
3842
668f612f
AK		 3843 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3844 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 3845
64a7ec06 3846 switch (type) {
37b96e98
GN		 3847 case INTR_TYPE_NMI_INTR:
3848 vmx->vcpu.arch.nmi_injected = true;
668f612f 3849 /*
7b4a25cb 3850 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 3851 * Clear bit "block by NMI" before VM entry if a NMI
3852 * delivery faulted.
668f612f 3853 */
37b96e98
GN		 3854 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3855 GUEST_INTR_STATE_NMI);
3856 break;
37b96e98 3857 case INTR_TYPE_SOFT_EXCEPTION:
66fd3f7f
GN		 3858 vmx->vcpu.arch.event_exit_inst_len =
3859 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3860 /* fall through */
3861 case INTR_TYPE_HARD_EXCEPTION:
35920a35 3862 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
37b96e98
GN		 3863 u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3864 kvm_queue_exception_e(&vmx->vcpu, vector, err);
35920a35
AK		 3865 } else
3866 kvm_queue_exception(&vmx->vcpu, vector);
37b96e98 3867 break;
66fd3f7f
GN		 3868 case INTR_TYPE_SOFT_INTR:
3869 vmx->vcpu.arch.event_exit_inst_len =
3870 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3871 /* fall through */
37b96e98 3872 case INTR_TYPE_EXT_INTR:
66fd3f7f
GN		 3873 kvm_queue_interrupt(&vmx->vcpu, vector,
3874 type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 3875 break;
3876 default:
3877 break;
f7d9238f 3878 }
cf393f75
AK		 3879}
3880
9c8cba37
AK		 3881/*
3882 * Failure to inject an interrupt should give us the information
3883 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
3884 * when fetching the interrupt redirection bitmap in the real-mode
3885 * tss, this doesn't happen. So we do it ourselves.
3886 */
3887static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3888{
3889 vmx->rmode.irq.pending = 0;
5fdbf976 3890 if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
9c8cba37 3891 return;
5fdbf976 3892 kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
9c8cba37
AK		 3893 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3894 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3895 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3896 return;
3897 }
3898 vmx->idt_vectoring_info =
3899 VECTORING_INFO_VALID_MASK
3900 | INTR_TYPE_EXT_INTR
3901 | vmx->rmode.irq.vector;
3902}
3903
c801949d
AK		 3904#ifdef CONFIG_X86_64
3905#define R "r"
3906#define Q "q"
3907#else
3908#define R "e"
3909#define Q "l"
3910#endif
3911
851ba692 3912static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 3913{
a2fa3e9f 3914 struct vcpu_vmx *vmx = to_vmx(vcpu);
e6adf283 3915
3b86cd99
JK		 3916 /* Record the guest's net vcpu time for enforced NMI injections. */
3917 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3918 vmx->entry_time = ktime_get();
3919
80ced186
MG		 3920 /* Don't enter VMX if guest state is invalid, let the exit handler
3921 start emulation until we arrive back to a valid state */
3922 if (vmx->emulation_required && emulate_invalid_guest_state)
a89a8fb9 3923 return;
a89a8fb9 3924
5fdbf976
MT		 3925 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3926 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3927 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3928 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3929
787ff736
GN		 3930 /* When single-stepping over STI and MOV SS, we must clear the
3931 * corresponding interruptibility bits in the guest state. Otherwise
3932 * vmentry fails as it then expects bit 14 (BS) in pending debug
3933 * exceptions being set, but that's not correct for the guest debugging
3934 * case. */
3935 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3936 vmx_set_interrupt_shadow(vcpu, 0);
3937
d77c26fc 3938 asm(
6aa8b732 3939 /* Store host registers */
c801949d
AK		 3940 "push %%"R"dx; push %%"R"bp;"
3941 "push %%"R"cx \n\t"
313dbd49
AK		 3942 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3943 "je 1f \n\t"
3944 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4ecac3fd 3945 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 3946 "1: \n\t"
d3edefc0
AK		 3947 /* Reload cr2 if changed */
3948 "mov %c[cr2](%0), %%"R"ax \n\t"
3949 "mov %%cr2, %%"R"dx \n\t"
3950 "cmp %%"R"ax, %%"R"dx \n\t"
3951 "je 2f \n\t"
3952 "mov %%"R"ax, %%cr2 \n\t"
3953 "2: \n\t"
6aa8b732 3954 /* Check if vmlaunch of vmresume is needed */
e08aa78a 3955 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 3956 /* Load guest registers. Don't clobber flags. */
c801949d
AK		 3957 "mov %c[rax](%0), %%"R"ax \n\t"
3958 "mov %c[rbx](%0), %%"R"bx \n\t"
3959 "mov %c[rdx](%0), %%"R"dx \n\t"
3960 "mov %c[rsi](%0), %%"R"si \n\t"
3961 "mov %c[rdi](%0), %%"R"di \n\t"
3962 "mov %c[rbp](%0), %%"R"bp \n\t"
05b3e0c2 3963#ifdef CONFIG_X86_64
e08aa78a
AK		 3964 "mov %c[r8](%0), %%r8 \n\t"
3965 "mov %c[r9](%0), %%r9 \n\t"
3966 "mov %c[r10](%0), %%r10 \n\t"
3967 "mov %c[r11](%0), %%r11 \n\t"
3968 "mov %c[r12](%0), %%r12 \n\t"
3969 "mov %c[r13](%0), %%r13 \n\t"
3970 "mov %c[r14](%0), %%r14 \n\t"
3971 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 3972#endif
c801949d
AK		 3973 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3974
6aa8b732 3975 /* Enter guest mode */
cd2276a7 3976 "jne .Llaunched \n\t"
4ecac3fd 3977 __ex(ASM_VMX_VMLAUNCH) "\n\t"
cd2276a7 3978 "jmp .Lkvm_vmx_return \n\t"
4ecac3fd 3979 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
cd2276a7 3980 ".Lkvm_vmx_return: "
6aa8b732 3981 /* Save guest registers, load host registers, keep flags */
c801949d
AK		 3982 "xchg %0, (%%"R"sp) \n\t"
3983 "mov %%"R"ax, %c[rax](%0) \n\t"
3984 "mov %%"R"bx, %c[rbx](%0) \n\t"
3985 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3986 "mov %%"R"dx, %c[rdx](%0) \n\t"
3987 "mov %%"R"si, %c[rsi](%0) \n\t"
3988 "mov %%"R"di, %c[rdi](%0) \n\t"
3989 "mov %%"R"bp, %c[rbp](%0) \n\t"
05b3e0c2 3990#ifdef CONFIG_X86_64
e08aa78a
AK		 3991 "mov %%r8, %c[r8](%0) \n\t"
3992 "mov %%r9, %c[r9](%0) \n\t"
3993 "mov %%r10, %c[r10](%0) \n\t"
3994 "mov %%r11, %c[r11](%0) \n\t"
3995 "mov %%r12, %c[r12](%0) \n\t"
3996 "mov %%r13, %c[r13](%0) \n\t"
3997 "mov %%r14, %c[r14](%0) \n\t"
3998 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 3999#endif
c801949d
AK		 4000 "mov %%cr2, %%"R"ax \n\t"
4001 "mov %%"R"ax, %c[cr2](%0) \n\t"
4002
4003 "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t"
e08aa78a
AK		 4004 "setbe %c[fail](%0) \n\t"
4005 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
4006 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
4007 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 4008 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 4009 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
4010 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
4011 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
4012 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
4013 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
4014 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
4015 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 4016#ifdef CONFIG_X86_64
ad312c7c
ZX		 4017 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
4018 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
4019 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
4020 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
4021 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
4022 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
4023 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
4024 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 4025#endif
ad312c7c 4026 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
c2036300 4027 : "cc", "memory"
c801949d 4028 , R"bx", R"di", R"si"
c2036300 4029#ifdef CONFIG_X86_64
c2036300
LV		 4030 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
4031#endif
4032 );
6aa8b732 4033
6de4f3ad
AK		 4034 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
4035 | (1 << VCPU_EXREG_PDPTR));
5fdbf976
MT		 4036 vcpu->arch.regs_dirty = 0;
4037
1155f76a 4038 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9c8cba37
AK		 4039 if (vmx->rmode.irq.pending)
4040 fixup_rmode_irq(vmx);
1155f76a 4041
d77c26fc 4042 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
15ad7146 4043 vmx->launched = 1;
1b6269db 4044
cf393f75 4045 vmx_complete_interrupts(vmx);
6aa8b732
AK		 4046}
4047
c801949d
AK		 4048#undef R
4049#undef Q
4050
6aa8b732
AK		 4051static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
4052{
a2fa3e9f
GH		 4053 struct vcpu_vmx *vmx = to_vmx(vcpu);
4054
4055 if (vmx->vmcs) {
543e4243 4056 vcpu_clear(vmx);
a2fa3e9f
GH		 4057 free_vmcs(vmx->vmcs);
4058 vmx->vmcs = NULL;
6aa8b732
AK		 4059 }
4060}
4061
4062static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
4063{
fb3f0f51
RR		 4064 struct vcpu_vmx *vmx = to_vmx(vcpu);
4065
cdbecfc3 4066 free_vpid(vmx);
6aa8b732 4067 vmx_free_vmcs(vcpu);
fb3f0f51
RR		 4068 kfree(vmx->guest_msrs);
4069 kvm_vcpu_uninit(vcpu);
a4770347 4070 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 4071}
4072
4610c9cc
DX		 4073static inline void vmcs_init(struct vmcs *vmcs)
4074{
4075 u64 phys_addr = __pa(per_cpu(vmxarea, raw_smp_processor_id()));
4076
4077 if (!vmm_exclusive)
4078 kvm_cpu_vmxon(phys_addr);
4079
4080 vmcs_clear(vmcs);
4081
4082 if (!vmm_exclusive)
4083 kvm_cpu_vmxoff();
4084}
4085
fb3f0f51 4086static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 4087{
fb3f0f51 4088 int err;
c16f862d 4089 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 4090 int cpu;
6aa8b732 4091
a2fa3e9f 4092 if (!vmx)
fb3f0f51
RR		 4093 return ERR_PTR(-ENOMEM);
4094
2384d2b3
SY		 4095 allocate_vpid(vmx);
4096
fb3f0f51
RR		 4097 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
4098 if (err)
4099 goto free_vcpu;
965b58a5 4100
a2fa3e9f 4101 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
fb3f0f51
RR		 4102 if (!vmx->guest_msrs) {
4103 err = -ENOMEM;
4104 goto uninit_vcpu;
4105 }
965b58a5 4106
a2fa3e9f
GH		 4107 vmx->vmcs = alloc_vmcs();
4108 if (!vmx->vmcs)
fb3f0f51 4109 goto free_msrs;
a2fa3e9f 4110
4610c9cc 4111 vmcs_init(vmx->vmcs);
a2fa3e9f 4112
15ad7146
AK		 4113 cpu = get_cpu();
4114 vmx_vcpu_load(&vmx->vcpu, cpu);
8b9cf98c 4115 err = vmx_vcpu_setup(vmx);
fb3f0f51 4116 vmx_vcpu_put(&vmx->vcpu);
15ad7146 4117 put_cpu();
fb3f0f51
RR		 4118 if (err)
4119 goto free_vmcs;
5e4a0b3c
MT		 4120 if (vm_need_virtualize_apic_accesses(kvm))
4121 if (alloc_apic_access_page(kvm) != 0)
4122 goto free_vmcs;
fb3f0f51 4123
b927a3ce
SY		 4124 if (enable_ept) {
4125 if (!kvm->arch.ept_identity_map_addr)
4126 kvm->arch.ept_identity_map_addr =
4127 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
b7ebfb05
SY		 4128 if (alloc_identity_pagetable(kvm) != 0)
4129 goto free_vmcs;
b927a3ce 4130 }
b7ebfb05 4131
fb3f0f51
RR		 4132 return &vmx->vcpu;
4133
4134free_vmcs:
4135 free_vmcs(vmx->vmcs);
4136free_msrs:
fb3f0f51
RR		 4137 kfree(vmx->guest_msrs);
4138uninit_vcpu:
4139 kvm_vcpu_uninit(&vmx->vcpu);
4140free_vcpu:
cdbecfc3 4141 free_vpid(vmx);
a4770347 4142 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 4143 return ERR_PTR(err);
6aa8b732
AK		 4144}
4145
002c7f7c
YS		 4146static void __init vmx_check_processor_compat(void *rtn)
4147{
4148 struct vmcs_config vmcs_conf;
4149
4150 *(int *)rtn = 0;
4151 if (setup_vmcs_config(&vmcs_conf) < 0)
4152 *(int *)rtn = -EIO;
4153 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
4154 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
4155 smp_processor_id());
4156 *(int *)rtn = -EIO;
4157 }
4158}
4159
67253af5
SY		 4160static int get_ept_level(void)
4161{
4162 return VMX_EPT_DEFAULT_GAW + 1;
4163}
4164
4b12f0de 4165static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 4166{
4b12f0de
SY		 4167 u64 ret;
4168
522c68c4
SY		 4169 /* For VT-d and EPT combination
4170 * 1. MMIO: always map as UC
4171 * 2. EPT with VT-d:
4172 * a. VT-d without snooping control feature: can't guarantee the
4173 * result, try to trust guest.
4174 * b. VT-d with snooping control feature: snooping control feature of
4175 * VT-d engine can guarantee the cache correctness. Just set it
4176 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 4177 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 4178 * consistent with host MTRR
4179 */
4b12f0de
SY		 4180 if (is_mmio)
4181 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 4182 else if (vcpu->kvm->arch.iommu_domain &&
4183 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
4184 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
4185 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 4186 else
522c68c4 4187 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 4188 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 4189
4190 return ret;
64d4d521
SY		 4191}
4192
f4c9e87c
AK		 4193#define _ER(x) { EXIT_REASON_##x, #x }
4194
229456fc 4195static const struct trace_print_flags vmx_exit_reasons_str[] = {
f4c9e87c
AK		 4196 _ER(EXCEPTION_NMI),
4197 _ER(EXTERNAL_INTERRUPT),
4198 _ER(TRIPLE_FAULT),
4199 _ER(PENDING_INTERRUPT),
4200 _ER(NMI_WINDOW),
4201 _ER(TASK_SWITCH),
4202 _ER(CPUID),
4203 _ER(HLT),
4204 _ER(INVLPG),
4205 _ER(RDPMC),
4206 _ER(RDTSC),
4207 _ER(VMCALL),
4208 _ER(VMCLEAR),
4209 _ER(VMLAUNCH),
4210 _ER(VMPTRLD),
4211 _ER(VMPTRST),
4212 _ER(VMREAD),
4213 _ER(VMRESUME),
4214 _ER(VMWRITE),
4215 _ER(VMOFF),
4216 _ER(VMON),
4217 _ER(CR_ACCESS),
4218 _ER(DR_ACCESS),
4219 _ER(IO_INSTRUCTION),
4220 _ER(MSR_READ),
4221 _ER(MSR_WRITE),
4222 _ER(MWAIT_INSTRUCTION),
4223 _ER(MONITOR_INSTRUCTION),
4224 _ER(PAUSE_INSTRUCTION),
4225 _ER(MCE_DURING_VMENTRY),
4226 _ER(TPR_BELOW_THRESHOLD),
4227 _ER(APIC_ACCESS),
4228 _ER(EPT_VIOLATION),
4229 _ER(EPT_MISCONFIG),
4230 _ER(WBINVD),
229456fc
MT		 4231 { -1, NULL }
4232};
4233
f4c9e87c
AK		 4234#undef _ER
4235
17cc3935 4236static int vmx_get_lpage_level(void)
344f414f 4237{
878403b7
SY		 4238 if (enable_ept && !cpu_has_vmx_ept_1g_page())
4239 return PT_DIRECTORY_LEVEL;
4240 else
4241 /* For shadow and EPT supported 1GB page */
4242 return PT_PDPE_LEVEL;
344f414f
JR		 4243}
4244
4e47c7a6
SY		 4245static inline u32 bit(int bitno)
4246{
4247 return 1 << (bitno & 31);
4248}
4249
0e851880
SY		 4250static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
4251{
4e47c7a6
SY		 4252 struct kvm_cpuid_entry2 *best;
4253 struct vcpu_vmx *vmx = to_vmx(vcpu);
4254 u32 exec_control;
4255
4256 vmx->rdtscp_enabled = false;
4257 if (vmx_rdtscp_supported()) {
4258 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
4259 if (exec_control & SECONDARY_EXEC_RDTSCP) {
4260 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
4261 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
4262 vmx->rdtscp_enabled = true;
4263 else {
4264 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4265 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4266 exec_control);
4267 }
4268 }
4269 }
0e851880
SY		 4270}
4271
d4330ef2
JR		 4272static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4273{
4274}
4275
cbdd1bea 4276static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 4277 .cpu_has_kvm_support = cpu_has_kvm_support,
4278 .disabled_by_bios = vmx_disabled_by_bios,
4279 .hardware_setup = hardware_setup,
4280 .hardware_unsetup = hardware_unsetup,
002c7f7c 4281 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 4282 .hardware_enable = hardware_enable,
4283 .hardware_disable = hardware_disable,
04547156 4284 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 4285
4286 .vcpu_create = vmx_create_vcpu,
4287 .vcpu_free = vmx_free_vcpu,
04d2cc77 4288 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 4289
04d2cc77 4290 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 4291 .vcpu_load = vmx_vcpu_load,
4292 .vcpu_put = vmx_vcpu_put,
4293
4294 .set_guest_debug = set_guest_debug,
4295 .get_msr = vmx_get_msr,
4296 .set_msr = vmx_set_msr,
4297 .get_segment_base = vmx_get_segment_base,
4298 .get_segment = vmx_get_segment,
4299 .set_segment = vmx_set_segment,
2e4d2653 4300 .get_cpl = vmx_get_cpl,
6aa8b732 4301 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 4302 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
25c4c276 4303 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 4304 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 4305 .set_cr3 = vmx_set_cr3,
4306 .set_cr4 = vmx_set_cr4,
6aa8b732 4307 .set_efer = vmx_set_efer,
6aa8b732
AK		 4308 .get_idt = vmx_get_idt,
4309 .set_idt = vmx_set_idt,
4310 .get_gdt = vmx_get_gdt,
4311 .set_gdt = vmx_set_gdt,
020df079 4312 .set_dr7 = vmx_set_dr7,
5fdbf976 4313 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 4314 .get_rflags = vmx_get_rflags,
4315 .set_rflags = vmx_set_rflags,
ebcbab4c 4316 .fpu_activate = vmx_fpu_activate,
02daab21 4317 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 4318
4319 .tlb_flush = vmx_flush_tlb,
6aa8b732 4320
6aa8b732 4321 .run = vmx_vcpu_run,
6062d012 4322 .handle_exit = vmx_handle_exit,
6aa8b732 4323 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 4324 .set_interrupt_shadow = vmx_set_interrupt_shadow,
4325 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 4326 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 4327 .set_irq = vmx_inject_irq,
95ba8273 4328 .set_nmi = vmx_inject_nmi,
298101da 4329 .queue_exception = vmx_queue_exception,
78646121 4330 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 4331 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 4332 .get_nmi_mask = vmx_get_nmi_mask,
4333 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 4334 .enable_nmi_window = enable_nmi_window,
4335 .enable_irq_window = enable_irq_window,
4336 .update_cr8_intercept = update_cr8_intercept,
95ba8273 4337
cbc94022 4338 .set_tss_addr = vmx_set_tss_addr,
67253af5 4339 .get_tdp_level = get_ept_level,
4b12f0de 4340 .get_mt_mask = vmx_get_mt_mask,
229456fc
MT		 4341
4342 .exit_reasons_str = vmx_exit_reasons_str,
17cc3935 4343 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 4344
4345 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 4346
4347 .rdtscp_supported = vmx_rdtscp_supported,
d4330ef2
JR		 4348
4349 .set_supported_cpuid = vmx_set_supported_cpuid,
6aa8b732
AK		 4350};
4351
4352static int __init vmx_init(void)
4353{
26bb0981
AK		 4354 int r, i;
4355
4356 rdmsrl_safe(MSR_EFER, &host_efer);
4357
4358 for (i = 0; i < NR_VMX_MSR; ++i)
4359 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 4360
3e7c73e9 4361 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 4362 if (!vmx_io_bitmap_a)
4363 return -ENOMEM;
4364
3e7c73e9 4365 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 4366 if (!vmx_io_bitmap_b) {
4367 r = -ENOMEM;
4368 goto out;
4369 }
4370
5897297b
AK		 4371 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4372 if (!vmx_msr_bitmap_legacy) {
25c5f225
SY		 4373 r = -ENOMEM;
4374 goto out1;
4375 }
4376
5897297b
AK		 4377 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4378 if (!vmx_msr_bitmap_longmode) {
4379 r = -ENOMEM;
4380 goto out2;
4381 }
4382
fdef3ad1
HQ		 4383 /*
4384 * Allow direct access to the PC debug port (it is often used for I/O
4385 * delays, but the vmexits simply slow things down).
4386 */
3e7c73e9
AK		 4387 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4388 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 4389
3e7c73e9 4390 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 4391
5897297b
AK		 4392 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4393 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 4394
2384d2b3
SY		 4395 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4396
0ee75bea
AK		 4397 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
4398 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 4399 if (r)
5897297b 4400 goto out3;
25c5f225 4401
5897297b
AK		 4402 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4403 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4404 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4405 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4406 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4407 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
fdef3ad1 4408
089d034e 4409 if (enable_ept) {
1439442c 4410 bypass_guest_pf = 0;
5fdbcb9d 4411 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
2aaf69dc 4412 VMX_EPT_WRITABLE_MASK);
534e38b4 4413 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4b12f0de 4414 VMX_EPT_EXECUTABLE_MASK);
5fdbcb9d
SY		 4415 kvm_enable_tdp();
4416 } else
4417 kvm_disable_tdp();
1439442c 4418
c7addb90
AK		 4419 if (bypass_guest_pf)
4420 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4421
fdef3ad1
HQ		 4422 return 0;
4423
5897297b
AK		 4424out3:
4425 free_page((unsigned long)vmx_msr_bitmap_longmode);
25c5f225 4426out2:
5897297b 4427 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 4428out1:
3e7c73e9 4429 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 4430out:
3e7c73e9 4431 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 4432 return r;
6aa8b732
AK		 4433}
4434
4435static void __exit vmx_exit(void)
4436{
5897297b
AK		 4437 free_page((unsigned long)vmx_msr_bitmap_legacy);
4438 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 4439 free_page((unsigned long)vmx_io_bitmap_b);
4440 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 4441
cb498ea2 4442 kvm_exit();
6aa8b732
AK		 4443}
4444
4445module_init(vmx_init)
4446module_exit(vmx_exit)
Linux kernel - Deliverables
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