Commit | Line | Data |
---|---|---|
6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 8 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
9 | * |
10 | * Authors: | |
11 | * Avi Kivity <avi@qumranet.com> | |
12 | * Yaniv Kamay <yaniv@qumranet.com> | |
13 | * | |
14 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
15 | * the COPYING file in the top-level directory. | |
16 | * | |
17 | */ | |
18 | ||
85f455f7 | 19 | #include "irq.h" |
1d737c8a | 20 | #include "mmu.h" |
00b27a3e | 21 | #include "cpuid.h" |
e495606d | 22 | |
edf88417 | 23 | #include <linux/kvm_host.h> |
6aa8b732 | 24 | #include <linux/module.h> |
9d8f549d | 25 | #include <linux/kernel.h> |
6aa8b732 AK |
26 | #include <linux/mm.h> |
27 | #include <linux/highmem.h> | |
e8edc6e0 | 28 | #include <linux/sched.h> |
c7addb90 | 29 | #include <linux/moduleparam.h> |
e9bda3b3 | 30 | #include <linux/mod_devicetable.h> |
229456fc | 31 | #include <linux/ftrace_event.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
cafd6659 | 33 | #include <linux/tboot.h> |
f4124500 | 34 | #include <linux/hrtimer.h> |
5fdbf976 | 35 | #include "kvm_cache_regs.h" |
35920a35 | 36 | #include "x86.h" |
e495606d | 37 | |
6aa8b732 | 38 | #include <asm/io.h> |
3b3be0d1 | 39 | #include <asm/desc.h> |
13673a90 | 40 | #include <asm/vmx.h> |
6210e37b | 41 | #include <asm/virtext.h> |
a0861c02 | 42 | #include <asm/mce.h> |
2acf923e DC |
43 | #include <asm/i387.h> |
44 | #include <asm/xcr.h> | |
d7cd9796 | 45 | #include <asm/perf_event.h> |
81908bf4 | 46 | #include <asm/debugreg.h> |
8f536b76 | 47 | #include <asm/kexec.h> |
6aa8b732 | 48 | |
229456fc MT |
49 | #include "trace.h" |
50 | ||
4ecac3fd | 51 | #define __ex(x) __kvm_handle_fault_on_reboot(x) |
5e520e62 AK |
52 | #define __ex_clear(x, reg) \ |
53 | ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg) | |
4ecac3fd | 54 | |
6aa8b732 AK |
55 | MODULE_AUTHOR("Qumranet"); |
56 | MODULE_LICENSE("GPL"); | |
57 | ||
e9bda3b3 JT |
58 | static const struct x86_cpu_id vmx_cpu_id[] = { |
59 | X86_FEATURE_MATCH(X86_FEATURE_VMX), | |
60 | {} | |
61 | }; | |
62 | MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id); | |
63 | ||
476bc001 | 64 | static bool __read_mostly enable_vpid = 1; |
736caefe | 65 | module_param_named(vpid, enable_vpid, bool, 0444); |
2384d2b3 | 66 | |
476bc001 | 67 | static bool __read_mostly flexpriority_enabled = 1; |
736caefe | 68 | module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO); |
4c9fc8ef | 69 | |
476bc001 | 70 | static bool __read_mostly enable_ept = 1; |
736caefe | 71 | module_param_named(ept, enable_ept, bool, S_IRUGO); |
d56f546d | 72 | |
476bc001 | 73 | static bool __read_mostly enable_unrestricted_guest = 1; |
3a624e29 NK |
74 | module_param_named(unrestricted_guest, |
75 | enable_unrestricted_guest, bool, S_IRUGO); | |
76 | ||
83c3a331 XH |
77 | static bool __read_mostly enable_ept_ad_bits = 1; |
78 | module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO); | |
79 | ||
a27685c3 | 80 | static bool __read_mostly emulate_invalid_guest_state = true; |
c1f8bc04 | 81 | module_param(emulate_invalid_guest_state, bool, S_IRUGO); |
04fa4d32 | 82 | |
476bc001 | 83 | static bool __read_mostly vmm_exclusive = 1; |
b923e62e DX |
84 | module_param(vmm_exclusive, bool, S_IRUGO); |
85 | ||
476bc001 | 86 | static bool __read_mostly fasteoi = 1; |
58fbbf26 KT |
87 | module_param(fasteoi, bool, S_IRUGO); |
88 | ||
5a71785d | 89 | static bool __read_mostly enable_apicv = 1; |
01e439be | 90 | module_param(enable_apicv, bool, S_IRUGO); |
83d4c286 | 91 | |
abc4fc58 AG |
92 | static bool __read_mostly enable_shadow_vmcs = 1; |
93 | module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO); | |
801d3424 NHE |
94 | /* |
95 | * If nested=1, nested virtualization is supported, i.e., guests may use | |
96 | * VMX and be a hypervisor for its own guests. If nested=0, guests may not | |
97 | * use VMX instructions. | |
98 | */ | |
476bc001 | 99 | static bool __read_mostly nested = 0; |
801d3424 NHE |
100 | module_param(nested, bool, S_IRUGO); |
101 | ||
20300099 WL |
102 | static u64 __read_mostly host_xss; |
103 | ||
5037878e GN |
104 | #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD) |
105 | #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE) | |
cdc0e244 AK |
106 | #define KVM_VM_CR0_ALWAYS_ON \ |
107 | (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE) | |
4c38609a AK |
108 | #define KVM_CR4_GUEST_OWNED_BITS \ |
109 | (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \ | |
52ce3c21 | 110 | | X86_CR4_OSXMMEXCPT | X86_CR4_TSD) |
4c38609a | 111 | |
cdc0e244 AK |
112 | #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE) |
113 | #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE) | |
114 | ||
78ac8b47 AK |
115 | #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM)) |
116 | ||
f4124500 JK |
117 | #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5 |
118 | ||
4b8d54f9 ZE |
119 | /* |
120 | * These 2 parameters are used to config the controls for Pause-Loop Exiting: | |
121 | * ple_gap: upper bound on the amount of time between two successive | |
122 | * executions of PAUSE in a loop. Also indicate if ple enabled. | |
00c25bce | 123 | * According to test, this time is usually smaller than 128 cycles. |
4b8d54f9 ZE |
124 | * ple_window: upper bound on the amount of time a guest is allowed to execute |
125 | * in a PAUSE loop. Tests indicate that most spinlocks are held for | |
126 | * less than 2^12 cycles | |
127 | * Time is measured based on a counter that runs at the same rate as the TSC, | |
128 | * refer SDM volume 3b section 21.6.13 & 22.1.3. | |
129 | */ | |
b4a2d31d RK |
130 | #define KVM_VMX_DEFAULT_PLE_GAP 128 |
131 | #define KVM_VMX_DEFAULT_PLE_WINDOW 4096 | |
132 | #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2 | |
133 | #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0 | |
134 | #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \ | |
135 | INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW | |
136 | ||
4b8d54f9 ZE |
137 | static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP; |
138 | module_param(ple_gap, int, S_IRUGO); | |
139 | ||
140 | static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW; | |
141 | module_param(ple_window, int, S_IRUGO); | |
142 | ||
b4a2d31d RK |
143 | /* Default doubles per-vcpu window every exit. */ |
144 | static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW; | |
145 | module_param(ple_window_grow, int, S_IRUGO); | |
146 | ||
147 | /* Default resets per-vcpu window every exit to ple_window. */ | |
148 | static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK; | |
149 | module_param(ple_window_shrink, int, S_IRUGO); | |
150 | ||
151 | /* Default is to compute the maximum so we can never overflow. */ | |
152 | static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX; | |
153 | static int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX; | |
154 | module_param(ple_window_max, int, S_IRUGO); | |
155 | ||
83287ea4 AK |
156 | extern const ulong vmx_return; |
157 | ||
8bf00a52 | 158 | #define NR_AUTOLOAD_MSRS 8 |
ff2f6fe9 | 159 | #define VMCS02_POOL_SIZE 1 |
61d2ef2c | 160 | |
a2fa3e9f GH |
161 | struct vmcs { |
162 | u32 revision_id; | |
163 | u32 abort; | |
164 | char data[0]; | |
165 | }; | |
166 | ||
d462b819 NHE |
167 | /* |
168 | * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also | |
169 | * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs | |
170 | * loaded on this CPU (so we can clear them if the CPU goes down). | |
171 | */ | |
172 | struct loaded_vmcs { | |
173 | struct vmcs *vmcs; | |
174 | int cpu; | |
175 | int launched; | |
176 | struct list_head loaded_vmcss_on_cpu_link; | |
177 | }; | |
178 | ||
26bb0981 AK |
179 | struct shared_msr_entry { |
180 | unsigned index; | |
181 | u64 data; | |
d5696725 | 182 | u64 mask; |
26bb0981 AK |
183 | }; |
184 | ||
a9d30f33 NHE |
185 | /* |
186 | * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a | |
187 | * single nested guest (L2), hence the name vmcs12. Any VMX implementation has | |
188 | * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is | |
189 | * stored in guest memory specified by VMPTRLD, but is opaque to the guest, | |
190 | * which must access it using VMREAD/VMWRITE/VMCLEAR instructions. | |
191 | * More than one of these structures may exist, if L1 runs multiple L2 guests. | |
192 | * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the | |
193 | * underlying hardware which will be used to run L2. | |
194 | * This structure is packed to ensure that its layout is identical across | |
195 | * machines (necessary for live migration). | |
196 | * If there are changes in this struct, VMCS12_REVISION must be changed. | |
197 | */ | |
22bd0358 | 198 | typedef u64 natural_width; |
a9d30f33 NHE |
199 | struct __packed vmcs12 { |
200 | /* According to the Intel spec, a VMCS region must start with the | |
201 | * following two fields. Then follow implementation-specific data. | |
202 | */ | |
203 | u32 revision_id; | |
204 | u32 abort; | |
22bd0358 | 205 | |
27d6c865 NHE |
206 | u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */ |
207 | u32 padding[7]; /* room for future expansion */ | |
208 | ||
22bd0358 NHE |
209 | u64 io_bitmap_a; |
210 | u64 io_bitmap_b; | |
211 | u64 msr_bitmap; | |
212 | u64 vm_exit_msr_store_addr; | |
213 | u64 vm_exit_msr_load_addr; | |
214 | u64 vm_entry_msr_load_addr; | |
215 | u64 tsc_offset; | |
216 | u64 virtual_apic_page_addr; | |
217 | u64 apic_access_addr; | |
218 | u64 ept_pointer; | |
81dc01f7 | 219 | u64 xss_exit_bitmap; |
22bd0358 NHE |
220 | u64 guest_physical_address; |
221 | u64 vmcs_link_pointer; | |
222 | u64 guest_ia32_debugctl; | |
223 | u64 guest_ia32_pat; | |
224 | u64 guest_ia32_efer; | |
225 | u64 guest_ia32_perf_global_ctrl; | |
226 | u64 guest_pdptr0; | |
227 | u64 guest_pdptr1; | |
228 | u64 guest_pdptr2; | |
229 | u64 guest_pdptr3; | |
36be0b9d | 230 | u64 guest_bndcfgs; |
22bd0358 NHE |
231 | u64 host_ia32_pat; |
232 | u64 host_ia32_efer; | |
233 | u64 host_ia32_perf_global_ctrl; | |
234 | u64 padding64[8]; /* room for future expansion */ | |
235 | /* | |
236 | * To allow migration of L1 (complete with its L2 guests) between | |
237 | * machines of different natural widths (32 or 64 bit), we cannot have | |
238 | * unsigned long fields with no explict size. We use u64 (aliased | |
239 | * natural_width) instead. Luckily, x86 is little-endian. | |
240 | */ | |
241 | natural_width cr0_guest_host_mask; | |
242 | natural_width cr4_guest_host_mask; | |
243 | natural_width cr0_read_shadow; | |
244 | natural_width cr4_read_shadow; | |
245 | natural_width cr3_target_value0; | |
246 | natural_width cr3_target_value1; | |
247 | natural_width cr3_target_value2; | |
248 | natural_width cr3_target_value3; | |
249 | natural_width exit_qualification; | |
250 | natural_width guest_linear_address; | |
251 | natural_width guest_cr0; | |
252 | natural_width guest_cr3; | |
253 | natural_width guest_cr4; | |
254 | natural_width guest_es_base; | |
255 | natural_width guest_cs_base; | |
256 | natural_width guest_ss_base; | |
257 | natural_width guest_ds_base; | |
258 | natural_width guest_fs_base; | |
259 | natural_width guest_gs_base; | |
260 | natural_width guest_ldtr_base; | |
261 | natural_width guest_tr_base; | |
262 | natural_width guest_gdtr_base; | |
263 | natural_width guest_idtr_base; | |
264 | natural_width guest_dr7; | |
265 | natural_width guest_rsp; | |
266 | natural_width guest_rip; | |
267 | natural_width guest_rflags; | |
268 | natural_width guest_pending_dbg_exceptions; | |
269 | natural_width guest_sysenter_esp; | |
270 | natural_width guest_sysenter_eip; | |
271 | natural_width host_cr0; | |
272 | natural_width host_cr3; | |
273 | natural_width host_cr4; | |
274 | natural_width host_fs_base; | |
275 | natural_width host_gs_base; | |
276 | natural_width host_tr_base; | |
277 | natural_width host_gdtr_base; | |
278 | natural_width host_idtr_base; | |
279 | natural_width host_ia32_sysenter_esp; | |
280 | natural_width host_ia32_sysenter_eip; | |
281 | natural_width host_rsp; | |
282 | natural_width host_rip; | |
283 | natural_width paddingl[8]; /* room for future expansion */ | |
284 | u32 pin_based_vm_exec_control; | |
285 | u32 cpu_based_vm_exec_control; | |
286 | u32 exception_bitmap; | |
287 | u32 page_fault_error_code_mask; | |
288 | u32 page_fault_error_code_match; | |
289 | u32 cr3_target_count; | |
290 | u32 vm_exit_controls; | |
291 | u32 vm_exit_msr_store_count; | |
292 | u32 vm_exit_msr_load_count; | |
293 | u32 vm_entry_controls; | |
294 | u32 vm_entry_msr_load_count; | |
295 | u32 vm_entry_intr_info_field; | |
296 | u32 vm_entry_exception_error_code; | |
297 | u32 vm_entry_instruction_len; | |
298 | u32 tpr_threshold; | |
299 | u32 secondary_vm_exec_control; | |
300 | u32 vm_instruction_error; | |
301 | u32 vm_exit_reason; | |
302 | u32 vm_exit_intr_info; | |
303 | u32 vm_exit_intr_error_code; | |
304 | u32 idt_vectoring_info_field; | |
305 | u32 idt_vectoring_error_code; | |
306 | u32 vm_exit_instruction_len; | |
307 | u32 vmx_instruction_info; | |
308 | u32 guest_es_limit; | |
309 | u32 guest_cs_limit; | |
310 | u32 guest_ss_limit; | |
311 | u32 guest_ds_limit; | |
312 | u32 guest_fs_limit; | |
313 | u32 guest_gs_limit; | |
314 | u32 guest_ldtr_limit; | |
315 | u32 guest_tr_limit; | |
316 | u32 guest_gdtr_limit; | |
317 | u32 guest_idtr_limit; | |
318 | u32 guest_es_ar_bytes; | |
319 | u32 guest_cs_ar_bytes; | |
320 | u32 guest_ss_ar_bytes; | |
321 | u32 guest_ds_ar_bytes; | |
322 | u32 guest_fs_ar_bytes; | |
323 | u32 guest_gs_ar_bytes; | |
324 | u32 guest_ldtr_ar_bytes; | |
325 | u32 guest_tr_ar_bytes; | |
326 | u32 guest_interruptibility_info; | |
327 | u32 guest_activity_state; | |
328 | u32 guest_sysenter_cs; | |
329 | u32 host_ia32_sysenter_cs; | |
0238ea91 JK |
330 | u32 vmx_preemption_timer_value; |
331 | u32 padding32[7]; /* room for future expansion */ | |
22bd0358 NHE |
332 | u16 virtual_processor_id; |
333 | u16 guest_es_selector; | |
334 | u16 guest_cs_selector; | |
335 | u16 guest_ss_selector; | |
336 | u16 guest_ds_selector; | |
337 | u16 guest_fs_selector; | |
338 | u16 guest_gs_selector; | |
339 | u16 guest_ldtr_selector; | |
340 | u16 guest_tr_selector; | |
341 | u16 host_es_selector; | |
342 | u16 host_cs_selector; | |
343 | u16 host_ss_selector; | |
344 | u16 host_ds_selector; | |
345 | u16 host_fs_selector; | |
346 | u16 host_gs_selector; | |
347 | u16 host_tr_selector; | |
a9d30f33 NHE |
348 | }; |
349 | ||
350 | /* | |
351 | * VMCS12_REVISION is an arbitrary id that should be changed if the content or | |
352 | * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and | |
353 | * VMPTRLD verifies that the VMCS region that L1 is loading contains this id. | |
354 | */ | |
355 | #define VMCS12_REVISION 0x11e57ed0 | |
356 | ||
357 | /* | |
358 | * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region | |
359 | * and any VMCS region. Although only sizeof(struct vmcs12) are used by the | |
360 | * current implementation, 4K are reserved to avoid future complications. | |
361 | */ | |
362 | #define VMCS12_SIZE 0x1000 | |
363 | ||
ff2f6fe9 NHE |
364 | /* Used to remember the last vmcs02 used for some recently used vmcs12s */ |
365 | struct vmcs02_list { | |
366 | struct list_head list; | |
367 | gpa_t vmptr; | |
368 | struct loaded_vmcs vmcs02; | |
369 | }; | |
370 | ||
ec378aee NHE |
371 | /* |
372 | * The nested_vmx structure is part of vcpu_vmx, and holds information we need | |
373 | * for correct emulation of VMX (i.e., nested VMX) on this vcpu. | |
374 | */ | |
375 | struct nested_vmx { | |
376 | /* Has the level1 guest done vmxon? */ | |
377 | bool vmxon; | |
3573e22c | 378 | gpa_t vmxon_ptr; |
a9d30f33 NHE |
379 | |
380 | /* The guest-physical address of the current VMCS L1 keeps for L2 */ | |
381 | gpa_t current_vmptr; | |
382 | /* The host-usable pointer to the above */ | |
383 | struct page *current_vmcs12_page; | |
384 | struct vmcs12 *current_vmcs12; | |
8de48833 | 385 | struct vmcs *current_shadow_vmcs; |
012f83cb AG |
386 | /* |
387 | * Indicates if the shadow vmcs must be updated with the | |
388 | * data hold by vmcs12 | |
389 | */ | |
390 | bool sync_shadow_vmcs; | |
ff2f6fe9 NHE |
391 | |
392 | /* vmcs02_list cache of VMCSs recently used to run L2 guests */ | |
393 | struct list_head vmcs02_pool; | |
394 | int vmcs02_num; | |
fe3ef05c | 395 | u64 vmcs01_tsc_offset; |
644d711a NHE |
396 | /* L2 must run next, and mustn't decide to exit to L1. */ |
397 | bool nested_run_pending; | |
fe3ef05c NHE |
398 | /* |
399 | * Guest pages referred to in vmcs02 with host-physical pointers, so | |
400 | * we must keep them pinned while L2 runs. | |
401 | */ | |
402 | struct page *apic_access_page; | |
a7c0b07d | 403 | struct page *virtual_apic_page; |
b3897a49 | 404 | u64 msr_ia32_feature_control; |
f4124500 JK |
405 | |
406 | struct hrtimer preemption_timer; | |
407 | bool preemption_timer_expired; | |
2996fca0 JK |
408 | |
409 | /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */ | |
410 | u64 vmcs01_debugctl; | |
ec378aee NHE |
411 | }; |
412 | ||
01e439be YZ |
413 | #define POSTED_INTR_ON 0 |
414 | /* Posted-Interrupt Descriptor */ | |
415 | struct pi_desc { | |
416 | u32 pir[8]; /* Posted interrupt requested */ | |
417 | u32 control; /* bit 0 of control is outstanding notification bit */ | |
418 | u32 rsvd[7]; | |
419 | } __aligned(64); | |
420 | ||
a20ed54d YZ |
421 | static bool pi_test_and_set_on(struct pi_desc *pi_desc) |
422 | { | |
423 | return test_and_set_bit(POSTED_INTR_ON, | |
424 | (unsigned long *)&pi_desc->control); | |
425 | } | |
426 | ||
427 | static bool pi_test_and_clear_on(struct pi_desc *pi_desc) | |
428 | { | |
429 | return test_and_clear_bit(POSTED_INTR_ON, | |
430 | (unsigned long *)&pi_desc->control); | |
431 | } | |
432 | ||
433 | static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc) | |
434 | { | |
435 | return test_and_set_bit(vector, (unsigned long *)pi_desc->pir); | |
436 | } | |
437 | ||
a2fa3e9f | 438 | struct vcpu_vmx { |
fb3f0f51 | 439 | struct kvm_vcpu vcpu; |
313dbd49 | 440 | unsigned long host_rsp; |
29bd8a78 | 441 | u8 fail; |
9d58b931 | 442 | bool nmi_known_unmasked; |
51aa01d1 | 443 | u32 exit_intr_info; |
1155f76a | 444 | u32 idt_vectoring_info; |
6de12732 | 445 | ulong rflags; |
26bb0981 | 446 | struct shared_msr_entry *guest_msrs; |
a2fa3e9f GH |
447 | int nmsrs; |
448 | int save_nmsrs; | |
a547c6db | 449 | unsigned long host_idt_base; |
a2fa3e9f | 450 | #ifdef CONFIG_X86_64 |
44ea2b17 AK |
451 | u64 msr_host_kernel_gs_base; |
452 | u64 msr_guest_kernel_gs_base; | |
a2fa3e9f | 453 | #endif |
2961e876 GN |
454 | u32 vm_entry_controls_shadow; |
455 | u32 vm_exit_controls_shadow; | |
d462b819 NHE |
456 | /* |
457 | * loaded_vmcs points to the VMCS currently used in this vcpu. For a | |
458 | * non-nested (L1) guest, it always points to vmcs01. For a nested | |
459 | * guest (L2), it points to a different VMCS. | |
460 | */ | |
461 | struct loaded_vmcs vmcs01; | |
462 | struct loaded_vmcs *loaded_vmcs; | |
463 | bool __launched; /* temporary, used in vmx_vcpu_run */ | |
61d2ef2c AK |
464 | struct msr_autoload { |
465 | unsigned nr; | |
466 | struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS]; | |
467 | struct vmx_msr_entry host[NR_AUTOLOAD_MSRS]; | |
468 | } msr_autoload; | |
a2fa3e9f GH |
469 | struct { |
470 | int loaded; | |
471 | u16 fs_sel, gs_sel, ldt_sel; | |
b2da15ac AK |
472 | #ifdef CONFIG_X86_64 |
473 | u16 ds_sel, es_sel; | |
474 | #endif | |
152d3f2f LV |
475 | int gs_ldt_reload_needed; |
476 | int fs_reload_needed; | |
da8999d3 | 477 | u64 msr_host_bndcfgs; |
d974baa3 | 478 | unsigned long vmcs_host_cr4; /* May not match real cr4 */ |
d77c26fc | 479 | } host_state; |
9c8cba37 | 480 | struct { |
7ffd92c5 | 481 | int vm86_active; |
78ac8b47 | 482 | ulong save_rflags; |
f5f7b2fe AK |
483 | struct kvm_segment segs[8]; |
484 | } rmode; | |
485 | struct { | |
486 | u32 bitmask; /* 4 bits per segment (1 bit per field) */ | |
7ffd92c5 AK |
487 | struct kvm_save_segment { |
488 | u16 selector; | |
489 | unsigned long base; | |
490 | u32 limit; | |
491 | u32 ar; | |
f5f7b2fe | 492 | } seg[8]; |
2fb92db1 | 493 | } segment_cache; |
2384d2b3 | 494 | int vpid; |
04fa4d32 | 495 | bool emulation_required; |
3b86cd99 JK |
496 | |
497 | /* Support for vnmi-less CPUs */ | |
498 | int soft_vnmi_blocked; | |
499 | ktime_t entry_time; | |
500 | s64 vnmi_blocked_time; | |
a0861c02 | 501 | u32 exit_reason; |
4e47c7a6 SY |
502 | |
503 | bool rdtscp_enabled; | |
ec378aee | 504 | |
01e439be YZ |
505 | /* Posted interrupt descriptor */ |
506 | struct pi_desc pi_desc; | |
507 | ||
ec378aee NHE |
508 | /* Support for a guest hypervisor (nested VMX) */ |
509 | struct nested_vmx nested; | |
a7653ecd RK |
510 | |
511 | /* Dynamic PLE window. */ | |
512 | int ple_window; | |
513 | bool ple_window_dirty; | |
a2fa3e9f GH |
514 | }; |
515 | ||
2fb92db1 AK |
516 | enum segment_cache_field { |
517 | SEG_FIELD_SEL = 0, | |
518 | SEG_FIELD_BASE = 1, | |
519 | SEG_FIELD_LIMIT = 2, | |
520 | SEG_FIELD_AR = 3, | |
521 | ||
522 | SEG_FIELD_NR = 4 | |
523 | }; | |
524 | ||
a2fa3e9f GH |
525 | static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu) |
526 | { | |
fb3f0f51 | 527 | return container_of(vcpu, struct vcpu_vmx, vcpu); |
a2fa3e9f GH |
528 | } |
529 | ||
22bd0358 NHE |
530 | #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x) |
531 | #define FIELD(number, name) [number] = VMCS12_OFFSET(name) | |
532 | #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \ | |
533 | [number##_HIGH] = VMCS12_OFFSET(name)+4 | |
534 | ||
4607c2d7 | 535 | |
fe2b201b | 536 | static unsigned long shadow_read_only_fields[] = { |
4607c2d7 AG |
537 | /* |
538 | * We do NOT shadow fields that are modified when L0 | |
539 | * traps and emulates any vmx instruction (e.g. VMPTRLD, | |
540 | * VMXON...) executed by L1. | |
541 | * For example, VM_INSTRUCTION_ERROR is read | |
542 | * by L1 if a vmx instruction fails (part of the error path). | |
543 | * Note the code assumes this logic. If for some reason | |
544 | * we start shadowing these fields then we need to | |
545 | * force a shadow sync when L0 emulates vmx instructions | |
546 | * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified | |
547 | * by nested_vmx_failValid) | |
548 | */ | |
549 | VM_EXIT_REASON, | |
550 | VM_EXIT_INTR_INFO, | |
551 | VM_EXIT_INSTRUCTION_LEN, | |
552 | IDT_VECTORING_INFO_FIELD, | |
553 | IDT_VECTORING_ERROR_CODE, | |
554 | VM_EXIT_INTR_ERROR_CODE, | |
555 | EXIT_QUALIFICATION, | |
556 | GUEST_LINEAR_ADDRESS, | |
557 | GUEST_PHYSICAL_ADDRESS | |
558 | }; | |
fe2b201b | 559 | static int max_shadow_read_only_fields = |
4607c2d7 AG |
560 | ARRAY_SIZE(shadow_read_only_fields); |
561 | ||
fe2b201b | 562 | static unsigned long shadow_read_write_fields[] = { |
a7c0b07d | 563 | TPR_THRESHOLD, |
4607c2d7 AG |
564 | GUEST_RIP, |
565 | GUEST_RSP, | |
566 | GUEST_CR0, | |
567 | GUEST_CR3, | |
568 | GUEST_CR4, | |
569 | GUEST_INTERRUPTIBILITY_INFO, | |
570 | GUEST_RFLAGS, | |
571 | GUEST_CS_SELECTOR, | |
572 | GUEST_CS_AR_BYTES, | |
573 | GUEST_CS_LIMIT, | |
574 | GUEST_CS_BASE, | |
575 | GUEST_ES_BASE, | |
36be0b9d | 576 | GUEST_BNDCFGS, |
4607c2d7 AG |
577 | CR0_GUEST_HOST_MASK, |
578 | CR0_READ_SHADOW, | |
579 | CR4_READ_SHADOW, | |
580 | TSC_OFFSET, | |
581 | EXCEPTION_BITMAP, | |
582 | CPU_BASED_VM_EXEC_CONTROL, | |
583 | VM_ENTRY_EXCEPTION_ERROR_CODE, | |
584 | VM_ENTRY_INTR_INFO_FIELD, | |
585 | VM_ENTRY_INSTRUCTION_LEN, | |
586 | VM_ENTRY_EXCEPTION_ERROR_CODE, | |
587 | HOST_FS_BASE, | |
588 | HOST_GS_BASE, | |
589 | HOST_FS_SELECTOR, | |
590 | HOST_GS_SELECTOR | |
591 | }; | |
fe2b201b | 592 | static int max_shadow_read_write_fields = |
4607c2d7 AG |
593 | ARRAY_SIZE(shadow_read_write_fields); |
594 | ||
772e0318 | 595 | static const unsigned short vmcs_field_to_offset_table[] = { |
22bd0358 NHE |
596 | FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id), |
597 | FIELD(GUEST_ES_SELECTOR, guest_es_selector), | |
598 | FIELD(GUEST_CS_SELECTOR, guest_cs_selector), | |
599 | FIELD(GUEST_SS_SELECTOR, guest_ss_selector), | |
600 | FIELD(GUEST_DS_SELECTOR, guest_ds_selector), | |
601 | FIELD(GUEST_FS_SELECTOR, guest_fs_selector), | |
602 | FIELD(GUEST_GS_SELECTOR, guest_gs_selector), | |
603 | FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector), | |
604 | FIELD(GUEST_TR_SELECTOR, guest_tr_selector), | |
605 | FIELD(HOST_ES_SELECTOR, host_es_selector), | |
606 | FIELD(HOST_CS_SELECTOR, host_cs_selector), | |
607 | FIELD(HOST_SS_SELECTOR, host_ss_selector), | |
608 | FIELD(HOST_DS_SELECTOR, host_ds_selector), | |
609 | FIELD(HOST_FS_SELECTOR, host_fs_selector), | |
610 | FIELD(HOST_GS_SELECTOR, host_gs_selector), | |
611 | FIELD(HOST_TR_SELECTOR, host_tr_selector), | |
612 | FIELD64(IO_BITMAP_A, io_bitmap_a), | |
613 | FIELD64(IO_BITMAP_B, io_bitmap_b), | |
614 | FIELD64(MSR_BITMAP, msr_bitmap), | |
615 | FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr), | |
616 | FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr), | |
617 | FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr), | |
618 | FIELD64(TSC_OFFSET, tsc_offset), | |
619 | FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr), | |
620 | FIELD64(APIC_ACCESS_ADDR, apic_access_addr), | |
621 | FIELD64(EPT_POINTER, ept_pointer), | |
81dc01f7 | 622 | FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap), |
22bd0358 NHE |
623 | FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address), |
624 | FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer), | |
625 | FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl), | |
626 | FIELD64(GUEST_IA32_PAT, guest_ia32_pat), | |
627 | FIELD64(GUEST_IA32_EFER, guest_ia32_efer), | |
628 | FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl), | |
629 | FIELD64(GUEST_PDPTR0, guest_pdptr0), | |
630 | FIELD64(GUEST_PDPTR1, guest_pdptr1), | |
631 | FIELD64(GUEST_PDPTR2, guest_pdptr2), | |
632 | FIELD64(GUEST_PDPTR3, guest_pdptr3), | |
36be0b9d | 633 | FIELD64(GUEST_BNDCFGS, guest_bndcfgs), |
22bd0358 NHE |
634 | FIELD64(HOST_IA32_PAT, host_ia32_pat), |
635 | FIELD64(HOST_IA32_EFER, host_ia32_efer), | |
636 | FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl), | |
637 | FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control), | |
638 | FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control), | |
639 | FIELD(EXCEPTION_BITMAP, exception_bitmap), | |
640 | FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask), | |
641 | FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match), | |
642 | FIELD(CR3_TARGET_COUNT, cr3_target_count), | |
643 | FIELD(VM_EXIT_CONTROLS, vm_exit_controls), | |
644 | FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count), | |
645 | FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count), | |
646 | FIELD(VM_ENTRY_CONTROLS, vm_entry_controls), | |
647 | FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count), | |
648 | FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field), | |
649 | FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code), | |
650 | FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len), | |
651 | FIELD(TPR_THRESHOLD, tpr_threshold), | |
652 | FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control), | |
653 | FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error), | |
654 | FIELD(VM_EXIT_REASON, vm_exit_reason), | |
655 | FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info), | |
656 | FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code), | |
657 | FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field), | |
658 | FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code), | |
659 | FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len), | |
660 | FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info), | |
661 | FIELD(GUEST_ES_LIMIT, guest_es_limit), | |
662 | FIELD(GUEST_CS_LIMIT, guest_cs_limit), | |
663 | FIELD(GUEST_SS_LIMIT, guest_ss_limit), | |
664 | FIELD(GUEST_DS_LIMIT, guest_ds_limit), | |
665 | FIELD(GUEST_FS_LIMIT, guest_fs_limit), | |
666 | FIELD(GUEST_GS_LIMIT, guest_gs_limit), | |
667 | FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit), | |
668 | FIELD(GUEST_TR_LIMIT, guest_tr_limit), | |
669 | FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit), | |
670 | FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit), | |
671 | FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes), | |
672 | FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes), | |
673 | FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes), | |
674 | FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes), | |
675 | FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes), | |
676 | FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes), | |
677 | FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes), | |
678 | FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes), | |
679 | FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info), | |
680 | FIELD(GUEST_ACTIVITY_STATE, guest_activity_state), | |
681 | FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs), | |
682 | FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs), | |
0238ea91 | 683 | FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value), |
22bd0358 NHE |
684 | FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask), |
685 | FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask), | |
686 | FIELD(CR0_READ_SHADOW, cr0_read_shadow), | |
687 | FIELD(CR4_READ_SHADOW, cr4_read_shadow), | |
688 | FIELD(CR3_TARGET_VALUE0, cr3_target_value0), | |
689 | FIELD(CR3_TARGET_VALUE1, cr3_target_value1), | |
690 | FIELD(CR3_TARGET_VALUE2, cr3_target_value2), | |
691 | FIELD(CR3_TARGET_VALUE3, cr3_target_value3), | |
692 | FIELD(EXIT_QUALIFICATION, exit_qualification), | |
693 | FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address), | |
694 | FIELD(GUEST_CR0, guest_cr0), | |
695 | FIELD(GUEST_CR3, guest_cr3), | |
696 | FIELD(GUEST_CR4, guest_cr4), | |
697 | FIELD(GUEST_ES_BASE, guest_es_base), | |
698 | FIELD(GUEST_CS_BASE, guest_cs_base), | |
699 | FIELD(GUEST_SS_BASE, guest_ss_base), | |
700 | FIELD(GUEST_DS_BASE, guest_ds_base), | |
701 | FIELD(GUEST_FS_BASE, guest_fs_base), | |
702 | FIELD(GUEST_GS_BASE, guest_gs_base), | |
703 | FIELD(GUEST_LDTR_BASE, guest_ldtr_base), | |
704 | FIELD(GUEST_TR_BASE, guest_tr_base), | |
705 | FIELD(GUEST_GDTR_BASE, guest_gdtr_base), | |
706 | FIELD(GUEST_IDTR_BASE, guest_idtr_base), | |
707 | FIELD(GUEST_DR7, guest_dr7), | |
708 | FIELD(GUEST_RSP, guest_rsp), | |
709 | FIELD(GUEST_RIP, guest_rip), | |
710 | FIELD(GUEST_RFLAGS, guest_rflags), | |
711 | FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions), | |
712 | FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp), | |
713 | FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip), | |
714 | FIELD(HOST_CR0, host_cr0), | |
715 | FIELD(HOST_CR3, host_cr3), | |
716 | FIELD(HOST_CR4, host_cr4), | |
717 | FIELD(HOST_FS_BASE, host_fs_base), | |
718 | FIELD(HOST_GS_BASE, host_gs_base), | |
719 | FIELD(HOST_TR_BASE, host_tr_base), | |
720 | FIELD(HOST_GDTR_BASE, host_gdtr_base), | |
721 | FIELD(HOST_IDTR_BASE, host_idtr_base), | |
722 | FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp), | |
723 | FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip), | |
724 | FIELD(HOST_RSP, host_rsp), | |
725 | FIELD(HOST_RIP, host_rip), | |
726 | }; | |
22bd0358 NHE |
727 | |
728 | static inline short vmcs_field_to_offset(unsigned long field) | |
729 | { | |
a2ae9df7 PB |
730 | BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX); |
731 | ||
732 | if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) || | |
733 | vmcs_field_to_offset_table[field] == 0) | |
734 | return -ENOENT; | |
735 | ||
22bd0358 NHE |
736 | return vmcs_field_to_offset_table[field]; |
737 | } | |
738 | ||
a9d30f33 NHE |
739 | static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu) |
740 | { | |
741 | return to_vmx(vcpu)->nested.current_vmcs12; | |
742 | } | |
743 | ||
744 | static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr) | |
745 | { | |
746 | struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT); | |
32cad84f | 747 | if (is_error_page(page)) |
a9d30f33 | 748 | return NULL; |
32cad84f | 749 | |
a9d30f33 NHE |
750 | return page; |
751 | } | |
752 | ||
753 | static void nested_release_page(struct page *page) | |
754 | { | |
755 | kvm_release_page_dirty(page); | |
756 | } | |
757 | ||
758 | static void nested_release_page_clean(struct page *page) | |
759 | { | |
760 | kvm_release_page_clean(page); | |
761 | } | |
762 | ||
bfd0a56b | 763 | static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu); |
4e1096d2 | 764 | static u64 construct_eptp(unsigned long root_hpa); |
4610c9cc DX |
765 | static void kvm_cpu_vmxon(u64 addr); |
766 | static void kvm_cpu_vmxoff(void); | |
93c4adc7 | 767 | static bool vmx_mpx_supported(void); |
f53cd63c | 768 | static bool vmx_xsaves_supported(void); |
776e58ea | 769 | static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr); |
b246dd5d OW |
770 | static void vmx_set_segment(struct kvm_vcpu *vcpu, |
771 | struct kvm_segment *var, int seg); | |
772 | static void vmx_get_segment(struct kvm_vcpu *vcpu, | |
773 | struct kvm_segment *var, int seg); | |
d99e4152 GN |
774 | static bool guest_state_valid(struct kvm_vcpu *vcpu); |
775 | static u32 vmx_segment_access_rights(struct kvm_segment *var); | |
a20ed54d | 776 | static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu); |
c3114420 | 777 | static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx); |
16f5b903 | 778 | static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx); |
a255d479 | 779 | static int alloc_identity_pagetable(struct kvm *kvm); |
75880a01 | 780 | |
6aa8b732 AK |
781 | static DEFINE_PER_CPU(struct vmcs *, vmxarea); |
782 | static DEFINE_PER_CPU(struct vmcs *, current_vmcs); | |
d462b819 NHE |
783 | /* |
784 | * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed | |
785 | * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it. | |
786 | */ | |
787 | static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu); | |
3444d7da | 788 | static DEFINE_PER_CPU(struct desc_ptr, host_gdt); |
6aa8b732 | 789 | |
3e7c73e9 AK |
790 | static unsigned long *vmx_io_bitmap_a; |
791 | static unsigned long *vmx_io_bitmap_b; | |
5897297b AK |
792 | static unsigned long *vmx_msr_bitmap_legacy; |
793 | static unsigned long *vmx_msr_bitmap_longmode; | |
8d14695f YZ |
794 | static unsigned long *vmx_msr_bitmap_legacy_x2apic; |
795 | static unsigned long *vmx_msr_bitmap_longmode_x2apic; | |
4607c2d7 AG |
796 | static unsigned long *vmx_vmread_bitmap; |
797 | static unsigned long *vmx_vmwrite_bitmap; | |
fdef3ad1 | 798 | |
110312c8 | 799 | static bool cpu_has_load_ia32_efer; |
8bf00a52 | 800 | static bool cpu_has_load_perf_global_ctrl; |
110312c8 | 801 | |
2384d2b3 SY |
802 | static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS); |
803 | static DEFINE_SPINLOCK(vmx_vpid_lock); | |
804 | ||
1c3d14fe | 805 | static struct vmcs_config { |
6aa8b732 AK |
806 | int size; |
807 | int order; | |
808 | u32 revision_id; | |
1c3d14fe YS |
809 | u32 pin_based_exec_ctrl; |
810 | u32 cpu_based_exec_ctrl; | |
f78e0e2e | 811 | u32 cpu_based_2nd_exec_ctrl; |
1c3d14fe YS |
812 | u32 vmexit_ctrl; |
813 | u32 vmentry_ctrl; | |
814 | } vmcs_config; | |
6aa8b732 | 815 | |
efff9e53 | 816 | static struct vmx_capability { |
d56f546d SY |
817 | u32 ept; |
818 | u32 vpid; | |
819 | } vmx_capability; | |
820 | ||
6aa8b732 AK |
821 | #define VMX_SEGMENT_FIELD(seg) \ |
822 | [VCPU_SREG_##seg] = { \ | |
823 | .selector = GUEST_##seg##_SELECTOR, \ | |
824 | .base = GUEST_##seg##_BASE, \ | |
825 | .limit = GUEST_##seg##_LIMIT, \ | |
826 | .ar_bytes = GUEST_##seg##_AR_BYTES, \ | |
827 | } | |
828 | ||
772e0318 | 829 | static const struct kvm_vmx_segment_field { |
6aa8b732 AK |
830 | unsigned selector; |
831 | unsigned base; | |
832 | unsigned limit; | |
833 | unsigned ar_bytes; | |
834 | } kvm_vmx_segment_fields[] = { | |
835 | VMX_SEGMENT_FIELD(CS), | |
836 | VMX_SEGMENT_FIELD(DS), | |
837 | VMX_SEGMENT_FIELD(ES), | |
838 | VMX_SEGMENT_FIELD(FS), | |
839 | VMX_SEGMENT_FIELD(GS), | |
840 | VMX_SEGMENT_FIELD(SS), | |
841 | VMX_SEGMENT_FIELD(TR), | |
842 | VMX_SEGMENT_FIELD(LDTR), | |
843 | }; | |
844 | ||
26bb0981 AK |
845 | static u64 host_efer; |
846 | ||
6de4f3ad AK |
847 | static void ept_save_pdptrs(struct kvm_vcpu *vcpu); |
848 | ||
4d56c8a7 | 849 | /* |
8c06585d | 850 | * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it |
4d56c8a7 AK |
851 | * away by decrementing the array size. |
852 | */ | |
6aa8b732 | 853 | static const u32 vmx_msr_index[] = { |
05b3e0c2 | 854 | #ifdef CONFIG_X86_64 |
44ea2b17 | 855 | MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, |
6aa8b732 | 856 | #endif |
8c06585d | 857 | MSR_EFER, MSR_TSC_AUX, MSR_STAR, |
6aa8b732 | 858 | }; |
6aa8b732 | 859 | |
31299944 | 860 | static inline bool is_page_fault(u32 intr_info) |
6aa8b732 AK |
861 | { |
862 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
863 | INTR_INFO_VALID_MASK)) == | |
8ab2d2e2 | 864 | (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK); |
6aa8b732 AK |
865 | } |
866 | ||
31299944 | 867 | static inline bool is_no_device(u32 intr_info) |
2ab455cc AL |
868 | { |
869 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
870 | INTR_INFO_VALID_MASK)) == | |
8ab2d2e2 | 871 | (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK); |
2ab455cc AL |
872 | } |
873 | ||
31299944 | 874 | static inline bool is_invalid_opcode(u32 intr_info) |
7aa81cc0 AL |
875 | { |
876 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
877 | INTR_INFO_VALID_MASK)) == | |
8ab2d2e2 | 878 | (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK); |
7aa81cc0 AL |
879 | } |
880 | ||
31299944 | 881 | static inline bool is_external_interrupt(u32 intr_info) |
6aa8b732 AK |
882 | { |
883 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK)) | |
884 | == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK); | |
885 | } | |
886 | ||
31299944 | 887 | static inline bool is_machine_check(u32 intr_info) |
a0861c02 AK |
888 | { |
889 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
890 | INTR_INFO_VALID_MASK)) == | |
891 | (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK); | |
892 | } | |
893 | ||
31299944 | 894 | static inline bool cpu_has_vmx_msr_bitmap(void) |
25c5f225 | 895 | { |
04547156 | 896 | return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS; |
25c5f225 SY |
897 | } |
898 | ||
31299944 | 899 | static inline bool cpu_has_vmx_tpr_shadow(void) |
6e5d865c | 900 | { |
04547156 | 901 | return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW; |
6e5d865c YS |
902 | } |
903 | ||
31299944 | 904 | static inline bool vm_need_tpr_shadow(struct kvm *kvm) |
6e5d865c | 905 | { |
04547156 | 906 | return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm)); |
6e5d865c YS |
907 | } |
908 | ||
31299944 | 909 | static inline bool cpu_has_secondary_exec_ctrls(void) |
f78e0e2e | 910 | { |
04547156 SY |
911 | return vmcs_config.cpu_based_exec_ctrl & |
912 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; | |
f78e0e2e SY |
913 | } |
914 | ||
774ead3a | 915 | static inline bool cpu_has_vmx_virtualize_apic_accesses(void) |
f78e0e2e | 916 | { |
04547156 SY |
917 | return vmcs_config.cpu_based_2nd_exec_ctrl & |
918 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
919 | } | |
920 | ||
8d14695f YZ |
921 | static inline bool cpu_has_vmx_virtualize_x2apic_mode(void) |
922 | { | |
923 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
924 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; | |
925 | } | |
926 | ||
83d4c286 YZ |
927 | static inline bool cpu_has_vmx_apic_register_virt(void) |
928 | { | |
929 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
930 | SECONDARY_EXEC_APIC_REGISTER_VIRT; | |
931 | } | |
932 | ||
c7c9c56c YZ |
933 | static inline bool cpu_has_vmx_virtual_intr_delivery(void) |
934 | { | |
935 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
936 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY; | |
937 | } | |
938 | ||
01e439be YZ |
939 | static inline bool cpu_has_vmx_posted_intr(void) |
940 | { | |
941 | return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR; | |
942 | } | |
943 | ||
944 | static inline bool cpu_has_vmx_apicv(void) | |
945 | { | |
946 | return cpu_has_vmx_apic_register_virt() && | |
947 | cpu_has_vmx_virtual_intr_delivery() && | |
948 | cpu_has_vmx_posted_intr(); | |
949 | } | |
950 | ||
04547156 SY |
951 | static inline bool cpu_has_vmx_flexpriority(void) |
952 | { | |
953 | return cpu_has_vmx_tpr_shadow() && | |
954 | cpu_has_vmx_virtualize_apic_accesses(); | |
f78e0e2e SY |
955 | } |
956 | ||
e799794e MT |
957 | static inline bool cpu_has_vmx_ept_execute_only(void) |
958 | { | |
31299944 | 959 | return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT; |
e799794e MT |
960 | } |
961 | ||
962 | static inline bool cpu_has_vmx_eptp_uncacheable(void) | |
963 | { | |
31299944 | 964 | return vmx_capability.ept & VMX_EPTP_UC_BIT; |
e799794e MT |
965 | } |
966 | ||
967 | static inline bool cpu_has_vmx_eptp_writeback(void) | |
968 | { | |
31299944 | 969 | return vmx_capability.ept & VMX_EPTP_WB_BIT; |
e799794e MT |
970 | } |
971 | ||
972 | static inline bool cpu_has_vmx_ept_2m_page(void) | |
973 | { | |
31299944 | 974 | return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT; |
e799794e MT |
975 | } |
976 | ||
878403b7 SY |
977 | static inline bool cpu_has_vmx_ept_1g_page(void) |
978 | { | |
31299944 | 979 | return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT; |
878403b7 SY |
980 | } |
981 | ||
4bc9b982 SY |
982 | static inline bool cpu_has_vmx_ept_4levels(void) |
983 | { | |
984 | return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT; | |
985 | } | |
986 | ||
83c3a331 XH |
987 | static inline bool cpu_has_vmx_ept_ad_bits(void) |
988 | { | |
989 | return vmx_capability.ept & VMX_EPT_AD_BIT; | |
990 | } | |
991 | ||
31299944 | 992 | static inline bool cpu_has_vmx_invept_context(void) |
d56f546d | 993 | { |
31299944 | 994 | return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT; |
d56f546d SY |
995 | } |
996 | ||
31299944 | 997 | static inline bool cpu_has_vmx_invept_global(void) |
d56f546d | 998 | { |
31299944 | 999 | return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT; |
d56f546d SY |
1000 | } |
1001 | ||
518c8aee GJ |
1002 | static inline bool cpu_has_vmx_invvpid_single(void) |
1003 | { | |
1004 | return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT; | |
1005 | } | |
1006 | ||
b9d762fa GJ |
1007 | static inline bool cpu_has_vmx_invvpid_global(void) |
1008 | { | |
1009 | return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT; | |
1010 | } | |
1011 | ||
31299944 | 1012 | static inline bool cpu_has_vmx_ept(void) |
d56f546d | 1013 | { |
04547156 SY |
1014 | return vmcs_config.cpu_based_2nd_exec_ctrl & |
1015 | SECONDARY_EXEC_ENABLE_EPT; | |
d56f546d SY |
1016 | } |
1017 | ||
31299944 | 1018 | static inline bool cpu_has_vmx_unrestricted_guest(void) |
3a624e29 NK |
1019 | { |
1020 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1021 | SECONDARY_EXEC_UNRESTRICTED_GUEST; | |
1022 | } | |
1023 | ||
31299944 | 1024 | static inline bool cpu_has_vmx_ple(void) |
4b8d54f9 ZE |
1025 | { |
1026 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1027 | SECONDARY_EXEC_PAUSE_LOOP_EXITING; | |
1028 | } | |
1029 | ||
31299944 | 1030 | static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm) |
f78e0e2e | 1031 | { |
6d3e435e | 1032 | return flexpriority_enabled && irqchip_in_kernel(kvm); |
f78e0e2e SY |
1033 | } |
1034 | ||
31299944 | 1035 | static inline bool cpu_has_vmx_vpid(void) |
2384d2b3 | 1036 | { |
04547156 SY |
1037 | return vmcs_config.cpu_based_2nd_exec_ctrl & |
1038 | SECONDARY_EXEC_ENABLE_VPID; | |
2384d2b3 SY |
1039 | } |
1040 | ||
31299944 | 1041 | static inline bool cpu_has_vmx_rdtscp(void) |
4e47c7a6 SY |
1042 | { |
1043 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1044 | SECONDARY_EXEC_RDTSCP; | |
1045 | } | |
1046 | ||
ad756a16 MJ |
1047 | static inline bool cpu_has_vmx_invpcid(void) |
1048 | { | |
1049 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1050 | SECONDARY_EXEC_ENABLE_INVPCID; | |
1051 | } | |
1052 | ||
31299944 | 1053 | static inline bool cpu_has_virtual_nmis(void) |
f08864b4 SY |
1054 | { |
1055 | return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS; | |
1056 | } | |
1057 | ||
f5f48ee1 SY |
1058 | static inline bool cpu_has_vmx_wbinvd_exit(void) |
1059 | { | |
1060 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1061 | SECONDARY_EXEC_WBINVD_EXITING; | |
1062 | } | |
1063 | ||
abc4fc58 AG |
1064 | static inline bool cpu_has_vmx_shadow_vmcs(void) |
1065 | { | |
1066 | u64 vmx_msr; | |
1067 | rdmsrl(MSR_IA32_VMX_MISC, vmx_msr); | |
1068 | /* check if the cpu supports writing r/o exit information fields */ | |
1069 | if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS)) | |
1070 | return false; | |
1071 | ||
1072 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
1073 | SECONDARY_EXEC_SHADOW_VMCS; | |
1074 | } | |
1075 | ||
04547156 SY |
1076 | static inline bool report_flexpriority(void) |
1077 | { | |
1078 | return flexpriority_enabled; | |
1079 | } | |
1080 | ||
fe3ef05c NHE |
1081 | static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit) |
1082 | { | |
1083 | return vmcs12->cpu_based_vm_exec_control & bit; | |
1084 | } | |
1085 | ||
1086 | static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit) | |
1087 | { | |
1088 | return (vmcs12->cpu_based_vm_exec_control & | |
1089 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) && | |
1090 | (vmcs12->secondary_vm_exec_control & bit); | |
1091 | } | |
1092 | ||
f5c4368f | 1093 | static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12) |
644d711a NHE |
1094 | { |
1095 | return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS; | |
1096 | } | |
1097 | ||
f4124500 JK |
1098 | static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12) |
1099 | { | |
1100 | return vmcs12->pin_based_vm_exec_control & | |
1101 | PIN_BASED_VMX_PREEMPTION_TIMER; | |
1102 | } | |
1103 | ||
155a97a3 NHE |
1104 | static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12) |
1105 | { | |
1106 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT); | |
1107 | } | |
1108 | ||
81dc01f7 WL |
1109 | static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12) |
1110 | { | |
1111 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) && | |
1112 | vmx_xsaves_supported(); | |
1113 | } | |
1114 | ||
644d711a NHE |
1115 | static inline bool is_exception(u32 intr_info) |
1116 | { | |
1117 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK)) | |
1118 | == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK); | |
1119 | } | |
1120 | ||
533558bc JK |
1121 | static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason, |
1122 | u32 exit_intr_info, | |
1123 | unsigned long exit_qualification); | |
7c177938 NHE |
1124 | static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu, |
1125 | struct vmcs12 *vmcs12, | |
1126 | u32 reason, unsigned long qualification); | |
1127 | ||
8b9cf98c | 1128 | static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr) |
7725f0ba AK |
1129 | { |
1130 | int i; | |
1131 | ||
a2fa3e9f | 1132 | for (i = 0; i < vmx->nmsrs; ++i) |
26bb0981 | 1133 | if (vmx_msr_index[vmx->guest_msrs[i].index] == msr) |
a75beee6 ED |
1134 | return i; |
1135 | return -1; | |
1136 | } | |
1137 | ||
2384d2b3 SY |
1138 | static inline void __invvpid(int ext, u16 vpid, gva_t gva) |
1139 | { | |
1140 | struct { | |
1141 | u64 vpid : 16; | |
1142 | u64 rsvd : 48; | |
1143 | u64 gva; | |
1144 | } operand = { vpid, 0, gva }; | |
1145 | ||
4ecac3fd | 1146 | asm volatile (__ex(ASM_VMX_INVVPID) |
2384d2b3 SY |
1147 | /* CF==1 or ZF==1 --> rc = -1 */ |
1148 | "; ja 1f ; ud2 ; 1:" | |
1149 | : : "a"(&operand), "c"(ext) : "cc", "memory"); | |
1150 | } | |
1151 | ||
1439442c SY |
1152 | static inline void __invept(int ext, u64 eptp, gpa_t gpa) |
1153 | { | |
1154 | struct { | |
1155 | u64 eptp, gpa; | |
1156 | } operand = {eptp, gpa}; | |
1157 | ||
4ecac3fd | 1158 | asm volatile (__ex(ASM_VMX_INVEPT) |
1439442c SY |
1159 | /* CF==1 or ZF==1 --> rc = -1 */ |
1160 | "; ja 1f ; ud2 ; 1:\n" | |
1161 | : : "a" (&operand), "c" (ext) : "cc", "memory"); | |
1162 | } | |
1163 | ||
26bb0981 | 1164 | static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr) |
a75beee6 ED |
1165 | { |
1166 | int i; | |
1167 | ||
8b9cf98c | 1168 | i = __find_msr_index(vmx, msr); |
a75beee6 | 1169 | if (i >= 0) |
a2fa3e9f | 1170 | return &vmx->guest_msrs[i]; |
8b6d44c7 | 1171 | return NULL; |
7725f0ba AK |
1172 | } |
1173 | ||
6aa8b732 AK |
1174 | static void vmcs_clear(struct vmcs *vmcs) |
1175 | { | |
1176 | u64 phys_addr = __pa(vmcs); | |
1177 | u8 error; | |
1178 | ||
4ecac3fd | 1179 | asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0" |
16d8f72f | 1180 | : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr) |
6aa8b732 AK |
1181 | : "cc", "memory"); |
1182 | if (error) | |
1183 | printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n", | |
1184 | vmcs, phys_addr); | |
1185 | } | |
1186 | ||
d462b819 NHE |
1187 | static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs) |
1188 | { | |
1189 | vmcs_clear(loaded_vmcs->vmcs); | |
1190 | loaded_vmcs->cpu = -1; | |
1191 | loaded_vmcs->launched = 0; | |
1192 | } | |
1193 | ||
7725b894 DX |
1194 | static void vmcs_load(struct vmcs *vmcs) |
1195 | { | |
1196 | u64 phys_addr = __pa(vmcs); | |
1197 | u8 error; | |
1198 | ||
1199 | asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0" | |
16d8f72f | 1200 | : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr) |
7725b894 DX |
1201 | : "cc", "memory"); |
1202 | if (error) | |
2844d849 | 1203 | printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n", |
7725b894 DX |
1204 | vmcs, phys_addr); |
1205 | } | |
1206 | ||
8f536b76 ZY |
1207 | #ifdef CONFIG_KEXEC |
1208 | /* | |
1209 | * This bitmap is used to indicate whether the vmclear | |
1210 | * operation is enabled on all cpus. All disabled by | |
1211 | * default. | |
1212 | */ | |
1213 | static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE; | |
1214 | ||
1215 | static inline void crash_enable_local_vmclear(int cpu) | |
1216 | { | |
1217 | cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap); | |
1218 | } | |
1219 | ||
1220 | static inline void crash_disable_local_vmclear(int cpu) | |
1221 | { | |
1222 | cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap); | |
1223 | } | |
1224 | ||
1225 | static inline int crash_local_vmclear_enabled(int cpu) | |
1226 | { | |
1227 | return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap); | |
1228 | } | |
1229 | ||
1230 | static void crash_vmclear_local_loaded_vmcss(void) | |
1231 | { | |
1232 | int cpu = raw_smp_processor_id(); | |
1233 | struct loaded_vmcs *v; | |
1234 | ||
1235 | if (!crash_local_vmclear_enabled(cpu)) | |
1236 | return; | |
1237 | ||
1238 | list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu), | |
1239 | loaded_vmcss_on_cpu_link) | |
1240 | vmcs_clear(v->vmcs); | |
1241 | } | |
1242 | #else | |
1243 | static inline void crash_enable_local_vmclear(int cpu) { } | |
1244 | static inline void crash_disable_local_vmclear(int cpu) { } | |
1245 | #endif /* CONFIG_KEXEC */ | |
1246 | ||
d462b819 | 1247 | static void __loaded_vmcs_clear(void *arg) |
6aa8b732 | 1248 | { |
d462b819 | 1249 | struct loaded_vmcs *loaded_vmcs = arg; |
d3b2c338 | 1250 | int cpu = raw_smp_processor_id(); |
6aa8b732 | 1251 | |
d462b819 NHE |
1252 | if (loaded_vmcs->cpu != cpu) |
1253 | return; /* vcpu migration can race with cpu offline */ | |
1254 | if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs) | |
6aa8b732 | 1255 | per_cpu(current_vmcs, cpu) = NULL; |
8f536b76 | 1256 | crash_disable_local_vmclear(cpu); |
d462b819 | 1257 | list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link); |
5a560f8b XG |
1258 | |
1259 | /* | |
1260 | * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link | |
1261 | * is before setting loaded_vmcs->vcpu to -1 which is done in | |
1262 | * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist | |
1263 | * then adds the vmcs into percpu list before it is deleted. | |
1264 | */ | |
1265 | smp_wmb(); | |
1266 | ||
d462b819 | 1267 | loaded_vmcs_init(loaded_vmcs); |
8f536b76 | 1268 | crash_enable_local_vmclear(cpu); |
6aa8b732 AK |
1269 | } |
1270 | ||
d462b819 | 1271 | static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs) |
8d0be2b3 | 1272 | { |
e6c7d321 XG |
1273 | int cpu = loaded_vmcs->cpu; |
1274 | ||
1275 | if (cpu != -1) | |
1276 | smp_call_function_single(cpu, | |
1277 | __loaded_vmcs_clear, loaded_vmcs, 1); | |
8d0be2b3 AK |
1278 | } |
1279 | ||
1760dd49 | 1280 | static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx) |
2384d2b3 SY |
1281 | { |
1282 | if (vmx->vpid == 0) | |
1283 | return; | |
1284 | ||
518c8aee GJ |
1285 | if (cpu_has_vmx_invvpid_single()) |
1286 | __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0); | |
2384d2b3 SY |
1287 | } |
1288 | ||
b9d762fa GJ |
1289 | static inline void vpid_sync_vcpu_global(void) |
1290 | { | |
1291 | if (cpu_has_vmx_invvpid_global()) | |
1292 | __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0); | |
1293 | } | |
1294 | ||
1295 | static inline void vpid_sync_context(struct vcpu_vmx *vmx) | |
1296 | { | |
1297 | if (cpu_has_vmx_invvpid_single()) | |
1760dd49 | 1298 | vpid_sync_vcpu_single(vmx); |
b9d762fa GJ |
1299 | else |
1300 | vpid_sync_vcpu_global(); | |
1301 | } | |
1302 | ||
1439442c SY |
1303 | static inline void ept_sync_global(void) |
1304 | { | |
1305 | if (cpu_has_vmx_invept_global()) | |
1306 | __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0); | |
1307 | } | |
1308 | ||
1309 | static inline void ept_sync_context(u64 eptp) | |
1310 | { | |
089d034e | 1311 | if (enable_ept) { |
1439442c SY |
1312 | if (cpu_has_vmx_invept_context()) |
1313 | __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0); | |
1314 | else | |
1315 | ept_sync_global(); | |
1316 | } | |
1317 | } | |
1318 | ||
96304217 | 1319 | static __always_inline unsigned long vmcs_readl(unsigned long field) |
6aa8b732 | 1320 | { |
5e520e62 | 1321 | unsigned long value; |
6aa8b732 | 1322 | |
5e520e62 AK |
1323 | asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0") |
1324 | : "=a"(value) : "d"(field) : "cc"); | |
6aa8b732 AK |
1325 | return value; |
1326 | } | |
1327 | ||
96304217 | 1328 | static __always_inline u16 vmcs_read16(unsigned long field) |
6aa8b732 AK |
1329 | { |
1330 | return vmcs_readl(field); | |
1331 | } | |
1332 | ||
96304217 | 1333 | static __always_inline u32 vmcs_read32(unsigned long field) |
6aa8b732 AK |
1334 | { |
1335 | return vmcs_readl(field); | |
1336 | } | |
1337 | ||
96304217 | 1338 | static __always_inline u64 vmcs_read64(unsigned long field) |
6aa8b732 | 1339 | { |
05b3e0c2 | 1340 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
1341 | return vmcs_readl(field); |
1342 | #else | |
1343 | return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32); | |
1344 | #endif | |
1345 | } | |
1346 | ||
e52de1b8 AK |
1347 | static noinline void vmwrite_error(unsigned long field, unsigned long value) |
1348 | { | |
1349 | printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n", | |
1350 | field, value, vmcs_read32(VM_INSTRUCTION_ERROR)); | |
1351 | dump_stack(); | |
1352 | } | |
1353 | ||
6aa8b732 AK |
1354 | static void vmcs_writel(unsigned long field, unsigned long value) |
1355 | { | |
1356 | u8 error; | |
1357 | ||
4ecac3fd | 1358 | asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0" |
d77c26fc | 1359 | : "=q"(error) : "a"(value), "d"(field) : "cc"); |
e52de1b8 AK |
1360 | if (unlikely(error)) |
1361 | vmwrite_error(field, value); | |
6aa8b732 AK |
1362 | } |
1363 | ||
1364 | static void vmcs_write16(unsigned long field, u16 value) | |
1365 | { | |
1366 | vmcs_writel(field, value); | |
1367 | } | |
1368 | ||
1369 | static void vmcs_write32(unsigned long field, u32 value) | |
1370 | { | |
1371 | vmcs_writel(field, value); | |
1372 | } | |
1373 | ||
1374 | static void vmcs_write64(unsigned long field, u64 value) | |
1375 | { | |
6aa8b732 | 1376 | vmcs_writel(field, value); |
7682f2d0 | 1377 | #ifndef CONFIG_X86_64 |
6aa8b732 AK |
1378 | asm volatile (""); |
1379 | vmcs_writel(field+1, value >> 32); | |
1380 | #endif | |
1381 | } | |
1382 | ||
2ab455cc AL |
1383 | static void vmcs_clear_bits(unsigned long field, u32 mask) |
1384 | { | |
1385 | vmcs_writel(field, vmcs_readl(field) & ~mask); | |
1386 | } | |
1387 | ||
1388 | static void vmcs_set_bits(unsigned long field, u32 mask) | |
1389 | { | |
1390 | vmcs_writel(field, vmcs_readl(field) | mask); | |
1391 | } | |
1392 | ||
2961e876 GN |
1393 | static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val) |
1394 | { | |
1395 | vmcs_write32(VM_ENTRY_CONTROLS, val); | |
1396 | vmx->vm_entry_controls_shadow = val; | |
1397 | } | |
1398 | ||
1399 | static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val) | |
1400 | { | |
1401 | if (vmx->vm_entry_controls_shadow != val) | |
1402 | vm_entry_controls_init(vmx, val); | |
1403 | } | |
1404 | ||
1405 | static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx) | |
1406 | { | |
1407 | return vmx->vm_entry_controls_shadow; | |
1408 | } | |
1409 | ||
1410 | ||
1411 | static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val) | |
1412 | { | |
1413 | vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val); | |
1414 | } | |
1415 | ||
1416 | static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val) | |
1417 | { | |
1418 | vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val); | |
1419 | } | |
1420 | ||
1421 | static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val) | |
1422 | { | |
1423 | vmcs_write32(VM_EXIT_CONTROLS, val); | |
1424 | vmx->vm_exit_controls_shadow = val; | |
1425 | } | |
1426 | ||
1427 | static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val) | |
1428 | { | |
1429 | if (vmx->vm_exit_controls_shadow != val) | |
1430 | vm_exit_controls_init(vmx, val); | |
1431 | } | |
1432 | ||
1433 | static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx) | |
1434 | { | |
1435 | return vmx->vm_exit_controls_shadow; | |
1436 | } | |
1437 | ||
1438 | ||
1439 | static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val) | |
1440 | { | |
1441 | vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val); | |
1442 | } | |
1443 | ||
1444 | static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val) | |
1445 | { | |
1446 | vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val); | |
1447 | } | |
1448 | ||
2fb92db1 AK |
1449 | static void vmx_segment_cache_clear(struct vcpu_vmx *vmx) |
1450 | { | |
1451 | vmx->segment_cache.bitmask = 0; | |
1452 | } | |
1453 | ||
1454 | static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg, | |
1455 | unsigned field) | |
1456 | { | |
1457 | bool ret; | |
1458 | u32 mask = 1 << (seg * SEG_FIELD_NR + field); | |
1459 | ||
1460 | if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) { | |
1461 | vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS); | |
1462 | vmx->segment_cache.bitmask = 0; | |
1463 | } | |
1464 | ret = vmx->segment_cache.bitmask & mask; | |
1465 | vmx->segment_cache.bitmask |= mask; | |
1466 | return ret; | |
1467 | } | |
1468 | ||
1469 | static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg) | |
1470 | { | |
1471 | u16 *p = &vmx->segment_cache.seg[seg].selector; | |
1472 | ||
1473 | if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL)) | |
1474 | *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector); | |
1475 | return *p; | |
1476 | } | |
1477 | ||
1478 | static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg) | |
1479 | { | |
1480 | ulong *p = &vmx->segment_cache.seg[seg].base; | |
1481 | ||
1482 | if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE)) | |
1483 | *p = vmcs_readl(kvm_vmx_segment_fields[seg].base); | |
1484 | return *p; | |
1485 | } | |
1486 | ||
1487 | static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg) | |
1488 | { | |
1489 | u32 *p = &vmx->segment_cache.seg[seg].limit; | |
1490 | ||
1491 | if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT)) | |
1492 | *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit); | |
1493 | return *p; | |
1494 | } | |
1495 | ||
1496 | static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg) | |
1497 | { | |
1498 | u32 *p = &vmx->segment_cache.seg[seg].ar; | |
1499 | ||
1500 | if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR)) | |
1501 | *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes); | |
1502 | return *p; | |
1503 | } | |
1504 | ||
abd3f2d6 AK |
1505 | static void update_exception_bitmap(struct kvm_vcpu *vcpu) |
1506 | { | |
1507 | u32 eb; | |
1508 | ||
fd7373cc JK |
1509 | eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) | |
1510 | (1u << NM_VECTOR) | (1u << DB_VECTOR); | |
1511 | if ((vcpu->guest_debug & | |
1512 | (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) == | |
1513 | (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) | |
1514 | eb |= 1u << BP_VECTOR; | |
7ffd92c5 | 1515 | if (to_vmx(vcpu)->rmode.vm86_active) |
abd3f2d6 | 1516 | eb = ~0; |
089d034e | 1517 | if (enable_ept) |
1439442c | 1518 | eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */ |
02daab21 AK |
1519 | if (vcpu->fpu_active) |
1520 | eb &= ~(1u << NM_VECTOR); | |
36cf24e0 NHE |
1521 | |
1522 | /* When we are running a nested L2 guest and L1 specified for it a | |
1523 | * certain exception bitmap, we must trap the same exceptions and pass | |
1524 | * them to L1. When running L2, we will only handle the exceptions | |
1525 | * specified above if L1 did not want them. | |
1526 | */ | |
1527 | if (is_guest_mode(vcpu)) | |
1528 | eb |= get_vmcs12(vcpu)->exception_bitmap; | |
1529 | ||
abd3f2d6 AK |
1530 | vmcs_write32(EXCEPTION_BITMAP, eb); |
1531 | } | |
1532 | ||
2961e876 GN |
1533 | static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx, |
1534 | unsigned long entry, unsigned long exit) | |
8bf00a52 | 1535 | { |
2961e876 GN |
1536 | vm_entry_controls_clearbit(vmx, entry); |
1537 | vm_exit_controls_clearbit(vmx, exit); | |
8bf00a52 GN |
1538 | } |
1539 | ||
61d2ef2c AK |
1540 | static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr) |
1541 | { | |
1542 | unsigned i; | |
1543 | struct msr_autoload *m = &vmx->msr_autoload; | |
1544 | ||
8bf00a52 GN |
1545 | switch (msr) { |
1546 | case MSR_EFER: | |
1547 | if (cpu_has_load_ia32_efer) { | |
2961e876 GN |
1548 | clear_atomic_switch_msr_special(vmx, |
1549 | VM_ENTRY_LOAD_IA32_EFER, | |
8bf00a52 GN |
1550 | VM_EXIT_LOAD_IA32_EFER); |
1551 | return; | |
1552 | } | |
1553 | break; | |
1554 | case MSR_CORE_PERF_GLOBAL_CTRL: | |
1555 | if (cpu_has_load_perf_global_ctrl) { | |
2961e876 | 1556 | clear_atomic_switch_msr_special(vmx, |
8bf00a52 GN |
1557 | VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, |
1558 | VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL); | |
1559 | return; | |
1560 | } | |
1561 | break; | |
110312c8 AK |
1562 | } |
1563 | ||
61d2ef2c AK |
1564 | for (i = 0; i < m->nr; ++i) |
1565 | if (m->guest[i].index == msr) | |
1566 | break; | |
1567 | ||
1568 | if (i == m->nr) | |
1569 | return; | |
1570 | --m->nr; | |
1571 | m->guest[i] = m->guest[m->nr]; | |
1572 | m->host[i] = m->host[m->nr]; | |
1573 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr); | |
1574 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr); | |
1575 | } | |
1576 | ||
2961e876 GN |
1577 | static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx, |
1578 | unsigned long entry, unsigned long exit, | |
1579 | unsigned long guest_val_vmcs, unsigned long host_val_vmcs, | |
1580 | u64 guest_val, u64 host_val) | |
8bf00a52 GN |
1581 | { |
1582 | vmcs_write64(guest_val_vmcs, guest_val); | |
1583 | vmcs_write64(host_val_vmcs, host_val); | |
2961e876 GN |
1584 | vm_entry_controls_setbit(vmx, entry); |
1585 | vm_exit_controls_setbit(vmx, exit); | |
8bf00a52 GN |
1586 | } |
1587 | ||
61d2ef2c AK |
1588 | static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr, |
1589 | u64 guest_val, u64 host_val) | |
1590 | { | |
1591 | unsigned i; | |
1592 | struct msr_autoload *m = &vmx->msr_autoload; | |
1593 | ||
8bf00a52 GN |
1594 | switch (msr) { |
1595 | case MSR_EFER: | |
1596 | if (cpu_has_load_ia32_efer) { | |
2961e876 GN |
1597 | add_atomic_switch_msr_special(vmx, |
1598 | VM_ENTRY_LOAD_IA32_EFER, | |
8bf00a52 GN |
1599 | VM_EXIT_LOAD_IA32_EFER, |
1600 | GUEST_IA32_EFER, | |
1601 | HOST_IA32_EFER, | |
1602 | guest_val, host_val); | |
1603 | return; | |
1604 | } | |
1605 | break; | |
1606 | case MSR_CORE_PERF_GLOBAL_CTRL: | |
1607 | if (cpu_has_load_perf_global_ctrl) { | |
2961e876 | 1608 | add_atomic_switch_msr_special(vmx, |
8bf00a52 GN |
1609 | VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, |
1610 | VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, | |
1611 | GUEST_IA32_PERF_GLOBAL_CTRL, | |
1612 | HOST_IA32_PERF_GLOBAL_CTRL, | |
1613 | guest_val, host_val); | |
1614 | return; | |
1615 | } | |
1616 | break; | |
110312c8 AK |
1617 | } |
1618 | ||
61d2ef2c AK |
1619 | for (i = 0; i < m->nr; ++i) |
1620 | if (m->guest[i].index == msr) | |
1621 | break; | |
1622 | ||
e7fc6f93 | 1623 | if (i == NR_AUTOLOAD_MSRS) { |
60266204 | 1624 | printk_once(KERN_WARNING "Not enough msr switch entries. " |
e7fc6f93 GN |
1625 | "Can't add msr %x\n", msr); |
1626 | return; | |
1627 | } else if (i == m->nr) { | |
61d2ef2c AK |
1628 | ++m->nr; |
1629 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr); | |
1630 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr); | |
1631 | } | |
1632 | ||
1633 | m->guest[i].index = msr; | |
1634 | m->guest[i].value = guest_val; | |
1635 | m->host[i].index = msr; | |
1636 | m->host[i].value = host_val; | |
1637 | } | |
1638 | ||
33ed6329 AK |
1639 | static void reload_tss(void) |
1640 | { | |
33ed6329 AK |
1641 | /* |
1642 | * VT restores TR but not its size. Useless. | |
1643 | */ | |
89cbc767 | 1644 | struct desc_ptr *gdt = this_cpu_ptr(&host_gdt); |
a5f61300 | 1645 | struct desc_struct *descs; |
33ed6329 | 1646 | |
d359192f | 1647 | descs = (void *)gdt->address; |
33ed6329 AK |
1648 | descs[GDT_ENTRY_TSS].type = 9; /* available TSS */ |
1649 | load_TR_desc(); | |
33ed6329 AK |
1650 | } |
1651 | ||
92c0d900 | 1652 | static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset) |
2cc51560 | 1653 | { |
3a34a881 | 1654 | u64 guest_efer; |
51c6cf66 AK |
1655 | u64 ignore_bits; |
1656 | ||
f6801dff | 1657 | guest_efer = vmx->vcpu.arch.efer; |
3a34a881 | 1658 | |
51c6cf66 | 1659 | /* |
0fa06071 | 1660 | * NX is emulated; LMA and LME handled by hardware; SCE meaningless |
51c6cf66 AK |
1661 | * outside long mode |
1662 | */ | |
1663 | ignore_bits = EFER_NX | EFER_SCE; | |
1664 | #ifdef CONFIG_X86_64 | |
1665 | ignore_bits |= EFER_LMA | EFER_LME; | |
1666 | /* SCE is meaningful only in long mode on Intel */ | |
1667 | if (guest_efer & EFER_LMA) | |
1668 | ignore_bits &= ~(u64)EFER_SCE; | |
1669 | #endif | |
51c6cf66 AK |
1670 | guest_efer &= ~ignore_bits; |
1671 | guest_efer |= host_efer & ignore_bits; | |
26bb0981 | 1672 | vmx->guest_msrs[efer_offset].data = guest_efer; |
d5696725 | 1673 | vmx->guest_msrs[efer_offset].mask = ~ignore_bits; |
84ad33ef AK |
1674 | |
1675 | clear_atomic_switch_msr(vmx, MSR_EFER); | |
f6577a5f AL |
1676 | |
1677 | /* | |
1678 | * On EPT, we can't emulate NX, so we must switch EFER atomically. | |
1679 | * On CPUs that support "load IA32_EFER", always switch EFER | |
1680 | * atomically, since it's faster than switching it manually. | |
1681 | */ | |
1682 | if (cpu_has_load_ia32_efer || | |
1683 | (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) { | |
84ad33ef AK |
1684 | guest_efer = vmx->vcpu.arch.efer; |
1685 | if (!(guest_efer & EFER_LMA)) | |
1686 | guest_efer &= ~EFER_LME; | |
54b98bff AL |
1687 | if (guest_efer != host_efer) |
1688 | add_atomic_switch_msr(vmx, MSR_EFER, | |
1689 | guest_efer, host_efer); | |
84ad33ef AK |
1690 | return false; |
1691 | } | |
1692 | ||
26bb0981 | 1693 | return true; |
51c6cf66 AK |
1694 | } |
1695 | ||
2d49ec72 GN |
1696 | static unsigned long segment_base(u16 selector) |
1697 | { | |
89cbc767 | 1698 | struct desc_ptr *gdt = this_cpu_ptr(&host_gdt); |
2d49ec72 GN |
1699 | struct desc_struct *d; |
1700 | unsigned long table_base; | |
1701 | unsigned long v; | |
1702 | ||
1703 | if (!(selector & ~3)) | |
1704 | return 0; | |
1705 | ||
d359192f | 1706 | table_base = gdt->address; |
2d49ec72 GN |
1707 | |
1708 | if (selector & 4) { /* from ldt */ | |
1709 | u16 ldt_selector = kvm_read_ldt(); | |
1710 | ||
1711 | if (!(ldt_selector & ~3)) | |
1712 | return 0; | |
1713 | ||
1714 | table_base = segment_base(ldt_selector); | |
1715 | } | |
1716 | d = (struct desc_struct *)(table_base + (selector & ~7)); | |
1717 | v = get_desc_base(d); | |
1718 | #ifdef CONFIG_X86_64 | |
1719 | if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11)) | |
1720 | v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32; | |
1721 | #endif | |
1722 | return v; | |
1723 | } | |
1724 | ||
1725 | static inline unsigned long kvm_read_tr_base(void) | |
1726 | { | |
1727 | u16 tr; | |
1728 | asm("str %0" : "=g"(tr)); | |
1729 | return segment_base(tr); | |
1730 | } | |
1731 | ||
04d2cc77 | 1732 | static void vmx_save_host_state(struct kvm_vcpu *vcpu) |
33ed6329 | 1733 | { |
04d2cc77 | 1734 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
26bb0981 | 1735 | int i; |
04d2cc77 | 1736 | |
a2fa3e9f | 1737 | if (vmx->host_state.loaded) |
33ed6329 AK |
1738 | return; |
1739 | ||
a2fa3e9f | 1740 | vmx->host_state.loaded = 1; |
33ed6329 AK |
1741 | /* |
1742 | * Set host fs and gs selectors. Unfortunately, 22.2.3 does not | |
1743 | * allow segment selectors with cpl > 0 or ti == 1. | |
1744 | */ | |
d6e88aec | 1745 | vmx->host_state.ldt_sel = kvm_read_ldt(); |
152d3f2f | 1746 | vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel; |
9581d442 | 1747 | savesegment(fs, vmx->host_state.fs_sel); |
152d3f2f | 1748 | if (!(vmx->host_state.fs_sel & 7)) { |
a2fa3e9f | 1749 | vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel); |
152d3f2f LV |
1750 | vmx->host_state.fs_reload_needed = 0; |
1751 | } else { | |
33ed6329 | 1752 | vmcs_write16(HOST_FS_SELECTOR, 0); |
152d3f2f | 1753 | vmx->host_state.fs_reload_needed = 1; |
33ed6329 | 1754 | } |
9581d442 | 1755 | savesegment(gs, vmx->host_state.gs_sel); |
a2fa3e9f GH |
1756 | if (!(vmx->host_state.gs_sel & 7)) |
1757 | vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel); | |
33ed6329 AK |
1758 | else { |
1759 | vmcs_write16(HOST_GS_SELECTOR, 0); | |
152d3f2f | 1760 | vmx->host_state.gs_ldt_reload_needed = 1; |
33ed6329 AK |
1761 | } |
1762 | ||
b2da15ac AK |
1763 | #ifdef CONFIG_X86_64 |
1764 | savesegment(ds, vmx->host_state.ds_sel); | |
1765 | savesegment(es, vmx->host_state.es_sel); | |
1766 | #endif | |
1767 | ||
33ed6329 AK |
1768 | #ifdef CONFIG_X86_64 |
1769 | vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE)); | |
1770 | vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE)); | |
1771 | #else | |
a2fa3e9f GH |
1772 | vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel)); |
1773 | vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel)); | |
33ed6329 | 1774 | #endif |
707c0874 AK |
1775 | |
1776 | #ifdef CONFIG_X86_64 | |
c8770e7b AK |
1777 | rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base); |
1778 | if (is_long_mode(&vmx->vcpu)) | |
44ea2b17 | 1779 | wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); |
707c0874 | 1780 | #endif |
da8999d3 LJ |
1781 | if (boot_cpu_has(X86_FEATURE_MPX)) |
1782 | rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs); | |
26bb0981 AK |
1783 | for (i = 0; i < vmx->save_nmsrs; ++i) |
1784 | kvm_set_shared_msr(vmx->guest_msrs[i].index, | |
d5696725 AK |
1785 | vmx->guest_msrs[i].data, |
1786 | vmx->guest_msrs[i].mask); | |
33ed6329 AK |
1787 | } |
1788 | ||
a9b21b62 | 1789 | static void __vmx_load_host_state(struct vcpu_vmx *vmx) |
33ed6329 | 1790 | { |
a2fa3e9f | 1791 | if (!vmx->host_state.loaded) |
33ed6329 AK |
1792 | return; |
1793 | ||
e1beb1d3 | 1794 | ++vmx->vcpu.stat.host_state_reload; |
a2fa3e9f | 1795 | vmx->host_state.loaded = 0; |
c8770e7b AK |
1796 | #ifdef CONFIG_X86_64 |
1797 | if (is_long_mode(&vmx->vcpu)) | |
1798 | rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); | |
1799 | #endif | |
152d3f2f | 1800 | if (vmx->host_state.gs_ldt_reload_needed) { |
d6e88aec | 1801 | kvm_load_ldt(vmx->host_state.ldt_sel); |
33ed6329 | 1802 | #ifdef CONFIG_X86_64 |
9581d442 | 1803 | load_gs_index(vmx->host_state.gs_sel); |
9581d442 AK |
1804 | #else |
1805 | loadsegment(gs, vmx->host_state.gs_sel); | |
33ed6329 | 1806 | #endif |
33ed6329 | 1807 | } |
0a77fe4c AK |
1808 | if (vmx->host_state.fs_reload_needed) |
1809 | loadsegment(fs, vmx->host_state.fs_sel); | |
b2da15ac AK |
1810 | #ifdef CONFIG_X86_64 |
1811 | if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) { | |
1812 | loadsegment(ds, vmx->host_state.ds_sel); | |
1813 | loadsegment(es, vmx->host_state.es_sel); | |
1814 | } | |
b2da15ac | 1815 | #endif |
152d3f2f | 1816 | reload_tss(); |
44ea2b17 | 1817 | #ifdef CONFIG_X86_64 |
c8770e7b | 1818 | wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base); |
44ea2b17 | 1819 | #endif |
da8999d3 LJ |
1820 | if (vmx->host_state.msr_host_bndcfgs) |
1821 | wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs); | |
b1a74bf8 SS |
1822 | /* |
1823 | * If the FPU is not active (through the host task or | |
1824 | * the guest vcpu), then restore the cr0.TS bit. | |
1825 | */ | |
1826 | if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded) | |
1827 | stts(); | |
89cbc767 | 1828 | load_gdt(this_cpu_ptr(&host_gdt)); |
33ed6329 AK |
1829 | } |
1830 | ||
a9b21b62 AK |
1831 | static void vmx_load_host_state(struct vcpu_vmx *vmx) |
1832 | { | |
1833 | preempt_disable(); | |
1834 | __vmx_load_host_state(vmx); | |
1835 | preempt_enable(); | |
1836 | } | |
1837 | ||
6aa8b732 AK |
1838 | /* |
1839 | * Switches to specified vcpu, until a matching vcpu_put(), but assumes | |
1840 | * vcpu mutex is already taken. | |
1841 | */ | |
15ad7146 | 1842 | static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 1843 | { |
a2fa3e9f | 1844 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
4610c9cc | 1845 | u64 phys_addr = __pa(per_cpu(vmxarea, cpu)); |
6aa8b732 | 1846 | |
4610c9cc DX |
1847 | if (!vmm_exclusive) |
1848 | kvm_cpu_vmxon(phys_addr); | |
d462b819 NHE |
1849 | else if (vmx->loaded_vmcs->cpu != cpu) |
1850 | loaded_vmcs_clear(vmx->loaded_vmcs); | |
6aa8b732 | 1851 | |
d462b819 NHE |
1852 | if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) { |
1853 | per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs; | |
1854 | vmcs_load(vmx->loaded_vmcs->vmcs); | |
6aa8b732 AK |
1855 | } |
1856 | ||
d462b819 | 1857 | if (vmx->loaded_vmcs->cpu != cpu) { |
89cbc767 | 1858 | struct desc_ptr *gdt = this_cpu_ptr(&host_gdt); |
6aa8b732 AK |
1859 | unsigned long sysenter_esp; |
1860 | ||
a8eeb04a | 1861 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
92fe13be | 1862 | local_irq_disable(); |
8f536b76 | 1863 | crash_disable_local_vmclear(cpu); |
5a560f8b XG |
1864 | |
1865 | /* | |
1866 | * Read loaded_vmcs->cpu should be before fetching | |
1867 | * loaded_vmcs->loaded_vmcss_on_cpu_link. | |
1868 | * See the comments in __loaded_vmcs_clear(). | |
1869 | */ | |
1870 | smp_rmb(); | |
1871 | ||
d462b819 NHE |
1872 | list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link, |
1873 | &per_cpu(loaded_vmcss_on_cpu, cpu)); | |
8f536b76 | 1874 | crash_enable_local_vmclear(cpu); |
92fe13be DX |
1875 | local_irq_enable(); |
1876 | ||
6aa8b732 AK |
1877 | /* |
1878 | * Linux uses per-cpu TSS and GDT, so set these when switching | |
1879 | * processors. | |
1880 | */ | |
d6e88aec | 1881 | vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */ |
d359192f | 1882 | vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */ |
6aa8b732 AK |
1883 | |
1884 | rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp); | |
1885 | vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */ | |
d462b819 | 1886 | vmx->loaded_vmcs->cpu = cpu; |
6aa8b732 | 1887 | } |
6aa8b732 AK |
1888 | } |
1889 | ||
1890 | static void vmx_vcpu_put(struct kvm_vcpu *vcpu) | |
1891 | { | |
a9b21b62 | 1892 | __vmx_load_host_state(to_vmx(vcpu)); |
4610c9cc | 1893 | if (!vmm_exclusive) { |
d462b819 NHE |
1894 | __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs); |
1895 | vcpu->cpu = -1; | |
4610c9cc DX |
1896 | kvm_cpu_vmxoff(); |
1897 | } | |
6aa8b732 AK |
1898 | } |
1899 | ||
5fd86fcf AK |
1900 | static void vmx_fpu_activate(struct kvm_vcpu *vcpu) |
1901 | { | |
81231c69 AK |
1902 | ulong cr0; |
1903 | ||
5fd86fcf AK |
1904 | if (vcpu->fpu_active) |
1905 | return; | |
1906 | vcpu->fpu_active = 1; | |
81231c69 AK |
1907 | cr0 = vmcs_readl(GUEST_CR0); |
1908 | cr0 &= ~(X86_CR0_TS | X86_CR0_MP); | |
1909 | cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP); | |
1910 | vmcs_writel(GUEST_CR0, cr0); | |
5fd86fcf | 1911 | update_exception_bitmap(vcpu); |
edcafe3c | 1912 | vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS; |
36cf24e0 NHE |
1913 | if (is_guest_mode(vcpu)) |
1914 | vcpu->arch.cr0_guest_owned_bits &= | |
1915 | ~get_vmcs12(vcpu)->cr0_guest_host_mask; | |
edcafe3c | 1916 | vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits); |
5fd86fcf AK |
1917 | } |
1918 | ||
edcafe3c AK |
1919 | static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu); |
1920 | ||
fe3ef05c NHE |
1921 | /* |
1922 | * Return the cr0 value that a nested guest would read. This is a combination | |
1923 | * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by | |
1924 | * its hypervisor (cr0_read_shadow). | |
1925 | */ | |
1926 | static inline unsigned long nested_read_cr0(struct vmcs12 *fields) | |
1927 | { | |
1928 | return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) | | |
1929 | (fields->cr0_read_shadow & fields->cr0_guest_host_mask); | |
1930 | } | |
1931 | static inline unsigned long nested_read_cr4(struct vmcs12 *fields) | |
1932 | { | |
1933 | return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) | | |
1934 | (fields->cr4_read_shadow & fields->cr4_guest_host_mask); | |
1935 | } | |
1936 | ||
5fd86fcf AK |
1937 | static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu) |
1938 | { | |
36cf24e0 NHE |
1939 | /* Note that there is no vcpu->fpu_active = 0 here. The caller must |
1940 | * set this *before* calling this function. | |
1941 | */ | |
edcafe3c | 1942 | vmx_decache_cr0_guest_bits(vcpu); |
81231c69 | 1943 | vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP); |
5fd86fcf | 1944 | update_exception_bitmap(vcpu); |
edcafe3c AK |
1945 | vcpu->arch.cr0_guest_owned_bits = 0; |
1946 | vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits); | |
36cf24e0 NHE |
1947 | if (is_guest_mode(vcpu)) { |
1948 | /* | |
1949 | * L1's specified read shadow might not contain the TS bit, | |
1950 | * so now that we turned on shadowing of this bit, we need to | |
1951 | * set this bit of the shadow. Like in nested_vmx_run we need | |
1952 | * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet | |
1953 | * up-to-date here because we just decached cr0.TS (and we'll | |
1954 | * only update vmcs12->guest_cr0 on nested exit). | |
1955 | */ | |
1956 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
1957 | vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) | | |
1958 | (vcpu->arch.cr0 & X86_CR0_TS); | |
1959 | vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12)); | |
1960 | } else | |
1961 | vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0); | |
5fd86fcf AK |
1962 | } |
1963 | ||
6aa8b732 AK |
1964 | static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu) |
1965 | { | |
78ac8b47 | 1966 | unsigned long rflags, save_rflags; |
345dcaa8 | 1967 | |
6de12732 AK |
1968 | if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) { |
1969 | __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail); | |
1970 | rflags = vmcs_readl(GUEST_RFLAGS); | |
1971 | if (to_vmx(vcpu)->rmode.vm86_active) { | |
1972 | rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS; | |
1973 | save_rflags = to_vmx(vcpu)->rmode.save_rflags; | |
1974 | rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS; | |
1975 | } | |
1976 | to_vmx(vcpu)->rflags = rflags; | |
78ac8b47 | 1977 | } |
6de12732 | 1978 | return to_vmx(vcpu)->rflags; |
6aa8b732 AK |
1979 | } |
1980 | ||
1981 | static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
1982 | { | |
6de12732 AK |
1983 | __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail); |
1984 | to_vmx(vcpu)->rflags = rflags; | |
78ac8b47 AK |
1985 | if (to_vmx(vcpu)->rmode.vm86_active) { |
1986 | to_vmx(vcpu)->rmode.save_rflags = rflags; | |
053de044 | 1987 | rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; |
78ac8b47 | 1988 | } |
6aa8b732 AK |
1989 | vmcs_writel(GUEST_RFLAGS, rflags); |
1990 | } | |
1991 | ||
37ccdcbe | 1992 | static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu) |
2809f5d2 GC |
1993 | { |
1994 | u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
1995 | int ret = 0; | |
1996 | ||
1997 | if (interruptibility & GUEST_INTR_STATE_STI) | |
48005f64 | 1998 | ret |= KVM_X86_SHADOW_INT_STI; |
2809f5d2 | 1999 | if (interruptibility & GUEST_INTR_STATE_MOV_SS) |
48005f64 | 2000 | ret |= KVM_X86_SHADOW_INT_MOV_SS; |
2809f5d2 | 2001 | |
37ccdcbe | 2002 | return ret; |
2809f5d2 GC |
2003 | } |
2004 | ||
2005 | static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) | |
2006 | { | |
2007 | u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
2008 | u32 interruptibility = interruptibility_old; | |
2009 | ||
2010 | interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS); | |
2011 | ||
48005f64 | 2012 | if (mask & KVM_X86_SHADOW_INT_MOV_SS) |
2809f5d2 | 2013 | interruptibility |= GUEST_INTR_STATE_MOV_SS; |
48005f64 | 2014 | else if (mask & KVM_X86_SHADOW_INT_STI) |
2809f5d2 GC |
2015 | interruptibility |= GUEST_INTR_STATE_STI; |
2016 | ||
2017 | if ((interruptibility != interruptibility_old)) | |
2018 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility); | |
2019 | } | |
2020 | ||
6aa8b732 AK |
2021 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) |
2022 | { | |
2023 | unsigned long rip; | |
6aa8b732 | 2024 | |
5fdbf976 | 2025 | rip = kvm_rip_read(vcpu); |
6aa8b732 | 2026 | rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN); |
5fdbf976 | 2027 | kvm_rip_write(vcpu, rip); |
6aa8b732 | 2028 | |
2809f5d2 GC |
2029 | /* skipping an emulated instruction also counts */ |
2030 | vmx_set_interrupt_shadow(vcpu, 0); | |
6aa8b732 AK |
2031 | } |
2032 | ||
0b6ac343 NHE |
2033 | /* |
2034 | * KVM wants to inject page-faults which it got to the guest. This function | |
2035 | * checks whether in a nested guest, we need to inject them to L1 or L2. | |
0b6ac343 | 2036 | */ |
e011c663 | 2037 | static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr) |
0b6ac343 NHE |
2038 | { |
2039 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
2040 | ||
e011c663 | 2041 | if (!(vmcs12->exception_bitmap & (1u << nr))) |
0b6ac343 NHE |
2042 | return 0; |
2043 | ||
533558bc JK |
2044 | nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason, |
2045 | vmcs_read32(VM_EXIT_INTR_INFO), | |
2046 | vmcs_readl(EXIT_QUALIFICATION)); | |
0b6ac343 NHE |
2047 | return 1; |
2048 | } | |
2049 | ||
298101da | 2050 | static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr, |
ce7ddec4 JR |
2051 | bool has_error_code, u32 error_code, |
2052 | bool reinject) | |
298101da | 2053 | { |
77ab6db0 | 2054 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
8ab2d2e2 | 2055 | u32 intr_info = nr | INTR_INFO_VALID_MASK; |
77ab6db0 | 2056 | |
e011c663 GN |
2057 | if (!reinject && is_guest_mode(vcpu) && |
2058 | nested_vmx_check_exception(vcpu, nr)) | |
0b6ac343 NHE |
2059 | return; |
2060 | ||
8ab2d2e2 | 2061 | if (has_error_code) { |
77ab6db0 | 2062 | vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code); |
8ab2d2e2 JK |
2063 | intr_info |= INTR_INFO_DELIVER_CODE_MASK; |
2064 | } | |
77ab6db0 | 2065 | |
7ffd92c5 | 2066 | if (vmx->rmode.vm86_active) { |
71f9833b SH |
2067 | int inc_eip = 0; |
2068 | if (kvm_exception_is_soft(nr)) | |
2069 | inc_eip = vcpu->arch.event_exit_inst_len; | |
2070 | if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE) | |
a92601bb | 2071 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
77ab6db0 JK |
2072 | return; |
2073 | } | |
2074 | ||
66fd3f7f GN |
2075 | if (kvm_exception_is_soft(nr)) { |
2076 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, | |
2077 | vmx->vcpu.arch.event_exit_inst_len); | |
8ab2d2e2 JK |
2078 | intr_info |= INTR_TYPE_SOFT_EXCEPTION; |
2079 | } else | |
2080 | intr_info |= INTR_TYPE_HARD_EXCEPTION; | |
2081 | ||
2082 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info); | |
298101da AK |
2083 | } |
2084 | ||
4e47c7a6 SY |
2085 | static bool vmx_rdtscp_supported(void) |
2086 | { | |
2087 | return cpu_has_vmx_rdtscp(); | |
2088 | } | |
2089 | ||
ad756a16 MJ |
2090 | static bool vmx_invpcid_supported(void) |
2091 | { | |
2092 | return cpu_has_vmx_invpcid() && enable_ept; | |
2093 | } | |
2094 | ||
a75beee6 ED |
2095 | /* |
2096 | * Swap MSR entry in host/guest MSR entry array. | |
2097 | */ | |
8b9cf98c | 2098 | static void move_msr_up(struct vcpu_vmx *vmx, int from, int to) |
a75beee6 | 2099 | { |
26bb0981 | 2100 | struct shared_msr_entry tmp; |
a2fa3e9f GH |
2101 | |
2102 | tmp = vmx->guest_msrs[to]; | |
2103 | vmx->guest_msrs[to] = vmx->guest_msrs[from]; | |
2104 | vmx->guest_msrs[from] = tmp; | |
a75beee6 ED |
2105 | } |
2106 | ||
8d14695f YZ |
2107 | static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu) |
2108 | { | |
2109 | unsigned long *msr_bitmap; | |
2110 | ||
2111 | if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) { | |
2112 | if (is_long_mode(vcpu)) | |
2113 | msr_bitmap = vmx_msr_bitmap_longmode_x2apic; | |
2114 | else | |
2115 | msr_bitmap = vmx_msr_bitmap_legacy_x2apic; | |
2116 | } else { | |
2117 | if (is_long_mode(vcpu)) | |
2118 | msr_bitmap = vmx_msr_bitmap_longmode; | |
2119 | else | |
2120 | msr_bitmap = vmx_msr_bitmap_legacy; | |
2121 | } | |
2122 | ||
2123 | vmcs_write64(MSR_BITMAP, __pa(msr_bitmap)); | |
2124 | } | |
2125 | ||
e38aea3e AK |
2126 | /* |
2127 | * Set up the vmcs to automatically save and restore system | |
2128 | * msrs. Don't touch the 64-bit msrs if the guest is in legacy | |
2129 | * mode, as fiddling with msrs is very expensive. | |
2130 | */ | |
8b9cf98c | 2131 | static void setup_msrs(struct vcpu_vmx *vmx) |
e38aea3e | 2132 | { |
26bb0981 | 2133 | int save_nmsrs, index; |
e38aea3e | 2134 | |
a75beee6 ED |
2135 | save_nmsrs = 0; |
2136 | #ifdef CONFIG_X86_64 | |
8b9cf98c | 2137 | if (is_long_mode(&vmx->vcpu)) { |
8b9cf98c | 2138 | index = __find_msr_index(vmx, MSR_SYSCALL_MASK); |
a75beee6 | 2139 | if (index >= 0) |
8b9cf98c RR |
2140 | move_msr_up(vmx, index, save_nmsrs++); |
2141 | index = __find_msr_index(vmx, MSR_LSTAR); | |
a75beee6 | 2142 | if (index >= 0) |
8b9cf98c RR |
2143 | move_msr_up(vmx, index, save_nmsrs++); |
2144 | index = __find_msr_index(vmx, MSR_CSTAR); | |
a75beee6 | 2145 | if (index >= 0) |
8b9cf98c | 2146 | move_msr_up(vmx, index, save_nmsrs++); |
4e47c7a6 SY |
2147 | index = __find_msr_index(vmx, MSR_TSC_AUX); |
2148 | if (index >= 0 && vmx->rdtscp_enabled) | |
2149 | move_msr_up(vmx, index, save_nmsrs++); | |
a75beee6 | 2150 | /* |
8c06585d | 2151 | * MSR_STAR is only needed on long mode guests, and only |
a75beee6 ED |
2152 | * if efer.sce is enabled. |
2153 | */ | |
8c06585d | 2154 | index = __find_msr_index(vmx, MSR_STAR); |
f6801dff | 2155 | if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE)) |
8b9cf98c | 2156 | move_msr_up(vmx, index, save_nmsrs++); |
a75beee6 ED |
2157 | } |
2158 | #endif | |
92c0d900 AK |
2159 | index = __find_msr_index(vmx, MSR_EFER); |
2160 | if (index >= 0 && update_transition_efer(vmx, index)) | |
26bb0981 | 2161 | move_msr_up(vmx, index, save_nmsrs++); |
e38aea3e | 2162 | |
26bb0981 | 2163 | vmx->save_nmsrs = save_nmsrs; |
5897297b | 2164 | |
8d14695f YZ |
2165 | if (cpu_has_vmx_msr_bitmap()) |
2166 | vmx_set_msr_bitmap(&vmx->vcpu); | |
e38aea3e AK |
2167 | } |
2168 | ||
6aa8b732 AK |
2169 | /* |
2170 | * reads and returns guest's timestamp counter "register" | |
2171 | * guest_tsc = host_tsc + tsc_offset -- 21.3 | |
2172 | */ | |
2173 | static u64 guest_read_tsc(void) | |
2174 | { | |
2175 | u64 host_tsc, tsc_offset; | |
2176 | ||
2177 | rdtscll(host_tsc); | |
2178 | tsc_offset = vmcs_read64(TSC_OFFSET); | |
2179 | return host_tsc + tsc_offset; | |
2180 | } | |
2181 | ||
d5c1785d NHE |
2182 | /* |
2183 | * Like guest_read_tsc, but always returns L1's notion of the timestamp | |
2184 | * counter, even if a nested guest (L2) is currently running. | |
2185 | */ | |
48d89b92 | 2186 | static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc) |
d5c1785d | 2187 | { |
886b470c | 2188 | u64 tsc_offset; |
d5c1785d | 2189 | |
d5c1785d NHE |
2190 | tsc_offset = is_guest_mode(vcpu) ? |
2191 | to_vmx(vcpu)->nested.vmcs01_tsc_offset : | |
2192 | vmcs_read64(TSC_OFFSET); | |
2193 | return host_tsc + tsc_offset; | |
2194 | } | |
2195 | ||
4051b188 | 2196 | /* |
cc578287 ZA |
2197 | * Engage any workarounds for mis-matched TSC rates. Currently limited to |
2198 | * software catchup for faster rates on slower CPUs. | |
4051b188 | 2199 | */ |
cc578287 | 2200 | static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale) |
4051b188 | 2201 | { |
cc578287 ZA |
2202 | if (!scale) |
2203 | return; | |
2204 | ||
2205 | if (user_tsc_khz > tsc_khz) { | |
2206 | vcpu->arch.tsc_catchup = 1; | |
2207 | vcpu->arch.tsc_always_catchup = 1; | |
2208 | } else | |
2209 | WARN(1, "user requested TSC rate below hardware speed\n"); | |
4051b188 JR |
2210 | } |
2211 | ||
ba904635 WA |
2212 | static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu) |
2213 | { | |
2214 | return vmcs_read64(TSC_OFFSET); | |
2215 | } | |
2216 | ||
6aa8b732 | 2217 | /* |
99e3e30a | 2218 | * writes 'offset' into guest's timestamp counter offset register |
6aa8b732 | 2219 | */ |
99e3e30a | 2220 | static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) |
6aa8b732 | 2221 | { |
27fc51b2 | 2222 | if (is_guest_mode(vcpu)) { |
7991825b | 2223 | /* |
27fc51b2 NHE |
2224 | * We're here if L1 chose not to trap WRMSR to TSC. According |
2225 | * to the spec, this should set L1's TSC; The offset that L1 | |
2226 | * set for L2 remains unchanged, and still needs to be added | |
2227 | * to the newly set TSC to get L2's TSC. | |
7991825b | 2228 | */ |
27fc51b2 NHE |
2229 | struct vmcs12 *vmcs12; |
2230 | to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset; | |
2231 | /* recalculate vmcs02.TSC_OFFSET: */ | |
2232 | vmcs12 = get_vmcs12(vcpu); | |
2233 | vmcs_write64(TSC_OFFSET, offset + | |
2234 | (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ? | |
2235 | vmcs12->tsc_offset : 0)); | |
2236 | } else { | |
489223ed YY |
2237 | trace_kvm_write_tsc_offset(vcpu->vcpu_id, |
2238 | vmcs_read64(TSC_OFFSET), offset); | |
27fc51b2 NHE |
2239 | vmcs_write64(TSC_OFFSET, offset); |
2240 | } | |
6aa8b732 AK |
2241 | } |
2242 | ||
f1e2b260 | 2243 | static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host) |
e48672fa ZA |
2244 | { |
2245 | u64 offset = vmcs_read64(TSC_OFFSET); | |
489223ed | 2246 | |
e48672fa | 2247 | vmcs_write64(TSC_OFFSET, offset + adjustment); |
7991825b NHE |
2248 | if (is_guest_mode(vcpu)) { |
2249 | /* Even when running L2, the adjustment needs to apply to L1 */ | |
2250 | to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment; | |
489223ed YY |
2251 | } else |
2252 | trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset, | |
2253 | offset + adjustment); | |
e48672fa ZA |
2254 | } |
2255 | ||
857e4099 JR |
2256 | static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc) |
2257 | { | |
2258 | return target_tsc - native_read_tsc(); | |
2259 | } | |
2260 | ||
801d3424 NHE |
2261 | static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu) |
2262 | { | |
2263 | struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0); | |
2264 | return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31))); | |
2265 | } | |
2266 | ||
2267 | /* | |
2268 | * nested_vmx_allowed() checks whether a guest should be allowed to use VMX | |
2269 | * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for | |
2270 | * all guests if the "nested" module option is off, and can also be disabled | |
2271 | * for a single guest by disabling its VMX cpuid bit. | |
2272 | */ | |
2273 | static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu) | |
2274 | { | |
2275 | return nested && guest_cpuid_has_vmx(vcpu); | |
2276 | } | |
2277 | ||
b87a51ae NHE |
2278 | /* |
2279 | * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be | |
2280 | * returned for the various VMX controls MSRs when nested VMX is enabled. | |
2281 | * The same values should also be used to verify that vmcs12 control fields are | |
2282 | * valid during nested entry from L1 to L2. | |
2283 | * Each of these control msrs has a low and high 32-bit half: A low bit is on | |
2284 | * if the corresponding bit in the (32-bit) control field *must* be on, and a | |
2285 | * bit in the high half is on if the corresponding bit in the control field | |
2286 | * may be on. See also vmx_control_verify(). | |
2287 | * TODO: allow these variables to be modified (downgraded) by module options | |
2288 | * or other means. | |
2289 | */ | |
2290 | static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high; | |
3dcdf3ec | 2291 | static u32 nested_vmx_true_procbased_ctls_low; |
b87a51ae NHE |
2292 | static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high; |
2293 | static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high; | |
2294 | static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high; | |
2996fca0 | 2295 | static u32 nested_vmx_true_exit_ctls_low; |
b87a51ae | 2296 | static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high; |
2996fca0 | 2297 | static u32 nested_vmx_true_entry_ctls_low; |
c18911a2 | 2298 | static u32 nested_vmx_misc_low, nested_vmx_misc_high; |
bfd0a56b | 2299 | static u32 nested_vmx_ept_caps; |
b87a51ae NHE |
2300 | static __init void nested_vmx_setup_ctls_msrs(void) |
2301 | { | |
2302 | /* | |
2303 | * Note that as a general rule, the high half of the MSRs (bits in | |
2304 | * the control fields which may be 1) should be initialized by the | |
2305 | * intersection of the underlying hardware's MSR (i.e., features which | |
2306 | * can be supported) and the list of features we want to expose - | |
2307 | * because they are known to be properly supported in our code. | |
2308 | * Also, usually, the low half of the MSRs (bits which must be 1) can | |
2309 | * be set to 0, meaning that L1 may turn off any of these bits. The | |
2310 | * reason is that if one of these bits is necessary, it will appear | |
2311 | * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control | |
2312 | * fields of vmcs01 and vmcs02, will turn these bits off - and | |
2313 | * nested_vmx_exit_handled() will not pass related exits to L1. | |
2314 | * These rules have exceptions below. | |
2315 | */ | |
2316 | ||
2317 | /* pin-based controls */ | |
eabeaacc JK |
2318 | rdmsr(MSR_IA32_VMX_PINBASED_CTLS, |
2319 | nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high); | |
eabeaacc JK |
2320 | nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR; |
2321 | nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK | | |
f4124500 JK |
2322 | PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS; |
2323 | nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR | | |
0238ea91 | 2324 | PIN_BASED_VMX_PREEMPTION_TIMER; |
b87a51ae | 2325 | |
3dbcd8da | 2326 | /* exit controls */ |
c0dfee58 ACL |
2327 | rdmsr(MSR_IA32_VMX_EXIT_CTLS, |
2328 | nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high); | |
33fb20c3 | 2329 | nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR; |
e0ba1a6f | 2330 | |
c0dfee58 | 2331 | nested_vmx_exit_ctls_high &= |
b87a51ae | 2332 | #ifdef CONFIG_X86_64 |
c0dfee58 | 2333 | VM_EXIT_HOST_ADDR_SPACE_SIZE | |
b87a51ae | 2334 | #endif |
f4124500 JK |
2335 | VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT; |
2336 | nested_vmx_exit_ctls_high |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR | | |
2337 | VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER | | |
e0ba1a6f BD |
2338 | VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT; |
2339 | ||
36be0b9d PB |
2340 | if (vmx_mpx_supported()) |
2341 | nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS; | |
b87a51ae | 2342 | |
2996fca0 JK |
2343 | /* We support free control of debug control saving. */ |
2344 | nested_vmx_true_exit_ctls_low = nested_vmx_exit_ctls_low & | |
2345 | ~VM_EXIT_SAVE_DEBUG_CONTROLS; | |
2346 | ||
b87a51ae NHE |
2347 | /* entry controls */ |
2348 | rdmsr(MSR_IA32_VMX_ENTRY_CTLS, | |
2349 | nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high); | |
33fb20c3 | 2350 | nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR; |
b87a51ae | 2351 | nested_vmx_entry_ctls_high &= |
57435349 JK |
2352 | #ifdef CONFIG_X86_64 |
2353 | VM_ENTRY_IA32E_MODE | | |
2354 | #endif | |
2355 | VM_ENTRY_LOAD_IA32_PAT; | |
8049d651 NHE |
2356 | nested_vmx_entry_ctls_high |= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | |
2357 | VM_ENTRY_LOAD_IA32_EFER); | |
36be0b9d PB |
2358 | if (vmx_mpx_supported()) |
2359 | nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS; | |
57435349 | 2360 | |
2996fca0 JK |
2361 | /* We support free control of debug control loading. */ |
2362 | nested_vmx_true_entry_ctls_low = nested_vmx_entry_ctls_low & | |
2363 | ~VM_ENTRY_LOAD_DEBUG_CONTROLS; | |
2364 | ||
b87a51ae NHE |
2365 | /* cpu-based controls */ |
2366 | rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, | |
2367 | nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high); | |
560b7ee1 | 2368 | nested_vmx_procbased_ctls_low = CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR; |
b87a51ae | 2369 | nested_vmx_procbased_ctls_high &= |
a294c9bb JK |
2370 | CPU_BASED_VIRTUAL_INTR_PENDING | |
2371 | CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING | | |
b87a51ae NHE |
2372 | CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING | |
2373 | CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING | | |
2374 | CPU_BASED_CR3_STORE_EXITING | | |
2375 | #ifdef CONFIG_X86_64 | |
2376 | CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING | | |
2377 | #endif | |
2378 | CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING | | |
2379 | CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING | | |
dbcb4e79 | 2380 | CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING | |
a7c0b07d | 2381 | CPU_BASED_PAUSE_EXITING | CPU_BASED_TPR_SHADOW | |
b87a51ae NHE |
2382 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; |
2383 | /* | |
2384 | * We can allow some features even when not supported by the | |
2385 | * hardware. For example, L1 can specify an MSR bitmap - and we | |
2386 | * can use it to avoid exits to L1 - even when L0 runs L2 | |
2387 | * without MSR bitmaps. | |
2388 | */ | |
560b7ee1 JK |
2389 | nested_vmx_procbased_ctls_high |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR | |
2390 | CPU_BASED_USE_MSR_BITMAPS; | |
b87a51ae | 2391 | |
3dcdf3ec JK |
2392 | /* We support free control of CR3 access interception. */ |
2393 | nested_vmx_true_procbased_ctls_low = nested_vmx_procbased_ctls_low & | |
2394 | ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING); | |
2395 | ||
b87a51ae NHE |
2396 | /* secondary cpu-based controls */ |
2397 | rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2, | |
2398 | nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high); | |
2399 | nested_vmx_secondary_ctls_low = 0; | |
2400 | nested_vmx_secondary_ctls_high &= | |
d6851fbe | 2401 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | |
81dc01f7 WL |
2402 | SECONDARY_EXEC_WBINVD_EXITING | |
2403 | SECONDARY_EXEC_XSAVES; | |
c18911a2 | 2404 | |
afa61f75 NHE |
2405 | if (enable_ept) { |
2406 | /* nested EPT: emulate EPT also to L1 */ | |
78051e3b BD |
2407 | nested_vmx_secondary_ctls_high |= SECONDARY_EXEC_ENABLE_EPT | |
2408 | SECONDARY_EXEC_UNRESTRICTED_GUEST; | |
ca72d970 | 2409 | nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT | |
d3134dbf JK |
2410 | VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT | |
2411 | VMX_EPT_INVEPT_BIT; | |
afa61f75 NHE |
2412 | nested_vmx_ept_caps &= vmx_capability.ept; |
2413 | /* | |
4b855078 BD |
2414 | * For nested guests, we don't do anything specific |
2415 | * for single context invalidation. Hence, only advertise | |
2416 | * support for global context invalidation. | |
afa61f75 | 2417 | */ |
4b855078 | 2418 | nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT; |
afa61f75 NHE |
2419 | } else |
2420 | nested_vmx_ept_caps = 0; | |
2421 | ||
c18911a2 JK |
2422 | /* miscellaneous data */ |
2423 | rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high); | |
f4124500 JK |
2424 | nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA; |
2425 | nested_vmx_misc_low |= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE | | |
2426 | VMX_MISC_ACTIVITY_HLT; | |
c18911a2 | 2427 | nested_vmx_misc_high = 0; |
b87a51ae NHE |
2428 | } |
2429 | ||
2430 | static inline bool vmx_control_verify(u32 control, u32 low, u32 high) | |
2431 | { | |
2432 | /* | |
2433 | * Bits 0 in high must be 0, and bits 1 in low must be 1. | |
2434 | */ | |
2435 | return ((control & high) | low) == control; | |
2436 | } | |
2437 | ||
2438 | static inline u64 vmx_control_msr(u32 low, u32 high) | |
2439 | { | |
2440 | return low | ((u64)high << 32); | |
2441 | } | |
2442 | ||
cae50139 | 2443 | /* Returns 0 on success, non-0 otherwise. */ |
b87a51ae NHE |
2444 | static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata) |
2445 | { | |
b87a51ae | 2446 | switch (msr_index) { |
b87a51ae NHE |
2447 | case MSR_IA32_VMX_BASIC: |
2448 | /* | |
2449 | * This MSR reports some information about VMX support. We | |
2450 | * should return information about the VMX we emulate for the | |
2451 | * guest, and the VMCS structure we give it - not about the | |
2452 | * VMX support of the underlying hardware. | |
2453 | */ | |
3dbcd8da | 2454 | *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS | |
b87a51ae NHE |
2455 | ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) | |
2456 | (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT); | |
2457 | break; | |
2458 | case MSR_IA32_VMX_TRUE_PINBASED_CTLS: | |
2459 | case MSR_IA32_VMX_PINBASED_CTLS: | |
2460 | *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low, | |
2461 | nested_vmx_pinbased_ctls_high); | |
2462 | break; | |
2463 | case MSR_IA32_VMX_TRUE_PROCBASED_CTLS: | |
3dcdf3ec JK |
2464 | *pdata = vmx_control_msr(nested_vmx_true_procbased_ctls_low, |
2465 | nested_vmx_procbased_ctls_high); | |
2466 | break; | |
b87a51ae NHE |
2467 | case MSR_IA32_VMX_PROCBASED_CTLS: |
2468 | *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low, | |
2469 | nested_vmx_procbased_ctls_high); | |
2470 | break; | |
2471 | case MSR_IA32_VMX_TRUE_EXIT_CTLS: | |
2996fca0 JK |
2472 | *pdata = vmx_control_msr(nested_vmx_true_exit_ctls_low, |
2473 | nested_vmx_exit_ctls_high); | |
2474 | break; | |
b87a51ae NHE |
2475 | case MSR_IA32_VMX_EXIT_CTLS: |
2476 | *pdata = vmx_control_msr(nested_vmx_exit_ctls_low, | |
2477 | nested_vmx_exit_ctls_high); | |
2478 | break; | |
2479 | case MSR_IA32_VMX_TRUE_ENTRY_CTLS: | |
2996fca0 JK |
2480 | *pdata = vmx_control_msr(nested_vmx_true_entry_ctls_low, |
2481 | nested_vmx_entry_ctls_high); | |
2482 | break; | |
b87a51ae NHE |
2483 | case MSR_IA32_VMX_ENTRY_CTLS: |
2484 | *pdata = vmx_control_msr(nested_vmx_entry_ctls_low, | |
2485 | nested_vmx_entry_ctls_high); | |
2486 | break; | |
2487 | case MSR_IA32_VMX_MISC: | |
c18911a2 JK |
2488 | *pdata = vmx_control_msr(nested_vmx_misc_low, |
2489 | nested_vmx_misc_high); | |
b87a51ae NHE |
2490 | break; |
2491 | /* | |
2492 | * These MSRs specify bits which the guest must keep fixed (on or off) | |
2493 | * while L1 is in VMXON mode (in L1's root mode, or running an L2). | |
2494 | * We picked the standard core2 setting. | |
2495 | */ | |
2496 | #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE) | |
2497 | #define VMXON_CR4_ALWAYSON X86_CR4_VMXE | |
2498 | case MSR_IA32_VMX_CR0_FIXED0: | |
2499 | *pdata = VMXON_CR0_ALWAYSON; | |
2500 | break; | |
2501 | case MSR_IA32_VMX_CR0_FIXED1: | |
2502 | *pdata = -1ULL; | |
2503 | break; | |
2504 | case MSR_IA32_VMX_CR4_FIXED0: | |
2505 | *pdata = VMXON_CR4_ALWAYSON; | |
2506 | break; | |
2507 | case MSR_IA32_VMX_CR4_FIXED1: | |
2508 | *pdata = -1ULL; | |
2509 | break; | |
2510 | case MSR_IA32_VMX_VMCS_ENUM: | |
5381417f | 2511 | *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */ |
b87a51ae NHE |
2512 | break; |
2513 | case MSR_IA32_VMX_PROCBASED_CTLS2: | |
2514 | *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low, | |
2515 | nested_vmx_secondary_ctls_high); | |
2516 | break; | |
2517 | case MSR_IA32_VMX_EPT_VPID_CAP: | |
afa61f75 NHE |
2518 | /* Currently, no nested vpid support */ |
2519 | *pdata = nested_vmx_ept_caps; | |
b87a51ae NHE |
2520 | break; |
2521 | default: | |
b87a51ae | 2522 | return 1; |
b3897a49 NHE |
2523 | } |
2524 | ||
b87a51ae NHE |
2525 | return 0; |
2526 | } | |
2527 | ||
6aa8b732 AK |
2528 | /* |
2529 | * Reads an msr value (of 'msr_index') into 'pdata'. | |
2530 | * Returns 0 on success, non-0 otherwise. | |
2531 | * Assumes vcpu_load() was already called. | |
2532 | */ | |
2533 | static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata) | |
2534 | { | |
2535 | u64 data; | |
26bb0981 | 2536 | struct shared_msr_entry *msr; |
6aa8b732 AK |
2537 | |
2538 | if (!pdata) { | |
2539 | printk(KERN_ERR "BUG: get_msr called with NULL pdata\n"); | |
2540 | return -EINVAL; | |
2541 | } | |
2542 | ||
2543 | switch (msr_index) { | |
05b3e0c2 | 2544 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
2545 | case MSR_FS_BASE: |
2546 | data = vmcs_readl(GUEST_FS_BASE); | |
2547 | break; | |
2548 | case MSR_GS_BASE: | |
2549 | data = vmcs_readl(GUEST_GS_BASE); | |
2550 | break; | |
44ea2b17 AK |
2551 | case MSR_KERNEL_GS_BASE: |
2552 | vmx_load_host_state(to_vmx(vcpu)); | |
2553 | data = to_vmx(vcpu)->msr_guest_kernel_gs_base; | |
2554 | break; | |
26bb0981 | 2555 | #endif |
6aa8b732 | 2556 | case MSR_EFER: |
3bab1f5d | 2557 | return kvm_get_msr_common(vcpu, msr_index, pdata); |
af24a4e4 | 2558 | case MSR_IA32_TSC: |
6aa8b732 AK |
2559 | data = guest_read_tsc(); |
2560 | break; | |
2561 | case MSR_IA32_SYSENTER_CS: | |
2562 | data = vmcs_read32(GUEST_SYSENTER_CS); | |
2563 | break; | |
2564 | case MSR_IA32_SYSENTER_EIP: | |
f5b42c33 | 2565 | data = vmcs_readl(GUEST_SYSENTER_EIP); |
6aa8b732 AK |
2566 | break; |
2567 | case MSR_IA32_SYSENTER_ESP: | |
f5b42c33 | 2568 | data = vmcs_readl(GUEST_SYSENTER_ESP); |
6aa8b732 | 2569 | break; |
0dd376e7 | 2570 | case MSR_IA32_BNDCFGS: |
93c4adc7 PB |
2571 | if (!vmx_mpx_supported()) |
2572 | return 1; | |
0dd376e7 LJ |
2573 | data = vmcs_read64(GUEST_BNDCFGS); |
2574 | break; | |
cae50139 JK |
2575 | case MSR_IA32_FEATURE_CONTROL: |
2576 | if (!nested_vmx_allowed(vcpu)) | |
2577 | return 1; | |
2578 | data = to_vmx(vcpu)->nested.msr_ia32_feature_control; | |
2579 | break; | |
2580 | case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: | |
2581 | if (!nested_vmx_allowed(vcpu)) | |
2582 | return 1; | |
2583 | return vmx_get_vmx_msr(vcpu, msr_index, pdata); | |
20300099 WL |
2584 | case MSR_IA32_XSS: |
2585 | if (!vmx_xsaves_supported()) | |
2586 | return 1; | |
2587 | data = vcpu->arch.ia32_xss; | |
2588 | break; | |
4e47c7a6 SY |
2589 | case MSR_TSC_AUX: |
2590 | if (!to_vmx(vcpu)->rdtscp_enabled) | |
2591 | return 1; | |
2592 | /* Otherwise falls through */ | |
6aa8b732 | 2593 | default: |
8b9cf98c | 2594 | msr = find_msr_entry(to_vmx(vcpu), msr_index); |
3bab1f5d AK |
2595 | if (msr) { |
2596 | data = msr->data; | |
2597 | break; | |
6aa8b732 | 2598 | } |
3bab1f5d | 2599 | return kvm_get_msr_common(vcpu, msr_index, pdata); |
6aa8b732 AK |
2600 | } |
2601 | ||
2602 | *pdata = data; | |
2603 | return 0; | |
2604 | } | |
2605 | ||
cae50139 JK |
2606 | static void vmx_leave_nested(struct kvm_vcpu *vcpu); |
2607 | ||
6aa8b732 AK |
2608 | /* |
2609 | * Writes msr value into into the appropriate "register". | |
2610 | * Returns 0 on success, non-0 otherwise. | |
2611 | * Assumes vcpu_load() was already called. | |
2612 | */ | |
8fe8ab46 | 2613 | static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
6aa8b732 | 2614 | { |
a2fa3e9f | 2615 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
26bb0981 | 2616 | struct shared_msr_entry *msr; |
2cc51560 | 2617 | int ret = 0; |
8fe8ab46 WA |
2618 | u32 msr_index = msr_info->index; |
2619 | u64 data = msr_info->data; | |
2cc51560 | 2620 | |
6aa8b732 | 2621 | switch (msr_index) { |
3bab1f5d | 2622 | case MSR_EFER: |
8fe8ab46 | 2623 | ret = kvm_set_msr_common(vcpu, msr_info); |
2cc51560 | 2624 | break; |
16175a79 | 2625 | #ifdef CONFIG_X86_64 |
6aa8b732 | 2626 | case MSR_FS_BASE: |
2fb92db1 | 2627 | vmx_segment_cache_clear(vmx); |
6aa8b732 AK |
2628 | vmcs_writel(GUEST_FS_BASE, data); |
2629 | break; | |
2630 | case MSR_GS_BASE: | |
2fb92db1 | 2631 | vmx_segment_cache_clear(vmx); |
6aa8b732 AK |
2632 | vmcs_writel(GUEST_GS_BASE, data); |
2633 | break; | |
44ea2b17 AK |
2634 | case MSR_KERNEL_GS_BASE: |
2635 | vmx_load_host_state(vmx); | |
2636 | vmx->msr_guest_kernel_gs_base = data; | |
2637 | break; | |
6aa8b732 AK |
2638 | #endif |
2639 | case MSR_IA32_SYSENTER_CS: | |
2640 | vmcs_write32(GUEST_SYSENTER_CS, data); | |
2641 | break; | |
2642 | case MSR_IA32_SYSENTER_EIP: | |
f5b42c33 | 2643 | vmcs_writel(GUEST_SYSENTER_EIP, data); |
6aa8b732 AK |
2644 | break; |
2645 | case MSR_IA32_SYSENTER_ESP: | |
f5b42c33 | 2646 | vmcs_writel(GUEST_SYSENTER_ESP, data); |
6aa8b732 | 2647 | break; |
0dd376e7 | 2648 | case MSR_IA32_BNDCFGS: |
93c4adc7 PB |
2649 | if (!vmx_mpx_supported()) |
2650 | return 1; | |
0dd376e7 LJ |
2651 | vmcs_write64(GUEST_BNDCFGS, data); |
2652 | break; | |
af24a4e4 | 2653 | case MSR_IA32_TSC: |
8fe8ab46 | 2654 | kvm_write_tsc(vcpu, msr_info); |
6aa8b732 | 2655 | break; |
468d472f SY |
2656 | case MSR_IA32_CR_PAT: |
2657 | if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) { | |
4566654b NA |
2658 | if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data)) |
2659 | return 1; | |
468d472f SY |
2660 | vmcs_write64(GUEST_IA32_PAT, data); |
2661 | vcpu->arch.pat = data; | |
2662 | break; | |
2663 | } | |
8fe8ab46 | 2664 | ret = kvm_set_msr_common(vcpu, msr_info); |
4e47c7a6 | 2665 | break; |
ba904635 WA |
2666 | case MSR_IA32_TSC_ADJUST: |
2667 | ret = kvm_set_msr_common(vcpu, msr_info); | |
4e47c7a6 | 2668 | break; |
cae50139 JK |
2669 | case MSR_IA32_FEATURE_CONTROL: |
2670 | if (!nested_vmx_allowed(vcpu) || | |
2671 | (to_vmx(vcpu)->nested.msr_ia32_feature_control & | |
2672 | FEATURE_CONTROL_LOCKED && !msr_info->host_initiated)) | |
2673 | return 1; | |
2674 | vmx->nested.msr_ia32_feature_control = data; | |
2675 | if (msr_info->host_initiated && data == 0) | |
2676 | vmx_leave_nested(vcpu); | |
2677 | break; | |
2678 | case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: | |
2679 | return 1; /* they are read-only */ | |
20300099 WL |
2680 | case MSR_IA32_XSS: |
2681 | if (!vmx_xsaves_supported()) | |
2682 | return 1; | |
2683 | /* | |
2684 | * The only supported bit as of Skylake is bit 8, but | |
2685 | * it is not supported on KVM. | |
2686 | */ | |
2687 | if (data != 0) | |
2688 | return 1; | |
2689 | vcpu->arch.ia32_xss = data; | |
2690 | if (vcpu->arch.ia32_xss != host_xss) | |
2691 | add_atomic_switch_msr(vmx, MSR_IA32_XSS, | |
2692 | vcpu->arch.ia32_xss, host_xss); | |
2693 | else | |
2694 | clear_atomic_switch_msr(vmx, MSR_IA32_XSS); | |
2695 | break; | |
4e47c7a6 SY |
2696 | case MSR_TSC_AUX: |
2697 | if (!vmx->rdtscp_enabled) | |
2698 | return 1; | |
2699 | /* Check reserved bit, higher 32 bits should be zero */ | |
2700 | if ((data >> 32) != 0) | |
2701 | return 1; | |
2702 | /* Otherwise falls through */ | |
6aa8b732 | 2703 | default: |
8b9cf98c | 2704 | msr = find_msr_entry(vmx, msr_index); |
3bab1f5d | 2705 | if (msr) { |
8b3c3104 | 2706 | u64 old_msr_data = msr->data; |
3bab1f5d | 2707 | msr->data = data; |
2225fd56 AK |
2708 | if (msr - vmx->guest_msrs < vmx->save_nmsrs) { |
2709 | preempt_disable(); | |
8b3c3104 AH |
2710 | ret = kvm_set_shared_msr(msr->index, msr->data, |
2711 | msr->mask); | |
2225fd56 | 2712 | preempt_enable(); |
8b3c3104 AH |
2713 | if (ret) |
2714 | msr->data = old_msr_data; | |
2225fd56 | 2715 | } |
3bab1f5d | 2716 | break; |
6aa8b732 | 2717 | } |
8fe8ab46 | 2718 | ret = kvm_set_msr_common(vcpu, msr_info); |
6aa8b732 AK |
2719 | } |
2720 | ||
2cc51560 | 2721 | return ret; |
6aa8b732 AK |
2722 | } |
2723 | ||
5fdbf976 | 2724 | static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) |
6aa8b732 | 2725 | { |
5fdbf976 MT |
2726 | __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail); |
2727 | switch (reg) { | |
2728 | case VCPU_REGS_RSP: | |
2729 | vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP); | |
2730 | break; | |
2731 | case VCPU_REGS_RIP: | |
2732 | vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP); | |
2733 | break; | |
6de4f3ad AK |
2734 | case VCPU_EXREG_PDPTR: |
2735 | if (enable_ept) | |
2736 | ept_save_pdptrs(vcpu); | |
2737 | break; | |
5fdbf976 MT |
2738 | default: |
2739 | break; | |
2740 | } | |
6aa8b732 AK |
2741 | } |
2742 | ||
6aa8b732 AK |
2743 | static __init int cpu_has_kvm_support(void) |
2744 | { | |
6210e37b | 2745 | return cpu_has_vmx(); |
6aa8b732 AK |
2746 | } |
2747 | ||
2748 | static __init int vmx_disabled_by_bios(void) | |
2749 | { | |
2750 | u64 msr; | |
2751 | ||
2752 | rdmsrl(MSR_IA32_FEATURE_CONTROL, msr); | |
cafd6659 | 2753 | if (msr & FEATURE_CONTROL_LOCKED) { |
23f3e991 | 2754 | /* launched w/ TXT and VMX disabled */ |
cafd6659 SW |
2755 | if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX) |
2756 | && tboot_enabled()) | |
2757 | return 1; | |
23f3e991 | 2758 | /* launched w/o TXT and VMX only enabled w/ TXT */ |
cafd6659 | 2759 | if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX) |
23f3e991 | 2760 | && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX) |
f9335afe SW |
2761 | && !tboot_enabled()) { |
2762 | printk(KERN_WARNING "kvm: disable TXT in the BIOS or " | |
23f3e991 | 2763 | "activate TXT before enabling KVM\n"); |
cafd6659 | 2764 | return 1; |
f9335afe | 2765 | } |
23f3e991 JC |
2766 | /* launched w/o TXT and VMX disabled */ |
2767 | if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX) | |
2768 | && !tboot_enabled()) | |
2769 | return 1; | |
cafd6659 SW |
2770 | } |
2771 | ||
2772 | return 0; | |
6aa8b732 AK |
2773 | } |
2774 | ||
7725b894 DX |
2775 | static void kvm_cpu_vmxon(u64 addr) |
2776 | { | |
2777 | asm volatile (ASM_VMX_VMXON_RAX | |
2778 | : : "a"(&addr), "m"(addr) | |
2779 | : "memory", "cc"); | |
2780 | } | |
2781 | ||
13a34e06 | 2782 | static int hardware_enable(void) |
6aa8b732 AK |
2783 | { |
2784 | int cpu = raw_smp_processor_id(); | |
2785 | u64 phys_addr = __pa(per_cpu(vmxarea, cpu)); | |
cafd6659 | 2786 | u64 old, test_bits; |
6aa8b732 | 2787 | |
10474ae8 AG |
2788 | if (read_cr4() & X86_CR4_VMXE) |
2789 | return -EBUSY; | |
2790 | ||
d462b819 | 2791 | INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu)); |
8f536b76 ZY |
2792 | |
2793 | /* | |
2794 | * Now we can enable the vmclear operation in kdump | |
2795 | * since the loaded_vmcss_on_cpu list on this cpu | |
2796 | * has been initialized. | |
2797 | * | |
2798 | * Though the cpu is not in VMX operation now, there | |
2799 | * is no problem to enable the vmclear operation | |
2800 | * for the loaded_vmcss_on_cpu list is empty! | |
2801 | */ | |
2802 | crash_enable_local_vmclear(cpu); | |
2803 | ||
6aa8b732 | 2804 | rdmsrl(MSR_IA32_FEATURE_CONTROL, old); |
cafd6659 SW |
2805 | |
2806 | test_bits = FEATURE_CONTROL_LOCKED; | |
2807 | test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; | |
2808 | if (tboot_enabled()) | |
2809 | test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX; | |
2810 | ||
2811 | if ((old & test_bits) != test_bits) { | |
6aa8b732 | 2812 | /* enable and lock */ |
cafd6659 SW |
2813 | wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits); |
2814 | } | |
66aee91a | 2815 | write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */ |
10474ae8 | 2816 | |
4610c9cc DX |
2817 | if (vmm_exclusive) { |
2818 | kvm_cpu_vmxon(phys_addr); | |
2819 | ept_sync_global(); | |
2820 | } | |
10474ae8 | 2821 | |
89cbc767 | 2822 | native_store_gdt(this_cpu_ptr(&host_gdt)); |
3444d7da | 2823 | |
10474ae8 | 2824 | return 0; |
6aa8b732 AK |
2825 | } |
2826 | ||
d462b819 | 2827 | static void vmclear_local_loaded_vmcss(void) |
543e4243 AK |
2828 | { |
2829 | int cpu = raw_smp_processor_id(); | |
d462b819 | 2830 | struct loaded_vmcs *v, *n; |
543e4243 | 2831 | |
d462b819 NHE |
2832 | list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu), |
2833 | loaded_vmcss_on_cpu_link) | |
2834 | __loaded_vmcs_clear(v); | |
543e4243 AK |
2835 | } |
2836 | ||
710ff4a8 EH |
2837 | |
2838 | /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot() | |
2839 | * tricks. | |
2840 | */ | |
2841 | static void kvm_cpu_vmxoff(void) | |
6aa8b732 | 2842 | { |
4ecac3fd | 2843 | asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc"); |
6aa8b732 AK |
2844 | } |
2845 | ||
13a34e06 | 2846 | static void hardware_disable(void) |
710ff4a8 | 2847 | { |
4610c9cc | 2848 | if (vmm_exclusive) { |
d462b819 | 2849 | vmclear_local_loaded_vmcss(); |
4610c9cc DX |
2850 | kvm_cpu_vmxoff(); |
2851 | } | |
7725b894 | 2852 | write_cr4(read_cr4() & ~X86_CR4_VMXE); |
710ff4a8 EH |
2853 | } |
2854 | ||
1c3d14fe | 2855 | static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt, |
d77c26fc | 2856 | u32 msr, u32 *result) |
1c3d14fe YS |
2857 | { |
2858 | u32 vmx_msr_low, vmx_msr_high; | |
2859 | u32 ctl = ctl_min | ctl_opt; | |
2860 | ||
2861 | rdmsr(msr, vmx_msr_low, vmx_msr_high); | |
2862 | ||
2863 | ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */ | |
2864 | ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */ | |
2865 | ||
2866 | /* Ensure minimum (required) set of control bits are supported. */ | |
2867 | if (ctl_min & ~ctl) | |
002c7f7c | 2868 | return -EIO; |
1c3d14fe YS |
2869 | |
2870 | *result = ctl; | |
2871 | return 0; | |
2872 | } | |
2873 | ||
110312c8 AK |
2874 | static __init bool allow_1_setting(u32 msr, u32 ctl) |
2875 | { | |
2876 | u32 vmx_msr_low, vmx_msr_high; | |
2877 | ||
2878 | rdmsr(msr, vmx_msr_low, vmx_msr_high); | |
2879 | return vmx_msr_high & ctl; | |
2880 | } | |
2881 | ||
002c7f7c | 2882 | static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf) |
6aa8b732 AK |
2883 | { |
2884 | u32 vmx_msr_low, vmx_msr_high; | |
d56f546d | 2885 | u32 min, opt, min2, opt2; |
1c3d14fe YS |
2886 | u32 _pin_based_exec_control = 0; |
2887 | u32 _cpu_based_exec_control = 0; | |
f78e0e2e | 2888 | u32 _cpu_based_2nd_exec_control = 0; |
1c3d14fe YS |
2889 | u32 _vmexit_control = 0; |
2890 | u32 _vmentry_control = 0; | |
2891 | ||
10166744 | 2892 | min = CPU_BASED_HLT_EXITING | |
1c3d14fe YS |
2893 | #ifdef CONFIG_X86_64 |
2894 | CPU_BASED_CR8_LOAD_EXITING | | |
2895 | CPU_BASED_CR8_STORE_EXITING | | |
2896 | #endif | |
d56f546d SY |
2897 | CPU_BASED_CR3_LOAD_EXITING | |
2898 | CPU_BASED_CR3_STORE_EXITING | | |
1c3d14fe YS |
2899 | CPU_BASED_USE_IO_BITMAPS | |
2900 | CPU_BASED_MOV_DR_EXITING | | |
a7052897 | 2901 | CPU_BASED_USE_TSC_OFFSETING | |
59708670 SY |
2902 | CPU_BASED_MWAIT_EXITING | |
2903 | CPU_BASED_MONITOR_EXITING | | |
fee84b07 AK |
2904 | CPU_BASED_INVLPG_EXITING | |
2905 | CPU_BASED_RDPMC_EXITING; | |
443381a8 | 2906 | |
f78e0e2e | 2907 | opt = CPU_BASED_TPR_SHADOW | |
25c5f225 | 2908 | CPU_BASED_USE_MSR_BITMAPS | |
f78e0e2e | 2909 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; |
1c3d14fe YS |
2910 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS, |
2911 | &_cpu_based_exec_control) < 0) | |
002c7f7c | 2912 | return -EIO; |
6e5d865c YS |
2913 | #ifdef CONFIG_X86_64 |
2914 | if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) | |
2915 | _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING & | |
2916 | ~CPU_BASED_CR8_STORE_EXITING; | |
2917 | #endif | |
f78e0e2e | 2918 | if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) { |
d56f546d SY |
2919 | min2 = 0; |
2920 | opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | | |
8d14695f | 2921 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | |
2384d2b3 | 2922 | SECONDARY_EXEC_WBINVD_EXITING | |
d56f546d | 2923 | SECONDARY_EXEC_ENABLE_VPID | |
3a624e29 | 2924 | SECONDARY_EXEC_ENABLE_EPT | |
4b8d54f9 | 2925 | SECONDARY_EXEC_UNRESTRICTED_GUEST | |
4e47c7a6 | 2926 | SECONDARY_EXEC_PAUSE_LOOP_EXITING | |
ad756a16 | 2927 | SECONDARY_EXEC_RDTSCP | |
83d4c286 | 2928 | SECONDARY_EXEC_ENABLE_INVPCID | |
c7c9c56c | 2929 | SECONDARY_EXEC_APIC_REGISTER_VIRT | |
abc4fc58 | 2930 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | |
20300099 WL |
2931 | SECONDARY_EXEC_SHADOW_VMCS | |
2932 | SECONDARY_EXEC_XSAVES; | |
d56f546d SY |
2933 | if (adjust_vmx_controls(min2, opt2, |
2934 | MSR_IA32_VMX_PROCBASED_CTLS2, | |
f78e0e2e SY |
2935 | &_cpu_based_2nd_exec_control) < 0) |
2936 | return -EIO; | |
2937 | } | |
2938 | #ifndef CONFIG_X86_64 | |
2939 | if (!(_cpu_based_2nd_exec_control & | |
2940 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) | |
2941 | _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW; | |
2942 | #endif | |
83d4c286 YZ |
2943 | |
2944 | if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) | |
2945 | _cpu_based_2nd_exec_control &= ~( | |
8d14695f | 2946 | SECONDARY_EXEC_APIC_REGISTER_VIRT | |
c7c9c56c YZ |
2947 | SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | |
2948 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); | |
83d4c286 | 2949 | |
d56f546d | 2950 | if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) { |
a7052897 MT |
2951 | /* CR3 accesses and invlpg don't need to cause VM Exits when EPT |
2952 | enabled */ | |
5fff7d27 GN |
2953 | _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING | |
2954 | CPU_BASED_CR3_STORE_EXITING | | |
2955 | CPU_BASED_INVLPG_EXITING); | |
d56f546d SY |
2956 | rdmsr(MSR_IA32_VMX_EPT_VPID_CAP, |
2957 | vmx_capability.ept, vmx_capability.vpid); | |
2958 | } | |
1c3d14fe | 2959 | |
81908bf4 | 2960 | min = VM_EXIT_SAVE_DEBUG_CONTROLS; |
1c3d14fe YS |
2961 | #ifdef CONFIG_X86_64 |
2962 | min |= VM_EXIT_HOST_ADDR_SPACE_SIZE; | |
2963 | #endif | |
a547c6db | 2964 | opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT | |
da8999d3 | 2965 | VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS; |
1c3d14fe YS |
2966 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS, |
2967 | &_vmexit_control) < 0) | |
002c7f7c | 2968 | return -EIO; |
1c3d14fe | 2969 | |
01e439be YZ |
2970 | min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING; |
2971 | opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR; | |
2972 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS, | |
2973 | &_pin_based_exec_control) < 0) | |
2974 | return -EIO; | |
2975 | ||
2976 | if (!(_cpu_based_2nd_exec_control & | |
2977 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) || | |
2978 | !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT)) | |
2979 | _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR; | |
2980 | ||
c845f9c6 | 2981 | min = VM_ENTRY_LOAD_DEBUG_CONTROLS; |
da8999d3 | 2982 | opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS; |
1c3d14fe YS |
2983 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS, |
2984 | &_vmentry_control) < 0) | |
002c7f7c | 2985 | return -EIO; |
6aa8b732 | 2986 | |
c68876fd | 2987 | rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high); |
1c3d14fe YS |
2988 | |
2989 | /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */ | |
2990 | if ((vmx_msr_high & 0x1fff) > PAGE_SIZE) | |
002c7f7c | 2991 | return -EIO; |
1c3d14fe YS |
2992 | |
2993 | #ifdef CONFIG_X86_64 | |
2994 | /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */ | |
2995 | if (vmx_msr_high & (1u<<16)) | |
002c7f7c | 2996 | return -EIO; |
1c3d14fe YS |
2997 | #endif |
2998 | ||
2999 | /* Require Write-Back (WB) memory type for VMCS accesses. */ | |
3000 | if (((vmx_msr_high >> 18) & 15) != 6) | |
002c7f7c | 3001 | return -EIO; |
1c3d14fe | 3002 | |
002c7f7c YS |
3003 | vmcs_conf->size = vmx_msr_high & 0x1fff; |
3004 | vmcs_conf->order = get_order(vmcs_config.size); | |
3005 | vmcs_conf->revision_id = vmx_msr_low; | |
1c3d14fe | 3006 | |
002c7f7c YS |
3007 | vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control; |
3008 | vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control; | |
f78e0e2e | 3009 | vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control; |
002c7f7c YS |
3010 | vmcs_conf->vmexit_ctrl = _vmexit_control; |
3011 | vmcs_conf->vmentry_ctrl = _vmentry_control; | |
1c3d14fe | 3012 | |
110312c8 AK |
3013 | cpu_has_load_ia32_efer = |
3014 | allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS, | |
3015 | VM_ENTRY_LOAD_IA32_EFER) | |
3016 | && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS, | |
3017 | VM_EXIT_LOAD_IA32_EFER); | |
3018 | ||
8bf00a52 GN |
3019 | cpu_has_load_perf_global_ctrl = |
3020 | allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS, | |
3021 | VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) | |
3022 | && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS, | |
3023 | VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL); | |
3024 | ||
3025 | /* | |
3026 | * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL | |
3027 | * but due to arrata below it can't be used. Workaround is to use | |
3028 | * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL. | |
3029 | * | |
3030 | * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32] | |
3031 | * | |
3032 | * AAK155 (model 26) | |
3033 | * AAP115 (model 30) | |
3034 | * AAT100 (model 37) | |
3035 | * BC86,AAY89,BD102 (model 44) | |
3036 | * BA97 (model 46) | |
3037 | * | |
3038 | */ | |
3039 | if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) { | |
3040 | switch (boot_cpu_data.x86_model) { | |
3041 | case 26: | |
3042 | case 30: | |
3043 | case 37: | |
3044 | case 44: | |
3045 | case 46: | |
3046 | cpu_has_load_perf_global_ctrl = false; | |
3047 | printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL " | |
3048 | "does not work properly. Using workaround\n"); | |
3049 | break; | |
3050 | default: | |
3051 | break; | |
3052 | } | |
3053 | } | |
3054 | ||
20300099 WL |
3055 | if (cpu_has_xsaves) |
3056 | rdmsrl(MSR_IA32_XSS, host_xss); | |
3057 | ||
1c3d14fe | 3058 | return 0; |
c68876fd | 3059 | } |
6aa8b732 AK |
3060 | |
3061 | static struct vmcs *alloc_vmcs_cpu(int cpu) | |
3062 | { | |
3063 | int node = cpu_to_node(cpu); | |
3064 | struct page *pages; | |
3065 | struct vmcs *vmcs; | |
3066 | ||
6484eb3e | 3067 | pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order); |
6aa8b732 AK |
3068 | if (!pages) |
3069 | return NULL; | |
3070 | vmcs = page_address(pages); | |
1c3d14fe YS |
3071 | memset(vmcs, 0, vmcs_config.size); |
3072 | vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */ | |
6aa8b732 AK |
3073 | return vmcs; |
3074 | } | |
3075 | ||
3076 | static struct vmcs *alloc_vmcs(void) | |
3077 | { | |
d3b2c338 | 3078 | return alloc_vmcs_cpu(raw_smp_processor_id()); |
6aa8b732 AK |
3079 | } |
3080 | ||
3081 | static void free_vmcs(struct vmcs *vmcs) | |
3082 | { | |
1c3d14fe | 3083 | free_pages((unsigned long)vmcs, vmcs_config.order); |
6aa8b732 AK |
3084 | } |
3085 | ||
d462b819 NHE |
3086 | /* |
3087 | * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded | |
3088 | */ | |
3089 | static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs) | |
3090 | { | |
3091 | if (!loaded_vmcs->vmcs) | |
3092 | return; | |
3093 | loaded_vmcs_clear(loaded_vmcs); | |
3094 | free_vmcs(loaded_vmcs->vmcs); | |
3095 | loaded_vmcs->vmcs = NULL; | |
3096 | } | |
3097 | ||
39959588 | 3098 | static void free_kvm_area(void) |
6aa8b732 AK |
3099 | { |
3100 | int cpu; | |
3101 | ||
3230bb47 | 3102 | for_each_possible_cpu(cpu) { |
6aa8b732 | 3103 | free_vmcs(per_cpu(vmxarea, cpu)); |
3230bb47 ZA |
3104 | per_cpu(vmxarea, cpu) = NULL; |
3105 | } | |
6aa8b732 AK |
3106 | } |
3107 | ||
fe2b201b BD |
3108 | static void init_vmcs_shadow_fields(void) |
3109 | { | |
3110 | int i, j; | |
3111 | ||
3112 | /* No checks for read only fields yet */ | |
3113 | ||
3114 | for (i = j = 0; i < max_shadow_read_write_fields; i++) { | |
3115 | switch (shadow_read_write_fields[i]) { | |
3116 | case GUEST_BNDCFGS: | |
3117 | if (!vmx_mpx_supported()) | |
3118 | continue; | |
3119 | break; | |
3120 | default: | |
3121 | break; | |
3122 | } | |
3123 | ||
3124 | if (j < i) | |
3125 | shadow_read_write_fields[j] = | |
3126 | shadow_read_write_fields[i]; | |
3127 | j++; | |
3128 | } | |
3129 | max_shadow_read_write_fields = j; | |
3130 | ||
3131 | /* shadowed fields guest access without vmexit */ | |
3132 | for (i = 0; i < max_shadow_read_write_fields; i++) { | |
3133 | clear_bit(shadow_read_write_fields[i], | |
3134 | vmx_vmwrite_bitmap); | |
3135 | clear_bit(shadow_read_write_fields[i], | |
3136 | vmx_vmread_bitmap); | |
3137 | } | |
3138 | for (i = 0; i < max_shadow_read_only_fields; i++) | |
3139 | clear_bit(shadow_read_only_fields[i], | |
3140 | vmx_vmread_bitmap); | |
3141 | } | |
3142 | ||
6aa8b732 AK |
3143 | static __init int alloc_kvm_area(void) |
3144 | { | |
3145 | int cpu; | |
3146 | ||
3230bb47 | 3147 | for_each_possible_cpu(cpu) { |
6aa8b732 AK |
3148 | struct vmcs *vmcs; |
3149 | ||
3150 | vmcs = alloc_vmcs_cpu(cpu); | |
3151 | if (!vmcs) { | |
3152 | free_kvm_area(); | |
3153 | return -ENOMEM; | |
3154 | } | |
3155 | ||
3156 | per_cpu(vmxarea, cpu) = vmcs; | |
3157 | } | |
3158 | return 0; | |
3159 | } | |
3160 | ||
14168786 GN |
3161 | static bool emulation_required(struct kvm_vcpu *vcpu) |
3162 | { | |
3163 | return emulate_invalid_guest_state && !guest_state_valid(vcpu); | |
3164 | } | |
3165 | ||
91b0aa2c | 3166 | static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg, |
d99e4152 | 3167 | struct kvm_segment *save) |
6aa8b732 | 3168 | { |
d99e4152 GN |
3169 | if (!emulate_invalid_guest_state) { |
3170 | /* | |
3171 | * CS and SS RPL should be equal during guest entry according | |
3172 | * to VMX spec, but in reality it is not always so. Since vcpu | |
3173 | * is in the middle of the transition from real mode to | |
3174 | * protected mode it is safe to assume that RPL 0 is a good | |
3175 | * default value. | |
3176 | */ | |
3177 | if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS) | |
3178 | save->selector &= ~SELECTOR_RPL_MASK; | |
3179 | save->dpl = save->selector & SELECTOR_RPL_MASK; | |
3180 | save->s = 1; | |
6aa8b732 | 3181 | } |
d99e4152 | 3182 | vmx_set_segment(vcpu, save, seg); |
6aa8b732 AK |
3183 | } |
3184 | ||
3185 | static void enter_pmode(struct kvm_vcpu *vcpu) | |
3186 | { | |
3187 | unsigned long flags; | |
a89a8fb9 | 3188 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6aa8b732 | 3189 | |
d99e4152 GN |
3190 | /* |
3191 | * Update real mode segment cache. It may be not up-to-date if sement | |
3192 | * register was written while vcpu was in a guest mode. | |
3193 | */ | |
3194 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES); | |
3195 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS); | |
3196 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS); | |
3197 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS); | |
3198 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS); | |
3199 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS); | |
3200 | ||
7ffd92c5 | 3201 | vmx->rmode.vm86_active = 0; |
6aa8b732 | 3202 | |
2fb92db1 AK |
3203 | vmx_segment_cache_clear(vmx); |
3204 | ||
f5f7b2fe | 3205 | vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR); |
6aa8b732 AK |
3206 | |
3207 | flags = vmcs_readl(GUEST_RFLAGS); | |
78ac8b47 AK |
3208 | flags &= RMODE_GUEST_OWNED_EFLAGS_BITS; |
3209 | flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS; | |
6aa8b732 AK |
3210 | vmcs_writel(GUEST_RFLAGS, flags); |
3211 | ||
66aee91a RR |
3212 | vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) | |
3213 | (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME)); | |
6aa8b732 AK |
3214 | |
3215 | update_exception_bitmap(vcpu); | |
3216 | ||
91b0aa2c GN |
3217 | fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]); |
3218 | fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]); | |
3219 | fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]); | |
3220 | fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]); | |
3221 | fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]); | |
3222 | fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]); | |
6aa8b732 AK |
3223 | } |
3224 | ||
f5f7b2fe | 3225 | static void fix_rmode_seg(int seg, struct kvm_segment *save) |
6aa8b732 | 3226 | { |
772e0318 | 3227 | const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; |
d99e4152 GN |
3228 | struct kvm_segment var = *save; |
3229 | ||
3230 | var.dpl = 0x3; | |
3231 | if (seg == VCPU_SREG_CS) | |
3232 | var.type = 0x3; | |
3233 | ||
3234 | if (!emulate_invalid_guest_state) { | |
3235 | var.selector = var.base >> 4; | |
3236 | var.base = var.base & 0xffff0; | |
3237 | var.limit = 0xffff; | |
3238 | var.g = 0; | |
3239 | var.db = 0; | |
3240 | var.present = 1; | |
3241 | var.s = 1; | |
3242 | var.l = 0; | |
3243 | var.unusable = 0; | |
3244 | var.type = 0x3; | |
3245 | var.avl = 0; | |
3246 | if (save->base & 0xf) | |
3247 | printk_once(KERN_WARNING "kvm: segment base is not " | |
3248 | "paragraph aligned when entering " | |
3249 | "protected mode (seg=%d)", seg); | |
3250 | } | |
6aa8b732 | 3251 | |
d99e4152 GN |
3252 | vmcs_write16(sf->selector, var.selector); |
3253 | vmcs_write32(sf->base, var.base); | |
3254 | vmcs_write32(sf->limit, var.limit); | |
3255 | vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var)); | |
6aa8b732 AK |
3256 | } |
3257 | ||
3258 | static void enter_rmode(struct kvm_vcpu *vcpu) | |
3259 | { | |
3260 | unsigned long flags; | |
a89a8fb9 | 3261 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6aa8b732 | 3262 | |
f5f7b2fe AK |
3263 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR); |
3264 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES); | |
3265 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS); | |
3266 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS); | |
3267 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS); | |
c6ad1153 GN |
3268 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS); |
3269 | vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS); | |
f5f7b2fe | 3270 | |
7ffd92c5 | 3271 | vmx->rmode.vm86_active = 1; |
6aa8b732 | 3272 | |
776e58ea GN |
3273 | /* |
3274 | * Very old userspace does not call KVM_SET_TSS_ADDR before entering | |
4918c6ca | 3275 | * vcpu. Warn the user that an update is overdue. |
776e58ea | 3276 | */ |
4918c6ca | 3277 | if (!vcpu->kvm->arch.tss_addr) |
776e58ea GN |
3278 | printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be " |
3279 | "called before entering vcpu\n"); | |
776e58ea | 3280 | |
2fb92db1 AK |
3281 | vmx_segment_cache_clear(vmx); |
3282 | ||
4918c6ca | 3283 | vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr); |
6aa8b732 | 3284 | vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1); |
6aa8b732 AK |
3285 | vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); |
3286 | ||
3287 | flags = vmcs_readl(GUEST_RFLAGS); | |
78ac8b47 | 3288 | vmx->rmode.save_rflags = flags; |
6aa8b732 | 3289 | |
053de044 | 3290 | flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; |
6aa8b732 AK |
3291 | |
3292 | vmcs_writel(GUEST_RFLAGS, flags); | |
66aee91a | 3293 | vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME); |
6aa8b732 AK |
3294 | update_exception_bitmap(vcpu); |
3295 | ||
d99e4152 GN |
3296 | fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]); |
3297 | fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]); | |
3298 | fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]); | |
3299 | fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]); | |
3300 | fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]); | |
3301 | fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]); | |
b246dd5d | 3302 | |
8668a3c4 | 3303 | kvm_mmu_reset_context(vcpu); |
6aa8b732 AK |
3304 | } |
3305 | ||
401d10de AS |
3306 | static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer) |
3307 | { | |
3308 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
26bb0981 AK |
3309 | struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER); |
3310 | ||
3311 | if (!msr) | |
3312 | return; | |
401d10de | 3313 | |
44ea2b17 AK |
3314 | /* |
3315 | * Force kernel_gs_base reloading before EFER changes, as control | |
3316 | * of this msr depends on is_long_mode(). | |
3317 | */ | |
3318 | vmx_load_host_state(to_vmx(vcpu)); | |
f6801dff | 3319 | vcpu->arch.efer = efer; |
401d10de | 3320 | if (efer & EFER_LMA) { |
2961e876 | 3321 | vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); |
401d10de AS |
3322 | msr->data = efer; |
3323 | } else { | |
2961e876 | 3324 | vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); |
401d10de AS |
3325 | |
3326 | msr->data = efer & ~EFER_LME; | |
3327 | } | |
3328 | setup_msrs(vmx); | |
3329 | } | |
3330 | ||
05b3e0c2 | 3331 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
3332 | |
3333 | static void enter_lmode(struct kvm_vcpu *vcpu) | |
3334 | { | |
3335 | u32 guest_tr_ar; | |
3336 | ||
2fb92db1 AK |
3337 | vmx_segment_cache_clear(to_vmx(vcpu)); |
3338 | ||
6aa8b732 AK |
3339 | guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES); |
3340 | if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) { | |
bd80158a JK |
3341 | pr_debug_ratelimited("%s: tss fixup for long mode. \n", |
3342 | __func__); | |
6aa8b732 AK |
3343 | vmcs_write32(GUEST_TR_AR_BYTES, |
3344 | (guest_tr_ar & ~AR_TYPE_MASK) | |
3345 | | AR_TYPE_BUSY_64_TSS); | |
3346 | } | |
da38f438 | 3347 | vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA); |
6aa8b732 AK |
3348 | } |
3349 | ||
3350 | static void exit_lmode(struct kvm_vcpu *vcpu) | |
3351 | { | |
2961e876 | 3352 | vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); |
da38f438 | 3353 | vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA); |
6aa8b732 AK |
3354 | } |
3355 | ||
3356 | #endif | |
3357 | ||
2384d2b3 SY |
3358 | static void vmx_flush_tlb(struct kvm_vcpu *vcpu) |
3359 | { | |
b9d762fa | 3360 | vpid_sync_context(to_vmx(vcpu)); |
dd180b3e XG |
3361 | if (enable_ept) { |
3362 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) | |
3363 | return; | |
4e1096d2 | 3364 | ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa)); |
dd180b3e | 3365 | } |
2384d2b3 SY |
3366 | } |
3367 | ||
e8467fda AK |
3368 | static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu) |
3369 | { | |
3370 | ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits; | |
3371 | ||
3372 | vcpu->arch.cr0 &= ~cr0_guest_owned_bits; | |
3373 | vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits; | |
3374 | } | |
3375 | ||
aff48baa AK |
3376 | static void vmx_decache_cr3(struct kvm_vcpu *vcpu) |
3377 | { | |
3378 | if (enable_ept && is_paging(vcpu)) | |
3379 | vcpu->arch.cr3 = vmcs_readl(GUEST_CR3); | |
3380 | __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); | |
3381 | } | |
3382 | ||
25c4c276 | 3383 | static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 | 3384 | { |
fc78f519 AK |
3385 | ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits; |
3386 | ||
3387 | vcpu->arch.cr4 &= ~cr4_guest_owned_bits; | |
3388 | vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits; | |
399badf3 AK |
3389 | } |
3390 | ||
1439442c SY |
3391 | static void ept_load_pdptrs(struct kvm_vcpu *vcpu) |
3392 | { | |
d0d538b9 GN |
3393 | struct kvm_mmu *mmu = vcpu->arch.walk_mmu; |
3394 | ||
6de4f3ad AK |
3395 | if (!test_bit(VCPU_EXREG_PDPTR, |
3396 | (unsigned long *)&vcpu->arch.regs_dirty)) | |
3397 | return; | |
3398 | ||
1439442c | 3399 | if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) { |
d0d538b9 GN |
3400 | vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]); |
3401 | vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]); | |
3402 | vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]); | |
3403 | vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]); | |
1439442c SY |
3404 | } |
3405 | } | |
3406 | ||
8f5d549f AK |
3407 | static void ept_save_pdptrs(struct kvm_vcpu *vcpu) |
3408 | { | |
d0d538b9 GN |
3409 | struct kvm_mmu *mmu = vcpu->arch.walk_mmu; |
3410 | ||
8f5d549f | 3411 | if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) { |
d0d538b9 GN |
3412 | mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0); |
3413 | mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1); | |
3414 | mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2); | |
3415 | mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3); | |
8f5d549f | 3416 | } |
6de4f3ad AK |
3417 | |
3418 | __set_bit(VCPU_EXREG_PDPTR, | |
3419 | (unsigned long *)&vcpu->arch.regs_avail); | |
3420 | __set_bit(VCPU_EXREG_PDPTR, | |
3421 | (unsigned long *)&vcpu->arch.regs_dirty); | |
8f5d549f AK |
3422 | } |
3423 | ||
5e1746d6 | 3424 | static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); |
1439442c SY |
3425 | |
3426 | static void ept_update_paging_mode_cr0(unsigned long *hw_cr0, | |
3427 | unsigned long cr0, | |
3428 | struct kvm_vcpu *vcpu) | |
3429 | { | |
5233dd51 MT |
3430 | if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail)) |
3431 | vmx_decache_cr3(vcpu); | |
1439442c SY |
3432 | if (!(cr0 & X86_CR0_PG)) { |
3433 | /* From paging/starting to nonpaging */ | |
3434 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, | |
65267ea1 | 3435 | vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) | |
1439442c SY |
3436 | (CPU_BASED_CR3_LOAD_EXITING | |
3437 | CPU_BASED_CR3_STORE_EXITING)); | |
3438 | vcpu->arch.cr0 = cr0; | |
fc78f519 | 3439 | vmx_set_cr4(vcpu, kvm_read_cr4(vcpu)); |
1439442c SY |
3440 | } else if (!is_paging(vcpu)) { |
3441 | /* From nonpaging to paging */ | |
3442 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, | |
65267ea1 | 3443 | vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) & |
1439442c SY |
3444 | ~(CPU_BASED_CR3_LOAD_EXITING | |
3445 | CPU_BASED_CR3_STORE_EXITING)); | |
3446 | vcpu->arch.cr0 = cr0; | |
fc78f519 | 3447 | vmx_set_cr4(vcpu, kvm_read_cr4(vcpu)); |
1439442c | 3448 | } |
95eb84a7 SY |
3449 | |
3450 | if (!(cr0 & X86_CR0_WP)) | |
3451 | *hw_cr0 &= ~X86_CR0_WP; | |
1439442c SY |
3452 | } |
3453 | ||
6aa8b732 AK |
3454 | static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
3455 | { | |
7ffd92c5 | 3456 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
3a624e29 NK |
3457 | unsigned long hw_cr0; |
3458 | ||
5037878e | 3459 | hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK); |
3a624e29 | 3460 | if (enable_unrestricted_guest) |
5037878e | 3461 | hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST; |
218e763f | 3462 | else { |
5037878e | 3463 | hw_cr0 |= KVM_VM_CR0_ALWAYS_ON; |
1439442c | 3464 | |
218e763f GN |
3465 | if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE)) |
3466 | enter_pmode(vcpu); | |
6aa8b732 | 3467 | |
218e763f GN |
3468 | if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE)) |
3469 | enter_rmode(vcpu); | |
3470 | } | |
6aa8b732 | 3471 | |
05b3e0c2 | 3472 | #ifdef CONFIG_X86_64 |
f6801dff | 3473 | if (vcpu->arch.efer & EFER_LME) { |
707d92fa | 3474 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) |
6aa8b732 | 3475 | enter_lmode(vcpu); |
707d92fa | 3476 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) |
6aa8b732 AK |
3477 | exit_lmode(vcpu); |
3478 | } | |
3479 | #endif | |
3480 | ||
089d034e | 3481 | if (enable_ept) |
1439442c SY |
3482 | ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu); |
3483 | ||
02daab21 | 3484 | if (!vcpu->fpu_active) |
81231c69 | 3485 | hw_cr0 |= X86_CR0_TS | X86_CR0_MP; |
02daab21 | 3486 | |
6aa8b732 | 3487 | vmcs_writel(CR0_READ_SHADOW, cr0); |
1439442c | 3488 | vmcs_writel(GUEST_CR0, hw_cr0); |
ad312c7c | 3489 | vcpu->arch.cr0 = cr0; |
14168786 GN |
3490 | |
3491 | /* depends on vcpu->arch.cr0 to be set to a new value */ | |
3492 | vmx->emulation_required = emulation_required(vcpu); | |
6aa8b732 AK |
3493 | } |
3494 | ||
1439442c SY |
3495 | static u64 construct_eptp(unsigned long root_hpa) |
3496 | { | |
3497 | u64 eptp; | |
3498 | ||
3499 | /* TODO write the value reading from MSR */ | |
3500 | eptp = VMX_EPT_DEFAULT_MT | | |
3501 | VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT; | |
b38f9934 XH |
3502 | if (enable_ept_ad_bits) |
3503 | eptp |= VMX_EPT_AD_ENABLE_BIT; | |
1439442c SY |
3504 | eptp |= (root_hpa & PAGE_MASK); |
3505 | ||
3506 | return eptp; | |
3507 | } | |
3508 | ||
6aa8b732 AK |
3509 | static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) |
3510 | { | |
1439442c SY |
3511 | unsigned long guest_cr3; |
3512 | u64 eptp; | |
3513 | ||
3514 | guest_cr3 = cr3; | |
089d034e | 3515 | if (enable_ept) { |
1439442c SY |
3516 | eptp = construct_eptp(cr3); |
3517 | vmcs_write64(EPT_POINTER, eptp); | |
59ab5a8f JK |
3518 | if (is_paging(vcpu) || is_guest_mode(vcpu)) |
3519 | guest_cr3 = kvm_read_cr3(vcpu); | |
3520 | else | |
3521 | guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr; | |
7c93be44 | 3522 | ept_load_pdptrs(vcpu); |
1439442c SY |
3523 | } |
3524 | ||
2384d2b3 | 3525 | vmx_flush_tlb(vcpu); |
1439442c | 3526 | vmcs_writel(GUEST_CR3, guest_cr3); |
6aa8b732 AK |
3527 | } |
3528 | ||
5e1746d6 | 3529 | static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
6aa8b732 | 3530 | { |
7ffd92c5 | 3531 | unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ? |
1439442c SY |
3532 | KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON); |
3533 | ||
5e1746d6 NHE |
3534 | if (cr4 & X86_CR4_VMXE) { |
3535 | /* | |
3536 | * To use VMXON (and later other VMX instructions), a guest | |
3537 | * must first be able to turn on cr4.VMXE (see handle_vmon()). | |
3538 | * So basically the check on whether to allow nested VMX | |
3539 | * is here. | |
3540 | */ | |
3541 | if (!nested_vmx_allowed(vcpu)) | |
3542 | return 1; | |
1a0d74e6 JK |
3543 | } |
3544 | if (to_vmx(vcpu)->nested.vmxon && | |
3545 | ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) | |
5e1746d6 NHE |
3546 | return 1; |
3547 | ||
ad312c7c | 3548 | vcpu->arch.cr4 = cr4; |
bc23008b AK |
3549 | if (enable_ept) { |
3550 | if (!is_paging(vcpu)) { | |
3551 | hw_cr4 &= ~X86_CR4_PAE; | |
3552 | hw_cr4 |= X86_CR4_PSE; | |
c08800a5 | 3553 | /* |
e1e746b3 FW |
3554 | * SMEP/SMAP is disabled if CPU is in non-paging mode |
3555 | * in hardware. However KVM always uses paging mode to | |
c08800a5 | 3556 | * emulate guest non-paging mode with TDP. |
e1e746b3 FW |
3557 | * To emulate this behavior, SMEP/SMAP needs to be |
3558 | * manually disabled when guest switches to non-paging | |
3559 | * mode. | |
c08800a5 | 3560 | */ |
e1e746b3 | 3561 | hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP); |
bc23008b AK |
3562 | } else if (!(cr4 & X86_CR4_PAE)) { |
3563 | hw_cr4 &= ~X86_CR4_PAE; | |
3564 | } | |
3565 | } | |
1439442c SY |
3566 | |
3567 | vmcs_writel(CR4_READ_SHADOW, cr4); | |
3568 | vmcs_writel(GUEST_CR4, hw_cr4); | |
5e1746d6 | 3569 | return 0; |
6aa8b732 AK |
3570 | } |
3571 | ||
6aa8b732 AK |
3572 | static void vmx_get_segment(struct kvm_vcpu *vcpu, |
3573 | struct kvm_segment *var, int seg) | |
3574 | { | |
a9179499 | 3575 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6aa8b732 AK |
3576 | u32 ar; |
3577 | ||
c6ad1153 | 3578 | if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) { |
f5f7b2fe | 3579 | *var = vmx->rmode.segs[seg]; |
a9179499 | 3580 | if (seg == VCPU_SREG_TR |
2fb92db1 | 3581 | || var->selector == vmx_read_guest_seg_selector(vmx, seg)) |
f5f7b2fe | 3582 | return; |
1390a28b AK |
3583 | var->base = vmx_read_guest_seg_base(vmx, seg); |
3584 | var->selector = vmx_read_guest_seg_selector(vmx, seg); | |
3585 | return; | |
a9179499 | 3586 | } |
2fb92db1 AK |
3587 | var->base = vmx_read_guest_seg_base(vmx, seg); |
3588 | var->limit = vmx_read_guest_seg_limit(vmx, seg); | |
3589 | var->selector = vmx_read_guest_seg_selector(vmx, seg); | |
3590 | ar = vmx_read_guest_seg_ar(vmx, seg); | |
03617c18 | 3591 | var->unusable = (ar >> 16) & 1; |
6aa8b732 AK |
3592 | var->type = ar & 15; |
3593 | var->s = (ar >> 4) & 1; | |
3594 | var->dpl = (ar >> 5) & 3; | |
03617c18 GN |
3595 | /* |
3596 | * Some userspaces do not preserve unusable property. Since usable | |
3597 | * segment has to be present according to VMX spec we can use present | |
3598 | * property to amend userspace bug by making unusable segment always | |
3599 | * nonpresent. vmx_segment_access_rights() already marks nonpresent | |
3600 | * segment as unusable. | |
3601 | */ | |
3602 | var->present = !var->unusable; | |
6aa8b732 AK |
3603 | var->avl = (ar >> 12) & 1; |
3604 | var->l = (ar >> 13) & 1; | |
3605 | var->db = (ar >> 14) & 1; | |
3606 | var->g = (ar >> 15) & 1; | |
6aa8b732 AK |
3607 | } |
3608 | ||
a9179499 AK |
3609 | static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg) |
3610 | { | |
a9179499 AK |
3611 | struct kvm_segment s; |
3612 | ||
3613 | if (to_vmx(vcpu)->rmode.vm86_active) { | |
3614 | vmx_get_segment(vcpu, &s, seg); | |
3615 | return s.base; | |
3616 | } | |
2fb92db1 | 3617 | return vmx_read_guest_seg_base(to_vmx(vcpu), seg); |
a9179499 AK |
3618 | } |
3619 | ||
b09408d0 | 3620 | static int vmx_get_cpl(struct kvm_vcpu *vcpu) |
2e4d2653 | 3621 | { |
b09408d0 MT |
3622 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
3623 | ||
ae9fedc7 | 3624 | if (unlikely(vmx->rmode.vm86_active)) |
2e4d2653 | 3625 | return 0; |
ae9fedc7 PB |
3626 | else { |
3627 | int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS); | |
3628 | return AR_DPL(ar); | |
69c73028 | 3629 | } |
69c73028 AK |
3630 | } |
3631 | ||
653e3108 | 3632 | static u32 vmx_segment_access_rights(struct kvm_segment *var) |
6aa8b732 | 3633 | { |
6aa8b732 AK |
3634 | u32 ar; |
3635 | ||
f0495f9b | 3636 | if (var->unusable || !var->present) |
6aa8b732 AK |
3637 | ar = 1 << 16; |
3638 | else { | |
3639 | ar = var->type & 15; | |
3640 | ar |= (var->s & 1) << 4; | |
3641 | ar |= (var->dpl & 3) << 5; | |
3642 | ar |= (var->present & 1) << 7; | |
3643 | ar |= (var->avl & 1) << 12; | |
3644 | ar |= (var->l & 1) << 13; | |
3645 | ar |= (var->db & 1) << 14; | |
3646 | ar |= (var->g & 1) << 15; | |
3647 | } | |
653e3108 AK |
3648 | |
3649 | return ar; | |
3650 | } | |
3651 | ||
3652 | static void vmx_set_segment(struct kvm_vcpu *vcpu, | |
3653 | struct kvm_segment *var, int seg) | |
3654 | { | |
7ffd92c5 | 3655 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
772e0318 | 3656 | const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; |
653e3108 | 3657 | |
2fb92db1 AK |
3658 | vmx_segment_cache_clear(vmx); |
3659 | ||
1ecd50a9 GN |
3660 | if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) { |
3661 | vmx->rmode.segs[seg] = *var; | |
3662 | if (seg == VCPU_SREG_TR) | |
3663 | vmcs_write16(sf->selector, var->selector); | |
3664 | else if (var->s) | |
3665 | fix_rmode_seg(seg, &vmx->rmode.segs[seg]); | |
d99e4152 | 3666 | goto out; |
653e3108 | 3667 | } |
1ecd50a9 | 3668 | |
653e3108 AK |
3669 | vmcs_writel(sf->base, var->base); |
3670 | vmcs_write32(sf->limit, var->limit); | |
3671 | vmcs_write16(sf->selector, var->selector); | |
3a624e29 NK |
3672 | |
3673 | /* | |
3674 | * Fix the "Accessed" bit in AR field of segment registers for older | |
3675 | * qemu binaries. | |
3676 | * IA32 arch specifies that at the time of processor reset the | |
3677 | * "Accessed" bit in the AR field of segment registers is 1. And qemu | |
0fa06071 | 3678 | * is setting it to 0 in the userland code. This causes invalid guest |
3a624e29 NK |
3679 | * state vmexit when "unrestricted guest" mode is turned on. |
3680 | * Fix for this setup issue in cpu_reset is being pushed in the qemu | |
3681 | * tree. Newer qemu binaries with that qemu fix would not need this | |
3682 | * kvm hack. | |
3683 | */ | |
3684 | if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR)) | |
f924d66d | 3685 | var->type |= 0x1; /* Accessed */ |
3a624e29 | 3686 | |
f924d66d | 3687 | vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var)); |
d99e4152 GN |
3688 | |
3689 | out: | |
98eb2f8b | 3690 | vmx->emulation_required = emulation_required(vcpu); |
6aa8b732 AK |
3691 | } |
3692 | ||
6aa8b732 AK |
3693 | static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) |
3694 | { | |
2fb92db1 | 3695 | u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS); |
6aa8b732 AK |
3696 | |
3697 | *db = (ar >> 14) & 1; | |
3698 | *l = (ar >> 13) & 1; | |
3699 | } | |
3700 | ||
89a27f4d | 3701 | static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 3702 | { |
89a27f4d GN |
3703 | dt->size = vmcs_read32(GUEST_IDTR_LIMIT); |
3704 | dt->address = vmcs_readl(GUEST_IDTR_BASE); | |
6aa8b732 AK |
3705 | } |
3706 | ||
89a27f4d | 3707 | static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 3708 | { |
89a27f4d GN |
3709 | vmcs_write32(GUEST_IDTR_LIMIT, dt->size); |
3710 | vmcs_writel(GUEST_IDTR_BASE, dt->address); | |
6aa8b732 AK |
3711 | } |
3712 | ||
89a27f4d | 3713 | static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 3714 | { |
89a27f4d GN |
3715 | dt->size = vmcs_read32(GUEST_GDTR_LIMIT); |
3716 | dt->address = vmcs_readl(GUEST_GDTR_BASE); | |
6aa8b732 AK |
3717 | } |
3718 | ||
89a27f4d | 3719 | static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 3720 | { |
89a27f4d GN |
3721 | vmcs_write32(GUEST_GDTR_LIMIT, dt->size); |
3722 | vmcs_writel(GUEST_GDTR_BASE, dt->address); | |
6aa8b732 AK |
3723 | } |
3724 | ||
648dfaa7 MG |
3725 | static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg) |
3726 | { | |
3727 | struct kvm_segment var; | |
3728 | u32 ar; | |
3729 | ||
3730 | vmx_get_segment(vcpu, &var, seg); | |
07f42f5f | 3731 | var.dpl = 0x3; |
0647f4aa GN |
3732 | if (seg == VCPU_SREG_CS) |
3733 | var.type = 0x3; | |
648dfaa7 MG |
3734 | ar = vmx_segment_access_rights(&var); |
3735 | ||
3736 | if (var.base != (var.selector << 4)) | |
3737 | return false; | |
89efbed0 | 3738 | if (var.limit != 0xffff) |
648dfaa7 | 3739 | return false; |
07f42f5f | 3740 | if (ar != 0xf3) |
648dfaa7 MG |
3741 | return false; |
3742 | ||
3743 | return true; | |
3744 | } | |
3745 | ||
3746 | static bool code_segment_valid(struct kvm_vcpu *vcpu) | |
3747 | { | |
3748 | struct kvm_segment cs; | |
3749 | unsigned int cs_rpl; | |
3750 | ||
3751 | vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
3752 | cs_rpl = cs.selector & SELECTOR_RPL_MASK; | |
3753 | ||
1872a3f4 AK |
3754 | if (cs.unusable) |
3755 | return false; | |
648dfaa7 MG |
3756 | if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK)) |
3757 | return false; | |
3758 | if (!cs.s) | |
3759 | return false; | |
1872a3f4 | 3760 | if (cs.type & AR_TYPE_WRITEABLE_MASK) { |
648dfaa7 MG |
3761 | if (cs.dpl > cs_rpl) |
3762 | return false; | |
1872a3f4 | 3763 | } else { |
648dfaa7 MG |
3764 | if (cs.dpl != cs_rpl) |
3765 | return false; | |
3766 | } | |
3767 | if (!cs.present) | |
3768 | return false; | |
3769 | ||
3770 | /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */ | |
3771 | return true; | |
3772 | } | |
3773 | ||
3774 | static bool stack_segment_valid(struct kvm_vcpu *vcpu) | |
3775 | { | |
3776 | struct kvm_segment ss; | |
3777 | unsigned int ss_rpl; | |
3778 | ||
3779 | vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); | |
3780 | ss_rpl = ss.selector & SELECTOR_RPL_MASK; | |
3781 | ||
1872a3f4 AK |
3782 | if (ss.unusable) |
3783 | return true; | |
3784 | if (ss.type != 3 && ss.type != 7) | |
648dfaa7 MG |
3785 | return false; |
3786 | if (!ss.s) | |
3787 | return false; | |
3788 | if (ss.dpl != ss_rpl) /* DPL != RPL */ | |
3789 | return false; | |
3790 | if (!ss.present) | |
3791 | return false; | |
3792 | ||
3793 | return true; | |
3794 | } | |
3795 | ||
3796 | static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg) | |
3797 | { | |
3798 | struct kvm_segment var; | |
3799 | unsigned int rpl; | |
3800 | ||
3801 | vmx_get_segment(vcpu, &var, seg); | |
3802 | rpl = var.selector & SELECTOR_RPL_MASK; | |
3803 | ||
1872a3f4 AK |
3804 | if (var.unusable) |
3805 | return true; | |
648dfaa7 MG |
3806 | if (!var.s) |
3807 | return false; | |
3808 | if (!var.present) | |
3809 | return false; | |
3810 | if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) { | |
3811 | if (var.dpl < rpl) /* DPL < RPL */ | |
3812 | return false; | |
3813 | } | |
3814 | ||
3815 | /* TODO: Add other members to kvm_segment_field to allow checking for other access | |
3816 | * rights flags | |
3817 | */ | |
3818 | return true; | |
3819 | } | |
3820 | ||
3821 | static bool tr_valid(struct kvm_vcpu *vcpu) | |
3822 | { | |
3823 | struct kvm_segment tr; | |
3824 | ||
3825 | vmx_get_segment(vcpu, &tr, VCPU_SREG_TR); | |
3826 | ||
1872a3f4 AK |
3827 | if (tr.unusable) |
3828 | return false; | |
648dfaa7 MG |
3829 | if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */ |
3830 | return false; | |
1872a3f4 | 3831 | if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */ |
648dfaa7 MG |
3832 | return false; |
3833 | if (!tr.present) | |
3834 | return false; | |
3835 | ||
3836 | return true; | |
3837 | } | |
3838 | ||
3839 | static bool ldtr_valid(struct kvm_vcpu *vcpu) | |
3840 | { | |
3841 | struct kvm_segment ldtr; | |
3842 | ||
3843 | vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR); | |
3844 | ||
1872a3f4 AK |
3845 | if (ldtr.unusable) |
3846 | return true; | |
648dfaa7 MG |
3847 | if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */ |
3848 | return false; | |
3849 | if (ldtr.type != 2) | |
3850 | return false; | |
3851 | if (!ldtr.present) | |
3852 | return false; | |
3853 | ||
3854 | return true; | |
3855 | } | |
3856 | ||
3857 | static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu) | |
3858 | { | |
3859 | struct kvm_segment cs, ss; | |
3860 | ||
3861 | vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
3862 | vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); | |
3863 | ||
3864 | return ((cs.selector & SELECTOR_RPL_MASK) == | |
3865 | (ss.selector & SELECTOR_RPL_MASK)); | |
3866 | } | |
3867 | ||
3868 | /* | |
3869 | * Check if guest state is valid. Returns true if valid, false if | |
3870 | * not. | |
3871 | * We assume that registers are always usable | |
3872 | */ | |
3873 | static bool guest_state_valid(struct kvm_vcpu *vcpu) | |
3874 | { | |
c5e97c80 GN |
3875 | if (enable_unrestricted_guest) |
3876 | return true; | |
3877 | ||
648dfaa7 | 3878 | /* real mode guest state checks */ |
f13882d8 | 3879 | if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) { |
648dfaa7 MG |
3880 | if (!rmode_segment_valid(vcpu, VCPU_SREG_CS)) |
3881 | return false; | |
3882 | if (!rmode_segment_valid(vcpu, VCPU_SREG_SS)) | |
3883 | return false; | |
3884 | if (!rmode_segment_valid(vcpu, VCPU_SREG_DS)) | |
3885 | return false; | |
3886 | if (!rmode_segment_valid(vcpu, VCPU_SREG_ES)) | |
3887 | return false; | |
3888 | if (!rmode_segment_valid(vcpu, VCPU_SREG_FS)) | |
3889 | return false; | |
3890 | if (!rmode_segment_valid(vcpu, VCPU_SREG_GS)) | |
3891 | return false; | |
3892 | } else { | |
3893 | /* protected mode guest state checks */ | |
3894 | if (!cs_ss_rpl_check(vcpu)) | |
3895 | return false; | |
3896 | if (!code_segment_valid(vcpu)) | |
3897 | return false; | |
3898 | if (!stack_segment_valid(vcpu)) | |
3899 | return false; | |
3900 | if (!data_segment_valid(vcpu, VCPU_SREG_DS)) | |
3901 | return false; | |
3902 | if (!data_segment_valid(vcpu, VCPU_SREG_ES)) | |
3903 | return false; | |
3904 | if (!data_segment_valid(vcpu, VCPU_SREG_FS)) | |
3905 | return false; | |
3906 | if (!data_segment_valid(vcpu, VCPU_SREG_GS)) | |
3907 | return false; | |
3908 | if (!tr_valid(vcpu)) | |
3909 | return false; | |
3910 | if (!ldtr_valid(vcpu)) | |
3911 | return false; | |
3912 | } | |
3913 | /* TODO: | |
3914 | * - Add checks on RIP | |
3915 | * - Add checks on RFLAGS | |
3916 | */ | |
3917 | ||
3918 | return true; | |
3919 | } | |
3920 | ||
d77c26fc | 3921 | static int init_rmode_tss(struct kvm *kvm) |
6aa8b732 | 3922 | { |
40dcaa9f | 3923 | gfn_t fn; |
195aefde | 3924 | u16 data = 0; |
1f755a82 | 3925 | int idx, r; |
6aa8b732 | 3926 | |
40dcaa9f | 3927 | idx = srcu_read_lock(&kvm->srcu); |
4918c6ca | 3928 | fn = kvm->arch.tss_addr >> PAGE_SHIFT; |
195aefde IE |
3929 | r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); |
3930 | if (r < 0) | |
10589a46 | 3931 | goto out; |
195aefde | 3932 | data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE; |
464d17c8 SY |
3933 | r = kvm_write_guest_page(kvm, fn++, &data, |
3934 | TSS_IOPB_BASE_OFFSET, sizeof(u16)); | |
195aefde | 3935 | if (r < 0) |
10589a46 | 3936 | goto out; |
195aefde IE |
3937 | r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE); |
3938 | if (r < 0) | |
10589a46 | 3939 | goto out; |
195aefde IE |
3940 | r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); |
3941 | if (r < 0) | |
10589a46 | 3942 | goto out; |
195aefde | 3943 | data = ~0; |
10589a46 MT |
3944 | r = kvm_write_guest_page(kvm, fn, &data, |
3945 | RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1, | |
3946 | sizeof(u8)); | |
10589a46 | 3947 | out: |
40dcaa9f | 3948 | srcu_read_unlock(&kvm->srcu, idx); |
1f755a82 | 3949 | return r; |
6aa8b732 AK |
3950 | } |
3951 | ||
b7ebfb05 SY |
3952 | static int init_rmode_identity_map(struct kvm *kvm) |
3953 | { | |
f51770ed | 3954 | int i, idx, r = 0; |
b7ebfb05 SY |
3955 | pfn_t identity_map_pfn; |
3956 | u32 tmp; | |
3957 | ||
089d034e | 3958 | if (!enable_ept) |
f51770ed | 3959 | return 0; |
a255d479 TC |
3960 | |
3961 | /* Protect kvm->arch.ept_identity_pagetable_done. */ | |
3962 | mutex_lock(&kvm->slots_lock); | |
3963 | ||
f51770ed | 3964 | if (likely(kvm->arch.ept_identity_pagetable_done)) |
a255d479 | 3965 | goto out2; |
a255d479 | 3966 | |
b927a3ce | 3967 | identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT; |
a255d479 TC |
3968 | |
3969 | r = alloc_identity_pagetable(kvm); | |
f51770ed | 3970 | if (r < 0) |
a255d479 TC |
3971 | goto out2; |
3972 | ||
40dcaa9f | 3973 | idx = srcu_read_lock(&kvm->srcu); |
b7ebfb05 SY |
3974 | r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE); |
3975 | if (r < 0) | |
3976 | goto out; | |
3977 | /* Set up identity-mapping pagetable for EPT in real mode */ | |
3978 | for (i = 0; i < PT32_ENT_PER_PAGE; i++) { | |
3979 | tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | | |
3980 | _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE); | |
3981 | r = kvm_write_guest_page(kvm, identity_map_pfn, | |
3982 | &tmp, i * sizeof(tmp), sizeof(tmp)); | |
3983 | if (r < 0) | |
3984 | goto out; | |
3985 | } | |
3986 | kvm->arch.ept_identity_pagetable_done = true; | |
f51770ed | 3987 | |
b7ebfb05 | 3988 | out: |
40dcaa9f | 3989 | srcu_read_unlock(&kvm->srcu, idx); |
a255d479 TC |
3990 | |
3991 | out2: | |
3992 | mutex_unlock(&kvm->slots_lock); | |
f51770ed | 3993 | return r; |
b7ebfb05 SY |
3994 | } |
3995 | ||
6aa8b732 AK |
3996 | static void seg_setup(int seg) |
3997 | { | |
772e0318 | 3998 | const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; |
3a624e29 | 3999 | unsigned int ar; |
6aa8b732 AK |
4000 | |
4001 | vmcs_write16(sf->selector, 0); | |
4002 | vmcs_writel(sf->base, 0); | |
4003 | vmcs_write32(sf->limit, 0xffff); | |
d54d07b2 GN |
4004 | ar = 0x93; |
4005 | if (seg == VCPU_SREG_CS) | |
4006 | ar |= 0x08; /* code segment */ | |
3a624e29 NK |
4007 | |
4008 | vmcs_write32(sf->ar_bytes, ar); | |
6aa8b732 AK |
4009 | } |
4010 | ||
f78e0e2e SY |
4011 | static int alloc_apic_access_page(struct kvm *kvm) |
4012 | { | |
4484141a | 4013 | struct page *page; |
f78e0e2e SY |
4014 | struct kvm_userspace_memory_region kvm_userspace_mem; |
4015 | int r = 0; | |
4016 | ||
79fac95e | 4017 | mutex_lock(&kvm->slots_lock); |
c24ae0dc | 4018 | if (kvm->arch.apic_access_page_done) |
f78e0e2e SY |
4019 | goto out; |
4020 | kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT; | |
4021 | kvm_userspace_mem.flags = 0; | |
73a6d941 | 4022 | kvm_userspace_mem.guest_phys_addr = APIC_DEFAULT_PHYS_BASE; |
f78e0e2e | 4023 | kvm_userspace_mem.memory_size = PAGE_SIZE; |
47ae31e2 | 4024 | r = __kvm_set_memory_region(kvm, &kvm_userspace_mem); |
f78e0e2e SY |
4025 | if (r) |
4026 | goto out; | |
72dc67a6 | 4027 | |
73a6d941 | 4028 | page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); |
4484141a XG |
4029 | if (is_error_page(page)) { |
4030 | r = -EFAULT; | |
4031 | goto out; | |
4032 | } | |
4033 | ||
c24ae0dc TC |
4034 | /* |
4035 | * Do not pin the page in memory, so that memory hot-unplug | |
4036 | * is able to migrate it. | |
4037 | */ | |
4038 | put_page(page); | |
4039 | kvm->arch.apic_access_page_done = true; | |
f78e0e2e | 4040 | out: |
79fac95e | 4041 | mutex_unlock(&kvm->slots_lock); |
f78e0e2e SY |
4042 | return r; |
4043 | } | |
4044 | ||
b7ebfb05 SY |
4045 | static int alloc_identity_pagetable(struct kvm *kvm) |
4046 | { | |
a255d479 TC |
4047 | /* Called with kvm->slots_lock held. */ |
4048 | ||
b7ebfb05 SY |
4049 | struct kvm_userspace_memory_region kvm_userspace_mem; |
4050 | int r = 0; | |
4051 | ||
a255d479 TC |
4052 | BUG_ON(kvm->arch.ept_identity_pagetable_done); |
4053 | ||
b7ebfb05 SY |
4054 | kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT; |
4055 | kvm_userspace_mem.flags = 0; | |
b927a3ce SY |
4056 | kvm_userspace_mem.guest_phys_addr = |
4057 | kvm->arch.ept_identity_map_addr; | |
b7ebfb05 | 4058 | kvm_userspace_mem.memory_size = PAGE_SIZE; |
47ae31e2 | 4059 | r = __kvm_set_memory_region(kvm, &kvm_userspace_mem); |
b7ebfb05 | 4060 | |
b7ebfb05 SY |
4061 | return r; |
4062 | } | |
4063 | ||
2384d2b3 SY |
4064 | static void allocate_vpid(struct vcpu_vmx *vmx) |
4065 | { | |
4066 | int vpid; | |
4067 | ||
4068 | vmx->vpid = 0; | |
919818ab | 4069 | if (!enable_vpid) |
2384d2b3 SY |
4070 | return; |
4071 | spin_lock(&vmx_vpid_lock); | |
4072 | vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS); | |
4073 | if (vpid < VMX_NR_VPIDS) { | |
4074 | vmx->vpid = vpid; | |
4075 | __set_bit(vpid, vmx_vpid_bitmap); | |
4076 | } | |
4077 | spin_unlock(&vmx_vpid_lock); | |
4078 | } | |
4079 | ||
cdbecfc3 LJ |
4080 | static void free_vpid(struct vcpu_vmx *vmx) |
4081 | { | |
4082 | if (!enable_vpid) | |
4083 | return; | |
4084 | spin_lock(&vmx_vpid_lock); | |
4085 | if (vmx->vpid != 0) | |
4086 | __clear_bit(vmx->vpid, vmx_vpid_bitmap); | |
4087 | spin_unlock(&vmx_vpid_lock); | |
4088 | } | |
4089 | ||
8d14695f YZ |
4090 | #define MSR_TYPE_R 1 |
4091 | #define MSR_TYPE_W 2 | |
4092 | static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, | |
4093 | u32 msr, int type) | |
25c5f225 | 4094 | { |
3e7c73e9 | 4095 | int f = sizeof(unsigned long); |
25c5f225 SY |
4096 | |
4097 | if (!cpu_has_vmx_msr_bitmap()) | |
4098 | return; | |
4099 | ||
4100 | /* | |
4101 | * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals | |
4102 | * have the write-low and read-high bitmap offsets the wrong way round. | |
4103 | * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. | |
4104 | */ | |
25c5f225 | 4105 | if (msr <= 0x1fff) { |
8d14695f YZ |
4106 | if (type & MSR_TYPE_R) |
4107 | /* read-low */ | |
4108 | __clear_bit(msr, msr_bitmap + 0x000 / f); | |
4109 | ||
4110 | if (type & MSR_TYPE_W) | |
4111 | /* write-low */ | |
4112 | __clear_bit(msr, msr_bitmap + 0x800 / f); | |
4113 | ||
25c5f225 SY |
4114 | } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { |
4115 | msr &= 0x1fff; | |
8d14695f YZ |
4116 | if (type & MSR_TYPE_R) |
4117 | /* read-high */ | |
4118 | __clear_bit(msr, msr_bitmap + 0x400 / f); | |
4119 | ||
4120 | if (type & MSR_TYPE_W) | |
4121 | /* write-high */ | |
4122 | __clear_bit(msr, msr_bitmap + 0xc00 / f); | |
4123 | ||
4124 | } | |
4125 | } | |
4126 | ||
4127 | static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap, | |
4128 | u32 msr, int type) | |
4129 | { | |
4130 | int f = sizeof(unsigned long); | |
4131 | ||
4132 | if (!cpu_has_vmx_msr_bitmap()) | |
4133 | return; | |
4134 | ||
4135 | /* | |
4136 | * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals | |
4137 | * have the write-low and read-high bitmap offsets the wrong way round. | |
4138 | * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. | |
4139 | */ | |
4140 | if (msr <= 0x1fff) { | |
4141 | if (type & MSR_TYPE_R) | |
4142 | /* read-low */ | |
4143 | __set_bit(msr, msr_bitmap + 0x000 / f); | |
4144 | ||
4145 | if (type & MSR_TYPE_W) | |
4146 | /* write-low */ | |
4147 | __set_bit(msr, msr_bitmap + 0x800 / f); | |
4148 | ||
4149 | } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { | |
4150 | msr &= 0x1fff; | |
4151 | if (type & MSR_TYPE_R) | |
4152 | /* read-high */ | |
4153 | __set_bit(msr, msr_bitmap + 0x400 / f); | |
4154 | ||
4155 | if (type & MSR_TYPE_W) | |
4156 | /* write-high */ | |
4157 | __set_bit(msr, msr_bitmap + 0xc00 / f); | |
4158 | ||
25c5f225 | 4159 | } |
25c5f225 SY |
4160 | } |
4161 | ||
5897297b AK |
4162 | static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only) |
4163 | { | |
4164 | if (!longmode_only) | |
8d14695f YZ |
4165 | __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, |
4166 | msr, MSR_TYPE_R | MSR_TYPE_W); | |
4167 | __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, | |
4168 | msr, MSR_TYPE_R | MSR_TYPE_W); | |
4169 | } | |
4170 | ||
4171 | static void vmx_enable_intercept_msr_read_x2apic(u32 msr) | |
4172 | { | |
4173 | __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic, | |
4174 | msr, MSR_TYPE_R); | |
4175 | __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic, | |
4176 | msr, MSR_TYPE_R); | |
4177 | } | |
4178 | ||
4179 | static void vmx_disable_intercept_msr_read_x2apic(u32 msr) | |
4180 | { | |
4181 | __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic, | |
4182 | msr, MSR_TYPE_R); | |
4183 | __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic, | |
4184 | msr, MSR_TYPE_R); | |
4185 | } | |
4186 | ||
4187 | static void vmx_disable_intercept_msr_write_x2apic(u32 msr) | |
4188 | { | |
4189 | __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic, | |
4190 | msr, MSR_TYPE_W); | |
4191 | __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic, | |
4192 | msr, MSR_TYPE_W); | |
5897297b AK |
4193 | } |
4194 | ||
01e439be YZ |
4195 | static int vmx_vm_has_apicv(struct kvm *kvm) |
4196 | { | |
4197 | return enable_apicv && irqchip_in_kernel(kvm); | |
4198 | } | |
4199 | ||
a20ed54d YZ |
4200 | /* |
4201 | * Send interrupt to vcpu via posted interrupt way. | |
4202 | * 1. If target vcpu is running(non-root mode), send posted interrupt | |
4203 | * notification to vcpu and hardware will sync PIR to vIRR atomically. | |
4204 | * 2. If target vcpu isn't running(root mode), kick it to pick up the | |
4205 | * interrupt from PIR in next vmentry. | |
4206 | */ | |
4207 | static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector) | |
4208 | { | |
4209 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
4210 | int r; | |
4211 | ||
4212 | if (pi_test_and_set_pir(vector, &vmx->pi_desc)) | |
4213 | return; | |
4214 | ||
4215 | r = pi_test_and_set_on(&vmx->pi_desc); | |
4216 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
6ffbbbba | 4217 | #ifdef CONFIG_SMP |
a20ed54d YZ |
4218 | if (!r && (vcpu->mode == IN_GUEST_MODE)) |
4219 | apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), | |
4220 | POSTED_INTR_VECTOR); | |
4221 | else | |
6ffbbbba | 4222 | #endif |
a20ed54d YZ |
4223 | kvm_vcpu_kick(vcpu); |
4224 | } | |
4225 | ||
4226 | static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu) | |
4227 | { | |
4228 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
4229 | ||
4230 | if (!pi_test_and_clear_on(&vmx->pi_desc)) | |
4231 | return; | |
4232 | ||
4233 | kvm_apic_update_irr(vcpu, vmx->pi_desc.pir); | |
4234 | } | |
4235 | ||
4236 | static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu) | |
4237 | { | |
4238 | return; | |
4239 | } | |
4240 | ||
a3a8ff8e NHE |
4241 | /* |
4242 | * Set up the vmcs's constant host-state fields, i.e., host-state fields that | |
4243 | * will not change in the lifetime of the guest. | |
4244 | * Note that host-state that does change is set elsewhere. E.g., host-state | |
4245 | * that is set differently for each CPU is set in vmx_vcpu_load(), not here. | |
4246 | */ | |
a547c6db | 4247 | static void vmx_set_constant_host_state(struct vcpu_vmx *vmx) |
a3a8ff8e NHE |
4248 | { |
4249 | u32 low32, high32; | |
4250 | unsigned long tmpl; | |
4251 | struct desc_ptr dt; | |
d974baa3 | 4252 | unsigned long cr4; |
a3a8ff8e | 4253 | |
b1a74bf8 | 4254 | vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */ |
a3a8ff8e NHE |
4255 | vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */ |
4256 | ||
d974baa3 AL |
4257 | /* Save the most likely value for this task's CR4 in the VMCS. */ |
4258 | cr4 = read_cr4(); | |
4259 | vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */ | |
4260 | vmx->host_state.vmcs_host_cr4 = cr4; | |
4261 | ||
a3a8ff8e | 4262 | vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */ |
b2da15ac AK |
4263 | #ifdef CONFIG_X86_64 |
4264 | /* | |
4265 | * Load null selectors, so we can avoid reloading them in | |
4266 | * __vmx_load_host_state(), in case userspace uses the null selectors | |
4267 | * too (the expected case). | |
4268 | */ | |
4269 | vmcs_write16(HOST_DS_SELECTOR, 0); | |
4270 | vmcs_write16(HOST_ES_SELECTOR, 0); | |
4271 | #else | |
a3a8ff8e NHE |
4272 | vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ |
4273 | vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */ | |
b2da15ac | 4274 | #endif |
a3a8ff8e NHE |
4275 | vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ |
4276 | vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */ | |
4277 | ||
4278 | native_store_idt(&dt); | |
4279 | vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */ | |
a547c6db | 4280 | vmx->host_idt_base = dt.address; |
a3a8ff8e | 4281 | |
83287ea4 | 4282 | vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */ |
a3a8ff8e NHE |
4283 | |
4284 | rdmsr(MSR_IA32_SYSENTER_CS, low32, high32); | |
4285 | vmcs_write32(HOST_IA32_SYSENTER_CS, low32); | |
4286 | rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl); | |
4287 | vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */ | |
4288 | ||
4289 | if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) { | |
4290 | rdmsr(MSR_IA32_CR_PAT, low32, high32); | |
4291 | vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32)); | |
4292 | } | |
4293 | } | |
4294 | ||
bf8179a0 NHE |
4295 | static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx) |
4296 | { | |
4297 | vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS; | |
4298 | if (enable_ept) | |
4299 | vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE; | |
fe3ef05c NHE |
4300 | if (is_guest_mode(&vmx->vcpu)) |
4301 | vmx->vcpu.arch.cr4_guest_owned_bits &= | |
4302 | ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask; | |
bf8179a0 NHE |
4303 | vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits); |
4304 | } | |
4305 | ||
01e439be YZ |
4306 | static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx) |
4307 | { | |
4308 | u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl; | |
4309 | ||
4310 | if (!vmx_vm_has_apicv(vmx->vcpu.kvm)) | |
4311 | pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR; | |
4312 | return pin_based_exec_ctrl; | |
4313 | } | |
4314 | ||
bf8179a0 NHE |
4315 | static u32 vmx_exec_control(struct vcpu_vmx *vmx) |
4316 | { | |
4317 | u32 exec_control = vmcs_config.cpu_based_exec_ctrl; | |
d16c293e PB |
4318 | |
4319 | if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT) | |
4320 | exec_control &= ~CPU_BASED_MOV_DR_EXITING; | |
4321 | ||
bf8179a0 NHE |
4322 | if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) { |
4323 | exec_control &= ~CPU_BASED_TPR_SHADOW; | |
4324 | #ifdef CONFIG_X86_64 | |
4325 | exec_control |= CPU_BASED_CR8_STORE_EXITING | | |
4326 | CPU_BASED_CR8_LOAD_EXITING; | |
4327 | #endif | |
4328 | } | |
4329 | if (!enable_ept) | |
4330 | exec_control |= CPU_BASED_CR3_STORE_EXITING | | |
4331 | CPU_BASED_CR3_LOAD_EXITING | | |
4332 | CPU_BASED_INVLPG_EXITING; | |
4333 | return exec_control; | |
4334 | } | |
4335 | ||
4336 | static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx) | |
4337 | { | |
4338 | u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl; | |
4339 | if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) | |
4340 | exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
4341 | if (vmx->vpid == 0) | |
4342 | exec_control &= ~SECONDARY_EXEC_ENABLE_VPID; | |
4343 | if (!enable_ept) { | |
4344 | exec_control &= ~SECONDARY_EXEC_ENABLE_EPT; | |
4345 | enable_unrestricted_guest = 0; | |
ad756a16 MJ |
4346 | /* Enable INVPCID for non-ept guests may cause performance regression. */ |
4347 | exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID; | |
bf8179a0 NHE |
4348 | } |
4349 | if (!enable_unrestricted_guest) | |
4350 | exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST; | |
4351 | if (!ple_gap) | |
4352 | exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING; | |
c7c9c56c YZ |
4353 | if (!vmx_vm_has_apicv(vmx->vcpu.kvm)) |
4354 | exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT | | |
4355 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); | |
8d14695f | 4356 | exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; |
abc4fc58 AG |
4357 | /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD |
4358 | (handle_vmptrld). | |
4359 | We can NOT enable shadow_vmcs here because we don't have yet | |
4360 | a current VMCS12 | |
4361 | */ | |
4362 | exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS; | |
bf8179a0 NHE |
4363 | return exec_control; |
4364 | } | |
4365 | ||
ce88decf XG |
4366 | static void ept_set_mmio_spte_mask(void) |
4367 | { | |
4368 | /* | |
4369 | * EPT Misconfigurations can be generated if the value of bits 2:0 | |
4370 | * of an EPT paging-structure entry is 110b (write/execute). | |
885032b9 | 4371 | * Also, magic bits (0x3ull << 62) is set to quickly identify mmio |
ce88decf XG |
4372 | * spte. |
4373 | */ | |
885032b9 | 4374 | kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull); |
ce88decf XG |
4375 | } |
4376 | ||
f53cd63c | 4377 | #define VMX_XSS_EXIT_BITMAP 0 |
6aa8b732 AK |
4378 | /* |
4379 | * Sets up the vmcs for emulated real mode. | |
4380 | */ | |
8b9cf98c | 4381 | static int vmx_vcpu_setup(struct vcpu_vmx *vmx) |
6aa8b732 | 4382 | { |
2e4ce7f5 | 4383 | #ifdef CONFIG_X86_64 |
6aa8b732 | 4384 | unsigned long a; |
2e4ce7f5 | 4385 | #endif |
6aa8b732 | 4386 | int i; |
6aa8b732 | 4387 | |
6aa8b732 | 4388 | /* I/O */ |
3e7c73e9 AK |
4389 | vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a)); |
4390 | vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b)); | |
6aa8b732 | 4391 | |
4607c2d7 AG |
4392 | if (enable_shadow_vmcs) { |
4393 | vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap)); | |
4394 | vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap)); | |
4395 | } | |
25c5f225 | 4396 | if (cpu_has_vmx_msr_bitmap()) |
5897297b | 4397 | vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy)); |
25c5f225 | 4398 | |
6aa8b732 AK |
4399 | vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */ |
4400 | ||
6aa8b732 | 4401 | /* Control */ |
01e439be | 4402 | vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx)); |
6e5d865c | 4403 | |
bf8179a0 | 4404 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx)); |
6aa8b732 | 4405 | |
83ff3b9d | 4406 | if (cpu_has_secondary_exec_ctrls()) { |
bf8179a0 NHE |
4407 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, |
4408 | vmx_secondary_exec_control(vmx)); | |
83ff3b9d | 4409 | } |
f78e0e2e | 4410 | |
01e439be | 4411 | if (vmx_vm_has_apicv(vmx->vcpu.kvm)) { |
c7c9c56c YZ |
4412 | vmcs_write64(EOI_EXIT_BITMAP0, 0); |
4413 | vmcs_write64(EOI_EXIT_BITMAP1, 0); | |
4414 | vmcs_write64(EOI_EXIT_BITMAP2, 0); | |
4415 | vmcs_write64(EOI_EXIT_BITMAP3, 0); | |
4416 | ||
4417 | vmcs_write16(GUEST_INTR_STATUS, 0); | |
01e439be YZ |
4418 | |
4419 | vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR); | |
4420 | vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc))); | |
c7c9c56c YZ |
4421 | } |
4422 | ||
4b8d54f9 ZE |
4423 | if (ple_gap) { |
4424 | vmcs_write32(PLE_GAP, ple_gap); | |
a7653ecd RK |
4425 | vmx->ple_window = ple_window; |
4426 | vmx->ple_window_dirty = true; | |
4b8d54f9 ZE |
4427 | } |
4428 | ||
c3707958 XG |
4429 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0); |
4430 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0); | |
6aa8b732 AK |
4431 | vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */ |
4432 | ||
9581d442 AK |
4433 | vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */ |
4434 | vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */ | |
a547c6db | 4435 | vmx_set_constant_host_state(vmx); |
05b3e0c2 | 4436 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
4437 | rdmsrl(MSR_FS_BASE, a); |
4438 | vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */ | |
4439 | rdmsrl(MSR_GS_BASE, a); | |
4440 | vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */ | |
4441 | #else | |
4442 | vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */ | |
4443 | vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */ | |
4444 | #endif | |
4445 | ||
2cc51560 ED |
4446 | vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0); |
4447 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0); | |
61d2ef2c | 4448 | vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host)); |
2cc51560 | 4449 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0); |
61d2ef2c | 4450 | vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest)); |
6aa8b732 | 4451 | |
468d472f | 4452 | if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) { |
a3a8ff8e NHE |
4453 | u32 msr_low, msr_high; |
4454 | u64 host_pat; | |
468d472f SY |
4455 | rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high); |
4456 | host_pat = msr_low | ((u64) msr_high << 32); | |
4457 | /* Write the default value follow host pat */ | |
4458 | vmcs_write64(GUEST_IA32_PAT, host_pat); | |
4459 | /* Keep arch.pat sync with GUEST_IA32_PAT */ | |
4460 | vmx->vcpu.arch.pat = host_pat; | |
4461 | } | |
4462 | ||
03916db9 | 4463 | for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) { |
6aa8b732 AK |
4464 | u32 index = vmx_msr_index[i]; |
4465 | u32 data_low, data_high; | |
a2fa3e9f | 4466 | int j = vmx->nmsrs; |
6aa8b732 AK |
4467 | |
4468 | if (rdmsr_safe(index, &data_low, &data_high) < 0) | |
4469 | continue; | |
432bd6cb AK |
4470 | if (wrmsr_safe(index, data_low, data_high) < 0) |
4471 | continue; | |
26bb0981 AK |
4472 | vmx->guest_msrs[j].index = i; |
4473 | vmx->guest_msrs[j].data = 0; | |
d5696725 | 4474 | vmx->guest_msrs[j].mask = -1ull; |
a2fa3e9f | 4475 | ++vmx->nmsrs; |
6aa8b732 | 4476 | } |
6aa8b732 | 4477 | |
2961e876 GN |
4478 | |
4479 | vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl); | |
6aa8b732 AK |
4480 | |
4481 | /* 22.2.1, 20.8.1 */ | |
2961e876 | 4482 | vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl); |
1c3d14fe | 4483 | |
e00c8cf2 | 4484 | vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL); |
bf8179a0 | 4485 | set_cr4_guest_host_mask(vmx); |
e00c8cf2 | 4486 | |
f53cd63c WL |
4487 | if (vmx_xsaves_supported()) |
4488 | vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP); | |
4489 | ||
e00c8cf2 AK |
4490 | return 0; |
4491 | } | |
4492 | ||
57f252f2 | 4493 | static void vmx_vcpu_reset(struct kvm_vcpu *vcpu) |
e00c8cf2 AK |
4494 | { |
4495 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
58cb628d | 4496 | struct msr_data apic_base_msr; |
e00c8cf2 | 4497 | |
7ffd92c5 | 4498 | vmx->rmode.vm86_active = 0; |
e00c8cf2 | 4499 | |
3b86cd99 JK |
4500 | vmx->soft_vnmi_blocked = 0; |
4501 | ||
ad312c7c | 4502 | vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val(); |
2d3ad1f4 | 4503 | kvm_set_cr8(&vmx->vcpu, 0); |
73a6d941 | 4504 | apic_base_msr.data = APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE; |
c5af89b6 | 4505 | if (kvm_vcpu_is_bsp(&vmx->vcpu)) |
58cb628d JK |
4506 | apic_base_msr.data |= MSR_IA32_APICBASE_BSP; |
4507 | apic_base_msr.host_initiated = true; | |
4508 | kvm_set_apic_base(&vmx->vcpu, &apic_base_msr); | |
e00c8cf2 | 4509 | |
2fb92db1 AK |
4510 | vmx_segment_cache_clear(vmx); |
4511 | ||
5706be0d | 4512 | seg_setup(VCPU_SREG_CS); |
66450a21 | 4513 | vmcs_write16(GUEST_CS_SELECTOR, 0xf000); |
04b66839 | 4514 | vmcs_write32(GUEST_CS_BASE, 0xffff0000); |
e00c8cf2 AK |
4515 | |
4516 | seg_setup(VCPU_SREG_DS); | |
4517 | seg_setup(VCPU_SREG_ES); | |
4518 | seg_setup(VCPU_SREG_FS); | |
4519 | seg_setup(VCPU_SREG_GS); | |
4520 | seg_setup(VCPU_SREG_SS); | |
4521 | ||
4522 | vmcs_write16(GUEST_TR_SELECTOR, 0); | |
4523 | vmcs_writel(GUEST_TR_BASE, 0); | |
4524 | vmcs_write32(GUEST_TR_LIMIT, 0xffff); | |
4525 | vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); | |
4526 | ||
4527 | vmcs_write16(GUEST_LDTR_SELECTOR, 0); | |
4528 | vmcs_writel(GUEST_LDTR_BASE, 0); | |
4529 | vmcs_write32(GUEST_LDTR_LIMIT, 0xffff); | |
4530 | vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082); | |
4531 | ||
4532 | vmcs_write32(GUEST_SYSENTER_CS, 0); | |
4533 | vmcs_writel(GUEST_SYSENTER_ESP, 0); | |
4534 | vmcs_writel(GUEST_SYSENTER_EIP, 0); | |
4535 | ||
4536 | vmcs_writel(GUEST_RFLAGS, 0x02); | |
66450a21 | 4537 | kvm_rip_write(vcpu, 0xfff0); |
e00c8cf2 | 4538 | |
e00c8cf2 AK |
4539 | vmcs_writel(GUEST_GDTR_BASE, 0); |
4540 | vmcs_write32(GUEST_GDTR_LIMIT, 0xffff); | |
4541 | ||
4542 | vmcs_writel(GUEST_IDTR_BASE, 0); | |
4543 | vmcs_write32(GUEST_IDTR_LIMIT, 0xffff); | |
4544 | ||
443381a8 | 4545 | vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE); |
e00c8cf2 AK |
4546 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0); |
4547 | vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0); | |
4548 | ||
e00c8cf2 AK |
4549 | /* Special registers */ |
4550 | vmcs_write64(GUEST_IA32_DEBUGCTL, 0); | |
4551 | ||
4552 | setup_msrs(vmx); | |
4553 | ||
6aa8b732 AK |
4554 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */ |
4555 | ||
f78e0e2e SY |
4556 | if (cpu_has_vmx_tpr_shadow()) { |
4557 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0); | |
4558 | if (vm_need_tpr_shadow(vmx->vcpu.kvm)) | |
4559 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, | |
afc20184 | 4560 | __pa(vmx->vcpu.arch.apic->regs)); |
f78e0e2e SY |
4561 | vmcs_write32(TPR_THRESHOLD, 0); |
4562 | } | |
4563 | ||
a73896cb | 4564 | kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu); |
6aa8b732 | 4565 | |
01e439be YZ |
4566 | if (vmx_vm_has_apicv(vcpu->kvm)) |
4567 | memset(&vmx->pi_desc, 0, sizeof(struct pi_desc)); | |
4568 | ||
2384d2b3 SY |
4569 | if (vmx->vpid != 0) |
4570 | vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid); | |
4571 | ||
fa40052c | 4572 | vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET; |
4d4ec087 | 4573 | vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */ |
8b9cf98c | 4574 | vmx_set_cr4(&vmx->vcpu, 0); |
8b9cf98c | 4575 | vmx_set_efer(&vmx->vcpu, 0); |
8b9cf98c RR |
4576 | vmx_fpu_activate(&vmx->vcpu); |
4577 | update_exception_bitmap(&vmx->vcpu); | |
6aa8b732 | 4578 | |
b9d762fa | 4579 | vpid_sync_context(vmx); |
6aa8b732 AK |
4580 | } |
4581 | ||
b6f1250e NHE |
4582 | /* |
4583 | * In nested virtualization, check if L1 asked to exit on external interrupts. | |
4584 | * For most existing hypervisors, this will always return true. | |
4585 | */ | |
4586 | static bool nested_exit_on_intr(struct kvm_vcpu *vcpu) | |
4587 | { | |
4588 | return get_vmcs12(vcpu)->pin_based_vm_exec_control & | |
4589 | PIN_BASED_EXT_INTR_MASK; | |
4590 | } | |
4591 | ||
77b0f5d6 BD |
4592 | /* |
4593 | * In nested virtualization, check if L1 has set | |
4594 | * VM_EXIT_ACK_INTR_ON_EXIT | |
4595 | */ | |
4596 | static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu) | |
4597 | { | |
4598 | return get_vmcs12(vcpu)->vm_exit_controls & | |
4599 | VM_EXIT_ACK_INTR_ON_EXIT; | |
4600 | } | |
4601 | ||
ea8ceb83 JK |
4602 | static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu) |
4603 | { | |
4604 | return get_vmcs12(vcpu)->pin_based_vm_exec_control & | |
4605 | PIN_BASED_NMI_EXITING; | |
4606 | } | |
4607 | ||
c9a7953f | 4608 | static void enable_irq_window(struct kvm_vcpu *vcpu) |
3b86cd99 JK |
4609 | { |
4610 | u32 cpu_based_vm_exec_control; | |
730dca42 | 4611 | |
3b86cd99 JK |
4612 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); |
4613 | cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING; | |
4614 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
4615 | } | |
4616 | ||
c9a7953f | 4617 | static void enable_nmi_window(struct kvm_vcpu *vcpu) |
3b86cd99 JK |
4618 | { |
4619 | u32 cpu_based_vm_exec_control; | |
4620 | ||
c9a7953f JK |
4621 | if (!cpu_has_virtual_nmis() || |
4622 | vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) { | |
4623 | enable_irq_window(vcpu); | |
4624 | return; | |
4625 | } | |
3b86cd99 JK |
4626 | |
4627 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
4628 | cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING; | |
4629 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
4630 | } | |
4631 | ||
66fd3f7f | 4632 | static void vmx_inject_irq(struct kvm_vcpu *vcpu) |
85f455f7 | 4633 | { |
9c8cba37 | 4634 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
66fd3f7f GN |
4635 | uint32_t intr; |
4636 | int irq = vcpu->arch.interrupt.nr; | |
9c8cba37 | 4637 | |
229456fc | 4638 | trace_kvm_inj_virq(irq); |
2714d1d3 | 4639 | |
fa89a817 | 4640 | ++vcpu->stat.irq_injections; |
7ffd92c5 | 4641 | if (vmx->rmode.vm86_active) { |
71f9833b SH |
4642 | int inc_eip = 0; |
4643 | if (vcpu->arch.interrupt.soft) | |
4644 | inc_eip = vcpu->arch.event_exit_inst_len; | |
4645 | if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE) | |
a92601bb | 4646 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
85f455f7 ED |
4647 | return; |
4648 | } | |
66fd3f7f GN |
4649 | intr = irq | INTR_INFO_VALID_MASK; |
4650 | if (vcpu->arch.interrupt.soft) { | |
4651 | intr |= INTR_TYPE_SOFT_INTR; | |
4652 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, | |
4653 | vmx->vcpu.arch.event_exit_inst_len); | |
4654 | } else | |
4655 | intr |= INTR_TYPE_EXT_INTR; | |
4656 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr); | |
85f455f7 ED |
4657 | } |
4658 | ||
f08864b4 SY |
4659 | static void vmx_inject_nmi(struct kvm_vcpu *vcpu) |
4660 | { | |
66a5a347 JK |
4661 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
4662 | ||
0b6ac343 NHE |
4663 | if (is_guest_mode(vcpu)) |
4664 | return; | |
4665 | ||
3b86cd99 JK |
4666 | if (!cpu_has_virtual_nmis()) { |
4667 | /* | |
4668 | * Tracking the NMI-blocked state in software is built upon | |
4669 | * finding the next open IRQ window. This, in turn, depends on | |
4670 | * well-behaving guests: They have to keep IRQs disabled at | |
4671 | * least as long as the NMI handler runs. Otherwise we may | |
4672 | * cause NMI nesting, maybe breaking the guest. But as this is | |
4673 | * highly unlikely, we can live with the residual risk. | |
4674 | */ | |
4675 | vmx->soft_vnmi_blocked = 1; | |
4676 | vmx->vnmi_blocked_time = 0; | |
4677 | } | |
4678 | ||
487b391d | 4679 | ++vcpu->stat.nmi_injections; |
9d58b931 | 4680 | vmx->nmi_known_unmasked = false; |
7ffd92c5 | 4681 | if (vmx->rmode.vm86_active) { |
71f9833b | 4682 | if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE) |
a92601bb | 4683 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
66a5a347 JK |
4684 | return; |
4685 | } | |
f08864b4 SY |
4686 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, |
4687 | INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR); | |
f08864b4 SY |
4688 | } |
4689 | ||
3cfc3092 JK |
4690 | static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu) |
4691 | { | |
4692 | if (!cpu_has_virtual_nmis()) | |
4693 | return to_vmx(vcpu)->soft_vnmi_blocked; | |
9d58b931 AK |
4694 | if (to_vmx(vcpu)->nmi_known_unmasked) |
4695 | return false; | |
c332c83a | 4696 | return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI; |
3cfc3092 JK |
4697 | } |
4698 | ||
4699 | static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked) | |
4700 | { | |
4701 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
4702 | ||
4703 | if (!cpu_has_virtual_nmis()) { | |
4704 | if (vmx->soft_vnmi_blocked != masked) { | |
4705 | vmx->soft_vnmi_blocked = masked; | |
4706 | vmx->vnmi_blocked_time = 0; | |
4707 | } | |
4708 | } else { | |
9d58b931 | 4709 | vmx->nmi_known_unmasked = !masked; |
3cfc3092 JK |
4710 | if (masked) |
4711 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, | |
4712 | GUEST_INTR_STATE_NMI); | |
4713 | else | |
4714 | vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO, | |
4715 | GUEST_INTR_STATE_NMI); | |
4716 | } | |
4717 | } | |
4718 | ||
2505dc9f JK |
4719 | static int vmx_nmi_allowed(struct kvm_vcpu *vcpu) |
4720 | { | |
b6b8a145 JK |
4721 | if (to_vmx(vcpu)->nested.nested_run_pending) |
4722 | return 0; | |
ea8ceb83 | 4723 | |
2505dc9f JK |
4724 | if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked) |
4725 | return 0; | |
4726 | ||
4727 | return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & | |
4728 | (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI | |
4729 | | GUEST_INTR_STATE_NMI)); | |
4730 | } | |
4731 | ||
78646121 GN |
4732 | static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu) |
4733 | { | |
b6b8a145 JK |
4734 | return (!to_vmx(vcpu)->nested.nested_run_pending && |
4735 | vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) && | |
c4282df9 GN |
4736 | !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & |
4737 | (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS)); | |
78646121 GN |
4738 | } |
4739 | ||
cbc94022 IE |
4740 | static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr) |
4741 | { | |
4742 | int ret; | |
4743 | struct kvm_userspace_memory_region tss_mem = { | |
6fe63979 | 4744 | .slot = TSS_PRIVATE_MEMSLOT, |
cbc94022 IE |
4745 | .guest_phys_addr = addr, |
4746 | .memory_size = PAGE_SIZE * 3, | |
4747 | .flags = 0, | |
4748 | }; | |
4749 | ||
47ae31e2 | 4750 | ret = kvm_set_memory_region(kvm, &tss_mem); |
cbc94022 IE |
4751 | if (ret) |
4752 | return ret; | |
bfc6d222 | 4753 | kvm->arch.tss_addr = addr; |
1f755a82 | 4754 | return init_rmode_tss(kvm); |
cbc94022 IE |
4755 | } |
4756 | ||
0ca1b4f4 | 4757 | static bool rmode_exception(struct kvm_vcpu *vcpu, int vec) |
6aa8b732 | 4758 | { |
77ab6db0 | 4759 | switch (vec) { |
77ab6db0 | 4760 | case BP_VECTOR: |
c573cd22 JK |
4761 | /* |
4762 | * Update instruction length as we may reinject the exception | |
4763 | * from user space while in guest debugging mode. | |
4764 | */ | |
4765 | to_vmx(vcpu)->vcpu.arch.event_exit_inst_len = | |
4766 | vmcs_read32(VM_EXIT_INSTRUCTION_LEN); | |
d0bfb940 | 4767 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) |
0ca1b4f4 GN |
4768 | return false; |
4769 | /* fall through */ | |
4770 | case DB_VECTOR: | |
4771 | if (vcpu->guest_debug & | |
4772 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) | |
4773 | return false; | |
d0bfb940 JK |
4774 | /* fall through */ |
4775 | case DE_VECTOR: | |
77ab6db0 JK |
4776 | case OF_VECTOR: |
4777 | case BR_VECTOR: | |
4778 | case UD_VECTOR: | |
4779 | case DF_VECTOR: | |
4780 | case SS_VECTOR: | |
4781 | case GP_VECTOR: | |
4782 | case MF_VECTOR: | |
0ca1b4f4 GN |
4783 | return true; |
4784 | break; | |
77ab6db0 | 4785 | } |
0ca1b4f4 GN |
4786 | return false; |
4787 | } | |
4788 | ||
4789 | static int handle_rmode_exception(struct kvm_vcpu *vcpu, | |
4790 | int vec, u32 err_code) | |
4791 | { | |
4792 | /* | |
4793 | * Instruction with address size override prefix opcode 0x67 | |
4794 | * Cause the #SS fault with 0 error code in VM86 mode. | |
4795 | */ | |
4796 | if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) { | |
4797 | if (emulate_instruction(vcpu, 0) == EMULATE_DONE) { | |
4798 | if (vcpu->arch.halt_request) { | |
4799 | vcpu->arch.halt_request = 0; | |
4800 | return kvm_emulate_halt(vcpu); | |
4801 | } | |
4802 | return 1; | |
4803 | } | |
4804 | return 0; | |
4805 | } | |
4806 | ||
4807 | /* | |
4808 | * Forward all other exceptions that are valid in real mode. | |
4809 | * FIXME: Breaks guest debugging in real mode, needs to be fixed with | |
4810 | * the required debugging infrastructure rework. | |
4811 | */ | |
4812 | kvm_queue_exception(vcpu, vec); | |
4813 | return 1; | |
6aa8b732 AK |
4814 | } |
4815 | ||
a0861c02 AK |
4816 | /* |
4817 | * Trigger machine check on the host. We assume all the MSRs are already set up | |
4818 | * by the CPU and that we still run on the same CPU as the MCE occurred on. | |
4819 | * We pass a fake environment to the machine check handler because we want | |
4820 | * the guest to be always treated like user space, no matter what context | |
4821 | * it used internally. | |
4822 | */ | |
4823 | static void kvm_machine_check(void) | |
4824 | { | |
4825 | #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64) | |
4826 | struct pt_regs regs = { | |
4827 | .cs = 3, /* Fake ring 3 no matter what the guest ran on */ | |
4828 | .flags = X86_EFLAGS_IF, | |
4829 | }; | |
4830 | ||
4831 | do_machine_check(®s, 0); | |
4832 | #endif | |
4833 | } | |
4834 | ||
851ba692 | 4835 | static int handle_machine_check(struct kvm_vcpu *vcpu) |
a0861c02 AK |
4836 | { |
4837 | /* already handled by vcpu_run */ | |
4838 | return 1; | |
4839 | } | |
4840 | ||
851ba692 | 4841 | static int handle_exception(struct kvm_vcpu *vcpu) |
6aa8b732 | 4842 | { |
1155f76a | 4843 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
851ba692 | 4844 | struct kvm_run *kvm_run = vcpu->run; |
d0bfb940 | 4845 | u32 intr_info, ex_no, error_code; |
42dbaa5a | 4846 | unsigned long cr2, rip, dr6; |
6aa8b732 AK |
4847 | u32 vect_info; |
4848 | enum emulation_result er; | |
4849 | ||
1155f76a | 4850 | vect_info = vmx->idt_vectoring_info; |
88786475 | 4851 | intr_info = vmx->exit_intr_info; |
6aa8b732 | 4852 | |
a0861c02 | 4853 | if (is_machine_check(intr_info)) |
851ba692 | 4854 | return handle_machine_check(vcpu); |
a0861c02 | 4855 | |
e4a41889 | 4856 | if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR) |
1b6269db | 4857 | return 1; /* already handled by vmx_vcpu_run() */ |
2ab455cc AL |
4858 | |
4859 | if (is_no_device(intr_info)) { | |
5fd86fcf | 4860 | vmx_fpu_activate(vcpu); |
2ab455cc AL |
4861 | return 1; |
4862 | } | |
4863 | ||
7aa81cc0 | 4864 | if (is_invalid_opcode(intr_info)) { |
51d8b661 | 4865 | er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD); |
7aa81cc0 | 4866 | if (er != EMULATE_DONE) |
7ee5d940 | 4867 | kvm_queue_exception(vcpu, UD_VECTOR); |
7aa81cc0 AL |
4868 | return 1; |
4869 | } | |
4870 | ||
6aa8b732 | 4871 | error_code = 0; |
2e11384c | 4872 | if (intr_info & INTR_INFO_DELIVER_CODE_MASK) |
6aa8b732 | 4873 | error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE); |
bf4ca23e XG |
4874 | |
4875 | /* | |
4876 | * The #PF with PFEC.RSVD = 1 indicates the guest is accessing | |
4877 | * MMIO, it is better to report an internal error. | |
4878 | * See the comments in vmx_handle_exit. | |
4879 | */ | |
4880 | if ((vect_info & VECTORING_INFO_VALID_MASK) && | |
4881 | !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) { | |
4882 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
4883 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX; | |
4884 | vcpu->run->internal.ndata = 2; | |
4885 | vcpu->run->internal.data[0] = vect_info; | |
4886 | vcpu->run->internal.data[1] = intr_info; | |
4887 | return 0; | |
4888 | } | |
4889 | ||
6aa8b732 | 4890 | if (is_page_fault(intr_info)) { |
1439442c | 4891 | /* EPT won't cause page fault directly */ |
cf3ace79 | 4892 | BUG_ON(enable_ept); |
6aa8b732 | 4893 | cr2 = vmcs_readl(EXIT_QUALIFICATION); |
229456fc MT |
4894 | trace_kvm_page_fault(cr2, error_code); |
4895 | ||
3298b75c | 4896 | if (kvm_event_needs_reinjection(vcpu)) |
577bdc49 | 4897 | kvm_mmu_unprotect_page_virt(vcpu, cr2); |
dc25e89e | 4898 | return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0); |
6aa8b732 AK |
4899 | } |
4900 | ||
d0bfb940 | 4901 | ex_no = intr_info & INTR_INFO_VECTOR_MASK; |
0ca1b4f4 GN |
4902 | |
4903 | if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no)) | |
4904 | return handle_rmode_exception(vcpu, ex_no, error_code); | |
4905 | ||
42dbaa5a JK |
4906 | switch (ex_no) { |
4907 | case DB_VECTOR: | |
4908 | dr6 = vmcs_readl(EXIT_QUALIFICATION); | |
4909 | if (!(vcpu->guest_debug & | |
4910 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) { | |
8246bf52 | 4911 | vcpu->arch.dr6 &= ~15; |
6f43ed01 | 4912 | vcpu->arch.dr6 |= dr6 | DR6_RTM; |
fd2a445a HD |
4913 | if (!(dr6 & ~DR6_RESERVED)) /* icebp */ |
4914 | skip_emulated_instruction(vcpu); | |
4915 | ||
42dbaa5a JK |
4916 | kvm_queue_exception(vcpu, DB_VECTOR); |
4917 | return 1; | |
4918 | } | |
4919 | kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1; | |
4920 | kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7); | |
4921 | /* fall through */ | |
4922 | case BP_VECTOR: | |
c573cd22 JK |
4923 | /* |
4924 | * Update instruction length as we may reinject #BP from | |
4925 | * user space while in guest debugging mode. Reading it for | |
4926 | * #DB as well causes no harm, it is not used in that case. | |
4927 | */ | |
4928 | vmx->vcpu.arch.event_exit_inst_len = | |
4929 | vmcs_read32(VM_EXIT_INSTRUCTION_LEN); | |
6aa8b732 | 4930 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
0a434bb2 | 4931 | rip = kvm_rip_read(vcpu); |
d0bfb940 JK |
4932 | kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip; |
4933 | kvm_run->debug.arch.exception = ex_no; | |
42dbaa5a JK |
4934 | break; |
4935 | default: | |
d0bfb940 JK |
4936 | kvm_run->exit_reason = KVM_EXIT_EXCEPTION; |
4937 | kvm_run->ex.exception = ex_no; | |
4938 | kvm_run->ex.error_code = error_code; | |
42dbaa5a | 4939 | break; |
6aa8b732 | 4940 | } |
6aa8b732 AK |
4941 | return 0; |
4942 | } | |
4943 | ||
851ba692 | 4944 | static int handle_external_interrupt(struct kvm_vcpu *vcpu) |
6aa8b732 | 4945 | { |
1165f5fe | 4946 | ++vcpu->stat.irq_exits; |
6aa8b732 AK |
4947 | return 1; |
4948 | } | |
4949 | ||
851ba692 | 4950 | static int handle_triple_fault(struct kvm_vcpu *vcpu) |
988ad74f | 4951 | { |
851ba692 | 4952 | vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; |
988ad74f AK |
4953 | return 0; |
4954 | } | |
6aa8b732 | 4955 | |
851ba692 | 4956 | static int handle_io(struct kvm_vcpu *vcpu) |
6aa8b732 | 4957 | { |
bfdaab09 | 4958 | unsigned long exit_qualification; |
34c33d16 | 4959 | int size, in, string; |
039576c0 | 4960 | unsigned port; |
6aa8b732 | 4961 | |
bfdaab09 | 4962 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
039576c0 | 4963 | string = (exit_qualification & 16) != 0; |
cf8f70bf | 4964 | in = (exit_qualification & 8) != 0; |
e70669ab | 4965 | |
cf8f70bf | 4966 | ++vcpu->stat.io_exits; |
e70669ab | 4967 | |
cf8f70bf | 4968 | if (string || in) |
51d8b661 | 4969 | return emulate_instruction(vcpu, 0) == EMULATE_DONE; |
e70669ab | 4970 | |
cf8f70bf GN |
4971 | port = exit_qualification >> 16; |
4972 | size = (exit_qualification & 7) + 1; | |
e93f36bc | 4973 | skip_emulated_instruction(vcpu); |
cf8f70bf GN |
4974 | |
4975 | return kvm_fast_pio_out(vcpu, size, port); | |
6aa8b732 AK |
4976 | } |
4977 | ||
102d8325 IM |
4978 | static void |
4979 | vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
4980 | { | |
4981 | /* | |
4982 | * Patch in the VMCALL instruction: | |
4983 | */ | |
4984 | hypercall[0] = 0x0f; | |
4985 | hypercall[1] = 0x01; | |
4986 | hypercall[2] = 0xc1; | |
102d8325 IM |
4987 | } |
4988 | ||
92fbc7b1 JK |
4989 | static bool nested_cr0_valid(struct vmcs12 *vmcs12, unsigned long val) |
4990 | { | |
4991 | unsigned long always_on = VMXON_CR0_ALWAYSON; | |
4992 | ||
4993 | if (nested_vmx_secondary_ctls_high & | |
4994 | SECONDARY_EXEC_UNRESTRICTED_GUEST && | |
4995 | nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST)) | |
4996 | always_on &= ~(X86_CR0_PE | X86_CR0_PG); | |
4997 | return (val & always_on) == always_on; | |
4998 | } | |
4999 | ||
0fa06071 | 5000 | /* called to set cr0 as appropriate for a mov-to-cr0 exit. */ |
eeadf9e7 NHE |
5001 | static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val) |
5002 | { | |
eeadf9e7 | 5003 | if (is_guest_mode(vcpu)) { |
1a0d74e6 JK |
5004 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
5005 | unsigned long orig_val = val; | |
5006 | ||
eeadf9e7 NHE |
5007 | /* |
5008 | * We get here when L2 changed cr0 in a way that did not change | |
5009 | * any of L1's shadowed bits (see nested_vmx_exit_handled_cr), | |
1a0d74e6 JK |
5010 | * but did change L0 shadowed bits. So we first calculate the |
5011 | * effective cr0 value that L1 would like to write into the | |
5012 | * hardware. It consists of the L2-owned bits from the new | |
5013 | * value combined with the L1-owned bits from L1's guest_cr0. | |
eeadf9e7 | 5014 | */ |
1a0d74e6 JK |
5015 | val = (val & ~vmcs12->cr0_guest_host_mask) | |
5016 | (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask); | |
5017 | ||
92fbc7b1 | 5018 | if (!nested_cr0_valid(vmcs12, val)) |
eeadf9e7 | 5019 | return 1; |
1a0d74e6 JK |
5020 | |
5021 | if (kvm_set_cr0(vcpu, val)) | |
5022 | return 1; | |
5023 | vmcs_writel(CR0_READ_SHADOW, orig_val); | |
eeadf9e7 | 5024 | return 0; |
1a0d74e6 JK |
5025 | } else { |
5026 | if (to_vmx(vcpu)->nested.vmxon && | |
5027 | ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON)) | |
5028 | return 1; | |
eeadf9e7 | 5029 | return kvm_set_cr0(vcpu, val); |
1a0d74e6 | 5030 | } |
eeadf9e7 NHE |
5031 | } |
5032 | ||
5033 | static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val) | |
5034 | { | |
5035 | if (is_guest_mode(vcpu)) { | |
1a0d74e6 JK |
5036 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
5037 | unsigned long orig_val = val; | |
5038 | ||
5039 | /* analogously to handle_set_cr0 */ | |
5040 | val = (val & ~vmcs12->cr4_guest_host_mask) | | |
5041 | (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask); | |
5042 | if (kvm_set_cr4(vcpu, val)) | |
eeadf9e7 | 5043 | return 1; |
1a0d74e6 | 5044 | vmcs_writel(CR4_READ_SHADOW, orig_val); |
eeadf9e7 NHE |
5045 | return 0; |
5046 | } else | |
5047 | return kvm_set_cr4(vcpu, val); | |
5048 | } | |
5049 | ||
5050 | /* called to set cr0 as approriate for clts instruction exit. */ | |
5051 | static void handle_clts(struct kvm_vcpu *vcpu) | |
5052 | { | |
5053 | if (is_guest_mode(vcpu)) { | |
5054 | /* | |
5055 | * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS | |
5056 | * but we did (!fpu_active). We need to keep GUEST_CR0.TS on, | |
5057 | * just pretend it's off (also in arch.cr0 for fpu_activate). | |
5058 | */ | |
5059 | vmcs_writel(CR0_READ_SHADOW, | |
5060 | vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS); | |
5061 | vcpu->arch.cr0 &= ~X86_CR0_TS; | |
5062 | } else | |
5063 | vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS)); | |
5064 | } | |
5065 | ||
851ba692 | 5066 | static int handle_cr(struct kvm_vcpu *vcpu) |
6aa8b732 | 5067 | { |
229456fc | 5068 | unsigned long exit_qualification, val; |
6aa8b732 AK |
5069 | int cr; |
5070 | int reg; | |
49a9b07e | 5071 | int err; |
6aa8b732 | 5072 | |
bfdaab09 | 5073 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
6aa8b732 AK |
5074 | cr = exit_qualification & 15; |
5075 | reg = (exit_qualification >> 8) & 15; | |
5076 | switch ((exit_qualification >> 4) & 3) { | |
5077 | case 0: /* mov to cr */ | |
1e32c079 | 5078 | val = kvm_register_readl(vcpu, reg); |
229456fc | 5079 | trace_kvm_cr_write(cr, val); |
6aa8b732 AK |
5080 | switch (cr) { |
5081 | case 0: | |
eeadf9e7 | 5082 | err = handle_set_cr0(vcpu, val); |
db8fcefa | 5083 | kvm_complete_insn_gp(vcpu, err); |
6aa8b732 AK |
5084 | return 1; |
5085 | case 3: | |
2390218b | 5086 | err = kvm_set_cr3(vcpu, val); |
db8fcefa | 5087 | kvm_complete_insn_gp(vcpu, err); |
6aa8b732 AK |
5088 | return 1; |
5089 | case 4: | |
eeadf9e7 | 5090 | err = handle_set_cr4(vcpu, val); |
db8fcefa | 5091 | kvm_complete_insn_gp(vcpu, err); |
6aa8b732 | 5092 | return 1; |
0a5fff19 GN |
5093 | case 8: { |
5094 | u8 cr8_prev = kvm_get_cr8(vcpu); | |
1e32c079 | 5095 | u8 cr8 = (u8)val; |
eea1cff9 | 5096 | err = kvm_set_cr8(vcpu, cr8); |
db8fcefa | 5097 | kvm_complete_insn_gp(vcpu, err); |
0a5fff19 GN |
5098 | if (irqchip_in_kernel(vcpu->kvm)) |
5099 | return 1; | |
5100 | if (cr8_prev <= cr8) | |
5101 | return 1; | |
851ba692 | 5102 | vcpu->run->exit_reason = KVM_EXIT_SET_TPR; |
0a5fff19 GN |
5103 | return 0; |
5104 | } | |
4b8073e4 | 5105 | } |
6aa8b732 | 5106 | break; |
25c4c276 | 5107 | case 2: /* clts */ |
eeadf9e7 | 5108 | handle_clts(vcpu); |
4d4ec087 | 5109 | trace_kvm_cr_write(0, kvm_read_cr0(vcpu)); |
25c4c276 | 5110 | skip_emulated_instruction(vcpu); |
6b52d186 | 5111 | vmx_fpu_activate(vcpu); |
25c4c276 | 5112 | return 1; |
6aa8b732 AK |
5113 | case 1: /*mov from cr*/ |
5114 | switch (cr) { | |
5115 | case 3: | |
9f8fe504 AK |
5116 | val = kvm_read_cr3(vcpu); |
5117 | kvm_register_write(vcpu, reg, val); | |
5118 | trace_kvm_cr_read(cr, val); | |
6aa8b732 AK |
5119 | skip_emulated_instruction(vcpu); |
5120 | return 1; | |
5121 | case 8: | |
229456fc MT |
5122 | val = kvm_get_cr8(vcpu); |
5123 | kvm_register_write(vcpu, reg, val); | |
5124 | trace_kvm_cr_read(cr, val); | |
6aa8b732 AK |
5125 | skip_emulated_instruction(vcpu); |
5126 | return 1; | |
5127 | } | |
5128 | break; | |
5129 | case 3: /* lmsw */ | |
a1f83a74 | 5130 | val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f; |
4d4ec087 | 5131 | trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val); |
a1f83a74 | 5132 | kvm_lmsw(vcpu, val); |
6aa8b732 AK |
5133 | |
5134 | skip_emulated_instruction(vcpu); | |
5135 | return 1; | |
5136 | default: | |
5137 | break; | |
5138 | } | |
851ba692 | 5139 | vcpu->run->exit_reason = 0; |
a737f256 | 5140 | vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n", |
6aa8b732 AK |
5141 | (int)(exit_qualification >> 4) & 3, cr); |
5142 | return 0; | |
5143 | } | |
5144 | ||
851ba692 | 5145 | static int handle_dr(struct kvm_vcpu *vcpu) |
6aa8b732 | 5146 | { |
bfdaab09 | 5147 | unsigned long exit_qualification; |
16f8a6f9 NA |
5148 | int dr, dr7, reg; |
5149 | ||
5150 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
5151 | dr = exit_qualification & DEBUG_REG_ACCESS_NUM; | |
5152 | ||
5153 | /* First, if DR does not exist, trigger UD */ | |
5154 | if (!kvm_require_dr(vcpu, dr)) | |
5155 | return 1; | |
6aa8b732 | 5156 | |
f2483415 | 5157 | /* Do not handle if the CPL > 0, will trigger GP on re-entry */ |
0a79b009 AK |
5158 | if (!kvm_require_cpl(vcpu, 0)) |
5159 | return 1; | |
16f8a6f9 NA |
5160 | dr7 = vmcs_readl(GUEST_DR7); |
5161 | if (dr7 & DR7_GD) { | |
42dbaa5a JK |
5162 | /* |
5163 | * As the vm-exit takes precedence over the debug trap, we | |
5164 | * need to emulate the latter, either for the host or the | |
5165 | * guest debugging itself. | |
5166 | */ | |
5167 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { | |
851ba692 | 5168 | vcpu->run->debug.arch.dr6 = vcpu->arch.dr6; |
16f8a6f9 | 5169 | vcpu->run->debug.arch.dr7 = dr7; |
82b32774 | 5170 | vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu); |
851ba692 AK |
5171 | vcpu->run->debug.arch.exception = DB_VECTOR; |
5172 | vcpu->run->exit_reason = KVM_EXIT_DEBUG; | |
42dbaa5a JK |
5173 | return 0; |
5174 | } else { | |
7305eb5d | 5175 | vcpu->arch.dr6 &= ~15; |
6f43ed01 | 5176 | vcpu->arch.dr6 |= DR6_BD | DR6_RTM; |
42dbaa5a JK |
5177 | kvm_queue_exception(vcpu, DB_VECTOR); |
5178 | return 1; | |
5179 | } | |
5180 | } | |
5181 | ||
81908bf4 PB |
5182 | if (vcpu->guest_debug == 0) { |
5183 | u32 cpu_based_vm_exec_control; | |
5184 | ||
5185 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
5186 | cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING; | |
5187 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
5188 | ||
5189 | /* | |
5190 | * No more DR vmexits; force a reload of the debug registers | |
5191 | * and reenter on this instruction. The next vmexit will | |
5192 | * retrieve the full state of the debug registers. | |
5193 | */ | |
5194 | vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT; | |
5195 | return 1; | |
5196 | } | |
5197 | ||
42dbaa5a JK |
5198 | reg = DEBUG_REG_ACCESS_REG(exit_qualification); |
5199 | if (exit_qualification & TYPE_MOV_FROM_DR) { | |
020df079 | 5200 | unsigned long val; |
4c4d563b JK |
5201 | |
5202 | if (kvm_get_dr(vcpu, dr, &val)) | |
5203 | return 1; | |
5204 | kvm_register_write(vcpu, reg, val); | |
020df079 | 5205 | } else |
5777392e | 5206 | if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg))) |
4c4d563b JK |
5207 | return 1; |
5208 | ||
6aa8b732 AK |
5209 | skip_emulated_instruction(vcpu); |
5210 | return 1; | |
5211 | } | |
5212 | ||
73aaf249 JK |
5213 | static u64 vmx_get_dr6(struct kvm_vcpu *vcpu) |
5214 | { | |
5215 | return vcpu->arch.dr6; | |
5216 | } | |
5217 | ||
5218 | static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val) | |
5219 | { | |
5220 | } | |
5221 | ||
81908bf4 PB |
5222 | static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu) |
5223 | { | |
5224 | u32 cpu_based_vm_exec_control; | |
5225 | ||
5226 | get_debugreg(vcpu->arch.db[0], 0); | |
5227 | get_debugreg(vcpu->arch.db[1], 1); | |
5228 | get_debugreg(vcpu->arch.db[2], 2); | |
5229 | get_debugreg(vcpu->arch.db[3], 3); | |
5230 | get_debugreg(vcpu->arch.dr6, 6); | |
5231 | vcpu->arch.dr7 = vmcs_readl(GUEST_DR7); | |
5232 | ||
5233 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT; | |
5234 | ||
5235 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
5236 | cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING; | |
5237 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
5238 | } | |
5239 | ||
020df079 GN |
5240 | static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val) |
5241 | { | |
5242 | vmcs_writel(GUEST_DR7, val); | |
5243 | } | |
5244 | ||
851ba692 | 5245 | static int handle_cpuid(struct kvm_vcpu *vcpu) |
6aa8b732 | 5246 | { |
06465c5a AK |
5247 | kvm_emulate_cpuid(vcpu); |
5248 | return 1; | |
6aa8b732 AK |
5249 | } |
5250 | ||
851ba692 | 5251 | static int handle_rdmsr(struct kvm_vcpu *vcpu) |
6aa8b732 | 5252 | { |
ad312c7c | 5253 | u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX]; |
6aa8b732 AK |
5254 | u64 data; |
5255 | ||
5256 | if (vmx_get_msr(vcpu, ecx, &data)) { | |
59200273 | 5257 | trace_kvm_msr_read_ex(ecx); |
c1a5d4f9 | 5258 | kvm_inject_gp(vcpu, 0); |
6aa8b732 AK |
5259 | return 1; |
5260 | } | |
5261 | ||
229456fc | 5262 | trace_kvm_msr_read(ecx, data); |
2714d1d3 | 5263 | |
6aa8b732 | 5264 | /* FIXME: handling of bits 32:63 of rax, rdx */ |
ad312c7c ZX |
5265 | vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u; |
5266 | vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u; | |
6aa8b732 AK |
5267 | skip_emulated_instruction(vcpu); |
5268 | return 1; | |
5269 | } | |
5270 | ||
851ba692 | 5271 | static int handle_wrmsr(struct kvm_vcpu *vcpu) |
6aa8b732 | 5272 | { |
8fe8ab46 | 5273 | struct msr_data msr; |
ad312c7c ZX |
5274 | u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX]; |
5275 | u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u) | |
5276 | | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32); | |
6aa8b732 | 5277 | |
8fe8ab46 WA |
5278 | msr.data = data; |
5279 | msr.index = ecx; | |
5280 | msr.host_initiated = false; | |
854e8bb1 | 5281 | if (kvm_set_msr(vcpu, &msr) != 0) { |
59200273 | 5282 | trace_kvm_msr_write_ex(ecx, data); |
c1a5d4f9 | 5283 | kvm_inject_gp(vcpu, 0); |
6aa8b732 AK |
5284 | return 1; |
5285 | } | |
5286 | ||
59200273 | 5287 | trace_kvm_msr_write(ecx, data); |
6aa8b732 AK |
5288 | skip_emulated_instruction(vcpu); |
5289 | return 1; | |
5290 | } | |
5291 | ||
851ba692 | 5292 | static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu) |
6e5d865c | 5293 | { |
3842d135 | 5294 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
6e5d865c YS |
5295 | return 1; |
5296 | } | |
5297 | ||
851ba692 | 5298 | static int handle_interrupt_window(struct kvm_vcpu *vcpu) |
6aa8b732 | 5299 | { |
85f455f7 ED |
5300 | u32 cpu_based_vm_exec_control; |
5301 | ||
5302 | /* clear pending irq */ | |
5303 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
5304 | cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING; | |
5305 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
2714d1d3 | 5306 | |
3842d135 AK |
5307 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
5308 | ||
a26bf12a | 5309 | ++vcpu->stat.irq_window_exits; |
2714d1d3 | 5310 | |
c1150d8c DL |
5311 | /* |
5312 | * If the user space waits to inject interrupts, exit as soon as | |
5313 | * possible | |
5314 | */ | |
8061823a | 5315 | if (!irqchip_in_kernel(vcpu->kvm) && |
851ba692 | 5316 | vcpu->run->request_interrupt_window && |
8061823a | 5317 | !kvm_cpu_has_interrupt(vcpu)) { |
851ba692 | 5318 | vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; |
c1150d8c DL |
5319 | return 0; |
5320 | } | |
6aa8b732 AK |
5321 | return 1; |
5322 | } | |
5323 | ||
851ba692 | 5324 | static int handle_halt(struct kvm_vcpu *vcpu) |
6aa8b732 AK |
5325 | { |
5326 | skip_emulated_instruction(vcpu); | |
d3bef15f | 5327 | return kvm_emulate_halt(vcpu); |
6aa8b732 AK |
5328 | } |
5329 | ||
851ba692 | 5330 | static int handle_vmcall(struct kvm_vcpu *vcpu) |
c21415e8 | 5331 | { |
510043da | 5332 | skip_emulated_instruction(vcpu); |
7aa81cc0 AL |
5333 | kvm_emulate_hypercall(vcpu); |
5334 | return 1; | |
c21415e8 IM |
5335 | } |
5336 | ||
ec25d5e6 GN |
5337 | static int handle_invd(struct kvm_vcpu *vcpu) |
5338 | { | |
51d8b661 | 5339 | return emulate_instruction(vcpu, 0) == EMULATE_DONE; |
ec25d5e6 GN |
5340 | } |
5341 | ||
851ba692 | 5342 | static int handle_invlpg(struct kvm_vcpu *vcpu) |
a7052897 | 5343 | { |
f9c617f6 | 5344 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
a7052897 MT |
5345 | |
5346 | kvm_mmu_invlpg(vcpu, exit_qualification); | |
5347 | skip_emulated_instruction(vcpu); | |
5348 | return 1; | |
5349 | } | |
5350 | ||
fee84b07 AK |
5351 | static int handle_rdpmc(struct kvm_vcpu *vcpu) |
5352 | { | |
5353 | int err; | |
5354 | ||
5355 | err = kvm_rdpmc(vcpu); | |
5356 | kvm_complete_insn_gp(vcpu, err); | |
5357 | ||
5358 | return 1; | |
5359 | } | |
5360 | ||
851ba692 | 5361 | static int handle_wbinvd(struct kvm_vcpu *vcpu) |
e5edaa01 ED |
5362 | { |
5363 | skip_emulated_instruction(vcpu); | |
f5f48ee1 | 5364 | kvm_emulate_wbinvd(vcpu); |
e5edaa01 ED |
5365 | return 1; |
5366 | } | |
5367 | ||
2acf923e DC |
5368 | static int handle_xsetbv(struct kvm_vcpu *vcpu) |
5369 | { | |
5370 | u64 new_bv = kvm_read_edx_eax(vcpu); | |
5371 | u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
5372 | ||
5373 | if (kvm_set_xcr(vcpu, index, new_bv) == 0) | |
5374 | skip_emulated_instruction(vcpu); | |
5375 | return 1; | |
5376 | } | |
5377 | ||
f53cd63c WL |
5378 | static int handle_xsaves(struct kvm_vcpu *vcpu) |
5379 | { | |
5380 | skip_emulated_instruction(vcpu); | |
5381 | WARN(1, "this should never happen\n"); | |
5382 | return 1; | |
5383 | } | |
5384 | ||
5385 | static int handle_xrstors(struct kvm_vcpu *vcpu) | |
5386 | { | |
5387 | skip_emulated_instruction(vcpu); | |
5388 | WARN(1, "this should never happen\n"); | |
5389 | return 1; | |
5390 | } | |
5391 | ||
851ba692 | 5392 | static int handle_apic_access(struct kvm_vcpu *vcpu) |
f78e0e2e | 5393 | { |
58fbbf26 KT |
5394 | if (likely(fasteoi)) { |
5395 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
5396 | int access_type, offset; | |
5397 | ||
5398 | access_type = exit_qualification & APIC_ACCESS_TYPE; | |
5399 | offset = exit_qualification & APIC_ACCESS_OFFSET; | |
5400 | /* | |
5401 | * Sane guest uses MOV to write EOI, with written value | |
5402 | * not cared. So make a short-circuit here by avoiding | |
5403 | * heavy instruction emulation. | |
5404 | */ | |
5405 | if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) && | |
5406 | (offset == APIC_EOI)) { | |
5407 | kvm_lapic_set_eoi(vcpu); | |
5408 | skip_emulated_instruction(vcpu); | |
5409 | return 1; | |
5410 | } | |
5411 | } | |
51d8b661 | 5412 | return emulate_instruction(vcpu, 0) == EMULATE_DONE; |
f78e0e2e SY |
5413 | } |
5414 | ||
c7c9c56c YZ |
5415 | static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu) |
5416 | { | |
5417 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
5418 | int vector = exit_qualification & 0xff; | |
5419 | ||
5420 | /* EOI-induced VM exit is trap-like and thus no need to adjust IP */ | |
5421 | kvm_apic_set_eoi_accelerated(vcpu, vector); | |
5422 | return 1; | |
5423 | } | |
5424 | ||
83d4c286 YZ |
5425 | static int handle_apic_write(struct kvm_vcpu *vcpu) |
5426 | { | |
5427 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
5428 | u32 offset = exit_qualification & 0xfff; | |
5429 | ||
5430 | /* APIC-write VM exit is trap-like and thus no need to adjust IP */ | |
5431 | kvm_apic_write_nodecode(vcpu, offset); | |
5432 | return 1; | |
5433 | } | |
5434 | ||
851ba692 | 5435 | static int handle_task_switch(struct kvm_vcpu *vcpu) |
37817f29 | 5436 | { |
60637aac | 5437 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
37817f29 | 5438 | unsigned long exit_qualification; |
e269fb21 JK |
5439 | bool has_error_code = false; |
5440 | u32 error_code = 0; | |
37817f29 | 5441 | u16 tss_selector; |
7f3d35fd | 5442 | int reason, type, idt_v, idt_index; |
64a7ec06 GN |
5443 | |
5444 | idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK); | |
7f3d35fd | 5445 | idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK); |
64a7ec06 | 5446 | type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK); |
37817f29 IE |
5447 | |
5448 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
5449 | ||
5450 | reason = (u32)exit_qualification >> 30; | |
64a7ec06 GN |
5451 | if (reason == TASK_SWITCH_GATE && idt_v) { |
5452 | switch (type) { | |
5453 | case INTR_TYPE_NMI_INTR: | |
5454 | vcpu->arch.nmi_injected = false; | |
654f06fc | 5455 | vmx_set_nmi_mask(vcpu, true); |
64a7ec06 GN |
5456 | break; |
5457 | case INTR_TYPE_EXT_INTR: | |
66fd3f7f | 5458 | case INTR_TYPE_SOFT_INTR: |
64a7ec06 GN |
5459 | kvm_clear_interrupt_queue(vcpu); |
5460 | break; | |
5461 | case INTR_TYPE_HARD_EXCEPTION: | |
e269fb21 JK |
5462 | if (vmx->idt_vectoring_info & |
5463 | VECTORING_INFO_DELIVER_CODE_MASK) { | |
5464 | has_error_code = true; | |
5465 | error_code = | |
5466 | vmcs_read32(IDT_VECTORING_ERROR_CODE); | |
5467 | } | |
5468 | /* fall through */ | |
64a7ec06 GN |
5469 | case INTR_TYPE_SOFT_EXCEPTION: |
5470 | kvm_clear_exception_queue(vcpu); | |
5471 | break; | |
5472 | default: | |
5473 | break; | |
5474 | } | |
60637aac | 5475 | } |
37817f29 IE |
5476 | tss_selector = exit_qualification; |
5477 | ||
64a7ec06 GN |
5478 | if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION && |
5479 | type != INTR_TYPE_EXT_INTR && | |
5480 | type != INTR_TYPE_NMI_INTR)) | |
5481 | skip_emulated_instruction(vcpu); | |
5482 | ||
7f3d35fd KW |
5483 | if (kvm_task_switch(vcpu, tss_selector, |
5484 | type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason, | |
5485 | has_error_code, error_code) == EMULATE_FAIL) { | |
acb54517 GN |
5486 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; |
5487 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
5488 | vcpu->run->internal.ndata = 0; | |
42dbaa5a | 5489 | return 0; |
acb54517 | 5490 | } |
42dbaa5a JK |
5491 | |
5492 | /* clear all local breakpoint enable flags */ | |
0e8a0996 | 5493 | vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~0x155); |
42dbaa5a JK |
5494 | |
5495 | /* | |
5496 | * TODO: What about debug traps on tss switch? | |
5497 | * Are we supposed to inject them and update dr6? | |
5498 | */ | |
5499 | ||
5500 | return 1; | |
37817f29 IE |
5501 | } |
5502 | ||
851ba692 | 5503 | static int handle_ept_violation(struct kvm_vcpu *vcpu) |
1439442c | 5504 | { |
f9c617f6 | 5505 | unsigned long exit_qualification; |
1439442c | 5506 | gpa_t gpa; |
4f5982a5 | 5507 | u32 error_code; |
1439442c | 5508 | int gla_validity; |
1439442c | 5509 | |
f9c617f6 | 5510 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
1439442c | 5511 | |
1439442c SY |
5512 | gla_validity = (exit_qualification >> 7) & 0x3; |
5513 | if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) { | |
5514 | printk(KERN_ERR "EPT: Handling EPT violation failed!\n"); | |
5515 | printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n", | |
5516 | (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS), | |
f9c617f6 | 5517 | vmcs_readl(GUEST_LINEAR_ADDRESS)); |
1439442c SY |
5518 | printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n", |
5519 | (long unsigned int)exit_qualification); | |
851ba692 AK |
5520 | vcpu->run->exit_reason = KVM_EXIT_UNKNOWN; |
5521 | vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION; | |
596ae895 | 5522 | return 0; |
1439442c SY |
5523 | } |
5524 | ||
0be9c7a8 GN |
5525 | /* |
5526 | * EPT violation happened while executing iret from NMI, | |
5527 | * "blocked by NMI" bit has to be set before next VM entry. | |
5528 | * There are errata that may cause this bit to not be set: | |
5529 | * AAK134, BY25. | |
5530 | */ | |
bcd1c294 GN |
5531 | if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) && |
5532 | cpu_has_virtual_nmis() && | |
5533 | (exit_qualification & INTR_INFO_UNBLOCK_NMI)) | |
0be9c7a8 GN |
5534 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI); |
5535 | ||
1439442c | 5536 | gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); |
229456fc | 5537 | trace_kvm_page_fault(gpa, exit_qualification); |
4f5982a5 XG |
5538 | |
5539 | /* It is a write fault? */ | |
81ed33e4 | 5540 | error_code = exit_qualification & PFERR_WRITE_MASK; |
25d92081 | 5541 | /* It is a fetch fault? */ |
81ed33e4 | 5542 | error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK; |
4f5982a5 | 5543 | /* ept page table is present? */ |
81ed33e4 | 5544 | error_code |= (exit_qualification >> 3) & PFERR_PRESENT_MASK; |
4f5982a5 | 5545 | |
25d92081 YZ |
5546 | vcpu->arch.exit_qualification = exit_qualification; |
5547 | ||
4f5982a5 | 5548 | return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0); |
1439442c SY |
5549 | } |
5550 | ||
68f89400 MT |
5551 | static u64 ept_rsvd_mask(u64 spte, int level) |
5552 | { | |
5553 | int i; | |
5554 | u64 mask = 0; | |
5555 | ||
5556 | for (i = 51; i > boot_cpu_data.x86_phys_bits; i--) | |
5557 | mask |= (1ULL << i); | |
5558 | ||
a32e8459 | 5559 | if (level == 4) |
68f89400 MT |
5560 | /* bits 7:3 reserved */ |
5561 | mask |= 0xf8; | |
a32e8459 WL |
5562 | else if (spte & (1ULL << 7)) |
5563 | /* | |
5564 | * 1GB/2MB page, bits 29:12 or 20:12 reserved respectively, | |
5565 | * level == 1 if the hypervisor is using the ignored bit 7. | |
5566 | */ | |
5567 | mask |= (PAGE_SIZE << ((level - 1) * 9)) - PAGE_SIZE; | |
5568 | else if (level > 1) | |
5569 | /* bits 6:3 reserved */ | |
5570 | mask |= 0x78; | |
68f89400 MT |
5571 | |
5572 | return mask; | |
5573 | } | |
5574 | ||
5575 | static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte, | |
5576 | int level) | |
5577 | { | |
5578 | printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level); | |
5579 | ||
5580 | /* 010b (write-only) */ | |
5581 | WARN_ON((spte & 0x7) == 0x2); | |
5582 | ||
5583 | /* 110b (write/execute) */ | |
5584 | WARN_ON((spte & 0x7) == 0x6); | |
5585 | ||
5586 | /* 100b (execute-only) and value not supported by logical processor */ | |
5587 | if (!cpu_has_vmx_ept_execute_only()) | |
5588 | WARN_ON((spte & 0x7) == 0x4); | |
5589 | ||
5590 | /* not 000b */ | |
5591 | if ((spte & 0x7)) { | |
5592 | u64 rsvd_bits = spte & ept_rsvd_mask(spte, level); | |
5593 | ||
5594 | if (rsvd_bits != 0) { | |
5595 | printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n", | |
5596 | __func__, rsvd_bits); | |
5597 | WARN_ON(1); | |
5598 | } | |
5599 | ||
a32e8459 WL |
5600 | /* bits 5:3 are _not_ reserved for large page or leaf page */ |
5601 | if ((rsvd_bits & 0x38) == 0) { | |
68f89400 MT |
5602 | u64 ept_mem_type = (spte & 0x38) >> 3; |
5603 | ||
5604 | if (ept_mem_type == 2 || ept_mem_type == 3 || | |
5605 | ept_mem_type == 7) { | |
5606 | printk(KERN_ERR "%s: ept_mem_type=0x%llx\n", | |
5607 | __func__, ept_mem_type); | |
5608 | WARN_ON(1); | |
5609 | } | |
5610 | } | |
5611 | } | |
5612 | } | |
5613 | ||
851ba692 | 5614 | static int handle_ept_misconfig(struct kvm_vcpu *vcpu) |
68f89400 MT |
5615 | { |
5616 | u64 sptes[4]; | |
ce88decf | 5617 | int nr_sptes, i, ret; |
68f89400 MT |
5618 | gpa_t gpa; |
5619 | ||
5620 | gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); | |
68c3b4d1 MT |
5621 | if (!kvm_io_bus_write(vcpu->kvm, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) { |
5622 | skip_emulated_instruction(vcpu); | |
5623 | return 1; | |
5624 | } | |
68f89400 | 5625 | |
ce88decf | 5626 | ret = handle_mmio_page_fault_common(vcpu, gpa, true); |
b37fbea6 | 5627 | if (likely(ret == RET_MMIO_PF_EMULATE)) |
ce88decf XG |
5628 | return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) == |
5629 | EMULATE_DONE; | |
f8f55942 XG |
5630 | |
5631 | if (unlikely(ret == RET_MMIO_PF_INVALID)) | |
5632 | return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0); | |
5633 | ||
b37fbea6 | 5634 | if (unlikely(ret == RET_MMIO_PF_RETRY)) |
ce88decf XG |
5635 | return 1; |
5636 | ||
5637 | /* It is the real ept misconfig */ | |
68f89400 MT |
5638 | printk(KERN_ERR "EPT: Misconfiguration.\n"); |
5639 | printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa); | |
5640 | ||
5641 | nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes); | |
5642 | ||
5643 | for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i) | |
5644 | ept_misconfig_inspect_spte(vcpu, sptes[i-1], i); | |
5645 | ||
851ba692 AK |
5646 | vcpu->run->exit_reason = KVM_EXIT_UNKNOWN; |
5647 | vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG; | |
68f89400 MT |
5648 | |
5649 | return 0; | |
5650 | } | |
5651 | ||
851ba692 | 5652 | static int handle_nmi_window(struct kvm_vcpu *vcpu) |
f08864b4 SY |
5653 | { |
5654 | u32 cpu_based_vm_exec_control; | |
5655 | ||
5656 | /* clear pending NMI */ | |
5657 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
5658 | cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING; | |
5659 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
5660 | ++vcpu->stat.nmi_window_exits; | |
3842d135 | 5661 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
f08864b4 SY |
5662 | |
5663 | return 1; | |
5664 | } | |
5665 | ||
80ced186 | 5666 | static int handle_invalid_guest_state(struct kvm_vcpu *vcpu) |
ea953ef0 | 5667 | { |
8b3079a5 AK |
5668 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
5669 | enum emulation_result err = EMULATE_DONE; | |
80ced186 | 5670 | int ret = 1; |
49e9d557 AK |
5671 | u32 cpu_exec_ctrl; |
5672 | bool intr_window_requested; | |
b8405c18 | 5673 | unsigned count = 130; |
49e9d557 AK |
5674 | |
5675 | cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
5676 | intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING; | |
ea953ef0 | 5677 | |
98eb2f8b | 5678 | while (vmx->emulation_required && count-- != 0) { |
bdea48e3 | 5679 | if (intr_window_requested && vmx_interrupt_allowed(vcpu)) |
49e9d557 AK |
5680 | return handle_interrupt_window(&vmx->vcpu); |
5681 | ||
de87dcdd AK |
5682 | if (test_bit(KVM_REQ_EVENT, &vcpu->requests)) |
5683 | return 1; | |
5684 | ||
991eebf9 | 5685 | err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE); |
ea953ef0 | 5686 | |
ac0a48c3 | 5687 | if (err == EMULATE_USER_EXIT) { |
94452b9e | 5688 | ++vcpu->stat.mmio_exits; |
80ced186 MG |
5689 | ret = 0; |
5690 | goto out; | |
5691 | } | |
1d5a4d9b | 5692 | |
de5f70e0 AK |
5693 | if (err != EMULATE_DONE) { |
5694 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
5695 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
5696 | vcpu->run->internal.ndata = 0; | |
6d77dbfc | 5697 | return 0; |
de5f70e0 | 5698 | } |
ea953ef0 | 5699 | |
8d76c49e GN |
5700 | if (vcpu->arch.halt_request) { |
5701 | vcpu->arch.halt_request = 0; | |
5702 | ret = kvm_emulate_halt(vcpu); | |
5703 | goto out; | |
5704 | } | |
5705 | ||
ea953ef0 | 5706 | if (signal_pending(current)) |
80ced186 | 5707 | goto out; |
ea953ef0 MG |
5708 | if (need_resched()) |
5709 | schedule(); | |
5710 | } | |
5711 | ||
80ced186 MG |
5712 | out: |
5713 | return ret; | |
ea953ef0 MG |
5714 | } |
5715 | ||
b4a2d31d RK |
5716 | static int __grow_ple_window(int val) |
5717 | { | |
5718 | if (ple_window_grow < 1) | |
5719 | return ple_window; | |
5720 | ||
5721 | val = min(val, ple_window_actual_max); | |
5722 | ||
5723 | if (ple_window_grow < ple_window) | |
5724 | val *= ple_window_grow; | |
5725 | else | |
5726 | val += ple_window_grow; | |
5727 | ||
5728 | return val; | |
5729 | } | |
5730 | ||
5731 | static int __shrink_ple_window(int val, int modifier, int minimum) | |
5732 | { | |
5733 | if (modifier < 1) | |
5734 | return ple_window; | |
5735 | ||
5736 | if (modifier < ple_window) | |
5737 | val /= modifier; | |
5738 | else | |
5739 | val -= modifier; | |
5740 | ||
5741 | return max(val, minimum); | |
5742 | } | |
5743 | ||
5744 | static void grow_ple_window(struct kvm_vcpu *vcpu) | |
5745 | { | |
5746 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
5747 | int old = vmx->ple_window; | |
5748 | ||
5749 | vmx->ple_window = __grow_ple_window(old); | |
5750 | ||
5751 | if (vmx->ple_window != old) | |
5752 | vmx->ple_window_dirty = true; | |
7b46268d RK |
5753 | |
5754 | trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old); | |
b4a2d31d RK |
5755 | } |
5756 | ||
5757 | static void shrink_ple_window(struct kvm_vcpu *vcpu) | |
5758 | { | |
5759 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
5760 | int old = vmx->ple_window; | |
5761 | ||
5762 | vmx->ple_window = __shrink_ple_window(old, | |
5763 | ple_window_shrink, ple_window); | |
5764 | ||
5765 | if (vmx->ple_window != old) | |
5766 | vmx->ple_window_dirty = true; | |
7b46268d RK |
5767 | |
5768 | trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old); | |
b4a2d31d RK |
5769 | } |
5770 | ||
5771 | /* | |
5772 | * ple_window_actual_max is computed to be one grow_ple_window() below | |
5773 | * ple_window_max. (See __grow_ple_window for the reason.) | |
5774 | * This prevents overflows, because ple_window_max is int. | |
5775 | * ple_window_max effectively rounded down to a multiple of ple_window_grow in | |
5776 | * this process. | |
5777 | * ple_window_max is also prevented from setting vmx->ple_window < ple_window. | |
5778 | */ | |
5779 | static void update_ple_window_actual_max(void) | |
5780 | { | |
5781 | ple_window_actual_max = | |
5782 | __shrink_ple_window(max(ple_window_max, ple_window), | |
5783 | ple_window_grow, INT_MIN); | |
5784 | } | |
5785 | ||
f2c7648d TC |
5786 | static __init int hardware_setup(void) |
5787 | { | |
34a1cd60 TC |
5788 | int r = -ENOMEM, i, msr; |
5789 | ||
5790 | rdmsrl_safe(MSR_EFER, &host_efer); | |
5791 | ||
5792 | for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) | |
5793 | kvm_define_shared_msr(i, vmx_msr_index[i]); | |
5794 | ||
5795 | vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL); | |
5796 | if (!vmx_io_bitmap_a) | |
5797 | return r; | |
5798 | ||
5799 | vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL); | |
5800 | if (!vmx_io_bitmap_b) | |
5801 | goto out; | |
5802 | ||
5803 | vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL); | |
5804 | if (!vmx_msr_bitmap_legacy) | |
5805 | goto out1; | |
5806 | ||
5807 | vmx_msr_bitmap_legacy_x2apic = | |
5808 | (unsigned long *)__get_free_page(GFP_KERNEL); | |
5809 | if (!vmx_msr_bitmap_legacy_x2apic) | |
5810 | goto out2; | |
5811 | ||
5812 | vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL); | |
5813 | if (!vmx_msr_bitmap_longmode) | |
5814 | goto out3; | |
5815 | ||
5816 | vmx_msr_bitmap_longmode_x2apic = | |
5817 | (unsigned long *)__get_free_page(GFP_KERNEL); | |
5818 | if (!vmx_msr_bitmap_longmode_x2apic) | |
5819 | goto out4; | |
5820 | vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL); | |
5821 | if (!vmx_vmread_bitmap) | |
5822 | goto out5; | |
5823 | ||
5824 | vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL); | |
5825 | if (!vmx_vmwrite_bitmap) | |
5826 | goto out6; | |
5827 | ||
5828 | memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE); | |
5829 | memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE); | |
5830 | ||
5831 | /* | |
5832 | * Allow direct access to the PC debug port (it is often used for I/O | |
5833 | * delays, but the vmexits simply slow things down). | |
5834 | */ | |
5835 | memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE); | |
5836 | clear_bit(0x80, vmx_io_bitmap_a); | |
5837 | ||
5838 | memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE); | |
5839 | ||
5840 | memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE); | |
5841 | memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE); | |
5842 | ||
34a1cd60 TC |
5843 | if (setup_vmcs_config(&vmcs_config) < 0) { |
5844 | r = -EIO; | |
5845 | goto out7; | |
baa03522 | 5846 | } |
f2c7648d TC |
5847 | |
5848 | if (boot_cpu_has(X86_FEATURE_NX)) | |
5849 | kvm_enable_efer_bits(EFER_NX); | |
5850 | ||
5851 | if (!cpu_has_vmx_vpid()) | |
5852 | enable_vpid = 0; | |
5853 | if (!cpu_has_vmx_shadow_vmcs()) | |
5854 | enable_shadow_vmcs = 0; | |
5855 | if (enable_shadow_vmcs) | |
5856 | init_vmcs_shadow_fields(); | |
5857 | ||
5858 | if (!cpu_has_vmx_ept() || | |
5859 | !cpu_has_vmx_ept_4levels()) { | |
5860 | enable_ept = 0; | |
5861 | enable_unrestricted_guest = 0; | |
5862 | enable_ept_ad_bits = 0; | |
5863 | } | |
5864 | ||
5865 | if (!cpu_has_vmx_ept_ad_bits()) | |
5866 | enable_ept_ad_bits = 0; | |
5867 | ||
5868 | if (!cpu_has_vmx_unrestricted_guest()) | |
5869 | enable_unrestricted_guest = 0; | |
5870 | ||
5871 | if (!cpu_has_vmx_flexpriority()) { | |
5872 | flexpriority_enabled = 0; | |
5873 | ||
5874 | /* | |
5875 | * set_apic_access_page_addr() is used to reload apic access | |
5876 | * page upon invalidation. No need to do anything if the | |
5877 | * processor does not have the APIC_ACCESS_ADDR VMCS field. | |
5878 | */ | |
5879 | kvm_x86_ops->set_apic_access_page_addr = NULL; | |
5880 | } | |
5881 | ||
5882 | if (!cpu_has_vmx_tpr_shadow()) | |
5883 | kvm_x86_ops->update_cr8_intercept = NULL; | |
5884 | ||
5885 | if (enable_ept && !cpu_has_vmx_ept_2m_page()) | |
5886 | kvm_disable_largepages(); | |
5887 | ||
5888 | if (!cpu_has_vmx_ple()) | |
5889 | ple_gap = 0; | |
5890 | ||
5891 | if (!cpu_has_vmx_apicv()) | |
5892 | enable_apicv = 0; | |
5893 | ||
5894 | if (enable_apicv) | |
5895 | kvm_x86_ops->update_cr8_intercept = NULL; | |
5896 | else { | |
5897 | kvm_x86_ops->hwapic_irr_update = NULL; | |
5898 | kvm_x86_ops->deliver_posted_interrupt = NULL; | |
5899 | kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy; | |
5900 | } | |
5901 | ||
5902 | if (nested) | |
5903 | nested_vmx_setup_ctls_msrs(); | |
5904 | ||
baa03522 TC |
5905 | vmx_disable_intercept_for_msr(MSR_FS_BASE, false); |
5906 | vmx_disable_intercept_for_msr(MSR_GS_BASE, false); | |
5907 | vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true); | |
5908 | vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false); | |
5909 | vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false); | |
5910 | vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false); | |
5911 | vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true); | |
5912 | ||
5913 | memcpy(vmx_msr_bitmap_legacy_x2apic, | |
5914 | vmx_msr_bitmap_legacy, PAGE_SIZE); | |
5915 | memcpy(vmx_msr_bitmap_longmode_x2apic, | |
5916 | vmx_msr_bitmap_longmode, PAGE_SIZE); | |
5917 | ||
5918 | if (enable_apicv) { | |
5919 | for (msr = 0x800; msr <= 0x8ff; msr++) | |
5920 | vmx_disable_intercept_msr_read_x2apic(msr); | |
5921 | ||
5922 | /* According SDM, in x2apic mode, the whole id reg is used. | |
5923 | * But in KVM, it only use the highest eight bits. Need to | |
5924 | * intercept it */ | |
5925 | vmx_enable_intercept_msr_read_x2apic(0x802); | |
5926 | /* TMCCT */ | |
5927 | vmx_enable_intercept_msr_read_x2apic(0x839); | |
5928 | /* TPR */ | |
5929 | vmx_disable_intercept_msr_write_x2apic(0x808); | |
5930 | /* EOI */ | |
5931 | vmx_disable_intercept_msr_write_x2apic(0x80b); | |
5932 | /* SELF-IPI */ | |
5933 | vmx_disable_intercept_msr_write_x2apic(0x83f); | |
5934 | } | |
5935 | ||
5936 | if (enable_ept) { | |
5937 | kvm_mmu_set_mask_ptes(0ull, | |
5938 | (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull, | |
5939 | (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull, | |
5940 | 0ull, VMX_EPT_EXECUTABLE_MASK); | |
5941 | ept_set_mmio_spte_mask(); | |
5942 | kvm_enable_tdp(); | |
5943 | } else | |
5944 | kvm_disable_tdp(); | |
5945 | ||
5946 | update_ple_window_actual_max(); | |
5947 | ||
f2c7648d | 5948 | return alloc_kvm_area(); |
34a1cd60 TC |
5949 | |
5950 | out7: | |
5951 | free_page((unsigned long)vmx_vmwrite_bitmap); | |
5952 | out6: | |
5953 | free_page((unsigned long)vmx_vmread_bitmap); | |
5954 | out5: | |
5955 | free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic); | |
5956 | out4: | |
5957 | free_page((unsigned long)vmx_msr_bitmap_longmode); | |
5958 | out3: | |
5959 | free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic); | |
5960 | out2: | |
5961 | free_page((unsigned long)vmx_msr_bitmap_legacy); | |
5962 | out1: | |
5963 | free_page((unsigned long)vmx_io_bitmap_b); | |
5964 | out: | |
5965 | free_page((unsigned long)vmx_io_bitmap_a); | |
5966 | ||
5967 | return r; | |
f2c7648d TC |
5968 | } |
5969 | ||
5970 | static __exit void hardware_unsetup(void) | |
5971 | { | |
34a1cd60 TC |
5972 | free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic); |
5973 | free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic); | |
5974 | free_page((unsigned long)vmx_msr_bitmap_legacy); | |
5975 | free_page((unsigned long)vmx_msr_bitmap_longmode); | |
5976 | free_page((unsigned long)vmx_io_bitmap_b); | |
5977 | free_page((unsigned long)vmx_io_bitmap_a); | |
5978 | free_page((unsigned long)vmx_vmwrite_bitmap); | |
5979 | free_page((unsigned long)vmx_vmread_bitmap); | |
5980 | ||
f2c7648d TC |
5981 | free_kvm_area(); |
5982 | } | |
5983 | ||
4b8d54f9 ZE |
5984 | /* |
5985 | * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE | |
5986 | * exiting, so only get here on cpu with PAUSE-Loop-Exiting. | |
5987 | */ | |
9fb41ba8 | 5988 | static int handle_pause(struct kvm_vcpu *vcpu) |
4b8d54f9 | 5989 | { |
b4a2d31d RK |
5990 | if (ple_gap) |
5991 | grow_ple_window(vcpu); | |
5992 | ||
4b8d54f9 ZE |
5993 | skip_emulated_instruction(vcpu); |
5994 | kvm_vcpu_on_spin(vcpu); | |
5995 | ||
5996 | return 1; | |
5997 | } | |
5998 | ||
87c00572 | 5999 | static int handle_nop(struct kvm_vcpu *vcpu) |
59708670 | 6000 | { |
87c00572 | 6001 | skip_emulated_instruction(vcpu); |
59708670 SY |
6002 | return 1; |
6003 | } | |
6004 | ||
87c00572 GS |
6005 | static int handle_mwait(struct kvm_vcpu *vcpu) |
6006 | { | |
6007 | printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n"); | |
6008 | return handle_nop(vcpu); | |
6009 | } | |
6010 | ||
6011 | static int handle_monitor(struct kvm_vcpu *vcpu) | |
6012 | { | |
6013 | printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n"); | |
6014 | return handle_nop(vcpu); | |
6015 | } | |
6016 | ||
ff2f6fe9 NHE |
6017 | /* |
6018 | * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12. | |
6019 | * We could reuse a single VMCS for all the L2 guests, but we also want the | |
6020 | * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this | |
6021 | * allows keeping them loaded on the processor, and in the future will allow | |
6022 | * optimizations where prepare_vmcs02 doesn't need to set all the fields on | |
6023 | * every entry if they never change. | |
6024 | * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE | |
6025 | * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first. | |
6026 | * | |
6027 | * The following functions allocate and free a vmcs02 in this pool. | |
6028 | */ | |
6029 | ||
6030 | /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */ | |
6031 | static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx) | |
6032 | { | |
6033 | struct vmcs02_list *item; | |
6034 | list_for_each_entry(item, &vmx->nested.vmcs02_pool, list) | |
6035 | if (item->vmptr == vmx->nested.current_vmptr) { | |
6036 | list_move(&item->list, &vmx->nested.vmcs02_pool); | |
6037 | return &item->vmcs02; | |
6038 | } | |
6039 | ||
6040 | if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) { | |
6041 | /* Recycle the least recently used VMCS. */ | |
6042 | item = list_entry(vmx->nested.vmcs02_pool.prev, | |
6043 | struct vmcs02_list, list); | |
6044 | item->vmptr = vmx->nested.current_vmptr; | |
6045 | list_move(&item->list, &vmx->nested.vmcs02_pool); | |
6046 | return &item->vmcs02; | |
6047 | } | |
6048 | ||
6049 | /* Create a new VMCS */ | |
0fa24ce3 | 6050 | item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL); |
ff2f6fe9 NHE |
6051 | if (!item) |
6052 | return NULL; | |
6053 | item->vmcs02.vmcs = alloc_vmcs(); | |
6054 | if (!item->vmcs02.vmcs) { | |
6055 | kfree(item); | |
6056 | return NULL; | |
6057 | } | |
6058 | loaded_vmcs_init(&item->vmcs02); | |
6059 | item->vmptr = vmx->nested.current_vmptr; | |
6060 | list_add(&(item->list), &(vmx->nested.vmcs02_pool)); | |
6061 | vmx->nested.vmcs02_num++; | |
6062 | return &item->vmcs02; | |
6063 | } | |
6064 | ||
6065 | /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */ | |
6066 | static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr) | |
6067 | { | |
6068 | struct vmcs02_list *item; | |
6069 | list_for_each_entry(item, &vmx->nested.vmcs02_pool, list) | |
6070 | if (item->vmptr == vmptr) { | |
6071 | free_loaded_vmcs(&item->vmcs02); | |
6072 | list_del(&item->list); | |
6073 | kfree(item); | |
6074 | vmx->nested.vmcs02_num--; | |
6075 | return; | |
6076 | } | |
6077 | } | |
6078 | ||
6079 | /* | |
6080 | * Free all VMCSs saved for this vcpu, except the one pointed by | |
4fa7734c PB |
6081 | * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs |
6082 | * must be &vmx->vmcs01. | |
ff2f6fe9 NHE |
6083 | */ |
6084 | static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx) | |
6085 | { | |
6086 | struct vmcs02_list *item, *n; | |
4fa7734c PB |
6087 | |
6088 | WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01); | |
ff2f6fe9 | 6089 | list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) { |
4fa7734c PB |
6090 | /* |
6091 | * Something will leak if the above WARN triggers. Better than | |
6092 | * a use-after-free. | |
6093 | */ | |
6094 | if (vmx->loaded_vmcs == &item->vmcs02) | |
6095 | continue; | |
6096 | ||
6097 | free_loaded_vmcs(&item->vmcs02); | |
ff2f6fe9 NHE |
6098 | list_del(&item->list); |
6099 | kfree(item); | |
4fa7734c | 6100 | vmx->nested.vmcs02_num--; |
ff2f6fe9 | 6101 | } |
ff2f6fe9 NHE |
6102 | } |
6103 | ||
0658fbaa ACL |
6104 | /* |
6105 | * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(), | |
6106 | * set the success or error code of an emulated VMX instruction, as specified | |
6107 | * by Vol 2B, VMX Instruction Reference, "Conventions". | |
6108 | */ | |
6109 | static void nested_vmx_succeed(struct kvm_vcpu *vcpu) | |
6110 | { | |
6111 | vmx_set_rflags(vcpu, vmx_get_rflags(vcpu) | |
6112 | & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | | |
6113 | X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF)); | |
6114 | } | |
6115 | ||
6116 | static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu) | |
6117 | { | |
6118 | vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu) | |
6119 | & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF | | |
6120 | X86_EFLAGS_SF | X86_EFLAGS_OF)) | |
6121 | | X86_EFLAGS_CF); | |
6122 | } | |
6123 | ||
145c28dd | 6124 | static void nested_vmx_failValid(struct kvm_vcpu *vcpu, |
0658fbaa ACL |
6125 | u32 vm_instruction_error) |
6126 | { | |
6127 | if (to_vmx(vcpu)->nested.current_vmptr == -1ull) { | |
6128 | /* | |
6129 | * failValid writes the error number to the current VMCS, which | |
6130 | * can't be done there isn't a current VMCS. | |
6131 | */ | |
6132 | nested_vmx_failInvalid(vcpu); | |
6133 | return; | |
6134 | } | |
6135 | vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu) | |
6136 | & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | | |
6137 | X86_EFLAGS_SF | X86_EFLAGS_OF)) | |
6138 | | X86_EFLAGS_ZF); | |
6139 | get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error; | |
6140 | /* | |
6141 | * We don't need to force a shadow sync because | |
6142 | * VM_INSTRUCTION_ERROR is not shadowed | |
6143 | */ | |
6144 | } | |
145c28dd | 6145 | |
f4124500 JK |
6146 | static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer) |
6147 | { | |
6148 | struct vcpu_vmx *vmx = | |
6149 | container_of(timer, struct vcpu_vmx, nested.preemption_timer); | |
6150 | ||
6151 | vmx->nested.preemption_timer_expired = true; | |
6152 | kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu); | |
6153 | kvm_vcpu_kick(&vmx->vcpu); | |
6154 | ||
6155 | return HRTIMER_NORESTART; | |
6156 | } | |
6157 | ||
19677e32 BD |
6158 | /* |
6159 | * Decode the memory-address operand of a vmx instruction, as recorded on an | |
6160 | * exit caused by such an instruction (run by a guest hypervisor). | |
6161 | * On success, returns 0. When the operand is invalid, returns 1 and throws | |
6162 | * #UD or #GP. | |
6163 | */ | |
6164 | static int get_vmx_mem_address(struct kvm_vcpu *vcpu, | |
6165 | unsigned long exit_qualification, | |
6166 | u32 vmx_instruction_info, gva_t *ret) | |
6167 | { | |
6168 | /* | |
6169 | * According to Vol. 3B, "Information for VM Exits Due to Instruction | |
6170 | * Execution", on an exit, vmx_instruction_info holds most of the | |
6171 | * addressing components of the operand. Only the displacement part | |
6172 | * is put in exit_qualification (see 3B, "Basic VM-Exit Information"). | |
6173 | * For how an actual address is calculated from all these components, | |
6174 | * refer to Vol. 1, "Operand Addressing". | |
6175 | */ | |
6176 | int scaling = vmx_instruction_info & 3; | |
6177 | int addr_size = (vmx_instruction_info >> 7) & 7; | |
6178 | bool is_reg = vmx_instruction_info & (1u << 10); | |
6179 | int seg_reg = (vmx_instruction_info >> 15) & 7; | |
6180 | int index_reg = (vmx_instruction_info >> 18) & 0xf; | |
6181 | bool index_is_valid = !(vmx_instruction_info & (1u << 22)); | |
6182 | int base_reg = (vmx_instruction_info >> 23) & 0xf; | |
6183 | bool base_is_valid = !(vmx_instruction_info & (1u << 27)); | |
6184 | ||
6185 | if (is_reg) { | |
6186 | kvm_queue_exception(vcpu, UD_VECTOR); | |
6187 | return 1; | |
6188 | } | |
6189 | ||
6190 | /* Addr = segment_base + offset */ | |
6191 | /* offset = base + [index * scale] + displacement */ | |
6192 | *ret = vmx_get_segment_base(vcpu, seg_reg); | |
6193 | if (base_is_valid) | |
6194 | *ret += kvm_register_read(vcpu, base_reg); | |
6195 | if (index_is_valid) | |
6196 | *ret += kvm_register_read(vcpu, index_reg)<<scaling; | |
6197 | *ret += exit_qualification; /* holds the displacement */ | |
6198 | ||
6199 | if (addr_size == 1) /* 32 bit */ | |
6200 | *ret &= 0xffffffff; | |
6201 | ||
6202 | /* | |
6203 | * TODO: throw #GP (and return 1) in various cases that the VM* | |
6204 | * instructions require it - e.g., offset beyond segment limit, | |
6205 | * unusable or unreadable/unwritable segment, non-canonical 64-bit | |
6206 | * address, and so on. Currently these are not checked. | |
6207 | */ | |
6208 | return 0; | |
6209 | } | |
6210 | ||
3573e22c BD |
6211 | /* |
6212 | * This function performs the various checks including | |
6213 | * - if it's 4KB aligned | |
6214 | * - No bits beyond the physical address width are set | |
6215 | * - Returns 0 on success or else 1 | |
4291b588 | 6216 | * (Intel SDM Section 30.3) |
3573e22c | 6217 | */ |
4291b588 BD |
6218 | static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason, |
6219 | gpa_t *vmpointer) | |
3573e22c BD |
6220 | { |
6221 | gva_t gva; | |
6222 | gpa_t vmptr; | |
6223 | struct x86_exception e; | |
6224 | struct page *page; | |
6225 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
6226 | int maxphyaddr = cpuid_maxphyaddr(vcpu); | |
6227 | ||
6228 | if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION), | |
6229 | vmcs_read32(VMX_INSTRUCTION_INFO), &gva)) | |
6230 | return 1; | |
6231 | ||
6232 | if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr, | |
6233 | sizeof(vmptr), &e)) { | |
6234 | kvm_inject_page_fault(vcpu, &e); | |
6235 | return 1; | |
6236 | } | |
6237 | ||
6238 | switch (exit_reason) { | |
6239 | case EXIT_REASON_VMON: | |
6240 | /* | |
6241 | * SDM 3: 24.11.5 | |
6242 | * The first 4 bytes of VMXON region contain the supported | |
6243 | * VMCS revision identifier | |
6244 | * | |
6245 | * Note - IA32_VMX_BASIC[48] will never be 1 | |
6246 | * for the nested case; | |
6247 | * which replaces physical address width with 32 | |
6248 | * | |
6249 | */ | |
bc39c4db | 6250 | if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) { |
3573e22c BD |
6251 | nested_vmx_failInvalid(vcpu); |
6252 | skip_emulated_instruction(vcpu); | |
6253 | return 1; | |
6254 | } | |
6255 | ||
6256 | page = nested_get_page(vcpu, vmptr); | |
6257 | if (page == NULL || | |
6258 | *(u32 *)kmap(page) != VMCS12_REVISION) { | |
6259 | nested_vmx_failInvalid(vcpu); | |
6260 | kunmap(page); | |
6261 | skip_emulated_instruction(vcpu); | |
6262 | return 1; | |
6263 | } | |
6264 | kunmap(page); | |
6265 | vmx->nested.vmxon_ptr = vmptr; | |
6266 | break; | |
4291b588 | 6267 | case EXIT_REASON_VMCLEAR: |
bc39c4db | 6268 | if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) { |
4291b588 BD |
6269 | nested_vmx_failValid(vcpu, |
6270 | VMXERR_VMCLEAR_INVALID_ADDRESS); | |
6271 | skip_emulated_instruction(vcpu); | |
6272 | return 1; | |
6273 | } | |
6274 | ||
6275 | if (vmptr == vmx->nested.vmxon_ptr) { | |
6276 | nested_vmx_failValid(vcpu, | |
6277 | VMXERR_VMCLEAR_VMXON_POINTER); | |
6278 | skip_emulated_instruction(vcpu); | |
6279 | return 1; | |
6280 | } | |
6281 | break; | |
6282 | case EXIT_REASON_VMPTRLD: | |
bc39c4db | 6283 | if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) { |
4291b588 BD |
6284 | nested_vmx_failValid(vcpu, |
6285 | VMXERR_VMPTRLD_INVALID_ADDRESS); | |
6286 | skip_emulated_instruction(vcpu); | |
6287 | return 1; | |
6288 | } | |
3573e22c | 6289 | |
4291b588 BD |
6290 | if (vmptr == vmx->nested.vmxon_ptr) { |
6291 | nested_vmx_failValid(vcpu, | |
6292 | VMXERR_VMCLEAR_VMXON_POINTER); | |
6293 | skip_emulated_instruction(vcpu); | |
6294 | return 1; | |
6295 | } | |
6296 | break; | |
3573e22c BD |
6297 | default: |
6298 | return 1; /* shouldn't happen */ | |
6299 | } | |
6300 | ||
4291b588 BD |
6301 | if (vmpointer) |
6302 | *vmpointer = vmptr; | |
3573e22c BD |
6303 | return 0; |
6304 | } | |
6305 | ||
ec378aee NHE |
6306 | /* |
6307 | * Emulate the VMXON instruction. | |
6308 | * Currently, we just remember that VMX is active, and do not save or even | |
6309 | * inspect the argument to VMXON (the so-called "VMXON pointer") because we | |
6310 | * do not currently need to store anything in that guest-allocated memory | |
6311 | * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their | |
6312 | * argument is different from the VMXON pointer (which the spec says they do). | |
6313 | */ | |
6314 | static int handle_vmon(struct kvm_vcpu *vcpu) | |
6315 | { | |
6316 | struct kvm_segment cs; | |
6317 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
8de48833 | 6318 | struct vmcs *shadow_vmcs; |
b3897a49 NHE |
6319 | const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED |
6320 | | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; | |
ec378aee NHE |
6321 | |
6322 | /* The Intel VMX Instruction Reference lists a bunch of bits that | |
6323 | * are prerequisite to running VMXON, most notably cr4.VMXE must be | |
6324 | * set to 1 (see vmx_set_cr4() for when we allow the guest to set this). | |
6325 | * Otherwise, we should fail with #UD. We test these now: | |
6326 | */ | |
6327 | if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) || | |
6328 | !kvm_read_cr0_bits(vcpu, X86_CR0_PE) || | |
6329 | (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) { | |
6330 | kvm_queue_exception(vcpu, UD_VECTOR); | |
6331 | return 1; | |
6332 | } | |
6333 | ||
6334 | vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
6335 | if (is_long_mode(vcpu) && !cs.l) { | |
6336 | kvm_queue_exception(vcpu, UD_VECTOR); | |
6337 | return 1; | |
6338 | } | |
6339 | ||
6340 | if (vmx_get_cpl(vcpu)) { | |
6341 | kvm_inject_gp(vcpu, 0); | |
6342 | return 1; | |
6343 | } | |
3573e22c | 6344 | |
4291b588 | 6345 | if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL)) |
3573e22c BD |
6346 | return 1; |
6347 | ||
145c28dd AG |
6348 | if (vmx->nested.vmxon) { |
6349 | nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION); | |
6350 | skip_emulated_instruction(vcpu); | |
6351 | return 1; | |
6352 | } | |
b3897a49 NHE |
6353 | |
6354 | if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES) | |
6355 | != VMXON_NEEDED_FEATURES) { | |
6356 | kvm_inject_gp(vcpu, 0); | |
6357 | return 1; | |
6358 | } | |
6359 | ||
8de48833 AG |
6360 | if (enable_shadow_vmcs) { |
6361 | shadow_vmcs = alloc_vmcs(); | |
6362 | if (!shadow_vmcs) | |
6363 | return -ENOMEM; | |
6364 | /* mark vmcs as shadow */ | |
6365 | shadow_vmcs->revision_id |= (1u << 31); | |
6366 | /* init shadow vmcs */ | |
6367 | vmcs_clear(shadow_vmcs); | |
6368 | vmx->nested.current_shadow_vmcs = shadow_vmcs; | |
6369 | } | |
ec378aee | 6370 | |
ff2f6fe9 NHE |
6371 | INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool)); |
6372 | vmx->nested.vmcs02_num = 0; | |
6373 | ||
f4124500 JK |
6374 | hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC, |
6375 | HRTIMER_MODE_REL); | |
6376 | vmx->nested.preemption_timer.function = vmx_preemption_timer_fn; | |
6377 | ||
ec378aee NHE |
6378 | vmx->nested.vmxon = true; |
6379 | ||
6380 | skip_emulated_instruction(vcpu); | |
a25eb114 | 6381 | nested_vmx_succeed(vcpu); |
ec378aee NHE |
6382 | return 1; |
6383 | } | |
6384 | ||
6385 | /* | |
6386 | * Intel's VMX Instruction Reference specifies a common set of prerequisites | |
6387 | * for running VMX instructions (except VMXON, whose prerequisites are | |
6388 | * slightly different). It also specifies what exception to inject otherwise. | |
6389 | */ | |
6390 | static int nested_vmx_check_permission(struct kvm_vcpu *vcpu) | |
6391 | { | |
6392 | struct kvm_segment cs; | |
6393 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
6394 | ||
6395 | if (!vmx->nested.vmxon) { | |
6396 | kvm_queue_exception(vcpu, UD_VECTOR); | |
6397 | return 0; | |
6398 | } | |
6399 | ||
6400 | vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
6401 | if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) || | |
6402 | (is_long_mode(vcpu) && !cs.l)) { | |
6403 | kvm_queue_exception(vcpu, UD_VECTOR); | |
6404 | return 0; | |
6405 | } | |
6406 | ||
6407 | if (vmx_get_cpl(vcpu)) { | |
6408 | kvm_inject_gp(vcpu, 0); | |
6409 | return 0; | |
6410 | } | |
6411 | ||
6412 | return 1; | |
6413 | } | |
6414 | ||
e7953d7f AG |
6415 | static inline void nested_release_vmcs12(struct vcpu_vmx *vmx) |
6416 | { | |
8a1b9dd0 | 6417 | u32 exec_control; |
9a2a05b9 PB |
6418 | if (vmx->nested.current_vmptr == -1ull) |
6419 | return; | |
6420 | ||
6421 | /* current_vmptr and current_vmcs12 are always set/reset together */ | |
6422 | if (WARN_ON(vmx->nested.current_vmcs12 == NULL)) | |
6423 | return; | |
6424 | ||
012f83cb | 6425 | if (enable_shadow_vmcs) { |
9a2a05b9 PB |
6426 | /* copy to memory all shadowed fields in case |
6427 | they were modified */ | |
6428 | copy_shadow_to_vmcs12(vmx); | |
6429 | vmx->nested.sync_shadow_vmcs = false; | |
6430 | exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL); | |
6431 | exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS; | |
6432 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control); | |
6433 | vmcs_write64(VMCS_LINK_POINTER, -1ull); | |
012f83cb | 6434 | } |
e7953d7f AG |
6435 | kunmap(vmx->nested.current_vmcs12_page); |
6436 | nested_release_page(vmx->nested.current_vmcs12_page); | |
9a2a05b9 PB |
6437 | vmx->nested.current_vmptr = -1ull; |
6438 | vmx->nested.current_vmcs12 = NULL; | |
e7953d7f AG |
6439 | } |
6440 | ||
ec378aee NHE |
6441 | /* |
6442 | * Free whatever needs to be freed from vmx->nested when L1 goes down, or | |
6443 | * just stops using VMX. | |
6444 | */ | |
6445 | static void free_nested(struct vcpu_vmx *vmx) | |
6446 | { | |
6447 | if (!vmx->nested.vmxon) | |
6448 | return; | |
9a2a05b9 | 6449 | |
ec378aee | 6450 | vmx->nested.vmxon = false; |
9a2a05b9 | 6451 | nested_release_vmcs12(vmx); |
e7953d7f AG |
6452 | if (enable_shadow_vmcs) |
6453 | free_vmcs(vmx->nested.current_shadow_vmcs); | |
fe3ef05c NHE |
6454 | /* Unpin physical memory we referred to in current vmcs02 */ |
6455 | if (vmx->nested.apic_access_page) { | |
6456 | nested_release_page(vmx->nested.apic_access_page); | |
48d89b92 | 6457 | vmx->nested.apic_access_page = NULL; |
fe3ef05c | 6458 | } |
a7c0b07d WL |
6459 | if (vmx->nested.virtual_apic_page) { |
6460 | nested_release_page(vmx->nested.virtual_apic_page); | |
48d89b92 | 6461 | vmx->nested.virtual_apic_page = NULL; |
a7c0b07d | 6462 | } |
ff2f6fe9 NHE |
6463 | |
6464 | nested_free_all_saved_vmcss(vmx); | |
ec378aee NHE |
6465 | } |
6466 | ||
6467 | /* Emulate the VMXOFF instruction */ | |
6468 | static int handle_vmoff(struct kvm_vcpu *vcpu) | |
6469 | { | |
6470 | if (!nested_vmx_check_permission(vcpu)) | |
6471 | return 1; | |
6472 | free_nested(to_vmx(vcpu)); | |
6473 | skip_emulated_instruction(vcpu); | |
a25eb114 | 6474 | nested_vmx_succeed(vcpu); |
ec378aee NHE |
6475 | return 1; |
6476 | } | |
6477 | ||
27d6c865 NHE |
6478 | /* Emulate the VMCLEAR instruction */ |
6479 | static int handle_vmclear(struct kvm_vcpu *vcpu) | |
6480 | { | |
6481 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
27d6c865 NHE |
6482 | gpa_t vmptr; |
6483 | struct vmcs12 *vmcs12; | |
6484 | struct page *page; | |
27d6c865 NHE |
6485 | |
6486 | if (!nested_vmx_check_permission(vcpu)) | |
6487 | return 1; | |
6488 | ||
4291b588 | 6489 | if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr)) |
27d6c865 | 6490 | return 1; |
27d6c865 | 6491 | |
9a2a05b9 | 6492 | if (vmptr == vmx->nested.current_vmptr) |
e7953d7f | 6493 | nested_release_vmcs12(vmx); |
27d6c865 NHE |
6494 | |
6495 | page = nested_get_page(vcpu, vmptr); | |
6496 | if (page == NULL) { | |
6497 | /* | |
6498 | * For accurate processor emulation, VMCLEAR beyond available | |
6499 | * physical memory should do nothing at all. However, it is | |
6500 | * possible that a nested vmx bug, not a guest hypervisor bug, | |
6501 | * resulted in this case, so let's shut down before doing any | |
6502 | * more damage: | |
6503 | */ | |
6504 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); | |
6505 | return 1; | |
6506 | } | |
6507 | vmcs12 = kmap(page); | |
6508 | vmcs12->launch_state = 0; | |
6509 | kunmap(page); | |
6510 | nested_release_page(page); | |
6511 | ||
6512 | nested_free_vmcs02(vmx, vmptr); | |
6513 | ||
6514 | skip_emulated_instruction(vcpu); | |
6515 | nested_vmx_succeed(vcpu); | |
6516 | return 1; | |
6517 | } | |
6518 | ||
cd232ad0 NHE |
6519 | static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch); |
6520 | ||
6521 | /* Emulate the VMLAUNCH instruction */ | |
6522 | static int handle_vmlaunch(struct kvm_vcpu *vcpu) | |
6523 | { | |
6524 | return nested_vmx_run(vcpu, true); | |
6525 | } | |
6526 | ||
6527 | /* Emulate the VMRESUME instruction */ | |
6528 | static int handle_vmresume(struct kvm_vcpu *vcpu) | |
6529 | { | |
6530 | ||
6531 | return nested_vmx_run(vcpu, false); | |
6532 | } | |
6533 | ||
49f705c5 NHE |
6534 | enum vmcs_field_type { |
6535 | VMCS_FIELD_TYPE_U16 = 0, | |
6536 | VMCS_FIELD_TYPE_U64 = 1, | |
6537 | VMCS_FIELD_TYPE_U32 = 2, | |
6538 | VMCS_FIELD_TYPE_NATURAL_WIDTH = 3 | |
6539 | }; | |
6540 | ||
6541 | static inline int vmcs_field_type(unsigned long field) | |
6542 | { | |
6543 | if (0x1 & field) /* the *_HIGH fields are all 32 bit */ | |
6544 | return VMCS_FIELD_TYPE_U32; | |
6545 | return (field >> 13) & 0x3 ; | |
6546 | } | |
6547 | ||
6548 | static inline int vmcs_field_readonly(unsigned long field) | |
6549 | { | |
6550 | return (((field >> 10) & 0x3) == 1); | |
6551 | } | |
6552 | ||
6553 | /* | |
6554 | * Read a vmcs12 field. Since these can have varying lengths and we return | |
6555 | * one type, we chose the biggest type (u64) and zero-extend the return value | |
6556 | * to that size. Note that the caller, handle_vmread, might need to use only | |
6557 | * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of | |
6558 | * 64-bit fields are to be returned). | |
6559 | */ | |
a2ae9df7 PB |
6560 | static inline int vmcs12_read_any(struct kvm_vcpu *vcpu, |
6561 | unsigned long field, u64 *ret) | |
49f705c5 NHE |
6562 | { |
6563 | short offset = vmcs_field_to_offset(field); | |
6564 | char *p; | |
6565 | ||
6566 | if (offset < 0) | |
a2ae9df7 | 6567 | return offset; |
49f705c5 NHE |
6568 | |
6569 | p = ((char *)(get_vmcs12(vcpu))) + offset; | |
6570 | ||
6571 | switch (vmcs_field_type(field)) { | |
6572 | case VMCS_FIELD_TYPE_NATURAL_WIDTH: | |
6573 | *ret = *((natural_width *)p); | |
a2ae9df7 | 6574 | return 0; |
49f705c5 NHE |
6575 | case VMCS_FIELD_TYPE_U16: |
6576 | *ret = *((u16 *)p); | |
a2ae9df7 | 6577 | return 0; |
49f705c5 NHE |
6578 | case VMCS_FIELD_TYPE_U32: |
6579 | *ret = *((u32 *)p); | |
a2ae9df7 | 6580 | return 0; |
49f705c5 NHE |
6581 | case VMCS_FIELD_TYPE_U64: |
6582 | *ret = *((u64 *)p); | |
a2ae9df7 | 6583 | return 0; |
49f705c5 | 6584 | default: |
a2ae9df7 PB |
6585 | WARN_ON(1); |
6586 | return -ENOENT; | |
49f705c5 NHE |
6587 | } |
6588 | } | |
6589 | ||
20b97fea | 6590 | |
a2ae9df7 PB |
6591 | static inline int vmcs12_write_any(struct kvm_vcpu *vcpu, |
6592 | unsigned long field, u64 field_value){ | |
20b97fea AG |
6593 | short offset = vmcs_field_to_offset(field); |
6594 | char *p = ((char *) get_vmcs12(vcpu)) + offset; | |
6595 | if (offset < 0) | |
a2ae9df7 | 6596 | return offset; |
20b97fea AG |
6597 | |
6598 | switch (vmcs_field_type(field)) { | |
6599 | case VMCS_FIELD_TYPE_U16: | |
6600 | *(u16 *)p = field_value; | |
a2ae9df7 | 6601 | return 0; |
20b97fea AG |
6602 | case VMCS_FIELD_TYPE_U32: |
6603 | *(u32 *)p = field_value; | |
a2ae9df7 | 6604 | return 0; |
20b97fea AG |
6605 | case VMCS_FIELD_TYPE_U64: |
6606 | *(u64 *)p = field_value; | |
a2ae9df7 | 6607 | return 0; |
20b97fea AG |
6608 | case VMCS_FIELD_TYPE_NATURAL_WIDTH: |
6609 | *(natural_width *)p = field_value; | |
a2ae9df7 | 6610 | return 0; |
20b97fea | 6611 | default: |
a2ae9df7 PB |
6612 | WARN_ON(1); |
6613 | return -ENOENT; | |
20b97fea AG |
6614 | } |
6615 | ||
6616 | } | |
6617 | ||
16f5b903 AG |
6618 | static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx) |
6619 | { | |
6620 | int i; | |
6621 | unsigned long field; | |
6622 | u64 field_value; | |
6623 | struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs; | |
c2bae893 MK |
6624 | const unsigned long *fields = shadow_read_write_fields; |
6625 | const int num_fields = max_shadow_read_write_fields; | |
16f5b903 | 6626 | |
282da870 JK |
6627 | preempt_disable(); |
6628 | ||
16f5b903 AG |
6629 | vmcs_load(shadow_vmcs); |
6630 | ||
6631 | for (i = 0; i < num_fields; i++) { | |
6632 | field = fields[i]; | |
6633 | switch (vmcs_field_type(field)) { | |
6634 | case VMCS_FIELD_TYPE_U16: | |
6635 | field_value = vmcs_read16(field); | |
6636 | break; | |
6637 | case VMCS_FIELD_TYPE_U32: | |
6638 | field_value = vmcs_read32(field); | |
6639 | break; | |
6640 | case VMCS_FIELD_TYPE_U64: | |
6641 | field_value = vmcs_read64(field); | |
6642 | break; | |
6643 | case VMCS_FIELD_TYPE_NATURAL_WIDTH: | |
6644 | field_value = vmcs_readl(field); | |
6645 | break; | |
a2ae9df7 PB |
6646 | default: |
6647 | WARN_ON(1); | |
6648 | continue; | |
16f5b903 AG |
6649 | } |
6650 | vmcs12_write_any(&vmx->vcpu, field, field_value); | |
6651 | } | |
6652 | ||
6653 | vmcs_clear(shadow_vmcs); | |
6654 | vmcs_load(vmx->loaded_vmcs->vmcs); | |
282da870 JK |
6655 | |
6656 | preempt_enable(); | |
16f5b903 AG |
6657 | } |
6658 | ||
c3114420 AG |
6659 | static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx) |
6660 | { | |
c2bae893 MK |
6661 | const unsigned long *fields[] = { |
6662 | shadow_read_write_fields, | |
6663 | shadow_read_only_fields | |
c3114420 | 6664 | }; |
c2bae893 | 6665 | const int max_fields[] = { |
c3114420 AG |
6666 | max_shadow_read_write_fields, |
6667 | max_shadow_read_only_fields | |
6668 | }; | |
6669 | int i, q; | |
6670 | unsigned long field; | |
6671 | u64 field_value = 0; | |
6672 | struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs; | |
6673 | ||
6674 | vmcs_load(shadow_vmcs); | |
6675 | ||
c2bae893 | 6676 | for (q = 0; q < ARRAY_SIZE(fields); q++) { |
c3114420 AG |
6677 | for (i = 0; i < max_fields[q]; i++) { |
6678 | field = fields[q][i]; | |
6679 | vmcs12_read_any(&vmx->vcpu, field, &field_value); | |
6680 | ||
6681 | switch (vmcs_field_type(field)) { | |
6682 | case VMCS_FIELD_TYPE_U16: | |
6683 | vmcs_write16(field, (u16)field_value); | |
6684 | break; | |
6685 | case VMCS_FIELD_TYPE_U32: | |
6686 | vmcs_write32(field, (u32)field_value); | |
6687 | break; | |
6688 | case VMCS_FIELD_TYPE_U64: | |
6689 | vmcs_write64(field, (u64)field_value); | |
6690 | break; | |
6691 | case VMCS_FIELD_TYPE_NATURAL_WIDTH: | |
6692 | vmcs_writel(field, (long)field_value); | |
6693 | break; | |
a2ae9df7 PB |
6694 | default: |
6695 | WARN_ON(1); | |
6696 | break; | |
c3114420 AG |
6697 | } |
6698 | } | |
6699 | } | |
6700 | ||
6701 | vmcs_clear(shadow_vmcs); | |
6702 | vmcs_load(vmx->loaded_vmcs->vmcs); | |
6703 | } | |
6704 | ||
49f705c5 NHE |
6705 | /* |
6706 | * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was | |
6707 | * used before) all generate the same failure when it is missing. | |
6708 | */ | |
6709 | static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu) | |
6710 | { | |
6711 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
6712 | if (vmx->nested.current_vmptr == -1ull) { | |
6713 | nested_vmx_failInvalid(vcpu); | |
6714 | skip_emulated_instruction(vcpu); | |
6715 | return 0; | |
6716 | } | |
6717 | return 1; | |
6718 | } | |
6719 | ||
6720 | static int handle_vmread(struct kvm_vcpu *vcpu) | |
6721 | { | |
6722 | unsigned long field; | |
6723 | u64 field_value; | |
6724 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
6725 | u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); | |
6726 | gva_t gva = 0; | |
6727 | ||
6728 | if (!nested_vmx_check_permission(vcpu) || | |
6729 | !nested_vmx_check_vmcs12(vcpu)) | |
6730 | return 1; | |
6731 | ||
6732 | /* Decode instruction info and find the field to read */ | |
27e6fb5d | 6733 | field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf)); |
49f705c5 | 6734 | /* Read the field, zero-extended to a u64 field_value */ |
a2ae9df7 | 6735 | if (vmcs12_read_any(vcpu, field, &field_value) < 0) { |
49f705c5 NHE |
6736 | nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT); |
6737 | skip_emulated_instruction(vcpu); | |
6738 | return 1; | |
6739 | } | |
6740 | /* | |
6741 | * Now copy part of this value to register or memory, as requested. | |
6742 | * Note that the number of bits actually copied is 32 or 64 depending | |
6743 | * on the guest's mode (32 or 64 bit), not on the given field's length. | |
6744 | */ | |
6745 | if (vmx_instruction_info & (1u << 10)) { | |
27e6fb5d | 6746 | kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf), |
49f705c5 NHE |
6747 | field_value); |
6748 | } else { | |
6749 | if (get_vmx_mem_address(vcpu, exit_qualification, | |
6750 | vmx_instruction_info, &gva)) | |
6751 | return 1; | |
6752 | /* _system ok, as nested_vmx_check_permission verified cpl=0 */ | |
6753 | kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva, | |
6754 | &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL); | |
6755 | } | |
6756 | ||
6757 | nested_vmx_succeed(vcpu); | |
6758 | skip_emulated_instruction(vcpu); | |
6759 | return 1; | |
6760 | } | |
6761 | ||
6762 | ||
6763 | static int handle_vmwrite(struct kvm_vcpu *vcpu) | |
6764 | { | |
6765 | unsigned long field; | |
6766 | gva_t gva; | |
6767 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
6768 | u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); | |
49f705c5 NHE |
6769 | /* The value to write might be 32 or 64 bits, depending on L1's long |
6770 | * mode, and eventually we need to write that into a field of several | |
6771 | * possible lengths. The code below first zero-extends the value to 64 | |
6772 | * bit (field_value), and then copies only the approriate number of | |
6773 | * bits into the vmcs12 field. | |
6774 | */ | |
6775 | u64 field_value = 0; | |
6776 | struct x86_exception e; | |
6777 | ||
6778 | if (!nested_vmx_check_permission(vcpu) || | |
6779 | !nested_vmx_check_vmcs12(vcpu)) | |
6780 | return 1; | |
6781 | ||
6782 | if (vmx_instruction_info & (1u << 10)) | |
27e6fb5d | 6783 | field_value = kvm_register_readl(vcpu, |
49f705c5 NHE |
6784 | (((vmx_instruction_info) >> 3) & 0xf)); |
6785 | else { | |
6786 | if (get_vmx_mem_address(vcpu, exit_qualification, | |
6787 | vmx_instruction_info, &gva)) | |
6788 | return 1; | |
6789 | if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, | |
27e6fb5d | 6790 | &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) { |
49f705c5 NHE |
6791 | kvm_inject_page_fault(vcpu, &e); |
6792 | return 1; | |
6793 | } | |
6794 | } | |
6795 | ||
6796 | ||
27e6fb5d | 6797 | field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf)); |
49f705c5 NHE |
6798 | if (vmcs_field_readonly(field)) { |
6799 | nested_vmx_failValid(vcpu, | |
6800 | VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT); | |
6801 | skip_emulated_instruction(vcpu); | |
6802 | return 1; | |
6803 | } | |
6804 | ||
a2ae9df7 | 6805 | if (vmcs12_write_any(vcpu, field, field_value) < 0) { |
49f705c5 NHE |
6806 | nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT); |
6807 | skip_emulated_instruction(vcpu); | |
6808 | return 1; | |
6809 | } | |
6810 | ||
6811 | nested_vmx_succeed(vcpu); | |
6812 | skip_emulated_instruction(vcpu); | |
6813 | return 1; | |
6814 | } | |
6815 | ||
63846663 NHE |
6816 | /* Emulate the VMPTRLD instruction */ |
6817 | static int handle_vmptrld(struct kvm_vcpu *vcpu) | |
6818 | { | |
6819 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
63846663 | 6820 | gpa_t vmptr; |
8a1b9dd0 | 6821 | u32 exec_control; |
63846663 NHE |
6822 | |
6823 | if (!nested_vmx_check_permission(vcpu)) | |
6824 | return 1; | |
6825 | ||
4291b588 | 6826 | if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr)) |
63846663 | 6827 | return 1; |
63846663 NHE |
6828 | |
6829 | if (vmx->nested.current_vmptr != vmptr) { | |
6830 | struct vmcs12 *new_vmcs12; | |
6831 | struct page *page; | |
6832 | page = nested_get_page(vcpu, vmptr); | |
6833 | if (page == NULL) { | |
6834 | nested_vmx_failInvalid(vcpu); | |
6835 | skip_emulated_instruction(vcpu); | |
6836 | return 1; | |
6837 | } | |
6838 | new_vmcs12 = kmap(page); | |
6839 | if (new_vmcs12->revision_id != VMCS12_REVISION) { | |
6840 | kunmap(page); | |
6841 | nested_release_page_clean(page); | |
6842 | nested_vmx_failValid(vcpu, | |
6843 | VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID); | |
6844 | skip_emulated_instruction(vcpu); | |
6845 | return 1; | |
6846 | } | |
63846663 | 6847 | |
9a2a05b9 | 6848 | nested_release_vmcs12(vmx); |
63846663 NHE |
6849 | vmx->nested.current_vmptr = vmptr; |
6850 | vmx->nested.current_vmcs12 = new_vmcs12; | |
6851 | vmx->nested.current_vmcs12_page = page; | |
012f83cb | 6852 | if (enable_shadow_vmcs) { |
8a1b9dd0 AG |
6853 | exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL); |
6854 | exec_control |= SECONDARY_EXEC_SHADOW_VMCS; | |
6855 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control); | |
6856 | vmcs_write64(VMCS_LINK_POINTER, | |
6857 | __pa(vmx->nested.current_shadow_vmcs)); | |
012f83cb AG |
6858 | vmx->nested.sync_shadow_vmcs = true; |
6859 | } | |
63846663 NHE |
6860 | } |
6861 | ||
6862 | nested_vmx_succeed(vcpu); | |
6863 | skip_emulated_instruction(vcpu); | |
6864 | return 1; | |
6865 | } | |
6866 | ||
6a4d7550 NHE |
6867 | /* Emulate the VMPTRST instruction */ |
6868 | static int handle_vmptrst(struct kvm_vcpu *vcpu) | |
6869 | { | |
6870 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
6871 | u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); | |
6872 | gva_t vmcs_gva; | |
6873 | struct x86_exception e; | |
6874 | ||
6875 | if (!nested_vmx_check_permission(vcpu)) | |
6876 | return 1; | |
6877 | ||
6878 | if (get_vmx_mem_address(vcpu, exit_qualification, | |
6879 | vmx_instruction_info, &vmcs_gva)) | |
6880 | return 1; | |
6881 | /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */ | |
6882 | if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva, | |
6883 | (void *)&to_vmx(vcpu)->nested.current_vmptr, | |
6884 | sizeof(u64), &e)) { | |
6885 | kvm_inject_page_fault(vcpu, &e); | |
6886 | return 1; | |
6887 | } | |
6888 | nested_vmx_succeed(vcpu); | |
6889 | skip_emulated_instruction(vcpu); | |
6890 | return 1; | |
6891 | } | |
6892 | ||
bfd0a56b NHE |
6893 | /* Emulate the INVEPT instruction */ |
6894 | static int handle_invept(struct kvm_vcpu *vcpu) | |
6895 | { | |
6896 | u32 vmx_instruction_info, types; | |
6897 | unsigned long type; | |
6898 | gva_t gva; | |
6899 | struct x86_exception e; | |
6900 | struct { | |
6901 | u64 eptp, gpa; | |
6902 | } operand; | |
bfd0a56b NHE |
6903 | |
6904 | if (!(nested_vmx_secondary_ctls_high & SECONDARY_EXEC_ENABLE_EPT) || | |
6905 | !(nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) { | |
6906 | kvm_queue_exception(vcpu, UD_VECTOR); | |
6907 | return 1; | |
6908 | } | |
6909 | ||
6910 | if (!nested_vmx_check_permission(vcpu)) | |
6911 | return 1; | |
6912 | ||
6913 | if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) { | |
6914 | kvm_queue_exception(vcpu, UD_VECTOR); | |
6915 | return 1; | |
6916 | } | |
6917 | ||
6918 | vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); | |
27e6fb5d | 6919 | type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf); |
bfd0a56b NHE |
6920 | |
6921 | types = (nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6; | |
6922 | ||
6923 | if (!(types & (1UL << type))) { | |
6924 | nested_vmx_failValid(vcpu, | |
6925 | VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID); | |
6926 | return 1; | |
6927 | } | |
6928 | ||
6929 | /* According to the Intel VMX instruction reference, the memory | |
6930 | * operand is read even if it isn't needed (e.g., for type==global) | |
6931 | */ | |
6932 | if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION), | |
6933 | vmx_instruction_info, &gva)) | |
6934 | return 1; | |
6935 | if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand, | |
6936 | sizeof(operand), &e)) { | |
6937 | kvm_inject_page_fault(vcpu, &e); | |
6938 | return 1; | |
6939 | } | |
6940 | ||
6941 | switch (type) { | |
bfd0a56b NHE |
6942 | case VMX_EPT_EXTENT_GLOBAL: |
6943 | kvm_mmu_sync_roots(vcpu); | |
77c3913b | 6944 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
bfd0a56b NHE |
6945 | nested_vmx_succeed(vcpu); |
6946 | break; | |
6947 | default: | |
4b855078 | 6948 | /* Trap single context invalidation invept calls */ |
bfd0a56b NHE |
6949 | BUG_ON(1); |
6950 | break; | |
6951 | } | |
6952 | ||
6953 | skip_emulated_instruction(vcpu); | |
6954 | return 1; | |
6955 | } | |
6956 | ||
a642fc30 PM |
6957 | static int handle_invvpid(struct kvm_vcpu *vcpu) |
6958 | { | |
6959 | kvm_queue_exception(vcpu, UD_VECTOR); | |
6960 | return 1; | |
6961 | } | |
6962 | ||
6aa8b732 AK |
6963 | /* |
6964 | * The exit handlers return 1 if the exit was handled fully and guest execution | |
6965 | * may resume. Otherwise they set the kvm_run parameter to indicate what needs | |
6966 | * to be done to userspace and return 0. | |
6967 | */ | |
772e0318 | 6968 | static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = { |
6aa8b732 AK |
6969 | [EXIT_REASON_EXCEPTION_NMI] = handle_exception, |
6970 | [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt, | |
988ad74f | 6971 | [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault, |
f08864b4 | 6972 | [EXIT_REASON_NMI_WINDOW] = handle_nmi_window, |
6aa8b732 | 6973 | [EXIT_REASON_IO_INSTRUCTION] = handle_io, |
6aa8b732 AK |
6974 | [EXIT_REASON_CR_ACCESS] = handle_cr, |
6975 | [EXIT_REASON_DR_ACCESS] = handle_dr, | |
6976 | [EXIT_REASON_CPUID] = handle_cpuid, | |
6977 | [EXIT_REASON_MSR_READ] = handle_rdmsr, | |
6978 | [EXIT_REASON_MSR_WRITE] = handle_wrmsr, | |
6979 | [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window, | |
6980 | [EXIT_REASON_HLT] = handle_halt, | |
ec25d5e6 | 6981 | [EXIT_REASON_INVD] = handle_invd, |
a7052897 | 6982 | [EXIT_REASON_INVLPG] = handle_invlpg, |
fee84b07 | 6983 | [EXIT_REASON_RDPMC] = handle_rdpmc, |
c21415e8 | 6984 | [EXIT_REASON_VMCALL] = handle_vmcall, |
27d6c865 | 6985 | [EXIT_REASON_VMCLEAR] = handle_vmclear, |
cd232ad0 | 6986 | [EXIT_REASON_VMLAUNCH] = handle_vmlaunch, |
63846663 | 6987 | [EXIT_REASON_VMPTRLD] = handle_vmptrld, |
6a4d7550 | 6988 | [EXIT_REASON_VMPTRST] = handle_vmptrst, |
49f705c5 | 6989 | [EXIT_REASON_VMREAD] = handle_vmread, |
cd232ad0 | 6990 | [EXIT_REASON_VMRESUME] = handle_vmresume, |
49f705c5 | 6991 | [EXIT_REASON_VMWRITE] = handle_vmwrite, |
ec378aee NHE |
6992 | [EXIT_REASON_VMOFF] = handle_vmoff, |
6993 | [EXIT_REASON_VMON] = handle_vmon, | |
f78e0e2e SY |
6994 | [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold, |
6995 | [EXIT_REASON_APIC_ACCESS] = handle_apic_access, | |
83d4c286 | 6996 | [EXIT_REASON_APIC_WRITE] = handle_apic_write, |
c7c9c56c | 6997 | [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced, |
e5edaa01 | 6998 | [EXIT_REASON_WBINVD] = handle_wbinvd, |
2acf923e | 6999 | [EXIT_REASON_XSETBV] = handle_xsetbv, |
37817f29 | 7000 | [EXIT_REASON_TASK_SWITCH] = handle_task_switch, |
a0861c02 | 7001 | [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check, |
68f89400 MT |
7002 | [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation, |
7003 | [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig, | |
4b8d54f9 | 7004 | [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause, |
87c00572 GS |
7005 | [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait, |
7006 | [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor, | |
bfd0a56b | 7007 | [EXIT_REASON_INVEPT] = handle_invept, |
a642fc30 | 7008 | [EXIT_REASON_INVVPID] = handle_invvpid, |
f53cd63c WL |
7009 | [EXIT_REASON_XSAVES] = handle_xsaves, |
7010 | [EXIT_REASON_XRSTORS] = handle_xrstors, | |
6aa8b732 AK |
7011 | }; |
7012 | ||
7013 | static const int kvm_vmx_max_exit_handlers = | |
50a3485c | 7014 | ARRAY_SIZE(kvm_vmx_exit_handlers); |
6aa8b732 | 7015 | |
908a7bdd JK |
7016 | static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu, |
7017 | struct vmcs12 *vmcs12) | |
7018 | { | |
7019 | unsigned long exit_qualification; | |
7020 | gpa_t bitmap, last_bitmap; | |
7021 | unsigned int port; | |
7022 | int size; | |
7023 | u8 b; | |
7024 | ||
908a7bdd | 7025 | if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS)) |
2f0a6397 | 7026 | return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING); |
908a7bdd JK |
7027 | |
7028 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
7029 | ||
7030 | port = exit_qualification >> 16; | |
7031 | size = (exit_qualification & 7) + 1; | |
7032 | ||
7033 | last_bitmap = (gpa_t)-1; | |
7034 | b = -1; | |
7035 | ||
7036 | while (size > 0) { | |
7037 | if (port < 0x8000) | |
7038 | bitmap = vmcs12->io_bitmap_a; | |
7039 | else if (port < 0x10000) | |
7040 | bitmap = vmcs12->io_bitmap_b; | |
7041 | else | |
7042 | return 1; | |
7043 | bitmap += (port & 0x7fff) / 8; | |
7044 | ||
7045 | if (last_bitmap != bitmap) | |
7046 | if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1)) | |
7047 | return 1; | |
7048 | if (b & (1 << (port & 7))) | |
7049 | return 1; | |
7050 | ||
7051 | port++; | |
7052 | size--; | |
7053 | last_bitmap = bitmap; | |
7054 | } | |
7055 | ||
7056 | return 0; | |
7057 | } | |
7058 | ||
644d711a NHE |
7059 | /* |
7060 | * Return 1 if we should exit from L2 to L1 to handle an MSR access access, | |
7061 | * rather than handle it ourselves in L0. I.e., check whether L1 expressed | |
7062 | * disinterest in the current event (read or write a specific MSR) by using an | |
7063 | * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps. | |
7064 | */ | |
7065 | static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu, | |
7066 | struct vmcs12 *vmcs12, u32 exit_reason) | |
7067 | { | |
7068 | u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX]; | |
7069 | gpa_t bitmap; | |
7070 | ||
cbd29cb6 | 7071 | if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS)) |
644d711a NHE |
7072 | return 1; |
7073 | ||
7074 | /* | |
7075 | * The MSR_BITMAP page is divided into four 1024-byte bitmaps, | |
7076 | * for the four combinations of read/write and low/high MSR numbers. | |
7077 | * First we need to figure out which of the four to use: | |
7078 | */ | |
7079 | bitmap = vmcs12->msr_bitmap; | |
7080 | if (exit_reason == EXIT_REASON_MSR_WRITE) | |
7081 | bitmap += 2048; | |
7082 | if (msr_index >= 0xc0000000) { | |
7083 | msr_index -= 0xc0000000; | |
7084 | bitmap += 1024; | |
7085 | } | |
7086 | ||
7087 | /* Then read the msr_index'th bit from this bitmap: */ | |
7088 | if (msr_index < 1024*8) { | |
7089 | unsigned char b; | |
bd31a7f5 JK |
7090 | if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1)) |
7091 | return 1; | |
644d711a NHE |
7092 | return 1 & (b >> (msr_index & 7)); |
7093 | } else | |
7094 | return 1; /* let L1 handle the wrong parameter */ | |
7095 | } | |
7096 | ||
7097 | /* | |
7098 | * Return 1 if we should exit from L2 to L1 to handle a CR access exit, | |
7099 | * rather than handle it ourselves in L0. I.e., check if L1 wanted to | |
7100 | * intercept (via guest_host_mask etc.) the current event. | |
7101 | */ | |
7102 | static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu, | |
7103 | struct vmcs12 *vmcs12) | |
7104 | { | |
7105 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
7106 | int cr = exit_qualification & 15; | |
7107 | int reg = (exit_qualification >> 8) & 15; | |
1e32c079 | 7108 | unsigned long val = kvm_register_readl(vcpu, reg); |
644d711a NHE |
7109 | |
7110 | switch ((exit_qualification >> 4) & 3) { | |
7111 | case 0: /* mov to cr */ | |
7112 | switch (cr) { | |
7113 | case 0: | |
7114 | if (vmcs12->cr0_guest_host_mask & | |
7115 | (val ^ vmcs12->cr0_read_shadow)) | |
7116 | return 1; | |
7117 | break; | |
7118 | case 3: | |
7119 | if ((vmcs12->cr3_target_count >= 1 && | |
7120 | vmcs12->cr3_target_value0 == val) || | |
7121 | (vmcs12->cr3_target_count >= 2 && | |
7122 | vmcs12->cr3_target_value1 == val) || | |
7123 | (vmcs12->cr3_target_count >= 3 && | |
7124 | vmcs12->cr3_target_value2 == val) || | |
7125 | (vmcs12->cr3_target_count >= 4 && | |
7126 | vmcs12->cr3_target_value3 == val)) | |
7127 | return 0; | |
7128 | if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING)) | |
7129 | return 1; | |
7130 | break; | |
7131 | case 4: | |
7132 | if (vmcs12->cr4_guest_host_mask & | |
7133 | (vmcs12->cr4_read_shadow ^ val)) | |
7134 | return 1; | |
7135 | break; | |
7136 | case 8: | |
7137 | if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING)) | |
7138 | return 1; | |
7139 | break; | |
7140 | } | |
7141 | break; | |
7142 | case 2: /* clts */ | |
7143 | if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) && | |
7144 | (vmcs12->cr0_read_shadow & X86_CR0_TS)) | |
7145 | return 1; | |
7146 | break; | |
7147 | case 1: /* mov from cr */ | |
7148 | switch (cr) { | |
7149 | case 3: | |
7150 | if (vmcs12->cpu_based_vm_exec_control & | |
7151 | CPU_BASED_CR3_STORE_EXITING) | |
7152 | return 1; | |
7153 | break; | |
7154 | case 8: | |
7155 | if (vmcs12->cpu_based_vm_exec_control & | |
7156 | CPU_BASED_CR8_STORE_EXITING) | |
7157 | return 1; | |
7158 | break; | |
7159 | } | |
7160 | break; | |
7161 | case 3: /* lmsw */ | |
7162 | /* | |
7163 | * lmsw can change bits 1..3 of cr0, and only set bit 0 of | |
7164 | * cr0. Other attempted changes are ignored, with no exit. | |
7165 | */ | |
7166 | if (vmcs12->cr0_guest_host_mask & 0xe & | |
7167 | (val ^ vmcs12->cr0_read_shadow)) | |
7168 | return 1; | |
7169 | if ((vmcs12->cr0_guest_host_mask & 0x1) && | |
7170 | !(vmcs12->cr0_read_shadow & 0x1) && | |
7171 | (val & 0x1)) | |
7172 | return 1; | |
7173 | break; | |
7174 | } | |
7175 | return 0; | |
7176 | } | |
7177 | ||
7178 | /* | |
7179 | * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we | |
7180 | * should handle it ourselves in L0 (and then continue L2). Only call this | |
7181 | * when in is_guest_mode (L2). | |
7182 | */ | |
7183 | static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu) | |
7184 | { | |
644d711a NHE |
7185 | u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO); |
7186 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
7187 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
957c897e | 7188 | u32 exit_reason = vmx->exit_reason; |
644d711a | 7189 | |
542060ea JK |
7190 | trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason, |
7191 | vmcs_readl(EXIT_QUALIFICATION), | |
7192 | vmx->idt_vectoring_info, | |
7193 | intr_info, | |
7194 | vmcs_read32(VM_EXIT_INTR_ERROR_CODE), | |
7195 | KVM_ISA_VMX); | |
7196 | ||
644d711a NHE |
7197 | if (vmx->nested.nested_run_pending) |
7198 | return 0; | |
7199 | ||
7200 | if (unlikely(vmx->fail)) { | |
bd80158a JK |
7201 | pr_info_ratelimited("%s failed vm entry %x\n", __func__, |
7202 | vmcs_read32(VM_INSTRUCTION_ERROR)); | |
644d711a NHE |
7203 | return 1; |
7204 | } | |
7205 | ||
7206 | switch (exit_reason) { | |
7207 | case EXIT_REASON_EXCEPTION_NMI: | |
7208 | if (!is_exception(intr_info)) | |
7209 | return 0; | |
7210 | else if (is_page_fault(intr_info)) | |
7211 | return enable_ept; | |
e504c909 | 7212 | else if (is_no_device(intr_info) && |
ccf9844e | 7213 | !(vmcs12->guest_cr0 & X86_CR0_TS)) |
e504c909 | 7214 | return 0; |
644d711a NHE |
7215 | return vmcs12->exception_bitmap & |
7216 | (1u << (intr_info & INTR_INFO_VECTOR_MASK)); | |
7217 | case EXIT_REASON_EXTERNAL_INTERRUPT: | |
7218 | return 0; | |
7219 | case EXIT_REASON_TRIPLE_FAULT: | |
7220 | return 1; | |
7221 | case EXIT_REASON_PENDING_INTERRUPT: | |
3b656cf7 | 7222 | return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING); |
644d711a | 7223 | case EXIT_REASON_NMI_WINDOW: |
3b656cf7 | 7224 | return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING); |
644d711a NHE |
7225 | case EXIT_REASON_TASK_SWITCH: |
7226 | return 1; | |
7227 | case EXIT_REASON_CPUID: | |
bc613494 MT |
7228 | if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa) |
7229 | return 0; | |
644d711a NHE |
7230 | return 1; |
7231 | case EXIT_REASON_HLT: | |
7232 | return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING); | |
7233 | case EXIT_REASON_INVD: | |
7234 | return 1; | |
7235 | case EXIT_REASON_INVLPG: | |
7236 | return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING); | |
7237 | case EXIT_REASON_RDPMC: | |
7238 | return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING); | |
7239 | case EXIT_REASON_RDTSC: | |
7240 | return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING); | |
7241 | case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR: | |
7242 | case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD: | |
7243 | case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD: | |
7244 | case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE: | |
7245 | case EXIT_REASON_VMOFF: case EXIT_REASON_VMON: | |
a642fc30 | 7246 | case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID: |
644d711a NHE |
7247 | /* |
7248 | * VMX instructions trap unconditionally. This allows L1 to | |
7249 | * emulate them for its L2 guest, i.e., allows 3-level nesting! | |
7250 | */ | |
7251 | return 1; | |
7252 | case EXIT_REASON_CR_ACCESS: | |
7253 | return nested_vmx_exit_handled_cr(vcpu, vmcs12); | |
7254 | case EXIT_REASON_DR_ACCESS: | |
7255 | return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING); | |
7256 | case EXIT_REASON_IO_INSTRUCTION: | |
908a7bdd | 7257 | return nested_vmx_exit_handled_io(vcpu, vmcs12); |
644d711a NHE |
7258 | case EXIT_REASON_MSR_READ: |
7259 | case EXIT_REASON_MSR_WRITE: | |
7260 | return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason); | |
7261 | case EXIT_REASON_INVALID_STATE: | |
7262 | return 1; | |
7263 | case EXIT_REASON_MWAIT_INSTRUCTION: | |
7264 | return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING); | |
7265 | case EXIT_REASON_MONITOR_INSTRUCTION: | |
7266 | return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING); | |
7267 | case EXIT_REASON_PAUSE_INSTRUCTION: | |
7268 | return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) || | |
7269 | nested_cpu_has2(vmcs12, | |
7270 | SECONDARY_EXEC_PAUSE_LOOP_EXITING); | |
7271 | case EXIT_REASON_MCE_DURING_VMENTRY: | |
7272 | return 0; | |
7273 | case EXIT_REASON_TPR_BELOW_THRESHOLD: | |
a7c0b07d | 7274 | return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW); |
644d711a NHE |
7275 | case EXIT_REASON_APIC_ACCESS: |
7276 | return nested_cpu_has2(vmcs12, | |
7277 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES); | |
7278 | case EXIT_REASON_EPT_VIOLATION: | |
2b1be677 NHE |
7279 | /* |
7280 | * L0 always deals with the EPT violation. If nested EPT is | |
7281 | * used, and the nested mmu code discovers that the address is | |
7282 | * missing in the guest EPT table (EPT12), the EPT violation | |
7283 | * will be injected with nested_ept_inject_page_fault() | |
7284 | */ | |
7285 | return 0; | |
644d711a | 7286 | case EXIT_REASON_EPT_MISCONFIG: |
2b1be677 NHE |
7287 | /* |
7288 | * L2 never uses directly L1's EPT, but rather L0's own EPT | |
7289 | * table (shadow on EPT) or a merged EPT table that L0 built | |
7290 | * (EPT on EPT). So any problems with the structure of the | |
7291 | * table is L0's fault. | |
7292 | */ | |
644d711a NHE |
7293 | return 0; |
7294 | case EXIT_REASON_WBINVD: | |
7295 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING); | |
7296 | case EXIT_REASON_XSETBV: | |
7297 | return 1; | |
81dc01f7 WL |
7298 | case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS: |
7299 | /* | |
7300 | * This should never happen, since it is not possible to | |
7301 | * set XSS to a non-zero value---neither in L1 nor in L2. | |
7302 | * If if it were, XSS would have to be checked against | |
7303 | * the XSS exit bitmap in vmcs12. | |
7304 | */ | |
7305 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES); | |
644d711a NHE |
7306 | default: |
7307 | return 1; | |
7308 | } | |
7309 | } | |
7310 | ||
586f9607 AK |
7311 | static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2) |
7312 | { | |
7313 | *info1 = vmcs_readl(EXIT_QUALIFICATION); | |
7314 | *info2 = vmcs_read32(VM_EXIT_INTR_INFO); | |
7315 | } | |
7316 | ||
6aa8b732 AK |
7317 | /* |
7318 | * The guest has exited. See if we can fix it or if we need userspace | |
7319 | * assistance. | |
7320 | */ | |
851ba692 | 7321 | static int vmx_handle_exit(struct kvm_vcpu *vcpu) |
6aa8b732 | 7322 | { |
29bd8a78 | 7323 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
a0861c02 | 7324 | u32 exit_reason = vmx->exit_reason; |
1155f76a | 7325 | u32 vectoring_info = vmx->idt_vectoring_info; |
29bd8a78 | 7326 | |
80ced186 | 7327 | /* If guest state is invalid, start emulating */ |
14168786 | 7328 | if (vmx->emulation_required) |
80ced186 | 7329 | return handle_invalid_guest_state(vcpu); |
1d5a4d9b | 7330 | |
644d711a | 7331 | if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) { |
533558bc JK |
7332 | nested_vmx_vmexit(vcpu, exit_reason, |
7333 | vmcs_read32(VM_EXIT_INTR_INFO), | |
7334 | vmcs_readl(EXIT_QUALIFICATION)); | |
644d711a NHE |
7335 | return 1; |
7336 | } | |
7337 | ||
5120702e MG |
7338 | if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) { |
7339 | vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY; | |
7340 | vcpu->run->fail_entry.hardware_entry_failure_reason | |
7341 | = exit_reason; | |
7342 | return 0; | |
7343 | } | |
7344 | ||
29bd8a78 | 7345 | if (unlikely(vmx->fail)) { |
851ba692 AK |
7346 | vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY; |
7347 | vcpu->run->fail_entry.hardware_entry_failure_reason | |
29bd8a78 AK |
7348 | = vmcs_read32(VM_INSTRUCTION_ERROR); |
7349 | return 0; | |
7350 | } | |
6aa8b732 | 7351 | |
b9bf6882 XG |
7352 | /* |
7353 | * Note: | |
7354 | * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by | |
7355 | * delivery event since it indicates guest is accessing MMIO. | |
7356 | * The vm-exit can be triggered again after return to guest that | |
7357 | * will cause infinite loop. | |
7358 | */ | |
d77c26fc | 7359 | if ((vectoring_info & VECTORING_INFO_VALID_MASK) && |
1439442c | 7360 | (exit_reason != EXIT_REASON_EXCEPTION_NMI && |
60637aac | 7361 | exit_reason != EXIT_REASON_EPT_VIOLATION && |
b9bf6882 XG |
7362 | exit_reason != EXIT_REASON_TASK_SWITCH)) { |
7363 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
7364 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV; | |
7365 | vcpu->run->internal.ndata = 2; | |
7366 | vcpu->run->internal.data[0] = vectoring_info; | |
7367 | vcpu->run->internal.data[1] = exit_reason; | |
7368 | return 0; | |
7369 | } | |
3b86cd99 | 7370 | |
644d711a NHE |
7371 | if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked && |
7372 | !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis( | |
f5c4368f | 7373 | get_vmcs12(vcpu))))) { |
c4282df9 | 7374 | if (vmx_interrupt_allowed(vcpu)) { |
3b86cd99 | 7375 | vmx->soft_vnmi_blocked = 0; |
3b86cd99 | 7376 | } else if (vmx->vnmi_blocked_time > 1000000000LL && |
4531220b | 7377 | vcpu->arch.nmi_pending) { |
3b86cd99 JK |
7378 | /* |
7379 | * This CPU don't support us in finding the end of an | |
7380 | * NMI-blocked window if the guest runs with IRQs | |
7381 | * disabled. So we pull the trigger after 1 s of | |
7382 | * futile waiting, but inform the user about this. | |
7383 | */ | |
7384 | printk(KERN_WARNING "%s: Breaking out of NMI-blocked " | |
7385 | "state on VCPU %d after 1 s timeout\n", | |
7386 | __func__, vcpu->vcpu_id); | |
7387 | vmx->soft_vnmi_blocked = 0; | |
3b86cd99 | 7388 | } |
3b86cd99 JK |
7389 | } |
7390 | ||
6aa8b732 AK |
7391 | if (exit_reason < kvm_vmx_max_exit_handlers |
7392 | && kvm_vmx_exit_handlers[exit_reason]) | |
851ba692 | 7393 | return kvm_vmx_exit_handlers[exit_reason](vcpu); |
6aa8b732 | 7394 | else { |
2bc19dc3 MT |
7395 | WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason); |
7396 | kvm_queue_exception(vcpu, UD_VECTOR); | |
7397 | return 1; | |
6aa8b732 | 7398 | } |
6aa8b732 AK |
7399 | } |
7400 | ||
95ba8273 | 7401 | static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr) |
6e5d865c | 7402 | { |
a7c0b07d WL |
7403 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
7404 | ||
7405 | if (is_guest_mode(vcpu) && | |
7406 | nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) | |
7407 | return; | |
7408 | ||
95ba8273 | 7409 | if (irr == -1 || tpr < irr) { |
6e5d865c YS |
7410 | vmcs_write32(TPR_THRESHOLD, 0); |
7411 | return; | |
7412 | } | |
7413 | ||
95ba8273 | 7414 | vmcs_write32(TPR_THRESHOLD, irr); |
6e5d865c YS |
7415 | } |
7416 | ||
8d14695f YZ |
7417 | static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set) |
7418 | { | |
7419 | u32 sec_exec_control; | |
7420 | ||
7421 | /* | |
7422 | * There is not point to enable virtualize x2apic without enable | |
7423 | * apicv | |
7424 | */ | |
c7c9c56c YZ |
7425 | if (!cpu_has_vmx_virtualize_x2apic_mode() || |
7426 | !vmx_vm_has_apicv(vcpu->kvm)) | |
8d14695f YZ |
7427 | return; |
7428 | ||
7429 | if (!vm_need_tpr_shadow(vcpu->kvm)) | |
7430 | return; | |
7431 | ||
7432 | sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL); | |
7433 | ||
7434 | if (set) { | |
7435 | sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
7436 | sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; | |
7437 | } else { | |
7438 | sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; | |
7439 | sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
7440 | } | |
7441 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control); | |
7442 | ||
7443 | vmx_set_msr_bitmap(vcpu); | |
7444 | } | |
7445 | ||
38b99173 TC |
7446 | static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa) |
7447 | { | |
7448 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
7449 | ||
7450 | /* | |
7451 | * Currently we do not handle the nested case where L2 has an | |
7452 | * APIC access page of its own; that page is still pinned. | |
7453 | * Hence, we skip the case where the VCPU is in guest mode _and_ | |
7454 | * L1 prepared an APIC access page for L2. | |
7455 | * | |
7456 | * For the case where L1 and L2 share the same APIC access page | |
7457 | * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear | |
7458 | * in the vmcs12), this function will only update either the vmcs01 | |
7459 | * or the vmcs02. If the former, the vmcs02 will be updated by | |
7460 | * prepare_vmcs02. If the latter, the vmcs01 will be updated in | |
7461 | * the next L2->L1 exit. | |
7462 | */ | |
7463 | if (!is_guest_mode(vcpu) || | |
7464 | !nested_cpu_has2(vmx->nested.current_vmcs12, | |
7465 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) | |
7466 | vmcs_write64(APIC_ACCESS_ADDR, hpa); | |
7467 | } | |
7468 | ||
c7c9c56c YZ |
7469 | static void vmx_hwapic_isr_update(struct kvm *kvm, int isr) |
7470 | { | |
7471 | u16 status; | |
7472 | u8 old; | |
7473 | ||
7474 | if (!vmx_vm_has_apicv(kvm)) | |
7475 | return; | |
7476 | ||
7477 | if (isr == -1) | |
7478 | isr = 0; | |
7479 | ||
7480 | status = vmcs_read16(GUEST_INTR_STATUS); | |
7481 | old = status >> 8; | |
7482 | if (isr != old) { | |
7483 | status &= 0xff; | |
7484 | status |= isr << 8; | |
7485 | vmcs_write16(GUEST_INTR_STATUS, status); | |
7486 | } | |
7487 | } | |
7488 | ||
7489 | static void vmx_set_rvi(int vector) | |
7490 | { | |
7491 | u16 status; | |
7492 | u8 old; | |
7493 | ||
4114c27d WW |
7494 | if (vector == -1) |
7495 | vector = 0; | |
7496 | ||
c7c9c56c YZ |
7497 | status = vmcs_read16(GUEST_INTR_STATUS); |
7498 | old = (u8)status & 0xff; | |
7499 | if ((u8)vector != old) { | |
7500 | status &= ~0xff; | |
7501 | status |= (u8)vector; | |
7502 | vmcs_write16(GUEST_INTR_STATUS, status); | |
7503 | } | |
7504 | } | |
7505 | ||
7506 | static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr) | |
7507 | { | |
4114c27d WW |
7508 | if (!is_guest_mode(vcpu)) { |
7509 | vmx_set_rvi(max_irr); | |
7510 | return; | |
7511 | } | |
7512 | ||
c7c9c56c YZ |
7513 | if (max_irr == -1) |
7514 | return; | |
7515 | ||
963fee16 | 7516 | /* |
4114c27d WW |
7517 | * In guest mode. If a vmexit is needed, vmx_check_nested_events |
7518 | * handles it. | |
963fee16 | 7519 | */ |
4114c27d | 7520 | if (nested_exit_on_intr(vcpu)) |
963fee16 WL |
7521 | return; |
7522 | ||
963fee16 | 7523 | /* |
4114c27d | 7524 | * Else, fall back to pre-APICv interrupt injection since L2 |
963fee16 WL |
7525 | * is run without virtual interrupt delivery. |
7526 | */ | |
7527 | if (!kvm_event_needs_reinjection(vcpu) && | |
7528 | vmx_interrupt_allowed(vcpu)) { | |
7529 | kvm_queue_interrupt(vcpu, max_irr, false); | |
7530 | vmx_inject_irq(vcpu); | |
7531 | } | |
c7c9c56c YZ |
7532 | } |
7533 | ||
7534 | static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap) | |
7535 | { | |
3d81bc7e YZ |
7536 | if (!vmx_vm_has_apicv(vcpu->kvm)) |
7537 | return; | |
7538 | ||
c7c9c56c YZ |
7539 | vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]); |
7540 | vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]); | |
7541 | vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]); | |
7542 | vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]); | |
7543 | } | |
7544 | ||
51aa01d1 | 7545 | static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx) |
cf393f75 | 7546 | { |
00eba012 AK |
7547 | u32 exit_intr_info; |
7548 | ||
7549 | if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY | |
7550 | || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI)) | |
7551 | return; | |
7552 | ||
c5ca8e57 | 7553 | vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); |
00eba012 | 7554 | exit_intr_info = vmx->exit_intr_info; |
a0861c02 AK |
7555 | |
7556 | /* Handle machine checks before interrupts are enabled */ | |
00eba012 | 7557 | if (is_machine_check(exit_intr_info)) |
a0861c02 AK |
7558 | kvm_machine_check(); |
7559 | ||
20f65983 | 7560 | /* We need to handle NMIs before interrupts are enabled */ |
00eba012 | 7561 | if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR && |
ff9d07a0 ZY |
7562 | (exit_intr_info & INTR_INFO_VALID_MASK)) { |
7563 | kvm_before_handle_nmi(&vmx->vcpu); | |
20f65983 | 7564 | asm("int $2"); |
ff9d07a0 ZY |
7565 | kvm_after_handle_nmi(&vmx->vcpu); |
7566 | } | |
51aa01d1 | 7567 | } |
20f65983 | 7568 | |
a547c6db YZ |
7569 | static void vmx_handle_external_intr(struct kvm_vcpu *vcpu) |
7570 | { | |
7571 | u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); | |
7572 | ||
7573 | /* | |
7574 | * If external interrupt exists, IF bit is set in rflags/eflags on the | |
7575 | * interrupt stack frame, and interrupt will be enabled on a return | |
7576 | * from interrupt handler. | |
7577 | */ | |
7578 | if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK)) | |
7579 | == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) { | |
7580 | unsigned int vector; | |
7581 | unsigned long entry; | |
7582 | gate_desc *desc; | |
7583 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
7584 | #ifdef CONFIG_X86_64 | |
7585 | unsigned long tmp; | |
7586 | #endif | |
7587 | ||
7588 | vector = exit_intr_info & INTR_INFO_VECTOR_MASK; | |
7589 | desc = (gate_desc *)vmx->host_idt_base + vector; | |
7590 | entry = gate_offset(*desc); | |
7591 | asm volatile( | |
7592 | #ifdef CONFIG_X86_64 | |
7593 | "mov %%" _ASM_SP ", %[sp]\n\t" | |
7594 | "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t" | |
7595 | "push $%c[ss]\n\t" | |
7596 | "push %[sp]\n\t" | |
7597 | #endif | |
7598 | "pushf\n\t" | |
7599 | "orl $0x200, (%%" _ASM_SP ")\n\t" | |
7600 | __ASM_SIZE(push) " $%c[cs]\n\t" | |
7601 | "call *%[entry]\n\t" | |
7602 | : | |
7603 | #ifdef CONFIG_X86_64 | |
7604 | [sp]"=&r"(tmp) | |
7605 | #endif | |
7606 | : | |
7607 | [entry]"r"(entry), | |
7608 | [ss]"i"(__KERNEL_DS), | |
7609 | [cs]"i"(__KERNEL_CS) | |
7610 | ); | |
7611 | } else | |
7612 | local_irq_enable(); | |
7613 | } | |
7614 | ||
da8999d3 LJ |
7615 | static bool vmx_mpx_supported(void) |
7616 | { | |
7617 | return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) && | |
7618 | (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS); | |
7619 | } | |
7620 | ||
55412b2e WL |
7621 | static bool vmx_xsaves_supported(void) |
7622 | { | |
7623 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
7624 | SECONDARY_EXEC_XSAVES; | |
7625 | } | |
7626 | ||
51aa01d1 AK |
7627 | static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx) |
7628 | { | |
c5ca8e57 | 7629 | u32 exit_intr_info; |
51aa01d1 AK |
7630 | bool unblock_nmi; |
7631 | u8 vector; | |
7632 | bool idtv_info_valid; | |
7633 | ||
7634 | idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK; | |
20f65983 | 7635 | |
cf393f75 | 7636 | if (cpu_has_virtual_nmis()) { |
9d58b931 AK |
7637 | if (vmx->nmi_known_unmasked) |
7638 | return; | |
c5ca8e57 AK |
7639 | /* |
7640 | * Can't use vmx->exit_intr_info since we're not sure what | |
7641 | * the exit reason is. | |
7642 | */ | |
7643 | exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); | |
cf393f75 AK |
7644 | unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0; |
7645 | vector = exit_intr_info & INTR_INFO_VECTOR_MASK; | |
7646 | /* | |
7b4a25cb | 7647 | * SDM 3: 27.7.1.2 (September 2008) |
cf393f75 AK |
7648 | * Re-set bit "block by NMI" before VM entry if vmexit caused by |
7649 | * a guest IRET fault. | |
7b4a25cb GN |
7650 | * SDM 3: 23.2.2 (September 2008) |
7651 | * Bit 12 is undefined in any of the following cases: | |
7652 | * If the VM exit sets the valid bit in the IDT-vectoring | |
7653 | * information field. | |
7654 | * If the VM exit is due to a double fault. | |
cf393f75 | 7655 | */ |
7b4a25cb GN |
7656 | if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi && |
7657 | vector != DF_VECTOR && !idtv_info_valid) | |
cf393f75 AK |
7658 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, |
7659 | GUEST_INTR_STATE_NMI); | |
9d58b931 AK |
7660 | else |
7661 | vmx->nmi_known_unmasked = | |
7662 | !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) | |
7663 | & GUEST_INTR_STATE_NMI); | |
3b86cd99 JK |
7664 | } else if (unlikely(vmx->soft_vnmi_blocked)) |
7665 | vmx->vnmi_blocked_time += | |
7666 | ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time)); | |
51aa01d1 AK |
7667 | } |
7668 | ||
3ab66e8a | 7669 | static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu, |
83422e17 AK |
7670 | u32 idt_vectoring_info, |
7671 | int instr_len_field, | |
7672 | int error_code_field) | |
51aa01d1 | 7673 | { |
51aa01d1 AK |
7674 | u8 vector; |
7675 | int type; | |
7676 | bool idtv_info_valid; | |
7677 | ||
7678 | idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK; | |
668f612f | 7679 | |
3ab66e8a JK |
7680 | vcpu->arch.nmi_injected = false; |
7681 | kvm_clear_exception_queue(vcpu); | |
7682 | kvm_clear_interrupt_queue(vcpu); | |
37b96e98 GN |
7683 | |
7684 | if (!idtv_info_valid) | |
7685 | return; | |
7686 | ||
3ab66e8a | 7687 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
3842d135 | 7688 | |
668f612f AK |
7689 | vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK; |
7690 | type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK; | |
37b96e98 | 7691 | |
64a7ec06 | 7692 | switch (type) { |
37b96e98 | 7693 | case INTR_TYPE_NMI_INTR: |
3ab66e8a | 7694 | vcpu->arch.nmi_injected = true; |
668f612f | 7695 | /* |
7b4a25cb | 7696 | * SDM 3: 27.7.1.2 (September 2008) |
37b96e98 GN |
7697 | * Clear bit "block by NMI" before VM entry if a NMI |
7698 | * delivery faulted. | |
668f612f | 7699 | */ |
3ab66e8a | 7700 | vmx_set_nmi_mask(vcpu, false); |
37b96e98 | 7701 | break; |
37b96e98 | 7702 | case INTR_TYPE_SOFT_EXCEPTION: |
3ab66e8a | 7703 | vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field); |
66fd3f7f GN |
7704 | /* fall through */ |
7705 | case INTR_TYPE_HARD_EXCEPTION: | |
35920a35 | 7706 | if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) { |
83422e17 | 7707 | u32 err = vmcs_read32(error_code_field); |
851eb667 | 7708 | kvm_requeue_exception_e(vcpu, vector, err); |
35920a35 | 7709 | } else |
851eb667 | 7710 | kvm_requeue_exception(vcpu, vector); |
37b96e98 | 7711 | break; |
66fd3f7f | 7712 | case INTR_TYPE_SOFT_INTR: |
3ab66e8a | 7713 | vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field); |
66fd3f7f | 7714 | /* fall through */ |
37b96e98 | 7715 | case INTR_TYPE_EXT_INTR: |
3ab66e8a | 7716 | kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR); |
37b96e98 GN |
7717 | break; |
7718 | default: | |
7719 | break; | |
f7d9238f | 7720 | } |
cf393f75 AK |
7721 | } |
7722 | ||
83422e17 AK |
7723 | static void vmx_complete_interrupts(struct vcpu_vmx *vmx) |
7724 | { | |
3ab66e8a | 7725 | __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info, |
83422e17 AK |
7726 | VM_EXIT_INSTRUCTION_LEN, |
7727 | IDT_VECTORING_ERROR_CODE); | |
7728 | } | |
7729 | ||
b463a6f7 AK |
7730 | static void vmx_cancel_injection(struct kvm_vcpu *vcpu) |
7731 | { | |
3ab66e8a | 7732 | __vmx_complete_interrupts(vcpu, |
b463a6f7 AK |
7733 | vmcs_read32(VM_ENTRY_INTR_INFO_FIELD), |
7734 | VM_ENTRY_INSTRUCTION_LEN, | |
7735 | VM_ENTRY_EXCEPTION_ERROR_CODE); | |
7736 | ||
7737 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); | |
7738 | } | |
7739 | ||
d7cd9796 GN |
7740 | static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx) |
7741 | { | |
7742 | int i, nr_msrs; | |
7743 | struct perf_guest_switch_msr *msrs; | |
7744 | ||
7745 | msrs = perf_guest_get_msrs(&nr_msrs); | |
7746 | ||
7747 | if (!msrs) | |
7748 | return; | |
7749 | ||
7750 | for (i = 0; i < nr_msrs; i++) | |
7751 | if (msrs[i].host == msrs[i].guest) | |
7752 | clear_atomic_switch_msr(vmx, msrs[i].msr); | |
7753 | else | |
7754 | add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest, | |
7755 | msrs[i].host); | |
7756 | } | |
7757 | ||
a3b5ba49 | 7758 | static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu) |
6aa8b732 | 7759 | { |
a2fa3e9f | 7760 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
d974baa3 | 7761 | unsigned long debugctlmsr, cr4; |
104f226b AK |
7762 | |
7763 | /* Record the guest's net vcpu time for enforced NMI injections. */ | |
7764 | if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) | |
7765 | vmx->entry_time = ktime_get(); | |
7766 | ||
7767 | /* Don't enter VMX if guest state is invalid, let the exit handler | |
7768 | start emulation until we arrive back to a valid state */ | |
14168786 | 7769 | if (vmx->emulation_required) |
104f226b AK |
7770 | return; |
7771 | ||
a7653ecd RK |
7772 | if (vmx->ple_window_dirty) { |
7773 | vmx->ple_window_dirty = false; | |
7774 | vmcs_write32(PLE_WINDOW, vmx->ple_window); | |
7775 | } | |
7776 | ||
012f83cb AG |
7777 | if (vmx->nested.sync_shadow_vmcs) { |
7778 | copy_vmcs12_to_shadow(vmx); | |
7779 | vmx->nested.sync_shadow_vmcs = false; | |
7780 | } | |
7781 | ||
104f226b AK |
7782 | if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty)) |
7783 | vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]); | |
7784 | if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty)) | |
7785 | vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]); | |
7786 | ||
d974baa3 AL |
7787 | cr4 = read_cr4(); |
7788 | if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) { | |
7789 | vmcs_writel(HOST_CR4, cr4); | |
7790 | vmx->host_state.vmcs_host_cr4 = cr4; | |
7791 | } | |
7792 | ||
104f226b AK |
7793 | /* When single-stepping over STI and MOV SS, we must clear the |
7794 | * corresponding interruptibility bits in the guest state. Otherwise | |
7795 | * vmentry fails as it then expects bit 14 (BS) in pending debug | |
7796 | * exceptions being set, but that's not correct for the guest debugging | |
7797 | * case. */ | |
7798 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) | |
7799 | vmx_set_interrupt_shadow(vcpu, 0); | |
7800 | ||
d7cd9796 | 7801 | atomic_switch_perf_msrs(vmx); |
2a7921b7 | 7802 | debugctlmsr = get_debugctlmsr(); |
d7cd9796 | 7803 | |
d462b819 | 7804 | vmx->__launched = vmx->loaded_vmcs->launched; |
104f226b | 7805 | asm( |
6aa8b732 | 7806 | /* Store host registers */ |
b188c81f AK |
7807 | "push %%" _ASM_DX "; push %%" _ASM_BP ";" |
7808 | "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */ | |
7809 | "push %%" _ASM_CX " \n\t" | |
7810 | "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t" | |
313dbd49 | 7811 | "je 1f \n\t" |
b188c81f | 7812 | "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t" |
4ecac3fd | 7813 | __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t" |
313dbd49 | 7814 | "1: \n\t" |
d3edefc0 | 7815 | /* Reload cr2 if changed */ |
b188c81f AK |
7816 | "mov %c[cr2](%0), %%" _ASM_AX " \n\t" |
7817 | "mov %%cr2, %%" _ASM_DX " \n\t" | |
7818 | "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t" | |
d3edefc0 | 7819 | "je 2f \n\t" |
b188c81f | 7820 | "mov %%" _ASM_AX", %%cr2 \n\t" |
d3edefc0 | 7821 | "2: \n\t" |
6aa8b732 | 7822 | /* Check if vmlaunch of vmresume is needed */ |
e08aa78a | 7823 | "cmpl $0, %c[launched](%0) \n\t" |
6aa8b732 | 7824 | /* Load guest registers. Don't clobber flags. */ |
b188c81f AK |
7825 | "mov %c[rax](%0), %%" _ASM_AX " \n\t" |
7826 | "mov %c[rbx](%0), %%" _ASM_BX " \n\t" | |
7827 | "mov %c[rdx](%0), %%" _ASM_DX " \n\t" | |
7828 | "mov %c[rsi](%0), %%" _ASM_SI " \n\t" | |
7829 | "mov %c[rdi](%0), %%" _ASM_DI " \n\t" | |
7830 | "mov %c[rbp](%0), %%" _ASM_BP " \n\t" | |
05b3e0c2 | 7831 | #ifdef CONFIG_X86_64 |
e08aa78a AK |
7832 | "mov %c[r8](%0), %%r8 \n\t" |
7833 | "mov %c[r9](%0), %%r9 \n\t" | |
7834 | "mov %c[r10](%0), %%r10 \n\t" | |
7835 | "mov %c[r11](%0), %%r11 \n\t" | |
7836 | "mov %c[r12](%0), %%r12 \n\t" | |
7837 | "mov %c[r13](%0), %%r13 \n\t" | |
7838 | "mov %c[r14](%0), %%r14 \n\t" | |
7839 | "mov %c[r15](%0), %%r15 \n\t" | |
6aa8b732 | 7840 | #endif |
b188c81f | 7841 | "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */ |
c801949d | 7842 | |
6aa8b732 | 7843 | /* Enter guest mode */ |
83287ea4 | 7844 | "jne 1f \n\t" |
4ecac3fd | 7845 | __ex(ASM_VMX_VMLAUNCH) "\n\t" |
83287ea4 AK |
7846 | "jmp 2f \n\t" |
7847 | "1: " __ex(ASM_VMX_VMRESUME) "\n\t" | |
7848 | "2: " | |
6aa8b732 | 7849 | /* Save guest registers, load host registers, keep flags */ |
b188c81f | 7850 | "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t" |
40712fae | 7851 | "pop %0 \n\t" |
b188c81f AK |
7852 | "mov %%" _ASM_AX ", %c[rax](%0) \n\t" |
7853 | "mov %%" _ASM_BX ", %c[rbx](%0) \n\t" | |
7854 | __ASM_SIZE(pop) " %c[rcx](%0) \n\t" | |
7855 | "mov %%" _ASM_DX ", %c[rdx](%0) \n\t" | |
7856 | "mov %%" _ASM_SI ", %c[rsi](%0) \n\t" | |
7857 | "mov %%" _ASM_DI ", %c[rdi](%0) \n\t" | |
7858 | "mov %%" _ASM_BP ", %c[rbp](%0) \n\t" | |
05b3e0c2 | 7859 | #ifdef CONFIG_X86_64 |
e08aa78a AK |
7860 | "mov %%r8, %c[r8](%0) \n\t" |
7861 | "mov %%r9, %c[r9](%0) \n\t" | |
7862 | "mov %%r10, %c[r10](%0) \n\t" | |
7863 | "mov %%r11, %c[r11](%0) \n\t" | |
7864 | "mov %%r12, %c[r12](%0) \n\t" | |
7865 | "mov %%r13, %c[r13](%0) \n\t" | |
7866 | "mov %%r14, %c[r14](%0) \n\t" | |
7867 | "mov %%r15, %c[r15](%0) \n\t" | |
6aa8b732 | 7868 | #endif |
b188c81f AK |
7869 | "mov %%cr2, %%" _ASM_AX " \n\t" |
7870 | "mov %%" _ASM_AX ", %c[cr2](%0) \n\t" | |
c801949d | 7871 | |
b188c81f | 7872 | "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t" |
e08aa78a | 7873 | "setbe %c[fail](%0) \n\t" |
83287ea4 AK |
7874 | ".pushsection .rodata \n\t" |
7875 | ".global vmx_return \n\t" | |
7876 | "vmx_return: " _ASM_PTR " 2b \n\t" | |
7877 | ".popsection" | |
e08aa78a | 7878 | : : "c"(vmx), "d"((unsigned long)HOST_RSP), |
d462b819 | 7879 | [launched]"i"(offsetof(struct vcpu_vmx, __launched)), |
e08aa78a | 7880 | [fail]"i"(offsetof(struct vcpu_vmx, fail)), |
313dbd49 | 7881 | [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)), |
ad312c7c ZX |
7882 | [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])), |
7883 | [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])), | |
7884 | [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])), | |
7885 | [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])), | |
7886 | [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])), | |
7887 | [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])), | |
7888 | [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])), | |
05b3e0c2 | 7889 | #ifdef CONFIG_X86_64 |
ad312c7c ZX |
7890 | [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])), |
7891 | [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])), | |
7892 | [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])), | |
7893 | [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])), | |
7894 | [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])), | |
7895 | [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])), | |
7896 | [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])), | |
7897 | [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])), | |
6aa8b732 | 7898 | #endif |
40712fae AK |
7899 | [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)), |
7900 | [wordsize]"i"(sizeof(ulong)) | |
c2036300 LV |
7901 | : "cc", "memory" |
7902 | #ifdef CONFIG_X86_64 | |
b188c81f | 7903 | , "rax", "rbx", "rdi", "rsi" |
c2036300 | 7904 | , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" |
b188c81f AK |
7905 | #else |
7906 | , "eax", "ebx", "edi", "esi" | |
c2036300 LV |
7907 | #endif |
7908 | ); | |
6aa8b732 | 7909 | |
2a7921b7 GN |
7910 | /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */ |
7911 | if (debugctlmsr) | |
7912 | update_debugctlmsr(debugctlmsr); | |
7913 | ||
aa67f609 AK |
7914 | #ifndef CONFIG_X86_64 |
7915 | /* | |
7916 | * The sysexit path does not restore ds/es, so we must set them to | |
7917 | * a reasonable value ourselves. | |
7918 | * | |
7919 | * We can't defer this to vmx_load_host_state() since that function | |
7920 | * may be executed in interrupt context, which saves and restore segments | |
7921 | * around it, nullifying its effect. | |
7922 | */ | |
7923 | loadsegment(ds, __USER_DS); | |
7924 | loadsegment(es, __USER_DS); | |
7925 | #endif | |
7926 | ||
6de4f3ad | 7927 | vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP) |
6de12732 | 7928 | | (1 << VCPU_EXREG_RFLAGS) |
aff48baa | 7929 | | (1 << VCPU_EXREG_PDPTR) |
2fb92db1 | 7930 | | (1 << VCPU_EXREG_SEGMENTS) |
aff48baa | 7931 | | (1 << VCPU_EXREG_CR3)); |
5fdbf976 MT |
7932 | vcpu->arch.regs_dirty = 0; |
7933 | ||
1155f76a AK |
7934 | vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD); |
7935 | ||
d462b819 | 7936 | vmx->loaded_vmcs->launched = 1; |
1b6269db | 7937 | |
51aa01d1 | 7938 | vmx->exit_reason = vmcs_read32(VM_EXIT_REASON); |
1e2b1dd7 | 7939 | trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX); |
51aa01d1 | 7940 | |
e0b890d3 GN |
7941 | /* |
7942 | * the KVM_REQ_EVENT optimization bit is only on for one entry, and if | |
7943 | * we did not inject a still-pending event to L1 now because of | |
7944 | * nested_run_pending, we need to re-enable this bit. | |
7945 | */ | |
7946 | if (vmx->nested.nested_run_pending) | |
7947 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
7948 | ||
7949 | vmx->nested.nested_run_pending = 0; | |
7950 | ||
51aa01d1 AK |
7951 | vmx_complete_atomic_exit(vmx); |
7952 | vmx_recover_nmi_blocking(vmx); | |
cf393f75 | 7953 | vmx_complete_interrupts(vmx); |
6aa8b732 AK |
7954 | } |
7955 | ||
4fa7734c PB |
7956 | static void vmx_load_vmcs01(struct kvm_vcpu *vcpu) |
7957 | { | |
7958 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
7959 | int cpu; | |
7960 | ||
7961 | if (vmx->loaded_vmcs == &vmx->vmcs01) | |
7962 | return; | |
7963 | ||
7964 | cpu = get_cpu(); | |
7965 | vmx->loaded_vmcs = &vmx->vmcs01; | |
7966 | vmx_vcpu_put(vcpu); | |
7967 | vmx_vcpu_load(vcpu, cpu); | |
7968 | vcpu->cpu = cpu; | |
7969 | put_cpu(); | |
7970 | } | |
7971 | ||
6aa8b732 AK |
7972 | static void vmx_free_vcpu(struct kvm_vcpu *vcpu) |
7973 | { | |
fb3f0f51 RR |
7974 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
7975 | ||
cdbecfc3 | 7976 | free_vpid(vmx); |
4fa7734c PB |
7977 | leave_guest_mode(vcpu); |
7978 | vmx_load_vmcs01(vcpu); | |
26a865f4 | 7979 | free_nested(vmx); |
4fa7734c | 7980 | free_loaded_vmcs(vmx->loaded_vmcs); |
fb3f0f51 RR |
7981 | kfree(vmx->guest_msrs); |
7982 | kvm_vcpu_uninit(vcpu); | |
a4770347 | 7983 | kmem_cache_free(kvm_vcpu_cache, vmx); |
6aa8b732 AK |
7984 | } |
7985 | ||
fb3f0f51 | 7986 | static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 7987 | { |
fb3f0f51 | 7988 | int err; |
c16f862d | 7989 | struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); |
15ad7146 | 7990 | int cpu; |
6aa8b732 | 7991 | |
a2fa3e9f | 7992 | if (!vmx) |
fb3f0f51 RR |
7993 | return ERR_PTR(-ENOMEM); |
7994 | ||
2384d2b3 SY |
7995 | allocate_vpid(vmx); |
7996 | ||
fb3f0f51 RR |
7997 | err = kvm_vcpu_init(&vmx->vcpu, kvm, id); |
7998 | if (err) | |
7999 | goto free_vcpu; | |
965b58a5 | 8000 | |
a2fa3e9f | 8001 | vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL); |
03916db9 PB |
8002 | BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0]) |
8003 | > PAGE_SIZE); | |
0123be42 | 8004 | |
be6d05cf | 8005 | err = -ENOMEM; |
fb3f0f51 | 8006 | if (!vmx->guest_msrs) { |
fb3f0f51 RR |
8007 | goto uninit_vcpu; |
8008 | } | |
965b58a5 | 8009 | |
d462b819 NHE |
8010 | vmx->loaded_vmcs = &vmx->vmcs01; |
8011 | vmx->loaded_vmcs->vmcs = alloc_vmcs(); | |
8012 | if (!vmx->loaded_vmcs->vmcs) | |
fb3f0f51 | 8013 | goto free_msrs; |
d462b819 NHE |
8014 | if (!vmm_exclusive) |
8015 | kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id()))); | |
8016 | loaded_vmcs_init(vmx->loaded_vmcs); | |
8017 | if (!vmm_exclusive) | |
8018 | kvm_cpu_vmxoff(); | |
a2fa3e9f | 8019 | |
15ad7146 AK |
8020 | cpu = get_cpu(); |
8021 | vmx_vcpu_load(&vmx->vcpu, cpu); | |
e48672fa | 8022 | vmx->vcpu.cpu = cpu; |
8b9cf98c | 8023 | err = vmx_vcpu_setup(vmx); |
fb3f0f51 | 8024 | vmx_vcpu_put(&vmx->vcpu); |
15ad7146 | 8025 | put_cpu(); |
fb3f0f51 RR |
8026 | if (err) |
8027 | goto free_vmcs; | |
a63cb560 | 8028 | if (vm_need_virtualize_apic_accesses(kvm)) { |
be6d05cf JK |
8029 | err = alloc_apic_access_page(kvm); |
8030 | if (err) | |
5e4a0b3c | 8031 | goto free_vmcs; |
a63cb560 | 8032 | } |
fb3f0f51 | 8033 | |
b927a3ce SY |
8034 | if (enable_ept) { |
8035 | if (!kvm->arch.ept_identity_map_addr) | |
8036 | kvm->arch.ept_identity_map_addr = | |
8037 | VMX_EPT_IDENTITY_PAGETABLE_ADDR; | |
f51770ed TC |
8038 | err = init_rmode_identity_map(kvm); |
8039 | if (err) | |
93ea5388 | 8040 | goto free_vmcs; |
b927a3ce | 8041 | } |
b7ebfb05 | 8042 | |
a9d30f33 NHE |
8043 | vmx->nested.current_vmptr = -1ull; |
8044 | vmx->nested.current_vmcs12 = NULL; | |
8045 | ||
fb3f0f51 RR |
8046 | return &vmx->vcpu; |
8047 | ||
8048 | free_vmcs: | |
5f3fbc34 | 8049 | free_loaded_vmcs(vmx->loaded_vmcs); |
fb3f0f51 | 8050 | free_msrs: |
fb3f0f51 RR |
8051 | kfree(vmx->guest_msrs); |
8052 | uninit_vcpu: | |
8053 | kvm_vcpu_uninit(&vmx->vcpu); | |
8054 | free_vcpu: | |
cdbecfc3 | 8055 | free_vpid(vmx); |
a4770347 | 8056 | kmem_cache_free(kvm_vcpu_cache, vmx); |
fb3f0f51 | 8057 | return ERR_PTR(err); |
6aa8b732 AK |
8058 | } |
8059 | ||
002c7f7c YS |
8060 | static void __init vmx_check_processor_compat(void *rtn) |
8061 | { | |
8062 | struct vmcs_config vmcs_conf; | |
8063 | ||
8064 | *(int *)rtn = 0; | |
8065 | if (setup_vmcs_config(&vmcs_conf) < 0) | |
8066 | *(int *)rtn = -EIO; | |
8067 | if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) { | |
8068 | printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n", | |
8069 | smp_processor_id()); | |
8070 | *(int *)rtn = -EIO; | |
8071 | } | |
8072 | } | |
8073 | ||
67253af5 SY |
8074 | static int get_ept_level(void) |
8075 | { | |
8076 | return VMX_EPT_DEFAULT_GAW + 1; | |
8077 | } | |
8078 | ||
4b12f0de | 8079 | static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio) |
64d4d521 | 8080 | { |
4b12f0de SY |
8081 | u64 ret; |
8082 | ||
522c68c4 SY |
8083 | /* For VT-d and EPT combination |
8084 | * 1. MMIO: always map as UC | |
8085 | * 2. EPT with VT-d: | |
8086 | * a. VT-d without snooping control feature: can't guarantee the | |
8087 | * result, try to trust guest. | |
8088 | * b. VT-d with snooping control feature: snooping control feature of | |
8089 | * VT-d engine can guarantee the cache correctness. Just set it | |
8090 | * to WB to keep consistent with host. So the same as item 3. | |
a19a6d11 | 8091 | * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep |
522c68c4 SY |
8092 | * consistent with host MTRR |
8093 | */ | |
4b12f0de SY |
8094 | if (is_mmio) |
8095 | ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT; | |
e0f0bbc5 | 8096 | else if (kvm_arch_has_noncoherent_dma(vcpu->kvm)) |
522c68c4 SY |
8097 | ret = kvm_get_guest_memory_type(vcpu, gfn) << |
8098 | VMX_EPT_MT_EPTE_SHIFT; | |
4b12f0de | 8099 | else |
522c68c4 | 8100 | ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT) |
a19a6d11 | 8101 | | VMX_EPT_IPAT_BIT; |
4b12f0de SY |
8102 | |
8103 | return ret; | |
64d4d521 SY |
8104 | } |
8105 | ||
17cc3935 | 8106 | static int vmx_get_lpage_level(void) |
344f414f | 8107 | { |
878403b7 SY |
8108 | if (enable_ept && !cpu_has_vmx_ept_1g_page()) |
8109 | return PT_DIRECTORY_LEVEL; | |
8110 | else | |
8111 | /* For shadow and EPT supported 1GB page */ | |
8112 | return PT_PDPE_LEVEL; | |
344f414f JR |
8113 | } |
8114 | ||
0e851880 SY |
8115 | static void vmx_cpuid_update(struct kvm_vcpu *vcpu) |
8116 | { | |
4e47c7a6 SY |
8117 | struct kvm_cpuid_entry2 *best; |
8118 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
8119 | u32 exec_control; | |
8120 | ||
8121 | vmx->rdtscp_enabled = false; | |
8122 | if (vmx_rdtscp_supported()) { | |
8123 | exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL); | |
8124 | if (exec_control & SECONDARY_EXEC_RDTSCP) { | |
8125 | best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); | |
8126 | if (best && (best->edx & bit(X86_FEATURE_RDTSCP))) | |
8127 | vmx->rdtscp_enabled = true; | |
8128 | else { | |
8129 | exec_control &= ~SECONDARY_EXEC_RDTSCP; | |
8130 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, | |
8131 | exec_control); | |
8132 | } | |
8133 | } | |
8134 | } | |
ad756a16 | 8135 | |
ad756a16 MJ |
8136 | /* Exposing INVPCID only when PCID is exposed */ |
8137 | best = kvm_find_cpuid_entry(vcpu, 0x7, 0); | |
8138 | if (vmx_invpcid_supported() && | |
4f977045 | 8139 | best && (best->ebx & bit(X86_FEATURE_INVPCID)) && |
ad756a16 | 8140 | guest_cpuid_has_pcid(vcpu)) { |
29282fde | 8141 | exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL); |
ad756a16 MJ |
8142 | exec_control |= SECONDARY_EXEC_ENABLE_INVPCID; |
8143 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, | |
8144 | exec_control); | |
8145 | } else { | |
29282fde TI |
8146 | if (cpu_has_secondary_exec_ctrls()) { |
8147 | exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL); | |
8148 | exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID; | |
8149 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, | |
8150 | exec_control); | |
8151 | } | |
ad756a16 | 8152 | if (best) |
4f977045 | 8153 | best->ebx &= ~bit(X86_FEATURE_INVPCID); |
ad756a16 | 8154 | } |
0e851880 SY |
8155 | } |
8156 | ||
d4330ef2 JR |
8157 | static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry) |
8158 | { | |
7b8050f5 NHE |
8159 | if (func == 1 && nested) |
8160 | entry->ecx |= bit(X86_FEATURE_VMX); | |
d4330ef2 JR |
8161 | } |
8162 | ||
25d92081 YZ |
8163 | static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu, |
8164 | struct x86_exception *fault) | |
8165 | { | |
533558bc JK |
8166 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
8167 | u32 exit_reason; | |
25d92081 YZ |
8168 | |
8169 | if (fault->error_code & PFERR_RSVD_MASK) | |
533558bc | 8170 | exit_reason = EXIT_REASON_EPT_MISCONFIG; |
25d92081 | 8171 | else |
533558bc JK |
8172 | exit_reason = EXIT_REASON_EPT_VIOLATION; |
8173 | nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification); | |
25d92081 YZ |
8174 | vmcs12->guest_physical_address = fault->address; |
8175 | } | |
8176 | ||
155a97a3 NHE |
8177 | /* Callbacks for nested_ept_init_mmu_context: */ |
8178 | ||
8179 | static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu) | |
8180 | { | |
8181 | /* return the page table to be shadowed - in our case, EPT12 */ | |
8182 | return get_vmcs12(vcpu)->ept_pointer; | |
8183 | } | |
8184 | ||
8a3c1a33 | 8185 | static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu) |
155a97a3 | 8186 | { |
8a3c1a33 | 8187 | kvm_init_shadow_ept_mmu(vcpu, &vcpu->arch.mmu, |
155a97a3 NHE |
8188 | nested_vmx_ept_caps & VMX_EPT_EXECUTE_ONLY_BIT); |
8189 | ||
8190 | vcpu->arch.mmu.set_cr3 = vmx_set_cr3; | |
8191 | vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3; | |
8192 | vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault; | |
8193 | ||
8194 | vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu; | |
155a97a3 NHE |
8195 | } |
8196 | ||
8197 | static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu) | |
8198 | { | |
8199 | vcpu->arch.walk_mmu = &vcpu->arch.mmu; | |
8200 | } | |
8201 | ||
feaf0c7d GN |
8202 | static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu, |
8203 | struct x86_exception *fault) | |
8204 | { | |
8205 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
8206 | ||
8207 | WARN_ON(!is_guest_mode(vcpu)); | |
8208 | ||
8209 | /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */ | |
8210 | if (vmcs12->exception_bitmap & (1u << PF_VECTOR)) | |
533558bc JK |
8211 | nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason, |
8212 | vmcs_read32(VM_EXIT_INTR_INFO), | |
8213 | vmcs_readl(EXIT_QUALIFICATION)); | |
feaf0c7d GN |
8214 | else |
8215 | kvm_inject_page_fault(vcpu, fault); | |
8216 | } | |
8217 | ||
a2bcba50 WL |
8218 | static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu, |
8219 | struct vmcs12 *vmcs12) | |
8220 | { | |
8221 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
8222 | ||
8223 | if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) { | |
a7c0b07d | 8224 | /* TODO: Also verify bits beyond physical address width are 0 */ |
a2bcba50 | 8225 | if (!PAGE_ALIGNED(vmcs12->apic_access_addr)) |
a2bcba50 WL |
8226 | return false; |
8227 | ||
8228 | /* | |
8229 | * Translate L1 physical address to host physical | |
8230 | * address for vmcs02. Keep the page pinned, so this | |
8231 | * physical address remains valid. We keep a reference | |
8232 | * to it so we can release it later. | |
8233 | */ | |
8234 | if (vmx->nested.apic_access_page) /* shouldn't happen */ | |
8235 | nested_release_page(vmx->nested.apic_access_page); | |
8236 | vmx->nested.apic_access_page = | |
8237 | nested_get_page(vcpu, vmcs12->apic_access_addr); | |
8238 | } | |
a7c0b07d WL |
8239 | |
8240 | if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) { | |
8241 | /* TODO: Also verify bits beyond physical address width are 0 */ | |
8242 | if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr)) | |
8243 | return false; | |
8244 | ||
8245 | if (vmx->nested.virtual_apic_page) /* shouldn't happen */ | |
8246 | nested_release_page(vmx->nested.virtual_apic_page); | |
8247 | vmx->nested.virtual_apic_page = | |
8248 | nested_get_page(vcpu, vmcs12->virtual_apic_page_addr); | |
8249 | ||
8250 | /* | |
8251 | * Failing the vm entry is _not_ what the processor does | |
8252 | * but it's basically the only possibility we have. | |
8253 | * We could still enter the guest if CR8 load exits are | |
8254 | * enabled, CR8 store exits are enabled, and virtualize APIC | |
8255 | * access is disabled; in this case the processor would never | |
8256 | * use the TPR shadow and we could simply clear the bit from | |
8257 | * the execution control. But such a configuration is useless, | |
8258 | * so let's keep the code simple. | |
8259 | */ | |
8260 | if (!vmx->nested.virtual_apic_page) | |
8261 | return false; | |
8262 | } | |
8263 | ||
a2bcba50 WL |
8264 | return true; |
8265 | } | |
8266 | ||
f4124500 JK |
8267 | static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu) |
8268 | { | |
8269 | u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value; | |
8270 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
8271 | ||
8272 | if (vcpu->arch.virtual_tsc_khz == 0) | |
8273 | return; | |
8274 | ||
8275 | /* Make sure short timeouts reliably trigger an immediate vmexit. | |
8276 | * hrtimer_start does not guarantee this. */ | |
8277 | if (preemption_timeout <= 1) { | |
8278 | vmx_preemption_timer_fn(&vmx->nested.preemption_timer); | |
8279 | return; | |
8280 | } | |
8281 | ||
8282 | preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE; | |
8283 | preemption_timeout *= 1000000; | |
8284 | do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz); | |
8285 | hrtimer_start(&vmx->nested.preemption_timer, | |
8286 | ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL); | |
8287 | } | |
8288 | ||
fe3ef05c NHE |
8289 | /* |
8290 | * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested | |
8291 | * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it | |
b4619660 | 8292 | * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2 |
fe3ef05c NHE |
8293 | * guest in a way that will both be appropriate to L1's requests, and our |
8294 | * needs. In addition to modifying the active vmcs (which is vmcs02), this | |
8295 | * function also has additional necessary side-effects, like setting various | |
8296 | * vcpu->arch fields. | |
8297 | */ | |
8298 | static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12) | |
8299 | { | |
8300 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
8301 | u32 exec_control; | |
8302 | ||
8303 | vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector); | |
8304 | vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector); | |
8305 | vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector); | |
8306 | vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector); | |
8307 | vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector); | |
8308 | vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector); | |
8309 | vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector); | |
8310 | vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector); | |
8311 | vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit); | |
8312 | vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit); | |
8313 | vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit); | |
8314 | vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit); | |
8315 | vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit); | |
8316 | vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit); | |
8317 | vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit); | |
8318 | vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit); | |
8319 | vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit); | |
8320 | vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit); | |
8321 | vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes); | |
8322 | vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes); | |
8323 | vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes); | |
8324 | vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes); | |
8325 | vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes); | |
8326 | vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes); | |
8327 | vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes); | |
8328 | vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes); | |
8329 | vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base); | |
8330 | vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base); | |
8331 | vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base); | |
8332 | vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base); | |
8333 | vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base); | |
8334 | vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base); | |
8335 | vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base); | |
8336 | vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base); | |
8337 | vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base); | |
8338 | vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base); | |
8339 | ||
2996fca0 JK |
8340 | if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) { |
8341 | kvm_set_dr(vcpu, 7, vmcs12->guest_dr7); | |
8342 | vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl); | |
8343 | } else { | |
8344 | kvm_set_dr(vcpu, 7, vcpu->arch.dr7); | |
8345 | vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl); | |
8346 | } | |
fe3ef05c NHE |
8347 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, |
8348 | vmcs12->vm_entry_intr_info_field); | |
8349 | vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, | |
8350 | vmcs12->vm_entry_exception_error_code); | |
8351 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, | |
8352 | vmcs12->vm_entry_instruction_len); | |
8353 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, | |
8354 | vmcs12->guest_interruptibility_info); | |
fe3ef05c | 8355 | vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs); |
63fbf59f | 8356 | vmx_set_rflags(vcpu, vmcs12->guest_rflags); |
fe3ef05c NHE |
8357 | vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, |
8358 | vmcs12->guest_pending_dbg_exceptions); | |
8359 | vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp); | |
8360 | vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip); | |
8361 | ||
81dc01f7 WL |
8362 | if (nested_cpu_has_xsaves(vmcs12)) |
8363 | vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap); | |
fe3ef05c NHE |
8364 | vmcs_write64(VMCS_LINK_POINTER, -1ull); |
8365 | ||
f4124500 JK |
8366 | exec_control = vmcs12->pin_based_vm_exec_control; |
8367 | exec_control |= vmcs_config.pin_based_exec_ctrl; | |
696dfd95 PB |
8368 | exec_control &= ~(PIN_BASED_VMX_PREEMPTION_TIMER | |
8369 | PIN_BASED_POSTED_INTR); | |
f4124500 | 8370 | vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control); |
fe3ef05c | 8371 | |
f4124500 JK |
8372 | vmx->nested.preemption_timer_expired = false; |
8373 | if (nested_cpu_has_preemption_timer(vmcs12)) | |
8374 | vmx_start_preemption_timer(vcpu); | |
0238ea91 | 8375 | |
fe3ef05c NHE |
8376 | /* |
8377 | * Whether page-faults are trapped is determined by a combination of | |
8378 | * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF. | |
8379 | * If enable_ept, L0 doesn't care about page faults and we should | |
8380 | * set all of these to L1's desires. However, if !enable_ept, L0 does | |
8381 | * care about (at least some) page faults, and because it is not easy | |
8382 | * (if at all possible?) to merge L0 and L1's desires, we simply ask | |
8383 | * to exit on each and every L2 page fault. This is done by setting | |
8384 | * MASK=MATCH=0 and (see below) EB.PF=1. | |
8385 | * Note that below we don't need special code to set EB.PF beyond the | |
8386 | * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept, | |
8387 | * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when | |
8388 | * !enable_ept, EB.PF is 1, so the "or" will always be 1. | |
8389 | * | |
8390 | * A problem with this approach (when !enable_ept) is that L1 may be | |
8391 | * injected with more page faults than it asked for. This could have | |
8392 | * caused problems, but in practice existing hypervisors don't care. | |
8393 | * To fix this, we will need to emulate the PFEC checking (on the L1 | |
8394 | * page tables), using walk_addr(), when injecting PFs to L1. | |
8395 | */ | |
8396 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, | |
8397 | enable_ept ? vmcs12->page_fault_error_code_mask : 0); | |
8398 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, | |
8399 | enable_ept ? vmcs12->page_fault_error_code_match : 0); | |
8400 | ||
8401 | if (cpu_has_secondary_exec_ctrls()) { | |
f4124500 | 8402 | exec_control = vmx_secondary_exec_control(vmx); |
fe3ef05c NHE |
8403 | if (!vmx->rdtscp_enabled) |
8404 | exec_control &= ~SECONDARY_EXEC_RDTSCP; | |
8405 | /* Take the following fields only from vmcs12 */ | |
696dfd95 PB |
8406 | exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | |
8407 | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | | |
8408 | SECONDARY_EXEC_APIC_REGISTER_VIRT); | |
fe3ef05c NHE |
8409 | if (nested_cpu_has(vmcs12, |
8410 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)) | |
8411 | exec_control |= vmcs12->secondary_vm_exec_control; | |
8412 | ||
8413 | if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) { | |
fe3ef05c NHE |
8414 | /* |
8415 | * If translation failed, no matter: This feature asks | |
8416 | * to exit when accessing the given address, and if it | |
8417 | * can never be accessed, this feature won't do | |
8418 | * anything anyway. | |
8419 | */ | |
8420 | if (!vmx->nested.apic_access_page) | |
8421 | exec_control &= | |
8422 | ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
8423 | else | |
8424 | vmcs_write64(APIC_ACCESS_ADDR, | |
8425 | page_to_phys(vmx->nested.apic_access_page)); | |
ca3f257a JK |
8426 | } else if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) { |
8427 | exec_control |= | |
8428 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
38b99173 | 8429 | kvm_vcpu_reload_apic_access_page(vcpu); |
fe3ef05c NHE |
8430 | } |
8431 | ||
8432 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control); | |
8433 | } | |
8434 | ||
8435 | ||
8436 | /* | |
8437 | * Set host-state according to L0's settings (vmcs12 is irrelevant here) | |
8438 | * Some constant fields are set here by vmx_set_constant_host_state(). | |
8439 | * Other fields are different per CPU, and will be set later when | |
8440 | * vmx_vcpu_load() is called, and when vmx_save_host_state() is called. | |
8441 | */ | |
a547c6db | 8442 | vmx_set_constant_host_state(vmx); |
fe3ef05c NHE |
8443 | |
8444 | /* | |
8445 | * HOST_RSP is normally set correctly in vmx_vcpu_run() just before | |
8446 | * entry, but only if the current (host) sp changed from the value | |
8447 | * we wrote last (vmx->host_rsp). This cache is no longer relevant | |
8448 | * if we switch vmcs, and rather than hold a separate cache per vmcs, | |
8449 | * here we just force the write to happen on entry. | |
8450 | */ | |
8451 | vmx->host_rsp = 0; | |
8452 | ||
8453 | exec_control = vmx_exec_control(vmx); /* L0's desires */ | |
8454 | exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING; | |
8455 | exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING; | |
8456 | exec_control &= ~CPU_BASED_TPR_SHADOW; | |
8457 | exec_control |= vmcs12->cpu_based_vm_exec_control; | |
a7c0b07d WL |
8458 | |
8459 | if (exec_control & CPU_BASED_TPR_SHADOW) { | |
8460 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, | |
8461 | page_to_phys(vmx->nested.virtual_apic_page)); | |
8462 | vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold); | |
8463 | } | |
8464 | ||
fe3ef05c NHE |
8465 | /* |
8466 | * Merging of IO and MSR bitmaps not currently supported. | |
8467 | * Rather, exit every time. | |
8468 | */ | |
8469 | exec_control &= ~CPU_BASED_USE_MSR_BITMAPS; | |
8470 | exec_control &= ~CPU_BASED_USE_IO_BITMAPS; | |
8471 | exec_control |= CPU_BASED_UNCOND_IO_EXITING; | |
8472 | ||
8473 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control); | |
8474 | ||
8475 | /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the | |
8476 | * bitwise-or of what L1 wants to trap for L2, and what we want to | |
8477 | * trap. Note that CR0.TS also needs updating - we do this later. | |
8478 | */ | |
8479 | update_exception_bitmap(vcpu); | |
8480 | vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask; | |
8481 | vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits); | |
8482 | ||
8049d651 NHE |
8483 | /* L2->L1 exit controls are emulated - the hardware exit is to L0 so |
8484 | * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER | |
8485 | * bits are further modified by vmx_set_efer() below. | |
8486 | */ | |
f4124500 | 8487 | vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl); |
8049d651 NHE |
8488 | |
8489 | /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are | |
8490 | * emulated by vmx_set_efer(), below. | |
8491 | */ | |
2961e876 | 8492 | vm_entry_controls_init(vmx, |
8049d651 NHE |
8493 | (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER & |
8494 | ~VM_ENTRY_IA32E_MODE) | | |
fe3ef05c NHE |
8495 | (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE)); |
8496 | ||
44811c02 | 8497 | if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) { |
fe3ef05c | 8498 | vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat); |
44811c02 JK |
8499 | vcpu->arch.pat = vmcs12->guest_ia32_pat; |
8500 | } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) | |
fe3ef05c NHE |
8501 | vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat); |
8502 | ||
8503 | ||
8504 | set_cr4_guest_host_mask(vmx); | |
8505 | ||
36be0b9d PB |
8506 | if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS) |
8507 | vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs); | |
8508 | ||
27fc51b2 NHE |
8509 | if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING) |
8510 | vmcs_write64(TSC_OFFSET, | |
8511 | vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset); | |
8512 | else | |
8513 | vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset); | |
fe3ef05c NHE |
8514 | |
8515 | if (enable_vpid) { | |
8516 | /* | |
8517 | * Trivially support vpid by letting L2s share their parent | |
8518 | * L1's vpid. TODO: move to a more elaborate solution, giving | |
8519 | * each L2 its own vpid and exposing the vpid feature to L1. | |
8520 | */ | |
8521 | vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid); | |
8522 | vmx_flush_tlb(vcpu); | |
8523 | } | |
8524 | ||
155a97a3 NHE |
8525 | if (nested_cpu_has_ept(vmcs12)) { |
8526 | kvm_mmu_unload(vcpu); | |
8527 | nested_ept_init_mmu_context(vcpu); | |
8528 | } | |
8529 | ||
fe3ef05c NHE |
8530 | if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) |
8531 | vcpu->arch.efer = vmcs12->guest_ia32_efer; | |
d1fa0352 | 8532 | else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) |
fe3ef05c NHE |
8533 | vcpu->arch.efer |= (EFER_LMA | EFER_LME); |
8534 | else | |
8535 | vcpu->arch.efer &= ~(EFER_LMA | EFER_LME); | |
8536 | /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */ | |
8537 | vmx_set_efer(vcpu, vcpu->arch.efer); | |
8538 | ||
8539 | /* | |
8540 | * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified | |
8541 | * TS bit (for lazy fpu) and bits which we consider mandatory enabled. | |
8542 | * The CR0_READ_SHADOW is what L2 should have expected to read given | |
8543 | * the specifications by L1; It's not enough to take | |
8544 | * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we | |
8545 | * have more bits than L1 expected. | |
8546 | */ | |
8547 | vmx_set_cr0(vcpu, vmcs12->guest_cr0); | |
8548 | vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12)); | |
8549 | ||
8550 | vmx_set_cr4(vcpu, vmcs12->guest_cr4); | |
8551 | vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12)); | |
8552 | ||
8553 | /* shadow page tables on either EPT or shadow page tables */ | |
8554 | kvm_set_cr3(vcpu, vmcs12->guest_cr3); | |
8555 | kvm_mmu_reset_context(vcpu); | |
8556 | ||
feaf0c7d GN |
8557 | if (!enable_ept) |
8558 | vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested; | |
8559 | ||
3633cfc3 NHE |
8560 | /* |
8561 | * L1 may access the L2's PDPTR, so save them to construct vmcs12 | |
8562 | */ | |
8563 | if (enable_ept) { | |
8564 | vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0); | |
8565 | vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1); | |
8566 | vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2); | |
8567 | vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3); | |
8568 | } | |
8569 | ||
fe3ef05c NHE |
8570 | kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp); |
8571 | kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip); | |
8572 | } | |
8573 | ||
cd232ad0 NHE |
8574 | /* |
8575 | * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1 | |
8576 | * for running an L2 nested guest. | |
8577 | */ | |
8578 | static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch) | |
8579 | { | |
8580 | struct vmcs12 *vmcs12; | |
8581 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
8582 | int cpu; | |
8583 | struct loaded_vmcs *vmcs02; | |
384bb783 | 8584 | bool ia32e; |
cd232ad0 NHE |
8585 | |
8586 | if (!nested_vmx_check_permission(vcpu) || | |
8587 | !nested_vmx_check_vmcs12(vcpu)) | |
8588 | return 1; | |
8589 | ||
8590 | skip_emulated_instruction(vcpu); | |
8591 | vmcs12 = get_vmcs12(vcpu); | |
8592 | ||
012f83cb AG |
8593 | if (enable_shadow_vmcs) |
8594 | copy_shadow_to_vmcs12(vmx); | |
8595 | ||
7c177938 NHE |
8596 | /* |
8597 | * The nested entry process starts with enforcing various prerequisites | |
8598 | * on vmcs12 as required by the Intel SDM, and act appropriately when | |
8599 | * they fail: As the SDM explains, some conditions should cause the | |
8600 | * instruction to fail, while others will cause the instruction to seem | |
8601 | * to succeed, but return an EXIT_REASON_INVALID_STATE. | |
8602 | * To speed up the normal (success) code path, we should avoid checking | |
8603 | * for misconfigurations which will anyway be caught by the processor | |
8604 | * when using the merged vmcs02. | |
8605 | */ | |
8606 | if (vmcs12->launch_state == launch) { | |
8607 | nested_vmx_failValid(vcpu, | |
8608 | launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS | |
8609 | : VMXERR_VMRESUME_NONLAUNCHED_VMCS); | |
8610 | return 1; | |
8611 | } | |
8612 | ||
6dfacadd JK |
8613 | if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE && |
8614 | vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) { | |
26539bd0 PB |
8615 | nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD); |
8616 | return 1; | |
8617 | } | |
8618 | ||
7c177938 | 8619 | if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) && |
bc39c4db | 8620 | !PAGE_ALIGNED(vmcs12->msr_bitmap)) { |
7c177938 NHE |
8621 | /*TODO: Also verify bits beyond physical address width are 0*/ |
8622 | nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD); | |
8623 | return 1; | |
8624 | } | |
8625 | ||
a2bcba50 | 8626 | if (!nested_get_vmcs12_pages(vcpu, vmcs12)) { |
7c177938 NHE |
8627 | /*TODO: Also verify bits beyond physical address width are 0*/ |
8628 | nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD); | |
8629 | return 1; | |
8630 | } | |
8631 | ||
8632 | if (vmcs12->vm_entry_msr_load_count > 0 || | |
8633 | vmcs12->vm_exit_msr_load_count > 0 || | |
8634 | vmcs12->vm_exit_msr_store_count > 0) { | |
bd80158a JK |
8635 | pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n", |
8636 | __func__); | |
7c177938 NHE |
8637 | nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD); |
8638 | return 1; | |
8639 | } | |
8640 | ||
8641 | if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control, | |
3dcdf3ec JK |
8642 | nested_vmx_true_procbased_ctls_low, |
8643 | nested_vmx_procbased_ctls_high) || | |
7c177938 NHE |
8644 | !vmx_control_verify(vmcs12->secondary_vm_exec_control, |
8645 | nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) || | |
8646 | !vmx_control_verify(vmcs12->pin_based_vm_exec_control, | |
8647 | nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) || | |
8648 | !vmx_control_verify(vmcs12->vm_exit_controls, | |
2996fca0 JK |
8649 | nested_vmx_true_exit_ctls_low, |
8650 | nested_vmx_exit_ctls_high) || | |
7c177938 | 8651 | !vmx_control_verify(vmcs12->vm_entry_controls, |
2996fca0 JK |
8652 | nested_vmx_true_entry_ctls_low, |
8653 | nested_vmx_entry_ctls_high)) | |
7c177938 NHE |
8654 | { |
8655 | nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD); | |
8656 | return 1; | |
8657 | } | |
8658 | ||
8659 | if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) || | |
8660 | ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) { | |
8661 | nested_vmx_failValid(vcpu, | |
8662 | VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); | |
8663 | return 1; | |
8664 | } | |
8665 | ||
92fbc7b1 | 8666 | if (!nested_cr0_valid(vmcs12, vmcs12->guest_cr0) || |
7c177938 NHE |
8667 | ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) { |
8668 | nested_vmx_entry_failure(vcpu, vmcs12, | |
8669 | EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT); | |
8670 | return 1; | |
8671 | } | |
8672 | if (vmcs12->vmcs_link_pointer != -1ull) { | |
8673 | nested_vmx_entry_failure(vcpu, vmcs12, | |
8674 | EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR); | |
8675 | return 1; | |
8676 | } | |
8677 | ||
384bb783 | 8678 | /* |
cb0c8cda | 8679 | * If the load IA32_EFER VM-entry control is 1, the following checks |
384bb783 JK |
8680 | * are performed on the field for the IA32_EFER MSR: |
8681 | * - Bits reserved in the IA32_EFER MSR must be 0. | |
8682 | * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of | |
8683 | * the IA-32e mode guest VM-exit control. It must also be identical | |
8684 | * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to | |
8685 | * CR0.PG) is 1. | |
8686 | */ | |
8687 | if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) { | |
8688 | ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0; | |
8689 | if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) || | |
8690 | ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) || | |
8691 | ((vmcs12->guest_cr0 & X86_CR0_PG) && | |
8692 | ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) { | |
8693 | nested_vmx_entry_failure(vcpu, vmcs12, | |
8694 | EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT); | |
8695 | return 1; | |
8696 | } | |
8697 | } | |
8698 | ||
8699 | /* | |
8700 | * If the load IA32_EFER VM-exit control is 1, bits reserved in the | |
8701 | * IA32_EFER MSR must be 0 in the field for that register. In addition, | |
8702 | * the values of the LMA and LME bits in the field must each be that of | |
8703 | * the host address-space size VM-exit control. | |
8704 | */ | |
8705 | if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) { | |
8706 | ia32e = (vmcs12->vm_exit_controls & | |
8707 | VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0; | |
8708 | if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) || | |
8709 | ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) || | |
8710 | ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) { | |
8711 | nested_vmx_entry_failure(vcpu, vmcs12, | |
8712 | EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT); | |
8713 | return 1; | |
8714 | } | |
8715 | } | |
8716 | ||
7c177938 NHE |
8717 | /* |
8718 | * We're finally done with prerequisite checking, and can start with | |
8719 | * the nested entry. | |
8720 | */ | |
8721 | ||
cd232ad0 NHE |
8722 | vmcs02 = nested_get_current_vmcs02(vmx); |
8723 | if (!vmcs02) | |
8724 | return -ENOMEM; | |
8725 | ||
8726 | enter_guest_mode(vcpu); | |
8727 | ||
8728 | vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET); | |
8729 | ||
2996fca0 JK |
8730 | if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) |
8731 | vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL); | |
8732 | ||
cd232ad0 NHE |
8733 | cpu = get_cpu(); |
8734 | vmx->loaded_vmcs = vmcs02; | |
8735 | vmx_vcpu_put(vcpu); | |
8736 | vmx_vcpu_load(vcpu, cpu); | |
8737 | vcpu->cpu = cpu; | |
8738 | put_cpu(); | |
8739 | ||
36c3cc42 JK |
8740 | vmx_segment_cache_clear(vmx); |
8741 | ||
cd232ad0 NHE |
8742 | vmcs12->launch_state = 1; |
8743 | ||
8744 | prepare_vmcs02(vcpu, vmcs12); | |
8745 | ||
6dfacadd JK |
8746 | if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT) |
8747 | return kvm_emulate_halt(vcpu); | |
8748 | ||
7af40ad3 JK |
8749 | vmx->nested.nested_run_pending = 1; |
8750 | ||
cd232ad0 NHE |
8751 | /* |
8752 | * Note no nested_vmx_succeed or nested_vmx_fail here. At this point | |
8753 | * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet | |
8754 | * returned as far as L1 is concerned. It will only return (and set | |
8755 | * the success flag) when L2 exits (see nested_vmx_vmexit()). | |
8756 | */ | |
8757 | return 1; | |
8758 | } | |
8759 | ||
4704d0be NHE |
8760 | /* |
8761 | * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date | |
8762 | * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK). | |
8763 | * This function returns the new value we should put in vmcs12.guest_cr0. | |
8764 | * It's not enough to just return the vmcs02 GUEST_CR0. Rather, | |
8765 | * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now | |
8766 | * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0 | |
8767 | * didn't trap the bit, because if L1 did, so would L0). | |
8768 | * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have | |
8769 | * been modified by L2, and L1 knows it. So just leave the old value of | |
8770 | * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0 | |
8771 | * isn't relevant, because if L0 traps this bit it can set it to anything. | |
8772 | * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have | |
8773 | * changed these bits, and therefore they need to be updated, but L0 | |
8774 | * didn't necessarily allow them to be changed in GUEST_CR0 - and rather | |
8775 | * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there. | |
8776 | */ | |
8777 | static inline unsigned long | |
8778 | vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12) | |
8779 | { | |
8780 | return | |
8781 | /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) | | |
8782 | /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) | | |
8783 | /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask | | |
8784 | vcpu->arch.cr0_guest_owned_bits)); | |
8785 | } | |
8786 | ||
8787 | static inline unsigned long | |
8788 | vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12) | |
8789 | { | |
8790 | return | |
8791 | /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) | | |
8792 | /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) | | |
8793 | /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask | | |
8794 | vcpu->arch.cr4_guest_owned_bits)); | |
8795 | } | |
8796 | ||
5f3d5799 JK |
8797 | static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu, |
8798 | struct vmcs12 *vmcs12) | |
8799 | { | |
8800 | u32 idt_vectoring; | |
8801 | unsigned int nr; | |
8802 | ||
851eb667 | 8803 | if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) { |
5f3d5799 JK |
8804 | nr = vcpu->arch.exception.nr; |
8805 | idt_vectoring = nr | VECTORING_INFO_VALID_MASK; | |
8806 | ||
8807 | if (kvm_exception_is_soft(nr)) { | |
8808 | vmcs12->vm_exit_instruction_len = | |
8809 | vcpu->arch.event_exit_inst_len; | |
8810 | idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION; | |
8811 | } else | |
8812 | idt_vectoring |= INTR_TYPE_HARD_EXCEPTION; | |
8813 | ||
8814 | if (vcpu->arch.exception.has_error_code) { | |
8815 | idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK; | |
8816 | vmcs12->idt_vectoring_error_code = | |
8817 | vcpu->arch.exception.error_code; | |
8818 | } | |
8819 | ||
8820 | vmcs12->idt_vectoring_info_field = idt_vectoring; | |
cd2633c5 | 8821 | } else if (vcpu->arch.nmi_injected) { |
5f3d5799 JK |
8822 | vmcs12->idt_vectoring_info_field = |
8823 | INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR; | |
8824 | } else if (vcpu->arch.interrupt.pending) { | |
8825 | nr = vcpu->arch.interrupt.nr; | |
8826 | idt_vectoring = nr | VECTORING_INFO_VALID_MASK; | |
8827 | ||
8828 | if (vcpu->arch.interrupt.soft) { | |
8829 | idt_vectoring |= INTR_TYPE_SOFT_INTR; | |
8830 | vmcs12->vm_entry_instruction_len = | |
8831 | vcpu->arch.event_exit_inst_len; | |
8832 | } else | |
8833 | idt_vectoring |= INTR_TYPE_EXT_INTR; | |
8834 | ||
8835 | vmcs12->idt_vectoring_info_field = idt_vectoring; | |
8836 | } | |
8837 | } | |
8838 | ||
b6b8a145 JK |
8839 | static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr) |
8840 | { | |
8841 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
8842 | ||
f4124500 JK |
8843 | if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) && |
8844 | vmx->nested.preemption_timer_expired) { | |
8845 | if (vmx->nested.nested_run_pending) | |
8846 | return -EBUSY; | |
8847 | nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0); | |
8848 | return 0; | |
8849 | } | |
8850 | ||
b6b8a145 | 8851 | if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) { |
220c5672 JK |
8852 | if (vmx->nested.nested_run_pending || |
8853 | vcpu->arch.interrupt.pending) | |
b6b8a145 JK |
8854 | return -EBUSY; |
8855 | nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI, | |
8856 | NMI_VECTOR | INTR_TYPE_NMI_INTR | | |
8857 | INTR_INFO_VALID_MASK, 0); | |
8858 | /* | |
8859 | * The NMI-triggered VM exit counts as injection: | |
8860 | * clear this one and block further NMIs. | |
8861 | */ | |
8862 | vcpu->arch.nmi_pending = 0; | |
8863 | vmx_set_nmi_mask(vcpu, true); | |
8864 | return 0; | |
8865 | } | |
8866 | ||
8867 | if ((kvm_cpu_has_interrupt(vcpu) || external_intr) && | |
8868 | nested_exit_on_intr(vcpu)) { | |
8869 | if (vmx->nested.nested_run_pending) | |
8870 | return -EBUSY; | |
8871 | nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0); | |
8872 | } | |
8873 | ||
8874 | return 0; | |
8875 | } | |
8876 | ||
f4124500 JK |
8877 | static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu) |
8878 | { | |
8879 | ktime_t remaining = | |
8880 | hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer); | |
8881 | u64 value; | |
8882 | ||
8883 | if (ktime_to_ns(remaining) <= 0) | |
8884 | return 0; | |
8885 | ||
8886 | value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz; | |
8887 | do_div(value, 1000000); | |
8888 | return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE; | |
8889 | } | |
8890 | ||
4704d0be NHE |
8891 | /* |
8892 | * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits | |
8893 | * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12), | |
8894 | * and this function updates it to reflect the changes to the guest state while | |
8895 | * L2 was running (and perhaps made some exits which were handled directly by L0 | |
8896 | * without going back to L1), and to reflect the exit reason. | |
8897 | * Note that we do not have to copy here all VMCS fields, just those that | |
8898 | * could have changed by the L2 guest or the exit - i.e., the guest-state and | |
8899 | * exit-information fields only. Other fields are modified by L1 with VMWRITE, | |
8900 | * which already writes to vmcs12 directly. | |
8901 | */ | |
533558bc JK |
8902 | static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12, |
8903 | u32 exit_reason, u32 exit_intr_info, | |
8904 | unsigned long exit_qualification) | |
4704d0be NHE |
8905 | { |
8906 | /* update guest state fields: */ | |
8907 | vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12); | |
8908 | vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12); | |
8909 | ||
4704d0be NHE |
8910 | vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP); |
8911 | vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP); | |
8912 | vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS); | |
8913 | ||
8914 | vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR); | |
8915 | vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR); | |
8916 | vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR); | |
8917 | vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR); | |
8918 | vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR); | |
8919 | vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR); | |
8920 | vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR); | |
8921 | vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR); | |
8922 | vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT); | |
8923 | vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT); | |
8924 | vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT); | |
8925 | vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT); | |
8926 | vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT); | |
8927 | vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT); | |
8928 | vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT); | |
8929 | vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT); | |
8930 | vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT); | |
8931 | vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT); | |
8932 | vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES); | |
8933 | vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES); | |
8934 | vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES); | |
8935 | vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES); | |
8936 | vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES); | |
8937 | vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES); | |
8938 | vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES); | |
8939 | vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES); | |
8940 | vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE); | |
8941 | vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE); | |
8942 | vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE); | |
8943 | vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE); | |
8944 | vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE); | |
8945 | vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE); | |
8946 | vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE); | |
8947 | vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE); | |
8948 | vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE); | |
8949 | vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE); | |
8950 | ||
4704d0be NHE |
8951 | vmcs12->guest_interruptibility_info = |
8952 | vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
8953 | vmcs12->guest_pending_dbg_exceptions = | |
8954 | vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS); | |
3edf1e69 JK |
8955 | if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED) |
8956 | vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT; | |
8957 | else | |
8958 | vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE; | |
4704d0be | 8959 | |
f4124500 JK |
8960 | if (nested_cpu_has_preemption_timer(vmcs12)) { |
8961 | if (vmcs12->vm_exit_controls & | |
8962 | VM_EXIT_SAVE_VMX_PREEMPTION_TIMER) | |
8963 | vmcs12->vmx_preemption_timer_value = | |
8964 | vmx_get_preemption_timer_value(vcpu); | |
8965 | hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer); | |
8966 | } | |
7854cbca | 8967 | |
3633cfc3 NHE |
8968 | /* |
8969 | * In some cases (usually, nested EPT), L2 is allowed to change its | |
8970 | * own CR3 without exiting. If it has changed it, we must keep it. | |
8971 | * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined | |
8972 | * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12. | |
8973 | * | |
8974 | * Additionally, restore L2's PDPTR to vmcs12. | |
8975 | */ | |
8976 | if (enable_ept) { | |
8977 | vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3); | |
8978 | vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0); | |
8979 | vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1); | |
8980 | vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2); | |
8981 | vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3); | |
8982 | } | |
8983 | ||
c18911a2 JK |
8984 | vmcs12->vm_entry_controls = |
8985 | (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) | | |
2961e876 | 8986 | (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE); |
c18911a2 | 8987 | |
2996fca0 JK |
8988 | if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) { |
8989 | kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7); | |
8990 | vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL); | |
8991 | } | |
8992 | ||
4704d0be NHE |
8993 | /* TODO: These cannot have changed unless we have MSR bitmaps and |
8994 | * the relevant bit asks not to trap the change */ | |
b8c07d55 | 8995 | if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT) |
4704d0be | 8996 | vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT); |
10ba54a5 JK |
8997 | if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER) |
8998 | vmcs12->guest_ia32_efer = vcpu->arch.efer; | |
4704d0be NHE |
8999 | vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS); |
9000 | vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP); | |
9001 | vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP); | |
36be0b9d PB |
9002 | if (vmx_mpx_supported()) |
9003 | vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS); | |
81dc01f7 WL |
9004 | if (nested_cpu_has_xsaves(vmcs12)) |
9005 | vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP); | |
4704d0be NHE |
9006 | |
9007 | /* update exit information fields: */ | |
9008 | ||
533558bc JK |
9009 | vmcs12->vm_exit_reason = exit_reason; |
9010 | vmcs12->exit_qualification = exit_qualification; | |
4704d0be | 9011 | |
533558bc | 9012 | vmcs12->vm_exit_intr_info = exit_intr_info; |
c0d1c770 JK |
9013 | if ((vmcs12->vm_exit_intr_info & |
9014 | (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) == | |
9015 | (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) | |
9016 | vmcs12->vm_exit_intr_error_code = | |
9017 | vmcs_read32(VM_EXIT_INTR_ERROR_CODE); | |
5f3d5799 | 9018 | vmcs12->idt_vectoring_info_field = 0; |
4704d0be NHE |
9019 | vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN); |
9020 | vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); | |
9021 | ||
5f3d5799 JK |
9022 | if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) { |
9023 | /* vm_entry_intr_info_field is cleared on exit. Emulate this | |
9024 | * instead of reading the real value. */ | |
4704d0be | 9025 | vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK; |
5f3d5799 JK |
9026 | |
9027 | /* | |
9028 | * Transfer the event that L0 or L1 may wanted to inject into | |
9029 | * L2 to IDT_VECTORING_INFO_FIELD. | |
9030 | */ | |
9031 | vmcs12_save_pending_event(vcpu, vmcs12); | |
9032 | } | |
9033 | ||
9034 | /* | |
9035 | * Drop what we picked up for L2 via vmx_complete_interrupts. It is | |
9036 | * preserved above and would only end up incorrectly in L1. | |
9037 | */ | |
9038 | vcpu->arch.nmi_injected = false; | |
9039 | kvm_clear_exception_queue(vcpu); | |
9040 | kvm_clear_interrupt_queue(vcpu); | |
4704d0be NHE |
9041 | } |
9042 | ||
9043 | /* | |
9044 | * A part of what we need to when the nested L2 guest exits and we want to | |
9045 | * run its L1 parent, is to reset L1's guest state to the host state specified | |
9046 | * in vmcs12. | |
9047 | * This function is to be called not only on normal nested exit, but also on | |
9048 | * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry | |
9049 | * Failures During or After Loading Guest State"). | |
9050 | * This function should be called when the active VMCS is L1's (vmcs01). | |
9051 | */ | |
733568f9 JK |
9052 | static void load_vmcs12_host_state(struct kvm_vcpu *vcpu, |
9053 | struct vmcs12 *vmcs12) | |
4704d0be | 9054 | { |
21feb4eb ACL |
9055 | struct kvm_segment seg; |
9056 | ||
4704d0be NHE |
9057 | if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) |
9058 | vcpu->arch.efer = vmcs12->host_ia32_efer; | |
d1fa0352 | 9059 | else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE) |
4704d0be NHE |
9060 | vcpu->arch.efer |= (EFER_LMA | EFER_LME); |
9061 | else | |
9062 | vcpu->arch.efer &= ~(EFER_LMA | EFER_LME); | |
9063 | vmx_set_efer(vcpu, vcpu->arch.efer); | |
9064 | ||
9065 | kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp); | |
9066 | kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip); | |
1adfa76a | 9067 | vmx_set_rflags(vcpu, X86_EFLAGS_FIXED); |
4704d0be NHE |
9068 | /* |
9069 | * Note that calling vmx_set_cr0 is important, even if cr0 hasn't | |
9070 | * actually changed, because it depends on the current state of | |
9071 | * fpu_active (which may have changed). | |
9072 | * Note that vmx_set_cr0 refers to efer set above. | |
9073 | */ | |
9e3e4dbf | 9074 | vmx_set_cr0(vcpu, vmcs12->host_cr0); |
4704d0be NHE |
9075 | /* |
9076 | * If we did fpu_activate()/fpu_deactivate() during L2's run, we need | |
9077 | * to apply the same changes to L1's vmcs. We just set cr0 correctly, | |
9078 | * but we also need to update cr0_guest_host_mask and exception_bitmap. | |
9079 | */ | |
9080 | update_exception_bitmap(vcpu); | |
9081 | vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0); | |
9082 | vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits); | |
9083 | ||
9084 | /* | |
9085 | * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01 | |
9086 | * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask(); | |
9087 | */ | |
9088 | vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK); | |
9089 | kvm_set_cr4(vcpu, vmcs12->host_cr4); | |
9090 | ||
29bf08f1 | 9091 | nested_ept_uninit_mmu_context(vcpu); |
155a97a3 | 9092 | |
4704d0be NHE |
9093 | kvm_set_cr3(vcpu, vmcs12->host_cr3); |
9094 | kvm_mmu_reset_context(vcpu); | |
9095 | ||
feaf0c7d GN |
9096 | if (!enable_ept) |
9097 | vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault; | |
9098 | ||
4704d0be NHE |
9099 | if (enable_vpid) { |
9100 | /* | |
9101 | * Trivially support vpid by letting L2s share their parent | |
9102 | * L1's vpid. TODO: move to a more elaborate solution, giving | |
9103 | * each L2 its own vpid and exposing the vpid feature to L1. | |
9104 | */ | |
9105 | vmx_flush_tlb(vcpu); | |
9106 | } | |
9107 | ||
9108 | ||
9109 | vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs); | |
9110 | vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp); | |
9111 | vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip); | |
9112 | vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base); | |
9113 | vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base); | |
4704d0be | 9114 | |
36be0b9d PB |
9115 | /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */ |
9116 | if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS) | |
9117 | vmcs_write64(GUEST_BNDCFGS, 0); | |
9118 | ||
44811c02 | 9119 | if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) { |
4704d0be | 9120 | vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat); |
44811c02 JK |
9121 | vcpu->arch.pat = vmcs12->host_ia32_pat; |
9122 | } | |
4704d0be NHE |
9123 | if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL) |
9124 | vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL, | |
9125 | vmcs12->host_ia32_perf_global_ctrl); | |
503cd0c5 | 9126 | |
21feb4eb ACL |
9127 | /* Set L1 segment info according to Intel SDM |
9128 | 27.5.2 Loading Host Segment and Descriptor-Table Registers */ | |
9129 | seg = (struct kvm_segment) { | |
9130 | .base = 0, | |
9131 | .limit = 0xFFFFFFFF, | |
9132 | .selector = vmcs12->host_cs_selector, | |
9133 | .type = 11, | |
9134 | .present = 1, | |
9135 | .s = 1, | |
9136 | .g = 1 | |
9137 | }; | |
9138 | if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE) | |
9139 | seg.l = 1; | |
9140 | else | |
9141 | seg.db = 1; | |
9142 | vmx_set_segment(vcpu, &seg, VCPU_SREG_CS); | |
9143 | seg = (struct kvm_segment) { | |
9144 | .base = 0, | |
9145 | .limit = 0xFFFFFFFF, | |
9146 | .type = 3, | |
9147 | .present = 1, | |
9148 | .s = 1, | |
9149 | .db = 1, | |
9150 | .g = 1 | |
9151 | }; | |
9152 | seg.selector = vmcs12->host_ds_selector; | |
9153 | vmx_set_segment(vcpu, &seg, VCPU_SREG_DS); | |
9154 | seg.selector = vmcs12->host_es_selector; | |
9155 | vmx_set_segment(vcpu, &seg, VCPU_SREG_ES); | |
9156 | seg.selector = vmcs12->host_ss_selector; | |
9157 | vmx_set_segment(vcpu, &seg, VCPU_SREG_SS); | |
9158 | seg.selector = vmcs12->host_fs_selector; | |
9159 | seg.base = vmcs12->host_fs_base; | |
9160 | vmx_set_segment(vcpu, &seg, VCPU_SREG_FS); | |
9161 | seg.selector = vmcs12->host_gs_selector; | |
9162 | seg.base = vmcs12->host_gs_base; | |
9163 | vmx_set_segment(vcpu, &seg, VCPU_SREG_GS); | |
9164 | seg = (struct kvm_segment) { | |
205befd9 | 9165 | .base = vmcs12->host_tr_base, |
21feb4eb ACL |
9166 | .limit = 0x67, |
9167 | .selector = vmcs12->host_tr_selector, | |
9168 | .type = 11, | |
9169 | .present = 1 | |
9170 | }; | |
9171 | vmx_set_segment(vcpu, &seg, VCPU_SREG_TR); | |
9172 | ||
503cd0c5 JK |
9173 | kvm_set_dr(vcpu, 7, 0x400); |
9174 | vmcs_write64(GUEST_IA32_DEBUGCTL, 0); | |
4704d0be NHE |
9175 | } |
9176 | ||
9177 | /* | |
9178 | * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1 | |
9179 | * and modify vmcs12 to make it see what it would expect to see there if | |
9180 | * L2 was its real guest. Must only be called when in L2 (is_guest_mode()) | |
9181 | */ | |
533558bc JK |
9182 | static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason, |
9183 | u32 exit_intr_info, | |
9184 | unsigned long exit_qualification) | |
4704d0be NHE |
9185 | { |
9186 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
4704d0be NHE |
9187 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); |
9188 | ||
5f3d5799 JK |
9189 | /* trying to cancel vmlaunch/vmresume is a bug */ |
9190 | WARN_ON_ONCE(vmx->nested.nested_run_pending); | |
9191 | ||
4704d0be | 9192 | leave_guest_mode(vcpu); |
533558bc JK |
9193 | prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info, |
9194 | exit_qualification); | |
4704d0be | 9195 | |
f3380ca5 WL |
9196 | vmx_load_vmcs01(vcpu); |
9197 | ||
77b0f5d6 BD |
9198 | if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT) |
9199 | && nested_exit_intr_ack_set(vcpu)) { | |
9200 | int irq = kvm_cpu_get_interrupt(vcpu); | |
9201 | WARN_ON(irq < 0); | |
9202 | vmcs12->vm_exit_intr_info = irq | | |
9203 | INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR; | |
9204 | } | |
9205 | ||
542060ea JK |
9206 | trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason, |
9207 | vmcs12->exit_qualification, | |
9208 | vmcs12->idt_vectoring_info_field, | |
9209 | vmcs12->vm_exit_intr_info, | |
9210 | vmcs12->vm_exit_intr_error_code, | |
9211 | KVM_ISA_VMX); | |
4704d0be | 9212 | |
2961e876 GN |
9213 | vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS)); |
9214 | vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS)); | |
36c3cc42 JK |
9215 | vmx_segment_cache_clear(vmx); |
9216 | ||
4704d0be NHE |
9217 | /* if no vmcs02 cache requested, remove the one we used */ |
9218 | if (VMCS02_POOL_SIZE == 0) | |
9219 | nested_free_vmcs02(vmx, vmx->nested.current_vmptr); | |
9220 | ||
9221 | load_vmcs12_host_state(vcpu, vmcs12); | |
9222 | ||
27fc51b2 | 9223 | /* Update TSC_OFFSET if TSC was changed while L2 ran */ |
4704d0be NHE |
9224 | vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset); |
9225 | ||
9226 | /* This is needed for same reason as it was needed in prepare_vmcs02 */ | |
9227 | vmx->host_rsp = 0; | |
9228 | ||
9229 | /* Unpin physical memory we referred to in vmcs02 */ | |
9230 | if (vmx->nested.apic_access_page) { | |
9231 | nested_release_page(vmx->nested.apic_access_page); | |
48d89b92 | 9232 | vmx->nested.apic_access_page = NULL; |
4704d0be | 9233 | } |
a7c0b07d WL |
9234 | if (vmx->nested.virtual_apic_page) { |
9235 | nested_release_page(vmx->nested.virtual_apic_page); | |
48d89b92 | 9236 | vmx->nested.virtual_apic_page = NULL; |
a7c0b07d | 9237 | } |
4704d0be | 9238 | |
38b99173 TC |
9239 | /* |
9240 | * We are now running in L2, mmu_notifier will force to reload the | |
9241 | * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1. | |
9242 | */ | |
9243 | kvm_vcpu_reload_apic_access_page(vcpu); | |
9244 | ||
4704d0be NHE |
9245 | /* |
9246 | * Exiting from L2 to L1, we're now back to L1 which thinks it just | |
9247 | * finished a VMLAUNCH or VMRESUME instruction, so we need to set the | |
9248 | * success or failure flag accordingly. | |
9249 | */ | |
9250 | if (unlikely(vmx->fail)) { | |
9251 | vmx->fail = 0; | |
9252 | nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR)); | |
9253 | } else | |
9254 | nested_vmx_succeed(vcpu); | |
012f83cb AG |
9255 | if (enable_shadow_vmcs) |
9256 | vmx->nested.sync_shadow_vmcs = true; | |
b6b8a145 JK |
9257 | |
9258 | /* in case we halted in L2 */ | |
9259 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; | |
4704d0be NHE |
9260 | } |
9261 | ||
42124925 JK |
9262 | /* |
9263 | * Forcibly leave nested mode in order to be able to reset the VCPU later on. | |
9264 | */ | |
9265 | static void vmx_leave_nested(struct kvm_vcpu *vcpu) | |
9266 | { | |
9267 | if (is_guest_mode(vcpu)) | |
533558bc | 9268 | nested_vmx_vmexit(vcpu, -1, 0, 0); |
42124925 JK |
9269 | free_nested(to_vmx(vcpu)); |
9270 | } | |
9271 | ||
7c177938 NHE |
9272 | /* |
9273 | * L1's failure to enter L2 is a subset of a normal exit, as explained in | |
9274 | * 23.7 "VM-entry failures during or after loading guest state" (this also | |
9275 | * lists the acceptable exit-reason and exit-qualification parameters). | |
9276 | * It should only be called before L2 actually succeeded to run, and when | |
9277 | * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss). | |
9278 | */ | |
9279 | static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu, | |
9280 | struct vmcs12 *vmcs12, | |
9281 | u32 reason, unsigned long qualification) | |
9282 | { | |
9283 | load_vmcs12_host_state(vcpu, vmcs12); | |
9284 | vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY; | |
9285 | vmcs12->exit_qualification = qualification; | |
9286 | nested_vmx_succeed(vcpu); | |
012f83cb AG |
9287 | if (enable_shadow_vmcs) |
9288 | to_vmx(vcpu)->nested.sync_shadow_vmcs = true; | |
7c177938 NHE |
9289 | } |
9290 | ||
8a76d7f2 JR |
9291 | static int vmx_check_intercept(struct kvm_vcpu *vcpu, |
9292 | struct x86_instruction_info *info, | |
9293 | enum x86_intercept_stage stage) | |
9294 | { | |
9295 | return X86EMUL_CONTINUE; | |
9296 | } | |
9297 | ||
48d89b92 | 9298 | static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu) |
ae97a3b8 | 9299 | { |
b4a2d31d RK |
9300 | if (ple_gap) |
9301 | shrink_ple_window(vcpu); | |
ae97a3b8 RK |
9302 | } |
9303 | ||
cbdd1bea | 9304 | static struct kvm_x86_ops vmx_x86_ops = { |
6aa8b732 AK |
9305 | .cpu_has_kvm_support = cpu_has_kvm_support, |
9306 | .disabled_by_bios = vmx_disabled_by_bios, | |
9307 | .hardware_setup = hardware_setup, | |
9308 | .hardware_unsetup = hardware_unsetup, | |
002c7f7c | 9309 | .check_processor_compatibility = vmx_check_processor_compat, |
6aa8b732 AK |
9310 | .hardware_enable = hardware_enable, |
9311 | .hardware_disable = hardware_disable, | |
04547156 | 9312 | .cpu_has_accelerated_tpr = report_flexpriority, |
6aa8b732 AK |
9313 | |
9314 | .vcpu_create = vmx_create_vcpu, | |
9315 | .vcpu_free = vmx_free_vcpu, | |
04d2cc77 | 9316 | .vcpu_reset = vmx_vcpu_reset, |
6aa8b732 | 9317 | |
04d2cc77 | 9318 | .prepare_guest_switch = vmx_save_host_state, |
6aa8b732 AK |
9319 | .vcpu_load = vmx_vcpu_load, |
9320 | .vcpu_put = vmx_vcpu_put, | |
9321 | ||
c8639010 | 9322 | .update_db_bp_intercept = update_exception_bitmap, |
6aa8b732 AK |
9323 | .get_msr = vmx_get_msr, |
9324 | .set_msr = vmx_set_msr, | |
9325 | .get_segment_base = vmx_get_segment_base, | |
9326 | .get_segment = vmx_get_segment, | |
9327 | .set_segment = vmx_set_segment, | |
2e4d2653 | 9328 | .get_cpl = vmx_get_cpl, |
6aa8b732 | 9329 | .get_cs_db_l_bits = vmx_get_cs_db_l_bits, |
e8467fda | 9330 | .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits, |
aff48baa | 9331 | .decache_cr3 = vmx_decache_cr3, |
25c4c276 | 9332 | .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits, |
6aa8b732 | 9333 | .set_cr0 = vmx_set_cr0, |
6aa8b732 AK |
9334 | .set_cr3 = vmx_set_cr3, |
9335 | .set_cr4 = vmx_set_cr4, | |
6aa8b732 | 9336 | .set_efer = vmx_set_efer, |
6aa8b732 AK |
9337 | .get_idt = vmx_get_idt, |
9338 | .set_idt = vmx_set_idt, | |
9339 | .get_gdt = vmx_get_gdt, | |
9340 | .set_gdt = vmx_set_gdt, | |
73aaf249 JK |
9341 | .get_dr6 = vmx_get_dr6, |
9342 | .set_dr6 = vmx_set_dr6, | |
020df079 | 9343 | .set_dr7 = vmx_set_dr7, |
81908bf4 | 9344 | .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs, |
5fdbf976 | 9345 | .cache_reg = vmx_cache_reg, |
6aa8b732 AK |
9346 | .get_rflags = vmx_get_rflags, |
9347 | .set_rflags = vmx_set_rflags, | |
02daab21 | 9348 | .fpu_deactivate = vmx_fpu_deactivate, |
6aa8b732 AK |
9349 | |
9350 | .tlb_flush = vmx_flush_tlb, | |
6aa8b732 | 9351 | |
6aa8b732 | 9352 | .run = vmx_vcpu_run, |
6062d012 | 9353 | .handle_exit = vmx_handle_exit, |
6aa8b732 | 9354 | .skip_emulated_instruction = skip_emulated_instruction, |
2809f5d2 GC |
9355 | .set_interrupt_shadow = vmx_set_interrupt_shadow, |
9356 | .get_interrupt_shadow = vmx_get_interrupt_shadow, | |
102d8325 | 9357 | .patch_hypercall = vmx_patch_hypercall, |
2a8067f1 | 9358 | .set_irq = vmx_inject_irq, |
95ba8273 | 9359 | .set_nmi = vmx_inject_nmi, |
298101da | 9360 | .queue_exception = vmx_queue_exception, |
b463a6f7 | 9361 | .cancel_injection = vmx_cancel_injection, |
78646121 | 9362 | .interrupt_allowed = vmx_interrupt_allowed, |
95ba8273 | 9363 | .nmi_allowed = vmx_nmi_allowed, |
3cfc3092 JK |
9364 | .get_nmi_mask = vmx_get_nmi_mask, |
9365 | .set_nmi_mask = vmx_set_nmi_mask, | |
95ba8273 GN |
9366 | .enable_nmi_window = enable_nmi_window, |
9367 | .enable_irq_window = enable_irq_window, | |
9368 | .update_cr8_intercept = update_cr8_intercept, | |
8d14695f | 9369 | .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode, |
38b99173 | 9370 | .set_apic_access_page_addr = vmx_set_apic_access_page_addr, |
c7c9c56c YZ |
9371 | .vm_has_apicv = vmx_vm_has_apicv, |
9372 | .load_eoi_exitmap = vmx_load_eoi_exitmap, | |
9373 | .hwapic_irr_update = vmx_hwapic_irr_update, | |
9374 | .hwapic_isr_update = vmx_hwapic_isr_update, | |
a20ed54d YZ |
9375 | .sync_pir_to_irr = vmx_sync_pir_to_irr, |
9376 | .deliver_posted_interrupt = vmx_deliver_posted_interrupt, | |
95ba8273 | 9377 | |
cbc94022 | 9378 | .set_tss_addr = vmx_set_tss_addr, |
67253af5 | 9379 | .get_tdp_level = get_ept_level, |
4b12f0de | 9380 | .get_mt_mask = vmx_get_mt_mask, |
229456fc | 9381 | |
586f9607 | 9382 | .get_exit_info = vmx_get_exit_info, |
586f9607 | 9383 | |
17cc3935 | 9384 | .get_lpage_level = vmx_get_lpage_level, |
0e851880 SY |
9385 | |
9386 | .cpuid_update = vmx_cpuid_update, | |
4e47c7a6 SY |
9387 | |
9388 | .rdtscp_supported = vmx_rdtscp_supported, | |
ad756a16 | 9389 | .invpcid_supported = vmx_invpcid_supported, |
d4330ef2 JR |
9390 | |
9391 | .set_supported_cpuid = vmx_set_supported_cpuid, | |
f5f48ee1 SY |
9392 | |
9393 | .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit, | |
99e3e30a | 9394 | |
4051b188 | 9395 | .set_tsc_khz = vmx_set_tsc_khz, |
ba904635 | 9396 | .read_tsc_offset = vmx_read_tsc_offset, |
99e3e30a | 9397 | .write_tsc_offset = vmx_write_tsc_offset, |
e48672fa | 9398 | .adjust_tsc_offset = vmx_adjust_tsc_offset, |
857e4099 | 9399 | .compute_tsc_offset = vmx_compute_tsc_offset, |
d5c1785d | 9400 | .read_l1_tsc = vmx_read_l1_tsc, |
1c97f0a0 JR |
9401 | |
9402 | .set_tdp_cr3 = vmx_set_cr3, | |
8a76d7f2 JR |
9403 | |
9404 | .check_intercept = vmx_check_intercept, | |
a547c6db | 9405 | .handle_external_intr = vmx_handle_external_intr, |
da8999d3 | 9406 | .mpx_supported = vmx_mpx_supported, |
55412b2e | 9407 | .xsaves_supported = vmx_xsaves_supported, |
b6b8a145 JK |
9408 | |
9409 | .check_nested_events = vmx_check_nested_events, | |
ae97a3b8 RK |
9410 | |
9411 | .sched_in = vmx_sched_in, | |
6aa8b732 AK |
9412 | }; |
9413 | ||
9414 | static int __init vmx_init(void) | |
9415 | { | |
34a1cd60 TC |
9416 | int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), |
9417 | __alignof__(struct vcpu_vmx), THIS_MODULE); | |
fdef3ad1 | 9418 | if (r) |
34a1cd60 | 9419 | return r; |
25c5f225 | 9420 | |
8f536b76 ZY |
9421 | #ifdef CONFIG_KEXEC |
9422 | rcu_assign_pointer(crash_vmclear_loaded_vmcss, | |
9423 | crash_vmclear_local_loaded_vmcss); | |
9424 | #endif | |
9425 | ||
fdef3ad1 | 9426 | return 0; |
6aa8b732 AK |
9427 | } |
9428 | ||
9429 | static void __exit vmx_exit(void) | |
9430 | { | |
8f536b76 | 9431 | #ifdef CONFIG_KEXEC |
3b63a43f | 9432 | RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL); |
8f536b76 ZY |
9433 | synchronize_rcu(); |
9434 | #endif | |
9435 | ||
cb498ea2 | 9436 | kvm_exit(); |
6aa8b732 AK |
9437 | } |
9438 | ||
9439 | module_init(vmx_init) | |
9440 | module_exit(vmx_exit) |