Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 8 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
9 | * |
10 | * Authors: | |
11 | * Avi Kivity <avi@qumranet.com> | |
12 | * Yaniv Kamay <yaniv@qumranet.com> | |
13 | * | |
14 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
15 | * the COPYING file in the top-level directory. | |
16 | * | |
17 | */ | |
18 | ||
85f455f7 | 19 | #include "irq.h" |
1d737c8a | 20 | #include "mmu.h" |
e495606d | 21 | |
edf88417 | 22 | #include <linux/kvm_host.h> |
6aa8b732 | 23 | #include <linux/module.h> |
9d8f549d | 24 | #include <linux/kernel.h> |
6aa8b732 AK |
25 | #include <linux/mm.h> |
26 | #include <linux/highmem.h> | |
e8edc6e0 | 27 | #include <linux/sched.h> |
c7addb90 | 28 | #include <linux/moduleparam.h> |
229456fc | 29 | #include <linux/ftrace_event.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
cafd6659 | 31 | #include <linux/tboot.h> |
5fdbf976 | 32 | #include "kvm_cache_regs.h" |
35920a35 | 33 | #include "x86.h" |
e495606d | 34 | |
6aa8b732 | 35 | #include <asm/io.h> |
3b3be0d1 | 36 | #include <asm/desc.h> |
13673a90 | 37 | #include <asm/vmx.h> |
6210e37b | 38 | #include <asm/virtext.h> |
a0861c02 | 39 | #include <asm/mce.h> |
2acf923e DC |
40 | #include <asm/i387.h> |
41 | #include <asm/xcr.h> | |
d7cd9796 | 42 | #include <asm/perf_event.h> |
6aa8b732 | 43 | |
229456fc MT |
44 | #include "trace.h" |
45 | ||
4ecac3fd | 46 | #define __ex(x) __kvm_handle_fault_on_reboot(x) |
5e520e62 AK |
47 | #define __ex_clear(x, reg) \ |
48 | ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg) | |
4ecac3fd | 49 | |
6aa8b732 AK |
50 | MODULE_AUTHOR("Qumranet"); |
51 | MODULE_LICENSE("GPL"); | |
52 | ||
4462d21a | 53 | static int __read_mostly enable_vpid = 1; |
736caefe | 54 | module_param_named(vpid, enable_vpid, bool, 0444); |
2384d2b3 | 55 | |
4462d21a | 56 | static int __read_mostly flexpriority_enabled = 1; |
736caefe | 57 | module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO); |
4c9fc8ef | 58 | |
4462d21a | 59 | static int __read_mostly enable_ept = 1; |
736caefe | 60 | module_param_named(ept, enable_ept, bool, S_IRUGO); |
d56f546d | 61 | |
3a624e29 NK |
62 | static int __read_mostly enable_unrestricted_guest = 1; |
63 | module_param_named(unrestricted_guest, | |
64 | enable_unrestricted_guest, bool, S_IRUGO); | |
65 | ||
4462d21a | 66 | static int __read_mostly emulate_invalid_guest_state = 0; |
c1f8bc04 | 67 | module_param(emulate_invalid_guest_state, bool, S_IRUGO); |
04fa4d32 | 68 | |
b923e62e DX |
69 | static int __read_mostly vmm_exclusive = 1; |
70 | module_param(vmm_exclusive, bool, S_IRUGO); | |
71 | ||
443381a8 AL |
72 | static int __read_mostly yield_on_hlt = 1; |
73 | module_param(yield_on_hlt, bool, S_IRUGO); | |
74 | ||
58fbbf26 KT |
75 | static int __read_mostly fasteoi = 1; |
76 | module_param(fasteoi, bool, S_IRUGO); | |
77 | ||
801d3424 NHE |
78 | /* |
79 | * If nested=1, nested virtualization is supported, i.e., guests may use | |
80 | * VMX and be a hypervisor for its own guests. If nested=0, guests may not | |
81 | * use VMX instructions. | |
82 | */ | |
83 | static int __read_mostly nested = 0; | |
84 | module_param(nested, bool, S_IRUGO); | |
85 | ||
cdc0e244 AK |
86 | #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \ |
87 | (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD) | |
88 | #define KVM_GUEST_CR0_MASK \ | |
89 | (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE) | |
90 | #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \ | |
81231c69 | 91 | (X86_CR0_WP | X86_CR0_NE) |
cdc0e244 AK |
92 | #define KVM_VM_CR0_ALWAYS_ON \ |
93 | (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE) | |
4c38609a AK |
94 | #define KVM_CR4_GUEST_OWNED_BITS \ |
95 | (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \ | |
96 | | X86_CR4_OSXMMEXCPT) | |
97 | ||
cdc0e244 AK |
98 | #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE) |
99 | #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE) | |
100 | ||
78ac8b47 AK |
101 | #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM)) |
102 | ||
4b8d54f9 ZE |
103 | /* |
104 | * These 2 parameters are used to config the controls for Pause-Loop Exiting: | |
105 | * ple_gap: upper bound on the amount of time between two successive | |
106 | * executions of PAUSE in a loop. Also indicate if ple enabled. | |
00c25bce | 107 | * According to test, this time is usually smaller than 128 cycles. |
4b8d54f9 ZE |
108 | * ple_window: upper bound on the amount of time a guest is allowed to execute |
109 | * in a PAUSE loop. Tests indicate that most spinlocks are held for | |
110 | * less than 2^12 cycles | |
111 | * Time is measured based on a counter that runs at the same rate as the TSC, | |
112 | * refer SDM volume 3b section 21.6.13 & 22.1.3. | |
113 | */ | |
00c25bce | 114 | #define KVM_VMX_DEFAULT_PLE_GAP 128 |
4b8d54f9 ZE |
115 | #define KVM_VMX_DEFAULT_PLE_WINDOW 4096 |
116 | static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP; | |
117 | module_param(ple_gap, int, S_IRUGO); | |
118 | ||
119 | static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW; | |
120 | module_param(ple_window, int, S_IRUGO); | |
121 | ||
8bf00a52 | 122 | #define NR_AUTOLOAD_MSRS 8 |
ff2f6fe9 | 123 | #define VMCS02_POOL_SIZE 1 |
61d2ef2c | 124 | |
a2fa3e9f GH |
125 | struct vmcs { |
126 | u32 revision_id; | |
127 | u32 abort; | |
128 | char data[0]; | |
129 | }; | |
130 | ||
d462b819 NHE |
131 | /* |
132 | * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also | |
133 | * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs | |
134 | * loaded on this CPU (so we can clear them if the CPU goes down). | |
135 | */ | |
136 | struct loaded_vmcs { | |
137 | struct vmcs *vmcs; | |
138 | int cpu; | |
139 | int launched; | |
140 | struct list_head loaded_vmcss_on_cpu_link; | |
141 | }; | |
142 | ||
26bb0981 AK |
143 | struct shared_msr_entry { |
144 | unsigned index; | |
145 | u64 data; | |
d5696725 | 146 | u64 mask; |
26bb0981 AK |
147 | }; |
148 | ||
a9d30f33 NHE |
149 | /* |
150 | * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a | |
151 | * single nested guest (L2), hence the name vmcs12. Any VMX implementation has | |
152 | * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is | |
153 | * stored in guest memory specified by VMPTRLD, but is opaque to the guest, | |
154 | * which must access it using VMREAD/VMWRITE/VMCLEAR instructions. | |
155 | * More than one of these structures may exist, if L1 runs multiple L2 guests. | |
156 | * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the | |
157 | * underlying hardware which will be used to run L2. | |
158 | * This structure is packed to ensure that its layout is identical across | |
159 | * machines (necessary for live migration). | |
160 | * If there are changes in this struct, VMCS12_REVISION must be changed. | |
161 | */ | |
22bd0358 | 162 | typedef u64 natural_width; |
a9d30f33 NHE |
163 | struct __packed vmcs12 { |
164 | /* According to the Intel spec, a VMCS region must start with the | |
165 | * following two fields. Then follow implementation-specific data. | |
166 | */ | |
167 | u32 revision_id; | |
168 | u32 abort; | |
22bd0358 | 169 | |
27d6c865 NHE |
170 | u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */ |
171 | u32 padding[7]; /* room for future expansion */ | |
172 | ||
22bd0358 NHE |
173 | u64 io_bitmap_a; |
174 | u64 io_bitmap_b; | |
175 | u64 msr_bitmap; | |
176 | u64 vm_exit_msr_store_addr; | |
177 | u64 vm_exit_msr_load_addr; | |
178 | u64 vm_entry_msr_load_addr; | |
179 | u64 tsc_offset; | |
180 | u64 virtual_apic_page_addr; | |
181 | u64 apic_access_addr; | |
182 | u64 ept_pointer; | |
183 | u64 guest_physical_address; | |
184 | u64 vmcs_link_pointer; | |
185 | u64 guest_ia32_debugctl; | |
186 | u64 guest_ia32_pat; | |
187 | u64 guest_ia32_efer; | |
188 | u64 guest_ia32_perf_global_ctrl; | |
189 | u64 guest_pdptr0; | |
190 | u64 guest_pdptr1; | |
191 | u64 guest_pdptr2; | |
192 | u64 guest_pdptr3; | |
193 | u64 host_ia32_pat; | |
194 | u64 host_ia32_efer; | |
195 | u64 host_ia32_perf_global_ctrl; | |
196 | u64 padding64[8]; /* room for future expansion */ | |
197 | /* | |
198 | * To allow migration of L1 (complete with its L2 guests) between | |
199 | * machines of different natural widths (32 or 64 bit), we cannot have | |
200 | * unsigned long fields with no explict size. We use u64 (aliased | |
201 | * natural_width) instead. Luckily, x86 is little-endian. | |
202 | */ | |
203 | natural_width cr0_guest_host_mask; | |
204 | natural_width cr4_guest_host_mask; | |
205 | natural_width cr0_read_shadow; | |
206 | natural_width cr4_read_shadow; | |
207 | natural_width cr3_target_value0; | |
208 | natural_width cr3_target_value1; | |
209 | natural_width cr3_target_value2; | |
210 | natural_width cr3_target_value3; | |
211 | natural_width exit_qualification; | |
212 | natural_width guest_linear_address; | |
213 | natural_width guest_cr0; | |
214 | natural_width guest_cr3; | |
215 | natural_width guest_cr4; | |
216 | natural_width guest_es_base; | |
217 | natural_width guest_cs_base; | |
218 | natural_width guest_ss_base; | |
219 | natural_width guest_ds_base; | |
220 | natural_width guest_fs_base; | |
221 | natural_width guest_gs_base; | |
222 | natural_width guest_ldtr_base; | |
223 | natural_width guest_tr_base; | |
224 | natural_width guest_gdtr_base; | |
225 | natural_width guest_idtr_base; | |
226 | natural_width guest_dr7; | |
227 | natural_width guest_rsp; | |
228 | natural_width guest_rip; | |
229 | natural_width guest_rflags; | |
230 | natural_width guest_pending_dbg_exceptions; | |
231 | natural_width guest_sysenter_esp; | |
232 | natural_width guest_sysenter_eip; | |
233 | natural_width host_cr0; | |
234 | natural_width host_cr3; | |
235 | natural_width host_cr4; | |
236 | natural_width host_fs_base; | |
237 | natural_width host_gs_base; | |
238 | natural_width host_tr_base; | |
239 | natural_width host_gdtr_base; | |
240 | natural_width host_idtr_base; | |
241 | natural_width host_ia32_sysenter_esp; | |
242 | natural_width host_ia32_sysenter_eip; | |
243 | natural_width host_rsp; | |
244 | natural_width host_rip; | |
245 | natural_width paddingl[8]; /* room for future expansion */ | |
246 | u32 pin_based_vm_exec_control; | |
247 | u32 cpu_based_vm_exec_control; | |
248 | u32 exception_bitmap; | |
249 | u32 page_fault_error_code_mask; | |
250 | u32 page_fault_error_code_match; | |
251 | u32 cr3_target_count; | |
252 | u32 vm_exit_controls; | |
253 | u32 vm_exit_msr_store_count; | |
254 | u32 vm_exit_msr_load_count; | |
255 | u32 vm_entry_controls; | |
256 | u32 vm_entry_msr_load_count; | |
257 | u32 vm_entry_intr_info_field; | |
258 | u32 vm_entry_exception_error_code; | |
259 | u32 vm_entry_instruction_len; | |
260 | u32 tpr_threshold; | |
261 | u32 secondary_vm_exec_control; | |
262 | u32 vm_instruction_error; | |
263 | u32 vm_exit_reason; | |
264 | u32 vm_exit_intr_info; | |
265 | u32 vm_exit_intr_error_code; | |
266 | u32 idt_vectoring_info_field; | |
267 | u32 idt_vectoring_error_code; | |
268 | u32 vm_exit_instruction_len; | |
269 | u32 vmx_instruction_info; | |
270 | u32 guest_es_limit; | |
271 | u32 guest_cs_limit; | |
272 | u32 guest_ss_limit; | |
273 | u32 guest_ds_limit; | |
274 | u32 guest_fs_limit; | |
275 | u32 guest_gs_limit; | |
276 | u32 guest_ldtr_limit; | |
277 | u32 guest_tr_limit; | |
278 | u32 guest_gdtr_limit; | |
279 | u32 guest_idtr_limit; | |
280 | u32 guest_es_ar_bytes; | |
281 | u32 guest_cs_ar_bytes; | |
282 | u32 guest_ss_ar_bytes; | |
283 | u32 guest_ds_ar_bytes; | |
284 | u32 guest_fs_ar_bytes; | |
285 | u32 guest_gs_ar_bytes; | |
286 | u32 guest_ldtr_ar_bytes; | |
287 | u32 guest_tr_ar_bytes; | |
288 | u32 guest_interruptibility_info; | |
289 | u32 guest_activity_state; | |
290 | u32 guest_sysenter_cs; | |
291 | u32 host_ia32_sysenter_cs; | |
292 | u32 padding32[8]; /* room for future expansion */ | |
293 | u16 virtual_processor_id; | |
294 | u16 guest_es_selector; | |
295 | u16 guest_cs_selector; | |
296 | u16 guest_ss_selector; | |
297 | u16 guest_ds_selector; | |
298 | u16 guest_fs_selector; | |
299 | u16 guest_gs_selector; | |
300 | u16 guest_ldtr_selector; | |
301 | u16 guest_tr_selector; | |
302 | u16 host_es_selector; | |
303 | u16 host_cs_selector; | |
304 | u16 host_ss_selector; | |
305 | u16 host_ds_selector; | |
306 | u16 host_fs_selector; | |
307 | u16 host_gs_selector; | |
308 | u16 host_tr_selector; | |
a9d30f33 NHE |
309 | }; |
310 | ||
311 | /* | |
312 | * VMCS12_REVISION is an arbitrary id that should be changed if the content or | |
313 | * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and | |
314 | * VMPTRLD verifies that the VMCS region that L1 is loading contains this id. | |
315 | */ | |
316 | #define VMCS12_REVISION 0x11e57ed0 | |
317 | ||
318 | /* | |
319 | * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region | |
320 | * and any VMCS region. Although only sizeof(struct vmcs12) are used by the | |
321 | * current implementation, 4K are reserved to avoid future complications. | |
322 | */ | |
323 | #define VMCS12_SIZE 0x1000 | |
324 | ||
ff2f6fe9 NHE |
325 | /* Used to remember the last vmcs02 used for some recently used vmcs12s */ |
326 | struct vmcs02_list { | |
327 | struct list_head list; | |
328 | gpa_t vmptr; | |
329 | struct loaded_vmcs vmcs02; | |
330 | }; | |
331 | ||
ec378aee NHE |
332 | /* |
333 | * The nested_vmx structure is part of vcpu_vmx, and holds information we need | |
334 | * for correct emulation of VMX (i.e., nested VMX) on this vcpu. | |
335 | */ | |
336 | struct nested_vmx { | |
337 | /* Has the level1 guest done vmxon? */ | |
338 | bool vmxon; | |
a9d30f33 NHE |
339 | |
340 | /* The guest-physical address of the current VMCS L1 keeps for L2 */ | |
341 | gpa_t current_vmptr; | |
342 | /* The host-usable pointer to the above */ | |
343 | struct page *current_vmcs12_page; | |
344 | struct vmcs12 *current_vmcs12; | |
ff2f6fe9 NHE |
345 | |
346 | /* vmcs02_list cache of VMCSs recently used to run L2 guests */ | |
347 | struct list_head vmcs02_pool; | |
348 | int vmcs02_num; | |
fe3ef05c | 349 | u64 vmcs01_tsc_offset; |
644d711a NHE |
350 | /* L2 must run next, and mustn't decide to exit to L1. */ |
351 | bool nested_run_pending; | |
fe3ef05c NHE |
352 | /* |
353 | * Guest pages referred to in vmcs02 with host-physical pointers, so | |
354 | * we must keep them pinned while L2 runs. | |
355 | */ | |
356 | struct page *apic_access_page; | |
ec378aee NHE |
357 | }; |
358 | ||
a2fa3e9f | 359 | struct vcpu_vmx { |
fb3f0f51 | 360 | struct kvm_vcpu vcpu; |
313dbd49 | 361 | unsigned long host_rsp; |
29bd8a78 | 362 | u8 fail; |
69c73028 | 363 | u8 cpl; |
9d58b931 | 364 | bool nmi_known_unmasked; |
51aa01d1 | 365 | u32 exit_intr_info; |
1155f76a | 366 | u32 idt_vectoring_info; |
6de12732 | 367 | ulong rflags; |
26bb0981 | 368 | struct shared_msr_entry *guest_msrs; |
a2fa3e9f GH |
369 | int nmsrs; |
370 | int save_nmsrs; | |
a2fa3e9f | 371 | #ifdef CONFIG_X86_64 |
44ea2b17 AK |
372 | u64 msr_host_kernel_gs_base; |
373 | u64 msr_guest_kernel_gs_base; | |
a2fa3e9f | 374 | #endif |
d462b819 NHE |
375 | /* |
376 | * loaded_vmcs points to the VMCS currently used in this vcpu. For a | |
377 | * non-nested (L1) guest, it always points to vmcs01. For a nested | |
378 | * guest (L2), it points to a different VMCS. | |
379 | */ | |
380 | struct loaded_vmcs vmcs01; | |
381 | struct loaded_vmcs *loaded_vmcs; | |
382 | bool __launched; /* temporary, used in vmx_vcpu_run */ | |
61d2ef2c AK |
383 | struct msr_autoload { |
384 | unsigned nr; | |
385 | struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS]; | |
386 | struct vmx_msr_entry host[NR_AUTOLOAD_MSRS]; | |
387 | } msr_autoload; | |
a2fa3e9f GH |
388 | struct { |
389 | int loaded; | |
390 | u16 fs_sel, gs_sel, ldt_sel; | |
152d3f2f LV |
391 | int gs_ldt_reload_needed; |
392 | int fs_reload_needed; | |
d77c26fc | 393 | } host_state; |
9c8cba37 | 394 | struct { |
7ffd92c5 | 395 | int vm86_active; |
78ac8b47 | 396 | ulong save_rflags; |
7ffd92c5 AK |
397 | struct kvm_save_segment { |
398 | u16 selector; | |
399 | unsigned long base; | |
400 | u32 limit; | |
401 | u32 ar; | |
402 | } tr, es, ds, fs, gs; | |
9c8cba37 | 403 | } rmode; |
2fb92db1 AK |
404 | struct { |
405 | u32 bitmask; /* 4 bits per segment (1 bit per field) */ | |
406 | struct kvm_save_segment seg[8]; | |
407 | } segment_cache; | |
2384d2b3 | 408 | int vpid; |
04fa4d32 | 409 | bool emulation_required; |
3b86cd99 JK |
410 | |
411 | /* Support for vnmi-less CPUs */ | |
412 | int soft_vnmi_blocked; | |
413 | ktime_t entry_time; | |
414 | s64 vnmi_blocked_time; | |
a0861c02 | 415 | u32 exit_reason; |
4e47c7a6 SY |
416 | |
417 | bool rdtscp_enabled; | |
ec378aee NHE |
418 | |
419 | /* Support for a guest hypervisor (nested VMX) */ | |
420 | struct nested_vmx nested; | |
a2fa3e9f GH |
421 | }; |
422 | ||
2fb92db1 AK |
423 | enum segment_cache_field { |
424 | SEG_FIELD_SEL = 0, | |
425 | SEG_FIELD_BASE = 1, | |
426 | SEG_FIELD_LIMIT = 2, | |
427 | SEG_FIELD_AR = 3, | |
428 | ||
429 | SEG_FIELD_NR = 4 | |
430 | }; | |
431 | ||
a2fa3e9f GH |
432 | static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu) |
433 | { | |
fb3f0f51 | 434 | return container_of(vcpu, struct vcpu_vmx, vcpu); |
a2fa3e9f GH |
435 | } |
436 | ||
22bd0358 NHE |
437 | #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x) |
438 | #define FIELD(number, name) [number] = VMCS12_OFFSET(name) | |
439 | #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \ | |
440 | [number##_HIGH] = VMCS12_OFFSET(name)+4 | |
441 | ||
442 | static unsigned short vmcs_field_to_offset_table[] = { | |
443 | FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id), | |
444 | FIELD(GUEST_ES_SELECTOR, guest_es_selector), | |
445 | FIELD(GUEST_CS_SELECTOR, guest_cs_selector), | |
446 | FIELD(GUEST_SS_SELECTOR, guest_ss_selector), | |
447 | FIELD(GUEST_DS_SELECTOR, guest_ds_selector), | |
448 | FIELD(GUEST_FS_SELECTOR, guest_fs_selector), | |
449 | FIELD(GUEST_GS_SELECTOR, guest_gs_selector), | |
450 | FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector), | |
451 | FIELD(GUEST_TR_SELECTOR, guest_tr_selector), | |
452 | FIELD(HOST_ES_SELECTOR, host_es_selector), | |
453 | FIELD(HOST_CS_SELECTOR, host_cs_selector), | |
454 | FIELD(HOST_SS_SELECTOR, host_ss_selector), | |
455 | FIELD(HOST_DS_SELECTOR, host_ds_selector), | |
456 | FIELD(HOST_FS_SELECTOR, host_fs_selector), | |
457 | FIELD(HOST_GS_SELECTOR, host_gs_selector), | |
458 | FIELD(HOST_TR_SELECTOR, host_tr_selector), | |
459 | FIELD64(IO_BITMAP_A, io_bitmap_a), | |
460 | FIELD64(IO_BITMAP_B, io_bitmap_b), | |
461 | FIELD64(MSR_BITMAP, msr_bitmap), | |
462 | FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr), | |
463 | FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr), | |
464 | FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr), | |
465 | FIELD64(TSC_OFFSET, tsc_offset), | |
466 | FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr), | |
467 | FIELD64(APIC_ACCESS_ADDR, apic_access_addr), | |
468 | FIELD64(EPT_POINTER, ept_pointer), | |
469 | FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address), | |
470 | FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer), | |
471 | FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl), | |
472 | FIELD64(GUEST_IA32_PAT, guest_ia32_pat), | |
473 | FIELD64(GUEST_IA32_EFER, guest_ia32_efer), | |
474 | FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl), | |
475 | FIELD64(GUEST_PDPTR0, guest_pdptr0), | |
476 | FIELD64(GUEST_PDPTR1, guest_pdptr1), | |
477 | FIELD64(GUEST_PDPTR2, guest_pdptr2), | |
478 | FIELD64(GUEST_PDPTR3, guest_pdptr3), | |
479 | FIELD64(HOST_IA32_PAT, host_ia32_pat), | |
480 | FIELD64(HOST_IA32_EFER, host_ia32_efer), | |
481 | FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl), | |
482 | FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control), | |
483 | FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control), | |
484 | FIELD(EXCEPTION_BITMAP, exception_bitmap), | |
485 | FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask), | |
486 | FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match), | |
487 | FIELD(CR3_TARGET_COUNT, cr3_target_count), | |
488 | FIELD(VM_EXIT_CONTROLS, vm_exit_controls), | |
489 | FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count), | |
490 | FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count), | |
491 | FIELD(VM_ENTRY_CONTROLS, vm_entry_controls), | |
492 | FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count), | |
493 | FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field), | |
494 | FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code), | |
495 | FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len), | |
496 | FIELD(TPR_THRESHOLD, tpr_threshold), | |
497 | FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control), | |
498 | FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error), | |
499 | FIELD(VM_EXIT_REASON, vm_exit_reason), | |
500 | FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info), | |
501 | FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code), | |
502 | FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field), | |
503 | FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code), | |
504 | FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len), | |
505 | FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info), | |
506 | FIELD(GUEST_ES_LIMIT, guest_es_limit), | |
507 | FIELD(GUEST_CS_LIMIT, guest_cs_limit), | |
508 | FIELD(GUEST_SS_LIMIT, guest_ss_limit), | |
509 | FIELD(GUEST_DS_LIMIT, guest_ds_limit), | |
510 | FIELD(GUEST_FS_LIMIT, guest_fs_limit), | |
511 | FIELD(GUEST_GS_LIMIT, guest_gs_limit), | |
512 | FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit), | |
513 | FIELD(GUEST_TR_LIMIT, guest_tr_limit), | |
514 | FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit), | |
515 | FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit), | |
516 | FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes), | |
517 | FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes), | |
518 | FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes), | |
519 | FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes), | |
520 | FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes), | |
521 | FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes), | |
522 | FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes), | |
523 | FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes), | |
524 | FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info), | |
525 | FIELD(GUEST_ACTIVITY_STATE, guest_activity_state), | |
526 | FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs), | |
527 | FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs), | |
528 | FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask), | |
529 | FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask), | |
530 | FIELD(CR0_READ_SHADOW, cr0_read_shadow), | |
531 | FIELD(CR4_READ_SHADOW, cr4_read_shadow), | |
532 | FIELD(CR3_TARGET_VALUE0, cr3_target_value0), | |
533 | FIELD(CR3_TARGET_VALUE1, cr3_target_value1), | |
534 | FIELD(CR3_TARGET_VALUE2, cr3_target_value2), | |
535 | FIELD(CR3_TARGET_VALUE3, cr3_target_value3), | |
536 | FIELD(EXIT_QUALIFICATION, exit_qualification), | |
537 | FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address), | |
538 | FIELD(GUEST_CR0, guest_cr0), | |
539 | FIELD(GUEST_CR3, guest_cr3), | |
540 | FIELD(GUEST_CR4, guest_cr4), | |
541 | FIELD(GUEST_ES_BASE, guest_es_base), | |
542 | FIELD(GUEST_CS_BASE, guest_cs_base), | |
543 | FIELD(GUEST_SS_BASE, guest_ss_base), | |
544 | FIELD(GUEST_DS_BASE, guest_ds_base), | |
545 | FIELD(GUEST_FS_BASE, guest_fs_base), | |
546 | FIELD(GUEST_GS_BASE, guest_gs_base), | |
547 | FIELD(GUEST_LDTR_BASE, guest_ldtr_base), | |
548 | FIELD(GUEST_TR_BASE, guest_tr_base), | |
549 | FIELD(GUEST_GDTR_BASE, guest_gdtr_base), | |
550 | FIELD(GUEST_IDTR_BASE, guest_idtr_base), | |
551 | FIELD(GUEST_DR7, guest_dr7), | |
552 | FIELD(GUEST_RSP, guest_rsp), | |
553 | FIELD(GUEST_RIP, guest_rip), | |
554 | FIELD(GUEST_RFLAGS, guest_rflags), | |
555 | FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions), | |
556 | FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp), | |
557 | FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip), | |
558 | FIELD(HOST_CR0, host_cr0), | |
559 | FIELD(HOST_CR3, host_cr3), | |
560 | FIELD(HOST_CR4, host_cr4), | |
561 | FIELD(HOST_FS_BASE, host_fs_base), | |
562 | FIELD(HOST_GS_BASE, host_gs_base), | |
563 | FIELD(HOST_TR_BASE, host_tr_base), | |
564 | FIELD(HOST_GDTR_BASE, host_gdtr_base), | |
565 | FIELD(HOST_IDTR_BASE, host_idtr_base), | |
566 | FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp), | |
567 | FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip), | |
568 | FIELD(HOST_RSP, host_rsp), | |
569 | FIELD(HOST_RIP, host_rip), | |
570 | }; | |
571 | static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table); | |
572 | ||
573 | static inline short vmcs_field_to_offset(unsigned long field) | |
574 | { | |
575 | if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0) | |
576 | return -1; | |
577 | return vmcs_field_to_offset_table[field]; | |
578 | } | |
579 | ||
a9d30f33 NHE |
580 | static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu) |
581 | { | |
582 | return to_vmx(vcpu)->nested.current_vmcs12; | |
583 | } | |
584 | ||
585 | static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr) | |
586 | { | |
587 | struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT); | |
588 | if (is_error_page(page)) { | |
589 | kvm_release_page_clean(page); | |
590 | return NULL; | |
591 | } | |
592 | return page; | |
593 | } | |
594 | ||
595 | static void nested_release_page(struct page *page) | |
596 | { | |
597 | kvm_release_page_dirty(page); | |
598 | } | |
599 | ||
600 | static void nested_release_page_clean(struct page *page) | |
601 | { | |
602 | kvm_release_page_clean(page); | |
603 | } | |
604 | ||
4e1096d2 | 605 | static u64 construct_eptp(unsigned long root_hpa); |
4610c9cc DX |
606 | static void kvm_cpu_vmxon(u64 addr); |
607 | static void kvm_cpu_vmxoff(void); | |
aff48baa | 608 | static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3); |
776e58ea | 609 | static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr); |
75880a01 | 610 | |
6aa8b732 AK |
611 | static DEFINE_PER_CPU(struct vmcs *, vmxarea); |
612 | static DEFINE_PER_CPU(struct vmcs *, current_vmcs); | |
d462b819 NHE |
613 | /* |
614 | * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed | |
615 | * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it. | |
616 | */ | |
617 | static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu); | |
3444d7da | 618 | static DEFINE_PER_CPU(struct desc_ptr, host_gdt); |
6aa8b732 | 619 | |
3e7c73e9 AK |
620 | static unsigned long *vmx_io_bitmap_a; |
621 | static unsigned long *vmx_io_bitmap_b; | |
5897297b AK |
622 | static unsigned long *vmx_msr_bitmap_legacy; |
623 | static unsigned long *vmx_msr_bitmap_longmode; | |
fdef3ad1 | 624 | |
110312c8 | 625 | static bool cpu_has_load_ia32_efer; |
8bf00a52 | 626 | static bool cpu_has_load_perf_global_ctrl; |
110312c8 | 627 | |
2384d2b3 SY |
628 | static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS); |
629 | static DEFINE_SPINLOCK(vmx_vpid_lock); | |
630 | ||
1c3d14fe | 631 | static struct vmcs_config { |
6aa8b732 AK |
632 | int size; |
633 | int order; | |
634 | u32 revision_id; | |
1c3d14fe YS |
635 | u32 pin_based_exec_ctrl; |
636 | u32 cpu_based_exec_ctrl; | |
f78e0e2e | 637 | u32 cpu_based_2nd_exec_ctrl; |
1c3d14fe YS |
638 | u32 vmexit_ctrl; |
639 | u32 vmentry_ctrl; | |
640 | } vmcs_config; | |
6aa8b732 | 641 | |
efff9e53 | 642 | static struct vmx_capability { |
d56f546d SY |
643 | u32 ept; |
644 | u32 vpid; | |
645 | } vmx_capability; | |
646 | ||
6aa8b732 AK |
647 | #define VMX_SEGMENT_FIELD(seg) \ |
648 | [VCPU_SREG_##seg] = { \ | |
649 | .selector = GUEST_##seg##_SELECTOR, \ | |
650 | .base = GUEST_##seg##_BASE, \ | |
651 | .limit = GUEST_##seg##_LIMIT, \ | |
652 | .ar_bytes = GUEST_##seg##_AR_BYTES, \ | |
653 | } | |
654 | ||
655 | static struct kvm_vmx_segment_field { | |
656 | unsigned selector; | |
657 | unsigned base; | |
658 | unsigned limit; | |
659 | unsigned ar_bytes; | |
660 | } kvm_vmx_segment_fields[] = { | |
661 | VMX_SEGMENT_FIELD(CS), | |
662 | VMX_SEGMENT_FIELD(DS), | |
663 | VMX_SEGMENT_FIELD(ES), | |
664 | VMX_SEGMENT_FIELD(FS), | |
665 | VMX_SEGMENT_FIELD(GS), | |
666 | VMX_SEGMENT_FIELD(SS), | |
667 | VMX_SEGMENT_FIELD(TR), | |
668 | VMX_SEGMENT_FIELD(LDTR), | |
669 | }; | |
670 | ||
26bb0981 AK |
671 | static u64 host_efer; |
672 | ||
6de4f3ad AK |
673 | static void ept_save_pdptrs(struct kvm_vcpu *vcpu); |
674 | ||
4d56c8a7 | 675 | /* |
8c06585d | 676 | * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it |
4d56c8a7 AK |
677 | * away by decrementing the array size. |
678 | */ | |
6aa8b732 | 679 | static const u32 vmx_msr_index[] = { |
05b3e0c2 | 680 | #ifdef CONFIG_X86_64 |
44ea2b17 | 681 | MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, |
6aa8b732 | 682 | #endif |
8c06585d | 683 | MSR_EFER, MSR_TSC_AUX, MSR_STAR, |
6aa8b732 | 684 | }; |
9d8f549d | 685 | #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index) |
6aa8b732 | 686 | |
31299944 | 687 | static inline bool is_page_fault(u32 intr_info) |
6aa8b732 AK |
688 | { |
689 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
690 | INTR_INFO_VALID_MASK)) == | |
8ab2d2e2 | 691 | (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK); |
6aa8b732 AK |
692 | } |
693 | ||
31299944 | 694 | static inline bool is_no_device(u32 intr_info) |
2ab455cc AL |
695 | { |
696 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
697 | INTR_INFO_VALID_MASK)) == | |
8ab2d2e2 | 698 | (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK); |
2ab455cc AL |
699 | } |
700 | ||
31299944 | 701 | static inline bool is_invalid_opcode(u32 intr_info) |
7aa81cc0 AL |
702 | { |
703 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
704 | INTR_INFO_VALID_MASK)) == | |
8ab2d2e2 | 705 | (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK); |
7aa81cc0 AL |
706 | } |
707 | ||
31299944 | 708 | static inline bool is_external_interrupt(u32 intr_info) |
6aa8b732 AK |
709 | { |
710 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK)) | |
711 | == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK); | |
712 | } | |
713 | ||
31299944 | 714 | static inline bool is_machine_check(u32 intr_info) |
a0861c02 AK |
715 | { |
716 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
717 | INTR_INFO_VALID_MASK)) == | |
718 | (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK); | |
719 | } | |
720 | ||
31299944 | 721 | static inline bool cpu_has_vmx_msr_bitmap(void) |
25c5f225 | 722 | { |
04547156 | 723 | return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS; |
25c5f225 SY |
724 | } |
725 | ||
31299944 | 726 | static inline bool cpu_has_vmx_tpr_shadow(void) |
6e5d865c | 727 | { |
04547156 | 728 | return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW; |
6e5d865c YS |
729 | } |
730 | ||
31299944 | 731 | static inline bool vm_need_tpr_shadow(struct kvm *kvm) |
6e5d865c | 732 | { |
04547156 | 733 | return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm)); |
6e5d865c YS |
734 | } |
735 | ||
31299944 | 736 | static inline bool cpu_has_secondary_exec_ctrls(void) |
f78e0e2e | 737 | { |
04547156 SY |
738 | return vmcs_config.cpu_based_exec_ctrl & |
739 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; | |
f78e0e2e SY |
740 | } |
741 | ||
774ead3a | 742 | static inline bool cpu_has_vmx_virtualize_apic_accesses(void) |
f78e0e2e | 743 | { |
04547156 SY |
744 | return vmcs_config.cpu_based_2nd_exec_ctrl & |
745 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
746 | } | |
747 | ||
748 | static inline bool cpu_has_vmx_flexpriority(void) | |
749 | { | |
750 | return cpu_has_vmx_tpr_shadow() && | |
751 | cpu_has_vmx_virtualize_apic_accesses(); | |
f78e0e2e SY |
752 | } |
753 | ||
e799794e MT |
754 | static inline bool cpu_has_vmx_ept_execute_only(void) |
755 | { | |
31299944 | 756 | return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT; |
e799794e MT |
757 | } |
758 | ||
759 | static inline bool cpu_has_vmx_eptp_uncacheable(void) | |
760 | { | |
31299944 | 761 | return vmx_capability.ept & VMX_EPTP_UC_BIT; |
e799794e MT |
762 | } |
763 | ||
764 | static inline bool cpu_has_vmx_eptp_writeback(void) | |
765 | { | |
31299944 | 766 | return vmx_capability.ept & VMX_EPTP_WB_BIT; |
e799794e MT |
767 | } |
768 | ||
769 | static inline bool cpu_has_vmx_ept_2m_page(void) | |
770 | { | |
31299944 | 771 | return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT; |
e799794e MT |
772 | } |
773 | ||
878403b7 SY |
774 | static inline bool cpu_has_vmx_ept_1g_page(void) |
775 | { | |
31299944 | 776 | return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT; |
878403b7 SY |
777 | } |
778 | ||
4bc9b982 SY |
779 | static inline bool cpu_has_vmx_ept_4levels(void) |
780 | { | |
781 | return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT; | |
782 | } | |
783 | ||
31299944 | 784 | static inline bool cpu_has_vmx_invept_individual_addr(void) |
d56f546d | 785 | { |
31299944 | 786 | return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT; |
d56f546d SY |
787 | } |
788 | ||
31299944 | 789 | static inline bool cpu_has_vmx_invept_context(void) |
d56f546d | 790 | { |
31299944 | 791 | return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT; |
d56f546d SY |
792 | } |
793 | ||
31299944 | 794 | static inline bool cpu_has_vmx_invept_global(void) |
d56f546d | 795 | { |
31299944 | 796 | return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT; |
d56f546d SY |
797 | } |
798 | ||
518c8aee GJ |
799 | static inline bool cpu_has_vmx_invvpid_single(void) |
800 | { | |
801 | return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT; | |
802 | } | |
803 | ||
b9d762fa GJ |
804 | static inline bool cpu_has_vmx_invvpid_global(void) |
805 | { | |
806 | return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT; | |
807 | } | |
808 | ||
31299944 | 809 | static inline bool cpu_has_vmx_ept(void) |
d56f546d | 810 | { |
04547156 SY |
811 | return vmcs_config.cpu_based_2nd_exec_ctrl & |
812 | SECONDARY_EXEC_ENABLE_EPT; | |
d56f546d SY |
813 | } |
814 | ||
31299944 | 815 | static inline bool cpu_has_vmx_unrestricted_guest(void) |
3a624e29 NK |
816 | { |
817 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
818 | SECONDARY_EXEC_UNRESTRICTED_GUEST; | |
819 | } | |
820 | ||
31299944 | 821 | static inline bool cpu_has_vmx_ple(void) |
4b8d54f9 ZE |
822 | { |
823 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
824 | SECONDARY_EXEC_PAUSE_LOOP_EXITING; | |
825 | } | |
826 | ||
31299944 | 827 | static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm) |
f78e0e2e | 828 | { |
6d3e435e | 829 | return flexpriority_enabled && irqchip_in_kernel(kvm); |
f78e0e2e SY |
830 | } |
831 | ||
31299944 | 832 | static inline bool cpu_has_vmx_vpid(void) |
2384d2b3 | 833 | { |
04547156 SY |
834 | return vmcs_config.cpu_based_2nd_exec_ctrl & |
835 | SECONDARY_EXEC_ENABLE_VPID; | |
2384d2b3 SY |
836 | } |
837 | ||
31299944 | 838 | static inline bool cpu_has_vmx_rdtscp(void) |
4e47c7a6 SY |
839 | { |
840 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
841 | SECONDARY_EXEC_RDTSCP; | |
842 | } | |
843 | ||
31299944 | 844 | static inline bool cpu_has_virtual_nmis(void) |
f08864b4 SY |
845 | { |
846 | return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS; | |
847 | } | |
848 | ||
f5f48ee1 SY |
849 | static inline bool cpu_has_vmx_wbinvd_exit(void) |
850 | { | |
851 | return vmcs_config.cpu_based_2nd_exec_ctrl & | |
852 | SECONDARY_EXEC_WBINVD_EXITING; | |
853 | } | |
854 | ||
04547156 SY |
855 | static inline bool report_flexpriority(void) |
856 | { | |
857 | return flexpriority_enabled; | |
858 | } | |
859 | ||
fe3ef05c NHE |
860 | static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit) |
861 | { | |
862 | return vmcs12->cpu_based_vm_exec_control & bit; | |
863 | } | |
864 | ||
865 | static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit) | |
866 | { | |
867 | return (vmcs12->cpu_based_vm_exec_control & | |
868 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) && | |
869 | (vmcs12->secondary_vm_exec_control & bit); | |
870 | } | |
871 | ||
644d711a NHE |
872 | static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12, |
873 | struct kvm_vcpu *vcpu) | |
874 | { | |
875 | return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS; | |
876 | } | |
877 | ||
878 | static inline bool is_exception(u32 intr_info) | |
879 | { | |
880 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK)) | |
881 | == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK); | |
882 | } | |
883 | ||
884 | static void nested_vmx_vmexit(struct kvm_vcpu *vcpu); | |
7c177938 NHE |
885 | static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu, |
886 | struct vmcs12 *vmcs12, | |
887 | u32 reason, unsigned long qualification); | |
888 | ||
8b9cf98c | 889 | static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr) |
7725f0ba AK |
890 | { |
891 | int i; | |
892 | ||
a2fa3e9f | 893 | for (i = 0; i < vmx->nmsrs; ++i) |
26bb0981 | 894 | if (vmx_msr_index[vmx->guest_msrs[i].index] == msr) |
a75beee6 ED |
895 | return i; |
896 | return -1; | |
897 | } | |
898 | ||
2384d2b3 SY |
899 | static inline void __invvpid(int ext, u16 vpid, gva_t gva) |
900 | { | |
901 | struct { | |
902 | u64 vpid : 16; | |
903 | u64 rsvd : 48; | |
904 | u64 gva; | |
905 | } operand = { vpid, 0, gva }; | |
906 | ||
4ecac3fd | 907 | asm volatile (__ex(ASM_VMX_INVVPID) |
2384d2b3 SY |
908 | /* CF==1 or ZF==1 --> rc = -1 */ |
909 | "; ja 1f ; ud2 ; 1:" | |
910 | : : "a"(&operand), "c"(ext) : "cc", "memory"); | |
911 | } | |
912 | ||
1439442c SY |
913 | static inline void __invept(int ext, u64 eptp, gpa_t gpa) |
914 | { | |
915 | struct { | |
916 | u64 eptp, gpa; | |
917 | } operand = {eptp, gpa}; | |
918 | ||
4ecac3fd | 919 | asm volatile (__ex(ASM_VMX_INVEPT) |
1439442c SY |
920 | /* CF==1 or ZF==1 --> rc = -1 */ |
921 | "; ja 1f ; ud2 ; 1:\n" | |
922 | : : "a" (&operand), "c" (ext) : "cc", "memory"); | |
923 | } | |
924 | ||
26bb0981 | 925 | static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr) |
a75beee6 ED |
926 | { |
927 | int i; | |
928 | ||
8b9cf98c | 929 | i = __find_msr_index(vmx, msr); |
a75beee6 | 930 | if (i >= 0) |
a2fa3e9f | 931 | return &vmx->guest_msrs[i]; |
8b6d44c7 | 932 | return NULL; |
7725f0ba AK |
933 | } |
934 | ||
6aa8b732 AK |
935 | static void vmcs_clear(struct vmcs *vmcs) |
936 | { | |
937 | u64 phys_addr = __pa(vmcs); | |
938 | u8 error; | |
939 | ||
4ecac3fd | 940 | asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0" |
16d8f72f | 941 | : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr) |
6aa8b732 AK |
942 | : "cc", "memory"); |
943 | if (error) | |
944 | printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n", | |
945 | vmcs, phys_addr); | |
946 | } | |
947 | ||
d462b819 NHE |
948 | static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs) |
949 | { | |
950 | vmcs_clear(loaded_vmcs->vmcs); | |
951 | loaded_vmcs->cpu = -1; | |
952 | loaded_vmcs->launched = 0; | |
953 | } | |
954 | ||
7725b894 DX |
955 | static void vmcs_load(struct vmcs *vmcs) |
956 | { | |
957 | u64 phys_addr = __pa(vmcs); | |
958 | u8 error; | |
959 | ||
960 | asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0" | |
16d8f72f | 961 | : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr) |
7725b894 DX |
962 | : "cc", "memory"); |
963 | if (error) | |
2844d849 | 964 | printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n", |
7725b894 DX |
965 | vmcs, phys_addr); |
966 | } | |
967 | ||
d462b819 | 968 | static void __loaded_vmcs_clear(void *arg) |
6aa8b732 | 969 | { |
d462b819 | 970 | struct loaded_vmcs *loaded_vmcs = arg; |
d3b2c338 | 971 | int cpu = raw_smp_processor_id(); |
6aa8b732 | 972 | |
d462b819 NHE |
973 | if (loaded_vmcs->cpu != cpu) |
974 | return; /* vcpu migration can race with cpu offline */ | |
975 | if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs) | |
6aa8b732 | 976 | per_cpu(current_vmcs, cpu) = NULL; |
d462b819 NHE |
977 | list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link); |
978 | loaded_vmcs_init(loaded_vmcs); | |
6aa8b732 AK |
979 | } |
980 | ||
d462b819 | 981 | static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs) |
8d0be2b3 | 982 | { |
d462b819 NHE |
983 | if (loaded_vmcs->cpu != -1) |
984 | smp_call_function_single( | |
985 | loaded_vmcs->cpu, __loaded_vmcs_clear, loaded_vmcs, 1); | |
8d0be2b3 AK |
986 | } |
987 | ||
1760dd49 | 988 | static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx) |
2384d2b3 SY |
989 | { |
990 | if (vmx->vpid == 0) | |
991 | return; | |
992 | ||
518c8aee GJ |
993 | if (cpu_has_vmx_invvpid_single()) |
994 | __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0); | |
2384d2b3 SY |
995 | } |
996 | ||
b9d762fa GJ |
997 | static inline void vpid_sync_vcpu_global(void) |
998 | { | |
999 | if (cpu_has_vmx_invvpid_global()) | |
1000 | __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0); | |
1001 | } | |
1002 | ||
1003 | static inline void vpid_sync_context(struct vcpu_vmx *vmx) | |
1004 | { | |
1005 | if (cpu_has_vmx_invvpid_single()) | |
1760dd49 | 1006 | vpid_sync_vcpu_single(vmx); |
b9d762fa GJ |
1007 | else |
1008 | vpid_sync_vcpu_global(); | |
1009 | } | |
1010 | ||
1439442c SY |
1011 | static inline void ept_sync_global(void) |
1012 | { | |
1013 | if (cpu_has_vmx_invept_global()) | |
1014 | __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0); | |
1015 | } | |
1016 | ||
1017 | static inline void ept_sync_context(u64 eptp) | |
1018 | { | |
089d034e | 1019 | if (enable_ept) { |
1439442c SY |
1020 | if (cpu_has_vmx_invept_context()) |
1021 | __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0); | |
1022 | else | |
1023 | ept_sync_global(); | |
1024 | } | |
1025 | } | |
1026 | ||
1027 | static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa) | |
1028 | { | |
089d034e | 1029 | if (enable_ept) { |
1439442c SY |
1030 | if (cpu_has_vmx_invept_individual_addr()) |
1031 | __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR, | |
1032 | eptp, gpa); | |
1033 | else | |
1034 | ept_sync_context(eptp); | |
1035 | } | |
1036 | } | |
1037 | ||
96304217 | 1038 | static __always_inline unsigned long vmcs_readl(unsigned long field) |
6aa8b732 | 1039 | { |
5e520e62 | 1040 | unsigned long value; |
6aa8b732 | 1041 | |
5e520e62 AK |
1042 | asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0") |
1043 | : "=a"(value) : "d"(field) : "cc"); | |
6aa8b732 AK |
1044 | return value; |
1045 | } | |
1046 | ||
96304217 | 1047 | static __always_inline u16 vmcs_read16(unsigned long field) |
6aa8b732 AK |
1048 | { |
1049 | return vmcs_readl(field); | |
1050 | } | |
1051 | ||
96304217 | 1052 | static __always_inline u32 vmcs_read32(unsigned long field) |
6aa8b732 AK |
1053 | { |
1054 | return vmcs_readl(field); | |
1055 | } | |
1056 | ||
96304217 | 1057 | static __always_inline u64 vmcs_read64(unsigned long field) |
6aa8b732 | 1058 | { |
05b3e0c2 | 1059 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
1060 | return vmcs_readl(field); |
1061 | #else | |
1062 | return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32); | |
1063 | #endif | |
1064 | } | |
1065 | ||
e52de1b8 AK |
1066 | static noinline void vmwrite_error(unsigned long field, unsigned long value) |
1067 | { | |
1068 | printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n", | |
1069 | field, value, vmcs_read32(VM_INSTRUCTION_ERROR)); | |
1070 | dump_stack(); | |
1071 | } | |
1072 | ||
6aa8b732 AK |
1073 | static void vmcs_writel(unsigned long field, unsigned long value) |
1074 | { | |
1075 | u8 error; | |
1076 | ||
4ecac3fd | 1077 | asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0" |
d77c26fc | 1078 | : "=q"(error) : "a"(value), "d"(field) : "cc"); |
e52de1b8 AK |
1079 | if (unlikely(error)) |
1080 | vmwrite_error(field, value); | |
6aa8b732 AK |
1081 | } |
1082 | ||
1083 | static void vmcs_write16(unsigned long field, u16 value) | |
1084 | { | |
1085 | vmcs_writel(field, value); | |
1086 | } | |
1087 | ||
1088 | static void vmcs_write32(unsigned long field, u32 value) | |
1089 | { | |
1090 | vmcs_writel(field, value); | |
1091 | } | |
1092 | ||
1093 | static void vmcs_write64(unsigned long field, u64 value) | |
1094 | { | |
6aa8b732 | 1095 | vmcs_writel(field, value); |
7682f2d0 | 1096 | #ifndef CONFIG_X86_64 |
6aa8b732 AK |
1097 | asm volatile (""); |
1098 | vmcs_writel(field+1, value >> 32); | |
1099 | #endif | |
1100 | } | |
1101 | ||
2ab455cc AL |
1102 | static void vmcs_clear_bits(unsigned long field, u32 mask) |
1103 | { | |
1104 | vmcs_writel(field, vmcs_readl(field) & ~mask); | |
1105 | } | |
1106 | ||
1107 | static void vmcs_set_bits(unsigned long field, u32 mask) | |
1108 | { | |
1109 | vmcs_writel(field, vmcs_readl(field) | mask); | |
1110 | } | |
1111 | ||
2fb92db1 AK |
1112 | static void vmx_segment_cache_clear(struct vcpu_vmx *vmx) |
1113 | { | |
1114 | vmx->segment_cache.bitmask = 0; | |
1115 | } | |
1116 | ||
1117 | static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg, | |
1118 | unsigned field) | |
1119 | { | |
1120 | bool ret; | |
1121 | u32 mask = 1 << (seg * SEG_FIELD_NR + field); | |
1122 | ||
1123 | if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) { | |
1124 | vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS); | |
1125 | vmx->segment_cache.bitmask = 0; | |
1126 | } | |
1127 | ret = vmx->segment_cache.bitmask & mask; | |
1128 | vmx->segment_cache.bitmask |= mask; | |
1129 | return ret; | |
1130 | } | |
1131 | ||
1132 | static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg) | |
1133 | { | |
1134 | u16 *p = &vmx->segment_cache.seg[seg].selector; | |
1135 | ||
1136 | if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL)) | |
1137 | *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector); | |
1138 | return *p; | |
1139 | } | |
1140 | ||
1141 | static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg) | |
1142 | { | |
1143 | ulong *p = &vmx->segment_cache.seg[seg].base; | |
1144 | ||
1145 | if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE)) | |
1146 | *p = vmcs_readl(kvm_vmx_segment_fields[seg].base); | |
1147 | return *p; | |
1148 | } | |
1149 | ||
1150 | static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg) | |
1151 | { | |
1152 | u32 *p = &vmx->segment_cache.seg[seg].limit; | |
1153 | ||
1154 | if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT)) | |
1155 | *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit); | |
1156 | return *p; | |
1157 | } | |
1158 | ||
1159 | static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg) | |
1160 | { | |
1161 | u32 *p = &vmx->segment_cache.seg[seg].ar; | |
1162 | ||
1163 | if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR)) | |
1164 | *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes); | |
1165 | return *p; | |
1166 | } | |
1167 | ||
abd3f2d6 AK |
1168 | static void update_exception_bitmap(struct kvm_vcpu *vcpu) |
1169 | { | |
1170 | u32 eb; | |
1171 | ||
fd7373cc JK |
1172 | eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) | |
1173 | (1u << NM_VECTOR) | (1u << DB_VECTOR); | |
1174 | if ((vcpu->guest_debug & | |
1175 | (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) == | |
1176 | (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) | |
1177 | eb |= 1u << BP_VECTOR; | |
7ffd92c5 | 1178 | if (to_vmx(vcpu)->rmode.vm86_active) |
abd3f2d6 | 1179 | eb = ~0; |
089d034e | 1180 | if (enable_ept) |
1439442c | 1181 | eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */ |
02daab21 AK |
1182 | if (vcpu->fpu_active) |
1183 | eb &= ~(1u << NM_VECTOR); | |
36cf24e0 NHE |
1184 | |
1185 | /* When we are running a nested L2 guest and L1 specified for it a | |
1186 | * certain exception bitmap, we must trap the same exceptions and pass | |
1187 | * them to L1. When running L2, we will only handle the exceptions | |
1188 | * specified above if L1 did not want them. | |
1189 | */ | |
1190 | if (is_guest_mode(vcpu)) | |
1191 | eb |= get_vmcs12(vcpu)->exception_bitmap; | |
1192 | ||
abd3f2d6 AK |
1193 | vmcs_write32(EXCEPTION_BITMAP, eb); |
1194 | } | |
1195 | ||
8bf00a52 GN |
1196 | static void clear_atomic_switch_msr_special(unsigned long entry, |
1197 | unsigned long exit) | |
1198 | { | |
1199 | vmcs_clear_bits(VM_ENTRY_CONTROLS, entry); | |
1200 | vmcs_clear_bits(VM_EXIT_CONTROLS, exit); | |
1201 | } | |
1202 | ||
61d2ef2c AK |
1203 | static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr) |
1204 | { | |
1205 | unsigned i; | |
1206 | struct msr_autoload *m = &vmx->msr_autoload; | |
1207 | ||
8bf00a52 GN |
1208 | switch (msr) { |
1209 | case MSR_EFER: | |
1210 | if (cpu_has_load_ia32_efer) { | |
1211 | clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER, | |
1212 | VM_EXIT_LOAD_IA32_EFER); | |
1213 | return; | |
1214 | } | |
1215 | break; | |
1216 | case MSR_CORE_PERF_GLOBAL_CTRL: | |
1217 | if (cpu_has_load_perf_global_ctrl) { | |
1218 | clear_atomic_switch_msr_special( | |
1219 | VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, | |
1220 | VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL); | |
1221 | return; | |
1222 | } | |
1223 | break; | |
110312c8 AK |
1224 | } |
1225 | ||
61d2ef2c AK |
1226 | for (i = 0; i < m->nr; ++i) |
1227 | if (m->guest[i].index == msr) | |
1228 | break; | |
1229 | ||
1230 | if (i == m->nr) | |
1231 | return; | |
1232 | --m->nr; | |
1233 | m->guest[i] = m->guest[m->nr]; | |
1234 | m->host[i] = m->host[m->nr]; | |
1235 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr); | |
1236 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr); | |
1237 | } | |
1238 | ||
8bf00a52 GN |
1239 | static void add_atomic_switch_msr_special(unsigned long entry, |
1240 | unsigned long exit, unsigned long guest_val_vmcs, | |
1241 | unsigned long host_val_vmcs, u64 guest_val, u64 host_val) | |
1242 | { | |
1243 | vmcs_write64(guest_val_vmcs, guest_val); | |
1244 | vmcs_write64(host_val_vmcs, host_val); | |
1245 | vmcs_set_bits(VM_ENTRY_CONTROLS, entry); | |
1246 | vmcs_set_bits(VM_EXIT_CONTROLS, exit); | |
1247 | } | |
1248 | ||
61d2ef2c AK |
1249 | static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr, |
1250 | u64 guest_val, u64 host_val) | |
1251 | { | |
1252 | unsigned i; | |
1253 | struct msr_autoload *m = &vmx->msr_autoload; | |
1254 | ||
8bf00a52 GN |
1255 | switch (msr) { |
1256 | case MSR_EFER: | |
1257 | if (cpu_has_load_ia32_efer) { | |
1258 | add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER, | |
1259 | VM_EXIT_LOAD_IA32_EFER, | |
1260 | GUEST_IA32_EFER, | |
1261 | HOST_IA32_EFER, | |
1262 | guest_val, host_val); | |
1263 | return; | |
1264 | } | |
1265 | break; | |
1266 | case MSR_CORE_PERF_GLOBAL_CTRL: | |
1267 | if (cpu_has_load_perf_global_ctrl) { | |
1268 | add_atomic_switch_msr_special( | |
1269 | VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, | |
1270 | VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, | |
1271 | GUEST_IA32_PERF_GLOBAL_CTRL, | |
1272 | HOST_IA32_PERF_GLOBAL_CTRL, | |
1273 | guest_val, host_val); | |
1274 | return; | |
1275 | } | |
1276 | break; | |
110312c8 AK |
1277 | } |
1278 | ||
61d2ef2c AK |
1279 | for (i = 0; i < m->nr; ++i) |
1280 | if (m->guest[i].index == msr) | |
1281 | break; | |
1282 | ||
1283 | if (i == m->nr) { | |
1284 | ++m->nr; | |
1285 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr); | |
1286 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr); | |
1287 | } | |
1288 | ||
1289 | m->guest[i].index = msr; | |
1290 | m->guest[i].value = guest_val; | |
1291 | m->host[i].index = msr; | |
1292 | m->host[i].value = host_val; | |
1293 | } | |
1294 | ||
33ed6329 AK |
1295 | static void reload_tss(void) |
1296 | { | |
33ed6329 AK |
1297 | /* |
1298 | * VT restores TR but not its size. Useless. | |
1299 | */ | |
d359192f | 1300 | struct desc_ptr *gdt = &__get_cpu_var(host_gdt); |
a5f61300 | 1301 | struct desc_struct *descs; |
33ed6329 | 1302 | |
d359192f | 1303 | descs = (void *)gdt->address; |
33ed6329 AK |
1304 | descs[GDT_ENTRY_TSS].type = 9; /* available TSS */ |
1305 | load_TR_desc(); | |
33ed6329 AK |
1306 | } |
1307 | ||
92c0d900 | 1308 | static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset) |
2cc51560 | 1309 | { |
3a34a881 | 1310 | u64 guest_efer; |
51c6cf66 AK |
1311 | u64 ignore_bits; |
1312 | ||
f6801dff | 1313 | guest_efer = vmx->vcpu.arch.efer; |
3a34a881 | 1314 | |
51c6cf66 AK |
1315 | /* |
1316 | * NX is emulated; LMA and LME handled by hardware; SCE meaninless | |
1317 | * outside long mode | |
1318 | */ | |
1319 | ignore_bits = EFER_NX | EFER_SCE; | |
1320 | #ifdef CONFIG_X86_64 | |
1321 | ignore_bits |= EFER_LMA | EFER_LME; | |
1322 | /* SCE is meaningful only in long mode on Intel */ | |
1323 | if (guest_efer & EFER_LMA) | |
1324 | ignore_bits &= ~(u64)EFER_SCE; | |
1325 | #endif | |
51c6cf66 AK |
1326 | guest_efer &= ~ignore_bits; |
1327 | guest_efer |= host_efer & ignore_bits; | |
26bb0981 | 1328 | vmx->guest_msrs[efer_offset].data = guest_efer; |
d5696725 | 1329 | vmx->guest_msrs[efer_offset].mask = ~ignore_bits; |
84ad33ef AK |
1330 | |
1331 | clear_atomic_switch_msr(vmx, MSR_EFER); | |
1332 | /* On ept, can't emulate nx, and must switch nx atomically */ | |
1333 | if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) { | |
1334 | guest_efer = vmx->vcpu.arch.efer; | |
1335 | if (!(guest_efer & EFER_LMA)) | |
1336 | guest_efer &= ~EFER_LME; | |
1337 | add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer); | |
1338 | return false; | |
1339 | } | |
1340 | ||
26bb0981 | 1341 | return true; |
51c6cf66 AK |
1342 | } |
1343 | ||
2d49ec72 GN |
1344 | static unsigned long segment_base(u16 selector) |
1345 | { | |
d359192f | 1346 | struct desc_ptr *gdt = &__get_cpu_var(host_gdt); |
2d49ec72 GN |
1347 | struct desc_struct *d; |
1348 | unsigned long table_base; | |
1349 | unsigned long v; | |
1350 | ||
1351 | if (!(selector & ~3)) | |
1352 | return 0; | |
1353 | ||
d359192f | 1354 | table_base = gdt->address; |
2d49ec72 GN |
1355 | |
1356 | if (selector & 4) { /* from ldt */ | |
1357 | u16 ldt_selector = kvm_read_ldt(); | |
1358 | ||
1359 | if (!(ldt_selector & ~3)) | |
1360 | return 0; | |
1361 | ||
1362 | table_base = segment_base(ldt_selector); | |
1363 | } | |
1364 | d = (struct desc_struct *)(table_base + (selector & ~7)); | |
1365 | v = get_desc_base(d); | |
1366 | #ifdef CONFIG_X86_64 | |
1367 | if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11)) | |
1368 | v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32; | |
1369 | #endif | |
1370 | return v; | |
1371 | } | |
1372 | ||
1373 | static inline unsigned long kvm_read_tr_base(void) | |
1374 | { | |
1375 | u16 tr; | |
1376 | asm("str %0" : "=g"(tr)); | |
1377 | return segment_base(tr); | |
1378 | } | |
1379 | ||
04d2cc77 | 1380 | static void vmx_save_host_state(struct kvm_vcpu *vcpu) |
33ed6329 | 1381 | { |
04d2cc77 | 1382 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
26bb0981 | 1383 | int i; |
04d2cc77 | 1384 | |
a2fa3e9f | 1385 | if (vmx->host_state.loaded) |
33ed6329 AK |
1386 | return; |
1387 | ||
a2fa3e9f | 1388 | vmx->host_state.loaded = 1; |
33ed6329 AK |
1389 | /* |
1390 | * Set host fs and gs selectors. Unfortunately, 22.2.3 does not | |
1391 | * allow segment selectors with cpl > 0 or ti == 1. | |
1392 | */ | |
d6e88aec | 1393 | vmx->host_state.ldt_sel = kvm_read_ldt(); |
152d3f2f | 1394 | vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel; |
9581d442 | 1395 | savesegment(fs, vmx->host_state.fs_sel); |
152d3f2f | 1396 | if (!(vmx->host_state.fs_sel & 7)) { |
a2fa3e9f | 1397 | vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel); |
152d3f2f LV |
1398 | vmx->host_state.fs_reload_needed = 0; |
1399 | } else { | |
33ed6329 | 1400 | vmcs_write16(HOST_FS_SELECTOR, 0); |
152d3f2f | 1401 | vmx->host_state.fs_reload_needed = 1; |
33ed6329 | 1402 | } |
9581d442 | 1403 | savesegment(gs, vmx->host_state.gs_sel); |
a2fa3e9f GH |
1404 | if (!(vmx->host_state.gs_sel & 7)) |
1405 | vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel); | |
33ed6329 AK |
1406 | else { |
1407 | vmcs_write16(HOST_GS_SELECTOR, 0); | |
152d3f2f | 1408 | vmx->host_state.gs_ldt_reload_needed = 1; |
33ed6329 AK |
1409 | } |
1410 | ||
1411 | #ifdef CONFIG_X86_64 | |
1412 | vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE)); | |
1413 | vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE)); | |
1414 | #else | |
a2fa3e9f GH |
1415 | vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel)); |
1416 | vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel)); | |
33ed6329 | 1417 | #endif |
707c0874 AK |
1418 | |
1419 | #ifdef CONFIG_X86_64 | |
c8770e7b AK |
1420 | rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base); |
1421 | if (is_long_mode(&vmx->vcpu)) | |
44ea2b17 | 1422 | wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); |
707c0874 | 1423 | #endif |
26bb0981 AK |
1424 | for (i = 0; i < vmx->save_nmsrs; ++i) |
1425 | kvm_set_shared_msr(vmx->guest_msrs[i].index, | |
d5696725 AK |
1426 | vmx->guest_msrs[i].data, |
1427 | vmx->guest_msrs[i].mask); | |
33ed6329 AK |
1428 | } |
1429 | ||
a9b21b62 | 1430 | static void __vmx_load_host_state(struct vcpu_vmx *vmx) |
33ed6329 | 1431 | { |
a2fa3e9f | 1432 | if (!vmx->host_state.loaded) |
33ed6329 AK |
1433 | return; |
1434 | ||
e1beb1d3 | 1435 | ++vmx->vcpu.stat.host_state_reload; |
a2fa3e9f | 1436 | vmx->host_state.loaded = 0; |
c8770e7b AK |
1437 | #ifdef CONFIG_X86_64 |
1438 | if (is_long_mode(&vmx->vcpu)) | |
1439 | rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); | |
1440 | #endif | |
152d3f2f | 1441 | if (vmx->host_state.gs_ldt_reload_needed) { |
d6e88aec | 1442 | kvm_load_ldt(vmx->host_state.ldt_sel); |
33ed6329 | 1443 | #ifdef CONFIG_X86_64 |
9581d442 | 1444 | load_gs_index(vmx->host_state.gs_sel); |
9581d442 AK |
1445 | #else |
1446 | loadsegment(gs, vmx->host_state.gs_sel); | |
33ed6329 | 1447 | #endif |
33ed6329 | 1448 | } |
0a77fe4c AK |
1449 | if (vmx->host_state.fs_reload_needed) |
1450 | loadsegment(fs, vmx->host_state.fs_sel); | |
152d3f2f | 1451 | reload_tss(); |
44ea2b17 | 1452 | #ifdef CONFIG_X86_64 |
c8770e7b | 1453 | wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base); |
44ea2b17 | 1454 | #endif |
1c11e713 AK |
1455 | if (current_thread_info()->status & TS_USEDFPU) |
1456 | clts(); | |
3444d7da | 1457 | load_gdt(&__get_cpu_var(host_gdt)); |
33ed6329 AK |
1458 | } |
1459 | ||
a9b21b62 AK |
1460 | static void vmx_load_host_state(struct vcpu_vmx *vmx) |
1461 | { | |
1462 | preempt_disable(); | |
1463 | __vmx_load_host_state(vmx); | |
1464 | preempt_enable(); | |
1465 | } | |
1466 | ||
6aa8b732 AK |
1467 | /* |
1468 | * Switches to specified vcpu, until a matching vcpu_put(), but assumes | |
1469 | * vcpu mutex is already taken. | |
1470 | */ | |
15ad7146 | 1471 | static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 1472 | { |
a2fa3e9f | 1473 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
4610c9cc | 1474 | u64 phys_addr = __pa(per_cpu(vmxarea, cpu)); |
6aa8b732 | 1475 | |
4610c9cc DX |
1476 | if (!vmm_exclusive) |
1477 | kvm_cpu_vmxon(phys_addr); | |
d462b819 NHE |
1478 | else if (vmx->loaded_vmcs->cpu != cpu) |
1479 | loaded_vmcs_clear(vmx->loaded_vmcs); | |
6aa8b732 | 1480 | |
d462b819 NHE |
1481 | if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) { |
1482 | per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs; | |
1483 | vmcs_load(vmx->loaded_vmcs->vmcs); | |
6aa8b732 AK |
1484 | } |
1485 | ||
d462b819 | 1486 | if (vmx->loaded_vmcs->cpu != cpu) { |
d359192f | 1487 | struct desc_ptr *gdt = &__get_cpu_var(host_gdt); |
6aa8b732 AK |
1488 | unsigned long sysenter_esp; |
1489 | ||
a8eeb04a | 1490 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
92fe13be | 1491 | local_irq_disable(); |
d462b819 NHE |
1492 | list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link, |
1493 | &per_cpu(loaded_vmcss_on_cpu, cpu)); | |
92fe13be DX |
1494 | local_irq_enable(); |
1495 | ||
6aa8b732 AK |
1496 | /* |
1497 | * Linux uses per-cpu TSS and GDT, so set these when switching | |
1498 | * processors. | |
1499 | */ | |
d6e88aec | 1500 | vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */ |
d359192f | 1501 | vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */ |
6aa8b732 AK |
1502 | |
1503 | rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp); | |
1504 | vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */ | |
d462b819 | 1505 | vmx->loaded_vmcs->cpu = cpu; |
6aa8b732 | 1506 | } |
6aa8b732 AK |
1507 | } |
1508 | ||
1509 | static void vmx_vcpu_put(struct kvm_vcpu *vcpu) | |
1510 | { | |
a9b21b62 | 1511 | __vmx_load_host_state(to_vmx(vcpu)); |
4610c9cc | 1512 | if (!vmm_exclusive) { |
d462b819 NHE |
1513 | __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs); |
1514 | vcpu->cpu = -1; | |
4610c9cc DX |
1515 | kvm_cpu_vmxoff(); |
1516 | } | |
6aa8b732 AK |
1517 | } |
1518 | ||
5fd86fcf AK |
1519 | static void vmx_fpu_activate(struct kvm_vcpu *vcpu) |
1520 | { | |
81231c69 AK |
1521 | ulong cr0; |
1522 | ||
5fd86fcf AK |
1523 | if (vcpu->fpu_active) |
1524 | return; | |
1525 | vcpu->fpu_active = 1; | |
81231c69 AK |
1526 | cr0 = vmcs_readl(GUEST_CR0); |
1527 | cr0 &= ~(X86_CR0_TS | X86_CR0_MP); | |
1528 | cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP); | |
1529 | vmcs_writel(GUEST_CR0, cr0); | |
5fd86fcf | 1530 | update_exception_bitmap(vcpu); |
edcafe3c | 1531 | vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS; |
36cf24e0 NHE |
1532 | if (is_guest_mode(vcpu)) |
1533 | vcpu->arch.cr0_guest_owned_bits &= | |
1534 | ~get_vmcs12(vcpu)->cr0_guest_host_mask; | |
edcafe3c | 1535 | vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits); |
5fd86fcf AK |
1536 | } |
1537 | ||
edcafe3c AK |
1538 | static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu); |
1539 | ||
fe3ef05c NHE |
1540 | /* |
1541 | * Return the cr0 value that a nested guest would read. This is a combination | |
1542 | * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by | |
1543 | * its hypervisor (cr0_read_shadow). | |
1544 | */ | |
1545 | static inline unsigned long nested_read_cr0(struct vmcs12 *fields) | |
1546 | { | |
1547 | return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) | | |
1548 | (fields->cr0_read_shadow & fields->cr0_guest_host_mask); | |
1549 | } | |
1550 | static inline unsigned long nested_read_cr4(struct vmcs12 *fields) | |
1551 | { | |
1552 | return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) | | |
1553 | (fields->cr4_read_shadow & fields->cr4_guest_host_mask); | |
1554 | } | |
1555 | ||
5fd86fcf AK |
1556 | static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu) |
1557 | { | |
36cf24e0 NHE |
1558 | /* Note that there is no vcpu->fpu_active = 0 here. The caller must |
1559 | * set this *before* calling this function. | |
1560 | */ | |
edcafe3c | 1561 | vmx_decache_cr0_guest_bits(vcpu); |
81231c69 | 1562 | vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP); |
5fd86fcf | 1563 | update_exception_bitmap(vcpu); |
edcafe3c AK |
1564 | vcpu->arch.cr0_guest_owned_bits = 0; |
1565 | vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits); | |
36cf24e0 NHE |
1566 | if (is_guest_mode(vcpu)) { |
1567 | /* | |
1568 | * L1's specified read shadow might not contain the TS bit, | |
1569 | * so now that we turned on shadowing of this bit, we need to | |
1570 | * set this bit of the shadow. Like in nested_vmx_run we need | |
1571 | * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet | |
1572 | * up-to-date here because we just decached cr0.TS (and we'll | |
1573 | * only update vmcs12->guest_cr0 on nested exit). | |
1574 | */ | |
1575 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
1576 | vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) | | |
1577 | (vcpu->arch.cr0 & X86_CR0_TS); | |
1578 | vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12)); | |
1579 | } else | |
1580 | vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0); | |
5fd86fcf AK |
1581 | } |
1582 | ||
6aa8b732 AK |
1583 | static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu) |
1584 | { | |
78ac8b47 | 1585 | unsigned long rflags, save_rflags; |
345dcaa8 | 1586 | |
6de12732 AK |
1587 | if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) { |
1588 | __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail); | |
1589 | rflags = vmcs_readl(GUEST_RFLAGS); | |
1590 | if (to_vmx(vcpu)->rmode.vm86_active) { | |
1591 | rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS; | |
1592 | save_rflags = to_vmx(vcpu)->rmode.save_rflags; | |
1593 | rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS; | |
1594 | } | |
1595 | to_vmx(vcpu)->rflags = rflags; | |
78ac8b47 | 1596 | } |
6de12732 | 1597 | return to_vmx(vcpu)->rflags; |
6aa8b732 AK |
1598 | } |
1599 | ||
1600 | static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
1601 | { | |
6de12732 | 1602 | __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail); |
69c73028 | 1603 | __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail); |
6de12732 | 1604 | to_vmx(vcpu)->rflags = rflags; |
78ac8b47 AK |
1605 | if (to_vmx(vcpu)->rmode.vm86_active) { |
1606 | to_vmx(vcpu)->rmode.save_rflags = rflags; | |
053de044 | 1607 | rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; |
78ac8b47 | 1608 | } |
6aa8b732 AK |
1609 | vmcs_writel(GUEST_RFLAGS, rflags); |
1610 | } | |
1611 | ||
2809f5d2 GC |
1612 | static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) |
1613 | { | |
1614 | u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
1615 | int ret = 0; | |
1616 | ||
1617 | if (interruptibility & GUEST_INTR_STATE_STI) | |
48005f64 | 1618 | ret |= KVM_X86_SHADOW_INT_STI; |
2809f5d2 | 1619 | if (interruptibility & GUEST_INTR_STATE_MOV_SS) |
48005f64 | 1620 | ret |= KVM_X86_SHADOW_INT_MOV_SS; |
2809f5d2 GC |
1621 | |
1622 | return ret & mask; | |
1623 | } | |
1624 | ||
1625 | static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) | |
1626 | { | |
1627 | u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
1628 | u32 interruptibility = interruptibility_old; | |
1629 | ||
1630 | interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS); | |
1631 | ||
48005f64 | 1632 | if (mask & KVM_X86_SHADOW_INT_MOV_SS) |
2809f5d2 | 1633 | interruptibility |= GUEST_INTR_STATE_MOV_SS; |
48005f64 | 1634 | else if (mask & KVM_X86_SHADOW_INT_STI) |
2809f5d2 GC |
1635 | interruptibility |= GUEST_INTR_STATE_STI; |
1636 | ||
1637 | if ((interruptibility != interruptibility_old)) | |
1638 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility); | |
1639 | } | |
1640 | ||
6aa8b732 AK |
1641 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) |
1642 | { | |
1643 | unsigned long rip; | |
6aa8b732 | 1644 | |
5fdbf976 | 1645 | rip = kvm_rip_read(vcpu); |
6aa8b732 | 1646 | rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN); |
5fdbf976 | 1647 | kvm_rip_write(vcpu, rip); |
6aa8b732 | 1648 | |
2809f5d2 GC |
1649 | /* skipping an emulated instruction also counts */ |
1650 | vmx_set_interrupt_shadow(vcpu, 0); | |
6aa8b732 AK |
1651 | } |
1652 | ||
443381a8 AL |
1653 | static void vmx_clear_hlt(struct kvm_vcpu *vcpu) |
1654 | { | |
1655 | /* Ensure that we clear the HLT state in the VMCS. We don't need to | |
1656 | * explicitly skip the instruction because if the HLT state is set, then | |
1657 | * the instruction is already executing and RIP has already been | |
1658 | * advanced. */ | |
1659 | if (!yield_on_hlt && | |
1660 | vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT) | |
1661 | vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE); | |
1662 | } | |
1663 | ||
0b6ac343 NHE |
1664 | /* |
1665 | * KVM wants to inject page-faults which it got to the guest. This function | |
1666 | * checks whether in a nested guest, we need to inject them to L1 or L2. | |
1667 | * This function assumes it is called with the exit reason in vmcs02 being | |
1668 | * a #PF exception (this is the only case in which KVM injects a #PF when L2 | |
1669 | * is running). | |
1670 | */ | |
1671 | static int nested_pf_handled(struct kvm_vcpu *vcpu) | |
1672 | { | |
1673 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
1674 | ||
1675 | /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */ | |
1676 | if (!(vmcs12->exception_bitmap & PF_VECTOR)) | |
1677 | return 0; | |
1678 | ||
1679 | nested_vmx_vmexit(vcpu); | |
1680 | return 1; | |
1681 | } | |
1682 | ||
298101da | 1683 | static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr, |
ce7ddec4 JR |
1684 | bool has_error_code, u32 error_code, |
1685 | bool reinject) | |
298101da | 1686 | { |
77ab6db0 | 1687 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
8ab2d2e2 | 1688 | u32 intr_info = nr | INTR_INFO_VALID_MASK; |
77ab6db0 | 1689 | |
0b6ac343 NHE |
1690 | if (nr == PF_VECTOR && is_guest_mode(vcpu) && |
1691 | nested_pf_handled(vcpu)) | |
1692 | return; | |
1693 | ||
8ab2d2e2 | 1694 | if (has_error_code) { |
77ab6db0 | 1695 | vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code); |
8ab2d2e2 JK |
1696 | intr_info |= INTR_INFO_DELIVER_CODE_MASK; |
1697 | } | |
77ab6db0 | 1698 | |
7ffd92c5 | 1699 | if (vmx->rmode.vm86_active) { |
71f9833b SH |
1700 | int inc_eip = 0; |
1701 | if (kvm_exception_is_soft(nr)) | |
1702 | inc_eip = vcpu->arch.event_exit_inst_len; | |
1703 | if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE) | |
a92601bb | 1704 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
77ab6db0 JK |
1705 | return; |
1706 | } | |
1707 | ||
66fd3f7f GN |
1708 | if (kvm_exception_is_soft(nr)) { |
1709 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, | |
1710 | vmx->vcpu.arch.event_exit_inst_len); | |
8ab2d2e2 JK |
1711 | intr_info |= INTR_TYPE_SOFT_EXCEPTION; |
1712 | } else | |
1713 | intr_info |= INTR_TYPE_HARD_EXCEPTION; | |
1714 | ||
1715 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info); | |
443381a8 | 1716 | vmx_clear_hlt(vcpu); |
298101da AK |
1717 | } |
1718 | ||
4e47c7a6 SY |
1719 | static bool vmx_rdtscp_supported(void) |
1720 | { | |
1721 | return cpu_has_vmx_rdtscp(); | |
1722 | } | |
1723 | ||
a75beee6 ED |
1724 | /* |
1725 | * Swap MSR entry in host/guest MSR entry array. | |
1726 | */ | |
8b9cf98c | 1727 | static void move_msr_up(struct vcpu_vmx *vmx, int from, int to) |
a75beee6 | 1728 | { |
26bb0981 | 1729 | struct shared_msr_entry tmp; |
a2fa3e9f GH |
1730 | |
1731 | tmp = vmx->guest_msrs[to]; | |
1732 | vmx->guest_msrs[to] = vmx->guest_msrs[from]; | |
1733 | vmx->guest_msrs[from] = tmp; | |
a75beee6 ED |
1734 | } |
1735 | ||
e38aea3e AK |
1736 | /* |
1737 | * Set up the vmcs to automatically save and restore system | |
1738 | * msrs. Don't touch the 64-bit msrs if the guest is in legacy | |
1739 | * mode, as fiddling with msrs is very expensive. | |
1740 | */ | |
8b9cf98c | 1741 | static void setup_msrs(struct vcpu_vmx *vmx) |
e38aea3e | 1742 | { |
26bb0981 | 1743 | int save_nmsrs, index; |
5897297b | 1744 | unsigned long *msr_bitmap; |
e38aea3e | 1745 | |
33f9c505 | 1746 | vmx_load_host_state(vmx); |
a75beee6 ED |
1747 | save_nmsrs = 0; |
1748 | #ifdef CONFIG_X86_64 | |
8b9cf98c | 1749 | if (is_long_mode(&vmx->vcpu)) { |
8b9cf98c | 1750 | index = __find_msr_index(vmx, MSR_SYSCALL_MASK); |
a75beee6 | 1751 | if (index >= 0) |
8b9cf98c RR |
1752 | move_msr_up(vmx, index, save_nmsrs++); |
1753 | index = __find_msr_index(vmx, MSR_LSTAR); | |
a75beee6 | 1754 | if (index >= 0) |
8b9cf98c RR |
1755 | move_msr_up(vmx, index, save_nmsrs++); |
1756 | index = __find_msr_index(vmx, MSR_CSTAR); | |
a75beee6 | 1757 | if (index >= 0) |
8b9cf98c | 1758 | move_msr_up(vmx, index, save_nmsrs++); |
4e47c7a6 SY |
1759 | index = __find_msr_index(vmx, MSR_TSC_AUX); |
1760 | if (index >= 0 && vmx->rdtscp_enabled) | |
1761 | move_msr_up(vmx, index, save_nmsrs++); | |
a75beee6 | 1762 | /* |
8c06585d | 1763 | * MSR_STAR is only needed on long mode guests, and only |
a75beee6 ED |
1764 | * if efer.sce is enabled. |
1765 | */ | |
8c06585d | 1766 | index = __find_msr_index(vmx, MSR_STAR); |
f6801dff | 1767 | if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE)) |
8b9cf98c | 1768 | move_msr_up(vmx, index, save_nmsrs++); |
a75beee6 ED |
1769 | } |
1770 | #endif | |
92c0d900 AK |
1771 | index = __find_msr_index(vmx, MSR_EFER); |
1772 | if (index >= 0 && update_transition_efer(vmx, index)) | |
26bb0981 | 1773 | move_msr_up(vmx, index, save_nmsrs++); |
e38aea3e | 1774 | |
26bb0981 | 1775 | vmx->save_nmsrs = save_nmsrs; |
5897297b AK |
1776 | |
1777 | if (cpu_has_vmx_msr_bitmap()) { | |
1778 | if (is_long_mode(&vmx->vcpu)) | |
1779 | msr_bitmap = vmx_msr_bitmap_longmode; | |
1780 | else | |
1781 | msr_bitmap = vmx_msr_bitmap_legacy; | |
1782 | ||
1783 | vmcs_write64(MSR_BITMAP, __pa(msr_bitmap)); | |
1784 | } | |
e38aea3e AK |
1785 | } |
1786 | ||
6aa8b732 AK |
1787 | /* |
1788 | * reads and returns guest's timestamp counter "register" | |
1789 | * guest_tsc = host_tsc + tsc_offset -- 21.3 | |
1790 | */ | |
1791 | static u64 guest_read_tsc(void) | |
1792 | { | |
1793 | u64 host_tsc, tsc_offset; | |
1794 | ||
1795 | rdtscll(host_tsc); | |
1796 | tsc_offset = vmcs_read64(TSC_OFFSET); | |
1797 | return host_tsc + tsc_offset; | |
1798 | } | |
1799 | ||
d5c1785d NHE |
1800 | /* |
1801 | * Like guest_read_tsc, but always returns L1's notion of the timestamp | |
1802 | * counter, even if a nested guest (L2) is currently running. | |
1803 | */ | |
1804 | u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu) | |
1805 | { | |
1806 | u64 host_tsc, tsc_offset; | |
1807 | ||
1808 | rdtscll(host_tsc); | |
1809 | tsc_offset = is_guest_mode(vcpu) ? | |
1810 | to_vmx(vcpu)->nested.vmcs01_tsc_offset : | |
1811 | vmcs_read64(TSC_OFFSET); | |
1812 | return host_tsc + tsc_offset; | |
1813 | } | |
1814 | ||
4051b188 JR |
1815 | /* |
1816 | * Empty call-back. Needs to be implemented when VMX enables the SET_TSC_KHZ | |
1817 | * ioctl. In this case the call-back should update internal vmx state to make | |
1818 | * the changes effective. | |
1819 | */ | |
1820 | static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz) | |
1821 | { | |
1822 | /* Nothing to do here */ | |
1823 | } | |
1824 | ||
6aa8b732 | 1825 | /* |
99e3e30a | 1826 | * writes 'offset' into guest's timestamp counter offset register |
6aa8b732 | 1827 | */ |
99e3e30a | 1828 | static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) |
6aa8b732 | 1829 | { |
27fc51b2 | 1830 | if (is_guest_mode(vcpu)) { |
7991825b | 1831 | /* |
27fc51b2 NHE |
1832 | * We're here if L1 chose not to trap WRMSR to TSC. According |
1833 | * to the spec, this should set L1's TSC; The offset that L1 | |
1834 | * set for L2 remains unchanged, and still needs to be added | |
1835 | * to the newly set TSC to get L2's TSC. | |
7991825b | 1836 | */ |
27fc51b2 NHE |
1837 | struct vmcs12 *vmcs12; |
1838 | to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset; | |
1839 | /* recalculate vmcs02.TSC_OFFSET: */ | |
1840 | vmcs12 = get_vmcs12(vcpu); | |
1841 | vmcs_write64(TSC_OFFSET, offset + | |
1842 | (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ? | |
1843 | vmcs12->tsc_offset : 0)); | |
1844 | } else { | |
1845 | vmcs_write64(TSC_OFFSET, offset); | |
1846 | } | |
6aa8b732 AK |
1847 | } |
1848 | ||
e48672fa ZA |
1849 | static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment) |
1850 | { | |
1851 | u64 offset = vmcs_read64(TSC_OFFSET); | |
1852 | vmcs_write64(TSC_OFFSET, offset + adjustment); | |
7991825b NHE |
1853 | if (is_guest_mode(vcpu)) { |
1854 | /* Even when running L2, the adjustment needs to apply to L1 */ | |
1855 | to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment; | |
1856 | } | |
e48672fa ZA |
1857 | } |
1858 | ||
857e4099 JR |
1859 | static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc) |
1860 | { | |
1861 | return target_tsc - native_read_tsc(); | |
1862 | } | |
1863 | ||
801d3424 NHE |
1864 | static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu) |
1865 | { | |
1866 | struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0); | |
1867 | return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31))); | |
1868 | } | |
1869 | ||
1870 | /* | |
1871 | * nested_vmx_allowed() checks whether a guest should be allowed to use VMX | |
1872 | * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for | |
1873 | * all guests if the "nested" module option is off, and can also be disabled | |
1874 | * for a single guest by disabling its VMX cpuid bit. | |
1875 | */ | |
1876 | static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu) | |
1877 | { | |
1878 | return nested && guest_cpuid_has_vmx(vcpu); | |
1879 | } | |
1880 | ||
b87a51ae NHE |
1881 | /* |
1882 | * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be | |
1883 | * returned for the various VMX controls MSRs when nested VMX is enabled. | |
1884 | * The same values should also be used to verify that vmcs12 control fields are | |
1885 | * valid during nested entry from L1 to L2. | |
1886 | * Each of these control msrs has a low and high 32-bit half: A low bit is on | |
1887 | * if the corresponding bit in the (32-bit) control field *must* be on, and a | |
1888 | * bit in the high half is on if the corresponding bit in the control field | |
1889 | * may be on. See also vmx_control_verify(). | |
1890 | * TODO: allow these variables to be modified (downgraded) by module options | |
1891 | * or other means. | |
1892 | */ | |
1893 | static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high; | |
1894 | static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high; | |
1895 | static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high; | |
1896 | static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high; | |
1897 | static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high; | |
1898 | static __init void nested_vmx_setup_ctls_msrs(void) | |
1899 | { | |
1900 | /* | |
1901 | * Note that as a general rule, the high half of the MSRs (bits in | |
1902 | * the control fields which may be 1) should be initialized by the | |
1903 | * intersection of the underlying hardware's MSR (i.e., features which | |
1904 | * can be supported) and the list of features we want to expose - | |
1905 | * because they are known to be properly supported in our code. | |
1906 | * Also, usually, the low half of the MSRs (bits which must be 1) can | |
1907 | * be set to 0, meaning that L1 may turn off any of these bits. The | |
1908 | * reason is that if one of these bits is necessary, it will appear | |
1909 | * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control | |
1910 | * fields of vmcs01 and vmcs02, will turn these bits off - and | |
1911 | * nested_vmx_exit_handled() will not pass related exits to L1. | |
1912 | * These rules have exceptions below. | |
1913 | */ | |
1914 | ||
1915 | /* pin-based controls */ | |
1916 | /* | |
1917 | * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is | |
1918 | * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR. | |
1919 | */ | |
1920 | nested_vmx_pinbased_ctls_low = 0x16 ; | |
1921 | nested_vmx_pinbased_ctls_high = 0x16 | | |
1922 | PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING | | |
1923 | PIN_BASED_VIRTUAL_NMIS; | |
1924 | ||
1925 | /* exit controls */ | |
1926 | nested_vmx_exit_ctls_low = 0; | |
b6f1250e | 1927 | /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */ |
b87a51ae NHE |
1928 | #ifdef CONFIG_X86_64 |
1929 | nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE; | |
1930 | #else | |
1931 | nested_vmx_exit_ctls_high = 0; | |
1932 | #endif | |
1933 | ||
1934 | /* entry controls */ | |
1935 | rdmsr(MSR_IA32_VMX_ENTRY_CTLS, | |
1936 | nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high); | |
1937 | nested_vmx_entry_ctls_low = 0; | |
1938 | nested_vmx_entry_ctls_high &= | |
1939 | VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE; | |
1940 | ||
1941 | /* cpu-based controls */ | |
1942 | rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, | |
1943 | nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high); | |
1944 | nested_vmx_procbased_ctls_low = 0; | |
1945 | nested_vmx_procbased_ctls_high &= | |
1946 | CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING | | |
1947 | CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING | | |
1948 | CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING | | |
1949 | CPU_BASED_CR3_STORE_EXITING | | |
1950 | #ifdef CONFIG_X86_64 | |
1951 | CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING | | |
1952 | #endif | |
1953 | CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING | | |
1954 | CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING | | |
1955 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; | |
1956 | /* | |
1957 | * We can allow some features even when not supported by the | |
1958 | * hardware. For example, L1 can specify an MSR bitmap - and we | |
1959 | * can use it to avoid exits to L1 - even when L0 runs L2 | |
1960 | * without MSR bitmaps. | |
1961 | */ | |
1962 | nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS; | |
1963 | ||
1964 | /* secondary cpu-based controls */ | |
1965 | rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2, | |
1966 | nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high); | |
1967 | nested_vmx_secondary_ctls_low = 0; | |
1968 | nested_vmx_secondary_ctls_high &= | |
1969 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
1970 | } | |
1971 | ||
1972 | static inline bool vmx_control_verify(u32 control, u32 low, u32 high) | |
1973 | { | |
1974 | /* | |
1975 | * Bits 0 in high must be 0, and bits 1 in low must be 1. | |
1976 | */ | |
1977 | return ((control & high) | low) == control; | |
1978 | } | |
1979 | ||
1980 | static inline u64 vmx_control_msr(u32 low, u32 high) | |
1981 | { | |
1982 | return low | ((u64)high << 32); | |
1983 | } | |
1984 | ||
1985 | /* | |
1986 | * If we allow our guest to use VMX instructions (i.e., nested VMX), we should | |
1987 | * also let it use VMX-specific MSRs. | |
1988 | * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a | |
1989 | * VMX-specific MSR, or 0 when we haven't (and the caller should handle it | |
1990 | * like all other MSRs). | |
1991 | */ | |
1992 | static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata) | |
1993 | { | |
1994 | if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC && | |
1995 | msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) { | |
1996 | /* | |
1997 | * According to the spec, processors which do not support VMX | |
1998 | * should throw a #GP(0) when VMX capability MSRs are read. | |
1999 | */ | |
2000 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
2001 | return 1; | |
2002 | } | |
2003 | ||
2004 | switch (msr_index) { | |
2005 | case MSR_IA32_FEATURE_CONTROL: | |
2006 | *pdata = 0; | |
2007 | break; | |
2008 | case MSR_IA32_VMX_BASIC: | |
2009 | /* | |
2010 | * This MSR reports some information about VMX support. We | |
2011 | * should return information about the VMX we emulate for the | |
2012 | * guest, and the VMCS structure we give it - not about the | |
2013 | * VMX support of the underlying hardware. | |
2014 | */ | |
2015 | *pdata = VMCS12_REVISION | | |
2016 | ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) | | |
2017 | (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT); | |
2018 | break; | |
2019 | case MSR_IA32_VMX_TRUE_PINBASED_CTLS: | |
2020 | case MSR_IA32_VMX_PINBASED_CTLS: | |
2021 | *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low, | |
2022 | nested_vmx_pinbased_ctls_high); | |
2023 | break; | |
2024 | case MSR_IA32_VMX_TRUE_PROCBASED_CTLS: | |
2025 | case MSR_IA32_VMX_PROCBASED_CTLS: | |
2026 | *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low, | |
2027 | nested_vmx_procbased_ctls_high); | |
2028 | break; | |
2029 | case MSR_IA32_VMX_TRUE_EXIT_CTLS: | |
2030 | case MSR_IA32_VMX_EXIT_CTLS: | |
2031 | *pdata = vmx_control_msr(nested_vmx_exit_ctls_low, | |
2032 | nested_vmx_exit_ctls_high); | |
2033 | break; | |
2034 | case MSR_IA32_VMX_TRUE_ENTRY_CTLS: | |
2035 | case MSR_IA32_VMX_ENTRY_CTLS: | |
2036 | *pdata = vmx_control_msr(nested_vmx_entry_ctls_low, | |
2037 | nested_vmx_entry_ctls_high); | |
2038 | break; | |
2039 | case MSR_IA32_VMX_MISC: | |
2040 | *pdata = 0; | |
2041 | break; | |
2042 | /* | |
2043 | * These MSRs specify bits which the guest must keep fixed (on or off) | |
2044 | * while L1 is in VMXON mode (in L1's root mode, or running an L2). | |
2045 | * We picked the standard core2 setting. | |
2046 | */ | |
2047 | #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE) | |
2048 | #define VMXON_CR4_ALWAYSON X86_CR4_VMXE | |
2049 | case MSR_IA32_VMX_CR0_FIXED0: | |
2050 | *pdata = VMXON_CR0_ALWAYSON; | |
2051 | break; | |
2052 | case MSR_IA32_VMX_CR0_FIXED1: | |
2053 | *pdata = -1ULL; | |
2054 | break; | |
2055 | case MSR_IA32_VMX_CR4_FIXED0: | |
2056 | *pdata = VMXON_CR4_ALWAYSON; | |
2057 | break; | |
2058 | case MSR_IA32_VMX_CR4_FIXED1: | |
2059 | *pdata = -1ULL; | |
2060 | break; | |
2061 | case MSR_IA32_VMX_VMCS_ENUM: | |
2062 | *pdata = 0x1f; | |
2063 | break; | |
2064 | case MSR_IA32_VMX_PROCBASED_CTLS2: | |
2065 | *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low, | |
2066 | nested_vmx_secondary_ctls_high); | |
2067 | break; | |
2068 | case MSR_IA32_VMX_EPT_VPID_CAP: | |
2069 | /* Currently, no nested ept or nested vpid */ | |
2070 | *pdata = 0; | |
2071 | break; | |
2072 | default: | |
2073 | return 0; | |
2074 | } | |
2075 | ||
2076 | return 1; | |
2077 | } | |
2078 | ||
2079 | static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data) | |
2080 | { | |
2081 | if (!nested_vmx_allowed(vcpu)) | |
2082 | return 0; | |
2083 | ||
2084 | if (msr_index == MSR_IA32_FEATURE_CONTROL) | |
2085 | /* TODO: the right thing. */ | |
2086 | return 1; | |
2087 | /* | |
2088 | * No need to treat VMX capability MSRs specially: If we don't handle | |
2089 | * them, handle_wrmsr will #GP(0), which is correct (they are readonly) | |
2090 | */ | |
2091 | return 0; | |
2092 | } | |
2093 | ||
6aa8b732 AK |
2094 | /* |
2095 | * Reads an msr value (of 'msr_index') into 'pdata'. | |
2096 | * Returns 0 on success, non-0 otherwise. | |
2097 | * Assumes vcpu_load() was already called. | |
2098 | */ | |
2099 | static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata) | |
2100 | { | |
2101 | u64 data; | |
26bb0981 | 2102 | struct shared_msr_entry *msr; |
6aa8b732 AK |
2103 | |
2104 | if (!pdata) { | |
2105 | printk(KERN_ERR "BUG: get_msr called with NULL pdata\n"); | |
2106 | return -EINVAL; | |
2107 | } | |
2108 | ||
2109 | switch (msr_index) { | |
05b3e0c2 | 2110 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
2111 | case MSR_FS_BASE: |
2112 | data = vmcs_readl(GUEST_FS_BASE); | |
2113 | break; | |
2114 | case MSR_GS_BASE: | |
2115 | data = vmcs_readl(GUEST_GS_BASE); | |
2116 | break; | |
44ea2b17 AK |
2117 | case MSR_KERNEL_GS_BASE: |
2118 | vmx_load_host_state(to_vmx(vcpu)); | |
2119 | data = to_vmx(vcpu)->msr_guest_kernel_gs_base; | |
2120 | break; | |
26bb0981 | 2121 | #endif |
6aa8b732 | 2122 | case MSR_EFER: |
3bab1f5d | 2123 | return kvm_get_msr_common(vcpu, msr_index, pdata); |
af24a4e4 | 2124 | case MSR_IA32_TSC: |
6aa8b732 AK |
2125 | data = guest_read_tsc(); |
2126 | break; | |
2127 | case MSR_IA32_SYSENTER_CS: | |
2128 | data = vmcs_read32(GUEST_SYSENTER_CS); | |
2129 | break; | |
2130 | case MSR_IA32_SYSENTER_EIP: | |
f5b42c33 | 2131 | data = vmcs_readl(GUEST_SYSENTER_EIP); |
6aa8b732 AK |
2132 | break; |
2133 | case MSR_IA32_SYSENTER_ESP: | |
f5b42c33 | 2134 | data = vmcs_readl(GUEST_SYSENTER_ESP); |
6aa8b732 | 2135 | break; |
4e47c7a6 SY |
2136 | case MSR_TSC_AUX: |
2137 | if (!to_vmx(vcpu)->rdtscp_enabled) | |
2138 | return 1; | |
2139 | /* Otherwise falls through */ | |
6aa8b732 | 2140 | default: |
26bb0981 | 2141 | vmx_load_host_state(to_vmx(vcpu)); |
b87a51ae NHE |
2142 | if (vmx_get_vmx_msr(vcpu, msr_index, pdata)) |
2143 | return 0; | |
8b9cf98c | 2144 | msr = find_msr_entry(to_vmx(vcpu), msr_index); |
3bab1f5d | 2145 | if (msr) { |
542423b0 | 2146 | vmx_load_host_state(to_vmx(vcpu)); |
3bab1f5d AK |
2147 | data = msr->data; |
2148 | break; | |
6aa8b732 | 2149 | } |
3bab1f5d | 2150 | return kvm_get_msr_common(vcpu, msr_index, pdata); |
6aa8b732 AK |
2151 | } |
2152 | ||
2153 | *pdata = data; | |
2154 | return 0; | |
2155 | } | |
2156 | ||
2157 | /* | |
2158 | * Writes msr value into into the appropriate "register". | |
2159 | * Returns 0 on success, non-0 otherwise. | |
2160 | * Assumes vcpu_load() was already called. | |
2161 | */ | |
2162 | static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data) | |
2163 | { | |
a2fa3e9f | 2164 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
26bb0981 | 2165 | struct shared_msr_entry *msr; |
2cc51560 ED |
2166 | int ret = 0; |
2167 | ||
6aa8b732 | 2168 | switch (msr_index) { |
3bab1f5d | 2169 | case MSR_EFER: |
a9b21b62 | 2170 | vmx_load_host_state(vmx); |
2cc51560 | 2171 | ret = kvm_set_msr_common(vcpu, msr_index, data); |
2cc51560 | 2172 | break; |
16175a79 | 2173 | #ifdef CONFIG_X86_64 |
6aa8b732 | 2174 | case MSR_FS_BASE: |
2fb92db1 | 2175 | vmx_segment_cache_clear(vmx); |
6aa8b732 AK |
2176 | vmcs_writel(GUEST_FS_BASE, data); |
2177 | break; | |
2178 | case MSR_GS_BASE: | |
2fb92db1 | 2179 | vmx_segment_cache_clear(vmx); |
6aa8b732 AK |
2180 | vmcs_writel(GUEST_GS_BASE, data); |
2181 | break; | |
44ea2b17 AK |
2182 | case MSR_KERNEL_GS_BASE: |
2183 | vmx_load_host_state(vmx); | |
2184 | vmx->msr_guest_kernel_gs_base = data; | |
2185 | break; | |
6aa8b732 AK |
2186 | #endif |
2187 | case MSR_IA32_SYSENTER_CS: | |
2188 | vmcs_write32(GUEST_SYSENTER_CS, data); | |
2189 | break; | |
2190 | case MSR_IA32_SYSENTER_EIP: | |
f5b42c33 | 2191 | vmcs_writel(GUEST_SYSENTER_EIP, data); |
6aa8b732 AK |
2192 | break; |
2193 | case MSR_IA32_SYSENTER_ESP: | |
f5b42c33 | 2194 | vmcs_writel(GUEST_SYSENTER_ESP, data); |
6aa8b732 | 2195 | break; |
af24a4e4 | 2196 | case MSR_IA32_TSC: |
99e3e30a | 2197 | kvm_write_tsc(vcpu, data); |
6aa8b732 | 2198 | break; |
468d472f SY |
2199 | case MSR_IA32_CR_PAT: |
2200 | if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) { | |
2201 | vmcs_write64(GUEST_IA32_PAT, data); | |
2202 | vcpu->arch.pat = data; | |
2203 | break; | |
2204 | } | |
4e47c7a6 SY |
2205 | ret = kvm_set_msr_common(vcpu, msr_index, data); |
2206 | break; | |
2207 | case MSR_TSC_AUX: | |
2208 | if (!vmx->rdtscp_enabled) | |
2209 | return 1; | |
2210 | /* Check reserved bit, higher 32 bits should be zero */ | |
2211 | if ((data >> 32) != 0) | |
2212 | return 1; | |
2213 | /* Otherwise falls through */ | |
6aa8b732 | 2214 | default: |
b87a51ae NHE |
2215 | if (vmx_set_vmx_msr(vcpu, msr_index, data)) |
2216 | break; | |
8b9cf98c | 2217 | msr = find_msr_entry(vmx, msr_index); |
3bab1f5d | 2218 | if (msr) { |
542423b0 | 2219 | vmx_load_host_state(vmx); |
3bab1f5d AK |
2220 | msr->data = data; |
2221 | break; | |
6aa8b732 | 2222 | } |
2cc51560 | 2223 | ret = kvm_set_msr_common(vcpu, msr_index, data); |
6aa8b732 AK |
2224 | } |
2225 | ||
2cc51560 | 2226 | return ret; |
6aa8b732 AK |
2227 | } |
2228 | ||
5fdbf976 | 2229 | static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) |
6aa8b732 | 2230 | { |
5fdbf976 MT |
2231 | __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail); |
2232 | switch (reg) { | |
2233 | case VCPU_REGS_RSP: | |
2234 | vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP); | |
2235 | break; | |
2236 | case VCPU_REGS_RIP: | |
2237 | vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP); | |
2238 | break; | |
6de4f3ad AK |
2239 | case VCPU_EXREG_PDPTR: |
2240 | if (enable_ept) | |
2241 | ept_save_pdptrs(vcpu); | |
2242 | break; | |
5fdbf976 MT |
2243 | default: |
2244 | break; | |
2245 | } | |
6aa8b732 AK |
2246 | } |
2247 | ||
355be0b9 | 2248 | static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg) |
6aa8b732 | 2249 | { |
ae675ef0 JK |
2250 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) |
2251 | vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]); | |
2252 | else | |
2253 | vmcs_writel(GUEST_DR7, vcpu->arch.dr7); | |
2254 | ||
abd3f2d6 | 2255 | update_exception_bitmap(vcpu); |
6aa8b732 AK |
2256 | } |
2257 | ||
2258 | static __init int cpu_has_kvm_support(void) | |
2259 | { | |
6210e37b | 2260 | return cpu_has_vmx(); |
6aa8b732 AK |
2261 | } |
2262 | ||
2263 | static __init int vmx_disabled_by_bios(void) | |
2264 | { | |
2265 | u64 msr; | |
2266 | ||
2267 | rdmsrl(MSR_IA32_FEATURE_CONTROL, msr); | |
cafd6659 | 2268 | if (msr & FEATURE_CONTROL_LOCKED) { |
23f3e991 | 2269 | /* launched w/ TXT and VMX disabled */ |
cafd6659 SW |
2270 | if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX) |
2271 | && tboot_enabled()) | |
2272 | return 1; | |
23f3e991 | 2273 | /* launched w/o TXT and VMX only enabled w/ TXT */ |
cafd6659 | 2274 | if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX) |
23f3e991 | 2275 | && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX) |
f9335afe SW |
2276 | && !tboot_enabled()) { |
2277 | printk(KERN_WARNING "kvm: disable TXT in the BIOS or " | |
23f3e991 | 2278 | "activate TXT before enabling KVM\n"); |
cafd6659 | 2279 | return 1; |
f9335afe | 2280 | } |
23f3e991 JC |
2281 | /* launched w/o TXT and VMX disabled */ |
2282 | if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX) | |
2283 | && !tboot_enabled()) | |
2284 | return 1; | |
cafd6659 SW |
2285 | } |
2286 | ||
2287 | return 0; | |
6aa8b732 AK |
2288 | } |
2289 | ||
7725b894 DX |
2290 | static void kvm_cpu_vmxon(u64 addr) |
2291 | { | |
2292 | asm volatile (ASM_VMX_VMXON_RAX | |
2293 | : : "a"(&addr), "m"(addr) | |
2294 | : "memory", "cc"); | |
2295 | } | |
2296 | ||
10474ae8 | 2297 | static int hardware_enable(void *garbage) |
6aa8b732 AK |
2298 | { |
2299 | int cpu = raw_smp_processor_id(); | |
2300 | u64 phys_addr = __pa(per_cpu(vmxarea, cpu)); | |
cafd6659 | 2301 | u64 old, test_bits; |
6aa8b732 | 2302 | |
10474ae8 AG |
2303 | if (read_cr4() & X86_CR4_VMXE) |
2304 | return -EBUSY; | |
2305 | ||
d462b819 | 2306 | INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu)); |
6aa8b732 | 2307 | rdmsrl(MSR_IA32_FEATURE_CONTROL, old); |
cafd6659 SW |
2308 | |
2309 | test_bits = FEATURE_CONTROL_LOCKED; | |
2310 | test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; | |
2311 | if (tboot_enabled()) | |
2312 | test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX; | |
2313 | ||
2314 | if ((old & test_bits) != test_bits) { | |
6aa8b732 | 2315 | /* enable and lock */ |
cafd6659 SW |
2316 | wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits); |
2317 | } | |
66aee91a | 2318 | write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */ |
10474ae8 | 2319 | |
4610c9cc DX |
2320 | if (vmm_exclusive) { |
2321 | kvm_cpu_vmxon(phys_addr); | |
2322 | ept_sync_global(); | |
2323 | } | |
10474ae8 | 2324 | |
3444d7da AK |
2325 | store_gdt(&__get_cpu_var(host_gdt)); |
2326 | ||
10474ae8 | 2327 | return 0; |
6aa8b732 AK |
2328 | } |
2329 | ||
d462b819 | 2330 | static void vmclear_local_loaded_vmcss(void) |
543e4243 AK |
2331 | { |
2332 | int cpu = raw_smp_processor_id(); | |
d462b819 | 2333 | struct loaded_vmcs *v, *n; |
543e4243 | 2334 | |
d462b819 NHE |
2335 | list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu), |
2336 | loaded_vmcss_on_cpu_link) | |
2337 | __loaded_vmcs_clear(v); | |
543e4243 AK |
2338 | } |
2339 | ||
710ff4a8 EH |
2340 | |
2341 | /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot() | |
2342 | * tricks. | |
2343 | */ | |
2344 | static void kvm_cpu_vmxoff(void) | |
6aa8b732 | 2345 | { |
4ecac3fd | 2346 | asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc"); |
6aa8b732 AK |
2347 | } |
2348 | ||
710ff4a8 EH |
2349 | static void hardware_disable(void *garbage) |
2350 | { | |
4610c9cc | 2351 | if (vmm_exclusive) { |
d462b819 | 2352 | vmclear_local_loaded_vmcss(); |
4610c9cc DX |
2353 | kvm_cpu_vmxoff(); |
2354 | } | |
7725b894 | 2355 | write_cr4(read_cr4() & ~X86_CR4_VMXE); |
710ff4a8 EH |
2356 | } |
2357 | ||
1c3d14fe | 2358 | static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt, |
d77c26fc | 2359 | u32 msr, u32 *result) |
1c3d14fe YS |
2360 | { |
2361 | u32 vmx_msr_low, vmx_msr_high; | |
2362 | u32 ctl = ctl_min | ctl_opt; | |
2363 | ||
2364 | rdmsr(msr, vmx_msr_low, vmx_msr_high); | |
2365 | ||
2366 | ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */ | |
2367 | ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */ | |
2368 | ||
2369 | /* Ensure minimum (required) set of control bits are supported. */ | |
2370 | if (ctl_min & ~ctl) | |
002c7f7c | 2371 | return -EIO; |
1c3d14fe YS |
2372 | |
2373 | *result = ctl; | |
2374 | return 0; | |
2375 | } | |
2376 | ||
110312c8 AK |
2377 | static __init bool allow_1_setting(u32 msr, u32 ctl) |
2378 | { | |
2379 | u32 vmx_msr_low, vmx_msr_high; | |
2380 | ||
2381 | rdmsr(msr, vmx_msr_low, vmx_msr_high); | |
2382 | return vmx_msr_high & ctl; | |
2383 | } | |
2384 | ||
002c7f7c | 2385 | static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf) |
6aa8b732 AK |
2386 | { |
2387 | u32 vmx_msr_low, vmx_msr_high; | |
d56f546d | 2388 | u32 min, opt, min2, opt2; |
1c3d14fe YS |
2389 | u32 _pin_based_exec_control = 0; |
2390 | u32 _cpu_based_exec_control = 0; | |
f78e0e2e | 2391 | u32 _cpu_based_2nd_exec_control = 0; |
1c3d14fe YS |
2392 | u32 _vmexit_control = 0; |
2393 | u32 _vmentry_control = 0; | |
2394 | ||
2395 | min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING; | |
f08864b4 | 2396 | opt = PIN_BASED_VIRTUAL_NMIS; |
1c3d14fe YS |
2397 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS, |
2398 | &_pin_based_exec_control) < 0) | |
002c7f7c | 2399 | return -EIO; |
1c3d14fe | 2400 | |
443381a8 | 2401 | min = |
1c3d14fe YS |
2402 | #ifdef CONFIG_X86_64 |
2403 | CPU_BASED_CR8_LOAD_EXITING | | |
2404 | CPU_BASED_CR8_STORE_EXITING | | |
2405 | #endif | |
d56f546d SY |
2406 | CPU_BASED_CR3_LOAD_EXITING | |
2407 | CPU_BASED_CR3_STORE_EXITING | | |
1c3d14fe YS |
2408 | CPU_BASED_USE_IO_BITMAPS | |
2409 | CPU_BASED_MOV_DR_EXITING | | |
a7052897 | 2410 | CPU_BASED_USE_TSC_OFFSETING | |
59708670 SY |
2411 | CPU_BASED_MWAIT_EXITING | |
2412 | CPU_BASED_MONITOR_EXITING | | |
a7052897 | 2413 | CPU_BASED_INVLPG_EXITING; |
443381a8 AL |
2414 | |
2415 | if (yield_on_hlt) | |
2416 | min |= CPU_BASED_HLT_EXITING; | |
2417 | ||
f78e0e2e | 2418 | opt = CPU_BASED_TPR_SHADOW | |
25c5f225 | 2419 | CPU_BASED_USE_MSR_BITMAPS | |
f78e0e2e | 2420 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; |
1c3d14fe YS |
2421 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS, |
2422 | &_cpu_based_exec_control) < 0) | |
002c7f7c | 2423 | return -EIO; |
6e5d865c YS |
2424 | #ifdef CONFIG_X86_64 |
2425 | if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) | |
2426 | _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING & | |
2427 | ~CPU_BASED_CR8_STORE_EXITING; | |
2428 | #endif | |
f78e0e2e | 2429 | if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) { |
d56f546d SY |
2430 | min2 = 0; |
2431 | opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | | |
2384d2b3 | 2432 | SECONDARY_EXEC_WBINVD_EXITING | |
d56f546d | 2433 | SECONDARY_EXEC_ENABLE_VPID | |
3a624e29 | 2434 | SECONDARY_EXEC_ENABLE_EPT | |
4b8d54f9 | 2435 | SECONDARY_EXEC_UNRESTRICTED_GUEST | |
4e47c7a6 SY |
2436 | SECONDARY_EXEC_PAUSE_LOOP_EXITING | |
2437 | SECONDARY_EXEC_RDTSCP; | |
d56f546d SY |
2438 | if (adjust_vmx_controls(min2, opt2, |
2439 | MSR_IA32_VMX_PROCBASED_CTLS2, | |
f78e0e2e SY |
2440 | &_cpu_based_2nd_exec_control) < 0) |
2441 | return -EIO; | |
2442 | } | |
2443 | #ifndef CONFIG_X86_64 | |
2444 | if (!(_cpu_based_2nd_exec_control & | |
2445 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) | |
2446 | _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW; | |
2447 | #endif | |
d56f546d | 2448 | if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) { |
a7052897 MT |
2449 | /* CR3 accesses and invlpg don't need to cause VM Exits when EPT |
2450 | enabled */ | |
5fff7d27 GN |
2451 | _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING | |
2452 | CPU_BASED_CR3_STORE_EXITING | | |
2453 | CPU_BASED_INVLPG_EXITING); | |
d56f546d SY |
2454 | rdmsr(MSR_IA32_VMX_EPT_VPID_CAP, |
2455 | vmx_capability.ept, vmx_capability.vpid); | |
2456 | } | |
1c3d14fe YS |
2457 | |
2458 | min = 0; | |
2459 | #ifdef CONFIG_X86_64 | |
2460 | min |= VM_EXIT_HOST_ADDR_SPACE_SIZE; | |
2461 | #endif | |
468d472f | 2462 | opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT; |
1c3d14fe YS |
2463 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS, |
2464 | &_vmexit_control) < 0) | |
002c7f7c | 2465 | return -EIO; |
1c3d14fe | 2466 | |
468d472f SY |
2467 | min = 0; |
2468 | opt = VM_ENTRY_LOAD_IA32_PAT; | |
1c3d14fe YS |
2469 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS, |
2470 | &_vmentry_control) < 0) | |
002c7f7c | 2471 | return -EIO; |
6aa8b732 | 2472 | |
c68876fd | 2473 | rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high); |
1c3d14fe YS |
2474 | |
2475 | /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */ | |
2476 | if ((vmx_msr_high & 0x1fff) > PAGE_SIZE) | |
002c7f7c | 2477 | return -EIO; |
1c3d14fe YS |
2478 | |
2479 | #ifdef CONFIG_X86_64 | |
2480 | /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */ | |
2481 | if (vmx_msr_high & (1u<<16)) | |
002c7f7c | 2482 | return -EIO; |
1c3d14fe YS |
2483 | #endif |
2484 | ||
2485 | /* Require Write-Back (WB) memory type for VMCS accesses. */ | |
2486 | if (((vmx_msr_high >> 18) & 15) != 6) | |
002c7f7c | 2487 | return -EIO; |
1c3d14fe | 2488 | |
002c7f7c YS |
2489 | vmcs_conf->size = vmx_msr_high & 0x1fff; |
2490 | vmcs_conf->order = get_order(vmcs_config.size); | |
2491 | vmcs_conf->revision_id = vmx_msr_low; | |
1c3d14fe | 2492 | |
002c7f7c YS |
2493 | vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control; |
2494 | vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control; | |
f78e0e2e | 2495 | vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control; |
002c7f7c YS |
2496 | vmcs_conf->vmexit_ctrl = _vmexit_control; |
2497 | vmcs_conf->vmentry_ctrl = _vmentry_control; | |
1c3d14fe | 2498 | |
110312c8 AK |
2499 | cpu_has_load_ia32_efer = |
2500 | allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS, | |
2501 | VM_ENTRY_LOAD_IA32_EFER) | |
2502 | && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS, | |
2503 | VM_EXIT_LOAD_IA32_EFER); | |
2504 | ||
8bf00a52 GN |
2505 | cpu_has_load_perf_global_ctrl = |
2506 | allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS, | |
2507 | VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) | |
2508 | && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS, | |
2509 | VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL); | |
2510 | ||
2511 | /* | |
2512 | * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL | |
2513 | * but due to arrata below it can't be used. Workaround is to use | |
2514 | * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL. | |
2515 | * | |
2516 | * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32] | |
2517 | * | |
2518 | * AAK155 (model 26) | |
2519 | * AAP115 (model 30) | |
2520 | * AAT100 (model 37) | |
2521 | * BC86,AAY89,BD102 (model 44) | |
2522 | * BA97 (model 46) | |
2523 | * | |
2524 | */ | |
2525 | if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) { | |
2526 | switch (boot_cpu_data.x86_model) { | |
2527 | case 26: | |
2528 | case 30: | |
2529 | case 37: | |
2530 | case 44: | |
2531 | case 46: | |
2532 | cpu_has_load_perf_global_ctrl = false; | |
2533 | printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL " | |
2534 | "does not work properly. Using workaround\n"); | |
2535 | break; | |
2536 | default: | |
2537 | break; | |
2538 | } | |
2539 | } | |
2540 | ||
1c3d14fe | 2541 | return 0; |
c68876fd | 2542 | } |
6aa8b732 AK |
2543 | |
2544 | static struct vmcs *alloc_vmcs_cpu(int cpu) | |
2545 | { | |
2546 | int node = cpu_to_node(cpu); | |
2547 | struct page *pages; | |
2548 | struct vmcs *vmcs; | |
2549 | ||
6484eb3e | 2550 | pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order); |
6aa8b732 AK |
2551 | if (!pages) |
2552 | return NULL; | |
2553 | vmcs = page_address(pages); | |
1c3d14fe YS |
2554 | memset(vmcs, 0, vmcs_config.size); |
2555 | vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */ | |
6aa8b732 AK |
2556 | return vmcs; |
2557 | } | |
2558 | ||
2559 | static struct vmcs *alloc_vmcs(void) | |
2560 | { | |
d3b2c338 | 2561 | return alloc_vmcs_cpu(raw_smp_processor_id()); |
6aa8b732 AK |
2562 | } |
2563 | ||
2564 | static void free_vmcs(struct vmcs *vmcs) | |
2565 | { | |
1c3d14fe | 2566 | free_pages((unsigned long)vmcs, vmcs_config.order); |
6aa8b732 AK |
2567 | } |
2568 | ||
d462b819 NHE |
2569 | /* |
2570 | * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded | |
2571 | */ | |
2572 | static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs) | |
2573 | { | |
2574 | if (!loaded_vmcs->vmcs) | |
2575 | return; | |
2576 | loaded_vmcs_clear(loaded_vmcs); | |
2577 | free_vmcs(loaded_vmcs->vmcs); | |
2578 | loaded_vmcs->vmcs = NULL; | |
2579 | } | |
2580 | ||
39959588 | 2581 | static void free_kvm_area(void) |
6aa8b732 AK |
2582 | { |
2583 | int cpu; | |
2584 | ||
3230bb47 | 2585 | for_each_possible_cpu(cpu) { |
6aa8b732 | 2586 | free_vmcs(per_cpu(vmxarea, cpu)); |
3230bb47 ZA |
2587 | per_cpu(vmxarea, cpu) = NULL; |
2588 | } | |
6aa8b732 AK |
2589 | } |
2590 | ||
6aa8b732 AK |
2591 | static __init int alloc_kvm_area(void) |
2592 | { | |
2593 | int cpu; | |
2594 | ||
3230bb47 | 2595 | for_each_possible_cpu(cpu) { |
6aa8b732 AK |
2596 | struct vmcs *vmcs; |
2597 | ||
2598 | vmcs = alloc_vmcs_cpu(cpu); | |
2599 | if (!vmcs) { | |
2600 | free_kvm_area(); | |
2601 | return -ENOMEM; | |
2602 | } | |
2603 | ||
2604 | per_cpu(vmxarea, cpu) = vmcs; | |
2605 | } | |
2606 | return 0; | |
2607 | } | |
2608 | ||
2609 | static __init int hardware_setup(void) | |
2610 | { | |
002c7f7c YS |
2611 | if (setup_vmcs_config(&vmcs_config) < 0) |
2612 | return -EIO; | |
50a37eb4 JR |
2613 | |
2614 | if (boot_cpu_has(X86_FEATURE_NX)) | |
2615 | kvm_enable_efer_bits(EFER_NX); | |
2616 | ||
93ba03c2 SY |
2617 | if (!cpu_has_vmx_vpid()) |
2618 | enable_vpid = 0; | |
2619 | ||
4bc9b982 SY |
2620 | if (!cpu_has_vmx_ept() || |
2621 | !cpu_has_vmx_ept_4levels()) { | |
93ba03c2 | 2622 | enable_ept = 0; |
3a624e29 NK |
2623 | enable_unrestricted_guest = 0; |
2624 | } | |
2625 | ||
2626 | if (!cpu_has_vmx_unrestricted_guest()) | |
2627 | enable_unrestricted_guest = 0; | |
93ba03c2 SY |
2628 | |
2629 | if (!cpu_has_vmx_flexpriority()) | |
2630 | flexpriority_enabled = 0; | |
2631 | ||
95ba8273 GN |
2632 | if (!cpu_has_vmx_tpr_shadow()) |
2633 | kvm_x86_ops->update_cr8_intercept = NULL; | |
2634 | ||
54dee993 MT |
2635 | if (enable_ept && !cpu_has_vmx_ept_2m_page()) |
2636 | kvm_disable_largepages(); | |
2637 | ||
4b8d54f9 ZE |
2638 | if (!cpu_has_vmx_ple()) |
2639 | ple_gap = 0; | |
2640 | ||
b87a51ae NHE |
2641 | if (nested) |
2642 | nested_vmx_setup_ctls_msrs(); | |
2643 | ||
6aa8b732 AK |
2644 | return alloc_kvm_area(); |
2645 | } | |
2646 | ||
2647 | static __exit void hardware_unsetup(void) | |
2648 | { | |
2649 | free_kvm_area(); | |
2650 | } | |
2651 | ||
6aa8b732 AK |
2652 | static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save) |
2653 | { | |
2654 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
2655 | ||
6af11b9e | 2656 | if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) { |
6aa8b732 AK |
2657 | vmcs_write16(sf->selector, save->selector); |
2658 | vmcs_writel(sf->base, save->base); | |
2659 | vmcs_write32(sf->limit, save->limit); | |
2660 | vmcs_write32(sf->ar_bytes, save->ar); | |
2661 | } else { | |
2662 | u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK) | |
2663 | << AR_DPL_SHIFT; | |
2664 | vmcs_write32(sf->ar_bytes, 0x93 | dpl); | |
2665 | } | |
2666 | } | |
2667 | ||
2668 | static void enter_pmode(struct kvm_vcpu *vcpu) | |
2669 | { | |
2670 | unsigned long flags; | |
a89a8fb9 | 2671 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6aa8b732 | 2672 | |
a89a8fb9 | 2673 | vmx->emulation_required = 1; |
7ffd92c5 | 2674 | vmx->rmode.vm86_active = 0; |
6aa8b732 | 2675 | |
2fb92db1 AK |
2676 | vmx_segment_cache_clear(vmx); |
2677 | ||
d0ba64f9 | 2678 | vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector); |
7ffd92c5 AK |
2679 | vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base); |
2680 | vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit); | |
2681 | vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar); | |
6aa8b732 AK |
2682 | |
2683 | flags = vmcs_readl(GUEST_RFLAGS); | |
78ac8b47 AK |
2684 | flags &= RMODE_GUEST_OWNED_EFLAGS_BITS; |
2685 | flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS; | |
6aa8b732 AK |
2686 | vmcs_writel(GUEST_RFLAGS, flags); |
2687 | ||
66aee91a RR |
2688 | vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) | |
2689 | (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME)); | |
6aa8b732 AK |
2690 | |
2691 | update_exception_bitmap(vcpu); | |
2692 | ||
a89a8fb9 MG |
2693 | if (emulate_invalid_guest_state) |
2694 | return; | |
2695 | ||
7ffd92c5 AK |
2696 | fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es); |
2697 | fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds); | |
2698 | fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs); | |
2699 | fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs); | |
6aa8b732 | 2700 | |
2fb92db1 AK |
2701 | vmx_segment_cache_clear(vmx); |
2702 | ||
6aa8b732 AK |
2703 | vmcs_write16(GUEST_SS_SELECTOR, 0); |
2704 | vmcs_write32(GUEST_SS_AR_BYTES, 0x93); | |
2705 | ||
2706 | vmcs_write16(GUEST_CS_SELECTOR, | |
2707 | vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK); | |
2708 | vmcs_write32(GUEST_CS_AR_BYTES, 0x9b); | |
2709 | } | |
2710 | ||
d77c26fc | 2711 | static gva_t rmode_tss_base(struct kvm *kvm) |
6aa8b732 | 2712 | { |
bfc6d222 | 2713 | if (!kvm->arch.tss_addr) { |
bc6678a3 MT |
2714 | struct kvm_memslots *slots; |
2715 | gfn_t base_gfn; | |
2716 | ||
90d83dc3 | 2717 | slots = kvm_memslots(kvm); |
f495c6e5 | 2718 | base_gfn = slots->memslots[0].base_gfn + |
46a26bf5 | 2719 | kvm->memslots->memslots[0].npages - 3; |
cbc94022 IE |
2720 | return base_gfn << PAGE_SHIFT; |
2721 | } | |
bfc6d222 | 2722 | return kvm->arch.tss_addr; |
6aa8b732 AK |
2723 | } |
2724 | ||
2725 | static void fix_rmode_seg(int seg, struct kvm_save_segment *save) | |
2726 | { | |
2727 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
2728 | ||
2729 | save->selector = vmcs_read16(sf->selector); | |
2730 | save->base = vmcs_readl(sf->base); | |
2731 | save->limit = vmcs_read32(sf->limit); | |
2732 | save->ar = vmcs_read32(sf->ar_bytes); | |
15b00f32 | 2733 | vmcs_write16(sf->selector, save->base >> 4); |
444e863d | 2734 | vmcs_write32(sf->base, save->base & 0xffff0); |
6aa8b732 AK |
2735 | vmcs_write32(sf->limit, 0xffff); |
2736 | vmcs_write32(sf->ar_bytes, 0xf3); | |
444e863d GN |
2737 | if (save->base & 0xf) |
2738 | printk_once(KERN_WARNING "kvm: segment base is not paragraph" | |
2739 | " aligned when entering protected mode (seg=%d)", | |
2740 | seg); | |
6aa8b732 AK |
2741 | } |
2742 | ||
2743 | static void enter_rmode(struct kvm_vcpu *vcpu) | |
2744 | { | |
2745 | unsigned long flags; | |
a89a8fb9 | 2746 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6aa8b732 | 2747 | |
3a624e29 NK |
2748 | if (enable_unrestricted_guest) |
2749 | return; | |
2750 | ||
a89a8fb9 | 2751 | vmx->emulation_required = 1; |
7ffd92c5 | 2752 | vmx->rmode.vm86_active = 1; |
6aa8b732 | 2753 | |
776e58ea GN |
2754 | /* |
2755 | * Very old userspace does not call KVM_SET_TSS_ADDR before entering | |
2756 | * vcpu. Call it here with phys address pointing 16M below 4G. | |
2757 | */ | |
2758 | if (!vcpu->kvm->arch.tss_addr) { | |
2759 | printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be " | |
2760 | "called before entering vcpu\n"); | |
2761 | srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); | |
2762 | vmx_set_tss_addr(vcpu->kvm, 0xfeffd000); | |
2763 | vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); | |
2764 | } | |
2765 | ||
2fb92db1 AK |
2766 | vmx_segment_cache_clear(vmx); |
2767 | ||
d0ba64f9 | 2768 | vmx->rmode.tr.selector = vmcs_read16(GUEST_TR_SELECTOR); |
7ffd92c5 | 2769 | vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE); |
6aa8b732 AK |
2770 | vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm)); |
2771 | ||
7ffd92c5 | 2772 | vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT); |
6aa8b732 AK |
2773 | vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1); |
2774 | ||
7ffd92c5 | 2775 | vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES); |
6aa8b732 AK |
2776 | vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); |
2777 | ||
2778 | flags = vmcs_readl(GUEST_RFLAGS); | |
78ac8b47 | 2779 | vmx->rmode.save_rflags = flags; |
6aa8b732 | 2780 | |
053de044 | 2781 | flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; |
6aa8b732 AK |
2782 | |
2783 | vmcs_writel(GUEST_RFLAGS, flags); | |
66aee91a | 2784 | vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME); |
6aa8b732 AK |
2785 | update_exception_bitmap(vcpu); |
2786 | ||
a89a8fb9 MG |
2787 | if (emulate_invalid_guest_state) |
2788 | goto continue_rmode; | |
2789 | ||
6aa8b732 AK |
2790 | vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4); |
2791 | vmcs_write32(GUEST_SS_LIMIT, 0xffff); | |
2792 | vmcs_write32(GUEST_SS_AR_BYTES, 0xf3); | |
2793 | ||
2794 | vmcs_write32(GUEST_CS_AR_BYTES, 0xf3); | |
abacf8df | 2795 | vmcs_write32(GUEST_CS_LIMIT, 0xffff); |
8cb5b033 AK |
2796 | if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000) |
2797 | vmcs_writel(GUEST_CS_BASE, 0xf0000); | |
6aa8b732 AK |
2798 | vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4); |
2799 | ||
7ffd92c5 AK |
2800 | fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es); |
2801 | fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds); | |
2802 | fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs); | |
2803 | fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs); | |
75880a01 | 2804 | |
a89a8fb9 | 2805 | continue_rmode: |
8668a3c4 | 2806 | kvm_mmu_reset_context(vcpu); |
6aa8b732 AK |
2807 | } |
2808 | ||
401d10de AS |
2809 | static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer) |
2810 | { | |
2811 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
26bb0981 AK |
2812 | struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER); |
2813 | ||
2814 | if (!msr) | |
2815 | return; | |
401d10de | 2816 | |
44ea2b17 AK |
2817 | /* |
2818 | * Force kernel_gs_base reloading before EFER changes, as control | |
2819 | * of this msr depends on is_long_mode(). | |
2820 | */ | |
2821 | vmx_load_host_state(to_vmx(vcpu)); | |
f6801dff | 2822 | vcpu->arch.efer = efer; |
401d10de AS |
2823 | if (efer & EFER_LMA) { |
2824 | vmcs_write32(VM_ENTRY_CONTROLS, | |
2825 | vmcs_read32(VM_ENTRY_CONTROLS) | | |
2826 | VM_ENTRY_IA32E_MODE); | |
2827 | msr->data = efer; | |
2828 | } else { | |
2829 | vmcs_write32(VM_ENTRY_CONTROLS, | |
2830 | vmcs_read32(VM_ENTRY_CONTROLS) & | |
2831 | ~VM_ENTRY_IA32E_MODE); | |
2832 | ||
2833 | msr->data = efer & ~EFER_LME; | |
2834 | } | |
2835 | setup_msrs(vmx); | |
2836 | } | |
2837 | ||
05b3e0c2 | 2838 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
2839 | |
2840 | static void enter_lmode(struct kvm_vcpu *vcpu) | |
2841 | { | |
2842 | u32 guest_tr_ar; | |
2843 | ||
2fb92db1 AK |
2844 | vmx_segment_cache_clear(to_vmx(vcpu)); |
2845 | ||
6aa8b732 AK |
2846 | guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES); |
2847 | if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) { | |
bd80158a JK |
2848 | pr_debug_ratelimited("%s: tss fixup for long mode. \n", |
2849 | __func__); | |
6aa8b732 AK |
2850 | vmcs_write32(GUEST_TR_AR_BYTES, |
2851 | (guest_tr_ar & ~AR_TYPE_MASK) | |
2852 | | AR_TYPE_BUSY_64_TSS); | |
2853 | } | |
da38f438 | 2854 | vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA); |
6aa8b732 AK |
2855 | } |
2856 | ||
2857 | static void exit_lmode(struct kvm_vcpu *vcpu) | |
2858 | { | |
6aa8b732 AK |
2859 | vmcs_write32(VM_ENTRY_CONTROLS, |
2860 | vmcs_read32(VM_ENTRY_CONTROLS) | |
1e4e6e00 | 2861 | & ~VM_ENTRY_IA32E_MODE); |
da38f438 | 2862 | vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA); |
6aa8b732 AK |
2863 | } |
2864 | ||
2865 | #endif | |
2866 | ||
2384d2b3 SY |
2867 | static void vmx_flush_tlb(struct kvm_vcpu *vcpu) |
2868 | { | |
b9d762fa | 2869 | vpid_sync_context(to_vmx(vcpu)); |
dd180b3e XG |
2870 | if (enable_ept) { |
2871 | if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) | |
2872 | return; | |
4e1096d2 | 2873 | ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa)); |
dd180b3e | 2874 | } |
2384d2b3 SY |
2875 | } |
2876 | ||
e8467fda AK |
2877 | static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu) |
2878 | { | |
2879 | ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits; | |
2880 | ||
2881 | vcpu->arch.cr0 &= ~cr0_guest_owned_bits; | |
2882 | vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits; | |
2883 | } | |
2884 | ||
aff48baa AK |
2885 | static void vmx_decache_cr3(struct kvm_vcpu *vcpu) |
2886 | { | |
2887 | if (enable_ept && is_paging(vcpu)) | |
2888 | vcpu->arch.cr3 = vmcs_readl(GUEST_CR3); | |
2889 | __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); | |
2890 | } | |
2891 | ||
25c4c276 | 2892 | static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 | 2893 | { |
fc78f519 AK |
2894 | ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits; |
2895 | ||
2896 | vcpu->arch.cr4 &= ~cr4_guest_owned_bits; | |
2897 | vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits; | |
399badf3 AK |
2898 | } |
2899 | ||
1439442c SY |
2900 | static void ept_load_pdptrs(struct kvm_vcpu *vcpu) |
2901 | { | |
6de4f3ad AK |
2902 | if (!test_bit(VCPU_EXREG_PDPTR, |
2903 | (unsigned long *)&vcpu->arch.regs_dirty)) | |
2904 | return; | |
2905 | ||
1439442c | 2906 | if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) { |
ff03a073 JR |
2907 | vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]); |
2908 | vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]); | |
2909 | vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]); | |
2910 | vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]); | |
1439442c SY |
2911 | } |
2912 | } | |
2913 | ||
8f5d549f AK |
2914 | static void ept_save_pdptrs(struct kvm_vcpu *vcpu) |
2915 | { | |
2916 | if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) { | |
ff03a073 JR |
2917 | vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0); |
2918 | vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1); | |
2919 | vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2); | |
2920 | vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3); | |
8f5d549f | 2921 | } |
6de4f3ad AK |
2922 | |
2923 | __set_bit(VCPU_EXREG_PDPTR, | |
2924 | (unsigned long *)&vcpu->arch.regs_avail); | |
2925 | __set_bit(VCPU_EXREG_PDPTR, | |
2926 | (unsigned long *)&vcpu->arch.regs_dirty); | |
8f5d549f AK |
2927 | } |
2928 | ||
5e1746d6 | 2929 | static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); |
1439442c SY |
2930 | |
2931 | static void ept_update_paging_mode_cr0(unsigned long *hw_cr0, | |
2932 | unsigned long cr0, | |
2933 | struct kvm_vcpu *vcpu) | |
2934 | { | |
5233dd51 MT |
2935 | if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail)) |
2936 | vmx_decache_cr3(vcpu); | |
1439442c SY |
2937 | if (!(cr0 & X86_CR0_PG)) { |
2938 | /* From paging/starting to nonpaging */ | |
2939 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, | |
65267ea1 | 2940 | vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) | |
1439442c SY |
2941 | (CPU_BASED_CR3_LOAD_EXITING | |
2942 | CPU_BASED_CR3_STORE_EXITING)); | |
2943 | vcpu->arch.cr0 = cr0; | |
fc78f519 | 2944 | vmx_set_cr4(vcpu, kvm_read_cr4(vcpu)); |
1439442c SY |
2945 | } else if (!is_paging(vcpu)) { |
2946 | /* From nonpaging to paging */ | |
2947 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, | |
65267ea1 | 2948 | vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) & |
1439442c SY |
2949 | ~(CPU_BASED_CR3_LOAD_EXITING | |
2950 | CPU_BASED_CR3_STORE_EXITING)); | |
2951 | vcpu->arch.cr0 = cr0; | |
fc78f519 | 2952 | vmx_set_cr4(vcpu, kvm_read_cr4(vcpu)); |
1439442c | 2953 | } |
95eb84a7 SY |
2954 | |
2955 | if (!(cr0 & X86_CR0_WP)) | |
2956 | *hw_cr0 &= ~X86_CR0_WP; | |
1439442c SY |
2957 | } |
2958 | ||
6aa8b732 AK |
2959 | static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
2960 | { | |
7ffd92c5 | 2961 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
3a624e29 NK |
2962 | unsigned long hw_cr0; |
2963 | ||
2964 | if (enable_unrestricted_guest) | |
2965 | hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST) | |
2966 | | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST; | |
2967 | else | |
2968 | hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON; | |
1439442c | 2969 | |
7ffd92c5 | 2970 | if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE)) |
6aa8b732 AK |
2971 | enter_pmode(vcpu); |
2972 | ||
7ffd92c5 | 2973 | if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE)) |
6aa8b732 AK |
2974 | enter_rmode(vcpu); |
2975 | ||
05b3e0c2 | 2976 | #ifdef CONFIG_X86_64 |
f6801dff | 2977 | if (vcpu->arch.efer & EFER_LME) { |
707d92fa | 2978 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) |
6aa8b732 | 2979 | enter_lmode(vcpu); |
707d92fa | 2980 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) |
6aa8b732 AK |
2981 | exit_lmode(vcpu); |
2982 | } | |
2983 | #endif | |
2984 | ||
089d034e | 2985 | if (enable_ept) |
1439442c SY |
2986 | ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu); |
2987 | ||
02daab21 | 2988 | if (!vcpu->fpu_active) |
81231c69 | 2989 | hw_cr0 |= X86_CR0_TS | X86_CR0_MP; |
02daab21 | 2990 | |
6aa8b732 | 2991 | vmcs_writel(CR0_READ_SHADOW, cr0); |
1439442c | 2992 | vmcs_writel(GUEST_CR0, hw_cr0); |
ad312c7c | 2993 | vcpu->arch.cr0 = cr0; |
69c73028 | 2994 | __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail); |
6aa8b732 AK |
2995 | } |
2996 | ||
1439442c SY |
2997 | static u64 construct_eptp(unsigned long root_hpa) |
2998 | { | |
2999 | u64 eptp; | |
3000 | ||
3001 | /* TODO write the value reading from MSR */ | |
3002 | eptp = VMX_EPT_DEFAULT_MT | | |
3003 | VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT; | |
3004 | eptp |= (root_hpa & PAGE_MASK); | |
3005 | ||
3006 | return eptp; | |
3007 | } | |
3008 | ||
6aa8b732 AK |
3009 | static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) |
3010 | { | |
1439442c SY |
3011 | unsigned long guest_cr3; |
3012 | u64 eptp; | |
3013 | ||
3014 | guest_cr3 = cr3; | |
089d034e | 3015 | if (enable_ept) { |
1439442c SY |
3016 | eptp = construct_eptp(cr3); |
3017 | vmcs_write64(EPT_POINTER, eptp); | |
9f8fe504 | 3018 | guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) : |
b927a3ce | 3019 | vcpu->kvm->arch.ept_identity_map_addr; |
7c93be44 | 3020 | ept_load_pdptrs(vcpu); |
1439442c SY |
3021 | } |
3022 | ||
2384d2b3 | 3023 | vmx_flush_tlb(vcpu); |
1439442c | 3024 | vmcs_writel(GUEST_CR3, guest_cr3); |
6aa8b732 AK |
3025 | } |
3026 | ||
5e1746d6 | 3027 | static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
6aa8b732 | 3028 | { |
7ffd92c5 | 3029 | unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ? |
1439442c SY |
3030 | KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON); |
3031 | ||
5e1746d6 NHE |
3032 | if (cr4 & X86_CR4_VMXE) { |
3033 | /* | |
3034 | * To use VMXON (and later other VMX instructions), a guest | |
3035 | * must first be able to turn on cr4.VMXE (see handle_vmon()). | |
3036 | * So basically the check on whether to allow nested VMX | |
3037 | * is here. | |
3038 | */ | |
3039 | if (!nested_vmx_allowed(vcpu)) | |
3040 | return 1; | |
3041 | } else if (to_vmx(vcpu)->nested.vmxon) | |
3042 | return 1; | |
3043 | ||
ad312c7c | 3044 | vcpu->arch.cr4 = cr4; |
bc23008b AK |
3045 | if (enable_ept) { |
3046 | if (!is_paging(vcpu)) { | |
3047 | hw_cr4 &= ~X86_CR4_PAE; | |
3048 | hw_cr4 |= X86_CR4_PSE; | |
3049 | } else if (!(cr4 & X86_CR4_PAE)) { | |
3050 | hw_cr4 &= ~X86_CR4_PAE; | |
3051 | } | |
3052 | } | |
1439442c SY |
3053 | |
3054 | vmcs_writel(CR4_READ_SHADOW, cr4); | |
3055 | vmcs_writel(GUEST_CR4, hw_cr4); | |
5e1746d6 | 3056 | return 0; |
6aa8b732 AK |
3057 | } |
3058 | ||
6aa8b732 AK |
3059 | static void vmx_get_segment(struct kvm_vcpu *vcpu, |
3060 | struct kvm_segment *var, int seg) | |
3061 | { | |
a9179499 | 3062 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
a9179499 | 3063 | struct kvm_save_segment *save; |
6aa8b732 AK |
3064 | u32 ar; |
3065 | ||
a9179499 AK |
3066 | if (vmx->rmode.vm86_active |
3067 | && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES | |
3068 | || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS | |
3069 | || seg == VCPU_SREG_GS) | |
3070 | && !emulate_invalid_guest_state) { | |
3071 | switch (seg) { | |
3072 | case VCPU_SREG_TR: save = &vmx->rmode.tr; break; | |
3073 | case VCPU_SREG_ES: save = &vmx->rmode.es; break; | |
3074 | case VCPU_SREG_DS: save = &vmx->rmode.ds; break; | |
3075 | case VCPU_SREG_FS: save = &vmx->rmode.fs; break; | |
3076 | case VCPU_SREG_GS: save = &vmx->rmode.gs; break; | |
3077 | default: BUG(); | |
3078 | } | |
3079 | var->selector = save->selector; | |
3080 | var->base = save->base; | |
3081 | var->limit = save->limit; | |
3082 | ar = save->ar; | |
3083 | if (seg == VCPU_SREG_TR | |
2fb92db1 | 3084 | || var->selector == vmx_read_guest_seg_selector(vmx, seg)) |
a9179499 AK |
3085 | goto use_saved_rmode_seg; |
3086 | } | |
2fb92db1 AK |
3087 | var->base = vmx_read_guest_seg_base(vmx, seg); |
3088 | var->limit = vmx_read_guest_seg_limit(vmx, seg); | |
3089 | var->selector = vmx_read_guest_seg_selector(vmx, seg); | |
3090 | ar = vmx_read_guest_seg_ar(vmx, seg); | |
a9179499 | 3091 | use_saved_rmode_seg: |
9fd4a3b7 | 3092 | if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state) |
6aa8b732 AK |
3093 | ar = 0; |
3094 | var->type = ar & 15; | |
3095 | var->s = (ar >> 4) & 1; | |
3096 | var->dpl = (ar >> 5) & 3; | |
3097 | var->present = (ar >> 7) & 1; | |
3098 | var->avl = (ar >> 12) & 1; | |
3099 | var->l = (ar >> 13) & 1; | |
3100 | var->db = (ar >> 14) & 1; | |
3101 | var->g = (ar >> 15) & 1; | |
3102 | var->unusable = (ar >> 16) & 1; | |
3103 | } | |
3104 | ||
a9179499 AK |
3105 | static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg) |
3106 | { | |
a9179499 AK |
3107 | struct kvm_segment s; |
3108 | ||
3109 | if (to_vmx(vcpu)->rmode.vm86_active) { | |
3110 | vmx_get_segment(vcpu, &s, seg); | |
3111 | return s.base; | |
3112 | } | |
2fb92db1 | 3113 | return vmx_read_guest_seg_base(to_vmx(vcpu), seg); |
a9179499 AK |
3114 | } |
3115 | ||
69c73028 | 3116 | static int __vmx_get_cpl(struct kvm_vcpu *vcpu) |
2e4d2653 | 3117 | { |
3eeb3288 | 3118 | if (!is_protmode(vcpu)) |
2e4d2653 IE |
3119 | return 0; |
3120 | ||
f4c63e5d AK |
3121 | if (!is_long_mode(vcpu) |
3122 | && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */ | |
2e4d2653 IE |
3123 | return 3; |
3124 | ||
2fb92db1 | 3125 | return vmx_read_guest_seg_selector(to_vmx(vcpu), VCPU_SREG_CS) & 3; |
2e4d2653 IE |
3126 | } |
3127 | ||
69c73028 AK |
3128 | static int vmx_get_cpl(struct kvm_vcpu *vcpu) |
3129 | { | |
3130 | if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) { | |
3131 | __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail); | |
3132 | to_vmx(vcpu)->cpl = __vmx_get_cpl(vcpu); | |
3133 | } | |
3134 | return to_vmx(vcpu)->cpl; | |
3135 | } | |
3136 | ||
3137 | ||
653e3108 | 3138 | static u32 vmx_segment_access_rights(struct kvm_segment *var) |
6aa8b732 | 3139 | { |
6aa8b732 AK |
3140 | u32 ar; |
3141 | ||
653e3108 | 3142 | if (var->unusable) |
6aa8b732 AK |
3143 | ar = 1 << 16; |
3144 | else { | |
3145 | ar = var->type & 15; | |
3146 | ar |= (var->s & 1) << 4; | |
3147 | ar |= (var->dpl & 3) << 5; | |
3148 | ar |= (var->present & 1) << 7; | |
3149 | ar |= (var->avl & 1) << 12; | |
3150 | ar |= (var->l & 1) << 13; | |
3151 | ar |= (var->db & 1) << 14; | |
3152 | ar |= (var->g & 1) << 15; | |
3153 | } | |
f7fbf1fd UL |
3154 | if (ar == 0) /* a 0 value means unusable */ |
3155 | ar = AR_UNUSABLE_MASK; | |
653e3108 AK |
3156 | |
3157 | return ar; | |
3158 | } | |
3159 | ||
3160 | static void vmx_set_segment(struct kvm_vcpu *vcpu, | |
3161 | struct kvm_segment *var, int seg) | |
3162 | { | |
7ffd92c5 | 3163 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
653e3108 AK |
3164 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; |
3165 | u32 ar; | |
3166 | ||
2fb92db1 AK |
3167 | vmx_segment_cache_clear(vmx); |
3168 | ||
7ffd92c5 | 3169 | if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) { |
a8ba6c26 | 3170 | vmcs_write16(sf->selector, var->selector); |
7ffd92c5 AK |
3171 | vmx->rmode.tr.selector = var->selector; |
3172 | vmx->rmode.tr.base = var->base; | |
3173 | vmx->rmode.tr.limit = var->limit; | |
3174 | vmx->rmode.tr.ar = vmx_segment_access_rights(var); | |
653e3108 AK |
3175 | return; |
3176 | } | |
3177 | vmcs_writel(sf->base, var->base); | |
3178 | vmcs_write32(sf->limit, var->limit); | |
3179 | vmcs_write16(sf->selector, var->selector); | |
7ffd92c5 | 3180 | if (vmx->rmode.vm86_active && var->s) { |
653e3108 AK |
3181 | /* |
3182 | * Hack real-mode segments into vm86 compatibility. | |
3183 | */ | |
3184 | if (var->base == 0xffff0000 && var->selector == 0xf000) | |
3185 | vmcs_writel(sf->base, 0xf0000); | |
3186 | ar = 0xf3; | |
3187 | } else | |
3188 | ar = vmx_segment_access_rights(var); | |
3a624e29 NK |
3189 | |
3190 | /* | |
3191 | * Fix the "Accessed" bit in AR field of segment registers for older | |
3192 | * qemu binaries. | |
3193 | * IA32 arch specifies that at the time of processor reset the | |
3194 | * "Accessed" bit in the AR field of segment registers is 1. And qemu | |
3195 | * is setting it to 0 in the usedland code. This causes invalid guest | |
3196 | * state vmexit when "unrestricted guest" mode is turned on. | |
3197 | * Fix for this setup issue in cpu_reset is being pushed in the qemu | |
3198 | * tree. Newer qemu binaries with that qemu fix would not need this | |
3199 | * kvm hack. | |
3200 | */ | |
3201 | if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR)) | |
3202 | ar |= 0x1; /* Accessed */ | |
3203 | ||
6aa8b732 | 3204 | vmcs_write32(sf->ar_bytes, ar); |
69c73028 | 3205 | __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail); |
6aa8b732 AK |
3206 | } |
3207 | ||
6aa8b732 AK |
3208 | static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) |
3209 | { | |
2fb92db1 | 3210 | u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS); |
6aa8b732 AK |
3211 | |
3212 | *db = (ar >> 14) & 1; | |
3213 | *l = (ar >> 13) & 1; | |
3214 | } | |
3215 | ||
89a27f4d | 3216 | static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 3217 | { |
89a27f4d GN |
3218 | dt->size = vmcs_read32(GUEST_IDTR_LIMIT); |
3219 | dt->address = vmcs_readl(GUEST_IDTR_BASE); | |
6aa8b732 AK |
3220 | } |
3221 | ||
89a27f4d | 3222 | static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 3223 | { |
89a27f4d GN |
3224 | vmcs_write32(GUEST_IDTR_LIMIT, dt->size); |
3225 | vmcs_writel(GUEST_IDTR_BASE, dt->address); | |
6aa8b732 AK |
3226 | } |
3227 | ||
89a27f4d | 3228 | static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 3229 | { |
89a27f4d GN |
3230 | dt->size = vmcs_read32(GUEST_GDTR_LIMIT); |
3231 | dt->address = vmcs_readl(GUEST_GDTR_BASE); | |
6aa8b732 AK |
3232 | } |
3233 | ||
89a27f4d | 3234 | static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) |
6aa8b732 | 3235 | { |
89a27f4d GN |
3236 | vmcs_write32(GUEST_GDTR_LIMIT, dt->size); |
3237 | vmcs_writel(GUEST_GDTR_BASE, dt->address); | |
6aa8b732 AK |
3238 | } |
3239 | ||
648dfaa7 MG |
3240 | static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg) |
3241 | { | |
3242 | struct kvm_segment var; | |
3243 | u32 ar; | |
3244 | ||
3245 | vmx_get_segment(vcpu, &var, seg); | |
3246 | ar = vmx_segment_access_rights(&var); | |
3247 | ||
3248 | if (var.base != (var.selector << 4)) | |
3249 | return false; | |
3250 | if (var.limit != 0xffff) | |
3251 | return false; | |
3252 | if (ar != 0xf3) | |
3253 | return false; | |
3254 | ||
3255 | return true; | |
3256 | } | |
3257 | ||
3258 | static bool code_segment_valid(struct kvm_vcpu *vcpu) | |
3259 | { | |
3260 | struct kvm_segment cs; | |
3261 | unsigned int cs_rpl; | |
3262 | ||
3263 | vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
3264 | cs_rpl = cs.selector & SELECTOR_RPL_MASK; | |
3265 | ||
1872a3f4 AK |
3266 | if (cs.unusable) |
3267 | return false; | |
648dfaa7 MG |
3268 | if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK)) |
3269 | return false; | |
3270 | if (!cs.s) | |
3271 | return false; | |
1872a3f4 | 3272 | if (cs.type & AR_TYPE_WRITEABLE_MASK) { |
648dfaa7 MG |
3273 | if (cs.dpl > cs_rpl) |
3274 | return false; | |
1872a3f4 | 3275 | } else { |
648dfaa7 MG |
3276 | if (cs.dpl != cs_rpl) |
3277 | return false; | |
3278 | } | |
3279 | if (!cs.present) | |
3280 | return false; | |
3281 | ||
3282 | /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */ | |
3283 | return true; | |
3284 | } | |
3285 | ||
3286 | static bool stack_segment_valid(struct kvm_vcpu *vcpu) | |
3287 | { | |
3288 | struct kvm_segment ss; | |
3289 | unsigned int ss_rpl; | |
3290 | ||
3291 | vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); | |
3292 | ss_rpl = ss.selector & SELECTOR_RPL_MASK; | |
3293 | ||
1872a3f4 AK |
3294 | if (ss.unusable) |
3295 | return true; | |
3296 | if (ss.type != 3 && ss.type != 7) | |
648dfaa7 MG |
3297 | return false; |
3298 | if (!ss.s) | |
3299 | return false; | |
3300 | if (ss.dpl != ss_rpl) /* DPL != RPL */ | |
3301 | return false; | |
3302 | if (!ss.present) | |
3303 | return false; | |
3304 | ||
3305 | return true; | |
3306 | } | |
3307 | ||
3308 | static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg) | |
3309 | { | |
3310 | struct kvm_segment var; | |
3311 | unsigned int rpl; | |
3312 | ||
3313 | vmx_get_segment(vcpu, &var, seg); | |
3314 | rpl = var.selector & SELECTOR_RPL_MASK; | |
3315 | ||
1872a3f4 AK |
3316 | if (var.unusable) |
3317 | return true; | |
648dfaa7 MG |
3318 | if (!var.s) |
3319 | return false; | |
3320 | if (!var.present) | |
3321 | return false; | |
3322 | if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) { | |
3323 | if (var.dpl < rpl) /* DPL < RPL */ | |
3324 | return false; | |
3325 | } | |
3326 | ||
3327 | /* TODO: Add other members to kvm_segment_field to allow checking for other access | |
3328 | * rights flags | |
3329 | */ | |
3330 | return true; | |
3331 | } | |
3332 | ||
3333 | static bool tr_valid(struct kvm_vcpu *vcpu) | |
3334 | { | |
3335 | struct kvm_segment tr; | |
3336 | ||
3337 | vmx_get_segment(vcpu, &tr, VCPU_SREG_TR); | |
3338 | ||
1872a3f4 AK |
3339 | if (tr.unusable) |
3340 | return false; | |
648dfaa7 MG |
3341 | if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */ |
3342 | return false; | |
1872a3f4 | 3343 | if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */ |
648dfaa7 MG |
3344 | return false; |
3345 | if (!tr.present) | |
3346 | return false; | |
3347 | ||
3348 | return true; | |
3349 | } | |
3350 | ||
3351 | static bool ldtr_valid(struct kvm_vcpu *vcpu) | |
3352 | { | |
3353 | struct kvm_segment ldtr; | |
3354 | ||
3355 | vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR); | |
3356 | ||
1872a3f4 AK |
3357 | if (ldtr.unusable) |
3358 | return true; | |
648dfaa7 MG |
3359 | if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */ |
3360 | return false; | |
3361 | if (ldtr.type != 2) | |
3362 | return false; | |
3363 | if (!ldtr.present) | |
3364 | return false; | |
3365 | ||
3366 | return true; | |
3367 | } | |
3368 | ||
3369 | static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu) | |
3370 | { | |
3371 | struct kvm_segment cs, ss; | |
3372 | ||
3373 | vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
3374 | vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); | |
3375 | ||
3376 | return ((cs.selector & SELECTOR_RPL_MASK) == | |
3377 | (ss.selector & SELECTOR_RPL_MASK)); | |
3378 | } | |
3379 | ||
3380 | /* | |
3381 | * Check if guest state is valid. Returns true if valid, false if | |
3382 | * not. | |
3383 | * We assume that registers are always usable | |
3384 | */ | |
3385 | static bool guest_state_valid(struct kvm_vcpu *vcpu) | |
3386 | { | |
3387 | /* real mode guest state checks */ | |
3eeb3288 | 3388 | if (!is_protmode(vcpu)) { |
648dfaa7 MG |
3389 | if (!rmode_segment_valid(vcpu, VCPU_SREG_CS)) |
3390 | return false; | |
3391 | if (!rmode_segment_valid(vcpu, VCPU_SREG_SS)) | |
3392 | return false; | |
3393 | if (!rmode_segment_valid(vcpu, VCPU_SREG_DS)) | |
3394 | return false; | |
3395 | if (!rmode_segment_valid(vcpu, VCPU_SREG_ES)) | |
3396 | return false; | |
3397 | if (!rmode_segment_valid(vcpu, VCPU_SREG_FS)) | |
3398 | return false; | |
3399 | if (!rmode_segment_valid(vcpu, VCPU_SREG_GS)) | |
3400 | return false; | |
3401 | } else { | |
3402 | /* protected mode guest state checks */ | |
3403 | if (!cs_ss_rpl_check(vcpu)) | |
3404 | return false; | |
3405 | if (!code_segment_valid(vcpu)) | |
3406 | return false; | |
3407 | if (!stack_segment_valid(vcpu)) | |
3408 | return false; | |
3409 | if (!data_segment_valid(vcpu, VCPU_SREG_DS)) | |
3410 | return false; | |
3411 | if (!data_segment_valid(vcpu, VCPU_SREG_ES)) | |
3412 | return false; | |
3413 | if (!data_segment_valid(vcpu, VCPU_SREG_FS)) | |
3414 | return false; | |
3415 | if (!data_segment_valid(vcpu, VCPU_SREG_GS)) | |
3416 | return false; | |
3417 | if (!tr_valid(vcpu)) | |
3418 | return false; | |
3419 | if (!ldtr_valid(vcpu)) | |
3420 | return false; | |
3421 | } | |
3422 | /* TODO: | |
3423 | * - Add checks on RIP | |
3424 | * - Add checks on RFLAGS | |
3425 | */ | |
3426 | ||
3427 | return true; | |
3428 | } | |
3429 | ||
d77c26fc | 3430 | static int init_rmode_tss(struct kvm *kvm) |
6aa8b732 | 3431 | { |
40dcaa9f | 3432 | gfn_t fn; |
195aefde | 3433 | u16 data = 0; |
40dcaa9f | 3434 | int r, idx, ret = 0; |
6aa8b732 | 3435 | |
40dcaa9f XG |
3436 | idx = srcu_read_lock(&kvm->srcu); |
3437 | fn = rmode_tss_base(kvm) >> PAGE_SHIFT; | |
195aefde IE |
3438 | r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); |
3439 | if (r < 0) | |
10589a46 | 3440 | goto out; |
195aefde | 3441 | data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE; |
464d17c8 SY |
3442 | r = kvm_write_guest_page(kvm, fn++, &data, |
3443 | TSS_IOPB_BASE_OFFSET, sizeof(u16)); | |
195aefde | 3444 | if (r < 0) |
10589a46 | 3445 | goto out; |
195aefde IE |
3446 | r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE); |
3447 | if (r < 0) | |
10589a46 | 3448 | goto out; |
195aefde IE |
3449 | r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); |
3450 | if (r < 0) | |
10589a46 | 3451 | goto out; |
195aefde | 3452 | data = ~0; |
10589a46 MT |
3453 | r = kvm_write_guest_page(kvm, fn, &data, |
3454 | RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1, | |
3455 | sizeof(u8)); | |
195aefde | 3456 | if (r < 0) |
10589a46 MT |
3457 | goto out; |
3458 | ||
3459 | ret = 1; | |
3460 | out: | |
40dcaa9f | 3461 | srcu_read_unlock(&kvm->srcu, idx); |
10589a46 | 3462 | return ret; |
6aa8b732 AK |
3463 | } |
3464 | ||
b7ebfb05 SY |
3465 | static int init_rmode_identity_map(struct kvm *kvm) |
3466 | { | |
40dcaa9f | 3467 | int i, idx, r, ret; |
b7ebfb05 SY |
3468 | pfn_t identity_map_pfn; |
3469 | u32 tmp; | |
3470 | ||
089d034e | 3471 | if (!enable_ept) |
b7ebfb05 SY |
3472 | return 1; |
3473 | if (unlikely(!kvm->arch.ept_identity_pagetable)) { | |
3474 | printk(KERN_ERR "EPT: identity-mapping pagetable " | |
3475 | "haven't been allocated!\n"); | |
3476 | return 0; | |
3477 | } | |
3478 | if (likely(kvm->arch.ept_identity_pagetable_done)) | |
3479 | return 1; | |
3480 | ret = 0; | |
b927a3ce | 3481 | identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT; |
40dcaa9f | 3482 | idx = srcu_read_lock(&kvm->srcu); |
b7ebfb05 SY |
3483 | r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE); |
3484 | if (r < 0) | |
3485 | goto out; | |
3486 | /* Set up identity-mapping pagetable for EPT in real mode */ | |
3487 | for (i = 0; i < PT32_ENT_PER_PAGE; i++) { | |
3488 | tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | | |
3489 | _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE); | |
3490 | r = kvm_write_guest_page(kvm, identity_map_pfn, | |
3491 | &tmp, i * sizeof(tmp), sizeof(tmp)); | |
3492 | if (r < 0) | |
3493 | goto out; | |
3494 | } | |
3495 | kvm->arch.ept_identity_pagetable_done = true; | |
3496 | ret = 1; | |
3497 | out: | |
40dcaa9f | 3498 | srcu_read_unlock(&kvm->srcu, idx); |
b7ebfb05 SY |
3499 | return ret; |
3500 | } | |
3501 | ||
6aa8b732 AK |
3502 | static void seg_setup(int seg) |
3503 | { | |
3504 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
3a624e29 | 3505 | unsigned int ar; |
6aa8b732 AK |
3506 | |
3507 | vmcs_write16(sf->selector, 0); | |
3508 | vmcs_writel(sf->base, 0); | |
3509 | vmcs_write32(sf->limit, 0xffff); | |
3a624e29 NK |
3510 | if (enable_unrestricted_guest) { |
3511 | ar = 0x93; | |
3512 | if (seg == VCPU_SREG_CS) | |
3513 | ar |= 0x08; /* code segment */ | |
3514 | } else | |
3515 | ar = 0xf3; | |
3516 | ||
3517 | vmcs_write32(sf->ar_bytes, ar); | |
6aa8b732 AK |
3518 | } |
3519 | ||
f78e0e2e SY |
3520 | static int alloc_apic_access_page(struct kvm *kvm) |
3521 | { | |
3522 | struct kvm_userspace_memory_region kvm_userspace_mem; | |
3523 | int r = 0; | |
3524 | ||
79fac95e | 3525 | mutex_lock(&kvm->slots_lock); |
bfc6d222 | 3526 | if (kvm->arch.apic_access_page) |
f78e0e2e SY |
3527 | goto out; |
3528 | kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT; | |
3529 | kvm_userspace_mem.flags = 0; | |
3530 | kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL; | |
3531 | kvm_userspace_mem.memory_size = PAGE_SIZE; | |
3532 | r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0); | |
3533 | if (r) | |
3534 | goto out; | |
72dc67a6 | 3535 | |
bfc6d222 | 3536 | kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00); |
f78e0e2e | 3537 | out: |
79fac95e | 3538 | mutex_unlock(&kvm->slots_lock); |
f78e0e2e SY |
3539 | return r; |
3540 | } | |
3541 | ||
b7ebfb05 SY |
3542 | static int alloc_identity_pagetable(struct kvm *kvm) |
3543 | { | |
3544 | struct kvm_userspace_memory_region kvm_userspace_mem; | |
3545 | int r = 0; | |
3546 | ||
79fac95e | 3547 | mutex_lock(&kvm->slots_lock); |
b7ebfb05 SY |
3548 | if (kvm->arch.ept_identity_pagetable) |
3549 | goto out; | |
3550 | kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT; | |
3551 | kvm_userspace_mem.flags = 0; | |
b927a3ce SY |
3552 | kvm_userspace_mem.guest_phys_addr = |
3553 | kvm->arch.ept_identity_map_addr; | |
b7ebfb05 SY |
3554 | kvm_userspace_mem.memory_size = PAGE_SIZE; |
3555 | r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0); | |
3556 | if (r) | |
3557 | goto out; | |
3558 | ||
b7ebfb05 | 3559 | kvm->arch.ept_identity_pagetable = gfn_to_page(kvm, |
b927a3ce | 3560 | kvm->arch.ept_identity_map_addr >> PAGE_SHIFT); |
b7ebfb05 | 3561 | out: |
79fac95e | 3562 | mutex_unlock(&kvm->slots_lock); |
b7ebfb05 SY |
3563 | return r; |
3564 | } | |
3565 | ||
2384d2b3 SY |
3566 | static void allocate_vpid(struct vcpu_vmx *vmx) |
3567 | { | |
3568 | int vpid; | |
3569 | ||
3570 | vmx->vpid = 0; | |
919818ab | 3571 | if (!enable_vpid) |
2384d2b3 SY |
3572 | return; |
3573 | spin_lock(&vmx_vpid_lock); | |
3574 | vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS); | |
3575 | if (vpid < VMX_NR_VPIDS) { | |
3576 | vmx->vpid = vpid; | |
3577 | __set_bit(vpid, vmx_vpid_bitmap); | |
3578 | } | |
3579 | spin_unlock(&vmx_vpid_lock); | |
3580 | } | |
3581 | ||
cdbecfc3 LJ |
3582 | static void free_vpid(struct vcpu_vmx *vmx) |
3583 | { | |
3584 | if (!enable_vpid) | |
3585 | return; | |
3586 | spin_lock(&vmx_vpid_lock); | |
3587 | if (vmx->vpid != 0) | |
3588 | __clear_bit(vmx->vpid, vmx_vpid_bitmap); | |
3589 | spin_unlock(&vmx_vpid_lock); | |
3590 | } | |
3591 | ||
5897297b | 3592 | static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr) |
25c5f225 | 3593 | { |
3e7c73e9 | 3594 | int f = sizeof(unsigned long); |
25c5f225 SY |
3595 | |
3596 | if (!cpu_has_vmx_msr_bitmap()) | |
3597 | return; | |
3598 | ||
3599 | /* | |
3600 | * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals | |
3601 | * have the write-low and read-high bitmap offsets the wrong way round. | |
3602 | * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. | |
3603 | */ | |
25c5f225 | 3604 | if (msr <= 0x1fff) { |
3e7c73e9 AK |
3605 | __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */ |
3606 | __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */ | |
25c5f225 SY |
3607 | } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { |
3608 | msr &= 0x1fff; | |
3e7c73e9 AK |
3609 | __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */ |
3610 | __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */ | |
25c5f225 | 3611 | } |
25c5f225 SY |
3612 | } |
3613 | ||
5897297b AK |
3614 | static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only) |
3615 | { | |
3616 | if (!longmode_only) | |
3617 | __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr); | |
3618 | __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr); | |
3619 | } | |
3620 | ||
a3a8ff8e NHE |
3621 | /* |
3622 | * Set up the vmcs's constant host-state fields, i.e., host-state fields that | |
3623 | * will not change in the lifetime of the guest. | |
3624 | * Note that host-state that does change is set elsewhere. E.g., host-state | |
3625 | * that is set differently for each CPU is set in vmx_vcpu_load(), not here. | |
3626 | */ | |
3627 | static void vmx_set_constant_host_state(void) | |
3628 | { | |
3629 | u32 low32, high32; | |
3630 | unsigned long tmpl; | |
3631 | struct desc_ptr dt; | |
3632 | ||
3633 | vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS); /* 22.2.3 */ | |
3634 | vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */ | |
3635 | vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */ | |
3636 | ||
3637 | vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */ | |
3638 | vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ | |
3639 | vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */ | |
3640 | vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ | |
3641 | vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */ | |
3642 | ||
3643 | native_store_idt(&dt); | |
3644 | vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */ | |
3645 | ||
3646 | asm("mov $.Lkvm_vmx_return, %0" : "=r"(tmpl)); | |
3647 | vmcs_writel(HOST_RIP, tmpl); /* 22.2.5 */ | |
3648 | ||
3649 | rdmsr(MSR_IA32_SYSENTER_CS, low32, high32); | |
3650 | vmcs_write32(HOST_IA32_SYSENTER_CS, low32); | |
3651 | rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl); | |
3652 | vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */ | |
3653 | ||
3654 | if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) { | |
3655 | rdmsr(MSR_IA32_CR_PAT, low32, high32); | |
3656 | vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32)); | |
3657 | } | |
3658 | } | |
3659 | ||
bf8179a0 NHE |
3660 | static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx) |
3661 | { | |
3662 | vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS; | |
3663 | if (enable_ept) | |
3664 | vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE; | |
fe3ef05c NHE |
3665 | if (is_guest_mode(&vmx->vcpu)) |
3666 | vmx->vcpu.arch.cr4_guest_owned_bits &= | |
3667 | ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask; | |
bf8179a0 NHE |
3668 | vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits); |
3669 | } | |
3670 | ||
3671 | static u32 vmx_exec_control(struct vcpu_vmx *vmx) | |
3672 | { | |
3673 | u32 exec_control = vmcs_config.cpu_based_exec_ctrl; | |
3674 | if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) { | |
3675 | exec_control &= ~CPU_BASED_TPR_SHADOW; | |
3676 | #ifdef CONFIG_X86_64 | |
3677 | exec_control |= CPU_BASED_CR8_STORE_EXITING | | |
3678 | CPU_BASED_CR8_LOAD_EXITING; | |
3679 | #endif | |
3680 | } | |
3681 | if (!enable_ept) | |
3682 | exec_control |= CPU_BASED_CR3_STORE_EXITING | | |
3683 | CPU_BASED_CR3_LOAD_EXITING | | |
3684 | CPU_BASED_INVLPG_EXITING; | |
3685 | return exec_control; | |
3686 | } | |
3687 | ||
3688 | static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx) | |
3689 | { | |
3690 | u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl; | |
3691 | if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) | |
3692 | exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
3693 | if (vmx->vpid == 0) | |
3694 | exec_control &= ~SECONDARY_EXEC_ENABLE_VPID; | |
3695 | if (!enable_ept) { | |
3696 | exec_control &= ~SECONDARY_EXEC_ENABLE_EPT; | |
3697 | enable_unrestricted_guest = 0; | |
3698 | } | |
3699 | if (!enable_unrestricted_guest) | |
3700 | exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST; | |
3701 | if (!ple_gap) | |
3702 | exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING; | |
3703 | return exec_control; | |
3704 | } | |
3705 | ||
ce88decf XG |
3706 | static void ept_set_mmio_spte_mask(void) |
3707 | { | |
3708 | /* | |
3709 | * EPT Misconfigurations can be generated if the value of bits 2:0 | |
3710 | * of an EPT paging-structure entry is 110b (write/execute). | |
3711 | * Also, magic bits (0xffull << 49) is set to quickly identify mmio | |
3712 | * spte. | |
3713 | */ | |
3714 | kvm_mmu_set_mmio_spte_mask(0xffull << 49 | 0x6ull); | |
3715 | } | |
3716 | ||
6aa8b732 AK |
3717 | /* |
3718 | * Sets up the vmcs for emulated real mode. | |
3719 | */ | |
8b9cf98c | 3720 | static int vmx_vcpu_setup(struct vcpu_vmx *vmx) |
6aa8b732 | 3721 | { |
2e4ce7f5 | 3722 | #ifdef CONFIG_X86_64 |
6aa8b732 | 3723 | unsigned long a; |
2e4ce7f5 | 3724 | #endif |
6aa8b732 | 3725 | int i; |
6aa8b732 | 3726 | |
6aa8b732 | 3727 | /* I/O */ |
3e7c73e9 AK |
3728 | vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a)); |
3729 | vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b)); | |
6aa8b732 | 3730 | |
25c5f225 | 3731 | if (cpu_has_vmx_msr_bitmap()) |
5897297b | 3732 | vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy)); |
25c5f225 | 3733 | |
6aa8b732 AK |
3734 | vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */ |
3735 | ||
6aa8b732 | 3736 | /* Control */ |
1c3d14fe YS |
3737 | vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, |
3738 | vmcs_config.pin_based_exec_ctrl); | |
6e5d865c | 3739 | |
bf8179a0 | 3740 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx)); |
6aa8b732 | 3741 | |
83ff3b9d | 3742 | if (cpu_has_secondary_exec_ctrls()) { |
bf8179a0 NHE |
3743 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, |
3744 | vmx_secondary_exec_control(vmx)); | |
83ff3b9d | 3745 | } |
f78e0e2e | 3746 | |
4b8d54f9 ZE |
3747 | if (ple_gap) { |
3748 | vmcs_write32(PLE_GAP, ple_gap); | |
3749 | vmcs_write32(PLE_WINDOW, ple_window); | |
3750 | } | |
3751 | ||
c3707958 XG |
3752 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0); |
3753 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0); | |
6aa8b732 AK |
3754 | vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */ |
3755 | ||
9581d442 AK |
3756 | vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */ |
3757 | vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */ | |
a3a8ff8e | 3758 | vmx_set_constant_host_state(); |
05b3e0c2 | 3759 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
3760 | rdmsrl(MSR_FS_BASE, a); |
3761 | vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */ | |
3762 | rdmsrl(MSR_GS_BASE, a); | |
3763 | vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */ | |
3764 | #else | |
3765 | vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */ | |
3766 | vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */ | |
3767 | #endif | |
3768 | ||
2cc51560 ED |
3769 | vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0); |
3770 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0); | |
61d2ef2c | 3771 | vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host)); |
2cc51560 | 3772 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0); |
61d2ef2c | 3773 | vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest)); |
6aa8b732 | 3774 | |
468d472f | 3775 | if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) { |
a3a8ff8e NHE |
3776 | u32 msr_low, msr_high; |
3777 | u64 host_pat; | |
468d472f SY |
3778 | rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high); |
3779 | host_pat = msr_low | ((u64) msr_high << 32); | |
3780 | /* Write the default value follow host pat */ | |
3781 | vmcs_write64(GUEST_IA32_PAT, host_pat); | |
3782 | /* Keep arch.pat sync with GUEST_IA32_PAT */ | |
3783 | vmx->vcpu.arch.pat = host_pat; | |
3784 | } | |
3785 | ||
6aa8b732 AK |
3786 | for (i = 0; i < NR_VMX_MSR; ++i) { |
3787 | u32 index = vmx_msr_index[i]; | |
3788 | u32 data_low, data_high; | |
a2fa3e9f | 3789 | int j = vmx->nmsrs; |
6aa8b732 AK |
3790 | |
3791 | if (rdmsr_safe(index, &data_low, &data_high) < 0) | |
3792 | continue; | |
432bd6cb AK |
3793 | if (wrmsr_safe(index, data_low, data_high) < 0) |
3794 | continue; | |
26bb0981 AK |
3795 | vmx->guest_msrs[j].index = i; |
3796 | vmx->guest_msrs[j].data = 0; | |
d5696725 | 3797 | vmx->guest_msrs[j].mask = -1ull; |
a2fa3e9f | 3798 | ++vmx->nmsrs; |
6aa8b732 | 3799 | } |
6aa8b732 | 3800 | |
1c3d14fe | 3801 | vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl); |
6aa8b732 AK |
3802 | |
3803 | /* 22.2.1, 20.8.1 */ | |
1c3d14fe YS |
3804 | vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl); |
3805 | ||
e00c8cf2 | 3806 | vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL); |
bf8179a0 | 3807 | set_cr4_guest_host_mask(vmx); |
e00c8cf2 | 3808 | |
99e3e30a | 3809 | kvm_write_tsc(&vmx->vcpu, 0); |
f78e0e2e | 3810 | |
e00c8cf2 AK |
3811 | return 0; |
3812 | } | |
3813 | ||
3814 | static int vmx_vcpu_reset(struct kvm_vcpu *vcpu) | |
3815 | { | |
3816 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
3817 | u64 msr; | |
4b9d3a04 | 3818 | int ret; |
e00c8cf2 | 3819 | |
5fdbf976 | 3820 | vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)); |
e00c8cf2 | 3821 | |
7ffd92c5 | 3822 | vmx->rmode.vm86_active = 0; |
e00c8cf2 | 3823 | |
3b86cd99 JK |
3824 | vmx->soft_vnmi_blocked = 0; |
3825 | ||
ad312c7c | 3826 | vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val(); |
2d3ad1f4 | 3827 | kvm_set_cr8(&vmx->vcpu, 0); |
e00c8cf2 | 3828 | msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE; |
c5af89b6 | 3829 | if (kvm_vcpu_is_bsp(&vmx->vcpu)) |
e00c8cf2 AK |
3830 | msr |= MSR_IA32_APICBASE_BSP; |
3831 | kvm_set_apic_base(&vmx->vcpu, msr); | |
3832 | ||
10ab25cd JK |
3833 | ret = fx_init(&vmx->vcpu); |
3834 | if (ret != 0) | |
3835 | goto out; | |
e00c8cf2 | 3836 | |
2fb92db1 AK |
3837 | vmx_segment_cache_clear(vmx); |
3838 | ||
5706be0d | 3839 | seg_setup(VCPU_SREG_CS); |
e00c8cf2 AK |
3840 | /* |
3841 | * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode | |
3842 | * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh. | |
3843 | */ | |
c5af89b6 | 3844 | if (kvm_vcpu_is_bsp(&vmx->vcpu)) { |
e00c8cf2 AK |
3845 | vmcs_write16(GUEST_CS_SELECTOR, 0xf000); |
3846 | vmcs_writel(GUEST_CS_BASE, 0x000f0000); | |
3847 | } else { | |
ad312c7c ZX |
3848 | vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8); |
3849 | vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12); | |
e00c8cf2 | 3850 | } |
e00c8cf2 AK |
3851 | |
3852 | seg_setup(VCPU_SREG_DS); | |
3853 | seg_setup(VCPU_SREG_ES); | |
3854 | seg_setup(VCPU_SREG_FS); | |
3855 | seg_setup(VCPU_SREG_GS); | |
3856 | seg_setup(VCPU_SREG_SS); | |
3857 | ||
3858 | vmcs_write16(GUEST_TR_SELECTOR, 0); | |
3859 | vmcs_writel(GUEST_TR_BASE, 0); | |
3860 | vmcs_write32(GUEST_TR_LIMIT, 0xffff); | |
3861 | vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); | |
3862 | ||
3863 | vmcs_write16(GUEST_LDTR_SELECTOR, 0); | |
3864 | vmcs_writel(GUEST_LDTR_BASE, 0); | |
3865 | vmcs_write32(GUEST_LDTR_LIMIT, 0xffff); | |
3866 | vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082); | |
3867 | ||
3868 | vmcs_write32(GUEST_SYSENTER_CS, 0); | |
3869 | vmcs_writel(GUEST_SYSENTER_ESP, 0); | |
3870 | vmcs_writel(GUEST_SYSENTER_EIP, 0); | |
3871 | ||
3872 | vmcs_writel(GUEST_RFLAGS, 0x02); | |
c5af89b6 | 3873 | if (kvm_vcpu_is_bsp(&vmx->vcpu)) |
5fdbf976 | 3874 | kvm_rip_write(vcpu, 0xfff0); |
e00c8cf2 | 3875 | else |
5fdbf976 MT |
3876 | kvm_rip_write(vcpu, 0); |
3877 | kvm_register_write(vcpu, VCPU_REGS_RSP, 0); | |
e00c8cf2 | 3878 | |
e00c8cf2 AK |
3879 | vmcs_writel(GUEST_DR7, 0x400); |
3880 | ||
3881 | vmcs_writel(GUEST_GDTR_BASE, 0); | |
3882 | vmcs_write32(GUEST_GDTR_LIMIT, 0xffff); | |
3883 | ||
3884 | vmcs_writel(GUEST_IDTR_BASE, 0); | |
3885 | vmcs_write32(GUEST_IDTR_LIMIT, 0xffff); | |
3886 | ||
443381a8 | 3887 | vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE); |
e00c8cf2 AK |
3888 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0); |
3889 | vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0); | |
3890 | ||
e00c8cf2 AK |
3891 | /* Special registers */ |
3892 | vmcs_write64(GUEST_IA32_DEBUGCTL, 0); | |
3893 | ||
3894 | setup_msrs(vmx); | |
3895 | ||
6aa8b732 AK |
3896 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */ |
3897 | ||
f78e0e2e SY |
3898 | if (cpu_has_vmx_tpr_shadow()) { |
3899 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0); | |
3900 | if (vm_need_tpr_shadow(vmx->vcpu.kvm)) | |
3901 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, | |
afc20184 | 3902 | __pa(vmx->vcpu.arch.apic->regs)); |
f78e0e2e SY |
3903 | vmcs_write32(TPR_THRESHOLD, 0); |
3904 | } | |
3905 | ||
3906 | if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) | |
3907 | vmcs_write64(APIC_ACCESS_ADDR, | |
bfc6d222 | 3908 | page_to_phys(vmx->vcpu.kvm->arch.apic_access_page)); |
6aa8b732 | 3909 | |
2384d2b3 SY |
3910 | if (vmx->vpid != 0) |
3911 | vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid); | |
3912 | ||
fa40052c | 3913 | vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET; |
4d4ec087 | 3914 | vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */ |
8b9cf98c | 3915 | vmx_set_cr4(&vmx->vcpu, 0); |
8b9cf98c | 3916 | vmx_set_efer(&vmx->vcpu, 0); |
8b9cf98c RR |
3917 | vmx_fpu_activate(&vmx->vcpu); |
3918 | update_exception_bitmap(&vmx->vcpu); | |
6aa8b732 | 3919 | |
b9d762fa | 3920 | vpid_sync_context(vmx); |
2384d2b3 | 3921 | |
3200f405 | 3922 | ret = 0; |
6aa8b732 | 3923 | |
a89a8fb9 MG |
3924 | /* HACK: Don't enable emulation on guest boot/reset */ |
3925 | vmx->emulation_required = 0; | |
3926 | ||
6aa8b732 AK |
3927 | out: |
3928 | return ret; | |
3929 | } | |
3930 | ||
b6f1250e NHE |
3931 | /* |
3932 | * In nested virtualization, check if L1 asked to exit on external interrupts. | |
3933 | * For most existing hypervisors, this will always return true. | |
3934 | */ | |
3935 | static bool nested_exit_on_intr(struct kvm_vcpu *vcpu) | |
3936 | { | |
3937 | return get_vmcs12(vcpu)->pin_based_vm_exec_control & | |
3938 | PIN_BASED_EXT_INTR_MASK; | |
3939 | } | |
3940 | ||
3b86cd99 JK |
3941 | static void enable_irq_window(struct kvm_vcpu *vcpu) |
3942 | { | |
3943 | u32 cpu_based_vm_exec_control; | |
b6f1250e NHE |
3944 | if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) |
3945 | /* We can get here when nested_run_pending caused | |
3946 | * vmx_interrupt_allowed() to return false. In this case, do | |
3947 | * nothing - the interrupt will be injected later. | |
3948 | */ | |
3949 | return; | |
3b86cd99 JK |
3950 | |
3951 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
3952 | cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING; | |
3953 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
3954 | } | |
3955 | ||
3956 | static void enable_nmi_window(struct kvm_vcpu *vcpu) | |
3957 | { | |
3958 | u32 cpu_based_vm_exec_control; | |
3959 | ||
3960 | if (!cpu_has_virtual_nmis()) { | |
3961 | enable_irq_window(vcpu); | |
3962 | return; | |
3963 | } | |
3964 | ||
30bd0c4c AK |
3965 | if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) { |
3966 | enable_irq_window(vcpu); | |
3967 | return; | |
3968 | } | |
3b86cd99 JK |
3969 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); |
3970 | cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING; | |
3971 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
3972 | } | |
3973 | ||
66fd3f7f | 3974 | static void vmx_inject_irq(struct kvm_vcpu *vcpu) |
85f455f7 | 3975 | { |
9c8cba37 | 3976 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
66fd3f7f GN |
3977 | uint32_t intr; |
3978 | int irq = vcpu->arch.interrupt.nr; | |
9c8cba37 | 3979 | |
229456fc | 3980 | trace_kvm_inj_virq(irq); |
2714d1d3 | 3981 | |
fa89a817 | 3982 | ++vcpu->stat.irq_injections; |
7ffd92c5 | 3983 | if (vmx->rmode.vm86_active) { |
71f9833b SH |
3984 | int inc_eip = 0; |
3985 | if (vcpu->arch.interrupt.soft) | |
3986 | inc_eip = vcpu->arch.event_exit_inst_len; | |
3987 | if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE) | |
a92601bb | 3988 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
85f455f7 ED |
3989 | return; |
3990 | } | |
66fd3f7f GN |
3991 | intr = irq | INTR_INFO_VALID_MASK; |
3992 | if (vcpu->arch.interrupt.soft) { | |
3993 | intr |= INTR_TYPE_SOFT_INTR; | |
3994 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, | |
3995 | vmx->vcpu.arch.event_exit_inst_len); | |
3996 | } else | |
3997 | intr |= INTR_TYPE_EXT_INTR; | |
3998 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr); | |
443381a8 | 3999 | vmx_clear_hlt(vcpu); |
85f455f7 ED |
4000 | } |
4001 | ||
f08864b4 SY |
4002 | static void vmx_inject_nmi(struct kvm_vcpu *vcpu) |
4003 | { | |
66a5a347 JK |
4004 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
4005 | ||
0b6ac343 NHE |
4006 | if (is_guest_mode(vcpu)) |
4007 | return; | |
4008 | ||
3b86cd99 JK |
4009 | if (!cpu_has_virtual_nmis()) { |
4010 | /* | |
4011 | * Tracking the NMI-blocked state in software is built upon | |
4012 | * finding the next open IRQ window. This, in turn, depends on | |
4013 | * well-behaving guests: They have to keep IRQs disabled at | |
4014 | * least as long as the NMI handler runs. Otherwise we may | |
4015 | * cause NMI nesting, maybe breaking the guest. But as this is | |
4016 | * highly unlikely, we can live with the residual risk. | |
4017 | */ | |
4018 | vmx->soft_vnmi_blocked = 1; | |
4019 | vmx->vnmi_blocked_time = 0; | |
4020 | } | |
4021 | ||
487b391d | 4022 | ++vcpu->stat.nmi_injections; |
9d58b931 | 4023 | vmx->nmi_known_unmasked = false; |
7ffd92c5 | 4024 | if (vmx->rmode.vm86_active) { |
71f9833b | 4025 | if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE) |
a92601bb | 4026 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
66a5a347 JK |
4027 | return; |
4028 | } | |
f08864b4 SY |
4029 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, |
4030 | INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR); | |
443381a8 | 4031 | vmx_clear_hlt(vcpu); |
f08864b4 SY |
4032 | } |
4033 | ||
c4282df9 | 4034 | static int vmx_nmi_allowed(struct kvm_vcpu *vcpu) |
33f089ca | 4035 | { |
3b86cd99 | 4036 | if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked) |
c4282df9 | 4037 | return 0; |
33f089ca | 4038 | |
c4282df9 | 4039 | return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & |
30bd0c4c AK |
4040 | (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI |
4041 | | GUEST_INTR_STATE_NMI)); | |
33f089ca JK |
4042 | } |
4043 | ||
3cfc3092 JK |
4044 | static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu) |
4045 | { | |
4046 | if (!cpu_has_virtual_nmis()) | |
4047 | return to_vmx(vcpu)->soft_vnmi_blocked; | |
9d58b931 AK |
4048 | if (to_vmx(vcpu)->nmi_known_unmasked) |
4049 | return false; | |
c332c83a | 4050 | return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI; |
3cfc3092 JK |
4051 | } |
4052 | ||
4053 | static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked) | |
4054 | { | |
4055 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
4056 | ||
4057 | if (!cpu_has_virtual_nmis()) { | |
4058 | if (vmx->soft_vnmi_blocked != masked) { | |
4059 | vmx->soft_vnmi_blocked = masked; | |
4060 | vmx->vnmi_blocked_time = 0; | |
4061 | } | |
4062 | } else { | |
9d58b931 | 4063 | vmx->nmi_known_unmasked = !masked; |
3cfc3092 JK |
4064 | if (masked) |
4065 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, | |
4066 | GUEST_INTR_STATE_NMI); | |
4067 | else | |
4068 | vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO, | |
4069 | GUEST_INTR_STATE_NMI); | |
4070 | } | |
4071 | } | |
4072 | ||
78646121 GN |
4073 | static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu) |
4074 | { | |
b6f1250e NHE |
4075 | if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) { |
4076 | struct vmcs12 *vmcs12; | |
4077 | if (to_vmx(vcpu)->nested.nested_run_pending) | |
4078 | return 0; | |
4079 | nested_vmx_vmexit(vcpu); | |
4080 | vmcs12 = get_vmcs12(vcpu); | |
4081 | vmcs12->vm_exit_reason = EXIT_REASON_EXTERNAL_INTERRUPT; | |
4082 | vmcs12->vm_exit_intr_info = 0; | |
4083 | /* fall through to normal code, but now in L1, not L2 */ | |
4084 | } | |
4085 | ||
c4282df9 GN |
4086 | return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) && |
4087 | !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & | |
4088 | (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS)); | |
78646121 GN |
4089 | } |
4090 | ||
cbc94022 IE |
4091 | static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr) |
4092 | { | |
4093 | int ret; | |
4094 | struct kvm_userspace_memory_region tss_mem = { | |
6fe63979 | 4095 | .slot = TSS_PRIVATE_MEMSLOT, |
cbc94022 IE |
4096 | .guest_phys_addr = addr, |
4097 | .memory_size = PAGE_SIZE * 3, | |
4098 | .flags = 0, | |
4099 | }; | |
4100 | ||
4101 | ret = kvm_set_memory_region(kvm, &tss_mem, 0); | |
4102 | if (ret) | |
4103 | return ret; | |
bfc6d222 | 4104 | kvm->arch.tss_addr = addr; |
93ea5388 GN |
4105 | if (!init_rmode_tss(kvm)) |
4106 | return -ENOMEM; | |
4107 | ||
cbc94022 IE |
4108 | return 0; |
4109 | } | |
4110 | ||
6aa8b732 AK |
4111 | static int handle_rmode_exception(struct kvm_vcpu *vcpu, |
4112 | int vec, u32 err_code) | |
4113 | { | |
b3f37707 NK |
4114 | /* |
4115 | * Instruction with address size override prefix opcode 0x67 | |
4116 | * Cause the #SS fault with 0 error code in VM86 mode. | |
4117 | */ | |
4118 | if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) | |
51d8b661 | 4119 | if (emulate_instruction(vcpu, 0) == EMULATE_DONE) |
6aa8b732 | 4120 | return 1; |
77ab6db0 JK |
4121 | /* |
4122 | * Forward all other exceptions that are valid in real mode. | |
4123 | * FIXME: Breaks guest debugging in real mode, needs to be fixed with | |
4124 | * the required debugging infrastructure rework. | |
4125 | */ | |
4126 | switch (vec) { | |
77ab6db0 | 4127 | case DB_VECTOR: |
d0bfb940 JK |
4128 | if (vcpu->guest_debug & |
4129 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) | |
4130 | return 0; | |
4131 | kvm_queue_exception(vcpu, vec); | |
4132 | return 1; | |
77ab6db0 | 4133 | case BP_VECTOR: |
c573cd22 JK |
4134 | /* |
4135 | * Update instruction length as we may reinject the exception | |
4136 | * from user space while in guest debugging mode. | |
4137 | */ | |
4138 | to_vmx(vcpu)->vcpu.arch.event_exit_inst_len = | |
4139 | vmcs_read32(VM_EXIT_INSTRUCTION_LEN); | |
d0bfb940 JK |
4140 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) |
4141 | return 0; | |
4142 | /* fall through */ | |
4143 | case DE_VECTOR: | |
77ab6db0 JK |
4144 | case OF_VECTOR: |
4145 | case BR_VECTOR: | |
4146 | case UD_VECTOR: | |
4147 | case DF_VECTOR: | |
4148 | case SS_VECTOR: | |
4149 | case GP_VECTOR: | |
4150 | case MF_VECTOR: | |
4151 | kvm_queue_exception(vcpu, vec); | |
4152 | return 1; | |
4153 | } | |
6aa8b732 AK |
4154 | return 0; |
4155 | } | |
4156 | ||
a0861c02 AK |
4157 | /* |
4158 | * Trigger machine check on the host. We assume all the MSRs are already set up | |
4159 | * by the CPU and that we still run on the same CPU as the MCE occurred on. | |
4160 | * We pass a fake environment to the machine check handler because we want | |
4161 | * the guest to be always treated like user space, no matter what context | |
4162 | * it used internally. | |
4163 | */ | |
4164 | static void kvm_machine_check(void) | |
4165 | { | |
4166 | #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64) | |
4167 | struct pt_regs regs = { | |
4168 | .cs = 3, /* Fake ring 3 no matter what the guest ran on */ | |
4169 | .flags = X86_EFLAGS_IF, | |
4170 | }; | |
4171 | ||
4172 | do_machine_check(®s, 0); | |
4173 | #endif | |
4174 | } | |
4175 | ||
851ba692 | 4176 | static int handle_machine_check(struct kvm_vcpu *vcpu) |
a0861c02 AK |
4177 | { |
4178 | /* already handled by vcpu_run */ | |
4179 | return 1; | |
4180 | } | |
4181 | ||
851ba692 | 4182 | static int handle_exception(struct kvm_vcpu *vcpu) |
6aa8b732 | 4183 | { |
1155f76a | 4184 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
851ba692 | 4185 | struct kvm_run *kvm_run = vcpu->run; |
d0bfb940 | 4186 | u32 intr_info, ex_no, error_code; |
42dbaa5a | 4187 | unsigned long cr2, rip, dr6; |
6aa8b732 AK |
4188 | u32 vect_info; |
4189 | enum emulation_result er; | |
4190 | ||
1155f76a | 4191 | vect_info = vmx->idt_vectoring_info; |
88786475 | 4192 | intr_info = vmx->exit_intr_info; |
6aa8b732 | 4193 | |
a0861c02 | 4194 | if (is_machine_check(intr_info)) |
851ba692 | 4195 | return handle_machine_check(vcpu); |
a0861c02 | 4196 | |
6aa8b732 | 4197 | if ((vect_info & VECTORING_INFO_VALID_MASK) && |
65ac7264 AK |
4198 | !is_page_fault(intr_info)) { |
4199 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
4200 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX; | |
4201 | vcpu->run->internal.ndata = 2; | |
4202 | vcpu->run->internal.data[0] = vect_info; | |
4203 | vcpu->run->internal.data[1] = intr_info; | |
4204 | return 0; | |
4205 | } | |
6aa8b732 | 4206 | |
e4a41889 | 4207 | if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR) |
1b6269db | 4208 | return 1; /* already handled by vmx_vcpu_run() */ |
2ab455cc AL |
4209 | |
4210 | if (is_no_device(intr_info)) { | |
5fd86fcf | 4211 | vmx_fpu_activate(vcpu); |
2ab455cc AL |
4212 | return 1; |
4213 | } | |
4214 | ||
7aa81cc0 | 4215 | if (is_invalid_opcode(intr_info)) { |
51d8b661 | 4216 | er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD); |
7aa81cc0 | 4217 | if (er != EMULATE_DONE) |
7ee5d940 | 4218 | kvm_queue_exception(vcpu, UD_VECTOR); |
7aa81cc0 AL |
4219 | return 1; |
4220 | } | |
4221 | ||
6aa8b732 | 4222 | error_code = 0; |
2e11384c | 4223 | if (intr_info & INTR_INFO_DELIVER_CODE_MASK) |
6aa8b732 AK |
4224 | error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE); |
4225 | if (is_page_fault(intr_info)) { | |
1439442c | 4226 | /* EPT won't cause page fault directly */ |
cf3ace79 | 4227 | BUG_ON(enable_ept); |
6aa8b732 | 4228 | cr2 = vmcs_readl(EXIT_QUALIFICATION); |
229456fc MT |
4229 | trace_kvm_page_fault(cr2, error_code); |
4230 | ||
3298b75c | 4231 | if (kvm_event_needs_reinjection(vcpu)) |
577bdc49 | 4232 | kvm_mmu_unprotect_page_virt(vcpu, cr2); |
dc25e89e | 4233 | return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0); |
6aa8b732 AK |
4234 | } |
4235 | ||
7ffd92c5 | 4236 | if (vmx->rmode.vm86_active && |
6aa8b732 | 4237 | handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK, |
72d6e5a0 | 4238 | error_code)) { |
ad312c7c ZX |
4239 | if (vcpu->arch.halt_request) { |
4240 | vcpu->arch.halt_request = 0; | |
72d6e5a0 AK |
4241 | return kvm_emulate_halt(vcpu); |
4242 | } | |
6aa8b732 | 4243 | return 1; |
72d6e5a0 | 4244 | } |
6aa8b732 | 4245 | |
d0bfb940 | 4246 | ex_no = intr_info & INTR_INFO_VECTOR_MASK; |
42dbaa5a JK |
4247 | switch (ex_no) { |
4248 | case DB_VECTOR: | |
4249 | dr6 = vmcs_readl(EXIT_QUALIFICATION); | |
4250 | if (!(vcpu->guest_debug & | |
4251 | (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) { | |
4252 | vcpu->arch.dr6 = dr6 | DR6_FIXED_1; | |
4253 | kvm_queue_exception(vcpu, DB_VECTOR); | |
4254 | return 1; | |
4255 | } | |
4256 | kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1; | |
4257 | kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7); | |
4258 | /* fall through */ | |
4259 | case BP_VECTOR: | |
c573cd22 JK |
4260 | /* |
4261 | * Update instruction length as we may reinject #BP from | |
4262 | * user space while in guest debugging mode. Reading it for | |
4263 | * #DB as well causes no harm, it is not used in that case. | |
4264 | */ | |
4265 | vmx->vcpu.arch.event_exit_inst_len = | |
4266 | vmcs_read32(VM_EXIT_INSTRUCTION_LEN); | |
6aa8b732 | 4267 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
0a434bb2 | 4268 | rip = kvm_rip_read(vcpu); |
d0bfb940 JK |
4269 | kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip; |
4270 | kvm_run->debug.arch.exception = ex_no; | |
42dbaa5a JK |
4271 | break; |
4272 | default: | |
d0bfb940 JK |
4273 | kvm_run->exit_reason = KVM_EXIT_EXCEPTION; |
4274 | kvm_run->ex.exception = ex_no; | |
4275 | kvm_run->ex.error_code = error_code; | |
42dbaa5a | 4276 | break; |
6aa8b732 | 4277 | } |
6aa8b732 AK |
4278 | return 0; |
4279 | } | |
4280 | ||
851ba692 | 4281 | static int handle_external_interrupt(struct kvm_vcpu *vcpu) |
6aa8b732 | 4282 | { |
1165f5fe | 4283 | ++vcpu->stat.irq_exits; |
6aa8b732 AK |
4284 | return 1; |
4285 | } | |
4286 | ||
851ba692 | 4287 | static int handle_triple_fault(struct kvm_vcpu *vcpu) |
988ad74f | 4288 | { |
851ba692 | 4289 | vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; |
988ad74f AK |
4290 | return 0; |
4291 | } | |
6aa8b732 | 4292 | |
851ba692 | 4293 | static int handle_io(struct kvm_vcpu *vcpu) |
6aa8b732 | 4294 | { |
bfdaab09 | 4295 | unsigned long exit_qualification; |
34c33d16 | 4296 | int size, in, string; |
039576c0 | 4297 | unsigned port; |
6aa8b732 | 4298 | |
bfdaab09 | 4299 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
039576c0 | 4300 | string = (exit_qualification & 16) != 0; |
cf8f70bf | 4301 | in = (exit_qualification & 8) != 0; |
e70669ab | 4302 | |
cf8f70bf | 4303 | ++vcpu->stat.io_exits; |
e70669ab | 4304 | |
cf8f70bf | 4305 | if (string || in) |
51d8b661 | 4306 | return emulate_instruction(vcpu, 0) == EMULATE_DONE; |
e70669ab | 4307 | |
cf8f70bf GN |
4308 | port = exit_qualification >> 16; |
4309 | size = (exit_qualification & 7) + 1; | |
e93f36bc | 4310 | skip_emulated_instruction(vcpu); |
cf8f70bf GN |
4311 | |
4312 | return kvm_fast_pio_out(vcpu, size, port); | |
6aa8b732 AK |
4313 | } |
4314 | ||
102d8325 IM |
4315 | static void |
4316 | vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
4317 | { | |
4318 | /* | |
4319 | * Patch in the VMCALL instruction: | |
4320 | */ | |
4321 | hypercall[0] = 0x0f; | |
4322 | hypercall[1] = 0x01; | |
4323 | hypercall[2] = 0xc1; | |
102d8325 IM |
4324 | } |
4325 | ||
eeadf9e7 NHE |
4326 | /* called to set cr0 as approriate for a mov-to-cr0 exit. */ |
4327 | static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val) | |
4328 | { | |
4329 | if (to_vmx(vcpu)->nested.vmxon && | |
4330 | ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON)) | |
4331 | return 1; | |
4332 | ||
4333 | if (is_guest_mode(vcpu)) { | |
4334 | /* | |
4335 | * We get here when L2 changed cr0 in a way that did not change | |
4336 | * any of L1's shadowed bits (see nested_vmx_exit_handled_cr), | |
4337 | * but did change L0 shadowed bits. This can currently happen | |
4338 | * with the TS bit: L0 may want to leave TS on (for lazy fpu | |
4339 | * loading) while pretending to allow the guest to change it. | |
4340 | */ | |
4341 | if (kvm_set_cr0(vcpu, (val & vcpu->arch.cr0_guest_owned_bits) | | |
4342 | (vcpu->arch.cr0 & ~vcpu->arch.cr0_guest_owned_bits))) | |
4343 | return 1; | |
4344 | vmcs_writel(CR0_READ_SHADOW, val); | |
4345 | return 0; | |
4346 | } else | |
4347 | return kvm_set_cr0(vcpu, val); | |
4348 | } | |
4349 | ||
4350 | static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val) | |
4351 | { | |
4352 | if (is_guest_mode(vcpu)) { | |
4353 | if (kvm_set_cr4(vcpu, (val & vcpu->arch.cr4_guest_owned_bits) | | |
4354 | (vcpu->arch.cr4 & ~vcpu->arch.cr4_guest_owned_bits))) | |
4355 | return 1; | |
4356 | vmcs_writel(CR4_READ_SHADOW, val); | |
4357 | return 0; | |
4358 | } else | |
4359 | return kvm_set_cr4(vcpu, val); | |
4360 | } | |
4361 | ||
4362 | /* called to set cr0 as approriate for clts instruction exit. */ | |
4363 | static void handle_clts(struct kvm_vcpu *vcpu) | |
4364 | { | |
4365 | if (is_guest_mode(vcpu)) { | |
4366 | /* | |
4367 | * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS | |
4368 | * but we did (!fpu_active). We need to keep GUEST_CR0.TS on, | |
4369 | * just pretend it's off (also in arch.cr0 for fpu_activate). | |
4370 | */ | |
4371 | vmcs_writel(CR0_READ_SHADOW, | |
4372 | vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS); | |
4373 | vcpu->arch.cr0 &= ~X86_CR0_TS; | |
4374 | } else | |
4375 | vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS)); | |
4376 | } | |
4377 | ||
851ba692 | 4378 | static int handle_cr(struct kvm_vcpu *vcpu) |
6aa8b732 | 4379 | { |
229456fc | 4380 | unsigned long exit_qualification, val; |
6aa8b732 AK |
4381 | int cr; |
4382 | int reg; | |
49a9b07e | 4383 | int err; |
6aa8b732 | 4384 | |
bfdaab09 | 4385 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
6aa8b732 AK |
4386 | cr = exit_qualification & 15; |
4387 | reg = (exit_qualification >> 8) & 15; | |
4388 | switch ((exit_qualification >> 4) & 3) { | |
4389 | case 0: /* mov to cr */ | |
229456fc MT |
4390 | val = kvm_register_read(vcpu, reg); |
4391 | trace_kvm_cr_write(cr, val); | |
6aa8b732 AK |
4392 | switch (cr) { |
4393 | case 0: | |
eeadf9e7 | 4394 | err = handle_set_cr0(vcpu, val); |
db8fcefa | 4395 | kvm_complete_insn_gp(vcpu, err); |
6aa8b732 AK |
4396 | return 1; |
4397 | case 3: | |
2390218b | 4398 | err = kvm_set_cr3(vcpu, val); |
db8fcefa | 4399 | kvm_complete_insn_gp(vcpu, err); |
6aa8b732 AK |
4400 | return 1; |
4401 | case 4: | |
eeadf9e7 | 4402 | err = handle_set_cr4(vcpu, val); |
db8fcefa | 4403 | kvm_complete_insn_gp(vcpu, err); |
6aa8b732 | 4404 | return 1; |
0a5fff19 GN |
4405 | case 8: { |
4406 | u8 cr8_prev = kvm_get_cr8(vcpu); | |
4407 | u8 cr8 = kvm_register_read(vcpu, reg); | |
eea1cff9 | 4408 | err = kvm_set_cr8(vcpu, cr8); |
db8fcefa | 4409 | kvm_complete_insn_gp(vcpu, err); |
0a5fff19 GN |
4410 | if (irqchip_in_kernel(vcpu->kvm)) |
4411 | return 1; | |
4412 | if (cr8_prev <= cr8) | |
4413 | return 1; | |
851ba692 | 4414 | vcpu->run->exit_reason = KVM_EXIT_SET_TPR; |
0a5fff19 GN |
4415 | return 0; |
4416 | } | |
6aa8b732 AK |
4417 | }; |
4418 | break; | |
25c4c276 | 4419 | case 2: /* clts */ |
eeadf9e7 | 4420 | handle_clts(vcpu); |
4d4ec087 | 4421 | trace_kvm_cr_write(0, kvm_read_cr0(vcpu)); |
25c4c276 | 4422 | skip_emulated_instruction(vcpu); |
6b52d186 | 4423 | vmx_fpu_activate(vcpu); |
25c4c276 | 4424 | return 1; |
6aa8b732 AK |
4425 | case 1: /*mov from cr*/ |
4426 | switch (cr) { | |
4427 | case 3: | |
9f8fe504 AK |
4428 | val = kvm_read_cr3(vcpu); |
4429 | kvm_register_write(vcpu, reg, val); | |
4430 | trace_kvm_cr_read(cr, val); | |
6aa8b732 AK |
4431 | skip_emulated_instruction(vcpu); |
4432 | return 1; | |
4433 | case 8: | |
229456fc MT |
4434 | val = kvm_get_cr8(vcpu); |
4435 | kvm_register_write(vcpu, reg, val); | |
4436 | trace_kvm_cr_read(cr, val); | |
6aa8b732 AK |
4437 | skip_emulated_instruction(vcpu); |
4438 | return 1; | |
4439 | } | |
4440 | break; | |
4441 | case 3: /* lmsw */ | |
a1f83a74 | 4442 | val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f; |
4d4ec087 | 4443 | trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val); |
a1f83a74 | 4444 | kvm_lmsw(vcpu, val); |
6aa8b732 AK |
4445 | |
4446 | skip_emulated_instruction(vcpu); | |
4447 | return 1; | |
4448 | default: | |
4449 | break; | |
4450 | } | |
851ba692 | 4451 | vcpu->run->exit_reason = 0; |
f0242478 | 4452 | pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n", |
6aa8b732 AK |
4453 | (int)(exit_qualification >> 4) & 3, cr); |
4454 | return 0; | |
4455 | } | |
4456 | ||
851ba692 | 4457 | static int handle_dr(struct kvm_vcpu *vcpu) |
6aa8b732 | 4458 | { |
bfdaab09 | 4459 | unsigned long exit_qualification; |
6aa8b732 AK |
4460 | int dr, reg; |
4461 | ||
f2483415 | 4462 | /* Do not handle if the CPL > 0, will trigger GP on re-entry */ |
0a79b009 AK |
4463 | if (!kvm_require_cpl(vcpu, 0)) |
4464 | return 1; | |
42dbaa5a JK |
4465 | dr = vmcs_readl(GUEST_DR7); |
4466 | if (dr & DR7_GD) { | |
4467 | /* | |
4468 | * As the vm-exit takes precedence over the debug trap, we | |
4469 | * need to emulate the latter, either for the host or the | |
4470 | * guest debugging itself. | |
4471 | */ | |
4472 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { | |
851ba692 AK |
4473 | vcpu->run->debug.arch.dr6 = vcpu->arch.dr6; |
4474 | vcpu->run->debug.arch.dr7 = dr; | |
4475 | vcpu->run->debug.arch.pc = | |
42dbaa5a JK |
4476 | vmcs_readl(GUEST_CS_BASE) + |
4477 | vmcs_readl(GUEST_RIP); | |
851ba692 AK |
4478 | vcpu->run->debug.arch.exception = DB_VECTOR; |
4479 | vcpu->run->exit_reason = KVM_EXIT_DEBUG; | |
42dbaa5a JK |
4480 | return 0; |
4481 | } else { | |
4482 | vcpu->arch.dr7 &= ~DR7_GD; | |
4483 | vcpu->arch.dr6 |= DR6_BD; | |
4484 | vmcs_writel(GUEST_DR7, vcpu->arch.dr7); | |
4485 | kvm_queue_exception(vcpu, DB_VECTOR); | |
4486 | return 1; | |
4487 | } | |
4488 | } | |
4489 | ||
bfdaab09 | 4490 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
42dbaa5a JK |
4491 | dr = exit_qualification & DEBUG_REG_ACCESS_NUM; |
4492 | reg = DEBUG_REG_ACCESS_REG(exit_qualification); | |
4493 | if (exit_qualification & TYPE_MOV_FROM_DR) { | |
020df079 GN |
4494 | unsigned long val; |
4495 | if (!kvm_get_dr(vcpu, dr, &val)) | |
4496 | kvm_register_write(vcpu, reg, val); | |
4497 | } else | |
4498 | kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]); | |
6aa8b732 AK |
4499 | skip_emulated_instruction(vcpu); |
4500 | return 1; | |
4501 | } | |
4502 | ||
020df079 GN |
4503 | static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val) |
4504 | { | |
4505 | vmcs_writel(GUEST_DR7, val); | |
4506 | } | |
4507 | ||
851ba692 | 4508 | static int handle_cpuid(struct kvm_vcpu *vcpu) |
6aa8b732 | 4509 | { |
06465c5a AK |
4510 | kvm_emulate_cpuid(vcpu); |
4511 | return 1; | |
6aa8b732 AK |
4512 | } |
4513 | ||
851ba692 | 4514 | static int handle_rdmsr(struct kvm_vcpu *vcpu) |
6aa8b732 | 4515 | { |
ad312c7c | 4516 | u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX]; |
6aa8b732 AK |
4517 | u64 data; |
4518 | ||
4519 | if (vmx_get_msr(vcpu, ecx, &data)) { | |
59200273 | 4520 | trace_kvm_msr_read_ex(ecx); |
c1a5d4f9 | 4521 | kvm_inject_gp(vcpu, 0); |
6aa8b732 AK |
4522 | return 1; |
4523 | } | |
4524 | ||
229456fc | 4525 | trace_kvm_msr_read(ecx, data); |
2714d1d3 | 4526 | |
6aa8b732 | 4527 | /* FIXME: handling of bits 32:63 of rax, rdx */ |
ad312c7c ZX |
4528 | vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u; |
4529 | vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u; | |
6aa8b732 AK |
4530 | skip_emulated_instruction(vcpu); |
4531 | return 1; | |
4532 | } | |
4533 | ||
851ba692 | 4534 | static int handle_wrmsr(struct kvm_vcpu *vcpu) |
6aa8b732 | 4535 | { |
ad312c7c ZX |
4536 | u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX]; |
4537 | u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u) | |
4538 | | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32); | |
6aa8b732 AK |
4539 | |
4540 | if (vmx_set_msr(vcpu, ecx, data) != 0) { | |
59200273 | 4541 | trace_kvm_msr_write_ex(ecx, data); |
c1a5d4f9 | 4542 | kvm_inject_gp(vcpu, 0); |
6aa8b732 AK |
4543 | return 1; |
4544 | } | |
4545 | ||
59200273 | 4546 | trace_kvm_msr_write(ecx, data); |
6aa8b732 AK |
4547 | skip_emulated_instruction(vcpu); |
4548 | return 1; | |
4549 | } | |
4550 | ||
851ba692 | 4551 | static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu) |
6e5d865c | 4552 | { |
3842d135 | 4553 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
6e5d865c YS |
4554 | return 1; |
4555 | } | |
4556 | ||
851ba692 | 4557 | static int handle_interrupt_window(struct kvm_vcpu *vcpu) |
6aa8b732 | 4558 | { |
85f455f7 ED |
4559 | u32 cpu_based_vm_exec_control; |
4560 | ||
4561 | /* clear pending irq */ | |
4562 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
4563 | cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING; | |
4564 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
2714d1d3 | 4565 | |
3842d135 AK |
4566 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
4567 | ||
a26bf12a | 4568 | ++vcpu->stat.irq_window_exits; |
2714d1d3 | 4569 | |
c1150d8c DL |
4570 | /* |
4571 | * If the user space waits to inject interrupts, exit as soon as | |
4572 | * possible | |
4573 | */ | |
8061823a | 4574 | if (!irqchip_in_kernel(vcpu->kvm) && |
851ba692 | 4575 | vcpu->run->request_interrupt_window && |
8061823a | 4576 | !kvm_cpu_has_interrupt(vcpu)) { |
851ba692 | 4577 | vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; |
c1150d8c DL |
4578 | return 0; |
4579 | } | |
6aa8b732 AK |
4580 | return 1; |
4581 | } | |
4582 | ||
851ba692 | 4583 | static int handle_halt(struct kvm_vcpu *vcpu) |
6aa8b732 AK |
4584 | { |
4585 | skip_emulated_instruction(vcpu); | |
d3bef15f | 4586 | return kvm_emulate_halt(vcpu); |
6aa8b732 AK |
4587 | } |
4588 | ||
851ba692 | 4589 | static int handle_vmcall(struct kvm_vcpu *vcpu) |
c21415e8 | 4590 | { |
510043da | 4591 | skip_emulated_instruction(vcpu); |
7aa81cc0 AL |
4592 | kvm_emulate_hypercall(vcpu); |
4593 | return 1; | |
c21415e8 IM |
4594 | } |
4595 | ||
ec25d5e6 GN |
4596 | static int handle_invd(struct kvm_vcpu *vcpu) |
4597 | { | |
51d8b661 | 4598 | return emulate_instruction(vcpu, 0) == EMULATE_DONE; |
ec25d5e6 GN |
4599 | } |
4600 | ||
851ba692 | 4601 | static int handle_invlpg(struct kvm_vcpu *vcpu) |
a7052897 | 4602 | { |
f9c617f6 | 4603 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
a7052897 MT |
4604 | |
4605 | kvm_mmu_invlpg(vcpu, exit_qualification); | |
4606 | skip_emulated_instruction(vcpu); | |
4607 | return 1; | |
4608 | } | |
4609 | ||
851ba692 | 4610 | static int handle_wbinvd(struct kvm_vcpu *vcpu) |
e5edaa01 ED |
4611 | { |
4612 | skip_emulated_instruction(vcpu); | |
f5f48ee1 | 4613 | kvm_emulate_wbinvd(vcpu); |
e5edaa01 ED |
4614 | return 1; |
4615 | } | |
4616 | ||
2acf923e DC |
4617 | static int handle_xsetbv(struct kvm_vcpu *vcpu) |
4618 | { | |
4619 | u64 new_bv = kvm_read_edx_eax(vcpu); | |
4620 | u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
4621 | ||
4622 | if (kvm_set_xcr(vcpu, index, new_bv) == 0) | |
4623 | skip_emulated_instruction(vcpu); | |
4624 | return 1; | |
4625 | } | |
4626 | ||
851ba692 | 4627 | static int handle_apic_access(struct kvm_vcpu *vcpu) |
f78e0e2e | 4628 | { |
58fbbf26 KT |
4629 | if (likely(fasteoi)) { |
4630 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
4631 | int access_type, offset; | |
4632 | ||
4633 | access_type = exit_qualification & APIC_ACCESS_TYPE; | |
4634 | offset = exit_qualification & APIC_ACCESS_OFFSET; | |
4635 | /* | |
4636 | * Sane guest uses MOV to write EOI, with written value | |
4637 | * not cared. So make a short-circuit here by avoiding | |
4638 | * heavy instruction emulation. | |
4639 | */ | |
4640 | if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) && | |
4641 | (offset == APIC_EOI)) { | |
4642 | kvm_lapic_set_eoi(vcpu); | |
4643 | skip_emulated_instruction(vcpu); | |
4644 | return 1; | |
4645 | } | |
4646 | } | |
51d8b661 | 4647 | return emulate_instruction(vcpu, 0) == EMULATE_DONE; |
f78e0e2e SY |
4648 | } |
4649 | ||
851ba692 | 4650 | static int handle_task_switch(struct kvm_vcpu *vcpu) |
37817f29 | 4651 | { |
60637aac | 4652 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
37817f29 | 4653 | unsigned long exit_qualification; |
e269fb21 JK |
4654 | bool has_error_code = false; |
4655 | u32 error_code = 0; | |
37817f29 | 4656 | u16 tss_selector; |
64a7ec06 GN |
4657 | int reason, type, idt_v; |
4658 | ||
4659 | idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK); | |
4660 | type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK); | |
37817f29 IE |
4661 | |
4662 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
4663 | ||
4664 | reason = (u32)exit_qualification >> 30; | |
64a7ec06 GN |
4665 | if (reason == TASK_SWITCH_GATE && idt_v) { |
4666 | switch (type) { | |
4667 | case INTR_TYPE_NMI_INTR: | |
4668 | vcpu->arch.nmi_injected = false; | |
654f06fc | 4669 | vmx_set_nmi_mask(vcpu, true); |
64a7ec06 GN |
4670 | break; |
4671 | case INTR_TYPE_EXT_INTR: | |
66fd3f7f | 4672 | case INTR_TYPE_SOFT_INTR: |
64a7ec06 GN |
4673 | kvm_clear_interrupt_queue(vcpu); |
4674 | break; | |
4675 | case INTR_TYPE_HARD_EXCEPTION: | |
e269fb21 JK |
4676 | if (vmx->idt_vectoring_info & |
4677 | VECTORING_INFO_DELIVER_CODE_MASK) { | |
4678 | has_error_code = true; | |
4679 | error_code = | |
4680 | vmcs_read32(IDT_VECTORING_ERROR_CODE); | |
4681 | } | |
4682 | /* fall through */ | |
64a7ec06 GN |
4683 | case INTR_TYPE_SOFT_EXCEPTION: |
4684 | kvm_clear_exception_queue(vcpu); | |
4685 | break; | |
4686 | default: | |
4687 | break; | |
4688 | } | |
60637aac | 4689 | } |
37817f29 IE |
4690 | tss_selector = exit_qualification; |
4691 | ||
64a7ec06 GN |
4692 | if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION && |
4693 | type != INTR_TYPE_EXT_INTR && | |
4694 | type != INTR_TYPE_NMI_INTR)) | |
4695 | skip_emulated_instruction(vcpu); | |
4696 | ||
acb54517 GN |
4697 | if (kvm_task_switch(vcpu, tss_selector, reason, |
4698 | has_error_code, error_code) == EMULATE_FAIL) { | |
4699 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
4700 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
4701 | vcpu->run->internal.ndata = 0; | |
42dbaa5a | 4702 | return 0; |
acb54517 | 4703 | } |
42dbaa5a JK |
4704 | |
4705 | /* clear all local breakpoint enable flags */ | |
4706 | vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55); | |
4707 | ||
4708 | /* | |
4709 | * TODO: What about debug traps on tss switch? | |
4710 | * Are we supposed to inject them and update dr6? | |
4711 | */ | |
4712 | ||
4713 | return 1; | |
37817f29 IE |
4714 | } |
4715 | ||
851ba692 | 4716 | static int handle_ept_violation(struct kvm_vcpu *vcpu) |
1439442c | 4717 | { |
f9c617f6 | 4718 | unsigned long exit_qualification; |
1439442c | 4719 | gpa_t gpa; |
1439442c | 4720 | int gla_validity; |
1439442c | 4721 | |
f9c617f6 | 4722 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
1439442c SY |
4723 | |
4724 | if (exit_qualification & (1 << 6)) { | |
4725 | printk(KERN_ERR "EPT: GPA exceeds GAW!\n"); | |
7f582ab6 | 4726 | return -EINVAL; |
1439442c SY |
4727 | } |
4728 | ||
4729 | gla_validity = (exit_qualification >> 7) & 0x3; | |
4730 | if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) { | |
4731 | printk(KERN_ERR "EPT: Handling EPT violation failed!\n"); | |
4732 | printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n", | |
4733 | (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS), | |
f9c617f6 | 4734 | vmcs_readl(GUEST_LINEAR_ADDRESS)); |
1439442c SY |
4735 | printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n", |
4736 | (long unsigned int)exit_qualification); | |
851ba692 AK |
4737 | vcpu->run->exit_reason = KVM_EXIT_UNKNOWN; |
4738 | vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION; | |
596ae895 | 4739 | return 0; |
1439442c SY |
4740 | } |
4741 | ||
4742 | gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); | |
229456fc | 4743 | trace_kvm_page_fault(gpa, exit_qualification); |
dc25e89e | 4744 | return kvm_mmu_page_fault(vcpu, gpa, exit_qualification & 0x3, NULL, 0); |
1439442c SY |
4745 | } |
4746 | ||
68f89400 MT |
4747 | static u64 ept_rsvd_mask(u64 spte, int level) |
4748 | { | |
4749 | int i; | |
4750 | u64 mask = 0; | |
4751 | ||
4752 | for (i = 51; i > boot_cpu_data.x86_phys_bits; i--) | |
4753 | mask |= (1ULL << i); | |
4754 | ||
4755 | if (level > 2) | |
4756 | /* bits 7:3 reserved */ | |
4757 | mask |= 0xf8; | |
4758 | else if (level == 2) { | |
4759 | if (spte & (1ULL << 7)) | |
4760 | /* 2MB ref, bits 20:12 reserved */ | |
4761 | mask |= 0x1ff000; | |
4762 | else | |
4763 | /* bits 6:3 reserved */ | |
4764 | mask |= 0x78; | |
4765 | } | |
4766 | ||
4767 | return mask; | |
4768 | } | |
4769 | ||
4770 | static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte, | |
4771 | int level) | |
4772 | { | |
4773 | printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level); | |
4774 | ||
4775 | /* 010b (write-only) */ | |
4776 | WARN_ON((spte & 0x7) == 0x2); | |
4777 | ||
4778 | /* 110b (write/execute) */ | |
4779 | WARN_ON((spte & 0x7) == 0x6); | |
4780 | ||
4781 | /* 100b (execute-only) and value not supported by logical processor */ | |
4782 | if (!cpu_has_vmx_ept_execute_only()) | |
4783 | WARN_ON((spte & 0x7) == 0x4); | |
4784 | ||
4785 | /* not 000b */ | |
4786 | if ((spte & 0x7)) { | |
4787 | u64 rsvd_bits = spte & ept_rsvd_mask(spte, level); | |
4788 | ||
4789 | if (rsvd_bits != 0) { | |
4790 | printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n", | |
4791 | __func__, rsvd_bits); | |
4792 | WARN_ON(1); | |
4793 | } | |
4794 | ||
4795 | if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) { | |
4796 | u64 ept_mem_type = (spte & 0x38) >> 3; | |
4797 | ||
4798 | if (ept_mem_type == 2 || ept_mem_type == 3 || | |
4799 | ept_mem_type == 7) { | |
4800 | printk(KERN_ERR "%s: ept_mem_type=0x%llx\n", | |
4801 | __func__, ept_mem_type); | |
4802 | WARN_ON(1); | |
4803 | } | |
4804 | } | |
4805 | } | |
4806 | } | |
4807 | ||
851ba692 | 4808 | static int handle_ept_misconfig(struct kvm_vcpu *vcpu) |
68f89400 MT |
4809 | { |
4810 | u64 sptes[4]; | |
ce88decf | 4811 | int nr_sptes, i, ret; |
68f89400 MT |
4812 | gpa_t gpa; |
4813 | ||
4814 | gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); | |
4815 | ||
ce88decf XG |
4816 | ret = handle_mmio_page_fault_common(vcpu, gpa, true); |
4817 | if (likely(ret == 1)) | |
4818 | return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) == | |
4819 | EMULATE_DONE; | |
4820 | if (unlikely(!ret)) | |
4821 | return 1; | |
4822 | ||
4823 | /* It is the real ept misconfig */ | |
68f89400 MT |
4824 | printk(KERN_ERR "EPT: Misconfiguration.\n"); |
4825 | printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa); | |
4826 | ||
4827 | nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes); | |
4828 | ||
4829 | for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i) | |
4830 | ept_misconfig_inspect_spte(vcpu, sptes[i-1], i); | |
4831 | ||
851ba692 AK |
4832 | vcpu->run->exit_reason = KVM_EXIT_UNKNOWN; |
4833 | vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG; | |
68f89400 MT |
4834 | |
4835 | return 0; | |
4836 | } | |
4837 | ||
851ba692 | 4838 | static int handle_nmi_window(struct kvm_vcpu *vcpu) |
f08864b4 SY |
4839 | { |
4840 | u32 cpu_based_vm_exec_control; | |
4841 | ||
4842 | /* clear pending NMI */ | |
4843 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
4844 | cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING; | |
4845 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
4846 | ++vcpu->stat.nmi_window_exits; | |
3842d135 | 4847 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
f08864b4 SY |
4848 | |
4849 | return 1; | |
4850 | } | |
4851 | ||
80ced186 | 4852 | static int handle_invalid_guest_state(struct kvm_vcpu *vcpu) |
ea953ef0 | 4853 | { |
8b3079a5 AK |
4854 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
4855 | enum emulation_result err = EMULATE_DONE; | |
80ced186 | 4856 | int ret = 1; |
49e9d557 AK |
4857 | u32 cpu_exec_ctrl; |
4858 | bool intr_window_requested; | |
4859 | ||
4860 | cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
4861 | intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING; | |
ea953ef0 MG |
4862 | |
4863 | while (!guest_state_valid(vcpu)) { | |
49e9d557 AK |
4864 | if (intr_window_requested |
4865 | && (kvm_get_rflags(&vmx->vcpu) & X86_EFLAGS_IF)) | |
4866 | return handle_interrupt_window(&vmx->vcpu); | |
4867 | ||
51d8b661 | 4868 | err = emulate_instruction(vcpu, 0); |
ea953ef0 | 4869 | |
80ced186 MG |
4870 | if (err == EMULATE_DO_MMIO) { |
4871 | ret = 0; | |
4872 | goto out; | |
4873 | } | |
1d5a4d9b | 4874 | |
6d77dbfc GN |
4875 | if (err != EMULATE_DONE) |
4876 | return 0; | |
ea953ef0 MG |
4877 | |
4878 | if (signal_pending(current)) | |
80ced186 | 4879 | goto out; |
ea953ef0 MG |
4880 | if (need_resched()) |
4881 | schedule(); | |
4882 | } | |
4883 | ||
80ced186 MG |
4884 | vmx->emulation_required = 0; |
4885 | out: | |
4886 | return ret; | |
ea953ef0 MG |
4887 | } |
4888 | ||
4b8d54f9 ZE |
4889 | /* |
4890 | * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE | |
4891 | * exiting, so only get here on cpu with PAUSE-Loop-Exiting. | |
4892 | */ | |
9fb41ba8 | 4893 | static int handle_pause(struct kvm_vcpu *vcpu) |
4b8d54f9 ZE |
4894 | { |
4895 | skip_emulated_instruction(vcpu); | |
4896 | kvm_vcpu_on_spin(vcpu); | |
4897 | ||
4898 | return 1; | |
4899 | } | |
4900 | ||
59708670 SY |
4901 | static int handle_invalid_op(struct kvm_vcpu *vcpu) |
4902 | { | |
4903 | kvm_queue_exception(vcpu, UD_VECTOR); | |
4904 | return 1; | |
4905 | } | |
4906 | ||
ff2f6fe9 NHE |
4907 | /* |
4908 | * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12. | |
4909 | * We could reuse a single VMCS for all the L2 guests, but we also want the | |
4910 | * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this | |
4911 | * allows keeping them loaded on the processor, and in the future will allow | |
4912 | * optimizations where prepare_vmcs02 doesn't need to set all the fields on | |
4913 | * every entry if they never change. | |
4914 | * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE | |
4915 | * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first. | |
4916 | * | |
4917 | * The following functions allocate and free a vmcs02 in this pool. | |
4918 | */ | |
4919 | ||
4920 | /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */ | |
4921 | static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx) | |
4922 | { | |
4923 | struct vmcs02_list *item; | |
4924 | list_for_each_entry(item, &vmx->nested.vmcs02_pool, list) | |
4925 | if (item->vmptr == vmx->nested.current_vmptr) { | |
4926 | list_move(&item->list, &vmx->nested.vmcs02_pool); | |
4927 | return &item->vmcs02; | |
4928 | } | |
4929 | ||
4930 | if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) { | |
4931 | /* Recycle the least recently used VMCS. */ | |
4932 | item = list_entry(vmx->nested.vmcs02_pool.prev, | |
4933 | struct vmcs02_list, list); | |
4934 | item->vmptr = vmx->nested.current_vmptr; | |
4935 | list_move(&item->list, &vmx->nested.vmcs02_pool); | |
4936 | return &item->vmcs02; | |
4937 | } | |
4938 | ||
4939 | /* Create a new VMCS */ | |
4940 | item = (struct vmcs02_list *) | |
4941 | kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL); | |
4942 | if (!item) | |
4943 | return NULL; | |
4944 | item->vmcs02.vmcs = alloc_vmcs(); | |
4945 | if (!item->vmcs02.vmcs) { | |
4946 | kfree(item); | |
4947 | return NULL; | |
4948 | } | |
4949 | loaded_vmcs_init(&item->vmcs02); | |
4950 | item->vmptr = vmx->nested.current_vmptr; | |
4951 | list_add(&(item->list), &(vmx->nested.vmcs02_pool)); | |
4952 | vmx->nested.vmcs02_num++; | |
4953 | return &item->vmcs02; | |
4954 | } | |
4955 | ||
4956 | /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */ | |
4957 | static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr) | |
4958 | { | |
4959 | struct vmcs02_list *item; | |
4960 | list_for_each_entry(item, &vmx->nested.vmcs02_pool, list) | |
4961 | if (item->vmptr == vmptr) { | |
4962 | free_loaded_vmcs(&item->vmcs02); | |
4963 | list_del(&item->list); | |
4964 | kfree(item); | |
4965 | vmx->nested.vmcs02_num--; | |
4966 | return; | |
4967 | } | |
4968 | } | |
4969 | ||
4970 | /* | |
4971 | * Free all VMCSs saved for this vcpu, except the one pointed by | |
4972 | * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one | |
4973 | * currently used, if running L2), and vmcs01 when running L2. | |
4974 | */ | |
4975 | static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx) | |
4976 | { | |
4977 | struct vmcs02_list *item, *n; | |
4978 | list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) { | |
4979 | if (vmx->loaded_vmcs != &item->vmcs02) | |
4980 | free_loaded_vmcs(&item->vmcs02); | |
4981 | list_del(&item->list); | |
4982 | kfree(item); | |
4983 | } | |
4984 | vmx->nested.vmcs02_num = 0; | |
4985 | ||
4986 | if (vmx->loaded_vmcs != &vmx->vmcs01) | |
4987 | free_loaded_vmcs(&vmx->vmcs01); | |
4988 | } | |
4989 | ||
ec378aee NHE |
4990 | /* |
4991 | * Emulate the VMXON instruction. | |
4992 | * Currently, we just remember that VMX is active, and do not save or even | |
4993 | * inspect the argument to VMXON (the so-called "VMXON pointer") because we | |
4994 | * do not currently need to store anything in that guest-allocated memory | |
4995 | * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their | |
4996 | * argument is different from the VMXON pointer (which the spec says they do). | |
4997 | */ | |
4998 | static int handle_vmon(struct kvm_vcpu *vcpu) | |
4999 | { | |
5000 | struct kvm_segment cs; | |
5001 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
5002 | ||
5003 | /* The Intel VMX Instruction Reference lists a bunch of bits that | |
5004 | * are prerequisite to running VMXON, most notably cr4.VMXE must be | |
5005 | * set to 1 (see vmx_set_cr4() for when we allow the guest to set this). | |
5006 | * Otherwise, we should fail with #UD. We test these now: | |
5007 | */ | |
5008 | if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) || | |
5009 | !kvm_read_cr0_bits(vcpu, X86_CR0_PE) || | |
5010 | (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) { | |
5011 | kvm_queue_exception(vcpu, UD_VECTOR); | |
5012 | return 1; | |
5013 | } | |
5014 | ||
5015 | vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
5016 | if (is_long_mode(vcpu) && !cs.l) { | |
5017 | kvm_queue_exception(vcpu, UD_VECTOR); | |
5018 | return 1; | |
5019 | } | |
5020 | ||
5021 | if (vmx_get_cpl(vcpu)) { | |
5022 | kvm_inject_gp(vcpu, 0); | |
5023 | return 1; | |
5024 | } | |
5025 | ||
ff2f6fe9 NHE |
5026 | INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool)); |
5027 | vmx->nested.vmcs02_num = 0; | |
5028 | ||
ec378aee NHE |
5029 | vmx->nested.vmxon = true; |
5030 | ||
5031 | skip_emulated_instruction(vcpu); | |
5032 | return 1; | |
5033 | } | |
5034 | ||
5035 | /* | |
5036 | * Intel's VMX Instruction Reference specifies a common set of prerequisites | |
5037 | * for running VMX instructions (except VMXON, whose prerequisites are | |
5038 | * slightly different). It also specifies what exception to inject otherwise. | |
5039 | */ | |
5040 | static int nested_vmx_check_permission(struct kvm_vcpu *vcpu) | |
5041 | { | |
5042 | struct kvm_segment cs; | |
5043 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
5044 | ||
5045 | if (!vmx->nested.vmxon) { | |
5046 | kvm_queue_exception(vcpu, UD_VECTOR); | |
5047 | return 0; | |
5048 | } | |
5049 | ||
5050 | vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
5051 | if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) || | |
5052 | (is_long_mode(vcpu) && !cs.l)) { | |
5053 | kvm_queue_exception(vcpu, UD_VECTOR); | |
5054 | return 0; | |
5055 | } | |
5056 | ||
5057 | if (vmx_get_cpl(vcpu)) { | |
5058 | kvm_inject_gp(vcpu, 0); | |
5059 | return 0; | |
5060 | } | |
5061 | ||
5062 | return 1; | |
5063 | } | |
5064 | ||
5065 | /* | |
5066 | * Free whatever needs to be freed from vmx->nested when L1 goes down, or | |
5067 | * just stops using VMX. | |
5068 | */ | |
5069 | static void free_nested(struct vcpu_vmx *vmx) | |
5070 | { | |
5071 | if (!vmx->nested.vmxon) | |
5072 | return; | |
5073 | vmx->nested.vmxon = false; | |
a9d30f33 NHE |
5074 | if (vmx->nested.current_vmptr != -1ull) { |
5075 | kunmap(vmx->nested.current_vmcs12_page); | |
5076 | nested_release_page(vmx->nested.current_vmcs12_page); | |
5077 | vmx->nested.current_vmptr = -1ull; | |
5078 | vmx->nested.current_vmcs12 = NULL; | |
5079 | } | |
fe3ef05c NHE |
5080 | /* Unpin physical memory we referred to in current vmcs02 */ |
5081 | if (vmx->nested.apic_access_page) { | |
5082 | nested_release_page(vmx->nested.apic_access_page); | |
5083 | vmx->nested.apic_access_page = 0; | |
5084 | } | |
ff2f6fe9 NHE |
5085 | |
5086 | nested_free_all_saved_vmcss(vmx); | |
ec378aee NHE |
5087 | } |
5088 | ||
5089 | /* Emulate the VMXOFF instruction */ | |
5090 | static int handle_vmoff(struct kvm_vcpu *vcpu) | |
5091 | { | |
5092 | if (!nested_vmx_check_permission(vcpu)) | |
5093 | return 1; | |
5094 | free_nested(to_vmx(vcpu)); | |
5095 | skip_emulated_instruction(vcpu); | |
5096 | return 1; | |
5097 | } | |
5098 | ||
064aea77 NHE |
5099 | /* |
5100 | * Decode the memory-address operand of a vmx instruction, as recorded on an | |
5101 | * exit caused by such an instruction (run by a guest hypervisor). | |
5102 | * On success, returns 0. When the operand is invalid, returns 1 and throws | |
5103 | * #UD or #GP. | |
5104 | */ | |
5105 | static int get_vmx_mem_address(struct kvm_vcpu *vcpu, | |
5106 | unsigned long exit_qualification, | |
5107 | u32 vmx_instruction_info, gva_t *ret) | |
5108 | { | |
5109 | /* | |
5110 | * According to Vol. 3B, "Information for VM Exits Due to Instruction | |
5111 | * Execution", on an exit, vmx_instruction_info holds most of the | |
5112 | * addressing components of the operand. Only the displacement part | |
5113 | * is put in exit_qualification (see 3B, "Basic VM-Exit Information"). | |
5114 | * For how an actual address is calculated from all these components, | |
5115 | * refer to Vol. 1, "Operand Addressing". | |
5116 | */ | |
5117 | int scaling = vmx_instruction_info & 3; | |
5118 | int addr_size = (vmx_instruction_info >> 7) & 7; | |
5119 | bool is_reg = vmx_instruction_info & (1u << 10); | |
5120 | int seg_reg = (vmx_instruction_info >> 15) & 7; | |
5121 | int index_reg = (vmx_instruction_info >> 18) & 0xf; | |
5122 | bool index_is_valid = !(vmx_instruction_info & (1u << 22)); | |
5123 | int base_reg = (vmx_instruction_info >> 23) & 0xf; | |
5124 | bool base_is_valid = !(vmx_instruction_info & (1u << 27)); | |
5125 | ||
5126 | if (is_reg) { | |
5127 | kvm_queue_exception(vcpu, UD_VECTOR); | |
5128 | return 1; | |
5129 | } | |
5130 | ||
5131 | /* Addr = segment_base + offset */ | |
5132 | /* offset = base + [index * scale] + displacement */ | |
5133 | *ret = vmx_get_segment_base(vcpu, seg_reg); | |
5134 | if (base_is_valid) | |
5135 | *ret += kvm_register_read(vcpu, base_reg); | |
5136 | if (index_is_valid) | |
5137 | *ret += kvm_register_read(vcpu, index_reg)<<scaling; | |
5138 | *ret += exit_qualification; /* holds the displacement */ | |
5139 | ||
5140 | if (addr_size == 1) /* 32 bit */ | |
5141 | *ret &= 0xffffffff; | |
5142 | ||
5143 | /* | |
5144 | * TODO: throw #GP (and return 1) in various cases that the VM* | |
5145 | * instructions require it - e.g., offset beyond segment limit, | |
5146 | * unusable or unreadable/unwritable segment, non-canonical 64-bit | |
5147 | * address, and so on. Currently these are not checked. | |
5148 | */ | |
5149 | return 0; | |
5150 | } | |
5151 | ||
0140caea NHE |
5152 | /* |
5153 | * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(), | |
5154 | * set the success or error code of an emulated VMX instruction, as specified | |
5155 | * by Vol 2B, VMX Instruction Reference, "Conventions". | |
5156 | */ | |
5157 | static void nested_vmx_succeed(struct kvm_vcpu *vcpu) | |
5158 | { | |
5159 | vmx_set_rflags(vcpu, vmx_get_rflags(vcpu) | |
5160 | & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | | |
5161 | X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF)); | |
5162 | } | |
5163 | ||
5164 | static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu) | |
5165 | { | |
5166 | vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu) | |
5167 | & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF | | |
5168 | X86_EFLAGS_SF | X86_EFLAGS_OF)) | |
5169 | | X86_EFLAGS_CF); | |
5170 | } | |
5171 | ||
5172 | static void nested_vmx_failValid(struct kvm_vcpu *vcpu, | |
5173 | u32 vm_instruction_error) | |
5174 | { | |
5175 | if (to_vmx(vcpu)->nested.current_vmptr == -1ull) { | |
5176 | /* | |
5177 | * failValid writes the error number to the current VMCS, which | |
5178 | * can't be done there isn't a current VMCS. | |
5179 | */ | |
5180 | nested_vmx_failInvalid(vcpu); | |
5181 | return; | |
5182 | } | |
5183 | vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu) | |
5184 | & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | | |
5185 | X86_EFLAGS_SF | X86_EFLAGS_OF)) | |
5186 | | X86_EFLAGS_ZF); | |
5187 | get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error; | |
5188 | } | |
5189 | ||
27d6c865 NHE |
5190 | /* Emulate the VMCLEAR instruction */ |
5191 | static int handle_vmclear(struct kvm_vcpu *vcpu) | |
5192 | { | |
5193 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
5194 | gva_t gva; | |
5195 | gpa_t vmptr; | |
5196 | struct vmcs12 *vmcs12; | |
5197 | struct page *page; | |
5198 | struct x86_exception e; | |
5199 | ||
5200 | if (!nested_vmx_check_permission(vcpu)) | |
5201 | return 1; | |
5202 | ||
5203 | if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION), | |
5204 | vmcs_read32(VMX_INSTRUCTION_INFO), &gva)) | |
5205 | return 1; | |
5206 | ||
5207 | if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr, | |
5208 | sizeof(vmptr), &e)) { | |
5209 | kvm_inject_page_fault(vcpu, &e); | |
5210 | return 1; | |
5211 | } | |
5212 | ||
5213 | if (!IS_ALIGNED(vmptr, PAGE_SIZE)) { | |
5214 | nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS); | |
5215 | skip_emulated_instruction(vcpu); | |
5216 | return 1; | |
5217 | } | |
5218 | ||
5219 | if (vmptr == vmx->nested.current_vmptr) { | |
5220 | kunmap(vmx->nested.current_vmcs12_page); | |
5221 | nested_release_page(vmx->nested.current_vmcs12_page); | |
5222 | vmx->nested.current_vmptr = -1ull; | |
5223 | vmx->nested.current_vmcs12 = NULL; | |
5224 | } | |
5225 | ||
5226 | page = nested_get_page(vcpu, vmptr); | |
5227 | if (page == NULL) { | |
5228 | /* | |
5229 | * For accurate processor emulation, VMCLEAR beyond available | |
5230 | * physical memory should do nothing at all. However, it is | |
5231 | * possible that a nested vmx bug, not a guest hypervisor bug, | |
5232 | * resulted in this case, so let's shut down before doing any | |
5233 | * more damage: | |
5234 | */ | |
5235 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); | |
5236 | return 1; | |
5237 | } | |
5238 | vmcs12 = kmap(page); | |
5239 | vmcs12->launch_state = 0; | |
5240 | kunmap(page); | |
5241 | nested_release_page(page); | |
5242 | ||
5243 | nested_free_vmcs02(vmx, vmptr); | |
5244 | ||
5245 | skip_emulated_instruction(vcpu); | |
5246 | nested_vmx_succeed(vcpu); | |
5247 | return 1; | |
5248 | } | |
5249 | ||
cd232ad0 NHE |
5250 | static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch); |
5251 | ||
5252 | /* Emulate the VMLAUNCH instruction */ | |
5253 | static int handle_vmlaunch(struct kvm_vcpu *vcpu) | |
5254 | { | |
5255 | return nested_vmx_run(vcpu, true); | |
5256 | } | |
5257 | ||
5258 | /* Emulate the VMRESUME instruction */ | |
5259 | static int handle_vmresume(struct kvm_vcpu *vcpu) | |
5260 | { | |
5261 | ||
5262 | return nested_vmx_run(vcpu, false); | |
5263 | } | |
5264 | ||
49f705c5 NHE |
5265 | enum vmcs_field_type { |
5266 | VMCS_FIELD_TYPE_U16 = 0, | |
5267 | VMCS_FIELD_TYPE_U64 = 1, | |
5268 | VMCS_FIELD_TYPE_U32 = 2, | |
5269 | VMCS_FIELD_TYPE_NATURAL_WIDTH = 3 | |
5270 | }; | |
5271 | ||
5272 | static inline int vmcs_field_type(unsigned long field) | |
5273 | { | |
5274 | if (0x1 & field) /* the *_HIGH fields are all 32 bit */ | |
5275 | return VMCS_FIELD_TYPE_U32; | |
5276 | return (field >> 13) & 0x3 ; | |
5277 | } | |
5278 | ||
5279 | static inline int vmcs_field_readonly(unsigned long field) | |
5280 | { | |
5281 | return (((field >> 10) & 0x3) == 1); | |
5282 | } | |
5283 | ||
5284 | /* | |
5285 | * Read a vmcs12 field. Since these can have varying lengths and we return | |
5286 | * one type, we chose the biggest type (u64) and zero-extend the return value | |
5287 | * to that size. Note that the caller, handle_vmread, might need to use only | |
5288 | * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of | |
5289 | * 64-bit fields are to be returned). | |
5290 | */ | |
5291 | static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu, | |
5292 | unsigned long field, u64 *ret) | |
5293 | { | |
5294 | short offset = vmcs_field_to_offset(field); | |
5295 | char *p; | |
5296 | ||
5297 | if (offset < 0) | |
5298 | return 0; | |
5299 | ||
5300 | p = ((char *)(get_vmcs12(vcpu))) + offset; | |
5301 | ||
5302 | switch (vmcs_field_type(field)) { | |
5303 | case VMCS_FIELD_TYPE_NATURAL_WIDTH: | |
5304 | *ret = *((natural_width *)p); | |
5305 | return 1; | |
5306 | case VMCS_FIELD_TYPE_U16: | |
5307 | *ret = *((u16 *)p); | |
5308 | return 1; | |
5309 | case VMCS_FIELD_TYPE_U32: | |
5310 | *ret = *((u32 *)p); | |
5311 | return 1; | |
5312 | case VMCS_FIELD_TYPE_U64: | |
5313 | *ret = *((u64 *)p); | |
5314 | return 1; | |
5315 | default: | |
5316 | return 0; /* can never happen. */ | |
5317 | } | |
5318 | } | |
5319 | ||
5320 | /* | |
5321 | * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was | |
5322 | * used before) all generate the same failure when it is missing. | |
5323 | */ | |
5324 | static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu) | |
5325 | { | |
5326 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
5327 | if (vmx->nested.current_vmptr == -1ull) { | |
5328 | nested_vmx_failInvalid(vcpu); | |
5329 | skip_emulated_instruction(vcpu); | |
5330 | return 0; | |
5331 | } | |
5332 | return 1; | |
5333 | } | |
5334 | ||
5335 | static int handle_vmread(struct kvm_vcpu *vcpu) | |
5336 | { | |
5337 | unsigned long field; | |
5338 | u64 field_value; | |
5339 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
5340 | u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); | |
5341 | gva_t gva = 0; | |
5342 | ||
5343 | if (!nested_vmx_check_permission(vcpu) || | |
5344 | !nested_vmx_check_vmcs12(vcpu)) | |
5345 | return 1; | |
5346 | ||
5347 | /* Decode instruction info and find the field to read */ | |
5348 | field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf)); | |
5349 | /* Read the field, zero-extended to a u64 field_value */ | |
5350 | if (!vmcs12_read_any(vcpu, field, &field_value)) { | |
5351 | nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT); | |
5352 | skip_emulated_instruction(vcpu); | |
5353 | return 1; | |
5354 | } | |
5355 | /* | |
5356 | * Now copy part of this value to register or memory, as requested. | |
5357 | * Note that the number of bits actually copied is 32 or 64 depending | |
5358 | * on the guest's mode (32 or 64 bit), not on the given field's length. | |
5359 | */ | |
5360 | if (vmx_instruction_info & (1u << 10)) { | |
5361 | kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf), | |
5362 | field_value); | |
5363 | } else { | |
5364 | if (get_vmx_mem_address(vcpu, exit_qualification, | |
5365 | vmx_instruction_info, &gva)) | |
5366 | return 1; | |
5367 | /* _system ok, as nested_vmx_check_permission verified cpl=0 */ | |
5368 | kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva, | |
5369 | &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL); | |
5370 | } | |
5371 | ||
5372 | nested_vmx_succeed(vcpu); | |
5373 | skip_emulated_instruction(vcpu); | |
5374 | return 1; | |
5375 | } | |
5376 | ||
5377 | ||
5378 | static int handle_vmwrite(struct kvm_vcpu *vcpu) | |
5379 | { | |
5380 | unsigned long field; | |
5381 | gva_t gva; | |
5382 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
5383 | u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); | |
5384 | char *p; | |
5385 | short offset; | |
5386 | /* The value to write might be 32 or 64 bits, depending on L1's long | |
5387 | * mode, and eventually we need to write that into a field of several | |
5388 | * possible lengths. The code below first zero-extends the value to 64 | |
5389 | * bit (field_value), and then copies only the approriate number of | |
5390 | * bits into the vmcs12 field. | |
5391 | */ | |
5392 | u64 field_value = 0; | |
5393 | struct x86_exception e; | |
5394 | ||
5395 | if (!nested_vmx_check_permission(vcpu) || | |
5396 | !nested_vmx_check_vmcs12(vcpu)) | |
5397 | return 1; | |
5398 | ||
5399 | if (vmx_instruction_info & (1u << 10)) | |
5400 | field_value = kvm_register_read(vcpu, | |
5401 | (((vmx_instruction_info) >> 3) & 0xf)); | |
5402 | else { | |
5403 | if (get_vmx_mem_address(vcpu, exit_qualification, | |
5404 | vmx_instruction_info, &gva)) | |
5405 | return 1; | |
5406 | if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, | |
5407 | &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) { | |
5408 | kvm_inject_page_fault(vcpu, &e); | |
5409 | return 1; | |
5410 | } | |
5411 | } | |
5412 | ||
5413 | ||
5414 | field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf)); | |
5415 | if (vmcs_field_readonly(field)) { | |
5416 | nested_vmx_failValid(vcpu, | |
5417 | VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT); | |
5418 | skip_emulated_instruction(vcpu); | |
5419 | return 1; | |
5420 | } | |
5421 | ||
5422 | offset = vmcs_field_to_offset(field); | |
5423 | if (offset < 0) { | |
5424 | nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT); | |
5425 | skip_emulated_instruction(vcpu); | |
5426 | return 1; | |
5427 | } | |
5428 | p = ((char *) get_vmcs12(vcpu)) + offset; | |
5429 | ||
5430 | switch (vmcs_field_type(field)) { | |
5431 | case VMCS_FIELD_TYPE_U16: | |
5432 | *(u16 *)p = field_value; | |
5433 | break; | |
5434 | case VMCS_FIELD_TYPE_U32: | |
5435 | *(u32 *)p = field_value; | |
5436 | break; | |
5437 | case VMCS_FIELD_TYPE_U64: | |
5438 | *(u64 *)p = field_value; | |
5439 | break; | |
5440 | case VMCS_FIELD_TYPE_NATURAL_WIDTH: | |
5441 | *(natural_width *)p = field_value; | |
5442 | break; | |
5443 | default: | |
5444 | nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT); | |
5445 | skip_emulated_instruction(vcpu); | |
5446 | return 1; | |
5447 | } | |
5448 | ||
5449 | nested_vmx_succeed(vcpu); | |
5450 | skip_emulated_instruction(vcpu); | |
5451 | return 1; | |
5452 | } | |
5453 | ||
63846663 NHE |
5454 | /* Emulate the VMPTRLD instruction */ |
5455 | static int handle_vmptrld(struct kvm_vcpu *vcpu) | |
5456 | { | |
5457 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
5458 | gva_t gva; | |
5459 | gpa_t vmptr; | |
5460 | struct x86_exception e; | |
5461 | ||
5462 | if (!nested_vmx_check_permission(vcpu)) | |
5463 | return 1; | |
5464 | ||
5465 | if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION), | |
5466 | vmcs_read32(VMX_INSTRUCTION_INFO), &gva)) | |
5467 | return 1; | |
5468 | ||
5469 | if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr, | |
5470 | sizeof(vmptr), &e)) { | |
5471 | kvm_inject_page_fault(vcpu, &e); | |
5472 | return 1; | |
5473 | } | |
5474 | ||
5475 | if (!IS_ALIGNED(vmptr, PAGE_SIZE)) { | |
5476 | nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS); | |
5477 | skip_emulated_instruction(vcpu); | |
5478 | return 1; | |
5479 | } | |
5480 | ||
5481 | if (vmx->nested.current_vmptr != vmptr) { | |
5482 | struct vmcs12 *new_vmcs12; | |
5483 | struct page *page; | |
5484 | page = nested_get_page(vcpu, vmptr); | |
5485 | if (page == NULL) { | |
5486 | nested_vmx_failInvalid(vcpu); | |
5487 | skip_emulated_instruction(vcpu); | |
5488 | return 1; | |
5489 | } | |
5490 | new_vmcs12 = kmap(page); | |
5491 | if (new_vmcs12->revision_id != VMCS12_REVISION) { | |
5492 | kunmap(page); | |
5493 | nested_release_page_clean(page); | |
5494 | nested_vmx_failValid(vcpu, | |
5495 | VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID); | |
5496 | skip_emulated_instruction(vcpu); | |
5497 | return 1; | |
5498 | } | |
5499 | if (vmx->nested.current_vmptr != -1ull) { | |
5500 | kunmap(vmx->nested.current_vmcs12_page); | |
5501 | nested_release_page(vmx->nested.current_vmcs12_page); | |
5502 | } | |
5503 | ||
5504 | vmx->nested.current_vmptr = vmptr; | |
5505 | vmx->nested.current_vmcs12 = new_vmcs12; | |
5506 | vmx->nested.current_vmcs12_page = page; | |
5507 | } | |
5508 | ||
5509 | nested_vmx_succeed(vcpu); | |
5510 | skip_emulated_instruction(vcpu); | |
5511 | return 1; | |
5512 | } | |
5513 | ||
6a4d7550 NHE |
5514 | /* Emulate the VMPTRST instruction */ |
5515 | static int handle_vmptrst(struct kvm_vcpu *vcpu) | |
5516 | { | |
5517 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
5518 | u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); | |
5519 | gva_t vmcs_gva; | |
5520 | struct x86_exception e; | |
5521 | ||
5522 | if (!nested_vmx_check_permission(vcpu)) | |
5523 | return 1; | |
5524 | ||
5525 | if (get_vmx_mem_address(vcpu, exit_qualification, | |
5526 | vmx_instruction_info, &vmcs_gva)) | |
5527 | return 1; | |
5528 | /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */ | |
5529 | if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva, | |
5530 | (void *)&to_vmx(vcpu)->nested.current_vmptr, | |
5531 | sizeof(u64), &e)) { | |
5532 | kvm_inject_page_fault(vcpu, &e); | |
5533 | return 1; | |
5534 | } | |
5535 | nested_vmx_succeed(vcpu); | |
5536 | skip_emulated_instruction(vcpu); | |
5537 | return 1; | |
5538 | } | |
5539 | ||
6aa8b732 AK |
5540 | /* |
5541 | * The exit handlers return 1 if the exit was handled fully and guest execution | |
5542 | * may resume. Otherwise they set the kvm_run parameter to indicate what needs | |
5543 | * to be done to userspace and return 0. | |
5544 | */ | |
851ba692 | 5545 | static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = { |
6aa8b732 AK |
5546 | [EXIT_REASON_EXCEPTION_NMI] = handle_exception, |
5547 | [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt, | |
988ad74f | 5548 | [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault, |
f08864b4 | 5549 | [EXIT_REASON_NMI_WINDOW] = handle_nmi_window, |
6aa8b732 | 5550 | [EXIT_REASON_IO_INSTRUCTION] = handle_io, |
6aa8b732 AK |
5551 | [EXIT_REASON_CR_ACCESS] = handle_cr, |
5552 | [EXIT_REASON_DR_ACCESS] = handle_dr, | |
5553 | [EXIT_REASON_CPUID] = handle_cpuid, | |
5554 | [EXIT_REASON_MSR_READ] = handle_rdmsr, | |
5555 | [EXIT_REASON_MSR_WRITE] = handle_wrmsr, | |
5556 | [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window, | |
5557 | [EXIT_REASON_HLT] = handle_halt, | |
ec25d5e6 | 5558 | [EXIT_REASON_INVD] = handle_invd, |
a7052897 | 5559 | [EXIT_REASON_INVLPG] = handle_invlpg, |
c21415e8 | 5560 | [EXIT_REASON_VMCALL] = handle_vmcall, |
27d6c865 | 5561 | [EXIT_REASON_VMCLEAR] = handle_vmclear, |
cd232ad0 | 5562 | [EXIT_REASON_VMLAUNCH] = handle_vmlaunch, |
63846663 | 5563 | [EXIT_REASON_VMPTRLD] = handle_vmptrld, |
6a4d7550 | 5564 | [EXIT_REASON_VMPTRST] = handle_vmptrst, |
49f705c5 | 5565 | [EXIT_REASON_VMREAD] = handle_vmread, |
cd232ad0 | 5566 | [EXIT_REASON_VMRESUME] = handle_vmresume, |
49f705c5 | 5567 | [EXIT_REASON_VMWRITE] = handle_vmwrite, |
ec378aee NHE |
5568 | [EXIT_REASON_VMOFF] = handle_vmoff, |
5569 | [EXIT_REASON_VMON] = handle_vmon, | |
f78e0e2e SY |
5570 | [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold, |
5571 | [EXIT_REASON_APIC_ACCESS] = handle_apic_access, | |
e5edaa01 | 5572 | [EXIT_REASON_WBINVD] = handle_wbinvd, |
2acf923e | 5573 | [EXIT_REASON_XSETBV] = handle_xsetbv, |
37817f29 | 5574 | [EXIT_REASON_TASK_SWITCH] = handle_task_switch, |
a0861c02 | 5575 | [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check, |
68f89400 MT |
5576 | [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation, |
5577 | [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig, | |
4b8d54f9 | 5578 | [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause, |
59708670 SY |
5579 | [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op, |
5580 | [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op, | |
6aa8b732 AK |
5581 | }; |
5582 | ||
5583 | static const int kvm_vmx_max_exit_handlers = | |
50a3485c | 5584 | ARRAY_SIZE(kvm_vmx_exit_handlers); |
6aa8b732 | 5585 | |
644d711a NHE |
5586 | /* |
5587 | * Return 1 if we should exit from L2 to L1 to handle an MSR access access, | |
5588 | * rather than handle it ourselves in L0. I.e., check whether L1 expressed | |
5589 | * disinterest in the current event (read or write a specific MSR) by using an | |
5590 | * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps. | |
5591 | */ | |
5592 | static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu, | |
5593 | struct vmcs12 *vmcs12, u32 exit_reason) | |
5594 | { | |
5595 | u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX]; | |
5596 | gpa_t bitmap; | |
5597 | ||
5598 | if (!nested_cpu_has(get_vmcs12(vcpu), CPU_BASED_USE_MSR_BITMAPS)) | |
5599 | return 1; | |
5600 | ||
5601 | /* | |
5602 | * The MSR_BITMAP page is divided into four 1024-byte bitmaps, | |
5603 | * for the four combinations of read/write and low/high MSR numbers. | |
5604 | * First we need to figure out which of the four to use: | |
5605 | */ | |
5606 | bitmap = vmcs12->msr_bitmap; | |
5607 | if (exit_reason == EXIT_REASON_MSR_WRITE) | |
5608 | bitmap += 2048; | |
5609 | if (msr_index >= 0xc0000000) { | |
5610 | msr_index -= 0xc0000000; | |
5611 | bitmap += 1024; | |
5612 | } | |
5613 | ||
5614 | /* Then read the msr_index'th bit from this bitmap: */ | |
5615 | if (msr_index < 1024*8) { | |
5616 | unsigned char b; | |
5617 | kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1); | |
5618 | return 1 & (b >> (msr_index & 7)); | |
5619 | } else | |
5620 | return 1; /* let L1 handle the wrong parameter */ | |
5621 | } | |
5622 | ||
5623 | /* | |
5624 | * Return 1 if we should exit from L2 to L1 to handle a CR access exit, | |
5625 | * rather than handle it ourselves in L0. I.e., check if L1 wanted to | |
5626 | * intercept (via guest_host_mask etc.) the current event. | |
5627 | */ | |
5628 | static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu, | |
5629 | struct vmcs12 *vmcs12) | |
5630 | { | |
5631 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
5632 | int cr = exit_qualification & 15; | |
5633 | int reg = (exit_qualification >> 8) & 15; | |
5634 | unsigned long val = kvm_register_read(vcpu, reg); | |
5635 | ||
5636 | switch ((exit_qualification >> 4) & 3) { | |
5637 | case 0: /* mov to cr */ | |
5638 | switch (cr) { | |
5639 | case 0: | |
5640 | if (vmcs12->cr0_guest_host_mask & | |
5641 | (val ^ vmcs12->cr0_read_shadow)) | |
5642 | return 1; | |
5643 | break; | |
5644 | case 3: | |
5645 | if ((vmcs12->cr3_target_count >= 1 && | |
5646 | vmcs12->cr3_target_value0 == val) || | |
5647 | (vmcs12->cr3_target_count >= 2 && | |
5648 | vmcs12->cr3_target_value1 == val) || | |
5649 | (vmcs12->cr3_target_count >= 3 && | |
5650 | vmcs12->cr3_target_value2 == val) || | |
5651 | (vmcs12->cr3_target_count >= 4 && | |
5652 | vmcs12->cr3_target_value3 == val)) | |
5653 | return 0; | |
5654 | if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING)) | |
5655 | return 1; | |
5656 | break; | |
5657 | case 4: | |
5658 | if (vmcs12->cr4_guest_host_mask & | |
5659 | (vmcs12->cr4_read_shadow ^ val)) | |
5660 | return 1; | |
5661 | break; | |
5662 | case 8: | |
5663 | if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING)) | |
5664 | return 1; | |
5665 | break; | |
5666 | } | |
5667 | break; | |
5668 | case 2: /* clts */ | |
5669 | if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) && | |
5670 | (vmcs12->cr0_read_shadow & X86_CR0_TS)) | |
5671 | return 1; | |
5672 | break; | |
5673 | case 1: /* mov from cr */ | |
5674 | switch (cr) { | |
5675 | case 3: | |
5676 | if (vmcs12->cpu_based_vm_exec_control & | |
5677 | CPU_BASED_CR3_STORE_EXITING) | |
5678 | return 1; | |
5679 | break; | |
5680 | case 8: | |
5681 | if (vmcs12->cpu_based_vm_exec_control & | |
5682 | CPU_BASED_CR8_STORE_EXITING) | |
5683 | return 1; | |
5684 | break; | |
5685 | } | |
5686 | break; | |
5687 | case 3: /* lmsw */ | |
5688 | /* | |
5689 | * lmsw can change bits 1..3 of cr0, and only set bit 0 of | |
5690 | * cr0. Other attempted changes are ignored, with no exit. | |
5691 | */ | |
5692 | if (vmcs12->cr0_guest_host_mask & 0xe & | |
5693 | (val ^ vmcs12->cr0_read_shadow)) | |
5694 | return 1; | |
5695 | if ((vmcs12->cr0_guest_host_mask & 0x1) && | |
5696 | !(vmcs12->cr0_read_shadow & 0x1) && | |
5697 | (val & 0x1)) | |
5698 | return 1; | |
5699 | break; | |
5700 | } | |
5701 | return 0; | |
5702 | } | |
5703 | ||
5704 | /* | |
5705 | * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we | |
5706 | * should handle it ourselves in L0 (and then continue L2). Only call this | |
5707 | * when in is_guest_mode (L2). | |
5708 | */ | |
5709 | static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu) | |
5710 | { | |
5711 | u32 exit_reason = vmcs_read32(VM_EXIT_REASON); | |
5712 | u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO); | |
5713 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
5714 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
5715 | ||
5716 | if (vmx->nested.nested_run_pending) | |
5717 | return 0; | |
5718 | ||
5719 | if (unlikely(vmx->fail)) { | |
bd80158a JK |
5720 | pr_info_ratelimited("%s failed vm entry %x\n", __func__, |
5721 | vmcs_read32(VM_INSTRUCTION_ERROR)); | |
644d711a NHE |
5722 | return 1; |
5723 | } | |
5724 | ||
5725 | switch (exit_reason) { | |
5726 | case EXIT_REASON_EXCEPTION_NMI: | |
5727 | if (!is_exception(intr_info)) | |
5728 | return 0; | |
5729 | else if (is_page_fault(intr_info)) | |
5730 | return enable_ept; | |
5731 | return vmcs12->exception_bitmap & | |
5732 | (1u << (intr_info & INTR_INFO_VECTOR_MASK)); | |
5733 | case EXIT_REASON_EXTERNAL_INTERRUPT: | |
5734 | return 0; | |
5735 | case EXIT_REASON_TRIPLE_FAULT: | |
5736 | return 1; | |
5737 | case EXIT_REASON_PENDING_INTERRUPT: | |
5738 | case EXIT_REASON_NMI_WINDOW: | |
5739 | /* | |
5740 | * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit | |
5741 | * (aka Interrupt Window Exiting) only when L1 turned it on, | |
5742 | * so if we got a PENDING_INTERRUPT exit, this must be for L1. | |
5743 | * Same for NMI Window Exiting. | |
5744 | */ | |
5745 | return 1; | |
5746 | case EXIT_REASON_TASK_SWITCH: | |
5747 | return 1; | |
5748 | case EXIT_REASON_CPUID: | |
5749 | return 1; | |
5750 | case EXIT_REASON_HLT: | |
5751 | return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING); | |
5752 | case EXIT_REASON_INVD: | |
5753 | return 1; | |
5754 | case EXIT_REASON_INVLPG: | |
5755 | return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING); | |
5756 | case EXIT_REASON_RDPMC: | |
5757 | return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING); | |
5758 | case EXIT_REASON_RDTSC: | |
5759 | return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING); | |
5760 | case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR: | |
5761 | case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD: | |
5762 | case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD: | |
5763 | case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE: | |
5764 | case EXIT_REASON_VMOFF: case EXIT_REASON_VMON: | |
5765 | /* | |
5766 | * VMX instructions trap unconditionally. This allows L1 to | |
5767 | * emulate them for its L2 guest, i.e., allows 3-level nesting! | |
5768 | */ | |
5769 | return 1; | |
5770 | case EXIT_REASON_CR_ACCESS: | |
5771 | return nested_vmx_exit_handled_cr(vcpu, vmcs12); | |
5772 | case EXIT_REASON_DR_ACCESS: | |
5773 | return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING); | |
5774 | case EXIT_REASON_IO_INSTRUCTION: | |
5775 | /* TODO: support IO bitmaps */ | |
5776 | return 1; | |
5777 | case EXIT_REASON_MSR_READ: | |
5778 | case EXIT_REASON_MSR_WRITE: | |
5779 | return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason); | |
5780 | case EXIT_REASON_INVALID_STATE: | |
5781 | return 1; | |
5782 | case EXIT_REASON_MWAIT_INSTRUCTION: | |
5783 | return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING); | |
5784 | case EXIT_REASON_MONITOR_INSTRUCTION: | |
5785 | return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING); | |
5786 | case EXIT_REASON_PAUSE_INSTRUCTION: | |
5787 | return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) || | |
5788 | nested_cpu_has2(vmcs12, | |
5789 | SECONDARY_EXEC_PAUSE_LOOP_EXITING); | |
5790 | case EXIT_REASON_MCE_DURING_VMENTRY: | |
5791 | return 0; | |
5792 | case EXIT_REASON_TPR_BELOW_THRESHOLD: | |
5793 | return 1; | |
5794 | case EXIT_REASON_APIC_ACCESS: | |
5795 | return nested_cpu_has2(vmcs12, | |
5796 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES); | |
5797 | case EXIT_REASON_EPT_VIOLATION: | |
5798 | case EXIT_REASON_EPT_MISCONFIG: | |
5799 | return 0; | |
5800 | case EXIT_REASON_WBINVD: | |
5801 | return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING); | |
5802 | case EXIT_REASON_XSETBV: | |
5803 | return 1; | |
5804 | default: | |
5805 | return 1; | |
5806 | } | |
5807 | } | |
5808 | ||
586f9607 AK |
5809 | static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2) |
5810 | { | |
5811 | *info1 = vmcs_readl(EXIT_QUALIFICATION); | |
5812 | *info2 = vmcs_read32(VM_EXIT_INTR_INFO); | |
5813 | } | |
5814 | ||
6aa8b732 AK |
5815 | /* |
5816 | * The guest has exited. See if we can fix it or if we need userspace | |
5817 | * assistance. | |
5818 | */ | |
851ba692 | 5819 | static int vmx_handle_exit(struct kvm_vcpu *vcpu) |
6aa8b732 | 5820 | { |
29bd8a78 | 5821 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
a0861c02 | 5822 | u32 exit_reason = vmx->exit_reason; |
1155f76a | 5823 | u32 vectoring_info = vmx->idt_vectoring_info; |
29bd8a78 | 5824 | |
80ced186 MG |
5825 | /* If guest state is invalid, start emulating */ |
5826 | if (vmx->emulation_required && emulate_invalid_guest_state) | |
5827 | return handle_invalid_guest_state(vcpu); | |
1d5a4d9b | 5828 | |
b6f1250e NHE |
5829 | /* |
5830 | * the KVM_REQ_EVENT optimization bit is only on for one entry, and if | |
5831 | * we did not inject a still-pending event to L1 now because of | |
5832 | * nested_run_pending, we need to re-enable this bit. | |
5833 | */ | |
5834 | if (vmx->nested.nested_run_pending) | |
5835 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
5836 | ||
509c75ea NHE |
5837 | if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH || |
5838 | exit_reason == EXIT_REASON_VMRESUME)) | |
644d711a NHE |
5839 | vmx->nested.nested_run_pending = 1; |
5840 | else | |
5841 | vmx->nested.nested_run_pending = 0; | |
5842 | ||
5843 | if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) { | |
5844 | nested_vmx_vmexit(vcpu); | |
5845 | return 1; | |
5846 | } | |
5847 | ||
5120702e MG |
5848 | if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) { |
5849 | vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY; | |
5850 | vcpu->run->fail_entry.hardware_entry_failure_reason | |
5851 | = exit_reason; | |
5852 | return 0; | |
5853 | } | |
5854 | ||
29bd8a78 | 5855 | if (unlikely(vmx->fail)) { |
851ba692 AK |
5856 | vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY; |
5857 | vcpu->run->fail_entry.hardware_entry_failure_reason | |
29bd8a78 AK |
5858 | = vmcs_read32(VM_INSTRUCTION_ERROR); |
5859 | return 0; | |
5860 | } | |
6aa8b732 | 5861 | |
d77c26fc | 5862 | if ((vectoring_info & VECTORING_INFO_VALID_MASK) && |
1439442c | 5863 | (exit_reason != EXIT_REASON_EXCEPTION_NMI && |
60637aac JK |
5864 | exit_reason != EXIT_REASON_EPT_VIOLATION && |
5865 | exit_reason != EXIT_REASON_TASK_SWITCH)) | |
5866 | printk(KERN_WARNING "%s: unexpected, valid vectoring info " | |
5867 | "(0x%x) and exit reason is 0x%x\n", | |
5868 | __func__, vectoring_info, exit_reason); | |
3b86cd99 | 5869 | |
644d711a NHE |
5870 | if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked && |
5871 | !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis( | |
5872 | get_vmcs12(vcpu), vcpu)))) { | |
c4282df9 | 5873 | if (vmx_interrupt_allowed(vcpu)) { |
3b86cd99 | 5874 | vmx->soft_vnmi_blocked = 0; |
3b86cd99 | 5875 | } else if (vmx->vnmi_blocked_time > 1000000000LL && |
4531220b | 5876 | vcpu->arch.nmi_pending) { |
3b86cd99 JK |
5877 | /* |
5878 | * This CPU don't support us in finding the end of an | |
5879 | * NMI-blocked window if the guest runs with IRQs | |
5880 | * disabled. So we pull the trigger after 1 s of | |
5881 | * futile waiting, but inform the user about this. | |
5882 | */ | |
5883 | printk(KERN_WARNING "%s: Breaking out of NMI-blocked " | |
5884 | "state on VCPU %d after 1 s timeout\n", | |
5885 | __func__, vcpu->vcpu_id); | |
5886 | vmx->soft_vnmi_blocked = 0; | |
3b86cd99 | 5887 | } |
3b86cd99 JK |
5888 | } |
5889 | ||
6aa8b732 AK |
5890 | if (exit_reason < kvm_vmx_max_exit_handlers |
5891 | && kvm_vmx_exit_handlers[exit_reason]) | |
851ba692 | 5892 | return kvm_vmx_exit_handlers[exit_reason](vcpu); |
6aa8b732 | 5893 | else { |
851ba692 AK |
5894 | vcpu->run->exit_reason = KVM_EXIT_UNKNOWN; |
5895 | vcpu->run->hw.hardware_exit_reason = exit_reason; | |
6aa8b732 AK |
5896 | } |
5897 | return 0; | |
5898 | } | |
5899 | ||
95ba8273 | 5900 | static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr) |
6e5d865c | 5901 | { |
95ba8273 | 5902 | if (irr == -1 || tpr < irr) { |
6e5d865c YS |
5903 | vmcs_write32(TPR_THRESHOLD, 0); |
5904 | return; | |
5905 | } | |
5906 | ||
95ba8273 | 5907 | vmcs_write32(TPR_THRESHOLD, irr); |
6e5d865c YS |
5908 | } |
5909 | ||
51aa01d1 | 5910 | static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx) |
cf393f75 | 5911 | { |
00eba012 AK |
5912 | u32 exit_intr_info; |
5913 | ||
5914 | if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY | |
5915 | || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI)) | |
5916 | return; | |
5917 | ||
c5ca8e57 | 5918 | vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); |
00eba012 | 5919 | exit_intr_info = vmx->exit_intr_info; |
a0861c02 AK |
5920 | |
5921 | /* Handle machine checks before interrupts are enabled */ | |
00eba012 | 5922 | if (is_machine_check(exit_intr_info)) |
a0861c02 AK |
5923 | kvm_machine_check(); |
5924 | ||
20f65983 | 5925 | /* We need to handle NMIs before interrupts are enabled */ |
00eba012 | 5926 | if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR && |
ff9d07a0 ZY |
5927 | (exit_intr_info & INTR_INFO_VALID_MASK)) { |
5928 | kvm_before_handle_nmi(&vmx->vcpu); | |
20f65983 | 5929 | asm("int $2"); |
ff9d07a0 ZY |
5930 | kvm_after_handle_nmi(&vmx->vcpu); |
5931 | } | |
51aa01d1 | 5932 | } |
20f65983 | 5933 | |
51aa01d1 AK |
5934 | static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx) |
5935 | { | |
c5ca8e57 | 5936 | u32 exit_intr_info; |
51aa01d1 AK |
5937 | bool unblock_nmi; |
5938 | u8 vector; | |
5939 | bool idtv_info_valid; | |
5940 | ||
5941 | idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK; | |
20f65983 | 5942 | |
cf393f75 | 5943 | if (cpu_has_virtual_nmis()) { |
9d58b931 AK |
5944 | if (vmx->nmi_known_unmasked) |
5945 | return; | |
c5ca8e57 AK |
5946 | /* |
5947 | * Can't use vmx->exit_intr_info since we're not sure what | |
5948 | * the exit reason is. | |
5949 | */ | |
5950 | exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); | |
cf393f75 AK |
5951 | unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0; |
5952 | vector = exit_intr_info & INTR_INFO_VECTOR_MASK; | |
5953 | /* | |
7b4a25cb | 5954 | * SDM 3: 27.7.1.2 (September 2008) |
cf393f75 AK |
5955 | * Re-set bit "block by NMI" before VM entry if vmexit caused by |
5956 | * a guest IRET fault. | |
7b4a25cb GN |
5957 | * SDM 3: 23.2.2 (September 2008) |
5958 | * Bit 12 is undefined in any of the following cases: | |
5959 | * If the VM exit sets the valid bit in the IDT-vectoring | |
5960 | * information field. | |
5961 | * If the VM exit is due to a double fault. | |
cf393f75 | 5962 | */ |
7b4a25cb GN |
5963 | if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi && |
5964 | vector != DF_VECTOR && !idtv_info_valid) | |
cf393f75 AK |
5965 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, |
5966 | GUEST_INTR_STATE_NMI); | |
9d58b931 AK |
5967 | else |
5968 | vmx->nmi_known_unmasked = | |
5969 | !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) | |
5970 | & GUEST_INTR_STATE_NMI); | |
3b86cd99 JK |
5971 | } else if (unlikely(vmx->soft_vnmi_blocked)) |
5972 | vmx->vnmi_blocked_time += | |
5973 | ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time)); | |
51aa01d1 AK |
5974 | } |
5975 | ||
83422e17 AK |
5976 | static void __vmx_complete_interrupts(struct vcpu_vmx *vmx, |
5977 | u32 idt_vectoring_info, | |
5978 | int instr_len_field, | |
5979 | int error_code_field) | |
51aa01d1 | 5980 | { |
51aa01d1 AK |
5981 | u8 vector; |
5982 | int type; | |
5983 | bool idtv_info_valid; | |
5984 | ||
5985 | idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK; | |
668f612f | 5986 | |
37b96e98 GN |
5987 | vmx->vcpu.arch.nmi_injected = false; |
5988 | kvm_clear_exception_queue(&vmx->vcpu); | |
5989 | kvm_clear_interrupt_queue(&vmx->vcpu); | |
5990 | ||
5991 | if (!idtv_info_valid) | |
5992 | return; | |
5993 | ||
3842d135 AK |
5994 | kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu); |
5995 | ||
668f612f AK |
5996 | vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK; |
5997 | type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK; | |
37b96e98 | 5998 | |
64a7ec06 | 5999 | switch (type) { |
37b96e98 GN |
6000 | case INTR_TYPE_NMI_INTR: |
6001 | vmx->vcpu.arch.nmi_injected = true; | |
668f612f | 6002 | /* |
7b4a25cb | 6003 | * SDM 3: 27.7.1.2 (September 2008) |
37b96e98 GN |
6004 | * Clear bit "block by NMI" before VM entry if a NMI |
6005 | * delivery faulted. | |
668f612f | 6006 | */ |
654f06fc | 6007 | vmx_set_nmi_mask(&vmx->vcpu, false); |
37b96e98 | 6008 | break; |
37b96e98 | 6009 | case INTR_TYPE_SOFT_EXCEPTION: |
66fd3f7f | 6010 | vmx->vcpu.arch.event_exit_inst_len = |
83422e17 | 6011 | vmcs_read32(instr_len_field); |
66fd3f7f GN |
6012 | /* fall through */ |
6013 | case INTR_TYPE_HARD_EXCEPTION: | |
35920a35 | 6014 | if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) { |
83422e17 | 6015 | u32 err = vmcs_read32(error_code_field); |
37b96e98 | 6016 | kvm_queue_exception_e(&vmx->vcpu, vector, err); |
35920a35 AK |
6017 | } else |
6018 | kvm_queue_exception(&vmx->vcpu, vector); | |
37b96e98 | 6019 | break; |
66fd3f7f GN |
6020 | case INTR_TYPE_SOFT_INTR: |
6021 | vmx->vcpu.arch.event_exit_inst_len = | |
83422e17 | 6022 | vmcs_read32(instr_len_field); |
66fd3f7f | 6023 | /* fall through */ |
37b96e98 | 6024 | case INTR_TYPE_EXT_INTR: |
66fd3f7f GN |
6025 | kvm_queue_interrupt(&vmx->vcpu, vector, |
6026 | type == INTR_TYPE_SOFT_INTR); | |
37b96e98 GN |
6027 | break; |
6028 | default: | |
6029 | break; | |
f7d9238f | 6030 | } |
cf393f75 AK |
6031 | } |
6032 | ||
83422e17 AK |
6033 | static void vmx_complete_interrupts(struct vcpu_vmx *vmx) |
6034 | { | |
66c78ae4 NHE |
6035 | if (is_guest_mode(&vmx->vcpu)) |
6036 | return; | |
83422e17 AK |
6037 | __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info, |
6038 | VM_EXIT_INSTRUCTION_LEN, | |
6039 | IDT_VECTORING_ERROR_CODE); | |
6040 | } | |
6041 | ||
b463a6f7 AK |
6042 | static void vmx_cancel_injection(struct kvm_vcpu *vcpu) |
6043 | { | |
66c78ae4 NHE |
6044 | if (is_guest_mode(vcpu)) |
6045 | return; | |
b463a6f7 AK |
6046 | __vmx_complete_interrupts(to_vmx(vcpu), |
6047 | vmcs_read32(VM_ENTRY_INTR_INFO_FIELD), | |
6048 | VM_ENTRY_INSTRUCTION_LEN, | |
6049 | VM_ENTRY_EXCEPTION_ERROR_CODE); | |
6050 | ||
6051 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); | |
6052 | } | |
6053 | ||
d7cd9796 GN |
6054 | static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx) |
6055 | { | |
6056 | int i, nr_msrs; | |
6057 | struct perf_guest_switch_msr *msrs; | |
6058 | ||
6059 | msrs = perf_guest_get_msrs(&nr_msrs); | |
6060 | ||
6061 | if (!msrs) | |
6062 | return; | |
6063 | ||
6064 | for (i = 0; i < nr_msrs; i++) | |
6065 | if (msrs[i].host == msrs[i].guest) | |
6066 | clear_atomic_switch_msr(vmx, msrs[i].msr); | |
6067 | else | |
6068 | add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest, | |
6069 | msrs[i].host); | |
6070 | } | |
6071 | ||
c801949d AK |
6072 | #ifdef CONFIG_X86_64 |
6073 | #define R "r" | |
6074 | #define Q "q" | |
6075 | #else | |
6076 | #define R "e" | |
6077 | #define Q "l" | |
6078 | #endif | |
6079 | ||
a3b5ba49 | 6080 | static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu) |
6aa8b732 | 6081 | { |
a2fa3e9f | 6082 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
104f226b | 6083 | |
66c78ae4 NHE |
6084 | if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending) { |
6085 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
6086 | if (vmcs12->idt_vectoring_info_field & | |
6087 | VECTORING_INFO_VALID_MASK) { | |
6088 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, | |
6089 | vmcs12->idt_vectoring_info_field); | |
6090 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, | |
6091 | vmcs12->vm_exit_instruction_len); | |
6092 | if (vmcs12->idt_vectoring_info_field & | |
6093 | VECTORING_INFO_DELIVER_CODE_MASK) | |
6094 | vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, | |
6095 | vmcs12->idt_vectoring_error_code); | |
6096 | } | |
6097 | } | |
6098 | ||
104f226b AK |
6099 | /* Record the guest's net vcpu time for enforced NMI injections. */ |
6100 | if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) | |
6101 | vmx->entry_time = ktime_get(); | |
6102 | ||
6103 | /* Don't enter VMX if guest state is invalid, let the exit handler | |
6104 | start emulation until we arrive back to a valid state */ | |
6105 | if (vmx->emulation_required && emulate_invalid_guest_state) | |
6106 | return; | |
6107 | ||
6108 | if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty)) | |
6109 | vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]); | |
6110 | if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty)) | |
6111 | vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]); | |
6112 | ||
6113 | /* When single-stepping over STI and MOV SS, we must clear the | |
6114 | * corresponding interruptibility bits in the guest state. Otherwise | |
6115 | * vmentry fails as it then expects bit 14 (BS) in pending debug | |
6116 | * exceptions being set, but that's not correct for the guest debugging | |
6117 | * case. */ | |
6118 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) | |
6119 | vmx_set_interrupt_shadow(vcpu, 0); | |
6120 | ||
d7cd9796 GN |
6121 | atomic_switch_perf_msrs(vmx); |
6122 | ||
d462b819 | 6123 | vmx->__launched = vmx->loaded_vmcs->launched; |
104f226b | 6124 | asm( |
6aa8b732 | 6125 | /* Store host registers */ |
c801949d | 6126 | "push %%"R"dx; push %%"R"bp;" |
40712fae | 6127 | "push %%"R"cx \n\t" /* placeholder for guest rcx */ |
c801949d | 6128 | "push %%"R"cx \n\t" |
313dbd49 AK |
6129 | "cmp %%"R"sp, %c[host_rsp](%0) \n\t" |
6130 | "je 1f \n\t" | |
6131 | "mov %%"R"sp, %c[host_rsp](%0) \n\t" | |
4ecac3fd | 6132 | __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t" |
313dbd49 | 6133 | "1: \n\t" |
d3edefc0 AK |
6134 | /* Reload cr2 if changed */ |
6135 | "mov %c[cr2](%0), %%"R"ax \n\t" | |
6136 | "mov %%cr2, %%"R"dx \n\t" | |
6137 | "cmp %%"R"ax, %%"R"dx \n\t" | |
6138 | "je 2f \n\t" | |
6139 | "mov %%"R"ax, %%cr2 \n\t" | |
6140 | "2: \n\t" | |
6aa8b732 | 6141 | /* Check if vmlaunch of vmresume is needed */ |
e08aa78a | 6142 | "cmpl $0, %c[launched](%0) \n\t" |
6aa8b732 | 6143 | /* Load guest registers. Don't clobber flags. */ |
c801949d AK |
6144 | "mov %c[rax](%0), %%"R"ax \n\t" |
6145 | "mov %c[rbx](%0), %%"R"bx \n\t" | |
6146 | "mov %c[rdx](%0), %%"R"dx \n\t" | |
6147 | "mov %c[rsi](%0), %%"R"si \n\t" | |
6148 | "mov %c[rdi](%0), %%"R"di \n\t" | |
6149 | "mov %c[rbp](%0), %%"R"bp \n\t" | |
05b3e0c2 | 6150 | #ifdef CONFIG_X86_64 |
e08aa78a AK |
6151 | "mov %c[r8](%0), %%r8 \n\t" |
6152 | "mov %c[r9](%0), %%r9 \n\t" | |
6153 | "mov %c[r10](%0), %%r10 \n\t" | |
6154 | "mov %c[r11](%0), %%r11 \n\t" | |
6155 | "mov %c[r12](%0), %%r12 \n\t" | |
6156 | "mov %c[r13](%0), %%r13 \n\t" | |
6157 | "mov %c[r14](%0), %%r14 \n\t" | |
6158 | "mov %c[r15](%0), %%r15 \n\t" | |
6aa8b732 | 6159 | #endif |
c801949d AK |
6160 | "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */ |
6161 | ||
6aa8b732 | 6162 | /* Enter guest mode */ |
cd2276a7 | 6163 | "jne .Llaunched \n\t" |
4ecac3fd | 6164 | __ex(ASM_VMX_VMLAUNCH) "\n\t" |
cd2276a7 | 6165 | "jmp .Lkvm_vmx_return \n\t" |
4ecac3fd | 6166 | ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t" |
cd2276a7 | 6167 | ".Lkvm_vmx_return: " |
6aa8b732 | 6168 | /* Save guest registers, load host registers, keep flags */ |
40712fae AK |
6169 | "mov %0, %c[wordsize](%%"R"sp) \n\t" |
6170 | "pop %0 \n\t" | |
c801949d AK |
6171 | "mov %%"R"ax, %c[rax](%0) \n\t" |
6172 | "mov %%"R"bx, %c[rbx](%0) \n\t" | |
1c696d0e | 6173 | "pop"Q" %c[rcx](%0) \n\t" |
c801949d AK |
6174 | "mov %%"R"dx, %c[rdx](%0) \n\t" |
6175 | "mov %%"R"si, %c[rsi](%0) \n\t" | |
6176 | "mov %%"R"di, %c[rdi](%0) \n\t" | |
6177 | "mov %%"R"bp, %c[rbp](%0) \n\t" | |
05b3e0c2 | 6178 | #ifdef CONFIG_X86_64 |
e08aa78a AK |
6179 | "mov %%r8, %c[r8](%0) \n\t" |
6180 | "mov %%r9, %c[r9](%0) \n\t" | |
6181 | "mov %%r10, %c[r10](%0) \n\t" | |
6182 | "mov %%r11, %c[r11](%0) \n\t" | |
6183 | "mov %%r12, %c[r12](%0) \n\t" | |
6184 | "mov %%r13, %c[r13](%0) \n\t" | |
6185 | "mov %%r14, %c[r14](%0) \n\t" | |
6186 | "mov %%r15, %c[r15](%0) \n\t" | |
6aa8b732 | 6187 | #endif |
c801949d AK |
6188 | "mov %%cr2, %%"R"ax \n\t" |
6189 | "mov %%"R"ax, %c[cr2](%0) \n\t" | |
6190 | ||
1c696d0e | 6191 | "pop %%"R"bp; pop %%"R"dx \n\t" |
e08aa78a AK |
6192 | "setbe %c[fail](%0) \n\t" |
6193 | : : "c"(vmx), "d"((unsigned long)HOST_RSP), | |
d462b819 | 6194 | [launched]"i"(offsetof(struct vcpu_vmx, __launched)), |
e08aa78a | 6195 | [fail]"i"(offsetof(struct vcpu_vmx, fail)), |
313dbd49 | 6196 | [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)), |
ad312c7c ZX |
6197 | [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])), |
6198 | [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])), | |
6199 | [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])), | |
6200 | [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])), | |
6201 | [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])), | |
6202 | [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])), | |
6203 | [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])), | |
05b3e0c2 | 6204 | #ifdef CONFIG_X86_64 |
ad312c7c ZX |
6205 | [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])), |
6206 | [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])), | |
6207 | [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])), | |
6208 | [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])), | |
6209 | [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])), | |
6210 | [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])), | |
6211 | [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])), | |
6212 | [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])), | |
6aa8b732 | 6213 | #endif |
40712fae AK |
6214 | [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)), |
6215 | [wordsize]"i"(sizeof(ulong)) | |
c2036300 | 6216 | : "cc", "memory" |
07d6f555 | 6217 | , R"ax", R"bx", R"di", R"si" |
c2036300 | 6218 | #ifdef CONFIG_X86_64 |
c2036300 LV |
6219 | , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" |
6220 | #endif | |
6221 | ); | |
6aa8b732 | 6222 | |
6de4f3ad | 6223 | vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP) |
6de12732 | 6224 | | (1 << VCPU_EXREG_RFLAGS) |
69c73028 | 6225 | | (1 << VCPU_EXREG_CPL) |
aff48baa | 6226 | | (1 << VCPU_EXREG_PDPTR) |
2fb92db1 | 6227 | | (1 << VCPU_EXREG_SEGMENTS) |
aff48baa | 6228 | | (1 << VCPU_EXREG_CR3)); |
5fdbf976 MT |
6229 | vcpu->arch.regs_dirty = 0; |
6230 | ||
1155f76a AK |
6231 | vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD); |
6232 | ||
66c78ae4 NHE |
6233 | if (is_guest_mode(vcpu)) { |
6234 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
6235 | vmcs12->idt_vectoring_info_field = vmx->idt_vectoring_info; | |
6236 | if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) { | |
6237 | vmcs12->idt_vectoring_error_code = | |
6238 | vmcs_read32(IDT_VECTORING_ERROR_CODE); | |
6239 | vmcs12->vm_exit_instruction_len = | |
6240 | vmcs_read32(VM_EXIT_INSTRUCTION_LEN); | |
6241 | } | |
6242 | } | |
6243 | ||
d77c26fc | 6244 | asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS)); |
d462b819 | 6245 | vmx->loaded_vmcs->launched = 1; |
1b6269db | 6246 | |
51aa01d1 | 6247 | vmx->exit_reason = vmcs_read32(VM_EXIT_REASON); |
1e2b1dd7 | 6248 | trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX); |
51aa01d1 AK |
6249 | |
6250 | vmx_complete_atomic_exit(vmx); | |
6251 | vmx_recover_nmi_blocking(vmx); | |
cf393f75 | 6252 | vmx_complete_interrupts(vmx); |
6aa8b732 AK |
6253 | } |
6254 | ||
c801949d AK |
6255 | #undef R |
6256 | #undef Q | |
6257 | ||
6aa8b732 AK |
6258 | static void vmx_free_vcpu(struct kvm_vcpu *vcpu) |
6259 | { | |
fb3f0f51 RR |
6260 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6261 | ||
cdbecfc3 | 6262 | free_vpid(vmx); |
ec378aee | 6263 | free_nested(vmx); |
d462b819 | 6264 | free_loaded_vmcs(vmx->loaded_vmcs); |
fb3f0f51 RR |
6265 | kfree(vmx->guest_msrs); |
6266 | kvm_vcpu_uninit(vcpu); | |
a4770347 | 6267 | kmem_cache_free(kvm_vcpu_cache, vmx); |
6aa8b732 AK |
6268 | } |
6269 | ||
fb3f0f51 | 6270 | static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 6271 | { |
fb3f0f51 | 6272 | int err; |
c16f862d | 6273 | struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); |
15ad7146 | 6274 | int cpu; |
6aa8b732 | 6275 | |
a2fa3e9f | 6276 | if (!vmx) |
fb3f0f51 RR |
6277 | return ERR_PTR(-ENOMEM); |
6278 | ||
2384d2b3 SY |
6279 | allocate_vpid(vmx); |
6280 | ||
fb3f0f51 RR |
6281 | err = kvm_vcpu_init(&vmx->vcpu, kvm, id); |
6282 | if (err) | |
6283 | goto free_vcpu; | |
965b58a5 | 6284 | |
a2fa3e9f | 6285 | vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL); |
be6d05cf | 6286 | err = -ENOMEM; |
fb3f0f51 | 6287 | if (!vmx->guest_msrs) { |
fb3f0f51 RR |
6288 | goto uninit_vcpu; |
6289 | } | |
965b58a5 | 6290 | |
d462b819 NHE |
6291 | vmx->loaded_vmcs = &vmx->vmcs01; |
6292 | vmx->loaded_vmcs->vmcs = alloc_vmcs(); | |
6293 | if (!vmx->loaded_vmcs->vmcs) | |
fb3f0f51 | 6294 | goto free_msrs; |
d462b819 NHE |
6295 | if (!vmm_exclusive) |
6296 | kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id()))); | |
6297 | loaded_vmcs_init(vmx->loaded_vmcs); | |
6298 | if (!vmm_exclusive) | |
6299 | kvm_cpu_vmxoff(); | |
a2fa3e9f | 6300 | |
15ad7146 AK |
6301 | cpu = get_cpu(); |
6302 | vmx_vcpu_load(&vmx->vcpu, cpu); | |
e48672fa | 6303 | vmx->vcpu.cpu = cpu; |
8b9cf98c | 6304 | err = vmx_vcpu_setup(vmx); |
fb3f0f51 | 6305 | vmx_vcpu_put(&vmx->vcpu); |
15ad7146 | 6306 | put_cpu(); |
fb3f0f51 RR |
6307 | if (err) |
6308 | goto free_vmcs; | |
5e4a0b3c | 6309 | if (vm_need_virtualize_apic_accesses(kvm)) |
be6d05cf JK |
6310 | err = alloc_apic_access_page(kvm); |
6311 | if (err) | |
5e4a0b3c | 6312 | goto free_vmcs; |
fb3f0f51 | 6313 | |
b927a3ce SY |
6314 | if (enable_ept) { |
6315 | if (!kvm->arch.ept_identity_map_addr) | |
6316 | kvm->arch.ept_identity_map_addr = | |
6317 | VMX_EPT_IDENTITY_PAGETABLE_ADDR; | |
93ea5388 | 6318 | err = -ENOMEM; |
b7ebfb05 SY |
6319 | if (alloc_identity_pagetable(kvm) != 0) |
6320 | goto free_vmcs; | |
93ea5388 GN |
6321 | if (!init_rmode_identity_map(kvm)) |
6322 | goto free_vmcs; | |
b927a3ce | 6323 | } |
b7ebfb05 | 6324 | |
a9d30f33 NHE |
6325 | vmx->nested.current_vmptr = -1ull; |
6326 | vmx->nested.current_vmcs12 = NULL; | |
6327 | ||
fb3f0f51 RR |
6328 | return &vmx->vcpu; |
6329 | ||
6330 | free_vmcs: | |
d462b819 | 6331 | free_vmcs(vmx->loaded_vmcs->vmcs); |
fb3f0f51 | 6332 | free_msrs: |
fb3f0f51 RR |
6333 | kfree(vmx->guest_msrs); |
6334 | uninit_vcpu: | |
6335 | kvm_vcpu_uninit(&vmx->vcpu); | |
6336 | free_vcpu: | |
cdbecfc3 | 6337 | free_vpid(vmx); |
a4770347 | 6338 | kmem_cache_free(kvm_vcpu_cache, vmx); |
fb3f0f51 | 6339 | return ERR_PTR(err); |
6aa8b732 AK |
6340 | } |
6341 | ||
002c7f7c YS |
6342 | static void __init vmx_check_processor_compat(void *rtn) |
6343 | { | |
6344 | struct vmcs_config vmcs_conf; | |
6345 | ||
6346 | *(int *)rtn = 0; | |
6347 | if (setup_vmcs_config(&vmcs_conf) < 0) | |
6348 | *(int *)rtn = -EIO; | |
6349 | if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) { | |
6350 | printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n", | |
6351 | smp_processor_id()); | |
6352 | *(int *)rtn = -EIO; | |
6353 | } | |
6354 | } | |
6355 | ||
67253af5 SY |
6356 | static int get_ept_level(void) |
6357 | { | |
6358 | return VMX_EPT_DEFAULT_GAW + 1; | |
6359 | } | |
6360 | ||
4b12f0de | 6361 | static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio) |
64d4d521 | 6362 | { |
4b12f0de SY |
6363 | u64 ret; |
6364 | ||
522c68c4 SY |
6365 | /* For VT-d and EPT combination |
6366 | * 1. MMIO: always map as UC | |
6367 | * 2. EPT with VT-d: | |
6368 | * a. VT-d without snooping control feature: can't guarantee the | |
6369 | * result, try to trust guest. | |
6370 | * b. VT-d with snooping control feature: snooping control feature of | |
6371 | * VT-d engine can guarantee the cache correctness. Just set it | |
6372 | * to WB to keep consistent with host. So the same as item 3. | |
a19a6d11 | 6373 | * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep |
522c68c4 SY |
6374 | * consistent with host MTRR |
6375 | */ | |
4b12f0de SY |
6376 | if (is_mmio) |
6377 | ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT; | |
522c68c4 SY |
6378 | else if (vcpu->kvm->arch.iommu_domain && |
6379 | !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY)) | |
6380 | ret = kvm_get_guest_memory_type(vcpu, gfn) << | |
6381 | VMX_EPT_MT_EPTE_SHIFT; | |
4b12f0de | 6382 | else |
522c68c4 | 6383 | ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT) |
a19a6d11 | 6384 | | VMX_EPT_IPAT_BIT; |
4b12f0de SY |
6385 | |
6386 | return ret; | |
64d4d521 SY |
6387 | } |
6388 | ||
17cc3935 | 6389 | static int vmx_get_lpage_level(void) |
344f414f | 6390 | { |
878403b7 SY |
6391 | if (enable_ept && !cpu_has_vmx_ept_1g_page()) |
6392 | return PT_DIRECTORY_LEVEL; | |
6393 | else | |
6394 | /* For shadow and EPT supported 1GB page */ | |
6395 | return PT_PDPE_LEVEL; | |
344f414f JR |
6396 | } |
6397 | ||
0e851880 SY |
6398 | static void vmx_cpuid_update(struct kvm_vcpu *vcpu) |
6399 | { | |
4e47c7a6 SY |
6400 | struct kvm_cpuid_entry2 *best; |
6401 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
6402 | u32 exec_control; | |
6403 | ||
6404 | vmx->rdtscp_enabled = false; | |
6405 | if (vmx_rdtscp_supported()) { | |
6406 | exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL); | |
6407 | if (exec_control & SECONDARY_EXEC_RDTSCP) { | |
6408 | best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); | |
6409 | if (best && (best->edx & bit(X86_FEATURE_RDTSCP))) | |
6410 | vmx->rdtscp_enabled = true; | |
6411 | else { | |
6412 | exec_control &= ~SECONDARY_EXEC_RDTSCP; | |
6413 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, | |
6414 | exec_control); | |
6415 | } | |
6416 | } | |
6417 | } | |
0e851880 SY |
6418 | } |
6419 | ||
d4330ef2 JR |
6420 | static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry) |
6421 | { | |
7b8050f5 NHE |
6422 | if (func == 1 && nested) |
6423 | entry->ecx |= bit(X86_FEATURE_VMX); | |
d4330ef2 JR |
6424 | } |
6425 | ||
fe3ef05c NHE |
6426 | /* |
6427 | * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested | |
6428 | * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it | |
6429 | * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2 | |
6430 | * guest in a way that will both be appropriate to L1's requests, and our | |
6431 | * needs. In addition to modifying the active vmcs (which is vmcs02), this | |
6432 | * function also has additional necessary side-effects, like setting various | |
6433 | * vcpu->arch fields. | |
6434 | */ | |
6435 | static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12) | |
6436 | { | |
6437 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
6438 | u32 exec_control; | |
6439 | ||
6440 | vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector); | |
6441 | vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector); | |
6442 | vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector); | |
6443 | vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector); | |
6444 | vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector); | |
6445 | vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector); | |
6446 | vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector); | |
6447 | vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector); | |
6448 | vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit); | |
6449 | vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit); | |
6450 | vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit); | |
6451 | vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit); | |
6452 | vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit); | |
6453 | vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit); | |
6454 | vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit); | |
6455 | vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit); | |
6456 | vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit); | |
6457 | vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit); | |
6458 | vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes); | |
6459 | vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes); | |
6460 | vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes); | |
6461 | vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes); | |
6462 | vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes); | |
6463 | vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes); | |
6464 | vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes); | |
6465 | vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes); | |
6466 | vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base); | |
6467 | vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base); | |
6468 | vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base); | |
6469 | vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base); | |
6470 | vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base); | |
6471 | vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base); | |
6472 | vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base); | |
6473 | vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base); | |
6474 | vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base); | |
6475 | vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base); | |
6476 | ||
6477 | vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl); | |
6478 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, | |
6479 | vmcs12->vm_entry_intr_info_field); | |
6480 | vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, | |
6481 | vmcs12->vm_entry_exception_error_code); | |
6482 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, | |
6483 | vmcs12->vm_entry_instruction_len); | |
6484 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, | |
6485 | vmcs12->guest_interruptibility_info); | |
6486 | vmcs_write32(GUEST_ACTIVITY_STATE, vmcs12->guest_activity_state); | |
6487 | vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs); | |
6488 | vmcs_writel(GUEST_DR7, vmcs12->guest_dr7); | |
6489 | vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags); | |
6490 | vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, | |
6491 | vmcs12->guest_pending_dbg_exceptions); | |
6492 | vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp); | |
6493 | vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip); | |
6494 | ||
6495 | vmcs_write64(VMCS_LINK_POINTER, -1ull); | |
6496 | ||
6497 | vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, | |
6498 | (vmcs_config.pin_based_exec_ctrl | | |
6499 | vmcs12->pin_based_vm_exec_control)); | |
6500 | ||
6501 | /* | |
6502 | * Whether page-faults are trapped is determined by a combination of | |
6503 | * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF. | |
6504 | * If enable_ept, L0 doesn't care about page faults and we should | |
6505 | * set all of these to L1's desires. However, if !enable_ept, L0 does | |
6506 | * care about (at least some) page faults, and because it is not easy | |
6507 | * (if at all possible?) to merge L0 and L1's desires, we simply ask | |
6508 | * to exit on each and every L2 page fault. This is done by setting | |
6509 | * MASK=MATCH=0 and (see below) EB.PF=1. | |
6510 | * Note that below we don't need special code to set EB.PF beyond the | |
6511 | * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept, | |
6512 | * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when | |
6513 | * !enable_ept, EB.PF is 1, so the "or" will always be 1. | |
6514 | * | |
6515 | * A problem with this approach (when !enable_ept) is that L1 may be | |
6516 | * injected with more page faults than it asked for. This could have | |
6517 | * caused problems, but in practice existing hypervisors don't care. | |
6518 | * To fix this, we will need to emulate the PFEC checking (on the L1 | |
6519 | * page tables), using walk_addr(), when injecting PFs to L1. | |
6520 | */ | |
6521 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, | |
6522 | enable_ept ? vmcs12->page_fault_error_code_mask : 0); | |
6523 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, | |
6524 | enable_ept ? vmcs12->page_fault_error_code_match : 0); | |
6525 | ||
6526 | if (cpu_has_secondary_exec_ctrls()) { | |
6527 | u32 exec_control = vmx_secondary_exec_control(vmx); | |
6528 | if (!vmx->rdtscp_enabled) | |
6529 | exec_control &= ~SECONDARY_EXEC_RDTSCP; | |
6530 | /* Take the following fields only from vmcs12 */ | |
6531 | exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
6532 | if (nested_cpu_has(vmcs12, | |
6533 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)) | |
6534 | exec_control |= vmcs12->secondary_vm_exec_control; | |
6535 | ||
6536 | if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) { | |
6537 | /* | |
6538 | * Translate L1 physical address to host physical | |
6539 | * address for vmcs02. Keep the page pinned, so this | |
6540 | * physical address remains valid. We keep a reference | |
6541 | * to it so we can release it later. | |
6542 | */ | |
6543 | if (vmx->nested.apic_access_page) /* shouldn't happen */ | |
6544 | nested_release_page(vmx->nested.apic_access_page); | |
6545 | vmx->nested.apic_access_page = | |
6546 | nested_get_page(vcpu, vmcs12->apic_access_addr); | |
6547 | /* | |
6548 | * If translation failed, no matter: This feature asks | |
6549 | * to exit when accessing the given address, and if it | |
6550 | * can never be accessed, this feature won't do | |
6551 | * anything anyway. | |
6552 | */ | |
6553 | if (!vmx->nested.apic_access_page) | |
6554 | exec_control &= | |
6555 | ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
6556 | else | |
6557 | vmcs_write64(APIC_ACCESS_ADDR, | |
6558 | page_to_phys(vmx->nested.apic_access_page)); | |
6559 | } | |
6560 | ||
6561 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control); | |
6562 | } | |
6563 | ||
6564 | ||
6565 | /* | |
6566 | * Set host-state according to L0's settings (vmcs12 is irrelevant here) | |
6567 | * Some constant fields are set here by vmx_set_constant_host_state(). | |
6568 | * Other fields are different per CPU, and will be set later when | |
6569 | * vmx_vcpu_load() is called, and when vmx_save_host_state() is called. | |
6570 | */ | |
6571 | vmx_set_constant_host_state(); | |
6572 | ||
6573 | /* | |
6574 | * HOST_RSP is normally set correctly in vmx_vcpu_run() just before | |
6575 | * entry, but only if the current (host) sp changed from the value | |
6576 | * we wrote last (vmx->host_rsp). This cache is no longer relevant | |
6577 | * if we switch vmcs, and rather than hold a separate cache per vmcs, | |
6578 | * here we just force the write to happen on entry. | |
6579 | */ | |
6580 | vmx->host_rsp = 0; | |
6581 | ||
6582 | exec_control = vmx_exec_control(vmx); /* L0's desires */ | |
6583 | exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING; | |
6584 | exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING; | |
6585 | exec_control &= ~CPU_BASED_TPR_SHADOW; | |
6586 | exec_control |= vmcs12->cpu_based_vm_exec_control; | |
6587 | /* | |
6588 | * Merging of IO and MSR bitmaps not currently supported. | |
6589 | * Rather, exit every time. | |
6590 | */ | |
6591 | exec_control &= ~CPU_BASED_USE_MSR_BITMAPS; | |
6592 | exec_control &= ~CPU_BASED_USE_IO_BITMAPS; | |
6593 | exec_control |= CPU_BASED_UNCOND_IO_EXITING; | |
6594 | ||
6595 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control); | |
6596 | ||
6597 | /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the | |
6598 | * bitwise-or of what L1 wants to trap for L2, and what we want to | |
6599 | * trap. Note that CR0.TS also needs updating - we do this later. | |
6600 | */ | |
6601 | update_exception_bitmap(vcpu); | |
6602 | vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask; | |
6603 | vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits); | |
6604 | ||
6605 | /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */ | |
6606 | vmcs_write32(VM_EXIT_CONTROLS, | |
6607 | vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl); | |
6608 | vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls | | |
6609 | (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE)); | |
6610 | ||
6611 | if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) | |
6612 | vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat); | |
6613 | else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) | |
6614 | vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat); | |
6615 | ||
6616 | ||
6617 | set_cr4_guest_host_mask(vmx); | |
6618 | ||
27fc51b2 NHE |
6619 | if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING) |
6620 | vmcs_write64(TSC_OFFSET, | |
6621 | vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset); | |
6622 | else | |
6623 | vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset); | |
fe3ef05c NHE |
6624 | |
6625 | if (enable_vpid) { | |
6626 | /* | |
6627 | * Trivially support vpid by letting L2s share their parent | |
6628 | * L1's vpid. TODO: move to a more elaborate solution, giving | |
6629 | * each L2 its own vpid and exposing the vpid feature to L1. | |
6630 | */ | |
6631 | vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid); | |
6632 | vmx_flush_tlb(vcpu); | |
6633 | } | |
6634 | ||
6635 | if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) | |
6636 | vcpu->arch.efer = vmcs12->guest_ia32_efer; | |
6637 | if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) | |
6638 | vcpu->arch.efer |= (EFER_LMA | EFER_LME); | |
6639 | else | |
6640 | vcpu->arch.efer &= ~(EFER_LMA | EFER_LME); | |
6641 | /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */ | |
6642 | vmx_set_efer(vcpu, vcpu->arch.efer); | |
6643 | ||
6644 | /* | |
6645 | * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified | |
6646 | * TS bit (for lazy fpu) and bits which we consider mandatory enabled. | |
6647 | * The CR0_READ_SHADOW is what L2 should have expected to read given | |
6648 | * the specifications by L1; It's not enough to take | |
6649 | * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we | |
6650 | * have more bits than L1 expected. | |
6651 | */ | |
6652 | vmx_set_cr0(vcpu, vmcs12->guest_cr0); | |
6653 | vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12)); | |
6654 | ||
6655 | vmx_set_cr4(vcpu, vmcs12->guest_cr4); | |
6656 | vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12)); | |
6657 | ||
6658 | /* shadow page tables on either EPT or shadow page tables */ | |
6659 | kvm_set_cr3(vcpu, vmcs12->guest_cr3); | |
6660 | kvm_mmu_reset_context(vcpu); | |
6661 | ||
6662 | kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp); | |
6663 | kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip); | |
6664 | } | |
6665 | ||
cd232ad0 NHE |
6666 | /* |
6667 | * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1 | |
6668 | * for running an L2 nested guest. | |
6669 | */ | |
6670 | static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch) | |
6671 | { | |
6672 | struct vmcs12 *vmcs12; | |
6673 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
6674 | int cpu; | |
6675 | struct loaded_vmcs *vmcs02; | |
6676 | ||
6677 | if (!nested_vmx_check_permission(vcpu) || | |
6678 | !nested_vmx_check_vmcs12(vcpu)) | |
6679 | return 1; | |
6680 | ||
6681 | skip_emulated_instruction(vcpu); | |
6682 | vmcs12 = get_vmcs12(vcpu); | |
6683 | ||
7c177938 NHE |
6684 | /* |
6685 | * The nested entry process starts with enforcing various prerequisites | |
6686 | * on vmcs12 as required by the Intel SDM, and act appropriately when | |
6687 | * they fail: As the SDM explains, some conditions should cause the | |
6688 | * instruction to fail, while others will cause the instruction to seem | |
6689 | * to succeed, but return an EXIT_REASON_INVALID_STATE. | |
6690 | * To speed up the normal (success) code path, we should avoid checking | |
6691 | * for misconfigurations which will anyway be caught by the processor | |
6692 | * when using the merged vmcs02. | |
6693 | */ | |
6694 | if (vmcs12->launch_state == launch) { | |
6695 | nested_vmx_failValid(vcpu, | |
6696 | launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS | |
6697 | : VMXERR_VMRESUME_NONLAUNCHED_VMCS); | |
6698 | return 1; | |
6699 | } | |
6700 | ||
6701 | if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) && | |
6702 | !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) { | |
6703 | /*TODO: Also verify bits beyond physical address width are 0*/ | |
6704 | nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD); | |
6705 | return 1; | |
6706 | } | |
6707 | ||
6708 | if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) && | |
6709 | !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) { | |
6710 | /*TODO: Also verify bits beyond physical address width are 0*/ | |
6711 | nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD); | |
6712 | return 1; | |
6713 | } | |
6714 | ||
6715 | if (vmcs12->vm_entry_msr_load_count > 0 || | |
6716 | vmcs12->vm_exit_msr_load_count > 0 || | |
6717 | vmcs12->vm_exit_msr_store_count > 0) { | |
bd80158a JK |
6718 | pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n", |
6719 | __func__); | |
7c177938 NHE |
6720 | nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD); |
6721 | return 1; | |
6722 | } | |
6723 | ||
6724 | if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control, | |
6725 | nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) || | |
6726 | !vmx_control_verify(vmcs12->secondary_vm_exec_control, | |
6727 | nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) || | |
6728 | !vmx_control_verify(vmcs12->pin_based_vm_exec_control, | |
6729 | nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) || | |
6730 | !vmx_control_verify(vmcs12->vm_exit_controls, | |
6731 | nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) || | |
6732 | !vmx_control_verify(vmcs12->vm_entry_controls, | |
6733 | nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high)) | |
6734 | { | |
6735 | nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD); | |
6736 | return 1; | |
6737 | } | |
6738 | ||
6739 | if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) || | |
6740 | ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) { | |
6741 | nested_vmx_failValid(vcpu, | |
6742 | VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); | |
6743 | return 1; | |
6744 | } | |
6745 | ||
6746 | if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) || | |
6747 | ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) { | |
6748 | nested_vmx_entry_failure(vcpu, vmcs12, | |
6749 | EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT); | |
6750 | return 1; | |
6751 | } | |
6752 | if (vmcs12->vmcs_link_pointer != -1ull) { | |
6753 | nested_vmx_entry_failure(vcpu, vmcs12, | |
6754 | EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR); | |
6755 | return 1; | |
6756 | } | |
6757 | ||
6758 | /* | |
6759 | * We're finally done with prerequisite checking, and can start with | |
6760 | * the nested entry. | |
6761 | */ | |
6762 | ||
cd232ad0 NHE |
6763 | vmcs02 = nested_get_current_vmcs02(vmx); |
6764 | if (!vmcs02) | |
6765 | return -ENOMEM; | |
6766 | ||
6767 | enter_guest_mode(vcpu); | |
6768 | ||
6769 | vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET); | |
6770 | ||
6771 | cpu = get_cpu(); | |
6772 | vmx->loaded_vmcs = vmcs02; | |
6773 | vmx_vcpu_put(vcpu); | |
6774 | vmx_vcpu_load(vcpu, cpu); | |
6775 | vcpu->cpu = cpu; | |
6776 | put_cpu(); | |
6777 | ||
6778 | vmcs12->launch_state = 1; | |
6779 | ||
6780 | prepare_vmcs02(vcpu, vmcs12); | |
6781 | ||
6782 | /* | |
6783 | * Note no nested_vmx_succeed or nested_vmx_fail here. At this point | |
6784 | * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet | |
6785 | * returned as far as L1 is concerned. It will only return (and set | |
6786 | * the success flag) when L2 exits (see nested_vmx_vmexit()). | |
6787 | */ | |
6788 | return 1; | |
6789 | } | |
6790 | ||
4704d0be NHE |
6791 | /* |
6792 | * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date | |
6793 | * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK). | |
6794 | * This function returns the new value we should put in vmcs12.guest_cr0. | |
6795 | * It's not enough to just return the vmcs02 GUEST_CR0. Rather, | |
6796 | * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now | |
6797 | * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0 | |
6798 | * didn't trap the bit, because if L1 did, so would L0). | |
6799 | * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have | |
6800 | * been modified by L2, and L1 knows it. So just leave the old value of | |
6801 | * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0 | |
6802 | * isn't relevant, because if L0 traps this bit it can set it to anything. | |
6803 | * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have | |
6804 | * changed these bits, and therefore they need to be updated, but L0 | |
6805 | * didn't necessarily allow them to be changed in GUEST_CR0 - and rather | |
6806 | * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there. | |
6807 | */ | |
6808 | static inline unsigned long | |
6809 | vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12) | |
6810 | { | |
6811 | return | |
6812 | /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) | | |
6813 | /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) | | |
6814 | /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask | | |
6815 | vcpu->arch.cr0_guest_owned_bits)); | |
6816 | } | |
6817 | ||
6818 | static inline unsigned long | |
6819 | vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12) | |
6820 | { | |
6821 | return | |
6822 | /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) | | |
6823 | /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) | | |
6824 | /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask | | |
6825 | vcpu->arch.cr4_guest_owned_bits)); | |
6826 | } | |
6827 | ||
6828 | /* | |
6829 | * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits | |
6830 | * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12), | |
6831 | * and this function updates it to reflect the changes to the guest state while | |
6832 | * L2 was running (and perhaps made some exits which were handled directly by L0 | |
6833 | * without going back to L1), and to reflect the exit reason. | |
6834 | * Note that we do not have to copy here all VMCS fields, just those that | |
6835 | * could have changed by the L2 guest or the exit - i.e., the guest-state and | |
6836 | * exit-information fields only. Other fields are modified by L1 with VMWRITE, | |
6837 | * which already writes to vmcs12 directly. | |
6838 | */ | |
6839 | void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12) | |
6840 | { | |
6841 | /* update guest state fields: */ | |
6842 | vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12); | |
6843 | vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12); | |
6844 | ||
6845 | kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7); | |
6846 | vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP); | |
6847 | vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP); | |
6848 | vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS); | |
6849 | ||
6850 | vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR); | |
6851 | vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR); | |
6852 | vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR); | |
6853 | vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR); | |
6854 | vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR); | |
6855 | vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR); | |
6856 | vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR); | |
6857 | vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR); | |
6858 | vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT); | |
6859 | vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT); | |
6860 | vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT); | |
6861 | vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT); | |
6862 | vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT); | |
6863 | vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT); | |
6864 | vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT); | |
6865 | vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT); | |
6866 | vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT); | |
6867 | vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT); | |
6868 | vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES); | |
6869 | vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES); | |
6870 | vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES); | |
6871 | vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES); | |
6872 | vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES); | |
6873 | vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES); | |
6874 | vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES); | |
6875 | vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES); | |
6876 | vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE); | |
6877 | vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE); | |
6878 | vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE); | |
6879 | vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE); | |
6880 | vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE); | |
6881 | vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE); | |
6882 | vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE); | |
6883 | vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE); | |
6884 | vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE); | |
6885 | vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE); | |
6886 | ||
6887 | vmcs12->guest_activity_state = vmcs_read32(GUEST_ACTIVITY_STATE); | |
6888 | vmcs12->guest_interruptibility_info = | |
6889 | vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
6890 | vmcs12->guest_pending_dbg_exceptions = | |
6891 | vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS); | |
6892 | ||
6893 | /* TODO: These cannot have changed unless we have MSR bitmaps and | |
6894 | * the relevant bit asks not to trap the change */ | |
6895 | vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL); | |
6896 | if (vmcs12->vm_entry_controls & VM_EXIT_SAVE_IA32_PAT) | |
6897 | vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT); | |
6898 | vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS); | |
6899 | vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP); | |
6900 | vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP); | |
6901 | ||
6902 | /* update exit information fields: */ | |
6903 | ||
6904 | vmcs12->vm_exit_reason = vmcs_read32(VM_EXIT_REASON); | |
6905 | vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
6906 | ||
6907 | vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); | |
6908 | vmcs12->vm_exit_intr_error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE); | |
6909 | vmcs12->idt_vectoring_info_field = | |
6910 | vmcs_read32(IDT_VECTORING_INFO_FIELD); | |
6911 | vmcs12->idt_vectoring_error_code = | |
6912 | vmcs_read32(IDT_VECTORING_ERROR_CODE); | |
6913 | vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN); | |
6914 | vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); | |
6915 | ||
6916 | /* clear vm-entry fields which are to be cleared on exit */ | |
6917 | if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) | |
6918 | vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK; | |
6919 | } | |
6920 | ||
6921 | /* | |
6922 | * A part of what we need to when the nested L2 guest exits and we want to | |
6923 | * run its L1 parent, is to reset L1's guest state to the host state specified | |
6924 | * in vmcs12. | |
6925 | * This function is to be called not only on normal nested exit, but also on | |
6926 | * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry | |
6927 | * Failures During or After Loading Guest State"). | |
6928 | * This function should be called when the active VMCS is L1's (vmcs01). | |
6929 | */ | |
6930 | void load_vmcs12_host_state(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12) | |
6931 | { | |
6932 | if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) | |
6933 | vcpu->arch.efer = vmcs12->host_ia32_efer; | |
6934 | if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE) | |
6935 | vcpu->arch.efer |= (EFER_LMA | EFER_LME); | |
6936 | else | |
6937 | vcpu->arch.efer &= ~(EFER_LMA | EFER_LME); | |
6938 | vmx_set_efer(vcpu, vcpu->arch.efer); | |
6939 | ||
6940 | kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp); | |
6941 | kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip); | |
6942 | /* | |
6943 | * Note that calling vmx_set_cr0 is important, even if cr0 hasn't | |
6944 | * actually changed, because it depends on the current state of | |
6945 | * fpu_active (which may have changed). | |
6946 | * Note that vmx_set_cr0 refers to efer set above. | |
6947 | */ | |
6948 | kvm_set_cr0(vcpu, vmcs12->host_cr0); | |
6949 | /* | |
6950 | * If we did fpu_activate()/fpu_deactivate() during L2's run, we need | |
6951 | * to apply the same changes to L1's vmcs. We just set cr0 correctly, | |
6952 | * but we also need to update cr0_guest_host_mask and exception_bitmap. | |
6953 | */ | |
6954 | update_exception_bitmap(vcpu); | |
6955 | vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0); | |
6956 | vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits); | |
6957 | ||
6958 | /* | |
6959 | * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01 | |
6960 | * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask(); | |
6961 | */ | |
6962 | vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK); | |
6963 | kvm_set_cr4(vcpu, vmcs12->host_cr4); | |
6964 | ||
6965 | /* shadow page tables on either EPT or shadow page tables */ | |
6966 | kvm_set_cr3(vcpu, vmcs12->host_cr3); | |
6967 | kvm_mmu_reset_context(vcpu); | |
6968 | ||
6969 | if (enable_vpid) { | |
6970 | /* | |
6971 | * Trivially support vpid by letting L2s share their parent | |
6972 | * L1's vpid. TODO: move to a more elaborate solution, giving | |
6973 | * each L2 its own vpid and exposing the vpid feature to L1. | |
6974 | */ | |
6975 | vmx_flush_tlb(vcpu); | |
6976 | } | |
6977 | ||
6978 | ||
6979 | vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs); | |
6980 | vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp); | |
6981 | vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip); | |
6982 | vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base); | |
6983 | vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base); | |
6984 | vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base); | |
6985 | vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base); | |
6986 | vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base); | |
6987 | vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector); | |
6988 | vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector); | |
6989 | vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector); | |
6990 | vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector); | |
6991 | vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector); | |
6992 | vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector); | |
6993 | vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector); | |
6994 | ||
6995 | if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) | |
6996 | vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat); | |
6997 | if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL) | |
6998 | vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL, | |
6999 | vmcs12->host_ia32_perf_global_ctrl); | |
7000 | } | |
7001 | ||
7002 | /* | |
7003 | * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1 | |
7004 | * and modify vmcs12 to make it see what it would expect to see there if | |
7005 | * L2 was its real guest. Must only be called when in L2 (is_guest_mode()) | |
7006 | */ | |
7007 | static void nested_vmx_vmexit(struct kvm_vcpu *vcpu) | |
7008 | { | |
7009 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
7010 | int cpu; | |
7011 | struct vmcs12 *vmcs12 = get_vmcs12(vcpu); | |
7012 | ||
7013 | leave_guest_mode(vcpu); | |
7014 | prepare_vmcs12(vcpu, vmcs12); | |
7015 | ||
7016 | cpu = get_cpu(); | |
7017 | vmx->loaded_vmcs = &vmx->vmcs01; | |
7018 | vmx_vcpu_put(vcpu); | |
7019 | vmx_vcpu_load(vcpu, cpu); | |
7020 | vcpu->cpu = cpu; | |
7021 | put_cpu(); | |
7022 | ||
7023 | /* if no vmcs02 cache requested, remove the one we used */ | |
7024 | if (VMCS02_POOL_SIZE == 0) | |
7025 | nested_free_vmcs02(vmx, vmx->nested.current_vmptr); | |
7026 | ||
7027 | load_vmcs12_host_state(vcpu, vmcs12); | |
7028 | ||
27fc51b2 | 7029 | /* Update TSC_OFFSET if TSC was changed while L2 ran */ |
4704d0be NHE |
7030 | vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset); |
7031 | ||
7032 | /* This is needed for same reason as it was needed in prepare_vmcs02 */ | |
7033 | vmx->host_rsp = 0; | |
7034 | ||
7035 | /* Unpin physical memory we referred to in vmcs02 */ | |
7036 | if (vmx->nested.apic_access_page) { | |
7037 | nested_release_page(vmx->nested.apic_access_page); | |
7038 | vmx->nested.apic_access_page = 0; | |
7039 | } | |
7040 | ||
7041 | /* | |
7042 | * Exiting from L2 to L1, we're now back to L1 which thinks it just | |
7043 | * finished a VMLAUNCH or VMRESUME instruction, so we need to set the | |
7044 | * success or failure flag accordingly. | |
7045 | */ | |
7046 | if (unlikely(vmx->fail)) { | |
7047 | vmx->fail = 0; | |
7048 | nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR)); | |
7049 | } else | |
7050 | nested_vmx_succeed(vcpu); | |
7051 | } | |
7052 | ||
7c177938 NHE |
7053 | /* |
7054 | * L1's failure to enter L2 is a subset of a normal exit, as explained in | |
7055 | * 23.7 "VM-entry failures during or after loading guest state" (this also | |
7056 | * lists the acceptable exit-reason and exit-qualification parameters). | |
7057 | * It should only be called before L2 actually succeeded to run, and when | |
7058 | * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss). | |
7059 | */ | |
7060 | static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu, | |
7061 | struct vmcs12 *vmcs12, | |
7062 | u32 reason, unsigned long qualification) | |
7063 | { | |
7064 | load_vmcs12_host_state(vcpu, vmcs12); | |
7065 | vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY; | |
7066 | vmcs12->exit_qualification = qualification; | |
7067 | nested_vmx_succeed(vcpu); | |
7068 | } | |
7069 | ||
8a76d7f2 JR |
7070 | static int vmx_check_intercept(struct kvm_vcpu *vcpu, |
7071 | struct x86_instruction_info *info, | |
7072 | enum x86_intercept_stage stage) | |
7073 | { | |
7074 | return X86EMUL_CONTINUE; | |
7075 | } | |
7076 | ||
cbdd1bea | 7077 | static struct kvm_x86_ops vmx_x86_ops = { |
6aa8b732 AK |
7078 | .cpu_has_kvm_support = cpu_has_kvm_support, |
7079 | .disabled_by_bios = vmx_disabled_by_bios, | |
7080 | .hardware_setup = hardware_setup, | |
7081 | .hardware_unsetup = hardware_unsetup, | |
002c7f7c | 7082 | .check_processor_compatibility = vmx_check_processor_compat, |
6aa8b732 AK |
7083 | .hardware_enable = hardware_enable, |
7084 | .hardware_disable = hardware_disable, | |
04547156 | 7085 | .cpu_has_accelerated_tpr = report_flexpriority, |
6aa8b732 AK |
7086 | |
7087 | .vcpu_create = vmx_create_vcpu, | |
7088 | .vcpu_free = vmx_free_vcpu, | |
04d2cc77 | 7089 | .vcpu_reset = vmx_vcpu_reset, |
6aa8b732 | 7090 | |
04d2cc77 | 7091 | .prepare_guest_switch = vmx_save_host_state, |
6aa8b732 AK |
7092 | .vcpu_load = vmx_vcpu_load, |
7093 | .vcpu_put = vmx_vcpu_put, | |
7094 | ||
7095 | .set_guest_debug = set_guest_debug, | |
7096 | .get_msr = vmx_get_msr, | |
7097 | .set_msr = vmx_set_msr, | |
7098 | .get_segment_base = vmx_get_segment_base, | |
7099 | .get_segment = vmx_get_segment, | |
7100 | .set_segment = vmx_set_segment, | |
2e4d2653 | 7101 | .get_cpl = vmx_get_cpl, |
6aa8b732 | 7102 | .get_cs_db_l_bits = vmx_get_cs_db_l_bits, |
e8467fda | 7103 | .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits, |
aff48baa | 7104 | .decache_cr3 = vmx_decache_cr3, |
25c4c276 | 7105 | .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits, |
6aa8b732 | 7106 | .set_cr0 = vmx_set_cr0, |
6aa8b732 AK |
7107 | .set_cr3 = vmx_set_cr3, |
7108 | .set_cr4 = vmx_set_cr4, | |
6aa8b732 | 7109 | .set_efer = vmx_set_efer, |
6aa8b732 AK |
7110 | .get_idt = vmx_get_idt, |
7111 | .set_idt = vmx_set_idt, | |
7112 | .get_gdt = vmx_get_gdt, | |
7113 | .set_gdt = vmx_set_gdt, | |
020df079 | 7114 | .set_dr7 = vmx_set_dr7, |
5fdbf976 | 7115 | .cache_reg = vmx_cache_reg, |
6aa8b732 AK |
7116 | .get_rflags = vmx_get_rflags, |
7117 | .set_rflags = vmx_set_rflags, | |
ebcbab4c | 7118 | .fpu_activate = vmx_fpu_activate, |
02daab21 | 7119 | .fpu_deactivate = vmx_fpu_deactivate, |
6aa8b732 AK |
7120 | |
7121 | .tlb_flush = vmx_flush_tlb, | |
6aa8b732 | 7122 | |
6aa8b732 | 7123 | .run = vmx_vcpu_run, |
6062d012 | 7124 | .handle_exit = vmx_handle_exit, |
6aa8b732 | 7125 | .skip_emulated_instruction = skip_emulated_instruction, |
2809f5d2 GC |
7126 | .set_interrupt_shadow = vmx_set_interrupt_shadow, |
7127 | .get_interrupt_shadow = vmx_get_interrupt_shadow, | |
102d8325 | 7128 | .patch_hypercall = vmx_patch_hypercall, |
2a8067f1 | 7129 | .set_irq = vmx_inject_irq, |
95ba8273 | 7130 | .set_nmi = vmx_inject_nmi, |
298101da | 7131 | .queue_exception = vmx_queue_exception, |
b463a6f7 | 7132 | .cancel_injection = vmx_cancel_injection, |
78646121 | 7133 | .interrupt_allowed = vmx_interrupt_allowed, |
95ba8273 | 7134 | .nmi_allowed = vmx_nmi_allowed, |
3cfc3092 JK |
7135 | .get_nmi_mask = vmx_get_nmi_mask, |
7136 | .set_nmi_mask = vmx_set_nmi_mask, | |
95ba8273 GN |
7137 | .enable_nmi_window = enable_nmi_window, |
7138 | .enable_irq_window = enable_irq_window, | |
7139 | .update_cr8_intercept = update_cr8_intercept, | |
95ba8273 | 7140 | |
cbc94022 | 7141 | .set_tss_addr = vmx_set_tss_addr, |
67253af5 | 7142 | .get_tdp_level = get_ept_level, |
4b12f0de | 7143 | .get_mt_mask = vmx_get_mt_mask, |
229456fc | 7144 | |
586f9607 | 7145 | .get_exit_info = vmx_get_exit_info, |
586f9607 | 7146 | |
17cc3935 | 7147 | .get_lpage_level = vmx_get_lpage_level, |
0e851880 SY |
7148 | |
7149 | .cpuid_update = vmx_cpuid_update, | |
4e47c7a6 SY |
7150 | |
7151 | .rdtscp_supported = vmx_rdtscp_supported, | |
d4330ef2 JR |
7152 | |
7153 | .set_supported_cpuid = vmx_set_supported_cpuid, | |
f5f48ee1 SY |
7154 | |
7155 | .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit, | |
99e3e30a | 7156 | |
4051b188 | 7157 | .set_tsc_khz = vmx_set_tsc_khz, |
99e3e30a | 7158 | .write_tsc_offset = vmx_write_tsc_offset, |
e48672fa | 7159 | .adjust_tsc_offset = vmx_adjust_tsc_offset, |
857e4099 | 7160 | .compute_tsc_offset = vmx_compute_tsc_offset, |
d5c1785d | 7161 | .read_l1_tsc = vmx_read_l1_tsc, |
1c97f0a0 JR |
7162 | |
7163 | .set_tdp_cr3 = vmx_set_cr3, | |
8a76d7f2 JR |
7164 | |
7165 | .check_intercept = vmx_check_intercept, | |
6aa8b732 AK |
7166 | }; |
7167 | ||
7168 | static int __init vmx_init(void) | |
7169 | { | |
26bb0981 AK |
7170 | int r, i; |
7171 | ||
7172 | rdmsrl_safe(MSR_EFER, &host_efer); | |
7173 | ||
7174 | for (i = 0; i < NR_VMX_MSR; ++i) | |
7175 | kvm_define_shared_msr(i, vmx_msr_index[i]); | |
fdef3ad1 | 7176 | |
3e7c73e9 | 7177 | vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL); |
fdef3ad1 HQ |
7178 | if (!vmx_io_bitmap_a) |
7179 | return -ENOMEM; | |
7180 | ||
3e7c73e9 | 7181 | vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL); |
fdef3ad1 HQ |
7182 | if (!vmx_io_bitmap_b) { |
7183 | r = -ENOMEM; | |
7184 | goto out; | |
7185 | } | |
7186 | ||
5897297b AK |
7187 | vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL); |
7188 | if (!vmx_msr_bitmap_legacy) { | |
25c5f225 SY |
7189 | r = -ENOMEM; |
7190 | goto out1; | |
7191 | } | |
7192 | ||
5897297b AK |
7193 | vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL); |
7194 | if (!vmx_msr_bitmap_longmode) { | |
7195 | r = -ENOMEM; | |
7196 | goto out2; | |
7197 | } | |
7198 | ||
fdef3ad1 HQ |
7199 | /* |
7200 | * Allow direct access to the PC debug port (it is often used for I/O | |
7201 | * delays, but the vmexits simply slow things down). | |
7202 | */ | |
3e7c73e9 AK |
7203 | memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE); |
7204 | clear_bit(0x80, vmx_io_bitmap_a); | |
fdef3ad1 | 7205 | |
3e7c73e9 | 7206 | memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE); |
fdef3ad1 | 7207 | |
5897297b AK |
7208 | memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE); |
7209 | memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE); | |
25c5f225 | 7210 | |
2384d2b3 SY |
7211 | set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */ |
7212 | ||
0ee75bea AK |
7213 | r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), |
7214 | __alignof__(struct vcpu_vmx), THIS_MODULE); | |
fdef3ad1 | 7215 | if (r) |
5897297b | 7216 | goto out3; |
25c5f225 | 7217 | |
5897297b AK |
7218 | vmx_disable_intercept_for_msr(MSR_FS_BASE, false); |
7219 | vmx_disable_intercept_for_msr(MSR_GS_BASE, false); | |
7220 | vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true); | |
7221 | vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false); | |
7222 | vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false); | |
7223 | vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false); | |
fdef3ad1 | 7224 | |
089d034e | 7225 | if (enable_ept) { |
534e38b4 | 7226 | kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull, |
4b12f0de | 7227 | VMX_EPT_EXECUTABLE_MASK); |
ce88decf | 7228 | ept_set_mmio_spte_mask(); |
5fdbcb9d SY |
7229 | kvm_enable_tdp(); |
7230 | } else | |
7231 | kvm_disable_tdp(); | |
1439442c | 7232 | |
fdef3ad1 HQ |
7233 | return 0; |
7234 | ||
5897297b AK |
7235 | out3: |
7236 | free_page((unsigned long)vmx_msr_bitmap_longmode); | |
25c5f225 | 7237 | out2: |
5897297b | 7238 | free_page((unsigned long)vmx_msr_bitmap_legacy); |
fdef3ad1 | 7239 | out1: |
3e7c73e9 | 7240 | free_page((unsigned long)vmx_io_bitmap_b); |
fdef3ad1 | 7241 | out: |
3e7c73e9 | 7242 | free_page((unsigned long)vmx_io_bitmap_a); |
fdef3ad1 | 7243 | return r; |
6aa8b732 AK |
7244 | } |
7245 | ||
7246 | static void __exit vmx_exit(void) | |
7247 | { | |
5897297b AK |
7248 | free_page((unsigned long)vmx_msr_bitmap_legacy); |
7249 | free_page((unsigned long)vmx_msr_bitmap_longmode); | |
3e7c73e9 AK |
7250 | free_page((unsigned long)vmx_io_bitmap_b); |
7251 | free_page((unsigned long)vmx_io_bitmap_a); | |
fdef3ad1 | 7252 | |
cb498ea2 | 7253 | kvm_exit(); |
6aa8b732 AK |
7254 | } |
7255 | ||
7256 | module_init(vmx_init) | |
7257 | module_exit(vmx_exit) |