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KVM: nVMX: Enable nested virtualize x2apic mode
[deliverable/linux.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
229456fc 31#include <linux/ftrace_event.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
f4124500 34#include <linux/hrtimer.h>
5fdbf976 35#include "kvm_cache_regs.h"
35920a35 36#include "x86.h"
e495606d 37
6aa8b732 38#include <asm/io.h>
3b3be0d1 39#include <asm/desc.h>
13673a90 40#include <asm/vmx.h>
6210e37b 41#include <asm/virtext.h>
a0861c02 42#include <asm/mce.h>
2acf923e
DC		 43#include <asm/i387.h>
44#include <asm/xcr.h>
d7cd9796 45#include <asm/perf_event.h>
81908bf4 46#include <asm/debugreg.h>
8f536b76 47#include <asm/kexec.h>
6aa8b732 48
229456fc
MT		 49#include "trace.h"
50
4ecac3fd 51#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 52#define __ex_clear(x, reg) \
53 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 54
6aa8b732
AK		 55MODULE_AUTHOR("Qumranet");
56MODULE_LICENSE("GPL");
57
e9bda3b3
JT		 58static const struct x86_cpu_id vmx_cpu_id[] = {
59 X86_FEATURE_MATCH(X86_FEATURE_VMX),
60 {}
61};
62MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
63
476bc001 64static bool __read_mostly enable_vpid = 1;
736caefe 65module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 66
476bc001 67static bool __read_mostly flexpriority_enabled = 1;
736caefe 68module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 69
476bc001 70static bool __read_mostly enable_ept = 1;
736caefe 71module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 72
476bc001 73static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 74module_param_named(unrestricted_guest,
75 enable_unrestricted_guest, bool, S_IRUGO);
76
83c3a331
XH		 77static bool __read_mostly enable_ept_ad_bits = 1;
78module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
79
a27685c3 80static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 81module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 82
476bc001 83static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 84module_param(vmm_exclusive, bool, S_IRUGO);
85
476bc001 86static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 87module_param(fasteoi, bool, S_IRUGO);
88
5a71785d 89static bool __read_mostly enable_apicv = 1;
01e439be 90module_param(enable_apicv, bool, S_IRUGO);
83d4c286 91
abc4fc58
AG		 92static bool __read_mostly enable_shadow_vmcs = 1;
93module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
801d3424
NHE		 94/*
95 * If nested=1, nested virtualization is supported, i.e., guests may use
96 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
97 * use VMX instructions.
98 */
476bc001 99static bool __read_mostly nested = 0;
801d3424
NHE		 100module_param(nested, bool, S_IRUGO);
101
20300099
WL		 102static u64 __read_mostly host_xss;
103
843e4330
KH		 104static bool __read_mostly enable_pml = 1;
105module_param_named(pml, enable_pml, bool, S_IRUGO);
106
5037878e
GN		 107#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
108#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 109#define KVM_VM_CR0_ALWAYS_ON \
110 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 111#define KVM_CR4_GUEST_OWNED_BITS \
112 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
52ce3c21 113 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
4c38609a 114
cdc0e244
AK		 115#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
116#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
117
78ac8b47
AK		 118#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
119
f4124500
JK		 120#define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
121
4b8d54f9
ZE		 122/*
123 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
124 * ple_gap: upper bound on the amount of time between two successive
125 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 126 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 127 * ple_window: upper bound on the amount of time a guest is allowed to execute
128 * in a PAUSE loop. Tests indicate that most spinlocks are held for
129 * less than 2^12 cycles
130 * Time is measured based on a counter that runs at the same rate as the TSC,
131 * refer SDM volume 3b section 21.6.13 & 22.1.3.
132 */
b4a2d31d
RK		 133#define KVM_VMX_DEFAULT_PLE_GAP 128
134#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
135#define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
136#define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
137#define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
138 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
139
4b8d54f9
ZE		 140static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
141module_param(ple_gap, int, S_IRUGO);
142
143static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
144module_param(ple_window, int, S_IRUGO);
145
b4a2d31d
RK		 146/* Default doubles per-vcpu window every exit. */
147static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
148module_param(ple_window_grow, int, S_IRUGO);
149
150/* Default resets per-vcpu window every exit to ple_window. */
151static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
152module_param(ple_window_shrink, int, S_IRUGO);
153
154/* Default is to compute the maximum so we can never overflow. */
155static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
156static int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
157module_param(ple_window_max, int, S_IRUGO);
158
83287ea4
AK		 159extern const ulong vmx_return;
160
8bf00a52 161#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 162#define VMCS02_POOL_SIZE 1
61d2ef2c 163
a2fa3e9f
GH		 164struct vmcs {
165 u32 revision_id;
166 u32 abort;
167 char data[0];
168};
169
d462b819
NHE		 170/*
171 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
172 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
173 * loaded on this CPU (so we can clear them if the CPU goes down).
174 */
175struct loaded_vmcs {
176 struct vmcs *vmcs;
177 int cpu;
178 int launched;
179 struct list_head loaded_vmcss_on_cpu_link;
180};
181
26bb0981
AK		 182struct shared_msr_entry {
183 unsigned index;
184 u64 data;
d5696725 185 u64 mask;
26bb0981
AK		 186};
187
a9d30f33
NHE		 188/*
189 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
190 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
191 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
192 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
193 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
194 * More than one of these structures may exist, if L1 runs multiple L2 guests.
195 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
196 * underlying hardware which will be used to run L2.
197 * This structure is packed to ensure that its layout is identical across
198 * machines (necessary for live migration).
199 * If there are changes in this struct, VMCS12_REVISION must be changed.
200 */
22bd0358 201typedef u64 natural_width;
a9d30f33
NHE		 202struct __packed vmcs12 {
203 /* According to the Intel spec, a VMCS region must start with the
204 * following two fields. Then follow implementation-specific data.
205 */
206 u32 revision_id;
207 u32 abort;
22bd0358 208
27d6c865
NHE		 209 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
210 u32 padding[7]; /* room for future expansion */
211
22bd0358
NHE		 212 u64 io_bitmap_a;
213 u64 io_bitmap_b;
214 u64 msr_bitmap;
215 u64 vm_exit_msr_store_addr;
216 u64 vm_exit_msr_load_addr;
217 u64 vm_entry_msr_load_addr;
218 u64 tsc_offset;
219 u64 virtual_apic_page_addr;
220 u64 apic_access_addr;
221 u64 ept_pointer;
81dc01f7 222 u64 xss_exit_bitmap;
22bd0358
NHE		 223 u64 guest_physical_address;
224 u64 vmcs_link_pointer;
225 u64 guest_ia32_debugctl;
226 u64 guest_ia32_pat;
227 u64 guest_ia32_efer;
228 u64 guest_ia32_perf_global_ctrl;
229 u64 guest_pdptr0;
230 u64 guest_pdptr1;
231 u64 guest_pdptr2;
232 u64 guest_pdptr3;
36be0b9d 233 u64 guest_bndcfgs;
22bd0358
NHE		 234 u64 host_ia32_pat;
235 u64 host_ia32_efer;
236 u64 host_ia32_perf_global_ctrl;
237 u64 padding64[8]; /* room for future expansion */
238 /*
239 * To allow migration of L1 (complete with its L2 guests) between
240 * machines of different natural widths (32 or 64 bit), we cannot have
241 * unsigned long fields with no explict size. We use u64 (aliased
242 * natural_width) instead. Luckily, x86 is little-endian.
243 */
244 natural_width cr0_guest_host_mask;
245 natural_width cr4_guest_host_mask;
246 natural_width cr0_read_shadow;
247 natural_width cr4_read_shadow;
248 natural_width cr3_target_value0;
249 natural_width cr3_target_value1;
250 natural_width cr3_target_value2;
251 natural_width cr3_target_value3;
252 natural_width exit_qualification;
253 natural_width guest_linear_address;
254 natural_width guest_cr0;
255 natural_width guest_cr3;
256 natural_width guest_cr4;
257 natural_width guest_es_base;
258 natural_width guest_cs_base;
259 natural_width guest_ss_base;
260 natural_width guest_ds_base;
261 natural_width guest_fs_base;
262 natural_width guest_gs_base;
263 natural_width guest_ldtr_base;
264 natural_width guest_tr_base;
265 natural_width guest_gdtr_base;
266 natural_width guest_idtr_base;
267 natural_width guest_dr7;
268 natural_width guest_rsp;
269 natural_width guest_rip;
270 natural_width guest_rflags;
271 natural_width guest_pending_dbg_exceptions;
272 natural_width guest_sysenter_esp;
273 natural_width guest_sysenter_eip;
274 natural_width host_cr0;
275 natural_width host_cr3;
276 natural_width host_cr4;
277 natural_width host_fs_base;
278 natural_width host_gs_base;
279 natural_width host_tr_base;
280 natural_width host_gdtr_base;
281 natural_width host_idtr_base;
282 natural_width host_ia32_sysenter_esp;
283 natural_width host_ia32_sysenter_eip;
284 natural_width host_rsp;
285 natural_width host_rip;
286 natural_width paddingl[8]; /* room for future expansion */
287 u32 pin_based_vm_exec_control;
288 u32 cpu_based_vm_exec_control;
289 u32 exception_bitmap;
290 u32 page_fault_error_code_mask;
291 u32 page_fault_error_code_match;
292 u32 cr3_target_count;
293 u32 vm_exit_controls;
294 u32 vm_exit_msr_store_count;
295 u32 vm_exit_msr_load_count;
296 u32 vm_entry_controls;
297 u32 vm_entry_msr_load_count;
298 u32 vm_entry_intr_info_field;
299 u32 vm_entry_exception_error_code;
300 u32 vm_entry_instruction_len;
301 u32 tpr_threshold;
302 u32 secondary_vm_exec_control;
303 u32 vm_instruction_error;
304 u32 vm_exit_reason;
305 u32 vm_exit_intr_info;
306 u32 vm_exit_intr_error_code;
307 u32 idt_vectoring_info_field;
308 u32 idt_vectoring_error_code;
309 u32 vm_exit_instruction_len;
310 u32 vmx_instruction_info;
311 u32 guest_es_limit;
312 u32 guest_cs_limit;
313 u32 guest_ss_limit;
314 u32 guest_ds_limit;
315 u32 guest_fs_limit;
316 u32 guest_gs_limit;
317 u32 guest_ldtr_limit;
318 u32 guest_tr_limit;
319 u32 guest_gdtr_limit;
320 u32 guest_idtr_limit;
321 u32 guest_es_ar_bytes;
322 u32 guest_cs_ar_bytes;
323 u32 guest_ss_ar_bytes;
324 u32 guest_ds_ar_bytes;
325 u32 guest_fs_ar_bytes;
326 u32 guest_gs_ar_bytes;
327 u32 guest_ldtr_ar_bytes;
328 u32 guest_tr_ar_bytes;
329 u32 guest_interruptibility_info;
330 u32 guest_activity_state;
331 u32 guest_sysenter_cs;
332 u32 host_ia32_sysenter_cs;
0238ea91
JK		 333 u32 vmx_preemption_timer_value;
334 u32 padding32[7]; /* room for future expansion */
22bd0358
NHE		 335 u16 virtual_processor_id;
336 u16 guest_es_selector;
337 u16 guest_cs_selector;
338 u16 guest_ss_selector;
339 u16 guest_ds_selector;
340 u16 guest_fs_selector;
341 u16 guest_gs_selector;
342 u16 guest_ldtr_selector;
343 u16 guest_tr_selector;
344 u16 host_es_selector;
345 u16 host_cs_selector;
346 u16 host_ss_selector;
347 u16 host_ds_selector;
348 u16 host_fs_selector;
349 u16 host_gs_selector;
350 u16 host_tr_selector;
a9d30f33
NHE		 351};
352
353/*
354 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
355 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
356 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
357 */
358#define VMCS12_REVISION 0x11e57ed0
359
360/*
361 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
362 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
363 * current implementation, 4K are reserved to avoid future complications.
364 */
365#define VMCS12_SIZE 0x1000
366
ff2f6fe9
NHE		 367/* Used to remember the last vmcs02 used for some recently used vmcs12s */
368struct vmcs02_list {
369 struct list_head list;
370 gpa_t vmptr;
371 struct loaded_vmcs vmcs02;
372};
373
ec378aee
NHE		 374/*
375 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
376 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
377 */
378struct nested_vmx {
379 /* Has the level1 guest done vmxon? */
380 bool vmxon;
3573e22c 381 gpa_t vmxon_ptr;
a9d30f33
NHE		 382
383 /* The guest-physical address of the current VMCS L1 keeps for L2 */
384 gpa_t current_vmptr;
385 /* The host-usable pointer to the above */
386 struct page *current_vmcs12_page;
387 struct vmcs12 *current_vmcs12;
8de48833 388 struct vmcs *current_shadow_vmcs;
012f83cb
AG		 389 /*
390 * Indicates if the shadow vmcs must be updated with the
391 * data hold by vmcs12
392 */
393 bool sync_shadow_vmcs;
ff2f6fe9
NHE		 394
395 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
396 struct list_head vmcs02_pool;
397 int vmcs02_num;
fe3ef05c 398 u64 vmcs01_tsc_offset;
644d711a
NHE		 399 /* L2 must run next, and mustn't decide to exit to L1. */
400 bool nested_run_pending;
fe3ef05c
NHE		 401 /*
402 * Guest pages referred to in vmcs02 with host-physical pointers, so
403 * we must keep them pinned while L2 runs.
404 */
405 struct page *apic_access_page;
a7c0b07d 406 struct page *virtual_apic_page;
b3897a49 407 u64 msr_ia32_feature_control;
f4124500
JK		 408
409 struct hrtimer preemption_timer;
410 bool preemption_timer_expired;
2996fca0
JK		 411
412 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
413 u64 vmcs01_debugctl;
ec378aee
NHE		 414};
415
01e439be
YZ		 416#define POSTED_INTR_ON 0
417/* Posted-Interrupt Descriptor */
418struct pi_desc {
419 u32 pir[8]; /* Posted interrupt requested */
420 u32 control; /* bit 0 of control is outstanding notification bit */
421 u32 rsvd[7];
422} __aligned(64);
423
a20ed54d
YZ		 424static bool pi_test_and_set_on(struct pi_desc *pi_desc)
425{
426 return test_and_set_bit(POSTED_INTR_ON,
427 (unsigned long *)&pi_desc->control);
428}
429
430static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
431{
432 return test_and_clear_bit(POSTED_INTR_ON,
433 (unsigned long *)&pi_desc->control);
434}
435
436static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
437{
438 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
439}
440
a2fa3e9f 441struct vcpu_vmx {
fb3f0f51 442 struct kvm_vcpu vcpu;
313dbd49 443 unsigned long host_rsp;
29bd8a78 444 u8 fail;
9d58b931 445 bool nmi_known_unmasked;
51aa01d1 446 u32 exit_intr_info;
1155f76a 447 u32 idt_vectoring_info;
6de12732 448 ulong rflags;
26bb0981 449 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 450 int nmsrs;
451 int save_nmsrs;
a547c6db 452 unsigned long host_idt_base;
a2fa3e9f 453#ifdef CONFIG_X86_64
44ea2b17
AK		 454 u64 msr_host_kernel_gs_base;
455 u64 msr_guest_kernel_gs_base;
a2fa3e9f 456#endif
2961e876
GN		 457 u32 vm_entry_controls_shadow;
458 u32 vm_exit_controls_shadow;
d462b819
NHE		 459 /*
460 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
461 * non-nested (L1) guest, it always points to vmcs01. For a nested
462 * guest (L2), it points to a different VMCS.
463 */
464 struct loaded_vmcs vmcs01;
465 struct loaded_vmcs *loaded_vmcs;
466 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 467 struct msr_autoload {
468 unsigned nr;
469 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
470 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
471 } msr_autoload;
a2fa3e9f
GH		 472 struct {
473 int loaded;
474 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 475#ifdef CONFIG_X86_64
476 u16 ds_sel, es_sel;
477#endif
152d3f2f
LV		 478 int gs_ldt_reload_needed;
479 int fs_reload_needed;
da8999d3 480 u64 msr_host_bndcfgs;
d974baa3 481 unsigned long vmcs_host_cr4; /* May not match real cr4 */
d77c26fc 482 } host_state;
9c8cba37 483 struct {
7ffd92c5 484 int vm86_active;
78ac8b47 485 ulong save_rflags;
f5f7b2fe
AK		 486 struct kvm_segment segs[8];
487 } rmode;
488 struct {
489 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 490 struct kvm_save_segment {
491 u16 selector;
492 unsigned long base;
493 u32 limit;
494 u32 ar;
f5f7b2fe 495 } seg[8];
2fb92db1 496 } segment_cache;
2384d2b3 497 int vpid;
04fa4d32 498 bool emulation_required;
3b86cd99
JK		 499
500 /* Support for vnmi-less CPUs */
501 int soft_vnmi_blocked;
502 ktime_t entry_time;
503 s64 vnmi_blocked_time;
a0861c02 504 u32 exit_reason;
4e47c7a6
SY		 505
506 bool rdtscp_enabled;
ec378aee 507
01e439be
YZ		 508 /* Posted interrupt descriptor */
509 struct pi_desc pi_desc;
510
ec378aee
NHE		 511 /* Support for a guest hypervisor (nested VMX) */
512 struct nested_vmx nested;
a7653ecd
RK		 513
514 /* Dynamic PLE window. */
515 int ple_window;
516 bool ple_window_dirty;
843e4330
KH		 517
518 /* Support for PML */
519#define PML_ENTITY_NUM 512
520 struct page *pml_pg;
a2fa3e9f
GH		 521};
522
2fb92db1
AK		 523enum segment_cache_field {
524 SEG_FIELD_SEL = 0,
525 SEG_FIELD_BASE = 1,
526 SEG_FIELD_LIMIT = 2,
527 SEG_FIELD_AR = 3,
528
529 SEG_FIELD_NR = 4
530};
531
a2fa3e9f
GH		 532static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
533{
fb3f0f51 534 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 535}
536
22bd0358
NHE		 537#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
538#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
539#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
540 [number##_HIGH] = VMCS12_OFFSET(name)+4
541
4607c2d7 542
fe2b201b 543static unsigned long shadow_read_only_fields[] = {
4607c2d7
AG		 544 /*
545 * We do NOT shadow fields that are modified when L0
546 * traps and emulates any vmx instruction (e.g. VMPTRLD,
547 * VMXON...) executed by L1.
548 * For example, VM_INSTRUCTION_ERROR is read
549 * by L1 if a vmx instruction fails (part of the error path).
550 * Note the code assumes this logic. If for some reason
551 * we start shadowing these fields then we need to
552 * force a shadow sync when L0 emulates vmx instructions
553 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
554 * by nested_vmx_failValid)
555 */
556 VM_EXIT_REASON,
557 VM_EXIT_INTR_INFO,
558 VM_EXIT_INSTRUCTION_LEN,
559 IDT_VECTORING_INFO_FIELD,
560 IDT_VECTORING_ERROR_CODE,
561 VM_EXIT_INTR_ERROR_CODE,
562 EXIT_QUALIFICATION,
563 GUEST_LINEAR_ADDRESS,
564 GUEST_PHYSICAL_ADDRESS
565};
fe2b201b 566static int max_shadow_read_only_fields =
4607c2d7
AG		 567 ARRAY_SIZE(shadow_read_only_fields);
568
fe2b201b 569static unsigned long shadow_read_write_fields[] = {
a7c0b07d 570 TPR_THRESHOLD,
4607c2d7
AG		 571 GUEST_RIP,
572 GUEST_RSP,
573 GUEST_CR0,
574 GUEST_CR3,
575 GUEST_CR4,
576 GUEST_INTERRUPTIBILITY_INFO,
577 GUEST_RFLAGS,
578 GUEST_CS_SELECTOR,
579 GUEST_CS_AR_BYTES,
580 GUEST_CS_LIMIT,
581 GUEST_CS_BASE,
582 GUEST_ES_BASE,
36be0b9d 583 GUEST_BNDCFGS,
4607c2d7
AG		 584 CR0_GUEST_HOST_MASK,
585 CR0_READ_SHADOW,
586 CR4_READ_SHADOW,
587 TSC_OFFSET,
588 EXCEPTION_BITMAP,
589 CPU_BASED_VM_EXEC_CONTROL,
590 VM_ENTRY_EXCEPTION_ERROR_CODE,
591 VM_ENTRY_INTR_INFO_FIELD,
592 VM_ENTRY_INSTRUCTION_LEN,
593 VM_ENTRY_EXCEPTION_ERROR_CODE,
594 HOST_FS_BASE,
595 HOST_GS_BASE,
596 HOST_FS_SELECTOR,
597 HOST_GS_SELECTOR
598};
fe2b201b 599static int max_shadow_read_write_fields =
4607c2d7
AG		 600 ARRAY_SIZE(shadow_read_write_fields);
601
772e0318 602static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358
NHE		 603 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
604 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
605 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
606 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
607 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
608 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
609 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
610 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
611 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
612 FIELD(HOST_ES_SELECTOR, host_es_selector),
613 FIELD(HOST_CS_SELECTOR, host_cs_selector),
614 FIELD(HOST_SS_SELECTOR, host_ss_selector),
615 FIELD(HOST_DS_SELECTOR, host_ds_selector),
616 FIELD(HOST_FS_SELECTOR, host_fs_selector),
617 FIELD(HOST_GS_SELECTOR, host_gs_selector),
618 FIELD(HOST_TR_SELECTOR, host_tr_selector),
619 FIELD64(IO_BITMAP_A, io_bitmap_a),
620 FIELD64(IO_BITMAP_B, io_bitmap_b),
621 FIELD64(MSR_BITMAP, msr_bitmap),
622 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
623 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
624 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
625 FIELD64(TSC_OFFSET, tsc_offset),
626 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
627 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
628 FIELD64(EPT_POINTER, ept_pointer),
81dc01f7 629 FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
22bd0358
NHE		 630 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
631 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
632 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
633 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
634 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
635 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
636 FIELD64(GUEST_PDPTR0, guest_pdptr0),
637 FIELD64(GUEST_PDPTR1, guest_pdptr1),
638 FIELD64(GUEST_PDPTR2, guest_pdptr2),
639 FIELD64(GUEST_PDPTR3, guest_pdptr3),
36be0b9d 640 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
22bd0358
NHE		 641 FIELD64(HOST_IA32_PAT, host_ia32_pat),
642 FIELD64(HOST_IA32_EFER, host_ia32_efer),
643 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
644 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
645 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
646 FIELD(EXCEPTION_BITMAP, exception_bitmap),
647 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
648 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
649 FIELD(CR3_TARGET_COUNT, cr3_target_count),
650 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
651 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
652 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
653 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
654 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
655 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
656 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
657 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
658 FIELD(TPR_THRESHOLD, tpr_threshold),
659 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
660 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
661 FIELD(VM_EXIT_REASON, vm_exit_reason),
662 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
663 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
664 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
665 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
666 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
667 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
668 FIELD(GUEST_ES_LIMIT, guest_es_limit),
669 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
670 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
671 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
672 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
673 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
674 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
675 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
676 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
677 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
678 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
679 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
680 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
681 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
682 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
683 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
684 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
685 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
686 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
687 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
688 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
689 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
0238ea91 690 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
22bd0358
NHE		 691 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
692 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
693 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
694 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
695 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
696 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
697 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
698 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
699 FIELD(EXIT_QUALIFICATION, exit_qualification),
700 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
701 FIELD(GUEST_CR0, guest_cr0),
702 FIELD(GUEST_CR3, guest_cr3),
703 FIELD(GUEST_CR4, guest_cr4),
704 FIELD(GUEST_ES_BASE, guest_es_base),
705 FIELD(GUEST_CS_BASE, guest_cs_base),
706 FIELD(GUEST_SS_BASE, guest_ss_base),
707 FIELD(GUEST_DS_BASE, guest_ds_base),
708 FIELD(GUEST_FS_BASE, guest_fs_base),
709 FIELD(GUEST_GS_BASE, guest_gs_base),
710 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
711 FIELD(GUEST_TR_BASE, guest_tr_base),
712 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
713 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
714 FIELD(GUEST_DR7, guest_dr7),
715 FIELD(GUEST_RSP, guest_rsp),
716 FIELD(GUEST_RIP, guest_rip),
717 FIELD(GUEST_RFLAGS, guest_rflags),
718 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
719 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
720 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
721 FIELD(HOST_CR0, host_cr0),
722 FIELD(HOST_CR3, host_cr3),
723 FIELD(HOST_CR4, host_cr4),
724 FIELD(HOST_FS_BASE, host_fs_base),
725 FIELD(HOST_GS_BASE, host_gs_base),
726 FIELD(HOST_TR_BASE, host_tr_base),
727 FIELD(HOST_GDTR_BASE, host_gdtr_base),
728 FIELD(HOST_IDTR_BASE, host_idtr_base),
729 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
730 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
731 FIELD(HOST_RSP, host_rsp),
732 FIELD(HOST_RIP, host_rip),
733};
22bd0358
NHE		 734
735static inline short vmcs_field_to_offset(unsigned long field)
736{
a2ae9df7
PB		 737 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
738
739 if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
740 vmcs_field_to_offset_table[field] == 0)
741 return -ENOENT;
742
22bd0358
NHE		 743 return vmcs_field_to_offset_table[field];
744}
745
a9d30f33
NHE		 746static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
747{
748 return to_vmx(vcpu)->nested.current_vmcs12;
749}
750
751static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
752{
753 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
32cad84f 754 if (is_error_page(page))
a9d30f33 755 return NULL;
32cad84f 756
a9d30f33
NHE		 757 return page;
758}
759
760static void nested_release_page(struct page *page)
761{
762 kvm_release_page_dirty(page);
763}
764
765static void nested_release_page_clean(struct page *page)
766{
767 kvm_release_page_clean(page);
768}
769
bfd0a56b 770static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
4e1096d2 771static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 772static void kvm_cpu_vmxon(u64 addr);
773static void kvm_cpu_vmxoff(void);
93c4adc7 774static bool vmx_mpx_supported(void);
f53cd63c 775static bool vmx_xsaves_supported(void);
776e58ea 776static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 777static void vmx_set_segment(struct kvm_vcpu *vcpu,
778 struct kvm_segment *var, int seg);
779static void vmx_get_segment(struct kvm_vcpu *vcpu,
780 struct kvm_segment *var, int seg);
d99e4152
GN		 781static bool guest_state_valid(struct kvm_vcpu *vcpu);
782static u32 vmx_segment_access_rights(struct kvm_segment *var);
a20ed54d 783static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
c3114420 784static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
16f5b903 785static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
a255d479 786static int alloc_identity_pagetable(struct kvm *kvm);
75880a01 787
6aa8b732
AK		 788static DEFINE_PER_CPU(struct vmcs *, vmxarea);
789static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 790/*
791 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
792 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
793 */
794static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 795static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 796
3e7c73e9
AK		 797static unsigned long *vmx_io_bitmap_a;
798static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 799static unsigned long *vmx_msr_bitmap_legacy;
800static unsigned long *vmx_msr_bitmap_longmode;
8d14695f
YZ		 801static unsigned long *vmx_msr_bitmap_legacy_x2apic;
802static unsigned long *vmx_msr_bitmap_longmode_x2apic;
3af18d9c 803static unsigned long *vmx_msr_bitmap_nested;
4607c2d7
AG		 804static unsigned long *vmx_vmread_bitmap;
805static unsigned long *vmx_vmwrite_bitmap;
fdef3ad1 806
110312c8 807static bool cpu_has_load_ia32_efer;
8bf00a52 808static bool cpu_has_load_perf_global_ctrl;
110312c8 809
2384d2b3
SY		 810static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
811static DEFINE_SPINLOCK(vmx_vpid_lock);
812
1c3d14fe 813static struct vmcs_config {
6aa8b732
AK		 814 int size;
815 int order;
816 u32 revision_id;
1c3d14fe
YS		 817 u32 pin_based_exec_ctrl;
818 u32 cpu_based_exec_ctrl;
f78e0e2e 819 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 820 u32 vmexit_ctrl;
821 u32 vmentry_ctrl;
822} vmcs_config;
6aa8b732 823
efff9e53 824static struct vmx_capability {
d56f546d
SY		 825 u32 ept;
826 u32 vpid;
827} vmx_capability;
828
6aa8b732
AK		 829#define VMX_SEGMENT_FIELD(seg) \
830 [VCPU_SREG_##seg] = { \
831 .selector = GUEST_##seg##_SELECTOR, \
832 .base = GUEST_##seg##_BASE, \
833 .limit = GUEST_##seg##_LIMIT, \
834 .ar_bytes = GUEST_##seg##_AR_BYTES, \
835 }
836
772e0318 837static const struct kvm_vmx_segment_field {
6aa8b732
AK		 838 unsigned selector;
839 unsigned base;
840 unsigned limit;
841 unsigned ar_bytes;
842} kvm_vmx_segment_fields[] = {
843 VMX_SEGMENT_FIELD(CS),
844 VMX_SEGMENT_FIELD(DS),
845 VMX_SEGMENT_FIELD(ES),
846 VMX_SEGMENT_FIELD(FS),
847 VMX_SEGMENT_FIELD(GS),
848 VMX_SEGMENT_FIELD(SS),
849 VMX_SEGMENT_FIELD(TR),
850 VMX_SEGMENT_FIELD(LDTR),
851};
852
26bb0981
AK		 853static u64 host_efer;
854
6de4f3ad
AK		 855static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
856
4d56c8a7 857/*
8c06585d 858 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 859 * away by decrementing the array size.
860 */
6aa8b732 861static const u32 vmx_msr_index[] = {
05b3e0c2 862#ifdef CONFIG_X86_64
44ea2b17 863 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 864#endif
8c06585d 865 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 866};
6aa8b732 867
31299944 868static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 869{
870 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
871 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 872 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 873}
874
31299944 875static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 876{
877 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
878 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 879 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 880}
881
31299944 882static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 883{
884 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
885 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 886 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 887}
888
31299944 889static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 890{
891 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
892 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
893}
894
31299944 895static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 896{
897 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
898 INTR_INFO_VALID_MASK)) ==
899 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
900}
901
31299944 902static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 903{
04547156 904 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 905}
906
31299944 907static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 908{
04547156 909 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 910}
911
31299944 912static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 913{
04547156 914 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 915}
916
31299944 917static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 918{
04547156
SY		 919 return vmcs_config.cpu_based_exec_ctrl &
920 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 921}
922
774ead3a 923static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 924{
04547156
SY		 925 return vmcs_config.cpu_based_2nd_exec_ctrl &
926 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
927}
928
8d14695f
YZ		 929static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
930{
931 return vmcs_config.cpu_based_2nd_exec_ctrl &
932 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
933}
934
83d4c286
YZ		 935static inline bool cpu_has_vmx_apic_register_virt(void)
936{
937 return vmcs_config.cpu_based_2nd_exec_ctrl &
938 SECONDARY_EXEC_APIC_REGISTER_VIRT;
939}
940
c7c9c56c
YZ		 941static inline bool cpu_has_vmx_virtual_intr_delivery(void)
942{
943 return vmcs_config.cpu_based_2nd_exec_ctrl &
944 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
945}
946
01e439be
YZ		 947static inline bool cpu_has_vmx_posted_intr(void)
948{
949 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
950}
951
952static inline bool cpu_has_vmx_apicv(void)
953{
954 return cpu_has_vmx_apic_register_virt() &&
955 cpu_has_vmx_virtual_intr_delivery() &&
956 cpu_has_vmx_posted_intr();
957}
958
04547156
SY		 959static inline bool cpu_has_vmx_flexpriority(void)
960{
961 return cpu_has_vmx_tpr_shadow() &&
962 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 963}
964
e799794e
MT		 965static inline bool cpu_has_vmx_ept_execute_only(void)
966{
31299944 967 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 968}
969
e799794e
MT		 970static inline bool cpu_has_vmx_ept_2m_page(void)
971{
31299944 972 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 973}
974
878403b7
SY		 975static inline bool cpu_has_vmx_ept_1g_page(void)
976{
31299944 977 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 978}
979
4bc9b982
SY		 980static inline bool cpu_has_vmx_ept_4levels(void)
981{
982 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
983}
984
83c3a331
XH		 985static inline bool cpu_has_vmx_ept_ad_bits(void)
986{
987 return vmx_capability.ept & VMX_EPT_AD_BIT;
988}
989
31299944 990static inline bool cpu_has_vmx_invept_context(void)
d56f546d 991{
31299944 992 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 993}
994
31299944 995static inline bool cpu_has_vmx_invept_global(void)
d56f546d 996{
31299944 997 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 998}
999
518c8aee
GJ		 1000static inline bool cpu_has_vmx_invvpid_single(void)
1001{
1002 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1003}
1004
b9d762fa
GJ		 1005static inline bool cpu_has_vmx_invvpid_global(void)
1006{
1007 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1008}
1009
31299944 1010static inline bool cpu_has_vmx_ept(void)
d56f546d 1011{
04547156
SY		 1012 return vmcs_config.cpu_based_2nd_exec_ctrl &
1013 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 1014}
1015
31299944 1016static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 1017{
1018 return vmcs_config.cpu_based_2nd_exec_ctrl &
1019 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1020}
1021
31299944 1022static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 1023{
1024 return vmcs_config.cpu_based_2nd_exec_ctrl &
1025 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1026}
1027
31299944 1028static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 1029{
6d3e435e 1030 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 1031}
1032
31299944 1033static inline bool cpu_has_vmx_vpid(void)
2384d2b3 1034{
04547156
SY		 1035 return vmcs_config.cpu_based_2nd_exec_ctrl &
1036 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 1037}
1038
31299944 1039static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 1040{
1041 return vmcs_config.cpu_based_2nd_exec_ctrl &
1042 SECONDARY_EXEC_RDTSCP;
1043}
1044
ad756a16
MJ		 1045static inline bool cpu_has_vmx_invpcid(void)
1046{
1047 return vmcs_config.cpu_based_2nd_exec_ctrl &
1048 SECONDARY_EXEC_ENABLE_INVPCID;
1049}
1050
31299944 1051static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 1052{
1053 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1054}
1055
f5f48ee1
SY		 1056static inline bool cpu_has_vmx_wbinvd_exit(void)
1057{
1058 return vmcs_config.cpu_based_2nd_exec_ctrl &
1059 SECONDARY_EXEC_WBINVD_EXITING;
1060}
1061
abc4fc58
AG		 1062static inline bool cpu_has_vmx_shadow_vmcs(void)
1063{
1064 u64 vmx_msr;
1065 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1066 /* check if the cpu supports writing r/o exit information fields */
1067 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1068 return false;
1069
1070 return vmcs_config.cpu_based_2nd_exec_ctrl &
1071 SECONDARY_EXEC_SHADOW_VMCS;
1072}
1073
843e4330
KH		 1074static inline bool cpu_has_vmx_pml(void)
1075{
1076 return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1077}
1078
04547156
SY		 1079static inline bool report_flexpriority(void)
1080{
1081 return flexpriority_enabled;
1082}
1083
fe3ef05c
NHE		 1084static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1085{
1086 return vmcs12->cpu_based_vm_exec_control & bit;
1087}
1088
1089static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1090{
1091 return (vmcs12->cpu_based_vm_exec_control &
1092 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1093 (vmcs12->secondary_vm_exec_control & bit);
1094}
1095
f5c4368f 1096static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
644d711a
NHE		 1097{
1098 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1099}
1100
f4124500
JK		 1101static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1102{
1103 return vmcs12->pin_based_vm_exec_control &
1104 PIN_BASED_VMX_PREEMPTION_TIMER;
1105}
1106
155a97a3
NHE		 1107static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1108{
1109 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1110}
1111
81dc01f7
WL		 1112static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1113{
1114 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1115 vmx_xsaves_supported();
1116}
1117
f2b93280
WV		 1118static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1119{
1120 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1121}
1122
644d711a
NHE		 1123static inline bool is_exception(u32 intr_info)
1124{
1125 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1126 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1127}
1128
533558bc
JK		 1129static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1130 u32 exit_intr_info,
1131 unsigned long exit_qualification);
7c177938
NHE		 1132static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1133 struct vmcs12 *vmcs12,
1134 u32 reason, unsigned long qualification);
1135
8b9cf98c 1136static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 1137{
1138 int i;
1139
a2fa3e9f 1140 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 1141 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 1142 return i;
1143 return -1;
1144}
1145
2384d2b3
SY		 1146static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1147{
1148 struct {
1149 u64 vpid : 16;
1150 u64 rsvd : 48;
1151 u64 gva;
1152 } operand = { vpid, 0, gva };
1153
4ecac3fd 1154 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 1155 /* CF==1 or ZF==1 --> rc = -1 */
1156 "; ja 1f ; ud2 ; 1:"
1157 : : "a"(&operand), "c"(ext) : "cc", "memory");
1158}
1159
1439442c
SY		 1160static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1161{
1162 struct {
1163 u64 eptp, gpa;
1164 } operand = {eptp, gpa};
1165
4ecac3fd 1166 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 1167 /* CF==1 or ZF==1 --> rc = -1 */
1168 "; ja 1f ; ud2 ; 1:\n"
1169 : : "a" (&operand), "c" (ext) : "cc", "memory");
1170}
1171
26bb0981 1172static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 1173{
1174 int i;
1175
8b9cf98c 1176 i = __find_msr_index(vmx, msr);
a75beee6 1177 if (i >= 0)
a2fa3e9f 1178 return &vmx->guest_msrs[i];
8b6d44c7 1179 return NULL;
7725f0ba
AK		 1180}
1181
6aa8b732
AK		 1182static void vmcs_clear(struct vmcs *vmcs)
1183{
1184 u64 phys_addr = __pa(vmcs);
1185 u8 error;
1186
4ecac3fd 1187 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 1188 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1189 : "cc", "memory");
1190 if (error)
1191 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1192 vmcs, phys_addr);
1193}
1194
d462b819
NHE		 1195static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1196{
1197 vmcs_clear(loaded_vmcs->vmcs);
1198 loaded_vmcs->cpu = -1;
1199 loaded_vmcs->launched = 0;
1200}
1201
7725b894
DX		 1202static void vmcs_load(struct vmcs *vmcs)
1203{
1204 u64 phys_addr = __pa(vmcs);
1205 u8 error;
1206
1207 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1208 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 1209 : "cc", "memory");
1210 if (error)
2844d849 1211 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 1212 vmcs, phys_addr);
1213}
1214
8f536b76
ZY		 1215#ifdef CONFIG_KEXEC
1216/*
1217 * This bitmap is used to indicate whether the vmclear
1218 * operation is enabled on all cpus. All disabled by
1219 * default.
1220 */
1221static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1222
1223static inline void crash_enable_local_vmclear(int cpu)
1224{
1225 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1226}
1227
1228static inline void crash_disable_local_vmclear(int cpu)
1229{
1230 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1231}
1232
1233static inline int crash_local_vmclear_enabled(int cpu)
1234{
1235 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1236}
1237
1238static void crash_vmclear_local_loaded_vmcss(void)
1239{
1240 int cpu = raw_smp_processor_id();
1241 struct loaded_vmcs *v;
1242
1243 if (!crash_local_vmclear_enabled(cpu))
1244 return;
1245
1246 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1247 loaded_vmcss_on_cpu_link)
1248 vmcs_clear(v->vmcs);
1249}
1250#else
1251static inline void crash_enable_local_vmclear(int cpu) { }
1252static inline void crash_disable_local_vmclear(int cpu) { }
1253#endif /* CONFIG_KEXEC */
1254
d462b819 1255static void __loaded_vmcs_clear(void *arg)
6aa8b732 1256{
d462b819 1257 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1258 int cpu = raw_smp_processor_id();
6aa8b732 1259
d462b819
NHE		 1260 if (loaded_vmcs->cpu != cpu)
1261 return; /* vcpu migration can race with cpu offline */
1262 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1263 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1264 crash_disable_local_vmclear(cpu);
d462b819 1265 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1266
1267 /*
1268 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1269 * is before setting loaded_vmcs->vcpu to -1 which is done in
1270 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1271 * then adds the vmcs into percpu list before it is deleted.
1272 */
1273 smp_wmb();
1274
d462b819 1275 loaded_vmcs_init(loaded_vmcs);
8f536b76 1276 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 1277}
1278
d462b819 1279static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1280{
e6c7d321
XG		 1281 int cpu = loaded_vmcs->cpu;
1282
1283 if (cpu != -1)
1284 smp_call_function_single(cpu,
1285 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1286}
1287
1760dd49 1288static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1289{
1290 if (vmx->vpid == 0)
1291 return;
1292
518c8aee
GJ		 1293 if (cpu_has_vmx_invvpid_single())
1294 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1295}
1296
b9d762fa
GJ		 1297static inline void vpid_sync_vcpu_global(void)
1298{
1299 if (cpu_has_vmx_invvpid_global())
1300 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1301}
1302
1303static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1304{
1305 if (cpu_has_vmx_invvpid_single())
1760dd49 1306 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1307 else
1308 vpid_sync_vcpu_global();
1309}
1310
1439442c
SY		 1311static inline void ept_sync_global(void)
1312{
1313 if (cpu_has_vmx_invept_global())
1314 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1315}
1316
1317static inline void ept_sync_context(u64 eptp)
1318{
089d034e 1319 if (enable_ept) {
1439442c
SY		 1320 if (cpu_has_vmx_invept_context())
1321 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1322 else
1323 ept_sync_global();
1324 }
1325}
1326
96304217 1327static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1328{
5e520e62 1329 unsigned long value;
6aa8b732 1330
5e520e62
AK		 1331 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1332 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1333 return value;
1334}
1335
96304217 1336static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1337{
1338 return vmcs_readl(field);
1339}
1340
96304217 1341static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1342{
1343 return vmcs_readl(field);
1344}
1345
96304217 1346static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1347{
05b3e0c2 1348#ifdef CONFIG_X86_64
6aa8b732
AK		 1349 return vmcs_readl(field);
1350#else
1351 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1352#endif
1353}
1354
e52de1b8
AK		 1355static noinline void vmwrite_error(unsigned long field, unsigned long value)
1356{
1357 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1358 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1359 dump_stack();
1360}
1361
6aa8b732
AK		 1362static void vmcs_writel(unsigned long field, unsigned long value)
1363{
1364 u8 error;
1365
4ecac3fd 1366 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1367 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1368 if (unlikely(error))
1369 vmwrite_error(field, value);
6aa8b732
AK		 1370}
1371
1372static void vmcs_write16(unsigned long field, u16 value)
1373{
1374 vmcs_writel(field, value);
1375}
1376
1377static void vmcs_write32(unsigned long field, u32 value)
1378{
1379 vmcs_writel(field, value);
1380}
1381
1382static void vmcs_write64(unsigned long field, u64 value)
1383{
6aa8b732 1384 vmcs_writel(field, value);
7682f2d0 1385#ifndef CONFIG_X86_64
6aa8b732
AK		 1386 asm volatile ("");
1387 vmcs_writel(field+1, value >> 32);
1388#endif
1389}
1390
2ab455cc
AL		 1391static void vmcs_clear_bits(unsigned long field, u32 mask)
1392{
1393 vmcs_writel(field, vmcs_readl(field) & ~mask);
1394}
1395
1396static void vmcs_set_bits(unsigned long field, u32 mask)
1397{
1398 vmcs_writel(field, vmcs_readl(field) | mask);
1399}
1400
2961e876
GN		 1401static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1402{
1403 vmcs_write32(VM_ENTRY_CONTROLS, val);
1404 vmx->vm_entry_controls_shadow = val;
1405}
1406
1407static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1408{
1409 if (vmx->vm_entry_controls_shadow != val)
1410 vm_entry_controls_init(vmx, val);
1411}
1412
1413static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1414{
1415 return vmx->vm_entry_controls_shadow;
1416}
1417
1418
1419static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1420{
1421 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1422}
1423
1424static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1425{
1426 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1427}
1428
1429static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1430{
1431 vmcs_write32(VM_EXIT_CONTROLS, val);
1432 vmx->vm_exit_controls_shadow = val;
1433}
1434
1435static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1436{
1437 if (vmx->vm_exit_controls_shadow != val)
1438 vm_exit_controls_init(vmx, val);
1439}
1440
1441static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1442{
1443 return vmx->vm_exit_controls_shadow;
1444}
1445
1446
1447static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1448{
1449 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1450}
1451
1452static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1453{
1454 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1455}
1456
2fb92db1
AK		 1457static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1458{
1459 vmx->segment_cache.bitmask = 0;
1460}
1461
1462static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1463 unsigned field)
1464{
1465 bool ret;
1466 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1467
1468 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1469 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1470 vmx->segment_cache.bitmask = 0;
1471 }
1472 ret = vmx->segment_cache.bitmask & mask;
1473 vmx->segment_cache.bitmask |= mask;
1474 return ret;
1475}
1476
1477static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1478{
1479 u16 *p = &vmx->segment_cache.seg[seg].selector;
1480
1481 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1482 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1483 return *p;
1484}
1485
1486static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1487{
1488 ulong *p = &vmx->segment_cache.seg[seg].base;
1489
1490 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1491 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1492 return *p;
1493}
1494
1495static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1496{
1497 u32 *p = &vmx->segment_cache.seg[seg].limit;
1498
1499 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1500 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1501 return *p;
1502}
1503
1504static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1505{
1506 u32 *p = &vmx->segment_cache.seg[seg].ar;
1507
1508 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1509 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1510 return *p;
1511}
1512
abd3f2d6
AK		 1513static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1514{
1515 u32 eb;
1516
fd7373cc
JK		 1517 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1518 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1519 if ((vcpu->guest_debug &
1520 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1521 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1522 eb |= 1u << BP_VECTOR;
7ffd92c5 1523 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1524 eb = ~0;
089d034e 1525 if (enable_ept)
1439442c 1526 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1527 if (vcpu->fpu_active)
1528 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1529
1530 /* When we are running a nested L2 guest and L1 specified for it a
1531 * certain exception bitmap, we must trap the same exceptions and pass
1532 * them to L1. When running L2, we will only handle the exceptions
1533 * specified above if L1 did not want them.
1534 */
1535 if (is_guest_mode(vcpu))
1536 eb |= get_vmcs12(vcpu)->exception_bitmap;
1537
abd3f2d6
AK		 1538 vmcs_write32(EXCEPTION_BITMAP, eb);
1539}
1540
2961e876
GN		 1541static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1542 unsigned long entry, unsigned long exit)
8bf00a52 1543{
2961e876
GN		 1544 vm_entry_controls_clearbit(vmx, entry);
1545 vm_exit_controls_clearbit(vmx, exit);
8bf00a52
GN		 1546}
1547
61d2ef2c
AK		 1548static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1549{
1550 unsigned i;
1551 struct msr_autoload *m = &vmx->msr_autoload;
1552
8bf00a52
GN		 1553 switch (msr) {
1554 case MSR_EFER:
1555 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1556 clear_atomic_switch_msr_special(vmx,
1557 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1558 VM_EXIT_LOAD_IA32_EFER);
1559 return;
1560 }
1561 break;
1562 case MSR_CORE_PERF_GLOBAL_CTRL:
1563 if (cpu_has_load_perf_global_ctrl) {
2961e876 1564 clear_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1565 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1566 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1567 return;
1568 }
1569 break;
110312c8
AK		 1570 }
1571
61d2ef2c
AK		 1572 for (i = 0; i < m->nr; ++i)
1573 if (m->guest[i].index == msr)
1574 break;
1575
1576 if (i == m->nr)
1577 return;
1578 --m->nr;
1579 m->guest[i] = m->guest[m->nr];
1580 m->host[i] = m->host[m->nr];
1581 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1582 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1583}
1584
2961e876
GN		 1585static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1586 unsigned long entry, unsigned long exit,
1587 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1588 u64 guest_val, u64 host_val)
8bf00a52
GN		 1589{
1590 vmcs_write64(guest_val_vmcs, guest_val);
1591 vmcs_write64(host_val_vmcs, host_val);
2961e876
GN		 1592 vm_entry_controls_setbit(vmx, entry);
1593 vm_exit_controls_setbit(vmx, exit);
8bf00a52
GN		 1594}
1595
61d2ef2c
AK		 1596static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1597 u64 guest_val, u64 host_val)
1598{
1599 unsigned i;
1600 struct msr_autoload *m = &vmx->msr_autoload;
1601
8bf00a52
GN		 1602 switch (msr) {
1603 case MSR_EFER:
1604 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1605 add_atomic_switch_msr_special(vmx,
1606 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1607 VM_EXIT_LOAD_IA32_EFER,
1608 GUEST_IA32_EFER,
1609 HOST_IA32_EFER,
1610 guest_val, host_val);
1611 return;
1612 }
1613 break;
1614 case MSR_CORE_PERF_GLOBAL_CTRL:
1615 if (cpu_has_load_perf_global_ctrl) {
2961e876 1616 add_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1617 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1618 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1619 GUEST_IA32_PERF_GLOBAL_CTRL,
1620 HOST_IA32_PERF_GLOBAL_CTRL,
1621 guest_val, host_val);
1622 return;
1623 }
1624 break;
110312c8
AK		 1625 }
1626
61d2ef2c
AK		 1627 for (i = 0; i < m->nr; ++i)
1628 if (m->guest[i].index == msr)
1629 break;
1630
e7fc6f93 1631 if (i == NR_AUTOLOAD_MSRS) {
60266204 1632 printk_once(KERN_WARNING "Not enough msr switch entries. "
e7fc6f93
GN		 1633 "Can't add msr %x\n", msr);
1634 return;
1635 } else if (i == m->nr) {
61d2ef2c
AK		 1636 ++m->nr;
1637 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1638 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1639 }
1640
1641 m->guest[i].index = msr;
1642 m->guest[i].value = guest_val;
1643 m->host[i].index = msr;
1644 m->host[i].value = host_val;
1645}
1646
33ed6329
AK		 1647static void reload_tss(void)
1648{
33ed6329
AK		 1649 /*
1650 * VT restores TR but not its size. Useless.
1651 */
89cbc767 1652 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
a5f61300 1653 struct desc_struct *descs;
33ed6329 1654
d359192f 1655 descs = (void *)gdt->address;
33ed6329
AK		 1656 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1657 load_TR_desc();
33ed6329
AK		 1658}
1659
92c0d900 1660static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1661{
3a34a881 1662 u64 guest_efer;
51c6cf66
AK		 1663 u64 ignore_bits;
1664
f6801dff 1665 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1666
51c6cf66 1667 /*
0fa06071 1668 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1669 * outside long mode
1670 */
1671 ignore_bits = EFER_NX | EFER_SCE;
1672#ifdef CONFIG_X86_64
1673 ignore_bits |= EFER_LMA | EFER_LME;
1674 /* SCE is meaningful only in long mode on Intel */
1675 if (guest_efer & EFER_LMA)
1676 ignore_bits &= ~(u64)EFER_SCE;
1677#endif
51c6cf66
AK		 1678 guest_efer &= ~ignore_bits;
1679 guest_efer |= host_efer & ignore_bits;
26bb0981 1680 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1681 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1682
1683 clear_atomic_switch_msr(vmx, MSR_EFER);
f6577a5f
AL		 1684
1685 /*
1686 * On EPT, we can't emulate NX, so we must switch EFER atomically.
1687 * On CPUs that support "load IA32_EFER", always switch EFER
1688 * atomically, since it's faster than switching it manually.
1689 */
1690 if (cpu_has_load_ia32_efer ||
1691 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
84ad33ef
AK		 1692 guest_efer = vmx->vcpu.arch.efer;
1693 if (!(guest_efer & EFER_LMA))
1694 guest_efer &= ~EFER_LME;
54b98bff
AL		 1695 if (guest_efer != host_efer)
1696 add_atomic_switch_msr(vmx, MSR_EFER,
1697 guest_efer, host_efer);
84ad33ef
AK		 1698 return false;
1699 }
1700
26bb0981 1701 return true;
51c6cf66
AK		 1702}
1703
2d49ec72
GN		 1704static unsigned long segment_base(u16 selector)
1705{
89cbc767 1706 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2d49ec72
GN		 1707 struct desc_struct *d;
1708 unsigned long table_base;
1709 unsigned long v;
1710
1711 if (!(selector & ~3))
1712 return 0;
1713
d359192f 1714 table_base = gdt->address;
2d49ec72
GN		 1715
1716 if (selector & 4) { /* from ldt */
1717 u16 ldt_selector = kvm_read_ldt();
1718
1719 if (!(ldt_selector & ~3))
1720 return 0;
1721
1722 table_base = segment_base(ldt_selector);
1723 }
1724 d = (struct desc_struct *)(table_base + (selector & ~7));
1725 v = get_desc_base(d);
1726#ifdef CONFIG_X86_64
1727 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1728 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1729#endif
1730 return v;
1731}
1732
1733static inline unsigned long kvm_read_tr_base(void)
1734{
1735 u16 tr;
1736 asm("str %0" : "=g"(tr));
1737 return segment_base(tr);
1738}
1739
04d2cc77 1740static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1741{
04d2cc77 1742 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1743 int i;
04d2cc77 1744
a2fa3e9f 1745 if (vmx->host_state.loaded)
33ed6329
AK		 1746 return;
1747
a2fa3e9f 1748 vmx->host_state.loaded = 1;
33ed6329
AK		 1749 /*
1750 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1751 * allow segment selectors with cpl > 0 or ti == 1.
1752 */
d6e88aec 1753 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1754 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1755 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1756 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1757 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1758 vmx->host_state.fs_reload_needed = 0;
1759 } else {
33ed6329 1760 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1761 vmx->host_state.fs_reload_needed = 1;
33ed6329 1762 }
9581d442 1763 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1764 if (!(vmx->host_state.gs_sel & 7))
1765 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1766 else {
1767 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1768 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1769 }
1770
b2da15ac
AK		 1771#ifdef CONFIG_X86_64
1772 savesegment(ds, vmx->host_state.ds_sel);
1773 savesegment(es, vmx->host_state.es_sel);
1774#endif
1775
33ed6329
AK		 1776#ifdef CONFIG_X86_64
1777 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1778 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1779#else
a2fa3e9f
GH		 1780 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1781 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1782#endif
707c0874
AK		 1783
1784#ifdef CONFIG_X86_64
c8770e7b
AK		 1785 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1786 if (is_long_mode(&vmx->vcpu))
44ea2b17 1787 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1788#endif
da8999d3
LJ		 1789 if (boot_cpu_has(X86_FEATURE_MPX))
1790 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
26bb0981
AK		 1791 for (i = 0; i < vmx->save_nmsrs; ++i)
1792 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1793 vmx->guest_msrs[i].data,
1794 vmx->guest_msrs[i].mask);
33ed6329
AK		 1795}
1796
a9b21b62 1797static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1798{
a2fa3e9f 1799 if (!vmx->host_state.loaded)
33ed6329
AK		 1800 return;
1801
e1beb1d3 1802 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1803 vmx->host_state.loaded = 0;
c8770e7b
AK		 1804#ifdef CONFIG_X86_64
1805 if (is_long_mode(&vmx->vcpu))
1806 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1807#endif
152d3f2f 1808 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1809 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1810#ifdef CONFIG_X86_64
9581d442 1811 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1812#else
1813 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1814#endif
33ed6329 1815 }
0a77fe4c
AK		 1816 if (vmx->host_state.fs_reload_needed)
1817 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1818#ifdef CONFIG_X86_64
1819 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1820 loadsegment(ds, vmx->host_state.ds_sel);
1821 loadsegment(es, vmx->host_state.es_sel);
1822 }
b2da15ac 1823#endif
152d3f2f 1824 reload_tss();
44ea2b17 1825#ifdef CONFIG_X86_64
c8770e7b 1826 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1827#endif
da8999d3
LJ		 1828 if (vmx->host_state.msr_host_bndcfgs)
1829 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
b1a74bf8
SS		 1830 /*
1831 * If the FPU is not active (through the host task or
1832 * the guest vcpu), then restore the cr0.TS bit.
1833 */
1834 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1835 stts();
89cbc767 1836 load_gdt(this_cpu_ptr(&host_gdt));
33ed6329
AK		 1837}
1838
a9b21b62
AK		 1839static void vmx_load_host_state(struct vcpu_vmx *vmx)
1840{
1841 preempt_disable();
1842 __vmx_load_host_state(vmx);
1843 preempt_enable();
1844}
1845
6aa8b732
AK		 1846/*
1847 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1848 * vcpu mutex is already taken.
1849 */
15ad7146 1850static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1851{
a2fa3e9f 1852 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1853 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1854
4610c9cc
DX		 1855 if (!vmm_exclusive)
1856 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1857 else if (vmx->loaded_vmcs->cpu != cpu)
1858 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1859
d462b819
NHE		 1860 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1861 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1862 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1863 }
1864
d462b819 1865 if (vmx->loaded_vmcs->cpu != cpu) {
89cbc767 1866 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
6aa8b732
AK		 1867 unsigned long sysenter_esp;
1868
a8eeb04a 1869 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1870 local_irq_disable();
8f536b76 1871 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1872
1873 /*
1874 * Read loaded_vmcs->cpu should be before fetching
1875 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1876 * See the comments in __loaded_vmcs_clear().
1877 */
1878 smp_rmb();
1879
d462b819
NHE		 1880 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1881 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1882 crash_enable_local_vmclear(cpu);
92fe13be
DX		 1883 local_irq_enable();
1884
6aa8b732
AK		 1885 /*
1886 * Linux uses per-cpu TSS and GDT, so set these when switching
1887 * processors.
1888 */
d6e88aec 1889 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1890 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1891
1892 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1893 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1894 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1895 }
6aa8b732
AK		 1896}
1897
1898static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1899{
a9b21b62 1900 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1901 if (!vmm_exclusive) {
d462b819
NHE		 1902 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1903 vcpu->cpu = -1;
4610c9cc
DX		 1904 kvm_cpu_vmxoff();
1905 }
6aa8b732
AK		 1906}
1907
5fd86fcf
AK		 1908static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1909{
81231c69
AK		 1910 ulong cr0;
1911
5fd86fcf
AK		 1912 if (vcpu->fpu_active)
1913 return;
1914 vcpu->fpu_active = 1;
81231c69
AK		 1915 cr0 = vmcs_readl(GUEST_CR0);
1916 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1917 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1918 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1919 update_exception_bitmap(vcpu);
edcafe3c 1920 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1921 if (is_guest_mode(vcpu))
1922 vcpu->arch.cr0_guest_owned_bits &=
1923 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1924 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1925}
1926
edcafe3c
AK		 1927static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1928
fe3ef05c
NHE		 1929/*
1930 * Return the cr0 value that a nested guest would read. This is a combination
1931 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1932 * its hypervisor (cr0_read_shadow).
1933 */
1934static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1935{
1936 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1937 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1938}
1939static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1940{
1941 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1942 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1943}
1944
5fd86fcf
AK		 1945static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1946{
36cf24e0
NHE		 1947 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1948 * set this *before* calling this function.
1949 */
edcafe3c 1950 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1951 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1952 update_exception_bitmap(vcpu);
edcafe3c
AK		 1953 vcpu->arch.cr0_guest_owned_bits = 0;
1954 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1955 if (is_guest_mode(vcpu)) {
1956 /*
1957 * L1's specified read shadow might not contain the TS bit,
1958 * so now that we turned on shadowing of this bit, we need to
1959 * set this bit of the shadow. Like in nested_vmx_run we need
1960 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1961 * up-to-date here because we just decached cr0.TS (and we'll
1962 * only update vmcs12->guest_cr0 on nested exit).
1963 */
1964 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1965 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1966 (vcpu->arch.cr0 & X86_CR0_TS);
1967 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1968 } else
1969 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1970}
1971
6aa8b732
AK		 1972static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1973{
78ac8b47 1974 unsigned long rflags, save_rflags;
345dcaa8 1975
6de12732
AK		 1976 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1977 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1978 rflags = vmcs_readl(GUEST_RFLAGS);
1979 if (to_vmx(vcpu)->rmode.vm86_active) {
1980 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1981 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1982 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1983 }
1984 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1985 }
6de12732 1986 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1987}
1988
1989static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1990{
6de12732
AK		 1991 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1992 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1993 if (to_vmx(vcpu)->rmode.vm86_active) {
1994 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1995 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1996 }
6aa8b732
AK		 1997 vmcs_writel(GUEST_RFLAGS, rflags);
1998}
1999
37ccdcbe 2000static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2809f5d2
GC		 2001{
2002 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2003 int ret = 0;
2004
2005 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 2006 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 2007 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 2008 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2 2009
37ccdcbe 2010 return ret;
2809f5d2
GC		 2011}
2012
2013static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2014{
2015 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2016 u32 interruptibility = interruptibility_old;
2017
2018 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2019
48005f64 2020 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 2021 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 2022 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 2023 interruptibility |= GUEST_INTR_STATE_STI;
2024
2025 if ((interruptibility != interruptibility_old))
2026 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2027}
2028
6aa8b732
AK		 2029static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2030{
2031 unsigned long rip;
6aa8b732 2032
5fdbf976 2033 rip = kvm_rip_read(vcpu);
6aa8b732 2034 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 2035 kvm_rip_write(vcpu, rip);
6aa8b732 2036
2809f5d2
GC		 2037 /* skipping an emulated instruction also counts */
2038 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 2039}
2040
0b6ac343
NHE		 2041/*
2042 * KVM wants to inject page-faults which it got to the guest. This function
2043 * checks whether in a nested guest, we need to inject them to L1 or L2.
0b6ac343 2044 */
e011c663 2045static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
0b6ac343
NHE		 2046{
2047 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2048
e011c663 2049 if (!(vmcs12->exception_bitmap & (1u << nr)))
0b6ac343
NHE		 2050 return 0;
2051
533558bc
JK		 2052 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2053 vmcs_read32(VM_EXIT_INTR_INFO),
2054 vmcs_readl(EXIT_QUALIFICATION));
0b6ac343
NHE		 2055 return 1;
2056}
2057
298101da 2058static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 2059 bool has_error_code, u32 error_code,
2060 bool reinject)
298101da 2061{
77ab6db0 2062 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 2063 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 2064
e011c663
GN		 2065 if (!reinject && is_guest_mode(vcpu) &&
2066 nested_vmx_check_exception(vcpu, nr))
0b6ac343
NHE		 2067 return;
2068
8ab2d2e2 2069 if (has_error_code) {
77ab6db0 2070 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 2071 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2072 }
77ab6db0 2073
7ffd92c5 2074 if (vmx->rmode.vm86_active) {
71f9833b
SH		 2075 int inc_eip = 0;
2076 if (kvm_exception_is_soft(nr))
2077 inc_eip = vcpu->arch.event_exit_inst_len;
2078 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 2079 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 2080 return;
2081 }
2082
66fd3f7f
GN		 2083 if (kvm_exception_is_soft(nr)) {
2084 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2085 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 2086 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2087 } else
2088 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2089
2090 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 2091}
2092
4e47c7a6
SY		 2093static bool vmx_rdtscp_supported(void)
2094{
2095 return cpu_has_vmx_rdtscp();
2096}
2097
ad756a16
MJ		 2098static bool vmx_invpcid_supported(void)
2099{
2100 return cpu_has_vmx_invpcid() && enable_ept;
2101}
2102
a75beee6
ED		 2103/*
2104 * Swap MSR entry in host/guest MSR entry array.
2105 */
8b9cf98c 2106static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 2107{
26bb0981 2108 struct shared_msr_entry tmp;
a2fa3e9f
GH		 2109
2110 tmp = vmx->guest_msrs[to];
2111 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2112 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 2113}
2114
8d14695f
YZ		 2115static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2116{
2117 unsigned long *msr_bitmap;
2118
2119 if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
2120 if (is_long_mode(vcpu))
2121 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2122 else
2123 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2124 } else {
2125 if (is_long_mode(vcpu))
2126 msr_bitmap = vmx_msr_bitmap_longmode;
2127 else
2128 msr_bitmap = vmx_msr_bitmap_legacy;
2129 }
2130
2131 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2132}
2133
e38aea3e
AK		 2134/*
2135 * Set up the vmcs to automatically save and restore system
2136 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2137 * mode, as fiddling with msrs is very expensive.
2138 */
8b9cf98c 2139static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 2140{
26bb0981 2141 int save_nmsrs, index;
e38aea3e 2142
a75beee6
ED		 2143 save_nmsrs = 0;
2144#ifdef CONFIG_X86_64
8b9cf98c 2145 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 2146 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 2147 if (index >= 0)
8b9cf98c
RR		 2148 move_msr_up(vmx, index, save_nmsrs++);
2149 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 2150 if (index >= 0)
8b9cf98c
RR		 2151 move_msr_up(vmx, index, save_nmsrs++);
2152 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 2153 if (index >= 0)
8b9cf98c 2154 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 2155 index = __find_msr_index(vmx, MSR_TSC_AUX);
2156 if (index >= 0 && vmx->rdtscp_enabled)
2157 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 2158 /*
8c06585d 2159 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 2160 * if efer.sce is enabled.
2161 */
8c06585d 2162 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 2163 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 2164 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 2165 }
2166#endif
92c0d900
AK		 2167 index = __find_msr_index(vmx, MSR_EFER);
2168 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 2169 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 2170
26bb0981 2171 vmx->save_nmsrs = save_nmsrs;
5897297b 2172
8d14695f
YZ		 2173 if (cpu_has_vmx_msr_bitmap())
2174 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 2175}
2176
6aa8b732
AK		 2177/*
2178 * reads and returns guest's timestamp counter "register"
2179 * guest_tsc = host_tsc + tsc_offset -- 21.3
2180 */
2181static u64 guest_read_tsc(void)
2182{
2183 u64 host_tsc, tsc_offset;
2184
2185 rdtscll(host_tsc);
2186 tsc_offset = vmcs_read64(TSC_OFFSET);
2187 return host_tsc + tsc_offset;
2188}
2189
d5c1785d
NHE		 2190/*
2191 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2192 * counter, even if a nested guest (L2) is currently running.
2193 */
48d89b92 2194static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 2195{
886b470c 2196 u64 tsc_offset;
d5c1785d 2197
d5c1785d
NHE		 2198 tsc_offset = is_guest_mode(vcpu) ?
2199 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2200 vmcs_read64(TSC_OFFSET);
2201 return host_tsc + tsc_offset;
2202}
2203
4051b188 2204/*
cc578287
ZA		 2205 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2206 * software catchup for faster rates on slower CPUs.
4051b188 2207 */
cc578287 2208static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 2209{
cc578287
ZA		 2210 if (!scale)
2211 return;
2212
2213 if (user_tsc_khz > tsc_khz) {
2214 vcpu->arch.tsc_catchup = 1;
2215 vcpu->arch.tsc_always_catchup = 1;
2216 } else
2217 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 2218}
2219
ba904635
WA		 2220static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2221{
2222 return vmcs_read64(TSC_OFFSET);
2223}
2224
6aa8b732 2225/*
99e3e30a 2226 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 2227 */
99e3e30a 2228static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 2229{
27fc51b2 2230 if (is_guest_mode(vcpu)) {
7991825b 2231 /*
27fc51b2
NHE		 2232 * We're here if L1 chose not to trap WRMSR to TSC. According
2233 * to the spec, this should set L1's TSC; The offset that L1
2234 * set for L2 remains unchanged, and still needs to be added
2235 * to the newly set TSC to get L2's TSC.
7991825b 2236 */
27fc51b2
NHE		 2237 struct vmcs12 *vmcs12;
2238 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2239 /* recalculate vmcs02.TSC_OFFSET: */
2240 vmcs12 = get_vmcs12(vcpu);
2241 vmcs_write64(TSC_OFFSET, offset +
2242 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2243 vmcs12->tsc_offset : 0));
2244 } else {
489223ed
YY		 2245 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2246 vmcs_read64(TSC_OFFSET), offset);
27fc51b2
NHE		 2247 vmcs_write64(TSC_OFFSET, offset);
2248 }
6aa8b732
AK		 2249}
2250
f1e2b260 2251static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 2252{
2253 u64 offset = vmcs_read64(TSC_OFFSET);
489223ed 2254
e48672fa 2255 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 2256 if (is_guest_mode(vcpu)) {
2257 /* Even when running L2, the adjustment needs to apply to L1 */
2258 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
489223ed
YY		 2259 } else
2260 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2261 offset + adjustment);
e48672fa
ZA		 2262}
2263
857e4099
JR		 2264static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2265{
2266 return target_tsc - native_read_tsc();
2267}
2268
801d3424
NHE		 2269static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2270{
2271 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2272 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2273}
2274
2275/*
2276 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2277 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2278 * all guests if the "nested" module option is off, and can also be disabled
2279 * for a single guest by disabling its VMX cpuid bit.
2280 */
2281static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2282{
2283 return nested && guest_cpuid_has_vmx(vcpu);
2284}
2285
b87a51ae
NHE		 2286/*
2287 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2288 * returned for the various VMX controls MSRs when nested VMX is enabled.
2289 * The same values should also be used to verify that vmcs12 control fields are
2290 * valid during nested entry from L1 to L2.
2291 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2292 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2293 * bit in the high half is on if the corresponding bit in the control field
2294 * may be on. See also vmx_control_verify().
2295 * TODO: allow these variables to be modified (downgraded) by module options
2296 * or other means.
2297 */
2298static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
3dcdf3ec 2299static u32 nested_vmx_true_procbased_ctls_low;
b87a51ae
NHE		 2300static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2301static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2302static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2996fca0 2303static u32 nested_vmx_true_exit_ctls_low;
b87a51ae 2304static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
2996fca0 2305static u32 nested_vmx_true_entry_ctls_low;
c18911a2 2306static u32 nested_vmx_misc_low, nested_vmx_misc_high;
bfd0a56b 2307static u32 nested_vmx_ept_caps;
b87a51ae
NHE		 2308static __init void nested_vmx_setup_ctls_msrs(void)
2309{
2310 /*
2311 * Note that as a general rule, the high half of the MSRs (bits in
2312 * the control fields which may be 1) should be initialized by the
2313 * intersection of the underlying hardware's MSR (i.e., features which
2314 * can be supported) and the list of features we want to expose -
2315 * because they are known to be properly supported in our code.
2316 * Also, usually, the low half of the MSRs (bits which must be 1) can
2317 * be set to 0, meaning that L1 may turn off any of these bits. The
2318 * reason is that if one of these bits is necessary, it will appear
2319 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2320 * fields of vmcs01 and vmcs02, will turn these bits off - and
2321 * nested_vmx_exit_handled() will not pass related exits to L1.
2322 * These rules have exceptions below.
2323 */
2324
2325 /* pin-based controls */
eabeaacc
JK		 2326 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2327 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
eabeaacc
JK		 2328 nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2329 nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
f4124500
JK		 2330 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS;
2331 nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
0238ea91 2332 PIN_BASED_VMX_PREEMPTION_TIMER;
b87a51ae 2333
3dbcd8da 2334 /* exit controls */
c0dfee58
ACL		 2335 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2336 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high);
33fb20c3 2337 nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
e0ba1a6f 2338
c0dfee58 2339 nested_vmx_exit_ctls_high &=
b87a51ae 2340#ifdef CONFIG_X86_64
c0dfee58 2341 VM_EXIT_HOST_ADDR_SPACE_SIZE |
b87a51ae 2342#endif
f4124500
JK		 2343 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2344 nested_vmx_exit_ctls_high |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2345 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
e0ba1a6f
BD		 2346 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2347
36be0b9d
PB		 2348 if (vmx_mpx_supported())
2349 nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
b87a51ae 2350
2996fca0
JK		 2351 /* We support free control of debug control saving. */
2352 nested_vmx_true_exit_ctls_low = nested_vmx_exit_ctls_low &
2353 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2354
b87a51ae
NHE		 2355 /* entry controls */
2356 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2357 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
33fb20c3 2358 nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2359 nested_vmx_entry_ctls_high &=
57435349
JK		 2360#ifdef CONFIG_X86_64
2361 VM_ENTRY_IA32E_MODE |
2362#endif
2363 VM_ENTRY_LOAD_IA32_PAT;
8049d651
NHE		 2364 nested_vmx_entry_ctls_high |= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR |
2365 VM_ENTRY_LOAD_IA32_EFER);
36be0b9d
PB		 2366 if (vmx_mpx_supported())
2367 nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
57435349 2368
2996fca0
JK		 2369 /* We support free control of debug control loading. */
2370 nested_vmx_true_entry_ctls_low = nested_vmx_entry_ctls_low &
2371 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2372
b87a51ae
NHE		 2373 /* cpu-based controls */
2374 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2375 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
560b7ee1 2376 nested_vmx_procbased_ctls_low = CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2377 nested_vmx_procbased_ctls_high &=
a294c9bb
JK		 2378 CPU_BASED_VIRTUAL_INTR_PENDING |
2379 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
b87a51ae
NHE		 2380 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2381 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2382 CPU_BASED_CR3_STORE_EXITING |
2383#ifdef CONFIG_X86_64
2384 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2385#endif
2386 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2387 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
dbcb4e79 2388 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
a7c0b07d 2389 CPU_BASED_PAUSE_EXITING | CPU_BASED_TPR_SHADOW |
b87a51ae
NHE		 2390 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2391 /*
2392 * We can allow some features even when not supported by the
2393 * hardware. For example, L1 can specify an MSR bitmap - and we
2394 * can use it to avoid exits to L1 - even when L0 runs L2
2395 * without MSR bitmaps.
2396 */
560b7ee1
JK		 2397 nested_vmx_procbased_ctls_high |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2398 CPU_BASED_USE_MSR_BITMAPS;
b87a51ae 2399
3dcdf3ec
JK		 2400 /* We support free control of CR3 access interception. */
2401 nested_vmx_true_procbased_ctls_low = nested_vmx_procbased_ctls_low &
2402 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2403
b87a51ae
NHE		 2404 /* secondary cpu-based controls */
2405 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2406 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2407 nested_vmx_secondary_ctls_low = 0;
2408 nested_vmx_secondary_ctls_high &=
d6851fbe 2409 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
f2b93280 2410 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
81dc01f7
WL		 2411 SECONDARY_EXEC_WBINVD_EXITING |
2412 SECONDARY_EXEC_XSAVES;
c18911a2 2413
afa61f75
NHE		 2414 if (enable_ept) {
2415 /* nested EPT: emulate EPT also to L1 */
78051e3b
BD		 2416 nested_vmx_secondary_ctls_high |= SECONDARY_EXEC_ENABLE_EPT |
2417 SECONDARY_EXEC_UNRESTRICTED_GUEST;
ca72d970 2418 nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
d3134dbf
JK		 2419 VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2420 VMX_EPT_INVEPT_BIT;
afa61f75
NHE		 2421 nested_vmx_ept_caps &= vmx_capability.ept;
2422 /*
4b855078
BD		 2423 * For nested guests, we don't do anything specific
2424 * for single context invalidation. Hence, only advertise
2425 * support for global context invalidation.
afa61f75 2426 */
4b855078 2427 nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
afa61f75
NHE		 2428 } else
2429 nested_vmx_ept_caps = 0;
2430
c18911a2
JK		 2431 /* miscellaneous data */
2432 rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
f4124500
JK		 2433 nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2434 nested_vmx_misc_low |= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2435 VMX_MISC_ACTIVITY_HLT;
c18911a2 2436 nested_vmx_misc_high = 0;
b87a51ae
NHE		 2437}
2438
2439static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2440{
2441 /*
2442 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2443 */
2444 return ((control & high) | low) == control;
2445}
2446
2447static inline u64 vmx_control_msr(u32 low, u32 high)
2448{
2449 return low | ((u64)high << 32);
2450}
2451
cae50139 2452/* Returns 0 on success, non-0 otherwise. */
b87a51ae
NHE		 2453static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2454{
b87a51ae 2455 switch (msr_index) {
b87a51ae
NHE		 2456 case MSR_IA32_VMX_BASIC:
2457 /*
2458 * This MSR reports some information about VMX support. We
2459 * should return information about the VMX we emulate for the
2460 * guest, and the VMCS structure we give it - not about the
2461 * VMX support of the underlying hardware.
2462 */
3dbcd8da 2463 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
b87a51ae
NHE		 2464 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2465 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2466 break;
2467 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2468 case MSR_IA32_VMX_PINBASED_CTLS:
2469 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2470 nested_vmx_pinbased_ctls_high);
2471 break;
2472 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3dcdf3ec
JK		 2473 *pdata = vmx_control_msr(nested_vmx_true_procbased_ctls_low,
2474 nested_vmx_procbased_ctls_high);
2475 break;
b87a51ae
NHE		 2476 case MSR_IA32_VMX_PROCBASED_CTLS:
2477 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2478 nested_vmx_procbased_ctls_high);
2479 break;
2480 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2996fca0
JK		 2481 *pdata = vmx_control_msr(nested_vmx_true_exit_ctls_low,
2482 nested_vmx_exit_ctls_high);
2483 break;
b87a51ae
NHE		 2484 case MSR_IA32_VMX_EXIT_CTLS:
2485 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2486 nested_vmx_exit_ctls_high);
2487 break;
2488 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2996fca0
JK		 2489 *pdata = vmx_control_msr(nested_vmx_true_entry_ctls_low,
2490 nested_vmx_entry_ctls_high);
2491 break;
b87a51ae
NHE		 2492 case MSR_IA32_VMX_ENTRY_CTLS:
2493 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2494 nested_vmx_entry_ctls_high);
2495 break;
2496 case MSR_IA32_VMX_MISC:
c18911a2
JK		 2497 *pdata = vmx_control_msr(nested_vmx_misc_low,
2498 nested_vmx_misc_high);
b87a51ae
NHE		 2499 break;
2500 /*
2501 * These MSRs specify bits which the guest must keep fixed (on or off)
2502 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2503 * We picked the standard core2 setting.
2504 */
2505#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2506#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2507 case MSR_IA32_VMX_CR0_FIXED0:
2508 *pdata = VMXON_CR0_ALWAYSON;
2509 break;
2510 case MSR_IA32_VMX_CR0_FIXED1:
2511 *pdata = -1ULL;
2512 break;
2513 case MSR_IA32_VMX_CR4_FIXED0:
2514 *pdata = VMXON_CR4_ALWAYSON;
2515 break;
2516 case MSR_IA32_VMX_CR4_FIXED1:
2517 *pdata = -1ULL;
2518 break;
2519 case MSR_IA32_VMX_VMCS_ENUM:
5381417f 2520 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
b87a51ae
NHE		 2521 break;
2522 case MSR_IA32_VMX_PROCBASED_CTLS2:
2523 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2524 nested_vmx_secondary_ctls_high);
2525 break;
2526 case MSR_IA32_VMX_EPT_VPID_CAP:
afa61f75
NHE		 2527 /* Currently, no nested vpid support */
2528 *pdata = nested_vmx_ept_caps;
b87a51ae
NHE		 2529 break;
2530 default:
b87a51ae 2531 return 1;
b3897a49
NHE		 2532 }
2533
b87a51ae
NHE		 2534 return 0;
2535}
2536
6aa8b732
AK		 2537/*
2538 * Reads an msr value (of 'msr_index') into 'pdata'.
2539 * Returns 0 on success, non-0 otherwise.
2540 * Assumes vcpu_load() was already called.
2541 */
2542static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2543{
2544 u64 data;
26bb0981 2545 struct shared_msr_entry *msr;
6aa8b732
AK		 2546
2547 if (!pdata) {
2548 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2549 return -EINVAL;
2550 }
2551
2552 switch (msr_index) {
05b3e0c2 2553#ifdef CONFIG_X86_64
6aa8b732
AK		 2554 case MSR_FS_BASE:
2555 data = vmcs_readl(GUEST_FS_BASE);
2556 break;
2557 case MSR_GS_BASE:
2558 data = vmcs_readl(GUEST_GS_BASE);
2559 break;
44ea2b17
AK		 2560 case MSR_KERNEL_GS_BASE:
2561 vmx_load_host_state(to_vmx(vcpu));
2562 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2563 break;
26bb0981 2564#endif
6aa8b732 2565 case MSR_EFER:
3bab1f5d 2566 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2567 case MSR_IA32_TSC:
6aa8b732
AK		 2568 data = guest_read_tsc();
2569 break;
2570 case MSR_IA32_SYSENTER_CS:
2571 data = vmcs_read32(GUEST_SYSENTER_CS);
2572 break;
2573 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2574 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2575 break;
2576 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2577 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2578 break;
0dd376e7 2579 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2580 if (!vmx_mpx_supported())
2581 return 1;
0dd376e7
LJ		 2582 data = vmcs_read64(GUEST_BNDCFGS);
2583 break;
cae50139
JK		 2584 case MSR_IA32_FEATURE_CONTROL:
2585 if (!nested_vmx_allowed(vcpu))
2586 return 1;
2587 data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2588 break;
2589 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2590 if (!nested_vmx_allowed(vcpu))
2591 return 1;
2592 return vmx_get_vmx_msr(vcpu, msr_index, pdata);
20300099
WL		 2593 case MSR_IA32_XSS:
2594 if (!vmx_xsaves_supported())
2595 return 1;
2596 data = vcpu->arch.ia32_xss;
2597 break;
4e47c7a6
SY		 2598 case MSR_TSC_AUX:
2599 if (!to_vmx(vcpu)->rdtscp_enabled)
2600 return 1;
2601 /* Otherwise falls through */
6aa8b732 2602 default:
8b9cf98c 2603 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2604 if (msr) {
2605 data = msr->data;
2606 break;
6aa8b732 2607 }
3bab1f5d 2608 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2609 }
2610
2611 *pdata = data;
2612 return 0;
2613}
2614
cae50139
JK		 2615static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2616
6aa8b732
AK		 2617/*
2618 * Writes msr value into into the appropriate "register".
2619 * Returns 0 on success, non-0 otherwise.
2620 * Assumes vcpu_load() was already called.
2621 */
8fe8ab46 2622static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2623{
a2fa3e9f 2624 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2625 struct shared_msr_entry *msr;
2cc51560 2626 int ret = 0;
8fe8ab46
WA		 2627 u32 msr_index = msr_info->index;
2628 u64 data = msr_info->data;
2cc51560 2629
6aa8b732 2630 switch (msr_index) {
3bab1f5d 2631 case MSR_EFER:
8fe8ab46 2632 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2633 break;
16175a79 2634#ifdef CONFIG_X86_64
6aa8b732 2635 case MSR_FS_BASE:
2fb92db1 2636 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2637 vmcs_writel(GUEST_FS_BASE, data);
2638 break;
2639 case MSR_GS_BASE:
2fb92db1 2640 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2641 vmcs_writel(GUEST_GS_BASE, data);
2642 break;
44ea2b17
AK		 2643 case MSR_KERNEL_GS_BASE:
2644 vmx_load_host_state(vmx);
2645 vmx->msr_guest_kernel_gs_base = data;
2646 break;
6aa8b732
AK		 2647#endif
2648 case MSR_IA32_SYSENTER_CS:
2649 vmcs_write32(GUEST_SYSENTER_CS, data);
2650 break;
2651 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2652 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2653 break;
2654 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2655 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2656 break;
0dd376e7 2657 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2658 if (!vmx_mpx_supported())
2659 return 1;
0dd376e7
LJ		 2660 vmcs_write64(GUEST_BNDCFGS, data);
2661 break;
af24a4e4 2662 case MSR_IA32_TSC:
8fe8ab46 2663 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2664 break;
468d472f
SY		 2665 case MSR_IA32_CR_PAT:
2666 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4566654b
NA		 2667 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2668 return 1;
468d472f
SY		 2669 vmcs_write64(GUEST_IA32_PAT, data);
2670 vcpu->arch.pat = data;
2671 break;
2672 }
8fe8ab46 2673 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2674 break;
ba904635
WA		 2675 case MSR_IA32_TSC_ADJUST:
2676 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2677 break;
cae50139
JK		 2678 case MSR_IA32_FEATURE_CONTROL:
2679 if (!nested_vmx_allowed(vcpu) ||
2680 (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2681 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2682 return 1;
2683 vmx->nested.msr_ia32_feature_control = data;
2684 if (msr_info->host_initiated && data == 0)
2685 vmx_leave_nested(vcpu);
2686 break;
2687 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2688 return 1; /* they are read-only */
20300099
WL		 2689 case MSR_IA32_XSS:
2690 if (!vmx_xsaves_supported())
2691 return 1;
2692 /*
2693 * The only supported bit as of Skylake is bit 8, but
2694 * it is not supported on KVM.
2695 */
2696 if (data != 0)
2697 return 1;
2698 vcpu->arch.ia32_xss = data;
2699 if (vcpu->arch.ia32_xss != host_xss)
2700 add_atomic_switch_msr(vmx, MSR_IA32_XSS,
2701 vcpu->arch.ia32_xss, host_xss);
2702 else
2703 clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
2704 break;
4e47c7a6
SY		 2705 case MSR_TSC_AUX:
2706 if (!vmx->rdtscp_enabled)
2707 return 1;
2708 /* Check reserved bit, higher 32 bits should be zero */
2709 if ((data >> 32) != 0)
2710 return 1;
2711 /* Otherwise falls through */
6aa8b732 2712 default:
8b9cf98c 2713 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 2714 if (msr) {
8b3c3104 2715 u64 old_msr_data = msr->data;
3bab1f5d 2716 msr->data = data;
2225fd56
AK		 2717 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2718 preempt_disable();
8b3c3104
AH		 2719 ret = kvm_set_shared_msr(msr->index, msr->data,
2720 msr->mask);
2225fd56 2721 preempt_enable();
8b3c3104
AH		 2722 if (ret)
2723 msr->data = old_msr_data;
2225fd56 2724 }
3bab1f5d 2725 break;
6aa8b732 2726 }
8fe8ab46 2727 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2728 }
2729
2cc51560 2730 return ret;
6aa8b732
AK		 2731}
2732
5fdbf976 2733static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2734{
5fdbf976
MT		 2735 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2736 switch (reg) {
2737 case VCPU_REGS_RSP:
2738 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2739 break;
2740 case VCPU_REGS_RIP:
2741 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2742 break;
6de4f3ad
AK		 2743 case VCPU_EXREG_PDPTR:
2744 if (enable_ept)
2745 ept_save_pdptrs(vcpu);
2746 break;
5fdbf976
MT		 2747 default:
2748 break;
2749 }
6aa8b732
AK		 2750}
2751
6aa8b732
AK		 2752static __init int cpu_has_kvm_support(void)
2753{
6210e37b 2754 return cpu_has_vmx();
6aa8b732
AK		 2755}
2756
2757static __init int vmx_disabled_by_bios(void)
2758{
2759 u64 msr;
2760
2761 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2762 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2763 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2764 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2765 && tboot_enabled())
2766 return 1;
23f3e991 2767 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2768 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2769 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2770 && !tboot_enabled()) {
2771 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2772 "activate TXT before enabling KVM\n");
cafd6659 2773 return 1;
f9335afe 2774 }
23f3e991
JC		 2775 /* launched w/o TXT and VMX disabled */
2776 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2777 && !tboot_enabled())
2778 return 1;
cafd6659
SW		 2779 }
2780
2781 return 0;
6aa8b732
AK		 2782}
2783
7725b894
DX		 2784static void kvm_cpu_vmxon(u64 addr)
2785{
2786 asm volatile (ASM_VMX_VMXON_RAX
2787 : : "a"(&addr), "m"(addr)
2788 : "memory", "cc");
2789}
2790
13a34e06 2791static int hardware_enable(void)
6aa8b732
AK		 2792{
2793 int cpu = raw_smp_processor_id();
2794 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2795 u64 old, test_bits;
6aa8b732 2796
10474ae8
AG		 2797 if (read_cr4() & X86_CR4_VMXE)
2798 return -EBUSY;
2799
d462b819 2800 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76
ZY		 2801
2802 /*
2803 * Now we can enable the vmclear operation in kdump
2804 * since the loaded_vmcss_on_cpu list on this cpu
2805 * has been initialized.
2806 *
2807 * Though the cpu is not in VMX operation now, there
2808 * is no problem to enable the vmclear operation
2809 * for the loaded_vmcss_on_cpu list is empty!
2810 */
2811 crash_enable_local_vmclear(cpu);
2812
6aa8b732 2813 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2814
2815 test_bits = FEATURE_CONTROL_LOCKED;
2816 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2817 if (tboot_enabled())
2818 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2819
2820 if ((old & test_bits) != test_bits) {
6aa8b732 2821 /* enable and lock */
cafd6659
SW		 2822 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2823 }
66aee91a 2824 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2825
4610c9cc
DX		 2826 if (vmm_exclusive) {
2827 kvm_cpu_vmxon(phys_addr);
2828 ept_sync_global();
2829 }
10474ae8 2830
89cbc767 2831 native_store_gdt(this_cpu_ptr(&host_gdt));
3444d7da 2832
10474ae8 2833 return 0;
6aa8b732
AK		 2834}
2835
d462b819 2836static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2837{
2838 int cpu = raw_smp_processor_id();
d462b819 2839 struct loaded_vmcs *v, *n;
543e4243 2840
d462b819
NHE		 2841 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2842 loaded_vmcss_on_cpu_link)
2843 __loaded_vmcs_clear(v);
543e4243
AK		 2844}
2845
710ff4a8
EH		 2846
2847/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2848 * tricks.
2849 */
2850static void kvm_cpu_vmxoff(void)
6aa8b732 2851{
4ecac3fd 2852 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2853}
2854
13a34e06 2855static void hardware_disable(void)
710ff4a8 2856{
4610c9cc 2857 if (vmm_exclusive) {
d462b819 2858 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2859 kvm_cpu_vmxoff();
2860 }
7725b894 2861 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2862}
2863
1c3d14fe 2864static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2865 u32 msr, u32 *result)
1c3d14fe
YS		 2866{
2867 u32 vmx_msr_low, vmx_msr_high;
2868 u32 ctl = ctl_min | ctl_opt;
2869
2870 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2871
2872 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2873 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2874
2875 /* Ensure minimum (required) set of control bits are supported. */
2876 if (ctl_min & ~ctl)
002c7f7c 2877 return -EIO;
1c3d14fe
YS		 2878
2879 *result = ctl;
2880 return 0;
2881}
2882
110312c8
AK		 2883static __init bool allow_1_setting(u32 msr, u32 ctl)
2884{
2885 u32 vmx_msr_low, vmx_msr_high;
2886
2887 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2888 return vmx_msr_high & ctl;
2889}
2890
002c7f7c 2891static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2892{
2893 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2894 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2895 u32 _pin_based_exec_control = 0;
2896 u32 _cpu_based_exec_control = 0;
f78e0e2e 2897 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2898 u32 _vmexit_control = 0;
2899 u32 _vmentry_control = 0;
2900
10166744 2901 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2902#ifdef CONFIG_X86_64
2903 CPU_BASED_CR8_LOAD_EXITING |
2904 CPU_BASED_CR8_STORE_EXITING |
2905#endif
d56f546d
SY		 2906 CPU_BASED_CR3_LOAD_EXITING |
2907 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2908 CPU_BASED_USE_IO_BITMAPS |
2909 CPU_BASED_MOV_DR_EXITING |
a7052897 2910 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2911 CPU_BASED_MWAIT_EXITING |
2912 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2913 CPU_BASED_INVLPG_EXITING |
2914 CPU_BASED_RDPMC_EXITING;
443381a8 2915
f78e0e2e 2916 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2917 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2918 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2919 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2920 &_cpu_based_exec_control) < 0)
002c7f7c 2921 return -EIO;
6e5d865c
YS		 2922#ifdef CONFIG_X86_64
2923 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2924 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2925 ~CPU_BASED_CR8_STORE_EXITING;
2926#endif
f78e0e2e 2927 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2928 min2 = 0;
2929 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 2930 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 2931 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2932 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2933 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2934 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2935 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 2936 SECONDARY_EXEC_RDTSCP |
83d4c286 2937 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 2938 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58 2939 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
20300099 2940 SECONDARY_EXEC_SHADOW_VMCS |
843e4330
KH		 2941 SECONDARY_EXEC_XSAVES |
2942 SECONDARY_EXEC_ENABLE_PML;
d56f546d
SY		 2943 if (adjust_vmx_controls(min2, opt2,
2944 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2945 &_cpu_based_2nd_exec_control) < 0)
2946 return -EIO;
2947 }
2948#ifndef CONFIG_X86_64
2949 if (!(_cpu_based_2nd_exec_control &
2950 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2951 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2952#endif
83d4c286
YZ		 2953
2954 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2955 _cpu_based_2nd_exec_control &= ~(
8d14695f 2956 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 2957 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2958 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 2959
d56f546d 2960 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2961 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2962 enabled */
5fff7d27
GN		 2963 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2964 CPU_BASED_CR3_STORE_EXITING |
2965 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2966 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2967 vmx_capability.ept, vmx_capability.vpid);
2968 }
1c3d14fe 2969
81908bf4 2970 min = VM_EXIT_SAVE_DEBUG_CONTROLS;
1c3d14fe
YS		 2971#ifdef CONFIG_X86_64
2972 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2973#endif
a547c6db 2974 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
da8999d3 2975 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
1c3d14fe
YS		 2976 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2977 &_vmexit_control) < 0)
002c7f7c 2978 return -EIO;
1c3d14fe 2979
01e439be
YZ		 2980 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2981 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2982 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2983 &_pin_based_exec_control) < 0)
2984 return -EIO;
2985
2986 if (!(_cpu_based_2nd_exec_control &
2987 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2988 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2989 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2990
c845f9c6 2991 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
da8999d3 2992 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
1c3d14fe
YS		 2993 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2994 &_vmentry_control) < 0)
002c7f7c 2995 return -EIO;
6aa8b732 2996
c68876fd 2997 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2998
2999 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3000 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 3001 return -EIO;
1c3d14fe
YS		 3002
3003#ifdef CONFIG_X86_64
3004 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3005 if (vmx_msr_high & (1u<<16))
002c7f7c 3006 return -EIO;
1c3d14fe
YS		 3007#endif
3008
3009 /* Require Write-Back (WB) memory type for VMCS accesses. */
3010 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 3011 return -EIO;
1c3d14fe 3012
002c7f7c
YS		 3013 vmcs_conf->size = vmx_msr_high & 0x1fff;
3014 vmcs_conf->order = get_order(vmcs_config.size);
3015 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 3016
002c7f7c
YS		 3017 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3018 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 3019 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 3020 vmcs_conf->vmexit_ctrl = _vmexit_control;
3021 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 3022
110312c8
AK		 3023 cpu_has_load_ia32_efer =
3024 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3025 VM_ENTRY_LOAD_IA32_EFER)
3026 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3027 VM_EXIT_LOAD_IA32_EFER);
3028
8bf00a52
GN		 3029 cpu_has_load_perf_global_ctrl =
3030 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3031 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3032 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3033 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3034
3035 /*
3036 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3037 * but due to arrata below it can't be used. Workaround is to use
3038 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3039 *
3040 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3041 *
3042 * AAK155 (model 26)
3043 * AAP115 (model 30)
3044 * AAT100 (model 37)
3045 * BC86,AAY89,BD102 (model 44)
3046 * BA97 (model 46)
3047 *
3048 */
3049 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3050 switch (boot_cpu_data.x86_model) {
3051 case 26:
3052 case 30:
3053 case 37:
3054 case 44:
3055 case 46:
3056 cpu_has_load_perf_global_ctrl = false;
3057 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3058 "does not work properly. Using workaround\n");
3059 break;
3060 default:
3061 break;
3062 }
3063 }
3064
20300099
WL		 3065 if (cpu_has_xsaves)
3066 rdmsrl(MSR_IA32_XSS, host_xss);
3067
1c3d14fe 3068 return 0;
c68876fd 3069}
6aa8b732
AK		 3070
3071static struct vmcs *alloc_vmcs_cpu(int cpu)
3072{
3073 int node = cpu_to_node(cpu);
3074 struct page *pages;
3075 struct vmcs *vmcs;
3076
6484eb3e 3077 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 3078 if (!pages)
3079 return NULL;
3080 vmcs = page_address(pages);
1c3d14fe
YS		 3081 memset(vmcs, 0, vmcs_config.size);
3082 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 3083 return vmcs;
3084}
3085
3086static struct vmcs *alloc_vmcs(void)
3087{
d3b2c338 3088 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 3089}
3090
3091static void free_vmcs(struct vmcs *vmcs)
3092{
1c3d14fe 3093 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 3094}
3095
d462b819
NHE		 3096/*
3097 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3098 */
3099static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3100{
3101 if (!loaded_vmcs->vmcs)
3102 return;
3103 loaded_vmcs_clear(loaded_vmcs);
3104 free_vmcs(loaded_vmcs->vmcs);
3105 loaded_vmcs->vmcs = NULL;
3106}
3107
39959588 3108static void free_kvm_area(void)
6aa8b732
AK		 3109{
3110 int cpu;
3111
3230bb47 3112 for_each_possible_cpu(cpu) {
6aa8b732 3113 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 3114 per_cpu(vmxarea, cpu) = NULL;
3115 }
6aa8b732
AK		 3116}
3117
fe2b201b
BD		 3118static void init_vmcs_shadow_fields(void)
3119{
3120 int i, j;
3121
3122 /* No checks for read only fields yet */
3123
3124 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3125 switch (shadow_read_write_fields[i]) {
3126 case GUEST_BNDCFGS:
3127 if (!vmx_mpx_supported())
3128 continue;
3129 break;
3130 default:
3131 break;
3132 }
3133
3134 if (j < i)
3135 shadow_read_write_fields[j] =
3136 shadow_read_write_fields[i];
3137 j++;
3138 }
3139 max_shadow_read_write_fields = j;
3140
3141 /* shadowed fields guest access without vmexit */
3142 for (i = 0; i < max_shadow_read_write_fields; i++) {
3143 clear_bit(shadow_read_write_fields[i],
3144 vmx_vmwrite_bitmap);
3145 clear_bit(shadow_read_write_fields[i],
3146 vmx_vmread_bitmap);
3147 }
3148 for (i = 0; i < max_shadow_read_only_fields; i++)
3149 clear_bit(shadow_read_only_fields[i],
3150 vmx_vmread_bitmap);
3151}
3152
6aa8b732
AK		 3153static __init int alloc_kvm_area(void)
3154{
3155 int cpu;
3156
3230bb47 3157 for_each_possible_cpu(cpu) {
6aa8b732
AK		 3158 struct vmcs *vmcs;
3159
3160 vmcs = alloc_vmcs_cpu(cpu);
3161 if (!vmcs) {
3162 free_kvm_area();
3163 return -ENOMEM;
3164 }
3165
3166 per_cpu(vmxarea, cpu) = vmcs;
3167 }
3168 return 0;
3169}
3170
14168786
GN		 3171static bool emulation_required(struct kvm_vcpu *vcpu)
3172{
3173 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3174}
3175
91b0aa2c 3176static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 3177 struct kvm_segment *save)
6aa8b732 3178{
d99e4152
GN		 3179 if (!emulate_invalid_guest_state) {
3180 /*
3181 * CS and SS RPL should be equal during guest entry according
3182 * to VMX spec, but in reality it is not always so. Since vcpu
3183 * is in the middle of the transition from real mode to
3184 * protected mode it is safe to assume that RPL 0 is a good
3185 * default value.
3186 */
3187 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3188 save->selector &= ~SELECTOR_RPL_MASK;
3189 save->dpl = save->selector & SELECTOR_RPL_MASK;
3190 save->s = 1;
6aa8b732 3191 }
d99e4152 3192 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 3193}
3194
3195static void enter_pmode(struct kvm_vcpu *vcpu)
3196{
3197 unsigned long flags;
a89a8fb9 3198 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3199
d99e4152
GN		 3200 /*
3201 * Update real mode segment cache. It may be not up-to-date if sement
3202 * register was written while vcpu was in a guest mode.
3203 */
3204 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3205 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3206 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3207 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3208 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3209 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3210
7ffd92c5 3211 vmx->rmode.vm86_active = 0;
6aa8b732 3212
2fb92db1
AK		 3213 vmx_segment_cache_clear(vmx);
3214
f5f7b2fe 3215 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 3216
3217 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 3218 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3219 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 3220 vmcs_writel(GUEST_RFLAGS, flags);
3221
66aee91a
RR		 3222 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3223 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 3224
3225 update_exception_bitmap(vcpu);
3226
91b0aa2c
GN		 3227 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3228 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3229 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3230 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3231 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3232 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
6aa8b732
AK		 3233}
3234
f5f7b2fe 3235static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 3236{
772e0318 3237 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 3238 struct kvm_segment var = *save;
3239
3240 var.dpl = 0x3;
3241 if (seg == VCPU_SREG_CS)
3242 var.type = 0x3;
3243
3244 if (!emulate_invalid_guest_state) {
3245 var.selector = var.base >> 4;
3246 var.base = var.base & 0xffff0;
3247 var.limit = 0xffff;
3248 var.g = 0;
3249 var.db = 0;
3250 var.present = 1;
3251 var.s = 1;
3252 var.l = 0;
3253 var.unusable = 0;
3254 var.type = 0x3;
3255 var.avl = 0;
3256 if (save->base & 0xf)
3257 printk_once(KERN_WARNING "kvm: segment base is not "
3258 "paragraph aligned when entering "
3259 "protected mode (seg=%d)", seg);
3260 }
6aa8b732 3261
d99e4152
GN		 3262 vmcs_write16(sf->selector, var.selector);
3263 vmcs_write32(sf->base, var.base);
3264 vmcs_write32(sf->limit, var.limit);
3265 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 3266}
3267
3268static void enter_rmode(struct kvm_vcpu *vcpu)
3269{
3270 unsigned long flags;
a89a8fb9 3271 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3272
f5f7b2fe
AK		 3273 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3274 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3275 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3276 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3277 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 3278 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3279 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 3280
7ffd92c5 3281 vmx->rmode.vm86_active = 1;
6aa8b732 3282
776e58ea
GN		 3283 /*
3284 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 3285 * vcpu. Warn the user that an update is overdue.
776e58ea 3286 */
4918c6ca 3287 if (!vcpu->kvm->arch.tss_addr)
776e58ea
GN		 3288 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3289 "called before entering vcpu\n");
776e58ea 3290
2fb92db1
AK		 3291 vmx_segment_cache_clear(vmx);
3292
4918c6ca 3293 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
6aa8b732 3294 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 3295 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3296
3297 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 3298 vmx->rmode.save_rflags = flags;
6aa8b732 3299
053de044 3300 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 3301
3302 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 3303 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 3304 update_exception_bitmap(vcpu);
3305
d99e4152
GN		 3306 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3307 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3308 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3309 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3310 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3311 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 3312
8668a3c4 3313 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 3314}
3315
401d10de
AS		 3316static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3317{
3318 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 3319 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3320
3321 if (!msr)
3322 return;
401d10de 3323
44ea2b17
AK		 3324 /*
3325 * Force kernel_gs_base reloading before EFER changes, as control
3326 * of this msr depends on is_long_mode().
3327 */
3328 vmx_load_host_state(to_vmx(vcpu));
f6801dff 3329 vcpu->arch.efer = efer;
401d10de 3330 if (efer & EFER_LMA) {
2961e876 3331 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3332 msr->data = efer;
3333 } else {
2961e876 3334 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3335
3336 msr->data = efer & ~EFER_LME;
3337 }
3338 setup_msrs(vmx);
3339}
3340
05b3e0c2 3341#ifdef CONFIG_X86_64
6aa8b732
AK		 3342
3343static void enter_lmode(struct kvm_vcpu *vcpu)
3344{
3345 u32 guest_tr_ar;
3346
2fb92db1
AK		 3347 vmx_segment_cache_clear(to_vmx(vcpu));
3348
6aa8b732
AK		 3349 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3350 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 3351 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3352 __func__);
6aa8b732
AK		 3353 vmcs_write32(GUEST_TR_AR_BYTES,
3354 (guest_tr_ar & ~AR_TYPE_MASK)
3355 | AR_TYPE_BUSY_64_TSS);
3356 }
da38f438 3357 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 3358}
3359
3360static void exit_lmode(struct kvm_vcpu *vcpu)
3361{
2961e876 3362 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
da38f438 3363 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 3364}
3365
3366#endif
3367
2384d2b3
SY		 3368static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3369{
b9d762fa 3370 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 3371 if (enable_ept) {
3372 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3373 return;
4e1096d2 3374 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 3375 }
2384d2b3
SY		 3376}
3377
e8467fda
AK		 3378static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3379{
3380 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3381
3382 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3383 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3384}
3385
aff48baa
AK		 3386static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3387{
3388 if (enable_ept && is_paging(vcpu))
3389 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3390 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3391}
3392
25c4c276 3393static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 3394{
fc78f519
AK		 3395 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3396
3397 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3398 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 3399}
3400
1439442c
SY		 3401static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3402{
d0d538b9
GN		 3403 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3404
6de4f3ad
AK		 3405 if (!test_bit(VCPU_EXREG_PDPTR,
3406 (unsigned long *)&vcpu->arch.regs_dirty))
3407 return;
3408
1439442c 3409 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3410 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3411 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3412 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3413 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
1439442c
SY		 3414 }
3415}
3416
8f5d549f
AK		 3417static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3418{
d0d538b9
GN		 3419 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3420
8f5d549f 3421 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3422 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3423 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3424 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3425 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 3426 }
6de4f3ad
AK		 3427
3428 __set_bit(VCPU_EXREG_PDPTR,
3429 (unsigned long *)&vcpu->arch.regs_avail);
3430 __set_bit(VCPU_EXREG_PDPTR,
3431 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 3432}
3433
5e1746d6 3434static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 3435
3436static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3437 unsigned long cr0,
3438 struct kvm_vcpu *vcpu)
3439{
5233dd51
MT		 3440 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3441 vmx_decache_cr3(vcpu);
1439442c
SY		 3442 if (!(cr0 & X86_CR0_PG)) {
3443 /* From paging/starting to nonpaging */
3444 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3445 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 3446 (CPU_BASED_CR3_LOAD_EXITING |
3447 CPU_BASED_CR3_STORE_EXITING));
3448 vcpu->arch.cr0 = cr0;
fc78f519 3449 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3450 } else if (!is_paging(vcpu)) {
3451 /* From nonpaging to paging */
3452 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3453 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3454 ~(CPU_BASED_CR3_LOAD_EXITING |
3455 CPU_BASED_CR3_STORE_EXITING));
3456 vcpu->arch.cr0 = cr0;
fc78f519 3457 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3458 }
95eb84a7
SY		 3459
3460 if (!(cr0 & X86_CR0_WP))
3461 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3462}
3463
6aa8b732
AK		 3464static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3465{
7ffd92c5 3466 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3467 unsigned long hw_cr0;
3468
5037878e 3469 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 3470 if (enable_unrestricted_guest)
5037878e 3471 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 3472 else {
5037878e 3473 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 3474
218e763f
GN		 3475 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3476 enter_pmode(vcpu);
6aa8b732 3477
218e763f
GN		 3478 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3479 enter_rmode(vcpu);
3480 }
6aa8b732 3481
05b3e0c2 3482#ifdef CONFIG_X86_64
f6801dff 3483 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3484 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3485 enter_lmode(vcpu);
707d92fa 3486 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3487 exit_lmode(vcpu);
3488 }
3489#endif
3490
089d034e 3491 if (enable_ept)
1439442c
SY		 3492 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3493
02daab21 3494 if (!vcpu->fpu_active)
81231c69 3495 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3496
6aa8b732 3497 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3498 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3499 vcpu->arch.cr0 = cr0;
14168786
GN		 3500
3501 /* depends on vcpu->arch.cr0 to be set to a new value */
3502 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3503}
3504
1439442c
SY		 3505static u64 construct_eptp(unsigned long root_hpa)
3506{
3507 u64 eptp;
3508
3509 /* TODO write the value reading from MSR */
3510 eptp = VMX_EPT_DEFAULT_MT |
3511 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3512 if (enable_ept_ad_bits)
3513 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3514 eptp |= (root_hpa & PAGE_MASK);
3515
3516 return eptp;
3517}
3518
6aa8b732
AK		 3519static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3520{
1439442c
SY		 3521 unsigned long guest_cr3;
3522 u64 eptp;
3523
3524 guest_cr3 = cr3;
089d034e 3525 if (enable_ept) {
1439442c
SY		 3526 eptp = construct_eptp(cr3);
3527 vmcs_write64(EPT_POINTER, eptp);
59ab5a8f
JK		 3528 if (is_paging(vcpu) || is_guest_mode(vcpu))
3529 guest_cr3 = kvm_read_cr3(vcpu);
3530 else
3531 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3532 ept_load_pdptrs(vcpu);
1439442c
SY		 3533 }
3534
2384d2b3 3535 vmx_flush_tlb(vcpu);
1439442c 3536 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3537}
3538
5e1746d6 3539static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3540{
7ffd92c5 3541 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3542 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3543
5e1746d6
NHE		 3544 if (cr4 & X86_CR4_VMXE) {
3545 /*
3546 * To use VMXON (and later other VMX instructions), a guest
3547 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3548 * So basically the check on whether to allow nested VMX
3549 * is here.
3550 */
3551 if (!nested_vmx_allowed(vcpu))
3552 return 1;
1a0d74e6
JK		 3553 }
3554 if (to_vmx(vcpu)->nested.vmxon &&
3555 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
5e1746d6
NHE		 3556 return 1;
3557
ad312c7c 3558 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3559 if (enable_ept) {
3560 if (!is_paging(vcpu)) {
3561 hw_cr4 &= ~X86_CR4_PAE;
3562 hw_cr4 |= X86_CR4_PSE;
c08800a5 3563 /*
e1e746b3
FW		 3564 * SMEP/SMAP is disabled if CPU is in non-paging mode
3565 * in hardware. However KVM always uses paging mode to
c08800a5 3566 * emulate guest non-paging mode with TDP.
e1e746b3
FW		 3567 * To emulate this behavior, SMEP/SMAP needs to be
3568 * manually disabled when guest switches to non-paging
3569 * mode.
c08800a5 3570 */
e1e746b3 3571 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
bc23008b
AK		 3572 } else if (!(cr4 & X86_CR4_PAE)) {
3573 hw_cr4 &= ~X86_CR4_PAE;
3574 }
3575 }
1439442c
SY		 3576
3577 vmcs_writel(CR4_READ_SHADOW, cr4);
3578 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3579 return 0;
6aa8b732
AK		 3580}
3581
6aa8b732
AK		 3582static void vmx_get_segment(struct kvm_vcpu *vcpu,
3583 struct kvm_segment *var, int seg)
3584{
a9179499 3585 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3586 u32 ar;
3587
c6ad1153 3588 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3589 *var = vmx->rmode.segs[seg];
a9179499 3590 if (seg == VCPU_SREG_TR
2fb92db1 3591 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3592 return;
1390a28b
AK		 3593 var->base = vmx_read_guest_seg_base(vmx, seg);
3594 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3595 return;
a9179499 3596 }
2fb92db1
AK		 3597 var->base = vmx_read_guest_seg_base(vmx, seg);
3598 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3599 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3600 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 3601 var->unusable = (ar >> 16) & 1;
6aa8b732
AK		 3602 var->type = ar & 15;
3603 var->s = (ar >> 4) & 1;
3604 var->dpl = (ar >> 5) & 3;
03617c18
GN		 3605 /*
3606 * Some userspaces do not preserve unusable property. Since usable
3607 * segment has to be present according to VMX spec we can use present
3608 * property to amend userspace bug by making unusable segment always
3609 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3610 * segment as unusable.
3611 */
3612 var->present = !var->unusable;
6aa8b732
AK		 3613 var->avl = (ar >> 12) & 1;
3614 var->l = (ar >> 13) & 1;
3615 var->db = (ar >> 14) & 1;
3616 var->g = (ar >> 15) & 1;
6aa8b732
AK		 3617}
3618
a9179499
AK		 3619static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3620{
a9179499
AK		 3621 struct kvm_segment s;
3622
3623 if (to_vmx(vcpu)->rmode.vm86_active) {
3624 vmx_get_segment(vcpu, &s, seg);
3625 return s.base;
3626 }
2fb92db1 3627 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3628}
3629
b09408d0 3630static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3631{
b09408d0
MT		 3632 struct vcpu_vmx *vmx = to_vmx(vcpu);
3633
ae9fedc7 3634 if (unlikely(vmx->rmode.vm86_active))
2e4d2653 3635 return 0;
ae9fedc7
PB		 3636 else {
3637 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3638 return AR_DPL(ar);
69c73028 3639 }
69c73028
AK		 3640}
3641
653e3108 3642static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3643{
6aa8b732
AK		 3644 u32 ar;
3645
f0495f9b 3646 if (var->unusable || !var->present)
6aa8b732
AK		 3647 ar = 1 << 16;
3648 else {
3649 ar = var->type & 15;
3650 ar |= (var->s & 1) << 4;
3651 ar |= (var->dpl & 3) << 5;
3652 ar |= (var->present & 1) << 7;
3653 ar |= (var->avl & 1) << 12;
3654 ar |= (var->l & 1) << 13;
3655 ar |= (var->db & 1) << 14;
3656 ar |= (var->g & 1) << 15;
3657 }
653e3108
AK		 3658
3659 return ar;
3660}
3661
3662static void vmx_set_segment(struct kvm_vcpu *vcpu,
3663 struct kvm_segment *var, int seg)
3664{
7ffd92c5 3665 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3666 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3667
2fb92db1
AK		 3668 vmx_segment_cache_clear(vmx);
3669
1ecd50a9
GN		 3670 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3671 vmx->rmode.segs[seg] = *var;
3672 if (seg == VCPU_SREG_TR)
3673 vmcs_write16(sf->selector, var->selector);
3674 else if (var->s)
3675 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3676 goto out;
653e3108 3677 }
1ecd50a9 3678
653e3108
AK		 3679 vmcs_writel(sf->base, var->base);
3680 vmcs_write32(sf->limit, var->limit);
3681 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3682
3683 /*
3684 * Fix the "Accessed" bit in AR field of segment registers for older
3685 * qemu binaries.
3686 * IA32 arch specifies that at the time of processor reset the
3687 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3688 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3689 * state vmexit when "unrestricted guest" mode is turned on.
3690 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3691 * tree. Newer qemu binaries with that qemu fix would not need this
3692 * kvm hack.
3693 */
3694 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3695 var->type |= 0x1; /* Accessed */
3a624e29 3696
f924d66d 3697 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3698
3699out:
98eb2f8b 3700 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3701}
3702
6aa8b732
AK		 3703static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3704{
2fb92db1 3705 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3706
3707 *db = (ar >> 14) & 1;
3708 *l = (ar >> 13) & 1;
3709}
3710
89a27f4d 3711static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3712{
89a27f4d
GN		 3713 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3714 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3715}
3716
89a27f4d 3717static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3718{
89a27f4d
GN		 3719 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3720 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3721}
3722
89a27f4d 3723static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3724{
89a27f4d
GN		 3725 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3726 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3727}
3728
89a27f4d 3729static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3730{
89a27f4d
GN		 3731 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3732 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3733}
3734
648dfaa7
MG		 3735static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3736{
3737 struct kvm_segment var;
3738 u32 ar;
3739
3740 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3741 var.dpl = 0x3;
0647f4aa
GN		 3742 if (seg == VCPU_SREG_CS)
3743 var.type = 0x3;
648dfaa7
MG		 3744 ar = vmx_segment_access_rights(&var);
3745
3746 if (var.base != (var.selector << 4))
3747 return false;
89efbed0 3748 if (var.limit != 0xffff)
648dfaa7 3749 return false;
07f42f5f 3750 if (ar != 0xf3)
648dfaa7
MG		 3751 return false;
3752
3753 return true;
3754}
3755
3756static bool code_segment_valid(struct kvm_vcpu *vcpu)
3757{
3758 struct kvm_segment cs;
3759 unsigned int cs_rpl;
3760
3761 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3762 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3763
1872a3f4
AK		 3764 if (cs.unusable)
3765 return false;
648dfaa7
MG		 3766 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3767 return false;
3768 if (!cs.s)
3769 return false;
1872a3f4 3770 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3771 if (cs.dpl > cs_rpl)
3772 return false;
1872a3f4 3773 } else {
648dfaa7
MG		 3774 if (cs.dpl != cs_rpl)
3775 return false;
3776 }
3777 if (!cs.present)
3778 return false;
3779
3780 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3781 return true;
3782}
3783
3784static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3785{
3786 struct kvm_segment ss;
3787 unsigned int ss_rpl;
3788
3789 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3790 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3791
1872a3f4
AK		 3792 if (ss.unusable)
3793 return true;
3794 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3795 return false;
3796 if (!ss.s)
3797 return false;
3798 if (ss.dpl != ss_rpl) /* DPL != RPL */
3799 return false;
3800 if (!ss.present)
3801 return false;
3802
3803 return true;
3804}
3805
3806static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3807{
3808 struct kvm_segment var;
3809 unsigned int rpl;
3810
3811 vmx_get_segment(vcpu, &var, seg);
3812 rpl = var.selector & SELECTOR_RPL_MASK;
3813
1872a3f4
AK		 3814 if (var.unusable)
3815 return true;
648dfaa7
MG		 3816 if (!var.s)
3817 return false;
3818 if (!var.present)
3819 return false;
3820 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3821 if (var.dpl < rpl) /* DPL < RPL */
3822 return false;
3823 }
3824
3825 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3826 * rights flags
3827 */
3828 return true;
3829}
3830
3831static bool tr_valid(struct kvm_vcpu *vcpu)
3832{
3833 struct kvm_segment tr;
3834
3835 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3836
1872a3f4
AK		 3837 if (tr.unusable)
3838 return false;
648dfaa7
MG		 3839 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3840 return false;
1872a3f4 3841 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3842 return false;
3843 if (!tr.present)
3844 return false;
3845
3846 return true;
3847}
3848
3849static bool ldtr_valid(struct kvm_vcpu *vcpu)
3850{
3851 struct kvm_segment ldtr;
3852
3853 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3854
1872a3f4
AK		 3855 if (ldtr.unusable)
3856 return true;
648dfaa7
MG		 3857 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3858 return false;
3859 if (ldtr.type != 2)
3860 return false;
3861 if (!ldtr.present)
3862 return false;
3863
3864 return true;
3865}
3866
3867static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3868{
3869 struct kvm_segment cs, ss;
3870
3871 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3872 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3873
3874 return ((cs.selector & SELECTOR_RPL_MASK) ==
3875 (ss.selector & SELECTOR_RPL_MASK));
3876}
3877
3878/*
3879 * Check if guest state is valid. Returns true if valid, false if
3880 * not.
3881 * We assume that registers are always usable
3882 */
3883static bool guest_state_valid(struct kvm_vcpu *vcpu)
3884{
c5e97c80
GN		 3885 if (enable_unrestricted_guest)
3886 return true;
3887
648dfaa7 3888 /* real mode guest state checks */
f13882d8 3889 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 3890 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3891 return false;
3892 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3893 return false;
3894 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3895 return false;
3896 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3897 return false;
3898 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3899 return false;
3900 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3901 return false;
3902 } else {
3903 /* protected mode guest state checks */
3904 if (!cs_ss_rpl_check(vcpu))
3905 return false;
3906 if (!code_segment_valid(vcpu))
3907 return false;
3908 if (!stack_segment_valid(vcpu))
3909 return false;
3910 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3911 return false;
3912 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3913 return false;
3914 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3915 return false;
3916 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3917 return false;
3918 if (!tr_valid(vcpu))
3919 return false;
3920 if (!ldtr_valid(vcpu))
3921 return false;
3922 }
3923 /* TODO:
3924 * - Add checks on RIP
3925 * - Add checks on RFLAGS
3926 */
3927
3928 return true;
3929}
3930
d77c26fc 3931static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3932{
40dcaa9f 3933 gfn_t fn;
195aefde 3934 u16 data = 0;
1f755a82 3935 int idx, r;
6aa8b732 3936
40dcaa9f 3937 idx = srcu_read_lock(&kvm->srcu);
4918c6ca 3938 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
195aefde
IE		 3939 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3940 if (r < 0)
10589a46 3941 goto out;
195aefde 3942 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3943 r = kvm_write_guest_page(kvm, fn++, &data,
3944 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3945 if (r < 0)
10589a46 3946 goto out;
195aefde
IE		 3947 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3948 if (r < 0)
10589a46 3949 goto out;
195aefde
IE		 3950 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3951 if (r < 0)
10589a46 3952 goto out;
195aefde 3953 data = ~0;
10589a46
MT		 3954 r = kvm_write_guest_page(kvm, fn, &data,
3955 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3956 sizeof(u8));
10589a46 3957out:
40dcaa9f 3958 srcu_read_unlock(&kvm->srcu, idx);
1f755a82 3959 return r;
6aa8b732
AK		 3960}
3961
b7ebfb05
SY		 3962static int init_rmode_identity_map(struct kvm *kvm)
3963{
f51770ed 3964 int i, idx, r = 0;
b7ebfb05
SY		 3965 pfn_t identity_map_pfn;
3966 u32 tmp;
3967
089d034e 3968 if (!enable_ept)
f51770ed 3969 return 0;
a255d479
TC		 3970
3971 /* Protect kvm->arch.ept_identity_pagetable_done. */
3972 mutex_lock(&kvm->slots_lock);
3973
f51770ed 3974 if (likely(kvm->arch.ept_identity_pagetable_done))
a255d479 3975 goto out2;
a255d479 3976
b927a3ce 3977 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
a255d479
TC		 3978
3979 r = alloc_identity_pagetable(kvm);
f51770ed 3980 if (r < 0)
a255d479
TC		 3981 goto out2;
3982
40dcaa9f 3983 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3984 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3985 if (r < 0)
3986 goto out;
3987 /* Set up identity-mapping pagetable for EPT in real mode */
3988 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3989 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3990 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3991 r = kvm_write_guest_page(kvm, identity_map_pfn,
3992 &tmp, i * sizeof(tmp), sizeof(tmp));
3993 if (r < 0)
3994 goto out;
3995 }
3996 kvm->arch.ept_identity_pagetable_done = true;
f51770ed 3997
b7ebfb05 3998out:
40dcaa9f 3999 srcu_read_unlock(&kvm->srcu, idx);
a255d479
TC		 4000
4001out2:
4002 mutex_unlock(&kvm->slots_lock);
f51770ed 4003 return r;
b7ebfb05
SY		 4004}
4005
6aa8b732
AK		 4006static void seg_setup(int seg)
4007{
772e0318 4008 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 4009 unsigned int ar;
6aa8b732
AK		 4010
4011 vmcs_write16(sf->selector, 0);
4012 vmcs_writel(sf->base, 0);
4013 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 4014 ar = 0x93;
4015 if (seg == VCPU_SREG_CS)
4016 ar |= 0x08; /* code segment */
3a624e29
NK		 4017
4018 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 4019}
4020
f78e0e2e
SY		 4021static int alloc_apic_access_page(struct kvm *kvm)
4022{
4484141a 4023 struct page *page;
f78e0e2e
SY		 4024 struct kvm_userspace_memory_region kvm_userspace_mem;
4025 int r = 0;
4026
79fac95e 4027 mutex_lock(&kvm->slots_lock);
c24ae0dc 4028 if (kvm->arch.apic_access_page_done)
f78e0e2e
SY		 4029 goto out;
4030 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
4031 kvm_userspace_mem.flags = 0;
73a6d941 4032 kvm_userspace_mem.guest_phys_addr = APIC_DEFAULT_PHYS_BASE;
f78e0e2e 4033 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 4034 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
f78e0e2e
SY		 4035 if (r)
4036 goto out;
72dc67a6 4037
73a6d941 4038 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4484141a
XG		 4039 if (is_error_page(page)) {
4040 r = -EFAULT;
4041 goto out;
4042 }
4043
c24ae0dc
TC		 4044 /*
4045 * Do not pin the page in memory, so that memory hot-unplug
4046 * is able to migrate it.
4047 */
4048 put_page(page);
4049 kvm->arch.apic_access_page_done = true;
f78e0e2e 4050out:
79fac95e 4051 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 4052 return r;
4053}
4054
b7ebfb05
SY		 4055static int alloc_identity_pagetable(struct kvm *kvm)
4056{
a255d479
TC		 4057 /* Called with kvm->slots_lock held. */
4058
b7ebfb05
SY		 4059 struct kvm_userspace_memory_region kvm_userspace_mem;
4060 int r = 0;
4061
a255d479
TC		 4062 BUG_ON(kvm->arch.ept_identity_pagetable_done);
4063
b7ebfb05
SY		 4064 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
4065 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 4066 kvm_userspace_mem.guest_phys_addr =
4067 kvm->arch.ept_identity_map_addr;
b7ebfb05 4068 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 4069 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
b7ebfb05 4070
b7ebfb05
SY		 4071 return r;
4072}
4073
2384d2b3
SY		 4074static void allocate_vpid(struct vcpu_vmx *vmx)
4075{
4076 int vpid;
4077
4078 vmx->vpid = 0;
919818ab 4079 if (!enable_vpid)
2384d2b3
SY		 4080 return;
4081 spin_lock(&vmx_vpid_lock);
4082 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4083 if (vpid < VMX_NR_VPIDS) {
4084 vmx->vpid = vpid;
4085 __set_bit(vpid, vmx_vpid_bitmap);
4086 }
4087 spin_unlock(&vmx_vpid_lock);
4088}
4089
cdbecfc3
LJ		 4090static void free_vpid(struct vcpu_vmx *vmx)
4091{
4092 if (!enable_vpid)
4093 return;
4094 spin_lock(&vmx_vpid_lock);
4095 if (vmx->vpid != 0)
4096 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
4097 spin_unlock(&vmx_vpid_lock);
4098}
4099
8d14695f
YZ		 4100#define MSR_TYPE_R 1
4101#define MSR_TYPE_W 2
4102static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4103 u32 msr, int type)
25c5f225 4104{
3e7c73e9 4105 int f = sizeof(unsigned long);
25c5f225
SY		 4106
4107 if (!cpu_has_vmx_msr_bitmap())
4108 return;
4109
4110 /*
4111 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4112 * have the write-low and read-high bitmap offsets the wrong way round.
4113 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4114 */
25c5f225 4115 if (msr <= 0x1fff) {
8d14695f
YZ		 4116 if (type & MSR_TYPE_R)
4117 /* read-low */
4118 __clear_bit(msr, msr_bitmap + 0x000 / f);
4119
4120 if (type & MSR_TYPE_W)
4121 /* write-low */
4122 __clear_bit(msr, msr_bitmap + 0x800 / f);
4123
25c5f225
SY		 4124 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4125 msr &= 0x1fff;
8d14695f
YZ		 4126 if (type & MSR_TYPE_R)
4127 /* read-high */
4128 __clear_bit(msr, msr_bitmap + 0x400 / f);
4129
4130 if (type & MSR_TYPE_W)
4131 /* write-high */
4132 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4133
4134 }
4135}
4136
4137static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4138 u32 msr, int type)
4139{
4140 int f = sizeof(unsigned long);
4141
4142 if (!cpu_has_vmx_msr_bitmap())
4143 return;
4144
4145 /*
4146 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4147 * have the write-low and read-high bitmap offsets the wrong way round.
4148 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4149 */
4150 if (msr <= 0x1fff) {
4151 if (type & MSR_TYPE_R)
4152 /* read-low */
4153 __set_bit(msr, msr_bitmap + 0x000 / f);
4154
4155 if (type & MSR_TYPE_W)
4156 /* write-low */
4157 __set_bit(msr, msr_bitmap + 0x800 / f);
4158
4159 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4160 msr &= 0x1fff;
4161 if (type & MSR_TYPE_R)
4162 /* read-high */
4163 __set_bit(msr, msr_bitmap + 0x400 / f);
4164
4165 if (type & MSR_TYPE_W)
4166 /* write-high */
4167 __set_bit(msr, msr_bitmap + 0xc00 / f);
4168
25c5f225 4169 }
25c5f225
SY		 4170}
4171
f2b93280
WV		 4172/*
4173 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4174 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4175 */
4176static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4177 unsigned long *msr_bitmap_nested,
4178 u32 msr, int type)
4179{
4180 int f = sizeof(unsigned long);
4181
4182 if (!cpu_has_vmx_msr_bitmap()) {
4183 WARN_ON(1);
4184 return;
4185 }
4186
4187 /*
4188 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4189 * have the write-low and read-high bitmap offsets the wrong way round.
4190 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4191 */
4192 if (msr <= 0x1fff) {
4193 if (type & MSR_TYPE_R &&
4194 !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4195 /* read-low */
4196 __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4197
4198 if (type & MSR_TYPE_W &&
4199 !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4200 /* write-low */
4201 __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4202
4203 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4204 msr &= 0x1fff;
4205 if (type & MSR_TYPE_R &&
4206 !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4207 /* read-high */
4208 __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4209
4210 if (type & MSR_TYPE_W &&
4211 !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4212 /* write-high */
4213 __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4214
4215 }
4216}
4217
5897297b
AK		 4218static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4219{
4220 if (!longmode_only)
8d14695f
YZ		 4221 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4222 msr, MSR_TYPE_R | MSR_TYPE_W);
4223 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4224 msr, MSR_TYPE_R | MSR_TYPE_W);
4225}
4226
4227static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4228{
4229 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4230 msr, MSR_TYPE_R);
4231 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4232 msr, MSR_TYPE_R);
4233}
4234
4235static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4236{
4237 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4238 msr, MSR_TYPE_R);
4239 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4240 msr, MSR_TYPE_R);
4241}
4242
4243static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4244{
4245 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4246 msr, MSR_TYPE_W);
4247 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4248 msr, MSR_TYPE_W);
5897297b
AK		 4249}
4250
01e439be
YZ		 4251static int vmx_vm_has_apicv(struct kvm *kvm)
4252{
4253 return enable_apicv && irqchip_in_kernel(kvm);
4254}
4255
a20ed54d
YZ		 4256/*
4257 * Send interrupt to vcpu via posted interrupt way.
4258 * 1. If target vcpu is running(non-root mode), send posted interrupt
4259 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4260 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4261 * interrupt from PIR in next vmentry.
4262 */
4263static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4264{
4265 struct vcpu_vmx *vmx = to_vmx(vcpu);
4266 int r;
4267
4268 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4269 return;
4270
4271 r = pi_test_and_set_on(&vmx->pi_desc);
4272 kvm_make_request(KVM_REQ_EVENT, vcpu);
6ffbbbba 4273#ifdef CONFIG_SMP
a20ed54d
YZ		 4274 if (!r && (vcpu->mode == IN_GUEST_MODE))
4275 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4276 POSTED_INTR_VECTOR);
4277 else
6ffbbbba 4278#endif
a20ed54d
YZ		 4279 kvm_vcpu_kick(vcpu);
4280}
4281
4282static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4283{
4284 struct vcpu_vmx *vmx = to_vmx(vcpu);
4285
4286 if (!pi_test_and_clear_on(&vmx->pi_desc))
4287 return;
4288
4289 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4290}
4291
4292static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4293{
4294 return;
4295}
4296
a3a8ff8e
NHE		 4297/*
4298 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4299 * will not change in the lifetime of the guest.
4300 * Note that host-state that does change is set elsewhere. E.g., host-state
4301 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4302 */
a547c6db 4303static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 4304{
4305 u32 low32, high32;
4306 unsigned long tmpl;
4307 struct desc_ptr dt;
d974baa3 4308 unsigned long cr4;
a3a8ff8e 4309
b1a74bf8 4310 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 4311 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4312
d974baa3
AL		 4313 /* Save the most likely value for this task's CR4 in the VMCS. */
4314 cr4 = read_cr4();
4315 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
4316 vmx->host_state.vmcs_host_cr4 = cr4;
4317
a3a8ff8e 4318 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 4319#ifdef CONFIG_X86_64
4320 /*
4321 * Load null selectors, so we can avoid reloading them in
4322 * __vmx_load_host_state(), in case userspace uses the null selectors
4323 * too (the expected case).
4324 */
4325 vmcs_write16(HOST_DS_SELECTOR, 0);
4326 vmcs_write16(HOST_ES_SELECTOR, 0);
4327#else
a3a8ff8e
NHE		 4328 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4329 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 4330#endif
a3a8ff8e
NHE		 4331 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4332 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4333
4334 native_store_idt(&dt);
4335 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 4336 vmx->host_idt_base = dt.address;
a3a8ff8e 4337
83287ea4 4338 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 4339
4340 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4341 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4342 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4343 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4344
4345 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4346 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4347 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4348 }
4349}
4350
bf8179a0
NHE		 4351static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4352{
4353 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4354 if (enable_ept)
4355 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 4356 if (is_guest_mode(&vmx->vcpu))
4357 vmx->vcpu.arch.cr4_guest_owned_bits &=
4358 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 4359 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4360}
4361
01e439be
YZ		 4362static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4363{
4364 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4365
4366 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4367 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4368 return pin_based_exec_ctrl;
4369}
4370
bf8179a0
NHE		 4371static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4372{
4373 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
d16c293e
PB		 4374
4375 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4376 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4377
bf8179a0
NHE		 4378 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4379 exec_control &= ~CPU_BASED_TPR_SHADOW;
4380#ifdef CONFIG_X86_64
4381 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4382 CPU_BASED_CR8_LOAD_EXITING;
4383#endif
4384 }
4385 if (!enable_ept)
4386 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4387 CPU_BASED_CR3_LOAD_EXITING |
4388 CPU_BASED_INVLPG_EXITING;
4389 return exec_control;
4390}
4391
4392static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4393{
4394 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4395 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4396 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4397 if (vmx->vpid == 0)
4398 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4399 if (!enable_ept) {
4400 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4401 enable_unrestricted_guest = 0;
ad756a16
MJ		 4402 /* Enable INVPCID for non-ept guests may cause performance regression. */
4403 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 4404 }
4405 if (!enable_unrestricted_guest)
4406 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4407 if (!ple_gap)
4408 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
c7c9c56c
YZ		 4409 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4410 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4411 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 4412 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
abc4fc58
AG		 4413 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4414 (handle_vmptrld).
4415 We can NOT enable shadow_vmcs here because we don't have yet
4416 a current VMCS12
4417 */
4418 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
843e4330
KH		 4419 /* PML is enabled/disabled in creating/destorying vcpu */
4420 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4421
bf8179a0
NHE		 4422 return exec_control;
4423}
4424
ce88decf
XG		 4425static void ept_set_mmio_spte_mask(void)
4426{
4427 /*
4428 * EPT Misconfigurations can be generated if the value of bits 2:0
4429 * of an EPT paging-structure entry is 110b (write/execute).
885032b9 4430 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
ce88decf
XG		 4431 * spte.
4432 */
885032b9 4433 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
ce88decf
XG		 4434}
4435
f53cd63c 4436#define VMX_XSS_EXIT_BITMAP 0
6aa8b732
AK		 4437/*
4438 * Sets up the vmcs for emulated real mode.
4439 */
8b9cf98c 4440static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 4441{
2e4ce7f5 4442#ifdef CONFIG_X86_64
6aa8b732 4443 unsigned long a;
2e4ce7f5 4444#endif
6aa8b732 4445 int i;
6aa8b732 4446
6aa8b732 4447 /* I/O */
3e7c73e9
AK		 4448 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4449 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 4450
4607c2d7
AG		 4451 if (enable_shadow_vmcs) {
4452 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4453 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4454 }
25c5f225 4455 if (cpu_has_vmx_msr_bitmap())
5897297b 4456 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 4457
6aa8b732
AK		 4458 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4459
6aa8b732 4460 /* Control */
01e439be 4461 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6e5d865c 4462
bf8179a0 4463 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 4464
83ff3b9d 4465 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 4466 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4467 vmx_secondary_exec_control(vmx));
83ff3b9d 4468 }
f78e0e2e 4469
01e439be 4470 if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
c7c9c56c
YZ		 4471 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4472 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4473 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4474 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4475
4476 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be
YZ		 4477
4478 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4479 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 4480 }
4481
4b8d54f9
ZE		 4482 if (ple_gap) {
4483 vmcs_write32(PLE_GAP, ple_gap);
a7653ecd
RK		 4484 vmx->ple_window = ple_window;
4485 vmx->ple_window_dirty = true;
4b8d54f9
ZE		 4486 }
4487
c3707958
XG		 4488 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4489 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4490 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4491
9581d442
AK		 4492 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4493 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4494 vmx_set_constant_host_state(vmx);
05b3e0c2 4495#ifdef CONFIG_X86_64
6aa8b732
AK		 4496 rdmsrl(MSR_FS_BASE, a);
4497 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4498 rdmsrl(MSR_GS_BASE, a);
4499 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4500#else
4501 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4502 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4503#endif
4504
2cc51560
ED		 4505 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4506 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 4507 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 4508 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 4509 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 4510
468d472f 4511 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 4512 u32 msr_low, msr_high;
4513 u64 host_pat;
468d472f
SY		 4514 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4515 host_pat = msr_low | ((u64) msr_high << 32);
4516 /* Write the default value follow host pat */
4517 vmcs_write64(GUEST_IA32_PAT, host_pat);
4518 /* Keep arch.pat sync with GUEST_IA32_PAT */
4519 vmx->vcpu.arch.pat = host_pat;
4520 }
4521
03916db9 4522 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6aa8b732
AK		 4523 u32 index = vmx_msr_index[i];
4524 u32 data_low, data_high;
a2fa3e9f 4525 int j = vmx->nmsrs;
6aa8b732
AK		 4526
4527 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4528 continue;
432bd6cb
AK		 4529 if (wrmsr_safe(index, data_low, data_high) < 0)
4530 continue;
26bb0981
AK		 4531 vmx->guest_msrs[j].index = i;
4532 vmx->guest_msrs[j].data = 0;
d5696725 4533 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 4534 ++vmx->nmsrs;
6aa8b732 4535 }
6aa8b732 4536
2961e876
GN		 4537
4538 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 4539
4540 /* 22.2.1, 20.8.1 */
2961e876 4541 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
1c3d14fe 4542
e00c8cf2 4543 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 4544 set_cr4_guest_host_mask(vmx);
e00c8cf2 4545
f53cd63c
WL		 4546 if (vmx_xsaves_supported())
4547 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4548
e00c8cf2
AK		 4549 return 0;
4550}
4551
57f252f2 4552static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
e00c8cf2
AK		 4553{
4554 struct vcpu_vmx *vmx = to_vmx(vcpu);
58cb628d 4555 struct msr_data apic_base_msr;
e00c8cf2 4556
7ffd92c5 4557 vmx->rmode.vm86_active = 0;
e00c8cf2 4558
3b86cd99
JK		 4559 vmx->soft_vnmi_blocked = 0;
4560
ad312c7c 4561 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 4562 kvm_set_cr8(&vmx->vcpu, 0);
73a6d941 4563 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE;
c5af89b6 4564 if (kvm_vcpu_is_bsp(&vmx->vcpu))
58cb628d
JK		 4565 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4566 apic_base_msr.host_initiated = true;
4567 kvm_set_apic_base(&vmx->vcpu, &apic_base_msr);
e00c8cf2 4568
2fb92db1
AK		 4569 vmx_segment_cache_clear(vmx);
4570
5706be0d 4571 seg_setup(VCPU_SREG_CS);
66450a21 4572 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
04b66839 4573 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
e00c8cf2
AK		 4574
4575 seg_setup(VCPU_SREG_DS);
4576 seg_setup(VCPU_SREG_ES);
4577 seg_setup(VCPU_SREG_FS);
4578 seg_setup(VCPU_SREG_GS);
4579 seg_setup(VCPU_SREG_SS);
4580
4581 vmcs_write16(GUEST_TR_SELECTOR, 0);
4582 vmcs_writel(GUEST_TR_BASE, 0);
4583 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4584 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4585
4586 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4587 vmcs_writel(GUEST_LDTR_BASE, 0);
4588 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4589 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4590
4591 vmcs_write32(GUEST_SYSENTER_CS, 0);
4592 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4593 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4594
4595 vmcs_writel(GUEST_RFLAGS, 0x02);
66450a21 4596 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4597
e00c8cf2
AK		 4598 vmcs_writel(GUEST_GDTR_BASE, 0);
4599 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4600
4601 vmcs_writel(GUEST_IDTR_BASE, 0);
4602 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4603
443381a8 4604 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 4605 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4606 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4607
e00c8cf2
AK		 4608 /* Special registers */
4609 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4610
4611 setup_msrs(vmx);
4612
6aa8b732
AK		 4613 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4614
f78e0e2e
SY		 4615 if (cpu_has_vmx_tpr_shadow()) {
4616 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4617 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4618 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 4619 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 4620 vmcs_write32(TPR_THRESHOLD, 0);
4621 }
4622
a73896cb 4623 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6aa8b732 4624
01e439be
YZ		 4625 if (vmx_vm_has_apicv(vcpu->kvm))
4626 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4627
2384d2b3
SY		 4628 if (vmx->vpid != 0)
4629 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4630
fa40052c 4631 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 4632 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 4633 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 4634 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 4635 vmx_fpu_activate(&vmx->vcpu);
4636 update_exception_bitmap(&vmx->vcpu);
6aa8b732 4637
b9d762fa 4638 vpid_sync_context(vmx);
6aa8b732
AK		 4639}
4640
b6f1250e
NHE		 4641/*
4642 * In nested virtualization, check if L1 asked to exit on external interrupts.
4643 * For most existing hypervisors, this will always return true.
4644 */
4645static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4646{
4647 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4648 PIN_BASED_EXT_INTR_MASK;
4649}
4650
77b0f5d6
BD		 4651/*
4652 * In nested virtualization, check if L1 has set
4653 * VM_EXIT_ACK_INTR_ON_EXIT
4654 */
4655static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
4656{
4657 return get_vmcs12(vcpu)->vm_exit_controls &
4658 VM_EXIT_ACK_INTR_ON_EXIT;
4659}
4660
ea8ceb83
JK		 4661static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4662{
4663 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4664 PIN_BASED_NMI_EXITING;
4665}
4666
c9a7953f 4667static void enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4668{
4669 u32 cpu_based_vm_exec_control;
730dca42 4670
3b86cd99
JK		 4671 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4672 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4673 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4674}
4675
c9a7953f 4676static void enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4677{
4678 u32 cpu_based_vm_exec_control;
4679
c9a7953f
JK		 4680 if (!cpu_has_virtual_nmis() ||
4681 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4682 enable_irq_window(vcpu);
4683 return;
4684 }
3b86cd99
JK		 4685
4686 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4687 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4688 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4689}
4690
66fd3f7f 4691static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4692{
9c8cba37 4693 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4694 uint32_t intr;
4695 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4696
229456fc 4697 trace_kvm_inj_virq(irq);
2714d1d3 4698
fa89a817 4699 ++vcpu->stat.irq_injections;
7ffd92c5 4700 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4701 int inc_eip = 0;
4702 if (vcpu->arch.interrupt.soft)
4703 inc_eip = vcpu->arch.event_exit_inst_len;
4704 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4705 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4706 return;
4707 }
66fd3f7f
GN		 4708 intr = irq | INTR_INFO_VALID_MASK;
4709 if (vcpu->arch.interrupt.soft) {
4710 intr |= INTR_TYPE_SOFT_INTR;
4711 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4712 vmx->vcpu.arch.event_exit_inst_len);
4713 } else
4714 intr |= INTR_TYPE_EXT_INTR;
4715 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4716}
4717
f08864b4
SY		 4718static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4719{
66a5a347
JK		 4720 struct vcpu_vmx *vmx = to_vmx(vcpu);
4721
0b6ac343
NHE		 4722 if (is_guest_mode(vcpu))
4723 return;
4724
3b86cd99
JK		 4725 if (!cpu_has_virtual_nmis()) {
4726 /*
4727 * Tracking the NMI-blocked state in software is built upon
4728 * finding the next open IRQ window. This, in turn, depends on
4729 * well-behaving guests: They have to keep IRQs disabled at
4730 * least as long as the NMI handler runs. Otherwise we may
4731 * cause NMI nesting, maybe breaking the guest. But as this is
4732 * highly unlikely, we can live with the residual risk.
4733 */
4734 vmx->soft_vnmi_blocked = 1;
4735 vmx->vnmi_blocked_time = 0;
4736 }
4737
487b391d 4738 ++vcpu->stat.nmi_injections;
9d58b931 4739 vmx->nmi_known_unmasked = false;
7ffd92c5 4740 if (vmx->rmode.vm86_active) {
71f9833b 4741 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4742 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4743 return;
4744 }
f08864b4
SY		 4745 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4746 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4747}
4748
3cfc3092
JK		 4749static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4750{
4751 if (!cpu_has_virtual_nmis())
4752 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4753 if (to_vmx(vcpu)->nmi_known_unmasked)
4754 return false;
c332c83a 4755 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4756}
4757
4758static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4759{
4760 struct vcpu_vmx *vmx = to_vmx(vcpu);
4761
4762 if (!cpu_has_virtual_nmis()) {
4763 if (vmx->soft_vnmi_blocked != masked) {
4764 vmx->soft_vnmi_blocked = masked;
4765 vmx->vnmi_blocked_time = 0;
4766 }
4767 } else {
9d58b931 4768 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4769 if (masked)
4770 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4771 GUEST_INTR_STATE_NMI);
4772 else
4773 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4774 GUEST_INTR_STATE_NMI);
4775 }
4776}
4777
2505dc9f
JK		 4778static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4779{
b6b8a145
JK		 4780 if (to_vmx(vcpu)->nested.nested_run_pending)
4781 return 0;
ea8ceb83 4782
2505dc9f
JK		 4783 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4784 return 0;
4785
4786 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4787 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4788 | GUEST_INTR_STATE_NMI));
4789}
4790
78646121
GN		 4791static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4792{
b6b8a145
JK		 4793 return (!to_vmx(vcpu)->nested.nested_run_pending &&
4794 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
c4282df9
GN		 4795 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4796 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4797}
4798
cbc94022
IE		 4799static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4800{
4801 int ret;
4802 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4803 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4804 .guest_phys_addr = addr,
4805 .memory_size = PAGE_SIZE * 3,
4806 .flags = 0,
4807 };
4808
47ae31e2 4809 ret = kvm_set_memory_region(kvm, &tss_mem);
cbc94022
IE		 4810 if (ret)
4811 return ret;
bfc6d222 4812 kvm->arch.tss_addr = addr;
1f755a82 4813 return init_rmode_tss(kvm);
cbc94022
IE		 4814}
4815
0ca1b4f4 4816static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4817{
77ab6db0 4818 switch (vec) {
77ab6db0 4819 case BP_VECTOR:
c573cd22
JK		 4820 /*
4821 * Update instruction length as we may reinject the exception
4822 * from user space while in guest debugging mode.
4823 */
4824 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4825 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4826 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4827 return false;
4828 /* fall through */
4829 case DB_VECTOR:
4830 if (vcpu->guest_debug &
4831 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4832 return false;
d0bfb940
JK		 4833 /* fall through */
4834 case DE_VECTOR:
77ab6db0
JK		 4835 case OF_VECTOR:
4836 case BR_VECTOR:
4837 case UD_VECTOR:
4838 case DF_VECTOR:
4839 case SS_VECTOR:
4840 case GP_VECTOR:
4841 case MF_VECTOR:
0ca1b4f4
GN		 4842 return true;
4843 break;
77ab6db0 4844 }
0ca1b4f4
GN		 4845 return false;
4846}
4847
4848static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4849 int vec, u32 err_code)
4850{
4851 /*
4852 * Instruction with address size override prefix opcode 0x67
4853 * Cause the #SS fault with 0 error code in VM86 mode.
4854 */
4855 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4856 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4857 if (vcpu->arch.halt_request) {
4858 vcpu->arch.halt_request = 0;
4859 return kvm_emulate_halt(vcpu);
4860 }
4861 return 1;
4862 }
4863 return 0;
4864 }
4865
4866 /*
4867 * Forward all other exceptions that are valid in real mode.
4868 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4869 * the required debugging infrastructure rework.
4870 */
4871 kvm_queue_exception(vcpu, vec);
4872 return 1;
6aa8b732
AK		 4873}
4874
a0861c02
AK		 4875/*
4876 * Trigger machine check on the host. We assume all the MSRs are already set up
4877 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4878 * We pass a fake environment to the machine check handler because we want
4879 * the guest to be always treated like user space, no matter what context
4880 * it used internally.
4881 */
4882static void kvm_machine_check(void)
4883{
4884#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4885 struct pt_regs regs = {
4886 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4887 .flags = X86_EFLAGS_IF,
4888 };
4889
4890 do_machine_check(&regs, 0);
4891#endif
4892}
4893
851ba692 4894static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4895{
4896 /* already handled by vcpu_run */
4897 return 1;
4898}
4899
851ba692 4900static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4901{
1155f76a 4902 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4903 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4904 u32 intr_info, ex_no, error_code;
42dbaa5a 4905 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4906 u32 vect_info;
4907 enum emulation_result er;
4908
1155f76a 4909 vect_info = vmx->idt_vectoring_info;
88786475 4910 intr_info = vmx->exit_intr_info;
6aa8b732 4911
a0861c02 4912 if (is_machine_check(intr_info))
851ba692 4913 return handle_machine_check(vcpu);
a0861c02 4914
e4a41889 4915 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4916 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4917
4918 if (is_no_device(intr_info)) {
5fd86fcf 4919 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4920 return 1;
4921 }
4922
7aa81cc0 4923 if (is_invalid_opcode(intr_info)) {
51d8b661 4924 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4925 if (er != EMULATE_DONE)
7ee5d940 4926 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4927 return 1;
4928 }
4929
6aa8b732 4930 error_code = 0;
2e11384c 4931 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4932 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 4933
4934 /*
4935 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4936 * MMIO, it is better to report an internal error.
4937 * See the comments in vmx_handle_exit.
4938 */
4939 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4940 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4941 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4942 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4943 vcpu->run->internal.ndata = 2;
4944 vcpu->run->internal.data[0] = vect_info;
4945 vcpu->run->internal.data[1] = intr_info;
4946 return 0;
4947 }
4948
6aa8b732 4949 if (is_page_fault(intr_info)) {
1439442c 4950 /* EPT won't cause page fault directly */
cf3ace79 4951 BUG_ON(enable_ept);
6aa8b732 4952 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4953 trace_kvm_page_fault(cr2, error_code);
4954
3298b75c 4955 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4956 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4957 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4958 }
4959
d0bfb940 4960 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 4961
4962 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4963 return handle_rmode_exception(vcpu, ex_no, error_code);
4964
42dbaa5a
JK		 4965 switch (ex_no) {
4966 case DB_VECTOR:
4967 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4968 if (!(vcpu->guest_debug &
4969 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
8246bf52 4970 vcpu->arch.dr6 &= ~15;
6f43ed01 4971 vcpu->arch.dr6 |= dr6 | DR6_RTM;
fd2a445a
HD		 4972 if (!(dr6 & ~DR6_RESERVED)) /* icebp */
4973 skip_emulated_instruction(vcpu);
4974
42dbaa5a
JK		 4975 kvm_queue_exception(vcpu, DB_VECTOR);
4976 return 1;
4977 }
4978 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4979 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4980 /* fall through */
4981 case BP_VECTOR:
c573cd22
JK		 4982 /*
4983 * Update instruction length as we may reinject #BP from
4984 * user space while in guest debugging mode. Reading it for
4985 * #DB as well causes no harm, it is not used in that case.
4986 */
4987 vmx->vcpu.arch.event_exit_inst_len =
4988 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4989 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4990 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4991 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4992 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4993 break;
4994 default:
d0bfb940
JK		 4995 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4996 kvm_run->ex.exception = ex_no;
4997 kvm_run->ex.error_code = error_code;
42dbaa5a 4998 break;
6aa8b732 4999 }
6aa8b732
AK		 5000 return 0;
5001}
5002
851ba692 5003static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 5004{
1165f5fe 5005 ++vcpu->stat.irq_exits;
6aa8b732
AK		 5006 return 1;
5007}
5008
851ba692 5009static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 5010{
851ba692 5011 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 5012 return 0;
5013}
6aa8b732 5014
851ba692 5015static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 5016{
bfdaab09 5017 unsigned long exit_qualification;
34c33d16 5018 int size, in, string;
039576c0 5019 unsigned port;
6aa8b732 5020
bfdaab09 5021 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 5022 string = (exit_qualification & 16) != 0;
cf8f70bf 5023 in = (exit_qualification & 8) != 0;
e70669ab 5024
cf8f70bf 5025 ++vcpu->stat.io_exits;
e70669ab 5026
cf8f70bf 5027 if (string || in)
51d8b661 5028 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 5029
cf8f70bf
GN		 5030 port = exit_qualification >> 16;
5031 size = (exit_qualification & 7) + 1;
e93f36bc 5032 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 5033
5034 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 5035}
5036
102d8325
IM		 5037static void
5038vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5039{
5040 /*
5041 * Patch in the VMCALL instruction:
5042 */
5043 hypercall[0] = 0x0f;
5044 hypercall[1] = 0x01;
5045 hypercall[2] = 0xc1;
102d8325
IM		 5046}
5047
92fbc7b1
JK		 5048static bool nested_cr0_valid(struct vmcs12 *vmcs12, unsigned long val)
5049{
5050 unsigned long always_on = VMXON_CR0_ALWAYSON;
5051
5052 if (nested_vmx_secondary_ctls_high &
5053 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5054 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5055 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5056 return (val & always_on) == always_on;
5057}
5058
0fa06071 5059/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 5060static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5061{
eeadf9e7 5062 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 5063 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5064 unsigned long orig_val = val;
5065
eeadf9e7
NHE		 5066 /*
5067 * We get here when L2 changed cr0 in a way that did not change
5068 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 5069 * but did change L0 shadowed bits. So we first calculate the
5070 * effective cr0 value that L1 would like to write into the
5071 * hardware. It consists of the L2-owned bits from the new
5072 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 5073 */
1a0d74e6
JK		 5074 val = (val & ~vmcs12->cr0_guest_host_mask) |
5075 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5076
92fbc7b1 5077 if (!nested_cr0_valid(vmcs12, val))
eeadf9e7 5078 return 1;
1a0d74e6
JK		 5079
5080 if (kvm_set_cr0(vcpu, val))
5081 return 1;
5082 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 5083 return 0;
1a0d74e6
JK		 5084 } else {
5085 if (to_vmx(vcpu)->nested.vmxon &&
5086 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5087 return 1;
eeadf9e7 5088 return kvm_set_cr0(vcpu, val);
1a0d74e6 5089 }
eeadf9e7
NHE		 5090}
5091
5092static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5093{
5094 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 5095 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5096 unsigned long orig_val = val;
5097
5098 /* analogously to handle_set_cr0 */
5099 val = (val & ~vmcs12->cr4_guest_host_mask) |
5100 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5101 if (kvm_set_cr4(vcpu, val))
eeadf9e7 5102 return 1;
1a0d74e6 5103 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 5104 return 0;
5105 } else
5106 return kvm_set_cr4(vcpu, val);
5107}
5108
5109/* called to set cr0 as approriate for clts instruction exit. */
5110static void handle_clts(struct kvm_vcpu *vcpu)
5111{
5112 if (is_guest_mode(vcpu)) {
5113 /*
5114 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5115 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5116 * just pretend it's off (also in arch.cr0 for fpu_activate).
5117 */
5118 vmcs_writel(CR0_READ_SHADOW,
5119 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5120 vcpu->arch.cr0 &= ~X86_CR0_TS;
5121 } else
5122 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5123}
5124
851ba692 5125static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 5126{
229456fc 5127 unsigned long exit_qualification, val;
6aa8b732
AK		 5128 int cr;
5129 int reg;
49a9b07e 5130 int err;
6aa8b732 5131
bfdaab09 5132 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 5133 cr = exit_qualification & 15;
5134 reg = (exit_qualification >> 8) & 15;
5135 switch ((exit_qualification >> 4) & 3) {
5136 case 0: /* mov to cr */
1e32c079 5137 val = kvm_register_readl(vcpu, reg);
229456fc 5138 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 5139 switch (cr) {
5140 case 0:
eeadf9e7 5141 err = handle_set_cr0(vcpu, val);
db8fcefa 5142 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5143 return 1;
5144 case 3:
2390218b 5145 err = kvm_set_cr3(vcpu, val);
db8fcefa 5146 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5147 return 1;
5148 case 4:
eeadf9e7 5149 err = handle_set_cr4(vcpu, val);
db8fcefa 5150 kvm_complete_insn_gp(vcpu, err);
6aa8b732 5151 return 1;
0a5fff19
GN		 5152 case 8: {
5153 u8 cr8_prev = kvm_get_cr8(vcpu);
1e32c079 5154 u8 cr8 = (u8)val;
eea1cff9 5155 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 5156 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 5157 if (irqchip_in_kernel(vcpu->kvm))
5158 return 1;
5159 if (cr8_prev <= cr8)
5160 return 1;
851ba692 5161 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 5162 return 0;
5163 }
4b8073e4 5164 }
6aa8b732 5165 break;
25c4c276 5166 case 2: /* clts */
eeadf9e7 5167 handle_clts(vcpu);
4d4ec087 5168 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 5169 skip_emulated_instruction(vcpu);
6b52d186 5170 vmx_fpu_activate(vcpu);
25c4c276 5171 return 1;
6aa8b732
AK		 5172 case 1: /*mov from cr*/
5173 switch (cr) {
5174 case 3:
9f8fe504
AK		 5175 val = kvm_read_cr3(vcpu);
5176 kvm_register_write(vcpu, reg, val);
5177 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5178 skip_emulated_instruction(vcpu);
5179 return 1;
5180 case 8:
229456fc
MT		 5181 val = kvm_get_cr8(vcpu);
5182 kvm_register_write(vcpu, reg, val);
5183 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5184 skip_emulated_instruction(vcpu);
5185 return 1;
5186 }
5187 break;
5188 case 3: /* lmsw */
a1f83a74 5189 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 5190 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 5191 kvm_lmsw(vcpu, val);
6aa8b732
AK		 5192
5193 skip_emulated_instruction(vcpu);
5194 return 1;
5195 default:
5196 break;
5197 }
851ba692 5198 vcpu->run->exit_reason = 0;
a737f256 5199 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 5200 (int)(exit_qualification >> 4) & 3, cr);
5201 return 0;
5202}
5203
851ba692 5204static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 5205{
bfdaab09 5206 unsigned long exit_qualification;
16f8a6f9
NA		 5207 int dr, dr7, reg;
5208
5209 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5210 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5211
5212 /* First, if DR does not exist, trigger UD */
5213 if (!kvm_require_dr(vcpu, dr))
5214 return 1;
6aa8b732 5215
f2483415 5216 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 5217 if (!kvm_require_cpl(vcpu, 0))
5218 return 1;
16f8a6f9
NA		 5219 dr7 = vmcs_readl(GUEST_DR7);
5220 if (dr7 & DR7_GD) {
42dbaa5a
JK		 5221 /*
5222 * As the vm-exit takes precedence over the debug trap, we
5223 * need to emulate the latter, either for the host or the
5224 * guest debugging itself.
5225 */
5226 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692 5227 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
16f8a6f9 5228 vcpu->run->debug.arch.dr7 = dr7;
82b32774 5229 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
851ba692
AK		 5230 vcpu->run->debug.arch.exception = DB_VECTOR;
5231 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 5232 return 0;
5233 } else {
7305eb5d 5234 vcpu->arch.dr6 &= ~15;
6f43ed01 5235 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
42dbaa5a
JK		 5236 kvm_queue_exception(vcpu, DB_VECTOR);
5237 return 1;
5238 }
5239 }
5240
81908bf4
PB		 5241 if (vcpu->guest_debug == 0) {
5242 u32 cpu_based_vm_exec_control;
5243
5244 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5245 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5246 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5247
5248 /*
5249 * No more DR vmexits; force a reload of the debug registers
5250 * and reenter on this instruction. The next vmexit will
5251 * retrieve the full state of the debug registers.
5252 */
5253 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5254 return 1;
5255 }
5256
42dbaa5a
JK		 5257 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5258 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079 5259 unsigned long val;
4c4d563b
JK		 5260
5261 if (kvm_get_dr(vcpu, dr, &val))
5262 return 1;
5263 kvm_register_write(vcpu, reg, val);
020df079 5264 } else
5777392e 5265 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
4c4d563b
JK		 5266 return 1;
5267
6aa8b732
AK		 5268 skip_emulated_instruction(vcpu);
5269 return 1;
5270}
5271
73aaf249
JK		 5272static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5273{
5274 return vcpu->arch.dr6;
5275}
5276
5277static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5278{
5279}
5280
81908bf4
PB		 5281static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5282{
5283 u32 cpu_based_vm_exec_control;
5284
5285 get_debugreg(vcpu->arch.db[0], 0);
5286 get_debugreg(vcpu->arch.db[1], 1);
5287 get_debugreg(vcpu->arch.db[2], 2);
5288 get_debugreg(vcpu->arch.db[3], 3);
5289 get_debugreg(vcpu->arch.dr6, 6);
5290 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5291
5292 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5293
5294 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5295 cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5296 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5297}
5298
020df079
GN		 5299static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5300{
5301 vmcs_writel(GUEST_DR7, val);
5302}
5303
851ba692 5304static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 5305{
06465c5a
AK		 5306 kvm_emulate_cpuid(vcpu);
5307 return 1;
6aa8b732
AK		 5308}
5309
851ba692 5310static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 5311{
ad312c7c 5312 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 5313 u64 data;
5314
5315 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 5316 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 5317 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5318 return 1;
5319 }
5320
229456fc 5321 trace_kvm_msr_read(ecx, data);
2714d1d3 5322
6aa8b732 5323 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 5324 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5325 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 5326 skip_emulated_instruction(vcpu);
5327 return 1;
5328}
5329
851ba692 5330static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 5331{
8fe8ab46 5332 struct msr_data msr;
ad312c7c
ZX		 5333 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5334 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5335 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 5336
8fe8ab46
WA		 5337 msr.data = data;
5338 msr.index = ecx;
5339 msr.host_initiated = false;
854e8bb1 5340 if (kvm_set_msr(vcpu, &msr) != 0) {
59200273 5341 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 5342 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5343 return 1;
5344 }
5345
59200273 5346 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 5347 skip_emulated_instruction(vcpu);
5348 return 1;
5349}
5350
851ba692 5351static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 5352{
3842d135 5353 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 5354 return 1;
5355}
5356
851ba692 5357static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 5358{
85f455f7
ED		 5359 u32 cpu_based_vm_exec_control;
5360
5361 /* clear pending irq */
5362 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5363 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5364 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 5365
3842d135
AK		 5366 kvm_make_request(KVM_REQ_EVENT, vcpu);
5367
a26bf12a 5368 ++vcpu->stat.irq_window_exits;
2714d1d3 5369
c1150d8c
DL		 5370 /*
5371 * If the user space waits to inject interrupts, exit as soon as
5372 * possible
5373 */
8061823a 5374 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 5375 vcpu->run->request_interrupt_window &&
8061823a 5376 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 5377 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 5378 return 0;
5379 }
6aa8b732
AK		 5380 return 1;
5381}
5382
851ba692 5383static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 5384{
5385 skip_emulated_instruction(vcpu);
d3bef15f 5386 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 5387}
5388
851ba692 5389static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 5390{
510043da 5391 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 5392 kvm_emulate_hypercall(vcpu);
5393 return 1;
c21415e8
IM		 5394}
5395
ec25d5e6
GN		 5396static int handle_invd(struct kvm_vcpu *vcpu)
5397{
51d8b661 5398 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 5399}
5400
851ba692 5401static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 5402{
f9c617f6 5403 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 5404
5405 kvm_mmu_invlpg(vcpu, exit_qualification);
5406 skip_emulated_instruction(vcpu);
5407 return 1;
5408}
5409
fee84b07
AK		 5410static int handle_rdpmc(struct kvm_vcpu *vcpu)
5411{
5412 int err;
5413
5414 err = kvm_rdpmc(vcpu);
5415 kvm_complete_insn_gp(vcpu, err);
5416
5417 return 1;
5418}
5419
851ba692 5420static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 5421{
5422 skip_emulated_instruction(vcpu);
f5f48ee1 5423 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 5424 return 1;
5425}
5426
2acf923e
DC		 5427static int handle_xsetbv(struct kvm_vcpu *vcpu)
5428{
5429 u64 new_bv = kvm_read_edx_eax(vcpu);
5430 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5431
5432 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5433 skip_emulated_instruction(vcpu);
5434 return 1;
5435}
5436
f53cd63c
WL		 5437static int handle_xsaves(struct kvm_vcpu *vcpu)
5438{
5439 skip_emulated_instruction(vcpu);
5440 WARN(1, "this should never happen\n");
5441 return 1;
5442}
5443
5444static int handle_xrstors(struct kvm_vcpu *vcpu)
5445{
5446 skip_emulated_instruction(vcpu);
5447 WARN(1, "this should never happen\n");
5448 return 1;
5449}
5450
851ba692 5451static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 5452{
58fbbf26
KT		 5453 if (likely(fasteoi)) {
5454 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5455 int access_type, offset;
5456
5457 access_type = exit_qualification & APIC_ACCESS_TYPE;
5458 offset = exit_qualification & APIC_ACCESS_OFFSET;
5459 /*
5460 * Sane guest uses MOV to write EOI, with written value
5461 * not cared. So make a short-circuit here by avoiding
5462 * heavy instruction emulation.
5463 */
5464 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5465 (offset == APIC_EOI)) {
5466 kvm_lapic_set_eoi(vcpu);
5467 skip_emulated_instruction(vcpu);
5468 return 1;
5469 }
5470 }
51d8b661 5471 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 5472}
5473
c7c9c56c
YZ		 5474static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5475{
5476 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5477 int vector = exit_qualification & 0xff;
5478
5479 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5480 kvm_apic_set_eoi_accelerated(vcpu, vector);
5481 return 1;
5482}
5483
83d4c286
YZ		 5484static int handle_apic_write(struct kvm_vcpu *vcpu)
5485{
5486 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5487 u32 offset = exit_qualification & 0xfff;
5488
5489 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5490 kvm_apic_write_nodecode(vcpu, offset);
5491 return 1;
5492}
5493
851ba692 5494static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 5495{
60637aac 5496 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 5497 unsigned long exit_qualification;
e269fb21
JK		 5498 bool has_error_code = false;
5499 u32 error_code = 0;
37817f29 5500 u16 tss_selector;
7f3d35fd 5501 int reason, type, idt_v, idt_index;
64a7ec06
GN		 5502
5503 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 5504 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 5505 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 5506
5507 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5508
5509 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 5510 if (reason == TASK_SWITCH_GATE && idt_v) {
5511 switch (type) {
5512 case INTR_TYPE_NMI_INTR:
5513 vcpu->arch.nmi_injected = false;
654f06fc 5514 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5515 break;
5516 case INTR_TYPE_EXT_INTR:
66fd3f7f 5517 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5518 kvm_clear_interrupt_queue(vcpu);
5519 break;
5520 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5521 if (vmx->idt_vectoring_info &
5522 VECTORING_INFO_DELIVER_CODE_MASK) {
5523 has_error_code = true;
5524 error_code =
5525 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5526 }
5527 /* fall through */
64a7ec06
GN		 5528 case INTR_TYPE_SOFT_EXCEPTION:
5529 kvm_clear_exception_queue(vcpu);
5530 break;
5531 default:
5532 break;
5533 }
60637aac 5534 }
37817f29
IE		 5535 tss_selector = exit_qualification;
5536
64a7ec06
GN		 5537 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5538 type != INTR_TYPE_EXT_INTR &&
5539 type != INTR_TYPE_NMI_INTR))
5540 skip_emulated_instruction(vcpu);
5541
7f3d35fd
KW		 5542 if (kvm_task_switch(vcpu, tss_selector,
5543 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5544 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 5545 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5546 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5547 vcpu->run->internal.ndata = 0;
42dbaa5a 5548 return 0;
acb54517 5549 }
42dbaa5a
JK		 5550
5551 /* clear all local breakpoint enable flags */
0e8a0996 5552 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~0x155);
42dbaa5a
JK		 5553
5554 /*
5555 * TODO: What about debug traps on tss switch?
5556 * Are we supposed to inject them and update dr6?
5557 */
5558
5559 return 1;
37817f29
IE		 5560}
5561
851ba692 5562static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5563{
f9c617f6 5564 unsigned long exit_qualification;
1439442c 5565 gpa_t gpa;
4f5982a5 5566 u32 error_code;
1439442c 5567 int gla_validity;
1439442c 5568
f9c617f6 5569 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5570
1439442c
SY		 5571 gla_validity = (exit_qualification >> 7) & 0x3;
5572 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5573 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5574 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5575 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 5576 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 5577 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5578 (long unsigned int)exit_qualification);
851ba692
AK		 5579 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5580 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 5581 return 0;
1439442c
SY		 5582 }
5583
0be9c7a8
GN		 5584 /*
5585 * EPT violation happened while executing iret from NMI,
5586 * "blocked by NMI" bit has to be set before next VM entry.
5587 * There are errata that may cause this bit to not be set:
5588 * AAK134, BY25.
5589 */
bcd1c294
GN		 5590 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5591 cpu_has_virtual_nmis() &&
5592 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
0be9c7a8
GN		 5593 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5594
1439442c 5595 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5596 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 5597
5598 /* It is a write fault? */
81ed33e4 5599 error_code = exit_qualification & PFERR_WRITE_MASK;
25d92081 5600 /* It is a fetch fault? */
81ed33e4 5601 error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK;
4f5982a5 5602 /* ept page table is present? */
81ed33e4 5603 error_code |= (exit_qualification >> 3) & PFERR_PRESENT_MASK;
4f5982a5 5604
25d92081
YZ		 5605 vcpu->arch.exit_qualification = exit_qualification;
5606
4f5982a5 5607 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5608}
5609
68f89400
MT		 5610static u64 ept_rsvd_mask(u64 spte, int level)
5611{
5612 int i;
5613 u64 mask = 0;
5614
5615 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5616 mask |= (1ULL << i);
5617
a32e8459 5618 if (level == 4)
68f89400
MT		 5619 /* bits 7:3 reserved */
5620 mask |= 0xf8;
a32e8459
WL		 5621 else if (spte & (1ULL << 7))
5622 /*
5623 * 1GB/2MB page, bits 29:12 or 20:12 reserved respectively,
5624 * level == 1 if the hypervisor is using the ignored bit 7.
5625 */
5626 mask |= (PAGE_SIZE << ((level - 1) * 9)) - PAGE_SIZE;
5627 else if (level > 1)
5628 /* bits 6:3 reserved */
5629 mask |= 0x78;
68f89400
MT		 5630
5631 return mask;
5632}
5633
5634static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5635 int level)
5636{
5637 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5638
5639 /* 010b (write-only) */
5640 WARN_ON((spte & 0x7) == 0x2);
5641
5642 /* 110b (write/execute) */
5643 WARN_ON((spte & 0x7) == 0x6);
5644
5645 /* 100b (execute-only) and value not supported by logical processor */
5646 if (!cpu_has_vmx_ept_execute_only())
5647 WARN_ON((spte & 0x7) == 0x4);
5648
5649 /* not 000b */
5650 if ((spte & 0x7)) {
5651 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5652
5653 if (rsvd_bits != 0) {
5654 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5655 __func__, rsvd_bits);
5656 WARN_ON(1);
5657 }
5658
a32e8459
WL		 5659 /* bits 5:3 are _not_ reserved for large page or leaf page */
5660 if ((rsvd_bits & 0x38) == 0) {
68f89400
MT		 5661 u64 ept_mem_type = (spte & 0x38) >> 3;
5662
5663 if (ept_mem_type == 2 || ept_mem_type == 3 ||
5664 ept_mem_type == 7) {
5665 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5666 __func__, ept_mem_type);
5667 WARN_ON(1);
5668 }
5669 }
5670 }
5671}
5672
851ba692 5673static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 5674{
5675 u64 sptes[4];
ce88decf 5676 int nr_sptes, i, ret;
68f89400
MT		 5677 gpa_t gpa;
5678
5679 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
68c3b4d1
MT		 5680 if (!kvm_io_bus_write(vcpu->kvm, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5681 skip_emulated_instruction(vcpu);
5682 return 1;
5683 }
68f89400 5684
ce88decf 5685 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
b37fbea6 5686 if (likely(ret == RET_MMIO_PF_EMULATE))
ce88decf
XG		 5687 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5688 EMULATE_DONE;
f8f55942
XG		 5689
5690 if (unlikely(ret == RET_MMIO_PF_INVALID))
5691 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5692
b37fbea6 5693 if (unlikely(ret == RET_MMIO_PF_RETRY))
ce88decf
XG		 5694 return 1;
5695
5696 /* It is the real ept misconfig */
68f89400
MT		 5697 printk(KERN_ERR "EPT: Misconfiguration.\n");
5698 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5699
5700 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5701
5702 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5703 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5704
851ba692
AK		 5705 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5706 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 5707
5708 return 0;
5709}
5710
851ba692 5711static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 5712{
5713 u32 cpu_based_vm_exec_control;
5714
5715 /* clear pending NMI */
5716 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5717 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5718 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5719 ++vcpu->stat.nmi_window_exits;
3842d135 5720 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5721
5722 return 1;
5723}
5724
80ced186 5725static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5726{
8b3079a5
AK		 5727 struct vcpu_vmx *vmx = to_vmx(vcpu);
5728 enum emulation_result err = EMULATE_DONE;
80ced186 5729 int ret = 1;
49e9d557
AK		 5730 u32 cpu_exec_ctrl;
5731 bool intr_window_requested;
b8405c18 5732 unsigned count = 130;
49e9d557
AK		 5733
5734 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5735 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5736
98eb2f8b 5737 while (vmx->emulation_required && count-- != 0) {
bdea48e3 5738 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5739 return handle_interrupt_window(&vmx->vcpu);
5740
de87dcdd
AK		 5741 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5742 return 1;
5743
991eebf9 5744 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
ea953ef0 5745
ac0a48c3 5746 if (err == EMULATE_USER_EXIT) {
94452b9e 5747 ++vcpu->stat.mmio_exits;
80ced186
MG		 5748 ret = 0;
5749 goto out;
5750 }
1d5a4d9b 5751
de5f70e0
AK		 5752 if (err != EMULATE_DONE) {
5753 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5754 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5755 vcpu->run->internal.ndata = 0;
6d77dbfc 5756 return 0;
de5f70e0 5757 }
ea953ef0 5758
8d76c49e
GN		 5759 if (vcpu->arch.halt_request) {
5760 vcpu->arch.halt_request = 0;
5761 ret = kvm_emulate_halt(vcpu);
5762 goto out;
5763 }
5764
ea953ef0 5765 if (signal_pending(current))
80ced186 5766 goto out;
ea953ef0
MG		 5767 if (need_resched())
5768 schedule();
5769 }
5770
80ced186
MG		 5771out:
5772 return ret;
ea953ef0
MG		 5773}
5774
b4a2d31d
RK		 5775static int __grow_ple_window(int val)
5776{
5777 if (ple_window_grow < 1)
5778 return ple_window;
5779
5780 val = min(val, ple_window_actual_max);
5781
5782 if (ple_window_grow < ple_window)
5783 val *= ple_window_grow;
5784 else
5785 val += ple_window_grow;
5786
5787 return val;
5788}
5789
5790static int __shrink_ple_window(int val, int modifier, int minimum)
5791{
5792 if (modifier < 1)
5793 return ple_window;
5794
5795 if (modifier < ple_window)
5796 val /= modifier;
5797 else
5798 val -= modifier;
5799
5800 return max(val, minimum);
5801}
5802
5803static void grow_ple_window(struct kvm_vcpu *vcpu)
5804{
5805 struct vcpu_vmx *vmx = to_vmx(vcpu);
5806 int old = vmx->ple_window;
5807
5808 vmx->ple_window = __grow_ple_window(old);
5809
5810 if (vmx->ple_window != old)
5811 vmx->ple_window_dirty = true;
7b46268d
RK		 5812
5813 trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK		 5814}
5815
5816static void shrink_ple_window(struct kvm_vcpu *vcpu)
5817{
5818 struct vcpu_vmx *vmx = to_vmx(vcpu);
5819 int old = vmx->ple_window;
5820
5821 vmx->ple_window = __shrink_ple_window(old,
5822 ple_window_shrink, ple_window);
5823
5824 if (vmx->ple_window != old)
5825 vmx->ple_window_dirty = true;
7b46268d
RK		 5826
5827 trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK		 5828}
5829
5830/*
5831 * ple_window_actual_max is computed to be one grow_ple_window() below
5832 * ple_window_max. (See __grow_ple_window for the reason.)
5833 * This prevents overflows, because ple_window_max is int.
5834 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
5835 * this process.
5836 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
5837 */
5838static void update_ple_window_actual_max(void)
5839{
5840 ple_window_actual_max =
5841 __shrink_ple_window(max(ple_window_max, ple_window),
5842 ple_window_grow, INT_MIN);
5843}
5844
f2c7648d
TC		 5845static __init int hardware_setup(void)
5846{
34a1cd60
TC		 5847 int r = -ENOMEM, i, msr;
5848
5849 rdmsrl_safe(MSR_EFER, &host_efer);
5850
5851 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
5852 kvm_define_shared_msr(i, vmx_msr_index[i]);
5853
5854 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
5855 if (!vmx_io_bitmap_a)
5856 return r;
5857
5858 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
5859 if (!vmx_io_bitmap_b)
5860 goto out;
5861
5862 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
5863 if (!vmx_msr_bitmap_legacy)
5864 goto out1;
5865
5866 vmx_msr_bitmap_legacy_x2apic =
5867 (unsigned long *)__get_free_page(GFP_KERNEL);
5868 if (!vmx_msr_bitmap_legacy_x2apic)
5869 goto out2;
5870
5871 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
5872 if (!vmx_msr_bitmap_longmode)
5873 goto out3;
5874
5875 vmx_msr_bitmap_longmode_x2apic =
5876 (unsigned long *)__get_free_page(GFP_KERNEL);
5877 if (!vmx_msr_bitmap_longmode_x2apic)
5878 goto out4;
3af18d9c
WV		 5879
5880 if (nested) {
5881 vmx_msr_bitmap_nested =
5882 (unsigned long *)__get_free_page(GFP_KERNEL);
5883 if (!vmx_msr_bitmap_nested)
5884 goto out5;
5885 }
5886
34a1cd60
TC		 5887 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
5888 if (!vmx_vmread_bitmap)
3af18d9c 5889 goto out6;
34a1cd60
TC		 5890
5891 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
5892 if (!vmx_vmwrite_bitmap)
3af18d9c 5893 goto out7;
34a1cd60
TC		 5894
5895 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
5896 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
5897
5898 /*
5899 * Allow direct access to the PC debug port (it is often used for I/O
5900 * delays, but the vmexits simply slow things down).
5901 */
5902 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
5903 clear_bit(0x80, vmx_io_bitmap_a);
5904
5905 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
5906
5907 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
5908 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
3af18d9c
WV		 5909 if (nested)
5910 memset(vmx_msr_bitmap_nested, 0xff, PAGE_SIZE);
34a1cd60 5911
34a1cd60
TC		 5912 if (setup_vmcs_config(&vmcs_config) < 0) {
5913 r = -EIO;
3af18d9c 5914 goto out8;
baa03522 5915 }
f2c7648d
TC		 5916
5917 if (boot_cpu_has(X86_FEATURE_NX))
5918 kvm_enable_efer_bits(EFER_NX);
5919
5920 if (!cpu_has_vmx_vpid())
5921 enable_vpid = 0;
5922 if (!cpu_has_vmx_shadow_vmcs())
5923 enable_shadow_vmcs = 0;
5924 if (enable_shadow_vmcs)
5925 init_vmcs_shadow_fields();
5926
5927 if (!cpu_has_vmx_ept() ||
5928 !cpu_has_vmx_ept_4levels()) {
5929 enable_ept = 0;
5930 enable_unrestricted_guest = 0;
5931 enable_ept_ad_bits = 0;
5932 }
5933
5934 if (!cpu_has_vmx_ept_ad_bits())
5935 enable_ept_ad_bits = 0;
5936
5937 if (!cpu_has_vmx_unrestricted_guest())
5938 enable_unrestricted_guest = 0;
5939
ad15a296 5940 if (!cpu_has_vmx_flexpriority())
f2c7648d
TC		 5941 flexpriority_enabled = 0;
5942
ad15a296
PB		 5943 /*
5944 * set_apic_access_page_addr() is used to reload apic access
5945 * page upon invalidation. No need to do anything if not
5946 * using the APIC_ACCESS_ADDR VMCS field.
5947 */
5948 if (!flexpriority_enabled)
f2c7648d 5949 kvm_x86_ops->set_apic_access_page_addr = NULL;
f2c7648d
TC		 5950
5951 if (!cpu_has_vmx_tpr_shadow())
5952 kvm_x86_ops->update_cr8_intercept = NULL;
5953
5954 if (enable_ept && !cpu_has_vmx_ept_2m_page())
5955 kvm_disable_largepages();
5956
5957 if (!cpu_has_vmx_ple())
5958 ple_gap = 0;
5959
5960 if (!cpu_has_vmx_apicv())
5961 enable_apicv = 0;
5962
5963 if (enable_apicv)
5964 kvm_x86_ops->update_cr8_intercept = NULL;
5965 else {
5966 kvm_x86_ops->hwapic_irr_update = NULL;
b4eef9b3 5967 kvm_x86_ops->hwapic_isr_update = NULL;
f2c7648d
TC		 5968 kvm_x86_ops->deliver_posted_interrupt = NULL;
5969 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
5970 }
5971
5972 if (nested)
5973 nested_vmx_setup_ctls_msrs();
5974
baa03522
TC		 5975 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
5976 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
5977 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
5978 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
5979 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
5980 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
5981 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
5982
5983 memcpy(vmx_msr_bitmap_legacy_x2apic,
5984 vmx_msr_bitmap_legacy, PAGE_SIZE);
5985 memcpy(vmx_msr_bitmap_longmode_x2apic,
5986 vmx_msr_bitmap_longmode, PAGE_SIZE);
5987
5988 if (enable_apicv) {
5989 for (msr = 0x800; msr <= 0x8ff; msr++)
5990 vmx_disable_intercept_msr_read_x2apic(msr);
5991
5992 /* According SDM, in x2apic mode, the whole id reg is used.
5993 * But in KVM, it only use the highest eight bits. Need to
5994 * intercept it */
5995 vmx_enable_intercept_msr_read_x2apic(0x802);
5996 /* TMCCT */
5997 vmx_enable_intercept_msr_read_x2apic(0x839);
5998 /* TPR */
5999 vmx_disable_intercept_msr_write_x2apic(0x808);
6000 /* EOI */
6001 vmx_disable_intercept_msr_write_x2apic(0x80b);
6002 /* SELF-IPI */
6003 vmx_disable_intercept_msr_write_x2apic(0x83f);
6004 }
6005
6006 if (enable_ept) {
6007 kvm_mmu_set_mask_ptes(0ull,
6008 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
6009 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
6010 0ull, VMX_EPT_EXECUTABLE_MASK);
6011 ept_set_mmio_spte_mask();
6012 kvm_enable_tdp();
6013 } else
6014 kvm_disable_tdp();
6015
6016 update_ple_window_actual_max();
6017
843e4330
KH		 6018 /*
6019 * Only enable PML when hardware supports PML feature, and both EPT
6020 * and EPT A/D bit features are enabled -- PML depends on them to work.
6021 */
6022 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6023 enable_pml = 0;
6024
6025 if (!enable_pml) {
6026 kvm_x86_ops->slot_enable_log_dirty = NULL;
6027 kvm_x86_ops->slot_disable_log_dirty = NULL;
6028 kvm_x86_ops->flush_log_dirty = NULL;
6029 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6030 }
6031
f2c7648d 6032 return alloc_kvm_area();
34a1cd60 6033
3af18d9c 6034out8:
34a1cd60 6035 free_page((unsigned long)vmx_vmwrite_bitmap);
3af18d9c 6036out7:
34a1cd60 6037 free_page((unsigned long)vmx_vmread_bitmap);
3af18d9c
WV		 6038out6:
6039 if (nested)
6040 free_page((unsigned long)vmx_msr_bitmap_nested);
34a1cd60
TC		 6041out5:
6042 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6043out4:
6044 free_page((unsigned long)vmx_msr_bitmap_longmode);
6045out3:
6046 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6047out2:
6048 free_page((unsigned long)vmx_msr_bitmap_legacy);
6049out1:
6050 free_page((unsigned long)vmx_io_bitmap_b);
6051out:
6052 free_page((unsigned long)vmx_io_bitmap_a);
6053
6054 return r;
f2c7648d
TC		 6055}
6056
6057static __exit void hardware_unsetup(void)
6058{
34a1cd60
TC		 6059 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6060 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6061 free_page((unsigned long)vmx_msr_bitmap_legacy);
6062 free_page((unsigned long)vmx_msr_bitmap_longmode);
6063 free_page((unsigned long)vmx_io_bitmap_b);
6064 free_page((unsigned long)vmx_io_bitmap_a);
6065 free_page((unsigned long)vmx_vmwrite_bitmap);
6066 free_page((unsigned long)vmx_vmread_bitmap);
3af18d9c
WV		 6067 if (nested)
6068 free_page((unsigned long)vmx_msr_bitmap_nested);
34a1cd60 6069
f2c7648d
TC		 6070 free_kvm_area();
6071}
6072
4b8d54f9
ZE		 6073/*
6074 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6075 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6076 */
9fb41ba8 6077static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9 6078{
b4a2d31d
RK		 6079 if (ple_gap)
6080 grow_ple_window(vcpu);
6081
4b8d54f9
ZE		 6082 skip_emulated_instruction(vcpu);
6083 kvm_vcpu_on_spin(vcpu);
6084
6085 return 1;
6086}
6087
87c00572 6088static int handle_nop(struct kvm_vcpu *vcpu)
59708670 6089{
87c00572 6090 skip_emulated_instruction(vcpu);
59708670
SY		 6091 return 1;
6092}
6093
87c00572
GS		 6094static int handle_mwait(struct kvm_vcpu *vcpu)
6095{
6096 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6097 return handle_nop(vcpu);
6098}
6099
6100static int handle_monitor(struct kvm_vcpu *vcpu)
6101{
6102 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6103 return handle_nop(vcpu);
6104}
6105
ff2f6fe9
NHE		 6106/*
6107 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6108 * We could reuse a single VMCS for all the L2 guests, but we also want the
6109 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6110 * allows keeping them loaded on the processor, and in the future will allow
6111 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6112 * every entry if they never change.
6113 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6114 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6115 *
6116 * The following functions allocate and free a vmcs02 in this pool.
6117 */
6118
6119/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6120static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6121{
6122 struct vmcs02_list *item;
6123 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6124 if (item->vmptr == vmx->nested.current_vmptr) {
6125 list_move(&item->list, &vmx->nested.vmcs02_pool);
6126 return &item->vmcs02;
6127 }
6128
6129 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6130 /* Recycle the least recently used VMCS. */
6131 item = list_entry(vmx->nested.vmcs02_pool.prev,
6132 struct vmcs02_list, list);
6133 item->vmptr = vmx->nested.current_vmptr;
6134 list_move(&item->list, &vmx->nested.vmcs02_pool);
6135 return &item->vmcs02;
6136 }
6137
6138 /* Create a new VMCS */
0fa24ce3 6139 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE		 6140 if (!item)
6141 return NULL;
6142 item->vmcs02.vmcs = alloc_vmcs();
6143 if (!item->vmcs02.vmcs) {
6144 kfree(item);
6145 return NULL;
6146 }
6147 loaded_vmcs_init(&item->vmcs02);
6148 item->vmptr = vmx->nested.current_vmptr;
6149 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6150 vmx->nested.vmcs02_num++;
6151 return &item->vmcs02;
6152}
6153
6154/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6155static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6156{
6157 struct vmcs02_list *item;
6158 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6159 if (item->vmptr == vmptr) {
6160 free_loaded_vmcs(&item->vmcs02);
6161 list_del(&item->list);
6162 kfree(item);
6163 vmx->nested.vmcs02_num--;
6164 return;
6165 }
6166}
6167
6168/*
6169 * Free all VMCSs saved for this vcpu, except the one pointed by
4fa7734c
PB		 6170 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6171 * must be &vmx->vmcs01.
ff2f6fe9
NHE		 6172 */
6173static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6174{
6175 struct vmcs02_list *item, *n;
4fa7734c
PB		 6176
6177 WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
ff2f6fe9 6178 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
4fa7734c
PB		 6179 /*
6180 * Something will leak if the above WARN triggers. Better than
6181 * a use-after-free.
6182 */
6183 if (vmx->loaded_vmcs == &item->vmcs02)
6184 continue;
6185
6186 free_loaded_vmcs(&item->vmcs02);
ff2f6fe9
NHE		 6187 list_del(&item->list);
6188 kfree(item);
4fa7734c 6189 vmx->nested.vmcs02_num--;
ff2f6fe9 6190 }
ff2f6fe9
NHE		 6191}
6192
0658fbaa
ACL		 6193/*
6194 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6195 * set the success or error code of an emulated VMX instruction, as specified
6196 * by Vol 2B, VMX Instruction Reference, "Conventions".
6197 */
6198static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6199{
6200 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6201 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6202 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6203}
6204
6205static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6206{
6207 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6208 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6209 X86_EFLAGS_SF | X86_EFLAGS_OF))
6210 | X86_EFLAGS_CF);
6211}
6212
145c28dd 6213static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
0658fbaa
ACL		 6214 u32 vm_instruction_error)
6215{
6216 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6217 /*
6218 * failValid writes the error number to the current VMCS, which
6219 * can't be done there isn't a current VMCS.
6220 */
6221 nested_vmx_failInvalid(vcpu);
6222 return;
6223 }
6224 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6225 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6226 X86_EFLAGS_SF | X86_EFLAGS_OF))
6227 | X86_EFLAGS_ZF);
6228 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6229 /*
6230 * We don't need to force a shadow sync because
6231 * VM_INSTRUCTION_ERROR is not shadowed
6232 */
6233}
145c28dd 6234
ff651cb6
WV		 6235static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6236{
6237 /* TODO: not to reset guest simply here. */
6238 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6239 pr_warn("kvm: nested vmx abort, indicator %d\n", indicator);
6240}
6241
f4124500
JK		 6242static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6243{
6244 struct vcpu_vmx *vmx =
6245 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6246
6247 vmx->nested.preemption_timer_expired = true;
6248 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6249 kvm_vcpu_kick(&vmx->vcpu);
6250
6251 return HRTIMER_NORESTART;
6252}
6253
19677e32
BD		 6254/*
6255 * Decode the memory-address operand of a vmx instruction, as recorded on an
6256 * exit caused by such an instruction (run by a guest hypervisor).
6257 * On success, returns 0. When the operand is invalid, returns 1 and throws
6258 * #UD or #GP.
6259 */
6260static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6261 unsigned long exit_qualification,
6262 u32 vmx_instruction_info, gva_t *ret)
6263{
6264 /*
6265 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6266 * Execution", on an exit, vmx_instruction_info holds most of the
6267 * addressing components of the operand. Only the displacement part
6268 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6269 * For how an actual address is calculated from all these components,
6270 * refer to Vol. 1, "Operand Addressing".
6271 */
6272 int scaling = vmx_instruction_info & 3;
6273 int addr_size = (vmx_instruction_info >> 7) & 7;
6274 bool is_reg = vmx_instruction_info & (1u << 10);
6275 int seg_reg = (vmx_instruction_info >> 15) & 7;
6276 int index_reg = (vmx_instruction_info >> 18) & 0xf;
6277 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6278 int base_reg = (vmx_instruction_info >> 23) & 0xf;
6279 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
6280
6281 if (is_reg) {
6282 kvm_queue_exception(vcpu, UD_VECTOR);
6283 return 1;
6284 }
6285
6286 /* Addr = segment_base + offset */
6287 /* offset = base + [index * scale] + displacement */
6288 *ret = vmx_get_segment_base(vcpu, seg_reg);
6289 if (base_is_valid)
6290 *ret += kvm_register_read(vcpu, base_reg);
6291 if (index_is_valid)
6292 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
6293 *ret += exit_qualification; /* holds the displacement */
6294
6295 if (addr_size == 1) /* 32 bit */
6296 *ret &= 0xffffffff;
6297
6298 /*
6299 * TODO: throw #GP (and return 1) in various cases that the VM*
6300 * instructions require it - e.g., offset beyond segment limit,
6301 * unusable or unreadable/unwritable segment, non-canonical 64-bit
6302 * address, and so on. Currently these are not checked.
6303 */
6304 return 0;
6305}
6306
3573e22c
BD		 6307/*
6308 * This function performs the various checks including
6309 * - if it's 4KB aligned
6310 * - No bits beyond the physical address width are set
6311 * - Returns 0 on success or else 1
4291b588 6312 * (Intel SDM Section 30.3)
3573e22c 6313 */
4291b588
BD		 6314static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6315 gpa_t *vmpointer)
3573e22c
BD		 6316{
6317 gva_t gva;
6318 gpa_t vmptr;
6319 struct x86_exception e;
6320 struct page *page;
6321 struct vcpu_vmx *vmx = to_vmx(vcpu);
6322 int maxphyaddr = cpuid_maxphyaddr(vcpu);
6323
6324 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6325 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6326 return 1;
6327
6328 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6329 sizeof(vmptr), &e)) {
6330 kvm_inject_page_fault(vcpu, &e);
6331 return 1;
6332 }
6333
6334 switch (exit_reason) {
6335 case EXIT_REASON_VMON:
6336 /*
6337 * SDM 3: 24.11.5
6338 * The first 4 bytes of VMXON region contain the supported
6339 * VMCS revision identifier
6340 *
6341 * Note - IA32_VMX_BASIC[48] will never be 1
6342 * for the nested case;
6343 * which replaces physical address width with 32
6344 *
6345 */
bc39c4db 6346 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
3573e22c
BD		 6347 nested_vmx_failInvalid(vcpu);
6348 skip_emulated_instruction(vcpu);
6349 return 1;
6350 }
6351
6352 page = nested_get_page(vcpu, vmptr);
6353 if (page == NULL ||
6354 *(u32 *)kmap(page) != VMCS12_REVISION) {
6355 nested_vmx_failInvalid(vcpu);
6356 kunmap(page);
6357 skip_emulated_instruction(vcpu);
6358 return 1;
6359 }
6360 kunmap(page);
6361 vmx->nested.vmxon_ptr = vmptr;
6362 break;
4291b588 6363 case EXIT_REASON_VMCLEAR:
bc39c4db 6364 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
4291b588
BD		 6365 nested_vmx_failValid(vcpu,
6366 VMXERR_VMCLEAR_INVALID_ADDRESS);
6367 skip_emulated_instruction(vcpu);
6368 return 1;
6369 }
6370
6371 if (vmptr == vmx->nested.vmxon_ptr) {
6372 nested_vmx_failValid(vcpu,
6373 VMXERR_VMCLEAR_VMXON_POINTER);
6374 skip_emulated_instruction(vcpu);
6375 return 1;
6376 }
6377 break;
6378 case EXIT_REASON_VMPTRLD:
bc39c4db 6379 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
4291b588
BD		 6380 nested_vmx_failValid(vcpu,
6381 VMXERR_VMPTRLD_INVALID_ADDRESS);
6382 skip_emulated_instruction(vcpu);
6383 return 1;
6384 }
3573e22c 6385
4291b588
BD		 6386 if (vmptr == vmx->nested.vmxon_ptr) {
6387 nested_vmx_failValid(vcpu,
6388 VMXERR_VMCLEAR_VMXON_POINTER);
6389 skip_emulated_instruction(vcpu);
6390 return 1;
6391 }
6392 break;
3573e22c
BD		 6393 default:
6394 return 1; /* shouldn't happen */
6395 }
6396
4291b588
BD		 6397 if (vmpointer)
6398 *vmpointer = vmptr;
3573e22c
BD		 6399 return 0;
6400}
6401
ec378aee
NHE		 6402/*
6403 * Emulate the VMXON instruction.
6404 * Currently, we just remember that VMX is active, and do not save or even
6405 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6406 * do not currently need to store anything in that guest-allocated memory
6407 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6408 * argument is different from the VMXON pointer (which the spec says they do).
6409 */
6410static int handle_vmon(struct kvm_vcpu *vcpu)
6411{
6412 struct kvm_segment cs;
6413 struct vcpu_vmx *vmx = to_vmx(vcpu);
8de48833 6414 struct vmcs *shadow_vmcs;
b3897a49
NHE		 6415 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6416 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
ec378aee
NHE		 6417
6418 /* The Intel VMX Instruction Reference lists a bunch of bits that
6419 * are prerequisite to running VMXON, most notably cr4.VMXE must be
6420 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6421 * Otherwise, we should fail with #UD. We test these now:
6422 */
6423 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6424 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6425 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6426 kvm_queue_exception(vcpu, UD_VECTOR);
6427 return 1;
6428 }
6429
6430 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6431 if (is_long_mode(vcpu) && !cs.l) {
6432 kvm_queue_exception(vcpu, UD_VECTOR);
6433 return 1;
6434 }
6435
6436 if (vmx_get_cpl(vcpu)) {
6437 kvm_inject_gp(vcpu, 0);
6438 return 1;
6439 }
3573e22c 6440
4291b588 6441 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
3573e22c
BD		 6442 return 1;
6443
145c28dd
AG		 6444 if (vmx->nested.vmxon) {
6445 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6446 skip_emulated_instruction(vcpu);
6447 return 1;
6448 }
b3897a49
NHE		 6449
6450 if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6451 != VMXON_NEEDED_FEATURES) {
6452 kvm_inject_gp(vcpu, 0);
6453 return 1;
6454 }
6455
8de48833
AG		 6456 if (enable_shadow_vmcs) {
6457 shadow_vmcs = alloc_vmcs();
6458 if (!shadow_vmcs)
6459 return -ENOMEM;
6460 /* mark vmcs as shadow */
6461 shadow_vmcs->revision_id |= (1u << 31);
6462 /* init shadow vmcs */
6463 vmcs_clear(shadow_vmcs);
6464 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6465 }
ec378aee 6466
ff2f6fe9
NHE		 6467 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6468 vmx->nested.vmcs02_num = 0;
6469
f4124500
JK		 6470 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6471 HRTIMER_MODE_REL);
6472 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6473
ec378aee
NHE		 6474 vmx->nested.vmxon = true;
6475
6476 skip_emulated_instruction(vcpu);
a25eb114 6477 nested_vmx_succeed(vcpu);
ec378aee
NHE		 6478 return 1;
6479}
6480
6481/*
6482 * Intel's VMX Instruction Reference specifies a common set of prerequisites
6483 * for running VMX instructions (except VMXON, whose prerequisites are
6484 * slightly different). It also specifies what exception to inject otherwise.
6485 */
6486static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6487{
6488 struct kvm_segment cs;
6489 struct vcpu_vmx *vmx = to_vmx(vcpu);
6490
6491 if (!vmx->nested.vmxon) {
6492 kvm_queue_exception(vcpu, UD_VECTOR);
6493 return 0;
6494 }
6495
6496 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6497 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6498 (is_long_mode(vcpu) && !cs.l)) {
6499 kvm_queue_exception(vcpu, UD_VECTOR);
6500 return 0;
6501 }
6502
6503 if (vmx_get_cpl(vcpu)) {
6504 kvm_inject_gp(vcpu, 0);
6505 return 0;
6506 }
6507
6508 return 1;
6509}
6510
e7953d7f
AG		 6511static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6512{
8a1b9dd0 6513 u32 exec_control;
9a2a05b9
PB		 6514 if (vmx->nested.current_vmptr == -1ull)
6515 return;
6516
6517 /* current_vmptr and current_vmcs12 are always set/reset together */
6518 if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
6519 return;
6520
012f83cb 6521 if (enable_shadow_vmcs) {
9a2a05b9
PB		 6522 /* copy to memory all shadowed fields in case
6523 they were modified */
6524 copy_shadow_to_vmcs12(vmx);
6525 vmx->nested.sync_shadow_vmcs = false;
6526 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6527 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
6528 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6529 vmcs_write64(VMCS_LINK_POINTER, -1ull);
012f83cb 6530 }
e7953d7f
AG		 6531 kunmap(vmx->nested.current_vmcs12_page);
6532 nested_release_page(vmx->nested.current_vmcs12_page);
9a2a05b9
PB		 6533 vmx->nested.current_vmptr = -1ull;
6534 vmx->nested.current_vmcs12 = NULL;
e7953d7f
AG		 6535}
6536
ec378aee
NHE		 6537/*
6538 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6539 * just stops using VMX.
6540 */
6541static void free_nested(struct vcpu_vmx *vmx)
6542{
6543 if (!vmx->nested.vmxon)
6544 return;
9a2a05b9 6545
ec378aee 6546 vmx->nested.vmxon = false;
9a2a05b9 6547 nested_release_vmcs12(vmx);
e7953d7f
AG		 6548 if (enable_shadow_vmcs)
6549 free_vmcs(vmx->nested.current_shadow_vmcs);
fe3ef05c
NHE		 6550 /* Unpin physical memory we referred to in current vmcs02 */
6551 if (vmx->nested.apic_access_page) {
6552 nested_release_page(vmx->nested.apic_access_page);
48d89b92 6553 vmx->nested.apic_access_page = NULL;
fe3ef05c 6554 }
a7c0b07d
WL		 6555 if (vmx->nested.virtual_apic_page) {
6556 nested_release_page(vmx->nested.virtual_apic_page);
48d89b92 6557 vmx->nested.virtual_apic_page = NULL;
a7c0b07d 6558 }
ff2f6fe9
NHE		 6559
6560 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 6561}
6562
6563/* Emulate the VMXOFF instruction */
6564static int handle_vmoff(struct kvm_vcpu *vcpu)
6565{
6566 if (!nested_vmx_check_permission(vcpu))
6567 return 1;
6568 free_nested(to_vmx(vcpu));
6569 skip_emulated_instruction(vcpu);
a25eb114 6570 nested_vmx_succeed(vcpu);
ec378aee
NHE		 6571 return 1;
6572}
6573
27d6c865
NHE		 6574/* Emulate the VMCLEAR instruction */
6575static int handle_vmclear(struct kvm_vcpu *vcpu)
6576{
6577 struct vcpu_vmx *vmx = to_vmx(vcpu);
27d6c865
NHE		 6578 gpa_t vmptr;
6579 struct vmcs12 *vmcs12;
6580 struct page *page;
27d6c865
NHE		 6581
6582 if (!nested_vmx_check_permission(vcpu))
6583 return 1;
6584
4291b588 6585 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
27d6c865 6586 return 1;
27d6c865 6587
9a2a05b9 6588 if (vmptr == vmx->nested.current_vmptr)
e7953d7f 6589 nested_release_vmcs12(vmx);
27d6c865
NHE		 6590
6591 page = nested_get_page(vcpu, vmptr);
6592 if (page == NULL) {
6593 /*
6594 * For accurate processor emulation, VMCLEAR beyond available
6595 * physical memory should do nothing at all. However, it is
6596 * possible that a nested vmx bug, not a guest hypervisor bug,
6597 * resulted in this case, so let's shut down before doing any
6598 * more damage:
6599 */
6600 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6601 return 1;
6602 }
6603 vmcs12 = kmap(page);
6604 vmcs12->launch_state = 0;
6605 kunmap(page);
6606 nested_release_page(page);
6607
6608 nested_free_vmcs02(vmx, vmptr);
6609
6610 skip_emulated_instruction(vcpu);
6611 nested_vmx_succeed(vcpu);
6612 return 1;
6613}
6614
cd232ad0
NHE		 6615static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6616
6617/* Emulate the VMLAUNCH instruction */
6618static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6619{
6620 return nested_vmx_run(vcpu, true);
6621}
6622
6623/* Emulate the VMRESUME instruction */
6624static int handle_vmresume(struct kvm_vcpu *vcpu)
6625{
6626
6627 return nested_vmx_run(vcpu, false);
6628}
6629
49f705c5
NHE		 6630enum vmcs_field_type {
6631 VMCS_FIELD_TYPE_U16 = 0,
6632 VMCS_FIELD_TYPE_U64 = 1,
6633 VMCS_FIELD_TYPE_U32 = 2,
6634 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6635};
6636
6637static inline int vmcs_field_type(unsigned long field)
6638{
6639 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
6640 return VMCS_FIELD_TYPE_U32;
6641 return (field >> 13) & 0x3 ;
6642}
6643
6644static inline int vmcs_field_readonly(unsigned long field)
6645{
6646 return (((field >> 10) & 0x3) == 1);
6647}
6648
6649/*
6650 * Read a vmcs12 field. Since these can have varying lengths and we return
6651 * one type, we chose the biggest type (u64) and zero-extend the return value
6652 * to that size. Note that the caller, handle_vmread, might need to use only
6653 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6654 * 64-bit fields are to be returned).
6655 */
a2ae9df7
PB		 6656static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
6657 unsigned long field, u64 *ret)
49f705c5
NHE		 6658{
6659 short offset = vmcs_field_to_offset(field);
6660 char *p;
6661
6662 if (offset < 0)
a2ae9df7 6663 return offset;
49f705c5
NHE		 6664
6665 p = ((char *)(get_vmcs12(vcpu))) + offset;
6666
6667 switch (vmcs_field_type(field)) {
6668 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6669 *ret = *((natural_width *)p);
a2ae9df7 6670 return 0;
49f705c5
NHE		 6671 case VMCS_FIELD_TYPE_U16:
6672 *ret = *((u16 *)p);
a2ae9df7 6673 return 0;
49f705c5
NHE		 6674 case VMCS_FIELD_TYPE_U32:
6675 *ret = *((u32 *)p);
a2ae9df7 6676 return 0;
49f705c5
NHE		 6677 case VMCS_FIELD_TYPE_U64:
6678 *ret = *((u64 *)p);
a2ae9df7 6679 return 0;
49f705c5 6680 default:
a2ae9df7
PB		 6681 WARN_ON(1);
6682 return -ENOENT;
49f705c5
NHE		 6683 }
6684}
6685
20b97fea 6686
a2ae9df7
PB		 6687static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
6688 unsigned long field, u64 field_value){
20b97fea
AG		 6689 short offset = vmcs_field_to_offset(field);
6690 char *p = ((char *) get_vmcs12(vcpu)) + offset;
6691 if (offset < 0)
a2ae9df7 6692 return offset;
20b97fea
AG		 6693
6694 switch (vmcs_field_type(field)) {
6695 case VMCS_FIELD_TYPE_U16:
6696 *(u16 *)p = field_value;
a2ae9df7 6697 return 0;
20b97fea
AG		 6698 case VMCS_FIELD_TYPE_U32:
6699 *(u32 *)p = field_value;
a2ae9df7 6700 return 0;
20b97fea
AG		 6701 case VMCS_FIELD_TYPE_U64:
6702 *(u64 *)p = field_value;
a2ae9df7 6703 return 0;
20b97fea
AG		 6704 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6705 *(natural_width *)p = field_value;
a2ae9df7 6706 return 0;
20b97fea 6707 default:
a2ae9df7
PB		 6708 WARN_ON(1);
6709 return -ENOENT;
20b97fea
AG		 6710 }
6711
6712}
6713
16f5b903
AG		 6714static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6715{
6716 int i;
6717 unsigned long field;
6718 u64 field_value;
6719 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
c2bae893
MK		 6720 const unsigned long *fields = shadow_read_write_fields;
6721 const int num_fields = max_shadow_read_write_fields;
16f5b903 6722
282da870
JK		 6723 preempt_disable();
6724
16f5b903
AG		 6725 vmcs_load(shadow_vmcs);
6726
6727 for (i = 0; i < num_fields; i++) {
6728 field = fields[i];
6729 switch (vmcs_field_type(field)) {
6730 case VMCS_FIELD_TYPE_U16:
6731 field_value = vmcs_read16(field);
6732 break;
6733 case VMCS_FIELD_TYPE_U32:
6734 field_value = vmcs_read32(field);
6735 break;
6736 case VMCS_FIELD_TYPE_U64:
6737 field_value = vmcs_read64(field);
6738 break;
6739 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6740 field_value = vmcs_readl(field);
6741 break;
a2ae9df7
PB		 6742 default:
6743 WARN_ON(1);
6744 continue;
16f5b903
AG		 6745 }
6746 vmcs12_write_any(&vmx->vcpu, field, field_value);
6747 }
6748
6749 vmcs_clear(shadow_vmcs);
6750 vmcs_load(vmx->loaded_vmcs->vmcs);
282da870
JK		 6751
6752 preempt_enable();
16f5b903
AG		 6753}
6754
c3114420
AG		 6755static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6756{
c2bae893
MK		 6757 const unsigned long *fields[] = {
6758 shadow_read_write_fields,
6759 shadow_read_only_fields
c3114420 6760 };
c2bae893 6761 const int max_fields[] = {
c3114420
AG		 6762 max_shadow_read_write_fields,
6763 max_shadow_read_only_fields
6764 };
6765 int i, q;
6766 unsigned long field;
6767 u64 field_value = 0;
6768 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6769
6770 vmcs_load(shadow_vmcs);
6771
c2bae893 6772 for (q = 0; q < ARRAY_SIZE(fields); q++) {
c3114420
AG		 6773 for (i = 0; i < max_fields[q]; i++) {
6774 field = fields[q][i];
6775 vmcs12_read_any(&vmx->vcpu, field, &field_value);
6776
6777 switch (vmcs_field_type(field)) {
6778 case VMCS_FIELD_TYPE_U16:
6779 vmcs_write16(field, (u16)field_value);
6780 break;
6781 case VMCS_FIELD_TYPE_U32:
6782 vmcs_write32(field, (u32)field_value);
6783 break;
6784 case VMCS_FIELD_TYPE_U64:
6785 vmcs_write64(field, (u64)field_value);
6786 break;
6787 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6788 vmcs_writel(field, (long)field_value);
6789 break;
a2ae9df7
PB		 6790 default:
6791 WARN_ON(1);
6792 break;
c3114420
AG		 6793 }
6794 }
6795 }
6796
6797 vmcs_clear(shadow_vmcs);
6798 vmcs_load(vmx->loaded_vmcs->vmcs);
6799}
6800
49f705c5
NHE		 6801/*
6802 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6803 * used before) all generate the same failure when it is missing.
6804 */
6805static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6806{
6807 struct vcpu_vmx *vmx = to_vmx(vcpu);
6808 if (vmx->nested.current_vmptr == -1ull) {
6809 nested_vmx_failInvalid(vcpu);
6810 skip_emulated_instruction(vcpu);
6811 return 0;
6812 }
6813 return 1;
6814}
6815
6816static int handle_vmread(struct kvm_vcpu *vcpu)
6817{
6818 unsigned long field;
6819 u64 field_value;
6820 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6821 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6822 gva_t gva = 0;
6823
6824 if (!nested_vmx_check_permission(vcpu) ||
6825 !nested_vmx_check_vmcs12(vcpu))
6826 return 1;
6827
6828 /* Decode instruction info and find the field to read */
27e6fb5d 6829 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5 6830 /* Read the field, zero-extended to a u64 field_value */
a2ae9df7 6831 if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
49f705c5
NHE		 6832 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6833 skip_emulated_instruction(vcpu);
6834 return 1;
6835 }
6836 /*
6837 * Now copy part of this value to register or memory, as requested.
6838 * Note that the number of bits actually copied is 32 or 64 depending
6839 * on the guest's mode (32 or 64 bit), not on the given field's length.
6840 */
6841 if (vmx_instruction_info & (1u << 10)) {
27e6fb5d 6842 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
49f705c5
NHE		 6843 field_value);
6844 } else {
6845 if (get_vmx_mem_address(vcpu, exit_qualification,
6846 vmx_instruction_info, &gva))
6847 return 1;
6848 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6849 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6850 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6851 }
6852
6853 nested_vmx_succeed(vcpu);
6854 skip_emulated_instruction(vcpu);
6855 return 1;
6856}
6857
6858
6859static int handle_vmwrite(struct kvm_vcpu *vcpu)
6860{
6861 unsigned long field;
6862 gva_t gva;
6863 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6864 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
49f705c5
NHE		 6865 /* The value to write might be 32 or 64 bits, depending on L1's long
6866 * mode, and eventually we need to write that into a field of several
6867 * possible lengths. The code below first zero-extends the value to 64
6868 * bit (field_value), and then copies only the approriate number of
6869 * bits into the vmcs12 field.
6870 */
6871 u64 field_value = 0;
6872 struct x86_exception e;
6873
6874 if (!nested_vmx_check_permission(vcpu) ||
6875 !nested_vmx_check_vmcs12(vcpu))
6876 return 1;
6877
6878 if (vmx_instruction_info & (1u << 10))
27e6fb5d 6879 field_value = kvm_register_readl(vcpu,
49f705c5
NHE		 6880 (((vmx_instruction_info) >> 3) & 0xf));
6881 else {
6882 if (get_vmx_mem_address(vcpu, exit_qualification,
6883 vmx_instruction_info, &gva))
6884 return 1;
6885 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
27e6fb5d 6886 &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
49f705c5
NHE		 6887 kvm_inject_page_fault(vcpu, &e);
6888 return 1;
6889 }
6890 }
6891
6892
27e6fb5d 6893 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5
NHE		 6894 if (vmcs_field_readonly(field)) {
6895 nested_vmx_failValid(vcpu,
6896 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6897 skip_emulated_instruction(vcpu);
6898 return 1;
6899 }
6900
a2ae9df7 6901 if (vmcs12_write_any(vcpu, field, field_value) < 0) {
49f705c5
NHE		 6902 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6903 skip_emulated_instruction(vcpu);
6904 return 1;
6905 }
6906
6907 nested_vmx_succeed(vcpu);
6908 skip_emulated_instruction(vcpu);
6909 return 1;
6910}
6911
63846663
NHE		 6912/* Emulate the VMPTRLD instruction */
6913static int handle_vmptrld(struct kvm_vcpu *vcpu)
6914{
6915 struct vcpu_vmx *vmx = to_vmx(vcpu);
63846663 6916 gpa_t vmptr;
8a1b9dd0 6917 u32 exec_control;
63846663
NHE		 6918
6919 if (!nested_vmx_check_permission(vcpu))
6920 return 1;
6921
4291b588 6922 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
63846663 6923 return 1;
63846663
NHE		 6924
6925 if (vmx->nested.current_vmptr != vmptr) {
6926 struct vmcs12 *new_vmcs12;
6927 struct page *page;
6928 page = nested_get_page(vcpu, vmptr);
6929 if (page == NULL) {
6930 nested_vmx_failInvalid(vcpu);
6931 skip_emulated_instruction(vcpu);
6932 return 1;
6933 }
6934 new_vmcs12 = kmap(page);
6935 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6936 kunmap(page);
6937 nested_release_page_clean(page);
6938 nested_vmx_failValid(vcpu,
6939 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6940 skip_emulated_instruction(vcpu);
6941 return 1;
6942 }
63846663 6943
9a2a05b9 6944 nested_release_vmcs12(vmx);
63846663
NHE		 6945 vmx->nested.current_vmptr = vmptr;
6946 vmx->nested.current_vmcs12 = new_vmcs12;
6947 vmx->nested.current_vmcs12_page = page;
012f83cb 6948 if (enable_shadow_vmcs) {
8a1b9dd0
AG		 6949 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6950 exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6951 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6952 vmcs_write64(VMCS_LINK_POINTER,
6953 __pa(vmx->nested.current_shadow_vmcs));
012f83cb
AG		 6954 vmx->nested.sync_shadow_vmcs = true;
6955 }
63846663
NHE		 6956 }
6957
6958 nested_vmx_succeed(vcpu);
6959 skip_emulated_instruction(vcpu);
6960 return 1;
6961}
6962
6a4d7550
NHE		 6963/* Emulate the VMPTRST instruction */
6964static int handle_vmptrst(struct kvm_vcpu *vcpu)
6965{
6966 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6967 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6968 gva_t vmcs_gva;
6969 struct x86_exception e;
6970
6971 if (!nested_vmx_check_permission(vcpu))
6972 return 1;
6973
6974 if (get_vmx_mem_address(vcpu, exit_qualification,
6975 vmx_instruction_info, &vmcs_gva))
6976 return 1;
6977 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6978 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6979 (void *)&to_vmx(vcpu)->nested.current_vmptr,
6980 sizeof(u64), &e)) {
6981 kvm_inject_page_fault(vcpu, &e);
6982 return 1;
6983 }
6984 nested_vmx_succeed(vcpu);
6985 skip_emulated_instruction(vcpu);
6986 return 1;
6987}
6988
bfd0a56b
NHE		 6989/* Emulate the INVEPT instruction */
6990static int handle_invept(struct kvm_vcpu *vcpu)
6991{
6992 u32 vmx_instruction_info, types;
6993 unsigned long type;
6994 gva_t gva;
6995 struct x86_exception e;
6996 struct {
6997 u64 eptp, gpa;
6998 } operand;
bfd0a56b
NHE		 6999
7000 if (!(nested_vmx_secondary_ctls_high & SECONDARY_EXEC_ENABLE_EPT) ||
7001 !(nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7002 kvm_queue_exception(vcpu, UD_VECTOR);
7003 return 1;
7004 }
7005
7006 if (!nested_vmx_check_permission(vcpu))
7007 return 1;
7008
7009 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7010 kvm_queue_exception(vcpu, UD_VECTOR);
7011 return 1;
7012 }
7013
7014 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
27e6fb5d 7015 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
bfd0a56b
NHE		 7016
7017 types = (nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7018
7019 if (!(types & (1UL << type))) {
7020 nested_vmx_failValid(vcpu,
7021 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7022 return 1;
7023 }
7024
7025 /* According to the Intel VMX instruction reference, the memory
7026 * operand is read even if it isn't needed (e.g., for type==global)
7027 */
7028 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7029 vmx_instruction_info, &gva))
7030 return 1;
7031 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7032 sizeof(operand), &e)) {
7033 kvm_inject_page_fault(vcpu, &e);
7034 return 1;
7035 }
7036
7037 switch (type) {
bfd0a56b
NHE		 7038 case VMX_EPT_EXTENT_GLOBAL:
7039 kvm_mmu_sync_roots(vcpu);
77c3913b 7040 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
bfd0a56b
NHE		 7041 nested_vmx_succeed(vcpu);
7042 break;
7043 default:
4b855078 7044 /* Trap single context invalidation invept calls */
bfd0a56b
NHE		 7045 BUG_ON(1);
7046 break;
7047 }
7048
7049 skip_emulated_instruction(vcpu);
7050 return 1;
7051}
7052
a642fc30
PM		 7053static int handle_invvpid(struct kvm_vcpu *vcpu)
7054{
7055 kvm_queue_exception(vcpu, UD_VECTOR);
7056 return 1;
7057}
7058
843e4330
KH		 7059static int handle_pml_full(struct kvm_vcpu *vcpu)
7060{
7061 unsigned long exit_qualification;
7062
7063 trace_kvm_pml_full(vcpu->vcpu_id);
7064
7065 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7066
7067 /*
7068 * PML buffer FULL happened while executing iret from NMI,
7069 * "blocked by NMI" bit has to be set before next VM entry.
7070 */
7071 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7072 cpu_has_virtual_nmis() &&
7073 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7074 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7075 GUEST_INTR_STATE_NMI);
7076
7077 /*
7078 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7079 * here.., and there's no userspace involvement needed for PML.
7080 */
7081 return 1;
7082}
7083
6aa8b732
AK		 7084/*
7085 * The exit handlers return 1 if the exit was handled fully and guest execution
7086 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
7087 * to be done to userspace and return 0.
7088 */
772e0318 7089static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 7090 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
7091 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 7092 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 7093 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 7094 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 7095 [EXIT_REASON_CR_ACCESS] = handle_cr,
7096 [EXIT_REASON_DR_ACCESS] = handle_dr,
7097 [EXIT_REASON_CPUID] = handle_cpuid,
7098 [EXIT_REASON_MSR_READ] = handle_rdmsr,
7099 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
7100 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
7101 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 7102 [EXIT_REASON_INVD] = handle_invd,
a7052897 7103 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 7104 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 7105 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 7106 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 7107 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 7108 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 7109 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 7110 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 7111 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 7112 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 7113 [EXIT_REASON_VMOFF] = handle_vmoff,
7114 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 7115 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
7116 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 7117 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 7118 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 7119 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 7120 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 7121 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 7122 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 7123 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
7124 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 7125 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
87c00572
GS		 7126 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
7127 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
bfd0a56b 7128 [EXIT_REASON_INVEPT] = handle_invept,
a642fc30 7129 [EXIT_REASON_INVVPID] = handle_invvpid,
f53cd63c
WL		 7130 [EXIT_REASON_XSAVES] = handle_xsaves,
7131 [EXIT_REASON_XRSTORS] = handle_xrstors,
843e4330 7132 [EXIT_REASON_PML_FULL] = handle_pml_full,
6aa8b732
AK		 7133};
7134
7135static const int kvm_vmx_max_exit_handlers =
50a3485c 7136 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 7137
908a7bdd
JK		 7138static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7139 struct vmcs12 *vmcs12)
7140{
7141 unsigned long exit_qualification;
7142 gpa_t bitmap, last_bitmap;
7143 unsigned int port;
7144 int size;
7145 u8 b;
7146
908a7bdd 7147 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
2f0a6397 7148 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
908a7bdd
JK		 7149
7150 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7151
7152 port = exit_qualification >> 16;
7153 size = (exit_qualification & 7) + 1;
7154
7155 last_bitmap = (gpa_t)-1;
7156 b = -1;
7157
7158 while (size > 0) {
7159 if (port < 0x8000)
7160 bitmap = vmcs12->io_bitmap_a;
7161 else if (port < 0x10000)
7162 bitmap = vmcs12->io_bitmap_b;
7163 else
7164 return 1;
7165 bitmap += (port & 0x7fff) / 8;
7166
7167 if (last_bitmap != bitmap)
7168 if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
7169 return 1;
7170 if (b & (1 << (port & 7)))
7171 return 1;
7172
7173 port++;
7174 size--;
7175 last_bitmap = bitmap;
7176 }
7177
7178 return 0;
7179}
7180
644d711a
NHE		 7181/*
7182 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7183 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7184 * disinterest in the current event (read or write a specific MSR) by using an
7185 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7186 */
7187static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7188 struct vmcs12 *vmcs12, u32 exit_reason)
7189{
7190 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7191 gpa_t bitmap;
7192
cbd29cb6 7193 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
644d711a
NHE		 7194 return 1;
7195
7196 /*
7197 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7198 * for the four combinations of read/write and low/high MSR numbers.
7199 * First we need to figure out which of the four to use:
7200 */
7201 bitmap = vmcs12->msr_bitmap;
7202 if (exit_reason == EXIT_REASON_MSR_WRITE)
7203 bitmap += 2048;
7204 if (msr_index >= 0xc0000000) {
7205 msr_index -= 0xc0000000;
7206 bitmap += 1024;
7207 }
7208
7209 /* Then read the msr_index'th bit from this bitmap: */
7210 if (msr_index < 1024*8) {
7211 unsigned char b;
bd31a7f5
JK		 7212 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
7213 return 1;
644d711a
NHE		 7214 return 1 & (b >> (msr_index & 7));
7215 } else
7216 return 1; /* let L1 handle the wrong parameter */
7217}
7218
7219/*
7220 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7221 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7222 * intercept (via guest_host_mask etc.) the current event.
7223 */
7224static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7225 struct vmcs12 *vmcs12)
7226{
7227 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7228 int cr = exit_qualification & 15;
7229 int reg = (exit_qualification >> 8) & 15;
1e32c079 7230 unsigned long val = kvm_register_readl(vcpu, reg);
644d711a
NHE		 7231
7232 switch ((exit_qualification >> 4) & 3) {
7233 case 0: /* mov to cr */
7234 switch (cr) {
7235 case 0:
7236 if (vmcs12->cr0_guest_host_mask &
7237 (val ^ vmcs12->cr0_read_shadow))
7238 return 1;
7239 break;
7240 case 3:
7241 if ((vmcs12->cr3_target_count >= 1 &&
7242 vmcs12->cr3_target_value0 == val) ||
7243 (vmcs12->cr3_target_count >= 2 &&
7244 vmcs12->cr3_target_value1 == val) ||
7245 (vmcs12->cr3_target_count >= 3 &&
7246 vmcs12->cr3_target_value2 == val) ||
7247 (vmcs12->cr3_target_count >= 4 &&
7248 vmcs12->cr3_target_value3 == val))
7249 return 0;
7250 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
7251 return 1;
7252 break;
7253 case 4:
7254 if (vmcs12->cr4_guest_host_mask &
7255 (vmcs12->cr4_read_shadow ^ val))
7256 return 1;
7257 break;
7258 case 8:
7259 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
7260 return 1;
7261 break;
7262 }
7263 break;
7264 case 2: /* clts */
7265 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7266 (vmcs12->cr0_read_shadow & X86_CR0_TS))
7267 return 1;
7268 break;
7269 case 1: /* mov from cr */
7270 switch (cr) {
7271 case 3:
7272 if (vmcs12->cpu_based_vm_exec_control &
7273 CPU_BASED_CR3_STORE_EXITING)
7274 return 1;
7275 break;
7276 case 8:
7277 if (vmcs12->cpu_based_vm_exec_control &
7278 CPU_BASED_CR8_STORE_EXITING)
7279 return 1;
7280 break;
7281 }
7282 break;
7283 case 3: /* lmsw */
7284 /*
7285 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7286 * cr0. Other attempted changes are ignored, with no exit.
7287 */
7288 if (vmcs12->cr0_guest_host_mask & 0xe &
7289 (val ^ vmcs12->cr0_read_shadow))
7290 return 1;
7291 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7292 !(vmcs12->cr0_read_shadow & 0x1) &&
7293 (val & 0x1))
7294 return 1;
7295 break;
7296 }
7297 return 0;
7298}
7299
7300/*
7301 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7302 * should handle it ourselves in L0 (and then continue L2). Only call this
7303 * when in is_guest_mode (L2).
7304 */
7305static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7306{
644d711a
NHE		 7307 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7308 struct vcpu_vmx *vmx = to_vmx(vcpu);
7309 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
957c897e 7310 u32 exit_reason = vmx->exit_reason;
644d711a 7311
542060ea
JK		 7312 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7313 vmcs_readl(EXIT_QUALIFICATION),
7314 vmx->idt_vectoring_info,
7315 intr_info,
7316 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7317 KVM_ISA_VMX);
7318
644d711a
NHE		 7319 if (vmx->nested.nested_run_pending)
7320 return 0;
7321
7322 if (unlikely(vmx->fail)) {
bd80158a
JK		 7323 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7324 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 7325 return 1;
7326 }
7327
7328 switch (exit_reason) {
7329 case EXIT_REASON_EXCEPTION_NMI:
7330 if (!is_exception(intr_info))
7331 return 0;
7332 else if (is_page_fault(intr_info))
7333 return enable_ept;
e504c909 7334 else if (is_no_device(intr_info) &&
ccf9844e 7335 !(vmcs12->guest_cr0 & X86_CR0_TS))
e504c909 7336 return 0;
644d711a
NHE		 7337 return vmcs12->exception_bitmap &
7338 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
7339 case EXIT_REASON_EXTERNAL_INTERRUPT:
7340 return 0;
7341 case EXIT_REASON_TRIPLE_FAULT:
7342 return 1;
7343 case EXIT_REASON_PENDING_INTERRUPT:
3b656cf7 7344 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
644d711a 7345 case EXIT_REASON_NMI_WINDOW:
3b656cf7 7346 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
644d711a
NHE		 7347 case EXIT_REASON_TASK_SWITCH:
7348 return 1;
7349 case EXIT_REASON_CPUID:
bc613494
MT		 7350 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
7351 return 0;
644d711a
NHE		 7352 return 1;
7353 case EXIT_REASON_HLT:
7354 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
7355 case EXIT_REASON_INVD:
7356 return 1;
7357 case EXIT_REASON_INVLPG:
7358 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7359 case EXIT_REASON_RDPMC:
7360 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
7361 case EXIT_REASON_RDTSC:
7362 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7363 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7364 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7365 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7366 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7367 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
a642fc30 7368 case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
644d711a
NHE		 7369 /*
7370 * VMX instructions trap unconditionally. This allows L1 to
7371 * emulate them for its L2 guest, i.e., allows 3-level nesting!
7372 */
7373 return 1;
7374 case EXIT_REASON_CR_ACCESS:
7375 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7376 case EXIT_REASON_DR_ACCESS:
7377 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7378 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 7379 return nested_vmx_exit_handled_io(vcpu, vmcs12);
644d711a
NHE		 7380 case EXIT_REASON_MSR_READ:
7381 case EXIT_REASON_MSR_WRITE:
7382 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7383 case EXIT_REASON_INVALID_STATE:
7384 return 1;
7385 case EXIT_REASON_MWAIT_INSTRUCTION:
7386 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
7387 case EXIT_REASON_MONITOR_INSTRUCTION:
7388 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7389 case EXIT_REASON_PAUSE_INSTRUCTION:
7390 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
7391 nested_cpu_has2(vmcs12,
7392 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
7393 case EXIT_REASON_MCE_DURING_VMENTRY:
7394 return 0;
7395 case EXIT_REASON_TPR_BELOW_THRESHOLD:
a7c0b07d 7396 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
644d711a
NHE		 7397 case EXIT_REASON_APIC_ACCESS:
7398 return nested_cpu_has2(vmcs12,
7399 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
7400 case EXIT_REASON_EPT_VIOLATION:
2b1be677
NHE		 7401 /*
7402 * L0 always deals with the EPT violation. If nested EPT is
7403 * used, and the nested mmu code discovers that the address is
7404 * missing in the guest EPT table (EPT12), the EPT violation
7405 * will be injected with nested_ept_inject_page_fault()
7406 */
7407 return 0;
644d711a 7408 case EXIT_REASON_EPT_MISCONFIG:
2b1be677
NHE		 7409 /*
7410 * L2 never uses directly L1's EPT, but rather L0's own EPT
7411 * table (shadow on EPT) or a merged EPT table that L0 built
7412 * (EPT on EPT). So any problems with the structure of the
7413 * table is L0's fault.
7414 */
644d711a
NHE		 7415 return 0;
7416 case EXIT_REASON_WBINVD:
7417 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
7418 case EXIT_REASON_XSETBV:
7419 return 1;
81dc01f7
WL		 7420 case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
7421 /*
7422 * This should never happen, since it is not possible to
7423 * set XSS to a non-zero value---neither in L1 nor in L2.
7424 * If if it were, XSS would have to be checked against
7425 * the XSS exit bitmap in vmcs12.
7426 */
7427 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
644d711a
NHE		 7428 default:
7429 return 1;
7430 }
7431}
7432
586f9607
AK		 7433static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
7434{
7435 *info1 = vmcs_readl(EXIT_QUALIFICATION);
7436 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
7437}
7438
843e4330
KH		 7439static int vmx_enable_pml(struct vcpu_vmx *vmx)
7440{
7441 struct page *pml_pg;
7442 u32 exec_control;
7443
7444 pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
7445 if (!pml_pg)
7446 return -ENOMEM;
7447
7448 vmx->pml_pg = pml_pg;
7449
7450 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
7451 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7452
7453 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7454 exec_control |= SECONDARY_EXEC_ENABLE_PML;
7455 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7456
7457 return 0;
7458}
7459
7460static void vmx_disable_pml(struct vcpu_vmx *vmx)
7461{
7462 u32 exec_control;
7463
7464 ASSERT(vmx->pml_pg);
7465 __free_page(vmx->pml_pg);
7466 vmx->pml_pg = NULL;
7467
7468 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7469 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
7470 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7471}
7472
7473static void vmx_flush_pml_buffer(struct vcpu_vmx *vmx)
7474{
7475 struct kvm *kvm = vmx->vcpu.kvm;
7476 u64 *pml_buf;
7477 u16 pml_idx;
7478
7479 pml_idx = vmcs_read16(GUEST_PML_INDEX);
7480
7481 /* Do nothing if PML buffer is empty */
7482 if (pml_idx == (PML_ENTITY_NUM - 1))
7483 return;
7484
7485 /* PML index always points to next available PML buffer entity */
7486 if (pml_idx >= PML_ENTITY_NUM)
7487 pml_idx = 0;
7488 else
7489 pml_idx++;
7490
7491 pml_buf = page_address(vmx->pml_pg);
7492 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
7493 u64 gpa;
7494
7495 gpa = pml_buf[pml_idx];
7496 WARN_ON(gpa & (PAGE_SIZE - 1));
7497 mark_page_dirty(kvm, gpa >> PAGE_SHIFT);
7498 }
7499
7500 /* reset PML index */
7501 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7502}
7503
7504/*
7505 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
7506 * Called before reporting dirty_bitmap to userspace.
7507 */
7508static void kvm_flush_pml_buffers(struct kvm *kvm)
7509{
7510 int i;
7511 struct kvm_vcpu *vcpu;
7512 /*
7513 * We only need to kick vcpu out of guest mode here, as PML buffer
7514 * is flushed at beginning of all VMEXITs, and it's obvious that only
7515 * vcpus running in guest are possible to have unflushed GPAs in PML
7516 * buffer.
7517 */
7518 kvm_for_each_vcpu(i, vcpu, kvm)
7519 kvm_vcpu_kick(vcpu);
7520}
7521
6aa8b732
AK		 7522/*
7523 * The guest has exited. See if we can fix it or if we need userspace
7524 * assistance.
7525 */
851ba692 7526static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 7527{
29bd8a78 7528 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 7529 u32 exit_reason = vmx->exit_reason;
1155f76a 7530 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 7531
843e4330
KH		 7532 /*
7533 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
7534 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
7535 * querying dirty_bitmap, we only need to kick all vcpus out of guest
7536 * mode as if vcpus is in root mode, the PML buffer must has been
7537 * flushed already.
7538 */
7539 if (enable_pml)
7540 vmx_flush_pml_buffer(vmx);
7541
80ced186 7542 /* If guest state is invalid, start emulating */
14168786 7543 if (vmx->emulation_required)
80ced186 7544 return handle_invalid_guest_state(vcpu);
1d5a4d9b 7545
644d711a 7546 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
533558bc
JK		 7547 nested_vmx_vmexit(vcpu, exit_reason,
7548 vmcs_read32(VM_EXIT_INTR_INFO),
7549 vmcs_readl(EXIT_QUALIFICATION));
644d711a
NHE		 7550 return 1;
7551 }
7552
5120702e
MG		 7553 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
7554 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7555 vcpu->run->fail_entry.hardware_entry_failure_reason
7556 = exit_reason;
7557 return 0;
7558 }
7559
29bd8a78 7560 if (unlikely(vmx->fail)) {
851ba692
AK		 7561 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7562 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 7563 = vmcs_read32(VM_INSTRUCTION_ERROR);
7564 return 0;
7565 }
6aa8b732 7566
b9bf6882
XG		 7567 /*
7568 * Note:
7569 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
7570 * delivery event since it indicates guest is accessing MMIO.
7571 * The vm-exit can be triggered again after return to guest that
7572 * will cause infinite loop.
7573 */
d77c26fc 7574 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 7575 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 7576 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 7577 exit_reason != EXIT_REASON_TASK_SWITCH)) {
7578 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7579 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
7580 vcpu->run->internal.ndata = 2;
7581 vcpu->run->internal.data[0] = vectoring_info;
7582 vcpu->run->internal.data[1] = exit_reason;
7583 return 0;
7584 }
3b86cd99 7585
644d711a
NHE		 7586 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
7587 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
f5c4368f 7588 get_vmcs12(vcpu))))) {
c4282df9 7589 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 7590 vmx->soft_vnmi_blocked = 0;
3b86cd99 7591 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 7592 vcpu->arch.nmi_pending) {
3b86cd99
JK		 7593 /*
7594 * This CPU don't support us in finding the end of an
7595 * NMI-blocked window if the guest runs with IRQs
7596 * disabled. So we pull the trigger after 1 s of
7597 * futile waiting, but inform the user about this.
7598 */
7599 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
7600 "state on VCPU %d after 1 s timeout\n",
7601 __func__, vcpu->vcpu_id);
7602 vmx->soft_vnmi_blocked = 0;
3b86cd99 7603 }
3b86cd99
JK		 7604 }
7605
6aa8b732
AK		 7606 if (exit_reason < kvm_vmx_max_exit_handlers
7607 && kvm_vmx_exit_handlers[exit_reason])
851ba692 7608 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 7609 else {
2bc19dc3
MT		 7610 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
7611 kvm_queue_exception(vcpu, UD_VECTOR);
7612 return 1;
6aa8b732 7613 }
6aa8b732
AK		 7614}
7615
95ba8273 7616static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 7617{
a7c0b07d
WL		 7618 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7619
7620 if (is_guest_mode(vcpu) &&
7621 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
7622 return;
7623
95ba8273 7624 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 7625 vmcs_write32(TPR_THRESHOLD, 0);
7626 return;
7627 }
7628
95ba8273 7629 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 7630}
7631
8d14695f
YZ		 7632static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
7633{
7634 u32 sec_exec_control;
7635
7636 /*
7637 * There is not point to enable virtualize x2apic without enable
7638 * apicv
7639 */
c7c9c56c
YZ		 7640 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
7641 !vmx_vm_has_apicv(vcpu->kvm))
8d14695f
YZ		 7642 return;
7643
7644 if (!vm_need_tpr_shadow(vcpu->kvm))
7645 return;
7646
7647 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7648
7649 if (set) {
7650 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7651 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7652 } else {
7653 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7654 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7655 }
7656 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
7657
7658 vmx_set_msr_bitmap(vcpu);
7659}
7660
38b99173
TC		 7661static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
7662{
7663 struct vcpu_vmx *vmx = to_vmx(vcpu);
7664
7665 /*
7666 * Currently we do not handle the nested case where L2 has an
7667 * APIC access page of its own; that page is still pinned.
7668 * Hence, we skip the case where the VCPU is in guest mode _and_
7669 * L1 prepared an APIC access page for L2.
7670 *
7671 * For the case where L1 and L2 share the same APIC access page
7672 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
7673 * in the vmcs12), this function will only update either the vmcs01
7674 * or the vmcs02. If the former, the vmcs02 will be updated by
7675 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
7676 * the next L2->L1 exit.
7677 */
7678 if (!is_guest_mode(vcpu) ||
7679 !nested_cpu_has2(vmx->nested.current_vmcs12,
7680 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
7681 vmcs_write64(APIC_ACCESS_ADDR, hpa);
7682}
7683
c7c9c56c
YZ		 7684static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
7685{
7686 u16 status;
7687 u8 old;
7688
c7c9c56c
YZ		 7689 if (isr == -1)
7690 isr = 0;
7691
7692 status = vmcs_read16(GUEST_INTR_STATUS);
7693 old = status >> 8;
7694 if (isr != old) {
7695 status &= 0xff;
7696 status |= isr << 8;
7697 vmcs_write16(GUEST_INTR_STATUS, status);
7698 }
7699}
7700
7701static void vmx_set_rvi(int vector)
7702{
7703 u16 status;
7704 u8 old;
7705
4114c27d
WW		 7706 if (vector == -1)
7707 vector = 0;
7708
c7c9c56c
YZ		 7709 status = vmcs_read16(GUEST_INTR_STATUS);
7710 old = (u8)status & 0xff;
7711 if ((u8)vector != old) {
7712 status &= ~0xff;
7713 status |= (u8)vector;
7714 vmcs_write16(GUEST_INTR_STATUS, status);
7715 }
7716}
7717
7718static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
7719{
4114c27d
WW		 7720 if (!is_guest_mode(vcpu)) {
7721 vmx_set_rvi(max_irr);
7722 return;
7723 }
7724
c7c9c56c
YZ		 7725 if (max_irr == -1)
7726 return;
7727
963fee16 7728 /*
4114c27d
WW		 7729 * In guest mode. If a vmexit is needed, vmx_check_nested_events
7730 * handles it.
963fee16 7731 */
4114c27d 7732 if (nested_exit_on_intr(vcpu))
963fee16
WL		 7733 return;
7734
963fee16 7735 /*
4114c27d 7736 * Else, fall back to pre-APICv interrupt injection since L2
963fee16
WL		 7737 * is run without virtual interrupt delivery.
7738 */
7739 if (!kvm_event_needs_reinjection(vcpu) &&
7740 vmx_interrupt_allowed(vcpu)) {
7741 kvm_queue_interrupt(vcpu, max_irr, false);
7742 vmx_inject_irq(vcpu);
7743 }
c7c9c56c
YZ		 7744}
7745
7746static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
7747{
3d81bc7e
YZ		 7748 if (!vmx_vm_has_apicv(vcpu->kvm))
7749 return;
7750
c7c9c56c
YZ		 7751 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
7752 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
7753 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
7754 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
7755}
7756
51aa01d1 7757static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 7758{
00eba012
AK		 7759 u32 exit_intr_info;
7760
7761 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
7762 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
7763 return;
7764
c5ca8e57 7765 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 7766 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 7767
7768 /* Handle machine checks before interrupts are enabled */
00eba012 7769 if (is_machine_check(exit_intr_info))
a0861c02
AK		 7770 kvm_machine_check();
7771
20f65983 7772 /* We need to handle NMIs before interrupts are enabled */
00eba012 7773 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 7774 (exit_intr_info & INTR_INFO_VALID_MASK)) {
7775 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 7776 asm("int $2");
ff9d07a0
ZY		 7777 kvm_after_handle_nmi(&vmx->vcpu);
7778 }
51aa01d1 7779}
20f65983 7780
a547c6db
YZ		 7781static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
7782{
7783 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7784
7785 /*
7786 * If external interrupt exists, IF bit is set in rflags/eflags on the
7787 * interrupt stack frame, and interrupt will be enabled on a return
7788 * from interrupt handler.
7789 */
7790 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
7791 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
7792 unsigned int vector;
7793 unsigned long entry;
7794 gate_desc *desc;
7795 struct vcpu_vmx *vmx = to_vmx(vcpu);
7796#ifdef CONFIG_X86_64
7797 unsigned long tmp;
7798#endif
7799
7800 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7801 desc = (gate_desc *)vmx->host_idt_base + vector;
7802 entry = gate_offset(*desc);
7803 asm volatile(
7804#ifdef CONFIG_X86_64
7805 "mov %%" _ASM_SP ", %[sp]\n\t"
7806 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
7807 "push $%c[ss]\n\t"
7808 "push %[sp]\n\t"
7809#endif
7810 "pushf\n\t"
7811 "orl $0x200, (%%" _ASM_SP ")\n\t"
7812 __ASM_SIZE(push) " $%c[cs]\n\t"
7813 "call *%[entry]\n\t"
7814 :
7815#ifdef CONFIG_X86_64
7816 [sp]"=&r"(tmp)
7817#endif
7818 :
7819 [entry]"r"(entry),
7820 [ss]"i"(__KERNEL_DS),
7821 [cs]"i"(__KERNEL_CS)
7822 );
7823 } else
7824 local_irq_enable();
7825}
7826
da8999d3
LJ		 7827static bool vmx_mpx_supported(void)
7828{
7829 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
7830 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
7831}
7832
55412b2e
WL		 7833static bool vmx_xsaves_supported(void)
7834{
7835 return vmcs_config.cpu_based_2nd_exec_ctrl &
7836 SECONDARY_EXEC_XSAVES;
7837}
7838
51aa01d1
AK		 7839static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
7840{
c5ca8e57 7841 u32 exit_intr_info;
51aa01d1
AK		 7842 bool unblock_nmi;
7843 u8 vector;
7844 bool idtv_info_valid;
7845
7846 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 7847
cf393f75 7848 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 7849 if (vmx->nmi_known_unmasked)
7850 return;
c5ca8e57
AK		 7851 /*
7852 * Can't use vmx->exit_intr_info since we're not sure what
7853 * the exit reason is.
7854 */
7855 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 7856 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
7857 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7858 /*
7b4a25cb 7859 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 7860 * Re-set bit "block by NMI" before VM entry if vmexit caused by
7861 * a guest IRET fault.
7b4a25cb
GN		 7862 * SDM 3: 23.2.2 (September 2008)
7863 * Bit 12 is undefined in any of the following cases:
7864 * If the VM exit sets the valid bit in the IDT-vectoring
7865 * information field.
7866 * If the VM exit is due to a double fault.
cf393f75 7867 */
7b4a25cb
GN		 7868 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
7869 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 7870 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7871 GUEST_INTR_STATE_NMI);
9d58b931
AK		 7872 else
7873 vmx->nmi_known_unmasked =
7874 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
7875 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 7876 } else if (unlikely(vmx->soft_vnmi_blocked))
7877 vmx->vnmi_blocked_time +=
7878 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 7879}
7880
3ab66e8a 7881static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK		 7882 u32 idt_vectoring_info,
7883 int instr_len_field,
7884 int error_code_field)
51aa01d1 7885{
51aa01d1
AK		 7886 u8 vector;
7887 int type;
7888 bool idtv_info_valid;
7889
7890 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 7891
3ab66e8a
JK		 7892 vcpu->arch.nmi_injected = false;
7893 kvm_clear_exception_queue(vcpu);
7894 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN		 7895
7896 if (!idtv_info_valid)
7897 return;
7898
3ab66e8a 7899 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 7900
668f612f
AK		 7901 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
7902 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 7903
64a7ec06 7904 switch (type) {
37b96e98 7905 case INTR_TYPE_NMI_INTR:
3ab66e8a 7906 vcpu->arch.nmi_injected = true;
668f612f 7907 /*
7b4a25cb 7908 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 7909 * Clear bit "block by NMI" before VM entry if a NMI
7910 * delivery faulted.
668f612f 7911 */
3ab66e8a 7912 vmx_set_nmi_mask(vcpu, false);
37b96e98 7913 break;
37b96e98 7914 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 7915 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN		 7916 /* fall through */
7917 case INTR_TYPE_HARD_EXCEPTION:
35920a35 7918 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 7919 u32 err = vmcs_read32(error_code_field);
851eb667 7920 kvm_requeue_exception_e(vcpu, vector, err);
35920a35 7921 } else
851eb667 7922 kvm_requeue_exception(vcpu, vector);
37b96e98 7923 break;
66fd3f7f 7924 case INTR_TYPE_SOFT_INTR:
3ab66e8a 7925 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 7926 /* fall through */
37b96e98 7927 case INTR_TYPE_EXT_INTR:
3ab66e8a 7928 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 7929 break;
7930 default:
7931 break;
f7d9238f 7932 }
cf393f75
AK		 7933}
7934
83422e17
AK		 7935static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
7936{
3ab66e8a 7937 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK		 7938 VM_EXIT_INSTRUCTION_LEN,
7939 IDT_VECTORING_ERROR_CODE);
7940}
7941
b463a6f7
AK		 7942static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
7943{
3ab66e8a 7944 __vmx_complete_interrupts(vcpu,
b463a6f7
AK		 7945 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7946 VM_ENTRY_INSTRUCTION_LEN,
7947 VM_ENTRY_EXCEPTION_ERROR_CODE);
7948
7949 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
7950}
7951
d7cd9796
GN		 7952static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
7953{
7954 int i, nr_msrs;
7955 struct perf_guest_switch_msr *msrs;
7956
7957 msrs = perf_guest_get_msrs(&nr_msrs);
7958
7959 if (!msrs)
7960 return;
7961
7962 for (i = 0; i < nr_msrs; i++)
7963 if (msrs[i].host == msrs[i].guest)
7964 clear_atomic_switch_msr(vmx, msrs[i].msr);
7965 else
7966 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
7967 msrs[i].host);
7968}
7969
a3b5ba49 7970static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 7971{
a2fa3e9f 7972 struct vcpu_vmx *vmx = to_vmx(vcpu);
d974baa3 7973 unsigned long debugctlmsr, cr4;
104f226b
AK		 7974
7975 /* Record the guest's net vcpu time for enforced NMI injections. */
7976 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
7977 vmx->entry_time = ktime_get();
7978
7979 /* Don't enter VMX if guest state is invalid, let the exit handler
7980 start emulation until we arrive back to a valid state */
14168786 7981 if (vmx->emulation_required)
104f226b
AK		 7982 return;
7983
a7653ecd
RK		 7984 if (vmx->ple_window_dirty) {
7985 vmx->ple_window_dirty = false;
7986 vmcs_write32(PLE_WINDOW, vmx->ple_window);
7987 }
7988
012f83cb
AG		 7989 if (vmx->nested.sync_shadow_vmcs) {
7990 copy_vmcs12_to_shadow(vmx);
7991 vmx->nested.sync_shadow_vmcs = false;
7992 }
7993
104f226b
AK		 7994 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
7995 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
7996 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
7997 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
7998
d974baa3
AL		 7999 cr4 = read_cr4();
8000 if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8001 vmcs_writel(HOST_CR4, cr4);
8002 vmx->host_state.vmcs_host_cr4 = cr4;
8003 }
8004
104f226b
AK		 8005 /* When single-stepping over STI and MOV SS, we must clear the
8006 * corresponding interruptibility bits in the guest state. Otherwise
8007 * vmentry fails as it then expects bit 14 (BS) in pending debug
8008 * exceptions being set, but that's not correct for the guest debugging
8009 * case. */
8010 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8011 vmx_set_interrupt_shadow(vcpu, 0);
8012
d7cd9796 8013 atomic_switch_perf_msrs(vmx);
2a7921b7 8014 debugctlmsr = get_debugctlmsr();
d7cd9796 8015
d462b819 8016 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 8017 asm(
6aa8b732 8018 /* Store host registers */
b188c81f
AK		 8019 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8020 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8021 "push %%" _ASM_CX " \n\t"
8022 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 8023 "je 1f \n\t"
b188c81f 8024 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 8025 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 8026 "1: \n\t"
d3edefc0 8027 /* Reload cr2 if changed */
b188c81f
AK		 8028 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8029 "mov %%cr2, %%" _ASM_DX " \n\t"
8030 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 8031 "je 2f \n\t"
b188c81f 8032 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 8033 "2: \n\t"
6aa8b732 8034 /* Check if vmlaunch of vmresume is needed */
e08aa78a 8035 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 8036 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 8037 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8038 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8039 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8040 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8041 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8042 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 8043#ifdef CONFIG_X86_64
e08aa78a
AK		 8044 "mov %c[r8](%0), %%r8 \n\t"
8045 "mov %c[r9](%0), %%r9 \n\t"
8046 "mov %c[r10](%0), %%r10 \n\t"
8047 "mov %c[r11](%0), %%r11 \n\t"
8048 "mov %c[r12](%0), %%r12 \n\t"
8049 "mov %c[r13](%0), %%r13 \n\t"
8050 "mov %c[r14](%0), %%r14 \n\t"
8051 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 8052#endif
b188c81f 8053 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 8054
6aa8b732 8055 /* Enter guest mode */
83287ea4 8056 "jne 1f \n\t"
4ecac3fd 8057 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 8058 "jmp 2f \n\t"
8059 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8060 "2: "
6aa8b732 8061 /* Save guest registers, load host registers, keep flags */
b188c81f 8062 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 8063 "pop %0 \n\t"
b188c81f
AK		 8064 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8065 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8066 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8067 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8068 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8069 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8070 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 8071#ifdef CONFIG_X86_64
e08aa78a
AK		 8072 "mov %%r8, %c[r8](%0) \n\t"
8073 "mov %%r9, %c[r9](%0) \n\t"
8074 "mov %%r10, %c[r10](%0) \n\t"
8075 "mov %%r11, %c[r11](%0) \n\t"
8076 "mov %%r12, %c[r12](%0) \n\t"
8077 "mov %%r13, %c[r13](%0) \n\t"
8078 "mov %%r14, %c[r14](%0) \n\t"
8079 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 8080#endif
b188c81f
AK		 8081 "mov %%cr2, %%" _ASM_AX " \n\t"
8082 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 8083
b188c81f 8084 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 8085 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 8086 ".pushsection .rodata \n\t"
8087 ".global vmx_return \n\t"
8088 "vmx_return: " _ASM_PTR " 2b \n\t"
8089 ".popsection"
e08aa78a 8090 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 8091 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 8092 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 8093 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 8094 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8095 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8096 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8097 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8098 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8099 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
8100 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 8101#ifdef CONFIG_X86_64
ad312c7c
ZX		 8102 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
8103 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
8104 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
8105 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
8106 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
8107 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
8108 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
8109 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 8110#endif
40712fae
AK		 8111 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
8112 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 8113 : "cc", "memory"
8114#ifdef CONFIG_X86_64
b188c81f 8115 , "rax", "rbx", "rdi", "rsi"
c2036300 8116 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 8117#else
8118 , "eax", "ebx", "edi", "esi"
c2036300
LV		 8119#endif
8120 );
6aa8b732 8121
2a7921b7
GN		 8122 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8123 if (debugctlmsr)
8124 update_debugctlmsr(debugctlmsr);
8125
aa67f609
AK		 8126#ifndef CONFIG_X86_64
8127 /*
8128 * The sysexit path does not restore ds/es, so we must set them to
8129 * a reasonable value ourselves.
8130 *
8131 * We can't defer this to vmx_load_host_state() since that function
8132 * may be executed in interrupt context, which saves and restore segments
8133 * around it, nullifying its effect.
8134 */
8135 loadsegment(ds, __USER_DS);
8136 loadsegment(es, __USER_DS);
8137#endif
8138
6de4f3ad 8139 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 8140 | (1 << VCPU_EXREG_RFLAGS)
aff48baa 8141 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 8142 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 8143 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 8144 vcpu->arch.regs_dirty = 0;
8145
1155f76a
AK		 8146 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
8147
d462b819 8148 vmx->loaded_vmcs->launched = 1;
1b6269db 8149
51aa01d1 8150 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 8151 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1 8152
e0b890d3
GN		 8153 /*
8154 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8155 * we did not inject a still-pending event to L1 now because of
8156 * nested_run_pending, we need to re-enable this bit.
8157 */
8158 if (vmx->nested.nested_run_pending)
8159 kvm_make_request(KVM_REQ_EVENT, vcpu);
8160
8161 vmx->nested.nested_run_pending = 0;
8162
51aa01d1
AK		 8163 vmx_complete_atomic_exit(vmx);
8164 vmx_recover_nmi_blocking(vmx);
cf393f75 8165 vmx_complete_interrupts(vmx);
6aa8b732
AK		 8166}
8167
4fa7734c
PB		 8168static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
8169{
8170 struct vcpu_vmx *vmx = to_vmx(vcpu);
8171 int cpu;
8172
8173 if (vmx->loaded_vmcs == &vmx->vmcs01)
8174 return;
8175
8176 cpu = get_cpu();
8177 vmx->loaded_vmcs = &vmx->vmcs01;
8178 vmx_vcpu_put(vcpu);
8179 vmx_vcpu_load(vcpu, cpu);
8180 vcpu->cpu = cpu;
8181 put_cpu();
8182}
8183
6aa8b732
AK		 8184static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
8185{
fb3f0f51
RR		 8186 struct vcpu_vmx *vmx = to_vmx(vcpu);
8187
843e4330
KH		 8188 if (enable_pml)
8189 vmx_disable_pml(vmx);
cdbecfc3 8190 free_vpid(vmx);
4fa7734c
PB		 8191 leave_guest_mode(vcpu);
8192 vmx_load_vmcs01(vcpu);
26a865f4 8193 free_nested(vmx);
4fa7734c 8194 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 8195 kfree(vmx->guest_msrs);
8196 kvm_vcpu_uninit(vcpu);
a4770347 8197 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 8198}
8199
fb3f0f51 8200static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 8201{
fb3f0f51 8202 int err;
c16f862d 8203 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 8204 int cpu;
6aa8b732 8205
a2fa3e9f 8206 if (!vmx)
fb3f0f51
RR		 8207 return ERR_PTR(-ENOMEM);
8208
2384d2b3
SY		 8209 allocate_vpid(vmx);
8210
fb3f0f51
RR		 8211 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
8212 if (err)
8213 goto free_vcpu;
965b58a5 8214
a2fa3e9f 8215 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
03916db9
PB		 8216 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
8217 > PAGE_SIZE);
0123be42 8218
be6d05cf 8219 err = -ENOMEM;
fb3f0f51 8220 if (!vmx->guest_msrs) {
fb3f0f51
RR		 8221 goto uninit_vcpu;
8222 }
965b58a5 8223
d462b819
NHE		 8224 vmx->loaded_vmcs = &vmx->vmcs01;
8225 vmx->loaded_vmcs->vmcs = alloc_vmcs();
8226 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 8227 goto free_msrs;
d462b819
NHE		 8228 if (!vmm_exclusive)
8229 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
8230 loaded_vmcs_init(vmx->loaded_vmcs);
8231 if (!vmm_exclusive)
8232 kvm_cpu_vmxoff();
a2fa3e9f 8233
15ad7146
AK		 8234 cpu = get_cpu();
8235 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 8236 vmx->vcpu.cpu = cpu;
8b9cf98c 8237 err = vmx_vcpu_setup(vmx);
fb3f0f51 8238 vmx_vcpu_put(&vmx->vcpu);
15ad7146 8239 put_cpu();
fb3f0f51
RR		 8240 if (err)
8241 goto free_vmcs;
a63cb560 8242 if (vm_need_virtualize_apic_accesses(kvm)) {
be6d05cf
JK		 8243 err = alloc_apic_access_page(kvm);
8244 if (err)
5e4a0b3c 8245 goto free_vmcs;
a63cb560 8246 }
fb3f0f51 8247
b927a3ce
SY		 8248 if (enable_ept) {
8249 if (!kvm->arch.ept_identity_map_addr)
8250 kvm->arch.ept_identity_map_addr =
8251 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
f51770ed
TC		 8252 err = init_rmode_identity_map(kvm);
8253 if (err)
93ea5388 8254 goto free_vmcs;
b927a3ce 8255 }
b7ebfb05 8256
a9d30f33
NHE		 8257 vmx->nested.current_vmptr = -1ull;
8258 vmx->nested.current_vmcs12 = NULL;
8259
843e4330
KH		 8260 /*
8261 * If PML is turned on, failure on enabling PML just results in failure
8262 * of creating the vcpu, therefore we can simplify PML logic (by
8263 * avoiding dealing with cases, such as enabling PML partially on vcpus
8264 * for the guest, etc.
8265 */
8266 if (enable_pml) {
8267 err = vmx_enable_pml(vmx);
8268 if (err)
8269 goto free_vmcs;
8270 }
8271
fb3f0f51
RR		 8272 return &vmx->vcpu;
8273
8274free_vmcs:
5f3fbc34 8275 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 8276free_msrs:
fb3f0f51
RR		 8277 kfree(vmx->guest_msrs);
8278uninit_vcpu:
8279 kvm_vcpu_uninit(&vmx->vcpu);
8280free_vcpu:
cdbecfc3 8281 free_vpid(vmx);
a4770347 8282 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 8283 return ERR_PTR(err);
6aa8b732
AK		 8284}
8285
002c7f7c
YS		 8286static void __init vmx_check_processor_compat(void *rtn)
8287{
8288 struct vmcs_config vmcs_conf;
8289
8290 *(int *)rtn = 0;
8291 if (setup_vmcs_config(&vmcs_conf) < 0)
8292 *(int *)rtn = -EIO;
8293 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
8294 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
8295 smp_processor_id());
8296 *(int *)rtn = -EIO;
8297 }
8298}
8299
67253af5
SY		 8300static int get_ept_level(void)
8301{
8302 return VMX_EPT_DEFAULT_GAW + 1;
8303}
8304
4b12f0de 8305static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 8306{
4b12f0de
SY		 8307 u64 ret;
8308
522c68c4
SY		 8309 /* For VT-d and EPT combination
8310 * 1. MMIO: always map as UC
8311 * 2. EPT with VT-d:
8312 * a. VT-d without snooping control feature: can't guarantee the
8313 * result, try to trust guest.
8314 * b. VT-d with snooping control feature: snooping control feature of
8315 * VT-d engine can guarantee the cache correctness. Just set it
8316 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 8317 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 8318 * consistent with host MTRR
8319 */
4b12f0de
SY		 8320 if (is_mmio)
8321 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
e0f0bbc5 8322 else if (kvm_arch_has_noncoherent_dma(vcpu->kvm))
522c68c4
SY		 8323 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
8324 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 8325 else
522c68c4 8326 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 8327 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 8328
8329 return ret;
64d4d521
SY		 8330}
8331
17cc3935 8332static int vmx_get_lpage_level(void)
344f414f 8333{
878403b7
SY		 8334 if (enable_ept && !cpu_has_vmx_ept_1g_page())
8335 return PT_DIRECTORY_LEVEL;
8336 else
8337 /* For shadow and EPT supported 1GB page */
8338 return PT_PDPE_LEVEL;
344f414f
JR		 8339}
8340
0e851880
SY		 8341static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
8342{
4e47c7a6
SY		 8343 struct kvm_cpuid_entry2 *best;
8344 struct vcpu_vmx *vmx = to_vmx(vcpu);
8345 u32 exec_control;
8346
8347 vmx->rdtscp_enabled = false;
8348 if (vmx_rdtscp_supported()) {
8349 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8350 if (exec_control & SECONDARY_EXEC_RDTSCP) {
8351 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
8352 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
8353 vmx->rdtscp_enabled = true;
8354 else {
8355 exec_control &= ~SECONDARY_EXEC_RDTSCP;
8356 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8357 exec_control);
8358 }
8359 }
8360 }
ad756a16 8361
ad756a16
MJ		 8362 /* Exposing INVPCID only when PCID is exposed */
8363 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
8364 if (vmx_invpcid_supported() &&
4f977045 8365 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
ad756a16 8366 guest_cpuid_has_pcid(vcpu)) {
29282fde 8367 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
ad756a16
MJ		 8368 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
8369 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8370 exec_control);
8371 } else {
29282fde
TI		 8372 if (cpu_has_secondary_exec_ctrls()) {
8373 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8374 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
8375 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8376 exec_control);
8377 }
ad756a16 8378 if (best)
4f977045 8379 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 8380 }
0e851880
SY		 8381}
8382
d4330ef2
JR		 8383static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
8384{
7b8050f5
NHE		 8385 if (func == 1 && nested)
8386 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 8387}
8388
25d92081
YZ		 8389static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
8390 struct x86_exception *fault)
8391{
533558bc
JK		 8392 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8393 u32 exit_reason;
25d92081
YZ		 8394
8395 if (fault->error_code & PFERR_RSVD_MASK)
533558bc 8396 exit_reason = EXIT_REASON_EPT_MISCONFIG;
25d92081 8397 else
533558bc
JK		 8398 exit_reason = EXIT_REASON_EPT_VIOLATION;
8399 nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
25d92081
YZ		 8400 vmcs12->guest_physical_address = fault->address;
8401}
8402
155a97a3
NHE		 8403/* Callbacks for nested_ept_init_mmu_context: */
8404
8405static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
8406{
8407 /* return the page table to be shadowed - in our case, EPT12 */
8408 return get_vmcs12(vcpu)->ept_pointer;
8409}
8410
8a3c1a33 8411static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
155a97a3 8412{
ad896af0
PB		 8413 WARN_ON(mmu_is_nested(vcpu));
8414 kvm_init_shadow_ept_mmu(vcpu,
155a97a3 8415 nested_vmx_ept_caps & VMX_EPT_EXECUTE_ONLY_BIT);
155a97a3
NHE		 8416 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
8417 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
8418 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
8419
8420 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
155a97a3
NHE		 8421}
8422
8423static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
8424{
8425 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
8426}
8427
19d5f10b
EK		 8428static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
8429 u16 error_code)
8430{
8431 bool inequality, bit;
8432
8433 bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
8434 inequality =
8435 (error_code & vmcs12->page_fault_error_code_mask) !=
8436 vmcs12->page_fault_error_code_match;
8437 return inequality ^ bit;
8438}
8439
feaf0c7d
GN		 8440static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
8441 struct x86_exception *fault)
8442{
8443 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8444
8445 WARN_ON(!is_guest_mode(vcpu));
8446
19d5f10b 8447 if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
533558bc
JK		 8448 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
8449 vmcs_read32(VM_EXIT_INTR_INFO),
8450 vmcs_readl(EXIT_QUALIFICATION));
feaf0c7d
GN		 8451 else
8452 kvm_inject_page_fault(vcpu, fault);
8453}
8454
a2bcba50
WL		 8455static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
8456 struct vmcs12 *vmcs12)
8457{
8458 struct vcpu_vmx *vmx = to_vmx(vcpu);
8459
8460 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
a7c0b07d 8461 /* TODO: Also verify bits beyond physical address width are 0 */
a2bcba50 8462 if (!PAGE_ALIGNED(vmcs12->apic_access_addr))
a2bcba50
WL		 8463 return false;
8464
8465 /*
8466 * Translate L1 physical address to host physical
8467 * address for vmcs02. Keep the page pinned, so this
8468 * physical address remains valid. We keep a reference
8469 * to it so we can release it later.
8470 */
8471 if (vmx->nested.apic_access_page) /* shouldn't happen */
8472 nested_release_page(vmx->nested.apic_access_page);
8473 vmx->nested.apic_access_page =
8474 nested_get_page(vcpu, vmcs12->apic_access_addr);
8475 }
a7c0b07d
WL		 8476
8477 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
8478 /* TODO: Also verify bits beyond physical address width are 0 */
8479 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr))
8480 return false;
8481
8482 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
8483 nested_release_page(vmx->nested.virtual_apic_page);
8484 vmx->nested.virtual_apic_page =
8485 nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
8486
8487 /*
8488 * Failing the vm entry is _not_ what the processor does
8489 * but it's basically the only possibility we have.
8490 * We could still enter the guest if CR8 load exits are
8491 * enabled, CR8 store exits are enabled, and virtualize APIC
8492 * access is disabled; in this case the processor would never
8493 * use the TPR shadow and we could simply clear the bit from
8494 * the execution control. But such a configuration is useless,
8495 * so let's keep the code simple.
8496 */
8497 if (!vmx->nested.virtual_apic_page)
8498 return false;
8499 }
8500
a2bcba50
WL		 8501 return true;
8502}
8503
f4124500
JK		 8504static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
8505{
8506 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
8507 struct vcpu_vmx *vmx = to_vmx(vcpu);
8508
8509 if (vcpu->arch.virtual_tsc_khz == 0)
8510 return;
8511
8512 /* Make sure short timeouts reliably trigger an immediate vmexit.
8513 * hrtimer_start does not guarantee this. */
8514 if (preemption_timeout <= 1) {
8515 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
8516 return;
8517 }
8518
8519 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
8520 preemption_timeout *= 1000000;
8521 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
8522 hrtimer_start(&vmx->nested.preemption_timer,
8523 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
8524}
8525
3af18d9c
WV		 8526static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
8527 struct vmcs12 *vmcs12)
8528{
8529 int maxphyaddr;
8530 u64 addr;
8531
8532 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
8533 return 0;
8534
8535 if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
8536 WARN_ON(1);
8537 return -EINVAL;
8538 }
8539 maxphyaddr = cpuid_maxphyaddr(vcpu);
8540
8541 if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
8542 ((addr + PAGE_SIZE) >> maxphyaddr))
8543 return -EINVAL;
8544
8545 return 0;
8546}
8547
8548/*
8549 * Merge L0's and L1's MSR bitmap, return false to indicate that
8550 * we do not use the hardware.
8551 */
8552static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
8553 struct vmcs12 *vmcs12)
8554{
f2b93280
WV		 8555 struct page *page;
8556 unsigned long *msr_bitmap;
8557
8558 if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
8559 return false;
8560
8561 page = nested_get_page(vcpu, vmcs12->msr_bitmap);
8562 if (!page) {
8563 WARN_ON(1);
8564 return false;
8565 }
8566 msr_bitmap = (unsigned long *)kmap(page);
8567 if (!msr_bitmap) {
8568 nested_release_page_clean(page);
8569 WARN_ON(1);
8570 return false;
8571 }
8572
8573 if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
8574 /* TPR is allowed */
8575 nested_vmx_disable_intercept_for_msr(msr_bitmap,
8576 vmx_msr_bitmap_nested,
8577 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
8578 MSR_TYPE_R | MSR_TYPE_W);
8579 } else
8580 __vmx_enable_intercept_for_msr(
8581 vmx_msr_bitmap_nested,
8582 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
8583 MSR_TYPE_R | MSR_TYPE_W);
8584 kunmap(page);
8585 nested_release_page_clean(page);
8586
8587 return true;
8588}
8589
8590static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
8591 struct vmcs12 *vmcs12)
8592{
8593 if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
8594 return 0;
8595
8596 /*
8597 * If virtualize x2apic mode is enabled,
8598 * virtualize apic access must be disabled.
8599 */
8600 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
8601 return -EINVAL;
8602
8603 /* tpr shadow is needed by all apicv features. */
8604 if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8605 return -EINVAL;
8606
8607 return 0;
3af18d9c
WV		 8608}
8609
e9ac033e
EK		 8610static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
8611 unsigned long count_field,
8612 unsigned long addr_field,
8613 int maxphyaddr)
ff651cb6 8614{
e9ac033e
EK		 8615 u64 count, addr;
8616
8617 if (vmcs12_read_any(vcpu, count_field, &count) ||
8618 vmcs12_read_any(vcpu, addr_field, &addr)) {
8619 WARN_ON(1);
8620 return -EINVAL;
8621 }
8622 if (count == 0)
8623 return 0;
8624 if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
8625 (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
8626 pr_warn_ratelimited(
8627 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
8628 addr_field, maxphyaddr, count, addr);
8629 return -EINVAL;
8630 }
8631 return 0;
8632}
8633
8634static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
8635 struct vmcs12 *vmcs12)
8636{
8637 int maxphyaddr;
8638
8639 if (vmcs12->vm_exit_msr_load_count == 0 &&
8640 vmcs12->vm_exit_msr_store_count == 0 &&
8641 vmcs12->vm_entry_msr_load_count == 0)
8642 return 0; /* Fast path */
8643 maxphyaddr = cpuid_maxphyaddr(vcpu);
8644 if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
8645 VM_EXIT_MSR_LOAD_ADDR, maxphyaddr) ||
8646 nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
8647 VM_EXIT_MSR_STORE_ADDR, maxphyaddr) ||
8648 nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
8649 VM_ENTRY_MSR_LOAD_ADDR, maxphyaddr))
8650 return -EINVAL;
8651 return 0;
8652}
8653
8654static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
8655 struct vmx_msr_entry *e)
8656{
8657 /* x2APIC MSR accesses are not allowed */
8658 if (apic_x2apic_mode(vcpu->arch.apic) && e->index >> 8 == 0x8)
8659 return -EINVAL;
8660 if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
8661 e->index == MSR_IA32_UCODE_REV)
8662 return -EINVAL;
8663 if (e->reserved != 0)
ff651cb6
WV		 8664 return -EINVAL;
8665 return 0;
8666}
8667
e9ac033e
EK		 8668static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
8669 struct vmx_msr_entry *e)
ff651cb6
WV		 8670{
8671 if (e->index == MSR_FS_BASE ||
8672 e->index == MSR_GS_BASE ||
e9ac033e
EK		 8673 e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
8674 nested_vmx_msr_check_common(vcpu, e))
8675 return -EINVAL;
8676 return 0;
8677}
8678
8679static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
8680 struct vmx_msr_entry *e)
8681{
8682 if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
8683 nested_vmx_msr_check_common(vcpu, e))
ff651cb6
WV		 8684 return -EINVAL;
8685 return 0;
8686}
8687
8688/*
8689 * Load guest's/host's msr at nested entry/exit.
8690 * return 0 for success, entry index for failure.
8691 */
8692static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
8693{
8694 u32 i;
8695 struct vmx_msr_entry e;
8696 struct msr_data msr;
8697
8698 msr.host_initiated = false;
8699 for (i = 0; i < count; i++) {
e9ac033e
EK		 8700 if (kvm_read_guest(vcpu->kvm, gpa + i * sizeof(e),
8701 &e, sizeof(e))) {
8702 pr_warn_ratelimited(
8703 "%s cannot read MSR entry (%u, 0x%08llx)\n",
8704 __func__, i, gpa + i * sizeof(e));
ff651cb6 8705 goto fail;
e9ac033e
EK		 8706 }
8707 if (nested_vmx_load_msr_check(vcpu, &e)) {
8708 pr_warn_ratelimited(
8709 "%s check failed (%u, 0x%x, 0x%x)\n",
8710 __func__, i, e.index, e.reserved);
8711 goto fail;
8712 }
ff651cb6
WV		 8713 msr.index = e.index;
8714 msr.data = e.value;
e9ac033e
EK		 8715 if (kvm_set_msr(vcpu, &msr)) {
8716 pr_warn_ratelimited(
8717 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
8718 __func__, i, e.index, e.value);
ff651cb6 8719 goto fail;
e9ac033e 8720 }
ff651cb6
WV		 8721 }
8722 return 0;
8723fail:
8724 return i + 1;
8725}
8726
8727static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
8728{
8729 u32 i;
8730 struct vmx_msr_entry e;
8731
8732 for (i = 0; i < count; i++) {
e9ac033e
EK		 8733 if (kvm_read_guest(vcpu->kvm,
8734 gpa + i * sizeof(e),
8735 &e, 2 * sizeof(u32))) {
8736 pr_warn_ratelimited(
8737 "%s cannot read MSR entry (%u, 0x%08llx)\n",
8738 __func__, i, gpa + i * sizeof(e));
ff651cb6 8739 return -EINVAL;
e9ac033e
EK		 8740 }
8741 if (nested_vmx_store_msr_check(vcpu, &e)) {
8742 pr_warn_ratelimited(
8743 "%s check failed (%u, 0x%x, 0x%x)\n",
8744 __func__, i, e.index, e.reserved);
ff651cb6 8745 return -EINVAL;
e9ac033e
EK		 8746 }
8747 if (kvm_get_msr(vcpu, e.index, &e.value)) {
8748 pr_warn_ratelimited(
8749 "%s cannot read MSR (%u, 0x%x)\n",
8750 __func__, i, e.index);
8751 return -EINVAL;
8752 }
8753 if (kvm_write_guest(vcpu->kvm,
8754 gpa + i * sizeof(e) +
ff651cb6 8755 offsetof(struct vmx_msr_entry, value),
e9ac033e
EK		 8756 &e.value, sizeof(e.value))) {
8757 pr_warn_ratelimited(
8758 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
8759 __func__, i, e.index, e.value);
8760 return -EINVAL;
8761 }
ff651cb6
WV		 8762 }
8763 return 0;
8764}
8765
fe3ef05c
NHE		 8766/*
8767 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
8768 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
b4619660 8769 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
fe3ef05c
NHE		 8770 * guest in a way that will both be appropriate to L1's requests, and our
8771 * needs. In addition to modifying the active vmcs (which is vmcs02), this
8772 * function also has additional necessary side-effects, like setting various
8773 * vcpu->arch fields.
8774 */
8775static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8776{
8777 struct vcpu_vmx *vmx = to_vmx(vcpu);
8778 u32 exec_control;
8779
8780 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
8781 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
8782 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
8783 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
8784 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
8785 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
8786 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
8787 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
8788 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
8789 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
8790 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
8791 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
8792 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
8793 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
8794 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
8795 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
8796 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
8797 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
8798 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
8799 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
8800 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
8801 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
8802 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
8803 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
8804 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
8805 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
8806 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
8807 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
8808 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
8809 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
8810 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
8811 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
8812 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
8813 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
8814 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
8815 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
8816
2996fca0
JK		 8817 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
8818 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
8819 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
8820 } else {
8821 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
8822 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
8823 }
fe3ef05c
NHE		 8824 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
8825 vmcs12->vm_entry_intr_info_field);
8826 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
8827 vmcs12->vm_entry_exception_error_code);
8828 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
8829 vmcs12->vm_entry_instruction_len);
8830 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
8831 vmcs12->guest_interruptibility_info);
fe3ef05c 8832 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
63fbf59f 8833 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
fe3ef05c
NHE		 8834 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
8835 vmcs12->guest_pending_dbg_exceptions);
8836 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
8837 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
8838
81dc01f7
WL		 8839 if (nested_cpu_has_xsaves(vmcs12))
8840 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
fe3ef05c
NHE		 8841 vmcs_write64(VMCS_LINK_POINTER, -1ull);
8842
f4124500
JK		 8843 exec_control = vmcs12->pin_based_vm_exec_control;
8844 exec_control |= vmcs_config.pin_based_exec_ctrl;
696dfd95
PB		 8845 exec_control &= ~(PIN_BASED_VMX_PREEMPTION_TIMER |
8846 PIN_BASED_POSTED_INTR);
f4124500 8847 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
fe3ef05c 8848
f4124500
JK		 8849 vmx->nested.preemption_timer_expired = false;
8850 if (nested_cpu_has_preemption_timer(vmcs12))
8851 vmx_start_preemption_timer(vcpu);
0238ea91 8852
fe3ef05c
NHE		 8853 /*
8854 * Whether page-faults are trapped is determined by a combination of
8855 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
8856 * If enable_ept, L0 doesn't care about page faults and we should
8857 * set all of these to L1's desires. However, if !enable_ept, L0 does
8858 * care about (at least some) page faults, and because it is not easy
8859 * (if at all possible?) to merge L0 and L1's desires, we simply ask
8860 * to exit on each and every L2 page fault. This is done by setting
8861 * MASK=MATCH=0 and (see below) EB.PF=1.
8862 * Note that below we don't need special code to set EB.PF beyond the
8863 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
8864 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
8865 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
8866 *
8867 * A problem with this approach (when !enable_ept) is that L1 may be
8868 * injected with more page faults than it asked for. This could have
8869 * caused problems, but in practice existing hypervisors don't care.
8870 * To fix this, we will need to emulate the PFEC checking (on the L1
8871 * page tables), using walk_addr(), when injecting PFs to L1.
8872 */
8873 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
8874 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
8875 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
8876 enable_ept ? vmcs12->page_fault_error_code_match : 0);
8877
8878 if (cpu_has_secondary_exec_ctrls()) {
f4124500 8879 exec_control = vmx_secondary_exec_control(vmx);
fe3ef05c
NHE		 8880 if (!vmx->rdtscp_enabled)
8881 exec_control &= ~SECONDARY_EXEC_RDTSCP;
8882 /* Take the following fields only from vmcs12 */
696dfd95
PB		 8883 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8884 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
8885 SECONDARY_EXEC_APIC_REGISTER_VIRT);
fe3ef05c
NHE		 8886 if (nested_cpu_has(vmcs12,
8887 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
8888 exec_control |= vmcs12->secondary_vm_exec_control;
8889
8890 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
fe3ef05c
NHE		 8891 /*
8892 * If translation failed, no matter: This feature asks
8893 * to exit when accessing the given address, and if it
8894 * can never be accessed, this feature won't do
8895 * anything anyway.
8896 */
8897 if (!vmx->nested.apic_access_page)
8898 exec_control &=
8899 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8900 else
8901 vmcs_write64(APIC_ACCESS_ADDR,
8902 page_to_phys(vmx->nested.apic_access_page));
f2b93280
WV		 8903 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
8904 (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))) {
ca3f257a
JK		 8905 exec_control |=
8906 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
38b99173 8907 kvm_vcpu_reload_apic_access_page(vcpu);
fe3ef05c
NHE		 8908 }
8909
8910 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
8911 }
8912
8913
8914 /*
8915 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
8916 * Some constant fields are set here by vmx_set_constant_host_state().
8917 * Other fields are different per CPU, and will be set later when
8918 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
8919 */
a547c6db 8920 vmx_set_constant_host_state(vmx);
fe3ef05c
NHE		 8921
8922 /*
8923 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
8924 * entry, but only if the current (host) sp changed from the value
8925 * we wrote last (vmx->host_rsp). This cache is no longer relevant
8926 * if we switch vmcs, and rather than hold a separate cache per vmcs,
8927 * here we just force the write to happen on entry.
8928 */
8929 vmx->host_rsp = 0;
8930
8931 exec_control = vmx_exec_control(vmx); /* L0's desires */
8932 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
8933 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
8934 exec_control &= ~CPU_BASED_TPR_SHADOW;
8935 exec_control |= vmcs12->cpu_based_vm_exec_control;
a7c0b07d
WL		 8936
8937 if (exec_control & CPU_BASED_TPR_SHADOW) {
8938 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
8939 page_to_phys(vmx->nested.virtual_apic_page));
8940 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
8941 }
8942
3af18d9c
WV		 8943 if (cpu_has_vmx_msr_bitmap() &&
8944 exec_control & CPU_BASED_USE_MSR_BITMAPS &&
8945 nested_vmx_merge_msr_bitmap(vcpu, vmcs12)) {
8946 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_nested));
8947 } else
8948 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
8949
fe3ef05c 8950 /*
3af18d9c 8951 * Merging of IO bitmap not currently supported.
fe3ef05c
NHE		 8952 * Rather, exit every time.
8953 */
fe3ef05c
NHE		 8954 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
8955 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
8956
8957 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
8958
8959 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
8960 * bitwise-or of what L1 wants to trap for L2, and what we want to
8961 * trap. Note that CR0.TS also needs updating - we do this later.
8962 */
8963 update_exception_bitmap(vcpu);
8964 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
8965 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8966
8049d651
NHE		 8967 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
8968 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
8969 * bits are further modified by vmx_set_efer() below.
8970 */
f4124500 8971 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
8049d651
NHE		 8972
8973 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
8974 * emulated by vmx_set_efer(), below.
8975 */
2961e876 8976 vm_entry_controls_init(vmx,
8049d651
NHE		 8977 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
8978 ~VM_ENTRY_IA32E_MODE) |
fe3ef05c
NHE		 8979 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
8980
44811c02 8981 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
fe3ef05c 8982 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
44811c02
JK		 8983 vcpu->arch.pat = vmcs12->guest_ia32_pat;
8984 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
fe3ef05c
NHE		 8985 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
8986
8987
8988 set_cr4_guest_host_mask(vmx);
8989
36be0b9d
PB		 8990 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
8991 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
8992
27fc51b2
NHE		 8993 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
8994 vmcs_write64(TSC_OFFSET,
8995 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
8996 else
8997 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 8998
8999 if (enable_vpid) {
9000 /*
9001 * Trivially support vpid by letting L2s share their parent
9002 * L1's vpid. TODO: move to a more elaborate solution, giving
9003 * each L2 its own vpid and exposing the vpid feature to L1.
9004 */
9005 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
9006 vmx_flush_tlb(vcpu);
9007 }
9008
155a97a3
NHE		 9009 if (nested_cpu_has_ept(vmcs12)) {
9010 kvm_mmu_unload(vcpu);
9011 nested_ept_init_mmu_context(vcpu);
9012 }
9013
fe3ef05c
NHE		 9014 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
9015 vcpu->arch.efer = vmcs12->guest_ia32_efer;
d1fa0352 9016 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
fe3ef05c
NHE		 9017 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9018 else
9019 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9020 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
9021 vmx_set_efer(vcpu, vcpu->arch.efer);
9022
9023 /*
9024 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
9025 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
9026 * The CR0_READ_SHADOW is what L2 should have expected to read given
9027 * the specifications by L1; It's not enough to take
9028 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
9029 * have more bits than L1 expected.
9030 */
9031 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
9032 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
9033
9034 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
9035 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
9036
9037 /* shadow page tables on either EPT or shadow page tables */
9038 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
9039 kvm_mmu_reset_context(vcpu);
9040
feaf0c7d
GN		 9041 if (!enable_ept)
9042 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
9043
3633cfc3
NHE		 9044 /*
9045 * L1 may access the L2's PDPTR, so save them to construct vmcs12
9046 */
9047 if (enable_ept) {
9048 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
9049 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
9050 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
9051 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
9052 }
9053
fe3ef05c
NHE		 9054 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
9055 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
9056}
9057
cd232ad0
NHE		 9058/*
9059 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
9060 * for running an L2 nested guest.
9061 */
9062static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
9063{
9064 struct vmcs12 *vmcs12;
9065 struct vcpu_vmx *vmx = to_vmx(vcpu);
9066 int cpu;
9067 struct loaded_vmcs *vmcs02;
384bb783 9068 bool ia32e;
ff651cb6 9069 u32 msr_entry_idx;
cd232ad0
NHE		 9070
9071 if (!nested_vmx_check_permission(vcpu) ||
9072 !nested_vmx_check_vmcs12(vcpu))
9073 return 1;
9074
9075 skip_emulated_instruction(vcpu);
9076 vmcs12 = get_vmcs12(vcpu);
9077
012f83cb
AG		 9078 if (enable_shadow_vmcs)
9079 copy_shadow_to_vmcs12(vmx);
9080
7c177938
NHE		 9081 /*
9082 * The nested entry process starts with enforcing various prerequisites
9083 * on vmcs12 as required by the Intel SDM, and act appropriately when
9084 * they fail: As the SDM explains, some conditions should cause the
9085 * instruction to fail, while others will cause the instruction to seem
9086 * to succeed, but return an EXIT_REASON_INVALID_STATE.
9087 * To speed up the normal (success) code path, we should avoid checking
9088 * for misconfigurations which will anyway be caught by the processor
9089 * when using the merged vmcs02.
9090 */
9091 if (vmcs12->launch_state == launch) {
9092 nested_vmx_failValid(vcpu,
9093 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
9094 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
9095 return 1;
9096 }
9097
6dfacadd
JK		 9098 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
9099 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
26539bd0
PB		 9100 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9101 return 1;
9102 }
9103
3af18d9c 9104 if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
7c177938
NHE		 9105 /*TODO: Also verify bits beyond physical address width are 0*/
9106 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9107 return 1;
9108 }
9109
3af18d9c 9110 if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) {
7c177938
NHE		 9111 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9112 return 1;
9113 }
9114
f2b93280
WV		 9115 if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) {
9116 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9117 return 1;
9118 }
9119
e9ac033e
EK		 9120 if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) {
9121 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9122 return 1;
9123 }
9124
7c177938 9125 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
3dcdf3ec
JK		 9126 nested_vmx_true_procbased_ctls_low,
9127 nested_vmx_procbased_ctls_high) ||
7c177938
NHE		 9128 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
9129 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
9130 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
9131 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
9132 !vmx_control_verify(vmcs12->vm_exit_controls,
2996fca0
JK		 9133 nested_vmx_true_exit_ctls_low,
9134 nested_vmx_exit_ctls_high) ||
7c177938 9135 !vmx_control_verify(vmcs12->vm_entry_controls,
2996fca0
JK		 9136 nested_vmx_true_entry_ctls_low,
9137 nested_vmx_entry_ctls_high))
7c177938
NHE		 9138 {
9139 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9140 return 1;
9141 }
9142
9143 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
9144 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9145 nested_vmx_failValid(vcpu,
9146 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
9147 return 1;
9148 }
9149
92fbc7b1 9150 if (!nested_cr0_valid(vmcs12, vmcs12->guest_cr0) ||
7c177938
NHE		 9151 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9152 nested_vmx_entry_failure(vcpu, vmcs12,
9153 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9154 return 1;
9155 }
9156 if (vmcs12->vmcs_link_pointer != -1ull) {
9157 nested_vmx_entry_failure(vcpu, vmcs12,
9158 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
9159 return 1;
9160 }
9161
384bb783 9162 /*
cb0c8cda 9163 * If the load IA32_EFER VM-entry control is 1, the following checks
384bb783
JK		 9164 * are performed on the field for the IA32_EFER MSR:
9165 * - Bits reserved in the IA32_EFER MSR must be 0.
9166 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
9167 * the IA-32e mode guest VM-exit control. It must also be identical
9168 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
9169 * CR0.PG) is 1.
9170 */
9171 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
9172 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
9173 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
9174 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
9175 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
9176 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
9177 nested_vmx_entry_failure(vcpu, vmcs12,
9178 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9179 return 1;
9180 }
9181 }
9182
9183 /*
9184 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
9185 * IA32_EFER MSR must be 0 in the field for that register. In addition,
9186 * the values of the LMA and LME bits in the field must each be that of
9187 * the host address-space size VM-exit control.
9188 */
9189 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
9190 ia32e = (vmcs12->vm_exit_controls &
9191 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
9192 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
9193 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
9194 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
9195 nested_vmx_entry_failure(vcpu, vmcs12,
9196 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9197 return 1;
9198 }
9199 }
9200
7c177938
NHE		 9201 /*
9202 * We're finally done with prerequisite checking, and can start with
9203 * the nested entry.
9204 */
9205
cd232ad0
NHE		 9206 vmcs02 = nested_get_current_vmcs02(vmx);
9207 if (!vmcs02)
9208 return -ENOMEM;
9209
9210 enter_guest_mode(vcpu);
9211
9212 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
9213
2996fca0
JK		 9214 if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
9215 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9216
cd232ad0
NHE		 9217 cpu = get_cpu();
9218 vmx->loaded_vmcs = vmcs02;
9219 vmx_vcpu_put(vcpu);
9220 vmx_vcpu_load(vcpu, cpu);
9221 vcpu->cpu = cpu;
9222 put_cpu();
9223
36c3cc42
JK		 9224 vmx_segment_cache_clear(vmx);
9225
cd232ad0
NHE		 9226 prepare_vmcs02(vcpu, vmcs12);
9227
ff651cb6
WV		 9228 msr_entry_idx = nested_vmx_load_msr(vcpu,
9229 vmcs12->vm_entry_msr_load_addr,
9230 vmcs12->vm_entry_msr_load_count);
9231 if (msr_entry_idx) {
9232 leave_guest_mode(vcpu);
9233 vmx_load_vmcs01(vcpu);
9234 nested_vmx_entry_failure(vcpu, vmcs12,
9235 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
9236 return 1;
9237 }
9238
9239 vmcs12->launch_state = 1;
9240
6dfacadd
JK		 9241 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
9242 return kvm_emulate_halt(vcpu);
9243
7af40ad3
JK		 9244 vmx->nested.nested_run_pending = 1;
9245
cd232ad0
NHE		 9246 /*
9247 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
9248 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
9249 * returned as far as L1 is concerned. It will only return (and set
9250 * the success flag) when L2 exits (see nested_vmx_vmexit()).
9251 */
9252 return 1;
9253}
9254
4704d0be
NHE		 9255/*
9256 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
9257 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
9258 * This function returns the new value we should put in vmcs12.guest_cr0.
9259 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
9260 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
9261 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
9262 * didn't trap the bit, because if L1 did, so would L0).
9263 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
9264 * been modified by L2, and L1 knows it. So just leave the old value of
9265 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
9266 * isn't relevant, because if L0 traps this bit it can set it to anything.
9267 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
9268 * changed these bits, and therefore they need to be updated, but L0
9269 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
9270 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
9271 */
9272static inline unsigned long
9273vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9274{
9275 return
9276 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
9277 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
9278 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
9279 vcpu->arch.cr0_guest_owned_bits));
9280}
9281
9282static inline unsigned long
9283vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9284{
9285 return
9286 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
9287 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
9288 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
9289 vcpu->arch.cr4_guest_owned_bits));
9290}
9291
5f3d5799
JK		 9292static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
9293 struct vmcs12 *vmcs12)
9294{
9295 u32 idt_vectoring;
9296 unsigned int nr;
9297
851eb667 9298 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
5f3d5799
JK		 9299 nr = vcpu->arch.exception.nr;
9300 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
9301
9302 if (kvm_exception_is_soft(nr)) {
9303 vmcs12->vm_exit_instruction_len =
9304 vcpu->arch.event_exit_inst_len;
9305 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
9306 } else
9307 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
9308
9309 if (vcpu->arch.exception.has_error_code) {
9310 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
9311 vmcs12->idt_vectoring_error_code =
9312 vcpu->arch.exception.error_code;
9313 }
9314
9315 vmcs12->idt_vectoring_info_field = idt_vectoring;
cd2633c5 9316 } else if (vcpu->arch.nmi_injected) {
5f3d5799
JK		 9317 vmcs12->idt_vectoring_info_field =
9318 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
9319 } else if (vcpu->arch.interrupt.pending) {
9320 nr = vcpu->arch.interrupt.nr;
9321 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
9322
9323 if (vcpu->arch.interrupt.soft) {
9324 idt_vectoring |= INTR_TYPE_SOFT_INTR;
9325 vmcs12->vm_entry_instruction_len =
9326 vcpu->arch.event_exit_inst_len;
9327 } else
9328 idt_vectoring |= INTR_TYPE_EXT_INTR;
9329
9330 vmcs12->idt_vectoring_info_field = idt_vectoring;
9331 }
9332}
9333
b6b8a145
JK		 9334static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
9335{
9336 struct vcpu_vmx *vmx = to_vmx(vcpu);
9337
f4124500
JK		 9338 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
9339 vmx->nested.preemption_timer_expired) {
9340 if (vmx->nested.nested_run_pending)
9341 return -EBUSY;
9342 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
9343 return 0;
9344 }
9345
b6b8a145 9346 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
220c5672
JK		 9347 if (vmx->nested.nested_run_pending ||
9348 vcpu->arch.interrupt.pending)
b6b8a145
JK		 9349 return -EBUSY;
9350 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
9351 NMI_VECTOR | INTR_TYPE_NMI_INTR |
9352 INTR_INFO_VALID_MASK, 0);
9353 /*
9354 * The NMI-triggered VM exit counts as injection:
9355 * clear this one and block further NMIs.
9356 */
9357 vcpu->arch.nmi_pending = 0;
9358 vmx_set_nmi_mask(vcpu, true);
9359 return 0;
9360 }
9361
9362 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
9363 nested_exit_on_intr(vcpu)) {
9364 if (vmx->nested.nested_run_pending)
9365 return -EBUSY;
9366 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
9367 }
9368
9369 return 0;
9370}
9371
f4124500
JK		 9372static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
9373{
9374 ktime_t remaining =
9375 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
9376 u64 value;
9377
9378 if (ktime_to_ns(remaining) <= 0)
9379 return 0;
9380
9381 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
9382 do_div(value, 1000000);
9383 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9384}
9385
4704d0be
NHE		 9386/*
9387 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
9388 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
9389 * and this function updates it to reflect the changes to the guest state while
9390 * L2 was running (and perhaps made some exits which were handled directly by L0
9391 * without going back to L1), and to reflect the exit reason.
9392 * Note that we do not have to copy here all VMCS fields, just those that
9393 * could have changed by the L2 guest or the exit - i.e., the guest-state and
9394 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
9395 * which already writes to vmcs12 directly.
9396 */
533558bc
JK		 9397static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
9398 u32 exit_reason, u32 exit_intr_info,
9399 unsigned long exit_qualification)
4704d0be
NHE		 9400{
9401 /* update guest state fields: */
9402 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
9403 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
9404
4704d0be
NHE		 9405 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
9406 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
9407 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
9408
9409 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
9410 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
9411 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
9412 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
9413 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
9414 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
9415 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
9416 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
9417 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
9418 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
9419 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
9420 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
9421 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
9422 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
9423 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
9424 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
9425 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
9426 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
9427 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
9428 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
9429 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
9430 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
9431 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
9432 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
9433 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
9434 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
9435 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
9436 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
9437 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
9438 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
9439 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
9440 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
9441 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
9442 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
9443 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
9444 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
9445
4704d0be
NHE		 9446 vmcs12->guest_interruptibility_info =
9447 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
9448 vmcs12->guest_pending_dbg_exceptions =
9449 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
3edf1e69
JK		 9450 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
9451 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
9452 else
9453 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
4704d0be 9454
f4124500
JK		 9455 if (nested_cpu_has_preemption_timer(vmcs12)) {
9456 if (vmcs12->vm_exit_controls &
9457 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
9458 vmcs12->vmx_preemption_timer_value =
9459 vmx_get_preemption_timer_value(vcpu);
9460 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
9461 }
7854cbca 9462
3633cfc3
NHE		 9463 /*
9464 * In some cases (usually, nested EPT), L2 is allowed to change its
9465 * own CR3 without exiting. If it has changed it, we must keep it.
9466 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
9467 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
9468 *
9469 * Additionally, restore L2's PDPTR to vmcs12.
9470 */
9471 if (enable_ept) {
9472 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
9473 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
9474 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
9475 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
9476 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
9477 }
9478
c18911a2
JK		 9479 vmcs12->vm_entry_controls =
9480 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
2961e876 9481 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
c18911a2 9482
2996fca0
JK		 9483 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
9484 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
9485 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9486 }
9487
4704d0be
NHE		 9488 /* TODO: These cannot have changed unless we have MSR bitmaps and
9489 * the relevant bit asks not to trap the change */
b8c07d55 9490 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
4704d0be 9491 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10ba54a5
JK		 9492 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
9493 vmcs12->guest_ia32_efer = vcpu->arch.efer;
4704d0be
NHE		 9494 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
9495 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
9496 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
36be0b9d
PB		 9497 if (vmx_mpx_supported())
9498 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
81dc01f7
WL		 9499 if (nested_cpu_has_xsaves(vmcs12))
9500 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
4704d0be
NHE		 9501
9502 /* update exit information fields: */
9503
533558bc
JK		 9504 vmcs12->vm_exit_reason = exit_reason;
9505 vmcs12->exit_qualification = exit_qualification;
4704d0be 9506
533558bc 9507 vmcs12->vm_exit_intr_info = exit_intr_info;
c0d1c770
JK		 9508 if ((vmcs12->vm_exit_intr_info &
9509 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
9510 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
9511 vmcs12->vm_exit_intr_error_code =
9512 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5f3d5799 9513 vmcs12->idt_vectoring_info_field = 0;
4704d0be
NHE		 9514 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
9515 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
9516
5f3d5799
JK		 9517 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
9518 /* vm_entry_intr_info_field is cleared on exit. Emulate this
9519 * instead of reading the real value. */
4704d0be 9520 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
5f3d5799
JK		 9521
9522 /*
9523 * Transfer the event that L0 or L1 may wanted to inject into
9524 * L2 to IDT_VECTORING_INFO_FIELD.
9525 */
9526 vmcs12_save_pending_event(vcpu, vmcs12);
9527 }
9528
9529 /*
9530 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
9531 * preserved above and would only end up incorrectly in L1.
9532 */
9533 vcpu->arch.nmi_injected = false;
9534 kvm_clear_exception_queue(vcpu);
9535 kvm_clear_interrupt_queue(vcpu);
4704d0be
NHE		 9536}
9537
9538/*
9539 * A part of what we need to when the nested L2 guest exits and we want to
9540 * run its L1 parent, is to reset L1's guest state to the host state specified
9541 * in vmcs12.
9542 * This function is to be called not only on normal nested exit, but also on
9543 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
9544 * Failures During or After Loading Guest State").
9545 * This function should be called when the active VMCS is L1's (vmcs01).
9546 */
733568f9
JK		 9547static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
9548 struct vmcs12 *vmcs12)
4704d0be 9549{
21feb4eb
ACL		 9550 struct kvm_segment seg;
9551
4704d0be
NHE		 9552 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
9553 vcpu->arch.efer = vmcs12->host_ia32_efer;
d1fa0352 9554 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4704d0be
NHE		 9555 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9556 else
9557 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9558 vmx_set_efer(vcpu, vcpu->arch.efer);
9559
9560 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
9561 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
1adfa76a 9562 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
4704d0be
NHE		 9563 /*
9564 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
9565 * actually changed, because it depends on the current state of
9566 * fpu_active (which may have changed).
9567 * Note that vmx_set_cr0 refers to efer set above.
9568 */
9e3e4dbf 9569 vmx_set_cr0(vcpu, vmcs12->host_cr0);
4704d0be
NHE		 9570 /*
9571 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
9572 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
9573 * but we also need to update cr0_guest_host_mask and exception_bitmap.
9574 */
9575 update_exception_bitmap(vcpu);
9576 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
9577 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9578
9579 /*
9580 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
9581 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
9582 */
9583 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
9584 kvm_set_cr4(vcpu, vmcs12->host_cr4);
9585
29bf08f1 9586 nested_ept_uninit_mmu_context(vcpu);
155a97a3 9587
4704d0be
NHE		 9588 kvm_set_cr3(vcpu, vmcs12->host_cr3);
9589 kvm_mmu_reset_context(vcpu);
9590
feaf0c7d
GN		 9591 if (!enable_ept)
9592 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
9593
4704d0be
NHE		 9594 if (enable_vpid) {
9595 /*
9596 * Trivially support vpid by letting L2s share their parent
9597 * L1's vpid. TODO: move to a more elaborate solution, giving
9598 * each L2 its own vpid and exposing the vpid feature to L1.
9599 */
9600 vmx_flush_tlb(vcpu);
9601 }
9602
9603
9604 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
9605 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
9606 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
9607 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
9608 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
4704d0be 9609
36be0b9d
PB		 9610 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
9611 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
9612 vmcs_write64(GUEST_BNDCFGS, 0);
9613
44811c02 9614 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
4704d0be 9615 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
44811c02
JK		 9616 vcpu->arch.pat = vmcs12->host_ia32_pat;
9617 }
4704d0be
NHE		 9618 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
9619 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
9620 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5 9621
21feb4eb
ACL		 9622 /* Set L1 segment info according to Intel SDM
9623 27.5.2 Loading Host Segment and Descriptor-Table Registers */
9624 seg = (struct kvm_segment) {
9625 .base = 0,
9626 .limit = 0xFFFFFFFF,
9627 .selector = vmcs12->host_cs_selector,
9628 .type = 11,
9629 .present = 1,
9630 .s = 1,
9631 .g = 1
9632 };
9633 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
9634 seg.l = 1;
9635 else
9636 seg.db = 1;
9637 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
9638 seg = (struct kvm_segment) {
9639 .base = 0,
9640 .limit = 0xFFFFFFFF,
9641 .type = 3,
9642 .present = 1,
9643 .s = 1,
9644 .db = 1,
9645 .g = 1
9646 };
9647 seg.selector = vmcs12->host_ds_selector;
9648 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
9649 seg.selector = vmcs12->host_es_selector;
9650 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
9651 seg.selector = vmcs12->host_ss_selector;
9652 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
9653 seg.selector = vmcs12->host_fs_selector;
9654 seg.base = vmcs12->host_fs_base;
9655 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
9656 seg.selector = vmcs12->host_gs_selector;
9657 seg.base = vmcs12->host_gs_base;
9658 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
9659 seg = (struct kvm_segment) {
205befd9 9660 .base = vmcs12->host_tr_base,
21feb4eb
ACL		 9661 .limit = 0x67,
9662 .selector = vmcs12->host_tr_selector,
9663 .type = 11,
9664 .present = 1
9665 };
9666 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
9667
503cd0c5
JK		 9668 kvm_set_dr(vcpu, 7, 0x400);
9669 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
ff651cb6 9670
3af18d9c
WV		 9671 if (cpu_has_vmx_msr_bitmap())
9672 vmx_set_msr_bitmap(vcpu);
9673
ff651cb6
WV		 9674 if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
9675 vmcs12->vm_exit_msr_load_count))
9676 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
4704d0be
NHE		 9677}
9678
9679/*
9680 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
9681 * and modify vmcs12 to make it see what it would expect to see there if
9682 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
9683 */
533558bc
JK		 9684static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
9685 u32 exit_intr_info,
9686 unsigned long exit_qualification)
4704d0be
NHE		 9687{
9688 struct vcpu_vmx *vmx = to_vmx(vcpu);
4704d0be
NHE		 9689 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9690
5f3d5799
JK		 9691 /* trying to cancel vmlaunch/vmresume is a bug */
9692 WARN_ON_ONCE(vmx->nested.nested_run_pending);
9693
4704d0be 9694 leave_guest_mode(vcpu);
533558bc
JK		 9695 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
9696 exit_qualification);
4704d0be 9697
ff651cb6
WV		 9698 if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
9699 vmcs12->vm_exit_msr_store_count))
9700 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
9701
f3380ca5
WL		 9702 vmx_load_vmcs01(vcpu);
9703
77b0f5d6
BD		 9704 if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
9705 && nested_exit_intr_ack_set(vcpu)) {
9706 int irq = kvm_cpu_get_interrupt(vcpu);
9707 WARN_ON(irq < 0);
9708 vmcs12->vm_exit_intr_info = irq |
9709 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
9710 }
9711
542060ea
JK		 9712 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
9713 vmcs12->exit_qualification,
9714 vmcs12->idt_vectoring_info_field,
9715 vmcs12->vm_exit_intr_info,
9716 vmcs12->vm_exit_intr_error_code,
9717 KVM_ISA_VMX);
4704d0be 9718
2961e876
GN		 9719 vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
9720 vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
36c3cc42
JK		 9721 vmx_segment_cache_clear(vmx);
9722
4704d0be
NHE		 9723 /* if no vmcs02 cache requested, remove the one we used */
9724 if (VMCS02_POOL_SIZE == 0)
9725 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
9726
9727 load_vmcs12_host_state(vcpu, vmcs12);
9728
27fc51b2 9729 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 9730 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
9731
9732 /* This is needed for same reason as it was needed in prepare_vmcs02 */
9733 vmx->host_rsp = 0;
9734
9735 /* Unpin physical memory we referred to in vmcs02 */
9736 if (vmx->nested.apic_access_page) {
9737 nested_release_page(vmx->nested.apic_access_page);
48d89b92 9738 vmx->nested.apic_access_page = NULL;
4704d0be 9739 }
a7c0b07d
WL		 9740 if (vmx->nested.virtual_apic_page) {
9741 nested_release_page(vmx->nested.virtual_apic_page);
48d89b92 9742 vmx->nested.virtual_apic_page = NULL;
a7c0b07d 9743 }
4704d0be 9744
38b99173
TC		 9745 /*
9746 * We are now running in L2, mmu_notifier will force to reload the
9747 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
9748 */
9749 kvm_vcpu_reload_apic_access_page(vcpu);
9750
4704d0be
NHE		 9751 /*
9752 * Exiting from L2 to L1, we're now back to L1 which thinks it just
9753 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
9754 * success or failure flag accordingly.
9755 */
9756 if (unlikely(vmx->fail)) {
9757 vmx->fail = 0;
9758 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
9759 } else
9760 nested_vmx_succeed(vcpu);
012f83cb
AG		 9761 if (enable_shadow_vmcs)
9762 vmx->nested.sync_shadow_vmcs = true;
b6b8a145
JK		 9763
9764 /* in case we halted in L2 */
9765 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4704d0be
NHE		 9766}
9767
42124925
JK		 9768/*
9769 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
9770 */
9771static void vmx_leave_nested(struct kvm_vcpu *vcpu)
9772{
9773 if (is_guest_mode(vcpu))
533558bc 9774 nested_vmx_vmexit(vcpu, -1, 0, 0);
42124925
JK		 9775 free_nested(to_vmx(vcpu));
9776}
9777
7c177938
NHE		 9778/*
9779 * L1's failure to enter L2 is a subset of a normal exit, as explained in
9780 * 23.7 "VM-entry failures during or after loading guest state" (this also
9781 * lists the acceptable exit-reason and exit-qualification parameters).
9782 * It should only be called before L2 actually succeeded to run, and when
9783 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
9784 */
9785static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
9786 struct vmcs12 *vmcs12,
9787 u32 reason, unsigned long qualification)
9788{
9789 load_vmcs12_host_state(vcpu, vmcs12);
9790 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
9791 vmcs12->exit_qualification = qualification;
9792 nested_vmx_succeed(vcpu);
012f83cb
AG		 9793 if (enable_shadow_vmcs)
9794 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
7c177938
NHE		 9795}
9796
8a76d7f2
JR		 9797static int vmx_check_intercept(struct kvm_vcpu *vcpu,
9798 struct x86_instruction_info *info,
9799 enum x86_intercept_stage stage)
9800{
9801 return X86EMUL_CONTINUE;
9802}
9803
48d89b92 9804static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
ae97a3b8 9805{
b4a2d31d
RK		 9806 if (ple_gap)
9807 shrink_ple_window(vcpu);
ae97a3b8
RK		 9808}
9809
843e4330
KH		 9810static void vmx_slot_enable_log_dirty(struct kvm *kvm,
9811 struct kvm_memory_slot *slot)
9812{
9813 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
9814 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
9815}
9816
9817static void vmx_slot_disable_log_dirty(struct kvm *kvm,
9818 struct kvm_memory_slot *slot)
9819{
9820 kvm_mmu_slot_set_dirty(kvm, slot);
9821}
9822
9823static void vmx_flush_log_dirty(struct kvm *kvm)
9824{
9825 kvm_flush_pml_buffers(kvm);
9826}
9827
9828static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
9829 struct kvm_memory_slot *memslot,
9830 gfn_t offset, unsigned long mask)
9831{
9832 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
9833}
9834
cbdd1bea 9835static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 9836 .cpu_has_kvm_support = cpu_has_kvm_support,
9837 .disabled_by_bios = vmx_disabled_by_bios,
9838 .hardware_setup = hardware_setup,
9839 .hardware_unsetup = hardware_unsetup,
002c7f7c 9840 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 9841 .hardware_enable = hardware_enable,
9842 .hardware_disable = hardware_disable,
04547156 9843 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 9844
9845 .vcpu_create = vmx_create_vcpu,
9846 .vcpu_free = vmx_free_vcpu,
04d2cc77 9847 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 9848
04d2cc77 9849 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 9850 .vcpu_load = vmx_vcpu_load,
9851 .vcpu_put = vmx_vcpu_put,
9852
c8639010 9853 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 9854 .get_msr = vmx_get_msr,
9855 .set_msr = vmx_set_msr,
9856 .get_segment_base = vmx_get_segment_base,
9857 .get_segment = vmx_get_segment,
9858 .set_segment = vmx_set_segment,
2e4d2653 9859 .get_cpl = vmx_get_cpl,
6aa8b732 9860 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 9861 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 9862 .decache_cr3 = vmx_decache_cr3,
25c4c276 9863 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 9864 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 9865 .set_cr3 = vmx_set_cr3,
9866 .set_cr4 = vmx_set_cr4,
6aa8b732 9867 .set_efer = vmx_set_efer,
6aa8b732
AK		 9868 .get_idt = vmx_get_idt,
9869 .set_idt = vmx_set_idt,
9870 .get_gdt = vmx_get_gdt,
9871 .set_gdt = vmx_set_gdt,
73aaf249
JK		 9872 .get_dr6 = vmx_get_dr6,
9873 .set_dr6 = vmx_set_dr6,
020df079 9874 .set_dr7 = vmx_set_dr7,
81908bf4 9875 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
5fdbf976 9876 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 9877 .get_rflags = vmx_get_rflags,
9878 .set_rflags = vmx_set_rflags,
02daab21 9879 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 9880
9881 .tlb_flush = vmx_flush_tlb,
6aa8b732 9882
6aa8b732 9883 .run = vmx_vcpu_run,
6062d012 9884 .handle_exit = vmx_handle_exit,
6aa8b732 9885 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 9886 .set_interrupt_shadow = vmx_set_interrupt_shadow,
9887 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 9888 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 9889 .set_irq = vmx_inject_irq,
95ba8273 9890 .set_nmi = vmx_inject_nmi,
298101da 9891 .queue_exception = vmx_queue_exception,
b463a6f7 9892 .cancel_injection = vmx_cancel_injection,
78646121 9893 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 9894 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 9895 .get_nmi_mask = vmx_get_nmi_mask,
9896 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 9897 .enable_nmi_window = enable_nmi_window,
9898 .enable_irq_window = enable_irq_window,
9899 .update_cr8_intercept = update_cr8_intercept,
8d14695f 9900 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
38b99173 9901 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
c7c9c56c
YZ		 9902 .vm_has_apicv = vmx_vm_has_apicv,
9903 .load_eoi_exitmap = vmx_load_eoi_exitmap,
9904 .hwapic_irr_update = vmx_hwapic_irr_update,
9905 .hwapic_isr_update = vmx_hwapic_isr_update,
a20ed54d
YZ		 9906 .sync_pir_to_irr = vmx_sync_pir_to_irr,
9907 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 9908
cbc94022 9909 .set_tss_addr = vmx_set_tss_addr,
67253af5 9910 .get_tdp_level = get_ept_level,
4b12f0de 9911 .get_mt_mask = vmx_get_mt_mask,
229456fc 9912
586f9607 9913 .get_exit_info = vmx_get_exit_info,
586f9607 9914
17cc3935 9915 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 9916
9917 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 9918
9919 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 9920 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 9921
9922 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 9923
9924 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 9925
4051b188 9926 .set_tsc_khz = vmx_set_tsc_khz,
ba904635 9927 .read_tsc_offset = vmx_read_tsc_offset,
99e3e30a 9928 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 9929 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 9930 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 9931 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 9932
9933 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 9934
9935 .check_intercept = vmx_check_intercept,
a547c6db 9936 .handle_external_intr = vmx_handle_external_intr,
da8999d3 9937 .mpx_supported = vmx_mpx_supported,
55412b2e 9938 .xsaves_supported = vmx_xsaves_supported,
b6b8a145
JK		 9939
9940 .check_nested_events = vmx_check_nested_events,
ae97a3b8
RK		 9941
9942 .sched_in = vmx_sched_in,
843e4330
KH		 9943
9944 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
9945 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
9946 .flush_log_dirty = vmx_flush_log_dirty,
9947 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
6aa8b732
AK		 9948};
9949
9950static int __init vmx_init(void)
9951{
34a1cd60
TC		 9952 int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
9953 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 9954 if (r)
34a1cd60 9955 return r;
25c5f225 9956
8f536b76
ZY		 9957#ifdef CONFIG_KEXEC
9958 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
9959 crash_vmclear_local_loaded_vmcss);
9960#endif
9961
fdef3ad1 9962 return 0;
6aa8b732
AK		 9963}
9964
9965static void __exit vmx_exit(void)
9966{
8f536b76 9967#ifdef CONFIG_KEXEC
3b63a43f 9968 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
8f536b76
ZY		 9969 synchronize_rcu();
9970#endif
9971
cb498ea2 9972 kvm_exit();
6aa8b732
AK		 9973}
9974
9975module_init(vmx_init)
9976module_exit(vmx_exit)
Linux kernel - Deliverables
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