Commit | Line | Data |
---|---|---|
043405e1 CO |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * derived from drivers/kvm/kvm_main.c | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
4d5c5d0f BAY |
7 | * Copyright (C) 2008 Qumranet, Inc. |
8 | * Copyright IBM Corporation, 2008 | |
043405e1 CO |
9 | * |
10 | * Authors: | |
11 | * Avi Kivity <avi@qumranet.com> | |
12 | * Yaniv Kamay <yaniv@qumranet.com> | |
4d5c5d0f BAY |
13 | * Amit Shah <amit.shah@qumranet.com> |
14 | * Ben-Ami Yassour <benami@il.ibm.com> | |
043405e1 CO |
15 | * |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | * | |
19 | */ | |
20 | ||
edf88417 | 21 | #include <linux/kvm_host.h> |
313a3dc7 | 22 | #include "irq.h" |
1d737c8a | 23 | #include "mmu.h" |
7837699f | 24 | #include "i8254.h" |
37817f29 | 25 | #include "tss.h" |
5fdbf976 | 26 | #include "kvm_cache_regs.h" |
26eef70c | 27 | #include "x86.h" |
313a3dc7 | 28 | |
18068523 | 29 | #include <linux/clocksource.h> |
4d5c5d0f | 30 | #include <linux/interrupt.h> |
313a3dc7 CO |
31 | #include <linux/kvm.h> |
32 | #include <linux/fs.h> | |
33 | #include <linux/vmalloc.h> | |
5fb76f9b | 34 | #include <linux/module.h> |
0de10343 | 35 | #include <linux/mman.h> |
2bacc55c | 36 | #include <linux/highmem.h> |
19de40a8 | 37 | #include <linux/iommu.h> |
62c476c7 | 38 | #include <linux/intel-iommu.h> |
c8076604 | 39 | #include <linux/cpufreq.h> |
18863bdd | 40 | #include <linux/user-return-notifier.h> |
aec51dc4 AK |
41 | #include <trace/events/kvm.h> |
42 | #undef TRACE_INCLUDE_FILE | |
229456fc MT |
43 | #define CREATE_TRACE_POINTS |
44 | #include "trace.h" | |
043405e1 CO |
45 | |
46 | #include <asm/uaccess.h> | |
d825ed0a | 47 | #include <asm/msr.h> |
a5f61300 | 48 | #include <asm/desc.h> |
0bed3b56 | 49 | #include <asm/mtrr.h> |
890ca9ae | 50 | #include <asm/mce.h> |
043405e1 | 51 | |
313a3dc7 | 52 | #define MAX_IO_MSRS 256 |
a03490ed CO |
53 | #define CR0_RESERVED_BITS \ |
54 | (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \ | |
55 | | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \ | |
56 | | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG)) | |
57 | #define CR4_RESERVED_BITS \ | |
58 | (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\ | |
59 | | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \ | |
60 | | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \ | |
61 | | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE)) | |
62 | ||
63 | #define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR) | |
890ca9ae HY |
64 | |
65 | #define KVM_MAX_MCE_BANKS 32 | |
66 | #define KVM_MCE_CAP_SUPPORTED MCG_CTL_P | |
67 | ||
50a37eb4 JR |
68 | /* EFER defaults: |
69 | * - enable syscall per default because its emulated by KVM | |
70 | * - enable LME and LMA per default on 64 bit KVM | |
71 | */ | |
72 | #ifdef CONFIG_X86_64 | |
73 | static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL; | |
74 | #else | |
75 | static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL; | |
76 | #endif | |
313a3dc7 | 77 | |
ba1389b7 AK |
78 | #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM |
79 | #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU | |
417bc304 | 80 | |
cb142eb7 | 81 | static void update_cr8_intercept(struct kvm_vcpu *vcpu); |
674eea0f AK |
82 | static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid, |
83 | struct kvm_cpuid_entry2 __user *entries); | |
84 | ||
97896d04 | 85 | struct kvm_x86_ops *kvm_x86_ops; |
5fdbf976 | 86 | EXPORT_SYMBOL_GPL(kvm_x86_ops); |
97896d04 | 87 | |
ed85c068 AP |
88 | int ignore_msrs = 0; |
89 | module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR); | |
90 | ||
18863bdd AK |
91 | #define KVM_NR_SHARED_MSRS 16 |
92 | ||
93 | struct kvm_shared_msrs_global { | |
94 | int nr; | |
95 | struct kvm_shared_msr { | |
96 | u32 msr; | |
97 | u64 value; | |
98 | } msrs[KVM_NR_SHARED_MSRS]; | |
99 | }; | |
100 | ||
101 | struct kvm_shared_msrs { | |
102 | struct user_return_notifier urn; | |
103 | bool registered; | |
104 | u64 current_value[KVM_NR_SHARED_MSRS]; | |
105 | }; | |
106 | ||
107 | static struct kvm_shared_msrs_global __read_mostly shared_msrs_global; | |
108 | static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs); | |
109 | ||
417bc304 | 110 | struct kvm_stats_debugfs_item debugfs_entries[] = { |
ba1389b7 AK |
111 | { "pf_fixed", VCPU_STAT(pf_fixed) }, |
112 | { "pf_guest", VCPU_STAT(pf_guest) }, | |
113 | { "tlb_flush", VCPU_STAT(tlb_flush) }, | |
114 | { "invlpg", VCPU_STAT(invlpg) }, | |
115 | { "exits", VCPU_STAT(exits) }, | |
116 | { "io_exits", VCPU_STAT(io_exits) }, | |
117 | { "mmio_exits", VCPU_STAT(mmio_exits) }, | |
118 | { "signal_exits", VCPU_STAT(signal_exits) }, | |
119 | { "irq_window", VCPU_STAT(irq_window_exits) }, | |
f08864b4 | 120 | { "nmi_window", VCPU_STAT(nmi_window_exits) }, |
ba1389b7 AK |
121 | { "halt_exits", VCPU_STAT(halt_exits) }, |
122 | { "halt_wakeup", VCPU_STAT(halt_wakeup) }, | |
f11c3a8d | 123 | { "hypercalls", VCPU_STAT(hypercalls) }, |
ba1389b7 AK |
124 | { "request_irq", VCPU_STAT(request_irq_exits) }, |
125 | { "irq_exits", VCPU_STAT(irq_exits) }, | |
126 | { "host_state_reload", VCPU_STAT(host_state_reload) }, | |
127 | { "efer_reload", VCPU_STAT(efer_reload) }, | |
128 | { "fpu_reload", VCPU_STAT(fpu_reload) }, | |
129 | { "insn_emulation", VCPU_STAT(insn_emulation) }, | |
130 | { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) }, | |
fa89a817 | 131 | { "irq_injections", VCPU_STAT(irq_injections) }, |
c4abb7c9 | 132 | { "nmi_injections", VCPU_STAT(nmi_injections) }, |
4cee5764 AK |
133 | { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) }, |
134 | { "mmu_pte_write", VM_STAT(mmu_pte_write) }, | |
135 | { "mmu_pte_updated", VM_STAT(mmu_pte_updated) }, | |
136 | { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) }, | |
137 | { "mmu_flooded", VM_STAT(mmu_flooded) }, | |
138 | { "mmu_recycled", VM_STAT(mmu_recycled) }, | |
dfc5aa00 | 139 | { "mmu_cache_miss", VM_STAT(mmu_cache_miss) }, |
4731d4c7 | 140 | { "mmu_unsync", VM_STAT(mmu_unsync) }, |
0f74a24c | 141 | { "remote_tlb_flush", VM_STAT(remote_tlb_flush) }, |
05da4558 | 142 | { "largepages", VM_STAT(lpages) }, |
417bc304 HB |
143 | { NULL } |
144 | }; | |
145 | ||
18863bdd AK |
146 | static void kvm_on_user_return(struct user_return_notifier *urn) |
147 | { | |
148 | unsigned slot; | |
149 | struct kvm_shared_msr *global; | |
150 | struct kvm_shared_msrs *locals | |
151 | = container_of(urn, struct kvm_shared_msrs, urn); | |
152 | ||
153 | for (slot = 0; slot < shared_msrs_global.nr; ++slot) { | |
154 | global = &shared_msrs_global.msrs[slot]; | |
155 | if (global->value != locals->current_value[slot]) { | |
156 | wrmsrl(global->msr, global->value); | |
157 | locals->current_value[slot] = global->value; | |
158 | } | |
159 | } | |
160 | locals->registered = false; | |
161 | user_return_notifier_unregister(urn); | |
162 | } | |
163 | ||
164 | void kvm_define_shared_msr(unsigned slot, u32 msr) | |
165 | { | |
166 | int cpu; | |
167 | u64 value; | |
168 | ||
169 | if (slot >= shared_msrs_global.nr) | |
170 | shared_msrs_global.nr = slot + 1; | |
171 | shared_msrs_global.msrs[slot].msr = msr; | |
172 | rdmsrl_safe(msr, &value); | |
173 | shared_msrs_global.msrs[slot].value = value; | |
174 | for_each_online_cpu(cpu) | |
175 | per_cpu(shared_msrs, cpu).current_value[slot] = value; | |
176 | } | |
177 | EXPORT_SYMBOL_GPL(kvm_define_shared_msr); | |
178 | ||
179 | static void kvm_shared_msr_cpu_online(void) | |
180 | { | |
181 | unsigned i; | |
182 | struct kvm_shared_msrs *locals = &__get_cpu_var(shared_msrs); | |
183 | ||
184 | for (i = 0; i < shared_msrs_global.nr; ++i) | |
185 | locals->current_value[i] = shared_msrs_global.msrs[i].value; | |
186 | } | |
187 | ||
188 | void kvm_set_shared_msr(unsigned slot, u64 value) | |
189 | { | |
190 | struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs); | |
191 | ||
192 | if (value == smsr->current_value[slot]) | |
193 | return; | |
194 | smsr->current_value[slot] = value; | |
195 | wrmsrl(shared_msrs_global.msrs[slot].msr, value); | |
196 | if (!smsr->registered) { | |
197 | smsr->urn.on_user_return = kvm_on_user_return; | |
198 | user_return_notifier_register(&smsr->urn); | |
199 | smsr->registered = true; | |
200 | } | |
201 | } | |
202 | EXPORT_SYMBOL_GPL(kvm_set_shared_msr); | |
203 | ||
5fb76f9b CO |
204 | unsigned long segment_base(u16 selector) |
205 | { | |
206 | struct descriptor_table gdt; | |
a5f61300 | 207 | struct desc_struct *d; |
5fb76f9b CO |
208 | unsigned long table_base; |
209 | unsigned long v; | |
210 | ||
211 | if (selector == 0) | |
212 | return 0; | |
213 | ||
b792c344 | 214 | kvm_get_gdt(&gdt); |
5fb76f9b CO |
215 | table_base = gdt.base; |
216 | ||
217 | if (selector & 4) { /* from ldt */ | |
b792c344 | 218 | u16 ldt_selector = kvm_read_ldt(); |
5fb76f9b | 219 | |
5fb76f9b CO |
220 | table_base = segment_base(ldt_selector); |
221 | } | |
a5f61300 | 222 | d = (struct desc_struct *)(table_base + (selector & ~7)); |
46a359e7 | 223 | v = get_desc_base(d); |
5fb76f9b | 224 | #ifdef CONFIG_X86_64 |
a5f61300 AK |
225 | if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11)) |
226 | v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32; | |
5fb76f9b CO |
227 | #endif |
228 | return v; | |
229 | } | |
230 | EXPORT_SYMBOL_GPL(segment_base); | |
231 | ||
6866b83e CO |
232 | u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) |
233 | { | |
234 | if (irqchip_in_kernel(vcpu->kvm)) | |
ad312c7c | 235 | return vcpu->arch.apic_base; |
6866b83e | 236 | else |
ad312c7c | 237 | return vcpu->arch.apic_base; |
6866b83e CO |
238 | } |
239 | EXPORT_SYMBOL_GPL(kvm_get_apic_base); | |
240 | ||
241 | void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data) | |
242 | { | |
243 | /* TODO: reserve bits check */ | |
244 | if (irqchip_in_kernel(vcpu->kvm)) | |
245 | kvm_lapic_set_base(vcpu, data); | |
246 | else | |
ad312c7c | 247 | vcpu->arch.apic_base = data; |
6866b83e CO |
248 | } |
249 | EXPORT_SYMBOL_GPL(kvm_set_apic_base); | |
250 | ||
298101da AK |
251 | void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
252 | { | |
ad312c7c ZX |
253 | WARN_ON(vcpu->arch.exception.pending); |
254 | vcpu->arch.exception.pending = true; | |
255 | vcpu->arch.exception.has_error_code = false; | |
256 | vcpu->arch.exception.nr = nr; | |
298101da AK |
257 | } |
258 | EXPORT_SYMBOL_GPL(kvm_queue_exception); | |
259 | ||
c3c91fee AK |
260 | void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr, |
261 | u32 error_code) | |
262 | { | |
263 | ++vcpu->stat.pf_guest; | |
d8017474 | 264 | |
71c4dfaf | 265 | if (vcpu->arch.exception.pending) { |
6edf14d8 GN |
266 | switch(vcpu->arch.exception.nr) { |
267 | case DF_VECTOR: | |
71c4dfaf JR |
268 | /* triple fault -> shutdown */ |
269 | set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests); | |
6edf14d8 GN |
270 | return; |
271 | case PF_VECTOR: | |
272 | vcpu->arch.exception.nr = DF_VECTOR; | |
273 | vcpu->arch.exception.error_code = 0; | |
274 | return; | |
275 | default: | |
276 | /* replace previous exception with a new one in a hope | |
277 | that instruction re-execution will regenerate lost | |
278 | exception */ | |
279 | vcpu->arch.exception.pending = false; | |
280 | break; | |
71c4dfaf | 281 | } |
c3c91fee | 282 | } |
ad312c7c | 283 | vcpu->arch.cr2 = addr; |
c3c91fee AK |
284 | kvm_queue_exception_e(vcpu, PF_VECTOR, error_code); |
285 | } | |
286 | ||
3419ffc8 SY |
287 | void kvm_inject_nmi(struct kvm_vcpu *vcpu) |
288 | { | |
289 | vcpu->arch.nmi_pending = 1; | |
290 | } | |
291 | EXPORT_SYMBOL_GPL(kvm_inject_nmi); | |
292 | ||
298101da AK |
293 | void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
294 | { | |
ad312c7c ZX |
295 | WARN_ON(vcpu->arch.exception.pending); |
296 | vcpu->arch.exception.pending = true; | |
297 | vcpu->arch.exception.has_error_code = true; | |
298 | vcpu->arch.exception.nr = nr; | |
299 | vcpu->arch.exception.error_code = error_code; | |
298101da AK |
300 | } |
301 | EXPORT_SYMBOL_GPL(kvm_queue_exception_e); | |
302 | ||
0a79b009 AK |
303 | /* |
304 | * Checks if cpl <= required_cpl; if true, return true. Otherwise queue | |
305 | * a #GP and return false. | |
306 | */ | |
307 | bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) | |
298101da | 308 | { |
0a79b009 AK |
309 | if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl) |
310 | return true; | |
311 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
312 | return false; | |
298101da | 313 | } |
0a79b009 | 314 | EXPORT_SYMBOL_GPL(kvm_require_cpl); |
298101da | 315 | |
a03490ed CO |
316 | /* |
317 | * Load the pae pdptrs. Return true is they are all valid. | |
318 | */ | |
319 | int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3) | |
320 | { | |
321 | gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; | |
322 | unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; | |
323 | int i; | |
324 | int ret; | |
ad312c7c | 325 | u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)]; |
a03490ed | 326 | |
a03490ed CO |
327 | ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte, |
328 | offset * sizeof(u64), sizeof(pdpte)); | |
329 | if (ret < 0) { | |
330 | ret = 0; | |
331 | goto out; | |
332 | } | |
333 | for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { | |
43a3795a | 334 | if (is_present_gpte(pdpte[i]) && |
20c466b5 | 335 | (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) { |
a03490ed CO |
336 | ret = 0; |
337 | goto out; | |
338 | } | |
339 | } | |
340 | ret = 1; | |
341 | ||
ad312c7c | 342 | memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs)); |
6de4f3ad AK |
343 | __set_bit(VCPU_EXREG_PDPTR, |
344 | (unsigned long *)&vcpu->arch.regs_avail); | |
345 | __set_bit(VCPU_EXREG_PDPTR, | |
346 | (unsigned long *)&vcpu->arch.regs_dirty); | |
a03490ed | 347 | out: |
a03490ed CO |
348 | |
349 | return ret; | |
350 | } | |
cc4b6871 | 351 | EXPORT_SYMBOL_GPL(load_pdptrs); |
a03490ed | 352 | |
d835dfec AK |
353 | static bool pdptrs_changed(struct kvm_vcpu *vcpu) |
354 | { | |
ad312c7c | 355 | u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)]; |
d835dfec AK |
356 | bool changed = true; |
357 | int r; | |
358 | ||
359 | if (is_long_mode(vcpu) || !is_pae(vcpu)) | |
360 | return false; | |
361 | ||
6de4f3ad AK |
362 | if (!test_bit(VCPU_EXREG_PDPTR, |
363 | (unsigned long *)&vcpu->arch.regs_avail)) | |
364 | return true; | |
365 | ||
ad312c7c | 366 | r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte)); |
d835dfec AK |
367 | if (r < 0) |
368 | goto out; | |
ad312c7c | 369 | changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0; |
d835dfec | 370 | out: |
d835dfec AK |
371 | |
372 | return changed; | |
373 | } | |
374 | ||
2d3ad1f4 | 375 | void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
a03490ed CO |
376 | { |
377 | if (cr0 & CR0_RESERVED_BITS) { | |
378 | printk(KERN_DEBUG "set_cr0: 0x%lx #GP, reserved bits 0x%lx\n", | |
ad312c7c | 379 | cr0, vcpu->arch.cr0); |
c1a5d4f9 | 380 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
381 | return; |
382 | } | |
383 | ||
384 | if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) { | |
385 | printk(KERN_DEBUG "set_cr0: #GP, CD == 0 && NW == 1\n"); | |
c1a5d4f9 | 386 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
387 | return; |
388 | } | |
389 | ||
390 | if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) { | |
391 | printk(KERN_DEBUG "set_cr0: #GP, set PG flag " | |
392 | "and a clear PE flag\n"); | |
c1a5d4f9 | 393 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
394 | return; |
395 | } | |
396 | ||
397 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { | |
398 | #ifdef CONFIG_X86_64 | |
ad312c7c | 399 | if ((vcpu->arch.shadow_efer & EFER_LME)) { |
a03490ed CO |
400 | int cs_db, cs_l; |
401 | ||
402 | if (!is_pae(vcpu)) { | |
403 | printk(KERN_DEBUG "set_cr0: #GP, start paging " | |
404 | "in long mode while PAE is disabled\n"); | |
c1a5d4f9 | 405 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
406 | return; |
407 | } | |
408 | kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); | |
409 | if (cs_l) { | |
410 | printk(KERN_DEBUG "set_cr0: #GP, start paging " | |
411 | "in long mode while CS.L == 1\n"); | |
c1a5d4f9 | 412 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
413 | return; |
414 | ||
415 | } | |
416 | } else | |
417 | #endif | |
ad312c7c | 418 | if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) { |
a03490ed CO |
419 | printk(KERN_DEBUG "set_cr0: #GP, pdptrs " |
420 | "reserved bits\n"); | |
c1a5d4f9 | 421 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
422 | return; |
423 | } | |
424 | ||
425 | } | |
426 | ||
427 | kvm_x86_ops->set_cr0(vcpu, cr0); | |
ad312c7c | 428 | vcpu->arch.cr0 = cr0; |
a03490ed | 429 | |
a03490ed | 430 | kvm_mmu_reset_context(vcpu); |
a03490ed CO |
431 | return; |
432 | } | |
2d3ad1f4 | 433 | EXPORT_SYMBOL_GPL(kvm_set_cr0); |
a03490ed | 434 | |
2d3ad1f4 | 435 | void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) |
a03490ed | 436 | { |
2d3ad1f4 | 437 | kvm_set_cr0(vcpu, (vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f)); |
a03490ed | 438 | } |
2d3ad1f4 | 439 | EXPORT_SYMBOL_GPL(kvm_lmsw); |
a03490ed | 440 | |
2d3ad1f4 | 441 | void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
a03490ed | 442 | { |
a2edf57f AK |
443 | unsigned long old_cr4 = vcpu->arch.cr4; |
444 | unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE; | |
445 | ||
a03490ed CO |
446 | if (cr4 & CR4_RESERVED_BITS) { |
447 | printk(KERN_DEBUG "set_cr4: #GP, reserved bits\n"); | |
c1a5d4f9 | 448 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
449 | return; |
450 | } | |
451 | ||
452 | if (is_long_mode(vcpu)) { | |
453 | if (!(cr4 & X86_CR4_PAE)) { | |
454 | printk(KERN_DEBUG "set_cr4: #GP, clearing PAE while " | |
455 | "in long mode\n"); | |
c1a5d4f9 | 456 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
457 | return; |
458 | } | |
a2edf57f AK |
459 | } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) |
460 | && ((cr4 ^ old_cr4) & pdptr_bits) | |
ad312c7c | 461 | && !load_pdptrs(vcpu, vcpu->arch.cr3)) { |
a03490ed | 462 | printk(KERN_DEBUG "set_cr4: #GP, pdptrs reserved bits\n"); |
c1a5d4f9 | 463 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
464 | return; |
465 | } | |
466 | ||
467 | if (cr4 & X86_CR4_VMXE) { | |
468 | printk(KERN_DEBUG "set_cr4: #GP, setting VMXE\n"); | |
c1a5d4f9 | 469 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
470 | return; |
471 | } | |
472 | kvm_x86_ops->set_cr4(vcpu, cr4); | |
ad312c7c | 473 | vcpu->arch.cr4 = cr4; |
5a41accd | 474 | vcpu->arch.mmu.base_role.cr4_pge = (cr4 & X86_CR4_PGE) && !tdp_enabled; |
a03490ed | 475 | kvm_mmu_reset_context(vcpu); |
a03490ed | 476 | } |
2d3ad1f4 | 477 | EXPORT_SYMBOL_GPL(kvm_set_cr4); |
a03490ed | 478 | |
2d3ad1f4 | 479 | void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) |
a03490ed | 480 | { |
ad312c7c | 481 | if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) { |
0ba73cda | 482 | kvm_mmu_sync_roots(vcpu); |
d835dfec AK |
483 | kvm_mmu_flush_tlb(vcpu); |
484 | return; | |
485 | } | |
486 | ||
a03490ed CO |
487 | if (is_long_mode(vcpu)) { |
488 | if (cr3 & CR3_L_MODE_RESERVED_BITS) { | |
489 | printk(KERN_DEBUG "set_cr3: #GP, reserved bits\n"); | |
c1a5d4f9 | 490 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
491 | return; |
492 | } | |
493 | } else { | |
494 | if (is_pae(vcpu)) { | |
495 | if (cr3 & CR3_PAE_RESERVED_BITS) { | |
496 | printk(KERN_DEBUG | |
497 | "set_cr3: #GP, reserved bits\n"); | |
c1a5d4f9 | 498 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
499 | return; |
500 | } | |
501 | if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) { | |
502 | printk(KERN_DEBUG "set_cr3: #GP, pdptrs " | |
503 | "reserved bits\n"); | |
c1a5d4f9 | 504 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
505 | return; |
506 | } | |
507 | } | |
508 | /* | |
509 | * We don't check reserved bits in nonpae mode, because | |
510 | * this isn't enforced, and VMware depends on this. | |
511 | */ | |
512 | } | |
513 | ||
a03490ed CO |
514 | /* |
515 | * Does the new cr3 value map to physical memory? (Note, we | |
516 | * catch an invalid cr3 even in real-mode, because it would | |
517 | * cause trouble later on when we turn on paging anyway.) | |
518 | * | |
519 | * A real CPU would silently accept an invalid cr3 and would | |
520 | * attempt to use it - with largely undefined (and often hard | |
521 | * to debug) behavior on the guest side. | |
522 | */ | |
523 | if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT))) | |
c1a5d4f9 | 524 | kvm_inject_gp(vcpu, 0); |
a03490ed | 525 | else { |
ad312c7c ZX |
526 | vcpu->arch.cr3 = cr3; |
527 | vcpu->arch.mmu.new_cr3(vcpu); | |
a03490ed | 528 | } |
a03490ed | 529 | } |
2d3ad1f4 | 530 | EXPORT_SYMBOL_GPL(kvm_set_cr3); |
a03490ed | 531 | |
2d3ad1f4 | 532 | void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) |
a03490ed CO |
533 | { |
534 | if (cr8 & CR8_RESERVED_BITS) { | |
535 | printk(KERN_DEBUG "set_cr8: #GP, reserved bits 0x%lx\n", cr8); | |
c1a5d4f9 | 536 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
537 | return; |
538 | } | |
539 | if (irqchip_in_kernel(vcpu->kvm)) | |
540 | kvm_lapic_set_tpr(vcpu, cr8); | |
541 | else | |
ad312c7c | 542 | vcpu->arch.cr8 = cr8; |
a03490ed | 543 | } |
2d3ad1f4 | 544 | EXPORT_SYMBOL_GPL(kvm_set_cr8); |
a03490ed | 545 | |
2d3ad1f4 | 546 | unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) |
a03490ed CO |
547 | { |
548 | if (irqchip_in_kernel(vcpu->kvm)) | |
549 | return kvm_lapic_get_cr8(vcpu); | |
550 | else | |
ad312c7c | 551 | return vcpu->arch.cr8; |
a03490ed | 552 | } |
2d3ad1f4 | 553 | EXPORT_SYMBOL_GPL(kvm_get_cr8); |
a03490ed | 554 | |
d8017474 AG |
555 | static inline u32 bit(int bitno) |
556 | { | |
557 | return 1 << (bitno & 31); | |
558 | } | |
559 | ||
043405e1 CO |
560 | /* |
561 | * List of msr numbers which we expose to userspace through KVM_GET_MSRS | |
562 | * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. | |
563 | * | |
564 | * This list is modified at module load time to reflect the | |
e3267cbb GC |
565 | * capabilities of the host cpu. This capabilities test skips MSRs that are |
566 | * kvm-specific. Those are put in the beginning of the list. | |
043405e1 | 567 | */ |
e3267cbb GC |
568 | |
569 | #define KVM_SAVE_MSRS_BEGIN 2 | |
043405e1 | 570 | static u32 msrs_to_save[] = { |
e3267cbb | 571 | MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, |
043405e1 CO |
572 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, |
573 | MSR_K6_STAR, | |
574 | #ifdef CONFIG_X86_64 | |
575 | MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, | |
576 | #endif | |
e3267cbb | 577 | MSR_IA32_TSC, MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA |
043405e1 CO |
578 | }; |
579 | ||
580 | static unsigned num_msrs_to_save; | |
581 | ||
582 | static u32 emulated_msrs[] = { | |
583 | MSR_IA32_MISC_ENABLE, | |
584 | }; | |
585 | ||
15c4a640 CO |
586 | static void set_efer(struct kvm_vcpu *vcpu, u64 efer) |
587 | { | |
f2b4b7dd | 588 | if (efer & efer_reserved_bits) { |
15c4a640 CO |
589 | printk(KERN_DEBUG "set_efer: 0x%llx #GP, reserved bits\n", |
590 | efer); | |
c1a5d4f9 | 591 | kvm_inject_gp(vcpu, 0); |
15c4a640 CO |
592 | return; |
593 | } | |
594 | ||
595 | if (is_paging(vcpu) | |
ad312c7c | 596 | && (vcpu->arch.shadow_efer & EFER_LME) != (efer & EFER_LME)) { |
15c4a640 | 597 | printk(KERN_DEBUG "set_efer: #GP, change LME while paging\n"); |
c1a5d4f9 | 598 | kvm_inject_gp(vcpu, 0); |
15c4a640 CO |
599 | return; |
600 | } | |
601 | ||
1b2fd70c AG |
602 | if (efer & EFER_FFXSR) { |
603 | struct kvm_cpuid_entry2 *feat; | |
604 | ||
605 | feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); | |
606 | if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) { | |
607 | printk(KERN_DEBUG "set_efer: #GP, enable FFXSR w/o CPUID capability\n"); | |
608 | kvm_inject_gp(vcpu, 0); | |
609 | return; | |
610 | } | |
611 | } | |
612 | ||
d8017474 AG |
613 | if (efer & EFER_SVME) { |
614 | struct kvm_cpuid_entry2 *feat; | |
615 | ||
616 | feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); | |
617 | if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) { | |
618 | printk(KERN_DEBUG "set_efer: #GP, enable SVM w/o SVM\n"); | |
619 | kvm_inject_gp(vcpu, 0); | |
620 | return; | |
621 | } | |
622 | } | |
623 | ||
15c4a640 CO |
624 | kvm_x86_ops->set_efer(vcpu, efer); |
625 | ||
626 | efer &= ~EFER_LMA; | |
ad312c7c | 627 | efer |= vcpu->arch.shadow_efer & EFER_LMA; |
15c4a640 | 628 | |
ad312c7c | 629 | vcpu->arch.shadow_efer = efer; |
9645bb56 AK |
630 | |
631 | vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled; | |
632 | kvm_mmu_reset_context(vcpu); | |
15c4a640 CO |
633 | } |
634 | ||
f2b4b7dd JR |
635 | void kvm_enable_efer_bits(u64 mask) |
636 | { | |
637 | efer_reserved_bits &= ~mask; | |
638 | } | |
639 | EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); | |
640 | ||
641 | ||
15c4a640 CO |
642 | /* |
643 | * Writes msr value into into the appropriate "register". | |
644 | * Returns 0 on success, non-0 otherwise. | |
645 | * Assumes vcpu_load() was already called. | |
646 | */ | |
647 | int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data) | |
648 | { | |
649 | return kvm_x86_ops->set_msr(vcpu, msr_index, data); | |
650 | } | |
651 | ||
313a3dc7 CO |
652 | /* |
653 | * Adapt set_msr() to msr_io()'s calling convention | |
654 | */ | |
655 | static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) | |
656 | { | |
657 | return kvm_set_msr(vcpu, index, *data); | |
658 | } | |
659 | ||
18068523 GOC |
660 | static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock) |
661 | { | |
662 | static int version; | |
50d0a0f9 GH |
663 | struct pvclock_wall_clock wc; |
664 | struct timespec now, sys, boot; | |
18068523 GOC |
665 | |
666 | if (!wall_clock) | |
667 | return; | |
668 | ||
669 | version++; | |
670 | ||
18068523 GOC |
671 | kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); |
672 | ||
50d0a0f9 GH |
673 | /* |
674 | * The guest calculates current wall clock time by adding | |
675 | * system time (updated by kvm_write_guest_time below) to the | |
676 | * wall clock specified here. guest system time equals host | |
677 | * system time for us, thus we must fill in host boot time here. | |
678 | */ | |
679 | now = current_kernel_time(); | |
680 | ktime_get_ts(&sys); | |
681 | boot = ns_to_timespec(timespec_to_ns(&now) - timespec_to_ns(&sys)); | |
682 | ||
683 | wc.sec = boot.tv_sec; | |
684 | wc.nsec = boot.tv_nsec; | |
685 | wc.version = version; | |
18068523 GOC |
686 | |
687 | kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); | |
688 | ||
689 | version++; | |
690 | kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); | |
18068523 GOC |
691 | } |
692 | ||
50d0a0f9 GH |
693 | static uint32_t div_frac(uint32_t dividend, uint32_t divisor) |
694 | { | |
695 | uint32_t quotient, remainder; | |
696 | ||
697 | /* Don't try to replace with do_div(), this one calculates | |
698 | * "(dividend << 32) / divisor" */ | |
699 | __asm__ ( "divl %4" | |
700 | : "=a" (quotient), "=d" (remainder) | |
701 | : "0" (0), "1" (dividend), "r" (divisor) ); | |
702 | return quotient; | |
703 | } | |
704 | ||
705 | static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock) | |
706 | { | |
707 | uint64_t nsecs = 1000000000LL; | |
708 | int32_t shift = 0; | |
709 | uint64_t tps64; | |
710 | uint32_t tps32; | |
711 | ||
712 | tps64 = tsc_khz * 1000LL; | |
713 | while (tps64 > nsecs*2) { | |
714 | tps64 >>= 1; | |
715 | shift--; | |
716 | } | |
717 | ||
718 | tps32 = (uint32_t)tps64; | |
719 | while (tps32 <= (uint32_t)nsecs) { | |
720 | tps32 <<= 1; | |
721 | shift++; | |
722 | } | |
723 | ||
724 | hv_clock->tsc_shift = shift; | |
725 | hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32); | |
726 | ||
727 | pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n", | |
80a914dc | 728 | __func__, tsc_khz, hv_clock->tsc_shift, |
50d0a0f9 GH |
729 | hv_clock->tsc_to_system_mul); |
730 | } | |
731 | ||
c8076604 GH |
732 | static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); |
733 | ||
18068523 GOC |
734 | static void kvm_write_guest_time(struct kvm_vcpu *v) |
735 | { | |
736 | struct timespec ts; | |
737 | unsigned long flags; | |
738 | struct kvm_vcpu_arch *vcpu = &v->arch; | |
739 | void *shared_kaddr; | |
463656c0 | 740 | unsigned long this_tsc_khz; |
18068523 GOC |
741 | |
742 | if ((!vcpu->time_page)) | |
743 | return; | |
744 | ||
463656c0 AK |
745 | this_tsc_khz = get_cpu_var(cpu_tsc_khz); |
746 | if (unlikely(vcpu->hv_clock_tsc_khz != this_tsc_khz)) { | |
747 | kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock); | |
748 | vcpu->hv_clock_tsc_khz = this_tsc_khz; | |
50d0a0f9 | 749 | } |
463656c0 | 750 | put_cpu_var(cpu_tsc_khz); |
50d0a0f9 | 751 | |
18068523 GOC |
752 | /* Keep irq disabled to prevent changes to the clock */ |
753 | local_irq_save(flags); | |
af24a4e4 | 754 | kvm_get_msr(v, MSR_IA32_TSC, &vcpu->hv_clock.tsc_timestamp); |
18068523 GOC |
755 | ktime_get_ts(&ts); |
756 | local_irq_restore(flags); | |
757 | ||
758 | /* With all the info we got, fill in the values */ | |
759 | ||
760 | vcpu->hv_clock.system_time = ts.tv_nsec + | |
afbcf7ab GC |
761 | (NSEC_PER_SEC * (u64)ts.tv_sec) + v->kvm->arch.kvmclock_offset; |
762 | ||
18068523 GOC |
763 | /* |
764 | * The interface expects us to write an even number signaling that the | |
765 | * update is finished. Since the guest won't see the intermediate | |
50d0a0f9 | 766 | * state, we just increase by 2 at the end. |
18068523 | 767 | */ |
50d0a0f9 | 768 | vcpu->hv_clock.version += 2; |
18068523 GOC |
769 | |
770 | shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0); | |
771 | ||
772 | memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock, | |
50d0a0f9 | 773 | sizeof(vcpu->hv_clock)); |
18068523 GOC |
774 | |
775 | kunmap_atomic(shared_kaddr, KM_USER0); | |
776 | ||
777 | mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT); | |
778 | } | |
779 | ||
c8076604 GH |
780 | static int kvm_request_guest_time_update(struct kvm_vcpu *v) |
781 | { | |
782 | struct kvm_vcpu_arch *vcpu = &v->arch; | |
783 | ||
784 | if (!vcpu->time_page) | |
785 | return 0; | |
786 | set_bit(KVM_REQ_KVMCLOCK_UPDATE, &v->requests); | |
787 | return 1; | |
788 | } | |
789 | ||
9ba075a6 AK |
790 | static bool msr_mtrr_valid(unsigned msr) |
791 | { | |
792 | switch (msr) { | |
793 | case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1: | |
794 | case MSR_MTRRfix64K_00000: | |
795 | case MSR_MTRRfix16K_80000: | |
796 | case MSR_MTRRfix16K_A0000: | |
797 | case MSR_MTRRfix4K_C0000: | |
798 | case MSR_MTRRfix4K_C8000: | |
799 | case MSR_MTRRfix4K_D0000: | |
800 | case MSR_MTRRfix4K_D8000: | |
801 | case MSR_MTRRfix4K_E0000: | |
802 | case MSR_MTRRfix4K_E8000: | |
803 | case MSR_MTRRfix4K_F0000: | |
804 | case MSR_MTRRfix4K_F8000: | |
805 | case MSR_MTRRdefType: | |
806 | case MSR_IA32_CR_PAT: | |
807 | return true; | |
808 | case 0x2f8: | |
809 | return true; | |
810 | } | |
811 | return false; | |
812 | } | |
813 | ||
d6289b93 MT |
814 | static bool valid_pat_type(unsigned t) |
815 | { | |
816 | return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */ | |
817 | } | |
818 | ||
819 | static bool valid_mtrr_type(unsigned t) | |
820 | { | |
821 | return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */ | |
822 | } | |
823 | ||
824 | static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data) | |
825 | { | |
826 | int i; | |
827 | ||
828 | if (!msr_mtrr_valid(msr)) | |
829 | return false; | |
830 | ||
831 | if (msr == MSR_IA32_CR_PAT) { | |
832 | for (i = 0; i < 8; i++) | |
833 | if (!valid_pat_type((data >> (i * 8)) & 0xff)) | |
834 | return false; | |
835 | return true; | |
836 | } else if (msr == MSR_MTRRdefType) { | |
837 | if (data & ~0xcff) | |
838 | return false; | |
839 | return valid_mtrr_type(data & 0xff); | |
840 | } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) { | |
841 | for (i = 0; i < 8 ; i++) | |
842 | if (!valid_mtrr_type((data >> (i * 8)) & 0xff)) | |
843 | return false; | |
844 | return true; | |
845 | } | |
846 | ||
847 | /* variable MTRRs */ | |
848 | return valid_mtrr_type(data & 0xff); | |
849 | } | |
850 | ||
9ba075a6 AK |
851 | static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data) |
852 | { | |
0bed3b56 SY |
853 | u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges; |
854 | ||
d6289b93 | 855 | if (!mtrr_valid(vcpu, msr, data)) |
9ba075a6 AK |
856 | return 1; |
857 | ||
0bed3b56 SY |
858 | if (msr == MSR_MTRRdefType) { |
859 | vcpu->arch.mtrr_state.def_type = data; | |
860 | vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10; | |
861 | } else if (msr == MSR_MTRRfix64K_00000) | |
862 | p[0] = data; | |
863 | else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000) | |
864 | p[1 + msr - MSR_MTRRfix16K_80000] = data; | |
865 | else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000) | |
866 | p[3 + msr - MSR_MTRRfix4K_C0000] = data; | |
867 | else if (msr == MSR_IA32_CR_PAT) | |
868 | vcpu->arch.pat = data; | |
869 | else { /* Variable MTRRs */ | |
870 | int idx, is_mtrr_mask; | |
871 | u64 *pt; | |
872 | ||
873 | idx = (msr - 0x200) / 2; | |
874 | is_mtrr_mask = msr - 0x200 - 2 * idx; | |
875 | if (!is_mtrr_mask) | |
876 | pt = | |
877 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo; | |
878 | else | |
879 | pt = | |
880 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo; | |
881 | *pt = data; | |
882 | } | |
883 | ||
884 | kvm_mmu_reset_context(vcpu); | |
9ba075a6 AK |
885 | return 0; |
886 | } | |
15c4a640 | 887 | |
890ca9ae | 888 | static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data) |
15c4a640 | 889 | { |
890ca9ae HY |
890 | u64 mcg_cap = vcpu->arch.mcg_cap; |
891 | unsigned bank_num = mcg_cap & 0xff; | |
892 | ||
15c4a640 | 893 | switch (msr) { |
15c4a640 | 894 | case MSR_IA32_MCG_STATUS: |
890ca9ae | 895 | vcpu->arch.mcg_status = data; |
15c4a640 | 896 | break; |
c7ac679c | 897 | case MSR_IA32_MCG_CTL: |
890ca9ae HY |
898 | if (!(mcg_cap & MCG_CTL_P)) |
899 | return 1; | |
900 | if (data != 0 && data != ~(u64)0) | |
901 | return -1; | |
902 | vcpu->arch.mcg_ctl = data; | |
903 | break; | |
904 | default: | |
905 | if (msr >= MSR_IA32_MC0_CTL && | |
906 | msr < MSR_IA32_MC0_CTL + 4 * bank_num) { | |
907 | u32 offset = msr - MSR_IA32_MC0_CTL; | |
908 | /* only 0 or all 1s can be written to IA32_MCi_CTL */ | |
909 | if ((offset & 0x3) == 0 && | |
910 | data != 0 && data != ~(u64)0) | |
911 | return -1; | |
912 | vcpu->arch.mce_banks[offset] = data; | |
913 | break; | |
914 | } | |
915 | return 1; | |
916 | } | |
917 | return 0; | |
918 | } | |
919 | ||
ffde22ac ES |
920 | static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data) |
921 | { | |
922 | struct kvm *kvm = vcpu->kvm; | |
923 | int lm = is_long_mode(vcpu); | |
924 | u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64 | |
925 | : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32; | |
926 | u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64 | |
927 | : kvm->arch.xen_hvm_config.blob_size_32; | |
928 | u32 page_num = data & ~PAGE_MASK; | |
929 | u64 page_addr = data & PAGE_MASK; | |
930 | u8 *page; | |
931 | int r; | |
932 | ||
933 | r = -E2BIG; | |
934 | if (page_num >= blob_size) | |
935 | goto out; | |
936 | r = -ENOMEM; | |
937 | page = kzalloc(PAGE_SIZE, GFP_KERNEL); | |
938 | if (!page) | |
939 | goto out; | |
940 | r = -EFAULT; | |
941 | if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE)) | |
942 | goto out_free; | |
943 | if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE)) | |
944 | goto out_free; | |
945 | r = 0; | |
946 | out_free: | |
947 | kfree(page); | |
948 | out: | |
949 | return r; | |
950 | } | |
951 | ||
15c4a640 CO |
952 | int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data) |
953 | { | |
954 | switch (msr) { | |
15c4a640 CO |
955 | case MSR_EFER: |
956 | set_efer(vcpu, data); | |
957 | break; | |
8f1589d9 AP |
958 | case MSR_K7_HWCR: |
959 | data &= ~(u64)0x40; /* ignore flush filter disable */ | |
960 | if (data != 0) { | |
961 | pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", | |
962 | data); | |
963 | return 1; | |
964 | } | |
15c4a640 | 965 | break; |
f7c6d140 AP |
966 | case MSR_FAM10H_MMIO_CONF_BASE: |
967 | if (data != 0) { | |
968 | pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " | |
969 | "0x%llx\n", data); | |
970 | return 1; | |
971 | } | |
15c4a640 | 972 | break; |
c323c0e5 | 973 | case MSR_AMD64_NB_CFG: |
c7ac679c | 974 | break; |
b5e2fec0 AG |
975 | case MSR_IA32_DEBUGCTLMSR: |
976 | if (!data) { | |
977 | /* We support the non-activated case already */ | |
978 | break; | |
979 | } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) { | |
980 | /* Values other than LBR and BTF are vendor-specific, | |
981 | thus reserved and should throw a #GP */ | |
982 | return 1; | |
983 | } | |
984 | pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n", | |
985 | __func__, data); | |
986 | break; | |
15c4a640 CO |
987 | case MSR_IA32_UCODE_REV: |
988 | case MSR_IA32_UCODE_WRITE: | |
61a6bd67 | 989 | case MSR_VM_HSAVE_PA: |
6098ca93 | 990 | case MSR_AMD64_PATCH_LOADER: |
15c4a640 | 991 | break; |
9ba075a6 AK |
992 | case 0x200 ... 0x2ff: |
993 | return set_msr_mtrr(vcpu, msr, data); | |
15c4a640 CO |
994 | case MSR_IA32_APICBASE: |
995 | kvm_set_apic_base(vcpu, data); | |
996 | break; | |
0105d1a5 GN |
997 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: |
998 | return kvm_x2apic_msr_write(vcpu, msr, data); | |
15c4a640 | 999 | case MSR_IA32_MISC_ENABLE: |
ad312c7c | 1000 | vcpu->arch.ia32_misc_enable_msr = data; |
15c4a640 | 1001 | break; |
18068523 GOC |
1002 | case MSR_KVM_WALL_CLOCK: |
1003 | vcpu->kvm->arch.wall_clock = data; | |
1004 | kvm_write_wall_clock(vcpu->kvm, data); | |
1005 | break; | |
1006 | case MSR_KVM_SYSTEM_TIME: { | |
1007 | if (vcpu->arch.time_page) { | |
1008 | kvm_release_page_dirty(vcpu->arch.time_page); | |
1009 | vcpu->arch.time_page = NULL; | |
1010 | } | |
1011 | ||
1012 | vcpu->arch.time = data; | |
1013 | ||
1014 | /* we verify if the enable bit is set... */ | |
1015 | if (!(data & 1)) | |
1016 | break; | |
1017 | ||
1018 | /* ...but clean it before doing the actual write */ | |
1019 | vcpu->arch.time_offset = data & ~(PAGE_MASK | 1); | |
1020 | ||
18068523 GOC |
1021 | vcpu->arch.time_page = |
1022 | gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT); | |
18068523 GOC |
1023 | |
1024 | if (is_error_page(vcpu->arch.time_page)) { | |
1025 | kvm_release_page_clean(vcpu->arch.time_page); | |
1026 | vcpu->arch.time_page = NULL; | |
1027 | } | |
1028 | ||
c8076604 | 1029 | kvm_request_guest_time_update(vcpu); |
18068523 GOC |
1030 | break; |
1031 | } | |
890ca9ae HY |
1032 | case MSR_IA32_MCG_CTL: |
1033 | case MSR_IA32_MCG_STATUS: | |
1034 | case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1: | |
1035 | return set_msr_mce(vcpu, msr, data); | |
71db6023 AP |
1036 | |
1037 | /* Performance counters are not protected by a CPUID bit, | |
1038 | * so we should check all of them in the generic path for the sake of | |
1039 | * cross vendor migration. | |
1040 | * Writing a zero into the event select MSRs disables them, | |
1041 | * which we perfectly emulate ;-). Any other value should be at least | |
1042 | * reported, some guests depend on them. | |
1043 | */ | |
1044 | case MSR_P6_EVNTSEL0: | |
1045 | case MSR_P6_EVNTSEL1: | |
1046 | case MSR_K7_EVNTSEL0: | |
1047 | case MSR_K7_EVNTSEL1: | |
1048 | case MSR_K7_EVNTSEL2: | |
1049 | case MSR_K7_EVNTSEL3: | |
1050 | if (data != 0) | |
1051 | pr_unimpl(vcpu, "unimplemented perfctr wrmsr: " | |
1052 | "0x%x data 0x%llx\n", msr, data); | |
1053 | break; | |
1054 | /* at least RHEL 4 unconditionally writes to the perfctr registers, | |
1055 | * so we ignore writes to make it happy. | |
1056 | */ | |
1057 | case MSR_P6_PERFCTR0: | |
1058 | case MSR_P6_PERFCTR1: | |
1059 | case MSR_K7_PERFCTR0: | |
1060 | case MSR_K7_PERFCTR1: | |
1061 | case MSR_K7_PERFCTR2: | |
1062 | case MSR_K7_PERFCTR3: | |
1063 | pr_unimpl(vcpu, "unimplemented perfctr wrmsr: " | |
1064 | "0x%x data 0x%llx\n", msr, data); | |
1065 | break; | |
15c4a640 | 1066 | default: |
ffde22ac ES |
1067 | if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr)) |
1068 | return xen_hvm_config(vcpu, data); | |
ed85c068 AP |
1069 | if (!ignore_msrs) { |
1070 | pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n", | |
1071 | msr, data); | |
1072 | return 1; | |
1073 | } else { | |
1074 | pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", | |
1075 | msr, data); | |
1076 | break; | |
1077 | } | |
15c4a640 CO |
1078 | } |
1079 | return 0; | |
1080 | } | |
1081 | EXPORT_SYMBOL_GPL(kvm_set_msr_common); | |
1082 | ||
1083 | ||
1084 | /* | |
1085 | * Reads an msr value (of 'msr_index') into 'pdata'. | |
1086 | * Returns 0 on success, non-0 otherwise. | |
1087 | * Assumes vcpu_load() was already called. | |
1088 | */ | |
1089 | int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata) | |
1090 | { | |
1091 | return kvm_x86_ops->get_msr(vcpu, msr_index, pdata); | |
1092 | } | |
1093 | ||
9ba075a6 AK |
1094 | static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) |
1095 | { | |
0bed3b56 SY |
1096 | u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges; |
1097 | ||
9ba075a6 AK |
1098 | if (!msr_mtrr_valid(msr)) |
1099 | return 1; | |
1100 | ||
0bed3b56 SY |
1101 | if (msr == MSR_MTRRdefType) |
1102 | *pdata = vcpu->arch.mtrr_state.def_type + | |
1103 | (vcpu->arch.mtrr_state.enabled << 10); | |
1104 | else if (msr == MSR_MTRRfix64K_00000) | |
1105 | *pdata = p[0]; | |
1106 | else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000) | |
1107 | *pdata = p[1 + msr - MSR_MTRRfix16K_80000]; | |
1108 | else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000) | |
1109 | *pdata = p[3 + msr - MSR_MTRRfix4K_C0000]; | |
1110 | else if (msr == MSR_IA32_CR_PAT) | |
1111 | *pdata = vcpu->arch.pat; | |
1112 | else { /* Variable MTRRs */ | |
1113 | int idx, is_mtrr_mask; | |
1114 | u64 *pt; | |
1115 | ||
1116 | idx = (msr - 0x200) / 2; | |
1117 | is_mtrr_mask = msr - 0x200 - 2 * idx; | |
1118 | if (!is_mtrr_mask) | |
1119 | pt = | |
1120 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo; | |
1121 | else | |
1122 | pt = | |
1123 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo; | |
1124 | *pdata = *pt; | |
1125 | } | |
1126 | ||
9ba075a6 AK |
1127 | return 0; |
1128 | } | |
1129 | ||
890ca9ae | 1130 | static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) |
15c4a640 CO |
1131 | { |
1132 | u64 data; | |
890ca9ae HY |
1133 | u64 mcg_cap = vcpu->arch.mcg_cap; |
1134 | unsigned bank_num = mcg_cap & 0xff; | |
15c4a640 CO |
1135 | |
1136 | switch (msr) { | |
15c4a640 CO |
1137 | case MSR_IA32_P5_MC_ADDR: |
1138 | case MSR_IA32_P5_MC_TYPE: | |
890ca9ae HY |
1139 | data = 0; |
1140 | break; | |
15c4a640 | 1141 | case MSR_IA32_MCG_CAP: |
890ca9ae HY |
1142 | data = vcpu->arch.mcg_cap; |
1143 | break; | |
c7ac679c | 1144 | case MSR_IA32_MCG_CTL: |
890ca9ae HY |
1145 | if (!(mcg_cap & MCG_CTL_P)) |
1146 | return 1; | |
1147 | data = vcpu->arch.mcg_ctl; | |
1148 | break; | |
1149 | case MSR_IA32_MCG_STATUS: | |
1150 | data = vcpu->arch.mcg_status; | |
1151 | break; | |
1152 | default: | |
1153 | if (msr >= MSR_IA32_MC0_CTL && | |
1154 | msr < MSR_IA32_MC0_CTL + 4 * bank_num) { | |
1155 | u32 offset = msr - MSR_IA32_MC0_CTL; | |
1156 | data = vcpu->arch.mce_banks[offset]; | |
1157 | break; | |
1158 | } | |
1159 | return 1; | |
1160 | } | |
1161 | *pdata = data; | |
1162 | return 0; | |
1163 | } | |
1164 | ||
1165 | int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) | |
1166 | { | |
1167 | u64 data; | |
1168 | ||
1169 | switch (msr) { | |
890ca9ae | 1170 | case MSR_IA32_PLATFORM_ID: |
15c4a640 | 1171 | case MSR_IA32_UCODE_REV: |
15c4a640 | 1172 | case MSR_IA32_EBL_CR_POWERON: |
b5e2fec0 AG |
1173 | case MSR_IA32_DEBUGCTLMSR: |
1174 | case MSR_IA32_LASTBRANCHFROMIP: | |
1175 | case MSR_IA32_LASTBRANCHTOIP: | |
1176 | case MSR_IA32_LASTINTFROMIP: | |
1177 | case MSR_IA32_LASTINTTOIP: | |
60af2ecd JSR |
1178 | case MSR_K8_SYSCFG: |
1179 | case MSR_K7_HWCR: | |
61a6bd67 | 1180 | case MSR_VM_HSAVE_PA: |
1f3ee616 AS |
1181 | case MSR_P6_PERFCTR0: |
1182 | case MSR_P6_PERFCTR1: | |
7fe29e0f AS |
1183 | case MSR_P6_EVNTSEL0: |
1184 | case MSR_P6_EVNTSEL1: | |
9e699624 | 1185 | case MSR_K7_EVNTSEL0: |
1f3ee616 | 1186 | case MSR_K7_PERFCTR0: |
1fdbd48c | 1187 | case MSR_K8_INT_PENDING_MSG: |
c323c0e5 | 1188 | case MSR_AMD64_NB_CFG: |
f7c6d140 | 1189 | case MSR_FAM10H_MMIO_CONF_BASE: |
15c4a640 CO |
1190 | data = 0; |
1191 | break; | |
9ba075a6 AK |
1192 | case MSR_MTRRcap: |
1193 | data = 0x500 | KVM_NR_VAR_MTRR; | |
1194 | break; | |
1195 | case 0x200 ... 0x2ff: | |
1196 | return get_msr_mtrr(vcpu, msr, pdata); | |
15c4a640 CO |
1197 | case 0xcd: /* fsb frequency */ |
1198 | data = 3; | |
1199 | break; | |
1200 | case MSR_IA32_APICBASE: | |
1201 | data = kvm_get_apic_base(vcpu); | |
1202 | break; | |
0105d1a5 GN |
1203 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff: |
1204 | return kvm_x2apic_msr_read(vcpu, msr, pdata); | |
1205 | break; | |
15c4a640 | 1206 | case MSR_IA32_MISC_ENABLE: |
ad312c7c | 1207 | data = vcpu->arch.ia32_misc_enable_msr; |
15c4a640 | 1208 | break; |
847f0ad8 AG |
1209 | case MSR_IA32_PERF_STATUS: |
1210 | /* TSC increment by tick */ | |
1211 | data = 1000ULL; | |
1212 | /* CPU multiplier */ | |
1213 | data |= (((uint64_t)4ULL) << 40); | |
1214 | break; | |
15c4a640 | 1215 | case MSR_EFER: |
ad312c7c | 1216 | data = vcpu->arch.shadow_efer; |
15c4a640 | 1217 | break; |
18068523 GOC |
1218 | case MSR_KVM_WALL_CLOCK: |
1219 | data = vcpu->kvm->arch.wall_clock; | |
1220 | break; | |
1221 | case MSR_KVM_SYSTEM_TIME: | |
1222 | data = vcpu->arch.time; | |
1223 | break; | |
890ca9ae HY |
1224 | case MSR_IA32_P5_MC_ADDR: |
1225 | case MSR_IA32_P5_MC_TYPE: | |
1226 | case MSR_IA32_MCG_CAP: | |
1227 | case MSR_IA32_MCG_CTL: | |
1228 | case MSR_IA32_MCG_STATUS: | |
1229 | case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1: | |
1230 | return get_msr_mce(vcpu, msr, pdata); | |
15c4a640 | 1231 | default: |
ed85c068 AP |
1232 | if (!ignore_msrs) { |
1233 | pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr); | |
1234 | return 1; | |
1235 | } else { | |
1236 | pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr); | |
1237 | data = 0; | |
1238 | } | |
1239 | break; | |
15c4a640 CO |
1240 | } |
1241 | *pdata = data; | |
1242 | return 0; | |
1243 | } | |
1244 | EXPORT_SYMBOL_GPL(kvm_get_msr_common); | |
1245 | ||
313a3dc7 CO |
1246 | /* |
1247 | * Read or write a bunch of msrs. All parameters are kernel addresses. | |
1248 | * | |
1249 | * @return number of msrs set successfully. | |
1250 | */ | |
1251 | static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, | |
1252 | struct kvm_msr_entry *entries, | |
1253 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
1254 | unsigned index, u64 *data)) | |
1255 | { | |
1256 | int i; | |
1257 | ||
1258 | vcpu_load(vcpu); | |
1259 | ||
3200f405 | 1260 | down_read(&vcpu->kvm->slots_lock); |
313a3dc7 CO |
1261 | for (i = 0; i < msrs->nmsrs; ++i) |
1262 | if (do_msr(vcpu, entries[i].index, &entries[i].data)) | |
1263 | break; | |
3200f405 | 1264 | up_read(&vcpu->kvm->slots_lock); |
313a3dc7 CO |
1265 | |
1266 | vcpu_put(vcpu); | |
1267 | ||
1268 | return i; | |
1269 | } | |
1270 | ||
1271 | /* | |
1272 | * Read or write a bunch of msrs. Parameters are user addresses. | |
1273 | * | |
1274 | * @return number of msrs set successfully. | |
1275 | */ | |
1276 | static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, | |
1277 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
1278 | unsigned index, u64 *data), | |
1279 | int writeback) | |
1280 | { | |
1281 | struct kvm_msrs msrs; | |
1282 | struct kvm_msr_entry *entries; | |
1283 | int r, n; | |
1284 | unsigned size; | |
1285 | ||
1286 | r = -EFAULT; | |
1287 | if (copy_from_user(&msrs, user_msrs, sizeof msrs)) | |
1288 | goto out; | |
1289 | ||
1290 | r = -E2BIG; | |
1291 | if (msrs.nmsrs >= MAX_IO_MSRS) | |
1292 | goto out; | |
1293 | ||
1294 | r = -ENOMEM; | |
1295 | size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; | |
1296 | entries = vmalloc(size); | |
1297 | if (!entries) | |
1298 | goto out; | |
1299 | ||
1300 | r = -EFAULT; | |
1301 | if (copy_from_user(entries, user_msrs->entries, size)) | |
1302 | goto out_free; | |
1303 | ||
1304 | r = n = __msr_io(vcpu, &msrs, entries, do_msr); | |
1305 | if (r < 0) | |
1306 | goto out_free; | |
1307 | ||
1308 | r = -EFAULT; | |
1309 | if (writeback && copy_to_user(user_msrs->entries, entries, size)) | |
1310 | goto out_free; | |
1311 | ||
1312 | r = n; | |
1313 | ||
1314 | out_free: | |
1315 | vfree(entries); | |
1316 | out: | |
1317 | return r; | |
1318 | } | |
1319 | ||
018d00d2 ZX |
1320 | int kvm_dev_ioctl_check_extension(long ext) |
1321 | { | |
1322 | int r; | |
1323 | ||
1324 | switch (ext) { | |
1325 | case KVM_CAP_IRQCHIP: | |
1326 | case KVM_CAP_HLT: | |
1327 | case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: | |
018d00d2 | 1328 | case KVM_CAP_SET_TSS_ADDR: |
07716717 | 1329 | case KVM_CAP_EXT_CPUID: |
c8076604 | 1330 | case KVM_CAP_CLOCKSOURCE: |
7837699f | 1331 | case KVM_CAP_PIT: |
a28e4f5a | 1332 | case KVM_CAP_NOP_IO_DELAY: |
62d9f0db | 1333 | case KVM_CAP_MP_STATE: |
ed848624 | 1334 | case KVM_CAP_SYNC_MMU: |
52d939a0 | 1335 | case KVM_CAP_REINJECT_CONTROL: |
4925663a | 1336 | case KVM_CAP_IRQ_INJECT_STATUS: |
e56d532f | 1337 | case KVM_CAP_ASSIGN_DEV_IRQ: |
721eecbf | 1338 | case KVM_CAP_IRQFD: |
d34e6b17 | 1339 | case KVM_CAP_IOEVENTFD: |
c5ff41ce | 1340 | case KVM_CAP_PIT2: |
e9f42757 | 1341 | case KVM_CAP_PIT_STATE2: |
b927a3ce | 1342 | case KVM_CAP_SET_IDENTITY_MAP_ADDR: |
ffde22ac | 1343 | case KVM_CAP_XEN_HVM: |
afbcf7ab | 1344 | case KVM_CAP_ADJUST_CLOCK: |
3cfc3092 | 1345 | case KVM_CAP_VCPU_EVENTS: |
018d00d2 ZX |
1346 | r = 1; |
1347 | break; | |
542472b5 LV |
1348 | case KVM_CAP_COALESCED_MMIO: |
1349 | r = KVM_COALESCED_MMIO_PAGE_OFFSET; | |
1350 | break; | |
774ead3a AK |
1351 | case KVM_CAP_VAPIC: |
1352 | r = !kvm_x86_ops->cpu_has_accelerated_tpr(); | |
1353 | break; | |
f725230a AK |
1354 | case KVM_CAP_NR_VCPUS: |
1355 | r = KVM_MAX_VCPUS; | |
1356 | break; | |
a988b910 AK |
1357 | case KVM_CAP_NR_MEMSLOTS: |
1358 | r = KVM_MEMORY_SLOTS; | |
1359 | break; | |
a68a6a72 MT |
1360 | case KVM_CAP_PV_MMU: /* obsolete */ |
1361 | r = 0; | |
2f333bcb | 1362 | break; |
62c476c7 | 1363 | case KVM_CAP_IOMMU: |
19de40a8 | 1364 | r = iommu_found(); |
62c476c7 | 1365 | break; |
890ca9ae HY |
1366 | case KVM_CAP_MCE: |
1367 | r = KVM_MAX_MCE_BANKS; | |
1368 | break; | |
018d00d2 ZX |
1369 | default: |
1370 | r = 0; | |
1371 | break; | |
1372 | } | |
1373 | return r; | |
1374 | ||
1375 | } | |
1376 | ||
043405e1 CO |
1377 | long kvm_arch_dev_ioctl(struct file *filp, |
1378 | unsigned int ioctl, unsigned long arg) | |
1379 | { | |
1380 | void __user *argp = (void __user *)arg; | |
1381 | long r; | |
1382 | ||
1383 | switch (ioctl) { | |
1384 | case KVM_GET_MSR_INDEX_LIST: { | |
1385 | struct kvm_msr_list __user *user_msr_list = argp; | |
1386 | struct kvm_msr_list msr_list; | |
1387 | unsigned n; | |
1388 | ||
1389 | r = -EFAULT; | |
1390 | if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list)) | |
1391 | goto out; | |
1392 | n = msr_list.nmsrs; | |
1393 | msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs); | |
1394 | if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list)) | |
1395 | goto out; | |
1396 | r = -E2BIG; | |
e125e7b6 | 1397 | if (n < msr_list.nmsrs) |
043405e1 CO |
1398 | goto out; |
1399 | r = -EFAULT; | |
1400 | if (copy_to_user(user_msr_list->indices, &msrs_to_save, | |
1401 | num_msrs_to_save * sizeof(u32))) | |
1402 | goto out; | |
e125e7b6 | 1403 | if (copy_to_user(user_msr_list->indices + num_msrs_to_save, |
043405e1 CO |
1404 | &emulated_msrs, |
1405 | ARRAY_SIZE(emulated_msrs) * sizeof(u32))) | |
1406 | goto out; | |
1407 | r = 0; | |
1408 | break; | |
1409 | } | |
674eea0f AK |
1410 | case KVM_GET_SUPPORTED_CPUID: { |
1411 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
1412 | struct kvm_cpuid2 cpuid; | |
1413 | ||
1414 | r = -EFAULT; | |
1415 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
1416 | goto out; | |
1417 | r = kvm_dev_ioctl_get_supported_cpuid(&cpuid, | |
19355475 | 1418 | cpuid_arg->entries); |
674eea0f AK |
1419 | if (r) |
1420 | goto out; | |
1421 | ||
1422 | r = -EFAULT; | |
1423 | if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) | |
1424 | goto out; | |
1425 | r = 0; | |
1426 | break; | |
1427 | } | |
890ca9ae HY |
1428 | case KVM_X86_GET_MCE_CAP_SUPPORTED: { |
1429 | u64 mce_cap; | |
1430 | ||
1431 | mce_cap = KVM_MCE_CAP_SUPPORTED; | |
1432 | r = -EFAULT; | |
1433 | if (copy_to_user(argp, &mce_cap, sizeof mce_cap)) | |
1434 | goto out; | |
1435 | r = 0; | |
1436 | break; | |
1437 | } | |
043405e1 CO |
1438 | default: |
1439 | r = -EINVAL; | |
1440 | } | |
1441 | out: | |
1442 | return r; | |
1443 | } | |
1444 | ||
313a3dc7 CO |
1445 | void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
1446 | { | |
1447 | kvm_x86_ops->vcpu_load(vcpu, cpu); | |
6b7d7e76 ZA |
1448 | if (unlikely(per_cpu(cpu_tsc_khz, cpu) == 0)) { |
1449 | unsigned long khz = cpufreq_quick_get(cpu); | |
1450 | if (!khz) | |
1451 | khz = tsc_khz; | |
1452 | per_cpu(cpu_tsc_khz, cpu) = khz; | |
1453 | } | |
c8076604 | 1454 | kvm_request_guest_time_update(vcpu); |
313a3dc7 CO |
1455 | } |
1456 | ||
1457 | void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) | |
1458 | { | |
1459 | kvm_x86_ops->vcpu_put(vcpu); | |
9327fd11 | 1460 | kvm_put_guest_fpu(vcpu); |
313a3dc7 CO |
1461 | } |
1462 | ||
07716717 | 1463 | static int is_efer_nx(void) |
313a3dc7 | 1464 | { |
e286e86e | 1465 | unsigned long long efer = 0; |
313a3dc7 | 1466 | |
e286e86e | 1467 | rdmsrl_safe(MSR_EFER, &efer); |
07716717 DK |
1468 | return efer & EFER_NX; |
1469 | } | |
1470 | ||
1471 | static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu) | |
1472 | { | |
1473 | int i; | |
1474 | struct kvm_cpuid_entry2 *e, *entry; | |
1475 | ||
313a3dc7 | 1476 | entry = NULL; |
ad312c7c ZX |
1477 | for (i = 0; i < vcpu->arch.cpuid_nent; ++i) { |
1478 | e = &vcpu->arch.cpuid_entries[i]; | |
313a3dc7 CO |
1479 | if (e->function == 0x80000001) { |
1480 | entry = e; | |
1481 | break; | |
1482 | } | |
1483 | } | |
07716717 | 1484 | if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) { |
313a3dc7 CO |
1485 | entry->edx &= ~(1 << 20); |
1486 | printk(KERN_INFO "kvm: guest NX capability removed\n"); | |
1487 | } | |
1488 | } | |
1489 | ||
07716717 | 1490 | /* when an old userspace process fills a new kernel module */ |
313a3dc7 CO |
1491 | static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu, |
1492 | struct kvm_cpuid *cpuid, | |
1493 | struct kvm_cpuid_entry __user *entries) | |
07716717 DK |
1494 | { |
1495 | int r, i; | |
1496 | struct kvm_cpuid_entry *cpuid_entries; | |
1497 | ||
1498 | r = -E2BIG; | |
1499 | if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) | |
1500 | goto out; | |
1501 | r = -ENOMEM; | |
1502 | cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent); | |
1503 | if (!cpuid_entries) | |
1504 | goto out; | |
1505 | r = -EFAULT; | |
1506 | if (copy_from_user(cpuid_entries, entries, | |
1507 | cpuid->nent * sizeof(struct kvm_cpuid_entry))) | |
1508 | goto out_free; | |
1509 | for (i = 0; i < cpuid->nent; i++) { | |
ad312c7c ZX |
1510 | vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function; |
1511 | vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax; | |
1512 | vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx; | |
1513 | vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx; | |
1514 | vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx; | |
1515 | vcpu->arch.cpuid_entries[i].index = 0; | |
1516 | vcpu->arch.cpuid_entries[i].flags = 0; | |
1517 | vcpu->arch.cpuid_entries[i].padding[0] = 0; | |
1518 | vcpu->arch.cpuid_entries[i].padding[1] = 0; | |
1519 | vcpu->arch.cpuid_entries[i].padding[2] = 0; | |
1520 | } | |
1521 | vcpu->arch.cpuid_nent = cpuid->nent; | |
07716717 DK |
1522 | cpuid_fix_nx_cap(vcpu); |
1523 | r = 0; | |
fc61b800 | 1524 | kvm_apic_set_version(vcpu); |
07716717 DK |
1525 | |
1526 | out_free: | |
1527 | vfree(cpuid_entries); | |
1528 | out: | |
1529 | return r; | |
1530 | } | |
1531 | ||
1532 | static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu, | |
19355475 AS |
1533 | struct kvm_cpuid2 *cpuid, |
1534 | struct kvm_cpuid_entry2 __user *entries) | |
313a3dc7 CO |
1535 | { |
1536 | int r; | |
1537 | ||
1538 | r = -E2BIG; | |
1539 | if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) | |
1540 | goto out; | |
1541 | r = -EFAULT; | |
ad312c7c | 1542 | if (copy_from_user(&vcpu->arch.cpuid_entries, entries, |
07716717 | 1543 | cpuid->nent * sizeof(struct kvm_cpuid_entry2))) |
313a3dc7 | 1544 | goto out; |
ad312c7c | 1545 | vcpu->arch.cpuid_nent = cpuid->nent; |
fc61b800 | 1546 | kvm_apic_set_version(vcpu); |
313a3dc7 CO |
1547 | return 0; |
1548 | ||
1549 | out: | |
1550 | return r; | |
1551 | } | |
1552 | ||
07716717 | 1553 | static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu, |
19355475 AS |
1554 | struct kvm_cpuid2 *cpuid, |
1555 | struct kvm_cpuid_entry2 __user *entries) | |
07716717 DK |
1556 | { |
1557 | int r; | |
1558 | ||
1559 | r = -E2BIG; | |
ad312c7c | 1560 | if (cpuid->nent < vcpu->arch.cpuid_nent) |
07716717 DK |
1561 | goto out; |
1562 | r = -EFAULT; | |
ad312c7c | 1563 | if (copy_to_user(entries, &vcpu->arch.cpuid_entries, |
19355475 | 1564 | vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2))) |
07716717 DK |
1565 | goto out; |
1566 | return 0; | |
1567 | ||
1568 | out: | |
ad312c7c | 1569 | cpuid->nent = vcpu->arch.cpuid_nent; |
07716717 DK |
1570 | return r; |
1571 | } | |
1572 | ||
07716717 | 1573 | static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function, |
19355475 | 1574 | u32 index) |
07716717 DK |
1575 | { |
1576 | entry->function = function; | |
1577 | entry->index = index; | |
1578 | cpuid_count(entry->function, entry->index, | |
19355475 | 1579 | &entry->eax, &entry->ebx, &entry->ecx, &entry->edx); |
07716717 DK |
1580 | entry->flags = 0; |
1581 | } | |
1582 | ||
7faa4ee1 AK |
1583 | #define F(x) bit(X86_FEATURE_##x) |
1584 | ||
07716717 DK |
1585 | static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function, |
1586 | u32 index, int *nent, int maxnent) | |
1587 | { | |
7faa4ee1 | 1588 | unsigned f_nx = is_efer_nx() ? F(NX) : 0; |
344f414f | 1589 | unsigned f_gbpages = kvm_x86_ops->gb_page_enable() ? F(GBPAGES) : 0; |
07716717 | 1590 | #ifdef CONFIG_X86_64 |
7faa4ee1 AK |
1591 | unsigned f_lm = F(LM); |
1592 | #else | |
1593 | unsigned f_lm = 0; | |
07716717 | 1594 | #endif |
7faa4ee1 AK |
1595 | |
1596 | /* cpuid 1.edx */ | |
1597 | const u32 kvm_supported_word0_x86_features = | |
1598 | F(FPU) | F(VME) | F(DE) | F(PSE) | | |
1599 | F(TSC) | F(MSR) | F(PAE) | F(MCE) | | |
1600 | F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) | | |
1601 | F(MTRR) | F(PGE) | F(MCA) | F(CMOV) | | |
1602 | F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) | | |
1603 | 0 /* Reserved, DS, ACPI */ | F(MMX) | | |
1604 | F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) | | |
1605 | 0 /* HTT, TM, Reserved, PBE */; | |
1606 | /* cpuid 0x80000001.edx */ | |
1607 | const u32 kvm_supported_word1_x86_features = | |
1608 | F(FPU) | F(VME) | F(DE) | F(PSE) | | |
1609 | F(TSC) | F(MSR) | F(PAE) | F(MCE) | | |
1610 | F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) | | |
1611 | F(MTRR) | F(PGE) | F(MCA) | F(CMOV) | | |
1612 | F(PAT) | F(PSE36) | 0 /* Reserved */ | | |
1613 | f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) | | |
344f414f | 1614 | F(FXSR) | F(FXSR_OPT) | f_gbpages | 0 /* RDTSCP */ | |
7faa4ee1 AK |
1615 | 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW); |
1616 | /* cpuid 1.ecx */ | |
1617 | const u32 kvm_supported_word4_x86_features = | |
d149c731 AK |
1618 | F(XMM3) | 0 /* Reserved, DTES64, MONITOR */ | |
1619 | 0 /* DS-CPL, VMX, SMX, EST */ | | |
1620 | 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ | | |
1621 | 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ | | |
1622 | 0 /* Reserved, DCA */ | F(XMM4_1) | | |
0105d1a5 | 1623 | F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) | |
d149c731 | 1624 | 0 /* Reserved, XSAVE, OSXSAVE */; |
7faa4ee1 | 1625 | /* cpuid 0x80000001.ecx */ |
07716717 | 1626 | const u32 kvm_supported_word6_x86_features = |
7faa4ee1 AK |
1627 | F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ | |
1628 | F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) | | |
1629 | F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) | | |
1630 | 0 /* SKINIT */ | 0 /* WDT */; | |
07716717 | 1631 | |
19355475 | 1632 | /* all calls to cpuid_count() should be made on the same cpu */ |
07716717 DK |
1633 | get_cpu(); |
1634 | do_cpuid_1_ent(entry, function, index); | |
1635 | ++*nent; | |
1636 | ||
1637 | switch (function) { | |
1638 | case 0: | |
1639 | entry->eax = min(entry->eax, (u32)0xb); | |
1640 | break; | |
1641 | case 1: | |
1642 | entry->edx &= kvm_supported_word0_x86_features; | |
7faa4ee1 | 1643 | entry->ecx &= kvm_supported_word4_x86_features; |
0d1de2d9 GN |
1644 | /* we support x2apic emulation even if host does not support |
1645 | * it since we emulate x2apic in software */ | |
1646 | entry->ecx |= F(X2APIC); | |
07716717 DK |
1647 | break; |
1648 | /* function 2 entries are STATEFUL. That is, repeated cpuid commands | |
1649 | * may return different values. This forces us to get_cpu() before | |
1650 | * issuing the first command, and also to emulate this annoying behavior | |
1651 | * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */ | |
1652 | case 2: { | |
1653 | int t, times = entry->eax & 0xff; | |
1654 | ||
1655 | entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC; | |
0fdf8e59 | 1656 | entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT; |
07716717 DK |
1657 | for (t = 1; t < times && *nent < maxnent; ++t) { |
1658 | do_cpuid_1_ent(&entry[t], function, 0); | |
1659 | entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC; | |
1660 | ++*nent; | |
1661 | } | |
1662 | break; | |
1663 | } | |
1664 | /* function 4 and 0xb have additional index. */ | |
1665 | case 4: { | |
14af3f3c | 1666 | int i, cache_type; |
07716717 DK |
1667 | |
1668 | entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; | |
1669 | /* read more entries until cache_type is zero */ | |
14af3f3c HH |
1670 | for (i = 1; *nent < maxnent; ++i) { |
1671 | cache_type = entry[i - 1].eax & 0x1f; | |
07716717 DK |
1672 | if (!cache_type) |
1673 | break; | |
14af3f3c HH |
1674 | do_cpuid_1_ent(&entry[i], function, i); |
1675 | entry[i].flags |= | |
07716717 DK |
1676 | KVM_CPUID_FLAG_SIGNIFCANT_INDEX; |
1677 | ++*nent; | |
1678 | } | |
1679 | break; | |
1680 | } | |
1681 | case 0xb: { | |
14af3f3c | 1682 | int i, level_type; |
07716717 DK |
1683 | |
1684 | entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; | |
1685 | /* read more entries until level_type is zero */ | |
14af3f3c | 1686 | for (i = 1; *nent < maxnent; ++i) { |
0853d2c1 | 1687 | level_type = entry[i - 1].ecx & 0xff00; |
07716717 DK |
1688 | if (!level_type) |
1689 | break; | |
14af3f3c HH |
1690 | do_cpuid_1_ent(&entry[i], function, i); |
1691 | entry[i].flags |= | |
07716717 DK |
1692 | KVM_CPUID_FLAG_SIGNIFCANT_INDEX; |
1693 | ++*nent; | |
1694 | } | |
1695 | break; | |
1696 | } | |
1697 | case 0x80000000: | |
1698 | entry->eax = min(entry->eax, 0x8000001a); | |
1699 | break; | |
1700 | case 0x80000001: | |
1701 | entry->edx &= kvm_supported_word1_x86_features; | |
1702 | entry->ecx &= kvm_supported_word6_x86_features; | |
1703 | break; | |
1704 | } | |
1705 | put_cpu(); | |
1706 | } | |
1707 | ||
7faa4ee1 AK |
1708 | #undef F |
1709 | ||
674eea0f | 1710 | static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid, |
19355475 | 1711 | struct kvm_cpuid_entry2 __user *entries) |
07716717 DK |
1712 | { |
1713 | struct kvm_cpuid_entry2 *cpuid_entries; | |
1714 | int limit, nent = 0, r = -E2BIG; | |
1715 | u32 func; | |
1716 | ||
1717 | if (cpuid->nent < 1) | |
1718 | goto out; | |
6a544355 AK |
1719 | if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) |
1720 | cpuid->nent = KVM_MAX_CPUID_ENTRIES; | |
07716717 DK |
1721 | r = -ENOMEM; |
1722 | cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent); | |
1723 | if (!cpuid_entries) | |
1724 | goto out; | |
1725 | ||
1726 | do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent); | |
1727 | limit = cpuid_entries[0].eax; | |
1728 | for (func = 1; func <= limit && nent < cpuid->nent; ++func) | |
1729 | do_cpuid_ent(&cpuid_entries[nent], func, 0, | |
19355475 | 1730 | &nent, cpuid->nent); |
07716717 DK |
1731 | r = -E2BIG; |
1732 | if (nent >= cpuid->nent) | |
1733 | goto out_free; | |
1734 | ||
1735 | do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent); | |
1736 | limit = cpuid_entries[nent - 1].eax; | |
1737 | for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func) | |
1738 | do_cpuid_ent(&cpuid_entries[nent], func, 0, | |
19355475 | 1739 | &nent, cpuid->nent); |
cb007648 MM |
1740 | r = -E2BIG; |
1741 | if (nent >= cpuid->nent) | |
1742 | goto out_free; | |
1743 | ||
07716717 DK |
1744 | r = -EFAULT; |
1745 | if (copy_to_user(entries, cpuid_entries, | |
19355475 | 1746 | nent * sizeof(struct kvm_cpuid_entry2))) |
07716717 DK |
1747 | goto out_free; |
1748 | cpuid->nent = nent; | |
1749 | r = 0; | |
1750 | ||
1751 | out_free: | |
1752 | vfree(cpuid_entries); | |
1753 | out: | |
1754 | return r; | |
1755 | } | |
1756 | ||
313a3dc7 CO |
1757 | static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, |
1758 | struct kvm_lapic_state *s) | |
1759 | { | |
1760 | vcpu_load(vcpu); | |
ad312c7c | 1761 | memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s); |
313a3dc7 CO |
1762 | vcpu_put(vcpu); |
1763 | ||
1764 | return 0; | |
1765 | } | |
1766 | ||
1767 | static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, | |
1768 | struct kvm_lapic_state *s) | |
1769 | { | |
1770 | vcpu_load(vcpu); | |
ad312c7c | 1771 | memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s); |
313a3dc7 | 1772 | kvm_apic_post_state_restore(vcpu); |
cb142eb7 | 1773 | update_cr8_intercept(vcpu); |
313a3dc7 CO |
1774 | vcpu_put(vcpu); |
1775 | ||
1776 | return 0; | |
1777 | } | |
1778 | ||
f77bc6a4 ZX |
1779 | static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, |
1780 | struct kvm_interrupt *irq) | |
1781 | { | |
1782 | if (irq->irq < 0 || irq->irq >= 256) | |
1783 | return -EINVAL; | |
1784 | if (irqchip_in_kernel(vcpu->kvm)) | |
1785 | return -ENXIO; | |
1786 | vcpu_load(vcpu); | |
1787 | ||
66fd3f7f | 1788 | kvm_queue_interrupt(vcpu, irq->irq, false); |
f77bc6a4 ZX |
1789 | |
1790 | vcpu_put(vcpu); | |
1791 | ||
1792 | return 0; | |
1793 | } | |
1794 | ||
c4abb7c9 JK |
1795 | static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) |
1796 | { | |
1797 | vcpu_load(vcpu); | |
1798 | kvm_inject_nmi(vcpu); | |
1799 | vcpu_put(vcpu); | |
1800 | ||
1801 | return 0; | |
1802 | } | |
1803 | ||
b209749f AK |
1804 | static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, |
1805 | struct kvm_tpr_access_ctl *tac) | |
1806 | { | |
1807 | if (tac->flags) | |
1808 | return -EINVAL; | |
1809 | vcpu->arch.tpr_access_reporting = !!tac->enabled; | |
1810 | return 0; | |
1811 | } | |
1812 | ||
890ca9ae HY |
1813 | static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, |
1814 | u64 mcg_cap) | |
1815 | { | |
1816 | int r; | |
1817 | unsigned bank_num = mcg_cap & 0xff, bank; | |
1818 | ||
1819 | r = -EINVAL; | |
a9e38c3e | 1820 | if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS) |
890ca9ae HY |
1821 | goto out; |
1822 | if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000)) | |
1823 | goto out; | |
1824 | r = 0; | |
1825 | vcpu->arch.mcg_cap = mcg_cap; | |
1826 | /* Init IA32_MCG_CTL to all 1s */ | |
1827 | if (mcg_cap & MCG_CTL_P) | |
1828 | vcpu->arch.mcg_ctl = ~(u64)0; | |
1829 | /* Init IA32_MCi_CTL to all 1s */ | |
1830 | for (bank = 0; bank < bank_num; bank++) | |
1831 | vcpu->arch.mce_banks[bank*4] = ~(u64)0; | |
1832 | out: | |
1833 | return r; | |
1834 | } | |
1835 | ||
1836 | static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, | |
1837 | struct kvm_x86_mce *mce) | |
1838 | { | |
1839 | u64 mcg_cap = vcpu->arch.mcg_cap; | |
1840 | unsigned bank_num = mcg_cap & 0xff; | |
1841 | u64 *banks = vcpu->arch.mce_banks; | |
1842 | ||
1843 | if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) | |
1844 | return -EINVAL; | |
1845 | /* | |
1846 | * if IA32_MCG_CTL is not all 1s, the uncorrected error | |
1847 | * reporting is disabled | |
1848 | */ | |
1849 | if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && | |
1850 | vcpu->arch.mcg_ctl != ~(u64)0) | |
1851 | return 0; | |
1852 | banks += 4 * mce->bank; | |
1853 | /* | |
1854 | * if IA32_MCi_CTL is not all 1s, the uncorrected error | |
1855 | * reporting is disabled for the bank | |
1856 | */ | |
1857 | if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) | |
1858 | return 0; | |
1859 | if (mce->status & MCI_STATUS_UC) { | |
1860 | if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || | |
1861 | !(vcpu->arch.cr4 & X86_CR4_MCE)) { | |
1862 | printk(KERN_DEBUG "kvm: set_mce: " | |
1863 | "injects mce exception while " | |
1864 | "previous one is in progress!\n"); | |
1865 | set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests); | |
1866 | return 0; | |
1867 | } | |
1868 | if (banks[1] & MCI_STATUS_VAL) | |
1869 | mce->status |= MCI_STATUS_OVER; | |
1870 | banks[2] = mce->addr; | |
1871 | banks[3] = mce->misc; | |
1872 | vcpu->arch.mcg_status = mce->mcg_status; | |
1873 | banks[1] = mce->status; | |
1874 | kvm_queue_exception(vcpu, MC_VECTOR); | |
1875 | } else if (!(banks[1] & MCI_STATUS_VAL) | |
1876 | || !(banks[1] & MCI_STATUS_UC)) { | |
1877 | if (banks[1] & MCI_STATUS_VAL) | |
1878 | mce->status |= MCI_STATUS_OVER; | |
1879 | banks[2] = mce->addr; | |
1880 | banks[3] = mce->misc; | |
1881 | banks[1] = mce->status; | |
1882 | } else | |
1883 | banks[1] |= MCI_STATUS_OVER; | |
1884 | return 0; | |
1885 | } | |
1886 | ||
3cfc3092 JK |
1887 | static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, |
1888 | struct kvm_vcpu_events *events) | |
1889 | { | |
1890 | vcpu_load(vcpu); | |
1891 | ||
1892 | events->exception.injected = vcpu->arch.exception.pending; | |
1893 | events->exception.nr = vcpu->arch.exception.nr; | |
1894 | events->exception.has_error_code = vcpu->arch.exception.has_error_code; | |
1895 | events->exception.error_code = vcpu->arch.exception.error_code; | |
1896 | ||
1897 | events->interrupt.injected = vcpu->arch.interrupt.pending; | |
1898 | events->interrupt.nr = vcpu->arch.interrupt.nr; | |
1899 | events->interrupt.soft = vcpu->arch.interrupt.soft; | |
1900 | ||
1901 | events->nmi.injected = vcpu->arch.nmi_injected; | |
1902 | events->nmi.pending = vcpu->arch.nmi_pending; | |
1903 | events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu); | |
1904 | ||
1905 | events->sipi_vector = vcpu->arch.sipi_vector; | |
1906 | ||
1907 | events->flags = 0; | |
1908 | ||
1909 | vcpu_put(vcpu); | |
1910 | } | |
1911 | ||
1912 | static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, | |
1913 | struct kvm_vcpu_events *events) | |
1914 | { | |
1915 | if (events->flags) | |
1916 | return -EINVAL; | |
1917 | ||
1918 | vcpu_load(vcpu); | |
1919 | ||
1920 | vcpu->arch.exception.pending = events->exception.injected; | |
1921 | vcpu->arch.exception.nr = events->exception.nr; | |
1922 | vcpu->arch.exception.has_error_code = events->exception.has_error_code; | |
1923 | vcpu->arch.exception.error_code = events->exception.error_code; | |
1924 | ||
1925 | vcpu->arch.interrupt.pending = events->interrupt.injected; | |
1926 | vcpu->arch.interrupt.nr = events->interrupt.nr; | |
1927 | vcpu->arch.interrupt.soft = events->interrupt.soft; | |
1928 | if (vcpu->arch.interrupt.pending && irqchip_in_kernel(vcpu->kvm)) | |
1929 | kvm_pic_clear_isr_ack(vcpu->kvm); | |
1930 | ||
1931 | vcpu->arch.nmi_injected = events->nmi.injected; | |
1932 | vcpu->arch.nmi_pending = events->nmi.pending; | |
1933 | kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked); | |
1934 | ||
1935 | vcpu->arch.sipi_vector = events->sipi_vector; | |
1936 | ||
1937 | vcpu_put(vcpu); | |
1938 | ||
1939 | return 0; | |
1940 | } | |
1941 | ||
313a3dc7 CO |
1942 | long kvm_arch_vcpu_ioctl(struct file *filp, |
1943 | unsigned int ioctl, unsigned long arg) | |
1944 | { | |
1945 | struct kvm_vcpu *vcpu = filp->private_data; | |
1946 | void __user *argp = (void __user *)arg; | |
1947 | int r; | |
b772ff36 | 1948 | struct kvm_lapic_state *lapic = NULL; |
313a3dc7 CO |
1949 | |
1950 | switch (ioctl) { | |
1951 | case KVM_GET_LAPIC: { | |
2204ae3c MT |
1952 | r = -EINVAL; |
1953 | if (!vcpu->arch.apic) | |
1954 | goto out; | |
b772ff36 | 1955 | lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL); |
313a3dc7 | 1956 | |
b772ff36 DH |
1957 | r = -ENOMEM; |
1958 | if (!lapic) | |
1959 | goto out; | |
1960 | r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic); | |
313a3dc7 CO |
1961 | if (r) |
1962 | goto out; | |
1963 | r = -EFAULT; | |
b772ff36 | 1964 | if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state))) |
313a3dc7 CO |
1965 | goto out; |
1966 | r = 0; | |
1967 | break; | |
1968 | } | |
1969 | case KVM_SET_LAPIC: { | |
2204ae3c MT |
1970 | r = -EINVAL; |
1971 | if (!vcpu->arch.apic) | |
1972 | goto out; | |
b772ff36 DH |
1973 | lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL); |
1974 | r = -ENOMEM; | |
1975 | if (!lapic) | |
1976 | goto out; | |
313a3dc7 | 1977 | r = -EFAULT; |
b772ff36 | 1978 | if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state))) |
313a3dc7 | 1979 | goto out; |
b772ff36 | 1980 | r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic); |
313a3dc7 CO |
1981 | if (r) |
1982 | goto out; | |
1983 | r = 0; | |
1984 | break; | |
1985 | } | |
f77bc6a4 ZX |
1986 | case KVM_INTERRUPT: { |
1987 | struct kvm_interrupt irq; | |
1988 | ||
1989 | r = -EFAULT; | |
1990 | if (copy_from_user(&irq, argp, sizeof irq)) | |
1991 | goto out; | |
1992 | r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); | |
1993 | if (r) | |
1994 | goto out; | |
1995 | r = 0; | |
1996 | break; | |
1997 | } | |
c4abb7c9 JK |
1998 | case KVM_NMI: { |
1999 | r = kvm_vcpu_ioctl_nmi(vcpu); | |
2000 | if (r) | |
2001 | goto out; | |
2002 | r = 0; | |
2003 | break; | |
2004 | } | |
313a3dc7 CO |
2005 | case KVM_SET_CPUID: { |
2006 | struct kvm_cpuid __user *cpuid_arg = argp; | |
2007 | struct kvm_cpuid cpuid; | |
2008 | ||
2009 | r = -EFAULT; | |
2010 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
2011 | goto out; | |
2012 | r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); | |
2013 | if (r) | |
2014 | goto out; | |
2015 | break; | |
2016 | } | |
07716717 DK |
2017 | case KVM_SET_CPUID2: { |
2018 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
2019 | struct kvm_cpuid2 cpuid; | |
2020 | ||
2021 | r = -EFAULT; | |
2022 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
2023 | goto out; | |
2024 | r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, | |
19355475 | 2025 | cpuid_arg->entries); |
07716717 DK |
2026 | if (r) |
2027 | goto out; | |
2028 | break; | |
2029 | } | |
2030 | case KVM_GET_CPUID2: { | |
2031 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
2032 | struct kvm_cpuid2 cpuid; | |
2033 | ||
2034 | r = -EFAULT; | |
2035 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
2036 | goto out; | |
2037 | r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, | |
19355475 | 2038 | cpuid_arg->entries); |
07716717 DK |
2039 | if (r) |
2040 | goto out; | |
2041 | r = -EFAULT; | |
2042 | if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) | |
2043 | goto out; | |
2044 | r = 0; | |
2045 | break; | |
2046 | } | |
313a3dc7 CO |
2047 | case KVM_GET_MSRS: |
2048 | r = msr_io(vcpu, argp, kvm_get_msr, 1); | |
2049 | break; | |
2050 | case KVM_SET_MSRS: | |
2051 | r = msr_io(vcpu, argp, do_set_msr, 0); | |
2052 | break; | |
b209749f AK |
2053 | case KVM_TPR_ACCESS_REPORTING: { |
2054 | struct kvm_tpr_access_ctl tac; | |
2055 | ||
2056 | r = -EFAULT; | |
2057 | if (copy_from_user(&tac, argp, sizeof tac)) | |
2058 | goto out; | |
2059 | r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); | |
2060 | if (r) | |
2061 | goto out; | |
2062 | r = -EFAULT; | |
2063 | if (copy_to_user(argp, &tac, sizeof tac)) | |
2064 | goto out; | |
2065 | r = 0; | |
2066 | break; | |
2067 | }; | |
b93463aa AK |
2068 | case KVM_SET_VAPIC_ADDR: { |
2069 | struct kvm_vapic_addr va; | |
2070 | ||
2071 | r = -EINVAL; | |
2072 | if (!irqchip_in_kernel(vcpu->kvm)) | |
2073 | goto out; | |
2074 | r = -EFAULT; | |
2075 | if (copy_from_user(&va, argp, sizeof va)) | |
2076 | goto out; | |
2077 | r = 0; | |
2078 | kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); | |
2079 | break; | |
2080 | } | |
890ca9ae HY |
2081 | case KVM_X86_SETUP_MCE: { |
2082 | u64 mcg_cap; | |
2083 | ||
2084 | r = -EFAULT; | |
2085 | if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap)) | |
2086 | goto out; | |
2087 | r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); | |
2088 | break; | |
2089 | } | |
2090 | case KVM_X86_SET_MCE: { | |
2091 | struct kvm_x86_mce mce; | |
2092 | ||
2093 | r = -EFAULT; | |
2094 | if (copy_from_user(&mce, argp, sizeof mce)) | |
2095 | goto out; | |
2096 | r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); | |
2097 | break; | |
2098 | } | |
3cfc3092 JK |
2099 | case KVM_GET_VCPU_EVENTS: { |
2100 | struct kvm_vcpu_events events; | |
2101 | ||
2102 | kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); | |
2103 | ||
2104 | r = -EFAULT; | |
2105 | if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) | |
2106 | break; | |
2107 | r = 0; | |
2108 | break; | |
2109 | } | |
2110 | case KVM_SET_VCPU_EVENTS: { | |
2111 | struct kvm_vcpu_events events; | |
2112 | ||
2113 | r = -EFAULT; | |
2114 | if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) | |
2115 | break; | |
2116 | ||
2117 | r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); | |
2118 | break; | |
2119 | } | |
313a3dc7 CO |
2120 | default: |
2121 | r = -EINVAL; | |
2122 | } | |
2123 | out: | |
7a6ce84c | 2124 | kfree(lapic); |
313a3dc7 CO |
2125 | return r; |
2126 | } | |
2127 | ||
1fe779f8 CO |
2128 | static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) |
2129 | { | |
2130 | int ret; | |
2131 | ||
2132 | if (addr > (unsigned int)(-3 * PAGE_SIZE)) | |
2133 | return -1; | |
2134 | ret = kvm_x86_ops->set_tss_addr(kvm, addr); | |
2135 | return ret; | |
2136 | } | |
2137 | ||
b927a3ce SY |
2138 | static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, |
2139 | u64 ident_addr) | |
2140 | { | |
2141 | kvm->arch.ept_identity_map_addr = ident_addr; | |
2142 | return 0; | |
2143 | } | |
2144 | ||
1fe779f8 CO |
2145 | static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, |
2146 | u32 kvm_nr_mmu_pages) | |
2147 | { | |
2148 | if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) | |
2149 | return -EINVAL; | |
2150 | ||
72dc67a6 | 2151 | down_write(&kvm->slots_lock); |
7c8a83b7 | 2152 | spin_lock(&kvm->mmu_lock); |
1fe779f8 CO |
2153 | |
2154 | kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); | |
f05e70ac | 2155 | kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; |
1fe779f8 | 2156 | |
7c8a83b7 | 2157 | spin_unlock(&kvm->mmu_lock); |
72dc67a6 | 2158 | up_write(&kvm->slots_lock); |
1fe779f8 CO |
2159 | return 0; |
2160 | } | |
2161 | ||
2162 | static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) | |
2163 | { | |
f05e70ac | 2164 | return kvm->arch.n_alloc_mmu_pages; |
1fe779f8 CO |
2165 | } |
2166 | ||
e9f85cde ZX |
2167 | gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn) |
2168 | { | |
2169 | int i; | |
2170 | struct kvm_mem_alias *alias; | |
2171 | ||
d69fb81f ZX |
2172 | for (i = 0; i < kvm->arch.naliases; ++i) { |
2173 | alias = &kvm->arch.aliases[i]; | |
e9f85cde ZX |
2174 | if (gfn >= alias->base_gfn |
2175 | && gfn < alias->base_gfn + alias->npages) | |
2176 | return alias->target_gfn + gfn - alias->base_gfn; | |
2177 | } | |
2178 | return gfn; | |
2179 | } | |
2180 | ||
1fe779f8 CO |
2181 | /* |
2182 | * Set a new alias region. Aliases map a portion of physical memory into | |
2183 | * another portion. This is useful for memory windows, for example the PC | |
2184 | * VGA region. | |
2185 | */ | |
2186 | static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm, | |
2187 | struct kvm_memory_alias *alias) | |
2188 | { | |
2189 | int r, n; | |
2190 | struct kvm_mem_alias *p; | |
2191 | ||
2192 | r = -EINVAL; | |
2193 | /* General sanity checks */ | |
2194 | if (alias->memory_size & (PAGE_SIZE - 1)) | |
2195 | goto out; | |
2196 | if (alias->guest_phys_addr & (PAGE_SIZE - 1)) | |
2197 | goto out; | |
2198 | if (alias->slot >= KVM_ALIAS_SLOTS) | |
2199 | goto out; | |
2200 | if (alias->guest_phys_addr + alias->memory_size | |
2201 | < alias->guest_phys_addr) | |
2202 | goto out; | |
2203 | if (alias->target_phys_addr + alias->memory_size | |
2204 | < alias->target_phys_addr) | |
2205 | goto out; | |
2206 | ||
72dc67a6 | 2207 | down_write(&kvm->slots_lock); |
a1708ce8 | 2208 | spin_lock(&kvm->mmu_lock); |
1fe779f8 | 2209 | |
d69fb81f | 2210 | p = &kvm->arch.aliases[alias->slot]; |
1fe779f8 CO |
2211 | p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT; |
2212 | p->npages = alias->memory_size >> PAGE_SHIFT; | |
2213 | p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT; | |
2214 | ||
2215 | for (n = KVM_ALIAS_SLOTS; n > 0; --n) | |
d69fb81f | 2216 | if (kvm->arch.aliases[n - 1].npages) |
1fe779f8 | 2217 | break; |
d69fb81f | 2218 | kvm->arch.naliases = n; |
1fe779f8 | 2219 | |
a1708ce8 | 2220 | spin_unlock(&kvm->mmu_lock); |
1fe779f8 CO |
2221 | kvm_mmu_zap_all(kvm); |
2222 | ||
72dc67a6 | 2223 | up_write(&kvm->slots_lock); |
1fe779f8 CO |
2224 | |
2225 | return 0; | |
2226 | ||
2227 | out: | |
2228 | return r; | |
2229 | } | |
2230 | ||
2231 | static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) | |
2232 | { | |
2233 | int r; | |
2234 | ||
2235 | r = 0; | |
2236 | switch (chip->chip_id) { | |
2237 | case KVM_IRQCHIP_PIC_MASTER: | |
2238 | memcpy(&chip->chip.pic, | |
2239 | &pic_irqchip(kvm)->pics[0], | |
2240 | sizeof(struct kvm_pic_state)); | |
2241 | break; | |
2242 | case KVM_IRQCHIP_PIC_SLAVE: | |
2243 | memcpy(&chip->chip.pic, | |
2244 | &pic_irqchip(kvm)->pics[1], | |
2245 | sizeof(struct kvm_pic_state)); | |
2246 | break; | |
2247 | case KVM_IRQCHIP_IOAPIC: | |
eba0226b | 2248 | r = kvm_get_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
2249 | break; |
2250 | default: | |
2251 | r = -EINVAL; | |
2252 | break; | |
2253 | } | |
2254 | return r; | |
2255 | } | |
2256 | ||
2257 | static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) | |
2258 | { | |
2259 | int r; | |
2260 | ||
2261 | r = 0; | |
2262 | switch (chip->chip_id) { | |
2263 | case KVM_IRQCHIP_PIC_MASTER: | |
894a9c55 | 2264 | spin_lock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
2265 | memcpy(&pic_irqchip(kvm)->pics[0], |
2266 | &chip->chip.pic, | |
2267 | sizeof(struct kvm_pic_state)); | |
894a9c55 | 2268 | spin_unlock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
2269 | break; |
2270 | case KVM_IRQCHIP_PIC_SLAVE: | |
894a9c55 | 2271 | spin_lock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
2272 | memcpy(&pic_irqchip(kvm)->pics[1], |
2273 | &chip->chip.pic, | |
2274 | sizeof(struct kvm_pic_state)); | |
894a9c55 | 2275 | spin_unlock(&pic_irqchip(kvm)->lock); |
1fe779f8 CO |
2276 | break; |
2277 | case KVM_IRQCHIP_IOAPIC: | |
eba0226b | 2278 | r = kvm_set_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
2279 | break; |
2280 | default: | |
2281 | r = -EINVAL; | |
2282 | break; | |
2283 | } | |
2284 | kvm_pic_update_irq(pic_irqchip(kvm)); | |
2285 | return r; | |
2286 | } | |
2287 | ||
e0f63cb9 SY |
2288 | static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) |
2289 | { | |
2290 | int r = 0; | |
2291 | ||
894a9c55 | 2292 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
e0f63cb9 | 2293 | memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state)); |
894a9c55 | 2294 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); |
e0f63cb9 SY |
2295 | return r; |
2296 | } | |
2297 | ||
2298 | static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) | |
2299 | { | |
2300 | int r = 0; | |
2301 | ||
894a9c55 | 2302 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
e0f63cb9 | 2303 | memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state)); |
e9f42757 BK |
2304 | kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0); |
2305 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); | |
2306 | return r; | |
2307 | } | |
2308 | ||
2309 | static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
2310 | { | |
2311 | int r = 0; | |
2312 | ||
2313 | mutex_lock(&kvm->arch.vpit->pit_state.lock); | |
2314 | memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, | |
2315 | sizeof(ps->channels)); | |
2316 | ps->flags = kvm->arch.vpit->pit_state.flags; | |
2317 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); | |
2318 | return r; | |
2319 | } | |
2320 | ||
2321 | static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
2322 | { | |
2323 | int r = 0, start = 0; | |
2324 | u32 prev_legacy, cur_legacy; | |
2325 | mutex_lock(&kvm->arch.vpit->pit_state.lock); | |
2326 | prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; | |
2327 | cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; | |
2328 | if (!prev_legacy && cur_legacy) | |
2329 | start = 1; | |
2330 | memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels, | |
2331 | sizeof(kvm->arch.vpit->pit_state.channels)); | |
2332 | kvm->arch.vpit->pit_state.flags = ps->flags; | |
2333 | kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start); | |
894a9c55 | 2334 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); |
e0f63cb9 SY |
2335 | return r; |
2336 | } | |
2337 | ||
52d939a0 MT |
2338 | static int kvm_vm_ioctl_reinject(struct kvm *kvm, |
2339 | struct kvm_reinject_control *control) | |
2340 | { | |
2341 | if (!kvm->arch.vpit) | |
2342 | return -ENXIO; | |
894a9c55 | 2343 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
52d939a0 | 2344 | kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject; |
894a9c55 | 2345 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); |
52d939a0 MT |
2346 | return 0; |
2347 | } | |
2348 | ||
5bb064dc ZX |
2349 | /* |
2350 | * Get (and clear) the dirty memory log for a memory slot. | |
2351 | */ | |
2352 | int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, | |
2353 | struct kvm_dirty_log *log) | |
2354 | { | |
2355 | int r; | |
2356 | int n; | |
2357 | struct kvm_memory_slot *memslot; | |
2358 | int is_dirty = 0; | |
2359 | ||
72dc67a6 | 2360 | down_write(&kvm->slots_lock); |
5bb064dc ZX |
2361 | |
2362 | r = kvm_get_dirty_log(kvm, log, &is_dirty); | |
2363 | if (r) | |
2364 | goto out; | |
2365 | ||
2366 | /* If nothing is dirty, don't bother messing with page tables. */ | |
2367 | if (is_dirty) { | |
7c8a83b7 | 2368 | spin_lock(&kvm->mmu_lock); |
5bb064dc | 2369 | kvm_mmu_slot_remove_write_access(kvm, log->slot); |
7c8a83b7 | 2370 | spin_unlock(&kvm->mmu_lock); |
5bb064dc ZX |
2371 | memslot = &kvm->memslots[log->slot]; |
2372 | n = ALIGN(memslot->npages, BITS_PER_LONG) / 8; | |
2373 | memset(memslot->dirty_bitmap, 0, n); | |
2374 | } | |
2375 | r = 0; | |
2376 | out: | |
72dc67a6 | 2377 | up_write(&kvm->slots_lock); |
5bb064dc ZX |
2378 | return r; |
2379 | } | |
2380 | ||
1fe779f8 CO |
2381 | long kvm_arch_vm_ioctl(struct file *filp, |
2382 | unsigned int ioctl, unsigned long arg) | |
2383 | { | |
2384 | struct kvm *kvm = filp->private_data; | |
2385 | void __user *argp = (void __user *)arg; | |
367e1319 | 2386 | int r = -ENOTTY; |
f0d66275 DH |
2387 | /* |
2388 | * This union makes it completely explicit to gcc-3.x | |
2389 | * that these two variables' stack usage should be | |
2390 | * combined, not added together. | |
2391 | */ | |
2392 | union { | |
2393 | struct kvm_pit_state ps; | |
e9f42757 | 2394 | struct kvm_pit_state2 ps2; |
f0d66275 | 2395 | struct kvm_memory_alias alias; |
c5ff41ce | 2396 | struct kvm_pit_config pit_config; |
f0d66275 | 2397 | } u; |
1fe779f8 CO |
2398 | |
2399 | switch (ioctl) { | |
2400 | case KVM_SET_TSS_ADDR: | |
2401 | r = kvm_vm_ioctl_set_tss_addr(kvm, arg); | |
2402 | if (r < 0) | |
2403 | goto out; | |
2404 | break; | |
b927a3ce SY |
2405 | case KVM_SET_IDENTITY_MAP_ADDR: { |
2406 | u64 ident_addr; | |
2407 | ||
2408 | r = -EFAULT; | |
2409 | if (copy_from_user(&ident_addr, argp, sizeof ident_addr)) | |
2410 | goto out; | |
2411 | r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); | |
2412 | if (r < 0) | |
2413 | goto out; | |
2414 | break; | |
2415 | } | |
1fe779f8 CO |
2416 | case KVM_SET_MEMORY_REGION: { |
2417 | struct kvm_memory_region kvm_mem; | |
2418 | struct kvm_userspace_memory_region kvm_userspace_mem; | |
2419 | ||
2420 | r = -EFAULT; | |
2421 | if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem)) | |
2422 | goto out; | |
2423 | kvm_userspace_mem.slot = kvm_mem.slot; | |
2424 | kvm_userspace_mem.flags = kvm_mem.flags; | |
2425 | kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr; | |
2426 | kvm_userspace_mem.memory_size = kvm_mem.memory_size; | |
2427 | r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0); | |
2428 | if (r) | |
2429 | goto out; | |
2430 | break; | |
2431 | } | |
2432 | case KVM_SET_NR_MMU_PAGES: | |
2433 | r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); | |
2434 | if (r) | |
2435 | goto out; | |
2436 | break; | |
2437 | case KVM_GET_NR_MMU_PAGES: | |
2438 | r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); | |
2439 | break; | |
f0d66275 | 2440 | case KVM_SET_MEMORY_ALIAS: |
1fe779f8 | 2441 | r = -EFAULT; |
f0d66275 | 2442 | if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias))) |
1fe779f8 | 2443 | goto out; |
f0d66275 | 2444 | r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias); |
1fe779f8 CO |
2445 | if (r) |
2446 | goto out; | |
2447 | break; | |
3ddea128 MT |
2448 | case KVM_CREATE_IRQCHIP: { |
2449 | struct kvm_pic *vpic; | |
2450 | ||
2451 | mutex_lock(&kvm->lock); | |
2452 | r = -EEXIST; | |
2453 | if (kvm->arch.vpic) | |
2454 | goto create_irqchip_unlock; | |
1fe779f8 | 2455 | r = -ENOMEM; |
3ddea128 MT |
2456 | vpic = kvm_create_pic(kvm); |
2457 | if (vpic) { | |
1fe779f8 CO |
2458 | r = kvm_ioapic_init(kvm); |
2459 | if (r) { | |
3ddea128 MT |
2460 | kfree(vpic); |
2461 | goto create_irqchip_unlock; | |
1fe779f8 CO |
2462 | } |
2463 | } else | |
3ddea128 MT |
2464 | goto create_irqchip_unlock; |
2465 | smp_wmb(); | |
2466 | kvm->arch.vpic = vpic; | |
2467 | smp_wmb(); | |
399ec807 AK |
2468 | r = kvm_setup_default_irq_routing(kvm); |
2469 | if (r) { | |
3ddea128 | 2470 | mutex_lock(&kvm->irq_lock); |
399ec807 AK |
2471 | kfree(kvm->arch.vpic); |
2472 | kfree(kvm->arch.vioapic); | |
3ddea128 MT |
2473 | kvm->arch.vpic = NULL; |
2474 | kvm->arch.vioapic = NULL; | |
2475 | mutex_unlock(&kvm->irq_lock); | |
399ec807 | 2476 | } |
3ddea128 MT |
2477 | create_irqchip_unlock: |
2478 | mutex_unlock(&kvm->lock); | |
1fe779f8 | 2479 | break; |
3ddea128 | 2480 | } |
7837699f | 2481 | case KVM_CREATE_PIT: |
c5ff41ce JK |
2482 | u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; |
2483 | goto create_pit; | |
2484 | case KVM_CREATE_PIT2: | |
2485 | r = -EFAULT; | |
2486 | if (copy_from_user(&u.pit_config, argp, | |
2487 | sizeof(struct kvm_pit_config))) | |
2488 | goto out; | |
2489 | create_pit: | |
108b5669 | 2490 | down_write(&kvm->slots_lock); |
269e05e4 AK |
2491 | r = -EEXIST; |
2492 | if (kvm->arch.vpit) | |
2493 | goto create_pit_unlock; | |
7837699f | 2494 | r = -ENOMEM; |
c5ff41ce | 2495 | kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); |
7837699f SY |
2496 | if (kvm->arch.vpit) |
2497 | r = 0; | |
269e05e4 | 2498 | create_pit_unlock: |
108b5669 | 2499 | up_write(&kvm->slots_lock); |
7837699f | 2500 | break; |
4925663a | 2501 | case KVM_IRQ_LINE_STATUS: |
1fe779f8 CO |
2502 | case KVM_IRQ_LINE: { |
2503 | struct kvm_irq_level irq_event; | |
2504 | ||
2505 | r = -EFAULT; | |
2506 | if (copy_from_user(&irq_event, argp, sizeof irq_event)) | |
2507 | goto out; | |
2508 | if (irqchip_in_kernel(kvm)) { | |
4925663a | 2509 | __s32 status; |
4925663a GN |
2510 | status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, |
2511 | irq_event.irq, irq_event.level); | |
4925663a GN |
2512 | if (ioctl == KVM_IRQ_LINE_STATUS) { |
2513 | irq_event.status = status; | |
2514 | if (copy_to_user(argp, &irq_event, | |
2515 | sizeof irq_event)) | |
2516 | goto out; | |
2517 | } | |
1fe779f8 CO |
2518 | r = 0; |
2519 | } | |
2520 | break; | |
2521 | } | |
2522 | case KVM_GET_IRQCHIP: { | |
2523 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
f0d66275 | 2524 | struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL); |
1fe779f8 | 2525 | |
f0d66275 DH |
2526 | r = -ENOMEM; |
2527 | if (!chip) | |
1fe779f8 | 2528 | goto out; |
f0d66275 DH |
2529 | r = -EFAULT; |
2530 | if (copy_from_user(chip, argp, sizeof *chip)) | |
2531 | goto get_irqchip_out; | |
1fe779f8 CO |
2532 | r = -ENXIO; |
2533 | if (!irqchip_in_kernel(kvm)) | |
f0d66275 DH |
2534 | goto get_irqchip_out; |
2535 | r = kvm_vm_ioctl_get_irqchip(kvm, chip); | |
1fe779f8 | 2536 | if (r) |
f0d66275 | 2537 | goto get_irqchip_out; |
1fe779f8 | 2538 | r = -EFAULT; |
f0d66275 DH |
2539 | if (copy_to_user(argp, chip, sizeof *chip)) |
2540 | goto get_irqchip_out; | |
1fe779f8 | 2541 | r = 0; |
f0d66275 DH |
2542 | get_irqchip_out: |
2543 | kfree(chip); | |
2544 | if (r) | |
2545 | goto out; | |
1fe779f8 CO |
2546 | break; |
2547 | } | |
2548 | case KVM_SET_IRQCHIP: { | |
2549 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
f0d66275 | 2550 | struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL); |
1fe779f8 | 2551 | |
f0d66275 DH |
2552 | r = -ENOMEM; |
2553 | if (!chip) | |
1fe779f8 | 2554 | goto out; |
f0d66275 DH |
2555 | r = -EFAULT; |
2556 | if (copy_from_user(chip, argp, sizeof *chip)) | |
2557 | goto set_irqchip_out; | |
1fe779f8 CO |
2558 | r = -ENXIO; |
2559 | if (!irqchip_in_kernel(kvm)) | |
f0d66275 DH |
2560 | goto set_irqchip_out; |
2561 | r = kvm_vm_ioctl_set_irqchip(kvm, chip); | |
1fe779f8 | 2562 | if (r) |
f0d66275 | 2563 | goto set_irqchip_out; |
1fe779f8 | 2564 | r = 0; |
f0d66275 DH |
2565 | set_irqchip_out: |
2566 | kfree(chip); | |
2567 | if (r) | |
2568 | goto out; | |
1fe779f8 CO |
2569 | break; |
2570 | } | |
e0f63cb9 | 2571 | case KVM_GET_PIT: { |
e0f63cb9 | 2572 | r = -EFAULT; |
f0d66275 | 2573 | if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
2574 | goto out; |
2575 | r = -ENXIO; | |
2576 | if (!kvm->arch.vpit) | |
2577 | goto out; | |
f0d66275 | 2578 | r = kvm_vm_ioctl_get_pit(kvm, &u.ps); |
e0f63cb9 SY |
2579 | if (r) |
2580 | goto out; | |
2581 | r = -EFAULT; | |
f0d66275 | 2582 | if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
2583 | goto out; |
2584 | r = 0; | |
2585 | break; | |
2586 | } | |
2587 | case KVM_SET_PIT: { | |
e0f63cb9 | 2588 | r = -EFAULT; |
f0d66275 | 2589 | if (copy_from_user(&u.ps, argp, sizeof u.ps)) |
e0f63cb9 SY |
2590 | goto out; |
2591 | r = -ENXIO; | |
2592 | if (!kvm->arch.vpit) | |
2593 | goto out; | |
f0d66275 | 2594 | r = kvm_vm_ioctl_set_pit(kvm, &u.ps); |
e0f63cb9 SY |
2595 | if (r) |
2596 | goto out; | |
2597 | r = 0; | |
2598 | break; | |
2599 | } | |
e9f42757 BK |
2600 | case KVM_GET_PIT2: { |
2601 | r = -ENXIO; | |
2602 | if (!kvm->arch.vpit) | |
2603 | goto out; | |
2604 | r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); | |
2605 | if (r) | |
2606 | goto out; | |
2607 | r = -EFAULT; | |
2608 | if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) | |
2609 | goto out; | |
2610 | r = 0; | |
2611 | break; | |
2612 | } | |
2613 | case KVM_SET_PIT2: { | |
2614 | r = -EFAULT; | |
2615 | if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) | |
2616 | goto out; | |
2617 | r = -ENXIO; | |
2618 | if (!kvm->arch.vpit) | |
2619 | goto out; | |
2620 | r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); | |
2621 | if (r) | |
2622 | goto out; | |
2623 | r = 0; | |
2624 | break; | |
2625 | } | |
52d939a0 MT |
2626 | case KVM_REINJECT_CONTROL: { |
2627 | struct kvm_reinject_control control; | |
2628 | r = -EFAULT; | |
2629 | if (copy_from_user(&control, argp, sizeof(control))) | |
2630 | goto out; | |
2631 | r = kvm_vm_ioctl_reinject(kvm, &control); | |
2632 | if (r) | |
2633 | goto out; | |
2634 | r = 0; | |
2635 | break; | |
2636 | } | |
ffde22ac ES |
2637 | case KVM_XEN_HVM_CONFIG: { |
2638 | r = -EFAULT; | |
2639 | if (copy_from_user(&kvm->arch.xen_hvm_config, argp, | |
2640 | sizeof(struct kvm_xen_hvm_config))) | |
2641 | goto out; | |
2642 | r = -EINVAL; | |
2643 | if (kvm->arch.xen_hvm_config.flags) | |
2644 | goto out; | |
2645 | r = 0; | |
2646 | break; | |
2647 | } | |
afbcf7ab GC |
2648 | case KVM_SET_CLOCK: { |
2649 | struct timespec now; | |
2650 | struct kvm_clock_data user_ns; | |
2651 | u64 now_ns; | |
2652 | s64 delta; | |
2653 | ||
2654 | r = -EFAULT; | |
2655 | if (copy_from_user(&user_ns, argp, sizeof(user_ns))) | |
2656 | goto out; | |
2657 | ||
2658 | r = -EINVAL; | |
2659 | if (user_ns.flags) | |
2660 | goto out; | |
2661 | ||
2662 | r = 0; | |
2663 | ktime_get_ts(&now); | |
2664 | now_ns = timespec_to_ns(&now); | |
2665 | delta = user_ns.clock - now_ns; | |
2666 | kvm->arch.kvmclock_offset = delta; | |
2667 | break; | |
2668 | } | |
2669 | case KVM_GET_CLOCK: { | |
2670 | struct timespec now; | |
2671 | struct kvm_clock_data user_ns; | |
2672 | u64 now_ns; | |
2673 | ||
2674 | ktime_get_ts(&now); | |
2675 | now_ns = timespec_to_ns(&now); | |
2676 | user_ns.clock = kvm->arch.kvmclock_offset + now_ns; | |
2677 | user_ns.flags = 0; | |
2678 | ||
2679 | r = -EFAULT; | |
2680 | if (copy_to_user(argp, &user_ns, sizeof(user_ns))) | |
2681 | goto out; | |
2682 | r = 0; | |
2683 | break; | |
2684 | } | |
2685 | ||
1fe779f8 CO |
2686 | default: |
2687 | ; | |
2688 | } | |
2689 | out: | |
2690 | return r; | |
2691 | } | |
2692 | ||
a16b043c | 2693 | static void kvm_init_msr_list(void) |
043405e1 CO |
2694 | { |
2695 | u32 dummy[2]; | |
2696 | unsigned i, j; | |
2697 | ||
e3267cbb GC |
2698 | /* skip the first msrs in the list. KVM-specific */ |
2699 | for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) { | |
043405e1 CO |
2700 | if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0) |
2701 | continue; | |
2702 | if (j < i) | |
2703 | msrs_to_save[j] = msrs_to_save[i]; | |
2704 | j++; | |
2705 | } | |
2706 | num_msrs_to_save = j; | |
2707 | } | |
2708 | ||
bda9020e MT |
2709 | static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, |
2710 | const void *v) | |
bbd9b64e | 2711 | { |
bda9020e MT |
2712 | if (vcpu->arch.apic && |
2713 | !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v)) | |
2714 | return 0; | |
bbd9b64e | 2715 | |
bda9020e | 2716 | return kvm_io_bus_write(&vcpu->kvm->mmio_bus, addr, len, v); |
bbd9b64e CO |
2717 | } |
2718 | ||
bda9020e | 2719 | static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) |
bbd9b64e | 2720 | { |
bda9020e MT |
2721 | if (vcpu->arch.apic && |
2722 | !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v)) | |
2723 | return 0; | |
bbd9b64e | 2724 | |
bda9020e | 2725 | return kvm_io_bus_read(&vcpu->kvm->mmio_bus, addr, len, v); |
bbd9b64e CO |
2726 | } |
2727 | ||
cded19f3 HE |
2728 | static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes, |
2729 | struct kvm_vcpu *vcpu) | |
bbd9b64e CO |
2730 | { |
2731 | void *data = val; | |
10589a46 | 2732 | int r = X86EMUL_CONTINUE; |
bbd9b64e CO |
2733 | |
2734 | while (bytes) { | |
ad312c7c | 2735 | gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr); |
bbd9b64e | 2736 | unsigned offset = addr & (PAGE_SIZE-1); |
77c2002e | 2737 | unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); |
bbd9b64e CO |
2738 | int ret; |
2739 | ||
10589a46 MT |
2740 | if (gpa == UNMAPPED_GVA) { |
2741 | r = X86EMUL_PROPAGATE_FAULT; | |
2742 | goto out; | |
2743 | } | |
77c2002e | 2744 | ret = kvm_read_guest(vcpu->kvm, gpa, data, toread); |
10589a46 MT |
2745 | if (ret < 0) { |
2746 | r = X86EMUL_UNHANDLEABLE; | |
2747 | goto out; | |
2748 | } | |
bbd9b64e | 2749 | |
77c2002e IE |
2750 | bytes -= toread; |
2751 | data += toread; | |
2752 | addr += toread; | |
bbd9b64e | 2753 | } |
10589a46 | 2754 | out: |
10589a46 | 2755 | return r; |
bbd9b64e | 2756 | } |
77c2002e | 2757 | |
cded19f3 HE |
2758 | static int kvm_write_guest_virt(gva_t addr, void *val, unsigned int bytes, |
2759 | struct kvm_vcpu *vcpu) | |
77c2002e IE |
2760 | { |
2761 | void *data = val; | |
2762 | int r = X86EMUL_CONTINUE; | |
2763 | ||
2764 | while (bytes) { | |
2765 | gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr); | |
2766 | unsigned offset = addr & (PAGE_SIZE-1); | |
2767 | unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); | |
2768 | int ret; | |
2769 | ||
2770 | if (gpa == UNMAPPED_GVA) { | |
2771 | r = X86EMUL_PROPAGATE_FAULT; | |
2772 | goto out; | |
2773 | } | |
2774 | ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite); | |
2775 | if (ret < 0) { | |
2776 | r = X86EMUL_UNHANDLEABLE; | |
2777 | goto out; | |
2778 | } | |
2779 | ||
2780 | bytes -= towrite; | |
2781 | data += towrite; | |
2782 | addr += towrite; | |
2783 | } | |
2784 | out: | |
2785 | return r; | |
2786 | } | |
2787 | ||
bbd9b64e | 2788 | |
bbd9b64e CO |
2789 | static int emulator_read_emulated(unsigned long addr, |
2790 | void *val, | |
2791 | unsigned int bytes, | |
2792 | struct kvm_vcpu *vcpu) | |
2793 | { | |
bbd9b64e CO |
2794 | gpa_t gpa; |
2795 | ||
2796 | if (vcpu->mmio_read_completed) { | |
2797 | memcpy(val, vcpu->mmio_data, bytes); | |
aec51dc4 AK |
2798 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, |
2799 | vcpu->mmio_phys_addr, *(u64 *)val); | |
bbd9b64e CO |
2800 | vcpu->mmio_read_completed = 0; |
2801 | return X86EMUL_CONTINUE; | |
2802 | } | |
2803 | ||
ad312c7c | 2804 | gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr); |
bbd9b64e CO |
2805 | |
2806 | /* For APIC access vmexit */ | |
2807 | if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
2808 | goto mmio; | |
2809 | ||
77c2002e IE |
2810 | if (kvm_read_guest_virt(addr, val, bytes, vcpu) |
2811 | == X86EMUL_CONTINUE) | |
bbd9b64e CO |
2812 | return X86EMUL_CONTINUE; |
2813 | if (gpa == UNMAPPED_GVA) | |
2814 | return X86EMUL_PROPAGATE_FAULT; | |
2815 | ||
2816 | mmio: | |
2817 | /* | |
2818 | * Is this MMIO handled locally? | |
2819 | */ | |
aec51dc4 AK |
2820 | if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) { |
2821 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val); | |
bbd9b64e CO |
2822 | return X86EMUL_CONTINUE; |
2823 | } | |
aec51dc4 AK |
2824 | |
2825 | trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0); | |
bbd9b64e CO |
2826 | |
2827 | vcpu->mmio_needed = 1; | |
2828 | vcpu->mmio_phys_addr = gpa; | |
2829 | vcpu->mmio_size = bytes; | |
2830 | vcpu->mmio_is_write = 0; | |
2831 | ||
2832 | return X86EMUL_UNHANDLEABLE; | |
2833 | } | |
2834 | ||
3200f405 | 2835 | int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, |
9f811285 | 2836 | const void *val, int bytes) |
bbd9b64e CO |
2837 | { |
2838 | int ret; | |
2839 | ||
2840 | ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes); | |
9f811285 | 2841 | if (ret < 0) |
bbd9b64e | 2842 | return 0; |
ad218f85 | 2843 | kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1); |
bbd9b64e CO |
2844 | return 1; |
2845 | } | |
2846 | ||
2847 | static int emulator_write_emulated_onepage(unsigned long addr, | |
2848 | const void *val, | |
2849 | unsigned int bytes, | |
2850 | struct kvm_vcpu *vcpu) | |
2851 | { | |
10589a46 MT |
2852 | gpa_t gpa; |
2853 | ||
10589a46 | 2854 | gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr); |
bbd9b64e CO |
2855 | |
2856 | if (gpa == UNMAPPED_GVA) { | |
c3c91fee | 2857 | kvm_inject_page_fault(vcpu, addr, 2); |
bbd9b64e CO |
2858 | return X86EMUL_PROPAGATE_FAULT; |
2859 | } | |
2860 | ||
2861 | /* For APIC access vmexit */ | |
2862 | if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
2863 | goto mmio; | |
2864 | ||
2865 | if (emulator_write_phys(vcpu, gpa, val, bytes)) | |
2866 | return X86EMUL_CONTINUE; | |
2867 | ||
2868 | mmio: | |
aec51dc4 | 2869 | trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val); |
bbd9b64e CO |
2870 | /* |
2871 | * Is this MMIO handled locally? | |
2872 | */ | |
bda9020e | 2873 | if (!vcpu_mmio_write(vcpu, gpa, bytes, val)) |
bbd9b64e | 2874 | return X86EMUL_CONTINUE; |
bbd9b64e CO |
2875 | |
2876 | vcpu->mmio_needed = 1; | |
2877 | vcpu->mmio_phys_addr = gpa; | |
2878 | vcpu->mmio_size = bytes; | |
2879 | vcpu->mmio_is_write = 1; | |
2880 | memcpy(vcpu->mmio_data, val, bytes); | |
2881 | ||
2882 | return X86EMUL_CONTINUE; | |
2883 | } | |
2884 | ||
2885 | int emulator_write_emulated(unsigned long addr, | |
2886 | const void *val, | |
2887 | unsigned int bytes, | |
2888 | struct kvm_vcpu *vcpu) | |
2889 | { | |
2890 | /* Crossing a page boundary? */ | |
2891 | if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { | |
2892 | int rc, now; | |
2893 | ||
2894 | now = -addr & ~PAGE_MASK; | |
2895 | rc = emulator_write_emulated_onepage(addr, val, now, vcpu); | |
2896 | if (rc != X86EMUL_CONTINUE) | |
2897 | return rc; | |
2898 | addr += now; | |
2899 | val += now; | |
2900 | bytes -= now; | |
2901 | } | |
2902 | return emulator_write_emulated_onepage(addr, val, bytes, vcpu); | |
2903 | } | |
2904 | EXPORT_SYMBOL_GPL(emulator_write_emulated); | |
2905 | ||
2906 | static int emulator_cmpxchg_emulated(unsigned long addr, | |
2907 | const void *old, | |
2908 | const void *new, | |
2909 | unsigned int bytes, | |
2910 | struct kvm_vcpu *vcpu) | |
2911 | { | |
9f51e24e | 2912 | printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); |
2bacc55c MT |
2913 | #ifndef CONFIG_X86_64 |
2914 | /* guests cmpxchg8b have to be emulated atomically */ | |
2915 | if (bytes == 8) { | |
10589a46 | 2916 | gpa_t gpa; |
2bacc55c | 2917 | struct page *page; |
c0b49b0d | 2918 | char *kaddr; |
2bacc55c MT |
2919 | u64 val; |
2920 | ||
10589a46 MT |
2921 | gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr); |
2922 | ||
2bacc55c MT |
2923 | if (gpa == UNMAPPED_GVA || |
2924 | (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
2925 | goto emul_write; | |
2926 | ||
2927 | if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK)) | |
2928 | goto emul_write; | |
2929 | ||
2930 | val = *(u64 *)new; | |
72dc67a6 | 2931 | |
2bacc55c | 2932 | page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT); |
72dc67a6 | 2933 | |
c0b49b0d AM |
2934 | kaddr = kmap_atomic(page, KM_USER0); |
2935 | set_64bit((u64 *)(kaddr + offset_in_page(gpa)), val); | |
2936 | kunmap_atomic(kaddr, KM_USER0); | |
2bacc55c MT |
2937 | kvm_release_page_dirty(page); |
2938 | } | |
3200f405 | 2939 | emul_write: |
2bacc55c MT |
2940 | #endif |
2941 | ||
bbd9b64e CO |
2942 | return emulator_write_emulated(addr, new, bytes, vcpu); |
2943 | } | |
2944 | ||
2945 | static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) | |
2946 | { | |
2947 | return kvm_x86_ops->get_segment_base(vcpu, seg); | |
2948 | } | |
2949 | ||
2950 | int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address) | |
2951 | { | |
a7052897 | 2952 | kvm_mmu_invlpg(vcpu, address); |
bbd9b64e CO |
2953 | return X86EMUL_CONTINUE; |
2954 | } | |
2955 | ||
2956 | int emulate_clts(struct kvm_vcpu *vcpu) | |
2957 | { | |
ad312c7c | 2958 | kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 & ~X86_CR0_TS); |
bbd9b64e CO |
2959 | return X86EMUL_CONTINUE; |
2960 | } | |
2961 | ||
2962 | int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest) | |
2963 | { | |
2964 | struct kvm_vcpu *vcpu = ctxt->vcpu; | |
2965 | ||
2966 | switch (dr) { | |
2967 | case 0 ... 3: | |
2968 | *dest = kvm_x86_ops->get_dr(vcpu, dr); | |
2969 | return X86EMUL_CONTINUE; | |
2970 | default: | |
b8688d51 | 2971 | pr_unimpl(vcpu, "%s: unexpected dr %u\n", __func__, dr); |
bbd9b64e CO |
2972 | return X86EMUL_UNHANDLEABLE; |
2973 | } | |
2974 | } | |
2975 | ||
2976 | int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value) | |
2977 | { | |
2978 | unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U; | |
2979 | int exception; | |
2980 | ||
2981 | kvm_x86_ops->set_dr(ctxt->vcpu, dr, value & mask, &exception); | |
2982 | if (exception) { | |
2983 | /* FIXME: better handling */ | |
2984 | return X86EMUL_UNHANDLEABLE; | |
2985 | } | |
2986 | return X86EMUL_CONTINUE; | |
2987 | } | |
2988 | ||
2989 | void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context) | |
2990 | { | |
bbd9b64e | 2991 | u8 opcodes[4]; |
5fdbf976 | 2992 | unsigned long rip = kvm_rip_read(vcpu); |
bbd9b64e CO |
2993 | unsigned long rip_linear; |
2994 | ||
f76c710d | 2995 | if (!printk_ratelimit()) |
bbd9b64e CO |
2996 | return; |
2997 | ||
25be4608 GC |
2998 | rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS); |
2999 | ||
77c2002e | 3000 | kvm_read_guest_virt(rip_linear, (void *)opcodes, 4, vcpu); |
bbd9b64e CO |
3001 | |
3002 | printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n", | |
3003 | context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]); | |
bbd9b64e CO |
3004 | } |
3005 | EXPORT_SYMBOL_GPL(kvm_report_emulation_failure); | |
3006 | ||
14af3f3c | 3007 | static struct x86_emulate_ops emulate_ops = { |
77c2002e | 3008 | .read_std = kvm_read_guest_virt, |
bbd9b64e CO |
3009 | .read_emulated = emulator_read_emulated, |
3010 | .write_emulated = emulator_write_emulated, | |
3011 | .cmpxchg_emulated = emulator_cmpxchg_emulated, | |
3012 | }; | |
3013 | ||
5fdbf976 MT |
3014 | static void cache_all_regs(struct kvm_vcpu *vcpu) |
3015 | { | |
3016 | kvm_register_read(vcpu, VCPU_REGS_RAX); | |
3017 | kvm_register_read(vcpu, VCPU_REGS_RSP); | |
3018 | kvm_register_read(vcpu, VCPU_REGS_RIP); | |
3019 | vcpu->arch.regs_dirty = ~0; | |
3020 | } | |
3021 | ||
bbd9b64e | 3022 | int emulate_instruction(struct kvm_vcpu *vcpu, |
bbd9b64e CO |
3023 | unsigned long cr2, |
3024 | u16 error_code, | |
571008da | 3025 | int emulation_type) |
bbd9b64e | 3026 | { |
310b5d30 | 3027 | int r, shadow_mask; |
571008da | 3028 | struct decode_cache *c; |
851ba692 | 3029 | struct kvm_run *run = vcpu->run; |
bbd9b64e | 3030 | |
26eef70c | 3031 | kvm_clear_exception_queue(vcpu); |
ad312c7c | 3032 | vcpu->arch.mmio_fault_cr2 = cr2; |
5fdbf976 | 3033 | /* |
56e82318 | 3034 | * TODO: fix emulate.c to use guest_read/write_register |
5fdbf976 MT |
3035 | * instead of direct ->regs accesses, can save hundred cycles |
3036 | * on Intel for instructions that don't read/change RSP, for | |
3037 | * for example. | |
3038 | */ | |
3039 | cache_all_regs(vcpu); | |
bbd9b64e CO |
3040 | |
3041 | vcpu->mmio_is_write = 0; | |
ad312c7c | 3042 | vcpu->arch.pio.string = 0; |
bbd9b64e | 3043 | |
571008da | 3044 | if (!(emulation_type & EMULTYPE_NO_DECODE)) { |
bbd9b64e CO |
3045 | int cs_db, cs_l; |
3046 | kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); | |
3047 | ||
ad312c7c | 3048 | vcpu->arch.emulate_ctxt.vcpu = vcpu; |
91586a3b | 3049 | vcpu->arch.emulate_ctxt.eflags = kvm_get_rflags(vcpu); |
ad312c7c ZX |
3050 | vcpu->arch.emulate_ctxt.mode = |
3051 | (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM) | |
bbd9b64e CO |
3052 | ? X86EMUL_MODE_REAL : cs_l |
3053 | ? X86EMUL_MODE_PROT64 : cs_db | |
3054 | ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16; | |
3055 | ||
ad312c7c | 3056 | r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops); |
571008da | 3057 | |
0cb5762e AP |
3058 | /* Only allow emulation of specific instructions on #UD |
3059 | * (namely VMMCALL, sysenter, sysexit, syscall)*/ | |
571008da | 3060 | c = &vcpu->arch.emulate_ctxt.decode; |
0cb5762e AP |
3061 | if (emulation_type & EMULTYPE_TRAP_UD) { |
3062 | if (!c->twobyte) | |
3063 | return EMULATE_FAIL; | |
3064 | switch (c->b) { | |
3065 | case 0x01: /* VMMCALL */ | |
3066 | if (c->modrm_mod != 3 || c->modrm_rm != 1) | |
3067 | return EMULATE_FAIL; | |
3068 | break; | |
3069 | case 0x34: /* sysenter */ | |
3070 | case 0x35: /* sysexit */ | |
3071 | if (c->modrm_mod != 0 || c->modrm_rm != 0) | |
3072 | return EMULATE_FAIL; | |
3073 | break; | |
3074 | case 0x05: /* syscall */ | |
3075 | if (c->modrm_mod != 0 || c->modrm_rm != 0) | |
3076 | return EMULATE_FAIL; | |
3077 | break; | |
3078 | default: | |
3079 | return EMULATE_FAIL; | |
3080 | } | |
3081 | ||
3082 | if (!(c->modrm_reg == 0 || c->modrm_reg == 3)) | |
3083 | return EMULATE_FAIL; | |
3084 | } | |
571008da | 3085 | |
f2b5756b | 3086 | ++vcpu->stat.insn_emulation; |
bbd9b64e | 3087 | if (r) { |
f2b5756b | 3088 | ++vcpu->stat.insn_emulation_fail; |
bbd9b64e CO |
3089 | if (kvm_mmu_unprotect_page_virt(vcpu, cr2)) |
3090 | return EMULATE_DONE; | |
3091 | return EMULATE_FAIL; | |
3092 | } | |
3093 | } | |
3094 | ||
ba8afb6b GN |
3095 | if (emulation_type & EMULTYPE_SKIP) { |
3096 | kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip); | |
3097 | return EMULATE_DONE; | |
3098 | } | |
3099 | ||
ad312c7c | 3100 | r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops); |
310b5d30 GC |
3101 | shadow_mask = vcpu->arch.emulate_ctxt.interruptibility; |
3102 | ||
3103 | if (r == 0) | |
3104 | kvm_x86_ops->set_interrupt_shadow(vcpu, shadow_mask); | |
bbd9b64e | 3105 | |
ad312c7c | 3106 | if (vcpu->arch.pio.string) |
bbd9b64e CO |
3107 | return EMULATE_DO_MMIO; |
3108 | ||
3109 | if ((r || vcpu->mmio_is_write) && run) { | |
3110 | run->exit_reason = KVM_EXIT_MMIO; | |
3111 | run->mmio.phys_addr = vcpu->mmio_phys_addr; | |
3112 | memcpy(run->mmio.data, vcpu->mmio_data, 8); | |
3113 | run->mmio.len = vcpu->mmio_size; | |
3114 | run->mmio.is_write = vcpu->mmio_is_write; | |
3115 | } | |
3116 | ||
3117 | if (r) { | |
3118 | if (kvm_mmu_unprotect_page_virt(vcpu, cr2)) | |
3119 | return EMULATE_DONE; | |
3120 | if (!vcpu->mmio_needed) { | |
3121 | kvm_report_emulation_failure(vcpu, "mmio"); | |
3122 | return EMULATE_FAIL; | |
3123 | } | |
3124 | return EMULATE_DO_MMIO; | |
3125 | } | |
3126 | ||
91586a3b | 3127 | kvm_set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags); |
bbd9b64e CO |
3128 | |
3129 | if (vcpu->mmio_is_write) { | |
3130 | vcpu->mmio_needed = 0; | |
3131 | return EMULATE_DO_MMIO; | |
3132 | } | |
3133 | ||
3134 | return EMULATE_DONE; | |
3135 | } | |
3136 | EXPORT_SYMBOL_GPL(emulate_instruction); | |
3137 | ||
de7d789a CO |
3138 | static int pio_copy_data(struct kvm_vcpu *vcpu) |
3139 | { | |
ad312c7c | 3140 | void *p = vcpu->arch.pio_data; |
0f346074 | 3141 | gva_t q = vcpu->arch.pio.guest_gva; |
de7d789a | 3142 | unsigned bytes; |
0f346074 | 3143 | int ret; |
de7d789a | 3144 | |
ad312c7c ZX |
3145 | bytes = vcpu->arch.pio.size * vcpu->arch.pio.cur_count; |
3146 | if (vcpu->arch.pio.in) | |
0f346074 | 3147 | ret = kvm_write_guest_virt(q, p, bytes, vcpu); |
de7d789a | 3148 | else |
0f346074 IE |
3149 | ret = kvm_read_guest_virt(q, p, bytes, vcpu); |
3150 | return ret; | |
de7d789a CO |
3151 | } |
3152 | ||
3153 | int complete_pio(struct kvm_vcpu *vcpu) | |
3154 | { | |
ad312c7c | 3155 | struct kvm_pio_request *io = &vcpu->arch.pio; |
de7d789a CO |
3156 | long delta; |
3157 | int r; | |
5fdbf976 | 3158 | unsigned long val; |
de7d789a CO |
3159 | |
3160 | if (!io->string) { | |
5fdbf976 MT |
3161 | if (io->in) { |
3162 | val = kvm_register_read(vcpu, VCPU_REGS_RAX); | |
3163 | memcpy(&val, vcpu->arch.pio_data, io->size); | |
3164 | kvm_register_write(vcpu, VCPU_REGS_RAX, val); | |
3165 | } | |
de7d789a CO |
3166 | } else { |
3167 | if (io->in) { | |
3168 | r = pio_copy_data(vcpu); | |
5fdbf976 | 3169 | if (r) |
de7d789a | 3170 | return r; |
de7d789a CO |
3171 | } |
3172 | ||
3173 | delta = 1; | |
3174 | if (io->rep) { | |
3175 | delta *= io->cur_count; | |
3176 | /* | |
3177 | * The size of the register should really depend on | |
3178 | * current address size. | |
3179 | */ | |
5fdbf976 MT |
3180 | val = kvm_register_read(vcpu, VCPU_REGS_RCX); |
3181 | val -= delta; | |
3182 | kvm_register_write(vcpu, VCPU_REGS_RCX, val); | |
de7d789a CO |
3183 | } |
3184 | if (io->down) | |
3185 | delta = -delta; | |
3186 | delta *= io->size; | |
5fdbf976 MT |
3187 | if (io->in) { |
3188 | val = kvm_register_read(vcpu, VCPU_REGS_RDI); | |
3189 | val += delta; | |
3190 | kvm_register_write(vcpu, VCPU_REGS_RDI, val); | |
3191 | } else { | |
3192 | val = kvm_register_read(vcpu, VCPU_REGS_RSI); | |
3193 | val += delta; | |
3194 | kvm_register_write(vcpu, VCPU_REGS_RSI, val); | |
3195 | } | |
de7d789a CO |
3196 | } |
3197 | ||
de7d789a CO |
3198 | io->count -= io->cur_count; |
3199 | io->cur_count = 0; | |
3200 | ||
3201 | return 0; | |
3202 | } | |
3203 | ||
bda9020e | 3204 | static int kernel_pio(struct kvm_vcpu *vcpu, void *pd) |
de7d789a CO |
3205 | { |
3206 | /* TODO: String I/O for in kernel device */ | |
bda9020e | 3207 | int r; |
de7d789a | 3208 | |
ad312c7c | 3209 | if (vcpu->arch.pio.in) |
bda9020e MT |
3210 | r = kvm_io_bus_read(&vcpu->kvm->pio_bus, vcpu->arch.pio.port, |
3211 | vcpu->arch.pio.size, pd); | |
de7d789a | 3212 | else |
bda9020e MT |
3213 | r = kvm_io_bus_write(&vcpu->kvm->pio_bus, vcpu->arch.pio.port, |
3214 | vcpu->arch.pio.size, pd); | |
3215 | return r; | |
de7d789a CO |
3216 | } |
3217 | ||
bda9020e | 3218 | static int pio_string_write(struct kvm_vcpu *vcpu) |
de7d789a | 3219 | { |
ad312c7c ZX |
3220 | struct kvm_pio_request *io = &vcpu->arch.pio; |
3221 | void *pd = vcpu->arch.pio_data; | |
bda9020e | 3222 | int i, r = 0; |
de7d789a | 3223 | |
de7d789a | 3224 | for (i = 0; i < io->cur_count; i++) { |
bda9020e MT |
3225 | if (kvm_io_bus_write(&vcpu->kvm->pio_bus, |
3226 | io->port, io->size, pd)) { | |
3227 | r = -EOPNOTSUPP; | |
3228 | break; | |
3229 | } | |
de7d789a CO |
3230 | pd += io->size; |
3231 | } | |
bda9020e | 3232 | return r; |
de7d789a CO |
3233 | } |
3234 | ||
851ba692 | 3235 | int kvm_emulate_pio(struct kvm_vcpu *vcpu, int in, int size, unsigned port) |
de7d789a | 3236 | { |
5fdbf976 | 3237 | unsigned long val; |
de7d789a CO |
3238 | |
3239 | vcpu->run->exit_reason = KVM_EXIT_IO; | |
3240 | vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; | |
ad312c7c | 3241 | vcpu->run->io.size = vcpu->arch.pio.size = size; |
de7d789a | 3242 | vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; |
ad312c7c ZX |
3243 | vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = 1; |
3244 | vcpu->run->io.port = vcpu->arch.pio.port = port; | |
3245 | vcpu->arch.pio.in = in; | |
3246 | vcpu->arch.pio.string = 0; | |
3247 | vcpu->arch.pio.down = 0; | |
ad312c7c | 3248 | vcpu->arch.pio.rep = 0; |
de7d789a | 3249 | |
229456fc MT |
3250 | trace_kvm_pio(vcpu->run->io.direction == KVM_EXIT_IO_OUT, port, |
3251 | size, 1); | |
2714d1d3 | 3252 | |
5fdbf976 MT |
3253 | val = kvm_register_read(vcpu, VCPU_REGS_RAX); |
3254 | memcpy(vcpu->arch.pio_data, &val, 4); | |
de7d789a | 3255 | |
bda9020e | 3256 | if (!kernel_pio(vcpu, vcpu->arch.pio_data)) { |
de7d789a CO |
3257 | complete_pio(vcpu); |
3258 | return 1; | |
3259 | } | |
3260 | return 0; | |
3261 | } | |
3262 | EXPORT_SYMBOL_GPL(kvm_emulate_pio); | |
3263 | ||
851ba692 | 3264 | int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, int in, |
de7d789a CO |
3265 | int size, unsigned long count, int down, |
3266 | gva_t address, int rep, unsigned port) | |
3267 | { | |
3268 | unsigned now, in_page; | |
0f346074 | 3269 | int ret = 0; |
de7d789a CO |
3270 | |
3271 | vcpu->run->exit_reason = KVM_EXIT_IO; | |
3272 | vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; | |
ad312c7c | 3273 | vcpu->run->io.size = vcpu->arch.pio.size = size; |
de7d789a | 3274 | vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; |
ad312c7c ZX |
3275 | vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = count; |
3276 | vcpu->run->io.port = vcpu->arch.pio.port = port; | |
3277 | vcpu->arch.pio.in = in; | |
3278 | vcpu->arch.pio.string = 1; | |
3279 | vcpu->arch.pio.down = down; | |
ad312c7c | 3280 | vcpu->arch.pio.rep = rep; |
de7d789a | 3281 | |
229456fc MT |
3282 | trace_kvm_pio(vcpu->run->io.direction == KVM_EXIT_IO_OUT, port, |
3283 | size, count); | |
2714d1d3 | 3284 | |
de7d789a CO |
3285 | if (!count) { |
3286 | kvm_x86_ops->skip_emulated_instruction(vcpu); | |
3287 | return 1; | |
3288 | } | |
3289 | ||
3290 | if (!down) | |
3291 | in_page = PAGE_SIZE - offset_in_page(address); | |
3292 | else | |
3293 | in_page = offset_in_page(address) + size; | |
3294 | now = min(count, (unsigned long)in_page / size); | |
0f346074 | 3295 | if (!now) |
de7d789a | 3296 | now = 1; |
de7d789a CO |
3297 | if (down) { |
3298 | /* | |
3299 | * String I/O in reverse. Yuck. Kill the guest, fix later. | |
3300 | */ | |
3301 | pr_unimpl(vcpu, "guest string pio down\n"); | |
c1a5d4f9 | 3302 | kvm_inject_gp(vcpu, 0); |
de7d789a CO |
3303 | return 1; |
3304 | } | |
3305 | vcpu->run->io.count = now; | |
ad312c7c | 3306 | vcpu->arch.pio.cur_count = now; |
de7d789a | 3307 | |
ad312c7c | 3308 | if (vcpu->arch.pio.cur_count == vcpu->arch.pio.count) |
de7d789a CO |
3309 | kvm_x86_ops->skip_emulated_instruction(vcpu); |
3310 | ||
0f346074 | 3311 | vcpu->arch.pio.guest_gva = address; |
de7d789a | 3312 | |
ad312c7c | 3313 | if (!vcpu->arch.pio.in) { |
de7d789a CO |
3314 | /* string PIO write */ |
3315 | ret = pio_copy_data(vcpu); | |
0f346074 IE |
3316 | if (ret == X86EMUL_PROPAGATE_FAULT) { |
3317 | kvm_inject_gp(vcpu, 0); | |
3318 | return 1; | |
3319 | } | |
bda9020e | 3320 | if (ret == 0 && !pio_string_write(vcpu)) { |
de7d789a | 3321 | complete_pio(vcpu); |
ad312c7c | 3322 | if (vcpu->arch.pio.count == 0) |
de7d789a CO |
3323 | ret = 1; |
3324 | } | |
bda9020e MT |
3325 | } |
3326 | /* no string PIO read support yet */ | |
de7d789a CO |
3327 | |
3328 | return ret; | |
3329 | } | |
3330 | EXPORT_SYMBOL_GPL(kvm_emulate_pio_string); | |
3331 | ||
c8076604 GH |
3332 | static void bounce_off(void *info) |
3333 | { | |
3334 | /* nothing */ | |
3335 | } | |
3336 | ||
c8076604 GH |
3337 | static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, |
3338 | void *data) | |
3339 | { | |
3340 | struct cpufreq_freqs *freq = data; | |
3341 | struct kvm *kvm; | |
3342 | struct kvm_vcpu *vcpu; | |
3343 | int i, send_ipi = 0; | |
3344 | ||
c8076604 GH |
3345 | if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) |
3346 | return 0; | |
3347 | if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) | |
3348 | return 0; | |
0cca7907 | 3349 | per_cpu(cpu_tsc_khz, freq->cpu) = freq->new; |
c8076604 GH |
3350 | |
3351 | spin_lock(&kvm_lock); | |
3352 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
988a2cae | 3353 | kvm_for_each_vcpu(i, vcpu, kvm) { |
c8076604 GH |
3354 | if (vcpu->cpu != freq->cpu) |
3355 | continue; | |
3356 | if (!kvm_request_guest_time_update(vcpu)) | |
3357 | continue; | |
3358 | if (vcpu->cpu != smp_processor_id()) | |
3359 | send_ipi++; | |
3360 | } | |
3361 | } | |
3362 | spin_unlock(&kvm_lock); | |
3363 | ||
3364 | if (freq->old < freq->new && send_ipi) { | |
3365 | /* | |
3366 | * We upscale the frequency. Must make the guest | |
3367 | * doesn't see old kvmclock values while running with | |
3368 | * the new frequency, otherwise we risk the guest sees | |
3369 | * time go backwards. | |
3370 | * | |
3371 | * In case we update the frequency for another cpu | |
3372 | * (which might be in guest context) send an interrupt | |
3373 | * to kick the cpu out of guest context. Next time | |
3374 | * guest context is entered kvmclock will be updated, | |
3375 | * so the guest will not see stale values. | |
3376 | */ | |
3377 | smp_call_function_single(freq->cpu, bounce_off, NULL, 1); | |
3378 | } | |
3379 | return 0; | |
3380 | } | |
3381 | ||
3382 | static struct notifier_block kvmclock_cpufreq_notifier_block = { | |
3383 | .notifier_call = kvmclock_cpufreq_notifier | |
3384 | }; | |
3385 | ||
b820cc0c ZA |
3386 | static void kvm_timer_init(void) |
3387 | { | |
3388 | int cpu; | |
3389 | ||
b820cc0c | 3390 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { |
b820cc0c ZA |
3391 | cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, |
3392 | CPUFREQ_TRANSITION_NOTIFIER); | |
6b7d7e76 ZA |
3393 | for_each_online_cpu(cpu) { |
3394 | unsigned long khz = cpufreq_get(cpu); | |
3395 | if (!khz) | |
3396 | khz = tsc_khz; | |
3397 | per_cpu(cpu_tsc_khz, cpu) = khz; | |
3398 | } | |
0cca7907 ZA |
3399 | } else { |
3400 | for_each_possible_cpu(cpu) | |
3401 | per_cpu(cpu_tsc_khz, cpu) = tsc_khz; | |
b820cc0c ZA |
3402 | } |
3403 | } | |
3404 | ||
f8c16bba | 3405 | int kvm_arch_init(void *opaque) |
043405e1 | 3406 | { |
b820cc0c | 3407 | int r; |
f8c16bba ZX |
3408 | struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque; |
3409 | ||
f8c16bba ZX |
3410 | if (kvm_x86_ops) { |
3411 | printk(KERN_ERR "kvm: already loaded the other module\n"); | |
56c6d28a ZX |
3412 | r = -EEXIST; |
3413 | goto out; | |
f8c16bba ZX |
3414 | } |
3415 | ||
3416 | if (!ops->cpu_has_kvm_support()) { | |
3417 | printk(KERN_ERR "kvm: no hardware support\n"); | |
56c6d28a ZX |
3418 | r = -EOPNOTSUPP; |
3419 | goto out; | |
f8c16bba ZX |
3420 | } |
3421 | if (ops->disabled_by_bios()) { | |
3422 | printk(KERN_ERR "kvm: disabled by bios\n"); | |
56c6d28a ZX |
3423 | r = -EOPNOTSUPP; |
3424 | goto out; | |
f8c16bba ZX |
3425 | } |
3426 | ||
97db56ce AK |
3427 | r = kvm_mmu_module_init(); |
3428 | if (r) | |
3429 | goto out; | |
3430 | ||
3431 | kvm_init_msr_list(); | |
3432 | ||
f8c16bba | 3433 | kvm_x86_ops = ops; |
56c6d28a | 3434 | kvm_mmu_set_nonpresent_ptes(0ull, 0ull); |
7b52345e SY |
3435 | kvm_mmu_set_base_ptes(PT_PRESENT_MASK); |
3436 | kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK, | |
4b12f0de | 3437 | PT_DIRTY_MASK, PT64_NX_MASK, 0); |
c8076604 | 3438 | |
b820cc0c | 3439 | kvm_timer_init(); |
c8076604 | 3440 | |
f8c16bba | 3441 | return 0; |
56c6d28a ZX |
3442 | |
3443 | out: | |
56c6d28a | 3444 | return r; |
043405e1 | 3445 | } |
8776e519 | 3446 | |
f8c16bba ZX |
3447 | void kvm_arch_exit(void) |
3448 | { | |
888d256e JK |
3449 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) |
3450 | cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, | |
3451 | CPUFREQ_TRANSITION_NOTIFIER); | |
f8c16bba | 3452 | kvm_x86_ops = NULL; |
56c6d28a ZX |
3453 | kvm_mmu_module_exit(); |
3454 | } | |
f8c16bba | 3455 | |
8776e519 HB |
3456 | int kvm_emulate_halt(struct kvm_vcpu *vcpu) |
3457 | { | |
3458 | ++vcpu->stat.halt_exits; | |
3459 | if (irqchip_in_kernel(vcpu->kvm)) { | |
a4535290 | 3460 | vcpu->arch.mp_state = KVM_MP_STATE_HALTED; |
8776e519 HB |
3461 | return 1; |
3462 | } else { | |
3463 | vcpu->run->exit_reason = KVM_EXIT_HLT; | |
3464 | return 0; | |
3465 | } | |
3466 | } | |
3467 | EXPORT_SYMBOL_GPL(kvm_emulate_halt); | |
3468 | ||
2f333bcb MT |
3469 | static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0, |
3470 | unsigned long a1) | |
3471 | { | |
3472 | if (is_long_mode(vcpu)) | |
3473 | return a0; | |
3474 | else | |
3475 | return a0 | ((gpa_t)a1 << 32); | |
3476 | } | |
3477 | ||
8776e519 HB |
3478 | int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) |
3479 | { | |
3480 | unsigned long nr, a0, a1, a2, a3, ret; | |
2f333bcb | 3481 | int r = 1; |
8776e519 | 3482 | |
5fdbf976 MT |
3483 | nr = kvm_register_read(vcpu, VCPU_REGS_RAX); |
3484 | a0 = kvm_register_read(vcpu, VCPU_REGS_RBX); | |
3485 | a1 = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
3486 | a2 = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
3487 | a3 = kvm_register_read(vcpu, VCPU_REGS_RSI); | |
8776e519 | 3488 | |
229456fc | 3489 | trace_kvm_hypercall(nr, a0, a1, a2, a3); |
2714d1d3 | 3490 | |
8776e519 HB |
3491 | if (!is_long_mode(vcpu)) { |
3492 | nr &= 0xFFFFFFFF; | |
3493 | a0 &= 0xFFFFFFFF; | |
3494 | a1 &= 0xFFFFFFFF; | |
3495 | a2 &= 0xFFFFFFFF; | |
3496 | a3 &= 0xFFFFFFFF; | |
3497 | } | |
3498 | ||
07708c4a JK |
3499 | if (kvm_x86_ops->get_cpl(vcpu) != 0) { |
3500 | ret = -KVM_EPERM; | |
3501 | goto out; | |
3502 | } | |
3503 | ||
8776e519 | 3504 | switch (nr) { |
b93463aa AK |
3505 | case KVM_HC_VAPIC_POLL_IRQ: |
3506 | ret = 0; | |
3507 | break; | |
2f333bcb MT |
3508 | case KVM_HC_MMU_OP: |
3509 | r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret); | |
3510 | break; | |
8776e519 HB |
3511 | default: |
3512 | ret = -KVM_ENOSYS; | |
3513 | break; | |
3514 | } | |
07708c4a | 3515 | out: |
5fdbf976 | 3516 | kvm_register_write(vcpu, VCPU_REGS_RAX, ret); |
f11c3a8d | 3517 | ++vcpu->stat.hypercalls; |
2f333bcb | 3518 | return r; |
8776e519 HB |
3519 | } |
3520 | EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); | |
3521 | ||
3522 | int kvm_fix_hypercall(struct kvm_vcpu *vcpu) | |
3523 | { | |
3524 | char instruction[3]; | |
3525 | int ret = 0; | |
5fdbf976 | 3526 | unsigned long rip = kvm_rip_read(vcpu); |
8776e519 | 3527 | |
8776e519 HB |
3528 | |
3529 | /* | |
3530 | * Blow out the MMU to ensure that no other VCPU has an active mapping | |
3531 | * to ensure that the updated hypercall appears atomically across all | |
3532 | * VCPUs. | |
3533 | */ | |
3534 | kvm_mmu_zap_all(vcpu->kvm); | |
3535 | ||
8776e519 | 3536 | kvm_x86_ops->patch_hypercall(vcpu, instruction); |
5fdbf976 | 3537 | if (emulator_write_emulated(rip, instruction, 3, vcpu) |
8776e519 HB |
3538 | != X86EMUL_CONTINUE) |
3539 | ret = -EFAULT; | |
3540 | ||
8776e519 HB |
3541 | return ret; |
3542 | } | |
3543 | ||
3544 | static u64 mk_cr_64(u64 curr_cr, u32 new_val) | |
3545 | { | |
3546 | return (curr_cr & ~((1ULL << 32) - 1)) | new_val; | |
3547 | } | |
3548 | ||
3549 | void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base) | |
3550 | { | |
3551 | struct descriptor_table dt = { limit, base }; | |
3552 | ||
3553 | kvm_x86_ops->set_gdt(vcpu, &dt); | |
3554 | } | |
3555 | ||
3556 | void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base) | |
3557 | { | |
3558 | struct descriptor_table dt = { limit, base }; | |
3559 | ||
3560 | kvm_x86_ops->set_idt(vcpu, &dt); | |
3561 | } | |
3562 | ||
3563 | void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw, | |
3564 | unsigned long *rflags) | |
3565 | { | |
2d3ad1f4 | 3566 | kvm_lmsw(vcpu, msw); |
91586a3b | 3567 | *rflags = kvm_get_rflags(vcpu); |
8776e519 HB |
3568 | } |
3569 | ||
3570 | unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr) | |
3571 | { | |
54e445ca JR |
3572 | unsigned long value; |
3573 | ||
8776e519 HB |
3574 | kvm_x86_ops->decache_cr4_guest_bits(vcpu); |
3575 | switch (cr) { | |
3576 | case 0: | |
54e445ca JR |
3577 | value = vcpu->arch.cr0; |
3578 | break; | |
8776e519 | 3579 | case 2: |
54e445ca JR |
3580 | value = vcpu->arch.cr2; |
3581 | break; | |
8776e519 | 3582 | case 3: |
54e445ca JR |
3583 | value = vcpu->arch.cr3; |
3584 | break; | |
8776e519 | 3585 | case 4: |
54e445ca JR |
3586 | value = vcpu->arch.cr4; |
3587 | break; | |
152ff9be | 3588 | case 8: |
54e445ca JR |
3589 | value = kvm_get_cr8(vcpu); |
3590 | break; | |
8776e519 | 3591 | default: |
b8688d51 | 3592 | vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr); |
8776e519 HB |
3593 | return 0; |
3594 | } | |
54e445ca JR |
3595 | |
3596 | return value; | |
8776e519 HB |
3597 | } |
3598 | ||
3599 | void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long val, | |
3600 | unsigned long *rflags) | |
3601 | { | |
3602 | switch (cr) { | |
3603 | case 0: | |
2d3ad1f4 | 3604 | kvm_set_cr0(vcpu, mk_cr_64(vcpu->arch.cr0, val)); |
91586a3b | 3605 | *rflags = kvm_get_rflags(vcpu); |
8776e519 HB |
3606 | break; |
3607 | case 2: | |
ad312c7c | 3608 | vcpu->arch.cr2 = val; |
8776e519 HB |
3609 | break; |
3610 | case 3: | |
2d3ad1f4 | 3611 | kvm_set_cr3(vcpu, val); |
8776e519 HB |
3612 | break; |
3613 | case 4: | |
2d3ad1f4 | 3614 | kvm_set_cr4(vcpu, mk_cr_64(vcpu->arch.cr4, val)); |
8776e519 | 3615 | break; |
152ff9be | 3616 | case 8: |
2d3ad1f4 | 3617 | kvm_set_cr8(vcpu, val & 0xfUL); |
152ff9be | 3618 | break; |
8776e519 | 3619 | default: |
b8688d51 | 3620 | vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr); |
8776e519 HB |
3621 | } |
3622 | } | |
3623 | ||
07716717 DK |
3624 | static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i) |
3625 | { | |
ad312c7c ZX |
3626 | struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i]; |
3627 | int j, nent = vcpu->arch.cpuid_nent; | |
07716717 DK |
3628 | |
3629 | e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT; | |
3630 | /* when no next entry is found, the current entry[i] is reselected */ | |
0fdf8e59 | 3631 | for (j = i + 1; ; j = (j + 1) % nent) { |
ad312c7c | 3632 | struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j]; |
07716717 DK |
3633 | if (ej->function == e->function) { |
3634 | ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT; | |
3635 | return j; | |
3636 | } | |
3637 | } | |
3638 | return 0; /* silence gcc, even though control never reaches here */ | |
3639 | } | |
3640 | ||
3641 | /* find an entry with matching function, matching index (if needed), and that | |
3642 | * should be read next (if it's stateful) */ | |
3643 | static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e, | |
3644 | u32 function, u32 index) | |
3645 | { | |
3646 | if (e->function != function) | |
3647 | return 0; | |
3648 | if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index) | |
3649 | return 0; | |
3650 | if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) && | |
19355475 | 3651 | !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT)) |
07716717 DK |
3652 | return 0; |
3653 | return 1; | |
3654 | } | |
3655 | ||
d8017474 AG |
3656 | struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu, |
3657 | u32 function, u32 index) | |
8776e519 HB |
3658 | { |
3659 | int i; | |
d8017474 | 3660 | struct kvm_cpuid_entry2 *best = NULL; |
8776e519 | 3661 | |
ad312c7c | 3662 | for (i = 0; i < vcpu->arch.cpuid_nent; ++i) { |
d8017474 AG |
3663 | struct kvm_cpuid_entry2 *e; |
3664 | ||
ad312c7c | 3665 | e = &vcpu->arch.cpuid_entries[i]; |
07716717 DK |
3666 | if (is_matching_cpuid_entry(e, function, index)) { |
3667 | if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) | |
3668 | move_to_next_stateful_cpuid_entry(vcpu, i); | |
8776e519 HB |
3669 | best = e; |
3670 | break; | |
3671 | } | |
3672 | /* | |
3673 | * Both basic or both extended? | |
3674 | */ | |
3675 | if (((e->function ^ function) & 0x80000000) == 0) | |
3676 | if (!best || e->function > best->function) | |
3677 | best = e; | |
3678 | } | |
d8017474 AG |
3679 | return best; |
3680 | } | |
3681 | ||
82725b20 DE |
3682 | int cpuid_maxphyaddr(struct kvm_vcpu *vcpu) |
3683 | { | |
3684 | struct kvm_cpuid_entry2 *best; | |
3685 | ||
3686 | best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0); | |
3687 | if (best) | |
3688 | return best->eax & 0xff; | |
3689 | return 36; | |
3690 | } | |
3691 | ||
d8017474 AG |
3692 | void kvm_emulate_cpuid(struct kvm_vcpu *vcpu) |
3693 | { | |
3694 | u32 function, index; | |
3695 | struct kvm_cpuid_entry2 *best; | |
3696 | ||
3697 | function = kvm_register_read(vcpu, VCPU_REGS_RAX); | |
3698 | index = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
3699 | kvm_register_write(vcpu, VCPU_REGS_RAX, 0); | |
3700 | kvm_register_write(vcpu, VCPU_REGS_RBX, 0); | |
3701 | kvm_register_write(vcpu, VCPU_REGS_RCX, 0); | |
3702 | kvm_register_write(vcpu, VCPU_REGS_RDX, 0); | |
3703 | best = kvm_find_cpuid_entry(vcpu, function, index); | |
8776e519 | 3704 | if (best) { |
5fdbf976 MT |
3705 | kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax); |
3706 | kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx); | |
3707 | kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx); | |
3708 | kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx); | |
8776e519 | 3709 | } |
8776e519 | 3710 | kvm_x86_ops->skip_emulated_instruction(vcpu); |
229456fc MT |
3711 | trace_kvm_cpuid(function, |
3712 | kvm_register_read(vcpu, VCPU_REGS_RAX), | |
3713 | kvm_register_read(vcpu, VCPU_REGS_RBX), | |
3714 | kvm_register_read(vcpu, VCPU_REGS_RCX), | |
3715 | kvm_register_read(vcpu, VCPU_REGS_RDX)); | |
8776e519 HB |
3716 | } |
3717 | EXPORT_SYMBOL_GPL(kvm_emulate_cpuid); | |
d0752060 | 3718 | |
b6c7a5dc HB |
3719 | /* |
3720 | * Check if userspace requested an interrupt window, and that the | |
3721 | * interrupt window is open. | |
3722 | * | |
3723 | * No need to exit to userspace if we already have an interrupt queued. | |
3724 | */ | |
851ba692 | 3725 | static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) |
b6c7a5dc | 3726 | { |
8061823a | 3727 | return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) && |
851ba692 | 3728 | vcpu->run->request_interrupt_window && |
5df56646 | 3729 | kvm_arch_interrupt_allowed(vcpu)); |
b6c7a5dc HB |
3730 | } |
3731 | ||
851ba692 | 3732 | static void post_kvm_run_save(struct kvm_vcpu *vcpu) |
b6c7a5dc | 3733 | { |
851ba692 AK |
3734 | struct kvm_run *kvm_run = vcpu->run; |
3735 | ||
91586a3b | 3736 | kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0; |
2d3ad1f4 | 3737 | kvm_run->cr8 = kvm_get_cr8(vcpu); |
b6c7a5dc | 3738 | kvm_run->apic_base = kvm_get_apic_base(vcpu); |
4531220b | 3739 | if (irqchip_in_kernel(vcpu->kvm)) |
b6c7a5dc | 3740 | kvm_run->ready_for_interrupt_injection = 1; |
4531220b | 3741 | else |
b6c7a5dc | 3742 | kvm_run->ready_for_interrupt_injection = |
fa9726b0 GN |
3743 | kvm_arch_interrupt_allowed(vcpu) && |
3744 | !kvm_cpu_has_interrupt(vcpu) && | |
3745 | !kvm_event_needs_reinjection(vcpu); | |
b6c7a5dc HB |
3746 | } |
3747 | ||
b93463aa AK |
3748 | static void vapic_enter(struct kvm_vcpu *vcpu) |
3749 | { | |
3750 | struct kvm_lapic *apic = vcpu->arch.apic; | |
3751 | struct page *page; | |
3752 | ||
3753 | if (!apic || !apic->vapic_addr) | |
3754 | return; | |
3755 | ||
3756 | page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT); | |
72dc67a6 IE |
3757 | |
3758 | vcpu->arch.apic->vapic_page = page; | |
b93463aa AK |
3759 | } |
3760 | ||
3761 | static void vapic_exit(struct kvm_vcpu *vcpu) | |
3762 | { | |
3763 | struct kvm_lapic *apic = vcpu->arch.apic; | |
3764 | ||
3765 | if (!apic || !apic->vapic_addr) | |
3766 | return; | |
3767 | ||
f8b78fa3 | 3768 | down_read(&vcpu->kvm->slots_lock); |
b93463aa AK |
3769 | kvm_release_page_dirty(apic->vapic_page); |
3770 | mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT); | |
f8b78fa3 | 3771 | up_read(&vcpu->kvm->slots_lock); |
b93463aa AK |
3772 | } |
3773 | ||
95ba8273 GN |
3774 | static void update_cr8_intercept(struct kvm_vcpu *vcpu) |
3775 | { | |
3776 | int max_irr, tpr; | |
3777 | ||
3778 | if (!kvm_x86_ops->update_cr8_intercept) | |
3779 | return; | |
3780 | ||
88c808fd AK |
3781 | if (!vcpu->arch.apic) |
3782 | return; | |
3783 | ||
8db3baa2 GN |
3784 | if (!vcpu->arch.apic->vapic_addr) |
3785 | max_irr = kvm_lapic_find_highest_irr(vcpu); | |
3786 | else | |
3787 | max_irr = -1; | |
95ba8273 GN |
3788 | |
3789 | if (max_irr != -1) | |
3790 | max_irr >>= 4; | |
3791 | ||
3792 | tpr = kvm_lapic_get_cr8(vcpu); | |
3793 | ||
3794 | kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr); | |
3795 | } | |
3796 | ||
851ba692 | 3797 | static void inject_pending_event(struct kvm_vcpu *vcpu) |
95ba8273 GN |
3798 | { |
3799 | /* try to reinject previous events if any */ | |
b59bb7bd GN |
3800 | if (vcpu->arch.exception.pending) { |
3801 | kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr, | |
3802 | vcpu->arch.exception.has_error_code, | |
3803 | vcpu->arch.exception.error_code); | |
3804 | return; | |
3805 | } | |
3806 | ||
95ba8273 GN |
3807 | if (vcpu->arch.nmi_injected) { |
3808 | kvm_x86_ops->set_nmi(vcpu); | |
3809 | return; | |
3810 | } | |
3811 | ||
3812 | if (vcpu->arch.interrupt.pending) { | |
66fd3f7f | 3813 | kvm_x86_ops->set_irq(vcpu); |
95ba8273 GN |
3814 | return; |
3815 | } | |
3816 | ||
3817 | /* try to inject new event if pending */ | |
3818 | if (vcpu->arch.nmi_pending) { | |
3819 | if (kvm_x86_ops->nmi_allowed(vcpu)) { | |
3820 | vcpu->arch.nmi_pending = false; | |
3821 | vcpu->arch.nmi_injected = true; | |
3822 | kvm_x86_ops->set_nmi(vcpu); | |
3823 | } | |
3824 | } else if (kvm_cpu_has_interrupt(vcpu)) { | |
3825 | if (kvm_x86_ops->interrupt_allowed(vcpu)) { | |
66fd3f7f GN |
3826 | kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), |
3827 | false); | |
3828 | kvm_x86_ops->set_irq(vcpu); | |
95ba8273 GN |
3829 | } |
3830 | } | |
3831 | } | |
3832 | ||
851ba692 | 3833 | static int vcpu_enter_guest(struct kvm_vcpu *vcpu) |
b6c7a5dc HB |
3834 | { |
3835 | int r; | |
6a8b1d13 | 3836 | bool req_int_win = !irqchip_in_kernel(vcpu->kvm) && |
851ba692 | 3837 | vcpu->run->request_interrupt_window; |
b6c7a5dc | 3838 | |
2e53d63a MT |
3839 | if (vcpu->requests) |
3840 | if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests)) | |
3841 | kvm_mmu_unload(vcpu); | |
3842 | ||
b6c7a5dc HB |
3843 | r = kvm_mmu_reload(vcpu); |
3844 | if (unlikely(r)) | |
3845 | goto out; | |
3846 | ||
2f52d58c AK |
3847 | if (vcpu->requests) { |
3848 | if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests)) | |
2f599714 | 3849 | __kvm_migrate_timers(vcpu); |
c8076604 GH |
3850 | if (test_and_clear_bit(KVM_REQ_KVMCLOCK_UPDATE, &vcpu->requests)) |
3851 | kvm_write_guest_time(vcpu); | |
4731d4c7 MT |
3852 | if (test_and_clear_bit(KVM_REQ_MMU_SYNC, &vcpu->requests)) |
3853 | kvm_mmu_sync_roots(vcpu); | |
d4acf7e7 MT |
3854 | if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests)) |
3855 | kvm_x86_ops->tlb_flush(vcpu); | |
b93463aa AK |
3856 | if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS, |
3857 | &vcpu->requests)) { | |
851ba692 | 3858 | vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; |
b93463aa AK |
3859 | r = 0; |
3860 | goto out; | |
3861 | } | |
71c4dfaf | 3862 | if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) { |
851ba692 | 3863 | vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; |
71c4dfaf JR |
3864 | r = 0; |
3865 | goto out; | |
3866 | } | |
2f52d58c | 3867 | } |
b93463aa | 3868 | |
b6c7a5dc HB |
3869 | preempt_disable(); |
3870 | ||
3871 | kvm_x86_ops->prepare_guest_switch(vcpu); | |
3872 | kvm_load_guest_fpu(vcpu); | |
3873 | ||
3874 | local_irq_disable(); | |
3875 | ||
32f88400 MT |
3876 | clear_bit(KVM_REQ_KICK, &vcpu->requests); |
3877 | smp_mb__after_clear_bit(); | |
3878 | ||
d7690175 | 3879 | if (vcpu->requests || need_resched() || signal_pending(current)) { |
c7f0f24b | 3880 | set_bit(KVM_REQ_KICK, &vcpu->requests); |
6c142801 AK |
3881 | local_irq_enable(); |
3882 | preempt_enable(); | |
3883 | r = 1; | |
3884 | goto out; | |
3885 | } | |
3886 | ||
851ba692 | 3887 | inject_pending_event(vcpu); |
b6c7a5dc | 3888 | |
6a8b1d13 GN |
3889 | /* enable NMI/IRQ window open exits if needed */ |
3890 | if (vcpu->arch.nmi_pending) | |
3891 | kvm_x86_ops->enable_nmi_window(vcpu); | |
3892 | else if (kvm_cpu_has_interrupt(vcpu) || req_int_win) | |
3893 | kvm_x86_ops->enable_irq_window(vcpu); | |
3894 | ||
95ba8273 | 3895 | if (kvm_lapic_enabled(vcpu)) { |
8db3baa2 GN |
3896 | update_cr8_intercept(vcpu); |
3897 | kvm_lapic_sync_to_vapic(vcpu); | |
95ba8273 | 3898 | } |
b93463aa | 3899 | |
3200f405 MT |
3900 | up_read(&vcpu->kvm->slots_lock); |
3901 | ||
b6c7a5dc HB |
3902 | kvm_guest_enter(); |
3903 | ||
42dbaa5a | 3904 | if (unlikely(vcpu->arch.switch_db_regs)) { |
42dbaa5a JK |
3905 | set_debugreg(0, 7); |
3906 | set_debugreg(vcpu->arch.eff_db[0], 0); | |
3907 | set_debugreg(vcpu->arch.eff_db[1], 1); | |
3908 | set_debugreg(vcpu->arch.eff_db[2], 2); | |
3909 | set_debugreg(vcpu->arch.eff_db[3], 3); | |
3910 | } | |
b6c7a5dc | 3911 | |
229456fc | 3912 | trace_kvm_entry(vcpu->vcpu_id); |
851ba692 | 3913 | kvm_x86_ops->run(vcpu); |
b6c7a5dc | 3914 | |
3d53c27d AK |
3915 | if (unlikely(vcpu->arch.switch_db_regs || test_thread_flag(TIF_DEBUG))) { |
3916 | set_debugreg(current->thread.debugreg0, 0); | |
3917 | set_debugreg(current->thread.debugreg1, 1); | |
3918 | set_debugreg(current->thread.debugreg2, 2); | |
3919 | set_debugreg(current->thread.debugreg3, 3); | |
3920 | set_debugreg(current->thread.debugreg6, 6); | |
3921 | set_debugreg(current->thread.debugreg7, 7); | |
42dbaa5a | 3922 | } |
42dbaa5a | 3923 | |
32f88400 | 3924 | set_bit(KVM_REQ_KICK, &vcpu->requests); |
b6c7a5dc HB |
3925 | local_irq_enable(); |
3926 | ||
3927 | ++vcpu->stat.exits; | |
3928 | ||
3929 | /* | |
3930 | * We must have an instruction between local_irq_enable() and | |
3931 | * kvm_guest_exit(), so the timer interrupt isn't delayed by | |
3932 | * the interrupt shadow. The stat.exits increment will do nicely. | |
3933 | * But we need to prevent reordering, hence this barrier(): | |
3934 | */ | |
3935 | barrier(); | |
3936 | ||
3937 | kvm_guest_exit(); | |
3938 | ||
3939 | preempt_enable(); | |
3940 | ||
3200f405 MT |
3941 | down_read(&vcpu->kvm->slots_lock); |
3942 | ||
b6c7a5dc HB |
3943 | /* |
3944 | * Profile KVM exit RIPs: | |
3945 | */ | |
3946 | if (unlikely(prof_on == KVM_PROFILING)) { | |
5fdbf976 MT |
3947 | unsigned long rip = kvm_rip_read(vcpu); |
3948 | profile_hit(KVM_PROFILING, (void *)rip); | |
b6c7a5dc HB |
3949 | } |
3950 | ||
298101da | 3951 | |
b93463aa AK |
3952 | kvm_lapic_sync_from_vapic(vcpu); |
3953 | ||
851ba692 | 3954 | r = kvm_x86_ops->handle_exit(vcpu); |
d7690175 MT |
3955 | out: |
3956 | return r; | |
3957 | } | |
b6c7a5dc | 3958 | |
09cec754 | 3959 | |
851ba692 | 3960 | static int __vcpu_run(struct kvm_vcpu *vcpu) |
d7690175 MT |
3961 | { |
3962 | int r; | |
3963 | ||
3964 | if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) { | |
1b10bf31 JK |
3965 | pr_debug("vcpu %d received sipi with vector # %x\n", |
3966 | vcpu->vcpu_id, vcpu->arch.sipi_vector); | |
d7690175 | 3967 | kvm_lapic_reset(vcpu); |
5f179287 | 3968 | r = kvm_arch_vcpu_reset(vcpu); |
d7690175 MT |
3969 | if (r) |
3970 | return r; | |
3971 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; | |
b6c7a5dc HB |
3972 | } |
3973 | ||
d7690175 MT |
3974 | down_read(&vcpu->kvm->slots_lock); |
3975 | vapic_enter(vcpu); | |
3976 | ||
3977 | r = 1; | |
3978 | while (r > 0) { | |
af2152f5 | 3979 | if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE) |
851ba692 | 3980 | r = vcpu_enter_guest(vcpu); |
d7690175 MT |
3981 | else { |
3982 | up_read(&vcpu->kvm->slots_lock); | |
3983 | kvm_vcpu_block(vcpu); | |
3984 | down_read(&vcpu->kvm->slots_lock); | |
3985 | if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests)) | |
09cec754 GN |
3986 | { |
3987 | switch(vcpu->arch.mp_state) { | |
3988 | case KVM_MP_STATE_HALTED: | |
d7690175 | 3989 | vcpu->arch.mp_state = |
09cec754 GN |
3990 | KVM_MP_STATE_RUNNABLE; |
3991 | case KVM_MP_STATE_RUNNABLE: | |
3992 | break; | |
3993 | case KVM_MP_STATE_SIPI_RECEIVED: | |
3994 | default: | |
3995 | r = -EINTR; | |
3996 | break; | |
3997 | } | |
3998 | } | |
d7690175 MT |
3999 | } |
4000 | ||
09cec754 GN |
4001 | if (r <= 0) |
4002 | break; | |
4003 | ||
4004 | clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests); | |
4005 | if (kvm_cpu_has_pending_timer(vcpu)) | |
4006 | kvm_inject_pending_timer_irqs(vcpu); | |
4007 | ||
851ba692 | 4008 | if (dm_request_for_irq_injection(vcpu)) { |
09cec754 | 4009 | r = -EINTR; |
851ba692 | 4010 | vcpu->run->exit_reason = KVM_EXIT_INTR; |
09cec754 GN |
4011 | ++vcpu->stat.request_irq_exits; |
4012 | } | |
4013 | if (signal_pending(current)) { | |
4014 | r = -EINTR; | |
851ba692 | 4015 | vcpu->run->exit_reason = KVM_EXIT_INTR; |
09cec754 GN |
4016 | ++vcpu->stat.signal_exits; |
4017 | } | |
4018 | if (need_resched()) { | |
4019 | up_read(&vcpu->kvm->slots_lock); | |
4020 | kvm_resched(vcpu); | |
4021 | down_read(&vcpu->kvm->slots_lock); | |
d7690175 | 4022 | } |
b6c7a5dc HB |
4023 | } |
4024 | ||
d7690175 | 4025 | up_read(&vcpu->kvm->slots_lock); |
851ba692 | 4026 | post_kvm_run_save(vcpu); |
b6c7a5dc | 4027 | |
b93463aa AK |
4028 | vapic_exit(vcpu); |
4029 | ||
b6c7a5dc HB |
4030 | return r; |
4031 | } | |
4032 | ||
4033 | int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
4034 | { | |
4035 | int r; | |
4036 | sigset_t sigsaved; | |
4037 | ||
4038 | vcpu_load(vcpu); | |
4039 | ||
ac9f6dc0 AK |
4040 | if (vcpu->sigset_active) |
4041 | sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved); | |
4042 | ||
a4535290 | 4043 | if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { |
b6c7a5dc | 4044 | kvm_vcpu_block(vcpu); |
d7690175 | 4045 | clear_bit(KVM_REQ_UNHALT, &vcpu->requests); |
ac9f6dc0 AK |
4046 | r = -EAGAIN; |
4047 | goto out; | |
b6c7a5dc HB |
4048 | } |
4049 | ||
b6c7a5dc HB |
4050 | /* re-sync apic's tpr */ |
4051 | if (!irqchip_in_kernel(vcpu->kvm)) | |
2d3ad1f4 | 4052 | kvm_set_cr8(vcpu, kvm_run->cr8); |
b6c7a5dc | 4053 | |
ad312c7c | 4054 | if (vcpu->arch.pio.cur_count) { |
b6c7a5dc HB |
4055 | r = complete_pio(vcpu); |
4056 | if (r) | |
4057 | goto out; | |
4058 | } | |
b6c7a5dc HB |
4059 | if (vcpu->mmio_needed) { |
4060 | memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8); | |
4061 | vcpu->mmio_read_completed = 1; | |
4062 | vcpu->mmio_needed = 0; | |
3200f405 MT |
4063 | |
4064 | down_read(&vcpu->kvm->slots_lock); | |
851ba692 | 4065 | r = emulate_instruction(vcpu, vcpu->arch.mmio_fault_cr2, 0, |
571008da | 4066 | EMULTYPE_NO_DECODE); |
3200f405 | 4067 | up_read(&vcpu->kvm->slots_lock); |
b6c7a5dc HB |
4068 | if (r == EMULATE_DO_MMIO) { |
4069 | /* | |
4070 | * Read-modify-write. Back to userspace. | |
4071 | */ | |
4072 | r = 0; | |
4073 | goto out; | |
4074 | } | |
4075 | } | |
5fdbf976 MT |
4076 | if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL) |
4077 | kvm_register_write(vcpu, VCPU_REGS_RAX, | |
4078 | kvm_run->hypercall.ret); | |
b6c7a5dc | 4079 | |
851ba692 | 4080 | r = __vcpu_run(vcpu); |
b6c7a5dc HB |
4081 | |
4082 | out: | |
4083 | if (vcpu->sigset_active) | |
4084 | sigprocmask(SIG_SETMASK, &sigsaved, NULL); | |
4085 | ||
4086 | vcpu_put(vcpu); | |
4087 | return r; | |
4088 | } | |
4089 | ||
4090 | int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) | |
4091 | { | |
4092 | vcpu_load(vcpu); | |
4093 | ||
5fdbf976 MT |
4094 | regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX); |
4095 | regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX); | |
4096 | regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
4097 | regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
4098 | regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI); | |
4099 | regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI); | |
4100 | regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP); | |
4101 | regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP); | |
b6c7a5dc | 4102 | #ifdef CONFIG_X86_64 |
5fdbf976 MT |
4103 | regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8); |
4104 | regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9); | |
4105 | regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10); | |
4106 | regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11); | |
4107 | regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12); | |
4108 | regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13); | |
4109 | regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14); | |
4110 | regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15); | |
b6c7a5dc HB |
4111 | #endif |
4112 | ||
5fdbf976 | 4113 | regs->rip = kvm_rip_read(vcpu); |
91586a3b | 4114 | regs->rflags = kvm_get_rflags(vcpu); |
b6c7a5dc HB |
4115 | |
4116 | vcpu_put(vcpu); | |
4117 | ||
4118 | return 0; | |
4119 | } | |
4120 | ||
4121 | int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) | |
4122 | { | |
4123 | vcpu_load(vcpu); | |
4124 | ||
5fdbf976 MT |
4125 | kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax); |
4126 | kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx); | |
4127 | kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx); | |
4128 | kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx); | |
4129 | kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi); | |
4130 | kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi); | |
4131 | kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp); | |
4132 | kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp); | |
b6c7a5dc | 4133 | #ifdef CONFIG_X86_64 |
5fdbf976 MT |
4134 | kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8); |
4135 | kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9); | |
4136 | kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10); | |
4137 | kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11); | |
4138 | kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12); | |
4139 | kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13); | |
4140 | kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14); | |
4141 | kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15); | |
b6c7a5dc HB |
4142 | #endif |
4143 | ||
5fdbf976 | 4144 | kvm_rip_write(vcpu, regs->rip); |
91586a3b | 4145 | kvm_set_rflags(vcpu, regs->rflags); |
b6c7a5dc | 4146 | |
b4f14abd JK |
4147 | vcpu->arch.exception.pending = false; |
4148 | ||
b6c7a5dc HB |
4149 | vcpu_put(vcpu); |
4150 | ||
4151 | return 0; | |
4152 | } | |
4153 | ||
3e6e0aab GT |
4154 | void kvm_get_segment(struct kvm_vcpu *vcpu, |
4155 | struct kvm_segment *var, int seg) | |
b6c7a5dc | 4156 | { |
14af3f3c | 4157 | kvm_x86_ops->get_segment(vcpu, var, seg); |
b6c7a5dc HB |
4158 | } |
4159 | ||
4160 | void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) | |
4161 | { | |
4162 | struct kvm_segment cs; | |
4163 | ||
3e6e0aab | 4164 | kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); |
b6c7a5dc HB |
4165 | *db = cs.db; |
4166 | *l = cs.l; | |
4167 | } | |
4168 | EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); | |
4169 | ||
4170 | int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, | |
4171 | struct kvm_sregs *sregs) | |
4172 | { | |
4173 | struct descriptor_table dt; | |
b6c7a5dc HB |
4174 | |
4175 | vcpu_load(vcpu); | |
4176 | ||
3e6e0aab GT |
4177 | kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
4178 | kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
4179 | kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
4180 | kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
4181 | kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
4182 | kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 4183 | |
3e6e0aab GT |
4184 | kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
4185 | kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc HB |
4186 | |
4187 | kvm_x86_ops->get_idt(vcpu, &dt); | |
4188 | sregs->idt.limit = dt.limit; | |
4189 | sregs->idt.base = dt.base; | |
4190 | kvm_x86_ops->get_gdt(vcpu, &dt); | |
4191 | sregs->gdt.limit = dt.limit; | |
4192 | sregs->gdt.base = dt.base; | |
4193 | ||
4194 | kvm_x86_ops->decache_cr4_guest_bits(vcpu); | |
ad312c7c ZX |
4195 | sregs->cr0 = vcpu->arch.cr0; |
4196 | sregs->cr2 = vcpu->arch.cr2; | |
4197 | sregs->cr3 = vcpu->arch.cr3; | |
4198 | sregs->cr4 = vcpu->arch.cr4; | |
2d3ad1f4 | 4199 | sregs->cr8 = kvm_get_cr8(vcpu); |
ad312c7c | 4200 | sregs->efer = vcpu->arch.shadow_efer; |
b6c7a5dc HB |
4201 | sregs->apic_base = kvm_get_apic_base(vcpu); |
4202 | ||
923c61bb | 4203 | memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap); |
b6c7a5dc | 4204 | |
36752c9b | 4205 | if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft) |
14d0bc1f GN |
4206 | set_bit(vcpu->arch.interrupt.nr, |
4207 | (unsigned long *)sregs->interrupt_bitmap); | |
16d7a191 | 4208 | |
b6c7a5dc HB |
4209 | vcpu_put(vcpu); |
4210 | ||
4211 | return 0; | |
4212 | } | |
4213 | ||
62d9f0db MT |
4214 | int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, |
4215 | struct kvm_mp_state *mp_state) | |
4216 | { | |
4217 | vcpu_load(vcpu); | |
4218 | mp_state->mp_state = vcpu->arch.mp_state; | |
4219 | vcpu_put(vcpu); | |
4220 | return 0; | |
4221 | } | |
4222 | ||
4223 | int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, | |
4224 | struct kvm_mp_state *mp_state) | |
4225 | { | |
4226 | vcpu_load(vcpu); | |
4227 | vcpu->arch.mp_state = mp_state->mp_state; | |
4228 | vcpu_put(vcpu); | |
4229 | return 0; | |
4230 | } | |
4231 | ||
3e6e0aab | 4232 | static void kvm_set_segment(struct kvm_vcpu *vcpu, |
b6c7a5dc HB |
4233 | struct kvm_segment *var, int seg) |
4234 | { | |
14af3f3c | 4235 | kvm_x86_ops->set_segment(vcpu, var, seg); |
b6c7a5dc HB |
4236 | } |
4237 | ||
37817f29 IE |
4238 | static void seg_desct_to_kvm_desct(struct desc_struct *seg_desc, u16 selector, |
4239 | struct kvm_segment *kvm_desct) | |
4240 | { | |
46a359e7 AM |
4241 | kvm_desct->base = get_desc_base(seg_desc); |
4242 | kvm_desct->limit = get_desc_limit(seg_desc); | |
c93cd3a5 MT |
4243 | if (seg_desc->g) { |
4244 | kvm_desct->limit <<= 12; | |
4245 | kvm_desct->limit |= 0xfff; | |
4246 | } | |
37817f29 IE |
4247 | kvm_desct->selector = selector; |
4248 | kvm_desct->type = seg_desc->type; | |
4249 | kvm_desct->present = seg_desc->p; | |
4250 | kvm_desct->dpl = seg_desc->dpl; | |
4251 | kvm_desct->db = seg_desc->d; | |
4252 | kvm_desct->s = seg_desc->s; | |
4253 | kvm_desct->l = seg_desc->l; | |
4254 | kvm_desct->g = seg_desc->g; | |
4255 | kvm_desct->avl = seg_desc->avl; | |
4256 | if (!selector) | |
4257 | kvm_desct->unusable = 1; | |
4258 | else | |
4259 | kvm_desct->unusable = 0; | |
4260 | kvm_desct->padding = 0; | |
4261 | } | |
4262 | ||
b8222ad2 AS |
4263 | static void get_segment_descriptor_dtable(struct kvm_vcpu *vcpu, |
4264 | u16 selector, | |
4265 | struct descriptor_table *dtable) | |
37817f29 IE |
4266 | { |
4267 | if (selector & 1 << 2) { | |
4268 | struct kvm_segment kvm_seg; | |
4269 | ||
3e6e0aab | 4270 | kvm_get_segment(vcpu, &kvm_seg, VCPU_SREG_LDTR); |
37817f29 IE |
4271 | |
4272 | if (kvm_seg.unusable) | |
4273 | dtable->limit = 0; | |
4274 | else | |
4275 | dtable->limit = kvm_seg.limit; | |
4276 | dtable->base = kvm_seg.base; | |
4277 | } | |
4278 | else | |
4279 | kvm_x86_ops->get_gdt(vcpu, dtable); | |
4280 | } | |
4281 | ||
4282 | /* allowed just for 8 bytes segments */ | |
4283 | static int load_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, | |
4284 | struct desc_struct *seg_desc) | |
4285 | { | |
4286 | struct descriptor_table dtable; | |
4287 | u16 index = selector >> 3; | |
4288 | ||
b8222ad2 | 4289 | get_segment_descriptor_dtable(vcpu, selector, &dtable); |
37817f29 IE |
4290 | |
4291 | if (dtable.limit < index * 8 + 7) { | |
4292 | kvm_queue_exception_e(vcpu, GP_VECTOR, selector & 0xfffc); | |
4293 | return 1; | |
4294 | } | |
d9048d32 | 4295 | return kvm_read_guest_virt(dtable.base + index*8, seg_desc, sizeof(*seg_desc), vcpu); |
37817f29 IE |
4296 | } |
4297 | ||
4298 | /* allowed just for 8 bytes segments */ | |
4299 | static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, | |
4300 | struct desc_struct *seg_desc) | |
4301 | { | |
4302 | struct descriptor_table dtable; | |
4303 | u16 index = selector >> 3; | |
4304 | ||
b8222ad2 | 4305 | get_segment_descriptor_dtable(vcpu, selector, &dtable); |
37817f29 IE |
4306 | |
4307 | if (dtable.limit < index * 8 + 7) | |
4308 | return 1; | |
d9048d32 | 4309 | return kvm_write_guest_virt(dtable.base + index*8, seg_desc, sizeof(*seg_desc), vcpu); |
37817f29 IE |
4310 | } |
4311 | ||
abb39119 | 4312 | static gpa_t get_tss_base_addr(struct kvm_vcpu *vcpu, |
37817f29 IE |
4313 | struct desc_struct *seg_desc) |
4314 | { | |
46a359e7 | 4315 | u32 base_addr = get_desc_base(seg_desc); |
37817f29 | 4316 | |
98899aa0 | 4317 | return vcpu->arch.mmu.gva_to_gpa(vcpu, base_addr); |
37817f29 IE |
4318 | } |
4319 | ||
37817f29 IE |
4320 | static u16 get_segment_selector(struct kvm_vcpu *vcpu, int seg) |
4321 | { | |
4322 | struct kvm_segment kvm_seg; | |
4323 | ||
3e6e0aab | 4324 | kvm_get_segment(vcpu, &kvm_seg, seg); |
37817f29 IE |
4325 | return kvm_seg.selector; |
4326 | } | |
4327 | ||
4328 | static int load_segment_descriptor_to_kvm_desct(struct kvm_vcpu *vcpu, | |
4329 | u16 selector, | |
4330 | struct kvm_segment *kvm_seg) | |
4331 | { | |
4332 | struct desc_struct seg_desc; | |
4333 | ||
4334 | if (load_guest_segment_descriptor(vcpu, selector, &seg_desc)) | |
4335 | return 1; | |
4336 | seg_desct_to_kvm_desct(&seg_desc, selector, kvm_seg); | |
4337 | return 0; | |
4338 | } | |
4339 | ||
2259e3a7 | 4340 | static int kvm_load_realmode_segment(struct kvm_vcpu *vcpu, u16 selector, int seg) |
f4bbd9aa AK |
4341 | { |
4342 | struct kvm_segment segvar = { | |
4343 | .base = selector << 4, | |
4344 | .limit = 0xffff, | |
4345 | .selector = selector, | |
4346 | .type = 3, | |
4347 | .present = 1, | |
4348 | .dpl = 3, | |
4349 | .db = 0, | |
4350 | .s = 1, | |
4351 | .l = 0, | |
4352 | .g = 0, | |
4353 | .avl = 0, | |
4354 | .unusable = 0, | |
4355 | }; | |
4356 | kvm_x86_ops->set_segment(vcpu, &segvar, seg); | |
4357 | return 0; | |
4358 | } | |
4359 | ||
c0c7c04b AL |
4360 | static int is_vm86_segment(struct kvm_vcpu *vcpu, int seg) |
4361 | { | |
4362 | return (seg != VCPU_SREG_LDTR) && | |
4363 | (seg != VCPU_SREG_TR) && | |
91586a3b | 4364 | (kvm_get_rflags(vcpu) & X86_EFLAGS_VM); |
c0c7c04b AL |
4365 | } |
4366 | ||
3e6e0aab GT |
4367 | int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, |
4368 | int type_bits, int seg) | |
37817f29 IE |
4369 | { |
4370 | struct kvm_segment kvm_seg; | |
4371 | ||
c0c7c04b | 4372 | if (is_vm86_segment(vcpu, seg) || !(vcpu->arch.cr0 & X86_CR0_PE)) |
f4bbd9aa | 4373 | return kvm_load_realmode_segment(vcpu, selector, seg); |
37817f29 IE |
4374 | if (load_segment_descriptor_to_kvm_desct(vcpu, selector, &kvm_seg)) |
4375 | return 1; | |
4376 | kvm_seg.type |= type_bits; | |
4377 | ||
4378 | if (seg != VCPU_SREG_SS && seg != VCPU_SREG_CS && | |
4379 | seg != VCPU_SREG_LDTR) | |
4380 | if (!kvm_seg.s) | |
4381 | kvm_seg.unusable = 1; | |
4382 | ||
3e6e0aab | 4383 | kvm_set_segment(vcpu, &kvm_seg, seg); |
37817f29 IE |
4384 | return 0; |
4385 | } | |
4386 | ||
4387 | static void save_state_to_tss32(struct kvm_vcpu *vcpu, | |
4388 | struct tss_segment_32 *tss) | |
4389 | { | |
4390 | tss->cr3 = vcpu->arch.cr3; | |
5fdbf976 | 4391 | tss->eip = kvm_rip_read(vcpu); |
91586a3b | 4392 | tss->eflags = kvm_get_rflags(vcpu); |
5fdbf976 MT |
4393 | tss->eax = kvm_register_read(vcpu, VCPU_REGS_RAX); |
4394 | tss->ecx = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
4395 | tss->edx = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
4396 | tss->ebx = kvm_register_read(vcpu, VCPU_REGS_RBX); | |
4397 | tss->esp = kvm_register_read(vcpu, VCPU_REGS_RSP); | |
4398 | tss->ebp = kvm_register_read(vcpu, VCPU_REGS_RBP); | |
4399 | tss->esi = kvm_register_read(vcpu, VCPU_REGS_RSI); | |
4400 | tss->edi = kvm_register_read(vcpu, VCPU_REGS_RDI); | |
37817f29 IE |
4401 | tss->es = get_segment_selector(vcpu, VCPU_SREG_ES); |
4402 | tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS); | |
4403 | tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS); | |
4404 | tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS); | |
4405 | tss->fs = get_segment_selector(vcpu, VCPU_SREG_FS); | |
4406 | tss->gs = get_segment_selector(vcpu, VCPU_SREG_GS); | |
4407 | tss->ldt_selector = get_segment_selector(vcpu, VCPU_SREG_LDTR); | |
37817f29 IE |
4408 | } |
4409 | ||
4410 | static int load_state_from_tss32(struct kvm_vcpu *vcpu, | |
4411 | struct tss_segment_32 *tss) | |
4412 | { | |
4413 | kvm_set_cr3(vcpu, tss->cr3); | |
4414 | ||
5fdbf976 | 4415 | kvm_rip_write(vcpu, tss->eip); |
91586a3b | 4416 | kvm_set_rflags(vcpu, tss->eflags | 2); |
37817f29 | 4417 | |
5fdbf976 MT |
4418 | kvm_register_write(vcpu, VCPU_REGS_RAX, tss->eax); |
4419 | kvm_register_write(vcpu, VCPU_REGS_RCX, tss->ecx); | |
4420 | kvm_register_write(vcpu, VCPU_REGS_RDX, tss->edx); | |
4421 | kvm_register_write(vcpu, VCPU_REGS_RBX, tss->ebx); | |
4422 | kvm_register_write(vcpu, VCPU_REGS_RSP, tss->esp); | |
4423 | kvm_register_write(vcpu, VCPU_REGS_RBP, tss->ebp); | |
4424 | kvm_register_write(vcpu, VCPU_REGS_RSI, tss->esi); | |
4425 | kvm_register_write(vcpu, VCPU_REGS_RDI, tss->edi); | |
37817f29 | 4426 | |
3e6e0aab | 4427 | if (kvm_load_segment_descriptor(vcpu, tss->ldt_selector, 0, VCPU_SREG_LDTR)) |
37817f29 IE |
4428 | return 1; |
4429 | ||
3e6e0aab | 4430 | if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES)) |
37817f29 IE |
4431 | return 1; |
4432 | ||
3e6e0aab | 4433 | if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS)) |
37817f29 IE |
4434 | return 1; |
4435 | ||
3e6e0aab | 4436 | if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS)) |
37817f29 IE |
4437 | return 1; |
4438 | ||
3e6e0aab | 4439 | if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS)) |
37817f29 IE |
4440 | return 1; |
4441 | ||
3e6e0aab | 4442 | if (kvm_load_segment_descriptor(vcpu, tss->fs, 1, VCPU_SREG_FS)) |
37817f29 IE |
4443 | return 1; |
4444 | ||
3e6e0aab | 4445 | if (kvm_load_segment_descriptor(vcpu, tss->gs, 1, VCPU_SREG_GS)) |
37817f29 IE |
4446 | return 1; |
4447 | return 0; | |
4448 | } | |
4449 | ||
4450 | static void save_state_to_tss16(struct kvm_vcpu *vcpu, | |
4451 | struct tss_segment_16 *tss) | |
4452 | { | |
5fdbf976 | 4453 | tss->ip = kvm_rip_read(vcpu); |
91586a3b | 4454 | tss->flag = kvm_get_rflags(vcpu); |
5fdbf976 MT |
4455 | tss->ax = kvm_register_read(vcpu, VCPU_REGS_RAX); |
4456 | tss->cx = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
4457 | tss->dx = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
4458 | tss->bx = kvm_register_read(vcpu, VCPU_REGS_RBX); | |
4459 | tss->sp = kvm_register_read(vcpu, VCPU_REGS_RSP); | |
4460 | tss->bp = kvm_register_read(vcpu, VCPU_REGS_RBP); | |
4461 | tss->si = kvm_register_read(vcpu, VCPU_REGS_RSI); | |
4462 | tss->di = kvm_register_read(vcpu, VCPU_REGS_RDI); | |
37817f29 IE |
4463 | |
4464 | tss->es = get_segment_selector(vcpu, VCPU_SREG_ES); | |
4465 | tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS); | |
4466 | tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS); | |
4467 | tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS); | |
4468 | tss->ldt = get_segment_selector(vcpu, VCPU_SREG_LDTR); | |
37817f29 IE |
4469 | } |
4470 | ||
4471 | static int load_state_from_tss16(struct kvm_vcpu *vcpu, | |
4472 | struct tss_segment_16 *tss) | |
4473 | { | |
5fdbf976 | 4474 | kvm_rip_write(vcpu, tss->ip); |
91586a3b | 4475 | kvm_set_rflags(vcpu, tss->flag | 2); |
5fdbf976 MT |
4476 | kvm_register_write(vcpu, VCPU_REGS_RAX, tss->ax); |
4477 | kvm_register_write(vcpu, VCPU_REGS_RCX, tss->cx); | |
4478 | kvm_register_write(vcpu, VCPU_REGS_RDX, tss->dx); | |
4479 | kvm_register_write(vcpu, VCPU_REGS_RBX, tss->bx); | |
4480 | kvm_register_write(vcpu, VCPU_REGS_RSP, tss->sp); | |
4481 | kvm_register_write(vcpu, VCPU_REGS_RBP, tss->bp); | |
4482 | kvm_register_write(vcpu, VCPU_REGS_RSI, tss->si); | |
4483 | kvm_register_write(vcpu, VCPU_REGS_RDI, tss->di); | |
37817f29 | 4484 | |
3e6e0aab | 4485 | if (kvm_load_segment_descriptor(vcpu, tss->ldt, 0, VCPU_SREG_LDTR)) |
37817f29 IE |
4486 | return 1; |
4487 | ||
3e6e0aab | 4488 | if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES)) |
37817f29 IE |
4489 | return 1; |
4490 | ||
3e6e0aab | 4491 | if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS)) |
37817f29 IE |
4492 | return 1; |
4493 | ||
3e6e0aab | 4494 | if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS)) |
37817f29 IE |
4495 | return 1; |
4496 | ||
3e6e0aab | 4497 | if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS)) |
37817f29 IE |
4498 | return 1; |
4499 | return 0; | |
4500 | } | |
4501 | ||
8b2cf73c | 4502 | static int kvm_task_switch_16(struct kvm_vcpu *vcpu, u16 tss_selector, |
b237ac37 GN |
4503 | u16 old_tss_sel, u32 old_tss_base, |
4504 | struct desc_struct *nseg_desc) | |
37817f29 IE |
4505 | { |
4506 | struct tss_segment_16 tss_segment_16; | |
4507 | int ret = 0; | |
4508 | ||
34198bf8 MT |
4509 | if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_16, |
4510 | sizeof tss_segment_16)) | |
37817f29 IE |
4511 | goto out; |
4512 | ||
4513 | save_state_to_tss16(vcpu, &tss_segment_16); | |
37817f29 | 4514 | |
34198bf8 MT |
4515 | if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_16, |
4516 | sizeof tss_segment_16)) | |
37817f29 | 4517 | goto out; |
34198bf8 MT |
4518 | |
4519 | if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc), | |
4520 | &tss_segment_16, sizeof tss_segment_16)) | |
4521 | goto out; | |
4522 | ||
b237ac37 GN |
4523 | if (old_tss_sel != 0xffff) { |
4524 | tss_segment_16.prev_task_link = old_tss_sel; | |
4525 | ||
4526 | if (kvm_write_guest(vcpu->kvm, | |
4527 | get_tss_base_addr(vcpu, nseg_desc), | |
4528 | &tss_segment_16.prev_task_link, | |
4529 | sizeof tss_segment_16.prev_task_link)) | |
4530 | goto out; | |
4531 | } | |
4532 | ||
37817f29 IE |
4533 | if (load_state_from_tss16(vcpu, &tss_segment_16)) |
4534 | goto out; | |
4535 | ||
4536 | ret = 1; | |
4537 | out: | |
4538 | return ret; | |
4539 | } | |
4540 | ||
8b2cf73c | 4541 | static int kvm_task_switch_32(struct kvm_vcpu *vcpu, u16 tss_selector, |
b237ac37 | 4542 | u16 old_tss_sel, u32 old_tss_base, |
37817f29 IE |
4543 | struct desc_struct *nseg_desc) |
4544 | { | |
4545 | struct tss_segment_32 tss_segment_32; | |
4546 | int ret = 0; | |
4547 | ||
34198bf8 MT |
4548 | if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_32, |
4549 | sizeof tss_segment_32)) | |
37817f29 IE |
4550 | goto out; |
4551 | ||
4552 | save_state_to_tss32(vcpu, &tss_segment_32); | |
37817f29 | 4553 | |
34198bf8 MT |
4554 | if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_32, |
4555 | sizeof tss_segment_32)) | |
4556 | goto out; | |
4557 | ||
4558 | if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc), | |
4559 | &tss_segment_32, sizeof tss_segment_32)) | |
37817f29 | 4560 | goto out; |
34198bf8 | 4561 | |
b237ac37 GN |
4562 | if (old_tss_sel != 0xffff) { |
4563 | tss_segment_32.prev_task_link = old_tss_sel; | |
4564 | ||
4565 | if (kvm_write_guest(vcpu->kvm, | |
4566 | get_tss_base_addr(vcpu, nseg_desc), | |
4567 | &tss_segment_32.prev_task_link, | |
4568 | sizeof tss_segment_32.prev_task_link)) | |
4569 | goto out; | |
4570 | } | |
4571 | ||
37817f29 IE |
4572 | if (load_state_from_tss32(vcpu, &tss_segment_32)) |
4573 | goto out; | |
4574 | ||
4575 | ret = 1; | |
4576 | out: | |
4577 | return ret; | |
4578 | } | |
4579 | ||
4580 | int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason) | |
4581 | { | |
4582 | struct kvm_segment tr_seg; | |
4583 | struct desc_struct cseg_desc; | |
4584 | struct desc_struct nseg_desc; | |
4585 | int ret = 0; | |
34198bf8 MT |
4586 | u32 old_tss_base = get_segment_base(vcpu, VCPU_SREG_TR); |
4587 | u16 old_tss_sel = get_segment_selector(vcpu, VCPU_SREG_TR); | |
37817f29 | 4588 | |
34198bf8 | 4589 | old_tss_base = vcpu->arch.mmu.gva_to_gpa(vcpu, old_tss_base); |
37817f29 | 4590 | |
34198bf8 MT |
4591 | /* FIXME: Handle errors. Failure to read either TSS or their |
4592 | * descriptors should generate a pagefault. | |
4593 | */ | |
37817f29 IE |
4594 | if (load_guest_segment_descriptor(vcpu, tss_selector, &nseg_desc)) |
4595 | goto out; | |
4596 | ||
34198bf8 | 4597 | if (load_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc)) |
37817f29 IE |
4598 | goto out; |
4599 | ||
37817f29 IE |
4600 | if (reason != TASK_SWITCH_IRET) { |
4601 | int cpl; | |
4602 | ||
4603 | cpl = kvm_x86_ops->get_cpl(vcpu); | |
4604 | if ((tss_selector & 3) > nseg_desc.dpl || cpl > nseg_desc.dpl) { | |
4605 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
4606 | return 1; | |
4607 | } | |
4608 | } | |
4609 | ||
46a359e7 | 4610 | if (!nseg_desc.p || get_desc_limit(&nseg_desc) < 0x67) { |
37817f29 IE |
4611 | kvm_queue_exception_e(vcpu, TS_VECTOR, tss_selector & 0xfffc); |
4612 | return 1; | |
4613 | } | |
4614 | ||
4615 | if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) { | |
3fe913e7 | 4616 | cseg_desc.type &= ~(1 << 1); //clear the B flag |
34198bf8 | 4617 | save_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc); |
37817f29 IE |
4618 | } |
4619 | ||
4620 | if (reason == TASK_SWITCH_IRET) { | |
91586a3b JK |
4621 | u32 eflags = kvm_get_rflags(vcpu); |
4622 | kvm_set_rflags(vcpu, eflags & ~X86_EFLAGS_NT); | |
37817f29 IE |
4623 | } |
4624 | ||
b237ac37 GN |
4625 | /* set back link to prev task only if NT bit is set in eflags |
4626 | note that old_tss_sel is not used afetr this point */ | |
4627 | if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE) | |
4628 | old_tss_sel = 0xffff; | |
4629 | ||
37817f29 | 4630 | if (nseg_desc.type & 8) |
b237ac37 GN |
4631 | ret = kvm_task_switch_32(vcpu, tss_selector, old_tss_sel, |
4632 | old_tss_base, &nseg_desc); | |
37817f29 | 4633 | else |
b237ac37 GN |
4634 | ret = kvm_task_switch_16(vcpu, tss_selector, old_tss_sel, |
4635 | old_tss_base, &nseg_desc); | |
37817f29 IE |
4636 | |
4637 | if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) { | |
91586a3b JK |
4638 | u32 eflags = kvm_get_rflags(vcpu); |
4639 | kvm_set_rflags(vcpu, eflags | X86_EFLAGS_NT); | |
37817f29 IE |
4640 | } |
4641 | ||
4642 | if (reason != TASK_SWITCH_IRET) { | |
3fe913e7 | 4643 | nseg_desc.type |= (1 << 1); |
37817f29 IE |
4644 | save_guest_segment_descriptor(vcpu, tss_selector, |
4645 | &nseg_desc); | |
4646 | } | |
4647 | ||
4648 | kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 | X86_CR0_TS); | |
4649 | seg_desct_to_kvm_desct(&nseg_desc, tss_selector, &tr_seg); | |
4650 | tr_seg.type = 11; | |
3e6e0aab | 4651 | kvm_set_segment(vcpu, &tr_seg, VCPU_SREG_TR); |
37817f29 | 4652 | out: |
37817f29 IE |
4653 | return ret; |
4654 | } | |
4655 | EXPORT_SYMBOL_GPL(kvm_task_switch); | |
4656 | ||
b6c7a5dc HB |
4657 | int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, |
4658 | struct kvm_sregs *sregs) | |
4659 | { | |
4660 | int mmu_reset_needed = 0; | |
923c61bb | 4661 | int pending_vec, max_bits; |
b6c7a5dc HB |
4662 | struct descriptor_table dt; |
4663 | ||
4664 | vcpu_load(vcpu); | |
4665 | ||
4666 | dt.limit = sregs->idt.limit; | |
4667 | dt.base = sregs->idt.base; | |
4668 | kvm_x86_ops->set_idt(vcpu, &dt); | |
4669 | dt.limit = sregs->gdt.limit; | |
4670 | dt.base = sregs->gdt.base; | |
4671 | kvm_x86_ops->set_gdt(vcpu, &dt); | |
4672 | ||
ad312c7c ZX |
4673 | vcpu->arch.cr2 = sregs->cr2; |
4674 | mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3; | |
dc7e795e | 4675 | vcpu->arch.cr3 = sregs->cr3; |
b6c7a5dc | 4676 | |
2d3ad1f4 | 4677 | kvm_set_cr8(vcpu, sregs->cr8); |
b6c7a5dc | 4678 | |
ad312c7c | 4679 | mmu_reset_needed |= vcpu->arch.shadow_efer != sregs->efer; |
b6c7a5dc | 4680 | kvm_x86_ops->set_efer(vcpu, sregs->efer); |
b6c7a5dc HB |
4681 | kvm_set_apic_base(vcpu, sregs->apic_base); |
4682 | ||
4683 | kvm_x86_ops->decache_cr4_guest_bits(vcpu); | |
4684 | ||
ad312c7c | 4685 | mmu_reset_needed |= vcpu->arch.cr0 != sregs->cr0; |
b6c7a5dc | 4686 | kvm_x86_ops->set_cr0(vcpu, sregs->cr0); |
d7306163 | 4687 | vcpu->arch.cr0 = sregs->cr0; |
b6c7a5dc | 4688 | |
ad312c7c | 4689 | mmu_reset_needed |= vcpu->arch.cr4 != sregs->cr4; |
b6c7a5dc | 4690 | kvm_x86_ops->set_cr4(vcpu, sregs->cr4); |
7c93be44 | 4691 | if (!is_long_mode(vcpu) && is_pae(vcpu)) { |
ad312c7c | 4692 | load_pdptrs(vcpu, vcpu->arch.cr3); |
7c93be44 MT |
4693 | mmu_reset_needed = 1; |
4694 | } | |
b6c7a5dc HB |
4695 | |
4696 | if (mmu_reset_needed) | |
4697 | kvm_mmu_reset_context(vcpu); | |
4698 | ||
923c61bb GN |
4699 | max_bits = (sizeof sregs->interrupt_bitmap) << 3; |
4700 | pending_vec = find_first_bit( | |
4701 | (const unsigned long *)sregs->interrupt_bitmap, max_bits); | |
4702 | if (pending_vec < max_bits) { | |
66fd3f7f | 4703 | kvm_queue_interrupt(vcpu, pending_vec, false); |
923c61bb GN |
4704 | pr_debug("Set back pending irq %d\n", pending_vec); |
4705 | if (irqchip_in_kernel(vcpu->kvm)) | |
4706 | kvm_pic_clear_isr_ack(vcpu->kvm); | |
b6c7a5dc HB |
4707 | } |
4708 | ||
3e6e0aab GT |
4709 | kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
4710 | kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
4711 | kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
4712 | kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
4713 | kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
4714 | kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 4715 | |
3e6e0aab GT |
4716 | kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
4717 | kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc | 4718 | |
5f0269f5 ME |
4719 | update_cr8_intercept(vcpu); |
4720 | ||
9c3e4aab | 4721 | /* Older userspace won't unhalt the vcpu on reset. */ |
c5af89b6 | 4722 | if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && |
9c3e4aab MT |
4723 | sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && |
4724 | !(vcpu->arch.cr0 & X86_CR0_PE)) | |
4725 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; | |
4726 | ||
b6c7a5dc HB |
4727 | vcpu_put(vcpu); |
4728 | ||
4729 | return 0; | |
4730 | } | |
4731 | ||
d0bfb940 JK |
4732 | int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, |
4733 | struct kvm_guest_debug *dbg) | |
b6c7a5dc | 4734 | { |
355be0b9 | 4735 | unsigned long rflags; |
4f926bf2 | 4736 | int i, r; |
b6c7a5dc HB |
4737 | |
4738 | vcpu_load(vcpu); | |
4739 | ||
4f926bf2 JK |
4740 | if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { |
4741 | r = -EBUSY; | |
4742 | if (vcpu->arch.exception.pending) | |
4743 | goto unlock_out; | |
4744 | if (dbg->control & KVM_GUESTDBG_INJECT_DB) | |
4745 | kvm_queue_exception(vcpu, DB_VECTOR); | |
4746 | else | |
4747 | kvm_queue_exception(vcpu, BP_VECTOR); | |
4748 | } | |
4749 | ||
91586a3b JK |
4750 | /* |
4751 | * Read rflags as long as potentially injected trace flags are still | |
4752 | * filtered out. | |
4753 | */ | |
4754 | rflags = kvm_get_rflags(vcpu); | |
355be0b9 JK |
4755 | |
4756 | vcpu->guest_debug = dbg->control; | |
4757 | if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) | |
4758 | vcpu->guest_debug = 0; | |
4759 | ||
4760 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { | |
ae675ef0 JK |
4761 | for (i = 0; i < KVM_NR_DB_REGS; ++i) |
4762 | vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; | |
4763 | vcpu->arch.switch_db_regs = | |
4764 | (dbg->arch.debugreg[7] & DR7_BP_EN_MASK); | |
4765 | } else { | |
4766 | for (i = 0; i < KVM_NR_DB_REGS; i++) | |
4767 | vcpu->arch.eff_db[i] = vcpu->arch.db[i]; | |
4768 | vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK); | |
4769 | } | |
4770 | ||
94fe45da JK |
4771 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { |
4772 | vcpu->arch.singlestep_cs = | |
4773 | get_segment_selector(vcpu, VCPU_SREG_CS); | |
4774 | vcpu->arch.singlestep_rip = kvm_rip_read(vcpu); | |
4775 | } | |
4776 | ||
91586a3b JK |
4777 | /* |
4778 | * Trigger an rflags update that will inject or remove the trace | |
4779 | * flags. | |
4780 | */ | |
4781 | kvm_set_rflags(vcpu, rflags); | |
b6c7a5dc | 4782 | |
355be0b9 JK |
4783 | kvm_x86_ops->set_guest_debug(vcpu, dbg); |
4784 | ||
4f926bf2 | 4785 | r = 0; |
d0bfb940 | 4786 | |
4f926bf2 | 4787 | unlock_out: |
b6c7a5dc HB |
4788 | vcpu_put(vcpu); |
4789 | ||
4f926bf2 | 4790 | return r; |
b6c7a5dc HB |
4791 | } |
4792 | ||
d0752060 HB |
4793 | /* |
4794 | * fxsave fpu state. Taken from x86_64/processor.h. To be killed when | |
4795 | * we have asm/x86/processor.h | |
4796 | */ | |
4797 | struct fxsave { | |
4798 | u16 cwd; | |
4799 | u16 swd; | |
4800 | u16 twd; | |
4801 | u16 fop; | |
4802 | u64 rip; | |
4803 | u64 rdp; | |
4804 | u32 mxcsr; | |
4805 | u32 mxcsr_mask; | |
4806 | u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */ | |
4807 | #ifdef CONFIG_X86_64 | |
4808 | u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */ | |
4809 | #else | |
4810 | u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */ | |
4811 | #endif | |
4812 | }; | |
4813 | ||
8b006791 ZX |
4814 | /* |
4815 | * Translate a guest virtual address to a guest physical address. | |
4816 | */ | |
4817 | int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, | |
4818 | struct kvm_translation *tr) | |
4819 | { | |
4820 | unsigned long vaddr = tr->linear_address; | |
4821 | gpa_t gpa; | |
4822 | ||
4823 | vcpu_load(vcpu); | |
72dc67a6 | 4824 | down_read(&vcpu->kvm->slots_lock); |
ad312c7c | 4825 | gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, vaddr); |
72dc67a6 | 4826 | up_read(&vcpu->kvm->slots_lock); |
8b006791 ZX |
4827 | tr->physical_address = gpa; |
4828 | tr->valid = gpa != UNMAPPED_GVA; | |
4829 | tr->writeable = 1; | |
4830 | tr->usermode = 0; | |
8b006791 ZX |
4831 | vcpu_put(vcpu); |
4832 | ||
4833 | return 0; | |
4834 | } | |
4835 | ||
d0752060 HB |
4836 | int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) |
4837 | { | |
ad312c7c | 4838 | struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image; |
d0752060 HB |
4839 | |
4840 | vcpu_load(vcpu); | |
4841 | ||
4842 | memcpy(fpu->fpr, fxsave->st_space, 128); | |
4843 | fpu->fcw = fxsave->cwd; | |
4844 | fpu->fsw = fxsave->swd; | |
4845 | fpu->ftwx = fxsave->twd; | |
4846 | fpu->last_opcode = fxsave->fop; | |
4847 | fpu->last_ip = fxsave->rip; | |
4848 | fpu->last_dp = fxsave->rdp; | |
4849 | memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space); | |
4850 | ||
4851 | vcpu_put(vcpu); | |
4852 | ||
4853 | return 0; | |
4854 | } | |
4855 | ||
4856 | int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) | |
4857 | { | |
ad312c7c | 4858 | struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image; |
d0752060 HB |
4859 | |
4860 | vcpu_load(vcpu); | |
4861 | ||
4862 | memcpy(fxsave->st_space, fpu->fpr, 128); | |
4863 | fxsave->cwd = fpu->fcw; | |
4864 | fxsave->swd = fpu->fsw; | |
4865 | fxsave->twd = fpu->ftwx; | |
4866 | fxsave->fop = fpu->last_opcode; | |
4867 | fxsave->rip = fpu->last_ip; | |
4868 | fxsave->rdp = fpu->last_dp; | |
4869 | memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space); | |
4870 | ||
4871 | vcpu_put(vcpu); | |
4872 | ||
4873 | return 0; | |
4874 | } | |
4875 | ||
4876 | void fx_init(struct kvm_vcpu *vcpu) | |
4877 | { | |
4878 | unsigned after_mxcsr_mask; | |
4879 | ||
bc1a34f1 AA |
4880 | /* |
4881 | * Touch the fpu the first time in non atomic context as if | |
4882 | * this is the first fpu instruction the exception handler | |
4883 | * will fire before the instruction returns and it'll have to | |
4884 | * allocate ram with GFP_KERNEL. | |
4885 | */ | |
4886 | if (!used_math()) | |
d6e88aec | 4887 | kvm_fx_save(&vcpu->arch.host_fx_image); |
bc1a34f1 | 4888 | |
d0752060 HB |
4889 | /* Initialize guest FPU by resetting ours and saving into guest's */ |
4890 | preempt_disable(); | |
d6e88aec AK |
4891 | kvm_fx_save(&vcpu->arch.host_fx_image); |
4892 | kvm_fx_finit(); | |
4893 | kvm_fx_save(&vcpu->arch.guest_fx_image); | |
4894 | kvm_fx_restore(&vcpu->arch.host_fx_image); | |
d0752060 HB |
4895 | preempt_enable(); |
4896 | ||
ad312c7c | 4897 | vcpu->arch.cr0 |= X86_CR0_ET; |
d0752060 | 4898 | after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space); |
ad312c7c ZX |
4899 | vcpu->arch.guest_fx_image.mxcsr = 0x1f80; |
4900 | memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask, | |
d0752060 HB |
4901 | 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask); |
4902 | } | |
4903 | EXPORT_SYMBOL_GPL(fx_init); | |
4904 | ||
4905 | void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) | |
4906 | { | |
4907 | if (!vcpu->fpu_active || vcpu->guest_fpu_loaded) | |
4908 | return; | |
4909 | ||
4910 | vcpu->guest_fpu_loaded = 1; | |
d6e88aec AK |
4911 | kvm_fx_save(&vcpu->arch.host_fx_image); |
4912 | kvm_fx_restore(&vcpu->arch.guest_fx_image); | |
d0752060 HB |
4913 | } |
4914 | EXPORT_SYMBOL_GPL(kvm_load_guest_fpu); | |
4915 | ||
4916 | void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) | |
4917 | { | |
4918 | if (!vcpu->guest_fpu_loaded) | |
4919 | return; | |
4920 | ||
4921 | vcpu->guest_fpu_loaded = 0; | |
d6e88aec AK |
4922 | kvm_fx_save(&vcpu->arch.guest_fx_image); |
4923 | kvm_fx_restore(&vcpu->arch.host_fx_image); | |
f096ed85 | 4924 | ++vcpu->stat.fpu_reload; |
d0752060 HB |
4925 | } |
4926 | EXPORT_SYMBOL_GPL(kvm_put_guest_fpu); | |
e9b11c17 ZX |
4927 | |
4928 | void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu) | |
4929 | { | |
7f1ea208 JR |
4930 | if (vcpu->arch.time_page) { |
4931 | kvm_release_page_dirty(vcpu->arch.time_page); | |
4932 | vcpu->arch.time_page = NULL; | |
4933 | } | |
4934 | ||
e9b11c17 ZX |
4935 | kvm_x86_ops->vcpu_free(vcpu); |
4936 | } | |
4937 | ||
4938 | struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, | |
4939 | unsigned int id) | |
4940 | { | |
26e5215f AK |
4941 | return kvm_x86_ops->vcpu_create(kvm, id); |
4942 | } | |
e9b11c17 | 4943 | |
26e5215f AK |
4944 | int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) |
4945 | { | |
4946 | int r; | |
e9b11c17 ZX |
4947 | |
4948 | /* We do fxsave: this must be aligned. */ | |
ad312c7c | 4949 | BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF); |
e9b11c17 | 4950 | |
0bed3b56 | 4951 | vcpu->arch.mtrr_state.have_fixed = 1; |
e9b11c17 ZX |
4952 | vcpu_load(vcpu); |
4953 | r = kvm_arch_vcpu_reset(vcpu); | |
4954 | if (r == 0) | |
4955 | r = kvm_mmu_setup(vcpu); | |
4956 | vcpu_put(vcpu); | |
4957 | if (r < 0) | |
4958 | goto free_vcpu; | |
4959 | ||
26e5215f | 4960 | return 0; |
e9b11c17 ZX |
4961 | free_vcpu: |
4962 | kvm_x86_ops->vcpu_free(vcpu); | |
26e5215f | 4963 | return r; |
e9b11c17 ZX |
4964 | } |
4965 | ||
d40ccc62 | 4966 | void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) |
e9b11c17 ZX |
4967 | { |
4968 | vcpu_load(vcpu); | |
4969 | kvm_mmu_unload(vcpu); | |
4970 | vcpu_put(vcpu); | |
4971 | ||
4972 | kvm_x86_ops->vcpu_free(vcpu); | |
4973 | } | |
4974 | ||
4975 | int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu) | |
4976 | { | |
448fa4a9 JK |
4977 | vcpu->arch.nmi_pending = false; |
4978 | vcpu->arch.nmi_injected = false; | |
4979 | ||
42dbaa5a JK |
4980 | vcpu->arch.switch_db_regs = 0; |
4981 | memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); | |
4982 | vcpu->arch.dr6 = DR6_FIXED_1; | |
4983 | vcpu->arch.dr7 = DR7_FIXED_1; | |
4984 | ||
e9b11c17 ZX |
4985 | return kvm_x86_ops->vcpu_reset(vcpu); |
4986 | } | |
4987 | ||
10474ae8 | 4988 | int kvm_arch_hardware_enable(void *garbage) |
e9b11c17 | 4989 | { |
0cca7907 ZA |
4990 | /* |
4991 | * Since this may be called from a hotplug notifcation, | |
4992 | * we can't get the CPU frequency directly. | |
4993 | */ | |
4994 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { | |
4995 | int cpu = raw_smp_processor_id(); | |
4996 | per_cpu(cpu_tsc_khz, cpu) = 0; | |
4997 | } | |
18863bdd AK |
4998 | |
4999 | kvm_shared_msr_cpu_online(); | |
5000 | ||
10474ae8 | 5001 | return kvm_x86_ops->hardware_enable(garbage); |
e9b11c17 ZX |
5002 | } |
5003 | ||
5004 | void kvm_arch_hardware_disable(void *garbage) | |
5005 | { | |
5006 | kvm_x86_ops->hardware_disable(garbage); | |
5007 | } | |
5008 | ||
5009 | int kvm_arch_hardware_setup(void) | |
5010 | { | |
5011 | return kvm_x86_ops->hardware_setup(); | |
5012 | } | |
5013 | ||
5014 | void kvm_arch_hardware_unsetup(void) | |
5015 | { | |
5016 | kvm_x86_ops->hardware_unsetup(); | |
5017 | } | |
5018 | ||
5019 | void kvm_arch_check_processor_compat(void *rtn) | |
5020 | { | |
5021 | kvm_x86_ops->check_processor_compatibility(rtn); | |
5022 | } | |
5023 | ||
5024 | int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) | |
5025 | { | |
5026 | struct page *page; | |
5027 | struct kvm *kvm; | |
5028 | int r; | |
5029 | ||
5030 | BUG_ON(vcpu->kvm == NULL); | |
5031 | kvm = vcpu->kvm; | |
5032 | ||
ad312c7c | 5033 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
c5af89b6 | 5034 | if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu)) |
a4535290 | 5035 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
e9b11c17 | 5036 | else |
a4535290 | 5037 | vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; |
e9b11c17 ZX |
5038 | |
5039 | page = alloc_page(GFP_KERNEL | __GFP_ZERO); | |
5040 | if (!page) { | |
5041 | r = -ENOMEM; | |
5042 | goto fail; | |
5043 | } | |
ad312c7c | 5044 | vcpu->arch.pio_data = page_address(page); |
e9b11c17 ZX |
5045 | |
5046 | r = kvm_mmu_create(vcpu); | |
5047 | if (r < 0) | |
5048 | goto fail_free_pio_data; | |
5049 | ||
5050 | if (irqchip_in_kernel(kvm)) { | |
5051 | r = kvm_create_lapic(vcpu); | |
5052 | if (r < 0) | |
5053 | goto fail_mmu_destroy; | |
5054 | } | |
5055 | ||
890ca9ae HY |
5056 | vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4, |
5057 | GFP_KERNEL); | |
5058 | if (!vcpu->arch.mce_banks) { | |
5059 | r = -ENOMEM; | |
5060 | goto fail_mmu_destroy; | |
5061 | } | |
5062 | vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; | |
5063 | ||
e9b11c17 ZX |
5064 | return 0; |
5065 | ||
5066 | fail_mmu_destroy: | |
5067 | kvm_mmu_destroy(vcpu); | |
5068 | fail_free_pio_data: | |
ad312c7c | 5069 | free_page((unsigned long)vcpu->arch.pio_data); |
e9b11c17 ZX |
5070 | fail: |
5071 | return r; | |
5072 | } | |
5073 | ||
5074 | void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) | |
5075 | { | |
5076 | kvm_free_lapic(vcpu); | |
3200f405 | 5077 | down_read(&vcpu->kvm->slots_lock); |
e9b11c17 | 5078 | kvm_mmu_destroy(vcpu); |
3200f405 | 5079 | up_read(&vcpu->kvm->slots_lock); |
ad312c7c | 5080 | free_page((unsigned long)vcpu->arch.pio_data); |
e9b11c17 | 5081 | } |
d19a9cd2 ZX |
5082 | |
5083 | struct kvm *kvm_arch_create_vm(void) | |
5084 | { | |
5085 | struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL); | |
5086 | ||
5087 | if (!kvm) | |
5088 | return ERR_PTR(-ENOMEM); | |
5089 | ||
f05e70ac | 5090 | INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); |
4d5c5d0f | 5091 | INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); |
d19a9cd2 | 5092 | |
5550af4d SY |
5093 | /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ |
5094 | set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); | |
5095 | ||
53f658b3 MT |
5096 | rdtscll(kvm->arch.vm_init_tsc); |
5097 | ||
d19a9cd2 ZX |
5098 | return kvm; |
5099 | } | |
5100 | ||
5101 | static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) | |
5102 | { | |
5103 | vcpu_load(vcpu); | |
5104 | kvm_mmu_unload(vcpu); | |
5105 | vcpu_put(vcpu); | |
5106 | } | |
5107 | ||
5108 | static void kvm_free_vcpus(struct kvm *kvm) | |
5109 | { | |
5110 | unsigned int i; | |
988a2cae | 5111 | struct kvm_vcpu *vcpu; |
d19a9cd2 ZX |
5112 | |
5113 | /* | |
5114 | * Unpin any mmu pages first. | |
5115 | */ | |
988a2cae GN |
5116 | kvm_for_each_vcpu(i, vcpu, kvm) |
5117 | kvm_unload_vcpu_mmu(vcpu); | |
5118 | kvm_for_each_vcpu(i, vcpu, kvm) | |
5119 | kvm_arch_vcpu_free(vcpu); | |
5120 | ||
5121 | mutex_lock(&kvm->lock); | |
5122 | for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) | |
5123 | kvm->vcpus[i] = NULL; | |
d19a9cd2 | 5124 | |
988a2cae GN |
5125 | atomic_set(&kvm->online_vcpus, 0); |
5126 | mutex_unlock(&kvm->lock); | |
d19a9cd2 ZX |
5127 | } |
5128 | ||
ad8ba2cd SY |
5129 | void kvm_arch_sync_events(struct kvm *kvm) |
5130 | { | |
ba4cef31 | 5131 | kvm_free_all_assigned_devices(kvm); |
ad8ba2cd SY |
5132 | } |
5133 | ||
d19a9cd2 ZX |
5134 | void kvm_arch_destroy_vm(struct kvm *kvm) |
5135 | { | |
6eb55818 | 5136 | kvm_iommu_unmap_guest(kvm); |
7837699f | 5137 | kvm_free_pit(kvm); |
d7deeeb0 ZX |
5138 | kfree(kvm->arch.vpic); |
5139 | kfree(kvm->arch.vioapic); | |
d19a9cd2 ZX |
5140 | kvm_free_vcpus(kvm); |
5141 | kvm_free_physmem(kvm); | |
3d45830c AK |
5142 | if (kvm->arch.apic_access_page) |
5143 | put_page(kvm->arch.apic_access_page); | |
b7ebfb05 SY |
5144 | if (kvm->arch.ept_identity_pagetable) |
5145 | put_page(kvm->arch.ept_identity_pagetable); | |
d19a9cd2 ZX |
5146 | kfree(kvm); |
5147 | } | |
0de10343 ZX |
5148 | |
5149 | int kvm_arch_set_memory_region(struct kvm *kvm, | |
5150 | struct kvm_userspace_memory_region *mem, | |
5151 | struct kvm_memory_slot old, | |
5152 | int user_alloc) | |
5153 | { | |
5154 | int npages = mem->memory_size >> PAGE_SHIFT; | |
5155 | struct kvm_memory_slot *memslot = &kvm->memslots[mem->slot]; | |
5156 | ||
5157 | /*To keep backward compatibility with older userspace, | |
5158 | *x86 needs to hanlde !user_alloc case. | |
5159 | */ | |
5160 | if (!user_alloc) { | |
5161 | if (npages && !old.rmap) { | |
604b38ac AA |
5162 | unsigned long userspace_addr; |
5163 | ||
72dc67a6 | 5164 | down_write(¤t->mm->mmap_sem); |
604b38ac AA |
5165 | userspace_addr = do_mmap(NULL, 0, |
5166 | npages * PAGE_SIZE, | |
5167 | PROT_READ | PROT_WRITE, | |
acee3c04 | 5168 | MAP_PRIVATE | MAP_ANONYMOUS, |
604b38ac | 5169 | 0); |
72dc67a6 | 5170 | up_write(¤t->mm->mmap_sem); |
0de10343 | 5171 | |
604b38ac AA |
5172 | if (IS_ERR((void *)userspace_addr)) |
5173 | return PTR_ERR((void *)userspace_addr); | |
5174 | ||
5175 | /* set userspace_addr atomically for kvm_hva_to_rmapp */ | |
5176 | spin_lock(&kvm->mmu_lock); | |
5177 | memslot->userspace_addr = userspace_addr; | |
5178 | spin_unlock(&kvm->mmu_lock); | |
0de10343 ZX |
5179 | } else { |
5180 | if (!old.user_alloc && old.rmap) { | |
5181 | int ret; | |
5182 | ||
72dc67a6 | 5183 | down_write(¤t->mm->mmap_sem); |
0de10343 ZX |
5184 | ret = do_munmap(current->mm, old.userspace_addr, |
5185 | old.npages * PAGE_SIZE); | |
72dc67a6 | 5186 | up_write(¤t->mm->mmap_sem); |
0de10343 ZX |
5187 | if (ret < 0) |
5188 | printk(KERN_WARNING | |
5189 | "kvm_vm_ioctl_set_memory_region: " | |
5190 | "failed to munmap memory\n"); | |
5191 | } | |
5192 | } | |
5193 | } | |
5194 | ||
7c8a83b7 | 5195 | spin_lock(&kvm->mmu_lock); |
f05e70ac | 5196 | if (!kvm->arch.n_requested_mmu_pages) { |
0de10343 ZX |
5197 | unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm); |
5198 | kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages); | |
5199 | } | |
5200 | ||
5201 | kvm_mmu_slot_remove_write_access(kvm, mem->slot); | |
7c8a83b7 | 5202 | spin_unlock(&kvm->mmu_lock); |
0de10343 ZX |
5203 | |
5204 | return 0; | |
5205 | } | |
1d737c8a | 5206 | |
34d4cb8f MT |
5207 | void kvm_arch_flush_shadow(struct kvm *kvm) |
5208 | { | |
5209 | kvm_mmu_zap_all(kvm); | |
8986ecc0 | 5210 | kvm_reload_remote_mmus(kvm); |
34d4cb8f MT |
5211 | } |
5212 | ||
1d737c8a ZX |
5213 | int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) |
5214 | { | |
a4535290 | 5215 | return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE |
a1b37100 GN |
5216 | || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED |
5217 | || vcpu->arch.nmi_pending || | |
5218 | (kvm_arch_interrupt_allowed(vcpu) && | |
5219 | kvm_cpu_has_interrupt(vcpu)); | |
1d737c8a | 5220 | } |
5736199a | 5221 | |
5736199a ZX |
5222 | void kvm_vcpu_kick(struct kvm_vcpu *vcpu) |
5223 | { | |
32f88400 MT |
5224 | int me; |
5225 | int cpu = vcpu->cpu; | |
5736199a ZX |
5226 | |
5227 | if (waitqueue_active(&vcpu->wq)) { | |
5228 | wake_up_interruptible(&vcpu->wq); | |
5229 | ++vcpu->stat.halt_wakeup; | |
5230 | } | |
32f88400 MT |
5231 | |
5232 | me = get_cpu(); | |
5233 | if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu)) | |
5234 | if (!test_and_set_bit(KVM_REQ_KICK, &vcpu->requests)) | |
5235 | smp_send_reschedule(cpu); | |
e9571ed5 | 5236 | put_cpu(); |
5736199a | 5237 | } |
78646121 GN |
5238 | |
5239 | int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) | |
5240 | { | |
5241 | return kvm_x86_ops->interrupt_allowed(vcpu); | |
5242 | } | |
229456fc | 5243 | |
94fe45da JK |
5244 | unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) |
5245 | { | |
5246 | unsigned long rflags; | |
5247 | ||
5248 | rflags = kvm_x86_ops->get_rflags(vcpu); | |
5249 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) | |
5250 | rflags &= ~(unsigned long)(X86_EFLAGS_TF | X86_EFLAGS_RF); | |
5251 | return rflags; | |
5252 | } | |
5253 | EXPORT_SYMBOL_GPL(kvm_get_rflags); | |
5254 | ||
5255 | void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
5256 | { | |
5257 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && | |
5258 | vcpu->arch.singlestep_cs == | |
5259 | get_segment_selector(vcpu, VCPU_SREG_CS) && | |
5260 | vcpu->arch.singlestep_rip == kvm_rip_read(vcpu)) | |
5261 | rflags |= X86_EFLAGS_TF | X86_EFLAGS_RF; | |
5262 | kvm_x86_ops->set_rflags(vcpu, rflags); | |
5263 | } | |
5264 | EXPORT_SYMBOL_GPL(kvm_set_rflags); | |
5265 | ||
229456fc MT |
5266 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); |
5267 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); | |
5268 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); | |
5269 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); | |
5270 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); | |
0ac406de | 5271 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun); |
d8cabddf | 5272 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); |
17897f36 | 5273 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); |
236649de | 5274 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); |
ec1ff790 | 5275 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); |
532a46b9 | 5276 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); |