Commit | Line | Data |
---|---|---|
043405e1 CO |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * derived from drivers/kvm/kvm_main.c | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
4d5c5d0f BAY |
7 | * Copyright (C) 2008 Qumranet, Inc. |
8 | * Copyright IBM Corporation, 2008 | |
043405e1 CO |
9 | * |
10 | * Authors: | |
11 | * Avi Kivity <avi@qumranet.com> | |
12 | * Yaniv Kamay <yaniv@qumranet.com> | |
4d5c5d0f BAY |
13 | * Amit Shah <amit.shah@qumranet.com> |
14 | * Ben-Ami Yassour <benami@il.ibm.com> | |
043405e1 CO |
15 | * |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | * | |
19 | */ | |
20 | ||
edf88417 | 21 | #include <linux/kvm_host.h> |
313a3dc7 | 22 | #include "irq.h" |
1d737c8a | 23 | #include "mmu.h" |
7837699f | 24 | #include "i8254.h" |
37817f29 | 25 | #include "tss.h" |
5fdbf976 | 26 | #include "kvm_cache_regs.h" |
26eef70c | 27 | #include "x86.h" |
313a3dc7 | 28 | |
18068523 | 29 | #include <linux/clocksource.h> |
4d5c5d0f | 30 | #include <linux/interrupt.h> |
313a3dc7 CO |
31 | #include <linux/kvm.h> |
32 | #include <linux/fs.h> | |
33 | #include <linux/vmalloc.h> | |
5fb76f9b | 34 | #include <linux/module.h> |
0de10343 | 35 | #include <linux/mman.h> |
2bacc55c | 36 | #include <linux/highmem.h> |
19de40a8 | 37 | #include <linux/iommu.h> |
62c476c7 | 38 | #include <linux/intel-iommu.h> |
c8076604 | 39 | #include <linux/cpufreq.h> |
043405e1 CO |
40 | |
41 | #include <asm/uaccess.h> | |
d825ed0a | 42 | #include <asm/msr.h> |
a5f61300 | 43 | #include <asm/desc.h> |
0bed3b56 | 44 | #include <asm/mtrr.h> |
043405e1 | 45 | |
313a3dc7 | 46 | #define MAX_IO_MSRS 256 |
a03490ed CO |
47 | #define CR0_RESERVED_BITS \ |
48 | (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \ | |
49 | | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \ | |
50 | | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG)) | |
51 | #define CR4_RESERVED_BITS \ | |
52 | (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\ | |
53 | | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \ | |
54 | | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \ | |
55 | | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE)) | |
56 | ||
57 | #define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR) | |
50a37eb4 JR |
58 | /* EFER defaults: |
59 | * - enable syscall per default because its emulated by KVM | |
60 | * - enable LME and LMA per default on 64 bit KVM | |
61 | */ | |
62 | #ifdef CONFIG_X86_64 | |
63 | static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL; | |
64 | #else | |
65 | static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL; | |
66 | #endif | |
313a3dc7 | 67 | |
ba1389b7 AK |
68 | #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM |
69 | #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU | |
417bc304 | 70 | |
674eea0f AK |
71 | static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid, |
72 | struct kvm_cpuid_entry2 __user *entries); | |
d8017474 AG |
73 | struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu, |
74 | u32 function, u32 index); | |
674eea0f | 75 | |
97896d04 | 76 | struct kvm_x86_ops *kvm_x86_ops; |
5fdbf976 | 77 | EXPORT_SYMBOL_GPL(kvm_x86_ops); |
97896d04 | 78 | |
417bc304 | 79 | struct kvm_stats_debugfs_item debugfs_entries[] = { |
ba1389b7 AK |
80 | { "pf_fixed", VCPU_STAT(pf_fixed) }, |
81 | { "pf_guest", VCPU_STAT(pf_guest) }, | |
82 | { "tlb_flush", VCPU_STAT(tlb_flush) }, | |
83 | { "invlpg", VCPU_STAT(invlpg) }, | |
84 | { "exits", VCPU_STAT(exits) }, | |
85 | { "io_exits", VCPU_STAT(io_exits) }, | |
86 | { "mmio_exits", VCPU_STAT(mmio_exits) }, | |
87 | { "signal_exits", VCPU_STAT(signal_exits) }, | |
88 | { "irq_window", VCPU_STAT(irq_window_exits) }, | |
f08864b4 | 89 | { "nmi_window", VCPU_STAT(nmi_window_exits) }, |
ba1389b7 AK |
90 | { "halt_exits", VCPU_STAT(halt_exits) }, |
91 | { "halt_wakeup", VCPU_STAT(halt_wakeup) }, | |
f11c3a8d | 92 | { "hypercalls", VCPU_STAT(hypercalls) }, |
ba1389b7 | 93 | { "request_irq", VCPU_STAT(request_irq_exits) }, |
c4abb7c9 | 94 | { "request_nmi", VCPU_STAT(request_nmi_exits) }, |
ba1389b7 AK |
95 | { "irq_exits", VCPU_STAT(irq_exits) }, |
96 | { "host_state_reload", VCPU_STAT(host_state_reload) }, | |
97 | { "efer_reload", VCPU_STAT(efer_reload) }, | |
98 | { "fpu_reload", VCPU_STAT(fpu_reload) }, | |
99 | { "insn_emulation", VCPU_STAT(insn_emulation) }, | |
100 | { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) }, | |
fa89a817 | 101 | { "irq_injections", VCPU_STAT(irq_injections) }, |
c4abb7c9 | 102 | { "nmi_injections", VCPU_STAT(nmi_injections) }, |
4cee5764 AK |
103 | { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) }, |
104 | { "mmu_pte_write", VM_STAT(mmu_pte_write) }, | |
105 | { "mmu_pte_updated", VM_STAT(mmu_pte_updated) }, | |
106 | { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) }, | |
107 | { "mmu_flooded", VM_STAT(mmu_flooded) }, | |
108 | { "mmu_recycled", VM_STAT(mmu_recycled) }, | |
dfc5aa00 | 109 | { "mmu_cache_miss", VM_STAT(mmu_cache_miss) }, |
4731d4c7 | 110 | { "mmu_unsync", VM_STAT(mmu_unsync) }, |
0f74a24c | 111 | { "remote_tlb_flush", VM_STAT(remote_tlb_flush) }, |
05da4558 | 112 | { "largepages", VM_STAT(lpages) }, |
417bc304 HB |
113 | { NULL } |
114 | }; | |
115 | ||
5fb76f9b CO |
116 | unsigned long segment_base(u16 selector) |
117 | { | |
118 | struct descriptor_table gdt; | |
a5f61300 | 119 | struct desc_struct *d; |
5fb76f9b CO |
120 | unsigned long table_base; |
121 | unsigned long v; | |
122 | ||
123 | if (selector == 0) | |
124 | return 0; | |
125 | ||
126 | asm("sgdt %0" : "=m"(gdt)); | |
127 | table_base = gdt.base; | |
128 | ||
129 | if (selector & 4) { /* from ldt */ | |
130 | u16 ldt_selector; | |
131 | ||
132 | asm("sldt %0" : "=g"(ldt_selector)); | |
133 | table_base = segment_base(ldt_selector); | |
134 | } | |
a5f61300 AK |
135 | d = (struct desc_struct *)(table_base + (selector & ~7)); |
136 | v = d->base0 | ((unsigned long)d->base1 << 16) | | |
137 | ((unsigned long)d->base2 << 24); | |
5fb76f9b | 138 | #ifdef CONFIG_X86_64 |
a5f61300 AK |
139 | if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11)) |
140 | v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32; | |
5fb76f9b CO |
141 | #endif |
142 | return v; | |
143 | } | |
144 | EXPORT_SYMBOL_GPL(segment_base); | |
145 | ||
6866b83e CO |
146 | u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) |
147 | { | |
148 | if (irqchip_in_kernel(vcpu->kvm)) | |
ad312c7c | 149 | return vcpu->arch.apic_base; |
6866b83e | 150 | else |
ad312c7c | 151 | return vcpu->arch.apic_base; |
6866b83e CO |
152 | } |
153 | EXPORT_SYMBOL_GPL(kvm_get_apic_base); | |
154 | ||
155 | void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data) | |
156 | { | |
157 | /* TODO: reserve bits check */ | |
158 | if (irqchip_in_kernel(vcpu->kvm)) | |
159 | kvm_lapic_set_base(vcpu, data); | |
160 | else | |
ad312c7c | 161 | vcpu->arch.apic_base = data; |
6866b83e CO |
162 | } |
163 | EXPORT_SYMBOL_GPL(kvm_set_apic_base); | |
164 | ||
298101da AK |
165 | void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
166 | { | |
ad312c7c ZX |
167 | WARN_ON(vcpu->arch.exception.pending); |
168 | vcpu->arch.exception.pending = true; | |
169 | vcpu->arch.exception.has_error_code = false; | |
170 | vcpu->arch.exception.nr = nr; | |
298101da AK |
171 | } |
172 | EXPORT_SYMBOL_GPL(kvm_queue_exception); | |
173 | ||
c3c91fee AK |
174 | void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr, |
175 | u32 error_code) | |
176 | { | |
177 | ++vcpu->stat.pf_guest; | |
d8017474 | 178 | |
71c4dfaf JR |
179 | if (vcpu->arch.exception.pending) { |
180 | if (vcpu->arch.exception.nr == PF_VECTOR) { | |
181 | printk(KERN_DEBUG "kvm: inject_page_fault:" | |
182 | " double fault 0x%lx\n", addr); | |
183 | vcpu->arch.exception.nr = DF_VECTOR; | |
184 | vcpu->arch.exception.error_code = 0; | |
185 | } else if (vcpu->arch.exception.nr == DF_VECTOR) { | |
186 | /* triple fault -> shutdown */ | |
187 | set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests); | |
188 | } | |
c3c91fee AK |
189 | return; |
190 | } | |
ad312c7c | 191 | vcpu->arch.cr2 = addr; |
c3c91fee AK |
192 | kvm_queue_exception_e(vcpu, PF_VECTOR, error_code); |
193 | } | |
194 | ||
3419ffc8 SY |
195 | void kvm_inject_nmi(struct kvm_vcpu *vcpu) |
196 | { | |
197 | vcpu->arch.nmi_pending = 1; | |
198 | } | |
199 | EXPORT_SYMBOL_GPL(kvm_inject_nmi); | |
200 | ||
298101da AK |
201 | void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
202 | { | |
ad312c7c ZX |
203 | WARN_ON(vcpu->arch.exception.pending); |
204 | vcpu->arch.exception.pending = true; | |
205 | vcpu->arch.exception.has_error_code = true; | |
206 | vcpu->arch.exception.nr = nr; | |
207 | vcpu->arch.exception.error_code = error_code; | |
298101da AK |
208 | } |
209 | EXPORT_SYMBOL_GPL(kvm_queue_exception_e); | |
210 | ||
211 | static void __queue_exception(struct kvm_vcpu *vcpu) | |
212 | { | |
ad312c7c ZX |
213 | kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr, |
214 | vcpu->arch.exception.has_error_code, | |
215 | vcpu->arch.exception.error_code); | |
298101da AK |
216 | } |
217 | ||
a03490ed CO |
218 | /* |
219 | * Load the pae pdptrs. Return true is they are all valid. | |
220 | */ | |
221 | int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3) | |
222 | { | |
223 | gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; | |
224 | unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2; | |
225 | int i; | |
226 | int ret; | |
ad312c7c | 227 | u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)]; |
a03490ed | 228 | |
a03490ed CO |
229 | ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte, |
230 | offset * sizeof(u64), sizeof(pdpte)); | |
231 | if (ret < 0) { | |
232 | ret = 0; | |
233 | goto out; | |
234 | } | |
235 | for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { | |
20c466b5 DE |
236 | if (is_present_pte(pdpte[i]) && |
237 | (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) { | |
a03490ed CO |
238 | ret = 0; |
239 | goto out; | |
240 | } | |
241 | } | |
242 | ret = 1; | |
243 | ||
ad312c7c | 244 | memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs)); |
a03490ed | 245 | out: |
a03490ed CO |
246 | |
247 | return ret; | |
248 | } | |
cc4b6871 | 249 | EXPORT_SYMBOL_GPL(load_pdptrs); |
a03490ed | 250 | |
d835dfec AK |
251 | static bool pdptrs_changed(struct kvm_vcpu *vcpu) |
252 | { | |
ad312c7c | 253 | u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)]; |
d835dfec AK |
254 | bool changed = true; |
255 | int r; | |
256 | ||
257 | if (is_long_mode(vcpu) || !is_pae(vcpu)) | |
258 | return false; | |
259 | ||
ad312c7c | 260 | r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte)); |
d835dfec AK |
261 | if (r < 0) |
262 | goto out; | |
ad312c7c | 263 | changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0; |
d835dfec | 264 | out: |
d835dfec AK |
265 | |
266 | return changed; | |
267 | } | |
268 | ||
2d3ad1f4 | 269 | void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
a03490ed CO |
270 | { |
271 | if (cr0 & CR0_RESERVED_BITS) { | |
272 | printk(KERN_DEBUG "set_cr0: 0x%lx #GP, reserved bits 0x%lx\n", | |
ad312c7c | 273 | cr0, vcpu->arch.cr0); |
c1a5d4f9 | 274 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
275 | return; |
276 | } | |
277 | ||
278 | if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) { | |
279 | printk(KERN_DEBUG "set_cr0: #GP, CD == 0 && NW == 1\n"); | |
c1a5d4f9 | 280 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
281 | return; |
282 | } | |
283 | ||
284 | if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) { | |
285 | printk(KERN_DEBUG "set_cr0: #GP, set PG flag " | |
286 | "and a clear PE flag\n"); | |
c1a5d4f9 | 287 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
288 | return; |
289 | } | |
290 | ||
291 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { | |
292 | #ifdef CONFIG_X86_64 | |
ad312c7c | 293 | if ((vcpu->arch.shadow_efer & EFER_LME)) { |
a03490ed CO |
294 | int cs_db, cs_l; |
295 | ||
296 | if (!is_pae(vcpu)) { | |
297 | printk(KERN_DEBUG "set_cr0: #GP, start paging " | |
298 | "in long mode while PAE is disabled\n"); | |
c1a5d4f9 | 299 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
300 | return; |
301 | } | |
302 | kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); | |
303 | if (cs_l) { | |
304 | printk(KERN_DEBUG "set_cr0: #GP, start paging " | |
305 | "in long mode while CS.L == 1\n"); | |
c1a5d4f9 | 306 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
307 | return; |
308 | ||
309 | } | |
310 | } else | |
311 | #endif | |
ad312c7c | 312 | if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) { |
a03490ed CO |
313 | printk(KERN_DEBUG "set_cr0: #GP, pdptrs " |
314 | "reserved bits\n"); | |
c1a5d4f9 | 315 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
316 | return; |
317 | } | |
318 | ||
319 | } | |
320 | ||
321 | kvm_x86_ops->set_cr0(vcpu, cr0); | |
ad312c7c | 322 | vcpu->arch.cr0 = cr0; |
a03490ed | 323 | |
a03490ed | 324 | kvm_mmu_reset_context(vcpu); |
a03490ed CO |
325 | return; |
326 | } | |
2d3ad1f4 | 327 | EXPORT_SYMBOL_GPL(kvm_set_cr0); |
a03490ed | 328 | |
2d3ad1f4 | 329 | void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) |
a03490ed | 330 | { |
2d3ad1f4 | 331 | kvm_set_cr0(vcpu, (vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f)); |
2714d1d3 FEL |
332 | KVMTRACE_1D(LMSW, vcpu, |
333 | (u32)((vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f)), | |
334 | handler); | |
a03490ed | 335 | } |
2d3ad1f4 | 336 | EXPORT_SYMBOL_GPL(kvm_lmsw); |
a03490ed | 337 | |
2d3ad1f4 | 338 | void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
a03490ed | 339 | { |
a2edf57f AK |
340 | unsigned long old_cr4 = vcpu->arch.cr4; |
341 | unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE; | |
342 | ||
a03490ed CO |
343 | if (cr4 & CR4_RESERVED_BITS) { |
344 | printk(KERN_DEBUG "set_cr4: #GP, reserved bits\n"); | |
c1a5d4f9 | 345 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
346 | return; |
347 | } | |
348 | ||
349 | if (is_long_mode(vcpu)) { | |
350 | if (!(cr4 & X86_CR4_PAE)) { | |
351 | printk(KERN_DEBUG "set_cr4: #GP, clearing PAE while " | |
352 | "in long mode\n"); | |
c1a5d4f9 | 353 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
354 | return; |
355 | } | |
a2edf57f AK |
356 | } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) |
357 | && ((cr4 ^ old_cr4) & pdptr_bits) | |
ad312c7c | 358 | && !load_pdptrs(vcpu, vcpu->arch.cr3)) { |
a03490ed | 359 | printk(KERN_DEBUG "set_cr4: #GP, pdptrs reserved bits\n"); |
c1a5d4f9 | 360 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
361 | return; |
362 | } | |
363 | ||
364 | if (cr4 & X86_CR4_VMXE) { | |
365 | printk(KERN_DEBUG "set_cr4: #GP, setting VMXE\n"); | |
c1a5d4f9 | 366 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
367 | return; |
368 | } | |
369 | kvm_x86_ops->set_cr4(vcpu, cr4); | |
ad312c7c | 370 | vcpu->arch.cr4 = cr4; |
5a41accd | 371 | vcpu->arch.mmu.base_role.cr4_pge = (cr4 & X86_CR4_PGE) && !tdp_enabled; |
a03490ed | 372 | kvm_mmu_reset_context(vcpu); |
a03490ed | 373 | } |
2d3ad1f4 | 374 | EXPORT_SYMBOL_GPL(kvm_set_cr4); |
a03490ed | 375 | |
2d3ad1f4 | 376 | void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) |
a03490ed | 377 | { |
ad312c7c | 378 | if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) { |
0ba73cda | 379 | kvm_mmu_sync_roots(vcpu); |
d835dfec AK |
380 | kvm_mmu_flush_tlb(vcpu); |
381 | return; | |
382 | } | |
383 | ||
a03490ed CO |
384 | if (is_long_mode(vcpu)) { |
385 | if (cr3 & CR3_L_MODE_RESERVED_BITS) { | |
386 | printk(KERN_DEBUG "set_cr3: #GP, reserved bits\n"); | |
c1a5d4f9 | 387 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
388 | return; |
389 | } | |
390 | } else { | |
391 | if (is_pae(vcpu)) { | |
392 | if (cr3 & CR3_PAE_RESERVED_BITS) { | |
393 | printk(KERN_DEBUG | |
394 | "set_cr3: #GP, reserved bits\n"); | |
c1a5d4f9 | 395 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
396 | return; |
397 | } | |
398 | if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) { | |
399 | printk(KERN_DEBUG "set_cr3: #GP, pdptrs " | |
400 | "reserved bits\n"); | |
c1a5d4f9 | 401 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
402 | return; |
403 | } | |
404 | } | |
405 | /* | |
406 | * We don't check reserved bits in nonpae mode, because | |
407 | * this isn't enforced, and VMware depends on this. | |
408 | */ | |
409 | } | |
410 | ||
a03490ed CO |
411 | /* |
412 | * Does the new cr3 value map to physical memory? (Note, we | |
413 | * catch an invalid cr3 even in real-mode, because it would | |
414 | * cause trouble later on when we turn on paging anyway.) | |
415 | * | |
416 | * A real CPU would silently accept an invalid cr3 and would | |
417 | * attempt to use it - with largely undefined (and often hard | |
418 | * to debug) behavior on the guest side. | |
419 | */ | |
420 | if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT))) | |
c1a5d4f9 | 421 | kvm_inject_gp(vcpu, 0); |
a03490ed | 422 | else { |
ad312c7c ZX |
423 | vcpu->arch.cr3 = cr3; |
424 | vcpu->arch.mmu.new_cr3(vcpu); | |
a03490ed | 425 | } |
a03490ed | 426 | } |
2d3ad1f4 | 427 | EXPORT_SYMBOL_GPL(kvm_set_cr3); |
a03490ed | 428 | |
2d3ad1f4 | 429 | void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) |
a03490ed CO |
430 | { |
431 | if (cr8 & CR8_RESERVED_BITS) { | |
432 | printk(KERN_DEBUG "set_cr8: #GP, reserved bits 0x%lx\n", cr8); | |
c1a5d4f9 | 433 | kvm_inject_gp(vcpu, 0); |
a03490ed CO |
434 | return; |
435 | } | |
436 | if (irqchip_in_kernel(vcpu->kvm)) | |
437 | kvm_lapic_set_tpr(vcpu, cr8); | |
438 | else | |
ad312c7c | 439 | vcpu->arch.cr8 = cr8; |
a03490ed | 440 | } |
2d3ad1f4 | 441 | EXPORT_SYMBOL_GPL(kvm_set_cr8); |
a03490ed | 442 | |
2d3ad1f4 | 443 | unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) |
a03490ed CO |
444 | { |
445 | if (irqchip_in_kernel(vcpu->kvm)) | |
446 | return kvm_lapic_get_cr8(vcpu); | |
447 | else | |
ad312c7c | 448 | return vcpu->arch.cr8; |
a03490ed | 449 | } |
2d3ad1f4 | 450 | EXPORT_SYMBOL_GPL(kvm_get_cr8); |
a03490ed | 451 | |
d8017474 AG |
452 | static inline u32 bit(int bitno) |
453 | { | |
454 | return 1 << (bitno & 31); | |
455 | } | |
456 | ||
043405e1 CO |
457 | /* |
458 | * List of msr numbers which we expose to userspace through KVM_GET_MSRS | |
459 | * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. | |
460 | * | |
461 | * This list is modified at module load time to reflect the | |
462 | * capabilities of the host cpu. | |
463 | */ | |
464 | static u32 msrs_to_save[] = { | |
465 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, | |
466 | MSR_K6_STAR, | |
467 | #ifdef CONFIG_X86_64 | |
468 | MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, | |
469 | #endif | |
18068523 | 470 | MSR_IA32_TIME_STAMP_COUNTER, MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, |
b286d5d8 | 471 | MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA |
043405e1 CO |
472 | }; |
473 | ||
474 | static unsigned num_msrs_to_save; | |
475 | ||
476 | static u32 emulated_msrs[] = { | |
477 | MSR_IA32_MISC_ENABLE, | |
478 | }; | |
479 | ||
15c4a640 CO |
480 | static void set_efer(struct kvm_vcpu *vcpu, u64 efer) |
481 | { | |
f2b4b7dd | 482 | if (efer & efer_reserved_bits) { |
15c4a640 CO |
483 | printk(KERN_DEBUG "set_efer: 0x%llx #GP, reserved bits\n", |
484 | efer); | |
c1a5d4f9 | 485 | kvm_inject_gp(vcpu, 0); |
15c4a640 CO |
486 | return; |
487 | } | |
488 | ||
489 | if (is_paging(vcpu) | |
ad312c7c | 490 | && (vcpu->arch.shadow_efer & EFER_LME) != (efer & EFER_LME)) { |
15c4a640 | 491 | printk(KERN_DEBUG "set_efer: #GP, change LME while paging\n"); |
c1a5d4f9 | 492 | kvm_inject_gp(vcpu, 0); |
15c4a640 CO |
493 | return; |
494 | } | |
495 | ||
1b2fd70c AG |
496 | if (efer & EFER_FFXSR) { |
497 | struct kvm_cpuid_entry2 *feat; | |
498 | ||
499 | feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); | |
500 | if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) { | |
501 | printk(KERN_DEBUG "set_efer: #GP, enable FFXSR w/o CPUID capability\n"); | |
502 | kvm_inject_gp(vcpu, 0); | |
503 | return; | |
504 | } | |
505 | } | |
506 | ||
d8017474 AG |
507 | if (efer & EFER_SVME) { |
508 | struct kvm_cpuid_entry2 *feat; | |
509 | ||
510 | feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); | |
511 | if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) { | |
512 | printk(KERN_DEBUG "set_efer: #GP, enable SVM w/o SVM\n"); | |
513 | kvm_inject_gp(vcpu, 0); | |
514 | return; | |
515 | } | |
516 | } | |
517 | ||
15c4a640 CO |
518 | kvm_x86_ops->set_efer(vcpu, efer); |
519 | ||
520 | efer &= ~EFER_LMA; | |
ad312c7c | 521 | efer |= vcpu->arch.shadow_efer & EFER_LMA; |
15c4a640 | 522 | |
ad312c7c | 523 | vcpu->arch.shadow_efer = efer; |
9645bb56 AK |
524 | |
525 | vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled; | |
526 | kvm_mmu_reset_context(vcpu); | |
15c4a640 CO |
527 | } |
528 | ||
f2b4b7dd JR |
529 | void kvm_enable_efer_bits(u64 mask) |
530 | { | |
531 | efer_reserved_bits &= ~mask; | |
532 | } | |
533 | EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); | |
534 | ||
535 | ||
15c4a640 CO |
536 | /* |
537 | * Writes msr value into into the appropriate "register". | |
538 | * Returns 0 on success, non-0 otherwise. | |
539 | * Assumes vcpu_load() was already called. | |
540 | */ | |
541 | int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data) | |
542 | { | |
543 | return kvm_x86_ops->set_msr(vcpu, msr_index, data); | |
544 | } | |
545 | ||
313a3dc7 CO |
546 | /* |
547 | * Adapt set_msr() to msr_io()'s calling convention | |
548 | */ | |
549 | static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) | |
550 | { | |
551 | return kvm_set_msr(vcpu, index, *data); | |
552 | } | |
553 | ||
18068523 GOC |
554 | static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock) |
555 | { | |
556 | static int version; | |
50d0a0f9 GH |
557 | struct pvclock_wall_clock wc; |
558 | struct timespec now, sys, boot; | |
18068523 GOC |
559 | |
560 | if (!wall_clock) | |
561 | return; | |
562 | ||
563 | version++; | |
564 | ||
18068523 GOC |
565 | kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); |
566 | ||
50d0a0f9 GH |
567 | /* |
568 | * The guest calculates current wall clock time by adding | |
569 | * system time (updated by kvm_write_guest_time below) to the | |
570 | * wall clock specified here. guest system time equals host | |
571 | * system time for us, thus we must fill in host boot time here. | |
572 | */ | |
573 | now = current_kernel_time(); | |
574 | ktime_get_ts(&sys); | |
575 | boot = ns_to_timespec(timespec_to_ns(&now) - timespec_to_ns(&sys)); | |
576 | ||
577 | wc.sec = boot.tv_sec; | |
578 | wc.nsec = boot.tv_nsec; | |
579 | wc.version = version; | |
18068523 GOC |
580 | |
581 | kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); | |
582 | ||
583 | version++; | |
584 | kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); | |
18068523 GOC |
585 | } |
586 | ||
50d0a0f9 GH |
587 | static uint32_t div_frac(uint32_t dividend, uint32_t divisor) |
588 | { | |
589 | uint32_t quotient, remainder; | |
590 | ||
591 | /* Don't try to replace with do_div(), this one calculates | |
592 | * "(dividend << 32) / divisor" */ | |
593 | __asm__ ( "divl %4" | |
594 | : "=a" (quotient), "=d" (remainder) | |
595 | : "0" (0), "1" (dividend), "r" (divisor) ); | |
596 | return quotient; | |
597 | } | |
598 | ||
599 | static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock) | |
600 | { | |
601 | uint64_t nsecs = 1000000000LL; | |
602 | int32_t shift = 0; | |
603 | uint64_t tps64; | |
604 | uint32_t tps32; | |
605 | ||
606 | tps64 = tsc_khz * 1000LL; | |
607 | while (tps64 > nsecs*2) { | |
608 | tps64 >>= 1; | |
609 | shift--; | |
610 | } | |
611 | ||
612 | tps32 = (uint32_t)tps64; | |
613 | while (tps32 <= (uint32_t)nsecs) { | |
614 | tps32 <<= 1; | |
615 | shift++; | |
616 | } | |
617 | ||
618 | hv_clock->tsc_shift = shift; | |
619 | hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32); | |
620 | ||
621 | pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n", | |
80a914dc | 622 | __func__, tsc_khz, hv_clock->tsc_shift, |
50d0a0f9 GH |
623 | hv_clock->tsc_to_system_mul); |
624 | } | |
625 | ||
c8076604 GH |
626 | static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); |
627 | ||
18068523 GOC |
628 | static void kvm_write_guest_time(struct kvm_vcpu *v) |
629 | { | |
630 | struct timespec ts; | |
631 | unsigned long flags; | |
632 | struct kvm_vcpu_arch *vcpu = &v->arch; | |
633 | void *shared_kaddr; | |
463656c0 | 634 | unsigned long this_tsc_khz; |
18068523 GOC |
635 | |
636 | if ((!vcpu->time_page)) | |
637 | return; | |
638 | ||
463656c0 AK |
639 | this_tsc_khz = get_cpu_var(cpu_tsc_khz); |
640 | if (unlikely(vcpu->hv_clock_tsc_khz != this_tsc_khz)) { | |
641 | kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock); | |
642 | vcpu->hv_clock_tsc_khz = this_tsc_khz; | |
50d0a0f9 | 643 | } |
463656c0 | 644 | put_cpu_var(cpu_tsc_khz); |
50d0a0f9 | 645 | |
18068523 GOC |
646 | /* Keep irq disabled to prevent changes to the clock */ |
647 | local_irq_save(flags); | |
648 | kvm_get_msr(v, MSR_IA32_TIME_STAMP_COUNTER, | |
649 | &vcpu->hv_clock.tsc_timestamp); | |
650 | ktime_get_ts(&ts); | |
651 | local_irq_restore(flags); | |
652 | ||
653 | /* With all the info we got, fill in the values */ | |
654 | ||
655 | vcpu->hv_clock.system_time = ts.tv_nsec + | |
656 | (NSEC_PER_SEC * (u64)ts.tv_sec); | |
657 | /* | |
658 | * The interface expects us to write an even number signaling that the | |
659 | * update is finished. Since the guest won't see the intermediate | |
50d0a0f9 | 660 | * state, we just increase by 2 at the end. |
18068523 | 661 | */ |
50d0a0f9 | 662 | vcpu->hv_clock.version += 2; |
18068523 GOC |
663 | |
664 | shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0); | |
665 | ||
666 | memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock, | |
50d0a0f9 | 667 | sizeof(vcpu->hv_clock)); |
18068523 GOC |
668 | |
669 | kunmap_atomic(shared_kaddr, KM_USER0); | |
670 | ||
671 | mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT); | |
672 | } | |
673 | ||
c8076604 GH |
674 | static int kvm_request_guest_time_update(struct kvm_vcpu *v) |
675 | { | |
676 | struct kvm_vcpu_arch *vcpu = &v->arch; | |
677 | ||
678 | if (!vcpu->time_page) | |
679 | return 0; | |
680 | set_bit(KVM_REQ_KVMCLOCK_UPDATE, &v->requests); | |
681 | return 1; | |
682 | } | |
683 | ||
9ba075a6 AK |
684 | static bool msr_mtrr_valid(unsigned msr) |
685 | { | |
686 | switch (msr) { | |
687 | case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1: | |
688 | case MSR_MTRRfix64K_00000: | |
689 | case MSR_MTRRfix16K_80000: | |
690 | case MSR_MTRRfix16K_A0000: | |
691 | case MSR_MTRRfix4K_C0000: | |
692 | case MSR_MTRRfix4K_C8000: | |
693 | case MSR_MTRRfix4K_D0000: | |
694 | case MSR_MTRRfix4K_D8000: | |
695 | case MSR_MTRRfix4K_E0000: | |
696 | case MSR_MTRRfix4K_E8000: | |
697 | case MSR_MTRRfix4K_F0000: | |
698 | case MSR_MTRRfix4K_F8000: | |
699 | case MSR_MTRRdefType: | |
700 | case MSR_IA32_CR_PAT: | |
701 | return true; | |
702 | case 0x2f8: | |
703 | return true; | |
704 | } | |
705 | return false; | |
706 | } | |
707 | ||
708 | static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data) | |
709 | { | |
0bed3b56 SY |
710 | u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges; |
711 | ||
9ba075a6 AK |
712 | if (!msr_mtrr_valid(msr)) |
713 | return 1; | |
714 | ||
0bed3b56 SY |
715 | if (msr == MSR_MTRRdefType) { |
716 | vcpu->arch.mtrr_state.def_type = data; | |
717 | vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10; | |
718 | } else if (msr == MSR_MTRRfix64K_00000) | |
719 | p[0] = data; | |
720 | else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000) | |
721 | p[1 + msr - MSR_MTRRfix16K_80000] = data; | |
722 | else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000) | |
723 | p[3 + msr - MSR_MTRRfix4K_C0000] = data; | |
724 | else if (msr == MSR_IA32_CR_PAT) | |
725 | vcpu->arch.pat = data; | |
726 | else { /* Variable MTRRs */ | |
727 | int idx, is_mtrr_mask; | |
728 | u64 *pt; | |
729 | ||
730 | idx = (msr - 0x200) / 2; | |
731 | is_mtrr_mask = msr - 0x200 - 2 * idx; | |
732 | if (!is_mtrr_mask) | |
733 | pt = | |
734 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo; | |
735 | else | |
736 | pt = | |
737 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo; | |
738 | *pt = data; | |
739 | } | |
740 | ||
741 | kvm_mmu_reset_context(vcpu); | |
9ba075a6 AK |
742 | return 0; |
743 | } | |
15c4a640 CO |
744 | |
745 | int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data) | |
746 | { | |
747 | switch (msr) { | |
15c4a640 CO |
748 | case MSR_EFER: |
749 | set_efer(vcpu, data); | |
750 | break; | |
15c4a640 CO |
751 | case MSR_IA32_MC0_STATUS: |
752 | pr_unimpl(vcpu, "%s: MSR_IA32_MC0_STATUS 0x%llx, nop\n", | |
b8688d51 | 753 | __func__, data); |
15c4a640 CO |
754 | break; |
755 | case MSR_IA32_MCG_STATUS: | |
756 | pr_unimpl(vcpu, "%s: MSR_IA32_MCG_STATUS 0x%llx, nop\n", | |
b8688d51 | 757 | __func__, data); |
15c4a640 | 758 | break; |
c7ac679c JR |
759 | case MSR_IA32_MCG_CTL: |
760 | pr_unimpl(vcpu, "%s: MSR_IA32_MCG_CTL 0x%llx, nop\n", | |
b8688d51 | 761 | __func__, data); |
c7ac679c | 762 | break; |
b5e2fec0 AG |
763 | case MSR_IA32_DEBUGCTLMSR: |
764 | if (!data) { | |
765 | /* We support the non-activated case already */ | |
766 | break; | |
767 | } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) { | |
768 | /* Values other than LBR and BTF are vendor-specific, | |
769 | thus reserved and should throw a #GP */ | |
770 | return 1; | |
771 | } | |
772 | pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n", | |
773 | __func__, data); | |
774 | break; | |
15c4a640 CO |
775 | case MSR_IA32_UCODE_REV: |
776 | case MSR_IA32_UCODE_WRITE: | |
61a6bd67 | 777 | case MSR_VM_HSAVE_PA: |
15c4a640 | 778 | break; |
9ba075a6 AK |
779 | case 0x200 ... 0x2ff: |
780 | return set_msr_mtrr(vcpu, msr, data); | |
15c4a640 CO |
781 | case MSR_IA32_APICBASE: |
782 | kvm_set_apic_base(vcpu, data); | |
783 | break; | |
784 | case MSR_IA32_MISC_ENABLE: | |
ad312c7c | 785 | vcpu->arch.ia32_misc_enable_msr = data; |
15c4a640 | 786 | break; |
18068523 GOC |
787 | case MSR_KVM_WALL_CLOCK: |
788 | vcpu->kvm->arch.wall_clock = data; | |
789 | kvm_write_wall_clock(vcpu->kvm, data); | |
790 | break; | |
791 | case MSR_KVM_SYSTEM_TIME: { | |
792 | if (vcpu->arch.time_page) { | |
793 | kvm_release_page_dirty(vcpu->arch.time_page); | |
794 | vcpu->arch.time_page = NULL; | |
795 | } | |
796 | ||
797 | vcpu->arch.time = data; | |
798 | ||
799 | /* we verify if the enable bit is set... */ | |
800 | if (!(data & 1)) | |
801 | break; | |
802 | ||
803 | /* ...but clean it before doing the actual write */ | |
804 | vcpu->arch.time_offset = data & ~(PAGE_MASK | 1); | |
805 | ||
18068523 GOC |
806 | vcpu->arch.time_page = |
807 | gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT); | |
18068523 GOC |
808 | |
809 | if (is_error_page(vcpu->arch.time_page)) { | |
810 | kvm_release_page_clean(vcpu->arch.time_page); | |
811 | vcpu->arch.time_page = NULL; | |
812 | } | |
813 | ||
c8076604 | 814 | kvm_request_guest_time_update(vcpu); |
18068523 GOC |
815 | break; |
816 | } | |
15c4a640 | 817 | default: |
565f1fbd | 818 | pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n", msr, data); |
15c4a640 CO |
819 | return 1; |
820 | } | |
821 | return 0; | |
822 | } | |
823 | EXPORT_SYMBOL_GPL(kvm_set_msr_common); | |
824 | ||
825 | ||
826 | /* | |
827 | * Reads an msr value (of 'msr_index') into 'pdata'. | |
828 | * Returns 0 on success, non-0 otherwise. | |
829 | * Assumes vcpu_load() was already called. | |
830 | */ | |
831 | int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata) | |
832 | { | |
833 | return kvm_x86_ops->get_msr(vcpu, msr_index, pdata); | |
834 | } | |
835 | ||
9ba075a6 AK |
836 | static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) |
837 | { | |
0bed3b56 SY |
838 | u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges; |
839 | ||
9ba075a6 AK |
840 | if (!msr_mtrr_valid(msr)) |
841 | return 1; | |
842 | ||
0bed3b56 SY |
843 | if (msr == MSR_MTRRdefType) |
844 | *pdata = vcpu->arch.mtrr_state.def_type + | |
845 | (vcpu->arch.mtrr_state.enabled << 10); | |
846 | else if (msr == MSR_MTRRfix64K_00000) | |
847 | *pdata = p[0]; | |
848 | else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000) | |
849 | *pdata = p[1 + msr - MSR_MTRRfix16K_80000]; | |
850 | else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000) | |
851 | *pdata = p[3 + msr - MSR_MTRRfix4K_C0000]; | |
852 | else if (msr == MSR_IA32_CR_PAT) | |
853 | *pdata = vcpu->arch.pat; | |
854 | else { /* Variable MTRRs */ | |
855 | int idx, is_mtrr_mask; | |
856 | u64 *pt; | |
857 | ||
858 | idx = (msr - 0x200) / 2; | |
859 | is_mtrr_mask = msr - 0x200 - 2 * idx; | |
860 | if (!is_mtrr_mask) | |
861 | pt = | |
862 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo; | |
863 | else | |
864 | pt = | |
865 | (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo; | |
866 | *pdata = *pt; | |
867 | } | |
868 | ||
9ba075a6 AK |
869 | return 0; |
870 | } | |
871 | ||
15c4a640 CO |
872 | int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata) |
873 | { | |
874 | u64 data; | |
875 | ||
876 | switch (msr) { | |
877 | case 0xc0010010: /* SYSCFG */ | |
878 | case 0xc0010015: /* HWCR */ | |
879 | case MSR_IA32_PLATFORM_ID: | |
880 | case MSR_IA32_P5_MC_ADDR: | |
881 | case MSR_IA32_P5_MC_TYPE: | |
882 | case MSR_IA32_MC0_CTL: | |
883 | case MSR_IA32_MCG_STATUS: | |
884 | case MSR_IA32_MCG_CAP: | |
c7ac679c | 885 | case MSR_IA32_MCG_CTL: |
15c4a640 CO |
886 | case MSR_IA32_MC0_MISC: |
887 | case MSR_IA32_MC0_MISC+4: | |
888 | case MSR_IA32_MC0_MISC+8: | |
889 | case MSR_IA32_MC0_MISC+12: | |
890 | case MSR_IA32_MC0_MISC+16: | |
a89c1ad2 | 891 | case MSR_IA32_MC0_MISC+20: |
15c4a640 | 892 | case MSR_IA32_UCODE_REV: |
15c4a640 | 893 | case MSR_IA32_EBL_CR_POWERON: |
b5e2fec0 AG |
894 | case MSR_IA32_DEBUGCTLMSR: |
895 | case MSR_IA32_LASTBRANCHFROMIP: | |
896 | case MSR_IA32_LASTBRANCHTOIP: | |
897 | case MSR_IA32_LASTINTFROMIP: | |
898 | case MSR_IA32_LASTINTTOIP: | |
61a6bd67 | 899 | case MSR_VM_HSAVE_PA: |
7fe29e0f AS |
900 | case MSR_P6_EVNTSEL0: |
901 | case MSR_P6_EVNTSEL1: | |
15c4a640 CO |
902 | data = 0; |
903 | break; | |
9ba075a6 AK |
904 | case MSR_MTRRcap: |
905 | data = 0x500 | KVM_NR_VAR_MTRR; | |
906 | break; | |
907 | case 0x200 ... 0x2ff: | |
908 | return get_msr_mtrr(vcpu, msr, pdata); | |
15c4a640 CO |
909 | case 0xcd: /* fsb frequency */ |
910 | data = 3; | |
911 | break; | |
912 | case MSR_IA32_APICBASE: | |
913 | data = kvm_get_apic_base(vcpu); | |
914 | break; | |
915 | case MSR_IA32_MISC_ENABLE: | |
ad312c7c | 916 | data = vcpu->arch.ia32_misc_enable_msr; |
15c4a640 | 917 | break; |
847f0ad8 AG |
918 | case MSR_IA32_PERF_STATUS: |
919 | /* TSC increment by tick */ | |
920 | data = 1000ULL; | |
921 | /* CPU multiplier */ | |
922 | data |= (((uint64_t)4ULL) << 40); | |
923 | break; | |
15c4a640 | 924 | case MSR_EFER: |
ad312c7c | 925 | data = vcpu->arch.shadow_efer; |
15c4a640 | 926 | break; |
18068523 GOC |
927 | case MSR_KVM_WALL_CLOCK: |
928 | data = vcpu->kvm->arch.wall_clock; | |
929 | break; | |
930 | case MSR_KVM_SYSTEM_TIME: | |
931 | data = vcpu->arch.time; | |
932 | break; | |
15c4a640 CO |
933 | default: |
934 | pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr); | |
935 | return 1; | |
936 | } | |
937 | *pdata = data; | |
938 | return 0; | |
939 | } | |
940 | EXPORT_SYMBOL_GPL(kvm_get_msr_common); | |
941 | ||
313a3dc7 CO |
942 | /* |
943 | * Read or write a bunch of msrs. All parameters are kernel addresses. | |
944 | * | |
945 | * @return number of msrs set successfully. | |
946 | */ | |
947 | static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, | |
948 | struct kvm_msr_entry *entries, | |
949 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
950 | unsigned index, u64 *data)) | |
951 | { | |
952 | int i; | |
953 | ||
954 | vcpu_load(vcpu); | |
955 | ||
3200f405 | 956 | down_read(&vcpu->kvm->slots_lock); |
313a3dc7 CO |
957 | for (i = 0; i < msrs->nmsrs; ++i) |
958 | if (do_msr(vcpu, entries[i].index, &entries[i].data)) | |
959 | break; | |
3200f405 | 960 | up_read(&vcpu->kvm->slots_lock); |
313a3dc7 CO |
961 | |
962 | vcpu_put(vcpu); | |
963 | ||
964 | return i; | |
965 | } | |
966 | ||
967 | /* | |
968 | * Read or write a bunch of msrs. Parameters are user addresses. | |
969 | * | |
970 | * @return number of msrs set successfully. | |
971 | */ | |
972 | static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, | |
973 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
974 | unsigned index, u64 *data), | |
975 | int writeback) | |
976 | { | |
977 | struct kvm_msrs msrs; | |
978 | struct kvm_msr_entry *entries; | |
979 | int r, n; | |
980 | unsigned size; | |
981 | ||
982 | r = -EFAULT; | |
983 | if (copy_from_user(&msrs, user_msrs, sizeof msrs)) | |
984 | goto out; | |
985 | ||
986 | r = -E2BIG; | |
987 | if (msrs.nmsrs >= MAX_IO_MSRS) | |
988 | goto out; | |
989 | ||
990 | r = -ENOMEM; | |
991 | size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; | |
992 | entries = vmalloc(size); | |
993 | if (!entries) | |
994 | goto out; | |
995 | ||
996 | r = -EFAULT; | |
997 | if (copy_from_user(entries, user_msrs->entries, size)) | |
998 | goto out_free; | |
999 | ||
1000 | r = n = __msr_io(vcpu, &msrs, entries, do_msr); | |
1001 | if (r < 0) | |
1002 | goto out_free; | |
1003 | ||
1004 | r = -EFAULT; | |
1005 | if (writeback && copy_to_user(user_msrs->entries, entries, size)) | |
1006 | goto out_free; | |
1007 | ||
1008 | r = n; | |
1009 | ||
1010 | out_free: | |
1011 | vfree(entries); | |
1012 | out: | |
1013 | return r; | |
1014 | } | |
1015 | ||
018d00d2 ZX |
1016 | int kvm_dev_ioctl_check_extension(long ext) |
1017 | { | |
1018 | int r; | |
1019 | ||
1020 | switch (ext) { | |
1021 | case KVM_CAP_IRQCHIP: | |
1022 | case KVM_CAP_HLT: | |
1023 | case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: | |
018d00d2 | 1024 | case KVM_CAP_SET_TSS_ADDR: |
07716717 | 1025 | case KVM_CAP_EXT_CPUID: |
c8076604 | 1026 | case KVM_CAP_CLOCKSOURCE: |
7837699f | 1027 | case KVM_CAP_PIT: |
a28e4f5a | 1028 | case KVM_CAP_NOP_IO_DELAY: |
62d9f0db | 1029 | case KVM_CAP_MP_STATE: |
ed848624 | 1030 | case KVM_CAP_SYNC_MMU: |
52d939a0 | 1031 | case KVM_CAP_REINJECT_CONTROL: |
4925663a | 1032 | case KVM_CAP_IRQ_INJECT_STATUS: |
e56d532f | 1033 | case KVM_CAP_ASSIGN_DEV_IRQ: |
018d00d2 ZX |
1034 | r = 1; |
1035 | break; | |
542472b5 LV |
1036 | case KVM_CAP_COALESCED_MMIO: |
1037 | r = KVM_COALESCED_MMIO_PAGE_OFFSET; | |
1038 | break; | |
774ead3a AK |
1039 | case KVM_CAP_VAPIC: |
1040 | r = !kvm_x86_ops->cpu_has_accelerated_tpr(); | |
1041 | break; | |
f725230a AK |
1042 | case KVM_CAP_NR_VCPUS: |
1043 | r = KVM_MAX_VCPUS; | |
1044 | break; | |
a988b910 AK |
1045 | case KVM_CAP_NR_MEMSLOTS: |
1046 | r = KVM_MEMORY_SLOTS; | |
1047 | break; | |
2f333bcb MT |
1048 | case KVM_CAP_PV_MMU: |
1049 | r = !tdp_enabled; | |
1050 | break; | |
62c476c7 | 1051 | case KVM_CAP_IOMMU: |
19de40a8 | 1052 | r = iommu_found(); |
62c476c7 | 1053 | break; |
018d00d2 ZX |
1054 | default: |
1055 | r = 0; | |
1056 | break; | |
1057 | } | |
1058 | return r; | |
1059 | ||
1060 | } | |
1061 | ||
043405e1 CO |
1062 | long kvm_arch_dev_ioctl(struct file *filp, |
1063 | unsigned int ioctl, unsigned long arg) | |
1064 | { | |
1065 | void __user *argp = (void __user *)arg; | |
1066 | long r; | |
1067 | ||
1068 | switch (ioctl) { | |
1069 | case KVM_GET_MSR_INDEX_LIST: { | |
1070 | struct kvm_msr_list __user *user_msr_list = argp; | |
1071 | struct kvm_msr_list msr_list; | |
1072 | unsigned n; | |
1073 | ||
1074 | r = -EFAULT; | |
1075 | if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list)) | |
1076 | goto out; | |
1077 | n = msr_list.nmsrs; | |
1078 | msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs); | |
1079 | if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list)) | |
1080 | goto out; | |
1081 | r = -E2BIG; | |
1082 | if (n < num_msrs_to_save) | |
1083 | goto out; | |
1084 | r = -EFAULT; | |
1085 | if (copy_to_user(user_msr_list->indices, &msrs_to_save, | |
1086 | num_msrs_to_save * sizeof(u32))) | |
1087 | goto out; | |
1088 | if (copy_to_user(user_msr_list->indices | |
1089 | + num_msrs_to_save * sizeof(u32), | |
1090 | &emulated_msrs, | |
1091 | ARRAY_SIZE(emulated_msrs) * sizeof(u32))) | |
1092 | goto out; | |
1093 | r = 0; | |
1094 | break; | |
1095 | } | |
674eea0f AK |
1096 | case KVM_GET_SUPPORTED_CPUID: { |
1097 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
1098 | struct kvm_cpuid2 cpuid; | |
1099 | ||
1100 | r = -EFAULT; | |
1101 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
1102 | goto out; | |
1103 | r = kvm_dev_ioctl_get_supported_cpuid(&cpuid, | |
19355475 | 1104 | cpuid_arg->entries); |
674eea0f AK |
1105 | if (r) |
1106 | goto out; | |
1107 | ||
1108 | r = -EFAULT; | |
1109 | if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) | |
1110 | goto out; | |
1111 | r = 0; | |
1112 | break; | |
1113 | } | |
043405e1 CO |
1114 | default: |
1115 | r = -EINVAL; | |
1116 | } | |
1117 | out: | |
1118 | return r; | |
1119 | } | |
1120 | ||
313a3dc7 CO |
1121 | void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
1122 | { | |
1123 | kvm_x86_ops->vcpu_load(vcpu, cpu); | |
c8076604 | 1124 | kvm_request_guest_time_update(vcpu); |
313a3dc7 CO |
1125 | } |
1126 | ||
1127 | void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) | |
1128 | { | |
1129 | kvm_x86_ops->vcpu_put(vcpu); | |
9327fd11 | 1130 | kvm_put_guest_fpu(vcpu); |
313a3dc7 CO |
1131 | } |
1132 | ||
07716717 | 1133 | static int is_efer_nx(void) |
313a3dc7 | 1134 | { |
e286e86e | 1135 | unsigned long long efer = 0; |
313a3dc7 | 1136 | |
e286e86e | 1137 | rdmsrl_safe(MSR_EFER, &efer); |
07716717 DK |
1138 | return efer & EFER_NX; |
1139 | } | |
1140 | ||
1141 | static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu) | |
1142 | { | |
1143 | int i; | |
1144 | struct kvm_cpuid_entry2 *e, *entry; | |
1145 | ||
313a3dc7 | 1146 | entry = NULL; |
ad312c7c ZX |
1147 | for (i = 0; i < vcpu->arch.cpuid_nent; ++i) { |
1148 | e = &vcpu->arch.cpuid_entries[i]; | |
313a3dc7 CO |
1149 | if (e->function == 0x80000001) { |
1150 | entry = e; | |
1151 | break; | |
1152 | } | |
1153 | } | |
07716717 | 1154 | if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) { |
313a3dc7 CO |
1155 | entry->edx &= ~(1 << 20); |
1156 | printk(KERN_INFO "kvm: guest NX capability removed\n"); | |
1157 | } | |
1158 | } | |
1159 | ||
07716717 | 1160 | /* when an old userspace process fills a new kernel module */ |
313a3dc7 CO |
1161 | static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu, |
1162 | struct kvm_cpuid *cpuid, | |
1163 | struct kvm_cpuid_entry __user *entries) | |
07716717 DK |
1164 | { |
1165 | int r, i; | |
1166 | struct kvm_cpuid_entry *cpuid_entries; | |
1167 | ||
1168 | r = -E2BIG; | |
1169 | if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) | |
1170 | goto out; | |
1171 | r = -ENOMEM; | |
1172 | cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent); | |
1173 | if (!cpuid_entries) | |
1174 | goto out; | |
1175 | r = -EFAULT; | |
1176 | if (copy_from_user(cpuid_entries, entries, | |
1177 | cpuid->nent * sizeof(struct kvm_cpuid_entry))) | |
1178 | goto out_free; | |
1179 | for (i = 0; i < cpuid->nent; i++) { | |
ad312c7c ZX |
1180 | vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function; |
1181 | vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax; | |
1182 | vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx; | |
1183 | vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx; | |
1184 | vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx; | |
1185 | vcpu->arch.cpuid_entries[i].index = 0; | |
1186 | vcpu->arch.cpuid_entries[i].flags = 0; | |
1187 | vcpu->arch.cpuid_entries[i].padding[0] = 0; | |
1188 | vcpu->arch.cpuid_entries[i].padding[1] = 0; | |
1189 | vcpu->arch.cpuid_entries[i].padding[2] = 0; | |
1190 | } | |
1191 | vcpu->arch.cpuid_nent = cpuid->nent; | |
07716717 DK |
1192 | cpuid_fix_nx_cap(vcpu); |
1193 | r = 0; | |
1194 | ||
1195 | out_free: | |
1196 | vfree(cpuid_entries); | |
1197 | out: | |
1198 | return r; | |
1199 | } | |
1200 | ||
1201 | static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu, | |
19355475 AS |
1202 | struct kvm_cpuid2 *cpuid, |
1203 | struct kvm_cpuid_entry2 __user *entries) | |
313a3dc7 CO |
1204 | { |
1205 | int r; | |
1206 | ||
1207 | r = -E2BIG; | |
1208 | if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) | |
1209 | goto out; | |
1210 | r = -EFAULT; | |
ad312c7c | 1211 | if (copy_from_user(&vcpu->arch.cpuid_entries, entries, |
07716717 | 1212 | cpuid->nent * sizeof(struct kvm_cpuid_entry2))) |
313a3dc7 | 1213 | goto out; |
ad312c7c | 1214 | vcpu->arch.cpuid_nent = cpuid->nent; |
313a3dc7 CO |
1215 | return 0; |
1216 | ||
1217 | out: | |
1218 | return r; | |
1219 | } | |
1220 | ||
07716717 | 1221 | static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu, |
19355475 AS |
1222 | struct kvm_cpuid2 *cpuid, |
1223 | struct kvm_cpuid_entry2 __user *entries) | |
07716717 DK |
1224 | { |
1225 | int r; | |
1226 | ||
1227 | r = -E2BIG; | |
ad312c7c | 1228 | if (cpuid->nent < vcpu->arch.cpuid_nent) |
07716717 DK |
1229 | goto out; |
1230 | r = -EFAULT; | |
ad312c7c | 1231 | if (copy_to_user(entries, &vcpu->arch.cpuid_entries, |
19355475 | 1232 | vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2))) |
07716717 DK |
1233 | goto out; |
1234 | return 0; | |
1235 | ||
1236 | out: | |
ad312c7c | 1237 | cpuid->nent = vcpu->arch.cpuid_nent; |
07716717 DK |
1238 | return r; |
1239 | } | |
1240 | ||
07716717 | 1241 | static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function, |
19355475 | 1242 | u32 index) |
07716717 DK |
1243 | { |
1244 | entry->function = function; | |
1245 | entry->index = index; | |
1246 | cpuid_count(entry->function, entry->index, | |
19355475 | 1247 | &entry->eax, &entry->ebx, &entry->ecx, &entry->edx); |
07716717 DK |
1248 | entry->flags = 0; |
1249 | } | |
1250 | ||
1251 | static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function, | |
1252 | u32 index, int *nent, int maxnent) | |
1253 | { | |
1254 | const u32 kvm_supported_word0_x86_features = bit(X86_FEATURE_FPU) | | |
1255 | bit(X86_FEATURE_VME) | bit(X86_FEATURE_DE) | | |
1256 | bit(X86_FEATURE_PSE) | bit(X86_FEATURE_TSC) | | |
1257 | bit(X86_FEATURE_MSR) | bit(X86_FEATURE_PAE) | | |
1258 | bit(X86_FEATURE_CX8) | bit(X86_FEATURE_APIC) | | |
1259 | bit(X86_FEATURE_SEP) | bit(X86_FEATURE_PGE) | | |
1260 | bit(X86_FEATURE_CMOV) | bit(X86_FEATURE_PSE36) | | |
1261 | bit(X86_FEATURE_CLFLSH) | bit(X86_FEATURE_MMX) | | |
1262 | bit(X86_FEATURE_FXSR) | bit(X86_FEATURE_XMM) | | |
1263 | bit(X86_FEATURE_XMM2) | bit(X86_FEATURE_SELFSNOOP); | |
1264 | const u32 kvm_supported_word1_x86_features = bit(X86_FEATURE_FPU) | | |
1265 | bit(X86_FEATURE_VME) | bit(X86_FEATURE_DE) | | |
1266 | bit(X86_FEATURE_PSE) | bit(X86_FEATURE_TSC) | | |
1267 | bit(X86_FEATURE_MSR) | bit(X86_FEATURE_PAE) | | |
1268 | bit(X86_FEATURE_CX8) | bit(X86_FEATURE_APIC) | | |
1269 | bit(X86_FEATURE_PGE) | | |
1270 | bit(X86_FEATURE_CMOV) | bit(X86_FEATURE_PSE36) | | |
1271 | bit(X86_FEATURE_MMX) | bit(X86_FEATURE_FXSR) | | |
1272 | bit(X86_FEATURE_SYSCALL) | | |
334b8ad7 | 1273 | (is_efer_nx() ? bit(X86_FEATURE_NX) : 0) | |
07716717 DK |
1274 | #ifdef CONFIG_X86_64 |
1275 | bit(X86_FEATURE_LM) | | |
1276 | #endif | |
1b2fd70c | 1277 | bit(X86_FEATURE_FXSR_OPT) | |
07716717 DK |
1278 | bit(X86_FEATURE_MMXEXT) | |
1279 | bit(X86_FEATURE_3DNOWEXT) | | |
1280 | bit(X86_FEATURE_3DNOW); | |
1281 | const u32 kvm_supported_word3_x86_features = | |
1282 | bit(X86_FEATURE_XMM3) | bit(X86_FEATURE_CX16); | |
1283 | const u32 kvm_supported_word6_x86_features = | |
d8017474 AG |
1284 | bit(X86_FEATURE_LAHF_LM) | bit(X86_FEATURE_CMP_LEGACY) | |
1285 | bit(X86_FEATURE_SVM); | |
07716717 | 1286 | |
19355475 | 1287 | /* all calls to cpuid_count() should be made on the same cpu */ |
07716717 DK |
1288 | get_cpu(); |
1289 | do_cpuid_1_ent(entry, function, index); | |
1290 | ++*nent; | |
1291 | ||
1292 | switch (function) { | |
1293 | case 0: | |
1294 | entry->eax = min(entry->eax, (u32)0xb); | |
1295 | break; | |
1296 | case 1: | |
1297 | entry->edx &= kvm_supported_word0_x86_features; | |
1298 | entry->ecx &= kvm_supported_word3_x86_features; | |
1299 | break; | |
1300 | /* function 2 entries are STATEFUL. That is, repeated cpuid commands | |
1301 | * may return different values. This forces us to get_cpu() before | |
1302 | * issuing the first command, and also to emulate this annoying behavior | |
1303 | * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */ | |
1304 | case 2: { | |
1305 | int t, times = entry->eax & 0xff; | |
1306 | ||
1307 | entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC; | |
0fdf8e59 | 1308 | entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT; |
07716717 DK |
1309 | for (t = 1; t < times && *nent < maxnent; ++t) { |
1310 | do_cpuid_1_ent(&entry[t], function, 0); | |
1311 | entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC; | |
1312 | ++*nent; | |
1313 | } | |
1314 | break; | |
1315 | } | |
1316 | /* function 4 and 0xb have additional index. */ | |
1317 | case 4: { | |
14af3f3c | 1318 | int i, cache_type; |
07716717 DK |
1319 | |
1320 | entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; | |
1321 | /* read more entries until cache_type is zero */ | |
14af3f3c HH |
1322 | for (i = 1; *nent < maxnent; ++i) { |
1323 | cache_type = entry[i - 1].eax & 0x1f; | |
07716717 DK |
1324 | if (!cache_type) |
1325 | break; | |
14af3f3c HH |
1326 | do_cpuid_1_ent(&entry[i], function, i); |
1327 | entry[i].flags |= | |
07716717 DK |
1328 | KVM_CPUID_FLAG_SIGNIFCANT_INDEX; |
1329 | ++*nent; | |
1330 | } | |
1331 | break; | |
1332 | } | |
1333 | case 0xb: { | |
14af3f3c | 1334 | int i, level_type; |
07716717 DK |
1335 | |
1336 | entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; | |
1337 | /* read more entries until level_type is zero */ | |
14af3f3c | 1338 | for (i = 1; *nent < maxnent; ++i) { |
0853d2c1 | 1339 | level_type = entry[i - 1].ecx & 0xff00; |
07716717 DK |
1340 | if (!level_type) |
1341 | break; | |
14af3f3c HH |
1342 | do_cpuid_1_ent(&entry[i], function, i); |
1343 | entry[i].flags |= | |
07716717 DK |
1344 | KVM_CPUID_FLAG_SIGNIFCANT_INDEX; |
1345 | ++*nent; | |
1346 | } | |
1347 | break; | |
1348 | } | |
1349 | case 0x80000000: | |
1350 | entry->eax = min(entry->eax, 0x8000001a); | |
1351 | break; | |
1352 | case 0x80000001: | |
1353 | entry->edx &= kvm_supported_word1_x86_features; | |
1354 | entry->ecx &= kvm_supported_word6_x86_features; | |
1355 | break; | |
1356 | } | |
1357 | put_cpu(); | |
1358 | } | |
1359 | ||
674eea0f | 1360 | static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid, |
19355475 | 1361 | struct kvm_cpuid_entry2 __user *entries) |
07716717 DK |
1362 | { |
1363 | struct kvm_cpuid_entry2 *cpuid_entries; | |
1364 | int limit, nent = 0, r = -E2BIG; | |
1365 | u32 func; | |
1366 | ||
1367 | if (cpuid->nent < 1) | |
1368 | goto out; | |
1369 | r = -ENOMEM; | |
1370 | cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent); | |
1371 | if (!cpuid_entries) | |
1372 | goto out; | |
1373 | ||
1374 | do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent); | |
1375 | limit = cpuid_entries[0].eax; | |
1376 | for (func = 1; func <= limit && nent < cpuid->nent; ++func) | |
1377 | do_cpuid_ent(&cpuid_entries[nent], func, 0, | |
19355475 | 1378 | &nent, cpuid->nent); |
07716717 DK |
1379 | r = -E2BIG; |
1380 | if (nent >= cpuid->nent) | |
1381 | goto out_free; | |
1382 | ||
1383 | do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent); | |
1384 | limit = cpuid_entries[nent - 1].eax; | |
1385 | for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func) | |
1386 | do_cpuid_ent(&cpuid_entries[nent], func, 0, | |
19355475 | 1387 | &nent, cpuid->nent); |
07716717 DK |
1388 | r = -EFAULT; |
1389 | if (copy_to_user(entries, cpuid_entries, | |
19355475 | 1390 | nent * sizeof(struct kvm_cpuid_entry2))) |
07716717 DK |
1391 | goto out_free; |
1392 | cpuid->nent = nent; | |
1393 | r = 0; | |
1394 | ||
1395 | out_free: | |
1396 | vfree(cpuid_entries); | |
1397 | out: | |
1398 | return r; | |
1399 | } | |
1400 | ||
313a3dc7 CO |
1401 | static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, |
1402 | struct kvm_lapic_state *s) | |
1403 | { | |
1404 | vcpu_load(vcpu); | |
ad312c7c | 1405 | memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s); |
313a3dc7 CO |
1406 | vcpu_put(vcpu); |
1407 | ||
1408 | return 0; | |
1409 | } | |
1410 | ||
1411 | static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, | |
1412 | struct kvm_lapic_state *s) | |
1413 | { | |
1414 | vcpu_load(vcpu); | |
ad312c7c | 1415 | memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s); |
313a3dc7 CO |
1416 | kvm_apic_post_state_restore(vcpu); |
1417 | vcpu_put(vcpu); | |
1418 | ||
1419 | return 0; | |
1420 | } | |
1421 | ||
f77bc6a4 ZX |
1422 | static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, |
1423 | struct kvm_interrupt *irq) | |
1424 | { | |
1425 | if (irq->irq < 0 || irq->irq >= 256) | |
1426 | return -EINVAL; | |
1427 | if (irqchip_in_kernel(vcpu->kvm)) | |
1428 | return -ENXIO; | |
1429 | vcpu_load(vcpu); | |
1430 | ||
ad312c7c ZX |
1431 | set_bit(irq->irq, vcpu->arch.irq_pending); |
1432 | set_bit(irq->irq / BITS_PER_LONG, &vcpu->arch.irq_summary); | |
f77bc6a4 ZX |
1433 | |
1434 | vcpu_put(vcpu); | |
1435 | ||
1436 | return 0; | |
1437 | } | |
1438 | ||
c4abb7c9 JK |
1439 | static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) |
1440 | { | |
1441 | vcpu_load(vcpu); | |
1442 | kvm_inject_nmi(vcpu); | |
1443 | vcpu_put(vcpu); | |
1444 | ||
1445 | return 0; | |
1446 | } | |
1447 | ||
b209749f AK |
1448 | static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, |
1449 | struct kvm_tpr_access_ctl *tac) | |
1450 | { | |
1451 | if (tac->flags) | |
1452 | return -EINVAL; | |
1453 | vcpu->arch.tpr_access_reporting = !!tac->enabled; | |
1454 | return 0; | |
1455 | } | |
1456 | ||
313a3dc7 CO |
1457 | long kvm_arch_vcpu_ioctl(struct file *filp, |
1458 | unsigned int ioctl, unsigned long arg) | |
1459 | { | |
1460 | struct kvm_vcpu *vcpu = filp->private_data; | |
1461 | void __user *argp = (void __user *)arg; | |
1462 | int r; | |
b772ff36 | 1463 | struct kvm_lapic_state *lapic = NULL; |
313a3dc7 CO |
1464 | |
1465 | switch (ioctl) { | |
1466 | case KVM_GET_LAPIC: { | |
b772ff36 | 1467 | lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL); |
313a3dc7 | 1468 | |
b772ff36 DH |
1469 | r = -ENOMEM; |
1470 | if (!lapic) | |
1471 | goto out; | |
1472 | r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic); | |
313a3dc7 CO |
1473 | if (r) |
1474 | goto out; | |
1475 | r = -EFAULT; | |
b772ff36 | 1476 | if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state))) |
313a3dc7 CO |
1477 | goto out; |
1478 | r = 0; | |
1479 | break; | |
1480 | } | |
1481 | case KVM_SET_LAPIC: { | |
b772ff36 DH |
1482 | lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL); |
1483 | r = -ENOMEM; | |
1484 | if (!lapic) | |
1485 | goto out; | |
313a3dc7 | 1486 | r = -EFAULT; |
b772ff36 | 1487 | if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state))) |
313a3dc7 | 1488 | goto out; |
b772ff36 | 1489 | r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic); |
313a3dc7 CO |
1490 | if (r) |
1491 | goto out; | |
1492 | r = 0; | |
1493 | break; | |
1494 | } | |
f77bc6a4 ZX |
1495 | case KVM_INTERRUPT: { |
1496 | struct kvm_interrupt irq; | |
1497 | ||
1498 | r = -EFAULT; | |
1499 | if (copy_from_user(&irq, argp, sizeof irq)) | |
1500 | goto out; | |
1501 | r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); | |
1502 | if (r) | |
1503 | goto out; | |
1504 | r = 0; | |
1505 | break; | |
1506 | } | |
c4abb7c9 JK |
1507 | case KVM_NMI: { |
1508 | r = kvm_vcpu_ioctl_nmi(vcpu); | |
1509 | if (r) | |
1510 | goto out; | |
1511 | r = 0; | |
1512 | break; | |
1513 | } | |
313a3dc7 CO |
1514 | case KVM_SET_CPUID: { |
1515 | struct kvm_cpuid __user *cpuid_arg = argp; | |
1516 | struct kvm_cpuid cpuid; | |
1517 | ||
1518 | r = -EFAULT; | |
1519 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
1520 | goto out; | |
1521 | r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); | |
1522 | if (r) | |
1523 | goto out; | |
1524 | break; | |
1525 | } | |
07716717 DK |
1526 | case KVM_SET_CPUID2: { |
1527 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
1528 | struct kvm_cpuid2 cpuid; | |
1529 | ||
1530 | r = -EFAULT; | |
1531 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
1532 | goto out; | |
1533 | r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, | |
19355475 | 1534 | cpuid_arg->entries); |
07716717 DK |
1535 | if (r) |
1536 | goto out; | |
1537 | break; | |
1538 | } | |
1539 | case KVM_GET_CPUID2: { | |
1540 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
1541 | struct kvm_cpuid2 cpuid; | |
1542 | ||
1543 | r = -EFAULT; | |
1544 | if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid)) | |
1545 | goto out; | |
1546 | r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, | |
19355475 | 1547 | cpuid_arg->entries); |
07716717 DK |
1548 | if (r) |
1549 | goto out; | |
1550 | r = -EFAULT; | |
1551 | if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid)) | |
1552 | goto out; | |
1553 | r = 0; | |
1554 | break; | |
1555 | } | |
313a3dc7 CO |
1556 | case KVM_GET_MSRS: |
1557 | r = msr_io(vcpu, argp, kvm_get_msr, 1); | |
1558 | break; | |
1559 | case KVM_SET_MSRS: | |
1560 | r = msr_io(vcpu, argp, do_set_msr, 0); | |
1561 | break; | |
b209749f AK |
1562 | case KVM_TPR_ACCESS_REPORTING: { |
1563 | struct kvm_tpr_access_ctl tac; | |
1564 | ||
1565 | r = -EFAULT; | |
1566 | if (copy_from_user(&tac, argp, sizeof tac)) | |
1567 | goto out; | |
1568 | r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); | |
1569 | if (r) | |
1570 | goto out; | |
1571 | r = -EFAULT; | |
1572 | if (copy_to_user(argp, &tac, sizeof tac)) | |
1573 | goto out; | |
1574 | r = 0; | |
1575 | break; | |
1576 | }; | |
b93463aa AK |
1577 | case KVM_SET_VAPIC_ADDR: { |
1578 | struct kvm_vapic_addr va; | |
1579 | ||
1580 | r = -EINVAL; | |
1581 | if (!irqchip_in_kernel(vcpu->kvm)) | |
1582 | goto out; | |
1583 | r = -EFAULT; | |
1584 | if (copy_from_user(&va, argp, sizeof va)) | |
1585 | goto out; | |
1586 | r = 0; | |
1587 | kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); | |
1588 | break; | |
1589 | } | |
313a3dc7 CO |
1590 | default: |
1591 | r = -EINVAL; | |
1592 | } | |
1593 | out: | |
7a6ce84c | 1594 | kfree(lapic); |
313a3dc7 CO |
1595 | return r; |
1596 | } | |
1597 | ||
1fe779f8 CO |
1598 | static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) |
1599 | { | |
1600 | int ret; | |
1601 | ||
1602 | if (addr > (unsigned int)(-3 * PAGE_SIZE)) | |
1603 | return -1; | |
1604 | ret = kvm_x86_ops->set_tss_addr(kvm, addr); | |
1605 | return ret; | |
1606 | } | |
1607 | ||
1608 | static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, | |
1609 | u32 kvm_nr_mmu_pages) | |
1610 | { | |
1611 | if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) | |
1612 | return -EINVAL; | |
1613 | ||
72dc67a6 | 1614 | down_write(&kvm->slots_lock); |
1fe779f8 CO |
1615 | |
1616 | kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); | |
f05e70ac | 1617 | kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; |
1fe779f8 | 1618 | |
72dc67a6 | 1619 | up_write(&kvm->slots_lock); |
1fe779f8 CO |
1620 | return 0; |
1621 | } | |
1622 | ||
1623 | static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) | |
1624 | { | |
f05e70ac | 1625 | return kvm->arch.n_alloc_mmu_pages; |
1fe779f8 CO |
1626 | } |
1627 | ||
e9f85cde ZX |
1628 | gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn) |
1629 | { | |
1630 | int i; | |
1631 | struct kvm_mem_alias *alias; | |
1632 | ||
d69fb81f ZX |
1633 | for (i = 0; i < kvm->arch.naliases; ++i) { |
1634 | alias = &kvm->arch.aliases[i]; | |
e9f85cde ZX |
1635 | if (gfn >= alias->base_gfn |
1636 | && gfn < alias->base_gfn + alias->npages) | |
1637 | return alias->target_gfn + gfn - alias->base_gfn; | |
1638 | } | |
1639 | return gfn; | |
1640 | } | |
1641 | ||
1fe779f8 CO |
1642 | /* |
1643 | * Set a new alias region. Aliases map a portion of physical memory into | |
1644 | * another portion. This is useful for memory windows, for example the PC | |
1645 | * VGA region. | |
1646 | */ | |
1647 | static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm, | |
1648 | struct kvm_memory_alias *alias) | |
1649 | { | |
1650 | int r, n; | |
1651 | struct kvm_mem_alias *p; | |
1652 | ||
1653 | r = -EINVAL; | |
1654 | /* General sanity checks */ | |
1655 | if (alias->memory_size & (PAGE_SIZE - 1)) | |
1656 | goto out; | |
1657 | if (alias->guest_phys_addr & (PAGE_SIZE - 1)) | |
1658 | goto out; | |
1659 | if (alias->slot >= KVM_ALIAS_SLOTS) | |
1660 | goto out; | |
1661 | if (alias->guest_phys_addr + alias->memory_size | |
1662 | < alias->guest_phys_addr) | |
1663 | goto out; | |
1664 | if (alias->target_phys_addr + alias->memory_size | |
1665 | < alias->target_phys_addr) | |
1666 | goto out; | |
1667 | ||
72dc67a6 | 1668 | down_write(&kvm->slots_lock); |
a1708ce8 | 1669 | spin_lock(&kvm->mmu_lock); |
1fe779f8 | 1670 | |
d69fb81f | 1671 | p = &kvm->arch.aliases[alias->slot]; |
1fe779f8 CO |
1672 | p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT; |
1673 | p->npages = alias->memory_size >> PAGE_SHIFT; | |
1674 | p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT; | |
1675 | ||
1676 | for (n = KVM_ALIAS_SLOTS; n > 0; --n) | |
d69fb81f | 1677 | if (kvm->arch.aliases[n - 1].npages) |
1fe779f8 | 1678 | break; |
d69fb81f | 1679 | kvm->arch.naliases = n; |
1fe779f8 | 1680 | |
a1708ce8 | 1681 | spin_unlock(&kvm->mmu_lock); |
1fe779f8 CO |
1682 | kvm_mmu_zap_all(kvm); |
1683 | ||
72dc67a6 | 1684 | up_write(&kvm->slots_lock); |
1fe779f8 CO |
1685 | |
1686 | return 0; | |
1687 | ||
1688 | out: | |
1689 | return r; | |
1690 | } | |
1691 | ||
1692 | static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) | |
1693 | { | |
1694 | int r; | |
1695 | ||
1696 | r = 0; | |
1697 | switch (chip->chip_id) { | |
1698 | case KVM_IRQCHIP_PIC_MASTER: | |
1699 | memcpy(&chip->chip.pic, | |
1700 | &pic_irqchip(kvm)->pics[0], | |
1701 | sizeof(struct kvm_pic_state)); | |
1702 | break; | |
1703 | case KVM_IRQCHIP_PIC_SLAVE: | |
1704 | memcpy(&chip->chip.pic, | |
1705 | &pic_irqchip(kvm)->pics[1], | |
1706 | sizeof(struct kvm_pic_state)); | |
1707 | break; | |
1708 | case KVM_IRQCHIP_IOAPIC: | |
1709 | memcpy(&chip->chip.ioapic, | |
1710 | ioapic_irqchip(kvm), | |
1711 | sizeof(struct kvm_ioapic_state)); | |
1712 | break; | |
1713 | default: | |
1714 | r = -EINVAL; | |
1715 | break; | |
1716 | } | |
1717 | return r; | |
1718 | } | |
1719 | ||
1720 | static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) | |
1721 | { | |
1722 | int r; | |
1723 | ||
1724 | r = 0; | |
1725 | switch (chip->chip_id) { | |
1726 | case KVM_IRQCHIP_PIC_MASTER: | |
1727 | memcpy(&pic_irqchip(kvm)->pics[0], | |
1728 | &chip->chip.pic, | |
1729 | sizeof(struct kvm_pic_state)); | |
1730 | break; | |
1731 | case KVM_IRQCHIP_PIC_SLAVE: | |
1732 | memcpy(&pic_irqchip(kvm)->pics[1], | |
1733 | &chip->chip.pic, | |
1734 | sizeof(struct kvm_pic_state)); | |
1735 | break; | |
1736 | case KVM_IRQCHIP_IOAPIC: | |
1737 | memcpy(ioapic_irqchip(kvm), | |
1738 | &chip->chip.ioapic, | |
1739 | sizeof(struct kvm_ioapic_state)); | |
1740 | break; | |
1741 | default: | |
1742 | r = -EINVAL; | |
1743 | break; | |
1744 | } | |
1745 | kvm_pic_update_irq(pic_irqchip(kvm)); | |
1746 | return r; | |
1747 | } | |
1748 | ||
e0f63cb9 SY |
1749 | static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) |
1750 | { | |
1751 | int r = 0; | |
1752 | ||
1753 | memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state)); | |
1754 | return r; | |
1755 | } | |
1756 | ||
1757 | static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) | |
1758 | { | |
1759 | int r = 0; | |
1760 | ||
1761 | memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state)); | |
1762 | kvm_pit_load_count(kvm, 0, ps->channels[0].count); | |
1763 | return r; | |
1764 | } | |
1765 | ||
52d939a0 MT |
1766 | static int kvm_vm_ioctl_reinject(struct kvm *kvm, |
1767 | struct kvm_reinject_control *control) | |
1768 | { | |
1769 | if (!kvm->arch.vpit) | |
1770 | return -ENXIO; | |
1771 | kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject; | |
1772 | return 0; | |
1773 | } | |
1774 | ||
5bb064dc ZX |
1775 | /* |
1776 | * Get (and clear) the dirty memory log for a memory slot. | |
1777 | */ | |
1778 | int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, | |
1779 | struct kvm_dirty_log *log) | |
1780 | { | |
1781 | int r; | |
1782 | int n; | |
1783 | struct kvm_memory_slot *memslot; | |
1784 | int is_dirty = 0; | |
1785 | ||
72dc67a6 | 1786 | down_write(&kvm->slots_lock); |
5bb064dc ZX |
1787 | |
1788 | r = kvm_get_dirty_log(kvm, log, &is_dirty); | |
1789 | if (r) | |
1790 | goto out; | |
1791 | ||
1792 | /* If nothing is dirty, don't bother messing with page tables. */ | |
1793 | if (is_dirty) { | |
1794 | kvm_mmu_slot_remove_write_access(kvm, log->slot); | |
1795 | kvm_flush_remote_tlbs(kvm); | |
1796 | memslot = &kvm->memslots[log->slot]; | |
1797 | n = ALIGN(memslot->npages, BITS_PER_LONG) / 8; | |
1798 | memset(memslot->dirty_bitmap, 0, n); | |
1799 | } | |
1800 | r = 0; | |
1801 | out: | |
72dc67a6 | 1802 | up_write(&kvm->slots_lock); |
5bb064dc ZX |
1803 | return r; |
1804 | } | |
1805 | ||
1fe779f8 CO |
1806 | long kvm_arch_vm_ioctl(struct file *filp, |
1807 | unsigned int ioctl, unsigned long arg) | |
1808 | { | |
1809 | struct kvm *kvm = filp->private_data; | |
1810 | void __user *argp = (void __user *)arg; | |
1811 | int r = -EINVAL; | |
f0d66275 DH |
1812 | /* |
1813 | * This union makes it completely explicit to gcc-3.x | |
1814 | * that these two variables' stack usage should be | |
1815 | * combined, not added together. | |
1816 | */ | |
1817 | union { | |
1818 | struct kvm_pit_state ps; | |
1819 | struct kvm_memory_alias alias; | |
1820 | } u; | |
1fe779f8 CO |
1821 | |
1822 | switch (ioctl) { | |
1823 | case KVM_SET_TSS_ADDR: | |
1824 | r = kvm_vm_ioctl_set_tss_addr(kvm, arg); | |
1825 | if (r < 0) | |
1826 | goto out; | |
1827 | break; | |
1828 | case KVM_SET_MEMORY_REGION: { | |
1829 | struct kvm_memory_region kvm_mem; | |
1830 | struct kvm_userspace_memory_region kvm_userspace_mem; | |
1831 | ||
1832 | r = -EFAULT; | |
1833 | if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem)) | |
1834 | goto out; | |
1835 | kvm_userspace_mem.slot = kvm_mem.slot; | |
1836 | kvm_userspace_mem.flags = kvm_mem.flags; | |
1837 | kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr; | |
1838 | kvm_userspace_mem.memory_size = kvm_mem.memory_size; | |
1839 | r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0); | |
1840 | if (r) | |
1841 | goto out; | |
1842 | break; | |
1843 | } | |
1844 | case KVM_SET_NR_MMU_PAGES: | |
1845 | r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); | |
1846 | if (r) | |
1847 | goto out; | |
1848 | break; | |
1849 | case KVM_GET_NR_MMU_PAGES: | |
1850 | r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); | |
1851 | break; | |
f0d66275 | 1852 | case KVM_SET_MEMORY_ALIAS: |
1fe779f8 | 1853 | r = -EFAULT; |
f0d66275 | 1854 | if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias))) |
1fe779f8 | 1855 | goto out; |
f0d66275 | 1856 | r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias); |
1fe779f8 CO |
1857 | if (r) |
1858 | goto out; | |
1859 | break; | |
1fe779f8 CO |
1860 | case KVM_CREATE_IRQCHIP: |
1861 | r = -ENOMEM; | |
d7deeeb0 ZX |
1862 | kvm->arch.vpic = kvm_create_pic(kvm); |
1863 | if (kvm->arch.vpic) { | |
1fe779f8 CO |
1864 | r = kvm_ioapic_init(kvm); |
1865 | if (r) { | |
d7deeeb0 ZX |
1866 | kfree(kvm->arch.vpic); |
1867 | kvm->arch.vpic = NULL; | |
1fe779f8 CO |
1868 | goto out; |
1869 | } | |
1870 | } else | |
1871 | goto out; | |
399ec807 AK |
1872 | r = kvm_setup_default_irq_routing(kvm); |
1873 | if (r) { | |
1874 | kfree(kvm->arch.vpic); | |
1875 | kfree(kvm->arch.vioapic); | |
1876 | goto out; | |
1877 | } | |
1fe779f8 | 1878 | break; |
7837699f | 1879 | case KVM_CREATE_PIT: |
269e05e4 AK |
1880 | mutex_lock(&kvm->lock); |
1881 | r = -EEXIST; | |
1882 | if (kvm->arch.vpit) | |
1883 | goto create_pit_unlock; | |
7837699f SY |
1884 | r = -ENOMEM; |
1885 | kvm->arch.vpit = kvm_create_pit(kvm); | |
1886 | if (kvm->arch.vpit) | |
1887 | r = 0; | |
269e05e4 AK |
1888 | create_pit_unlock: |
1889 | mutex_unlock(&kvm->lock); | |
7837699f | 1890 | break; |
4925663a | 1891 | case KVM_IRQ_LINE_STATUS: |
1fe779f8 CO |
1892 | case KVM_IRQ_LINE: { |
1893 | struct kvm_irq_level irq_event; | |
1894 | ||
1895 | r = -EFAULT; | |
1896 | if (copy_from_user(&irq_event, argp, sizeof irq_event)) | |
1897 | goto out; | |
1898 | if (irqchip_in_kernel(kvm)) { | |
4925663a | 1899 | __s32 status; |
1fe779f8 | 1900 | mutex_lock(&kvm->lock); |
4925663a GN |
1901 | status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, |
1902 | irq_event.irq, irq_event.level); | |
1fe779f8 | 1903 | mutex_unlock(&kvm->lock); |
4925663a GN |
1904 | if (ioctl == KVM_IRQ_LINE_STATUS) { |
1905 | irq_event.status = status; | |
1906 | if (copy_to_user(argp, &irq_event, | |
1907 | sizeof irq_event)) | |
1908 | goto out; | |
1909 | } | |
1fe779f8 CO |
1910 | r = 0; |
1911 | } | |
1912 | break; | |
1913 | } | |
1914 | case KVM_GET_IRQCHIP: { | |
1915 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
f0d66275 | 1916 | struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL); |
1fe779f8 | 1917 | |
f0d66275 DH |
1918 | r = -ENOMEM; |
1919 | if (!chip) | |
1fe779f8 | 1920 | goto out; |
f0d66275 DH |
1921 | r = -EFAULT; |
1922 | if (copy_from_user(chip, argp, sizeof *chip)) | |
1923 | goto get_irqchip_out; | |
1fe779f8 CO |
1924 | r = -ENXIO; |
1925 | if (!irqchip_in_kernel(kvm)) | |
f0d66275 DH |
1926 | goto get_irqchip_out; |
1927 | r = kvm_vm_ioctl_get_irqchip(kvm, chip); | |
1fe779f8 | 1928 | if (r) |
f0d66275 | 1929 | goto get_irqchip_out; |
1fe779f8 | 1930 | r = -EFAULT; |
f0d66275 DH |
1931 | if (copy_to_user(argp, chip, sizeof *chip)) |
1932 | goto get_irqchip_out; | |
1fe779f8 | 1933 | r = 0; |
f0d66275 DH |
1934 | get_irqchip_out: |
1935 | kfree(chip); | |
1936 | if (r) | |
1937 | goto out; | |
1fe779f8 CO |
1938 | break; |
1939 | } | |
1940 | case KVM_SET_IRQCHIP: { | |
1941 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
f0d66275 | 1942 | struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL); |
1fe779f8 | 1943 | |
f0d66275 DH |
1944 | r = -ENOMEM; |
1945 | if (!chip) | |
1fe779f8 | 1946 | goto out; |
f0d66275 DH |
1947 | r = -EFAULT; |
1948 | if (copy_from_user(chip, argp, sizeof *chip)) | |
1949 | goto set_irqchip_out; | |
1fe779f8 CO |
1950 | r = -ENXIO; |
1951 | if (!irqchip_in_kernel(kvm)) | |
f0d66275 DH |
1952 | goto set_irqchip_out; |
1953 | r = kvm_vm_ioctl_set_irqchip(kvm, chip); | |
1fe779f8 | 1954 | if (r) |
f0d66275 | 1955 | goto set_irqchip_out; |
1fe779f8 | 1956 | r = 0; |
f0d66275 DH |
1957 | set_irqchip_out: |
1958 | kfree(chip); | |
1959 | if (r) | |
1960 | goto out; | |
1fe779f8 CO |
1961 | break; |
1962 | } | |
e0f63cb9 | 1963 | case KVM_GET_PIT: { |
e0f63cb9 | 1964 | r = -EFAULT; |
f0d66275 | 1965 | if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
1966 | goto out; |
1967 | r = -ENXIO; | |
1968 | if (!kvm->arch.vpit) | |
1969 | goto out; | |
f0d66275 | 1970 | r = kvm_vm_ioctl_get_pit(kvm, &u.ps); |
e0f63cb9 SY |
1971 | if (r) |
1972 | goto out; | |
1973 | r = -EFAULT; | |
f0d66275 | 1974 | if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
1975 | goto out; |
1976 | r = 0; | |
1977 | break; | |
1978 | } | |
1979 | case KVM_SET_PIT: { | |
e0f63cb9 | 1980 | r = -EFAULT; |
f0d66275 | 1981 | if (copy_from_user(&u.ps, argp, sizeof u.ps)) |
e0f63cb9 SY |
1982 | goto out; |
1983 | r = -ENXIO; | |
1984 | if (!kvm->arch.vpit) | |
1985 | goto out; | |
f0d66275 | 1986 | r = kvm_vm_ioctl_set_pit(kvm, &u.ps); |
e0f63cb9 SY |
1987 | if (r) |
1988 | goto out; | |
1989 | r = 0; | |
1990 | break; | |
1991 | } | |
52d939a0 MT |
1992 | case KVM_REINJECT_CONTROL: { |
1993 | struct kvm_reinject_control control; | |
1994 | r = -EFAULT; | |
1995 | if (copy_from_user(&control, argp, sizeof(control))) | |
1996 | goto out; | |
1997 | r = kvm_vm_ioctl_reinject(kvm, &control); | |
1998 | if (r) | |
1999 | goto out; | |
2000 | r = 0; | |
2001 | break; | |
2002 | } | |
1fe779f8 CO |
2003 | default: |
2004 | ; | |
2005 | } | |
2006 | out: | |
2007 | return r; | |
2008 | } | |
2009 | ||
a16b043c | 2010 | static void kvm_init_msr_list(void) |
043405e1 CO |
2011 | { |
2012 | u32 dummy[2]; | |
2013 | unsigned i, j; | |
2014 | ||
2015 | for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) { | |
2016 | if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0) | |
2017 | continue; | |
2018 | if (j < i) | |
2019 | msrs_to_save[j] = msrs_to_save[i]; | |
2020 | j++; | |
2021 | } | |
2022 | num_msrs_to_save = j; | |
2023 | } | |
2024 | ||
bbd9b64e CO |
2025 | /* |
2026 | * Only apic need an MMIO device hook, so shortcut now.. | |
2027 | */ | |
2028 | static struct kvm_io_device *vcpu_find_pervcpu_dev(struct kvm_vcpu *vcpu, | |
92760499 LV |
2029 | gpa_t addr, int len, |
2030 | int is_write) | |
bbd9b64e CO |
2031 | { |
2032 | struct kvm_io_device *dev; | |
2033 | ||
ad312c7c ZX |
2034 | if (vcpu->arch.apic) { |
2035 | dev = &vcpu->arch.apic->dev; | |
92760499 | 2036 | if (dev->in_range(dev, addr, len, is_write)) |
bbd9b64e CO |
2037 | return dev; |
2038 | } | |
2039 | return NULL; | |
2040 | } | |
2041 | ||
2042 | ||
2043 | static struct kvm_io_device *vcpu_find_mmio_dev(struct kvm_vcpu *vcpu, | |
92760499 LV |
2044 | gpa_t addr, int len, |
2045 | int is_write) | |
bbd9b64e CO |
2046 | { |
2047 | struct kvm_io_device *dev; | |
2048 | ||
92760499 | 2049 | dev = vcpu_find_pervcpu_dev(vcpu, addr, len, is_write); |
bbd9b64e | 2050 | if (dev == NULL) |
92760499 LV |
2051 | dev = kvm_io_bus_find_dev(&vcpu->kvm->mmio_bus, addr, len, |
2052 | is_write); | |
bbd9b64e CO |
2053 | return dev; |
2054 | } | |
2055 | ||
cded19f3 HE |
2056 | static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes, |
2057 | struct kvm_vcpu *vcpu) | |
bbd9b64e CO |
2058 | { |
2059 | void *data = val; | |
10589a46 | 2060 | int r = X86EMUL_CONTINUE; |
bbd9b64e CO |
2061 | |
2062 | while (bytes) { | |
ad312c7c | 2063 | gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr); |
bbd9b64e | 2064 | unsigned offset = addr & (PAGE_SIZE-1); |
77c2002e | 2065 | unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); |
bbd9b64e CO |
2066 | int ret; |
2067 | ||
10589a46 MT |
2068 | if (gpa == UNMAPPED_GVA) { |
2069 | r = X86EMUL_PROPAGATE_FAULT; | |
2070 | goto out; | |
2071 | } | |
77c2002e | 2072 | ret = kvm_read_guest(vcpu->kvm, gpa, data, toread); |
10589a46 MT |
2073 | if (ret < 0) { |
2074 | r = X86EMUL_UNHANDLEABLE; | |
2075 | goto out; | |
2076 | } | |
bbd9b64e | 2077 | |
77c2002e IE |
2078 | bytes -= toread; |
2079 | data += toread; | |
2080 | addr += toread; | |
bbd9b64e | 2081 | } |
10589a46 | 2082 | out: |
10589a46 | 2083 | return r; |
bbd9b64e | 2084 | } |
77c2002e | 2085 | |
cded19f3 HE |
2086 | static int kvm_write_guest_virt(gva_t addr, void *val, unsigned int bytes, |
2087 | struct kvm_vcpu *vcpu) | |
77c2002e IE |
2088 | { |
2089 | void *data = val; | |
2090 | int r = X86EMUL_CONTINUE; | |
2091 | ||
2092 | while (bytes) { | |
2093 | gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr); | |
2094 | unsigned offset = addr & (PAGE_SIZE-1); | |
2095 | unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); | |
2096 | int ret; | |
2097 | ||
2098 | if (gpa == UNMAPPED_GVA) { | |
2099 | r = X86EMUL_PROPAGATE_FAULT; | |
2100 | goto out; | |
2101 | } | |
2102 | ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite); | |
2103 | if (ret < 0) { | |
2104 | r = X86EMUL_UNHANDLEABLE; | |
2105 | goto out; | |
2106 | } | |
2107 | ||
2108 | bytes -= towrite; | |
2109 | data += towrite; | |
2110 | addr += towrite; | |
2111 | } | |
2112 | out: | |
2113 | return r; | |
2114 | } | |
2115 | ||
bbd9b64e | 2116 | |
bbd9b64e CO |
2117 | static int emulator_read_emulated(unsigned long addr, |
2118 | void *val, | |
2119 | unsigned int bytes, | |
2120 | struct kvm_vcpu *vcpu) | |
2121 | { | |
2122 | struct kvm_io_device *mmio_dev; | |
2123 | gpa_t gpa; | |
2124 | ||
2125 | if (vcpu->mmio_read_completed) { | |
2126 | memcpy(val, vcpu->mmio_data, bytes); | |
2127 | vcpu->mmio_read_completed = 0; | |
2128 | return X86EMUL_CONTINUE; | |
2129 | } | |
2130 | ||
ad312c7c | 2131 | gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr); |
bbd9b64e CO |
2132 | |
2133 | /* For APIC access vmexit */ | |
2134 | if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
2135 | goto mmio; | |
2136 | ||
77c2002e IE |
2137 | if (kvm_read_guest_virt(addr, val, bytes, vcpu) |
2138 | == X86EMUL_CONTINUE) | |
bbd9b64e CO |
2139 | return X86EMUL_CONTINUE; |
2140 | if (gpa == UNMAPPED_GVA) | |
2141 | return X86EMUL_PROPAGATE_FAULT; | |
2142 | ||
2143 | mmio: | |
2144 | /* | |
2145 | * Is this MMIO handled locally? | |
2146 | */ | |
10589a46 | 2147 | mutex_lock(&vcpu->kvm->lock); |
92760499 | 2148 | mmio_dev = vcpu_find_mmio_dev(vcpu, gpa, bytes, 0); |
bbd9b64e CO |
2149 | if (mmio_dev) { |
2150 | kvm_iodevice_read(mmio_dev, gpa, bytes, val); | |
10589a46 | 2151 | mutex_unlock(&vcpu->kvm->lock); |
bbd9b64e CO |
2152 | return X86EMUL_CONTINUE; |
2153 | } | |
10589a46 | 2154 | mutex_unlock(&vcpu->kvm->lock); |
bbd9b64e CO |
2155 | |
2156 | vcpu->mmio_needed = 1; | |
2157 | vcpu->mmio_phys_addr = gpa; | |
2158 | vcpu->mmio_size = bytes; | |
2159 | vcpu->mmio_is_write = 0; | |
2160 | ||
2161 | return X86EMUL_UNHANDLEABLE; | |
2162 | } | |
2163 | ||
3200f405 | 2164 | int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, |
9f811285 | 2165 | const void *val, int bytes) |
bbd9b64e CO |
2166 | { |
2167 | int ret; | |
2168 | ||
2169 | ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes); | |
9f811285 | 2170 | if (ret < 0) |
bbd9b64e | 2171 | return 0; |
ad218f85 | 2172 | kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1); |
bbd9b64e CO |
2173 | return 1; |
2174 | } | |
2175 | ||
2176 | static int emulator_write_emulated_onepage(unsigned long addr, | |
2177 | const void *val, | |
2178 | unsigned int bytes, | |
2179 | struct kvm_vcpu *vcpu) | |
2180 | { | |
2181 | struct kvm_io_device *mmio_dev; | |
10589a46 MT |
2182 | gpa_t gpa; |
2183 | ||
10589a46 | 2184 | gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr); |
bbd9b64e CO |
2185 | |
2186 | if (gpa == UNMAPPED_GVA) { | |
c3c91fee | 2187 | kvm_inject_page_fault(vcpu, addr, 2); |
bbd9b64e CO |
2188 | return X86EMUL_PROPAGATE_FAULT; |
2189 | } | |
2190 | ||
2191 | /* For APIC access vmexit */ | |
2192 | if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
2193 | goto mmio; | |
2194 | ||
2195 | if (emulator_write_phys(vcpu, gpa, val, bytes)) | |
2196 | return X86EMUL_CONTINUE; | |
2197 | ||
2198 | mmio: | |
2199 | /* | |
2200 | * Is this MMIO handled locally? | |
2201 | */ | |
10589a46 | 2202 | mutex_lock(&vcpu->kvm->lock); |
92760499 | 2203 | mmio_dev = vcpu_find_mmio_dev(vcpu, gpa, bytes, 1); |
bbd9b64e CO |
2204 | if (mmio_dev) { |
2205 | kvm_iodevice_write(mmio_dev, gpa, bytes, val); | |
10589a46 | 2206 | mutex_unlock(&vcpu->kvm->lock); |
bbd9b64e CO |
2207 | return X86EMUL_CONTINUE; |
2208 | } | |
10589a46 | 2209 | mutex_unlock(&vcpu->kvm->lock); |
bbd9b64e CO |
2210 | |
2211 | vcpu->mmio_needed = 1; | |
2212 | vcpu->mmio_phys_addr = gpa; | |
2213 | vcpu->mmio_size = bytes; | |
2214 | vcpu->mmio_is_write = 1; | |
2215 | memcpy(vcpu->mmio_data, val, bytes); | |
2216 | ||
2217 | return X86EMUL_CONTINUE; | |
2218 | } | |
2219 | ||
2220 | int emulator_write_emulated(unsigned long addr, | |
2221 | const void *val, | |
2222 | unsigned int bytes, | |
2223 | struct kvm_vcpu *vcpu) | |
2224 | { | |
2225 | /* Crossing a page boundary? */ | |
2226 | if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { | |
2227 | int rc, now; | |
2228 | ||
2229 | now = -addr & ~PAGE_MASK; | |
2230 | rc = emulator_write_emulated_onepage(addr, val, now, vcpu); | |
2231 | if (rc != X86EMUL_CONTINUE) | |
2232 | return rc; | |
2233 | addr += now; | |
2234 | val += now; | |
2235 | bytes -= now; | |
2236 | } | |
2237 | return emulator_write_emulated_onepage(addr, val, bytes, vcpu); | |
2238 | } | |
2239 | EXPORT_SYMBOL_GPL(emulator_write_emulated); | |
2240 | ||
2241 | static int emulator_cmpxchg_emulated(unsigned long addr, | |
2242 | const void *old, | |
2243 | const void *new, | |
2244 | unsigned int bytes, | |
2245 | struct kvm_vcpu *vcpu) | |
2246 | { | |
2247 | static int reported; | |
2248 | ||
2249 | if (!reported) { | |
2250 | reported = 1; | |
2251 | printk(KERN_WARNING "kvm: emulating exchange as write\n"); | |
2252 | } | |
2bacc55c MT |
2253 | #ifndef CONFIG_X86_64 |
2254 | /* guests cmpxchg8b have to be emulated atomically */ | |
2255 | if (bytes == 8) { | |
10589a46 | 2256 | gpa_t gpa; |
2bacc55c | 2257 | struct page *page; |
c0b49b0d | 2258 | char *kaddr; |
2bacc55c MT |
2259 | u64 val; |
2260 | ||
10589a46 MT |
2261 | gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr); |
2262 | ||
2bacc55c MT |
2263 | if (gpa == UNMAPPED_GVA || |
2264 | (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
2265 | goto emul_write; | |
2266 | ||
2267 | if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK)) | |
2268 | goto emul_write; | |
2269 | ||
2270 | val = *(u64 *)new; | |
72dc67a6 | 2271 | |
2bacc55c | 2272 | page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT); |
72dc67a6 | 2273 | |
c0b49b0d AM |
2274 | kaddr = kmap_atomic(page, KM_USER0); |
2275 | set_64bit((u64 *)(kaddr + offset_in_page(gpa)), val); | |
2276 | kunmap_atomic(kaddr, KM_USER0); | |
2bacc55c MT |
2277 | kvm_release_page_dirty(page); |
2278 | } | |
3200f405 | 2279 | emul_write: |
2bacc55c MT |
2280 | #endif |
2281 | ||
bbd9b64e CO |
2282 | return emulator_write_emulated(addr, new, bytes, vcpu); |
2283 | } | |
2284 | ||
2285 | static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) | |
2286 | { | |
2287 | return kvm_x86_ops->get_segment_base(vcpu, seg); | |
2288 | } | |
2289 | ||
2290 | int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address) | |
2291 | { | |
a7052897 | 2292 | kvm_mmu_invlpg(vcpu, address); |
bbd9b64e CO |
2293 | return X86EMUL_CONTINUE; |
2294 | } | |
2295 | ||
2296 | int emulate_clts(struct kvm_vcpu *vcpu) | |
2297 | { | |
54e445ca | 2298 | KVMTRACE_0D(CLTS, vcpu, handler); |
ad312c7c | 2299 | kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 & ~X86_CR0_TS); |
bbd9b64e CO |
2300 | return X86EMUL_CONTINUE; |
2301 | } | |
2302 | ||
2303 | int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest) | |
2304 | { | |
2305 | struct kvm_vcpu *vcpu = ctxt->vcpu; | |
2306 | ||
2307 | switch (dr) { | |
2308 | case 0 ... 3: | |
2309 | *dest = kvm_x86_ops->get_dr(vcpu, dr); | |
2310 | return X86EMUL_CONTINUE; | |
2311 | default: | |
b8688d51 | 2312 | pr_unimpl(vcpu, "%s: unexpected dr %u\n", __func__, dr); |
bbd9b64e CO |
2313 | return X86EMUL_UNHANDLEABLE; |
2314 | } | |
2315 | } | |
2316 | ||
2317 | int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value) | |
2318 | { | |
2319 | unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U; | |
2320 | int exception; | |
2321 | ||
2322 | kvm_x86_ops->set_dr(ctxt->vcpu, dr, value & mask, &exception); | |
2323 | if (exception) { | |
2324 | /* FIXME: better handling */ | |
2325 | return X86EMUL_UNHANDLEABLE; | |
2326 | } | |
2327 | return X86EMUL_CONTINUE; | |
2328 | } | |
2329 | ||
2330 | void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context) | |
2331 | { | |
bbd9b64e | 2332 | u8 opcodes[4]; |
5fdbf976 | 2333 | unsigned long rip = kvm_rip_read(vcpu); |
bbd9b64e CO |
2334 | unsigned long rip_linear; |
2335 | ||
f76c710d | 2336 | if (!printk_ratelimit()) |
bbd9b64e CO |
2337 | return; |
2338 | ||
25be4608 GC |
2339 | rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS); |
2340 | ||
77c2002e | 2341 | kvm_read_guest_virt(rip_linear, (void *)opcodes, 4, vcpu); |
bbd9b64e CO |
2342 | |
2343 | printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n", | |
2344 | context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]); | |
bbd9b64e CO |
2345 | } |
2346 | EXPORT_SYMBOL_GPL(kvm_report_emulation_failure); | |
2347 | ||
14af3f3c | 2348 | static struct x86_emulate_ops emulate_ops = { |
77c2002e | 2349 | .read_std = kvm_read_guest_virt, |
bbd9b64e CO |
2350 | .read_emulated = emulator_read_emulated, |
2351 | .write_emulated = emulator_write_emulated, | |
2352 | .cmpxchg_emulated = emulator_cmpxchg_emulated, | |
2353 | }; | |
2354 | ||
5fdbf976 MT |
2355 | static void cache_all_regs(struct kvm_vcpu *vcpu) |
2356 | { | |
2357 | kvm_register_read(vcpu, VCPU_REGS_RAX); | |
2358 | kvm_register_read(vcpu, VCPU_REGS_RSP); | |
2359 | kvm_register_read(vcpu, VCPU_REGS_RIP); | |
2360 | vcpu->arch.regs_dirty = ~0; | |
2361 | } | |
2362 | ||
bbd9b64e CO |
2363 | int emulate_instruction(struct kvm_vcpu *vcpu, |
2364 | struct kvm_run *run, | |
2365 | unsigned long cr2, | |
2366 | u16 error_code, | |
571008da | 2367 | int emulation_type) |
bbd9b64e CO |
2368 | { |
2369 | int r; | |
571008da | 2370 | struct decode_cache *c; |
bbd9b64e | 2371 | |
26eef70c | 2372 | kvm_clear_exception_queue(vcpu); |
ad312c7c | 2373 | vcpu->arch.mmio_fault_cr2 = cr2; |
5fdbf976 MT |
2374 | /* |
2375 | * TODO: fix x86_emulate.c to use guest_read/write_register | |
2376 | * instead of direct ->regs accesses, can save hundred cycles | |
2377 | * on Intel for instructions that don't read/change RSP, for | |
2378 | * for example. | |
2379 | */ | |
2380 | cache_all_regs(vcpu); | |
bbd9b64e CO |
2381 | |
2382 | vcpu->mmio_is_write = 0; | |
ad312c7c | 2383 | vcpu->arch.pio.string = 0; |
bbd9b64e | 2384 | |
571008da | 2385 | if (!(emulation_type & EMULTYPE_NO_DECODE)) { |
bbd9b64e CO |
2386 | int cs_db, cs_l; |
2387 | kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l); | |
2388 | ||
ad312c7c ZX |
2389 | vcpu->arch.emulate_ctxt.vcpu = vcpu; |
2390 | vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu); | |
2391 | vcpu->arch.emulate_ctxt.mode = | |
2392 | (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM) | |
bbd9b64e CO |
2393 | ? X86EMUL_MODE_REAL : cs_l |
2394 | ? X86EMUL_MODE_PROT64 : cs_db | |
2395 | ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16; | |
2396 | ||
ad312c7c | 2397 | r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops); |
571008da SY |
2398 | |
2399 | /* Reject the instructions other than VMCALL/VMMCALL when | |
2400 | * try to emulate invalid opcode */ | |
2401 | c = &vcpu->arch.emulate_ctxt.decode; | |
2402 | if ((emulation_type & EMULTYPE_TRAP_UD) && | |
2403 | (!(c->twobyte && c->b == 0x01 && | |
2404 | (c->modrm_reg == 0 || c->modrm_reg == 3) && | |
2405 | c->modrm_mod == 3 && c->modrm_rm == 1))) | |
2406 | return EMULATE_FAIL; | |
2407 | ||
f2b5756b | 2408 | ++vcpu->stat.insn_emulation; |
bbd9b64e | 2409 | if (r) { |
f2b5756b | 2410 | ++vcpu->stat.insn_emulation_fail; |
bbd9b64e CO |
2411 | if (kvm_mmu_unprotect_page_virt(vcpu, cr2)) |
2412 | return EMULATE_DONE; | |
2413 | return EMULATE_FAIL; | |
2414 | } | |
2415 | } | |
2416 | ||
ba8afb6b GN |
2417 | if (emulation_type & EMULTYPE_SKIP) { |
2418 | kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip); | |
2419 | return EMULATE_DONE; | |
2420 | } | |
2421 | ||
ad312c7c | 2422 | r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops); |
bbd9b64e | 2423 | |
ad312c7c | 2424 | if (vcpu->arch.pio.string) |
bbd9b64e CO |
2425 | return EMULATE_DO_MMIO; |
2426 | ||
2427 | if ((r || vcpu->mmio_is_write) && run) { | |
2428 | run->exit_reason = KVM_EXIT_MMIO; | |
2429 | run->mmio.phys_addr = vcpu->mmio_phys_addr; | |
2430 | memcpy(run->mmio.data, vcpu->mmio_data, 8); | |
2431 | run->mmio.len = vcpu->mmio_size; | |
2432 | run->mmio.is_write = vcpu->mmio_is_write; | |
2433 | } | |
2434 | ||
2435 | if (r) { | |
2436 | if (kvm_mmu_unprotect_page_virt(vcpu, cr2)) | |
2437 | return EMULATE_DONE; | |
2438 | if (!vcpu->mmio_needed) { | |
2439 | kvm_report_emulation_failure(vcpu, "mmio"); | |
2440 | return EMULATE_FAIL; | |
2441 | } | |
2442 | return EMULATE_DO_MMIO; | |
2443 | } | |
2444 | ||
ad312c7c | 2445 | kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags); |
bbd9b64e CO |
2446 | |
2447 | if (vcpu->mmio_is_write) { | |
2448 | vcpu->mmio_needed = 0; | |
2449 | return EMULATE_DO_MMIO; | |
2450 | } | |
2451 | ||
2452 | return EMULATE_DONE; | |
2453 | } | |
2454 | EXPORT_SYMBOL_GPL(emulate_instruction); | |
2455 | ||
de7d789a CO |
2456 | static int pio_copy_data(struct kvm_vcpu *vcpu) |
2457 | { | |
ad312c7c | 2458 | void *p = vcpu->arch.pio_data; |
0f346074 | 2459 | gva_t q = vcpu->arch.pio.guest_gva; |
de7d789a | 2460 | unsigned bytes; |
0f346074 | 2461 | int ret; |
de7d789a | 2462 | |
ad312c7c ZX |
2463 | bytes = vcpu->arch.pio.size * vcpu->arch.pio.cur_count; |
2464 | if (vcpu->arch.pio.in) | |
0f346074 | 2465 | ret = kvm_write_guest_virt(q, p, bytes, vcpu); |
de7d789a | 2466 | else |
0f346074 IE |
2467 | ret = kvm_read_guest_virt(q, p, bytes, vcpu); |
2468 | return ret; | |
de7d789a CO |
2469 | } |
2470 | ||
2471 | int complete_pio(struct kvm_vcpu *vcpu) | |
2472 | { | |
ad312c7c | 2473 | struct kvm_pio_request *io = &vcpu->arch.pio; |
de7d789a CO |
2474 | long delta; |
2475 | int r; | |
5fdbf976 | 2476 | unsigned long val; |
de7d789a CO |
2477 | |
2478 | if (!io->string) { | |
5fdbf976 MT |
2479 | if (io->in) { |
2480 | val = kvm_register_read(vcpu, VCPU_REGS_RAX); | |
2481 | memcpy(&val, vcpu->arch.pio_data, io->size); | |
2482 | kvm_register_write(vcpu, VCPU_REGS_RAX, val); | |
2483 | } | |
de7d789a CO |
2484 | } else { |
2485 | if (io->in) { | |
2486 | r = pio_copy_data(vcpu); | |
5fdbf976 | 2487 | if (r) |
de7d789a | 2488 | return r; |
de7d789a CO |
2489 | } |
2490 | ||
2491 | delta = 1; | |
2492 | if (io->rep) { | |
2493 | delta *= io->cur_count; | |
2494 | /* | |
2495 | * The size of the register should really depend on | |
2496 | * current address size. | |
2497 | */ | |
5fdbf976 MT |
2498 | val = kvm_register_read(vcpu, VCPU_REGS_RCX); |
2499 | val -= delta; | |
2500 | kvm_register_write(vcpu, VCPU_REGS_RCX, val); | |
de7d789a CO |
2501 | } |
2502 | if (io->down) | |
2503 | delta = -delta; | |
2504 | delta *= io->size; | |
5fdbf976 MT |
2505 | if (io->in) { |
2506 | val = kvm_register_read(vcpu, VCPU_REGS_RDI); | |
2507 | val += delta; | |
2508 | kvm_register_write(vcpu, VCPU_REGS_RDI, val); | |
2509 | } else { | |
2510 | val = kvm_register_read(vcpu, VCPU_REGS_RSI); | |
2511 | val += delta; | |
2512 | kvm_register_write(vcpu, VCPU_REGS_RSI, val); | |
2513 | } | |
de7d789a CO |
2514 | } |
2515 | ||
de7d789a CO |
2516 | io->count -= io->cur_count; |
2517 | io->cur_count = 0; | |
2518 | ||
2519 | return 0; | |
2520 | } | |
2521 | ||
2522 | static void kernel_pio(struct kvm_io_device *pio_dev, | |
2523 | struct kvm_vcpu *vcpu, | |
2524 | void *pd) | |
2525 | { | |
2526 | /* TODO: String I/O for in kernel device */ | |
2527 | ||
2528 | mutex_lock(&vcpu->kvm->lock); | |
ad312c7c ZX |
2529 | if (vcpu->arch.pio.in) |
2530 | kvm_iodevice_read(pio_dev, vcpu->arch.pio.port, | |
2531 | vcpu->arch.pio.size, | |
de7d789a CO |
2532 | pd); |
2533 | else | |
ad312c7c ZX |
2534 | kvm_iodevice_write(pio_dev, vcpu->arch.pio.port, |
2535 | vcpu->arch.pio.size, | |
de7d789a CO |
2536 | pd); |
2537 | mutex_unlock(&vcpu->kvm->lock); | |
2538 | } | |
2539 | ||
2540 | static void pio_string_write(struct kvm_io_device *pio_dev, | |
2541 | struct kvm_vcpu *vcpu) | |
2542 | { | |
ad312c7c ZX |
2543 | struct kvm_pio_request *io = &vcpu->arch.pio; |
2544 | void *pd = vcpu->arch.pio_data; | |
de7d789a CO |
2545 | int i; |
2546 | ||
2547 | mutex_lock(&vcpu->kvm->lock); | |
2548 | for (i = 0; i < io->cur_count; i++) { | |
2549 | kvm_iodevice_write(pio_dev, io->port, | |
2550 | io->size, | |
2551 | pd); | |
2552 | pd += io->size; | |
2553 | } | |
2554 | mutex_unlock(&vcpu->kvm->lock); | |
2555 | } | |
2556 | ||
2557 | static struct kvm_io_device *vcpu_find_pio_dev(struct kvm_vcpu *vcpu, | |
92760499 LV |
2558 | gpa_t addr, int len, |
2559 | int is_write) | |
de7d789a | 2560 | { |
92760499 | 2561 | return kvm_io_bus_find_dev(&vcpu->kvm->pio_bus, addr, len, is_write); |
de7d789a CO |
2562 | } |
2563 | ||
2564 | int kvm_emulate_pio(struct kvm_vcpu *vcpu, struct kvm_run *run, int in, | |
2565 | int size, unsigned port) | |
2566 | { | |
2567 | struct kvm_io_device *pio_dev; | |
5fdbf976 | 2568 | unsigned long val; |
de7d789a CO |
2569 | |
2570 | vcpu->run->exit_reason = KVM_EXIT_IO; | |
2571 | vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; | |
ad312c7c | 2572 | vcpu->run->io.size = vcpu->arch.pio.size = size; |
de7d789a | 2573 | vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; |
ad312c7c ZX |
2574 | vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = 1; |
2575 | vcpu->run->io.port = vcpu->arch.pio.port = port; | |
2576 | vcpu->arch.pio.in = in; | |
2577 | vcpu->arch.pio.string = 0; | |
2578 | vcpu->arch.pio.down = 0; | |
ad312c7c | 2579 | vcpu->arch.pio.rep = 0; |
de7d789a | 2580 | |
2714d1d3 FEL |
2581 | if (vcpu->run->io.direction == KVM_EXIT_IO_IN) |
2582 | KVMTRACE_2D(IO_READ, vcpu, vcpu->run->io.port, (u32)size, | |
2583 | handler); | |
2584 | else | |
2585 | KVMTRACE_2D(IO_WRITE, vcpu, vcpu->run->io.port, (u32)size, | |
2586 | handler); | |
2587 | ||
5fdbf976 MT |
2588 | val = kvm_register_read(vcpu, VCPU_REGS_RAX); |
2589 | memcpy(vcpu->arch.pio_data, &val, 4); | |
de7d789a | 2590 | |
92760499 | 2591 | pio_dev = vcpu_find_pio_dev(vcpu, port, size, !in); |
de7d789a | 2592 | if (pio_dev) { |
ad312c7c | 2593 | kernel_pio(pio_dev, vcpu, vcpu->arch.pio_data); |
de7d789a CO |
2594 | complete_pio(vcpu); |
2595 | return 1; | |
2596 | } | |
2597 | return 0; | |
2598 | } | |
2599 | EXPORT_SYMBOL_GPL(kvm_emulate_pio); | |
2600 | ||
2601 | int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, struct kvm_run *run, int in, | |
2602 | int size, unsigned long count, int down, | |
2603 | gva_t address, int rep, unsigned port) | |
2604 | { | |
2605 | unsigned now, in_page; | |
0f346074 | 2606 | int ret = 0; |
de7d789a CO |
2607 | struct kvm_io_device *pio_dev; |
2608 | ||
2609 | vcpu->run->exit_reason = KVM_EXIT_IO; | |
2610 | vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; | |
ad312c7c | 2611 | vcpu->run->io.size = vcpu->arch.pio.size = size; |
de7d789a | 2612 | vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; |
ad312c7c ZX |
2613 | vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = count; |
2614 | vcpu->run->io.port = vcpu->arch.pio.port = port; | |
2615 | vcpu->arch.pio.in = in; | |
2616 | vcpu->arch.pio.string = 1; | |
2617 | vcpu->arch.pio.down = down; | |
ad312c7c | 2618 | vcpu->arch.pio.rep = rep; |
de7d789a | 2619 | |
2714d1d3 FEL |
2620 | if (vcpu->run->io.direction == KVM_EXIT_IO_IN) |
2621 | KVMTRACE_2D(IO_READ, vcpu, vcpu->run->io.port, (u32)size, | |
2622 | handler); | |
2623 | else | |
2624 | KVMTRACE_2D(IO_WRITE, vcpu, vcpu->run->io.port, (u32)size, | |
2625 | handler); | |
2626 | ||
de7d789a CO |
2627 | if (!count) { |
2628 | kvm_x86_ops->skip_emulated_instruction(vcpu); | |
2629 | return 1; | |
2630 | } | |
2631 | ||
2632 | if (!down) | |
2633 | in_page = PAGE_SIZE - offset_in_page(address); | |
2634 | else | |
2635 | in_page = offset_in_page(address) + size; | |
2636 | now = min(count, (unsigned long)in_page / size); | |
0f346074 | 2637 | if (!now) |
de7d789a | 2638 | now = 1; |
de7d789a CO |
2639 | if (down) { |
2640 | /* | |
2641 | * String I/O in reverse. Yuck. Kill the guest, fix later. | |
2642 | */ | |
2643 | pr_unimpl(vcpu, "guest string pio down\n"); | |
c1a5d4f9 | 2644 | kvm_inject_gp(vcpu, 0); |
de7d789a CO |
2645 | return 1; |
2646 | } | |
2647 | vcpu->run->io.count = now; | |
ad312c7c | 2648 | vcpu->arch.pio.cur_count = now; |
de7d789a | 2649 | |
ad312c7c | 2650 | if (vcpu->arch.pio.cur_count == vcpu->arch.pio.count) |
de7d789a CO |
2651 | kvm_x86_ops->skip_emulated_instruction(vcpu); |
2652 | ||
0f346074 | 2653 | vcpu->arch.pio.guest_gva = address; |
de7d789a | 2654 | |
92760499 LV |
2655 | pio_dev = vcpu_find_pio_dev(vcpu, port, |
2656 | vcpu->arch.pio.cur_count, | |
2657 | !vcpu->arch.pio.in); | |
ad312c7c | 2658 | if (!vcpu->arch.pio.in) { |
de7d789a CO |
2659 | /* string PIO write */ |
2660 | ret = pio_copy_data(vcpu); | |
0f346074 IE |
2661 | if (ret == X86EMUL_PROPAGATE_FAULT) { |
2662 | kvm_inject_gp(vcpu, 0); | |
2663 | return 1; | |
2664 | } | |
2665 | if (ret == 0 && pio_dev) { | |
de7d789a CO |
2666 | pio_string_write(pio_dev, vcpu); |
2667 | complete_pio(vcpu); | |
ad312c7c | 2668 | if (vcpu->arch.pio.count == 0) |
de7d789a CO |
2669 | ret = 1; |
2670 | } | |
2671 | } else if (pio_dev) | |
2672 | pr_unimpl(vcpu, "no string pio read support yet, " | |
2673 | "port %x size %d count %ld\n", | |
2674 | port, size, count); | |
2675 | ||
2676 | return ret; | |
2677 | } | |
2678 | EXPORT_SYMBOL_GPL(kvm_emulate_pio_string); | |
2679 | ||
c8076604 GH |
2680 | static void bounce_off(void *info) |
2681 | { | |
2682 | /* nothing */ | |
2683 | } | |
2684 | ||
2685 | static unsigned int ref_freq; | |
2686 | static unsigned long tsc_khz_ref; | |
2687 | ||
2688 | static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, | |
2689 | void *data) | |
2690 | { | |
2691 | struct cpufreq_freqs *freq = data; | |
2692 | struct kvm *kvm; | |
2693 | struct kvm_vcpu *vcpu; | |
2694 | int i, send_ipi = 0; | |
2695 | ||
2696 | if (!ref_freq) | |
2697 | ref_freq = freq->old; | |
2698 | ||
2699 | if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) | |
2700 | return 0; | |
2701 | if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) | |
2702 | return 0; | |
2703 | per_cpu(cpu_tsc_khz, freq->cpu) = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new); | |
2704 | ||
2705 | spin_lock(&kvm_lock); | |
2706 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
2707 | for (i = 0; i < KVM_MAX_VCPUS; ++i) { | |
2708 | vcpu = kvm->vcpus[i]; | |
2709 | if (!vcpu) | |
2710 | continue; | |
2711 | if (vcpu->cpu != freq->cpu) | |
2712 | continue; | |
2713 | if (!kvm_request_guest_time_update(vcpu)) | |
2714 | continue; | |
2715 | if (vcpu->cpu != smp_processor_id()) | |
2716 | send_ipi++; | |
2717 | } | |
2718 | } | |
2719 | spin_unlock(&kvm_lock); | |
2720 | ||
2721 | if (freq->old < freq->new && send_ipi) { | |
2722 | /* | |
2723 | * We upscale the frequency. Must make the guest | |
2724 | * doesn't see old kvmclock values while running with | |
2725 | * the new frequency, otherwise we risk the guest sees | |
2726 | * time go backwards. | |
2727 | * | |
2728 | * In case we update the frequency for another cpu | |
2729 | * (which might be in guest context) send an interrupt | |
2730 | * to kick the cpu out of guest context. Next time | |
2731 | * guest context is entered kvmclock will be updated, | |
2732 | * so the guest will not see stale values. | |
2733 | */ | |
2734 | smp_call_function_single(freq->cpu, bounce_off, NULL, 1); | |
2735 | } | |
2736 | return 0; | |
2737 | } | |
2738 | ||
2739 | static struct notifier_block kvmclock_cpufreq_notifier_block = { | |
2740 | .notifier_call = kvmclock_cpufreq_notifier | |
2741 | }; | |
2742 | ||
f8c16bba | 2743 | int kvm_arch_init(void *opaque) |
043405e1 | 2744 | { |
c8076604 | 2745 | int r, cpu; |
f8c16bba ZX |
2746 | struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque; |
2747 | ||
f8c16bba ZX |
2748 | if (kvm_x86_ops) { |
2749 | printk(KERN_ERR "kvm: already loaded the other module\n"); | |
56c6d28a ZX |
2750 | r = -EEXIST; |
2751 | goto out; | |
f8c16bba ZX |
2752 | } |
2753 | ||
2754 | if (!ops->cpu_has_kvm_support()) { | |
2755 | printk(KERN_ERR "kvm: no hardware support\n"); | |
56c6d28a ZX |
2756 | r = -EOPNOTSUPP; |
2757 | goto out; | |
f8c16bba ZX |
2758 | } |
2759 | if (ops->disabled_by_bios()) { | |
2760 | printk(KERN_ERR "kvm: disabled by bios\n"); | |
56c6d28a ZX |
2761 | r = -EOPNOTSUPP; |
2762 | goto out; | |
f8c16bba ZX |
2763 | } |
2764 | ||
97db56ce AK |
2765 | r = kvm_mmu_module_init(); |
2766 | if (r) | |
2767 | goto out; | |
2768 | ||
2769 | kvm_init_msr_list(); | |
2770 | ||
f8c16bba | 2771 | kvm_x86_ops = ops; |
56c6d28a | 2772 | kvm_mmu_set_nonpresent_ptes(0ull, 0ull); |
7b52345e SY |
2773 | kvm_mmu_set_base_ptes(PT_PRESENT_MASK); |
2774 | kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK, | |
64d4d521 | 2775 | PT_DIRTY_MASK, PT64_NX_MASK, 0, 0); |
c8076604 GH |
2776 | |
2777 | for_each_possible_cpu(cpu) | |
2778 | per_cpu(cpu_tsc_khz, cpu) = tsc_khz; | |
2779 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { | |
2780 | tsc_khz_ref = tsc_khz; | |
2781 | cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, | |
2782 | CPUFREQ_TRANSITION_NOTIFIER); | |
2783 | } | |
2784 | ||
f8c16bba | 2785 | return 0; |
56c6d28a ZX |
2786 | |
2787 | out: | |
56c6d28a | 2788 | return r; |
043405e1 | 2789 | } |
8776e519 | 2790 | |
f8c16bba ZX |
2791 | void kvm_arch_exit(void) |
2792 | { | |
888d256e JK |
2793 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) |
2794 | cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, | |
2795 | CPUFREQ_TRANSITION_NOTIFIER); | |
f8c16bba | 2796 | kvm_x86_ops = NULL; |
56c6d28a ZX |
2797 | kvm_mmu_module_exit(); |
2798 | } | |
f8c16bba | 2799 | |
8776e519 HB |
2800 | int kvm_emulate_halt(struct kvm_vcpu *vcpu) |
2801 | { | |
2802 | ++vcpu->stat.halt_exits; | |
2714d1d3 | 2803 | KVMTRACE_0D(HLT, vcpu, handler); |
8776e519 | 2804 | if (irqchip_in_kernel(vcpu->kvm)) { |
a4535290 | 2805 | vcpu->arch.mp_state = KVM_MP_STATE_HALTED; |
8776e519 HB |
2806 | return 1; |
2807 | } else { | |
2808 | vcpu->run->exit_reason = KVM_EXIT_HLT; | |
2809 | return 0; | |
2810 | } | |
2811 | } | |
2812 | EXPORT_SYMBOL_GPL(kvm_emulate_halt); | |
2813 | ||
2f333bcb MT |
2814 | static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0, |
2815 | unsigned long a1) | |
2816 | { | |
2817 | if (is_long_mode(vcpu)) | |
2818 | return a0; | |
2819 | else | |
2820 | return a0 | ((gpa_t)a1 << 32); | |
2821 | } | |
2822 | ||
8776e519 HB |
2823 | int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) |
2824 | { | |
2825 | unsigned long nr, a0, a1, a2, a3, ret; | |
2f333bcb | 2826 | int r = 1; |
8776e519 | 2827 | |
5fdbf976 MT |
2828 | nr = kvm_register_read(vcpu, VCPU_REGS_RAX); |
2829 | a0 = kvm_register_read(vcpu, VCPU_REGS_RBX); | |
2830 | a1 = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
2831 | a2 = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
2832 | a3 = kvm_register_read(vcpu, VCPU_REGS_RSI); | |
8776e519 | 2833 | |
2714d1d3 FEL |
2834 | KVMTRACE_1D(VMMCALL, vcpu, (u32)nr, handler); |
2835 | ||
8776e519 HB |
2836 | if (!is_long_mode(vcpu)) { |
2837 | nr &= 0xFFFFFFFF; | |
2838 | a0 &= 0xFFFFFFFF; | |
2839 | a1 &= 0xFFFFFFFF; | |
2840 | a2 &= 0xFFFFFFFF; | |
2841 | a3 &= 0xFFFFFFFF; | |
2842 | } | |
2843 | ||
2844 | switch (nr) { | |
b93463aa AK |
2845 | case KVM_HC_VAPIC_POLL_IRQ: |
2846 | ret = 0; | |
2847 | break; | |
2f333bcb MT |
2848 | case KVM_HC_MMU_OP: |
2849 | r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret); | |
2850 | break; | |
8776e519 HB |
2851 | default: |
2852 | ret = -KVM_ENOSYS; | |
2853 | break; | |
2854 | } | |
5fdbf976 | 2855 | kvm_register_write(vcpu, VCPU_REGS_RAX, ret); |
f11c3a8d | 2856 | ++vcpu->stat.hypercalls; |
2f333bcb | 2857 | return r; |
8776e519 HB |
2858 | } |
2859 | EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); | |
2860 | ||
2861 | int kvm_fix_hypercall(struct kvm_vcpu *vcpu) | |
2862 | { | |
2863 | char instruction[3]; | |
2864 | int ret = 0; | |
5fdbf976 | 2865 | unsigned long rip = kvm_rip_read(vcpu); |
8776e519 | 2866 | |
8776e519 HB |
2867 | |
2868 | /* | |
2869 | * Blow out the MMU to ensure that no other VCPU has an active mapping | |
2870 | * to ensure that the updated hypercall appears atomically across all | |
2871 | * VCPUs. | |
2872 | */ | |
2873 | kvm_mmu_zap_all(vcpu->kvm); | |
2874 | ||
8776e519 | 2875 | kvm_x86_ops->patch_hypercall(vcpu, instruction); |
5fdbf976 | 2876 | if (emulator_write_emulated(rip, instruction, 3, vcpu) |
8776e519 HB |
2877 | != X86EMUL_CONTINUE) |
2878 | ret = -EFAULT; | |
2879 | ||
8776e519 HB |
2880 | return ret; |
2881 | } | |
2882 | ||
2883 | static u64 mk_cr_64(u64 curr_cr, u32 new_val) | |
2884 | { | |
2885 | return (curr_cr & ~((1ULL << 32) - 1)) | new_val; | |
2886 | } | |
2887 | ||
2888 | void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base) | |
2889 | { | |
2890 | struct descriptor_table dt = { limit, base }; | |
2891 | ||
2892 | kvm_x86_ops->set_gdt(vcpu, &dt); | |
2893 | } | |
2894 | ||
2895 | void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base) | |
2896 | { | |
2897 | struct descriptor_table dt = { limit, base }; | |
2898 | ||
2899 | kvm_x86_ops->set_idt(vcpu, &dt); | |
2900 | } | |
2901 | ||
2902 | void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw, | |
2903 | unsigned long *rflags) | |
2904 | { | |
2d3ad1f4 | 2905 | kvm_lmsw(vcpu, msw); |
8776e519 HB |
2906 | *rflags = kvm_x86_ops->get_rflags(vcpu); |
2907 | } | |
2908 | ||
2909 | unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr) | |
2910 | { | |
54e445ca JR |
2911 | unsigned long value; |
2912 | ||
8776e519 HB |
2913 | kvm_x86_ops->decache_cr4_guest_bits(vcpu); |
2914 | switch (cr) { | |
2915 | case 0: | |
54e445ca JR |
2916 | value = vcpu->arch.cr0; |
2917 | break; | |
8776e519 | 2918 | case 2: |
54e445ca JR |
2919 | value = vcpu->arch.cr2; |
2920 | break; | |
8776e519 | 2921 | case 3: |
54e445ca JR |
2922 | value = vcpu->arch.cr3; |
2923 | break; | |
8776e519 | 2924 | case 4: |
54e445ca JR |
2925 | value = vcpu->arch.cr4; |
2926 | break; | |
152ff9be | 2927 | case 8: |
54e445ca JR |
2928 | value = kvm_get_cr8(vcpu); |
2929 | break; | |
8776e519 | 2930 | default: |
b8688d51 | 2931 | vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr); |
8776e519 HB |
2932 | return 0; |
2933 | } | |
54e445ca JR |
2934 | KVMTRACE_3D(CR_READ, vcpu, (u32)cr, (u32)value, |
2935 | (u32)((u64)value >> 32), handler); | |
2936 | ||
2937 | return value; | |
8776e519 HB |
2938 | } |
2939 | ||
2940 | void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long val, | |
2941 | unsigned long *rflags) | |
2942 | { | |
54e445ca JR |
2943 | KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr, (u32)val, |
2944 | (u32)((u64)val >> 32), handler); | |
2945 | ||
8776e519 HB |
2946 | switch (cr) { |
2947 | case 0: | |
2d3ad1f4 | 2948 | kvm_set_cr0(vcpu, mk_cr_64(vcpu->arch.cr0, val)); |
8776e519 HB |
2949 | *rflags = kvm_x86_ops->get_rflags(vcpu); |
2950 | break; | |
2951 | case 2: | |
ad312c7c | 2952 | vcpu->arch.cr2 = val; |
8776e519 HB |
2953 | break; |
2954 | case 3: | |
2d3ad1f4 | 2955 | kvm_set_cr3(vcpu, val); |
8776e519 HB |
2956 | break; |
2957 | case 4: | |
2d3ad1f4 | 2958 | kvm_set_cr4(vcpu, mk_cr_64(vcpu->arch.cr4, val)); |
8776e519 | 2959 | break; |
152ff9be | 2960 | case 8: |
2d3ad1f4 | 2961 | kvm_set_cr8(vcpu, val & 0xfUL); |
152ff9be | 2962 | break; |
8776e519 | 2963 | default: |
b8688d51 | 2964 | vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr); |
8776e519 HB |
2965 | } |
2966 | } | |
2967 | ||
07716717 DK |
2968 | static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i) |
2969 | { | |
ad312c7c ZX |
2970 | struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i]; |
2971 | int j, nent = vcpu->arch.cpuid_nent; | |
07716717 DK |
2972 | |
2973 | e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT; | |
2974 | /* when no next entry is found, the current entry[i] is reselected */ | |
0fdf8e59 | 2975 | for (j = i + 1; ; j = (j + 1) % nent) { |
ad312c7c | 2976 | struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j]; |
07716717 DK |
2977 | if (ej->function == e->function) { |
2978 | ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT; | |
2979 | return j; | |
2980 | } | |
2981 | } | |
2982 | return 0; /* silence gcc, even though control never reaches here */ | |
2983 | } | |
2984 | ||
2985 | /* find an entry with matching function, matching index (if needed), and that | |
2986 | * should be read next (if it's stateful) */ | |
2987 | static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e, | |
2988 | u32 function, u32 index) | |
2989 | { | |
2990 | if (e->function != function) | |
2991 | return 0; | |
2992 | if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index) | |
2993 | return 0; | |
2994 | if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) && | |
19355475 | 2995 | !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT)) |
07716717 DK |
2996 | return 0; |
2997 | return 1; | |
2998 | } | |
2999 | ||
d8017474 AG |
3000 | struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu, |
3001 | u32 function, u32 index) | |
8776e519 HB |
3002 | { |
3003 | int i; | |
d8017474 | 3004 | struct kvm_cpuid_entry2 *best = NULL; |
8776e519 | 3005 | |
ad312c7c | 3006 | for (i = 0; i < vcpu->arch.cpuid_nent; ++i) { |
d8017474 AG |
3007 | struct kvm_cpuid_entry2 *e; |
3008 | ||
ad312c7c | 3009 | e = &vcpu->arch.cpuid_entries[i]; |
07716717 DK |
3010 | if (is_matching_cpuid_entry(e, function, index)) { |
3011 | if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) | |
3012 | move_to_next_stateful_cpuid_entry(vcpu, i); | |
8776e519 HB |
3013 | best = e; |
3014 | break; | |
3015 | } | |
3016 | /* | |
3017 | * Both basic or both extended? | |
3018 | */ | |
3019 | if (((e->function ^ function) & 0x80000000) == 0) | |
3020 | if (!best || e->function > best->function) | |
3021 | best = e; | |
3022 | } | |
d8017474 AG |
3023 | return best; |
3024 | } | |
3025 | ||
82725b20 DE |
3026 | int cpuid_maxphyaddr(struct kvm_vcpu *vcpu) |
3027 | { | |
3028 | struct kvm_cpuid_entry2 *best; | |
3029 | ||
3030 | best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0); | |
3031 | if (best) | |
3032 | return best->eax & 0xff; | |
3033 | return 36; | |
3034 | } | |
3035 | ||
d8017474 AG |
3036 | void kvm_emulate_cpuid(struct kvm_vcpu *vcpu) |
3037 | { | |
3038 | u32 function, index; | |
3039 | struct kvm_cpuid_entry2 *best; | |
3040 | ||
3041 | function = kvm_register_read(vcpu, VCPU_REGS_RAX); | |
3042 | index = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
3043 | kvm_register_write(vcpu, VCPU_REGS_RAX, 0); | |
3044 | kvm_register_write(vcpu, VCPU_REGS_RBX, 0); | |
3045 | kvm_register_write(vcpu, VCPU_REGS_RCX, 0); | |
3046 | kvm_register_write(vcpu, VCPU_REGS_RDX, 0); | |
3047 | best = kvm_find_cpuid_entry(vcpu, function, index); | |
8776e519 | 3048 | if (best) { |
5fdbf976 MT |
3049 | kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax); |
3050 | kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx); | |
3051 | kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx); | |
3052 | kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx); | |
8776e519 | 3053 | } |
8776e519 | 3054 | kvm_x86_ops->skip_emulated_instruction(vcpu); |
2714d1d3 | 3055 | KVMTRACE_5D(CPUID, vcpu, function, |
5fdbf976 MT |
3056 | (u32)kvm_register_read(vcpu, VCPU_REGS_RAX), |
3057 | (u32)kvm_register_read(vcpu, VCPU_REGS_RBX), | |
3058 | (u32)kvm_register_read(vcpu, VCPU_REGS_RCX), | |
3059 | (u32)kvm_register_read(vcpu, VCPU_REGS_RDX), handler); | |
8776e519 HB |
3060 | } |
3061 | EXPORT_SYMBOL_GPL(kvm_emulate_cpuid); | |
d0752060 | 3062 | |
b6c7a5dc HB |
3063 | /* |
3064 | * Check if userspace requested an interrupt window, and that the | |
3065 | * interrupt window is open. | |
3066 | * | |
3067 | * No need to exit to userspace if we already have an interrupt queued. | |
3068 | */ | |
3069 | static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu, | |
3070 | struct kvm_run *kvm_run) | |
3071 | { | |
ad312c7c | 3072 | return (!vcpu->arch.irq_summary && |
b6c7a5dc | 3073 | kvm_run->request_interrupt_window && |
ad312c7c | 3074 | vcpu->arch.interrupt_window_open && |
b6c7a5dc HB |
3075 | (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_IF)); |
3076 | } | |
3077 | ||
3078 | static void post_kvm_run_save(struct kvm_vcpu *vcpu, | |
3079 | struct kvm_run *kvm_run) | |
3080 | { | |
3081 | kvm_run->if_flag = (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_IF) != 0; | |
2d3ad1f4 | 3082 | kvm_run->cr8 = kvm_get_cr8(vcpu); |
b6c7a5dc | 3083 | kvm_run->apic_base = kvm_get_apic_base(vcpu); |
4531220b | 3084 | if (irqchip_in_kernel(vcpu->kvm)) |
b6c7a5dc | 3085 | kvm_run->ready_for_interrupt_injection = 1; |
4531220b | 3086 | else |
b6c7a5dc | 3087 | kvm_run->ready_for_interrupt_injection = |
ad312c7c ZX |
3088 | (vcpu->arch.interrupt_window_open && |
3089 | vcpu->arch.irq_summary == 0); | |
b6c7a5dc HB |
3090 | } |
3091 | ||
b93463aa AK |
3092 | static void vapic_enter(struct kvm_vcpu *vcpu) |
3093 | { | |
3094 | struct kvm_lapic *apic = vcpu->arch.apic; | |
3095 | struct page *page; | |
3096 | ||
3097 | if (!apic || !apic->vapic_addr) | |
3098 | return; | |
3099 | ||
3100 | page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT); | |
72dc67a6 IE |
3101 | |
3102 | vcpu->arch.apic->vapic_page = page; | |
b93463aa AK |
3103 | } |
3104 | ||
3105 | static void vapic_exit(struct kvm_vcpu *vcpu) | |
3106 | { | |
3107 | struct kvm_lapic *apic = vcpu->arch.apic; | |
3108 | ||
3109 | if (!apic || !apic->vapic_addr) | |
3110 | return; | |
3111 | ||
f8b78fa3 | 3112 | down_read(&vcpu->kvm->slots_lock); |
b93463aa AK |
3113 | kvm_release_page_dirty(apic->vapic_page); |
3114 | mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT); | |
f8b78fa3 | 3115 | up_read(&vcpu->kvm->slots_lock); |
b93463aa AK |
3116 | } |
3117 | ||
d7690175 | 3118 | static int vcpu_enter_guest(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
b6c7a5dc HB |
3119 | { |
3120 | int r; | |
3121 | ||
2e53d63a MT |
3122 | if (vcpu->requests) |
3123 | if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests)) | |
3124 | kvm_mmu_unload(vcpu); | |
3125 | ||
b6c7a5dc HB |
3126 | r = kvm_mmu_reload(vcpu); |
3127 | if (unlikely(r)) | |
3128 | goto out; | |
3129 | ||
2f52d58c AK |
3130 | if (vcpu->requests) { |
3131 | if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests)) | |
2f599714 | 3132 | __kvm_migrate_timers(vcpu); |
c8076604 GH |
3133 | if (test_and_clear_bit(KVM_REQ_KVMCLOCK_UPDATE, &vcpu->requests)) |
3134 | kvm_write_guest_time(vcpu); | |
4731d4c7 MT |
3135 | if (test_and_clear_bit(KVM_REQ_MMU_SYNC, &vcpu->requests)) |
3136 | kvm_mmu_sync_roots(vcpu); | |
d4acf7e7 MT |
3137 | if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests)) |
3138 | kvm_x86_ops->tlb_flush(vcpu); | |
b93463aa AK |
3139 | if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS, |
3140 | &vcpu->requests)) { | |
3141 | kvm_run->exit_reason = KVM_EXIT_TPR_ACCESS; | |
3142 | r = 0; | |
3143 | goto out; | |
3144 | } | |
71c4dfaf JR |
3145 | if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) { |
3146 | kvm_run->exit_reason = KVM_EXIT_SHUTDOWN; | |
3147 | r = 0; | |
3148 | goto out; | |
3149 | } | |
2f52d58c | 3150 | } |
b93463aa | 3151 | |
b6c7a5dc HB |
3152 | preempt_disable(); |
3153 | ||
3154 | kvm_x86_ops->prepare_guest_switch(vcpu); | |
3155 | kvm_load_guest_fpu(vcpu); | |
3156 | ||
3157 | local_irq_disable(); | |
3158 | ||
d7690175 | 3159 | if (vcpu->requests || need_resched() || signal_pending(current)) { |
6c142801 AK |
3160 | local_irq_enable(); |
3161 | preempt_enable(); | |
3162 | r = 1; | |
3163 | goto out; | |
3164 | } | |
3165 | ||
e9571ed5 MT |
3166 | vcpu->guest_mode = 1; |
3167 | /* | |
3168 | * Make sure that guest_mode assignment won't happen after | |
3169 | * testing the pending IRQ vector bitmap. | |
3170 | */ | |
3171 | smp_wmb(); | |
3172 | ||
ad312c7c | 3173 | if (vcpu->arch.exception.pending) |
298101da AK |
3174 | __queue_exception(vcpu); |
3175 | else if (irqchip_in_kernel(vcpu->kvm)) | |
b6c7a5dc | 3176 | kvm_x86_ops->inject_pending_irq(vcpu); |
eb9774f0 | 3177 | else |
b6c7a5dc HB |
3178 | kvm_x86_ops->inject_pending_vectors(vcpu, kvm_run); |
3179 | ||
b93463aa AK |
3180 | kvm_lapic_sync_to_vapic(vcpu); |
3181 | ||
3200f405 MT |
3182 | up_read(&vcpu->kvm->slots_lock); |
3183 | ||
b6c7a5dc HB |
3184 | kvm_guest_enter(); |
3185 | ||
42dbaa5a JK |
3186 | get_debugreg(vcpu->arch.host_dr6, 6); |
3187 | get_debugreg(vcpu->arch.host_dr7, 7); | |
3188 | if (unlikely(vcpu->arch.switch_db_regs)) { | |
3189 | get_debugreg(vcpu->arch.host_db[0], 0); | |
3190 | get_debugreg(vcpu->arch.host_db[1], 1); | |
3191 | get_debugreg(vcpu->arch.host_db[2], 2); | |
3192 | get_debugreg(vcpu->arch.host_db[3], 3); | |
3193 | ||
3194 | set_debugreg(0, 7); | |
3195 | set_debugreg(vcpu->arch.eff_db[0], 0); | |
3196 | set_debugreg(vcpu->arch.eff_db[1], 1); | |
3197 | set_debugreg(vcpu->arch.eff_db[2], 2); | |
3198 | set_debugreg(vcpu->arch.eff_db[3], 3); | |
3199 | } | |
b6c7a5dc | 3200 | |
2714d1d3 | 3201 | KVMTRACE_0D(VMENTRY, vcpu, entryexit); |
b6c7a5dc HB |
3202 | kvm_x86_ops->run(vcpu, kvm_run); |
3203 | ||
42dbaa5a JK |
3204 | if (unlikely(vcpu->arch.switch_db_regs)) { |
3205 | set_debugreg(0, 7); | |
3206 | set_debugreg(vcpu->arch.host_db[0], 0); | |
3207 | set_debugreg(vcpu->arch.host_db[1], 1); | |
3208 | set_debugreg(vcpu->arch.host_db[2], 2); | |
3209 | set_debugreg(vcpu->arch.host_db[3], 3); | |
3210 | } | |
3211 | set_debugreg(vcpu->arch.host_dr6, 6); | |
3212 | set_debugreg(vcpu->arch.host_dr7, 7); | |
3213 | ||
b6c7a5dc HB |
3214 | vcpu->guest_mode = 0; |
3215 | local_irq_enable(); | |
3216 | ||
3217 | ++vcpu->stat.exits; | |
3218 | ||
3219 | /* | |
3220 | * We must have an instruction between local_irq_enable() and | |
3221 | * kvm_guest_exit(), so the timer interrupt isn't delayed by | |
3222 | * the interrupt shadow. The stat.exits increment will do nicely. | |
3223 | * But we need to prevent reordering, hence this barrier(): | |
3224 | */ | |
3225 | barrier(); | |
3226 | ||
3227 | kvm_guest_exit(); | |
3228 | ||
3229 | preempt_enable(); | |
3230 | ||
3200f405 MT |
3231 | down_read(&vcpu->kvm->slots_lock); |
3232 | ||
b6c7a5dc HB |
3233 | /* |
3234 | * Profile KVM exit RIPs: | |
3235 | */ | |
3236 | if (unlikely(prof_on == KVM_PROFILING)) { | |
5fdbf976 MT |
3237 | unsigned long rip = kvm_rip_read(vcpu); |
3238 | profile_hit(KVM_PROFILING, (void *)rip); | |
b6c7a5dc HB |
3239 | } |
3240 | ||
ad312c7c ZX |
3241 | if (vcpu->arch.exception.pending && kvm_x86_ops->exception_injected(vcpu)) |
3242 | vcpu->arch.exception.pending = false; | |
298101da | 3243 | |
b93463aa AK |
3244 | kvm_lapic_sync_from_vapic(vcpu); |
3245 | ||
b6c7a5dc | 3246 | r = kvm_x86_ops->handle_exit(kvm_run, vcpu); |
d7690175 MT |
3247 | out: |
3248 | return r; | |
3249 | } | |
b6c7a5dc | 3250 | |
09cec754 | 3251 | |
d7690175 MT |
3252 | static int __vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
3253 | { | |
3254 | int r; | |
3255 | ||
3256 | if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) { | |
1b10bf31 JK |
3257 | pr_debug("vcpu %d received sipi with vector # %x\n", |
3258 | vcpu->vcpu_id, vcpu->arch.sipi_vector); | |
d7690175 | 3259 | kvm_lapic_reset(vcpu); |
5f179287 | 3260 | r = kvm_arch_vcpu_reset(vcpu); |
d7690175 MT |
3261 | if (r) |
3262 | return r; | |
3263 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; | |
b6c7a5dc HB |
3264 | } |
3265 | ||
d7690175 MT |
3266 | down_read(&vcpu->kvm->slots_lock); |
3267 | vapic_enter(vcpu); | |
3268 | ||
3269 | r = 1; | |
3270 | while (r > 0) { | |
af2152f5 | 3271 | if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE) |
d7690175 MT |
3272 | r = vcpu_enter_guest(vcpu, kvm_run); |
3273 | else { | |
3274 | up_read(&vcpu->kvm->slots_lock); | |
3275 | kvm_vcpu_block(vcpu); | |
3276 | down_read(&vcpu->kvm->slots_lock); | |
3277 | if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests)) | |
09cec754 GN |
3278 | { |
3279 | switch(vcpu->arch.mp_state) { | |
3280 | case KVM_MP_STATE_HALTED: | |
d7690175 | 3281 | vcpu->arch.mp_state = |
09cec754 GN |
3282 | KVM_MP_STATE_RUNNABLE; |
3283 | case KVM_MP_STATE_RUNNABLE: | |
3284 | break; | |
3285 | case KVM_MP_STATE_SIPI_RECEIVED: | |
3286 | default: | |
3287 | r = -EINTR; | |
3288 | break; | |
3289 | } | |
3290 | } | |
d7690175 MT |
3291 | } |
3292 | ||
09cec754 GN |
3293 | if (r <= 0) |
3294 | break; | |
3295 | ||
3296 | clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests); | |
3297 | if (kvm_cpu_has_pending_timer(vcpu)) | |
3298 | kvm_inject_pending_timer_irqs(vcpu); | |
3299 | ||
3300 | if (dm_request_for_irq_injection(vcpu, kvm_run)) { | |
3301 | r = -EINTR; | |
3302 | kvm_run->exit_reason = KVM_EXIT_INTR; | |
3303 | ++vcpu->stat.request_irq_exits; | |
3304 | } | |
3305 | if (signal_pending(current)) { | |
3306 | r = -EINTR; | |
3307 | kvm_run->exit_reason = KVM_EXIT_INTR; | |
3308 | ++vcpu->stat.signal_exits; | |
3309 | } | |
3310 | if (need_resched()) { | |
3311 | up_read(&vcpu->kvm->slots_lock); | |
3312 | kvm_resched(vcpu); | |
3313 | down_read(&vcpu->kvm->slots_lock); | |
d7690175 | 3314 | } |
b6c7a5dc HB |
3315 | } |
3316 | ||
d7690175 | 3317 | up_read(&vcpu->kvm->slots_lock); |
b6c7a5dc HB |
3318 | post_kvm_run_save(vcpu, kvm_run); |
3319 | ||
b93463aa AK |
3320 | vapic_exit(vcpu); |
3321 | ||
b6c7a5dc HB |
3322 | return r; |
3323 | } | |
3324 | ||
3325 | int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
3326 | { | |
3327 | int r; | |
3328 | sigset_t sigsaved; | |
3329 | ||
3330 | vcpu_load(vcpu); | |
3331 | ||
ac9f6dc0 AK |
3332 | if (vcpu->sigset_active) |
3333 | sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved); | |
3334 | ||
a4535290 | 3335 | if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { |
b6c7a5dc | 3336 | kvm_vcpu_block(vcpu); |
d7690175 | 3337 | clear_bit(KVM_REQ_UNHALT, &vcpu->requests); |
ac9f6dc0 AK |
3338 | r = -EAGAIN; |
3339 | goto out; | |
b6c7a5dc HB |
3340 | } |
3341 | ||
b6c7a5dc HB |
3342 | /* re-sync apic's tpr */ |
3343 | if (!irqchip_in_kernel(vcpu->kvm)) | |
2d3ad1f4 | 3344 | kvm_set_cr8(vcpu, kvm_run->cr8); |
b6c7a5dc | 3345 | |
ad312c7c | 3346 | if (vcpu->arch.pio.cur_count) { |
b6c7a5dc HB |
3347 | r = complete_pio(vcpu); |
3348 | if (r) | |
3349 | goto out; | |
3350 | } | |
3351 | #if CONFIG_HAS_IOMEM | |
3352 | if (vcpu->mmio_needed) { | |
3353 | memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8); | |
3354 | vcpu->mmio_read_completed = 1; | |
3355 | vcpu->mmio_needed = 0; | |
3200f405 MT |
3356 | |
3357 | down_read(&vcpu->kvm->slots_lock); | |
b6c7a5dc | 3358 | r = emulate_instruction(vcpu, kvm_run, |
571008da SY |
3359 | vcpu->arch.mmio_fault_cr2, 0, |
3360 | EMULTYPE_NO_DECODE); | |
3200f405 | 3361 | up_read(&vcpu->kvm->slots_lock); |
b6c7a5dc HB |
3362 | if (r == EMULATE_DO_MMIO) { |
3363 | /* | |
3364 | * Read-modify-write. Back to userspace. | |
3365 | */ | |
3366 | r = 0; | |
3367 | goto out; | |
3368 | } | |
3369 | } | |
3370 | #endif | |
5fdbf976 MT |
3371 | if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL) |
3372 | kvm_register_write(vcpu, VCPU_REGS_RAX, | |
3373 | kvm_run->hypercall.ret); | |
b6c7a5dc HB |
3374 | |
3375 | r = __vcpu_run(vcpu, kvm_run); | |
3376 | ||
3377 | out: | |
3378 | if (vcpu->sigset_active) | |
3379 | sigprocmask(SIG_SETMASK, &sigsaved, NULL); | |
3380 | ||
3381 | vcpu_put(vcpu); | |
3382 | return r; | |
3383 | } | |
3384 | ||
3385 | int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) | |
3386 | { | |
3387 | vcpu_load(vcpu); | |
3388 | ||
5fdbf976 MT |
3389 | regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX); |
3390 | regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX); | |
3391 | regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
3392 | regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
3393 | regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI); | |
3394 | regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI); | |
3395 | regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP); | |
3396 | regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP); | |
b6c7a5dc | 3397 | #ifdef CONFIG_X86_64 |
5fdbf976 MT |
3398 | regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8); |
3399 | regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9); | |
3400 | regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10); | |
3401 | regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11); | |
3402 | regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12); | |
3403 | regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13); | |
3404 | regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14); | |
3405 | regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15); | |
b6c7a5dc HB |
3406 | #endif |
3407 | ||
5fdbf976 | 3408 | regs->rip = kvm_rip_read(vcpu); |
b6c7a5dc HB |
3409 | regs->rflags = kvm_x86_ops->get_rflags(vcpu); |
3410 | ||
3411 | /* | |
3412 | * Don't leak debug flags in case they were set for guest debugging | |
3413 | */ | |
d0bfb940 | 3414 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) |
b6c7a5dc HB |
3415 | regs->rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF); |
3416 | ||
3417 | vcpu_put(vcpu); | |
3418 | ||
3419 | return 0; | |
3420 | } | |
3421 | ||
3422 | int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) | |
3423 | { | |
3424 | vcpu_load(vcpu); | |
3425 | ||
5fdbf976 MT |
3426 | kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax); |
3427 | kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx); | |
3428 | kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx); | |
3429 | kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx); | |
3430 | kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi); | |
3431 | kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi); | |
3432 | kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp); | |
3433 | kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp); | |
b6c7a5dc | 3434 | #ifdef CONFIG_X86_64 |
5fdbf976 MT |
3435 | kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8); |
3436 | kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9); | |
3437 | kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10); | |
3438 | kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11); | |
3439 | kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12); | |
3440 | kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13); | |
3441 | kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14); | |
3442 | kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15); | |
3443 | ||
b6c7a5dc HB |
3444 | #endif |
3445 | ||
5fdbf976 | 3446 | kvm_rip_write(vcpu, regs->rip); |
b6c7a5dc HB |
3447 | kvm_x86_ops->set_rflags(vcpu, regs->rflags); |
3448 | ||
b6c7a5dc | 3449 | |
b4f14abd JK |
3450 | vcpu->arch.exception.pending = false; |
3451 | ||
b6c7a5dc HB |
3452 | vcpu_put(vcpu); |
3453 | ||
3454 | return 0; | |
3455 | } | |
3456 | ||
3e6e0aab GT |
3457 | void kvm_get_segment(struct kvm_vcpu *vcpu, |
3458 | struct kvm_segment *var, int seg) | |
b6c7a5dc | 3459 | { |
14af3f3c | 3460 | kvm_x86_ops->get_segment(vcpu, var, seg); |
b6c7a5dc HB |
3461 | } |
3462 | ||
3463 | void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) | |
3464 | { | |
3465 | struct kvm_segment cs; | |
3466 | ||
3e6e0aab | 3467 | kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); |
b6c7a5dc HB |
3468 | *db = cs.db; |
3469 | *l = cs.l; | |
3470 | } | |
3471 | EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits); | |
3472 | ||
3473 | int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, | |
3474 | struct kvm_sregs *sregs) | |
3475 | { | |
3476 | struct descriptor_table dt; | |
3477 | int pending_vec; | |
3478 | ||
3479 | vcpu_load(vcpu); | |
3480 | ||
3e6e0aab GT |
3481 | kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
3482 | kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
3483 | kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
3484 | kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
3485 | kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
3486 | kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 3487 | |
3e6e0aab GT |
3488 | kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
3489 | kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc HB |
3490 | |
3491 | kvm_x86_ops->get_idt(vcpu, &dt); | |
3492 | sregs->idt.limit = dt.limit; | |
3493 | sregs->idt.base = dt.base; | |
3494 | kvm_x86_ops->get_gdt(vcpu, &dt); | |
3495 | sregs->gdt.limit = dt.limit; | |
3496 | sregs->gdt.base = dt.base; | |
3497 | ||
3498 | kvm_x86_ops->decache_cr4_guest_bits(vcpu); | |
ad312c7c ZX |
3499 | sregs->cr0 = vcpu->arch.cr0; |
3500 | sregs->cr2 = vcpu->arch.cr2; | |
3501 | sregs->cr3 = vcpu->arch.cr3; | |
3502 | sregs->cr4 = vcpu->arch.cr4; | |
2d3ad1f4 | 3503 | sregs->cr8 = kvm_get_cr8(vcpu); |
ad312c7c | 3504 | sregs->efer = vcpu->arch.shadow_efer; |
b6c7a5dc HB |
3505 | sregs->apic_base = kvm_get_apic_base(vcpu); |
3506 | ||
3507 | if (irqchip_in_kernel(vcpu->kvm)) { | |
3508 | memset(sregs->interrupt_bitmap, 0, | |
3509 | sizeof sregs->interrupt_bitmap); | |
3510 | pending_vec = kvm_x86_ops->get_irq(vcpu); | |
3511 | if (pending_vec >= 0) | |
3512 | set_bit(pending_vec, | |
3513 | (unsigned long *)sregs->interrupt_bitmap); | |
3514 | } else | |
ad312c7c | 3515 | memcpy(sregs->interrupt_bitmap, vcpu->arch.irq_pending, |
b6c7a5dc HB |
3516 | sizeof sregs->interrupt_bitmap); |
3517 | ||
3518 | vcpu_put(vcpu); | |
3519 | ||
3520 | return 0; | |
3521 | } | |
3522 | ||
62d9f0db MT |
3523 | int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, |
3524 | struct kvm_mp_state *mp_state) | |
3525 | { | |
3526 | vcpu_load(vcpu); | |
3527 | mp_state->mp_state = vcpu->arch.mp_state; | |
3528 | vcpu_put(vcpu); | |
3529 | return 0; | |
3530 | } | |
3531 | ||
3532 | int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, | |
3533 | struct kvm_mp_state *mp_state) | |
3534 | { | |
3535 | vcpu_load(vcpu); | |
3536 | vcpu->arch.mp_state = mp_state->mp_state; | |
3537 | vcpu_put(vcpu); | |
3538 | return 0; | |
3539 | } | |
3540 | ||
3e6e0aab | 3541 | static void kvm_set_segment(struct kvm_vcpu *vcpu, |
b6c7a5dc HB |
3542 | struct kvm_segment *var, int seg) |
3543 | { | |
14af3f3c | 3544 | kvm_x86_ops->set_segment(vcpu, var, seg); |
b6c7a5dc HB |
3545 | } |
3546 | ||
37817f29 IE |
3547 | static void seg_desct_to_kvm_desct(struct desc_struct *seg_desc, u16 selector, |
3548 | struct kvm_segment *kvm_desct) | |
3549 | { | |
3550 | kvm_desct->base = seg_desc->base0; | |
3551 | kvm_desct->base |= seg_desc->base1 << 16; | |
3552 | kvm_desct->base |= seg_desc->base2 << 24; | |
3553 | kvm_desct->limit = seg_desc->limit0; | |
3554 | kvm_desct->limit |= seg_desc->limit << 16; | |
c93cd3a5 MT |
3555 | if (seg_desc->g) { |
3556 | kvm_desct->limit <<= 12; | |
3557 | kvm_desct->limit |= 0xfff; | |
3558 | } | |
37817f29 IE |
3559 | kvm_desct->selector = selector; |
3560 | kvm_desct->type = seg_desc->type; | |
3561 | kvm_desct->present = seg_desc->p; | |
3562 | kvm_desct->dpl = seg_desc->dpl; | |
3563 | kvm_desct->db = seg_desc->d; | |
3564 | kvm_desct->s = seg_desc->s; | |
3565 | kvm_desct->l = seg_desc->l; | |
3566 | kvm_desct->g = seg_desc->g; | |
3567 | kvm_desct->avl = seg_desc->avl; | |
3568 | if (!selector) | |
3569 | kvm_desct->unusable = 1; | |
3570 | else | |
3571 | kvm_desct->unusable = 0; | |
3572 | kvm_desct->padding = 0; | |
3573 | } | |
3574 | ||
b8222ad2 AS |
3575 | static void get_segment_descriptor_dtable(struct kvm_vcpu *vcpu, |
3576 | u16 selector, | |
3577 | struct descriptor_table *dtable) | |
37817f29 IE |
3578 | { |
3579 | if (selector & 1 << 2) { | |
3580 | struct kvm_segment kvm_seg; | |
3581 | ||
3e6e0aab | 3582 | kvm_get_segment(vcpu, &kvm_seg, VCPU_SREG_LDTR); |
37817f29 IE |
3583 | |
3584 | if (kvm_seg.unusable) | |
3585 | dtable->limit = 0; | |
3586 | else | |
3587 | dtable->limit = kvm_seg.limit; | |
3588 | dtable->base = kvm_seg.base; | |
3589 | } | |
3590 | else | |
3591 | kvm_x86_ops->get_gdt(vcpu, dtable); | |
3592 | } | |
3593 | ||
3594 | /* allowed just for 8 bytes segments */ | |
3595 | static int load_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, | |
3596 | struct desc_struct *seg_desc) | |
3597 | { | |
98899aa0 | 3598 | gpa_t gpa; |
37817f29 IE |
3599 | struct descriptor_table dtable; |
3600 | u16 index = selector >> 3; | |
3601 | ||
b8222ad2 | 3602 | get_segment_descriptor_dtable(vcpu, selector, &dtable); |
37817f29 IE |
3603 | |
3604 | if (dtable.limit < index * 8 + 7) { | |
3605 | kvm_queue_exception_e(vcpu, GP_VECTOR, selector & 0xfffc); | |
3606 | return 1; | |
3607 | } | |
98899aa0 MT |
3608 | gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base); |
3609 | gpa += index * 8; | |
3610 | return kvm_read_guest(vcpu->kvm, gpa, seg_desc, 8); | |
37817f29 IE |
3611 | } |
3612 | ||
3613 | /* allowed just for 8 bytes segments */ | |
3614 | static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, | |
3615 | struct desc_struct *seg_desc) | |
3616 | { | |
98899aa0 | 3617 | gpa_t gpa; |
37817f29 IE |
3618 | struct descriptor_table dtable; |
3619 | u16 index = selector >> 3; | |
3620 | ||
b8222ad2 | 3621 | get_segment_descriptor_dtable(vcpu, selector, &dtable); |
37817f29 IE |
3622 | |
3623 | if (dtable.limit < index * 8 + 7) | |
3624 | return 1; | |
98899aa0 MT |
3625 | gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base); |
3626 | gpa += index * 8; | |
3627 | return kvm_write_guest(vcpu->kvm, gpa, seg_desc, 8); | |
37817f29 IE |
3628 | } |
3629 | ||
3630 | static u32 get_tss_base_addr(struct kvm_vcpu *vcpu, | |
3631 | struct desc_struct *seg_desc) | |
3632 | { | |
3633 | u32 base_addr; | |
3634 | ||
3635 | base_addr = seg_desc->base0; | |
3636 | base_addr |= (seg_desc->base1 << 16); | |
3637 | base_addr |= (seg_desc->base2 << 24); | |
3638 | ||
98899aa0 | 3639 | return vcpu->arch.mmu.gva_to_gpa(vcpu, base_addr); |
37817f29 IE |
3640 | } |
3641 | ||
37817f29 IE |
3642 | static u16 get_segment_selector(struct kvm_vcpu *vcpu, int seg) |
3643 | { | |
3644 | struct kvm_segment kvm_seg; | |
3645 | ||
3e6e0aab | 3646 | kvm_get_segment(vcpu, &kvm_seg, seg); |
37817f29 IE |
3647 | return kvm_seg.selector; |
3648 | } | |
3649 | ||
3650 | static int load_segment_descriptor_to_kvm_desct(struct kvm_vcpu *vcpu, | |
3651 | u16 selector, | |
3652 | struct kvm_segment *kvm_seg) | |
3653 | { | |
3654 | struct desc_struct seg_desc; | |
3655 | ||
3656 | if (load_guest_segment_descriptor(vcpu, selector, &seg_desc)) | |
3657 | return 1; | |
3658 | seg_desct_to_kvm_desct(&seg_desc, selector, kvm_seg); | |
3659 | return 0; | |
3660 | } | |
3661 | ||
2259e3a7 | 3662 | static int kvm_load_realmode_segment(struct kvm_vcpu *vcpu, u16 selector, int seg) |
f4bbd9aa AK |
3663 | { |
3664 | struct kvm_segment segvar = { | |
3665 | .base = selector << 4, | |
3666 | .limit = 0xffff, | |
3667 | .selector = selector, | |
3668 | .type = 3, | |
3669 | .present = 1, | |
3670 | .dpl = 3, | |
3671 | .db = 0, | |
3672 | .s = 1, | |
3673 | .l = 0, | |
3674 | .g = 0, | |
3675 | .avl = 0, | |
3676 | .unusable = 0, | |
3677 | }; | |
3678 | kvm_x86_ops->set_segment(vcpu, &segvar, seg); | |
3679 | return 0; | |
3680 | } | |
3681 | ||
3e6e0aab GT |
3682 | int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, |
3683 | int type_bits, int seg) | |
37817f29 IE |
3684 | { |
3685 | struct kvm_segment kvm_seg; | |
3686 | ||
f4bbd9aa AK |
3687 | if (!(vcpu->arch.cr0 & X86_CR0_PE)) |
3688 | return kvm_load_realmode_segment(vcpu, selector, seg); | |
37817f29 IE |
3689 | if (load_segment_descriptor_to_kvm_desct(vcpu, selector, &kvm_seg)) |
3690 | return 1; | |
3691 | kvm_seg.type |= type_bits; | |
3692 | ||
3693 | if (seg != VCPU_SREG_SS && seg != VCPU_SREG_CS && | |
3694 | seg != VCPU_SREG_LDTR) | |
3695 | if (!kvm_seg.s) | |
3696 | kvm_seg.unusable = 1; | |
3697 | ||
3e6e0aab | 3698 | kvm_set_segment(vcpu, &kvm_seg, seg); |
37817f29 IE |
3699 | return 0; |
3700 | } | |
3701 | ||
3702 | static void save_state_to_tss32(struct kvm_vcpu *vcpu, | |
3703 | struct tss_segment_32 *tss) | |
3704 | { | |
3705 | tss->cr3 = vcpu->arch.cr3; | |
5fdbf976 | 3706 | tss->eip = kvm_rip_read(vcpu); |
37817f29 | 3707 | tss->eflags = kvm_x86_ops->get_rflags(vcpu); |
5fdbf976 MT |
3708 | tss->eax = kvm_register_read(vcpu, VCPU_REGS_RAX); |
3709 | tss->ecx = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
3710 | tss->edx = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
3711 | tss->ebx = kvm_register_read(vcpu, VCPU_REGS_RBX); | |
3712 | tss->esp = kvm_register_read(vcpu, VCPU_REGS_RSP); | |
3713 | tss->ebp = kvm_register_read(vcpu, VCPU_REGS_RBP); | |
3714 | tss->esi = kvm_register_read(vcpu, VCPU_REGS_RSI); | |
3715 | tss->edi = kvm_register_read(vcpu, VCPU_REGS_RDI); | |
37817f29 IE |
3716 | tss->es = get_segment_selector(vcpu, VCPU_SREG_ES); |
3717 | tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS); | |
3718 | tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS); | |
3719 | tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS); | |
3720 | tss->fs = get_segment_selector(vcpu, VCPU_SREG_FS); | |
3721 | tss->gs = get_segment_selector(vcpu, VCPU_SREG_GS); | |
3722 | tss->ldt_selector = get_segment_selector(vcpu, VCPU_SREG_LDTR); | |
37817f29 IE |
3723 | } |
3724 | ||
3725 | static int load_state_from_tss32(struct kvm_vcpu *vcpu, | |
3726 | struct tss_segment_32 *tss) | |
3727 | { | |
3728 | kvm_set_cr3(vcpu, tss->cr3); | |
3729 | ||
5fdbf976 | 3730 | kvm_rip_write(vcpu, tss->eip); |
37817f29 IE |
3731 | kvm_x86_ops->set_rflags(vcpu, tss->eflags | 2); |
3732 | ||
5fdbf976 MT |
3733 | kvm_register_write(vcpu, VCPU_REGS_RAX, tss->eax); |
3734 | kvm_register_write(vcpu, VCPU_REGS_RCX, tss->ecx); | |
3735 | kvm_register_write(vcpu, VCPU_REGS_RDX, tss->edx); | |
3736 | kvm_register_write(vcpu, VCPU_REGS_RBX, tss->ebx); | |
3737 | kvm_register_write(vcpu, VCPU_REGS_RSP, tss->esp); | |
3738 | kvm_register_write(vcpu, VCPU_REGS_RBP, tss->ebp); | |
3739 | kvm_register_write(vcpu, VCPU_REGS_RSI, tss->esi); | |
3740 | kvm_register_write(vcpu, VCPU_REGS_RDI, tss->edi); | |
37817f29 | 3741 | |
3e6e0aab | 3742 | if (kvm_load_segment_descriptor(vcpu, tss->ldt_selector, 0, VCPU_SREG_LDTR)) |
37817f29 IE |
3743 | return 1; |
3744 | ||
3e6e0aab | 3745 | if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES)) |
37817f29 IE |
3746 | return 1; |
3747 | ||
3e6e0aab | 3748 | if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS)) |
37817f29 IE |
3749 | return 1; |
3750 | ||
3e6e0aab | 3751 | if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS)) |
37817f29 IE |
3752 | return 1; |
3753 | ||
3e6e0aab | 3754 | if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS)) |
37817f29 IE |
3755 | return 1; |
3756 | ||
3e6e0aab | 3757 | if (kvm_load_segment_descriptor(vcpu, tss->fs, 1, VCPU_SREG_FS)) |
37817f29 IE |
3758 | return 1; |
3759 | ||
3e6e0aab | 3760 | if (kvm_load_segment_descriptor(vcpu, tss->gs, 1, VCPU_SREG_GS)) |
37817f29 IE |
3761 | return 1; |
3762 | return 0; | |
3763 | } | |
3764 | ||
3765 | static void save_state_to_tss16(struct kvm_vcpu *vcpu, | |
3766 | struct tss_segment_16 *tss) | |
3767 | { | |
5fdbf976 | 3768 | tss->ip = kvm_rip_read(vcpu); |
37817f29 | 3769 | tss->flag = kvm_x86_ops->get_rflags(vcpu); |
5fdbf976 MT |
3770 | tss->ax = kvm_register_read(vcpu, VCPU_REGS_RAX); |
3771 | tss->cx = kvm_register_read(vcpu, VCPU_REGS_RCX); | |
3772 | tss->dx = kvm_register_read(vcpu, VCPU_REGS_RDX); | |
3773 | tss->bx = kvm_register_read(vcpu, VCPU_REGS_RBX); | |
3774 | tss->sp = kvm_register_read(vcpu, VCPU_REGS_RSP); | |
3775 | tss->bp = kvm_register_read(vcpu, VCPU_REGS_RBP); | |
3776 | tss->si = kvm_register_read(vcpu, VCPU_REGS_RSI); | |
3777 | tss->di = kvm_register_read(vcpu, VCPU_REGS_RDI); | |
37817f29 IE |
3778 | |
3779 | tss->es = get_segment_selector(vcpu, VCPU_SREG_ES); | |
3780 | tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS); | |
3781 | tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS); | |
3782 | tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS); | |
3783 | tss->ldt = get_segment_selector(vcpu, VCPU_SREG_LDTR); | |
3784 | tss->prev_task_link = get_segment_selector(vcpu, VCPU_SREG_TR); | |
3785 | } | |
3786 | ||
3787 | static int load_state_from_tss16(struct kvm_vcpu *vcpu, | |
3788 | struct tss_segment_16 *tss) | |
3789 | { | |
5fdbf976 | 3790 | kvm_rip_write(vcpu, tss->ip); |
37817f29 | 3791 | kvm_x86_ops->set_rflags(vcpu, tss->flag | 2); |
5fdbf976 MT |
3792 | kvm_register_write(vcpu, VCPU_REGS_RAX, tss->ax); |
3793 | kvm_register_write(vcpu, VCPU_REGS_RCX, tss->cx); | |
3794 | kvm_register_write(vcpu, VCPU_REGS_RDX, tss->dx); | |
3795 | kvm_register_write(vcpu, VCPU_REGS_RBX, tss->bx); | |
3796 | kvm_register_write(vcpu, VCPU_REGS_RSP, tss->sp); | |
3797 | kvm_register_write(vcpu, VCPU_REGS_RBP, tss->bp); | |
3798 | kvm_register_write(vcpu, VCPU_REGS_RSI, tss->si); | |
3799 | kvm_register_write(vcpu, VCPU_REGS_RDI, tss->di); | |
37817f29 | 3800 | |
3e6e0aab | 3801 | if (kvm_load_segment_descriptor(vcpu, tss->ldt, 0, VCPU_SREG_LDTR)) |
37817f29 IE |
3802 | return 1; |
3803 | ||
3e6e0aab | 3804 | if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES)) |
37817f29 IE |
3805 | return 1; |
3806 | ||
3e6e0aab | 3807 | if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS)) |
37817f29 IE |
3808 | return 1; |
3809 | ||
3e6e0aab | 3810 | if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS)) |
37817f29 IE |
3811 | return 1; |
3812 | ||
3e6e0aab | 3813 | if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS)) |
37817f29 IE |
3814 | return 1; |
3815 | return 0; | |
3816 | } | |
3817 | ||
8b2cf73c | 3818 | static int kvm_task_switch_16(struct kvm_vcpu *vcpu, u16 tss_selector, |
b237ac37 GN |
3819 | u16 old_tss_sel, u32 old_tss_base, |
3820 | struct desc_struct *nseg_desc) | |
37817f29 IE |
3821 | { |
3822 | struct tss_segment_16 tss_segment_16; | |
3823 | int ret = 0; | |
3824 | ||
34198bf8 MT |
3825 | if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_16, |
3826 | sizeof tss_segment_16)) | |
37817f29 IE |
3827 | goto out; |
3828 | ||
3829 | save_state_to_tss16(vcpu, &tss_segment_16); | |
37817f29 | 3830 | |
34198bf8 MT |
3831 | if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_16, |
3832 | sizeof tss_segment_16)) | |
37817f29 | 3833 | goto out; |
34198bf8 MT |
3834 | |
3835 | if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc), | |
3836 | &tss_segment_16, sizeof tss_segment_16)) | |
3837 | goto out; | |
3838 | ||
b237ac37 GN |
3839 | if (old_tss_sel != 0xffff) { |
3840 | tss_segment_16.prev_task_link = old_tss_sel; | |
3841 | ||
3842 | if (kvm_write_guest(vcpu->kvm, | |
3843 | get_tss_base_addr(vcpu, nseg_desc), | |
3844 | &tss_segment_16.prev_task_link, | |
3845 | sizeof tss_segment_16.prev_task_link)) | |
3846 | goto out; | |
3847 | } | |
3848 | ||
37817f29 IE |
3849 | if (load_state_from_tss16(vcpu, &tss_segment_16)) |
3850 | goto out; | |
3851 | ||
3852 | ret = 1; | |
3853 | out: | |
3854 | return ret; | |
3855 | } | |
3856 | ||
8b2cf73c | 3857 | static int kvm_task_switch_32(struct kvm_vcpu *vcpu, u16 tss_selector, |
b237ac37 | 3858 | u16 old_tss_sel, u32 old_tss_base, |
37817f29 IE |
3859 | struct desc_struct *nseg_desc) |
3860 | { | |
3861 | struct tss_segment_32 tss_segment_32; | |
3862 | int ret = 0; | |
3863 | ||
34198bf8 MT |
3864 | if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_32, |
3865 | sizeof tss_segment_32)) | |
37817f29 IE |
3866 | goto out; |
3867 | ||
3868 | save_state_to_tss32(vcpu, &tss_segment_32); | |
37817f29 | 3869 | |
34198bf8 MT |
3870 | if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_32, |
3871 | sizeof tss_segment_32)) | |
3872 | goto out; | |
3873 | ||
3874 | if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc), | |
3875 | &tss_segment_32, sizeof tss_segment_32)) | |
37817f29 | 3876 | goto out; |
34198bf8 | 3877 | |
b237ac37 GN |
3878 | if (old_tss_sel != 0xffff) { |
3879 | tss_segment_32.prev_task_link = old_tss_sel; | |
3880 | ||
3881 | if (kvm_write_guest(vcpu->kvm, | |
3882 | get_tss_base_addr(vcpu, nseg_desc), | |
3883 | &tss_segment_32.prev_task_link, | |
3884 | sizeof tss_segment_32.prev_task_link)) | |
3885 | goto out; | |
3886 | } | |
3887 | ||
37817f29 IE |
3888 | if (load_state_from_tss32(vcpu, &tss_segment_32)) |
3889 | goto out; | |
3890 | ||
3891 | ret = 1; | |
3892 | out: | |
3893 | return ret; | |
3894 | } | |
3895 | ||
3896 | int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason) | |
3897 | { | |
3898 | struct kvm_segment tr_seg; | |
3899 | struct desc_struct cseg_desc; | |
3900 | struct desc_struct nseg_desc; | |
3901 | int ret = 0; | |
34198bf8 MT |
3902 | u32 old_tss_base = get_segment_base(vcpu, VCPU_SREG_TR); |
3903 | u16 old_tss_sel = get_segment_selector(vcpu, VCPU_SREG_TR); | |
37817f29 | 3904 | |
34198bf8 | 3905 | old_tss_base = vcpu->arch.mmu.gva_to_gpa(vcpu, old_tss_base); |
37817f29 | 3906 | |
34198bf8 MT |
3907 | /* FIXME: Handle errors. Failure to read either TSS or their |
3908 | * descriptors should generate a pagefault. | |
3909 | */ | |
37817f29 IE |
3910 | if (load_guest_segment_descriptor(vcpu, tss_selector, &nseg_desc)) |
3911 | goto out; | |
3912 | ||
34198bf8 | 3913 | if (load_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc)) |
37817f29 IE |
3914 | goto out; |
3915 | ||
37817f29 IE |
3916 | if (reason != TASK_SWITCH_IRET) { |
3917 | int cpl; | |
3918 | ||
3919 | cpl = kvm_x86_ops->get_cpl(vcpu); | |
3920 | if ((tss_selector & 3) > nseg_desc.dpl || cpl > nseg_desc.dpl) { | |
3921 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
3922 | return 1; | |
3923 | } | |
3924 | } | |
3925 | ||
3926 | if (!nseg_desc.p || (nseg_desc.limit0 | nseg_desc.limit << 16) < 0x67) { | |
3927 | kvm_queue_exception_e(vcpu, TS_VECTOR, tss_selector & 0xfffc); | |
3928 | return 1; | |
3929 | } | |
3930 | ||
3931 | if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) { | |
3fe913e7 | 3932 | cseg_desc.type &= ~(1 << 1); //clear the B flag |
34198bf8 | 3933 | save_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc); |
37817f29 IE |
3934 | } |
3935 | ||
3936 | if (reason == TASK_SWITCH_IRET) { | |
3937 | u32 eflags = kvm_x86_ops->get_rflags(vcpu); | |
3938 | kvm_x86_ops->set_rflags(vcpu, eflags & ~X86_EFLAGS_NT); | |
3939 | } | |
3940 | ||
64a7ec06 GN |
3941 | /* set back link to prev task only if NT bit is set in eflags |
3942 | note that old_tss_sel is not used afetr this point */ | |
3943 | if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE) | |
3944 | old_tss_sel = 0xffff; | |
37817f29 | 3945 | |
b237ac37 GN |
3946 | /* set back link to prev task only if NT bit is set in eflags |
3947 | note that old_tss_sel is not used afetr this point */ | |
3948 | if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE) | |
3949 | old_tss_sel = 0xffff; | |
3950 | ||
37817f29 | 3951 | if (nseg_desc.type & 8) |
b237ac37 GN |
3952 | ret = kvm_task_switch_32(vcpu, tss_selector, old_tss_sel, |
3953 | old_tss_base, &nseg_desc); | |
37817f29 | 3954 | else |
b237ac37 GN |
3955 | ret = kvm_task_switch_16(vcpu, tss_selector, old_tss_sel, |
3956 | old_tss_base, &nseg_desc); | |
37817f29 IE |
3957 | |
3958 | if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) { | |
3959 | u32 eflags = kvm_x86_ops->get_rflags(vcpu); | |
3960 | kvm_x86_ops->set_rflags(vcpu, eflags | X86_EFLAGS_NT); | |
3961 | } | |
3962 | ||
3963 | if (reason != TASK_SWITCH_IRET) { | |
3fe913e7 | 3964 | nseg_desc.type |= (1 << 1); |
37817f29 IE |
3965 | save_guest_segment_descriptor(vcpu, tss_selector, |
3966 | &nseg_desc); | |
3967 | } | |
3968 | ||
3969 | kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 | X86_CR0_TS); | |
3970 | seg_desct_to_kvm_desct(&nseg_desc, tss_selector, &tr_seg); | |
3971 | tr_seg.type = 11; | |
3e6e0aab | 3972 | kvm_set_segment(vcpu, &tr_seg, VCPU_SREG_TR); |
37817f29 | 3973 | out: |
37817f29 IE |
3974 | return ret; |
3975 | } | |
3976 | EXPORT_SYMBOL_GPL(kvm_task_switch); | |
3977 | ||
b6c7a5dc HB |
3978 | int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, |
3979 | struct kvm_sregs *sregs) | |
3980 | { | |
3981 | int mmu_reset_needed = 0; | |
3982 | int i, pending_vec, max_bits; | |
3983 | struct descriptor_table dt; | |
3984 | ||
3985 | vcpu_load(vcpu); | |
3986 | ||
3987 | dt.limit = sregs->idt.limit; | |
3988 | dt.base = sregs->idt.base; | |
3989 | kvm_x86_ops->set_idt(vcpu, &dt); | |
3990 | dt.limit = sregs->gdt.limit; | |
3991 | dt.base = sregs->gdt.base; | |
3992 | kvm_x86_ops->set_gdt(vcpu, &dt); | |
3993 | ||
ad312c7c ZX |
3994 | vcpu->arch.cr2 = sregs->cr2; |
3995 | mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3; | |
59839dff MT |
3996 | |
3997 | down_read(&vcpu->kvm->slots_lock); | |
3998 | if (gfn_to_memslot(vcpu->kvm, sregs->cr3 >> PAGE_SHIFT)) | |
3999 | vcpu->arch.cr3 = sregs->cr3; | |
4000 | else | |
4001 | set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests); | |
4002 | up_read(&vcpu->kvm->slots_lock); | |
b6c7a5dc | 4003 | |
2d3ad1f4 | 4004 | kvm_set_cr8(vcpu, sregs->cr8); |
b6c7a5dc | 4005 | |
ad312c7c | 4006 | mmu_reset_needed |= vcpu->arch.shadow_efer != sregs->efer; |
b6c7a5dc | 4007 | kvm_x86_ops->set_efer(vcpu, sregs->efer); |
b6c7a5dc HB |
4008 | kvm_set_apic_base(vcpu, sregs->apic_base); |
4009 | ||
4010 | kvm_x86_ops->decache_cr4_guest_bits(vcpu); | |
4011 | ||
ad312c7c | 4012 | mmu_reset_needed |= vcpu->arch.cr0 != sregs->cr0; |
b6c7a5dc | 4013 | kvm_x86_ops->set_cr0(vcpu, sregs->cr0); |
d7306163 | 4014 | vcpu->arch.cr0 = sregs->cr0; |
b6c7a5dc | 4015 | |
ad312c7c | 4016 | mmu_reset_needed |= vcpu->arch.cr4 != sregs->cr4; |
b6c7a5dc HB |
4017 | kvm_x86_ops->set_cr4(vcpu, sregs->cr4); |
4018 | if (!is_long_mode(vcpu) && is_pae(vcpu)) | |
ad312c7c | 4019 | load_pdptrs(vcpu, vcpu->arch.cr3); |
b6c7a5dc HB |
4020 | |
4021 | if (mmu_reset_needed) | |
4022 | kvm_mmu_reset_context(vcpu); | |
4023 | ||
4024 | if (!irqchip_in_kernel(vcpu->kvm)) { | |
ad312c7c ZX |
4025 | memcpy(vcpu->arch.irq_pending, sregs->interrupt_bitmap, |
4026 | sizeof vcpu->arch.irq_pending); | |
4027 | vcpu->arch.irq_summary = 0; | |
4028 | for (i = 0; i < ARRAY_SIZE(vcpu->arch.irq_pending); ++i) | |
4029 | if (vcpu->arch.irq_pending[i]) | |
4030 | __set_bit(i, &vcpu->arch.irq_summary); | |
b6c7a5dc HB |
4031 | } else { |
4032 | max_bits = (sizeof sregs->interrupt_bitmap) << 3; | |
4033 | pending_vec = find_first_bit( | |
4034 | (const unsigned long *)sregs->interrupt_bitmap, | |
4035 | max_bits); | |
4036 | /* Only pending external irq is handled here */ | |
4037 | if (pending_vec < max_bits) { | |
4038 | kvm_x86_ops->set_irq(vcpu, pending_vec); | |
4039 | pr_debug("Set back pending irq %d\n", | |
4040 | pending_vec); | |
4041 | } | |
e4825800 | 4042 | kvm_pic_clear_isr_ack(vcpu->kvm); |
b6c7a5dc HB |
4043 | } |
4044 | ||
3e6e0aab GT |
4045 | kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
4046 | kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
4047 | kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
4048 | kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
4049 | kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
4050 | kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 4051 | |
3e6e0aab GT |
4052 | kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
4053 | kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc | 4054 | |
9c3e4aab MT |
4055 | /* Older userspace won't unhalt the vcpu on reset. */ |
4056 | if (vcpu->vcpu_id == 0 && kvm_rip_read(vcpu) == 0xfff0 && | |
4057 | sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && | |
4058 | !(vcpu->arch.cr0 & X86_CR0_PE)) | |
4059 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; | |
4060 | ||
b6c7a5dc HB |
4061 | vcpu_put(vcpu); |
4062 | ||
4063 | return 0; | |
4064 | } | |
4065 | ||
d0bfb940 JK |
4066 | int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, |
4067 | struct kvm_guest_debug *dbg) | |
b6c7a5dc | 4068 | { |
ae675ef0 | 4069 | int i, r; |
b6c7a5dc HB |
4070 | |
4071 | vcpu_load(vcpu); | |
4072 | ||
ae675ef0 JK |
4073 | if ((dbg->control & (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP)) == |
4074 | (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP)) { | |
4075 | for (i = 0; i < KVM_NR_DB_REGS; ++i) | |
4076 | vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; | |
4077 | vcpu->arch.switch_db_regs = | |
4078 | (dbg->arch.debugreg[7] & DR7_BP_EN_MASK); | |
4079 | } else { | |
4080 | for (i = 0; i < KVM_NR_DB_REGS; i++) | |
4081 | vcpu->arch.eff_db[i] = vcpu->arch.db[i]; | |
4082 | vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK); | |
4083 | } | |
4084 | ||
b6c7a5dc HB |
4085 | r = kvm_x86_ops->set_guest_debug(vcpu, dbg); |
4086 | ||
d0bfb940 JK |
4087 | if (dbg->control & KVM_GUESTDBG_INJECT_DB) |
4088 | kvm_queue_exception(vcpu, DB_VECTOR); | |
4089 | else if (dbg->control & KVM_GUESTDBG_INJECT_BP) | |
4090 | kvm_queue_exception(vcpu, BP_VECTOR); | |
4091 | ||
b6c7a5dc HB |
4092 | vcpu_put(vcpu); |
4093 | ||
4094 | return r; | |
4095 | } | |
4096 | ||
d0752060 HB |
4097 | /* |
4098 | * fxsave fpu state. Taken from x86_64/processor.h. To be killed when | |
4099 | * we have asm/x86/processor.h | |
4100 | */ | |
4101 | struct fxsave { | |
4102 | u16 cwd; | |
4103 | u16 swd; | |
4104 | u16 twd; | |
4105 | u16 fop; | |
4106 | u64 rip; | |
4107 | u64 rdp; | |
4108 | u32 mxcsr; | |
4109 | u32 mxcsr_mask; | |
4110 | u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */ | |
4111 | #ifdef CONFIG_X86_64 | |
4112 | u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */ | |
4113 | #else | |
4114 | u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */ | |
4115 | #endif | |
4116 | }; | |
4117 | ||
8b006791 ZX |
4118 | /* |
4119 | * Translate a guest virtual address to a guest physical address. | |
4120 | */ | |
4121 | int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, | |
4122 | struct kvm_translation *tr) | |
4123 | { | |
4124 | unsigned long vaddr = tr->linear_address; | |
4125 | gpa_t gpa; | |
4126 | ||
4127 | vcpu_load(vcpu); | |
72dc67a6 | 4128 | down_read(&vcpu->kvm->slots_lock); |
ad312c7c | 4129 | gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, vaddr); |
72dc67a6 | 4130 | up_read(&vcpu->kvm->slots_lock); |
8b006791 ZX |
4131 | tr->physical_address = gpa; |
4132 | tr->valid = gpa != UNMAPPED_GVA; | |
4133 | tr->writeable = 1; | |
4134 | tr->usermode = 0; | |
8b006791 ZX |
4135 | vcpu_put(vcpu); |
4136 | ||
4137 | return 0; | |
4138 | } | |
4139 | ||
d0752060 HB |
4140 | int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) |
4141 | { | |
ad312c7c | 4142 | struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image; |
d0752060 HB |
4143 | |
4144 | vcpu_load(vcpu); | |
4145 | ||
4146 | memcpy(fpu->fpr, fxsave->st_space, 128); | |
4147 | fpu->fcw = fxsave->cwd; | |
4148 | fpu->fsw = fxsave->swd; | |
4149 | fpu->ftwx = fxsave->twd; | |
4150 | fpu->last_opcode = fxsave->fop; | |
4151 | fpu->last_ip = fxsave->rip; | |
4152 | fpu->last_dp = fxsave->rdp; | |
4153 | memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space); | |
4154 | ||
4155 | vcpu_put(vcpu); | |
4156 | ||
4157 | return 0; | |
4158 | } | |
4159 | ||
4160 | int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) | |
4161 | { | |
ad312c7c | 4162 | struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image; |
d0752060 HB |
4163 | |
4164 | vcpu_load(vcpu); | |
4165 | ||
4166 | memcpy(fxsave->st_space, fpu->fpr, 128); | |
4167 | fxsave->cwd = fpu->fcw; | |
4168 | fxsave->swd = fpu->fsw; | |
4169 | fxsave->twd = fpu->ftwx; | |
4170 | fxsave->fop = fpu->last_opcode; | |
4171 | fxsave->rip = fpu->last_ip; | |
4172 | fxsave->rdp = fpu->last_dp; | |
4173 | memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space); | |
4174 | ||
4175 | vcpu_put(vcpu); | |
4176 | ||
4177 | return 0; | |
4178 | } | |
4179 | ||
4180 | void fx_init(struct kvm_vcpu *vcpu) | |
4181 | { | |
4182 | unsigned after_mxcsr_mask; | |
4183 | ||
bc1a34f1 AA |
4184 | /* |
4185 | * Touch the fpu the first time in non atomic context as if | |
4186 | * this is the first fpu instruction the exception handler | |
4187 | * will fire before the instruction returns and it'll have to | |
4188 | * allocate ram with GFP_KERNEL. | |
4189 | */ | |
4190 | if (!used_math()) | |
d6e88aec | 4191 | kvm_fx_save(&vcpu->arch.host_fx_image); |
bc1a34f1 | 4192 | |
d0752060 HB |
4193 | /* Initialize guest FPU by resetting ours and saving into guest's */ |
4194 | preempt_disable(); | |
d6e88aec AK |
4195 | kvm_fx_save(&vcpu->arch.host_fx_image); |
4196 | kvm_fx_finit(); | |
4197 | kvm_fx_save(&vcpu->arch.guest_fx_image); | |
4198 | kvm_fx_restore(&vcpu->arch.host_fx_image); | |
d0752060 HB |
4199 | preempt_enable(); |
4200 | ||
ad312c7c | 4201 | vcpu->arch.cr0 |= X86_CR0_ET; |
d0752060 | 4202 | after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space); |
ad312c7c ZX |
4203 | vcpu->arch.guest_fx_image.mxcsr = 0x1f80; |
4204 | memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask, | |
d0752060 HB |
4205 | 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask); |
4206 | } | |
4207 | EXPORT_SYMBOL_GPL(fx_init); | |
4208 | ||
4209 | void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) | |
4210 | { | |
4211 | if (!vcpu->fpu_active || vcpu->guest_fpu_loaded) | |
4212 | return; | |
4213 | ||
4214 | vcpu->guest_fpu_loaded = 1; | |
d6e88aec AK |
4215 | kvm_fx_save(&vcpu->arch.host_fx_image); |
4216 | kvm_fx_restore(&vcpu->arch.guest_fx_image); | |
d0752060 HB |
4217 | } |
4218 | EXPORT_SYMBOL_GPL(kvm_load_guest_fpu); | |
4219 | ||
4220 | void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) | |
4221 | { | |
4222 | if (!vcpu->guest_fpu_loaded) | |
4223 | return; | |
4224 | ||
4225 | vcpu->guest_fpu_loaded = 0; | |
d6e88aec AK |
4226 | kvm_fx_save(&vcpu->arch.guest_fx_image); |
4227 | kvm_fx_restore(&vcpu->arch.host_fx_image); | |
f096ed85 | 4228 | ++vcpu->stat.fpu_reload; |
d0752060 HB |
4229 | } |
4230 | EXPORT_SYMBOL_GPL(kvm_put_guest_fpu); | |
e9b11c17 ZX |
4231 | |
4232 | void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu) | |
4233 | { | |
7f1ea208 JR |
4234 | if (vcpu->arch.time_page) { |
4235 | kvm_release_page_dirty(vcpu->arch.time_page); | |
4236 | vcpu->arch.time_page = NULL; | |
4237 | } | |
4238 | ||
e9b11c17 ZX |
4239 | kvm_x86_ops->vcpu_free(vcpu); |
4240 | } | |
4241 | ||
4242 | struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, | |
4243 | unsigned int id) | |
4244 | { | |
26e5215f AK |
4245 | return kvm_x86_ops->vcpu_create(kvm, id); |
4246 | } | |
e9b11c17 | 4247 | |
26e5215f AK |
4248 | int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) |
4249 | { | |
4250 | int r; | |
e9b11c17 ZX |
4251 | |
4252 | /* We do fxsave: this must be aligned. */ | |
ad312c7c | 4253 | BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF); |
e9b11c17 | 4254 | |
0bed3b56 | 4255 | vcpu->arch.mtrr_state.have_fixed = 1; |
e9b11c17 ZX |
4256 | vcpu_load(vcpu); |
4257 | r = kvm_arch_vcpu_reset(vcpu); | |
4258 | if (r == 0) | |
4259 | r = kvm_mmu_setup(vcpu); | |
4260 | vcpu_put(vcpu); | |
4261 | if (r < 0) | |
4262 | goto free_vcpu; | |
4263 | ||
26e5215f | 4264 | return 0; |
e9b11c17 ZX |
4265 | free_vcpu: |
4266 | kvm_x86_ops->vcpu_free(vcpu); | |
26e5215f | 4267 | return r; |
e9b11c17 ZX |
4268 | } |
4269 | ||
d40ccc62 | 4270 | void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) |
e9b11c17 ZX |
4271 | { |
4272 | vcpu_load(vcpu); | |
4273 | kvm_mmu_unload(vcpu); | |
4274 | vcpu_put(vcpu); | |
4275 | ||
4276 | kvm_x86_ops->vcpu_free(vcpu); | |
4277 | } | |
4278 | ||
4279 | int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu) | |
4280 | { | |
448fa4a9 JK |
4281 | vcpu->arch.nmi_pending = false; |
4282 | vcpu->arch.nmi_injected = false; | |
4283 | ||
42dbaa5a JK |
4284 | vcpu->arch.switch_db_regs = 0; |
4285 | memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); | |
4286 | vcpu->arch.dr6 = DR6_FIXED_1; | |
4287 | vcpu->arch.dr7 = DR7_FIXED_1; | |
4288 | ||
e9b11c17 ZX |
4289 | return kvm_x86_ops->vcpu_reset(vcpu); |
4290 | } | |
4291 | ||
4292 | void kvm_arch_hardware_enable(void *garbage) | |
4293 | { | |
4294 | kvm_x86_ops->hardware_enable(garbage); | |
4295 | } | |
4296 | ||
4297 | void kvm_arch_hardware_disable(void *garbage) | |
4298 | { | |
4299 | kvm_x86_ops->hardware_disable(garbage); | |
4300 | } | |
4301 | ||
4302 | int kvm_arch_hardware_setup(void) | |
4303 | { | |
4304 | return kvm_x86_ops->hardware_setup(); | |
4305 | } | |
4306 | ||
4307 | void kvm_arch_hardware_unsetup(void) | |
4308 | { | |
4309 | kvm_x86_ops->hardware_unsetup(); | |
4310 | } | |
4311 | ||
4312 | void kvm_arch_check_processor_compat(void *rtn) | |
4313 | { | |
4314 | kvm_x86_ops->check_processor_compatibility(rtn); | |
4315 | } | |
4316 | ||
4317 | int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) | |
4318 | { | |
4319 | struct page *page; | |
4320 | struct kvm *kvm; | |
4321 | int r; | |
4322 | ||
4323 | BUG_ON(vcpu->kvm == NULL); | |
4324 | kvm = vcpu->kvm; | |
4325 | ||
ad312c7c | 4326 | vcpu->arch.mmu.root_hpa = INVALID_PAGE; |
e9b11c17 | 4327 | if (!irqchip_in_kernel(kvm) || vcpu->vcpu_id == 0) |
a4535290 | 4328 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
e9b11c17 | 4329 | else |
a4535290 | 4330 | vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; |
e9b11c17 ZX |
4331 | |
4332 | page = alloc_page(GFP_KERNEL | __GFP_ZERO); | |
4333 | if (!page) { | |
4334 | r = -ENOMEM; | |
4335 | goto fail; | |
4336 | } | |
ad312c7c | 4337 | vcpu->arch.pio_data = page_address(page); |
e9b11c17 ZX |
4338 | |
4339 | r = kvm_mmu_create(vcpu); | |
4340 | if (r < 0) | |
4341 | goto fail_free_pio_data; | |
4342 | ||
4343 | if (irqchip_in_kernel(kvm)) { | |
4344 | r = kvm_create_lapic(vcpu); | |
4345 | if (r < 0) | |
4346 | goto fail_mmu_destroy; | |
4347 | } | |
4348 | ||
4349 | return 0; | |
4350 | ||
4351 | fail_mmu_destroy: | |
4352 | kvm_mmu_destroy(vcpu); | |
4353 | fail_free_pio_data: | |
ad312c7c | 4354 | free_page((unsigned long)vcpu->arch.pio_data); |
e9b11c17 ZX |
4355 | fail: |
4356 | return r; | |
4357 | } | |
4358 | ||
4359 | void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) | |
4360 | { | |
4361 | kvm_free_lapic(vcpu); | |
3200f405 | 4362 | down_read(&vcpu->kvm->slots_lock); |
e9b11c17 | 4363 | kvm_mmu_destroy(vcpu); |
3200f405 | 4364 | up_read(&vcpu->kvm->slots_lock); |
ad312c7c | 4365 | free_page((unsigned long)vcpu->arch.pio_data); |
e9b11c17 | 4366 | } |
d19a9cd2 ZX |
4367 | |
4368 | struct kvm *kvm_arch_create_vm(void) | |
4369 | { | |
4370 | struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL); | |
4371 | ||
4372 | if (!kvm) | |
4373 | return ERR_PTR(-ENOMEM); | |
4374 | ||
f05e70ac | 4375 | INIT_LIST_HEAD(&kvm->arch.active_mmu_pages); |
4d5c5d0f | 4376 | INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); |
d19a9cd2 | 4377 | |
5550af4d SY |
4378 | /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ |
4379 | set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); | |
4380 | ||
53f658b3 MT |
4381 | rdtscll(kvm->arch.vm_init_tsc); |
4382 | ||
d19a9cd2 ZX |
4383 | return kvm; |
4384 | } | |
4385 | ||
4386 | static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) | |
4387 | { | |
4388 | vcpu_load(vcpu); | |
4389 | kvm_mmu_unload(vcpu); | |
4390 | vcpu_put(vcpu); | |
4391 | } | |
4392 | ||
4393 | static void kvm_free_vcpus(struct kvm *kvm) | |
4394 | { | |
4395 | unsigned int i; | |
4396 | ||
4397 | /* | |
4398 | * Unpin any mmu pages first. | |
4399 | */ | |
4400 | for (i = 0; i < KVM_MAX_VCPUS; ++i) | |
4401 | if (kvm->vcpus[i]) | |
4402 | kvm_unload_vcpu_mmu(kvm->vcpus[i]); | |
4403 | for (i = 0; i < KVM_MAX_VCPUS; ++i) { | |
4404 | if (kvm->vcpus[i]) { | |
4405 | kvm_arch_vcpu_free(kvm->vcpus[i]); | |
4406 | kvm->vcpus[i] = NULL; | |
4407 | } | |
4408 | } | |
4409 | ||
4410 | } | |
4411 | ||
ad8ba2cd SY |
4412 | void kvm_arch_sync_events(struct kvm *kvm) |
4413 | { | |
ba4cef31 | 4414 | kvm_free_all_assigned_devices(kvm); |
ad8ba2cd SY |
4415 | } |
4416 | ||
d19a9cd2 ZX |
4417 | void kvm_arch_destroy_vm(struct kvm *kvm) |
4418 | { | |
6eb55818 | 4419 | kvm_iommu_unmap_guest(kvm); |
7837699f | 4420 | kvm_free_pit(kvm); |
d7deeeb0 ZX |
4421 | kfree(kvm->arch.vpic); |
4422 | kfree(kvm->arch.vioapic); | |
d19a9cd2 ZX |
4423 | kvm_free_vcpus(kvm); |
4424 | kvm_free_physmem(kvm); | |
3d45830c AK |
4425 | if (kvm->arch.apic_access_page) |
4426 | put_page(kvm->arch.apic_access_page); | |
b7ebfb05 SY |
4427 | if (kvm->arch.ept_identity_pagetable) |
4428 | put_page(kvm->arch.ept_identity_pagetable); | |
d19a9cd2 ZX |
4429 | kfree(kvm); |
4430 | } | |
0de10343 ZX |
4431 | |
4432 | int kvm_arch_set_memory_region(struct kvm *kvm, | |
4433 | struct kvm_userspace_memory_region *mem, | |
4434 | struct kvm_memory_slot old, | |
4435 | int user_alloc) | |
4436 | { | |
4437 | int npages = mem->memory_size >> PAGE_SHIFT; | |
4438 | struct kvm_memory_slot *memslot = &kvm->memslots[mem->slot]; | |
4439 | ||
4440 | /*To keep backward compatibility with older userspace, | |
4441 | *x86 needs to hanlde !user_alloc case. | |
4442 | */ | |
4443 | if (!user_alloc) { | |
4444 | if (npages && !old.rmap) { | |
604b38ac AA |
4445 | unsigned long userspace_addr; |
4446 | ||
72dc67a6 | 4447 | down_write(¤t->mm->mmap_sem); |
604b38ac AA |
4448 | userspace_addr = do_mmap(NULL, 0, |
4449 | npages * PAGE_SIZE, | |
4450 | PROT_READ | PROT_WRITE, | |
acee3c04 | 4451 | MAP_PRIVATE | MAP_ANONYMOUS, |
604b38ac | 4452 | 0); |
72dc67a6 | 4453 | up_write(¤t->mm->mmap_sem); |
0de10343 | 4454 | |
604b38ac AA |
4455 | if (IS_ERR((void *)userspace_addr)) |
4456 | return PTR_ERR((void *)userspace_addr); | |
4457 | ||
4458 | /* set userspace_addr atomically for kvm_hva_to_rmapp */ | |
4459 | spin_lock(&kvm->mmu_lock); | |
4460 | memslot->userspace_addr = userspace_addr; | |
4461 | spin_unlock(&kvm->mmu_lock); | |
0de10343 ZX |
4462 | } else { |
4463 | if (!old.user_alloc && old.rmap) { | |
4464 | int ret; | |
4465 | ||
72dc67a6 | 4466 | down_write(¤t->mm->mmap_sem); |
0de10343 ZX |
4467 | ret = do_munmap(current->mm, old.userspace_addr, |
4468 | old.npages * PAGE_SIZE); | |
72dc67a6 | 4469 | up_write(¤t->mm->mmap_sem); |
0de10343 ZX |
4470 | if (ret < 0) |
4471 | printk(KERN_WARNING | |
4472 | "kvm_vm_ioctl_set_memory_region: " | |
4473 | "failed to munmap memory\n"); | |
4474 | } | |
4475 | } | |
4476 | } | |
4477 | ||
f05e70ac | 4478 | if (!kvm->arch.n_requested_mmu_pages) { |
0de10343 ZX |
4479 | unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm); |
4480 | kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages); | |
4481 | } | |
4482 | ||
4483 | kvm_mmu_slot_remove_write_access(kvm, mem->slot); | |
4484 | kvm_flush_remote_tlbs(kvm); | |
4485 | ||
4486 | return 0; | |
4487 | } | |
1d737c8a | 4488 | |
34d4cb8f MT |
4489 | void kvm_arch_flush_shadow(struct kvm *kvm) |
4490 | { | |
4491 | kvm_mmu_zap_all(kvm); | |
4492 | } | |
4493 | ||
1d737c8a ZX |
4494 | int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) |
4495 | { | |
a4535290 | 4496 | return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE |
0496fbb9 JK |
4497 | || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED |
4498 | || vcpu->arch.nmi_pending; | |
1d737c8a | 4499 | } |
5736199a ZX |
4500 | |
4501 | static void vcpu_kick_intr(void *info) | |
4502 | { | |
4503 | #ifdef DEBUG | |
4504 | struct kvm_vcpu *vcpu = (struct kvm_vcpu *)info; | |
4505 | printk(KERN_DEBUG "vcpu_kick_intr %p \n", vcpu); | |
4506 | #endif | |
4507 | } | |
4508 | ||
4509 | void kvm_vcpu_kick(struct kvm_vcpu *vcpu) | |
4510 | { | |
4511 | int ipi_pcpu = vcpu->cpu; | |
e9571ed5 | 4512 | int cpu = get_cpu(); |
5736199a ZX |
4513 | |
4514 | if (waitqueue_active(&vcpu->wq)) { | |
4515 | wake_up_interruptible(&vcpu->wq); | |
4516 | ++vcpu->stat.halt_wakeup; | |
4517 | } | |
e9571ed5 MT |
4518 | /* |
4519 | * We may be called synchronously with irqs disabled in guest mode, | |
4520 | * So need not to call smp_call_function_single() in that case. | |
4521 | */ | |
4522 | if (vcpu->guest_mode && vcpu->cpu != cpu) | |
8691e5a8 | 4523 | smp_call_function_single(ipi_pcpu, vcpu_kick_intr, vcpu, 0); |
e9571ed5 | 4524 | put_cpu(); |
5736199a | 4525 | } |
78646121 GN |
4526 | |
4527 | int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) | |
4528 | { | |
4529 | return kvm_x86_ops->interrupt_allowed(vcpu); | |
4530 | } |