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KVM: x86: use get_desc_base() and get_desc_limit()
[deliverable/linux.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
043405e1
CO		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 13 * Amit Shah <amit.shah@qumranet.com>
14 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
edf88417 21#include <linux/kvm_host.h>
313a3dc7 22#include "irq.h"
1d737c8a 23#include "mmu.h"
7837699f 24#include "i8254.h"
37817f29 25#include "tss.h"
5fdbf976 26#include "kvm_cache_regs.h"
26eef70c 27#include "x86.h"
313a3dc7 28
18068523 29#include <linux/clocksource.h>
4d5c5d0f 30#include <linux/interrupt.h>
313a3dc7
CO		 31#include <linux/kvm.h>
32#include <linux/fs.h>
33#include <linux/vmalloc.h>
5fb76f9b 34#include <linux/module.h>
0de10343 35#include <linux/mman.h>
2bacc55c 36#include <linux/highmem.h>
19de40a8 37#include <linux/iommu.h>
62c476c7 38#include <linux/intel-iommu.h>
c8076604 39#include <linux/cpufreq.h>
aec51dc4
AK		 40#include <trace/events/kvm.h>
41#undef TRACE_INCLUDE_FILE
229456fc
MT		 42#define CREATE_TRACE_POINTS
43#include "trace.h"
043405e1
CO		 44
45#include <asm/uaccess.h>
d825ed0a 46#include <asm/msr.h>
a5f61300 47#include <asm/desc.h>
0bed3b56 48#include <asm/mtrr.h>
890ca9ae 49#include <asm/mce.h>
043405e1 50
313a3dc7 51#define MAX_IO_MSRS 256
a03490ed
CO		 52#define CR0_RESERVED_BITS \
53 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
54 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
55 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
56#define CR4_RESERVED_BITS \
57 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
58 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
59 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
60 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
61
62#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
890ca9ae
HY		 63
64#define KVM_MAX_MCE_BANKS 32
65#define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
66
50a37eb4
JR		 67/* EFER defaults:
68 * - enable syscall per default because its emulated by KVM
69 * - enable LME and LMA per default on 64 bit KVM
70 */
71#ifdef CONFIG_X86_64
72static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
73#else
74static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
75#endif
313a3dc7 76
ba1389b7
AK		 77#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
78#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 79
674eea0f
AK		 80static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
81 struct kvm_cpuid_entry2 __user *entries);
82
97896d04 83struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 84EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 85
ed85c068
AP		 86int ignore_msrs = 0;
87module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
88
417bc304 89struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 90 { "pf_fixed", VCPU_STAT(pf_fixed) },
91 { "pf_guest", VCPU_STAT(pf_guest) },
92 { "tlb_flush", VCPU_STAT(tlb_flush) },
93 { "invlpg", VCPU_STAT(invlpg) },
94 { "exits", VCPU_STAT(exits) },
95 { "io_exits", VCPU_STAT(io_exits) },
96 { "mmio_exits", VCPU_STAT(mmio_exits) },
97 { "signal_exits", VCPU_STAT(signal_exits) },
98 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 99 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 100 { "halt_exits", VCPU_STAT(halt_exits) },
101 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 102 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 103 { "request_irq", VCPU_STAT(request_irq_exits) },
104 { "irq_exits", VCPU_STAT(irq_exits) },
105 { "host_state_reload", VCPU_STAT(host_state_reload) },
106 { "efer_reload", VCPU_STAT(efer_reload) },
107 { "fpu_reload", VCPU_STAT(fpu_reload) },
108 { "insn_emulation", VCPU_STAT(insn_emulation) },
109 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 110 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 111 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 112 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
113 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
114 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
115 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
116 { "mmu_flooded", VM_STAT(mmu_flooded) },
117 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 118 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 119 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 120 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 121 { "largepages", VM_STAT(lpages) },
417bc304
HB		 122 { NULL }
123};
124
5fb76f9b
CO		 125unsigned long segment_base(u16 selector)
126{
127 struct descriptor_table gdt;
a5f61300 128 struct desc_struct *d;
5fb76f9b
CO		 129 unsigned long table_base;
130 unsigned long v;
131
132 if (selector == 0)
133 return 0;
134
135 asm("sgdt %0" : "=m"(gdt));
136 table_base = gdt.base;
137
138 if (selector & 4) { /* from ldt */
139 u16 ldt_selector;
140
141 asm("sldt %0" : "=g"(ldt_selector));
142 table_base = segment_base(ldt_selector);
143 }
a5f61300 144 d = (struct desc_struct *)(table_base + (selector & ~7));
46a359e7 145 v = get_desc_base(d);
5fb76f9b 146#ifdef CONFIG_X86_64
a5f61300
AK		 147 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
148 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
5fb76f9b
CO		 149#endif
150 return v;
151}
152EXPORT_SYMBOL_GPL(segment_base);
153
6866b83e
CO		 154u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
155{
156 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 157 return vcpu->arch.apic_base;
6866b83e 158 else
ad312c7c 159 return vcpu->arch.apic_base;
6866b83e
CO		 160}
161EXPORT_SYMBOL_GPL(kvm_get_apic_base);
162
163void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
164{
165 /* TODO: reserve bits check */
166 if (irqchip_in_kernel(vcpu->kvm))
167 kvm_lapic_set_base(vcpu, data);
168 else
ad312c7c 169 vcpu->arch.apic_base = data;
6866b83e
CO		 170}
171EXPORT_SYMBOL_GPL(kvm_set_apic_base);
172
298101da
AK		 173void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
174{
ad312c7c
ZX		 175 WARN_ON(vcpu->arch.exception.pending);
176 vcpu->arch.exception.pending = true;
177 vcpu->arch.exception.has_error_code = false;
178 vcpu->arch.exception.nr = nr;
298101da
AK		 179}
180EXPORT_SYMBOL_GPL(kvm_queue_exception);
181
c3c91fee
AK		 182void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
183 u32 error_code)
184{
185 ++vcpu->stat.pf_guest;
d8017474 186
71c4dfaf 187 if (vcpu->arch.exception.pending) {
6edf14d8
GN		 188 switch(vcpu->arch.exception.nr) {
189 case DF_VECTOR:
71c4dfaf
JR		 190 /* triple fault -> shutdown */
191 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
6edf14d8
GN		 192 return;
193 case PF_VECTOR:
194 vcpu->arch.exception.nr = DF_VECTOR;
195 vcpu->arch.exception.error_code = 0;
196 return;
197 default:
198 /* replace previous exception with a new one in a hope
199 that instruction re-execution will regenerate lost
200 exception */
201 vcpu->arch.exception.pending = false;
202 break;
71c4dfaf 203 }
c3c91fee 204 }
ad312c7c 205 vcpu->arch.cr2 = addr;
c3c91fee
AK		 206 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
207}
208
3419ffc8
SY		 209void kvm_inject_nmi(struct kvm_vcpu *vcpu)
210{
211 vcpu->arch.nmi_pending = 1;
212}
213EXPORT_SYMBOL_GPL(kvm_inject_nmi);
214
298101da
AK		 215void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
216{
ad312c7c
ZX		 217 WARN_ON(vcpu->arch.exception.pending);
218 vcpu->arch.exception.pending = true;
219 vcpu->arch.exception.has_error_code = true;
220 vcpu->arch.exception.nr = nr;
221 vcpu->arch.exception.error_code = error_code;
298101da
AK		 222}
223EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
224
a03490ed
CO		 225/*
226 * Load the pae pdptrs. Return true is they are all valid.
227 */
228int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
229{
230 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
231 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
232 int i;
233 int ret;
ad312c7c 234 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 235
a03490ed
CO		 236 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
237 offset * sizeof(u64), sizeof(pdpte));
238 if (ret < 0) {
239 ret = 0;
240 goto out;
241 }
242 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 243 if (is_present_gpte(pdpte[i]) &&
20c466b5 244 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 245 ret = 0;
246 goto out;
247 }
248 }
249 ret = 1;
250
ad312c7c 251 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
6de4f3ad
AK		 252 __set_bit(VCPU_EXREG_PDPTR,
253 (unsigned long *)&vcpu->arch.regs_avail);
254 __set_bit(VCPU_EXREG_PDPTR,
255 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 256out:
a03490ed
CO		 257
258 return ret;
259}
cc4b6871 260EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 261
d835dfec
AK		 262static bool pdptrs_changed(struct kvm_vcpu *vcpu)
263{
ad312c7c 264 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 265 bool changed = true;
266 int r;
267
268 if (is_long_mode(vcpu) || !is_pae(vcpu))
269 return false;
270
6de4f3ad
AK		 271 if (!test_bit(VCPU_EXREG_PDPTR,
272 (unsigned long *)&vcpu->arch.regs_avail))
273 return true;
274
ad312c7c 275 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 276 if (r < 0)
277 goto out;
ad312c7c 278 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 279out:
d835dfec
AK		 280
281 return changed;
282}
283
2d3ad1f4 284void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed
CO		 285{
286 if (cr0 & CR0_RESERVED_BITS) {
287 printk(KERN_DEBUG "set_cr0: 0x%lx #GP, reserved bits 0x%lx\n",
ad312c7c 288 cr0, vcpu->arch.cr0);
c1a5d4f9 289 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 290 return;
291 }
292
293 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) {
294 printk(KERN_DEBUG "set_cr0: #GP, CD == 0 && NW == 1\n");
c1a5d4f9 295 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 296 return;
297 }
298
299 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) {
300 printk(KERN_DEBUG "set_cr0: #GP, set PG flag "
301 "and a clear PE flag\n");
c1a5d4f9 302 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 303 return;
304 }
305
306 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
307#ifdef CONFIG_X86_64
ad312c7c 308 if ((vcpu->arch.shadow_efer & EFER_LME)) {
a03490ed
CO		 309 int cs_db, cs_l;
310
311 if (!is_pae(vcpu)) {
312 printk(KERN_DEBUG "set_cr0: #GP, start paging "
313 "in long mode while PAE is disabled\n");
c1a5d4f9 314 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 315 return;
316 }
317 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
318 if (cs_l) {
319 printk(KERN_DEBUG "set_cr0: #GP, start paging "
320 "in long mode while CS.L == 1\n");
c1a5d4f9 321 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 322 return;
323
324 }
325 } else
326#endif
ad312c7c 327 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed
CO		 328 printk(KERN_DEBUG "set_cr0: #GP, pdptrs "
329 "reserved bits\n");
c1a5d4f9 330 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 331 return;
332 }
333
334 }
335
336 kvm_x86_ops->set_cr0(vcpu, cr0);
ad312c7c 337 vcpu->arch.cr0 = cr0;
a03490ed 338
a03490ed 339 kvm_mmu_reset_context(vcpu);
a03490ed
CO		 340 return;
341}
2d3ad1f4 342EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 343
2d3ad1f4 344void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 345{
2d3ad1f4 346 kvm_set_cr0(vcpu, (vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f));
a03490ed 347}
2d3ad1f4 348EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 349
2d3ad1f4 350void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 351{
a2edf57f
AK		 352 unsigned long old_cr4 = vcpu->arch.cr4;
353 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
354
a03490ed
CO		 355 if (cr4 & CR4_RESERVED_BITS) {
356 printk(KERN_DEBUG "set_cr4: #GP, reserved bits\n");
c1a5d4f9 357 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 358 return;
359 }
360
361 if (is_long_mode(vcpu)) {
362 if (!(cr4 & X86_CR4_PAE)) {
363 printk(KERN_DEBUG "set_cr4: #GP, clearing PAE while "
364 "in long mode\n");
c1a5d4f9 365 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 366 return;
367 }
a2edf57f
AK		 368 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
369 && ((cr4 ^ old_cr4) & pdptr_bits)
ad312c7c 370 && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed 371 printk(KERN_DEBUG "set_cr4: #GP, pdptrs reserved bits\n");
c1a5d4f9 372 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 373 return;
374 }
375
376 if (cr4 & X86_CR4_VMXE) {
377 printk(KERN_DEBUG "set_cr4: #GP, setting VMXE\n");
c1a5d4f9 378 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 379 return;
380 }
381 kvm_x86_ops->set_cr4(vcpu, cr4);
ad312c7c 382 vcpu->arch.cr4 = cr4;
5a41accd 383 vcpu->arch.mmu.base_role.cr4_pge = (cr4 & X86_CR4_PGE) && !tdp_enabled;
a03490ed 384 kvm_mmu_reset_context(vcpu);
a03490ed 385}
2d3ad1f4 386EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 387
2d3ad1f4 388void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 389{
ad312c7c 390 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 391 kvm_mmu_sync_roots(vcpu);
d835dfec
AK		 392 kvm_mmu_flush_tlb(vcpu);
393 return;
394 }
395
a03490ed
CO		 396 if (is_long_mode(vcpu)) {
397 if (cr3 & CR3_L_MODE_RESERVED_BITS) {
398 printk(KERN_DEBUG "set_cr3: #GP, reserved bits\n");
c1a5d4f9 399 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 400 return;
401 }
402 } else {
403 if (is_pae(vcpu)) {
404 if (cr3 & CR3_PAE_RESERVED_BITS) {
405 printk(KERN_DEBUG
406 "set_cr3: #GP, reserved bits\n");
c1a5d4f9 407 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 408 return;
409 }
410 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) {
411 printk(KERN_DEBUG "set_cr3: #GP, pdptrs "
412 "reserved bits\n");
c1a5d4f9 413 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 414 return;
415 }
416 }
417 /*
418 * We don't check reserved bits in nonpae mode, because
419 * this isn't enforced, and VMware depends on this.
420 */
421 }
422
a03490ed
CO		 423 /*
424 * Does the new cr3 value map to physical memory? (Note, we
425 * catch an invalid cr3 even in real-mode, because it would
426 * cause trouble later on when we turn on paging anyway.)
427 *
428 * A real CPU would silently accept an invalid cr3 and would
429 * attempt to use it - with largely undefined (and often hard
430 * to debug) behavior on the guest side.
431 */
432 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
c1a5d4f9 433 kvm_inject_gp(vcpu, 0);
a03490ed 434 else {
ad312c7c
ZX		 435 vcpu->arch.cr3 = cr3;
436 vcpu->arch.mmu.new_cr3(vcpu);
a03490ed 437 }
a03490ed 438}
2d3ad1f4 439EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 440
2d3ad1f4 441void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed
CO		 442{
443 if (cr8 & CR8_RESERVED_BITS) {
444 printk(KERN_DEBUG "set_cr8: #GP, reserved bits 0x%lx\n", cr8);
c1a5d4f9 445 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 446 return;
447 }
448 if (irqchip_in_kernel(vcpu->kvm))
449 kvm_lapic_set_tpr(vcpu, cr8);
450 else
ad312c7c 451 vcpu->arch.cr8 = cr8;
a03490ed 452}
2d3ad1f4 453EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 454
2d3ad1f4 455unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 456{
457 if (irqchip_in_kernel(vcpu->kvm))
458 return kvm_lapic_get_cr8(vcpu);
459 else
ad312c7c 460 return vcpu->arch.cr8;
a03490ed 461}
2d3ad1f4 462EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 463
d8017474
AG		 464static inline u32 bit(int bitno)
465{
466 return 1 << (bitno & 31);
467}
468
043405e1
CO		 469/*
470 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
471 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
472 *
473 * This list is modified at module load time to reflect the
474 * capabilities of the host cpu.
475 */
476static u32 msrs_to_save[] = {
477 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
478 MSR_K6_STAR,
479#ifdef CONFIG_X86_64
480 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
481#endif
af24a4e4 482 MSR_IA32_TSC, MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
b286d5d8 483 MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 484};
485
486static unsigned num_msrs_to_save;
487
488static u32 emulated_msrs[] = {
489 MSR_IA32_MISC_ENABLE,
490};
491
15c4a640
CO		 492static void set_efer(struct kvm_vcpu *vcpu, u64 efer)
493{
f2b4b7dd 494 if (efer & efer_reserved_bits) {
15c4a640
CO		 495 printk(KERN_DEBUG "set_efer: 0x%llx #GP, reserved bits\n",
496 efer);
c1a5d4f9 497 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 498 return;
499 }
500
501 if (is_paging(vcpu)
ad312c7c 502 && (vcpu->arch.shadow_efer & EFER_LME) != (efer & EFER_LME)) {
15c4a640 503 printk(KERN_DEBUG "set_efer: #GP, change LME while paging\n");
c1a5d4f9 504 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 505 return;
506 }
507
1b2fd70c
AG		 508 if (efer & EFER_FFXSR) {
509 struct kvm_cpuid_entry2 *feat;
510
511 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
512 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) {
513 printk(KERN_DEBUG "set_efer: #GP, enable FFXSR w/o CPUID capability\n");
514 kvm_inject_gp(vcpu, 0);
515 return;
516 }
517 }
518
d8017474
AG		 519 if (efer & EFER_SVME) {
520 struct kvm_cpuid_entry2 *feat;
521
522 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
523 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) {
524 printk(KERN_DEBUG "set_efer: #GP, enable SVM w/o SVM\n");
525 kvm_inject_gp(vcpu, 0);
526 return;
527 }
528 }
529
15c4a640
CO		 530 kvm_x86_ops->set_efer(vcpu, efer);
531
532 efer &= ~EFER_LMA;
ad312c7c 533 efer |= vcpu->arch.shadow_efer & EFER_LMA;
15c4a640 534
ad312c7c 535 vcpu->arch.shadow_efer = efer;
9645bb56
AK		 536
537 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
538 kvm_mmu_reset_context(vcpu);
15c4a640
CO		 539}
540
f2b4b7dd
JR		 541void kvm_enable_efer_bits(u64 mask)
542{
543 efer_reserved_bits &= ~mask;
544}
545EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
546
547
15c4a640
CO		 548/*
549 * Writes msr value into into the appropriate "register".
550 * Returns 0 on success, non-0 otherwise.
551 * Assumes vcpu_load() was already called.
552 */
553int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
554{
555 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
556}
557
313a3dc7
CO		 558/*
559 * Adapt set_msr() to msr_io()'s calling convention
560 */
561static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
562{
563 return kvm_set_msr(vcpu, index, *data);
564}
565
18068523
GOC		 566static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
567{
568 static int version;
50d0a0f9
GH		 569 struct pvclock_wall_clock wc;
570 struct timespec now, sys, boot;
18068523
GOC		 571
572 if (!wall_clock)
573 return;
574
575 version++;
576
18068523
GOC		 577 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
578
50d0a0f9
GH		 579 /*
580 * The guest calculates current wall clock time by adding
581 * system time (updated by kvm_write_guest_time below) to the
582 * wall clock specified here. guest system time equals host
583 * system time for us, thus we must fill in host boot time here.
584 */
585 now = current_kernel_time();
586 ktime_get_ts(&sys);
587 boot = ns_to_timespec(timespec_to_ns(&now) - timespec_to_ns(&sys));
588
589 wc.sec = boot.tv_sec;
590 wc.nsec = boot.tv_nsec;
591 wc.version = version;
18068523
GOC		 592
593 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
594
595 version++;
596 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 597}
598
50d0a0f9
GH		 599static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
600{
601 uint32_t quotient, remainder;
602
603 /* Don't try to replace with do_div(), this one calculates
604 * "(dividend << 32) / divisor" */
605 __asm__ ( "divl %4"
606 : "=a" (quotient), "=d" (remainder)
607 : "0" (0), "1" (dividend), "r" (divisor) );
608 return quotient;
609}
610
611static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
612{
613 uint64_t nsecs = 1000000000LL;
614 int32_t shift = 0;
615 uint64_t tps64;
616 uint32_t tps32;
617
618 tps64 = tsc_khz * 1000LL;
619 while (tps64 > nsecs*2) {
620 tps64 >>= 1;
621 shift--;
622 }
623
624 tps32 = (uint32_t)tps64;
625 while (tps32 <= (uint32_t)nsecs) {
626 tps32 <<= 1;
627 shift++;
628 }
629
630 hv_clock->tsc_shift = shift;
631 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
632
633 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
80a914dc 634 __func__, tsc_khz, hv_clock->tsc_shift,
50d0a0f9
GH		 635 hv_clock->tsc_to_system_mul);
636}
637
c8076604
GH		 638static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
639
18068523
GOC		 640static void kvm_write_guest_time(struct kvm_vcpu *v)
641{
642 struct timespec ts;
643 unsigned long flags;
644 struct kvm_vcpu_arch *vcpu = &v->arch;
645 void *shared_kaddr;
463656c0 646 unsigned long this_tsc_khz;
18068523
GOC		 647
648 if ((!vcpu->time_page))
649 return;
650
463656c0
AK		 651 this_tsc_khz = get_cpu_var(cpu_tsc_khz);
652 if (unlikely(vcpu->hv_clock_tsc_khz != this_tsc_khz)) {
653 kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock);
654 vcpu->hv_clock_tsc_khz = this_tsc_khz;
50d0a0f9 655 }
463656c0 656 put_cpu_var(cpu_tsc_khz);
50d0a0f9 657
18068523
GOC		 658 /* Keep irq disabled to prevent changes to the clock */
659 local_irq_save(flags);
af24a4e4 660 kvm_get_msr(v, MSR_IA32_TSC, &vcpu->hv_clock.tsc_timestamp);
18068523
GOC		 661 ktime_get_ts(&ts);
662 local_irq_restore(flags);
663
664 /* With all the info we got, fill in the values */
665
666 vcpu->hv_clock.system_time = ts.tv_nsec +
667 (NSEC_PER_SEC * (u64)ts.tv_sec);
668 /*
669 * The interface expects us to write an even number signaling that the
670 * update is finished. Since the guest won't see the intermediate
50d0a0f9 671 * state, we just increase by 2 at the end.
18068523 672 */
50d0a0f9 673 vcpu->hv_clock.version += 2;
18068523
GOC		 674
675 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
676
677 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 678 sizeof(vcpu->hv_clock));
18068523
GOC		 679
680 kunmap_atomic(shared_kaddr, KM_USER0);
681
682 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
683}
684
c8076604
GH		 685static int kvm_request_guest_time_update(struct kvm_vcpu *v)
686{
687 struct kvm_vcpu_arch *vcpu = &v->arch;
688
689 if (!vcpu->time_page)
690 return 0;
691 set_bit(KVM_REQ_KVMCLOCK_UPDATE, &v->requests);
692 return 1;
693}
694
9ba075a6
AK		 695static bool msr_mtrr_valid(unsigned msr)
696{
697 switch (msr) {
698 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
699 case MSR_MTRRfix64K_00000:
700 case MSR_MTRRfix16K_80000:
701 case MSR_MTRRfix16K_A0000:
702 case MSR_MTRRfix4K_C0000:
703 case MSR_MTRRfix4K_C8000:
704 case MSR_MTRRfix4K_D0000:
705 case MSR_MTRRfix4K_D8000:
706 case MSR_MTRRfix4K_E0000:
707 case MSR_MTRRfix4K_E8000:
708 case MSR_MTRRfix4K_F0000:
709 case MSR_MTRRfix4K_F8000:
710 case MSR_MTRRdefType:
711 case MSR_IA32_CR_PAT:
712 return true;
713 case 0x2f8:
714 return true;
715 }
716 return false;
717}
718
d6289b93
MT		 719static bool valid_pat_type(unsigned t)
720{
721 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
722}
723
724static bool valid_mtrr_type(unsigned t)
725{
726 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
727}
728
729static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
730{
731 int i;
732
733 if (!msr_mtrr_valid(msr))
734 return false;
735
736 if (msr == MSR_IA32_CR_PAT) {
737 for (i = 0; i < 8; i++)
738 if (!valid_pat_type((data >> (i * 8)) & 0xff))
739 return false;
740 return true;
741 } else if (msr == MSR_MTRRdefType) {
742 if (data & ~0xcff)
743 return false;
744 return valid_mtrr_type(data & 0xff);
745 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
746 for (i = 0; i < 8 ; i++)
747 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
748 return false;
749 return true;
750 }
751
752 /* variable MTRRs */
753 return valid_mtrr_type(data & 0xff);
754}
755
9ba075a6
AK		 756static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
757{
0bed3b56
SY		 758 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
759
d6289b93 760 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 761 return 1;
762
0bed3b56
SY		 763 if (msr == MSR_MTRRdefType) {
764 vcpu->arch.mtrr_state.def_type = data;
765 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
766 } else if (msr == MSR_MTRRfix64K_00000)
767 p[0] = data;
768 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
769 p[1 + msr - MSR_MTRRfix16K_80000] = data;
770 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
771 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
772 else if (msr == MSR_IA32_CR_PAT)
773 vcpu->arch.pat = data;
774 else { /* Variable MTRRs */
775 int idx, is_mtrr_mask;
776 u64 *pt;
777
778 idx = (msr - 0x200) / 2;
779 is_mtrr_mask = msr - 0x200 - 2 * idx;
780 if (!is_mtrr_mask)
781 pt =
782 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
783 else
784 pt =
785 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
786 *pt = data;
787 }
788
789 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 790 return 0;
791}
15c4a640 792
890ca9ae 793static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 794{
890ca9ae
HY		 795 u64 mcg_cap = vcpu->arch.mcg_cap;
796 unsigned bank_num = mcg_cap & 0xff;
797
15c4a640 798 switch (msr) {
15c4a640 799 case MSR_IA32_MCG_STATUS:
890ca9ae 800 vcpu->arch.mcg_status = data;
15c4a640 801 break;
c7ac679c 802 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 803 if (!(mcg_cap & MCG_CTL_P))
804 return 1;
805 if (data != 0 && data != ~(u64)0)
806 return -1;
807 vcpu->arch.mcg_ctl = data;
808 break;
809 default:
810 if (msr >= MSR_IA32_MC0_CTL &&
811 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
812 u32 offset = msr - MSR_IA32_MC0_CTL;
813 /* only 0 or all 1s can be written to IA32_MCi_CTL */
814 if ((offset & 0x3) == 0 &&
815 data != 0 && data != ~(u64)0)
816 return -1;
817 vcpu->arch.mce_banks[offset] = data;
818 break;
819 }
820 return 1;
821 }
822 return 0;
823}
824
825int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
826{
827 switch (msr) {
828 case MSR_EFER:
829 set_efer(vcpu, data);
c7ac679c 830 break;
8f1589d9
AP		 831 case MSR_K7_HWCR:
832 data &= ~(u64)0x40; /* ignore flush filter disable */
833 if (data != 0) {
834 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
835 data);
836 return 1;
837 }
838 break;
f7c6d140
AP		 839 case MSR_FAM10H_MMIO_CONF_BASE:
840 if (data != 0) {
841 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
842 "0x%llx\n", data);
843 return 1;
844 }
845 break;
c323c0e5
AP		 846 case MSR_AMD64_NB_CFG:
847 break;
b5e2fec0
AG		 848 case MSR_IA32_DEBUGCTLMSR:
849 if (!data) {
850 /* We support the non-activated case already */
851 break;
852 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
853 /* Values other than LBR and BTF are vendor-specific,
854 thus reserved and should throw a #GP */
855 return 1;
856 }
857 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
858 __func__, data);
859 break;
15c4a640
CO		 860 case MSR_IA32_UCODE_REV:
861 case MSR_IA32_UCODE_WRITE:
61a6bd67 862 case MSR_VM_HSAVE_PA:
6098ca93 863 case MSR_AMD64_PATCH_LOADER:
15c4a640 864 break;
9ba075a6
AK		 865 case 0x200 ... 0x2ff:
866 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 867 case MSR_IA32_APICBASE:
868 kvm_set_apic_base(vcpu, data);
869 break;
0105d1a5
GN		 870 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
871 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 872 case MSR_IA32_MISC_ENABLE:
ad312c7c 873 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 874 break;
18068523
GOC		 875 case MSR_KVM_WALL_CLOCK:
876 vcpu->kvm->arch.wall_clock = data;
877 kvm_write_wall_clock(vcpu->kvm, data);
878 break;
879 case MSR_KVM_SYSTEM_TIME: {
880 if (vcpu->arch.time_page) {
881 kvm_release_page_dirty(vcpu->arch.time_page);
882 vcpu->arch.time_page = NULL;
883 }
884
885 vcpu->arch.time = data;
886
887 /* we verify if the enable bit is set... */
888 if (!(data & 1))
889 break;
890
891 /* ...but clean it before doing the actual write */
892 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
893
18068523
GOC		 894 vcpu->arch.time_page =
895 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 896
897 if (is_error_page(vcpu->arch.time_page)) {
898 kvm_release_page_clean(vcpu->arch.time_page);
899 vcpu->arch.time_page = NULL;
900 }
901
c8076604 902 kvm_request_guest_time_update(vcpu);
18068523
GOC		 903 break;
904 }
890ca9ae
HY		 905 case MSR_IA32_MCG_CTL:
906 case MSR_IA32_MCG_STATUS:
907 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
908 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 909
910 /* Performance counters are not protected by a CPUID bit,
911 * so we should check all of them in the generic path for the sake of
912 * cross vendor migration.
913 * Writing a zero into the event select MSRs disables them,
914 * which we perfectly emulate ;-). Any other value should be at least
915 * reported, some guests depend on them.
916 */
917 case MSR_P6_EVNTSEL0:
918 case MSR_P6_EVNTSEL1:
919 case MSR_K7_EVNTSEL0:
920 case MSR_K7_EVNTSEL1:
921 case MSR_K7_EVNTSEL2:
922 case MSR_K7_EVNTSEL3:
923 if (data != 0)
924 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
925 "0x%x data 0x%llx\n", msr, data);
926 break;
927 /* at least RHEL 4 unconditionally writes to the perfctr registers,
928 * so we ignore writes to make it happy.
929 */
930 case MSR_P6_PERFCTR0:
931 case MSR_P6_PERFCTR1:
932 case MSR_K7_PERFCTR0:
933 case MSR_K7_PERFCTR1:
934 case MSR_K7_PERFCTR2:
935 case MSR_K7_PERFCTR3:
936 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
937 "0x%x data 0x%llx\n", msr, data);
938 break;
15c4a640 939 default:
ed85c068
AP		 940 if (!ignore_msrs) {
941 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
942 msr, data);
943 return 1;
944 } else {
945 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
946 msr, data);
947 break;
948 }
15c4a640
CO		 949 }
950 return 0;
951}
952EXPORT_SYMBOL_GPL(kvm_set_msr_common);
953
954
955/*
956 * Reads an msr value (of 'msr_index') into 'pdata'.
957 * Returns 0 on success, non-0 otherwise.
958 * Assumes vcpu_load() was already called.
959 */
960int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
961{
962 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
963}
964
9ba075a6
AK		 965static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
966{
0bed3b56
SY		 967 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
968
9ba075a6
AK		 969 if (!msr_mtrr_valid(msr))
970 return 1;
971
0bed3b56
SY		 972 if (msr == MSR_MTRRdefType)
973 *pdata = vcpu->arch.mtrr_state.def_type +
974 (vcpu->arch.mtrr_state.enabled << 10);
975 else if (msr == MSR_MTRRfix64K_00000)
976 *pdata = p[0];
977 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
978 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
979 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
980 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
981 else if (msr == MSR_IA32_CR_PAT)
982 *pdata = vcpu->arch.pat;
983 else { /* Variable MTRRs */
984 int idx, is_mtrr_mask;
985 u64 *pt;
986
987 idx = (msr - 0x200) / 2;
988 is_mtrr_mask = msr - 0x200 - 2 * idx;
989 if (!is_mtrr_mask)
990 pt =
991 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
992 else
993 pt =
994 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
995 *pdata = *pt;
996 }
997
9ba075a6
AK		 998 return 0;
999}
1000
890ca9ae 1001static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1002{
1003 u64 data;
890ca9ae
HY		 1004 u64 mcg_cap = vcpu->arch.mcg_cap;
1005 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1006
1007 switch (msr) {
15c4a640
CO		 1008 case MSR_IA32_P5_MC_ADDR:
1009 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1010 data = 0;
1011 break;
15c4a640 1012 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1013 data = vcpu->arch.mcg_cap;
1014 break;
c7ac679c 1015 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1016 if (!(mcg_cap & MCG_CTL_P))
1017 return 1;
1018 data = vcpu->arch.mcg_ctl;
1019 break;
1020 case MSR_IA32_MCG_STATUS:
1021 data = vcpu->arch.mcg_status;
1022 break;
1023 default:
1024 if (msr >= MSR_IA32_MC0_CTL &&
1025 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1026 u32 offset = msr - MSR_IA32_MC0_CTL;
1027 data = vcpu->arch.mce_banks[offset];
1028 break;
1029 }
1030 return 1;
1031 }
1032 *pdata = data;
1033 return 0;
1034}
1035
1036int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1037{
1038 u64 data;
1039
1040 switch (msr) {
890ca9ae 1041 case MSR_IA32_PLATFORM_ID:
15c4a640 1042 case MSR_IA32_UCODE_REV:
15c4a640 1043 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1044 case MSR_IA32_DEBUGCTLMSR:
1045 case MSR_IA32_LASTBRANCHFROMIP:
1046 case MSR_IA32_LASTBRANCHTOIP:
1047 case MSR_IA32_LASTINTFROMIP:
1048 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1049 case MSR_K8_SYSCFG:
1050 case MSR_K7_HWCR:
61a6bd67 1051 case MSR_VM_HSAVE_PA:
7fe29e0f
AS		 1052 case MSR_P6_EVNTSEL0:
1053 case MSR_P6_EVNTSEL1:
9e699624 1054 case MSR_K7_EVNTSEL0:
1fdbd48c 1055 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1056 case MSR_AMD64_NB_CFG:
f7c6d140 1057 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1058 data = 0;
1059 break;
9ba075a6
AK		 1060 case MSR_MTRRcap:
1061 data = 0x500 | KVM_NR_VAR_MTRR;
1062 break;
1063 case 0x200 ... 0x2ff:
1064 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1065 case 0xcd: /* fsb frequency */
1066 data = 3;
1067 break;
1068 case MSR_IA32_APICBASE:
1069 data = kvm_get_apic_base(vcpu);
1070 break;
0105d1a5
GN		 1071 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1072 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1073 break;
15c4a640 1074 case MSR_IA32_MISC_ENABLE:
ad312c7c 1075 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1076 break;
847f0ad8
AG		 1077 case MSR_IA32_PERF_STATUS:
1078 /* TSC increment by tick */
1079 data = 1000ULL;
1080 /* CPU multiplier */
1081 data |= (((uint64_t)4ULL) << 40);
1082 break;
15c4a640 1083 case MSR_EFER:
ad312c7c 1084 data = vcpu->arch.shadow_efer;
15c4a640 1085 break;
18068523
GOC		 1086 case MSR_KVM_WALL_CLOCK:
1087 data = vcpu->kvm->arch.wall_clock;
1088 break;
1089 case MSR_KVM_SYSTEM_TIME:
1090 data = vcpu->arch.time;
1091 break;
890ca9ae
HY		 1092 case MSR_IA32_P5_MC_ADDR:
1093 case MSR_IA32_P5_MC_TYPE:
1094 case MSR_IA32_MCG_CAP:
1095 case MSR_IA32_MCG_CTL:
1096 case MSR_IA32_MCG_STATUS:
1097 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1098 return get_msr_mce(vcpu, msr, pdata);
15c4a640 1099 default:
ed85c068
AP		 1100 if (!ignore_msrs) {
1101 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1102 return 1;
1103 } else {
1104 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1105 data = 0;
1106 }
1107 break;
15c4a640
CO		 1108 }
1109 *pdata = data;
1110 return 0;
1111}
1112EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1113
313a3dc7
CO		 1114/*
1115 * Read or write a bunch of msrs. All parameters are kernel addresses.
1116 *
1117 * @return number of msrs set successfully.
1118 */
1119static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1120 struct kvm_msr_entry *entries,
1121 int (*do_msr)(struct kvm_vcpu *vcpu,
1122 unsigned index, u64 *data))
1123{
1124 int i;
1125
1126 vcpu_load(vcpu);
1127
3200f405 1128 down_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 1129 for (i = 0; i < msrs->nmsrs; ++i)
1130 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1131 break;
3200f405 1132 up_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 1133
1134 vcpu_put(vcpu);
1135
1136 return i;
1137}
1138
1139/*
1140 * Read or write a bunch of msrs. Parameters are user addresses.
1141 *
1142 * @return number of msrs set successfully.
1143 */
1144static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1145 int (*do_msr)(struct kvm_vcpu *vcpu,
1146 unsigned index, u64 *data),
1147 int writeback)
1148{
1149 struct kvm_msrs msrs;
1150 struct kvm_msr_entry *entries;
1151 int r, n;
1152 unsigned size;
1153
1154 r = -EFAULT;
1155 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1156 goto out;
1157
1158 r = -E2BIG;
1159 if (msrs.nmsrs >= MAX_IO_MSRS)
1160 goto out;
1161
1162 r = -ENOMEM;
1163 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
1164 entries = vmalloc(size);
1165 if (!entries)
1166 goto out;
1167
1168 r = -EFAULT;
1169 if (copy_from_user(entries, user_msrs->entries, size))
1170 goto out_free;
1171
1172 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1173 if (r < 0)
1174 goto out_free;
1175
1176 r = -EFAULT;
1177 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1178 goto out_free;
1179
1180 r = n;
1181
1182out_free:
1183 vfree(entries);
1184out:
1185 return r;
1186}
1187
018d00d2
ZX		 1188int kvm_dev_ioctl_check_extension(long ext)
1189{
1190 int r;
1191
1192 switch (ext) {
1193 case KVM_CAP_IRQCHIP:
1194 case KVM_CAP_HLT:
1195 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1196 case KVM_CAP_SET_TSS_ADDR:
07716717 1197 case KVM_CAP_EXT_CPUID:
c8076604 1198 case KVM_CAP_CLOCKSOURCE:
7837699f 1199 case KVM_CAP_PIT:
a28e4f5a 1200 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1201 case KVM_CAP_MP_STATE:
ed848624 1202 case KVM_CAP_SYNC_MMU:
52d939a0 1203 case KVM_CAP_REINJECT_CONTROL:
4925663a 1204 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1205 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1206 case KVM_CAP_IRQFD:
d34e6b17 1207 case KVM_CAP_IOEVENTFD:
c5ff41ce 1208 case KVM_CAP_PIT2:
e9f42757 1209 case KVM_CAP_PIT_STATE2:
018d00d2
ZX		 1210 r = 1;
1211 break;
542472b5
LV		 1212 case KVM_CAP_COALESCED_MMIO:
1213 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1214 break;
774ead3a
AK		 1215 case KVM_CAP_VAPIC:
1216 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1217 break;
f725230a
AK		 1218 case KVM_CAP_NR_VCPUS:
1219 r = KVM_MAX_VCPUS;
1220 break;
a988b910
AK		 1221 case KVM_CAP_NR_MEMSLOTS:
1222 r = KVM_MEMORY_SLOTS;
1223 break;
2f333bcb
MT		 1224 case KVM_CAP_PV_MMU:
1225 r = !tdp_enabled;
1226 break;
62c476c7 1227 case KVM_CAP_IOMMU:
19de40a8 1228 r = iommu_found();
62c476c7 1229 break;
890ca9ae
HY		 1230 case KVM_CAP_MCE:
1231 r = KVM_MAX_MCE_BANKS;
1232 break;
018d00d2
ZX		 1233 default:
1234 r = 0;
1235 break;
1236 }
1237 return r;
1238
1239}
1240
043405e1
CO		 1241long kvm_arch_dev_ioctl(struct file *filp,
1242 unsigned int ioctl, unsigned long arg)
1243{
1244 void __user *argp = (void __user *)arg;
1245 long r;
1246
1247 switch (ioctl) {
1248 case KVM_GET_MSR_INDEX_LIST: {
1249 struct kvm_msr_list __user *user_msr_list = argp;
1250 struct kvm_msr_list msr_list;
1251 unsigned n;
1252
1253 r = -EFAULT;
1254 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1255 goto out;
1256 n = msr_list.nmsrs;
1257 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1258 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1259 goto out;
1260 r = -E2BIG;
e125e7b6 1261 if (n < msr_list.nmsrs)
043405e1
CO		 1262 goto out;
1263 r = -EFAULT;
1264 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1265 num_msrs_to_save * sizeof(u32)))
1266 goto out;
e125e7b6 1267 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 1268 &emulated_msrs,
1269 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1270 goto out;
1271 r = 0;
1272 break;
1273 }
674eea0f
AK		 1274 case KVM_GET_SUPPORTED_CPUID: {
1275 struct kvm_cpuid2 __user *cpuid_arg = argp;
1276 struct kvm_cpuid2 cpuid;
1277
1278 r = -EFAULT;
1279 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1280 goto out;
1281 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 1282 cpuid_arg->entries);
674eea0f
AK		 1283 if (r)
1284 goto out;
1285
1286 r = -EFAULT;
1287 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1288 goto out;
1289 r = 0;
1290 break;
1291 }
890ca9ae
HY		 1292 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
1293 u64 mce_cap;
1294
1295 mce_cap = KVM_MCE_CAP_SUPPORTED;
1296 r = -EFAULT;
1297 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
1298 goto out;
1299 r = 0;
1300 break;
1301 }
043405e1
CO		 1302 default:
1303 r = -EINVAL;
1304 }
1305out:
1306 return r;
1307}
1308
313a3dc7
CO		 1309void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1310{
1311 kvm_x86_ops->vcpu_load(vcpu, cpu);
c8076604 1312 kvm_request_guest_time_update(vcpu);
313a3dc7
CO		 1313}
1314
1315void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1316{
1317 kvm_x86_ops->vcpu_put(vcpu);
9327fd11 1318 kvm_put_guest_fpu(vcpu);
313a3dc7
CO		 1319}
1320
07716717 1321static int is_efer_nx(void)
313a3dc7 1322{
e286e86e 1323 unsigned long long efer = 0;
313a3dc7 1324
e286e86e 1325 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 1326 return efer & EFER_NX;
1327}
1328
1329static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1330{
1331 int i;
1332 struct kvm_cpuid_entry2 *e, *entry;
1333
313a3dc7 1334 entry = NULL;
ad312c7c
ZX		 1335 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1336 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 1337 if (e->function == 0x80000001) {
1338 entry = e;
1339 break;
1340 }
1341 }
07716717 1342 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 1343 entry->edx &= ~(1 << 20);
1344 printk(KERN_INFO "kvm: guest NX capability removed\n");
1345 }
1346}
1347
07716717 1348/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 1349static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1350 struct kvm_cpuid *cpuid,
1351 struct kvm_cpuid_entry __user *entries)
07716717
DK		 1352{
1353 int r, i;
1354 struct kvm_cpuid_entry *cpuid_entries;
1355
1356 r = -E2BIG;
1357 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1358 goto out;
1359 r = -ENOMEM;
1360 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1361 if (!cpuid_entries)
1362 goto out;
1363 r = -EFAULT;
1364 if (copy_from_user(cpuid_entries, entries,
1365 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1366 goto out_free;
1367 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 1368 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1369 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1370 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1371 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1372 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1373 vcpu->arch.cpuid_entries[i].index = 0;
1374 vcpu->arch.cpuid_entries[i].flags = 0;
1375 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1376 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1377 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1378 }
1379 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 1380 cpuid_fix_nx_cap(vcpu);
1381 r = 0;
fc61b800 1382 kvm_apic_set_version(vcpu);
07716717
DK		 1383
1384out_free:
1385 vfree(cpuid_entries);
1386out:
1387 return r;
1388}
1389
1390static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1391 struct kvm_cpuid2 *cpuid,
1392 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 1393{
1394 int r;
1395
1396 r = -E2BIG;
1397 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1398 goto out;
1399 r = -EFAULT;
ad312c7c 1400 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 1401 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 1402 goto out;
ad312c7c 1403 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 1404 kvm_apic_set_version(vcpu);
313a3dc7
CO		 1405 return 0;
1406
1407out:
1408 return r;
1409}
1410
07716717 1411static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1412 struct kvm_cpuid2 *cpuid,
1413 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1414{
1415 int r;
1416
1417 r = -E2BIG;
ad312c7c 1418 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 1419 goto out;
1420 r = -EFAULT;
ad312c7c 1421 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 1422 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1423 goto out;
1424 return 0;
1425
1426out:
ad312c7c 1427 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 1428 return r;
1429}
1430
07716717 1431static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 1432 u32 index)
07716717
DK		 1433{
1434 entry->function = function;
1435 entry->index = index;
1436 cpuid_count(entry->function, entry->index,
19355475 1437 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 1438 entry->flags = 0;
1439}
1440
7faa4ee1
AK		 1441#define F(x) bit(X86_FEATURE_##x)
1442
07716717
DK		 1443static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1444 u32 index, int *nent, int maxnent)
1445{
7faa4ee1 1446 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 1447#ifdef CONFIG_X86_64
7faa4ee1
AK		 1448 unsigned f_lm = F(LM);
1449#else
1450 unsigned f_lm = 0;
07716717 1451#endif
7faa4ee1
AK		 1452
1453 /* cpuid 1.edx */
1454 const u32 kvm_supported_word0_x86_features =
1455 F(FPU) | F(VME) | F(DE) | F(PSE) |
1456 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1457 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
1458 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1459 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
1460 0 /* Reserved, DS, ACPI */ | F(MMX) |
1461 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
1462 0 /* HTT, TM, Reserved, PBE */;
1463 /* cpuid 0x80000001.edx */
1464 const u32 kvm_supported_word1_x86_features =
1465 F(FPU) | F(VME) | F(DE) | F(PSE) |
1466 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1467 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
1468 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1469 F(PAT) | F(PSE36) | 0 /* Reserved */ |
1470 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
1471 F(FXSR) | F(FXSR_OPT) | 0 /* GBPAGES */ | 0 /* RDTSCP */ |
1472 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
1473 /* cpuid 1.ecx */
1474 const u32 kvm_supported_word4_x86_features =
d149c731
AK		 1475 F(XMM3) | 0 /* Reserved, DTES64, MONITOR */ |
1476 0 /* DS-CPL, VMX, SMX, EST */ |
1477 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
1478 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
1479 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 1480 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
d149c731 1481 0 /* Reserved, XSAVE, OSXSAVE */;
7faa4ee1 1482 /* cpuid 0x80000001.ecx */
07716717 1483 const u32 kvm_supported_word6_x86_features =
7faa4ee1
AK		 1484 F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ |
1485 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
1486 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
1487 0 /* SKINIT */ | 0 /* WDT */;
07716717 1488
19355475 1489 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 1490 get_cpu();
1491 do_cpuid_1_ent(entry, function, index);
1492 ++*nent;
1493
1494 switch (function) {
1495 case 0:
1496 entry->eax = min(entry->eax, (u32)0xb);
1497 break;
1498 case 1:
1499 entry->edx &= kvm_supported_word0_x86_features;
7faa4ee1 1500 entry->ecx &= kvm_supported_word4_x86_features;
0d1de2d9
GN		 1501 /* we support x2apic emulation even if host does not support
1502 * it since we emulate x2apic in software */
1503 entry->ecx |= F(X2APIC);
07716717
DK		 1504 break;
1505 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1506 * may return different values. This forces us to get_cpu() before
1507 * issuing the first command, and also to emulate this annoying behavior
1508 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1509 case 2: {
1510 int t, times = entry->eax & 0xff;
1511
1512 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 1513 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 1514 for (t = 1; t < times && *nent < maxnent; ++t) {
1515 do_cpuid_1_ent(&entry[t], function, 0);
1516 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1517 ++*nent;
1518 }
1519 break;
1520 }
1521 /* function 4 and 0xb have additional index. */
1522 case 4: {
14af3f3c 1523 int i, cache_type;
07716717
DK		 1524
1525 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1526 /* read more entries until cache_type is zero */
14af3f3c
HH		 1527 for (i = 1; *nent < maxnent; ++i) {
1528 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 1529 if (!cache_type)
1530 break;
14af3f3c
HH		 1531 do_cpuid_1_ent(&entry[i], function, i);
1532 entry[i].flags |=
07716717
DK		 1533 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1534 ++*nent;
1535 }
1536 break;
1537 }
1538 case 0xb: {
14af3f3c 1539 int i, level_type;
07716717
DK		 1540
1541 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1542 /* read more entries until level_type is zero */
14af3f3c 1543 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 1544 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 1545 if (!level_type)
1546 break;
14af3f3c
HH		 1547 do_cpuid_1_ent(&entry[i], function, i);
1548 entry[i].flags |=
07716717
DK		 1549 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1550 ++*nent;
1551 }
1552 break;
1553 }
1554 case 0x80000000:
1555 entry->eax = min(entry->eax, 0x8000001a);
1556 break;
1557 case 0x80000001:
1558 entry->edx &= kvm_supported_word1_x86_features;
1559 entry->ecx &= kvm_supported_word6_x86_features;
1560 break;
1561 }
1562 put_cpu();
1563}
1564
7faa4ee1
AK		 1565#undef F
1566
674eea0f 1567static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 1568 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1569{
1570 struct kvm_cpuid_entry2 *cpuid_entries;
1571 int limit, nent = 0, r = -E2BIG;
1572 u32 func;
1573
1574 if (cpuid->nent < 1)
1575 goto out;
1576 r = -ENOMEM;
1577 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
1578 if (!cpuid_entries)
1579 goto out;
1580
1581 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
1582 limit = cpuid_entries[0].eax;
1583 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
1584 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1585 &nent, cpuid->nent);
07716717
DK		 1586 r = -E2BIG;
1587 if (nent >= cpuid->nent)
1588 goto out_free;
1589
1590 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
1591 limit = cpuid_entries[nent - 1].eax;
1592 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
1593 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1594 &nent, cpuid->nent);
cb007648
MM		 1595 r = -E2BIG;
1596 if (nent >= cpuid->nent)
1597 goto out_free;
1598
07716717
DK		 1599 r = -EFAULT;
1600 if (copy_to_user(entries, cpuid_entries,
19355475 1601 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1602 goto out_free;
1603 cpuid->nent = nent;
1604 r = 0;
1605
1606out_free:
1607 vfree(cpuid_entries);
1608out:
1609 return r;
1610}
1611
313a3dc7
CO		 1612static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
1613 struct kvm_lapic_state *s)
1614{
1615 vcpu_load(vcpu);
ad312c7c 1616 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 1617 vcpu_put(vcpu);
1618
1619 return 0;
1620}
1621
1622static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
1623 struct kvm_lapic_state *s)
1624{
1625 vcpu_load(vcpu);
ad312c7c 1626 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7
CO		 1627 kvm_apic_post_state_restore(vcpu);
1628 vcpu_put(vcpu);
1629
1630 return 0;
1631}
1632
f77bc6a4
ZX		 1633static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
1634 struct kvm_interrupt *irq)
1635{
1636 if (irq->irq < 0 || irq->irq >= 256)
1637 return -EINVAL;
1638 if (irqchip_in_kernel(vcpu->kvm))
1639 return -ENXIO;
1640 vcpu_load(vcpu);
1641
66fd3f7f 1642 kvm_queue_interrupt(vcpu, irq->irq, false);
f77bc6a4
ZX		 1643
1644 vcpu_put(vcpu);
1645
1646 return 0;
1647}
1648
c4abb7c9
JK		 1649static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
1650{
1651 vcpu_load(vcpu);
1652 kvm_inject_nmi(vcpu);
1653 vcpu_put(vcpu);
1654
1655 return 0;
1656}
1657
b209749f
AK		 1658static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
1659 struct kvm_tpr_access_ctl *tac)
1660{
1661 if (tac->flags)
1662 return -EINVAL;
1663 vcpu->arch.tpr_access_reporting = !!tac->enabled;
1664 return 0;
1665}
1666
890ca9ae
HY		 1667static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
1668 u64 mcg_cap)
1669{
1670 int r;
1671 unsigned bank_num = mcg_cap & 0xff, bank;
1672
1673 r = -EINVAL;
1674 if (!bank_num)
1675 goto out;
1676 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
1677 goto out;
1678 r = 0;
1679 vcpu->arch.mcg_cap = mcg_cap;
1680 /* Init IA32_MCG_CTL to all 1s */
1681 if (mcg_cap & MCG_CTL_P)
1682 vcpu->arch.mcg_ctl = ~(u64)0;
1683 /* Init IA32_MCi_CTL to all 1s */
1684 for (bank = 0; bank < bank_num; bank++)
1685 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
1686out:
1687 return r;
1688}
1689
1690static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
1691 struct kvm_x86_mce *mce)
1692{
1693 u64 mcg_cap = vcpu->arch.mcg_cap;
1694 unsigned bank_num = mcg_cap & 0xff;
1695 u64 *banks = vcpu->arch.mce_banks;
1696
1697 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
1698 return -EINVAL;
1699 /*
1700 * if IA32_MCG_CTL is not all 1s, the uncorrected error
1701 * reporting is disabled
1702 */
1703 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
1704 vcpu->arch.mcg_ctl != ~(u64)0)
1705 return 0;
1706 banks += 4 * mce->bank;
1707 /*
1708 * if IA32_MCi_CTL is not all 1s, the uncorrected error
1709 * reporting is disabled for the bank
1710 */
1711 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
1712 return 0;
1713 if (mce->status & MCI_STATUS_UC) {
1714 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
1715 !(vcpu->arch.cr4 & X86_CR4_MCE)) {
1716 printk(KERN_DEBUG "kvm: set_mce: "
1717 "injects mce exception while "
1718 "previous one is in progress!\n");
1719 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
1720 return 0;
1721 }
1722 if (banks[1] & MCI_STATUS_VAL)
1723 mce->status |= MCI_STATUS_OVER;
1724 banks[2] = mce->addr;
1725 banks[3] = mce->misc;
1726 vcpu->arch.mcg_status = mce->mcg_status;
1727 banks[1] = mce->status;
1728 kvm_queue_exception(vcpu, MC_VECTOR);
1729 } else if (!(banks[1] & MCI_STATUS_VAL)
1730 || !(banks[1] & MCI_STATUS_UC)) {
1731 if (banks[1] & MCI_STATUS_VAL)
1732 mce->status |= MCI_STATUS_OVER;
1733 banks[2] = mce->addr;
1734 banks[3] = mce->misc;
1735 banks[1] = mce->status;
1736 } else
1737 banks[1] |= MCI_STATUS_OVER;
1738 return 0;
1739}
1740
313a3dc7
CO		 1741long kvm_arch_vcpu_ioctl(struct file *filp,
1742 unsigned int ioctl, unsigned long arg)
1743{
1744 struct kvm_vcpu *vcpu = filp->private_data;
1745 void __user *argp = (void __user *)arg;
1746 int r;
b772ff36 1747 struct kvm_lapic_state *lapic = NULL;
313a3dc7
CO		 1748
1749 switch (ioctl) {
1750 case KVM_GET_LAPIC: {
b772ff36 1751 lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 1752
b772ff36
DH		 1753 r = -ENOMEM;
1754 if (!lapic)
1755 goto out;
1756 r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic);
313a3dc7
CO		 1757 if (r)
1758 goto out;
1759 r = -EFAULT;
b772ff36 1760 if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 1761 goto out;
1762 r = 0;
1763 break;
1764 }
1765 case KVM_SET_LAPIC: {
b772ff36
DH		 1766 lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
1767 r = -ENOMEM;
1768 if (!lapic)
1769 goto out;
313a3dc7 1770 r = -EFAULT;
b772ff36 1771 if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 1772 goto out;
b772ff36 1773 r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic);
313a3dc7
CO		 1774 if (r)
1775 goto out;
1776 r = 0;
1777 break;
1778 }
f77bc6a4
ZX		 1779 case KVM_INTERRUPT: {
1780 struct kvm_interrupt irq;
1781
1782 r = -EFAULT;
1783 if (copy_from_user(&irq, argp, sizeof irq))
1784 goto out;
1785 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
1786 if (r)
1787 goto out;
1788 r = 0;
1789 break;
1790 }
c4abb7c9
JK		 1791 case KVM_NMI: {
1792 r = kvm_vcpu_ioctl_nmi(vcpu);
1793 if (r)
1794 goto out;
1795 r = 0;
1796 break;
1797 }
313a3dc7
CO		 1798 case KVM_SET_CPUID: {
1799 struct kvm_cpuid __user *cpuid_arg = argp;
1800 struct kvm_cpuid cpuid;
1801
1802 r = -EFAULT;
1803 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1804 goto out;
1805 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
1806 if (r)
1807 goto out;
1808 break;
1809 }
07716717
DK		 1810 case KVM_SET_CPUID2: {
1811 struct kvm_cpuid2 __user *cpuid_arg = argp;
1812 struct kvm_cpuid2 cpuid;
1813
1814 r = -EFAULT;
1815 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1816 goto out;
1817 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 1818 cpuid_arg->entries);
07716717
DK		 1819 if (r)
1820 goto out;
1821 break;
1822 }
1823 case KVM_GET_CPUID2: {
1824 struct kvm_cpuid2 __user *cpuid_arg = argp;
1825 struct kvm_cpuid2 cpuid;
1826
1827 r = -EFAULT;
1828 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1829 goto out;
1830 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 1831 cpuid_arg->entries);
07716717
DK		 1832 if (r)
1833 goto out;
1834 r = -EFAULT;
1835 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1836 goto out;
1837 r = 0;
1838 break;
1839 }
313a3dc7
CO		 1840 case KVM_GET_MSRS:
1841 r = msr_io(vcpu, argp, kvm_get_msr, 1);
1842 break;
1843 case KVM_SET_MSRS:
1844 r = msr_io(vcpu, argp, do_set_msr, 0);
1845 break;
b209749f
AK		 1846 case KVM_TPR_ACCESS_REPORTING: {
1847 struct kvm_tpr_access_ctl tac;
1848
1849 r = -EFAULT;
1850 if (copy_from_user(&tac, argp, sizeof tac))
1851 goto out;
1852 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
1853 if (r)
1854 goto out;
1855 r = -EFAULT;
1856 if (copy_to_user(argp, &tac, sizeof tac))
1857 goto out;
1858 r = 0;
1859 break;
1860 };
b93463aa
AK		 1861 case KVM_SET_VAPIC_ADDR: {
1862 struct kvm_vapic_addr va;
1863
1864 r = -EINVAL;
1865 if (!irqchip_in_kernel(vcpu->kvm))
1866 goto out;
1867 r = -EFAULT;
1868 if (copy_from_user(&va, argp, sizeof va))
1869 goto out;
1870 r = 0;
1871 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
1872 break;
1873 }
890ca9ae
HY		 1874 case KVM_X86_SETUP_MCE: {
1875 u64 mcg_cap;
1876
1877 r = -EFAULT;
1878 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
1879 goto out;
1880 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
1881 break;
1882 }
1883 case KVM_X86_SET_MCE: {
1884 struct kvm_x86_mce mce;
1885
1886 r = -EFAULT;
1887 if (copy_from_user(&mce, argp, sizeof mce))
1888 goto out;
1889 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
1890 break;
1891 }
313a3dc7
CO		 1892 default:
1893 r = -EINVAL;
1894 }
1895out:
7a6ce84c 1896 kfree(lapic);
313a3dc7
CO		 1897 return r;
1898}
1899
1fe779f8
CO		 1900static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
1901{
1902 int ret;
1903
1904 if (addr > (unsigned int)(-3 * PAGE_SIZE))
1905 return -1;
1906 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
1907 return ret;
1908}
1909
1910static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
1911 u32 kvm_nr_mmu_pages)
1912{
1913 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
1914 return -EINVAL;
1915
72dc67a6 1916 down_write(&kvm->slots_lock);
7c8a83b7 1917 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 1918
1919 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 1920 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 1921
7c8a83b7 1922 spin_unlock(&kvm->mmu_lock);
72dc67a6 1923 up_write(&kvm->slots_lock);
1fe779f8
CO		 1924 return 0;
1925}
1926
1927static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
1928{
f05e70ac 1929 return kvm->arch.n_alloc_mmu_pages;
1fe779f8
CO		 1930}
1931
e9f85cde
ZX		 1932gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
1933{
1934 int i;
1935 struct kvm_mem_alias *alias;
1936
d69fb81f
ZX		 1937 for (i = 0; i < kvm->arch.naliases; ++i) {
1938 alias = &kvm->arch.aliases[i];
e9f85cde
ZX		 1939 if (gfn >= alias->base_gfn
1940 && gfn < alias->base_gfn + alias->npages)
1941 return alias->target_gfn + gfn - alias->base_gfn;
1942 }
1943 return gfn;
1944}
1945
1fe779f8
CO		 1946/*
1947 * Set a new alias region. Aliases map a portion of physical memory into
1948 * another portion. This is useful for memory windows, for example the PC
1949 * VGA region.
1950 */
1951static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
1952 struct kvm_memory_alias *alias)
1953{
1954 int r, n;
1955 struct kvm_mem_alias *p;
1956
1957 r = -EINVAL;
1958 /* General sanity checks */
1959 if (alias->memory_size & (PAGE_SIZE - 1))
1960 goto out;
1961 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
1962 goto out;
1963 if (alias->slot >= KVM_ALIAS_SLOTS)
1964 goto out;
1965 if (alias->guest_phys_addr + alias->memory_size
1966 < alias->guest_phys_addr)
1967 goto out;
1968 if (alias->target_phys_addr + alias->memory_size
1969 < alias->target_phys_addr)
1970 goto out;
1971
72dc67a6 1972 down_write(&kvm->slots_lock);
a1708ce8 1973 spin_lock(&kvm->mmu_lock);
1fe779f8 1974
d69fb81f 1975 p = &kvm->arch.aliases[alias->slot];
1fe779f8
CO		 1976 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
1977 p->npages = alias->memory_size >> PAGE_SHIFT;
1978 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
1979
1980 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
d69fb81f 1981 if (kvm->arch.aliases[n - 1].npages)
1fe779f8 1982 break;
d69fb81f 1983 kvm->arch.naliases = n;
1fe779f8 1984
a1708ce8 1985 spin_unlock(&kvm->mmu_lock);
1fe779f8
CO		 1986 kvm_mmu_zap_all(kvm);
1987
72dc67a6 1988 up_write(&kvm->slots_lock);
1fe779f8
CO		 1989
1990 return 0;
1991
1992out:
1993 return r;
1994}
1995
1996static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
1997{
1998 int r;
1999
2000 r = 0;
2001 switch (chip->chip_id) {
2002 case KVM_IRQCHIP_PIC_MASTER:
2003 memcpy(&chip->chip.pic,
2004 &pic_irqchip(kvm)->pics[0],
2005 sizeof(struct kvm_pic_state));
2006 break;
2007 case KVM_IRQCHIP_PIC_SLAVE:
2008 memcpy(&chip->chip.pic,
2009 &pic_irqchip(kvm)->pics[1],
2010 sizeof(struct kvm_pic_state));
2011 break;
2012 case KVM_IRQCHIP_IOAPIC:
2013 memcpy(&chip->chip.ioapic,
2014 ioapic_irqchip(kvm),
2015 sizeof(struct kvm_ioapic_state));
2016 break;
2017 default:
2018 r = -EINVAL;
2019 break;
2020 }
2021 return r;
2022}
2023
2024static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2025{
2026 int r;
2027
2028 r = 0;
2029 switch (chip->chip_id) {
2030 case KVM_IRQCHIP_PIC_MASTER:
894a9c55 2031 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2032 memcpy(&pic_irqchip(kvm)->pics[0],
2033 &chip->chip.pic,
2034 sizeof(struct kvm_pic_state));
894a9c55 2035 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2036 break;
2037 case KVM_IRQCHIP_PIC_SLAVE:
894a9c55 2038 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2039 memcpy(&pic_irqchip(kvm)->pics[1],
2040 &chip->chip.pic,
2041 sizeof(struct kvm_pic_state));
894a9c55 2042 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2043 break;
2044 case KVM_IRQCHIP_IOAPIC:
894a9c55 2045 mutex_lock(&kvm->irq_lock);
1fe779f8
CO		 2046 memcpy(ioapic_irqchip(kvm),
2047 &chip->chip.ioapic,
2048 sizeof(struct kvm_ioapic_state));
894a9c55 2049 mutex_unlock(&kvm->irq_lock);
1fe779f8
CO		 2050 break;
2051 default:
2052 r = -EINVAL;
2053 break;
2054 }
2055 kvm_pic_update_irq(pic_irqchip(kvm));
2056 return r;
2057}
2058
e0f63cb9
SY		 2059static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2060{
2061 int r = 0;
2062
894a9c55 2063 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2064 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 2065 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2066 return r;
2067}
2068
2069static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2070{
2071 int r = 0;
2072
894a9c55 2073 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2074 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 2075 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
2076 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2077 return r;
2078}
2079
2080static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2081{
2082 int r = 0;
2083
2084 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2085 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
2086 sizeof(ps->channels));
2087 ps->flags = kvm->arch.vpit->pit_state.flags;
2088 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2089 return r;
2090}
2091
2092static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2093{
2094 int r = 0, start = 0;
2095 u32 prev_legacy, cur_legacy;
2096 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2097 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
2098 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
2099 if (!prev_legacy && cur_legacy)
2100 start = 1;
2101 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
2102 sizeof(kvm->arch.vpit->pit_state.channels));
2103 kvm->arch.vpit->pit_state.flags = ps->flags;
2104 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 2105 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2106 return r;
2107}
2108
52d939a0
MT		 2109static int kvm_vm_ioctl_reinject(struct kvm *kvm,
2110 struct kvm_reinject_control *control)
2111{
2112 if (!kvm->arch.vpit)
2113 return -ENXIO;
894a9c55 2114 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 2115 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 2116 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 2117 return 0;
2118}
2119
5bb064dc
ZX		 2120/*
2121 * Get (and clear) the dirty memory log for a memory slot.
2122 */
2123int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
2124 struct kvm_dirty_log *log)
2125{
2126 int r;
2127 int n;
2128 struct kvm_memory_slot *memslot;
2129 int is_dirty = 0;
2130
72dc67a6 2131 down_write(&kvm->slots_lock);
5bb064dc
ZX		 2132
2133 r = kvm_get_dirty_log(kvm, log, &is_dirty);
2134 if (r)
2135 goto out;
2136
2137 /* If nothing is dirty, don't bother messing with page tables. */
2138 if (is_dirty) {
7c8a83b7 2139 spin_lock(&kvm->mmu_lock);
5bb064dc 2140 kvm_mmu_slot_remove_write_access(kvm, log->slot);
7c8a83b7 2141 spin_unlock(&kvm->mmu_lock);
5bb064dc
ZX		 2142 kvm_flush_remote_tlbs(kvm);
2143 memslot = &kvm->memslots[log->slot];
2144 n = ALIGN(memslot->npages, BITS_PER_LONG) / 8;
2145 memset(memslot->dirty_bitmap, 0, n);
2146 }
2147 r = 0;
2148out:
72dc67a6 2149 up_write(&kvm->slots_lock);
5bb064dc
ZX		 2150 return r;
2151}
2152
1fe779f8
CO		 2153long kvm_arch_vm_ioctl(struct file *filp,
2154 unsigned int ioctl, unsigned long arg)
2155{
2156 struct kvm *kvm = filp->private_data;
2157 void __user *argp = (void __user *)arg;
2158 int r = -EINVAL;
f0d66275
DH		 2159 /*
2160 * This union makes it completely explicit to gcc-3.x
2161 * that these two variables' stack usage should be
2162 * combined, not added together.
2163 */
2164 union {
2165 struct kvm_pit_state ps;
e9f42757 2166 struct kvm_pit_state2 ps2;
f0d66275 2167 struct kvm_memory_alias alias;
c5ff41ce 2168 struct kvm_pit_config pit_config;
f0d66275 2169 } u;
1fe779f8
CO		 2170
2171 switch (ioctl) {
2172 case KVM_SET_TSS_ADDR:
2173 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
2174 if (r < 0)
2175 goto out;
2176 break;
2177 case KVM_SET_MEMORY_REGION: {
2178 struct kvm_memory_region kvm_mem;
2179 struct kvm_userspace_memory_region kvm_userspace_mem;
2180
2181 r = -EFAULT;
2182 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
2183 goto out;
2184 kvm_userspace_mem.slot = kvm_mem.slot;
2185 kvm_userspace_mem.flags = kvm_mem.flags;
2186 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
2187 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
2188 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
2189 if (r)
2190 goto out;
2191 break;
2192 }
2193 case KVM_SET_NR_MMU_PAGES:
2194 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
2195 if (r)
2196 goto out;
2197 break;
2198 case KVM_GET_NR_MMU_PAGES:
2199 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
2200 break;
f0d66275 2201 case KVM_SET_MEMORY_ALIAS:
1fe779f8 2202 r = -EFAULT;
f0d66275 2203 if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias)))
1fe779f8 2204 goto out;
f0d66275 2205 r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias);
1fe779f8
CO		 2206 if (r)
2207 goto out;
2208 break;
1fe779f8
CO		 2209 case KVM_CREATE_IRQCHIP:
2210 r = -ENOMEM;
d7deeeb0
ZX		 2211 kvm->arch.vpic = kvm_create_pic(kvm);
2212 if (kvm->arch.vpic) {
1fe779f8
CO		 2213 r = kvm_ioapic_init(kvm);
2214 if (r) {
d7deeeb0
ZX		 2215 kfree(kvm->arch.vpic);
2216 kvm->arch.vpic = NULL;
1fe779f8
CO		 2217 goto out;
2218 }
2219 } else
2220 goto out;
399ec807
AK		 2221 r = kvm_setup_default_irq_routing(kvm);
2222 if (r) {
2223 kfree(kvm->arch.vpic);
2224 kfree(kvm->arch.vioapic);
2225 goto out;
2226 }
1fe779f8 2227 break;
7837699f 2228 case KVM_CREATE_PIT:
c5ff41ce
JK		 2229 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
2230 goto create_pit;
2231 case KVM_CREATE_PIT2:
2232 r = -EFAULT;
2233 if (copy_from_user(&u.pit_config, argp,
2234 sizeof(struct kvm_pit_config)))
2235 goto out;
2236 create_pit:
108b5669 2237 down_write(&kvm->slots_lock);
269e05e4
AK		 2238 r = -EEXIST;
2239 if (kvm->arch.vpit)
2240 goto create_pit_unlock;
7837699f 2241 r = -ENOMEM;
c5ff41ce 2242 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 2243 if (kvm->arch.vpit)
2244 r = 0;
269e05e4 2245 create_pit_unlock:
108b5669 2246 up_write(&kvm->slots_lock);
7837699f 2247 break;
4925663a 2248 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 2249 case KVM_IRQ_LINE: {
2250 struct kvm_irq_level irq_event;
2251
2252 r = -EFAULT;
2253 if (copy_from_user(&irq_event, argp, sizeof irq_event))
2254 goto out;
2255 if (irqchip_in_kernel(kvm)) {
4925663a 2256 __s32 status;
fa40a821 2257 mutex_lock(&kvm->irq_lock);
4925663a
GN		 2258 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
2259 irq_event.irq, irq_event.level);
fa40a821 2260 mutex_unlock(&kvm->irq_lock);
4925663a
GN		 2261 if (ioctl == KVM_IRQ_LINE_STATUS) {
2262 irq_event.status = status;
2263 if (copy_to_user(argp, &irq_event,
2264 sizeof irq_event))
2265 goto out;
2266 }
1fe779f8
CO		 2267 r = 0;
2268 }
2269 break;
2270 }
2271 case KVM_GET_IRQCHIP: {
2272 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2273 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2274
f0d66275
DH		 2275 r = -ENOMEM;
2276 if (!chip)
1fe779f8 2277 goto out;
f0d66275
DH		 2278 r = -EFAULT;
2279 if (copy_from_user(chip, argp, sizeof *chip))
2280 goto get_irqchip_out;
1fe779f8
CO		 2281 r = -ENXIO;
2282 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2283 goto get_irqchip_out;
2284 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 2285 if (r)
f0d66275 2286 goto get_irqchip_out;
1fe779f8 2287 r = -EFAULT;
f0d66275
DH		 2288 if (copy_to_user(argp, chip, sizeof *chip))
2289 goto get_irqchip_out;
1fe779f8 2290 r = 0;
f0d66275
DH		 2291 get_irqchip_out:
2292 kfree(chip);
2293 if (r)
2294 goto out;
1fe779f8
CO		 2295 break;
2296 }
2297 case KVM_SET_IRQCHIP: {
2298 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2299 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2300
f0d66275
DH		 2301 r = -ENOMEM;
2302 if (!chip)
1fe779f8 2303 goto out;
f0d66275
DH		 2304 r = -EFAULT;
2305 if (copy_from_user(chip, argp, sizeof *chip))
2306 goto set_irqchip_out;
1fe779f8
CO		 2307 r = -ENXIO;
2308 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2309 goto set_irqchip_out;
2310 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 2311 if (r)
f0d66275 2312 goto set_irqchip_out;
1fe779f8 2313 r = 0;
f0d66275
DH		 2314 set_irqchip_out:
2315 kfree(chip);
2316 if (r)
2317 goto out;
1fe779f8
CO		 2318 break;
2319 }
e0f63cb9 2320 case KVM_GET_PIT: {
e0f63cb9 2321 r = -EFAULT;
f0d66275 2322 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2323 goto out;
2324 r = -ENXIO;
2325 if (!kvm->arch.vpit)
2326 goto out;
f0d66275 2327 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 2328 if (r)
2329 goto out;
2330 r = -EFAULT;
f0d66275 2331 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2332 goto out;
2333 r = 0;
2334 break;
2335 }
2336 case KVM_SET_PIT: {
e0f63cb9 2337 r = -EFAULT;
f0d66275 2338 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 2339 goto out;
2340 r = -ENXIO;
2341 if (!kvm->arch.vpit)
2342 goto out;
f0d66275 2343 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 2344 if (r)
2345 goto out;
2346 r = 0;
2347 break;
2348 }
e9f42757
BK		 2349 case KVM_GET_PIT2: {
2350 r = -ENXIO;
2351 if (!kvm->arch.vpit)
2352 goto out;
2353 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
2354 if (r)
2355 goto out;
2356 r = -EFAULT;
2357 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
2358 goto out;
2359 r = 0;
2360 break;
2361 }
2362 case KVM_SET_PIT2: {
2363 r = -EFAULT;
2364 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
2365 goto out;
2366 r = -ENXIO;
2367 if (!kvm->arch.vpit)
2368 goto out;
2369 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
2370 if (r)
2371 goto out;
2372 r = 0;
2373 break;
2374 }
52d939a0
MT		 2375 case KVM_REINJECT_CONTROL: {
2376 struct kvm_reinject_control control;
2377 r = -EFAULT;
2378 if (copy_from_user(&control, argp, sizeof(control)))
2379 goto out;
2380 r = kvm_vm_ioctl_reinject(kvm, &control);
2381 if (r)
2382 goto out;
2383 r = 0;
2384 break;
2385 }
1fe779f8
CO		 2386 default:
2387 ;
2388 }
2389out:
2390 return r;
2391}
2392
a16b043c 2393static void kvm_init_msr_list(void)
043405e1
CO		 2394{
2395 u32 dummy[2];
2396 unsigned i, j;
2397
2398 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
2399 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
2400 continue;
2401 if (j < i)
2402 msrs_to_save[j] = msrs_to_save[i];
2403 j++;
2404 }
2405 num_msrs_to_save = j;
2406}
2407
bda9020e
MT		 2408static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
2409 const void *v)
bbd9b64e 2410{
bda9020e
MT		 2411 if (vcpu->arch.apic &&
2412 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
2413 return 0;
bbd9b64e 2414
bda9020e 2415 return kvm_io_bus_write(&vcpu->kvm->mmio_bus, addr, len, v);
bbd9b64e
CO		 2416}
2417
bda9020e 2418static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 2419{
bda9020e
MT		 2420 if (vcpu->arch.apic &&
2421 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
2422 return 0;
bbd9b64e 2423
bda9020e 2424 return kvm_io_bus_read(&vcpu->kvm->mmio_bus, addr, len, v);
bbd9b64e
CO		 2425}
2426
cded19f3
HE		 2427static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
2428 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 2429{
2430 void *data = val;
10589a46 2431 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 2432
2433 while (bytes) {
ad312c7c 2434 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e 2435 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 2436 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 2437 int ret;
2438
10589a46
MT		 2439 if (gpa == UNMAPPED_GVA) {
2440 r = X86EMUL_PROPAGATE_FAULT;
2441 goto out;
2442 }
77c2002e 2443 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46
MT		 2444 if (ret < 0) {
2445 r = X86EMUL_UNHANDLEABLE;
2446 goto out;
2447 }
bbd9b64e 2448
77c2002e
IE		 2449 bytes -= toread;
2450 data += toread;
2451 addr += toread;
bbd9b64e 2452 }
10589a46 2453out:
10589a46 2454 return r;
bbd9b64e 2455}
77c2002e 2456
cded19f3
HE		 2457static int kvm_write_guest_virt(gva_t addr, void *val, unsigned int bytes,
2458 struct kvm_vcpu *vcpu)
77c2002e
IE		 2459{
2460 void *data = val;
2461 int r = X86EMUL_CONTINUE;
2462
2463 while (bytes) {
2464 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2465 unsigned offset = addr & (PAGE_SIZE-1);
2466 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
2467 int ret;
2468
2469 if (gpa == UNMAPPED_GVA) {
2470 r = X86EMUL_PROPAGATE_FAULT;
2471 goto out;
2472 }
2473 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
2474 if (ret < 0) {
2475 r = X86EMUL_UNHANDLEABLE;
2476 goto out;
2477 }
2478
2479 bytes -= towrite;
2480 data += towrite;
2481 addr += towrite;
2482 }
2483out:
2484 return r;
2485}
2486
bbd9b64e 2487
bbd9b64e
CO		 2488static int emulator_read_emulated(unsigned long addr,
2489 void *val,
2490 unsigned int bytes,
2491 struct kvm_vcpu *vcpu)
2492{
bbd9b64e
CO		 2493 gpa_t gpa;
2494
2495 if (vcpu->mmio_read_completed) {
2496 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 2497 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
2498 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 2499 vcpu->mmio_read_completed = 0;
2500 return X86EMUL_CONTINUE;
2501 }
2502
ad312c7c 2503 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2504
2505 /* For APIC access vmexit */
2506 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2507 goto mmio;
2508
77c2002e
IE		 2509 if (kvm_read_guest_virt(addr, val, bytes, vcpu)
2510 == X86EMUL_CONTINUE)
bbd9b64e
CO		 2511 return X86EMUL_CONTINUE;
2512 if (gpa == UNMAPPED_GVA)
2513 return X86EMUL_PROPAGATE_FAULT;
2514
2515mmio:
2516 /*
2517 * Is this MMIO handled locally?
2518 */
aec51dc4
AK		 2519 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
2520 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
bbd9b64e 2521 return X86EMUL_CONTINUE;
aec51dc4
AK		 2522 }
2523
2524 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 2525
2526 vcpu->mmio_needed = 1;
2527 vcpu->mmio_phys_addr = gpa;
2528 vcpu->mmio_size = bytes;
2529 vcpu->mmio_is_write = 0;
2530
2531 return X86EMUL_UNHANDLEABLE;
2532}
2533
3200f405 2534int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 2535 const void *val, int bytes)
bbd9b64e
CO		 2536{
2537 int ret;
2538
2539 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 2540 if (ret < 0)
bbd9b64e 2541 return 0;
ad218f85 2542 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 2543 return 1;
2544}
2545
2546static int emulator_write_emulated_onepage(unsigned long addr,
2547 const void *val,
2548 unsigned int bytes,
2549 struct kvm_vcpu *vcpu)
2550{
10589a46
MT		 2551 gpa_t gpa;
2552
10589a46 2553 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2554
2555 if (gpa == UNMAPPED_GVA) {
c3c91fee 2556 kvm_inject_page_fault(vcpu, addr, 2);
bbd9b64e
CO		 2557 return X86EMUL_PROPAGATE_FAULT;
2558 }
2559
2560 /* For APIC access vmexit */
2561 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2562 goto mmio;
2563
2564 if (emulator_write_phys(vcpu, gpa, val, bytes))
2565 return X86EMUL_CONTINUE;
2566
2567mmio:
aec51dc4 2568 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 2569 /*
2570 * Is this MMIO handled locally?
2571 */
bda9020e 2572 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
bbd9b64e 2573 return X86EMUL_CONTINUE;
bbd9b64e
CO		 2574
2575 vcpu->mmio_needed = 1;
2576 vcpu->mmio_phys_addr = gpa;
2577 vcpu->mmio_size = bytes;
2578 vcpu->mmio_is_write = 1;
2579 memcpy(vcpu->mmio_data, val, bytes);
2580
2581 return X86EMUL_CONTINUE;
2582}
2583
2584int emulator_write_emulated(unsigned long addr,
2585 const void *val,
2586 unsigned int bytes,
2587 struct kvm_vcpu *vcpu)
2588{
2589 /* Crossing a page boundary? */
2590 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
2591 int rc, now;
2592
2593 now = -addr & ~PAGE_MASK;
2594 rc = emulator_write_emulated_onepage(addr, val, now, vcpu);
2595 if (rc != X86EMUL_CONTINUE)
2596 return rc;
2597 addr += now;
2598 val += now;
2599 bytes -= now;
2600 }
2601 return emulator_write_emulated_onepage(addr, val, bytes, vcpu);
2602}
2603EXPORT_SYMBOL_GPL(emulator_write_emulated);
2604
2605static int emulator_cmpxchg_emulated(unsigned long addr,
2606 const void *old,
2607 const void *new,
2608 unsigned int bytes,
2609 struct kvm_vcpu *vcpu)
2610{
2611 static int reported;
2612
2613 if (!reported) {
2614 reported = 1;
2615 printk(KERN_WARNING "kvm: emulating exchange as write\n");
2616 }
2bacc55c
MT		 2617#ifndef CONFIG_X86_64
2618 /* guests cmpxchg8b have to be emulated atomically */
2619 if (bytes == 8) {
10589a46 2620 gpa_t gpa;
2bacc55c 2621 struct page *page;
c0b49b0d 2622 char *kaddr;
2bacc55c
MT		 2623 u64 val;
2624
10589a46
MT		 2625 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2626
2bacc55c
MT		 2627 if (gpa == UNMAPPED_GVA ||
2628 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2629 goto emul_write;
2630
2631 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
2632 goto emul_write;
2633
2634 val = *(u64 *)new;
72dc67a6 2635
2bacc55c 2636 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6 2637
c0b49b0d
AM		 2638 kaddr = kmap_atomic(page, KM_USER0);
2639 set_64bit((u64 *)(kaddr + offset_in_page(gpa)), val);
2640 kunmap_atomic(kaddr, KM_USER0);
2bacc55c
MT		 2641 kvm_release_page_dirty(page);
2642 }
3200f405 2643emul_write:
2bacc55c
MT		 2644#endif
2645
bbd9b64e
CO		 2646 return emulator_write_emulated(addr, new, bytes, vcpu);
2647}
2648
2649static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
2650{
2651 return kvm_x86_ops->get_segment_base(vcpu, seg);
2652}
2653
2654int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
2655{
a7052897 2656 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 2657 return X86EMUL_CONTINUE;
2658}
2659
2660int emulate_clts(struct kvm_vcpu *vcpu)
2661{
ad312c7c 2662 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 & ~X86_CR0_TS);
bbd9b64e
CO		 2663 return X86EMUL_CONTINUE;
2664}
2665
2666int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
2667{
2668 struct kvm_vcpu *vcpu = ctxt->vcpu;
2669
2670 switch (dr) {
2671 case 0 ... 3:
2672 *dest = kvm_x86_ops->get_dr(vcpu, dr);
2673 return X86EMUL_CONTINUE;
2674 default:
b8688d51 2675 pr_unimpl(vcpu, "%s: unexpected dr %u\n", __func__, dr);
bbd9b64e
CO		 2676 return X86EMUL_UNHANDLEABLE;
2677 }
2678}
2679
2680int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
2681{
2682 unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U;
2683 int exception;
2684
2685 kvm_x86_ops->set_dr(ctxt->vcpu, dr, value & mask, &exception);
2686 if (exception) {
2687 /* FIXME: better handling */
2688 return X86EMUL_UNHANDLEABLE;
2689 }
2690 return X86EMUL_CONTINUE;
2691}
2692
2693void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context)
2694{
bbd9b64e 2695 u8 opcodes[4];
5fdbf976 2696 unsigned long rip = kvm_rip_read(vcpu);
bbd9b64e
CO		 2697 unsigned long rip_linear;
2698
f76c710d 2699 if (!printk_ratelimit())
bbd9b64e
CO		 2700 return;
2701
25be4608
GC		 2702 rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS);
2703
77c2002e 2704 kvm_read_guest_virt(rip_linear, (void *)opcodes, 4, vcpu);
bbd9b64e
CO		 2705
2706 printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n",
2707 context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]);
bbd9b64e
CO		 2708}
2709EXPORT_SYMBOL_GPL(kvm_report_emulation_failure);
2710
14af3f3c 2711static struct x86_emulate_ops emulate_ops = {
77c2002e 2712 .read_std = kvm_read_guest_virt,
bbd9b64e
CO		 2713 .read_emulated = emulator_read_emulated,
2714 .write_emulated = emulator_write_emulated,
2715 .cmpxchg_emulated = emulator_cmpxchg_emulated,
2716};
2717
5fdbf976
MT		 2718static void cache_all_regs(struct kvm_vcpu *vcpu)
2719{
2720 kvm_register_read(vcpu, VCPU_REGS_RAX);
2721 kvm_register_read(vcpu, VCPU_REGS_RSP);
2722 kvm_register_read(vcpu, VCPU_REGS_RIP);
2723 vcpu->arch.regs_dirty = ~0;
2724}
2725
bbd9b64e
CO		 2726int emulate_instruction(struct kvm_vcpu *vcpu,
2727 struct kvm_run *run,
2728 unsigned long cr2,
2729 u16 error_code,
571008da 2730 int emulation_type)
bbd9b64e 2731{
310b5d30 2732 int r, shadow_mask;
571008da 2733 struct decode_cache *c;
bbd9b64e 2734
26eef70c 2735 kvm_clear_exception_queue(vcpu);
ad312c7c 2736 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976
MT		 2737 /*
2738 * TODO: fix x86_emulate.c to use guest_read/write_register
2739 * instead of direct ->regs accesses, can save hundred cycles
2740 * on Intel for instructions that don't read/change RSP, for
2741 * for example.
2742 */
2743 cache_all_regs(vcpu);
bbd9b64e
CO		 2744
2745 vcpu->mmio_is_write = 0;
ad312c7c 2746 vcpu->arch.pio.string = 0;
bbd9b64e 2747
571008da 2748 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
bbd9b64e
CO		 2749 int cs_db, cs_l;
2750 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
2751
ad312c7c
ZX		 2752 vcpu->arch.emulate_ctxt.vcpu = vcpu;
2753 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
2754 vcpu->arch.emulate_ctxt.mode =
2755 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
bbd9b64e
CO		 2756 ? X86EMUL_MODE_REAL : cs_l
2757 ? X86EMUL_MODE_PROT64 : cs_db
2758 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
2759
ad312c7c 2760 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
571008da 2761
0cb5762e
AP		 2762 /* Only allow emulation of specific instructions on #UD
2763 * (namely VMMCALL, sysenter, sysexit, syscall)*/
571008da 2764 c = &vcpu->arch.emulate_ctxt.decode;
0cb5762e
AP		 2765 if (emulation_type & EMULTYPE_TRAP_UD) {
2766 if (!c->twobyte)
2767 return EMULATE_FAIL;
2768 switch (c->b) {
2769 case 0x01: /* VMMCALL */
2770 if (c->modrm_mod != 3 || c->modrm_rm != 1)
2771 return EMULATE_FAIL;
2772 break;
2773 case 0x34: /* sysenter */
2774 case 0x35: /* sysexit */
2775 if (c->modrm_mod != 0 || c->modrm_rm != 0)
2776 return EMULATE_FAIL;
2777 break;
2778 case 0x05: /* syscall */
2779 if (c->modrm_mod != 0 || c->modrm_rm != 0)
2780 return EMULATE_FAIL;
2781 break;
2782 default:
2783 return EMULATE_FAIL;
2784 }
2785
2786 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
2787 return EMULATE_FAIL;
2788 }
571008da 2789
f2b5756b 2790 ++vcpu->stat.insn_emulation;
bbd9b64e 2791 if (r) {
f2b5756b 2792 ++vcpu->stat.insn_emulation_fail;
bbd9b64e
CO		 2793 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2794 return EMULATE_DONE;
2795 return EMULATE_FAIL;
2796 }
2797 }
2798
ba8afb6b
GN		 2799 if (emulation_type & EMULTYPE_SKIP) {
2800 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
2801 return EMULATE_DONE;
2802 }
2803
ad312c7c 2804 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
310b5d30
GC		 2805 shadow_mask = vcpu->arch.emulate_ctxt.interruptibility;
2806
2807 if (r == 0)
2808 kvm_x86_ops->set_interrupt_shadow(vcpu, shadow_mask);
bbd9b64e 2809
ad312c7c 2810 if (vcpu->arch.pio.string)
bbd9b64e
CO		 2811 return EMULATE_DO_MMIO;
2812
2813 if ((r || vcpu->mmio_is_write) && run) {
2814 run->exit_reason = KVM_EXIT_MMIO;
2815 run->mmio.phys_addr = vcpu->mmio_phys_addr;
2816 memcpy(run->mmio.data, vcpu->mmio_data, 8);
2817 run->mmio.len = vcpu->mmio_size;
2818 run->mmio.is_write = vcpu->mmio_is_write;
2819 }
2820
2821 if (r) {
2822 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2823 return EMULATE_DONE;
2824 if (!vcpu->mmio_needed) {
2825 kvm_report_emulation_failure(vcpu, "mmio");
2826 return EMULATE_FAIL;
2827 }
2828 return EMULATE_DO_MMIO;
2829 }
2830
ad312c7c 2831 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
bbd9b64e
CO		 2832
2833 if (vcpu->mmio_is_write) {
2834 vcpu->mmio_needed = 0;
2835 return EMULATE_DO_MMIO;
2836 }
2837
2838 return EMULATE_DONE;
2839}
2840EXPORT_SYMBOL_GPL(emulate_instruction);
2841
de7d789a
CO		 2842static int pio_copy_data(struct kvm_vcpu *vcpu)
2843{
ad312c7c 2844 void *p = vcpu->arch.pio_data;
0f346074 2845 gva_t q = vcpu->arch.pio.guest_gva;
de7d789a 2846 unsigned bytes;
0f346074 2847 int ret;
de7d789a 2848
ad312c7c
ZX		 2849 bytes = vcpu->arch.pio.size * vcpu->arch.pio.cur_count;
2850 if (vcpu->arch.pio.in)
0f346074 2851 ret = kvm_write_guest_virt(q, p, bytes, vcpu);
de7d789a 2852 else
0f346074
IE		 2853 ret = kvm_read_guest_virt(q, p, bytes, vcpu);
2854 return ret;
de7d789a
CO		 2855}
2856
2857int complete_pio(struct kvm_vcpu *vcpu)
2858{
ad312c7c 2859 struct kvm_pio_request *io = &vcpu->arch.pio;
de7d789a
CO		 2860 long delta;
2861 int r;
5fdbf976 2862 unsigned long val;
de7d789a
CO		 2863
2864 if (!io->string) {
5fdbf976
MT		 2865 if (io->in) {
2866 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2867 memcpy(&val, vcpu->arch.pio_data, io->size);
2868 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
2869 }
de7d789a
CO		 2870 } else {
2871 if (io->in) {
2872 r = pio_copy_data(vcpu);
5fdbf976 2873 if (r)
de7d789a 2874 return r;
de7d789a
CO		 2875 }
2876
2877 delta = 1;
2878 if (io->rep) {
2879 delta *= io->cur_count;
2880 /*
2881 * The size of the register should really depend on
2882 * current address size.
2883 */
5fdbf976
MT		 2884 val = kvm_register_read(vcpu, VCPU_REGS_RCX);
2885 val -= delta;
2886 kvm_register_write(vcpu, VCPU_REGS_RCX, val);
de7d789a
CO		 2887 }
2888 if (io->down)
2889 delta = -delta;
2890 delta *= io->size;
5fdbf976
MT		 2891 if (io->in) {
2892 val = kvm_register_read(vcpu, VCPU_REGS_RDI);
2893 val += delta;
2894 kvm_register_write(vcpu, VCPU_REGS_RDI, val);
2895 } else {
2896 val = kvm_register_read(vcpu, VCPU_REGS_RSI);
2897 val += delta;
2898 kvm_register_write(vcpu, VCPU_REGS_RSI, val);
2899 }
de7d789a
CO		 2900 }
2901
de7d789a
CO		 2902 io->count -= io->cur_count;
2903 io->cur_count = 0;
2904
2905 return 0;
2906}
2907
bda9020e 2908static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
de7d789a
CO		 2909{
2910 /* TODO: String I/O for in kernel device */
bda9020e 2911 int r;
de7d789a 2912
ad312c7c 2913 if (vcpu->arch.pio.in)
bda9020e
MT		 2914 r = kvm_io_bus_read(&vcpu->kvm->pio_bus, vcpu->arch.pio.port,
2915 vcpu->arch.pio.size, pd);
de7d789a 2916 else
bda9020e
MT		 2917 r = kvm_io_bus_write(&vcpu->kvm->pio_bus, vcpu->arch.pio.port,
2918 vcpu->arch.pio.size, pd);
2919 return r;
de7d789a
CO		 2920}
2921
bda9020e 2922static int pio_string_write(struct kvm_vcpu *vcpu)
de7d789a 2923{
ad312c7c
ZX		 2924 struct kvm_pio_request *io = &vcpu->arch.pio;
2925 void *pd = vcpu->arch.pio_data;
bda9020e 2926 int i, r = 0;
de7d789a 2927
de7d789a 2928 for (i = 0; i < io->cur_count; i++) {
bda9020e
MT		 2929 if (kvm_io_bus_write(&vcpu->kvm->pio_bus,
2930 io->port, io->size, pd)) {
2931 r = -EOPNOTSUPP;
2932 break;
2933 }
de7d789a
CO		 2934 pd += io->size;
2935 }
bda9020e 2936 return r;
de7d789a
CO		 2937}
2938
2939int kvm_emulate_pio(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2940 int size, unsigned port)
2941{
5fdbf976 2942 unsigned long val;
de7d789a
CO		 2943
2944 vcpu->run->exit_reason = KVM_EXIT_IO;
2945 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 2946 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 2947 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 2948 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = 1;
2949 vcpu->run->io.port = vcpu->arch.pio.port = port;
2950 vcpu->arch.pio.in = in;
2951 vcpu->arch.pio.string = 0;
2952 vcpu->arch.pio.down = 0;
ad312c7c 2953 vcpu->arch.pio.rep = 0;
de7d789a 2954
229456fc
MT		 2955 trace_kvm_pio(vcpu->run->io.direction == KVM_EXIT_IO_OUT, port,
2956 size, 1);
2714d1d3 2957
5fdbf976
MT		 2958 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2959 memcpy(vcpu->arch.pio_data, &val, 4);
de7d789a 2960
bda9020e 2961 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
de7d789a
CO		 2962 complete_pio(vcpu);
2963 return 1;
2964 }
2965 return 0;
2966}
2967EXPORT_SYMBOL_GPL(kvm_emulate_pio);
2968
2969int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2970 int size, unsigned long count, int down,
2971 gva_t address, int rep, unsigned port)
2972{
2973 unsigned now, in_page;
0f346074 2974 int ret = 0;
de7d789a
CO		 2975
2976 vcpu->run->exit_reason = KVM_EXIT_IO;
2977 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 2978 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 2979 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 2980 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = count;
2981 vcpu->run->io.port = vcpu->arch.pio.port = port;
2982 vcpu->arch.pio.in = in;
2983 vcpu->arch.pio.string = 1;
2984 vcpu->arch.pio.down = down;
ad312c7c 2985 vcpu->arch.pio.rep = rep;
de7d789a 2986
229456fc
MT		 2987 trace_kvm_pio(vcpu->run->io.direction == KVM_EXIT_IO_OUT, port,
2988 size, count);
2714d1d3 2989
de7d789a
CO		 2990 if (!count) {
2991 kvm_x86_ops->skip_emulated_instruction(vcpu);
2992 return 1;
2993 }
2994
2995 if (!down)
2996 in_page = PAGE_SIZE - offset_in_page(address);
2997 else
2998 in_page = offset_in_page(address) + size;
2999 now = min(count, (unsigned long)in_page / size);
0f346074 3000 if (!now)
de7d789a 3001 now = 1;
de7d789a
CO		 3002 if (down) {
3003 /*
3004 * String I/O in reverse. Yuck. Kill the guest, fix later.
3005 */
3006 pr_unimpl(vcpu, "guest string pio down\n");
c1a5d4f9 3007 kvm_inject_gp(vcpu, 0);
de7d789a
CO		 3008 return 1;
3009 }
3010 vcpu->run->io.count = now;
ad312c7c 3011 vcpu->arch.pio.cur_count = now;
de7d789a 3012
ad312c7c 3013 if (vcpu->arch.pio.cur_count == vcpu->arch.pio.count)
de7d789a
CO		 3014 kvm_x86_ops->skip_emulated_instruction(vcpu);
3015
0f346074 3016 vcpu->arch.pio.guest_gva = address;
de7d789a 3017
ad312c7c 3018 if (!vcpu->arch.pio.in) {
de7d789a
CO		 3019 /* string PIO write */
3020 ret = pio_copy_data(vcpu);
0f346074
IE		 3021 if (ret == X86EMUL_PROPAGATE_FAULT) {
3022 kvm_inject_gp(vcpu, 0);
3023 return 1;
3024 }
bda9020e 3025 if (ret == 0 && !pio_string_write(vcpu)) {
de7d789a 3026 complete_pio(vcpu);
ad312c7c 3027 if (vcpu->arch.pio.count == 0)
de7d789a
CO		 3028 ret = 1;
3029 }
bda9020e
MT		 3030 }
3031 /* no string PIO read support yet */
de7d789a
CO		 3032
3033 return ret;
3034}
3035EXPORT_SYMBOL_GPL(kvm_emulate_pio_string);
3036
c8076604
GH		 3037static void bounce_off(void *info)
3038{
3039 /* nothing */
3040}
3041
3042static unsigned int ref_freq;
3043static unsigned long tsc_khz_ref;
3044
3045static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
3046 void *data)
3047{
3048 struct cpufreq_freqs *freq = data;
3049 struct kvm *kvm;
3050 struct kvm_vcpu *vcpu;
3051 int i, send_ipi = 0;
3052
3053 if (!ref_freq)
3054 ref_freq = freq->old;
3055
3056 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
3057 return 0;
3058 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
3059 return 0;
3060 per_cpu(cpu_tsc_khz, freq->cpu) = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new);
3061
3062 spin_lock(&kvm_lock);
3063 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 3064 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 3065 if (vcpu->cpu != freq->cpu)
3066 continue;
3067 if (!kvm_request_guest_time_update(vcpu))
3068 continue;
3069 if (vcpu->cpu != smp_processor_id())
3070 send_ipi++;
3071 }
3072 }
3073 spin_unlock(&kvm_lock);
3074
3075 if (freq->old < freq->new && send_ipi) {
3076 /*
3077 * We upscale the frequency. Must make the guest
3078 * doesn't see old kvmclock values while running with
3079 * the new frequency, otherwise we risk the guest sees
3080 * time go backwards.
3081 *
3082 * In case we update the frequency for another cpu
3083 * (which might be in guest context) send an interrupt
3084 * to kick the cpu out of guest context. Next time
3085 * guest context is entered kvmclock will be updated,
3086 * so the guest will not see stale values.
3087 */
3088 smp_call_function_single(freq->cpu, bounce_off, NULL, 1);
3089 }
3090 return 0;
3091}
3092
3093static struct notifier_block kvmclock_cpufreq_notifier_block = {
3094 .notifier_call = kvmclock_cpufreq_notifier
3095};
3096
f8c16bba 3097int kvm_arch_init(void *opaque)
043405e1 3098{
c8076604 3099 int r, cpu;
f8c16bba
ZX		 3100 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
3101
f8c16bba
ZX		 3102 if (kvm_x86_ops) {
3103 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 3104 r = -EEXIST;
3105 goto out;
f8c16bba
ZX		 3106 }
3107
3108 if (!ops->cpu_has_kvm_support()) {
3109 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 3110 r = -EOPNOTSUPP;
3111 goto out;
f8c16bba
ZX		 3112 }
3113 if (ops->disabled_by_bios()) {
3114 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 3115 r = -EOPNOTSUPP;
3116 goto out;
f8c16bba
ZX		 3117 }
3118
97db56ce
AK		 3119 r = kvm_mmu_module_init();
3120 if (r)
3121 goto out;
3122
3123 kvm_init_msr_list();
3124
f8c16bba 3125 kvm_x86_ops = ops;
56c6d28a 3126 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 3127 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
3128 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 3129 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604
GH		 3130
3131 for_each_possible_cpu(cpu)
3132 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
3133 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
3134 tsc_khz_ref = tsc_khz;
3135 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
3136 CPUFREQ_TRANSITION_NOTIFIER);
3137 }
3138
f8c16bba 3139 return 0;
56c6d28a
ZX		 3140
3141out:
56c6d28a 3142 return r;
043405e1 3143}
8776e519 3144
f8c16bba
ZX		 3145void kvm_arch_exit(void)
3146{
888d256e
JK		 3147 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
3148 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
3149 CPUFREQ_TRANSITION_NOTIFIER);
f8c16bba 3150 kvm_x86_ops = NULL;
56c6d28a
ZX		 3151 kvm_mmu_module_exit();
3152}
f8c16bba 3153
8776e519
HB		 3154int kvm_emulate_halt(struct kvm_vcpu *vcpu)
3155{
3156 ++vcpu->stat.halt_exits;
3157 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 3158 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 3159 return 1;
3160 } else {
3161 vcpu->run->exit_reason = KVM_EXIT_HLT;
3162 return 0;
3163 }
3164}
3165EXPORT_SYMBOL_GPL(kvm_emulate_halt);
3166
2f333bcb
MT		 3167static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
3168 unsigned long a1)
3169{
3170 if (is_long_mode(vcpu))
3171 return a0;
3172 else
3173 return a0 | ((gpa_t)a1 << 32);
3174}
3175
8776e519
HB		 3176int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
3177{
3178 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 3179 int r = 1;
8776e519 3180
5fdbf976
MT		 3181 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
3182 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
3183 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
3184 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
3185 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 3186
229456fc 3187 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 3188
8776e519
HB		 3189 if (!is_long_mode(vcpu)) {
3190 nr &= 0xFFFFFFFF;
3191 a0 &= 0xFFFFFFFF;
3192 a1 &= 0xFFFFFFFF;
3193 a2 &= 0xFFFFFFFF;
3194 a3 &= 0xFFFFFFFF;
3195 }
3196
3197 switch (nr) {
b93463aa
AK		 3198 case KVM_HC_VAPIC_POLL_IRQ:
3199 ret = 0;
3200 break;
2f333bcb
MT		 3201 case KVM_HC_MMU_OP:
3202 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
3203 break;
8776e519
HB		 3204 default:
3205 ret = -KVM_ENOSYS;
3206 break;
3207 }
5fdbf976 3208 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 3209 ++vcpu->stat.hypercalls;
2f333bcb 3210 return r;
8776e519
HB		 3211}
3212EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
3213
3214int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
3215{
3216 char instruction[3];
3217 int ret = 0;
5fdbf976 3218 unsigned long rip = kvm_rip_read(vcpu);
8776e519 3219
8776e519
HB		 3220
3221 /*
3222 * Blow out the MMU to ensure that no other VCPU has an active mapping
3223 * to ensure that the updated hypercall appears atomically across all
3224 * VCPUs.
3225 */
3226 kvm_mmu_zap_all(vcpu->kvm);
3227
8776e519 3228 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5fdbf976 3229 if (emulator_write_emulated(rip, instruction, 3, vcpu)
8776e519
HB		 3230 != X86EMUL_CONTINUE)
3231 ret = -EFAULT;
3232
8776e519
HB		 3233 return ret;
3234}
3235
3236static u64 mk_cr_64(u64 curr_cr, u32 new_val)
3237{
3238 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
3239}
3240
3241void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
3242{
3243 struct descriptor_table dt = { limit, base };
3244
3245 kvm_x86_ops->set_gdt(vcpu, &dt);
3246}
3247
3248void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
3249{
3250 struct descriptor_table dt = { limit, base };
3251
3252 kvm_x86_ops->set_idt(vcpu, &dt);
3253}
3254
3255void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw,
3256 unsigned long *rflags)
3257{
2d3ad1f4 3258 kvm_lmsw(vcpu, msw);
8776e519
HB		 3259 *rflags = kvm_x86_ops->get_rflags(vcpu);
3260}
3261
3262unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr)
3263{
54e445ca
JR		 3264 unsigned long value;
3265
8776e519
HB		 3266 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
3267 switch (cr) {
3268 case 0:
54e445ca
JR		 3269 value = vcpu->arch.cr0;
3270 break;
8776e519 3271 case 2:
54e445ca
JR		 3272 value = vcpu->arch.cr2;
3273 break;
8776e519 3274 case 3:
54e445ca
JR		 3275 value = vcpu->arch.cr3;
3276 break;
8776e519 3277 case 4:
54e445ca
JR		 3278 value = vcpu->arch.cr4;
3279 break;
152ff9be 3280 case 8:
54e445ca
JR		 3281 value = kvm_get_cr8(vcpu);
3282 break;
8776e519 3283 default:
b8688d51 3284 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 3285 return 0;
3286 }
54e445ca
JR		 3287
3288 return value;
8776e519
HB		 3289}
3290
3291void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long val,
3292 unsigned long *rflags)
3293{
3294 switch (cr) {
3295 case 0:
2d3ad1f4 3296 kvm_set_cr0(vcpu, mk_cr_64(vcpu->arch.cr0, val));
8776e519
HB		 3297 *rflags = kvm_x86_ops->get_rflags(vcpu);
3298 break;
3299 case 2:
ad312c7c 3300 vcpu->arch.cr2 = val;
8776e519
HB		 3301 break;
3302 case 3:
2d3ad1f4 3303 kvm_set_cr3(vcpu, val);
8776e519
HB		 3304 break;
3305 case 4:
2d3ad1f4 3306 kvm_set_cr4(vcpu, mk_cr_64(vcpu->arch.cr4, val));
8776e519 3307 break;
152ff9be 3308 case 8:
2d3ad1f4 3309 kvm_set_cr8(vcpu, val & 0xfUL);
152ff9be 3310 break;
8776e519 3311 default:
b8688d51 3312 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 3313 }
3314}
3315
07716717
DK		 3316static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
3317{
ad312c7c
ZX		 3318 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
3319 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 3320
3321 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
3322 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 3323 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 3324 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 3325 if (ej->function == e->function) {
3326 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
3327 return j;
3328 }
3329 }
3330 return 0; /* silence gcc, even though control never reaches here */
3331}
3332
3333/* find an entry with matching function, matching index (if needed), and that
3334 * should be read next (if it's stateful) */
3335static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
3336 u32 function, u32 index)
3337{
3338 if (e->function != function)
3339 return 0;
3340 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
3341 return 0;
3342 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 3343 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 3344 return 0;
3345 return 1;
3346}
3347
d8017474
AG		 3348struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
3349 u32 function, u32 index)
8776e519
HB		 3350{
3351 int i;
d8017474 3352 struct kvm_cpuid_entry2 *best = NULL;
8776e519 3353
ad312c7c 3354 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 3355 struct kvm_cpuid_entry2 *e;
3356
ad312c7c 3357 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 3358 if (is_matching_cpuid_entry(e, function, index)) {
3359 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
3360 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 3361 best = e;
3362 break;
3363 }
3364 /*
3365 * Both basic or both extended?
3366 */
3367 if (((e->function ^ function) & 0x80000000) == 0)
3368 if (!best || e->function > best->function)
3369 best = e;
3370 }
d8017474
AG		 3371 return best;
3372}
3373
82725b20
DE		 3374int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
3375{
3376 struct kvm_cpuid_entry2 *best;
3377
3378 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
3379 if (best)
3380 return best->eax & 0xff;
3381 return 36;
3382}
3383
d8017474
AG		 3384void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
3385{
3386 u32 function, index;
3387 struct kvm_cpuid_entry2 *best;
3388
3389 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
3390 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3391 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
3392 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
3393 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
3394 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
3395 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 3396 if (best) {
5fdbf976
MT		 3397 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
3398 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
3399 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
3400 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 3401 }
8776e519 3402 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 3403 trace_kvm_cpuid(function,
3404 kvm_register_read(vcpu, VCPU_REGS_RAX),
3405 kvm_register_read(vcpu, VCPU_REGS_RBX),
3406 kvm_register_read(vcpu, VCPU_REGS_RCX),
3407 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 3408}
3409EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 3410
b6c7a5dc
HB		 3411/*
3412 * Check if userspace requested an interrupt window, and that the
3413 * interrupt window is open.
3414 *
3415 * No need to exit to userspace if we already have an interrupt queued.
3416 */
3417static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu,
3418 struct kvm_run *kvm_run)
3419{
8061823a 3420 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
b6c7a5dc 3421 kvm_run->request_interrupt_window &&
5df56646 3422 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 3423}
3424
3425static void post_kvm_run_save(struct kvm_vcpu *vcpu,
3426 struct kvm_run *kvm_run)
3427{
3428 kvm_run->if_flag = (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 3429 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 3430 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 3431 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 3432 kvm_run->ready_for_interrupt_injection = 1;
4531220b 3433 else
b6c7a5dc 3434 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 3435 kvm_arch_interrupt_allowed(vcpu) &&
3436 !kvm_cpu_has_interrupt(vcpu) &&
3437 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 3438}
3439
b93463aa
AK		 3440static void vapic_enter(struct kvm_vcpu *vcpu)
3441{
3442 struct kvm_lapic *apic = vcpu->arch.apic;
3443 struct page *page;
3444
3445 if (!apic || !apic->vapic_addr)
3446 return;
3447
3448 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 3449
3450 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 3451}
3452
3453static void vapic_exit(struct kvm_vcpu *vcpu)
3454{
3455 struct kvm_lapic *apic = vcpu->arch.apic;
3456
3457 if (!apic || !apic->vapic_addr)
3458 return;
3459
f8b78fa3 3460 down_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 3461 kvm_release_page_dirty(apic->vapic_page);
3462 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f8b78fa3 3463 up_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 3464}
3465
95ba8273
GN		 3466static void update_cr8_intercept(struct kvm_vcpu *vcpu)
3467{
3468 int max_irr, tpr;
3469
3470 if (!kvm_x86_ops->update_cr8_intercept)
3471 return;
3472
8db3baa2
GN		 3473 if (!vcpu->arch.apic->vapic_addr)
3474 max_irr = kvm_lapic_find_highest_irr(vcpu);
3475 else
3476 max_irr = -1;
95ba8273
GN		 3477
3478 if (max_irr != -1)
3479 max_irr >>= 4;
3480
3481 tpr = kvm_lapic_get_cr8(vcpu);
3482
3483 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
3484}
3485
b59bb7bd 3486static void inject_pending_event(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
95ba8273
GN		 3487{
3488 /* try to reinject previous events if any */
b59bb7bd
GN		 3489 if (vcpu->arch.exception.pending) {
3490 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
3491 vcpu->arch.exception.has_error_code,
3492 vcpu->arch.exception.error_code);
3493 return;
3494 }
3495
95ba8273
GN		 3496 if (vcpu->arch.nmi_injected) {
3497 kvm_x86_ops->set_nmi(vcpu);
3498 return;
3499 }
3500
3501 if (vcpu->arch.interrupt.pending) {
66fd3f7f 3502 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 3503 return;
3504 }
3505
3506 /* try to inject new event if pending */
3507 if (vcpu->arch.nmi_pending) {
3508 if (kvm_x86_ops->nmi_allowed(vcpu)) {
3509 vcpu->arch.nmi_pending = false;
3510 vcpu->arch.nmi_injected = true;
3511 kvm_x86_ops->set_nmi(vcpu);
3512 }
3513 } else if (kvm_cpu_has_interrupt(vcpu)) {
3514 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 3515 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
3516 false);
3517 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 3518 }
3519 }
3520}
3521
d7690175 3522static int vcpu_enter_guest(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
b6c7a5dc
HB		 3523{
3524 int r;
6a8b1d13
GN		 3525 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
3526 kvm_run->request_interrupt_window;
b6c7a5dc 3527
2e53d63a
MT		 3528 if (vcpu->requests)
3529 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
3530 kvm_mmu_unload(vcpu);
3531
b6c7a5dc
HB		 3532 r = kvm_mmu_reload(vcpu);
3533 if (unlikely(r))
3534 goto out;
3535
2f52d58c
AK		 3536 if (vcpu->requests) {
3537 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
2f599714 3538 __kvm_migrate_timers(vcpu);
c8076604
GH		 3539 if (test_and_clear_bit(KVM_REQ_KVMCLOCK_UPDATE, &vcpu->requests))
3540 kvm_write_guest_time(vcpu);
4731d4c7
MT		 3541 if (test_and_clear_bit(KVM_REQ_MMU_SYNC, &vcpu->requests))
3542 kvm_mmu_sync_roots(vcpu);
d4acf7e7
MT		 3543 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
3544 kvm_x86_ops->tlb_flush(vcpu);
b93463aa
AK		 3545 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
3546 &vcpu->requests)) {
3547 kvm_run->exit_reason = KVM_EXIT_TPR_ACCESS;
3548 r = 0;
3549 goto out;
3550 }
71c4dfaf
JR		 3551 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
3552 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
3553 r = 0;
3554 goto out;
3555 }
2f52d58c 3556 }
b93463aa 3557
b6c7a5dc
HB		 3558 preempt_disable();
3559
3560 kvm_x86_ops->prepare_guest_switch(vcpu);
3561 kvm_load_guest_fpu(vcpu);
3562
3563 local_irq_disable();
3564
32f88400
MT		 3565 clear_bit(KVM_REQ_KICK, &vcpu->requests);
3566 smp_mb__after_clear_bit();
3567
d7690175 3568 if (vcpu->requests || need_resched() || signal_pending(current)) {
c7f0f24b 3569 set_bit(KVM_REQ_KICK, &vcpu->requests);
6c142801
AK		 3570 local_irq_enable();
3571 preempt_enable();
3572 r = 1;
3573 goto out;
3574 }
3575
b59bb7bd 3576 inject_pending_event(vcpu, kvm_run);
b6c7a5dc 3577
6a8b1d13
GN		 3578 /* enable NMI/IRQ window open exits if needed */
3579 if (vcpu->arch.nmi_pending)
3580 kvm_x86_ops->enable_nmi_window(vcpu);
3581 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
3582 kvm_x86_ops->enable_irq_window(vcpu);
3583
95ba8273 3584 if (kvm_lapic_enabled(vcpu)) {
8db3baa2
GN		 3585 update_cr8_intercept(vcpu);
3586 kvm_lapic_sync_to_vapic(vcpu);
95ba8273 3587 }
b93463aa 3588
3200f405
MT		 3589 up_read(&vcpu->kvm->slots_lock);
3590
b6c7a5dc
HB		 3591 kvm_guest_enter();
3592
42dbaa5a
JK		 3593 get_debugreg(vcpu->arch.host_dr6, 6);
3594 get_debugreg(vcpu->arch.host_dr7, 7);
3595 if (unlikely(vcpu->arch.switch_db_regs)) {
3596 get_debugreg(vcpu->arch.host_db[0], 0);
3597 get_debugreg(vcpu->arch.host_db[1], 1);
3598 get_debugreg(vcpu->arch.host_db[2], 2);
3599 get_debugreg(vcpu->arch.host_db[3], 3);
3600
3601 set_debugreg(0, 7);
3602 set_debugreg(vcpu->arch.eff_db[0], 0);
3603 set_debugreg(vcpu->arch.eff_db[1], 1);
3604 set_debugreg(vcpu->arch.eff_db[2], 2);
3605 set_debugreg(vcpu->arch.eff_db[3], 3);
3606 }
b6c7a5dc 3607
229456fc 3608 trace_kvm_entry(vcpu->vcpu_id);
b6c7a5dc
HB		 3609 kvm_x86_ops->run(vcpu, kvm_run);
3610
42dbaa5a
JK		 3611 if (unlikely(vcpu->arch.switch_db_regs)) {
3612 set_debugreg(0, 7);
3613 set_debugreg(vcpu->arch.host_db[0], 0);
3614 set_debugreg(vcpu->arch.host_db[1], 1);
3615 set_debugreg(vcpu->arch.host_db[2], 2);
3616 set_debugreg(vcpu->arch.host_db[3], 3);
3617 }
3618 set_debugreg(vcpu->arch.host_dr6, 6);
3619 set_debugreg(vcpu->arch.host_dr7, 7);
3620
32f88400 3621 set_bit(KVM_REQ_KICK, &vcpu->requests);
b6c7a5dc
HB		 3622 local_irq_enable();
3623
3624 ++vcpu->stat.exits;
3625
3626 /*
3627 * We must have an instruction between local_irq_enable() and
3628 * kvm_guest_exit(), so the timer interrupt isn't delayed by
3629 * the interrupt shadow. The stat.exits increment will do nicely.
3630 * But we need to prevent reordering, hence this barrier():
3631 */
3632 barrier();
3633
3634 kvm_guest_exit();
3635
3636 preempt_enable();
3637
3200f405
MT		 3638 down_read(&vcpu->kvm->slots_lock);
3639
b6c7a5dc
HB		 3640 /*
3641 * Profile KVM exit RIPs:
3642 */
3643 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 3644 unsigned long rip = kvm_rip_read(vcpu);
3645 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 3646 }
3647
298101da 3648
b93463aa
AK		 3649 kvm_lapic_sync_from_vapic(vcpu);
3650
b6c7a5dc 3651 r = kvm_x86_ops->handle_exit(kvm_run, vcpu);
d7690175
MT		 3652out:
3653 return r;
3654}
b6c7a5dc 3655
09cec754 3656
d7690175
MT		 3657static int __vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3658{
3659 int r;
3660
3661 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 3662 pr_debug("vcpu %d received sipi with vector # %x\n",
3663 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 3664 kvm_lapic_reset(vcpu);
5f179287 3665 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 3666 if (r)
3667 return r;
3668 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 3669 }
3670
d7690175
MT		 3671 down_read(&vcpu->kvm->slots_lock);
3672 vapic_enter(vcpu);
3673
3674 r = 1;
3675 while (r > 0) {
af2152f5 3676 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
d7690175
MT		 3677 r = vcpu_enter_guest(vcpu, kvm_run);
3678 else {
3679 up_read(&vcpu->kvm->slots_lock);
3680 kvm_vcpu_block(vcpu);
3681 down_read(&vcpu->kvm->slots_lock);
3682 if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests))
09cec754
GN		 3683 {
3684 switch(vcpu->arch.mp_state) {
3685 case KVM_MP_STATE_HALTED:
d7690175 3686 vcpu->arch.mp_state =
09cec754
GN		 3687 KVM_MP_STATE_RUNNABLE;
3688 case KVM_MP_STATE_RUNNABLE:
3689 break;
3690 case KVM_MP_STATE_SIPI_RECEIVED:
3691 default:
3692 r = -EINTR;
3693 break;
3694 }
3695 }
d7690175
MT		 3696 }
3697
09cec754
GN		 3698 if (r <= 0)
3699 break;
3700
3701 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
3702 if (kvm_cpu_has_pending_timer(vcpu))
3703 kvm_inject_pending_timer_irqs(vcpu);
3704
3705 if (dm_request_for_irq_injection(vcpu, kvm_run)) {
3706 r = -EINTR;
3707 kvm_run->exit_reason = KVM_EXIT_INTR;
3708 ++vcpu->stat.request_irq_exits;
3709 }
3710 if (signal_pending(current)) {
3711 r = -EINTR;
3712 kvm_run->exit_reason = KVM_EXIT_INTR;
3713 ++vcpu->stat.signal_exits;
3714 }
3715 if (need_resched()) {
3716 up_read(&vcpu->kvm->slots_lock);
3717 kvm_resched(vcpu);
3718 down_read(&vcpu->kvm->slots_lock);
d7690175 3719 }
b6c7a5dc
HB		 3720 }
3721
d7690175 3722 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 3723 post_kvm_run_save(vcpu, kvm_run);
3724
b93463aa
AK		 3725 vapic_exit(vcpu);
3726
b6c7a5dc
HB		 3727 return r;
3728}
3729
3730int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3731{
3732 int r;
3733 sigset_t sigsaved;
3734
3735 vcpu_load(vcpu);
3736
ac9f6dc0
AK		 3737 if (vcpu->sigset_active)
3738 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
3739
a4535290 3740 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 3741 kvm_vcpu_block(vcpu);
d7690175 3742 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 3743 r = -EAGAIN;
3744 goto out;
b6c7a5dc
HB		 3745 }
3746
b6c7a5dc
HB		 3747 /* re-sync apic's tpr */
3748 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 3749 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 3750
ad312c7c 3751 if (vcpu->arch.pio.cur_count) {
b6c7a5dc
HB		 3752 r = complete_pio(vcpu);
3753 if (r)
3754 goto out;
3755 }
3756#if CONFIG_HAS_IOMEM
3757 if (vcpu->mmio_needed) {
3758 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
3759 vcpu->mmio_read_completed = 1;
3760 vcpu->mmio_needed = 0;
3200f405
MT		 3761
3762 down_read(&vcpu->kvm->slots_lock);
b6c7a5dc 3763 r = emulate_instruction(vcpu, kvm_run,
571008da
SY		 3764 vcpu->arch.mmio_fault_cr2, 0,
3765 EMULTYPE_NO_DECODE);
3200f405 3766 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 3767 if (r == EMULATE_DO_MMIO) {
3768 /*
3769 * Read-modify-write. Back to userspace.
3770 */
3771 r = 0;
3772 goto out;
3773 }
3774 }
3775#endif
5fdbf976
MT		 3776 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
3777 kvm_register_write(vcpu, VCPU_REGS_RAX,
3778 kvm_run->hypercall.ret);
b6c7a5dc
HB		 3779
3780 r = __vcpu_run(vcpu, kvm_run);
3781
3782out:
3783 if (vcpu->sigset_active)
3784 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
3785
3786 vcpu_put(vcpu);
3787 return r;
3788}
3789
3790int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3791{
3792 vcpu_load(vcpu);
3793
5fdbf976
MT		 3794 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
3795 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
3796 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
3797 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
3798 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
3799 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
3800 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
3801 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 3802#ifdef CONFIG_X86_64
5fdbf976
MT		 3803 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
3804 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
3805 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
3806 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
3807 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
3808 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
3809 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
3810 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 3811#endif
3812
5fdbf976 3813 regs->rip = kvm_rip_read(vcpu);
b6c7a5dc
HB		 3814 regs->rflags = kvm_x86_ops->get_rflags(vcpu);
3815
3816 /*
3817 * Don't leak debug flags in case they were set for guest debugging
3818 */
d0bfb940 3819 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
b6c7a5dc
HB		 3820 regs->rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
3821
3822 vcpu_put(vcpu);
3823
3824 return 0;
3825}
3826
3827int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3828{
3829 vcpu_load(vcpu);
3830
5fdbf976
MT		 3831 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
3832 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
3833 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
3834 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
3835 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
3836 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
3837 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
3838 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 3839#ifdef CONFIG_X86_64
5fdbf976
MT		 3840 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
3841 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
3842 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
3843 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
3844 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
3845 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
3846 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
3847 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
3848
b6c7a5dc
HB		 3849#endif
3850
5fdbf976 3851 kvm_rip_write(vcpu, regs->rip);
b6c7a5dc
HB		 3852 kvm_x86_ops->set_rflags(vcpu, regs->rflags);
3853
b6c7a5dc 3854
b4f14abd
JK		 3855 vcpu->arch.exception.pending = false;
3856
b6c7a5dc
HB		 3857 vcpu_put(vcpu);
3858
3859 return 0;
3860}
3861
3e6e0aab
GT		 3862void kvm_get_segment(struct kvm_vcpu *vcpu,
3863 struct kvm_segment *var, int seg)
b6c7a5dc 3864{
14af3f3c 3865 kvm_x86_ops->get_segment(vcpu, var, seg);
b6c7a5dc
HB		 3866}
3867
3868void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3869{
3870 struct kvm_segment cs;
3871
3e6e0aab 3872 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 3873 *db = cs.db;
3874 *l = cs.l;
3875}
3876EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
3877
3878int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
3879 struct kvm_sregs *sregs)
3880{
3881 struct descriptor_table dt;
b6c7a5dc
HB		 3882
3883 vcpu_load(vcpu);
3884
3e6e0aab
GT		 3885 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
3886 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
3887 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
3888 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
3889 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
3890 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 3891
3e6e0aab
GT		 3892 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
3893 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 3894
3895 kvm_x86_ops->get_idt(vcpu, &dt);
3896 sregs->idt.limit = dt.limit;
3897 sregs->idt.base = dt.base;
3898 kvm_x86_ops->get_gdt(vcpu, &dt);
3899 sregs->gdt.limit = dt.limit;
3900 sregs->gdt.base = dt.base;
3901
3902 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
ad312c7c
ZX		 3903 sregs->cr0 = vcpu->arch.cr0;
3904 sregs->cr2 = vcpu->arch.cr2;
3905 sregs->cr3 = vcpu->arch.cr3;
3906 sregs->cr4 = vcpu->arch.cr4;
2d3ad1f4 3907 sregs->cr8 = kvm_get_cr8(vcpu);
ad312c7c 3908 sregs->efer = vcpu->arch.shadow_efer;
b6c7a5dc
HB		 3909 sregs->apic_base = kvm_get_apic_base(vcpu);
3910
923c61bb 3911 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 3912
36752c9b 3913 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 3914 set_bit(vcpu->arch.interrupt.nr,
3915 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 3916
b6c7a5dc
HB		 3917 vcpu_put(vcpu);
3918
3919 return 0;
3920}
3921
62d9f0db
MT		 3922int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
3923 struct kvm_mp_state *mp_state)
3924{
3925 vcpu_load(vcpu);
3926 mp_state->mp_state = vcpu->arch.mp_state;
3927 vcpu_put(vcpu);
3928 return 0;
3929}
3930
3931int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
3932 struct kvm_mp_state *mp_state)
3933{
3934 vcpu_load(vcpu);
3935 vcpu->arch.mp_state = mp_state->mp_state;
3936 vcpu_put(vcpu);
3937 return 0;
3938}
3939
3e6e0aab 3940static void kvm_set_segment(struct kvm_vcpu *vcpu,
b6c7a5dc
HB		 3941 struct kvm_segment *var, int seg)
3942{
14af3f3c 3943 kvm_x86_ops->set_segment(vcpu, var, seg);
b6c7a5dc
HB		 3944}
3945
37817f29
IE		 3946static void seg_desct_to_kvm_desct(struct desc_struct *seg_desc, u16 selector,
3947 struct kvm_segment *kvm_desct)
3948{
46a359e7
AM		 3949 kvm_desct->base = get_desc_base(seg_desc);
3950 kvm_desct->limit = get_desc_limit(seg_desc);
c93cd3a5
MT		 3951 if (seg_desc->g) {
3952 kvm_desct->limit <<= 12;
3953 kvm_desct->limit |= 0xfff;
3954 }
37817f29
IE		 3955 kvm_desct->selector = selector;
3956 kvm_desct->type = seg_desc->type;
3957 kvm_desct->present = seg_desc->p;
3958 kvm_desct->dpl = seg_desc->dpl;
3959 kvm_desct->db = seg_desc->d;
3960 kvm_desct->s = seg_desc->s;
3961 kvm_desct->l = seg_desc->l;
3962 kvm_desct->g = seg_desc->g;
3963 kvm_desct->avl = seg_desc->avl;
3964 if (!selector)
3965 kvm_desct->unusable = 1;
3966 else
3967 kvm_desct->unusable = 0;
3968 kvm_desct->padding = 0;
3969}
3970
b8222ad2
AS		 3971static void get_segment_descriptor_dtable(struct kvm_vcpu *vcpu,
3972 u16 selector,
3973 struct descriptor_table *dtable)
37817f29
IE		 3974{
3975 if (selector & 1 << 2) {
3976 struct kvm_segment kvm_seg;
3977
3e6e0aab 3978 kvm_get_segment(vcpu, &kvm_seg, VCPU_SREG_LDTR);
37817f29
IE		 3979
3980 if (kvm_seg.unusable)
3981 dtable->limit = 0;
3982 else
3983 dtable->limit = kvm_seg.limit;
3984 dtable->base = kvm_seg.base;
3985 }
3986 else
3987 kvm_x86_ops->get_gdt(vcpu, dtable);
3988}
3989
3990/* allowed just for 8 bytes segments */
3991static int load_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3992 struct desc_struct *seg_desc)
3993{
98899aa0 3994 gpa_t gpa;
37817f29
IE		 3995 struct descriptor_table dtable;
3996 u16 index = selector >> 3;
3997
b8222ad2 3998 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 3999
4000 if (dtable.limit < index * 8 + 7) {
4001 kvm_queue_exception_e(vcpu, GP_VECTOR, selector & 0xfffc);
4002 return 1;
4003 }
98899aa0
MT		 4004 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
4005 gpa += index * 8;
4006 return kvm_read_guest(vcpu->kvm, gpa, seg_desc, 8);
37817f29
IE		 4007}
4008
4009/* allowed just for 8 bytes segments */
4010static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4011 struct desc_struct *seg_desc)
4012{
98899aa0 4013 gpa_t gpa;
37817f29
IE		 4014 struct descriptor_table dtable;
4015 u16 index = selector >> 3;
4016
b8222ad2 4017 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 4018
4019 if (dtable.limit < index * 8 + 7)
4020 return 1;
98899aa0
MT		 4021 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
4022 gpa += index * 8;
4023 return kvm_write_guest(vcpu->kvm, gpa, seg_desc, 8);
37817f29
IE		 4024}
4025
4026static u32 get_tss_base_addr(struct kvm_vcpu *vcpu,
4027 struct desc_struct *seg_desc)
4028{
46a359e7 4029 u32 base_addr = get_desc_base(seg_desc);
37817f29 4030
98899aa0 4031 return vcpu->arch.mmu.gva_to_gpa(vcpu, base_addr);
37817f29
IE		 4032}
4033
37817f29
IE		 4034static u16 get_segment_selector(struct kvm_vcpu *vcpu, int seg)
4035{
4036 struct kvm_segment kvm_seg;
4037
3e6e0aab 4038 kvm_get_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 4039 return kvm_seg.selector;
4040}
4041
4042static int load_segment_descriptor_to_kvm_desct(struct kvm_vcpu *vcpu,
4043 u16 selector,
4044 struct kvm_segment *kvm_seg)
4045{
4046 struct desc_struct seg_desc;
4047
4048 if (load_guest_segment_descriptor(vcpu, selector, &seg_desc))
4049 return 1;
4050 seg_desct_to_kvm_desct(&seg_desc, selector, kvm_seg);
4051 return 0;
4052}
4053
2259e3a7 4054static int kvm_load_realmode_segment(struct kvm_vcpu *vcpu, u16 selector, int seg)
f4bbd9aa
AK		 4055{
4056 struct kvm_segment segvar = {
4057 .base = selector << 4,
4058 .limit = 0xffff,
4059 .selector = selector,
4060 .type = 3,
4061 .present = 1,
4062 .dpl = 3,
4063 .db = 0,
4064 .s = 1,
4065 .l = 0,
4066 .g = 0,
4067 .avl = 0,
4068 .unusable = 0,
4069 };
4070 kvm_x86_ops->set_segment(vcpu, &segvar, seg);
4071 return 0;
4072}
4073
3e6e0aab
GT		 4074int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4075 int type_bits, int seg)
37817f29
IE		 4076{
4077 struct kvm_segment kvm_seg;
4078
f4bbd9aa
AK		 4079 if (!(vcpu->arch.cr0 & X86_CR0_PE))
4080 return kvm_load_realmode_segment(vcpu, selector, seg);
37817f29
IE		 4081 if (load_segment_descriptor_to_kvm_desct(vcpu, selector, &kvm_seg))
4082 return 1;
4083 kvm_seg.type |= type_bits;
4084
4085 if (seg != VCPU_SREG_SS && seg != VCPU_SREG_CS &&
4086 seg != VCPU_SREG_LDTR)
4087 if (!kvm_seg.s)
4088 kvm_seg.unusable = 1;
4089
3e6e0aab 4090 kvm_set_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 4091 return 0;
4092}
4093
4094static void save_state_to_tss32(struct kvm_vcpu *vcpu,
4095 struct tss_segment_32 *tss)
4096{
4097 tss->cr3 = vcpu->arch.cr3;
5fdbf976 4098 tss->eip = kvm_rip_read(vcpu);
37817f29 4099 tss->eflags = kvm_x86_ops->get_rflags(vcpu);
5fdbf976
MT		 4100 tss->eax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4101 tss->ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4102 tss->edx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4103 tss->ebx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4104 tss->esp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4105 tss->ebp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4106 tss->esi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4107 tss->edi = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 4108 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
4109 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
4110 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
4111 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
4112 tss->fs = get_segment_selector(vcpu, VCPU_SREG_FS);
4113 tss->gs = get_segment_selector(vcpu, VCPU_SREG_GS);
4114 tss->ldt_selector = get_segment_selector(vcpu, VCPU_SREG_LDTR);
37817f29
IE		 4115}
4116
4117static int load_state_from_tss32(struct kvm_vcpu *vcpu,
4118 struct tss_segment_32 *tss)
4119{
4120 kvm_set_cr3(vcpu, tss->cr3);
4121
5fdbf976 4122 kvm_rip_write(vcpu, tss->eip);
37817f29
IE		 4123 kvm_x86_ops->set_rflags(vcpu, tss->eflags | 2);
4124
5fdbf976
MT		 4125 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->eax);
4126 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->ecx);
4127 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->edx);
4128 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->ebx);
4129 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->esp);
4130 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->ebp);
4131 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->esi);
4132 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->edi);
37817f29 4133
3e6e0aab 4134 if (kvm_load_segment_descriptor(vcpu, tss->ldt_selector, 0, VCPU_SREG_LDTR))
37817f29
IE		 4135 return 1;
4136
3e6e0aab 4137 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 4138 return 1;
4139
3e6e0aab 4140 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 4141 return 1;
4142
3e6e0aab 4143 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 4144 return 1;
4145
3e6e0aab 4146 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 4147 return 1;
4148
3e6e0aab 4149 if (kvm_load_segment_descriptor(vcpu, tss->fs, 1, VCPU_SREG_FS))
37817f29
IE		 4150 return 1;
4151
3e6e0aab 4152 if (kvm_load_segment_descriptor(vcpu, tss->gs, 1, VCPU_SREG_GS))
37817f29
IE		 4153 return 1;
4154 return 0;
4155}
4156
4157static void save_state_to_tss16(struct kvm_vcpu *vcpu,
4158 struct tss_segment_16 *tss)
4159{
5fdbf976 4160 tss->ip = kvm_rip_read(vcpu);
37817f29 4161 tss->flag = kvm_x86_ops->get_rflags(vcpu);
5fdbf976
MT		 4162 tss->ax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4163 tss->cx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4164 tss->dx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4165 tss->bx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4166 tss->sp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4167 tss->bp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4168 tss->si = kvm_register_read(vcpu, VCPU_REGS_RSI);
4169 tss->di = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 4170
4171 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
4172 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
4173 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
4174 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
4175 tss->ldt = get_segment_selector(vcpu, VCPU_SREG_LDTR);
4176 tss->prev_task_link = get_segment_selector(vcpu, VCPU_SREG_TR);
4177}
4178
4179static int load_state_from_tss16(struct kvm_vcpu *vcpu,
4180 struct tss_segment_16 *tss)
4181{
5fdbf976 4182 kvm_rip_write(vcpu, tss->ip);
37817f29 4183 kvm_x86_ops->set_rflags(vcpu, tss->flag | 2);
5fdbf976
MT		 4184 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->ax);
4185 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->cx);
4186 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->dx);
4187 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->bx);
4188 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->sp);
4189 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->bp);
4190 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->si);
4191 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->di);
37817f29 4192
3e6e0aab 4193 if (kvm_load_segment_descriptor(vcpu, tss->ldt, 0, VCPU_SREG_LDTR))
37817f29
IE		 4194 return 1;
4195
3e6e0aab 4196 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 4197 return 1;
4198
3e6e0aab 4199 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 4200 return 1;
4201
3e6e0aab 4202 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 4203 return 1;
4204
3e6e0aab 4205 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 4206 return 1;
4207 return 0;
4208}
4209
8b2cf73c 4210static int kvm_task_switch_16(struct kvm_vcpu *vcpu, u16 tss_selector,
b237ac37
GN		 4211 u16 old_tss_sel, u32 old_tss_base,
4212 struct desc_struct *nseg_desc)
37817f29
IE		 4213{
4214 struct tss_segment_16 tss_segment_16;
4215 int ret = 0;
4216
34198bf8
MT		 4217 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
4218 sizeof tss_segment_16))
37817f29
IE		 4219 goto out;
4220
4221 save_state_to_tss16(vcpu, &tss_segment_16);
37817f29 4222
34198bf8
MT		 4223 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
4224 sizeof tss_segment_16))
37817f29 4225 goto out;
34198bf8
MT		 4226
4227 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
4228 &tss_segment_16, sizeof tss_segment_16))
4229 goto out;
4230
b237ac37
GN		 4231 if (old_tss_sel != 0xffff) {
4232 tss_segment_16.prev_task_link = old_tss_sel;
4233
4234 if (kvm_write_guest(vcpu->kvm,
4235 get_tss_base_addr(vcpu, nseg_desc),
4236 &tss_segment_16.prev_task_link,
4237 sizeof tss_segment_16.prev_task_link))
4238 goto out;
4239 }
4240
37817f29
IE		 4241 if (load_state_from_tss16(vcpu, &tss_segment_16))
4242 goto out;
4243
4244 ret = 1;
4245out:
4246 return ret;
4247}
4248
8b2cf73c 4249static int kvm_task_switch_32(struct kvm_vcpu *vcpu, u16 tss_selector,
b237ac37 4250 u16 old_tss_sel, u32 old_tss_base,
37817f29
IE		 4251 struct desc_struct *nseg_desc)
4252{
4253 struct tss_segment_32 tss_segment_32;
4254 int ret = 0;
4255
34198bf8
MT		 4256 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
4257 sizeof tss_segment_32))
37817f29
IE		 4258 goto out;
4259
4260 save_state_to_tss32(vcpu, &tss_segment_32);
37817f29 4261
34198bf8
MT		 4262 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
4263 sizeof tss_segment_32))
4264 goto out;
4265
4266 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
4267 &tss_segment_32, sizeof tss_segment_32))
37817f29 4268 goto out;
34198bf8 4269
b237ac37
GN		 4270 if (old_tss_sel != 0xffff) {
4271 tss_segment_32.prev_task_link = old_tss_sel;
4272
4273 if (kvm_write_guest(vcpu->kvm,
4274 get_tss_base_addr(vcpu, nseg_desc),
4275 &tss_segment_32.prev_task_link,
4276 sizeof tss_segment_32.prev_task_link))
4277 goto out;
4278 }
4279
37817f29
IE		 4280 if (load_state_from_tss32(vcpu, &tss_segment_32))
4281 goto out;
4282
4283 ret = 1;
4284out:
4285 return ret;
4286}
4287
4288int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason)
4289{
4290 struct kvm_segment tr_seg;
4291 struct desc_struct cseg_desc;
4292 struct desc_struct nseg_desc;
4293 int ret = 0;
34198bf8
MT		 4294 u32 old_tss_base = get_segment_base(vcpu, VCPU_SREG_TR);
4295 u16 old_tss_sel = get_segment_selector(vcpu, VCPU_SREG_TR);
37817f29 4296
34198bf8 4297 old_tss_base = vcpu->arch.mmu.gva_to_gpa(vcpu, old_tss_base);
37817f29 4298
34198bf8
MT		 4299 /* FIXME: Handle errors. Failure to read either TSS or their
4300 * descriptors should generate a pagefault.
4301 */
37817f29
IE		 4302 if (load_guest_segment_descriptor(vcpu, tss_selector, &nseg_desc))
4303 goto out;
4304
34198bf8 4305 if (load_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc))
37817f29
IE		 4306 goto out;
4307
37817f29
IE		 4308 if (reason != TASK_SWITCH_IRET) {
4309 int cpl;
4310
4311 cpl = kvm_x86_ops->get_cpl(vcpu);
4312 if ((tss_selector & 3) > nseg_desc.dpl || cpl > nseg_desc.dpl) {
4313 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
4314 return 1;
4315 }
4316 }
4317
46a359e7 4318 if (!nseg_desc.p || get_desc_limit(&nseg_desc) < 0x67) {
37817f29
IE		 4319 kvm_queue_exception_e(vcpu, TS_VECTOR, tss_selector & 0xfffc);
4320 return 1;
4321 }
4322
4323 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
3fe913e7 4324 cseg_desc.type &= ~(1 << 1); //clear the B flag
34198bf8 4325 save_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc);
37817f29
IE		 4326 }
4327
4328 if (reason == TASK_SWITCH_IRET) {
4329 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
4330 kvm_x86_ops->set_rflags(vcpu, eflags & ~X86_EFLAGS_NT);
4331 }
4332
64a7ec06
GN		 4333 /* set back link to prev task only if NT bit is set in eflags
4334 note that old_tss_sel is not used afetr this point */
4335 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
4336 old_tss_sel = 0xffff;
37817f29 4337
b237ac37
GN		 4338 /* set back link to prev task only if NT bit is set in eflags
4339 note that old_tss_sel is not used afetr this point */
4340 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
4341 old_tss_sel = 0xffff;
4342
37817f29 4343 if (nseg_desc.type & 8)
b237ac37
GN		 4344 ret = kvm_task_switch_32(vcpu, tss_selector, old_tss_sel,
4345 old_tss_base, &nseg_desc);
37817f29 4346 else
b237ac37
GN		 4347 ret = kvm_task_switch_16(vcpu, tss_selector, old_tss_sel,
4348 old_tss_base, &nseg_desc);
37817f29
IE		 4349
4350 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) {
4351 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
4352 kvm_x86_ops->set_rflags(vcpu, eflags | X86_EFLAGS_NT);
4353 }
4354
4355 if (reason != TASK_SWITCH_IRET) {
3fe913e7 4356 nseg_desc.type |= (1 << 1);
37817f29
IE		 4357 save_guest_segment_descriptor(vcpu, tss_selector,
4358 &nseg_desc);
4359 }
4360
4361 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 | X86_CR0_TS);
4362 seg_desct_to_kvm_desct(&nseg_desc, tss_selector, &tr_seg);
4363 tr_seg.type = 11;
3e6e0aab 4364 kvm_set_segment(vcpu, &tr_seg, VCPU_SREG_TR);
37817f29 4365out:
37817f29
IE		 4366 return ret;
4367}
4368EXPORT_SYMBOL_GPL(kvm_task_switch);
4369
b6c7a5dc
HB		 4370int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
4371 struct kvm_sregs *sregs)
4372{
4373 int mmu_reset_needed = 0;
923c61bb 4374 int pending_vec, max_bits;
b6c7a5dc
HB		 4375 struct descriptor_table dt;
4376
4377 vcpu_load(vcpu);
4378
4379 dt.limit = sregs->idt.limit;
4380 dt.base = sregs->idt.base;
4381 kvm_x86_ops->set_idt(vcpu, &dt);
4382 dt.limit = sregs->gdt.limit;
4383 dt.base = sregs->gdt.base;
4384 kvm_x86_ops->set_gdt(vcpu, &dt);
4385
ad312c7c
ZX		 4386 vcpu->arch.cr2 = sregs->cr2;
4387 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
dc7e795e 4388 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 4389
2d3ad1f4 4390 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 4391
ad312c7c 4392 mmu_reset_needed |= vcpu->arch.shadow_efer != sregs->efer;
b6c7a5dc 4393 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 4394 kvm_set_apic_base(vcpu, sregs->apic_base);
4395
4396 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
4397
ad312c7c 4398 mmu_reset_needed |= vcpu->arch.cr0 != sregs->cr0;
b6c7a5dc 4399 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 4400 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 4401
ad312c7c 4402 mmu_reset_needed |= vcpu->arch.cr4 != sregs->cr4;
b6c7a5dc
HB		 4403 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
4404 if (!is_long_mode(vcpu) && is_pae(vcpu))
ad312c7c 4405 load_pdptrs(vcpu, vcpu->arch.cr3);
b6c7a5dc
HB		 4406
4407 if (mmu_reset_needed)
4408 kvm_mmu_reset_context(vcpu);
4409
923c61bb
GN		 4410 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
4411 pending_vec = find_first_bit(
4412 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
4413 if (pending_vec < max_bits) {
66fd3f7f 4414 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 4415 pr_debug("Set back pending irq %d\n", pending_vec);
4416 if (irqchip_in_kernel(vcpu->kvm))
4417 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 4418 }
4419
3e6e0aab
GT		 4420 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
4421 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
4422 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
4423 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
4424 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
4425 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 4426
3e6e0aab
GT		 4427 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
4428 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 4429
9c3e4aab 4430 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 4431 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab
MT		 4432 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
4433 !(vcpu->arch.cr0 & X86_CR0_PE))
4434 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4435
b6c7a5dc
HB		 4436 vcpu_put(vcpu);
4437
4438 return 0;
4439}
4440
d0bfb940
JK		 4441int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
4442 struct kvm_guest_debug *dbg)
b6c7a5dc 4443{
ae675ef0 4444 int i, r;
b6c7a5dc
HB		 4445
4446 vcpu_load(vcpu);
4447
ae675ef0
JK		 4448 if ((dbg->control & (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP)) ==
4449 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP)) {
4450 for (i = 0; i < KVM_NR_DB_REGS; ++i)
4451 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
4452 vcpu->arch.switch_db_regs =
4453 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
4454 } else {
4455 for (i = 0; i < KVM_NR_DB_REGS; i++)
4456 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
4457 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
4458 }
4459
b6c7a5dc
HB		 4460 r = kvm_x86_ops->set_guest_debug(vcpu, dbg);
4461
d0bfb940
JK		 4462 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
4463 kvm_queue_exception(vcpu, DB_VECTOR);
4464 else if (dbg->control & KVM_GUESTDBG_INJECT_BP)
4465 kvm_queue_exception(vcpu, BP_VECTOR);
4466
b6c7a5dc
HB		 4467 vcpu_put(vcpu);
4468
4469 return r;
4470}
4471
d0752060
HB		 4472/*
4473 * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
4474 * we have asm/x86/processor.h
4475 */
4476struct fxsave {
4477 u16 cwd;
4478 u16 swd;
4479 u16 twd;
4480 u16 fop;
4481 u64 rip;
4482 u64 rdp;
4483 u32 mxcsr;
4484 u32 mxcsr_mask;
4485 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
4486#ifdef CONFIG_X86_64
4487 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
4488#else
4489 u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
4490#endif
4491};
4492
8b006791
ZX		 4493/*
4494 * Translate a guest virtual address to a guest physical address.
4495 */
4496int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
4497 struct kvm_translation *tr)
4498{
4499 unsigned long vaddr = tr->linear_address;
4500 gpa_t gpa;
4501
4502 vcpu_load(vcpu);
72dc67a6 4503 down_read(&vcpu->kvm->slots_lock);
ad312c7c 4504 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, vaddr);
72dc67a6 4505 up_read(&vcpu->kvm->slots_lock);
8b006791
ZX		 4506 tr->physical_address = gpa;
4507 tr->valid = gpa != UNMAPPED_GVA;
4508 tr->writeable = 1;
4509 tr->usermode = 0;
8b006791
ZX		 4510 vcpu_put(vcpu);
4511
4512 return 0;
4513}
4514
d0752060
HB		 4515int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
4516{
ad312c7c 4517 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 4518
4519 vcpu_load(vcpu);
4520
4521 memcpy(fpu->fpr, fxsave->st_space, 128);
4522 fpu->fcw = fxsave->cwd;
4523 fpu->fsw = fxsave->swd;
4524 fpu->ftwx = fxsave->twd;
4525 fpu->last_opcode = fxsave->fop;
4526 fpu->last_ip = fxsave->rip;
4527 fpu->last_dp = fxsave->rdp;
4528 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
4529
4530 vcpu_put(vcpu);
4531
4532 return 0;
4533}
4534
4535int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
4536{
ad312c7c 4537 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 4538
4539 vcpu_load(vcpu);
4540
4541 memcpy(fxsave->st_space, fpu->fpr, 128);
4542 fxsave->cwd = fpu->fcw;
4543 fxsave->swd = fpu->fsw;
4544 fxsave->twd = fpu->ftwx;
4545 fxsave->fop = fpu->last_opcode;
4546 fxsave->rip = fpu->last_ip;
4547 fxsave->rdp = fpu->last_dp;
4548 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
4549
4550 vcpu_put(vcpu);
4551
4552 return 0;
4553}
4554
4555void fx_init(struct kvm_vcpu *vcpu)
4556{
4557 unsigned after_mxcsr_mask;
4558
bc1a34f1
AA		 4559 /*
4560 * Touch the fpu the first time in non atomic context as if
4561 * this is the first fpu instruction the exception handler
4562 * will fire before the instruction returns and it'll have to
4563 * allocate ram with GFP_KERNEL.
4564 */
4565 if (!used_math())
d6e88aec 4566 kvm_fx_save(&vcpu->arch.host_fx_image);
bc1a34f1 4567
d0752060
HB		 4568 /* Initialize guest FPU by resetting ours and saving into guest's */
4569 preempt_disable();
d6e88aec
AK		 4570 kvm_fx_save(&vcpu->arch.host_fx_image);
4571 kvm_fx_finit();
4572 kvm_fx_save(&vcpu->arch.guest_fx_image);
4573 kvm_fx_restore(&vcpu->arch.host_fx_image);
d0752060
HB		 4574 preempt_enable();
4575
ad312c7c 4576 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 4577 after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
ad312c7c
ZX		 4578 vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
4579 memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
d0752060
HB		 4580 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
4581}
4582EXPORT_SYMBOL_GPL(fx_init);
4583
4584void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
4585{
4586 if (!vcpu->fpu_active || vcpu->guest_fpu_loaded)
4587 return;
4588
4589 vcpu->guest_fpu_loaded = 1;
d6e88aec
AK		 4590 kvm_fx_save(&vcpu->arch.host_fx_image);
4591 kvm_fx_restore(&vcpu->arch.guest_fx_image);
d0752060
HB		 4592}
4593EXPORT_SYMBOL_GPL(kvm_load_guest_fpu);
4594
4595void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
4596{
4597 if (!vcpu->guest_fpu_loaded)
4598 return;
4599
4600 vcpu->guest_fpu_loaded = 0;
d6e88aec
AK		 4601 kvm_fx_save(&vcpu->arch.guest_fx_image);
4602 kvm_fx_restore(&vcpu->arch.host_fx_image);
f096ed85 4603 ++vcpu->stat.fpu_reload;
d0752060
HB		 4604}
4605EXPORT_SYMBOL_GPL(kvm_put_guest_fpu);
e9b11c17
ZX		 4606
4607void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
4608{
7f1ea208
JR		 4609 if (vcpu->arch.time_page) {
4610 kvm_release_page_dirty(vcpu->arch.time_page);
4611 vcpu->arch.time_page = NULL;
4612 }
4613
e9b11c17
ZX		 4614 kvm_x86_ops->vcpu_free(vcpu);
4615}
4616
4617struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
4618 unsigned int id)
4619{
26e5215f
AK		 4620 return kvm_x86_ops->vcpu_create(kvm, id);
4621}
e9b11c17 4622
26e5215f
AK		 4623int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
4624{
4625 int r;
e9b11c17
ZX		 4626
4627 /* We do fxsave: this must be aligned. */
ad312c7c 4628 BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
e9b11c17 4629
0bed3b56 4630 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 4631 vcpu_load(vcpu);
4632 r = kvm_arch_vcpu_reset(vcpu);
4633 if (r == 0)
4634 r = kvm_mmu_setup(vcpu);
4635 vcpu_put(vcpu);
4636 if (r < 0)
4637 goto free_vcpu;
4638
26e5215f 4639 return 0;
e9b11c17
ZX		 4640free_vcpu:
4641 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 4642 return r;
e9b11c17
ZX		 4643}
4644
d40ccc62 4645void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 4646{
4647 vcpu_load(vcpu);
4648 kvm_mmu_unload(vcpu);
4649 vcpu_put(vcpu);
4650
4651 kvm_x86_ops->vcpu_free(vcpu);
4652}
4653
4654int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
4655{
448fa4a9
JK		 4656 vcpu->arch.nmi_pending = false;
4657 vcpu->arch.nmi_injected = false;
4658
42dbaa5a
JK		 4659 vcpu->arch.switch_db_regs = 0;
4660 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
4661 vcpu->arch.dr6 = DR6_FIXED_1;
4662 vcpu->arch.dr7 = DR7_FIXED_1;
4663
e9b11c17
ZX		 4664 return kvm_x86_ops->vcpu_reset(vcpu);
4665}
4666
4667void kvm_arch_hardware_enable(void *garbage)
4668{
4669 kvm_x86_ops->hardware_enable(garbage);
4670}
4671
4672void kvm_arch_hardware_disable(void *garbage)
4673{
4674 kvm_x86_ops->hardware_disable(garbage);
4675}
4676
4677int kvm_arch_hardware_setup(void)
4678{
4679 return kvm_x86_ops->hardware_setup();
4680}
4681
4682void kvm_arch_hardware_unsetup(void)
4683{
4684 kvm_x86_ops->hardware_unsetup();
4685}
4686
4687void kvm_arch_check_processor_compat(void *rtn)
4688{
4689 kvm_x86_ops->check_processor_compatibility(rtn);
4690}
4691
4692int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
4693{
4694 struct page *page;
4695 struct kvm *kvm;
4696 int r;
4697
4698 BUG_ON(vcpu->kvm == NULL);
4699 kvm = vcpu->kvm;
4700
ad312c7c 4701 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c5af89b6 4702 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 4703 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 4704 else
a4535290 4705 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 4706
4707 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
4708 if (!page) {
4709 r = -ENOMEM;
4710 goto fail;
4711 }
ad312c7c 4712 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 4713
4714 r = kvm_mmu_create(vcpu);
4715 if (r < 0)
4716 goto fail_free_pio_data;
4717
4718 if (irqchip_in_kernel(kvm)) {
4719 r = kvm_create_lapic(vcpu);
4720 if (r < 0)
4721 goto fail_mmu_destroy;
4722 }
4723
890ca9ae
HY		 4724 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
4725 GFP_KERNEL);
4726 if (!vcpu->arch.mce_banks) {
4727 r = -ENOMEM;
4728 goto fail_mmu_destroy;
4729 }
4730 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
4731
e9b11c17
ZX		 4732 return 0;
4733
4734fail_mmu_destroy:
4735 kvm_mmu_destroy(vcpu);
4736fail_free_pio_data:
ad312c7c 4737 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 4738fail:
4739 return r;
4740}
4741
4742void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
4743{
4744 kvm_free_lapic(vcpu);
3200f405 4745 down_read(&vcpu->kvm->slots_lock);
e9b11c17 4746 kvm_mmu_destroy(vcpu);
3200f405 4747 up_read(&vcpu->kvm->slots_lock);
ad312c7c 4748 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 4749}
d19a9cd2
ZX		 4750
4751struct kvm *kvm_arch_create_vm(void)
4752{
4753 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
4754
4755 if (!kvm)
4756 return ERR_PTR(-ENOMEM);
4757
f05e70ac 4758 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 4759 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 4760
5550af4d
SY		 4761 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
4762 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
4763
53f658b3
MT		 4764 rdtscll(kvm->arch.vm_init_tsc);
4765
d19a9cd2
ZX		 4766 return kvm;
4767}
4768
4769static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
4770{
4771 vcpu_load(vcpu);
4772 kvm_mmu_unload(vcpu);
4773 vcpu_put(vcpu);
4774}
4775
4776static void kvm_free_vcpus(struct kvm *kvm)
4777{
4778 unsigned int i;
988a2cae 4779 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 4780
4781 /*
4782 * Unpin any mmu pages first.
4783 */
988a2cae
GN		 4784 kvm_for_each_vcpu(i, vcpu, kvm)
4785 kvm_unload_vcpu_mmu(vcpu);
4786 kvm_for_each_vcpu(i, vcpu, kvm)
4787 kvm_arch_vcpu_free(vcpu);
4788
4789 mutex_lock(&kvm->lock);
4790 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
4791 kvm->vcpus[i] = NULL;
d19a9cd2 4792
988a2cae
GN		 4793 atomic_set(&kvm->online_vcpus, 0);
4794 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 4795}
4796
ad8ba2cd
SY		 4797void kvm_arch_sync_events(struct kvm *kvm)
4798{
ba4cef31 4799 kvm_free_all_assigned_devices(kvm);
ad8ba2cd
SY		 4800}
4801
d19a9cd2
ZX		 4802void kvm_arch_destroy_vm(struct kvm *kvm)
4803{
6eb55818 4804 kvm_iommu_unmap_guest(kvm);
7837699f 4805 kvm_free_pit(kvm);
d7deeeb0
ZX		 4806 kfree(kvm->arch.vpic);
4807 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 4808 kvm_free_vcpus(kvm);
4809 kvm_free_physmem(kvm);
3d45830c
AK		 4810 if (kvm->arch.apic_access_page)
4811 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 4812 if (kvm->arch.ept_identity_pagetable)
4813 put_page(kvm->arch.ept_identity_pagetable);
d19a9cd2
ZX		 4814 kfree(kvm);
4815}
0de10343
ZX		 4816
4817int kvm_arch_set_memory_region(struct kvm *kvm,
4818 struct kvm_userspace_memory_region *mem,
4819 struct kvm_memory_slot old,
4820 int user_alloc)
4821{
4822 int npages = mem->memory_size >> PAGE_SHIFT;
4823 struct kvm_memory_slot *memslot = &kvm->memslots[mem->slot];
4824
4825 /*To keep backward compatibility with older userspace,
4826 *x86 needs to hanlde !user_alloc case.
4827 */
4828 if (!user_alloc) {
4829 if (npages && !old.rmap) {
604b38ac
AA		 4830 unsigned long userspace_addr;
4831
72dc67a6 4832 down_write(&current->mm->mmap_sem);
604b38ac
AA		 4833 userspace_addr = do_mmap(NULL, 0,
4834 npages * PAGE_SIZE,
4835 PROT_READ | PROT_WRITE,
acee3c04 4836 MAP_PRIVATE | MAP_ANONYMOUS,
604b38ac 4837 0);
72dc67a6 4838 up_write(&current->mm->mmap_sem);
0de10343 4839
604b38ac
AA		 4840 if (IS_ERR((void *)userspace_addr))
4841 return PTR_ERR((void *)userspace_addr);
4842
4843 /* set userspace_addr atomically for kvm_hva_to_rmapp */
4844 spin_lock(&kvm->mmu_lock);
4845 memslot->userspace_addr = userspace_addr;
4846 spin_unlock(&kvm->mmu_lock);
0de10343
ZX		 4847 } else {
4848 if (!old.user_alloc && old.rmap) {
4849 int ret;
4850
72dc67a6 4851 down_write(&current->mm->mmap_sem);
0de10343
ZX		 4852 ret = do_munmap(current->mm, old.userspace_addr,
4853 old.npages * PAGE_SIZE);
72dc67a6 4854 up_write(&current->mm->mmap_sem);
0de10343
ZX		 4855 if (ret < 0)
4856 printk(KERN_WARNING
4857 "kvm_vm_ioctl_set_memory_region: "
4858 "failed to munmap memory\n");
4859 }
4860 }
4861 }
4862
7c8a83b7 4863 spin_lock(&kvm->mmu_lock);
f05e70ac 4864 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 4865 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
4866 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
4867 }
4868
4869 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 4870 spin_unlock(&kvm->mmu_lock);
0de10343
ZX		 4871 kvm_flush_remote_tlbs(kvm);
4872
4873 return 0;
4874}
1d737c8a 4875
34d4cb8f
MT		 4876void kvm_arch_flush_shadow(struct kvm *kvm)
4877{
4878 kvm_mmu_zap_all(kvm);
8986ecc0 4879 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 4880}
4881
1d737c8a
ZX		 4882int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
4883{
a4535290 4884 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
a1b37100
GN		 4885 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
4886 || vcpu->arch.nmi_pending ||
4887 (kvm_arch_interrupt_allowed(vcpu) &&
4888 kvm_cpu_has_interrupt(vcpu));
1d737c8a 4889}
5736199a 4890
5736199a
ZX		 4891void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
4892{
32f88400
MT		 4893 int me;
4894 int cpu = vcpu->cpu;
5736199a
ZX		 4895
4896 if (waitqueue_active(&vcpu->wq)) {
4897 wake_up_interruptible(&vcpu->wq);
4898 ++vcpu->stat.halt_wakeup;
4899 }
32f88400
MT		 4900
4901 me = get_cpu();
4902 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
4903 if (!test_and_set_bit(KVM_REQ_KICK, &vcpu->requests))
4904 smp_send_reschedule(cpu);
e9571ed5 4905 put_cpu();
5736199a 4906}
78646121
GN		 4907
4908int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
4909{
4910 return kvm_x86_ops->interrupt_allowed(vcpu);
4911}
229456fc
MT		 4912
4913EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
4914EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
4915EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
4916EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
4917EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
Linux kernel - Deliverables
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