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KVM: Fix user memslot overlap check
[deliverable/linux.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
313a3dc7 30
18068523 31#include <linux/clocksource.h>
4d5c5d0f 32#include <linux/interrupt.h>
313a3dc7
CO		 33#include <linux/kvm.h>
34#include <linux/fs.h>
35#include <linux/vmalloc.h>
5fb76f9b 36#include <linux/module.h>
0de10343 37#include <linux/mman.h>
2bacc55c 38#include <linux/highmem.h>
19de40a8 39#include <linux/iommu.h>
62c476c7 40#include <linux/intel-iommu.h>
c8076604 41#include <linux/cpufreq.h>
18863bdd 42#include <linux/user-return-notifier.h>
a983fb23 43#include <linux/srcu.h>
5a0e3ad6 44#include <linux/slab.h>
ff9d07a0 45#include <linux/perf_event.h>
7bee342a 46#include <linux/uaccess.h>
af585b92 47#include <linux/hash.h>
a1b60c1c 48#include <linux/pci.h>
16e8d74d
MT		 49#include <linux/timekeeper_internal.h>
50#include <linux/pvclock_gtod.h>
aec51dc4 51#include <trace/events/kvm.h>
2ed152af 52
229456fc
MT		 53#define CREATE_TRACE_POINTS
54#include "trace.h"
043405e1 55
24f1e32c 56#include <asm/debugreg.h>
d825ed0a 57#include <asm/msr.h>
a5f61300 58#include <asm/desc.h>
0bed3b56 59#include <asm/mtrr.h>
890ca9ae 60#include <asm/mce.h>
7cf30855 61#include <asm/i387.h>
1361b83a 62#include <asm/fpu-internal.h> /* Ugh! */
98918833 63#include <asm/xcr.h>
1d5f066e 64#include <asm/pvclock.h>
217fc9cf 65#include <asm/div64.h>
043405e1 66
313a3dc7 67#define MAX_IO_MSRS 256
890ca9ae 68#define KVM_MAX_MCE_BANKS 32
5854dbca 69#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 70
0f65dd70
AK		 71#define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
73
50a37eb4
JR		 74/* EFER defaults:
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
77 */
78#ifdef CONFIG_X86_64
1260edbe
LJ		 79static
80u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 81#else
1260edbe 82static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 83#endif
313a3dc7 84
ba1389b7
AK		 85#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 87
cb142eb7 88static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 89static void process_nmi(struct kvm_vcpu *vcpu);
674eea0f 90
97896d04 91struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 92EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 93
476bc001
RR		 94static bool ignore_msrs = 0;
95module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 96
92a1f12d
JR		 97bool kvm_has_tsc_control;
98EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
99u32 kvm_max_guest_tsc_khz;
100EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
101
cc578287
ZA		 102/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
103static u32 tsc_tolerance_ppm = 250;
104module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
105
18863bdd
AK		 106#define KVM_NR_SHARED_MSRS 16
107
108struct kvm_shared_msrs_global {
109 int nr;
2bf78fa7 110 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 111};
112
113struct kvm_shared_msrs {
114 struct user_return_notifier urn;
115 bool registered;
2bf78fa7
SY		 116 struct kvm_shared_msr_values {
117 u64 host;
118 u64 curr;
119 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 120};
121
122static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
123static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
124
417bc304 125struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 126 { "pf_fixed", VCPU_STAT(pf_fixed) },
127 { "pf_guest", VCPU_STAT(pf_guest) },
128 { "tlb_flush", VCPU_STAT(tlb_flush) },
129 { "invlpg", VCPU_STAT(invlpg) },
130 { "exits", VCPU_STAT(exits) },
131 { "io_exits", VCPU_STAT(io_exits) },
132 { "mmio_exits", VCPU_STAT(mmio_exits) },
133 { "signal_exits", VCPU_STAT(signal_exits) },
134 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 135 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 136 { "halt_exits", VCPU_STAT(halt_exits) },
137 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 138 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 139 { "request_irq", VCPU_STAT(request_irq_exits) },
140 { "irq_exits", VCPU_STAT(irq_exits) },
141 { "host_state_reload", VCPU_STAT(host_state_reload) },
142 { "efer_reload", VCPU_STAT(efer_reload) },
143 { "fpu_reload", VCPU_STAT(fpu_reload) },
144 { "insn_emulation", VCPU_STAT(insn_emulation) },
145 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 146 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 147 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 148 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
149 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
150 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
151 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
152 { "mmu_flooded", VM_STAT(mmu_flooded) },
153 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 154 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 155 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 156 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 157 { "largepages", VM_STAT(lpages) },
417bc304
HB		 158 { NULL }
159};
160
2acf923e
DC		 161u64 __read_mostly host_xcr0;
162
b6785def 163static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 164
8b6e4547
JK		 165static int kvm_vcpu_reset(struct kvm_vcpu *vcpu);
166
af585b92
GN		 167static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
168{
169 int i;
170 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
171 vcpu->arch.apf.gfns[i] = ~0;
172}
173
18863bdd
AK		 174static void kvm_on_user_return(struct user_return_notifier *urn)
175{
176 unsigned slot;
18863bdd
AK		 177 struct kvm_shared_msrs *locals
178 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 179 struct kvm_shared_msr_values *values;
18863bdd
AK		 180
181 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 182 values = &locals->values[slot];
183 if (values->host != values->curr) {
184 wrmsrl(shared_msrs_global.msrs[slot], values->host);
185 values->curr = values->host;
18863bdd
AK		 186 }
187 }
188 locals->registered = false;
189 user_return_notifier_unregister(urn);
190}
191
2bf78fa7 192static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 193{
2bf78fa7 194 struct kvm_shared_msrs *smsr;
18863bdd
AK		 195 u64 value;
196
2bf78fa7
SY		 197 smsr = &__get_cpu_var(shared_msrs);
198 /* only read, and nobody should modify it at this time,
199 * so don't need lock */
200 if (slot >= shared_msrs_global.nr) {
201 printk(KERN_ERR "kvm: invalid MSR slot!");
202 return;
203 }
204 rdmsrl_safe(msr, &value);
205 smsr->values[slot].host = value;
206 smsr->values[slot].curr = value;
207}
208
209void kvm_define_shared_msr(unsigned slot, u32 msr)
210{
18863bdd
AK		 211 if (slot >= shared_msrs_global.nr)
212 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 213 shared_msrs_global.msrs[slot] = msr;
214 /* we need ensured the shared_msr_global have been updated */
215 smp_wmb();
18863bdd
AK		 216}
217EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
218
219static void kvm_shared_msr_cpu_online(void)
220{
221 unsigned i;
18863bdd
AK		 222
223 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 224 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 225}
226
d5696725 227void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 228{
229 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
230
2bf78fa7 231 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 232 return;
2bf78fa7
SY		 233 smsr->values[slot].curr = value;
234 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 235 if (!smsr->registered) {
236 smsr->urn.on_user_return = kvm_on_user_return;
237 user_return_notifier_register(&smsr->urn);
238 smsr->registered = true;
239 }
240}
241EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
242
3548bab5
AK		 243static void drop_user_return_notifiers(void *ignore)
244{
245 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
246
247 if (smsr->registered)
248 kvm_on_user_return(&smsr->urn);
249}
250
6866b83e
CO		 251u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
252{
8a5a87d9 253 return vcpu->arch.apic_base;
6866b83e
CO		 254}
255EXPORT_SYMBOL_GPL(kvm_get_apic_base);
256
257void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
258{
259 /* TODO: reserve bits check */
8a5a87d9 260 kvm_lapic_set_base(vcpu, data);
6866b83e
CO		 261}
262EXPORT_SYMBOL_GPL(kvm_set_apic_base);
263
3fd28fce
ED		 264#define EXCPT_BENIGN 0
265#define EXCPT_CONTRIBUTORY 1
266#define EXCPT_PF 2
267
268static int exception_class(int vector)
269{
270 switch (vector) {
271 case PF_VECTOR:
272 return EXCPT_PF;
273 case DE_VECTOR:
274 case TS_VECTOR:
275 case NP_VECTOR:
276 case SS_VECTOR:
277 case GP_VECTOR:
278 return EXCPT_CONTRIBUTORY;
279 default:
280 break;
281 }
282 return EXCPT_BENIGN;
283}
284
285static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 286 unsigned nr, bool has_error, u32 error_code,
287 bool reinject)
3fd28fce
ED		 288{
289 u32 prev_nr;
290 int class1, class2;
291
3842d135
AK		 292 kvm_make_request(KVM_REQ_EVENT, vcpu);
293
3fd28fce
ED		 294 if (!vcpu->arch.exception.pending) {
295 queue:
296 vcpu->arch.exception.pending = true;
297 vcpu->arch.exception.has_error_code = has_error;
298 vcpu->arch.exception.nr = nr;
299 vcpu->arch.exception.error_code = error_code;
3f0fd292 300 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 301 return;
302 }
303
304 /* to check exception */
305 prev_nr = vcpu->arch.exception.nr;
306 if (prev_nr == DF_VECTOR) {
307 /* triple fault -> shutdown */
a8eeb04a 308 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 309 return;
310 }
311 class1 = exception_class(prev_nr);
312 class2 = exception_class(nr);
313 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
314 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
315 /* generate double fault per SDM Table 5-5 */
316 vcpu->arch.exception.pending = true;
317 vcpu->arch.exception.has_error_code = true;
318 vcpu->arch.exception.nr = DF_VECTOR;
319 vcpu->arch.exception.error_code = 0;
320 } else
321 /* replace previous exception with a new one in a hope
322 that instruction re-execution will regenerate lost
323 exception */
324 goto queue;
325}
326
298101da
AK		 327void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
328{
ce7ddec4 329 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 330}
331EXPORT_SYMBOL_GPL(kvm_queue_exception);
332
ce7ddec4
JR		 333void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
334{
335 kvm_multiple_exception(vcpu, nr, false, 0, true);
336}
337EXPORT_SYMBOL_GPL(kvm_requeue_exception);
338
db8fcefa 339void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 340{
db8fcefa
AP		 341 if (err)
342 kvm_inject_gp(vcpu, 0);
343 else
344 kvm_x86_ops->skip_emulated_instruction(vcpu);
345}
346EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 347
6389ee94 348void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 349{
350 ++vcpu->stat.pf_guest;
6389ee94
AK		 351 vcpu->arch.cr2 = fault->address;
352 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 353}
27d6c865 354EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 355
6389ee94 356void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 357{
6389ee94
AK		 358 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
359 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 360 else
6389ee94 361 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 362}
363
3419ffc8
SY		 364void kvm_inject_nmi(struct kvm_vcpu *vcpu)
365{
7460fb4a
AK		 366 atomic_inc(&vcpu->arch.nmi_queued);
367 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 368}
369EXPORT_SYMBOL_GPL(kvm_inject_nmi);
370
298101da
AK		 371void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
372{
ce7ddec4 373 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 374}
375EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
376
ce7ddec4
JR		 377void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
378{
379 kvm_multiple_exception(vcpu, nr, true, error_code, true);
380}
381EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
382
0a79b009
AK		 383/*
384 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
385 * a #GP and return false.
386 */
387bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 388{
0a79b009
AK		 389 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
390 return true;
391 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
392 return false;
298101da 393}
0a79b009 394EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 395
ec92fe44
JR		 396/*
397 * This function will be used to read from the physical memory of the currently
398 * running guest. The difference to kvm_read_guest_page is that this function
399 * can read from guest physical or from the guest's guest physical memory.
400 */
401int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
402 gfn_t ngfn, void *data, int offset, int len,
403 u32 access)
404{
405 gfn_t real_gfn;
406 gpa_t ngpa;
407
408 ngpa = gfn_to_gpa(ngfn);
409 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
410 if (real_gfn == UNMAPPED_GVA)
411 return -EFAULT;
412
413 real_gfn = gpa_to_gfn(real_gfn);
414
415 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
416}
417EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
418
3d06b8bf
JR		 419int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
420 void *data, int offset, int len, u32 access)
421{
422 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
423 data, offset, len, access);
424}
425
a03490ed
CO		 426/*
427 * Load the pae pdptrs. Return true is they are all valid.
428 */
ff03a073 429int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 430{
431 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
432 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
433 int i;
434 int ret;
ff03a073 435 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 436
ff03a073
JR		 437 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
438 offset * sizeof(u64), sizeof(pdpte),
439 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 440 if (ret < 0) {
441 ret = 0;
442 goto out;
443 }
444 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 445 if (is_present_gpte(pdpte[i]) &&
20c466b5 446 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 447 ret = 0;
448 goto out;
449 }
450 }
451 ret = 1;
452
ff03a073 453 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 454 __set_bit(VCPU_EXREG_PDPTR,
455 (unsigned long *)&vcpu->arch.regs_avail);
456 __set_bit(VCPU_EXREG_PDPTR,
457 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 458out:
a03490ed
CO		 459
460 return ret;
461}
cc4b6871 462EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 463
d835dfec
AK		 464static bool pdptrs_changed(struct kvm_vcpu *vcpu)
465{
ff03a073 466 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 467 bool changed = true;
3d06b8bf
JR		 468 int offset;
469 gfn_t gfn;
d835dfec
AK		 470 int r;
471
472 if (is_long_mode(vcpu) || !is_pae(vcpu))
473 return false;
474
6de4f3ad
AK		 475 if (!test_bit(VCPU_EXREG_PDPTR,
476 (unsigned long *)&vcpu->arch.regs_avail))
477 return true;
478
9f8fe504
AK		 479 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
480 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 481 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
482 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 483 if (r < 0)
484 goto out;
ff03a073 485 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 486out:
d835dfec
AK		 487
488 return changed;
489}
490
49a9b07e 491int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 492{
aad82703
SY		 493 unsigned long old_cr0 = kvm_read_cr0(vcpu);
494 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
495 X86_CR0_CD | X86_CR0_NW;
496
f9a48e6a
AK		 497 cr0 |= X86_CR0_ET;
498
ab344828 499#ifdef CONFIG_X86_64
0f12244f
GN		 500 if (cr0 & 0xffffffff00000000UL)
501 return 1;
ab344828
GN		 502#endif
503
504 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 505
0f12244f
GN		 506 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
507 return 1;
a03490ed 508
0f12244f
GN		 509 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
510 return 1;
a03490ed
CO		 511
512 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
513#ifdef CONFIG_X86_64
f6801dff 514 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 515 int cs_db, cs_l;
516
0f12244f
GN		 517 if (!is_pae(vcpu))
518 return 1;
a03490ed 519 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 520 if (cs_l)
521 return 1;
a03490ed
CO		 522 } else
523#endif
ff03a073 524 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 525 kvm_read_cr3(vcpu)))
0f12244f 526 return 1;
a03490ed
CO		 527 }
528
ad756a16
MJ		 529 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
530 return 1;
531
a03490ed 532 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 533
d170c419 534 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 535 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 536 kvm_async_pf_hash_reset(vcpu);
537 }
e5f3f027 538
aad82703
SY		 539 if ((cr0 ^ old_cr0) & update_bits)
540 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 541 return 0;
542}
2d3ad1f4 543EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 544
2d3ad1f4 545void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 546{
49a9b07e 547 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 548}
2d3ad1f4 549EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 550
2acf923e
DC		 551int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
552{
553 u64 xcr0;
554
555 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
556 if (index != XCR_XFEATURE_ENABLED_MASK)
557 return 1;
558 xcr0 = xcr;
559 if (kvm_x86_ops->get_cpl(vcpu) != 0)
560 return 1;
561 if (!(xcr0 & XSTATE_FP))
562 return 1;
563 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
564 return 1;
565 if (xcr0 & ~host_xcr0)
566 return 1;
567 vcpu->arch.xcr0 = xcr0;
568 vcpu->guest_xcr0_loaded = 0;
569 return 0;
570}
571
572int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
573{
574 if (__kvm_set_xcr(vcpu, index, xcr)) {
575 kvm_inject_gp(vcpu, 0);
576 return 1;
577 }
578 return 0;
579}
580EXPORT_SYMBOL_GPL(kvm_set_xcr);
581
a83b29c6 582int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 583{
fc78f519 584 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 585 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
586 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 587 if (cr4 & CR4_RESERVED_BITS)
588 return 1;
a03490ed 589
2acf923e
DC		 590 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
591 return 1;
592
c68b734f
YW		 593 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
594 return 1;
595
74dc2b4f
YW		 596 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_RDWRGSFS))
597 return 1;
598
a03490ed 599 if (is_long_mode(vcpu)) {
0f12244f
GN		 600 if (!(cr4 & X86_CR4_PAE))
601 return 1;
a2edf57f
AK		 602 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
603 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 604 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
605 kvm_read_cr3(vcpu)))
0f12244f
GN		 606 return 1;
607
ad756a16
MJ		 608 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
609 if (!guest_cpuid_has_pcid(vcpu))
610 return 1;
611
612 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
613 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
614 return 1;
615 }
616
5e1746d6 617 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 618 return 1;
a03490ed 619
ad756a16
MJ		 620 if (((cr4 ^ old_cr4) & pdptr_bits) ||
621 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 622 kvm_mmu_reset_context(vcpu);
0f12244f 623
2acf923e 624 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 625 kvm_update_cpuid(vcpu);
2acf923e 626
0f12244f
GN		 627 return 0;
628}
2d3ad1f4 629EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 630
2390218b 631int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 632{
9f8fe504 633 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 634 kvm_mmu_sync_roots(vcpu);
d835dfec 635 kvm_mmu_flush_tlb(vcpu);
0f12244f 636 return 0;
d835dfec
AK		 637 }
638
a03490ed 639 if (is_long_mode(vcpu)) {
471842ec 640 if (kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) {
ad756a16
MJ		 641 if (cr3 & CR3_PCID_ENABLED_RESERVED_BITS)
642 return 1;
643 } else
644 if (cr3 & CR3_L_MODE_RESERVED_BITS)
645 return 1;
a03490ed
CO		 646 } else {
647 if (is_pae(vcpu)) {
0f12244f
GN		 648 if (cr3 & CR3_PAE_RESERVED_BITS)
649 return 1;
ff03a073
JR		 650 if (is_paging(vcpu) &&
651 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 652 return 1;
a03490ed
CO		 653 }
654 /*
655 * We don't check reserved bits in nonpae mode, because
656 * this isn't enforced, and VMware depends on this.
657 */
658 }
659
a03490ed
CO		 660 /*
661 * Does the new cr3 value map to physical memory? (Note, we
662 * catch an invalid cr3 even in real-mode, because it would
663 * cause trouble later on when we turn on paging anyway.)
664 *
665 * A real CPU would silently accept an invalid cr3 and would
666 * attempt to use it - with largely undefined (and often hard
667 * to debug) behavior on the guest side.
668 */
669 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 670 return 1;
671 vcpu->arch.cr3 = cr3;
aff48baa 672 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
0f12244f
GN		 673 vcpu->arch.mmu.new_cr3(vcpu);
674 return 0;
675}
2d3ad1f4 676EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 677
eea1cff9 678int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 679{
0f12244f
GN		 680 if (cr8 & CR8_RESERVED_BITS)
681 return 1;
a03490ed
CO		 682 if (irqchip_in_kernel(vcpu->kvm))
683 kvm_lapic_set_tpr(vcpu, cr8);
684 else
ad312c7c 685 vcpu->arch.cr8 = cr8;
0f12244f
GN		 686 return 0;
687}
2d3ad1f4 688EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 689
2d3ad1f4 690unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 691{
692 if (irqchip_in_kernel(vcpu->kvm))
693 return kvm_lapic_get_cr8(vcpu);
694 else
ad312c7c 695 return vcpu->arch.cr8;
a03490ed 696}
2d3ad1f4 697EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 698
c8639010
JK		 699static void kvm_update_dr7(struct kvm_vcpu *vcpu)
700{
701 unsigned long dr7;
702
703 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
704 dr7 = vcpu->arch.guest_debug_dr7;
705 else
706 dr7 = vcpu->arch.dr7;
707 kvm_x86_ops->set_dr7(vcpu, dr7);
708 vcpu->arch.switch_db_regs = (dr7 & DR7_BP_EN_MASK);
709}
710
338dbc97 711static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 712{
713 switch (dr) {
714 case 0 ... 3:
715 vcpu->arch.db[dr] = val;
716 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
717 vcpu->arch.eff_db[dr] = val;
718 break;
719 case 4:
338dbc97
GN		 720 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
721 return 1; /* #UD */
020df079
GN		 722 /* fall through */
723 case 6:
338dbc97
GN		 724 if (val & 0xffffffff00000000ULL)
725 return -1; /* #GP */
020df079
GN		 726 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
727 break;
728 case 5:
338dbc97
GN		 729 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
730 return 1; /* #UD */
020df079
GN		 731 /* fall through */
732 default: /* 7 */
338dbc97
GN		 733 if (val & 0xffffffff00000000ULL)
734 return -1; /* #GP */
020df079 735 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 736 kvm_update_dr7(vcpu);
020df079
GN		 737 break;
738 }
739
740 return 0;
741}
338dbc97
GN		 742
743int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
744{
745 int res;
746
747 res = __kvm_set_dr(vcpu, dr, val);
748 if (res > 0)
749 kvm_queue_exception(vcpu, UD_VECTOR);
750 else if (res < 0)
751 kvm_inject_gp(vcpu, 0);
752
753 return res;
754}
020df079
GN		 755EXPORT_SYMBOL_GPL(kvm_set_dr);
756
338dbc97 757static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 758{
759 switch (dr) {
760 case 0 ... 3:
761 *val = vcpu->arch.db[dr];
762 break;
763 case 4:
338dbc97 764 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 765 return 1;
020df079
GN		 766 /* fall through */
767 case 6:
768 *val = vcpu->arch.dr6;
769 break;
770 case 5:
338dbc97 771 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 772 return 1;
020df079
GN		 773 /* fall through */
774 default: /* 7 */
775 *val = vcpu->arch.dr7;
776 break;
777 }
778
779 return 0;
780}
338dbc97
GN		 781
782int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
783{
784 if (_kvm_get_dr(vcpu, dr, val)) {
785 kvm_queue_exception(vcpu, UD_VECTOR);
786 return 1;
787 }
788 return 0;
789}
020df079
GN		 790EXPORT_SYMBOL_GPL(kvm_get_dr);
791
022cd0e8
AK		 792bool kvm_rdpmc(struct kvm_vcpu *vcpu)
793{
794 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
795 u64 data;
796 int err;
797
798 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
799 if (err)
800 return err;
801 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
802 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
803 return err;
804}
805EXPORT_SYMBOL_GPL(kvm_rdpmc);
806
043405e1
CO		 807/*
808 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
809 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
810 *
811 * This list is modified at module load time to reflect the
e3267cbb
GC		 812 * capabilities of the host cpu. This capabilities test skips MSRs that are
813 * kvm-specific. Those are put in the beginning of the list.
043405e1 814 */
e3267cbb 815
439793d4 816#define KVM_SAVE_MSRS_BEGIN 10
043405e1 817static u32 msrs_to_save[] = {
e3267cbb 818 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 819 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 820 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
c9aaa895 821 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
ae7a2a3f 822 MSR_KVM_PV_EOI_EN,
043405e1 823 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 824 MSR_STAR,
043405e1
CO		 825#ifdef CONFIG_X86_64
826 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
827#endif
e90aa41e 828 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 829};
830
831static unsigned num_msrs_to_save;
832
f1d24831 833static const u32 emulated_msrs[] = {
a3e06bbe 834 MSR_IA32_TSCDEADLINE,
043405e1 835 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 836 MSR_IA32_MCG_STATUS,
837 MSR_IA32_MCG_CTL,
043405e1
CO		 838};
839
b69e8cae 840static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 841{
aad82703
SY		 842 u64 old_efer = vcpu->arch.efer;
843
b69e8cae
RJ		 844 if (efer & efer_reserved_bits)
845 return 1;
15c4a640
CO		 846
847 if (is_paging(vcpu)
b69e8cae
RJ		 848 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
849 return 1;
15c4a640 850
1b2fd70c
AG		 851 if (efer & EFER_FFXSR) {
852 struct kvm_cpuid_entry2 *feat;
853
854 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 855 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
856 return 1;
1b2fd70c
AG		 857 }
858
d8017474
AG		 859 if (efer & EFER_SVME) {
860 struct kvm_cpuid_entry2 *feat;
861
862 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 863 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
864 return 1;
d8017474
AG		 865 }
866
15c4a640 867 efer &= ~EFER_LMA;
f6801dff 868 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 869
a3d204e2
SY		 870 kvm_x86_ops->set_efer(vcpu, efer);
871
9645bb56 872 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
b69e8cae 873
aad82703
SY		 874 /* Update reserved bits */
875 if ((efer ^ old_efer) & EFER_NX)
876 kvm_mmu_reset_context(vcpu);
877
b69e8cae 878 return 0;
15c4a640
CO		 879}
880
f2b4b7dd
JR		 881void kvm_enable_efer_bits(u64 mask)
882{
883 efer_reserved_bits &= ~mask;
884}
885EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
886
887
15c4a640
CO		 888/*
889 * Writes msr value into into the appropriate "register".
890 * Returns 0 on success, non-0 otherwise.
891 * Assumes vcpu_load() was already called.
892 */
893int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
894{
895 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
896}
897
313a3dc7
CO		 898/*
899 * Adapt set_msr() to msr_io()'s calling convention
900 */
901static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
902{
903 return kvm_set_msr(vcpu, index, *data);
904}
905
16e8d74d
MT		 906#ifdef CONFIG_X86_64
907struct pvclock_gtod_data {
908 seqcount_t seq;
909
910 struct { /* extract of a clocksource struct */
911 int vclock_mode;
912 cycle_t cycle_last;
913 cycle_t mask;
914 u32 mult;
915 u32 shift;
916 } clock;
917
918 /* open coded 'struct timespec' */
919 u64 monotonic_time_snsec;
920 time_t monotonic_time_sec;
921};
922
923static struct pvclock_gtod_data pvclock_gtod_data;
924
925static void update_pvclock_gtod(struct timekeeper *tk)
926{
927 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
928
929 write_seqcount_begin(&vdata->seq);
930
931 /* copy pvclock gtod data */
932 vdata->clock.vclock_mode = tk->clock->archdata.vclock_mode;
933 vdata->clock.cycle_last = tk->clock->cycle_last;
934 vdata->clock.mask = tk->clock->mask;
935 vdata->clock.mult = tk->mult;
936 vdata->clock.shift = tk->shift;
937
938 vdata->monotonic_time_sec = tk->xtime_sec
939 + tk->wall_to_monotonic.tv_sec;
940 vdata->monotonic_time_snsec = tk->xtime_nsec
941 + (tk->wall_to_monotonic.tv_nsec
942 << tk->shift);
943 while (vdata->monotonic_time_snsec >=
944 (((u64)NSEC_PER_SEC) << tk->shift)) {
945 vdata->monotonic_time_snsec -=
946 ((u64)NSEC_PER_SEC) << tk->shift;
947 vdata->monotonic_time_sec++;
948 }
949
950 write_seqcount_end(&vdata->seq);
951}
952#endif
953
954
18068523
GOC		 955static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
956{
9ed3c444
AK		 957 int version;
958 int r;
50d0a0f9 959 struct pvclock_wall_clock wc;
923de3cf 960 struct timespec boot;
18068523
GOC		 961
962 if (!wall_clock)
963 return;
964
9ed3c444
AK		 965 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
966 if (r)
967 return;
968
969 if (version & 1)
970 ++version; /* first time write, random junk */
971
972 ++version;
18068523 973
18068523
GOC		 974 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
975
50d0a0f9
GH		 976 /*
977 * The guest calculates current wall clock time by adding
34c238a1 978 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 979 * wall clock specified here. guest system time equals host
980 * system time for us, thus we must fill in host boot time here.
981 */
923de3cf 982 getboottime(&boot);
50d0a0f9 983
4b648665
BR		 984 if (kvm->arch.kvmclock_offset) {
985 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
986 boot = timespec_sub(boot, ts);
987 }
50d0a0f9
GH		 988 wc.sec = boot.tv_sec;
989 wc.nsec = boot.tv_nsec;
990 wc.version = version;
18068523
GOC		 991
992 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
993
994 version++;
995 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 996}
997
50d0a0f9
GH		 998static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
999{
1000 uint32_t quotient, remainder;
1001
1002 /* Don't try to replace with do_div(), this one calculates
1003 * "(dividend << 32) / divisor" */
1004 __asm__ ( "divl %4"
1005 : "=a" (quotient), "=d" (remainder)
1006 : "0" (0), "1" (dividend), "r" (divisor) );
1007 return quotient;
1008}
1009
5f4e3f88
ZA		 1010static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1011 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1012{
5f4e3f88 1013 uint64_t scaled64;
50d0a0f9
GH		 1014 int32_t shift = 0;
1015 uint64_t tps64;
1016 uint32_t tps32;
1017
5f4e3f88
ZA		 1018 tps64 = base_khz * 1000LL;
1019 scaled64 = scaled_khz * 1000LL;
50933623 1020 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1021 tps64 >>= 1;
1022 shift--;
1023 }
1024
1025 tps32 = (uint32_t)tps64;
50933623
JK		 1026 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1027 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1028 scaled64 >>= 1;
1029 else
1030 tps32 <<= 1;
50d0a0f9
GH		 1031 shift++;
1032 }
1033
5f4e3f88
ZA		 1034 *pshift = shift;
1035 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1036
5f4e3f88
ZA		 1037 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1038 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1039}
1040
759379dd
ZA		 1041static inline u64 get_kernel_ns(void)
1042{
1043 struct timespec ts;
1044
1045 WARN_ON(preemptible());
1046 ktime_get_ts(&ts);
1047 monotonic_to_bootbased(&ts);
1048 return timespec_to_ns(&ts);
50d0a0f9
GH		 1049}
1050
d828199e 1051#ifdef CONFIG_X86_64
16e8d74d 1052static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1053#endif
16e8d74d 1054
c8076604 1055static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 1056unsigned long max_tsc_khz;
c8076604 1057
cc578287 1058static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1059{
cc578287
ZA		 1060 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1061 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1062}
1063
cc578287 1064static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1065{
cc578287
ZA		 1066 u64 v = (u64)khz * (1000000 + ppm);
1067 do_div(v, 1000000);
1068 return v;
1e993611
JR		 1069}
1070
cc578287 1071static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1072{
cc578287
ZA		 1073 u32 thresh_lo, thresh_hi;
1074 int use_scaling = 0;
217fc9cf 1075
c285545f
ZA		 1076 /* Compute a scale to convert nanoseconds in TSC cycles */
1077 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1078 &vcpu->arch.virtual_tsc_shift,
1079 &vcpu->arch.virtual_tsc_mult);
1080 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1081
1082 /*
1083 * Compute the variation in TSC rate which is acceptable
1084 * within the range of tolerance and decide if the
1085 * rate being applied is within that bounds of the hardware
1086 * rate. If so, no scaling or compensation need be done.
1087 */
1088 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1089 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1090 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1091 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1092 use_scaling = 1;
1093 }
1094 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1095}
1096
1097static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1098{
e26101b1 1099 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1100 vcpu->arch.virtual_tsc_mult,
1101 vcpu->arch.virtual_tsc_shift);
e26101b1 1102 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1103 return tsc;
1104}
1105
b48aa97e
MT		 1106void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1107{
1108#ifdef CONFIG_X86_64
1109 bool vcpus_matched;
1110 bool do_request = false;
1111 struct kvm_arch *ka = &vcpu->kvm->arch;
1112 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1113
1114 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1115 atomic_read(&vcpu->kvm->online_vcpus));
1116
1117 if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC)
1118 if (!ka->use_master_clock)
1119 do_request = 1;
1120
1121 if (!vcpus_matched && ka->use_master_clock)
1122 do_request = 1;
1123
1124 if (do_request)
1125 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1126
1127 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1128 atomic_read(&vcpu->kvm->online_vcpus),
1129 ka->use_master_clock, gtod->clock.vclock_mode);
1130#endif
1131}
1132
99e3e30a
ZA		 1133void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
1134{
1135 struct kvm *kvm = vcpu->kvm;
f38e098f 1136 u64 offset, ns, elapsed;
99e3e30a 1137 unsigned long flags;
02626b6a 1138 s64 usdiff;
b48aa97e 1139 bool matched;
99e3e30a 1140
038f8c11 1141 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1142 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1143 ns = get_kernel_ns();
f38e098f 1144 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6
ZA		 1145
1146 /* n.b - signed multiplication and division required */
02626b6a 1147 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1148#ifdef CONFIG_X86_64
02626b6a 1149 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6
ZA		 1150#else
1151 /* do_div() only does unsigned */
1152 asm("idivl %2; xor %%edx, %%edx"
02626b6a
MT		 1153 : "=A"(usdiff)
1154 : "A"(usdiff * 1000), "rm"(vcpu->arch.virtual_tsc_khz));
5d3cb0f6 1155#endif
02626b6a
MT		 1156 do_div(elapsed, 1000);
1157 usdiff -= elapsed;
1158 if (usdiff < 0)
1159 usdiff = -usdiff;
f38e098f
ZA		 1160
1161 /*
5d3cb0f6
ZA		 1162 * Special case: TSC write with a small delta (1 second) of virtual
1163 * cycle time against real time is interpreted as an attempt to
1164 * synchronize the CPU.
1165 *
1166 * For a reliable TSC, we can match TSC offsets, and for an unstable
1167 * TSC, we add elapsed time in this computation. We could let the
1168 * compensation code attempt to catch up if we fall behind, but
1169 * it's better to try to match offsets from the beginning.
1170 */
02626b6a 1171 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1172 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1173 if (!check_tsc_unstable()) {
e26101b1 1174 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1175 pr_debug("kvm: matched tsc offset for %llu\n", data);
1176 } else {
857e4099 1177 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1178 data += delta;
1179 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1180 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1181 }
b48aa97e 1182 matched = true;
e26101b1
ZA		 1183 } else {
1184 /*
1185 * We split periods of matched TSC writes into generations.
1186 * For each generation, we track the original measured
1187 * nanosecond time, offset, and write, so if TSCs are in
1188 * sync, we can match exact offset, and if not, we can match
4a969980 1189 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1190 *
1191 * These values are tracked in kvm->arch.cur_xxx variables.
1192 */
1193 kvm->arch.cur_tsc_generation++;
1194 kvm->arch.cur_tsc_nsec = ns;
1195 kvm->arch.cur_tsc_write = data;
1196 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1197 matched = false;
e26101b1
ZA		 1198 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1199 kvm->arch.cur_tsc_generation, data);
f38e098f 1200 }
e26101b1
ZA		 1201
1202 /*
1203 * We also track th most recent recorded KHZ, write and time to
1204 * allow the matching interval to be extended at each write.
1205 */
f38e098f
ZA		 1206 kvm->arch.last_tsc_nsec = ns;
1207 kvm->arch.last_tsc_write = data;
5d3cb0f6 1208 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a
ZA		 1209
1210 /* Reset of TSC must disable overshoot protection below */
1211 vcpu->arch.hv_clock.tsc_timestamp = 0;
b183aa58 1212 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1213
1214 /* Keep track of which generation this VCPU has synchronized to */
1215 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1216 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1217 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1218
1219 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1220 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1221
1222 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1223 if (matched)
1224 kvm->arch.nr_vcpus_matched_tsc++;
1225 else
1226 kvm->arch.nr_vcpus_matched_tsc = 0;
1227
1228 kvm_track_tsc_matching(vcpu);
1229 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1230}
e26101b1 1231
99e3e30a
ZA		 1232EXPORT_SYMBOL_GPL(kvm_write_tsc);
1233
d828199e
MT		 1234#ifdef CONFIG_X86_64
1235
1236static cycle_t read_tsc(void)
1237{
1238 cycle_t ret;
1239 u64 last;
1240
1241 /*
1242 * Empirically, a fence (of type that depends on the CPU)
1243 * before rdtsc is enough to ensure that rdtsc is ordered
1244 * with respect to loads. The various CPU manuals are unclear
1245 * as to whether rdtsc can be reordered with later loads,
1246 * but no one has ever seen it happen.
1247 */
1248 rdtsc_barrier();
1249 ret = (cycle_t)vget_cycles();
1250
1251 last = pvclock_gtod_data.clock.cycle_last;
1252
1253 if (likely(ret >= last))
1254 return ret;
1255
1256 /*
1257 * GCC likes to generate cmov here, but this branch is extremely
1258 * predictable (it's just a funciton of time and the likely is
1259 * very likely) and there's a data dependence, so force GCC
1260 * to generate a branch instead. I don't barrier() because
1261 * we don't actually need a barrier, and if this function
1262 * ever gets inlined it will generate worse code.
1263 */
1264 asm volatile ("");
1265 return last;
1266}
1267
1268static inline u64 vgettsc(cycle_t *cycle_now)
1269{
1270 long v;
1271 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1272
1273 *cycle_now = read_tsc();
1274
1275 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1276 return v * gtod->clock.mult;
1277}
1278
1279static int do_monotonic(struct timespec *ts, cycle_t *cycle_now)
1280{
1281 unsigned long seq;
1282 u64 ns;
1283 int mode;
1284 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1285
1286 ts->tv_nsec = 0;
1287 do {
1288 seq = read_seqcount_begin(&gtod->seq);
1289 mode = gtod->clock.vclock_mode;
1290 ts->tv_sec = gtod->monotonic_time_sec;
1291 ns = gtod->monotonic_time_snsec;
1292 ns += vgettsc(cycle_now);
1293 ns >>= gtod->clock.shift;
1294 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1295 timespec_add_ns(ts, ns);
1296
1297 return mode;
1298}
1299
1300/* returns true if host is using tsc clocksource */
1301static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1302{
1303 struct timespec ts;
1304
1305 /* checked again under seqlock below */
1306 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1307 return false;
1308
1309 if (do_monotonic(&ts, cycle_now) != VCLOCK_TSC)
1310 return false;
1311
1312 monotonic_to_bootbased(&ts);
1313 *kernel_ns = timespec_to_ns(&ts);
1314
1315 return true;
1316}
1317#endif
1318
1319/*
1320 *
b48aa97e
MT		 1321 * Assuming a stable TSC across physical CPUS, and a stable TSC
1322 * across virtual CPUs, the following condition is possible.
1323 * Each numbered line represents an event visible to both
d828199e
MT		 1324 * CPUs at the next numbered event.
1325 *
1326 * "timespecX" represents host monotonic time. "tscX" represents
1327 * RDTSC value.
1328 *
1329 * VCPU0 on CPU0 | VCPU1 on CPU1
1330 *
1331 * 1. read timespec0,tsc0
1332 * 2. | timespec1 = timespec0 + N
1333 * | tsc1 = tsc0 + M
1334 * 3. transition to guest | transition to guest
1335 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1336 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1337 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1338 *
1339 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1340 *
1341 * - ret0 < ret1
1342 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1343 * ...
1344 * - 0 < N - M => M < N
1345 *
1346 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1347 * always the case (the difference between two distinct xtime instances
1348 * might be smaller then the difference between corresponding TSC reads,
1349 * when updating guest vcpus pvclock areas).
1350 *
1351 * To avoid that problem, do not allow visibility of distinct
1352 * system_timestamp/tsc_timestamp values simultaneously: use a master
1353 * copy of host monotonic time values. Update that master copy
1354 * in lockstep.
1355 *
b48aa97e 1356 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1357 *
1358 */
1359
1360static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1361{
1362#ifdef CONFIG_X86_64
1363 struct kvm_arch *ka = &kvm->arch;
1364 int vclock_mode;
b48aa97e
MT		 1365 bool host_tsc_clocksource, vcpus_matched;
1366
1367 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1368 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1369
1370 /*
1371 * If the host uses TSC clock, then passthrough TSC as stable
1372 * to the guest.
1373 */
b48aa97e 1374 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1375 &ka->master_kernel_ns,
1376 &ka->master_cycle_now);
1377
b48aa97e
MT		 1378 ka->use_master_clock = host_tsc_clocksource & vcpus_matched;
1379
d828199e
MT		 1380 if (ka->use_master_clock)
1381 atomic_set(&kvm_guest_has_master_clock, 1);
1382
1383 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1384 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1385 vcpus_matched);
d828199e
MT		 1386#endif
1387}
1388
34c238a1 1389static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1390{
d828199e 1391 unsigned long flags, this_tsc_khz;
18068523 1392 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1393 struct kvm_arch *ka = &v->kvm->arch;
18068523 1394 void *shared_kaddr;
1d5f066e 1395 s64 kernel_ns, max_kernel_ns;
d828199e 1396 u64 tsc_timestamp, host_tsc;
78c0337a 1397 struct pvclock_vcpu_time_info *guest_hv_clock;
51d59c6b 1398 u8 pvclock_flags;
d828199e
MT		 1399 bool use_master_clock;
1400
1401 kernel_ns = 0;
1402 host_tsc = 0;
18068523 1403
18068523
GOC		 1404 /* Keep irq disabled to prevent changes to the clock */
1405 local_irq_save(flags);
cc578287 1406 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
8cfdc000 1407 if (unlikely(this_tsc_khz == 0)) {
c285545f 1408 local_irq_restore(flags);
34c238a1 1409 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
8cfdc000
ZA		 1410 return 1;
1411 }
18068523 1412
d828199e
MT		 1413 /*
1414 * If the host uses TSC clock, then passthrough TSC as stable
1415 * to the guest.
1416 */
1417 spin_lock(&ka->pvclock_gtod_sync_lock);
1418 use_master_clock = ka->use_master_clock;
1419 if (use_master_clock) {
1420 host_tsc = ka->master_cycle_now;
1421 kernel_ns = ka->master_kernel_ns;
1422 }
1423 spin_unlock(&ka->pvclock_gtod_sync_lock);
1424 if (!use_master_clock) {
1425 host_tsc = native_read_tsc();
1426 kernel_ns = get_kernel_ns();
1427 }
1428
1429 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1430
c285545f
ZA		 1431 /*
1432 * We may have to catch up the TSC to match elapsed wall clock
1433 * time for two reasons, even if kvmclock is used.
1434 * 1) CPU could have been running below the maximum TSC rate
1435 * 2) Broken TSC compensation resets the base at each VCPU
1436 * entry to avoid unknown leaps of TSC even when running
1437 * again on the same CPU. This may cause apparent elapsed
1438 * time to disappear, and the guest to stand still or run
1439 * very slowly.
1440 */
1441 if (vcpu->tsc_catchup) {
1442 u64 tsc = compute_guest_tsc(v, kernel_ns);
1443 if (tsc > tsc_timestamp) {
f1e2b260 1444 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1445 tsc_timestamp = tsc;
1446 }
50d0a0f9
GH		 1447 }
1448
18068523
GOC		 1449 local_irq_restore(flags);
1450
c285545f
ZA		 1451 if (!vcpu->time_page)
1452 return 0;
18068523 1453
1d5f066e
ZA		 1454 /*
1455 * Time as measured by the TSC may go backwards when resetting the base
1456 * tsc_timestamp. The reason for this is that the TSC resolution is
1457 * higher than the resolution of the other clock scales. Thus, many
1458 * possible measurments of the TSC correspond to one measurement of any
1459 * other clock, and so a spread of values is possible. This is not a
1460 * problem for the computation of the nanosecond clock; with TSC rates
1461 * around 1GHZ, there can only be a few cycles which correspond to one
1462 * nanosecond value, and any path through this code will inevitably
1463 * take longer than that. However, with the kernel_ns value itself,
1464 * the precision may be much lower, down to HZ granularity. If the
1465 * first sampling of TSC against kernel_ns ends in the low part of the
1466 * range, and the second in the high end of the range, we can get:
1467 *
1468 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1469 *
1470 * As the sampling errors potentially range in the thousands of cycles,
1471 * it is possible such a time value has already been observed by the
1472 * guest. To protect against this, we must compute the system time as
1473 * observed by the guest and ensure the new system time is greater.
1474 */
1475 max_kernel_ns = 0;
b183aa58 1476 if (vcpu->hv_clock.tsc_timestamp) {
1d5f066e
ZA		 1477 max_kernel_ns = vcpu->last_guest_tsc -
1478 vcpu->hv_clock.tsc_timestamp;
1479 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1480 vcpu->hv_clock.tsc_to_system_mul,
1481 vcpu->hv_clock.tsc_shift);
1482 max_kernel_ns += vcpu->last_kernel_ns;
1483 }
afbcf7ab 1484
e48672fa 1485 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1486 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1487 &vcpu->hv_clock.tsc_shift,
1488 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1489 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1490 }
1491
d828199e
MT		 1492 /* with a master <monotonic time, tsc value> tuple,
1493 * pvclock clock reads always increase at the (scaled) rate
1494 * of guest TSC - no need to deal with sampling errors.
1495 */
1496 if (!use_master_clock) {
1497 if (max_kernel_ns > kernel_ns)
1498 kernel_ns = max_kernel_ns;
1499 }
8cfdc000 1500 /* With all the info we got, fill in the values */
1d5f066e 1501 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1502 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1503 vcpu->last_kernel_ns = kernel_ns;
28e4639a 1504 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1505
18068523
GOC		 1506 /*
1507 * The interface expects us to write an even number signaling that the
1508 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1509 * state, we just increase by 2 at the end.
18068523 1510 */
50d0a0f9 1511 vcpu->hv_clock.version += 2;
18068523 1512
8fd75e12 1513 shared_kaddr = kmap_atomic(vcpu->time_page);
18068523 1514
78c0337a
MT		 1515 guest_hv_clock = shared_kaddr + vcpu->time_offset;
1516
1517 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1518 pvclock_flags = (guest_hv_clock->flags & PVCLOCK_GUEST_STOPPED);
1519
1520 if (vcpu->pvclock_set_guest_stopped_request) {
1521 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1522 vcpu->pvclock_set_guest_stopped_request = false;
1523 }
1524
d828199e
MT		 1525 /* If the host uses TSC clocksource, then it is stable */
1526 if (use_master_clock)
1527 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1528
78c0337a
MT		 1529 vcpu->hv_clock.flags = pvclock_flags;
1530
18068523 1531 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 1532 sizeof(vcpu->hv_clock));
18068523 1533
8fd75e12 1534 kunmap_atomic(shared_kaddr);
18068523
GOC		 1535
1536 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
8cfdc000 1537 return 0;
c8076604
GH		 1538}
1539
9ba075a6
AK		 1540static bool msr_mtrr_valid(unsigned msr)
1541{
1542 switch (msr) {
1543 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1544 case MSR_MTRRfix64K_00000:
1545 case MSR_MTRRfix16K_80000:
1546 case MSR_MTRRfix16K_A0000:
1547 case MSR_MTRRfix4K_C0000:
1548 case MSR_MTRRfix4K_C8000:
1549 case MSR_MTRRfix4K_D0000:
1550 case MSR_MTRRfix4K_D8000:
1551 case MSR_MTRRfix4K_E0000:
1552 case MSR_MTRRfix4K_E8000:
1553 case MSR_MTRRfix4K_F0000:
1554 case MSR_MTRRfix4K_F8000:
1555 case MSR_MTRRdefType:
1556 case MSR_IA32_CR_PAT:
1557 return true;
1558 case 0x2f8:
1559 return true;
1560 }
1561 return false;
1562}
1563
d6289b93
MT		 1564static bool valid_pat_type(unsigned t)
1565{
1566 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1567}
1568
1569static bool valid_mtrr_type(unsigned t)
1570{
1571 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1572}
1573
1574static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1575{
1576 int i;
1577
1578 if (!msr_mtrr_valid(msr))
1579 return false;
1580
1581 if (msr == MSR_IA32_CR_PAT) {
1582 for (i = 0; i < 8; i++)
1583 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1584 return false;
1585 return true;
1586 } else if (msr == MSR_MTRRdefType) {
1587 if (data & ~0xcff)
1588 return false;
1589 return valid_mtrr_type(data & 0xff);
1590 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1591 for (i = 0; i < 8 ; i++)
1592 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1593 return false;
1594 return true;
1595 }
1596
1597 /* variable MTRRs */
1598 return valid_mtrr_type(data & 0xff);
1599}
1600
9ba075a6
AK		 1601static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1602{
0bed3b56
SY		 1603 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1604
d6289b93 1605 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1606 return 1;
1607
0bed3b56
SY		 1608 if (msr == MSR_MTRRdefType) {
1609 vcpu->arch.mtrr_state.def_type = data;
1610 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1611 } else if (msr == MSR_MTRRfix64K_00000)
1612 p[0] = data;
1613 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1614 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1615 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1616 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1617 else if (msr == MSR_IA32_CR_PAT)
1618 vcpu->arch.pat = data;
1619 else { /* Variable MTRRs */
1620 int idx, is_mtrr_mask;
1621 u64 *pt;
1622
1623 idx = (msr - 0x200) / 2;
1624 is_mtrr_mask = msr - 0x200 - 2 * idx;
1625 if (!is_mtrr_mask)
1626 pt =
1627 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1628 else
1629 pt =
1630 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1631 *pt = data;
1632 }
1633
1634 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1635 return 0;
1636}
15c4a640 1637
890ca9ae 1638static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1639{
890ca9ae
HY		 1640 u64 mcg_cap = vcpu->arch.mcg_cap;
1641 unsigned bank_num = mcg_cap & 0xff;
1642
15c4a640 1643 switch (msr) {
15c4a640 1644 case MSR_IA32_MCG_STATUS:
890ca9ae 1645 vcpu->arch.mcg_status = data;
15c4a640 1646 break;
c7ac679c 1647 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1648 if (!(mcg_cap & MCG_CTL_P))
1649 return 1;
1650 if (data != 0 && data != ~(u64)0)
1651 return -1;
1652 vcpu->arch.mcg_ctl = data;
1653 break;
1654 default:
1655 if (msr >= MSR_IA32_MC0_CTL &&
1656 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1657 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1658 /* only 0 or all 1s can be written to IA32_MCi_CTL
1659 * some Linux kernels though clear bit 10 in bank 4 to
1660 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1661 * this to avoid an uncatched #GP in the guest
1662 */
890ca9ae 1663 if ((offset & 0x3) == 0 &&
114be429 1664 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1665 return -1;
1666 vcpu->arch.mce_banks[offset] = data;
1667 break;
1668 }
1669 return 1;
1670 }
1671 return 0;
1672}
1673
ffde22ac
ES		 1674static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1675{
1676 struct kvm *kvm = vcpu->kvm;
1677 int lm = is_long_mode(vcpu);
1678 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1679 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1680 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1681 : kvm->arch.xen_hvm_config.blob_size_32;
1682 u32 page_num = data & ~PAGE_MASK;
1683 u64 page_addr = data & PAGE_MASK;
1684 u8 *page;
1685 int r;
1686
1687 r = -E2BIG;
1688 if (page_num >= blob_size)
1689 goto out;
1690 r = -ENOMEM;
ff5c2c03
SL		 1691 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1692 if (IS_ERR(page)) {
1693 r = PTR_ERR(page);
ffde22ac 1694 goto out;
ff5c2c03 1695 }
ffde22ac
ES		 1696 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1697 goto out_free;
1698 r = 0;
1699out_free:
1700 kfree(page);
1701out:
1702 return r;
1703}
1704
55cd8e5a
GN		 1705static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1706{
1707 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1708}
1709
1710static bool kvm_hv_msr_partition_wide(u32 msr)
1711{
1712 bool r = false;
1713 switch (msr) {
1714 case HV_X64_MSR_GUEST_OS_ID:
1715 case HV_X64_MSR_HYPERCALL:
1716 r = true;
1717 break;
1718 }
1719
1720 return r;
1721}
1722
1723static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1724{
1725 struct kvm *kvm = vcpu->kvm;
1726
1727 switch (msr) {
1728 case HV_X64_MSR_GUEST_OS_ID:
1729 kvm->arch.hv_guest_os_id = data;
1730 /* setting guest os id to zero disables hypercall page */
1731 if (!kvm->arch.hv_guest_os_id)
1732 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1733 break;
1734 case HV_X64_MSR_HYPERCALL: {
1735 u64 gfn;
1736 unsigned long addr;
1737 u8 instructions[4];
1738
1739 /* if guest os id is not set hypercall should remain disabled */
1740 if (!kvm->arch.hv_guest_os_id)
1741 break;
1742 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1743 kvm->arch.hv_hypercall = data;
1744 break;
1745 }
1746 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1747 addr = gfn_to_hva(kvm, gfn);
1748 if (kvm_is_error_hva(addr))
1749 return 1;
1750 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1751 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1752 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1753 return 1;
1754 kvm->arch.hv_hypercall = data;
1755 break;
1756 }
1757 default:
a737f256
CD		 1758 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1759 "data 0x%llx\n", msr, data);
55cd8e5a
GN		 1760 return 1;
1761 }
1762 return 0;
1763}
1764
1765static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1766{
10388a07
GN		 1767 switch (msr) {
1768 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1769 unsigned long addr;
55cd8e5a 1770
10388a07
GN		 1771 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1772 vcpu->arch.hv_vapic = data;
1773 break;
1774 }
1775 addr = gfn_to_hva(vcpu->kvm, data >>
1776 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1777 if (kvm_is_error_hva(addr))
1778 return 1;
8b0cedff 1779 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 1780 return 1;
1781 vcpu->arch.hv_vapic = data;
1782 break;
1783 }
1784 case HV_X64_MSR_EOI:
1785 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1786 case HV_X64_MSR_ICR:
1787 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1788 case HV_X64_MSR_TPR:
1789 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1790 default:
a737f256
CD		 1791 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1792 "data 0x%llx\n", msr, data);
10388a07
GN		 1793 return 1;
1794 }
1795
1796 return 0;
55cd8e5a
GN		 1797}
1798
344d9588
GN		 1799static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1800{
1801 gpa_t gpa = data & ~0x3f;
1802
4a969980 1803 /* Bits 2:5 are reserved, Should be zero */
6adba527 1804 if (data & 0x3c)
344d9588
GN		 1805 return 1;
1806
1807 vcpu->arch.apf.msr_val = data;
1808
1809 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1810 kvm_clear_async_pf_completion_queue(vcpu);
1811 kvm_async_pf_hash_reset(vcpu);
1812 return 0;
1813 }
1814
1815 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
1816 return 1;
1817
6adba527 1818 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1819 kvm_async_pf_wakeup_all(vcpu);
1820 return 0;
1821}
1822
12f9a48f
GC		 1823static void kvmclock_reset(struct kvm_vcpu *vcpu)
1824{
1825 if (vcpu->arch.time_page) {
1826 kvm_release_page_dirty(vcpu->arch.time_page);
1827 vcpu->arch.time_page = NULL;
1828 }
1829}
1830
c9aaa895
GC		 1831static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1832{
1833 u64 delta;
1834
1835 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1836 return;
1837
1838 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1839 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1840 vcpu->arch.st.accum_steal = delta;
1841}
1842
1843static void record_steal_time(struct kvm_vcpu *vcpu)
1844{
1845 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1846 return;
1847
1848 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1849 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1850 return;
1851
1852 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1853 vcpu->arch.st.steal.version += 2;
1854 vcpu->arch.st.accum_steal = 0;
1855
1856 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1857 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1858}
1859
15c4a640
CO		 1860int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1861{
5753785f
GN		 1862 bool pr = false;
1863
15c4a640 1864 switch (msr) {
15c4a640 1865 case MSR_EFER:
b69e8cae 1866 return set_efer(vcpu, data);
8f1589d9
AP		 1867 case MSR_K7_HWCR:
1868 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1869 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 1870 data &= ~(u64)0x8; /* ignore TLB cache disable */
8f1589d9 1871 if (data != 0) {
a737f256
CD		 1872 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1873 data);
8f1589d9
AP		 1874 return 1;
1875 }
15c4a640 1876 break;
f7c6d140
AP		 1877 case MSR_FAM10H_MMIO_CONF_BASE:
1878 if (data != 0) {
a737f256
CD		 1879 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1880 "0x%llx\n", data);
f7c6d140
AP		 1881 return 1;
1882 }
15c4a640 1883 break;
c323c0e5 1884 case MSR_AMD64_NB_CFG:
c7ac679c 1885 break;
b5e2fec0
AG		 1886 case MSR_IA32_DEBUGCTLMSR:
1887 if (!data) {
1888 /* We support the non-activated case already */
1889 break;
1890 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1891 /* Values other than LBR and BTF are vendor-specific,
1892 thus reserved and should throw a #GP */
1893 return 1;
1894 }
a737f256
CD		 1895 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1896 __func__, data);
b5e2fec0 1897 break;
15c4a640
CO		 1898 case MSR_IA32_UCODE_REV:
1899 case MSR_IA32_UCODE_WRITE:
61a6bd67 1900 case MSR_VM_HSAVE_PA:
6098ca93 1901 case MSR_AMD64_PATCH_LOADER:
15c4a640 1902 break;
9ba075a6
AK		 1903 case 0x200 ... 0x2ff:
1904 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1905 case MSR_IA32_APICBASE:
1906 kvm_set_apic_base(vcpu, data);
1907 break;
0105d1a5
GN		 1908 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1909 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 1910 case MSR_IA32_TSCDEADLINE:
1911 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1912 break;
15c4a640 1913 case MSR_IA32_MISC_ENABLE:
ad312c7c 1914 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1915 break;
11c6bffa 1916 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1917 case MSR_KVM_WALL_CLOCK:
1918 vcpu->kvm->arch.wall_clock = data;
1919 kvm_write_wall_clock(vcpu->kvm, data);
1920 break;
11c6bffa 1921 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 1922 case MSR_KVM_SYSTEM_TIME: {
12f9a48f 1923 kvmclock_reset(vcpu);
18068523
GOC		 1924
1925 vcpu->arch.time = data;
c285545f 1926 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
18068523
GOC		 1927
1928 /* we verify if the enable bit is set... */
1929 if (!(data & 1))
1930 break;
1931
1932 /* ...but clean it before doing the actual write */
1933 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1934
18068523
GOC		 1935 vcpu->arch.time_page =
1936 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523 1937
32cad84f 1938 if (is_error_page(vcpu->arch.time_page))
18068523 1939 vcpu->arch.time_page = NULL;
32cad84f 1940
18068523
GOC		 1941 break;
1942 }
344d9588
GN		 1943 case MSR_KVM_ASYNC_PF_EN:
1944 if (kvm_pv_enable_async_pf(vcpu, data))
1945 return 1;
1946 break;
c9aaa895
GC		 1947 case MSR_KVM_STEAL_TIME:
1948
1949 if (unlikely(!sched_info_on()))
1950 return 1;
1951
1952 if (data & KVM_STEAL_RESERVED_MASK)
1953 return 1;
1954
1955 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
1956 data & KVM_STEAL_VALID_BITS))
1957 return 1;
1958
1959 vcpu->arch.st.msr_val = data;
1960
1961 if (!(data & KVM_MSR_ENABLED))
1962 break;
1963
1964 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1965
1966 preempt_disable();
1967 accumulate_steal_time(vcpu);
1968 preempt_enable();
1969
1970 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
1971
1972 break;
ae7a2a3f
MT		 1973 case MSR_KVM_PV_EOI_EN:
1974 if (kvm_lapic_enable_pv_eoi(vcpu, data))
1975 return 1;
1976 break;
c9aaa895 1977
890ca9ae
HY		 1978 case MSR_IA32_MCG_CTL:
1979 case MSR_IA32_MCG_STATUS:
1980 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1981 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1982
1983 /* Performance counters are not protected by a CPUID bit,
1984 * so we should check all of them in the generic path for the sake of
1985 * cross vendor migration.
1986 * Writing a zero into the event select MSRs disables them,
1987 * which we perfectly emulate ;-). Any other value should be at least
1988 * reported, some guests depend on them.
1989 */
71db6023
AP		 1990 case MSR_K7_EVNTSEL0:
1991 case MSR_K7_EVNTSEL1:
1992 case MSR_K7_EVNTSEL2:
1993 case MSR_K7_EVNTSEL3:
1994 if (data != 0)
a737f256
CD		 1995 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1996 "0x%x data 0x%llx\n", msr, data);
71db6023
AP		 1997 break;
1998 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1999 * so we ignore writes to make it happy.
2000 */
71db6023
AP		 2001 case MSR_K7_PERFCTR0:
2002 case MSR_K7_PERFCTR1:
2003 case MSR_K7_PERFCTR2:
2004 case MSR_K7_PERFCTR3:
a737f256
CD		 2005 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2006 "0x%x data 0x%llx\n", msr, data);
71db6023 2007 break;
5753785f
GN		 2008 case MSR_P6_PERFCTR0:
2009 case MSR_P6_PERFCTR1:
2010 pr = true;
2011 case MSR_P6_EVNTSEL0:
2012 case MSR_P6_EVNTSEL1:
2013 if (kvm_pmu_msr(vcpu, msr))
2014 return kvm_pmu_set_msr(vcpu, msr, data);
2015
2016 if (pr || data != 0)
a737f256
CD		 2017 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2018 "0x%x data 0x%llx\n", msr, data);
5753785f 2019 break;
84e0cefa
JS		 2020 case MSR_K7_CLK_CTL:
2021 /*
2022 * Ignore all writes to this no longer documented MSR.
2023 * Writes are only relevant for old K7 processors,
2024 * all pre-dating SVM, but a recommended workaround from
4a969980 2025 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2026 * affected processor models on the command line, hence
2027 * the need to ignore the workaround.
2028 */
2029 break;
55cd8e5a
GN		 2030 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2031 if (kvm_hv_msr_partition_wide(msr)) {
2032 int r;
2033 mutex_lock(&vcpu->kvm->lock);
2034 r = set_msr_hyperv_pw(vcpu, msr, data);
2035 mutex_unlock(&vcpu->kvm->lock);
2036 return r;
2037 } else
2038 return set_msr_hyperv(vcpu, msr, data);
2039 break;
91c9c3ed 2040 case MSR_IA32_BBL_CR_CTL3:
2041 /* Drop writes to this legacy MSR -- see rdmsr
2042 * counterpart for further detail.
2043 */
a737f256 2044 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2045 break;
2b036c6b
BO		 2046 case MSR_AMD64_OSVW_ID_LENGTH:
2047 if (!guest_cpuid_has_osvw(vcpu))
2048 return 1;
2049 vcpu->arch.osvw.length = data;
2050 break;
2051 case MSR_AMD64_OSVW_STATUS:
2052 if (!guest_cpuid_has_osvw(vcpu))
2053 return 1;
2054 vcpu->arch.osvw.status = data;
2055 break;
15c4a640 2056 default:
ffde22ac
ES		 2057 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2058 return xen_hvm_config(vcpu, data);
f5132b01
GN		 2059 if (kvm_pmu_msr(vcpu, msr))
2060 return kvm_pmu_set_msr(vcpu, msr, data);
ed85c068 2061 if (!ignore_msrs) {
a737f256
CD		 2062 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2063 msr, data);
ed85c068
AP		 2064 return 1;
2065 } else {
a737f256
CD		 2066 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2067 msr, data);
ed85c068
AP		 2068 break;
2069 }
15c4a640
CO		 2070 }
2071 return 0;
2072}
2073EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2074
2075
2076/*
2077 * Reads an msr value (of 'msr_index') into 'pdata'.
2078 * Returns 0 on success, non-0 otherwise.
2079 * Assumes vcpu_load() was already called.
2080 */
2081int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2082{
2083 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2084}
2085
9ba075a6
AK		 2086static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2087{
0bed3b56
SY		 2088 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2089
9ba075a6
AK		 2090 if (!msr_mtrr_valid(msr))
2091 return 1;
2092
0bed3b56
SY		 2093 if (msr == MSR_MTRRdefType)
2094 *pdata = vcpu->arch.mtrr_state.def_type +
2095 (vcpu->arch.mtrr_state.enabled << 10);
2096 else if (msr == MSR_MTRRfix64K_00000)
2097 *pdata = p[0];
2098 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2099 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2100 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2101 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2102 else if (msr == MSR_IA32_CR_PAT)
2103 *pdata = vcpu->arch.pat;
2104 else { /* Variable MTRRs */
2105 int idx, is_mtrr_mask;
2106 u64 *pt;
2107
2108 idx = (msr - 0x200) / 2;
2109 is_mtrr_mask = msr - 0x200 - 2 * idx;
2110 if (!is_mtrr_mask)
2111 pt =
2112 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2113 else
2114 pt =
2115 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2116 *pdata = *pt;
2117 }
2118
9ba075a6
AK		 2119 return 0;
2120}
2121
890ca9ae 2122static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2123{
2124 u64 data;
890ca9ae
HY		 2125 u64 mcg_cap = vcpu->arch.mcg_cap;
2126 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2127
2128 switch (msr) {
15c4a640
CO		 2129 case MSR_IA32_P5_MC_ADDR:
2130 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2131 data = 0;
2132 break;
15c4a640 2133 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2134 data = vcpu->arch.mcg_cap;
2135 break;
c7ac679c 2136 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2137 if (!(mcg_cap & MCG_CTL_P))
2138 return 1;
2139 data = vcpu->arch.mcg_ctl;
2140 break;
2141 case MSR_IA32_MCG_STATUS:
2142 data = vcpu->arch.mcg_status;
2143 break;
2144 default:
2145 if (msr >= MSR_IA32_MC0_CTL &&
2146 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
2147 u32 offset = msr - MSR_IA32_MC0_CTL;
2148 data = vcpu->arch.mce_banks[offset];
2149 break;
2150 }
2151 return 1;
2152 }
2153 *pdata = data;
2154 return 0;
2155}
2156
55cd8e5a
GN		 2157static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2158{
2159 u64 data = 0;
2160 struct kvm *kvm = vcpu->kvm;
2161
2162 switch (msr) {
2163 case HV_X64_MSR_GUEST_OS_ID:
2164 data = kvm->arch.hv_guest_os_id;
2165 break;
2166 case HV_X64_MSR_HYPERCALL:
2167 data = kvm->arch.hv_hypercall;
2168 break;
2169 default:
a737f256 2170 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2171 return 1;
2172 }
2173
2174 *pdata = data;
2175 return 0;
2176}
2177
2178static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2179{
2180 u64 data = 0;
2181
2182 switch (msr) {
2183 case HV_X64_MSR_VP_INDEX: {
2184 int r;
2185 struct kvm_vcpu *v;
2186 kvm_for_each_vcpu(r, v, vcpu->kvm)
2187 if (v == vcpu)
2188 data = r;
2189 break;
2190 }
10388a07
GN		 2191 case HV_X64_MSR_EOI:
2192 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2193 case HV_X64_MSR_ICR:
2194 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2195 case HV_X64_MSR_TPR:
2196 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 2197 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 2198 data = vcpu->arch.hv_vapic;
2199 break;
55cd8e5a 2200 default:
a737f256 2201 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2202 return 1;
2203 }
2204 *pdata = data;
2205 return 0;
2206}
2207
890ca9ae
HY		 2208int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2209{
2210 u64 data;
2211
2212 switch (msr) {
890ca9ae 2213 case MSR_IA32_PLATFORM_ID:
15c4a640 2214 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2215 case MSR_IA32_DEBUGCTLMSR:
2216 case MSR_IA32_LASTBRANCHFROMIP:
2217 case MSR_IA32_LASTBRANCHTOIP:
2218 case MSR_IA32_LASTINTFROMIP:
2219 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 2220 case MSR_K8_SYSCFG:
2221 case MSR_K7_HWCR:
61a6bd67 2222 case MSR_VM_HSAVE_PA:
9e699624 2223 case MSR_K7_EVNTSEL0:
1f3ee616 2224 case MSR_K7_PERFCTR0:
1fdbd48c 2225 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2226 case MSR_AMD64_NB_CFG:
f7c6d140 2227 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 2228 data = 0;
2229 break;
5753785f
GN		 2230 case MSR_P6_PERFCTR0:
2231 case MSR_P6_PERFCTR1:
2232 case MSR_P6_EVNTSEL0:
2233 case MSR_P6_EVNTSEL1:
2234 if (kvm_pmu_msr(vcpu, msr))
2235 return kvm_pmu_get_msr(vcpu, msr, pdata);
2236 data = 0;
2237 break;
742bc670
MT		 2238 case MSR_IA32_UCODE_REV:
2239 data = 0x100000000ULL;
2240 break;
9ba075a6
AK		 2241 case MSR_MTRRcap:
2242 data = 0x500 | KVM_NR_VAR_MTRR;
2243 break;
2244 case 0x200 ... 0x2ff:
2245 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 2246 case 0xcd: /* fsb frequency */
2247 data = 3;
2248 break;
7b914098
JS		 2249 /*
2250 * MSR_EBC_FREQUENCY_ID
2251 * Conservative value valid for even the basic CPU models.
2252 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2253 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2254 * and 266MHz for model 3, or 4. Set Core Clock
2255 * Frequency to System Bus Frequency Ratio to 1 (bits
2256 * 31:24) even though these are only valid for CPU
2257 * models > 2, however guests may end up dividing or
2258 * multiplying by zero otherwise.
2259 */
2260 case MSR_EBC_FREQUENCY_ID:
2261 data = 1 << 24;
2262 break;
15c4a640
CO		 2263 case MSR_IA32_APICBASE:
2264 data = kvm_get_apic_base(vcpu);
2265 break;
0105d1a5
GN		 2266 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2267 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2268 break;
a3e06bbe
LJ		 2269 case MSR_IA32_TSCDEADLINE:
2270 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2271 break;
15c4a640 2272 case MSR_IA32_MISC_ENABLE:
ad312c7c 2273 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2274 break;
847f0ad8
AG		 2275 case MSR_IA32_PERF_STATUS:
2276 /* TSC increment by tick */
2277 data = 1000ULL;
2278 /* CPU multiplier */
2279 data |= (((uint64_t)4ULL) << 40);
2280 break;
15c4a640 2281 case MSR_EFER:
f6801dff 2282 data = vcpu->arch.efer;
15c4a640 2283 break;
18068523 2284 case MSR_KVM_WALL_CLOCK:
11c6bffa 2285 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2286 data = vcpu->kvm->arch.wall_clock;
2287 break;
2288 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2289 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 2290 data = vcpu->arch.time;
2291 break;
344d9588
GN		 2292 case MSR_KVM_ASYNC_PF_EN:
2293 data = vcpu->arch.apf.msr_val;
2294 break;
c9aaa895
GC		 2295 case MSR_KVM_STEAL_TIME:
2296 data = vcpu->arch.st.msr_val;
2297 break;
1d92128f
MT		 2298 case MSR_KVM_PV_EOI_EN:
2299 data = vcpu->arch.pv_eoi.msr_val;
2300 break;
890ca9ae
HY		 2301 case MSR_IA32_P5_MC_ADDR:
2302 case MSR_IA32_P5_MC_TYPE:
2303 case MSR_IA32_MCG_CAP:
2304 case MSR_IA32_MCG_CTL:
2305 case MSR_IA32_MCG_STATUS:
2306 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2307 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 2308 case MSR_K7_CLK_CTL:
2309 /*
2310 * Provide expected ramp-up count for K7. All other
2311 * are set to zero, indicating minimum divisors for
2312 * every field.
2313 *
2314 * This prevents guest kernels on AMD host with CPU
2315 * type 6, model 8 and higher from exploding due to
2316 * the rdmsr failing.
2317 */
2318 data = 0x20000000;
2319 break;
55cd8e5a
GN		 2320 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2321 if (kvm_hv_msr_partition_wide(msr)) {
2322 int r;
2323 mutex_lock(&vcpu->kvm->lock);
2324 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2325 mutex_unlock(&vcpu->kvm->lock);
2326 return r;
2327 } else
2328 return get_msr_hyperv(vcpu, msr, pdata);
2329 break;
91c9c3ed 2330 case MSR_IA32_BBL_CR_CTL3:
2331 /* This legacy MSR exists but isn't fully documented in current
2332 * silicon. It is however accessed by winxp in very narrow
2333 * scenarios where it sets bit #19, itself documented as
2334 * a "reserved" bit. Best effort attempt to source coherent
2335 * read data here should the balance of the register be
2336 * interpreted by the guest:
2337 *
2338 * L2 cache control register 3: 64GB range, 256KB size,
2339 * enabled, latency 0x1, configured
2340 */
2341 data = 0xbe702111;
2342 break;
2b036c6b
BO		 2343 case MSR_AMD64_OSVW_ID_LENGTH:
2344 if (!guest_cpuid_has_osvw(vcpu))
2345 return 1;
2346 data = vcpu->arch.osvw.length;
2347 break;
2348 case MSR_AMD64_OSVW_STATUS:
2349 if (!guest_cpuid_has_osvw(vcpu))
2350 return 1;
2351 data = vcpu->arch.osvw.status;
2352 break;
15c4a640 2353 default:
f5132b01
GN		 2354 if (kvm_pmu_msr(vcpu, msr))
2355 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068 2356 if (!ignore_msrs) {
a737f256 2357 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
ed85c068
AP		 2358 return 1;
2359 } else {
a737f256 2360 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
ed85c068
AP		 2361 data = 0;
2362 }
2363 break;
15c4a640
CO		 2364 }
2365 *pdata = data;
2366 return 0;
2367}
2368EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2369
313a3dc7
CO		 2370/*
2371 * Read or write a bunch of msrs. All parameters are kernel addresses.
2372 *
2373 * @return number of msrs set successfully.
2374 */
2375static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2376 struct kvm_msr_entry *entries,
2377 int (*do_msr)(struct kvm_vcpu *vcpu,
2378 unsigned index, u64 *data))
2379{
f656ce01 2380 int i, idx;
313a3dc7 2381
f656ce01 2382 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2383 for (i = 0; i < msrs->nmsrs; ++i)
2384 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2385 break;
f656ce01 2386 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2387
313a3dc7
CO		 2388 return i;
2389}
2390
2391/*
2392 * Read or write a bunch of msrs. Parameters are user addresses.
2393 *
2394 * @return number of msrs set successfully.
2395 */
2396static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2397 int (*do_msr)(struct kvm_vcpu *vcpu,
2398 unsigned index, u64 *data),
2399 int writeback)
2400{
2401 struct kvm_msrs msrs;
2402 struct kvm_msr_entry *entries;
2403 int r, n;
2404 unsigned size;
2405
2406 r = -EFAULT;
2407 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2408 goto out;
2409
2410 r = -E2BIG;
2411 if (msrs.nmsrs >= MAX_IO_MSRS)
2412 goto out;
2413
313a3dc7 2414 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2415 entries = memdup_user(user_msrs->entries, size);
2416 if (IS_ERR(entries)) {
2417 r = PTR_ERR(entries);
313a3dc7 2418 goto out;
ff5c2c03 2419 }
313a3dc7
CO		 2420
2421 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2422 if (r < 0)
2423 goto out_free;
2424
2425 r = -EFAULT;
2426 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2427 goto out_free;
2428
2429 r = n;
2430
2431out_free:
7a73c028 2432 kfree(entries);
313a3dc7
CO		 2433out:
2434 return r;
2435}
2436
018d00d2
ZX		 2437int kvm_dev_ioctl_check_extension(long ext)
2438{
2439 int r;
2440
2441 switch (ext) {
2442 case KVM_CAP_IRQCHIP:
2443 case KVM_CAP_HLT:
2444 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2445 case KVM_CAP_SET_TSS_ADDR:
07716717 2446 case KVM_CAP_EXT_CPUID:
c8076604 2447 case KVM_CAP_CLOCKSOURCE:
7837699f 2448 case KVM_CAP_PIT:
a28e4f5a 2449 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2450 case KVM_CAP_MP_STATE:
ed848624 2451 case KVM_CAP_SYNC_MMU:
a355c85c 2452 case KVM_CAP_USER_NMI:
52d939a0 2453 case KVM_CAP_REINJECT_CONTROL:
4925663a 2454 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 2455 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 2456 case KVM_CAP_IRQFD:
d34e6b17 2457 case KVM_CAP_IOEVENTFD:
c5ff41ce 2458 case KVM_CAP_PIT2:
e9f42757 2459 case KVM_CAP_PIT_STATE2:
b927a3ce 2460 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2461 case KVM_CAP_XEN_HVM:
afbcf7ab 2462 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2463 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2464 case KVM_CAP_HYPERV:
10388a07 2465 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2466 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2467 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2468 case KVM_CAP_DEBUGREGS:
d2be1651 2469 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2470 case KVM_CAP_XSAVE:
344d9588 2471 case KVM_CAP_ASYNC_PF:
92a1f12d 2472 case KVM_CAP_GET_TSC_KHZ:
07700a94 2473 case KVM_CAP_PCI_2_3:
1c0b28c2 2474 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2475 case KVM_CAP_READONLY_MEM:
7a84428a 2476 case KVM_CAP_IRQFD_RESAMPLE:
018d00d2
ZX		 2477 r = 1;
2478 break;
542472b5
LV		 2479 case KVM_CAP_COALESCED_MMIO:
2480 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2481 break;
774ead3a
AK		 2482 case KVM_CAP_VAPIC:
2483 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2484 break;
f725230a 2485 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2486 r = KVM_SOFT_MAX_VCPUS;
2487 break;
2488 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2489 r = KVM_MAX_VCPUS;
2490 break;
a988b910
AK		 2491 case KVM_CAP_NR_MEMSLOTS:
2492 r = KVM_MEMORY_SLOTS;
2493 break;
a68a6a72
MT		 2494 case KVM_CAP_PV_MMU: /* obsolete */
2495 r = 0;
2f333bcb 2496 break;
62c476c7 2497 case KVM_CAP_IOMMU:
a1b60c1c 2498 r = iommu_present(&pci_bus_type);
62c476c7 2499 break;
890ca9ae
HY		 2500 case KVM_CAP_MCE:
2501 r = KVM_MAX_MCE_BANKS;
2502 break;
2d5b5a66
SY		 2503 case KVM_CAP_XCRS:
2504 r = cpu_has_xsave;
2505 break;
92a1f12d
JR		 2506 case KVM_CAP_TSC_CONTROL:
2507 r = kvm_has_tsc_control;
2508 break;
4d25a066
JK		 2509 case KVM_CAP_TSC_DEADLINE_TIMER:
2510 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2511 break;
018d00d2
ZX		 2512 default:
2513 r = 0;
2514 break;
2515 }
2516 return r;
2517
2518}
2519
043405e1
CO		 2520long kvm_arch_dev_ioctl(struct file *filp,
2521 unsigned int ioctl, unsigned long arg)
2522{
2523 void __user *argp = (void __user *)arg;
2524 long r;
2525
2526 switch (ioctl) {
2527 case KVM_GET_MSR_INDEX_LIST: {
2528 struct kvm_msr_list __user *user_msr_list = argp;
2529 struct kvm_msr_list msr_list;
2530 unsigned n;
2531
2532 r = -EFAULT;
2533 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2534 goto out;
2535 n = msr_list.nmsrs;
2536 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2537 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2538 goto out;
2539 r = -E2BIG;
e125e7b6 2540 if (n < msr_list.nmsrs)
043405e1
CO		 2541 goto out;
2542 r = -EFAULT;
2543 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2544 num_msrs_to_save * sizeof(u32)))
2545 goto out;
e125e7b6 2546 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2547 &emulated_msrs,
2548 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2549 goto out;
2550 r = 0;
2551 break;
2552 }
674eea0f
AK		 2553 case KVM_GET_SUPPORTED_CPUID: {
2554 struct kvm_cpuid2 __user *cpuid_arg = argp;
2555 struct kvm_cpuid2 cpuid;
2556
2557 r = -EFAULT;
2558 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2559 goto out;
2560 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 2561 cpuid_arg->entries);
674eea0f
AK		 2562 if (r)
2563 goto out;
2564
2565 r = -EFAULT;
2566 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2567 goto out;
2568 r = 0;
2569 break;
2570 }
890ca9ae
HY		 2571 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2572 u64 mce_cap;
2573
2574 mce_cap = KVM_MCE_CAP_SUPPORTED;
2575 r = -EFAULT;
2576 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2577 goto out;
2578 r = 0;
2579 break;
2580 }
043405e1
CO		 2581 default:
2582 r = -EINVAL;
2583 }
2584out:
2585 return r;
2586}
2587
f5f48ee1
SY		 2588static void wbinvd_ipi(void *garbage)
2589{
2590 wbinvd();
2591}
2592
2593static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2594{
2595 return vcpu->kvm->arch.iommu_domain &&
2596 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2597}
2598
313a3dc7
CO		 2599void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2600{
f5f48ee1
SY		 2601 /* Address WBINVD may be executed by guest */
2602 if (need_emulate_wbinvd(vcpu)) {
2603 if (kvm_x86_ops->has_wbinvd_exit())
2604 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2605 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2606 smp_call_function_single(vcpu->cpu,
2607 wbinvd_ipi, NULL, 1);
2608 }
2609
313a3dc7 2610 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2611
0dd6a6ed
ZA		 2612 /* Apply any externally detected TSC adjustments (due to suspend) */
2613 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2614 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2615 vcpu->arch.tsc_offset_adjustment = 0;
2616 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2617 }
8f6055cb 2618
48434c20 2619 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 2620 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2621 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2622 if (tsc_delta < 0)
2623 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2624 if (check_tsc_unstable()) {
b183aa58
ZA		 2625 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2626 vcpu->arch.last_guest_tsc);
2627 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2628 vcpu->arch.tsc_catchup = 1;
c285545f 2629 }
d98d07ca
MT		 2630 /*
2631 * On a host with synchronized TSC, there is no need to update
2632 * kvmclock on vcpu->cpu migration
2633 */
2634 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2635 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2636 if (vcpu->cpu != cpu)
2637 kvm_migrate_timers(vcpu);
e48672fa 2638 vcpu->cpu = cpu;
6b7d7e76 2639 }
c9aaa895
GC		 2640
2641 accumulate_steal_time(vcpu);
2642 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2643}
2644
2645void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2646{
02daab21 2647 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2648 kvm_put_guest_fpu(vcpu);
6f526ec5 2649 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2650}
2651
313a3dc7
CO		 2652static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2653 struct kvm_lapic_state *s)
2654{
ad312c7c 2655 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2656
2657 return 0;
2658}
2659
2660static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2661 struct kvm_lapic_state *s)
2662{
64eb0620 2663 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2664 update_cr8_intercept(vcpu);
313a3dc7
CO		 2665
2666 return 0;
2667}
2668
f77bc6a4
ZX		 2669static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2670 struct kvm_interrupt *irq)
2671{
a50abc3b 2672 if (irq->irq < 0 || irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4
ZX		 2673 return -EINVAL;
2674 if (irqchip_in_kernel(vcpu->kvm))
2675 return -ENXIO;
f77bc6a4 2676
66fd3f7f 2677 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2678 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2679
f77bc6a4
ZX		 2680 return 0;
2681}
2682
c4abb7c9
JK		 2683static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2684{
c4abb7c9 2685 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2686
2687 return 0;
2688}
2689
b209749f
AK		 2690static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2691 struct kvm_tpr_access_ctl *tac)
2692{
2693 if (tac->flags)
2694 return -EINVAL;
2695 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2696 return 0;
2697}
2698
890ca9ae
HY		 2699static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2700 u64 mcg_cap)
2701{
2702 int r;
2703 unsigned bank_num = mcg_cap & 0xff, bank;
2704
2705 r = -EINVAL;
a9e38c3e 2706 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2707 goto out;
2708 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2709 goto out;
2710 r = 0;
2711 vcpu->arch.mcg_cap = mcg_cap;
2712 /* Init IA32_MCG_CTL to all 1s */
2713 if (mcg_cap & MCG_CTL_P)
2714 vcpu->arch.mcg_ctl = ~(u64)0;
2715 /* Init IA32_MCi_CTL to all 1s */
2716 for (bank = 0; bank < bank_num; bank++)
2717 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2718out:
2719 return r;
2720}
2721
2722static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2723 struct kvm_x86_mce *mce)
2724{
2725 u64 mcg_cap = vcpu->arch.mcg_cap;
2726 unsigned bank_num = mcg_cap & 0xff;
2727 u64 *banks = vcpu->arch.mce_banks;
2728
2729 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2730 return -EINVAL;
2731 /*
2732 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2733 * reporting is disabled
2734 */
2735 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2736 vcpu->arch.mcg_ctl != ~(u64)0)
2737 return 0;
2738 banks += 4 * mce->bank;
2739 /*
2740 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2741 * reporting is disabled for the bank
2742 */
2743 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2744 return 0;
2745 if (mce->status & MCI_STATUS_UC) {
2746 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2747 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2748 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2749 return 0;
2750 }
2751 if (banks[1] & MCI_STATUS_VAL)
2752 mce->status |= MCI_STATUS_OVER;
2753 banks[2] = mce->addr;
2754 banks[3] = mce->misc;
2755 vcpu->arch.mcg_status = mce->mcg_status;
2756 banks[1] = mce->status;
2757 kvm_queue_exception(vcpu, MC_VECTOR);
2758 } else if (!(banks[1] & MCI_STATUS_VAL)
2759 || !(banks[1] & MCI_STATUS_UC)) {
2760 if (banks[1] & MCI_STATUS_VAL)
2761 mce->status |= MCI_STATUS_OVER;
2762 banks[2] = mce->addr;
2763 banks[3] = mce->misc;
2764 banks[1] = mce->status;
2765 } else
2766 banks[1] |= MCI_STATUS_OVER;
2767 return 0;
2768}
2769
3cfc3092
JK		 2770static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2771 struct kvm_vcpu_events *events)
2772{
7460fb4a 2773 process_nmi(vcpu);
03b82a30
JK		 2774 events->exception.injected =
2775 vcpu->arch.exception.pending &&
2776 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2777 events->exception.nr = vcpu->arch.exception.nr;
2778 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2779 events->exception.pad = 0;
3cfc3092
JK		 2780 events->exception.error_code = vcpu->arch.exception.error_code;
2781
03b82a30
JK		 2782 events->interrupt.injected =
2783 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2784 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2785 events->interrupt.soft = 0;
48005f64
JK		 2786 events->interrupt.shadow =
2787 kvm_x86_ops->get_interrupt_shadow(vcpu,
2788 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2789
2790 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2791 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2792 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2793 events->nmi.pad = 0;
3cfc3092
JK		 2794
2795 events->sipi_vector = vcpu->arch.sipi_vector;
2796
dab4b911 2797 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2798 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2799 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2800 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2801}
2802
2803static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2804 struct kvm_vcpu_events *events)
2805{
dab4b911 2806 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2807 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2808 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2809 return -EINVAL;
2810
7460fb4a 2811 process_nmi(vcpu);
3cfc3092
JK		 2812 vcpu->arch.exception.pending = events->exception.injected;
2813 vcpu->arch.exception.nr = events->exception.nr;
2814 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2815 vcpu->arch.exception.error_code = events->exception.error_code;
2816
2817 vcpu->arch.interrupt.pending = events->interrupt.injected;
2818 vcpu->arch.interrupt.nr = events->interrupt.nr;
2819 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2820 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2821 kvm_x86_ops->set_interrupt_shadow(vcpu,
2822 events->interrupt.shadow);
3cfc3092
JK		 2823
2824 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2825 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2826 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2827 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2828
dab4b911
JK		 2829 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2830 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092 2831
3842d135
AK		 2832 kvm_make_request(KVM_REQ_EVENT, vcpu);
2833
3cfc3092
JK		 2834 return 0;
2835}
2836
a1efbe77
JK		 2837static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2838 struct kvm_debugregs *dbgregs)
2839{
a1efbe77
JK		 2840 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2841 dbgregs->dr6 = vcpu->arch.dr6;
2842 dbgregs->dr7 = vcpu->arch.dr7;
2843 dbgregs->flags = 0;
97e69aa6 2844 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2845}
2846
2847static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2848 struct kvm_debugregs *dbgregs)
2849{
2850 if (dbgregs->flags)
2851 return -EINVAL;
2852
a1efbe77
JK		 2853 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2854 vcpu->arch.dr6 = dbgregs->dr6;
2855 vcpu->arch.dr7 = dbgregs->dr7;
2856
a1efbe77
JK		 2857 return 0;
2858}
2859
2d5b5a66
SY		 2860static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2861 struct kvm_xsave *guest_xsave)
2862{
2863 if (cpu_has_xsave)
2864 memcpy(guest_xsave->region,
2865 &vcpu->arch.guest_fpu.state->xsave,
f45755b8 2866 xstate_size);
2d5b5a66
SY		 2867 else {
2868 memcpy(guest_xsave->region,
2869 &vcpu->arch.guest_fpu.state->fxsave,
2870 sizeof(struct i387_fxsave_struct));
2871 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2872 XSTATE_FPSSE;
2873 }
2874}
2875
2876static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2877 struct kvm_xsave *guest_xsave)
2878{
2879 u64 xstate_bv =
2880 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2881
2882 if (cpu_has_xsave)
2883 memcpy(&vcpu->arch.guest_fpu.state->xsave,
f45755b8 2884 guest_xsave->region, xstate_size);
2d5b5a66
SY		 2885 else {
2886 if (xstate_bv & ~XSTATE_FPSSE)
2887 return -EINVAL;
2888 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2889 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2890 }
2891 return 0;
2892}
2893
2894static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2895 struct kvm_xcrs *guest_xcrs)
2896{
2897 if (!cpu_has_xsave) {
2898 guest_xcrs->nr_xcrs = 0;
2899 return;
2900 }
2901
2902 guest_xcrs->nr_xcrs = 1;
2903 guest_xcrs->flags = 0;
2904 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2905 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2906}
2907
2908static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2909 struct kvm_xcrs *guest_xcrs)
2910{
2911 int i, r = 0;
2912
2913 if (!cpu_has_xsave)
2914 return -EINVAL;
2915
2916 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2917 return -EINVAL;
2918
2919 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2920 /* Only support XCR0 currently */
2921 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2922 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2923 guest_xcrs->xcrs[0].value);
2924 break;
2925 }
2926 if (r)
2927 r = -EINVAL;
2928 return r;
2929}
2930
1c0b28c2
EM		 2931/*
2932 * kvm_set_guest_paused() indicates to the guest kernel that it has been
2933 * stopped by the hypervisor. This function will be called from the host only.
2934 * EINVAL is returned when the host attempts to set the flag for a guest that
2935 * does not support pv clocks.
2936 */
2937static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
2938{
1c0b28c2
EM		 2939 if (!vcpu->arch.time_page)
2940 return -EINVAL;
51d59c6b 2941 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 2942 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2943 return 0;
2944}
2945
313a3dc7
CO		 2946long kvm_arch_vcpu_ioctl(struct file *filp,
2947 unsigned int ioctl, unsigned long arg)
2948{
2949 struct kvm_vcpu *vcpu = filp->private_data;
2950 void __user *argp = (void __user *)arg;
2951 int r;
d1ac91d8
AK		 2952 union {
2953 struct kvm_lapic_state *lapic;
2954 struct kvm_xsave *xsave;
2955 struct kvm_xcrs *xcrs;
2956 void *buffer;
2957 } u;
2958
2959 u.buffer = NULL;
313a3dc7
CO		 2960 switch (ioctl) {
2961 case KVM_GET_LAPIC: {
2204ae3c
MT		 2962 r = -EINVAL;
2963 if (!vcpu->arch.apic)
2964 goto out;
d1ac91d8 2965 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2966
b772ff36 2967 r = -ENOMEM;
d1ac91d8 2968 if (!u.lapic)
b772ff36 2969 goto out;
d1ac91d8 2970 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 2971 if (r)
2972 goto out;
2973 r = -EFAULT;
d1ac91d8 2974 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2975 goto out;
2976 r = 0;
2977 break;
2978 }
2979 case KVM_SET_LAPIC: {
2204ae3c
MT		 2980 if (!vcpu->arch.apic)
2981 goto out;
ff5c2c03 2982 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 2983 if (IS_ERR(u.lapic))
2984 return PTR_ERR(u.lapic);
ff5c2c03 2985
d1ac91d8 2986 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 2987 break;
2988 }
f77bc6a4
ZX		 2989 case KVM_INTERRUPT: {
2990 struct kvm_interrupt irq;
2991
2992 r = -EFAULT;
2993 if (copy_from_user(&irq, argp, sizeof irq))
2994 goto out;
2995 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 2996 break;
2997 }
c4abb7c9
JK		 2998 case KVM_NMI: {
2999 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3000 break;
3001 }
313a3dc7
CO		 3002 case KVM_SET_CPUID: {
3003 struct kvm_cpuid __user *cpuid_arg = argp;
3004 struct kvm_cpuid cpuid;
3005
3006 r = -EFAULT;
3007 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3008 goto out;
3009 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3010 break;
3011 }
07716717
DK		 3012 case KVM_SET_CPUID2: {
3013 struct kvm_cpuid2 __user *cpuid_arg = argp;
3014 struct kvm_cpuid2 cpuid;
3015
3016 r = -EFAULT;
3017 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3018 goto out;
3019 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3020 cpuid_arg->entries);
07716717
DK		 3021 break;
3022 }
3023 case KVM_GET_CPUID2: {
3024 struct kvm_cpuid2 __user *cpuid_arg = argp;
3025 struct kvm_cpuid2 cpuid;
3026
3027 r = -EFAULT;
3028 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3029 goto out;
3030 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3031 cpuid_arg->entries);
07716717
DK		 3032 if (r)
3033 goto out;
3034 r = -EFAULT;
3035 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3036 goto out;
3037 r = 0;
3038 break;
3039 }
313a3dc7
CO		 3040 case KVM_GET_MSRS:
3041 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3042 break;
3043 case KVM_SET_MSRS:
3044 r = msr_io(vcpu, argp, do_set_msr, 0);
3045 break;
b209749f
AK		 3046 case KVM_TPR_ACCESS_REPORTING: {
3047 struct kvm_tpr_access_ctl tac;
3048
3049 r = -EFAULT;
3050 if (copy_from_user(&tac, argp, sizeof tac))
3051 goto out;
3052 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3053 if (r)
3054 goto out;
3055 r = -EFAULT;
3056 if (copy_to_user(argp, &tac, sizeof tac))
3057 goto out;
3058 r = 0;
3059 break;
3060 };
b93463aa
AK		 3061 case KVM_SET_VAPIC_ADDR: {
3062 struct kvm_vapic_addr va;
3063
3064 r = -EINVAL;
3065 if (!irqchip_in_kernel(vcpu->kvm))
3066 goto out;
3067 r = -EFAULT;
3068 if (copy_from_user(&va, argp, sizeof va))
3069 goto out;
3070 r = 0;
3071 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3072 break;
3073 }
890ca9ae
HY		 3074 case KVM_X86_SETUP_MCE: {
3075 u64 mcg_cap;
3076
3077 r = -EFAULT;
3078 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3079 goto out;
3080 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3081 break;
3082 }
3083 case KVM_X86_SET_MCE: {
3084 struct kvm_x86_mce mce;
3085
3086 r = -EFAULT;
3087 if (copy_from_user(&mce, argp, sizeof mce))
3088 goto out;
3089 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3090 break;
3091 }
3cfc3092
JK		 3092 case KVM_GET_VCPU_EVENTS: {
3093 struct kvm_vcpu_events events;
3094
3095 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3096
3097 r = -EFAULT;
3098 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3099 break;
3100 r = 0;
3101 break;
3102 }
3103 case KVM_SET_VCPU_EVENTS: {
3104 struct kvm_vcpu_events events;
3105
3106 r = -EFAULT;
3107 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3108 break;
3109
3110 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3111 break;
3112 }
a1efbe77
JK		 3113 case KVM_GET_DEBUGREGS: {
3114 struct kvm_debugregs dbgregs;
3115
3116 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3117
3118 r = -EFAULT;
3119 if (copy_to_user(argp, &dbgregs,
3120 sizeof(struct kvm_debugregs)))
3121 break;
3122 r = 0;
3123 break;
3124 }
3125 case KVM_SET_DEBUGREGS: {
3126 struct kvm_debugregs dbgregs;
3127
3128 r = -EFAULT;
3129 if (copy_from_user(&dbgregs, argp,
3130 sizeof(struct kvm_debugregs)))
3131 break;
3132
3133 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3134 break;
3135 }
2d5b5a66 3136 case KVM_GET_XSAVE: {
d1ac91d8 3137 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3138 r = -ENOMEM;
d1ac91d8 3139 if (!u.xsave)
2d5b5a66
SY		 3140 break;
3141
d1ac91d8 3142 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3143
3144 r = -EFAULT;
d1ac91d8 3145 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3146 break;
3147 r = 0;
3148 break;
3149 }
3150 case KVM_SET_XSAVE: {
ff5c2c03 3151 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3152 if (IS_ERR(u.xsave))
3153 return PTR_ERR(u.xsave);
2d5b5a66 3154
d1ac91d8 3155 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3156 break;
3157 }
3158 case KVM_GET_XCRS: {
d1ac91d8 3159 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3160 r = -ENOMEM;
d1ac91d8 3161 if (!u.xcrs)
2d5b5a66
SY		 3162 break;
3163
d1ac91d8 3164 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3165
3166 r = -EFAULT;
d1ac91d8 3167 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3168 sizeof(struct kvm_xcrs)))
3169 break;
3170 r = 0;
3171 break;
3172 }
3173 case KVM_SET_XCRS: {
ff5c2c03 3174 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3175 if (IS_ERR(u.xcrs))
3176 return PTR_ERR(u.xcrs);
2d5b5a66 3177
d1ac91d8 3178 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3179 break;
3180 }
92a1f12d
JR		 3181 case KVM_SET_TSC_KHZ: {
3182 u32 user_tsc_khz;
3183
3184 r = -EINVAL;
92a1f12d
JR		 3185 user_tsc_khz = (u32)arg;
3186
3187 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3188 goto out;
3189
cc578287
ZA		 3190 if (user_tsc_khz == 0)
3191 user_tsc_khz = tsc_khz;
3192
3193 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 3194
3195 r = 0;
3196 goto out;
3197 }
3198 case KVM_GET_TSC_KHZ: {
cc578287 3199 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3200 goto out;
3201 }
1c0b28c2
EM		 3202 case KVM_KVMCLOCK_CTRL: {
3203 r = kvm_set_guest_paused(vcpu);
3204 goto out;
3205 }
313a3dc7
CO		 3206 default:
3207 r = -EINVAL;
3208 }
3209out:
d1ac91d8 3210 kfree(u.buffer);
313a3dc7
CO		 3211 return r;
3212}
3213
5b1c1493
CO		 3214int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3215{
3216 return VM_FAULT_SIGBUS;
3217}
3218
1fe779f8
CO		 3219static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3220{
3221 int ret;
3222
3223 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3224 return -EINVAL;
1fe779f8
CO		 3225 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3226 return ret;
3227}
3228
b927a3ce
SY		 3229static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3230 u64 ident_addr)
3231{
3232 kvm->arch.ept_identity_map_addr = ident_addr;
3233 return 0;
3234}
3235
1fe779f8
CO		 3236static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3237 u32 kvm_nr_mmu_pages)
3238{
3239 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3240 return -EINVAL;
3241
79fac95e 3242 mutex_lock(&kvm->slots_lock);
7c8a83b7 3243 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 3244
3245 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3246 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3247
7c8a83b7 3248 spin_unlock(&kvm->mmu_lock);
79fac95e 3249 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3250 return 0;
3251}
3252
3253static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3254{
39de71ec 3255 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3256}
3257
1fe779f8
CO		 3258static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3259{
3260 int r;
3261
3262 r = 0;
3263 switch (chip->chip_id) {
3264 case KVM_IRQCHIP_PIC_MASTER:
3265 memcpy(&chip->chip.pic,
3266 &pic_irqchip(kvm)->pics[0],
3267 sizeof(struct kvm_pic_state));
3268 break;
3269 case KVM_IRQCHIP_PIC_SLAVE:
3270 memcpy(&chip->chip.pic,
3271 &pic_irqchip(kvm)->pics[1],
3272 sizeof(struct kvm_pic_state));
3273 break;
3274 case KVM_IRQCHIP_IOAPIC:
eba0226b 3275 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3276 break;
3277 default:
3278 r = -EINVAL;
3279 break;
3280 }
3281 return r;
3282}
3283
3284static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3285{
3286 int r;
3287
3288 r = 0;
3289 switch (chip->chip_id) {
3290 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3291 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3292 memcpy(&pic_irqchip(kvm)->pics[0],
3293 &chip->chip.pic,
3294 sizeof(struct kvm_pic_state));
f4f51050 3295 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3296 break;
3297 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3298 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3299 memcpy(&pic_irqchip(kvm)->pics[1],
3300 &chip->chip.pic,
3301 sizeof(struct kvm_pic_state));
f4f51050 3302 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3303 break;
3304 case KVM_IRQCHIP_IOAPIC:
eba0226b 3305 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3306 break;
3307 default:
3308 r = -EINVAL;
3309 break;
3310 }
3311 kvm_pic_update_irq(pic_irqchip(kvm));
3312 return r;
3313}
3314
e0f63cb9
SY		 3315static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3316{
3317 int r = 0;
3318
894a9c55 3319 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3320 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3321 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3322 return r;
3323}
3324
3325static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3326{
3327 int r = 0;
3328
894a9c55 3329 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3330 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3331 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3332 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3333 return r;
3334}
3335
3336static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3337{
3338 int r = 0;
3339
3340 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3341 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3342 sizeof(ps->channels));
3343 ps->flags = kvm->arch.vpit->pit_state.flags;
3344 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3345 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3346 return r;
3347}
3348
3349static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3350{
3351 int r = 0, start = 0;
3352 u32 prev_legacy, cur_legacy;
3353 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3354 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3355 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3356 if (!prev_legacy && cur_legacy)
3357 start = 1;
3358 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3359 sizeof(kvm->arch.vpit->pit_state.channels));
3360 kvm->arch.vpit->pit_state.flags = ps->flags;
3361 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3362 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3363 return r;
3364}
3365
52d939a0
MT		 3366static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3367 struct kvm_reinject_control *control)
3368{
3369 if (!kvm->arch.vpit)
3370 return -ENXIO;
894a9c55 3371 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3372 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3373 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3374 return 0;
3375}
3376
95d4c16c 3377/**
60c34612
TY		 3378 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3379 * @kvm: kvm instance
3380 * @log: slot id and address to which we copy the log
95d4c16c 3381 *
60c34612
TY		 3382 * We need to keep it in mind that VCPU threads can write to the bitmap
3383 * concurrently. So, to avoid losing data, we keep the following order for
3384 * each bit:
95d4c16c 3385 *
60c34612
TY		 3386 * 1. Take a snapshot of the bit and clear it if needed.
3387 * 2. Write protect the corresponding page.
3388 * 3. Flush TLB's if needed.
3389 * 4. Copy the snapshot to the userspace.
95d4c16c 3390 *
60c34612
TY		 3391 * Between 2 and 3, the guest may write to the page using the remaining TLB
3392 * entry. This is not a problem because the page will be reported dirty at
3393 * step 4 using the snapshot taken before and step 3 ensures that successive
3394 * writes will be logged for the next call.
5bb064dc 3395 */
60c34612 3396int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3397{
7850ac54 3398 int r;
5bb064dc 3399 struct kvm_memory_slot *memslot;
60c34612
TY		 3400 unsigned long n, i;
3401 unsigned long *dirty_bitmap;
3402 unsigned long *dirty_bitmap_buffer;
3403 bool is_dirty = false;
5bb064dc 3404
79fac95e 3405 mutex_lock(&kvm->slots_lock);
5bb064dc 3406
b050b015
MT		 3407 r = -EINVAL;
3408 if (log->slot >= KVM_MEMORY_SLOTS)
3409 goto out;
3410
28a37544 3411 memslot = id_to_memslot(kvm->memslots, log->slot);
60c34612
TY		 3412
3413 dirty_bitmap = memslot->dirty_bitmap;
b050b015 3414 r = -ENOENT;
60c34612 3415 if (!dirty_bitmap)
b050b015
MT		 3416 goto out;
3417
87bf6e7d 3418 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3419
60c34612
TY		 3420 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3421 memset(dirty_bitmap_buffer, 0, n);
b050b015 3422
60c34612 3423 spin_lock(&kvm->mmu_lock);
b050b015 3424
60c34612
TY		 3425 for (i = 0; i < n / sizeof(long); i++) {
3426 unsigned long mask;
3427 gfn_t offset;
cdfca7b3 3428
60c34612
TY		 3429 if (!dirty_bitmap[i])
3430 continue;
b050b015 3431
60c34612 3432 is_dirty = true;
914ebccd 3433
60c34612
TY		 3434 mask = xchg(&dirty_bitmap[i], 0);
3435 dirty_bitmap_buffer[i] = mask;
edde99ce 3436
60c34612
TY		 3437 offset = i * BITS_PER_LONG;
3438 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
5bb064dc 3439 }
60c34612
TY		 3440 if (is_dirty)
3441 kvm_flush_remote_tlbs(kvm);
3442
3443 spin_unlock(&kvm->mmu_lock);
3444
3445 r = -EFAULT;
3446 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3447 goto out;
b050b015 3448
5bb064dc
ZX		 3449 r = 0;
3450out:
79fac95e 3451 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3452 return r;
3453}
3454
23d43cf9
CD		 3455int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event)
3456{
3457 if (!irqchip_in_kernel(kvm))
3458 return -ENXIO;
3459
3460 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3461 irq_event->irq, irq_event->level);
3462 return 0;
3463}
3464
1fe779f8
CO		 3465long kvm_arch_vm_ioctl(struct file *filp,
3466 unsigned int ioctl, unsigned long arg)
3467{
3468 struct kvm *kvm = filp->private_data;
3469 void __user *argp = (void __user *)arg;
367e1319 3470 int r = -ENOTTY;
f0d66275
DH		 3471 /*
3472 * This union makes it completely explicit to gcc-3.x
3473 * that these two variables' stack usage should be
3474 * combined, not added together.
3475 */
3476 union {
3477 struct kvm_pit_state ps;
e9f42757 3478 struct kvm_pit_state2 ps2;
c5ff41ce 3479 struct kvm_pit_config pit_config;
f0d66275 3480 } u;
1fe779f8
CO		 3481
3482 switch (ioctl) {
3483 case KVM_SET_TSS_ADDR:
3484 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3485 break;
b927a3ce
SY		 3486 case KVM_SET_IDENTITY_MAP_ADDR: {
3487 u64 ident_addr;
3488
3489 r = -EFAULT;
3490 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3491 goto out;
3492 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3493 break;
3494 }
1fe779f8
CO		 3495 case KVM_SET_NR_MMU_PAGES:
3496 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3497 break;
3498 case KVM_GET_NR_MMU_PAGES:
3499 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3500 break;
3ddea128
MT		 3501 case KVM_CREATE_IRQCHIP: {
3502 struct kvm_pic *vpic;
3503
3504 mutex_lock(&kvm->lock);
3505 r = -EEXIST;
3506 if (kvm->arch.vpic)
3507 goto create_irqchip_unlock;
3e515705
AK		 3508 r = -EINVAL;
3509 if (atomic_read(&kvm->online_vcpus))
3510 goto create_irqchip_unlock;
1fe779f8 3511 r = -ENOMEM;
3ddea128
MT		 3512 vpic = kvm_create_pic(kvm);
3513 if (vpic) {
1fe779f8
CO		 3514 r = kvm_ioapic_init(kvm);
3515 if (r) {
175504cd 3516 mutex_lock(&kvm->slots_lock);
72bb2fcd 3517 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3518 &vpic->dev_master);
3519 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3520 &vpic->dev_slave);
3521 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3522 &vpic->dev_eclr);
175504cd 3523 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3524 kfree(vpic);
3525 goto create_irqchip_unlock;
1fe779f8
CO		 3526 }
3527 } else
3ddea128
MT		 3528 goto create_irqchip_unlock;
3529 smp_wmb();
3530 kvm->arch.vpic = vpic;
3531 smp_wmb();
399ec807
AK		 3532 r = kvm_setup_default_irq_routing(kvm);
3533 if (r) {
175504cd 3534 mutex_lock(&kvm->slots_lock);
3ddea128 3535 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3536 kvm_ioapic_destroy(kvm);
3537 kvm_destroy_pic(kvm);
3ddea128 3538 mutex_unlock(&kvm->irq_lock);
175504cd 3539 mutex_unlock(&kvm->slots_lock);
399ec807 3540 }
3ddea128
MT		 3541 create_irqchip_unlock:
3542 mutex_unlock(&kvm->lock);
1fe779f8 3543 break;
3ddea128 3544 }
7837699f 3545 case KVM_CREATE_PIT:
c5ff41ce
JK		 3546 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3547 goto create_pit;
3548 case KVM_CREATE_PIT2:
3549 r = -EFAULT;
3550 if (copy_from_user(&u.pit_config, argp,
3551 sizeof(struct kvm_pit_config)))
3552 goto out;
3553 create_pit:
79fac95e 3554 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3555 r = -EEXIST;
3556 if (kvm->arch.vpit)
3557 goto create_pit_unlock;
7837699f 3558 r = -ENOMEM;
c5ff41ce 3559 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3560 if (kvm->arch.vpit)
3561 r = 0;
269e05e4 3562 create_pit_unlock:
79fac95e 3563 mutex_unlock(&kvm->slots_lock);
7837699f 3564 break;
1fe779f8
CO		 3565 case KVM_GET_IRQCHIP: {
3566 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3567 struct kvm_irqchip *chip;
1fe779f8 3568
ff5c2c03
SL		 3569 chip = memdup_user(argp, sizeof(*chip));
3570 if (IS_ERR(chip)) {
3571 r = PTR_ERR(chip);
1fe779f8 3572 goto out;
ff5c2c03
SL		 3573 }
3574
1fe779f8
CO		 3575 r = -ENXIO;
3576 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3577 goto get_irqchip_out;
3578 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3579 if (r)
f0d66275 3580 goto get_irqchip_out;
1fe779f8 3581 r = -EFAULT;
f0d66275
DH		 3582 if (copy_to_user(argp, chip, sizeof *chip))
3583 goto get_irqchip_out;
1fe779f8 3584 r = 0;
f0d66275
DH		 3585 get_irqchip_out:
3586 kfree(chip);
1fe779f8
CO		 3587 break;
3588 }
3589 case KVM_SET_IRQCHIP: {
3590 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3591 struct kvm_irqchip *chip;
1fe779f8 3592
ff5c2c03
SL		 3593 chip = memdup_user(argp, sizeof(*chip));
3594 if (IS_ERR(chip)) {
3595 r = PTR_ERR(chip);
1fe779f8 3596 goto out;
ff5c2c03
SL		 3597 }
3598
1fe779f8
CO		 3599 r = -ENXIO;
3600 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3601 goto set_irqchip_out;
3602 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3603 if (r)
f0d66275 3604 goto set_irqchip_out;
1fe779f8 3605 r = 0;
f0d66275
DH		 3606 set_irqchip_out:
3607 kfree(chip);
1fe779f8
CO		 3608 break;
3609 }
e0f63cb9 3610 case KVM_GET_PIT: {
e0f63cb9 3611 r = -EFAULT;
f0d66275 3612 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3613 goto out;
3614 r = -ENXIO;
3615 if (!kvm->arch.vpit)
3616 goto out;
f0d66275 3617 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3618 if (r)
3619 goto out;
3620 r = -EFAULT;
f0d66275 3621 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3622 goto out;
3623 r = 0;
3624 break;
3625 }
3626 case KVM_SET_PIT: {
e0f63cb9 3627 r = -EFAULT;
f0d66275 3628 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3629 goto out;
3630 r = -ENXIO;
3631 if (!kvm->arch.vpit)
3632 goto out;
f0d66275 3633 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3634 break;
3635 }
e9f42757
BK		 3636 case KVM_GET_PIT2: {
3637 r = -ENXIO;
3638 if (!kvm->arch.vpit)
3639 goto out;
3640 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3641 if (r)
3642 goto out;
3643 r = -EFAULT;
3644 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3645 goto out;
3646 r = 0;
3647 break;
3648 }
3649 case KVM_SET_PIT2: {
3650 r = -EFAULT;
3651 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3652 goto out;
3653 r = -ENXIO;
3654 if (!kvm->arch.vpit)
3655 goto out;
3656 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3657 break;
3658 }
52d939a0
MT		 3659 case KVM_REINJECT_CONTROL: {
3660 struct kvm_reinject_control control;
3661 r = -EFAULT;
3662 if (copy_from_user(&control, argp, sizeof(control)))
3663 goto out;
3664 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3665 break;
3666 }
ffde22ac
ES		 3667 case KVM_XEN_HVM_CONFIG: {
3668 r = -EFAULT;
3669 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3670 sizeof(struct kvm_xen_hvm_config)))
3671 goto out;
3672 r = -EINVAL;
3673 if (kvm->arch.xen_hvm_config.flags)
3674 goto out;
3675 r = 0;
3676 break;
3677 }
afbcf7ab 3678 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3679 struct kvm_clock_data user_ns;
3680 u64 now_ns;
3681 s64 delta;
3682
3683 r = -EFAULT;
3684 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3685 goto out;
3686
3687 r = -EINVAL;
3688 if (user_ns.flags)
3689 goto out;
3690
3691 r = 0;
395c6b0a 3692 local_irq_disable();
759379dd 3693 now_ns = get_kernel_ns();
afbcf7ab 3694 delta = user_ns.clock - now_ns;
395c6b0a 3695 local_irq_enable();
afbcf7ab
GC		 3696 kvm->arch.kvmclock_offset = delta;
3697 break;
3698 }
3699 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3700 struct kvm_clock_data user_ns;
3701 u64 now_ns;
3702
395c6b0a 3703 local_irq_disable();
759379dd 3704 now_ns = get_kernel_ns();
afbcf7ab 3705 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3706 local_irq_enable();
afbcf7ab 3707 user_ns.flags = 0;
97e69aa6 3708 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3709
3710 r = -EFAULT;
3711 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3712 goto out;
3713 r = 0;
3714 break;
3715 }
3716
1fe779f8
CO		 3717 default:
3718 ;
3719 }
3720out:
3721 return r;
3722}
3723
a16b043c 3724static void kvm_init_msr_list(void)
043405e1
CO		 3725{
3726 u32 dummy[2];
3727 unsigned i, j;
3728
e3267cbb
GC		 3729 /* skip the first msrs in the list. KVM-specific */
3730 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3731 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3732 continue;
3733 if (j < i)
3734 msrs_to_save[j] = msrs_to_save[i];
3735 j++;
3736 }
3737 num_msrs_to_save = j;
3738}
3739
bda9020e
MT		 3740static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3741 const void *v)
bbd9b64e 3742{
70252a10
AK		 3743 int handled = 0;
3744 int n;
3745
3746 do {
3747 n = min(len, 8);
3748 if (!(vcpu->arch.apic &&
3749 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3750 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3751 break;
3752 handled += n;
3753 addr += n;
3754 len -= n;
3755 v += n;
3756 } while (len);
bbd9b64e 3757
70252a10 3758 return handled;
bbd9b64e
CO		 3759}
3760
bda9020e 3761static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3762{
70252a10
AK		 3763 int handled = 0;
3764 int n;
3765
3766 do {
3767 n = min(len, 8);
3768 if (!(vcpu->arch.apic &&
3769 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3770 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3771 break;
3772 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3773 handled += n;
3774 addr += n;
3775 len -= n;
3776 v += n;
3777 } while (len);
bbd9b64e 3778
70252a10 3779 return handled;
bbd9b64e
CO		 3780}
3781
2dafc6c2
GN		 3782static void kvm_set_segment(struct kvm_vcpu *vcpu,
3783 struct kvm_segment *var, int seg)
3784{
3785 kvm_x86_ops->set_segment(vcpu, var, seg);
3786}
3787
3788void kvm_get_segment(struct kvm_vcpu *vcpu,
3789 struct kvm_segment *var, int seg)
3790{
3791 kvm_x86_ops->get_segment(vcpu, var, seg);
3792}
3793
e459e322 3794gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
02f59dc9
JR		 3795{
3796 gpa_t t_gpa;
ab9ae313 3797 struct x86_exception exception;
02f59dc9
JR		 3798
3799 BUG_ON(!mmu_is_nested(vcpu));
3800
3801 /* NPT walks are always user-walks */
3802 access |= PFERR_USER_MASK;
ab9ae313 3803 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 3804
3805 return t_gpa;
3806}
3807
ab9ae313
AK		 3808gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3809 struct x86_exception *exception)
1871c602
GN		 3810{
3811 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 3812 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3813}
3814
ab9ae313
AK		 3815 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3816 struct x86_exception *exception)
1871c602
GN		 3817{
3818 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3819 access |= PFERR_FETCH_MASK;
ab9ae313 3820 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3821}
3822
ab9ae313
AK		 3823gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3824 struct x86_exception *exception)
1871c602
GN		 3825{
3826 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3827 access |= PFERR_WRITE_MASK;
ab9ae313 3828 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3829}
3830
3831/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 3832gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3833 struct x86_exception *exception)
1871c602 3834{
ab9ae313 3835 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 3836}
3837
3838static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3839 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 3840 struct x86_exception *exception)
bbd9b64e
CO		 3841{
3842 void *data = val;
10589a46 3843 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3844
3845 while (bytes) {
14dfe855 3846 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 3847 exception);
bbd9b64e 3848 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3849 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3850 int ret;
3851
bcc55cba 3852 if (gpa == UNMAPPED_GVA)
ab9ae313 3853 return X86EMUL_PROPAGATE_FAULT;
77c2002e 3854 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3855 if (ret < 0) {
c3cd7ffa 3856 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3857 goto out;
3858 }
bbd9b64e 3859
77c2002e
IE		 3860 bytes -= toread;
3861 data += toread;
3862 addr += toread;
bbd9b64e 3863 }
10589a46 3864out:
10589a46 3865 return r;
bbd9b64e 3866}
77c2002e 3867
1871c602 3868/* used for instruction fetching */
0f65dd70
AK		 3869static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
3870 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3871 struct x86_exception *exception)
1871c602 3872{
0f65dd70 3873 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3874 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3875
1871c602 3876 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
bcc55cba
AK		 3877 access | PFERR_FETCH_MASK,
3878 exception);
1871c602
GN		 3879}
3880
064aea77 3881int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 3882 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3883 struct x86_exception *exception)
1871c602 3884{
0f65dd70 3885 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3886 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3887
1871c602 3888 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 3889 exception);
1871c602 3890}
064aea77 3891EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 3892
0f65dd70
AK		 3893static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3894 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3895 struct x86_exception *exception)
1871c602 3896{
0f65dd70 3897 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 3898 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 3899}
3900
6a4d7550 3901int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 3902 gva_t addr, void *val,
2dafc6c2 3903 unsigned int bytes,
bcc55cba 3904 struct x86_exception *exception)
77c2002e 3905{
0f65dd70 3906 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 3907 void *data = val;
3908 int r = X86EMUL_CONTINUE;
3909
3910 while (bytes) {
14dfe855
JR		 3911 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3912 PFERR_WRITE_MASK,
ab9ae313 3913 exception);
77c2002e
IE		 3914 unsigned offset = addr & (PAGE_SIZE-1);
3915 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3916 int ret;
3917
bcc55cba 3918 if (gpa == UNMAPPED_GVA)
ab9ae313 3919 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 3920 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3921 if (ret < 0) {
c3cd7ffa 3922 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 3923 goto out;
3924 }
3925
3926 bytes -= towrite;
3927 data += towrite;
3928 addr += towrite;
3929 }
3930out:
3931 return r;
3932}
6a4d7550 3933EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 3934
af7cc7d1
XG		 3935static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
3936 gpa_t *gpa, struct x86_exception *exception,
3937 bool write)
3938{
97d64b78
AK		 3939 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
3940 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 3941
97d64b78
AK		 3942 if (vcpu_match_mmio_gva(vcpu, gva)
3943 && !permission_fault(vcpu->arch.walk_mmu, vcpu->arch.access, access)) {
bebb106a
XG		 3944 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
3945 (gva & (PAGE_SIZE - 1));
4f022648 3946 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 3947 return 1;
3948 }
3949
af7cc7d1
XG		 3950 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3951
3952 if (*gpa == UNMAPPED_GVA)
3953 return -1;
3954
3955 /* For APIC access vmexit */
3956 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3957 return 1;
3958
4f022648
XG		 3959 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
3960 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 3961 return 1;
4f022648 3962 }
bebb106a 3963
af7cc7d1
XG		 3964 return 0;
3965}
3966
3200f405 3967int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 3968 const void *val, int bytes)
bbd9b64e
CO		 3969{
3970 int ret;
3971
3972 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3973 if (ret < 0)
bbd9b64e 3974 return 0;
f57f2ef5 3975 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 3976 return 1;
3977}
3978
77d197b2
XG		 3979struct read_write_emulator_ops {
3980 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
3981 int bytes);
3982 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
3983 void *val, int bytes);
3984 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
3985 int bytes, void *val);
3986 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
3987 void *val, int bytes);
3988 bool write;
3989};
3990
3991static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
3992{
3993 if (vcpu->mmio_read_completed) {
77d197b2 3994 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 3995 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 3996 vcpu->mmio_read_completed = 0;
3997 return 1;
3998 }
3999
4000 return 0;
4001}
4002
4003static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4004 void *val, int bytes)
4005{
4006 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4007}
4008
4009static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4010 void *val, int bytes)
4011{
4012 return emulator_write_phys(vcpu, gpa, val, bytes);
4013}
4014
4015static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4016{
4017 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4018 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4019}
4020
4021static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4022 void *val, int bytes)
4023{
4024 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4025 return X86EMUL_IO_NEEDED;
4026}
4027
4028static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4029 void *val, int bytes)
4030{
f78146b0
AK		 4031 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4032
4033 memcpy(vcpu->run->mmio.data, frag->data, frag->len);
77d197b2
XG		 4034 return X86EMUL_CONTINUE;
4035}
4036
0fbe9b0b 4037static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4038 .read_write_prepare = read_prepare,
4039 .read_write_emulate = read_emulate,
4040 .read_write_mmio = vcpu_mmio_read,
4041 .read_write_exit_mmio = read_exit_mmio,
4042};
4043
0fbe9b0b 4044static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4045 .read_write_emulate = write_emulate,
4046 .read_write_mmio = write_mmio,
4047 .read_write_exit_mmio = write_exit_mmio,
4048 .write = true,
4049};
4050
22388a3c
XG		 4051static int emulator_read_write_onepage(unsigned long addr, void *val,
4052 unsigned int bytes,
4053 struct x86_exception *exception,
4054 struct kvm_vcpu *vcpu,
0fbe9b0b 4055 const struct read_write_emulator_ops *ops)
bbd9b64e 4056{
af7cc7d1
XG		 4057 gpa_t gpa;
4058 int handled, ret;
22388a3c 4059 bool write = ops->write;
f78146b0 4060 struct kvm_mmio_fragment *frag;
10589a46 4061
22388a3c 4062 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4063
af7cc7d1 4064 if (ret < 0)
bbd9b64e 4065 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4066
4067 /* For APIC access vmexit */
af7cc7d1 4068 if (ret)
bbd9b64e
CO		 4069 goto mmio;
4070
22388a3c 4071 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4072 return X86EMUL_CONTINUE;
4073
4074mmio:
4075 /*
4076 * Is this MMIO handled locally?
4077 */
22388a3c 4078 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4079 if (handled == bytes)
bbd9b64e 4080 return X86EMUL_CONTINUE;
bbd9b64e 4081
70252a10
AK		 4082 gpa += handled;
4083 bytes -= handled;
4084 val += handled;
4085
f78146b0
AK		 4086 while (bytes) {
4087 unsigned now = min(bytes, 8U);
bbd9b64e 4088
f78146b0
AK		 4089 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4090 frag->gpa = gpa;
4091 frag->data = val;
4092 frag->len = now;
4093
4094 gpa += now;
4095 val += now;
4096 bytes -= now;
4097 }
4098 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4099}
4100
22388a3c
XG		 4101int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4102 void *val, unsigned int bytes,
4103 struct x86_exception *exception,
0fbe9b0b 4104 const struct read_write_emulator_ops *ops)
bbd9b64e 4105{
0f65dd70 4106 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4107 gpa_t gpa;
4108 int rc;
4109
4110 if (ops->read_write_prepare &&
4111 ops->read_write_prepare(vcpu, val, bytes))
4112 return X86EMUL_CONTINUE;
4113
4114 vcpu->mmio_nr_fragments = 0;
0f65dd70 4115
bbd9b64e
CO		 4116 /* Crossing a page boundary? */
4117 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4118 int now;
bbd9b64e
CO		 4119
4120 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4121 rc = emulator_read_write_onepage(addr, val, now, exception,
4122 vcpu, ops);
4123
bbd9b64e
CO		 4124 if (rc != X86EMUL_CONTINUE)
4125 return rc;
4126 addr += now;
4127 val += now;
4128 bytes -= now;
4129 }
22388a3c 4130
f78146b0
AK		 4131 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4132 vcpu, ops);
4133 if (rc != X86EMUL_CONTINUE)
4134 return rc;
4135
4136 if (!vcpu->mmio_nr_fragments)
4137 return rc;
4138
4139 gpa = vcpu->mmio_fragments[0].gpa;
4140
4141 vcpu->mmio_needed = 1;
4142 vcpu->mmio_cur_fragment = 0;
4143
4144 vcpu->run->mmio.len = vcpu->mmio_fragments[0].len;
4145 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4146 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4147 vcpu->run->mmio.phys_addr = gpa;
4148
4149 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4150}
4151
4152static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4153 unsigned long addr,
4154 void *val,
4155 unsigned int bytes,
4156 struct x86_exception *exception)
4157{
4158 return emulator_read_write(ctxt, addr, val, bytes,
4159 exception, &read_emultor);
4160}
4161
4162int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4163 unsigned long addr,
4164 const void *val,
4165 unsigned int bytes,
4166 struct x86_exception *exception)
4167{
4168 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4169 exception, &write_emultor);
bbd9b64e 4170}
bbd9b64e 4171
daea3e73
AK		 4172#define CMPXCHG_TYPE(t, ptr, old, new) \
4173 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4174
4175#ifdef CONFIG_X86_64
4176# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4177#else
4178# define CMPXCHG64(ptr, old, new) \
9749a6c0 4179 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4180#endif
4181
0f65dd70
AK		 4182static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4183 unsigned long addr,
bbd9b64e
CO		 4184 const void *old,
4185 const void *new,
4186 unsigned int bytes,
0f65dd70 4187 struct x86_exception *exception)
bbd9b64e 4188{
0f65dd70 4189 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4190 gpa_t gpa;
4191 struct page *page;
4192 char *kaddr;
4193 bool exchanged;
2bacc55c 4194
daea3e73
AK		 4195 /* guests cmpxchg8b have to be emulated atomically */
4196 if (bytes > 8 || (bytes & (bytes - 1)))
4197 goto emul_write;
10589a46 4198
daea3e73 4199 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4200
daea3e73
AK		 4201 if (gpa == UNMAPPED_GVA ||
4202 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4203 goto emul_write;
2bacc55c 4204
daea3e73
AK		 4205 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4206 goto emul_write;
72dc67a6 4207
daea3e73 4208 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
32cad84f 4209 if (is_error_page(page))
c19b8bd6 4210 goto emul_write;
72dc67a6 4211
8fd75e12 4212 kaddr = kmap_atomic(page);
daea3e73
AK		 4213 kaddr += offset_in_page(gpa);
4214 switch (bytes) {
4215 case 1:
4216 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4217 break;
4218 case 2:
4219 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4220 break;
4221 case 4:
4222 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4223 break;
4224 case 8:
4225 exchanged = CMPXCHG64(kaddr, old, new);
4226 break;
4227 default:
4228 BUG();
2bacc55c 4229 }
8fd75e12 4230 kunmap_atomic(kaddr);
daea3e73
AK		 4231 kvm_release_page_dirty(page);
4232
4233 if (!exchanged)
4234 return X86EMUL_CMPXCHG_FAILED;
4235
f57f2ef5 4236 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4237
4238 return X86EMUL_CONTINUE;
4a5f48f6 4239
3200f405 4240emul_write:
daea3e73 4241 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4242
0f65dd70 4243 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4244}
4245
cf8f70bf
GN		 4246static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4247{
4248 /* TODO: String I/O for in kernel device */
4249 int r;
4250
4251 if (vcpu->arch.pio.in)
4252 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4253 vcpu->arch.pio.size, pd);
4254 else
4255 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4256 vcpu->arch.pio.port, vcpu->arch.pio.size,
4257 pd);
4258 return r;
4259}
4260
6f6fbe98
XG		 4261static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4262 unsigned short port, void *val,
4263 unsigned int count, bool in)
cf8f70bf 4264{
6f6fbe98 4265 trace_kvm_pio(!in, port, size, count);
cf8f70bf
GN		 4266
4267 vcpu->arch.pio.port = port;
6f6fbe98 4268 vcpu->arch.pio.in = in;
7972995b 4269 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4270 vcpu->arch.pio.size = size;
4271
4272 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4273 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4274 return 1;
4275 }
4276
4277 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4278 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4279 vcpu->run->io.size = size;
4280 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4281 vcpu->run->io.count = count;
4282 vcpu->run->io.port = port;
4283
4284 return 0;
4285}
4286
6f6fbe98
XG		 4287static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4288 int size, unsigned short port, void *val,
4289 unsigned int count)
cf8f70bf 4290{
ca1d4a9e 4291 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4292 int ret;
ca1d4a9e 4293
6f6fbe98
XG		 4294 if (vcpu->arch.pio.count)
4295 goto data_avail;
cf8f70bf 4296
6f6fbe98
XG		 4297 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4298 if (ret) {
4299data_avail:
4300 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 4301 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4302 return 1;
4303 }
4304
cf8f70bf
GN		 4305 return 0;
4306}
4307
6f6fbe98
XG		 4308static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4309 int size, unsigned short port,
4310 const void *val, unsigned int count)
4311{
4312 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4313
4314 memcpy(vcpu->arch.pio_data, val, size * count);
4315 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4316}
4317
bbd9b64e
CO		 4318static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4319{
4320 return kvm_x86_ops->get_segment_base(vcpu, seg);
4321}
4322
3cb16fe7 4323static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4324{
3cb16fe7 4325 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4326}
4327
f5f48ee1
SY		 4328int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4329{
4330 if (!need_emulate_wbinvd(vcpu))
4331 return X86EMUL_CONTINUE;
4332
4333 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4334 int cpu = get_cpu();
4335
4336 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4337 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4338 wbinvd_ipi, NULL, 1);
2eec7343 4339 put_cpu();
f5f48ee1 4340 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4341 } else
4342 wbinvd();
f5f48ee1
SY		 4343 return X86EMUL_CONTINUE;
4344}
4345EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4346
bcaf5cc5
AK		 4347static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4348{
4349 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4350}
4351
717746e3 4352int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4353{
717746e3 4354 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4355}
4356
717746e3 4357int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4358{
338dbc97 4359
717746e3 4360 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4361}
4362
52a46617 4363static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4364{
52a46617 4365 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4366}
4367
717746e3 4368static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4369{
717746e3 4370 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4371 unsigned long value;
4372
4373 switch (cr) {
4374 case 0:
4375 value = kvm_read_cr0(vcpu);
4376 break;
4377 case 2:
4378 value = vcpu->arch.cr2;
4379 break;
4380 case 3:
9f8fe504 4381 value = kvm_read_cr3(vcpu);
52a46617
GN		 4382 break;
4383 case 4:
4384 value = kvm_read_cr4(vcpu);
4385 break;
4386 case 8:
4387 value = kvm_get_cr8(vcpu);
4388 break;
4389 default:
a737f256 4390 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4391 return 0;
4392 }
4393
4394 return value;
4395}
4396
717746e3 4397static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4398{
717746e3 4399 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4400 int res = 0;
4401
52a46617
GN		 4402 switch (cr) {
4403 case 0:
49a9b07e 4404 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4405 break;
4406 case 2:
4407 vcpu->arch.cr2 = val;
4408 break;
4409 case 3:
2390218b 4410 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4411 break;
4412 case 4:
a83b29c6 4413 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4414 break;
4415 case 8:
eea1cff9 4416 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4417 break;
4418 default:
a737f256 4419 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4420 res = -1;
52a46617 4421 }
0f12244f
GN		 4422
4423 return res;
52a46617
GN		 4424}
4425
4cee4798
KW		 4426static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val)
4427{
4428 kvm_set_rflags(emul_to_vcpu(ctxt), val);
4429}
4430
717746e3 4431static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4432{
717746e3 4433 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4434}
4435
4bff1e86 4436static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4437{
4bff1e86 4438 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4439}
4440
4bff1e86 4441static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4442{
4bff1e86 4443 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4444}
4445
1ac9d0cf
AK		 4446static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4447{
4448 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4449}
4450
4451static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4452{
4453 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4454}
4455
4bff1e86
AK		 4456static unsigned long emulator_get_cached_segment_base(
4457 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4458{
4bff1e86 4459 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4460}
4461
1aa36616
AK		 4462static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4463 struct desc_struct *desc, u32 *base3,
4464 int seg)
2dafc6c2
GN		 4465{
4466 struct kvm_segment var;
4467
4bff1e86 4468 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4469 *selector = var.selector;
2dafc6c2
GN		 4470
4471 if (var.unusable)
4472 return false;
4473
4474 if (var.g)
4475 var.limit >>= 12;
4476 set_desc_limit(desc, var.limit);
4477 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4478#ifdef CONFIG_X86_64
4479 if (base3)
4480 *base3 = var.base >> 32;
4481#endif
2dafc6c2
GN		 4482 desc->type = var.type;
4483 desc->s = var.s;
4484 desc->dpl = var.dpl;
4485 desc->p = var.present;
4486 desc->avl = var.avl;
4487 desc->l = var.l;
4488 desc->d = var.db;
4489 desc->g = var.g;
4490
4491 return true;
4492}
4493
1aa36616
AK		 4494static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4495 struct desc_struct *desc, u32 base3,
4496 int seg)
2dafc6c2 4497{
4bff1e86 4498 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4499 struct kvm_segment var;
4500
1aa36616 4501 var.selector = selector;
2dafc6c2 4502 var.base = get_desc_base(desc);
5601d05b
GN		 4503#ifdef CONFIG_X86_64
4504 var.base |= ((u64)base3) << 32;
4505#endif
2dafc6c2
GN		 4506 var.limit = get_desc_limit(desc);
4507 if (desc->g)
4508 var.limit = (var.limit << 12) | 0xfff;
4509 var.type = desc->type;
4510 var.present = desc->p;
4511 var.dpl = desc->dpl;
4512 var.db = desc->d;
4513 var.s = desc->s;
4514 var.l = desc->l;
4515 var.g = desc->g;
4516 var.avl = desc->avl;
4517 var.present = desc->p;
4518 var.unusable = !var.present;
4519 var.padding = 0;
4520
4521 kvm_set_segment(vcpu, &var, seg);
4522 return;
4523}
4524
717746e3
AK		 4525static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4526 u32 msr_index, u64 *pdata)
4527{
4528 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4529}
4530
4531static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4532 u32 msr_index, u64 data)
4533{
4534 return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
4535}
4536
222d21aa
AK		 4537static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4538 u32 pmc, u64 *pdata)
4539{
4540 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4541}
4542
6c3287f7
AK		 4543static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4544{
4545 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4546}
4547
5037f6f3
AK		 4548static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4549{
4550 preempt_disable();
5197b808 4551 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4552 /*
4553 * CR0.TS may reference the host fpu state, not the guest fpu state,
4554 * so it may be clear at this point.
4555 */
4556 clts();
4557}
4558
4559static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4560{
4561 preempt_enable();
4562}
4563
2953538e 4564static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4565 struct x86_instruction_info *info,
c4f035c6
AK		 4566 enum x86_intercept_stage stage)
4567{
2953538e 4568 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4569}
4570
0017f93a 4571static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4572 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4573{
0017f93a 4574 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4575}
4576
dd856efa
AK		 4577static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4578{
4579 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4580}
4581
4582static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4583{
4584 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4585}
4586
0225fb50 4587static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 4588 .read_gpr = emulator_read_gpr,
4589 .write_gpr = emulator_write_gpr,
1871c602 4590 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4591 .write_std = kvm_write_guest_virt_system,
1871c602 4592 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4593 .read_emulated = emulator_read_emulated,
4594 .write_emulated = emulator_write_emulated,
4595 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4596 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4597 .pio_in_emulated = emulator_pio_in_emulated,
4598 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4599 .get_segment = emulator_get_segment,
4600 .set_segment = emulator_set_segment,
5951c442 4601 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4602 .get_gdt = emulator_get_gdt,
160ce1f1 4603 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4604 .set_gdt = emulator_set_gdt,
4605 .set_idt = emulator_set_idt,
52a46617
GN		 4606 .get_cr = emulator_get_cr,
4607 .set_cr = emulator_set_cr,
4cee4798 4608 .set_rflags = emulator_set_rflags,
9c537244 4609 .cpl = emulator_get_cpl,
35aa5375
GN		 4610 .get_dr = emulator_get_dr,
4611 .set_dr = emulator_set_dr,
717746e3
AK		 4612 .set_msr = emulator_set_msr,
4613 .get_msr = emulator_get_msr,
222d21aa 4614 .read_pmc = emulator_read_pmc,
6c3287f7 4615 .halt = emulator_halt,
bcaf5cc5 4616 .wbinvd = emulator_wbinvd,
d6aa1000 4617 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4618 .get_fpu = emulator_get_fpu,
4619 .put_fpu = emulator_put_fpu,
c4f035c6 4620 .intercept = emulator_intercept,
bdb42f5a 4621 .get_cpuid = emulator_get_cpuid,
bbd9b64e
CO		 4622};
4623
95cb2295
GN		 4624static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4625{
4626 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4627 /*
4628 * an sti; sti; sequence only disable interrupts for the first
4629 * instruction. So, if the last instruction, be it emulated or
4630 * not, left the system with the INT_STI flag enabled, it
4631 * means that the last instruction is an sti. We should not
4632 * leave the flag on in this case. The same goes for mov ss
4633 */
4634 if (!(int_shadow & mask))
4635 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4636}
4637
54b8486f
GN		 4638static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4639{
4640 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4641 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4642 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4643 else if (ctxt->exception.error_code_valid)
4644 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4645 ctxt->exception.error_code);
54b8486f 4646 else
da9cb575 4647 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4648}
4649
dd856efa 4650static void init_decode_cache(struct x86_emulate_ctxt *ctxt)
b5c9ff73 4651{
9dac77fa 4652 memset(&ctxt->twobyte, 0,
dd856efa 4653 (void *)&ctxt->_regs - (void *)&ctxt->twobyte);
b5c9ff73 4654
9dac77fa
AK		 4655 ctxt->fetch.start = 0;
4656 ctxt->fetch.end = 0;
4657 ctxt->io_read.pos = 0;
4658 ctxt->io_read.end = 0;
4659 ctxt->mem_read.pos = 0;
4660 ctxt->mem_read.end = 0;
b5c9ff73
TY		 4661}
4662
8ec4722d
MG		 4663static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4664{
adf52235 4665 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4666 int cs_db, cs_l;
4667
8ec4722d
MG		 4668 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4669
adf52235
TY		 4670 ctxt->eflags = kvm_get_rflags(vcpu);
4671 ctxt->eip = kvm_rip_read(vcpu);
4672 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4673 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4674 cs_l ? X86EMUL_MODE_PROT64 :
4675 cs_db ? X86EMUL_MODE_PROT32 :
4676 X86EMUL_MODE_PROT16;
4677 ctxt->guest_mode = is_guest_mode(vcpu);
4678
dd856efa 4679 init_decode_cache(ctxt);
7ae441ea 4680 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4681}
4682
71f9833b 4683int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4684{
9d74191a 4685 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4686 int ret;
4687
4688 init_emulate_ctxt(vcpu);
4689
9dac77fa
AK		 4690 ctxt->op_bytes = 2;
4691 ctxt->ad_bytes = 2;
4692 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4693 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4694
4695 if (ret != X86EMUL_CONTINUE)
4696 return EMULATE_FAIL;
4697
9dac77fa 4698 ctxt->eip = ctxt->_eip;
9d74191a
TY		 4699 kvm_rip_write(vcpu, ctxt->eip);
4700 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4701
4702 if (irq == NMI_VECTOR)
7460fb4a 4703 vcpu->arch.nmi_pending = 0;
63995653
MG		 4704 else
4705 vcpu->arch.interrupt.pending = false;
4706
4707 return EMULATE_DONE;
4708}
4709EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4710
6d77dbfc
GN		 4711static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4712{
fc3a9157
JR		 4713 int r = EMULATE_DONE;
4714
6d77dbfc
GN		 4715 ++vcpu->stat.insn_emulation_fail;
4716 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4717 if (!is_guest_mode(vcpu)) {
4718 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4719 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4720 vcpu->run->internal.ndata = 0;
4721 r = EMULATE_FAIL;
4722 }
6d77dbfc 4723 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4724
4725 return r;
6d77dbfc
GN		 4726}
4727
a6f177ef
GN		 4728static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4729{
4730 gpa_t gpa;
8e3d9d06 4731 pfn_t pfn;
a6f177ef 4732
68be0803
GN		 4733 if (tdp_enabled)
4734 return false;
4735
a6f177ef
GN		 4736 /*
4737 * if emulation was due to access to shadowed page table
4a969980 4738 * and it failed try to unshadow page and re-enter the
a6f177ef
GN		 4739 * guest to let CPU execute the instruction.
4740 */
4741 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4742 return true;
4743
4744 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4745
4746 if (gpa == UNMAPPED_GVA)
4747 return true; /* let cpu generate fault */
4748
8e3d9d06
XG		 4749 /*
4750 * Do not retry the unhandleable instruction if it faults on the
4751 * readonly host memory, otherwise it will goto a infinite loop:
4752 * retry instruction -> write #PF -> emulation fail -> retry
4753 * instruction -> ...
4754 */
4755 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
81c52c56 4756 if (!is_error_noslot_pfn(pfn)) {
8e3d9d06 4757 kvm_release_pfn_clean(pfn);
a6f177ef 4758 return true;
8e3d9d06 4759 }
a6f177ef
GN		 4760
4761 return false;
4762}
4763
1cb3f3ae
XG		 4764static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
4765 unsigned long cr2, int emulation_type)
4766{
4767 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4768 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
4769
4770 last_retry_eip = vcpu->arch.last_retry_eip;
4771 last_retry_addr = vcpu->arch.last_retry_addr;
4772
4773 /*
4774 * If the emulation is caused by #PF and it is non-page_table
4775 * writing instruction, it means the VM-EXIT is caused by shadow
4776 * page protected, we can zap the shadow page and retry this
4777 * instruction directly.
4778 *
4779 * Note: if the guest uses a non-page-table modifying instruction
4780 * on the PDE that points to the instruction, then we will unmap
4781 * the instruction and go to an infinite loop. So, we cache the
4782 * last retried eip and the last fault address, if we meet the eip
4783 * and the address again, we can break out of the potential infinite
4784 * loop.
4785 */
4786 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
4787
4788 if (!(emulation_type & EMULTYPE_RETRY))
4789 return false;
4790
4791 if (x86_page_table_writing_insn(ctxt))
4792 return false;
4793
4794 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
4795 return false;
4796
4797 vcpu->arch.last_retry_eip = ctxt->eip;
4798 vcpu->arch.last_retry_addr = cr2;
4799
4800 if (!vcpu->arch.mmu.direct_map)
4801 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4802
4803 kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4804
4805 return true;
4806}
4807
716d51ab
GN		 4808static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
4809static int complete_emulated_pio(struct kvm_vcpu *vcpu);
4810
51d8b661
AP		 4811int x86_emulate_instruction(struct kvm_vcpu *vcpu,
4812 unsigned long cr2,
dc25e89e
AP		 4813 int emulation_type,
4814 void *insn,
4815 int insn_len)
bbd9b64e 4816{
95cb2295 4817 int r;
9d74191a 4818 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 4819 bool writeback = true;
bbd9b64e 4820
26eef70c 4821 kvm_clear_exception_queue(vcpu);
8d7d8102 4822
571008da 4823 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 4824 init_emulate_ctxt(vcpu);
9d74191a
TY		 4825 ctxt->interruptibility = 0;
4826 ctxt->have_exception = false;
4827 ctxt->perm_ok = false;
bbd9b64e 4828
9d74191a 4829 ctxt->only_vendor_specific_insn
4005996e
AK		 4830 = emulation_type & EMULTYPE_TRAP_UD;
4831
9d74191a 4832 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 4833
e46479f8 4834 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 4835 ++vcpu->stat.insn_emulation;
1d2887e2 4836 if (r != EMULATION_OK) {
4005996e
AK		 4837 if (emulation_type & EMULTYPE_TRAP_UD)
4838 return EMULATE_FAIL;
a6f177ef 4839 if (reexecute_instruction(vcpu, cr2))
bbd9b64e 4840 return EMULATE_DONE;
6d77dbfc
GN		 4841 if (emulation_type & EMULTYPE_SKIP)
4842 return EMULATE_FAIL;
4843 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4844 }
4845 }
4846
ba8afb6b 4847 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 4848 kvm_rip_write(vcpu, ctxt->_eip);
ba8afb6b
GN		 4849 return EMULATE_DONE;
4850 }
4851
1cb3f3ae
XG		 4852 if (retry_instruction(ctxt, cr2, emulation_type))
4853 return EMULATE_DONE;
4854
7ae441ea 4855 /* this is needed for vmware backdoor interface to work since it
4d2179e1 4856 changes registers values during IO operation */
7ae441ea
GN		 4857 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
4858 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 4859 emulator_invalidate_register_cache(ctxt);
7ae441ea 4860 }
4d2179e1 4861
5cd21917 4862restart:
9d74191a 4863 r = x86_emulate_insn(ctxt);
bbd9b64e 4864
775fde86
JR		 4865 if (r == EMULATION_INTERCEPTED)
4866 return EMULATE_DONE;
4867
d2ddd1c4 4868 if (r == EMULATION_FAILED) {
a6f177ef 4869 if (reexecute_instruction(vcpu, cr2))
c3cd7ffa
GN		 4870 return EMULATE_DONE;
4871
6d77dbfc 4872 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4873 }
4874
9d74191a 4875 if (ctxt->have_exception) {
54b8486f 4876 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 4877 r = EMULATE_DONE;
4878 } else if (vcpu->arch.pio.count) {
3457e419
GN		 4879 if (!vcpu->arch.pio.in)
4880 vcpu->arch.pio.count = 0;
716d51ab 4881 else {
7ae441ea 4882 writeback = false;
716d51ab
GN		 4883 vcpu->arch.complete_userspace_io = complete_emulated_pio;
4884 }
e85d28f8 4885 r = EMULATE_DO_MMIO;
7ae441ea
GN		 4886 } else if (vcpu->mmio_needed) {
4887 if (!vcpu->mmio_is_write)
4888 writeback = false;
e85d28f8 4889 r = EMULATE_DO_MMIO;
716d51ab 4890 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 4891 } else if (r == EMULATION_RESTART)
5cd21917 4892 goto restart;
d2ddd1c4
GN		 4893 else
4894 r = EMULATE_DONE;
f850e2e6 4895
7ae441ea 4896 if (writeback) {
9d74191a
TY		 4897 toggle_interruptibility(vcpu, ctxt->interruptibility);
4898 kvm_set_rflags(vcpu, ctxt->eflags);
7ae441ea 4899 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea 4900 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 4901 kvm_rip_write(vcpu, ctxt->eip);
7ae441ea
GN		 4902 } else
4903 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 4904
4905 return r;
de7d789a 4906}
51d8b661 4907EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 4908
cf8f70bf 4909int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 4910{
cf8f70bf 4911 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 4912 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
4913 size, port, &val, 1);
cf8f70bf 4914 /* do not return to emulator after return from userspace */
7972995b 4915 vcpu->arch.pio.count = 0;
de7d789a
CO		 4916 return ret;
4917}
cf8f70bf 4918EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 4919
8cfdc000
ZA		 4920static void tsc_bad(void *info)
4921{
0a3aee0d 4922 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 4923}
4924
4925static void tsc_khz_changed(void *data)
c8076604 4926{
8cfdc000
ZA		 4927 struct cpufreq_freqs *freq = data;
4928 unsigned long khz = 0;
4929
4930 if (data)
4931 khz = freq->new;
4932 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4933 khz = cpufreq_quick_get(raw_smp_processor_id());
4934 if (!khz)
4935 khz = tsc_khz;
0a3aee0d 4936 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 4937}
4938
c8076604
GH		 4939static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4940 void *data)
4941{
4942 struct cpufreq_freqs *freq = data;
4943 struct kvm *kvm;
4944 struct kvm_vcpu *vcpu;
4945 int i, send_ipi = 0;
4946
8cfdc000
ZA		 4947 /*
4948 * We allow guests to temporarily run on slowing clocks,
4949 * provided we notify them after, or to run on accelerating
4950 * clocks, provided we notify them before. Thus time never
4951 * goes backwards.
4952 *
4953 * However, we have a problem. We can't atomically update
4954 * the frequency of a given CPU from this function; it is
4955 * merely a notifier, which can be called from any CPU.
4956 * Changing the TSC frequency at arbitrary points in time
4957 * requires a recomputation of local variables related to
4958 * the TSC for each VCPU. We must flag these local variables
4959 * to be updated and be sure the update takes place with the
4960 * new frequency before any guests proceed.
4961 *
4962 * Unfortunately, the combination of hotplug CPU and frequency
4963 * change creates an intractable locking scenario; the order
4964 * of when these callouts happen is undefined with respect to
4965 * CPU hotplug, and they can race with each other. As such,
4966 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4967 * undefined; you can actually have a CPU frequency change take
4968 * place in between the computation of X and the setting of the
4969 * variable. To protect against this problem, all updates of
4970 * the per_cpu tsc_khz variable are done in an interrupt
4971 * protected IPI, and all callers wishing to update the value
4972 * must wait for a synchronous IPI to complete (which is trivial
4973 * if the caller is on the CPU already). This establishes the
4974 * necessary total order on variable updates.
4975 *
4976 * Note that because a guest time update may take place
4977 * anytime after the setting of the VCPU's request bit, the
4978 * correct TSC value must be set before the request. However,
4979 * to ensure the update actually makes it to any guest which
4980 * starts running in hardware virtualization between the set
4981 * and the acquisition of the spinlock, we must also ping the
4982 * CPU after setting the request bit.
4983 *
4984 */
4985
c8076604
GH		 4986 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4987 return 0;
4988 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4989 return 0;
8cfdc000
ZA		 4990
4991 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 4992
e935b837 4993 raw_spin_lock(&kvm_lock);
c8076604 4994 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 4995 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 4996 if (vcpu->cpu != freq->cpu)
4997 continue;
c285545f 4998 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 4999 if (vcpu->cpu != smp_processor_id())
8cfdc000 5000 send_ipi = 1;
c8076604
GH		 5001 }
5002 }
e935b837 5003 raw_spin_unlock(&kvm_lock);
c8076604
GH		 5004
5005 if (freq->old < freq->new && send_ipi) {
5006 /*
5007 * We upscale the frequency. Must make the guest
5008 * doesn't see old kvmclock values while running with
5009 * the new frequency, otherwise we risk the guest sees
5010 * time go backwards.
5011 *
5012 * In case we update the frequency for another cpu
5013 * (which might be in guest context) send an interrupt
5014 * to kick the cpu out of guest context. Next time
5015 * guest context is entered kvmclock will be updated,
5016 * so the guest will not see stale values.
5017 */
8cfdc000 5018 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5019 }
5020 return 0;
5021}
5022
5023static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5024 .notifier_call = kvmclock_cpufreq_notifier
5025};
5026
5027static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5028 unsigned long action, void *hcpu)
5029{
5030 unsigned int cpu = (unsigned long)hcpu;
5031
5032 switch (action) {
5033 case CPU_ONLINE:
5034 case CPU_DOWN_FAILED:
5035 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5036 break;
5037 case CPU_DOWN_PREPARE:
5038 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5039 break;
5040 }
5041 return NOTIFY_OK;
5042}
5043
5044static struct notifier_block kvmclock_cpu_notifier_block = {
5045 .notifier_call = kvmclock_cpu_notifier,
5046 .priority = -INT_MAX
c8076604
GH		 5047};
5048
b820cc0c
ZA		 5049static void kvm_timer_init(void)
5050{
5051 int cpu;
5052
c285545f 5053 max_tsc_khz = tsc_khz;
8cfdc000 5054 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 5055 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5056#ifdef CONFIG_CPU_FREQ
5057 struct cpufreq_policy policy;
5058 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5059 cpu = get_cpu();
5060 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5061 if (policy.cpuinfo.max_freq)
5062 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5063 put_cpu();
c285545f 5064#endif
b820cc0c
ZA		 5065 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5066 CPUFREQ_TRANSITION_NOTIFIER);
5067 }
c285545f 5068 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5069 for_each_online_cpu(cpu)
5070 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 5071}
5072
ff9d07a0
ZY		 5073static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5074
f5132b01 5075int kvm_is_in_guest(void)
ff9d07a0 5076{
086c9855 5077 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5078}
5079
5080static int kvm_is_user_mode(void)
5081{
5082 int user_mode = 3;
dcf46b94 5083
086c9855
AS		 5084 if (__this_cpu_read(current_vcpu))
5085 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5086
ff9d07a0
ZY		 5087 return user_mode != 0;
5088}
5089
5090static unsigned long kvm_get_guest_ip(void)
5091{
5092 unsigned long ip = 0;
dcf46b94 5093
086c9855
AS		 5094 if (__this_cpu_read(current_vcpu))
5095 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5096
ff9d07a0
ZY		 5097 return ip;
5098}
5099
5100static struct perf_guest_info_callbacks kvm_guest_cbs = {
5101 .is_in_guest = kvm_is_in_guest,
5102 .is_user_mode = kvm_is_user_mode,
5103 .get_guest_ip = kvm_get_guest_ip,
5104};
5105
5106void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5107{
086c9855 5108 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5109}
5110EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5111
5112void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5113{
086c9855 5114 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5115}
5116EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5117
ce88decf
XG		 5118static void kvm_set_mmio_spte_mask(void)
5119{
5120 u64 mask;
5121 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5122
5123 /*
5124 * Set the reserved bits and the present bit of an paging-structure
5125 * entry to generate page fault with PFER.RSV = 1.
5126 */
5127 mask = ((1ull << (62 - maxphyaddr + 1)) - 1) << maxphyaddr;
5128 mask |= 1ull;
5129
5130#ifdef CONFIG_X86_64
5131 /*
5132 * If reserved bit is not supported, clear the present bit to disable
5133 * mmio page fault.
5134 */
5135 if (maxphyaddr == 52)
5136 mask &= ~1ull;
5137#endif
5138
5139 kvm_mmu_set_mmio_spte_mask(mask);
5140}
5141
16e8d74d
MT		 5142#ifdef CONFIG_X86_64
5143static void pvclock_gtod_update_fn(struct work_struct *work)
5144{
d828199e
MT		 5145 struct kvm *kvm;
5146
5147 struct kvm_vcpu *vcpu;
5148 int i;
5149
5150 raw_spin_lock(&kvm_lock);
5151 list_for_each_entry(kvm, &vm_list, vm_list)
5152 kvm_for_each_vcpu(i, vcpu, kvm)
5153 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, &vcpu->requests);
5154 atomic_set(&kvm_guest_has_master_clock, 0);
5155 raw_spin_unlock(&kvm_lock);
16e8d74d
MT		 5156}
5157
5158static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5159
5160/*
5161 * Notification about pvclock gtod data update.
5162 */
5163static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5164 void *priv)
5165{
5166 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5167 struct timekeeper *tk = priv;
5168
5169 update_pvclock_gtod(tk);
5170
5171 /* disable master clock if host does not trust, or does not
5172 * use, TSC clocksource
5173 */
5174 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5175 atomic_read(&kvm_guest_has_master_clock) != 0)
5176 queue_work(system_long_wq, &pvclock_gtod_work);
5177
5178 return 0;
5179}
5180
5181static struct notifier_block pvclock_gtod_notifier = {
5182 .notifier_call = pvclock_gtod_notify,
5183};
5184#endif
5185
f8c16bba 5186int kvm_arch_init(void *opaque)
043405e1 5187{
b820cc0c 5188 int r;
f8c16bba
ZX		 5189 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
5190
f8c16bba
ZX		 5191 if (kvm_x86_ops) {
5192 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5193 r = -EEXIST;
5194 goto out;
f8c16bba
ZX		 5195 }
5196
5197 if (!ops->cpu_has_kvm_support()) {
5198 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5199 r = -EOPNOTSUPP;
5200 goto out;
f8c16bba
ZX		 5201 }
5202 if (ops->disabled_by_bios()) {
5203 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5204 r = -EOPNOTSUPP;
5205 goto out;
f8c16bba
ZX		 5206 }
5207
97db56ce
AK		 5208 r = kvm_mmu_module_init();
5209 if (r)
5210 goto out;
5211
ce88decf 5212 kvm_set_mmio_spte_mask();
97db56ce
AK		 5213 kvm_init_msr_list();
5214
f8c16bba 5215 kvm_x86_ops = ops;
7b52345e 5216 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5217 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5218
b820cc0c 5219 kvm_timer_init();
c8076604 5220
ff9d07a0
ZY		 5221 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5222
2acf923e
DC		 5223 if (cpu_has_xsave)
5224 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5225
c5cc421b 5226 kvm_lapic_init();
16e8d74d
MT		 5227#ifdef CONFIG_X86_64
5228 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5229#endif
5230
f8c16bba 5231 return 0;
56c6d28a
ZX		 5232
5233out:
56c6d28a 5234 return r;
043405e1 5235}
8776e519 5236
f8c16bba
ZX		 5237void kvm_arch_exit(void)
5238{
ff9d07a0
ZY		 5239 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5240
888d256e
JK		 5241 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5242 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5243 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5244 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5245#ifdef CONFIG_X86_64
5246 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5247#endif
f8c16bba 5248 kvm_x86_ops = NULL;
56c6d28a
ZX		 5249 kvm_mmu_module_exit();
5250}
f8c16bba 5251
8776e519
HB		 5252int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5253{
5254 ++vcpu->stat.halt_exits;
5255 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 5256 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5257 return 1;
5258 } else {
5259 vcpu->run->exit_reason = KVM_EXIT_HLT;
5260 return 0;
5261 }
5262}
5263EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5264
55cd8e5a
GN		 5265int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5266{
5267 u64 param, ingpa, outgpa, ret;
5268 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5269 bool fast, longmode;
5270 int cs_db, cs_l;
5271
5272 /*
5273 * hypercall generates UD from non zero cpl and real mode
5274 * per HYPER-V spec
5275 */
3eeb3288 5276 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 5277 kvm_queue_exception(vcpu, UD_VECTOR);
5278 return 0;
5279 }
5280
5281 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5282 longmode = is_long_mode(vcpu) && cs_l == 1;
5283
5284 if (!longmode) {
ccd46936
GN		 5285 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5286 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5287 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5288 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5289 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5290 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 5291 }
5292#ifdef CONFIG_X86_64
5293 else {
5294 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5295 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5296 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5297 }
5298#endif
5299
5300 code = param & 0xffff;
5301 fast = (param >> 16) & 0x1;
5302 rep_cnt = (param >> 32) & 0xfff;
5303 rep_idx = (param >> 48) & 0xfff;
5304
5305 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5306
c25bc163
GN		 5307 switch (code) {
5308 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5309 kvm_vcpu_on_spin(vcpu);
5310 break;
5311 default:
5312 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5313 break;
5314 }
55cd8e5a
GN		 5315
5316 ret = res | (((u64)rep_done & 0xfff) << 32);
5317 if (longmode) {
5318 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5319 } else {
5320 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5321 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5322 }
5323
5324 return 1;
5325}
5326
8776e519
HB		 5327int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5328{
5329 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 5330 int r = 1;
8776e519 5331
55cd8e5a
GN		 5332 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5333 return kvm_hv_hypercall(vcpu);
5334
5fdbf976
MT		 5335 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5336 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5337 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5338 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5339 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5340
229456fc 5341 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5342
8776e519
HB		 5343 if (!is_long_mode(vcpu)) {
5344 nr &= 0xFFFFFFFF;
5345 a0 &= 0xFFFFFFFF;
5346 a1 &= 0xFFFFFFFF;
5347 a2 &= 0xFFFFFFFF;
5348 a3 &= 0xFFFFFFFF;
5349 }
5350
07708c4a
JK		 5351 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5352 ret = -KVM_EPERM;
5353 goto out;
5354 }
5355
8776e519 5356 switch (nr) {
b93463aa
AK		 5357 case KVM_HC_VAPIC_POLL_IRQ:
5358 ret = 0;
5359 break;
8776e519
HB		 5360 default:
5361 ret = -KVM_ENOSYS;
5362 break;
5363 }
07708c4a 5364out:
5fdbf976 5365 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5366 ++vcpu->stat.hypercalls;
2f333bcb 5367 return r;
8776e519
HB		 5368}
5369EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5370
b6785def 5371static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5372{
d6aa1000 5373 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5374 char instruction[3];
5fdbf976 5375 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5376
8776e519
HB		 5377 /*
5378 * Blow out the MMU to ensure that no other VCPU has an active mapping
5379 * to ensure that the updated hypercall appears atomically across all
5380 * VCPUs.
5381 */
5382 kvm_mmu_zap_all(vcpu->kvm);
5383
8776e519 5384 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5385
9d74191a 5386 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5387}
5388
b6c7a5dc
HB		 5389/*
5390 * Check if userspace requested an interrupt window, and that the
5391 * interrupt window is open.
5392 *
5393 * No need to exit to userspace if we already have an interrupt queued.
5394 */
851ba692 5395static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5396{
8061823a 5397 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5398 vcpu->run->request_interrupt_window &&
5df56646 5399 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5400}
5401
851ba692 5402static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5403{
851ba692
AK		 5404 struct kvm_run *kvm_run = vcpu->run;
5405
91586a3b 5406 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5407 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5408 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5409 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5410 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5411 else
b6c7a5dc 5412 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5413 kvm_arch_interrupt_allowed(vcpu) &&
5414 !kvm_cpu_has_interrupt(vcpu) &&
5415 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5416}
5417
4484141a 5418static int vapic_enter(struct kvm_vcpu *vcpu)
b93463aa
AK		 5419{
5420 struct kvm_lapic *apic = vcpu->arch.apic;
5421 struct page *page;
5422
5423 if (!apic || !apic->vapic_addr)
4484141a 5424 return 0;
b93463aa
AK		 5425
5426 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
4484141a
XG		 5427 if (is_error_page(page))
5428 return -EFAULT;
72dc67a6
IE		 5429
5430 vcpu->arch.apic->vapic_page = page;
4484141a 5431 return 0;
b93463aa
AK		 5432}
5433
5434static void vapic_exit(struct kvm_vcpu *vcpu)
5435{
5436 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 5437 int idx;
b93463aa
AK		 5438
5439 if (!apic || !apic->vapic_addr)
5440 return;
5441
f656ce01 5442 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 5443 kvm_release_page_dirty(apic->vapic_page);
5444 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 5445 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 5446}
5447
95ba8273
GN		 5448static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5449{
5450 int max_irr, tpr;
5451
5452 if (!kvm_x86_ops->update_cr8_intercept)
5453 return;
5454
88c808fd
AK		 5455 if (!vcpu->arch.apic)
5456 return;
5457
8db3baa2
GN		 5458 if (!vcpu->arch.apic->vapic_addr)
5459 max_irr = kvm_lapic_find_highest_irr(vcpu);
5460 else
5461 max_irr = -1;
95ba8273
GN		 5462
5463 if (max_irr != -1)
5464 max_irr >>= 4;
5465
5466 tpr = kvm_lapic_get_cr8(vcpu);
5467
5468 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5469}
5470
851ba692 5471static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 5472{
5473 /* try to reinject previous events if any */
b59bb7bd 5474 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5475 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5476 vcpu->arch.exception.has_error_code,
5477 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5478 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5479 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5480 vcpu->arch.exception.error_code,
5481 vcpu->arch.exception.reinject);
b59bb7bd
GN		 5482 return;
5483 }
5484
95ba8273
GN		 5485 if (vcpu->arch.nmi_injected) {
5486 kvm_x86_ops->set_nmi(vcpu);
5487 return;
5488 }
5489
5490 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5491 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5492 return;
5493 }
5494
5495 /* try to inject new event if pending */
5496 if (vcpu->arch.nmi_pending) {
5497 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5498 --vcpu->arch.nmi_pending;
95ba8273
GN		 5499 vcpu->arch.nmi_injected = true;
5500 kvm_x86_ops->set_nmi(vcpu);
5501 }
5502 } else if (kvm_cpu_has_interrupt(vcpu)) {
5503 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5504 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5505 false);
5506 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5507 }
5508 }
5509}
5510
2acf923e
DC		 5511static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5512{
5513 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5514 !vcpu->guest_xcr0_loaded) {
5515 /* kvm_set_xcr() also depends on this */
5516 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5517 vcpu->guest_xcr0_loaded = 1;
5518 }
5519}
5520
5521static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5522{
5523 if (vcpu->guest_xcr0_loaded) {
5524 if (vcpu->arch.xcr0 != host_xcr0)
5525 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5526 vcpu->guest_xcr0_loaded = 0;
5527 }
5528}
5529
7460fb4a
AK		 5530static void process_nmi(struct kvm_vcpu *vcpu)
5531{
5532 unsigned limit = 2;
5533
5534 /*
5535 * x86 is limited to one NMI running, and one NMI pending after it.
5536 * If an NMI is already in progress, limit further NMIs to just one.
5537 * Otherwise, allow two (and we'll inject the first one immediately).
5538 */
5539 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5540 limit = 1;
5541
5542 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5543 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5544 kvm_make_request(KVM_REQ_EVENT, vcpu);
5545}
5546
d828199e
MT		 5547static void kvm_gen_update_masterclock(struct kvm *kvm)
5548{
5549#ifdef CONFIG_X86_64
5550 int i;
5551 struct kvm_vcpu *vcpu;
5552 struct kvm_arch *ka = &kvm->arch;
5553
5554 spin_lock(&ka->pvclock_gtod_sync_lock);
5555 kvm_make_mclock_inprogress_request(kvm);
5556 /* no guest entries from this point */
5557 pvclock_update_vm_gtod_copy(kvm);
5558
5559 kvm_for_each_vcpu(i, vcpu, kvm)
5560 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
5561
5562 /* guest entries allowed */
5563 kvm_for_each_vcpu(i, vcpu, kvm)
5564 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
5565
5566 spin_unlock(&ka->pvclock_gtod_sync_lock);
5567#endif
5568}
5569
851ba692 5570static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5571{
5572 int r;
6a8b1d13 5573 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5574 vcpu->run->request_interrupt_window;
d6185f20 5575 bool req_immediate_exit = 0;
b6c7a5dc 5576
3e007509 5577 if (vcpu->requests) {
a8eeb04a 5578 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5579 kvm_mmu_unload(vcpu);
a8eeb04a 5580 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5581 __kvm_migrate_timers(vcpu);
d828199e
MT		 5582 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
5583 kvm_gen_update_masterclock(vcpu->kvm);
34c238a1
ZA		 5584 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5585 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5586 if (unlikely(r))
5587 goto out;
5588 }
a8eeb04a 5589 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5590 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5591 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5592 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5593 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5594 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5595 r = 0;
5596 goto out;
5597 }
a8eeb04a 5598 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5599 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5600 r = 0;
5601 goto out;
5602 }
a8eeb04a 5603 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5604 vcpu->fpu_active = 0;
5605 kvm_x86_ops->fpu_deactivate(vcpu);
5606 }
af585b92
GN		 5607 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5608 /* Page is swapped out. Do synthetic halt */
5609 vcpu->arch.apf.halted = true;
5610 r = 1;
5611 goto out;
5612 }
c9aaa895
GC		 5613 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5614 record_steal_time(vcpu);
7460fb4a
AK		 5615 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5616 process_nmi(vcpu);
d6185f20
NHE		 5617 req_immediate_exit =
5618 kvm_check_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
f5132b01
GN		 5619 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5620 kvm_handle_pmu_event(vcpu);
5621 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5622 kvm_deliver_pmi(vcpu);
2f52d58c 5623 }
b93463aa 5624
b463a6f7
AK		 5625 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5626 inject_pending_event(vcpu);
5627
5628 /* enable NMI/IRQ window open exits if needed */
7460fb4a 5629 if (vcpu->arch.nmi_pending)
b463a6f7
AK		 5630 kvm_x86_ops->enable_nmi_window(vcpu);
5631 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
5632 kvm_x86_ops->enable_irq_window(vcpu);
5633
5634 if (kvm_lapic_enabled(vcpu)) {
5635 update_cr8_intercept(vcpu);
5636 kvm_lapic_sync_to_vapic(vcpu);
5637 }
5638 }
5639
d8368af8
AK		 5640 r = kvm_mmu_reload(vcpu);
5641 if (unlikely(r)) {
d905c069 5642 goto cancel_injection;
d8368af8
AK		 5643 }
5644
b6c7a5dc
HB		 5645 preempt_disable();
5646
5647 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5648 if (vcpu->fpu_active)
5649 kvm_load_guest_fpu(vcpu);
2acf923e 5650 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5651
6b7e2d09
XG		 5652 vcpu->mode = IN_GUEST_MODE;
5653
5654 /* We should set ->mode before check ->requests,
5655 * see the comment in make_all_cpus_request.
5656 */
5657 smp_mb();
b6c7a5dc 5658
d94e1dc9 5659 local_irq_disable();
32f88400 5660
6b7e2d09 5661 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 5662 || need_resched() || signal_pending(current)) {
6b7e2d09 5663 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5664 smp_wmb();
6c142801
AK		 5665 local_irq_enable();
5666 preempt_enable();
5667 r = 1;
d905c069 5668 goto cancel_injection;
6c142801
AK		 5669 }
5670
f656ce01 5671 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 5672
d6185f20
NHE		 5673 if (req_immediate_exit)
5674 smp_send_reschedule(vcpu->cpu);
5675
b6c7a5dc
HB		 5676 kvm_guest_enter();
5677
42dbaa5a 5678 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5679 set_debugreg(0, 7);
5680 set_debugreg(vcpu->arch.eff_db[0], 0);
5681 set_debugreg(vcpu->arch.eff_db[1], 1);
5682 set_debugreg(vcpu->arch.eff_db[2], 2);
5683 set_debugreg(vcpu->arch.eff_db[3], 3);
5684 }
b6c7a5dc 5685
229456fc 5686 trace_kvm_entry(vcpu->vcpu_id);
851ba692 5687 kvm_x86_ops->run(vcpu);
b6c7a5dc 5688
24f1e32c
FW		 5689 /*
5690 * If the guest has used debug registers, at least dr7
5691 * will be disabled while returning to the host.
5692 * If we don't have active breakpoints in the host, we don't
5693 * care about the messed up debug address registers. But if
5694 * we have some of them active, restore the old state.
5695 */
59d8eb53 5696 if (hw_breakpoint_active())
24f1e32c 5697 hw_breakpoint_restore();
42dbaa5a 5698
886b470c
MT		 5699 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
5700 native_read_tsc());
1d5f066e 5701
6b7e2d09 5702 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5703 smp_wmb();
b6c7a5dc
HB		 5704 local_irq_enable();
5705
5706 ++vcpu->stat.exits;
5707
5708 /*
5709 * We must have an instruction between local_irq_enable() and
5710 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5711 * the interrupt shadow. The stat.exits increment will do nicely.
5712 * But we need to prevent reordering, hence this barrier():
5713 */
5714 barrier();
5715
5716 kvm_guest_exit();
5717
5718 preempt_enable();
5719
f656ce01 5720 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 5721
b6c7a5dc
HB		 5722 /*
5723 * Profile KVM exit RIPs:
5724 */
5725 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 5726 unsigned long rip = kvm_rip_read(vcpu);
5727 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 5728 }
5729
cc578287
ZA		 5730 if (unlikely(vcpu->arch.tsc_always_catchup))
5731 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 5732
5cfb1d5a
MT		 5733 if (vcpu->arch.apic_attention)
5734 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 5735
851ba692 5736 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 5737 return r;
5738
5739cancel_injection:
5740 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 5741 if (unlikely(vcpu->arch.apic_attention))
5742 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 5743out:
5744 return r;
5745}
b6c7a5dc 5746
09cec754 5747
851ba692 5748static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 5749{
5750 int r;
f656ce01 5751 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 5752
5753 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 5754 pr_debug("vcpu %d received sipi with vector # %x\n",
5755 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 5756 kvm_lapic_reset(vcpu);
8b6e4547 5757 r = kvm_vcpu_reset(vcpu);
d7690175
MT		 5758 if (r)
5759 return r;
5760 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 5761 }
5762
f656ce01 5763 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
4484141a
XG		 5764 r = vapic_enter(vcpu);
5765 if (r) {
5766 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5767 return r;
5768 }
d7690175
MT		 5769
5770 r = 1;
5771 while (r > 0) {
af585b92
GN		 5772 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5773 !vcpu->arch.apf.halted)
851ba692 5774 r = vcpu_enter_guest(vcpu);
d7690175 5775 else {
f656ce01 5776 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 5777 kvm_vcpu_block(vcpu);
f656ce01 5778 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
a8eeb04a 5779 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
09cec754
GN		 5780 {
5781 switch(vcpu->arch.mp_state) {
5782 case KVM_MP_STATE_HALTED:
d7690175 5783 vcpu->arch.mp_state =
09cec754
GN		 5784 KVM_MP_STATE_RUNNABLE;
5785 case KVM_MP_STATE_RUNNABLE:
af585b92 5786 vcpu->arch.apf.halted = false;
09cec754
GN		 5787 break;
5788 case KVM_MP_STATE_SIPI_RECEIVED:
5789 default:
5790 r = -EINTR;
5791 break;
5792 }
5793 }
d7690175
MT		 5794 }
5795
09cec754
GN		 5796 if (r <= 0)
5797 break;
5798
5799 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5800 if (kvm_cpu_has_pending_timer(vcpu))
5801 kvm_inject_pending_timer_irqs(vcpu);
5802
851ba692 5803 if (dm_request_for_irq_injection(vcpu)) {
09cec754 5804 r = -EINTR;
851ba692 5805 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5806 ++vcpu->stat.request_irq_exits;
5807 }
af585b92
GN		 5808
5809 kvm_check_async_pf_completion(vcpu);
5810
09cec754
GN		 5811 if (signal_pending(current)) {
5812 r = -EINTR;
851ba692 5813 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5814 ++vcpu->stat.signal_exits;
5815 }
5816 if (need_resched()) {
f656ce01 5817 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 5818 kvm_resched(vcpu);
f656ce01 5819 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 5820 }
b6c7a5dc
HB		 5821 }
5822
f656ce01 5823 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 5824
b93463aa
AK		 5825 vapic_exit(vcpu);
5826
b6c7a5dc
HB		 5827 return r;
5828}
5829
716d51ab
GN		 5830static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
5831{
5832 int r;
5833 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5834 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
5835 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5836 if (r != EMULATE_DONE)
5837 return 0;
5838 return 1;
5839}
5840
5841static int complete_emulated_pio(struct kvm_vcpu *vcpu)
5842{
5843 BUG_ON(!vcpu->arch.pio.count);
5844
5845 return complete_emulated_io(vcpu);
5846}
5847
f78146b0
AK		 5848/*
5849 * Implements the following, as a state machine:
5850 *
5851 * read:
5852 * for each fragment
5853 * write gpa, len
5854 * exit
5855 * copy data
5856 * execute insn
5857 *
5858 * write:
5859 * for each fragment
5860 * write gpa, len
5861 * copy data
5862 * exit
5863 */
716d51ab 5864static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 5865{
5866 struct kvm_run *run = vcpu->run;
f78146b0 5867 struct kvm_mmio_fragment *frag;
5287f194 5868
716d51ab 5869 BUG_ON(!vcpu->mmio_needed);
5287f194 5870
716d51ab
GN		 5871 /* Complete previous fragment */
5872 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment++];
5873 if (!vcpu->mmio_is_write)
5874 memcpy(frag->data, run->mmio.data, frag->len);
5875 if (vcpu->mmio_cur_fragment == vcpu->mmio_nr_fragments) {
5876 vcpu->mmio_needed = 0;
cef4dea0 5877 if (vcpu->mmio_is_write)
716d51ab
GN		 5878 return 1;
5879 vcpu->mmio_read_completed = 1;
5880 return complete_emulated_io(vcpu);
5881 }
5882 /* Initiate next fragment */
5883 ++frag;
5884 run->exit_reason = KVM_EXIT_MMIO;
5885 run->mmio.phys_addr = frag->gpa;
5886 if (vcpu->mmio_is_write)
5887 memcpy(run->mmio.data, frag->data, frag->len);
5888 run->mmio.len = frag->len;
5889 run->mmio.is_write = vcpu->mmio_is_write;
5890 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
5891 return 0;
5287f194
AK		 5892}
5893
716d51ab 5894
b6c7a5dc
HB		 5895int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5896{
5897 int r;
5898 sigset_t sigsaved;
5899
e5c30142
AK		 5900 if (!tsk_used_math(current) && init_fpu(current))
5901 return -ENOMEM;
5902
ac9f6dc0
AK		 5903 if (vcpu->sigset_active)
5904 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5905
a4535290 5906 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 5907 kvm_vcpu_block(vcpu);
d7690175 5908 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 5909 r = -EAGAIN;
5910 goto out;
b6c7a5dc
HB		 5911 }
5912
b6c7a5dc 5913 /* re-sync apic's tpr */
eea1cff9
AP		 5914 if (!irqchip_in_kernel(vcpu->kvm)) {
5915 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
5916 r = -EINVAL;
5917 goto out;
5918 }
5919 }
b6c7a5dc 5920
716d51ab
GN		 5921 if (unlikely(vcpu->arch.complete_userspace_io)) {
5922 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
5923 vcpu->arch.complete_userspace_io = NULL;
5924 r = cui(vcpu);
5925 if (r <= 0)
5926 goto out;
5927 } else
5928 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 5929
851ba692 5930 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 5931
5932out:
f1d86e46 5933 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 5934 if (vcpu->sigset_active)
5935 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5936
b6c7a5dc
HB		 5937 return r;
5938}
5939
5940int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5941{
7ae441ea
GN		 5942 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
5943 /*
5944 * We are here if userspace calls get_regs() in the middle of
5945 * instruction emulation. Registers state needs to be copied
4a969980 5946 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 5947 * that usually, but some bad designed PV devices (vmware
5948 * backdoor interface) need this to work
5949 */
dd856efa 5950 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 5951 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5952 }
5fdbf976
MT		 5953 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5954 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5955 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5956 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5957 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5958 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5959 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5960 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 5961#ifdef CONFIG_X86_64
5fdbf976
MT		 5962 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5963 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5964 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5965 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5966 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5967 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5968 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5969 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 5970#endif
5971
5fdbf976 5972 regs->rip = kvm_rip_read(vcpu);
91586a3b 5973 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 5974
b6c7a5dc
HB		 5975 return 0;
5976}
5977
5978int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5979{
7ae441ea
GN		 5980 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
5981 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5982
5fdbf976
MT		 5983 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
5984 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
5985 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
5986 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
5987 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
5988 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
5989 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
5990 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 5991#ifdef CONFIG_X86_64
5fdbf976
MT		 5992 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
5993 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
5994 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
5995 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
5996 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
5997 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
5998 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
5999 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6000#endif
6001
5fdbf976 6002 kvm_rip_write(vcpu, regs->rip);
91586a3b 6003 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6004
b4f14abd
JK		 6005 vcpu->arch.exception.pending = false;
6006
3842d135
AK		 6007 kvm_make_request(KVM_REQ_EVENT, vcpu);
6008
b6c7a5dc
HB		 6009 return 0;
6010}
6011
b6c7a5dc
HB		 6012void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6013{
6014 struct kvm_segment cs;
6015
3e6e0aab 6016 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6017 *db = cs.db;
6018 *l = cs.l;
6019}
6020EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6021
6022int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6023 struct kvm_sregs *sregs)
6024{
89a27f4d 6025 struct desc_ptr dt;
b6c7a5dc 6026
3e6e0aab
GT		 6027 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6028 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6029 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6030 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6031 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6032 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6033
3e6e0aab
GT		 6034 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6035 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6036
6037 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6038 sregs->idt.limit = dt.size;
6039 sregs->idt.base = dt.address;
b6c7a5dc 6040 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6041 sregs->gdt.limit = dt.size;
6042 sregs->gdt.base = dt.address;
b6c7a5dc 6043
4d4ec087 6044 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6045 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6046 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6047 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6048 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6049 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6050 sregs->apic_base = kvm_get_apic_base(vcpu);
6051
923c61bb 6052 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6053
36752c9b 6054 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6055 set_bit(vcpu->arch.interrupt.nr,
6056 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6057
b6c7a5dc
HB		 6058 return 0;
6059}
6060
62d9f0db
MT		 6061int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6062 struct kvm_mp_state *mp_state)
6063{
62d9f0db 6064 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 6065 return 0;
6066}
6067
6068int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6069 struct kvm_mp_state *mp_state)
6070{
62d9f0db 6071 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6072 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6073 return 0;
6074}
6075
7f3d35fd
KW		 6076int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6077 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6078{
9d74191a 6079 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6080 int ret;
e01c2426 6081
8ec4722d 6082 init_emulate_ctxt(vcpu);
c697518a 6083
7f3d35fd 6084 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6085 has_error_code, error_code);
c697518a 6086
c697518a 6087 if (ret)
19d04437 6088 return EMULATE_FAIL;
37817f29 6089
9d74191a
TY		 6090 kvm_rip_write(vcpu, ctxt->eip);
6091 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6092 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6093 return EMULATE_DONE;
37817f29
IE		 6094}
6095EXPORT_SYMBOL_GPL(kvm_task_switch);
6096
b6c7a5dc
HB		 6097int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6098 struct kvm_sregs *sregs)
6099{
6100 int mmu_reset_needed = 0;
63f42e02 6101 int pending_vec, max_bits, idx;
89a27f4d 6102 struct desc_ptr dt;
b6c7a5dc 6103
89a27f4d
GN		 6104 dt.size = sregs->idt.limit;
6105 dt.address = sregs->idt.base;
b6c7a5dc 6106 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6107 dt.size = sregs->gdt.limit;
6108 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6109 kvm_x86_ops->set_gdt(vcpu, &dt);
6110
ad312c7c 6111 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6112 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6113 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6114 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6115
2d3ad1f4 6116 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6117
f6801dff 6118 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6119 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 6120 kvm_set_apic_base(vcpu, sregs->apic_base);
6121
4d4ec087 6122 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6123 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6124 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6125
fc78f519 6126 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6127 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 6128 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 6129 kvm_update_cpuid(vcpu);
63f42e02
XG		 6130
6131 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6132 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6133 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6134 mmu_reset_needed = 1;
6135 }
63f42e02 6136 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6137
6138 if (mmu_reset_needed)
6139 kvm_mmu_reset_context(vcpu);
6140
a50abc3b 6141 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 6142 pending_vec = find_first_bit(
6143 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6144 if (pending_vec < max_bits) {
66fd3f7f 6145 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 6146 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 6147 }
6148
3e6e0aab
GT		 6149 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6150 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6151 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6152 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6153 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6154 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6155
3e6e0aab
GT		 6156 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6157 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 6158
5f0269f5
ME		 6159 update_cr8_intercept(vcpu);
6160
9c3e4aab 6161 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 6162 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 6163 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 6164 !is_protmode(vcpu))
9c3e4aab
MT		 6165 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6166
3842d135
AK		 6167 kvm_make_request(KVM_REQ_EVENT, vcpu);
6168
b6c7a5dc
HB		 6169 return 0;
6170}
6171
d0bfb940
JK		 6172int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6173 struct kvm_guest_debug *dbg)
b6c7a5dc 6174{
355be0b9 6175 unsigned long rflags;
ae675ef0 6176 int i, r;
b6c7a5dc 6177
4f926bf2
JK		 6178 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6179 r = -EBUSY;
6180 if (vcpu->arch.exception.pending)
2122ff5e 6181 goto out;
4f926bf2
JK		 6182 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6183 kvm_queue_exception(vcpu, DB_VECTOR);
6184 else
6185 kvm_queue_exception(vcpu, BP_VECTOR);
6186 }
6187
91586a3b
JK		 6188 /*
6189 * Read rflags as long as potentially injected trace flags are still
6190 * filtered out.
6191 */
6192 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 6193
6194 vcpu->guest_debug = dbg->control;
6195 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6196 vcpu->guest_debug = 0;
6197
6198 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 6199 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6200 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 6201 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 6202 } else {
6203 for (i = 0; i < KVM_NR_DB_REGS; i++)
6204 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 6205 }
c8639010 6206 kvm_update_dr7(vcpu);
ae675ef0 6207
f92653ee
JK		 6208 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6209 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6210 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 6211
91586a3b
JK		 6212 /*
6213 * Trigger an rflags update that will inject or remove the trace
6214 * flags.
6215 */
6216 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 6217
c8639010 6218 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 6219
4f926bf2 6220 r = 0;
d0bfb940 6221
2122ff5e 6222out:
b6c7a5dc
HB		 6223
6224 return r;
6225}
6226
8b006791
ZX		 6227/*
6228 * Translate a guest virtual address to a guest physical address.
6229 */
6230int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6231 struct kvm_translation *tr)
6232{
6233 unsigned long vaddr = tr->linear_address;
6234 gpa_t gpa;
f656ce01 6235 int idx;
8b006791 6236
f656ce01 6237 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 6238 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 6239 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 6240 tr->physical_address = gpa;
6241 tr->valid = gpa != UNMAPPED_GVA;
6242 tr->writeable = 1;
6243 tr->usermode = 0;
8b006791
ZX		 6244
6245 return 0;
6246}
6247
d0752060
HB		 6248int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6249{
98918833
SY		 6250 struct i387_fxsave_struct *fxsave =
6251 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6252
d0752060
HB		 6253 memcpy(fpu->fpr, fxsave->st_space, 128);
6254 fpu->fcw = fxsave->cwd;
6255 fpu->fsw = fxsave->swd;
6256 fpu->ftwx = fxsave->twd;
6257 fpu->last_opcode = fxsave->fop;
6258 fpu->last_ip = fxsave->rip;
6259 fpu->last_dp = fxsave->rdp;
6260 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6261
d0752060
HB		 6262 return 0;
6263}
6264
6265int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6266{
98918833
SY		 6267 struct i387_fxsave_struct *fxsave =
6268 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6269
d0752060
HB		 6270 memcpy(fxsave->st_space, fpu->fpr, 128);
6271 fxsave->cwd = fpu->fcw;
6272 fxsave->swd = fpu->fsw;
6273 fxsave->twd = fpu->ftwx;
6274 fxsave->fop = fpu->last_opcode;
6275 fxsave->rip = fpu->last_ip;
6276 fxsave->rdp = fpu->last_dp;
6277 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6278
d0752060
HB		 6279 return 0;
6280}
6281
10ab25cd 6282int fx_init(struct kvm_vcpu *vcpu)
d0752060 6283{
10ab25cd
JK		 6284 int err;
6285
6286 err = fpu_alloc(&vcpu->arch.guest_fpu);
6287 if (err)
6288 return err;
6289
98918833 6290 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 6291
2acf923e
DC		 6292 /*
6293 * Ensure guest xcr0 is valid for loading
6294 */
6295 vcpu->arch.xcr0 = XSTATE_FP;
6296
ad312c7c 6297 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 6298
6299 return 0;
d0752060
HB		 6300}
6301EXPORT_SYMBOL_GPL(fx_init);
6302
98918833
SY		 6303static void fx_free(struct kvm_vcpu *vcpu)
6304{
6305 fpu_free(&vcpu->arch.guest_fpu);
6306}
6307
d0752060
HB		 6308void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6309{
2608d7a1 6310 if (vcpu->guest_fpu_loaded)
d0752060
HB		 6311 return;
6312
2acf923e
DC		 6313 /*
6314 * Restore all possible states in the guest,
6315 * and assume host would use all available bits.
6316 * Guest xcr0 would be loaded later.
6317 */
6318 kvm_put_guest_xcr0(vcpu);
d0752060 6319 vcpu->guest_fpu_loaded = 1;
b1a74bf8 6320 __kernel_fpu_begin();
98918833 6321 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 6322 trace_kvm_fpu(1);
d0752060 6323}
d0752060
HB		 6324
6325void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6326{
2acf923e
DC		 6327 kvm_put_guest_xcr0(vcpu);
6328
d0752060
HB		 6329 if (!vcpu->guest_fpu_loaded)
6330 return;
6331
6332 vcpu->guest_fpu_loaded = 0;
98918833 6333 fpu_save_init(&vcpu->arch.guest_fpu);
b1a74bf8 6334 __kernel_fpu_end();
f096ed85 6335 ++vcpu->stat.fpu_reload;
a8eeb04a 6336 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 6337 trace_kvm_fpu(0);
d0752060 6338}
e9b11c17
ZX		 6339
6340void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6341{
12f9a48f 6342 kvmclock_reset(vcpu);
7f1ea208 6343
f5f48ee1 6344 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 6345 fx_free(vcpu);
e9b11c17
ZX		 6346 kvm_x86_ops->vcpu_free(vcpu);
6347}
6348
6349struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6350 unsigned int id)
6351{
6755bae8
ZA		 6352 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6353 printk_once(KERN_WARNING
6354 "kvm: SMP vm created on host with unstable TSC; "
6355 "guest TSC will not be reliable\n");
26e5215f
AK		 6356 return kvm_x86_ops->vcpu_create(kvm, id);
6357}
e9b11c17 6358
26e5215f
AK		 6359int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6360{
6361 int r;
e9b11c17 6362
0bed3b56 6363 vcpu->arch.mtrr_state.have_fixed = 1;
9fc77441
MT		 6364 r = vcpu_load(vcpu);
6365 if (r)
6366 return r;
8b6e4547 6367 r = kvm_vcpu_reset(vcpu);
e9b11c17
ZX		 6368 if (r == 0)
6369 r = kvm_mmu_setup(vcpu);
6370 vcpu_put(vcpu);
e9b11c17 6371
26e5215f 6372 return r;
e9b11c17
ZX		 6373}
6374
42897d86
MT		 6375int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
6376{
6377 int r;
6378
6379 r = vcpu_load(vcpu);
6380 if (r)
6381 return r;
6382 kvm_write_tsc(vcpu, 0);
6383 vcpu_put(vcpu);
6384
6385 return r;
6386}
6387
d40ccc62 6388void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 6389{
9fc77441 6390 int r;
344d9588
GN		 6391 vcpu->arch.apf.msr_val = 0;
6392
9fc77441
MT		 6393 r = vcpu_load(vcpu);
6394 BUG_ON(r);
e9b11c17
ZX		 6395 kvm_mmu_unload(vcpu);
6396 vcpu_put(vcpu);
6397
98918833 6398 fx_free(vcpu);
e9b11c17
ZX		 6399 kvm_x86_ops->vcpu_free(vcpu);
6400}
6401
8b6e4547 6402static int kvm_vcpu_reset(struct kvm_vcpu *vcpu)
e9b11c17 6403{
7460fb4a
AK		 6404 atomic_set(&vcpu->arch.nmi_queued, 0);
6405 vcpu->arch.nmi_pending = 0;
448fa4a9
JK		 6406 vcpu->arch.nmi_injected = false;
6407
42dbaa5a
JK		 6408 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6409 vcpu->arch.dr6 = DR6_FIXED_1;
6410 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 6411 kvm_update_dr7(vcpu);
42dbaa5a 6412
3842d135 6413 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 6414 vcpu->arch.apf.msr_val = 0;
c9aaa895 6415 vcpu->arch.st.msr_val = 0;
3842d135 6416
12f9a48f
GC		 6417 kvmclock_reset(vcpu);
6418
af585b92
GN		 6419 kvm_clear_async_pf_completion_queue(vcpu);
6420 kvm_async_pf_hash_reset(vcpu);
6421 vcpu->arch.apf.halted = false;
3842d135 6422
f5132b01
GN		 6423 kvm_pmu_reset(vcpu);
6424
e9b11c17
ZX		 6425 return kvm_x86_ops->vcpu_reset(vcpu);
6426}
6427
10474ae8 6428int kvm_arch_hardware_enable(void *garbage)
e9b11c17 6429{
ca84d1a2
ZA		 6430 struct kvm *kvm;
6431 struct kvm_vcpu *vcpu;
6432 int i;
0dd6a6ed
ZA		 6433 int ret;
6434 u64 local_tsc;
6435 u64 max_tsc = 0;
6436 bool stable, backwards_tsc = false;
18863bdd
AK		 6437
6438 kvm_shared_msr_cpu_online();
0dd6a6ed
ZA		 6439 ret = kvm_x86_ops->hardware_enable(garbage);
6440 if (ret != 0)
6441 return ret;
6442
6443 local_tsc = native_read_tsc();
6444 stable = !check_tsc_unstable();
6445 list_for_each_entry(kvm, &vm_list, vm_list) {
6446 kvm_for_each_vcpu(i, vcpu, kvm) {
6447 if (!stable && vcpu->cpu == smp_processor_id())
6448 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6449 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6450 backwards_tsc = true;
6451 if (vcpu->arch.last_host_tsc > max_tsc)
6452 max_tsc = vcpu->arch.last_host_tsc;
6453 }
6454 }
6455 }
6456
6457 /*
6458 * Sometimes, even reliable TSCs go backwards. This happens on
6459 * platforms that reset TSC during suspend or hibernate actions, but
6460 * maintain synchronization. We must compensate. Fortunately, we can
6461 * detect that condition here, which happens early in CPU bringup,
6462 * before any KVM threads can be running. Unfortunately, we can't
6463 * bring the TSCs fully up to date with real time, as we aren't yet far
6464 * enough into CPU bringup that we know how much real time has actually
6465 * elapsed; our helper function, get_kernel_ns() will be using boot
6466 * variables that haven't been updated yet.
6467 *
6468 * So we simply find the maximum observed TSC above, then record the
6469 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6470 * the adjustment will be applied. Note that we accumulate
6471 * adjustments, in case multiple suspend cycles happen before some VCPU
6472 * gets a chance to run again. In the event that no KVM threads get a
6473 * chance to run, we will miss the entire elapsed period, as we'll have
6474 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6475 * loose cycle time. This isn't too big a deal, since the loss will be
6476 * uniform across all VCPUs (not to mention the scenario is extremely
6477 * unlikely). It is possible that a second hibernate recovery happens
6478 * much faster than a first, causing the observed TSC here to be
6479 * smaller; this would require additional padding adjustment, which is
6480 * why we set last_host_tsc to the local tsc observed here.
6481 *
6482 * N.B. - this code below runs only on platforms with reliable TSC,
6483 * as that is the only way backwards_tsc is set above. Also note
6484 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6485 * have the same delta_cyc adjustment applied if backwards_tsc
6486 * is detected. Note further, this adjustment is only done once,
6487 * as we reset last_host_tsc on all VCPUs to stop this from being
6488 * called multiple times (one for each physical CPU bringup).
6489 *
4a969980 6490 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 6491 * will be compensated by the logic in vcpu_load, which sets the TSC to
6492 * catchup mode. This will catchup all VCPUs to real time, but cannot
6493 * guarantee that they stay in perfect synchronization.
6494 */
6495 if (backwards_tsc) {
6496 u64 delta_cyc = max_tsc - local_tsc;
6497 list_for_each_entry(kvm, &vm_list, vm_list) {
6498 kvm_for_each_vcpu(i, vcpu, kvm) {
6499 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6500 vcpu->arch.last_host_tsc = local_tsc;
d828199e
MT		 6501 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
6502 &vcpu->requests);
0dd6a6ed
ZA		 6503 }
6504
6505 /*
6506 * We have to disable TSC offset matching.. if you were
6507 * booting a VM while issuing an S4 host suspend....
6508 * you may have some problem. Solving this issue is
6509 * left as an exercise to the reader.
6510 */
6511 kvm->arch.last_tsc_nsec = 0;
6512 kvm->arch.last_tsc_write = 0;
6513 }
6514
6515 }
6516 return 0;
e9b11c17
ZX		 6517}
6518
6519void kvm_arch_hardware_disable(void *garbage)
6520{
6521 kvm_x86_ops->hardware_disable(garbage);
3548bab5 6522 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 6523}
6524
6525int kvm_arch_hardware_setup(void)
6526{
6527 return kvm_x86_ops->hardware_setup();
6528}
6529
6530void kvm_arch_hardware_unsetup(void)
6531{
6532 kvm_x86_ops->hardware_unsetup();
6533}
6534
6535void kvm_arch_check_processor_compat(void *rtn)
6536{
6537 kvm_x86_ops->check_processor_compatibility(rtn);
6538}
6539
3e515705
AK		 6540bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
6541{
6542 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
6543}
6544
54e9818f
GN		 6545struct static_key kvm_no_apic_vcpu __read_mostly;
6546
e9b11c17
ZX		 6547int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6548{
6549 struct page *page;
6550 struct kvm *kvm;
6551 int r;
6552
6553 BUG_ON(vcpu->kvm == NULL);
6554 kvm = vcpu->kvm;
6555
9aabc88f 6556 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
c5af89b6 6557 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 6558 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 6559 else
a4535290 6560 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 6561
6562 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6563 if (!page) {
6564 r = -ENOMEM;
6565 goto fail;
6566 }
ad312c7c 6567 vcpu->arch.pio_data = page_address(page);
e9b11c17 6568
cc578287 6569 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 6570
e9b11c17
ZX		 6571 r = kvm_mmu_create(vcpu);
6572 if (r < 0)
6573 goto fail_free_pio_data;
6574
6575 if (irqchip_in_kernel(kvm)) {
6576 r = kvm_create_lapic(vcpu);
6577 if (r < 0)
6578 goto fail_mmu_destroy;
54e9818f
GN		 6579 } else
6580 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 6581
890ca9ae
HY		 6582 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6583 GFP_KERNEL);
6584 if (!vcpu->arch.mce_banks) {
6585 r = -ENOMEM;
443c39bc 6586 goto fail_free_lapic;
890ca9ae
HY		 6587 }
6588 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6589
f5f48ee1
SY		 6590 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
6591 goto fail_free_mce_banks;
6592
af585b92 6593 kvm_async_pf_hash_reset(vcpu);
f5132b01 6594 kvm_pmu_init(vcpu);
af585b92 6595
e9b11c17 6596 return 0;
f5f48ee1
SY		 6597fail_free_mce_banks:
6598 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 6599fail_free_lapic:
6600 kvm_free_lapic(vcpu);
e9b11c17
ZX		 6601fail_mmu_destroy:
6602 kvm_mmu_destroy(vcpu);
6603fail_free_pio_data:
ad312c7c 6604 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 6605fail:
6606 return r;
6607}
6608
6609void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6610{
f656ce01
MT		 6611 int idx;
6612
f5132b01 6613 kvm_pmu_destroy(vcpu);
36cb93fd 6614 kfree(vcpu->arch.mce_banks);
e9b11c17 6615 kvm_free_lapic(vcpu);
f656ce01 6616 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 6617 kvm_mmu_destroy(vcpu);
f656ce01 6618 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 6619 free_page((unsigned long)vcpu->arch.pio_data);
54e9818f
GN		 6620 if (!irqchip_in_kernel(vcpu->kvm))
6621 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 6622}
d19a9cd2 6623
e08b9637 6624int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 6625{
e08b9637
CO		 6626 if (type)
6627 return -EINVAL;
6628
f05e70ac 6629 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 6630 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 6631
5550af4d
SY		 6632 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
6633 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 6634 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
6635 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
6636 &kvm->arch.irq_sources_bitmap);
5550af4d 6637
038f8c11 6638 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 6639 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 6640 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
6641
6642 pvclock_update_vm_gtod_copy(kvm);
53f658b3 6643
d89f5eff 6644 return 0;
d19a9cd2
ZX		 6645}
6646
6647static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
6648{
9fc77441
MT		 6649 int r;
6650 r = vcpu_load(vcpu);
6651 BUG_ON(r);
d19a9cd2
ZX		 6652 kvm_mmu_unload(vcpu);
6653 vcpu_put(vcpu);
6654}
6655
6656static void kvm_free_vcpus(struct kvm *kvm)
6657{
6658 unsigned int i;
988a2cae 6659 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 6660
6661 /*
6662 * Unpin any mmu pages first.
6663 */
af585b92
GN		 6664 kvm_for_each_vcpu(i, vcpu, kvm) {
6665 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 6666 kvm_unload_vcpu_mmu(vcpu);
af585b92 6667 }
988a2cae
GN		 6668 kvm_for_each_vcpu(i, vcpu, kvm)
6669 kvm_arch_vcpu_free(vcpu);
6670
6671 mutex_lock(&kvm->lock);
6672 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6673 kvm->vcpus[i] = NULL;
d19a9cd2 6674
988a2cae
GN		 6675 atomic_set(&kvm->online_vcpus, 0);
6676 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 6677}
6678
ad8ba2cd
SY		 6679void kvm_arch_sync_events(struct kvm *kvm)
6680{
ba4cef31 6681 kvm_free_all_assigned_devices(kvm);
aea924f6 6682 kvm_free_pit(kvm);
ad8ba2cd
SY		 6683}
6684
d19a9cd2
ZX		 6685void kvm_arch_destroy_vm(struct kvm *kvm)
6686{
6eb55818 6687 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 6688 kfree(kvm->arch.vpic);
6689 kfree(kvm->arch.vioapic);
d19a9cd2 6690 kvm_free_vcpus(kvm);
3d45830c
AK		 6691 if (kvm->arch.apic_access_page)
6692 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 6693 if (kvm->arch.ept_identity_pagetable)
6694 put_page(kvm->arch.ept_identity_pagetable);
1e08ec4a 6695 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 6696}
0de10343 6697
db3fe4eb
TY		 6698void kvm_arch_free_memslot(struct kvm_memory_slot *free,
6699 struct kvm_memory_slot *dont)
6700{
6701 int i;
6702
d89cc617
TY		 6703 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
6704 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
6705 kvm_kvfree(free->arch.rmap[i]);
6706 free->arch.rmap[i] = NULL;
77d11309 6707 }
d89cc617
TY		 6708 if (i == 0)
6709 continue;
6710
6711 if (!dont || free->arch.lpage_info[i - 1] !=
6712 dont->arch.lpage_info[i - 1]) {
6713 kvm_kvfree(free->arch.lpage_info[i - 1]);
6714 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 6715 }
6716 }
6717}
6718
6719int kvm_arch_create_memslot(struct kvm_memory_slot *slot, unsigned long npages)
6720{
6721 int i;
6722
d89cc617 6723 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 6724 unsigned long ugfn;
6725 int lpages;
d89cc617 6726 int level = i + 1;
db3fe4eb
TY		 6727
6728 lpages = gfn_to_index(slot->base_gfn + npages - 1,
6729 slot->base_gfn, level) + 1;
6730
d89cc617
TY		 6731 slot->arch.rmap[i] =
6732 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
6733 if (!slot->arch.rmap[i])
77d11309 6734 goto out_free;
d89cc617
TY		 6735 if (i == 0)
6736 continue;
77d11309 6737
d89cc617
TY		 6738 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
6739 sizeof(*slot->arch.lpage_info[i - 1]));
6740 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 6741 goto out_free;
6742
6743 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 6744 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 6745 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 6746 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 6747 ugfn = slot->userspace_addr >> PAGE_SHIFT;
6748 /*
6749 * If the gfn and userspace address are not aligned wrt each
6750 * other, or if explicitly asked to, disable large page
6751 * support for this slot
6752 */
6753 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
6754 !kvm_largepages_enabled()) {
6755 unsigned long j;
6756
6757 for (j = 0; j < lpages; ++j)
d89cc617 6758 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 6759 }
6760 }
6761
6762 return 0;
6763
6764out_free:
d89cc617
TY		 6765 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
6766 kvm_kvfree(slot->arch.rmap[i]);
6767 slot->arch.rmap[i] = NULL;
6768 if (i == 0)
6769 continue;
6770
6771 kvm_kvfree(slot->arch.lpage_info[i - 1]);
6772 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 6773 }
6774 return -ENOMEM;
6775}
6776
f7784b8e
MT		 6777int kvm_arch_prepare_memory_region(struct kvm *kvm,
6778 struct kvm_memory_slot *memslot,
0de10343 6779 struct kvm_memory_slot old,
f7784b8e 6780 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 6781 int user_alloc)
6782{
f7784b8e 6783 int npages = memslot->npages;
7ac77099
AK		 6784 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
6785
6786 /* Prevent internal slot pages from being moved by fork()/COW. */
6787 if (memslot->id >= KVM_MEMORY_SLOTS)
6788 map_flags = MAP_SHARED | MAP_ANONYMOUS;
0de10343
ZX		 6789
6790 /*To keep backward compatibility with older userspace,
4a969980 6791 *x86 needs to handle !user_alloc case.
0de10343
ZX		 6792 */
6793 if (!user_alloc) {
aab2eb7a 6794 if (npages && !old.npages) {
604b38ac
AA		 6795 unsigned long userspace_addr;
6796
6be5ceb0 6797 userspace_addr = vm_mmap(NULL, 0,
604b38ac
AA		 6798 npages * PAGE_SIZE,
6799 PROT_READ | PROT_WRITE,
7ac77099 6800 map_flags,
604b38ac 6801 0);
0de10343 6802
604b38ac
AA		 6803 if (IS_ERR((void *)userspace_addr))
6804 return PTR_ERR((void *)userspace_addr);
6805
604b38ac 6806 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 6807 }
6808 }
6809
f7784b8e
MT		 6810
6811 return 0;
6812}
6813
6814void kvm_arch_commit_memory_region(struct kvm *kvm,
6815 struct kvm_userspace_memory_region *mem,
6816 struct kvm_memory_slot old,
6817 int user_alloc)
6818{
6819
48c0e4e9 6820 int nr_mmu_pages = 0, npages = mem->memory_size >> PAGE_SHIFT;
f7784b8e 6821
aab2eb7a 6822 if (!user_alloc && !old.user_alloc && old.npages && !npages) {
f7784b8e
MT		 6823 int ret;
6824
bfce281c 6825 ret = vm_munmap(old.userspace_addr,
f7784b8e 6826 old.npages * PAGE_SIZE);
f7784b8e
MT		 6827 if (ret < 0)
6828 printk(KERN_WARNING
6829 "kvm_vm_ioctl_set_memory_region: "
6830 "failed to munmap memory\n");
6831 }
6832
48c0e4e9
XG		 6833 if (!kvm->arch.n_requested_mmu_pages)
6834 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
6835
7c8a83b7 6836 spin_lock(&kvm->mmu_lock);
48c0e4e9 6837 if (nr_mmu_pages)
0de10343 6838 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
0de10343 6839 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 6840 spin_unlock(&kvm->mmu_lock);
3b4dc3a0
MT		 6841 /*
6842 * If memory slot is created, or moved, we need to clear all
6843 * mmio sptes.
6844 */
6845 if (npages && old.base_gfn != mem->guest_phys_addr >> PAGE_SHIFT) {
6846 kvm_mmu_zap_all(kvm);
6847 kvm_reload_remote_mmus(kvm);
6848 }
0de10343 6849}
1d737c8a 6850
2df72e9b 6851void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f
MT		 6852{
6853 kvm_mmu_zap_all(kvm);
8986ecc0 6854 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 6855}
6856
2df72e9b
MT		 6857void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
6858 struct kvm_memory_slot *slot)
6859{
6860 kvm_arch_flush_shadow_all(kvm);
6861}
6862
1d737c8a
ZX		 6863int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
6864{
af585b92
GN		 6865 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6866 !vcpu->arch.apf.halted)
6867 || !list_empty_careful(&vcpu->async_pf.done)
a1b37100 6868 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
7460fb4a 6869 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 6870 (kvm_arch_interrupt_allowed(vcpu) &&
6871 kvm_cpu_has_interrupt(vcpu));
1d737c8a 6872}
5736199a 6873
b6d33834 6874int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 6875{
b6d33834 6876 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 6877}
78646121
GN		 6878
6879int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
6880{
6881 return kvm_x86_ops->interrupt_allowed(vcpu);
6882}
229456fc 6883
f92653ee
JK		 6884bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
6885{
6886 unsigned long current_rip = kvm_rip_read(vcpu) +
6887 get_segment_base(vcpu, VCPU_SREG_CS);
6888
6889 return current_rip == linear_rip;
6890}
6891EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
6892
94fe45da
JK		 6893unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
6894{
6895 unsigned long rflags;
6896
6897 rflags = kvm_x86_ops->get_rflags(vcpu);
6898 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 6899 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 6900 return rflags;
6901}
6902EXPORT_SYMBOL_GPL(kvm_get_rflags);
6903
6904void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6905{
6906 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 6907 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 6908 rflags |= X86_EFLAGS_TF;
94fe45da 6909 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 6910 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 6911}
6912EXPORT_SYMBOL_GPL(kvm_set_rflags);
6913
56028d08
GN		 6914void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
6915{
6916 int r;
6917
fb67e14f 6918 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
c4806acd 6919 is_error_page(work->page))
56028d08
GN		 6920 return;
6921
6922 r = kvm_mmu_reload(vcpu);
6923 if (unlikely(r))
6924 return;
6925
fb67e14f
XG		 6926 if (!vcpu->arch.mmu.direct_map &&
6927 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
6928 return;
6929
56028d08
GN		 6930 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
6931}
6932
af585b92
GN		 6933static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
6934{
6935 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
6936}
6937
6938static inline u32 kvm_async_pf_next_probe(u32 key)
6939{
6940 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
6941}
6942
6943static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6944{
6945 u32 key = kvm_async_pf_hash_fn(gfn);
6946
6947 while (vcpu->arch.apf.gfns[key] != ~0)
6948 key = kvm_async_pf_next_probe(key);
6949
6950 vcpu->arch.apf.gfns[key] = gfn;
6951}
6952
6953static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
6954{
6955 int i;
6956 u32 key = kvm_async_pf_hash_fn(gfn);
6957
6958 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 6959 (vcpu->arch.apf.gfns[key] != gfn &&
6960 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 6961 key = kvm_async_pf_next_probe(key);
6962
6963 return key;
6964}
6965
6966bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6967{
6968 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
6969}
6970
6971static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6972{
6973 u32 i, j, k;
6974
6975 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
6976 while (true) {
6977 vcpu->arch.apf.gfns[i] = ~0;
6978 do {
6979 j = kvm_async_pf_next_probe(j);
6980 if (vcpu->arch.apf.gfns[j] == ~0)
6981 return;
6982 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
6983 /*
6984 * k lies cyclically in ]i,j]
6985 * | i.k.j |
6986 * |....j i.k.| or |.k..j i...|
6987 */
6988 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
6989 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
6990 i = j;
6991 }
6992}
6993
7c90705b
GN		 6994static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
6995{
6996
6997 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
6998 sizeof(val));
6999}
7000
af585b92
GN		 7001void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7002 struct kvm_async_pf *work)
7003{
6389ee94
AK		 7004 struct x86_exception fault;
7005
7c90705b 7006 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 7007 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 7008
7009 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 7010 (vcpu->arch.apf.send_user_only &&
7011 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 7012 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7013 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 7014 fault.vector = PF_VECTOR;
7015 fault.error_code_valid = true;
7016 fault.error_code = 0;
7017 fault.nested_page_fault = false;
7018 fault.address = work->arch.token;
7019 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7020 }
af585b92
GN		 7021}
7022
7023void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7024 struct kvm_async_pf *work)
7025{
6389ee94
AK		 7026 struct x86_exception fault;
7027
7c90705b
GN		 7028 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7029 if (is_error_page(work->page))
7030 work->arch.token = ~0; /* broadcast wakeup */
7031 else
7032 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7033
7034 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7035 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 7036 fault.vector = PF_VECTOR;
7037 fault.error_code_valid = true;
7038 fault.error_code = 0;
7039 fault.nested_page_fault = false;
7040 fault.address = work->arch.token;
7041 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7042 }
e6d53e3b 7043 vcpu->arch.apf.halted = false;
a4fa1635 7044 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 7045}
7046
7047bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7048{
7049 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7050 return true;
7051 else
7052 return !kvm_event_needs_reinjection(vcpu) &&
7053 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 7054}
7055
229456fc
MT		 7056EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7057EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7058EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7059EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7060EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 7061EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 7062EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 7063EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 7064EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 7065EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 7066EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 7067EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
Linux kernel - Deliverables
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