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KVM: use SRCU for dirty log
[deliverable/linux.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
043405e1
CO		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 13 * Amit Shah <amit.shah@qumranet.com>
14 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
edf88417 21#include <linux/kvm_host.h>
313a3dc7 22#include "irq.h"
1d737c8a 23#include "mmu.h"
7837699f 24#include "i8254.h"
37817f29 25#include "tss.h"
5fdbf976 26#include "kvm_cache_regs.h"
26eef70c 27#include "x86.h"
313a3dc7 28
18068523 29#include <linux/clocksource.h>
4d5c5d0f 30#include <linux/interrupt.h>
313a3dc7
CO		 31#include <linux/kvm.h>
32#include <linux/fs.h>
33#include <linux/vmalloc.h>
5fb76f9b 34#include <linux/module.h>
0de10343 35#include <linux/mman.h>
2bacc55c 36#include <linux/highmem.h>
19de40a8 37#include <linux/iommu.h>
62c476c7 38#include <linux/intel-iommu.h>
c8076604 39#include <linux/cpufreq.h>
18863bdd 40#include <linux/user-return-notifier.h>
aec51dc4
AK		 41#include <trace/events/kvm.h>
42#undef TRACE_INCLUDE_FILE
229456fc
MT		 43#define CREATE_TRACE_POINTS
44#include "trace.h"
043405e1 45
24f1e32c 46#include <asm/debugreg.h>
043405e1 47#include <asm/uaccess.h>
d825ed0a 48#include <asm/msr.h>
a5f61300 49#include <asm/desc.h>
0bed3b56 50#include <asm/mtrr.h>
890ca9ae 51#include <asm/mce.h>
043405e1 52
313a3dc7 53#define MAX_IO_MSRS 256
a03490ed
CO		 54#define CR0_RESERVED_BITS \
55 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
56 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
57 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
58#define CR4_RESERVED_BITS \
59 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
60 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
61 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
62 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
63
64#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
890ca9ae
HY		 65
66#define KVM_MAX_MCE_BANKS 32
67#define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
68
50a37eb4
JR		 69/* EFER defaults:
70 * - enable syscall per default because its emulated by KVM
71 * - enable LME and LMA per default on 64 bit KVM
72 */
73#ifdef CONFIG_X86_64
74static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
75#else
76static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
77#endif
313a3dc7 78
ba1389b7
AK		 79#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
80#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 81
cb142eb7 82static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 83static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
84 struct kvm_cpuid_entry2 __user *entries);
85
97896d04 86struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 87EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 88
ed85c068
AP		 89int ignore_msrs = 0;
90module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
91
18863bdd
AK		 92#define KVM_NR_SHARED_MSRS 16
93
94struct kvm_shared_msrs_global {
95 int nr;
2bf78fa7 96 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 97};
98
99struct kvm_shared_msrs {
100 struct user_return_notifier urn;
101 bool registered;
2bf78fa7
SY		 102 struct kvm_shared_msr_values {
103 u64 host;
104 u64 curr;
105 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 106};
107
108static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
109static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
110
417bc304 111struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 112 { "pf_fixed", VCPU_STAT(pf_fixed) },
113 { "pf_guest", VCPU_STAT(pf_guest) },
114 { "tlb_flush", VCPU_STAT(tlb_flush) },
115 { "invlpg", VCPU_STAT(invlpg) },
116 { "exits", VCPU_STAT(exits) },
117 { "io_exits", VCPU_STAT(io_exits) },
118 { "mmio_exits", VCPU_STAT(mmio_exits) },
119 { "signal_exits", VCPU_STAT(signal_exits) },
120 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 121 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 122 { "halt_exits", VCPU_STAT(halt_exits) },
123 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 124 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 125 { "request_irq", VCPU_STAT(request_irq_exits) },
126 { "irq_exits", VCPU_STAT(irq_exits) },
127 { "host_state_reload", VCPU_STAT(host_state_reload) },
128 { "efer_reload", VCPU_STAT(efer_reload) },
129 { "fpu_reload", VCPU_STAT(fpu_reload) },
130 { "insn_emulation", VCPU_STAT(insn_emulation) },
131 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 132 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 133 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 134 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
135 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
136 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
137 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
138 { "mmu_flooded", VM_STAT(mmu_flooded) },
139 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 140 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 141 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 142 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 143 { "largepages", VM_STAT(lpages) },
417bc304
HB		 144 { NULL }
145};
146
18863bdd
AK		 147static void kvm_on_user_return(struct user_return_notifier *urn)
148{
149 unsigned slot;
18863bdd
AK		 150 struct kvm_shared_msrs *locals
151 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 152 struct kvm_shared_msr_values *values;
18863bdd
AK		 153
154 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 155 values = &locals->values[slot];
156 if (values->host != values->curr) {
157 wrmsrl(shared_msrs_global.msrs[slot], values->host);
158 values->curr = values->host;
18863bdd
AK		 159 }
160 }
161 locals->registered = false;
162 user_return_notifier_unregister(urn);
163}
164
2bf78fa7 165static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 166{
2bf78fa7 167 struct kvm_shared_msrs *smsr;
18863bdd
AK		 168 u64 value;
169
2bf78fa7
SY		 170 smsr = &__get_cpu_var(shared_msrs);
171 /* only read, and nobody should modify it at this time,
172 * so don't need lock */
173 if (slot >= shared_msrs_global.nr) {
174 printk(KERN_ERR "kvm: invalid MSR slot!");
175 return;
176 }
177 rdmsrl_safe(msr, &value);
178 smsr->values[slot].host = value;
179 smsr->values[slot].curr = value;
180}
181
182void kvm_define_shared_msr(unsigned slot, u32 msr)
183{
18863bdd
AK		 184 if (slot >= shared_msrs_global.nr)
185 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 186 shared_msrs_global.msrs[slot] = msr;
187 /* we need ensured the shared_msr_global have been updated */
188 smp_wmb();
18863bdd
AK		 189}
190EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
191
192static void kvm_shared_msr_cpu_online(void)
193{
194 unsigned i;
18863bdd
AK		 195
196 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 197 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 198}
199
d5696725 200void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 201{
202 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
203
2bf78fa7 204 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 205 return;
2bf78fa7
SY		 206 smsr->values[slot].curr = value;
207 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 208 if (!smsr->registered) {
209 smsr->urn.on_user_return = kvm_on_user_return;
210 user_return_notifier_register(&smsr->urn);
211 smsr->registered = true;
212 }
213}
214EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
215
3548bab5
AK		 216static void drop_user_return_notifiers(void *ignore)
217{
218 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
219
220 if (smsr->registered)
221 kvm_on_user_return(&smsr->urn);
222}
223
5fb76f9b
CO		 224unsigned long segment_base(u16 selector)
225{
226 struct descriptor_table gdt;
a5f61300 227 struct desc_struct *d;
5fb76f9b
CO		 228 unsigned long table_base;
229 unsigned long v;
230
231 if (selector == 0)
232 return 0;
233
b792c344 234 kvm_get_gdt(&gdt);
5fb76f9b
CO		 235 table_base = gdt.base;
236
237 if (selector & 4) { /* from ldt */
b792c344 238 u16 ldt_selector = kvm_read_ldt();
5fb76f9b 239
5fb76f9b
CO		 240 table_base = segment_base(ldt_selector);
241 }
a5f61300 242 d = (struct desc_struct *)(table_base + (selector & ~7));
46a359e7 243 v = get_desc_base(d);
5fb76f9b 244#ifdef CONFIG_X86_64
a5f61300
AK		 245 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
246 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
5fb76f9b
CO		 247#endif
248 return v;
249}
250EXPORT_SYMBOL_GPL(segment_base);
251
6866b83e
CO		 252u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
253{
254 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 255 return vcpu->arch.apic_base;
6866b83e 256 else
ad312c7c 257 return vcpu->arch.apic_base;
6866b83e
CO		 258}
259EXPORT_SYMBOL_GPL(kvm_get_apic_base);
260
261void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
262{
263 /* TODO: reserve bits check */
264 if (irqchip_in_kernel(vcpu->kvm))
265 kvm_lapic_set_base(vcpu, data);
266 else
ad312c7c 267 vcpu->arch.apic_base = data;
6866b83e
CO		 268}
269EXPORT_SYMBOL_GPL(kvm_set_apic_base);
270
3fd28fce
ED		 271#define EXCPT_BENIGN 0
272#define EXCPT_CONTRIBUTORY 1
273#define EXCPT_PF 2
274
275static int exception_class(int vector)
276{
277 switch (vector) {
278 case PF_VECTOR:
279 return EXCPT_PF;
280 case DE_VECTOR:
281 case TS_VECTOR:
282 case NP_VECTOR:
283 case SS_VECTOR:
284 case GP_VECTOR:
285 return EXCPT_CONTRIBUTORY;
286 default:
287 break;
288 }
289 return EXCPT_BENIGN;
290}
291
292static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
293 unsigned nr, bool has_error, u32 error_code)
294{
295 u32 prev_nr;
296 int class1, class2;
297
298 if (!vcpu->arch.exception.pending) {
299 queue:
300 vcpu->arch.exception.pending = true;
301 vcpu->arch.exception.has_error_code = has_error;
302 vcpu->arch.exception.nr = nr;
303 vcpu->arch.exception.error_code = error_code;
304 return;
305 }
306
307 /* to check exception */
308 prev_nr = vcpu->arch.exception.nr;
309 if (prev_nr == DF_VECTOR) {
310 /* triple fault -> shutdown */
311 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
312 return;
313 }
314 class1 = exception_class(prev_nr);
315 class2 = exception_class(nr);
316 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
317 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
318 /* generate double fault per SDM Table 5-5 */
319 vcpu->arch.exception.pending = true;
320 vcpu->arch.exception.has_error_code = true;
321 vcpu->arch.exception.nr = DF_VECTOR;
322 vcpu->arch.exception.error_code = 0;
323 } else
324 /* replace previous exception with a new one in a hope
325 that instruction re-execution will regenerate lost
326 exception */
327 goto queue;
328}
329
298101da
AK		 330void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
331{
3fd28fce 332 kvm_multiple_exception(vcpu, nr, false, 0);
298101da
AK		 333}
334EXPORT_SYMBOL_GPL(kvm_queue_exception);
335
c3c91fee
AK		 336void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
337 u32 error_code)
338{
339 ++vcpu->stat.pf_guest;
ad312c7c 340 vcpu->arch.cr2 = addr;
c3c91fee
AK		 341 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
342}
343
3419ffc8
SY		 344void kvm_inject_nmi(struct kvm_vcpu *vcpu)
345{
346 vcpu->arch.nmi_pending = 1;
347}
348EXPORT_SYMBOL_GPL(kvm_inject_nmi);
349
298101da
AK		 350void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
351{
3fd28fce 352 kvm_multiple_exception(vcpu, nr, true, error_code);
298101da
AK		 353}
354EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
355
0a79b009
AK		 356/*
357 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
358 * a #GP and return false.
359 */
360bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 361{
0a79b009
AK		 362 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
363 return true;
364 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
365 return false;
298101da 366}
0a79b009 367EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 368
a03490ed
CO		 369/*
370 * Load the pae pdptrs. Return true is they are all valid.
371 */
372int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
373{
374 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
375 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
376 int i;
377 int ret;
ad312c7c 378 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 379
a03490ed
CO		 380 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
381 offset * sizeof(u64), sizeof(pdpte));
382 if (ret < 0) {
383 ret = 0;
384 goto out;
385 }
386 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 387 if (is_present_gpte(pdpte[i]) &&
20c466b5 388 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 389 ret = 0;
390 goto out;
391 }
392 }
393 ret = 1;
394
ad312c7c 395 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
6de4f3ad
AK		 396 __set_bit(VCPU_EXREG_PDPTR,
397 (unsigned long *)&vcpu->arch.regs_avail);
398 __set_bit(VCPU_EXREG_PDPTR,
399 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 400out:
a03490ed
CO		 401
402 return ret;
403}
cc4b6871 404EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 405
d835dfec
AK		 406static bool pdptrs_changed(struct kvm_vcpu *vcpu)
407{
ad312c7c 408 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 409 bool changed = true;
410 int r;
411
412 if (is_long_mode(vcpu) || !is_pae(vcpu))
413 return false;
414
6de4f3ad
AK		 415 if (!test_bit(VCPU_EXREG_PDPTR,
416 (unsigned long *)&vcpu->arch.regs_avail))
417 return true;
418
ad312c7c 419 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 420 if (r < 0)
421 goto out;
ad312c7c 422 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 423out:
d835dfec
AK		 424
425 return changed;
426}
427
2d3ad1f4 428void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed
CO		 429{
430 if (cr0 & CR0_RESERVED_BITS) {
431 printk(KERN_DEBUG "set_cr0: 0x%lx #GP, reserved bits 0x%lx\n",
ad312c7c 432 cr0, vcpu->arch.cr0);
c1a5d4f9 433 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 434 return;
435 }
436
437 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) {
438 printk(KERN_DEBUG "set_cr0: #GP, CD == 0 && NW == 1\n");
c1a5d4f9 439 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 440 return;
441 }
442
443 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) {
444 printk(KERN_DEBUG "set_cr0: #GP, set PG flag "
445 "and a clear PE flag\n");
c1a5d4f9 446 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 447 return;
448 }
449
450 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
451#ifdef CONFIG_X86_64
ad312c7c 452 if ((vcpu->arch.shadow_efer & EFER_LME)) {
a03490ed
CO		 453 int cs_db, cs_l;
454
455 if (!is_pae(vcpu)) {
456 printk(KERN_DEBUG "set_cr0: #GP, start paging "
457 "in long mode while PAE is disabled\n");
c1a5d4f9 458 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 459 return;
460 }
461 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
462 if (cs_l) {
463 printk(KERN_DEBUG "set_cr0: #GP, start paging "
464 "in long mode while CS.L == 1\n");
c1a5d4f9 465 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 466 return;
467
468 }
469 } else
470#endif
ad312c7c 471 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed
CO		 472 printk(KERN_DEBUG "set_cr0: #GP, pdptrs "
473 "reserved bits\n");
c1a5d4f9 474 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 475 return;
476 }
477
478 }
479
480 kvm_x86_ops->set_cr0(vcpu, cr0);
ad312c7c 481 vcpu->arch.cr0 = cr0;
a03490ed 482
a03490ed 483 kvm_mmu_reset_context(vcpu);
a03490ed
CO		 484 return;
485}
2d3ad1f4 486EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 487
2d3ad1f4 488void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 489{
2d3ad1f4 490 kvm_set_cr0(vcpu, (vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f));
a03490ed 491}
2d3ad1f4 492EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 493
2d3ad1f4 494void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 495{
fc78f519 496 unsigned long old_cr4 = kvm_read_cr4(vcpu);
a2edf57f
AK		 497 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
498
a03490ed
CO		 499 if (cr4 & CR4_RESERVED_BITS) {
500 printk(KERN_DEBUG "set_cr4: #GP, reserved bits\n");
c1a5d4f9 501 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 502 return;
503 }
504
505 if (is_long_mode(vcpu)) {
506 if (!(cr4 & X86_CR4_PAE)) {
507 printk(KERN_DEBUG "set_cr4: #GP, clearing PAE while "
508 "in long mode\n");
c1a5d4f9 509 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 510 return;
511 }
a2edf57f
AK		 512 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
513 && ((cr4 ^ old_cr4) & pdptr_bits)
ad312c7c 514 && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed 515 printk(KERN_DEBUG "set_cr4: #GP, pdptrs reserved bits\n");
c1a5d4f9 516 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 517 return;
518 }
519
520 if (cr4 & X86_CR4_VMXE) {
521 printk(KERN_DEBUG "set_cr4: #GP, setting VMXE\n");
c1a5d4f9 522 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 523 return;
524 }
525 kvm_x86_ops->set_cr4(vcpu, cr4);
ad312c7c 526 vcpu->arch.cr4 = cr4;
5a41accd 527 vcpu->arch.mmu.base_role.cr4_pge = (cr4 & X86_CR4_PGE) && !tdp_enabled;
a03490ed 528 kvm_mmu_reset_context(vcpu);
a03490ed 529}
2d3ad1f4 530EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 531
2d3ad1f4 532void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 533{
ad312c7c 534 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 535 kvm_mmu_sync_roots(vcpu);
d835dfec
AK		 536 kvm_mmu_flush_tlb(vcpu);
537 return;
538 }
539
a03490ed
CO		 540 if (is_long_mode(vcpu)) {
541 if (cr3 & CR3_L_MODE_RESERVED_BITS) {
542 printk(KERN_DEBUG "set_cr3: #GP, reserved bits\n");
c1a5d4f9 543 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 544 return;
545 }
546 } else {
547 if (is_pae(vcpu)) {
548 if (cr3 & CR3_PAE_RESERVED_BITS) {
549 printk(KERN_DEBUG
550 "set_cr3: #GP, reserved bits\n");
c1a5d4f9 551 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 552 return;
553 }
554 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) {
555 printk(KERN_DEBUG "set_cr3: #GP, pdptrs "
556 "reserved bits\n");
c1a5d4f9 557 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 558 return;
559 }
560 }
561 /*
562 * We don't check reserved bits in nonpae mode, because
563 * this isn't enforced, and VMware depends on this.
564 */
565 }
566
a03490ed
CO		 567 /*
568 * Does the new cr3 value map to physical memory? (Note, we
569 * catch an invalid cr3 even in real-mode, because it would
570 * cause trouble later on when we turn on paging anyway.)
571 *
572 * A real CPU would silently accept an invalid cr3 and would
573 * attempt to use it - with largely undefined (and often hard
574 * to debug) behavior on the guest side.
575 */
576 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
c1a5d4f9 577 kvm_inject_gp(vcpu, 0);
a03490ed 578 else {
ad312c7c
ZX		 579 vcpu->arch.cr3 = cr3;
580 vcpu->arch.mmu.new_cr3(vcpu);
a03490ed 581 }
a03490ed 582}
2d3ad1f4 583EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 584
2d3ad1f4 585void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed
CO		 586{
587 if (cr8 & CR8_RESERVED_BITS) {
588 printk(KERN_DEBUG "set_cr8: #GP, reserved bits 0x%lx\n", cr8);
c1a5d4f9 589 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 590 return;
591 }
592 if (irqchip_in_kernel(vcpu->kvm))
593 kvm_lapic_set_tpr(vcpu, cr8);
594 else
ad312c7c 595 vcpu->arch.cr8 = cr8;
a03490ed 596}
2d3ad1f4 597EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 598
2d3ad1f4 599unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 600{
601 if (irqchip_in_kernel(vcpu->kvm))
602 return kvm_lapic_get_cr8(vcpu);
603 else
ad312c7c 604 return vcpu->arch.cr8;
a03490ed 605}
2d3ad1f4 606EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 607
d8017474
AG		 608static inline u32 bit(int bitno)
609{
610 return 1 << (bitno & 31);
611}
612
043405e1
CO		 613/*
614 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
615 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
616 *
617 * This list is modified at module load time to reflect the
e3267cbb
GC		 618 * capabilities of the host cpu. This capabilities test skips MSRs that are
619 * kvm-specific. Those are put in the beginning of the list.
043405e1 620 */
e3267cbb
GC		 621
622#define KVM_SAVE_MSRS_BEGIN 2
043405e1 623static u32 msrs_to_save[] = {
e3267cbb 624 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
043405e1
CO		 625 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
626 MSR_K6_STAR,
627#ifdef CONFIG_X86_64
628 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
629#endif
e3267cbb 630 MSR_IA32_TSC, MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 631};
632
633static unsigned num_msrs_to_save;
634
635static u32 emulated_msrs[] = {
636 MSR_IA32_MISC_ENABLE,
637};
638
15c4a640
CO		 639static void set_efer(struct kvm_vcpu *vcpu, u64 efer)
640{
f2b4b7dd 641 if (efer & efer_reserved_bits) {
15c4a640
CO		 642 printk(KERN_DEBUG "set_efer: 0x%llx #GP, reserved bits\n",
643 efer);
c1a5d4f9 644 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 645 return;
646 }
647
648 if (is_paging(vcpu)
ad312c7c 649 && (vcpu->arch.shadow_efer & EFER_LME) != (efer & EFER_LME)) {
15c4a640 650 printk(KERN_DEBUG "set_efer: #GP, change LME while paging\n");
c1a5d4f9 651 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 652 return;
653 }
654
1b2fd70c
AG		 655 if (efer & EFER_FFXSR) {
656 struct kvm_cpuid_entry2 *feat;
657
658 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
659 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) {
660 printk(KERN_DEBUG "set_efer: #GP, enable FFXSR w/o CPUID capability\n");
661 kvm_inject_gp(vcpu, 0);
662 return;
663 }
664 }
665
d8017474
AG		 666 if (efer & EFER_SVME) {
667 struct kvm_cpuid_entry2 *feat;
668
669 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
670 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) {
671 printk(KERN_DEBUG "set_efer: #GP, enable SVM w/o SVM\n");
672 kvm_inject_gp(vcpu, 0);
673 return;
674 }
675 }
676
15c4a640
CO		 677 kvm_x86_ops->set_efer(vcpu, efer);
678
679 efer &= ~EFER_LMA;
ad312c7c 680 efer |= vcpu->arch.shadow_efer & EFER_LMA;
15c4a640 681
ad312c7c 682 vcpu->arch.shadow_efer = efer;
9645bb56
AK		 683
684 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
685 kvm_mmu_reset_context(vcpu);
15c4a640
CO		 686}
687
f2b4b7dd
JR		 688void kvm_enable_efer_bits(u64 mask)
689{
690 efer_reserved_bits &= ~mask;
691}
692EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
693
694
15c4a640
CO		 695/*
696 * Writes msr value into into the appropriate "register".
697 * Returns 0 on success, non-0 otherwise.
698 * Assumes vcpu_load() was already called.
699 */
700int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
701{
702 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
703}
704
313a3dc7
CO		 705/*
706 * Adapt set_msr() to msr_io()'s calling convention
707 */
708static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
709{
710 return kvm_set_msr(vcpu, index, *data);
711}
712
18068523
GOC		 713static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
714{
715 static int version;
50d0a0f9 716 struct pvclock_wall_clock wc;
923de3cf 717 struct timespec boot;
18068523
GOC		 718
719 if (!wall_clock)
720 return;
721
722 version++;
723
18068523
GOC		 724 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
725
50d0a0f9
GH		 726 /*
727 * The guest calculates current wall clock time by adding
728 * system time (updated by kvm_write_guest_time below) to the
729 * wall clock specified here. guest system time equals host
730 * system time for us, thus we must fill in host boot time here.
731 */
923de3cf 732 getboottime(&boot);
50d0a0f9
GH		 733
734 wc.sec = boot.tv_sec;
735 wc.nsec = boot.tv_nsec;
736 wc.version = version;
18068523
GOC		 737
738 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
739
740 version++;
741 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 742}
743
50d0a0f9
GH		 744static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
745{
746 uint32_t quotient, remainder;
747
748 /* Don't try to replace with do_div(), this one calculates
749 * "(dividend << 32) / divisor" */
750 __asm__ ( "divl %4"
751 : "=a" (quotient), "=d" (remainder)
752 : "0" (0), "1" (dividend), "r" (divisor) );
753 return quotient;
754}
755
756static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
757{
758 uint64_t nsecs = 1000000000LL;
759 int32_t shift = 0;
760 uint64_t tps64;
761 uint32_t tps32;
762
763 tps64 = tsc_khz * 1000LL;
764 while (tps64 > nsecs*2) {
765 tps64 >>= 1;
766 shift--;
767 }
768
769 tps32 = (uint32_t)tps64;
770 while (tps32 <= (uint32_t)nsecs) {
771 tps32 <<= 1;
772 shift++;
773 }
774
775 hv_clock->tsc_shift = shift;
776 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
777
778 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
80a914dc 779 __func__, tsc_khz, hv_clock->tsc_shift,
50d0a0f9
GH		 780 hv_clock->tsc_to_system_mul);
781}
782
c8076604
GH		 783static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
784
18068523
GOC		 785static void kvm_write_guest_time(struct kvm_vcpu *v)
786{
787 struct timespec ts;
788 unsigned long flags;
789 struct kvm_vcpu_arch *vcpu = &v->arch;
790 void *shared_kaddr;
463656c0 791 unsigned long this_tsc_khz;
18068523
GOC		 792
793 if ((!vcpu->time_page))
794 return;
795
463656c0
AK		 796 this_tsc_khz = get_cpu_var(cpu_tsc_khz);
797 if (unlikely(vcpu->hv_clock_tsc_khz != this_tsc_khz)) {
798 kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock);
799 vcpu->hv_clock_tsc_khz = this_tsc_khz;
50d0a0f9 800 }
463656c0 801 put_cpu_var(cpu_tsc_khz);
50d0a0f9 802
18068523
GOC		 803 /* Keep irq disabled to prevent changes to the clock */
804 local_irq_save(flags);
af24a4e4 805 kvm_get_msr(v, MSR_IA32_TSC, &vcpu->hv_clock.tsc_timestamp);
18068523 806 ktime_get_ts(&ts);
923de3cf 807 monotonic_to_bootbased(&ts);
18068523
GOC		 808 local_irq_restore(flags);
809
810 /* With all the info we got, fill in the values */
811
812 vcpu->hv_clock.system_time = ts.tv_nsec +
afbcf7ab
GC		 813 (NSEC_PER_SEC * (u64)ts.tv_sec) + v->kvm->arch.kvmclock_offset;
814
18068523
GOC		 815 /*
816 * The interface expects us to write an even number signaling that the
817 * update is finished. Since the guest won't see the intermediate
50d0a0f9 818 * state, we just increase by 2 at the end.
18068523 819 */
50d0a0f9 820 vcpu->hv_clock.version += 2;
18068523
GOC		 821
822 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
823
824 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 825 sizeof(vcpu->hv_clock));
18068523
GOC		 826
827 kunmap_atomic(shared_kaddr, KM_USER0);
828
829 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
830}
831
c8076604
GH		 832static int kvm_request_guest_time_update(struct kvm_vcpu *v)
833{
834 struct kvm_vcpu_arch *vcpu = &v->arch;
835
836 if (!vcpu->time_page)
837 return 0;
838 set_bit(KVM_REQ_KVMCLOCK_UPDATE, &v->requests);
839 return 1;
840}
841
9ba075a6
AK		 842static bool msr_mtrr_valid(unsigned msr)
843{
844 switch (msr) {
845 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
846 case MSR_MTRRfix64K_00000:
847 case MSR_MTRRfix16K_80000:
848 case MSR_MTRRfix16K_A0000:
849 case MSR_MTRRfix4K_C0000:
850 case MSR_MTRRfix4K_C8000:
851 case MSR_MTRRfix4K_D0000:
852 case MSR_MTRRfix4K_D8000:
853 case MSR_MTRRfix4K_E0000:
854 case MSR_MTRRfix4K_E8000:
855 case MSR_MTRRfix4K_F0000:
856 case MSR_MTRRfix4K_F8000:
857 case MSR_MTRRdefType:
858 case MSR_IA32_CR_PAT:
859 return true;
860 case 0x2f8:
861 return true;
862 }
863 return false;
864}
865
d6289b93
MT		 866static bool valid_pat_type(unsigned t)
867{
868 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
869}
870
871static bool valid_mtrr_type(unsigned t)
872{
873 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
874}
875
876static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
877{
878 int i;
879
880 if (!msr_mtrr_valid(msr))
881 return false;
882
883 if (msr == MSR_IA32_CR_PAT) {
884 for (i = 0; i < 8; i++)
885 if (!valid_pat_type((data >> (i * 8)) & 0xff))
886 return false;
887 return true;
888 } else if (msr == MSR_MTRRdefType) {
889 if (data & ~0xcff)
890 return false;
891 return valid_mtrr_type(data & 0xff);
892 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
893 for (i = 0; i < 8 ; i++)
894 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
895 return false;
896 return true;
897 }
898
899 /* variable MTRRs */
900 return valid_mtrr_type(data & 0xff);
901}
902
9ba075a6
AK		 903static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
904{
0bed3b56
SY		 905 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
906
d6289b93 907 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 908 return 1;
909
0bed3b56
SY		 910 if (msr == MSR_MTRRdefType) {
911 vcpu->arch.mtrr_state.def_type = data;
912 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
913 } else if (msr == MSR_MTRRfix64K_00000)
914 p[0] = data;
915 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
916 p[1 + msr - MSR_MTRRfix16K_80000] = data;
917 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
918 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
919 else if (msr == MSR_IA32_CR_PAT)
920 vcpu->arch.pat = data;
921 else { /* Variable MTRRs */
922 int idx, is_mtrr_mask;
923 u64 *pt;
924
925 idx = (msr - 0x200) / 2;
926 is_mtrr_mask = msr - 0x200 - 2 * idx;
927 if (!is_mtrr_mask)
928 pt =
929 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
930 else
931 pt =
932 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
933 *pt = data;
934 }
935
936 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 937 return 0;
938}
15c4a640 939
890ca9ae 940static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 941{
890ca9ae
HY		 942 u64 mcg_cap = vcpu->arch.mcg_cap;
943 unsigned bank_num = mcg_cap & 0xff;
944
15c4a640 945 switch (msr) {
15c4a640 946 case MSR_IA32_MCG_STATUS:
890ca9ae 947 vcpu->arch.mcg_status = data;
15c4a640 948 break;
c7ac679c 949 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 950 if (!(mcg_cap & MCG_CTL_P))
951 return 1;
952 if (data != 0 && data != ~(u64)0)
953 return -1;
954 vcpu->arch.mcg_ctl = data;
955 break;
956 default:
957 if (msr >= MSR_IA32_MC0_CTL &&
958 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
959 u32 offset = msr - MSR_IA32_MC0_CTL;
960 /* only 0 or all 1s can be written to IA32_MCi_CTL */
961 if ((offset & 0x3) == 0 &&
962 data != 0 && data != ~(u64)0)
963 return -1;
964 vcpu->arch.mce_banks[offset] = data;
965 break;
966 }
967 return 1;
968 }
969 return 0;
970}
971
ffde22ac
ES		 972static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
973{
974 struct kvm *kvm = vcpu->kvm;
975 int lm = is_long_mode(vcpu);
976 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
977 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
978 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
979 : kvm->arch.xen_hvm_config.blob_size_32;
980 u32 page_num = data & ~PAGE_MASK;
981 u64 page_addr = data & PAGE_MASK;
982 u8 *page;
983 int r;
984
985 r = -E2BIG;
986 if (page_num >= blob_size)
987 goto out;
988 r = -ENOMEM;
989 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
990 if (!page)
991 goto out;
992 r = -EFAULT;
993 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
994 goto out_free;
995 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
996 goto out_free;
997 r = 0;
998out_free:
999 kfree(page);
1000out:
1001 return r;
1002}
1003
15c4a640
CO		 1004int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1005{
1006 switch (msr) {
15c4a640
CO		 1007 case MSR_EFER:
1008 set_efer(vcpu, data);
1009 break;
8f1589d9
AP		 1010 case MSR_K7_HWCR:
1011 data &= ~(u64)0x40; /* ignore flush filter disable */
1012 if (data != 0) {
1013 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1014 data);
1015 return 1;
1016 }
15c4a640 1017 break;
f7c6d140
AP		 1018 case MSR_FAM10H_MMIO_CONF_BASE:
1019 if (data != 0) {
1020 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1021 "0x%llx\n", data);
1022 return 1;
1023 }
15c4a640 1024 break;
c323c0e5 1025 case MSR_AMD64_NB_CFG:
c7ac679c 1026 break;
b5e2fec0
AG		 1027 case MSR_IA32_DEBUGCTLMSR:
1028 if (!data) {
1029 /* We support the non-activated case already */
1030 break;
1031 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1032 /* Values other than LBR and BTF are vendor-specific,
1033 thus reserved and should throw a #GP */
1034 return 1;
1035 }
1036 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1037 __func__, data);
1038 break;
15c4a640
CO		 1039 case MSR_IA32_UCODE_REV:
1040 case MSR_IA32_UCODE_WRITE:
61a6bd67 1041 case MSR_VM_HSAVE_PA:
6098ca93 1042 case MSR_AMD64_PATCH_LOADER:
15c4a640 1043 break;
9ba075a6
AK		 1044 case 0x200 ... 0x2ff:
1045 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1046 case MSR_IA32_APICBASE:
1047 kvm_set_apic_base(vcpu, data);
1048 break;
0105d1a5
GN		 1049 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1050 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 1051 case MSR_IA32_MISC_ENABLE:
ad312c7c 1052 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1053 break;
18068523
GOC		 1054 case MSR_KVM_WALL_CLOCK:
1055 vcpu->kvm->arch.wall_clock = data;
1056 kvm_write_wall_clock(vcpu->kvm, data);
1057 break;
1058 case MSR_KVM_SYSTEM_TIME: {
1059 if (vcpu->arch.time_page) {
1060 kvm_release_page_dirty(vcpu->arch.time_page);
1061 vcpu->arch.time_page = NULL;
1062 }
1063
1064 vcpu->arch.time = data;
1065
1066 /* we verify if the enable bit is set... */
1067 if (!(data & 1))
1068 break;
1069
1070 /* ...but clean it before doing the actual write */
1071 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1072
18068523
GOC		 1073 vcpu->arch.time_page =
1074 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1075
1076 if (is_error_page(vcpu->arch.time_page)) {
1077 kvm_release_page_clean(vcpu->arch.time_page);
1078 vcpu->arch.time_page = NULL;
1079 }
1080
c8076604 1081 kvm_request_guest_time_update(vcpu);
18068523
GOC		 1082 break;
1083 }
890ca9ae
HY		 1084 case MSR_IA32_MCG_CTL:
1085 case MSR_IA32_MCG_STATUS:
1086 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1087 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1088
1089 /* Performance counters are not protected by a CPUID bit,
1090 * so we should check all of them in the generic path for the sake of
1091 * cross vendor migration.
1092 * Writing a zero into the event select MSRs disables them,
1093 * which we perfectly emulate ;-). Any other value should be at least
1094 * reported, some guests depend on them.
1095 */
1096 case MSR_P6_EVNTSEL0:
1097 case MSR_P6_EVNTSEL1:
1098 case MSR_K7_EVNTSEL0:
1099 case MSR_K7_EVNTSEL1:
1100 case MSR_K7_EVNTSEL2:
1101 case MSR_K7_EVNTSEL3:
1102 if (data != 0)
1103 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1104 "0x%x data 0x%llx\n", msr, data);
1105 break;
1106 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1107 * so we ignore writes to make it happy.
1108 */
1109 case MSR_P6_PERFCTR0:
1110 case MSR_P6_PERFCTR1:
1111 case MSR_K7_PERFCTR0:
1112 case MSR_K7_PERFCTR1:
1113 case MSR_K7_PERFCTR2:
1114 case MSR_K7_PERFCTR3:
1115 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1116 "0x%x data 0x%llx\n", msr, data);
1117 break;
15c4a640 1118 default:
ffde22ac
ES		 1119 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1120 return xen_hvm_config(vcpu, data);
ed85c068
AP		 1121 if (!ignore_msrs) {
1122 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1123 msr, data);
1124 return 1;
1125 } else {
1126 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1127 msr, data);
1128 break;
1129 }
15c4a640
CO		 1130 }
1131 return 0;
1132}
1133EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1134
1135
1136/*
1137 * Reads an msr value (of 'msr_index') into 'pdata'.
1138 * Returns 0 on success, non-0 otherwise.
1139 * Assumes vcpu_load() was already called.
1140 */
1141int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1142{
1143 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1144}
1145
9ba075a6
AK		 1146static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1147{
0bed3b56
SY		 1148 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1149
9ba075a6
AK		 1150 if (!msr_mtrr_valid(msr))
1151 return 1;
1152
0bed3b56
SY		 1153 if (msr == MSR_MTRRdefType)
1154 *pdata = vcpu->arch.mtrr_state.def_type +
1155 (vcpu->arch.mtrr_state.enabled << 10);
1156 else if (msr == MSR_MTRRfix64K_00000)
1157 *pdata = p[0];
1158 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1159 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1160 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1161 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1162 else if (msr == MSR_IA32_CR_PAT)
1163 *pdata = vcpu->arch.pat;
1164 else { /* Variable MTRRs */
1165 int idx, is_mtrr_mask;
1166 u64 *pt;
1167
1168 idx = (msr - 0x200) / 2;
1169 is_mtrr_mask = msr - 0x200 - 2 * idx;
1170 if (!is_mtrr_mask)
1171 pt =
1172 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1173 else
1174 pt =
1175 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1176 *pdata = *pt;
1177 }
1178
9ba075a6
AK		 1179 return 0;
1180}
1181
890ca9ae 1182static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1183{
1184 u64 data;
890ca9ae
HY		 1185 u64 mcg_cap = vcpu->arch.mcg_cap;
1186 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1187
1188 switch (msr) {
15c4a640
CO		 1189 case MSR_IA32_P5_MC_ADDR:
1190 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1191 data = 0;
1192 break;
15c4a640 1193 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1194 data = vcpu->arch.mcg_cap;
1195 break;
c7ac679c 1196 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1197 if (!(mcg_cap & MCG_CTL_P))
1198 return 1;
1199 data = vcpu->arch.mcg_ctl;
1200 break;
1201 case MSR_IA32_MCG_STATUS:
1202 data = vcpu->arch.mcg_status;
1203 break;
1204 default:
1205 if (msr >= MSR_IA32_MC0_CTL &&
1206 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1207 u32 offset = msr - MSR_IA32_MC0_CTL;
1208 data = vcpu->arch.mce_banks[offset];
1209 break;
1210 }
1211 return 1;
1212 }
1213 *pdata = data;
1214 return 0;
1215}
1216
1217int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1218{
1219 u64 data;
1220
1221 switch (msr) {
890ca9ae 1222 case MSR_IA32_PLATFORM_ID:
15c4a640 1223 case MSR_IA32_UCODE_REV:
15c4a640 1224 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1225 case MSR_IA32_DEBUGCTLMSR:
1226 case MSR_IA32_LASTBRANCHFROMIP:
1227 case MSR_IA32_LASTBRANCHTOIP:
1228 case MSR_IA32_LASTINTFROMIP:
1229 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1230 case MSR_K8_SYSCFG:
1231 case MSR_K7_HWCR:
61a6bd67 1232 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1233 case MSR_P6_PERFCTR0:
1234 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1235 case MSR_P6_EVNTSEL0:
1236 case MSR_P6_EVNTSEL1:
9e699624 1237 case MSR_K7_EVNTSEL0:
1f3ee616 1238 case MSR_K7_PERFCTR0:
1fdbd48c 1239 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1240 case MSR_AMD64_NB_CFG:
f7c6d140 1241 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1242 data = 0;
1243 break;
9ba075a6
AK		 1244 case MSR_MTRRcap:
1245 data = 0x500 | KVM_NR_VAR_MTRR;
1246 break;
1247 case 0x200 ... 0x2ff:
1248 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1249 case 0xcd: /* fsb frequency */
1250 data = 3;
1251 break;
1252 case MSR_IA32_APICBASE:
1253 data = kvm_get_apic_base(vcpu);
1254 break;
0105d1a5
GN		 1255 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1256 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1257 break;
15c4a640 1258 case MSR_IA32_MISC_ENABLE:
ad312c7c 1259 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1260 break;
847f0ad8
AG		 1261 case MSR_IA32_PERF_STATUS:
1262 /* TSC increment by tick */
1263 data = 1000ULL;
1264 /* CPU multiplier */
1265 data |= (((uint64_t)4ULL) << 40);
1266 break;
15c4a640 1267 case MSR_EFER:
ad312c7c 1268 data = vcpu->arch.shadow_efer;
15c4a640 1269 break;
18068523
GOC		 1270 case MSR_KVM_WALL_CLOCK:
1271 data = vcpu->kvm->arch.wall_clock;
1272 break;
1273 case MSR_KVM_SYSTEM_TIME:
1274 data = vcpu->arch.time;
1275 break;
890ca9ae
HY		 1276 case MSR_IA32_P5_MC_ADDR:
1277 case MSR_IA32_P5_MC_TYPE:
1278 case MSR_IA32_MCG_CAP:
1279 case MSR_IA32_MCG_CTL:
1280 case MSR_IA32_MCG_STATUS:
1281 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1282 return get_msr_mce(vcpu, msr, pdata);
15c4a640 1283 default:
ed85c068
AP		 1284 if (!ignore_msrs) {
1285 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1286 return 1;
1287 } else {
1288 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1289 data = 0;
1290 }
1291 break;
15c4a640
CO		 1292 }
1293 *pdata = data;
1294 return 0;
1295}
1296EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1297
313a3dc7
CO		 1298/*
1299 * Read or write a bunch of msrs. All parameters are kernel addresses.
1300 *
1301 * @return number of msrs set successfully.
1302 */
1303static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1304 struct kvm_msr_entry *entries,
1305 int (*do_msr)(struct kvm_vcpu *vcpu,
1306 unsigned index, u64 *data))
1307{
1308 int i;
1309
1310 vcpu_load(vcpu);
1311
3200f405 1312 down_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 1313 for (i = 0; i < msrs->nmsrs; ++i)
1314 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1315 break;
3200f405 1316 up_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 1317
1318 vcpu_put(vcpu);
1319
1320 return i;
1321}
1322
1323/*
1324 * Read or write a bunch of msrs. Parameters are user addresses.
1325 *
1326 * @return number of msrs set successfully.
1327 */
1328static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1329 int (*do_msr)(struct kvm_vcpu *vcpu,
1330 unsigned index, u64 *data),
1331 int writeback)
1332{
1333 struct kvm_msrs msrs;
1334 struct kvm_msr_entry *entries;
1335 int r, n;
1336 unsigned size;
1337
1338 r = -EFAULT;
1339 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1340 goto out;
1341
1342 r = -E2BIG;
1343 if (msrs.nmsrs >= MAX_IO_MSRS)
1344 goto out;
1345
1346 r = -ENOMEM;
1347 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
1348 entries = vmalloc(size);
1349 if (!entries)
1350 goto out;
1351
1352 r = -EFAULT;
1353 if (copy_from_user(entries, user_msrs->entries, size))
1354 goto out_free;
1355
1356 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1357 if (r < 0)
1358 goto out_free;
1359
1360 r = -EFAULT;
1361 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1362 goto out_free;
1363
1364 r = n;
1365
1366out_free:
1367 vfree(entries);
1368out:
1369 return r;
1370}
1371
018d00d2
ZX		 1372int kvm_dev_ioctl_check_extension(long ext)
1373{
1374 int r;
1375
1376 switch (ext) {
1377 case KVM_CAP_IRQCHIP:
1378 case KVM_CAP_HLT:
1379 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1380 case KVM_CAP_SET_TSS_ADDR:
07716717 1381 case KVM_CAP_EXT_CPUID:
c8076604 1382 case KVM_CAP_CLOCKSOURCE:
7837699f 1383 case KVM_CAP_PIT:
a28e4f5a 1384 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1385 case KVM_CAP_MP_STATE:
ed848624 1386 case KVM_CAP_SYNC_MMU:
52d939a0 1387 case KVM_CAP_REINJECT_CONTROL:
4925663a 1388 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1389 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1390 case KVM_CAP_IRQFD:
d34e6b17 1391 case KVM_CAP_IOEVENTFD:
c5ff41ce 1392 case KVM_CAP_PIT2:
e9f42757 1393 case KVM_CAP_PIT_STATE2:
b927a3ce 1394 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 1395 case KVM_CAP_XEN_HVM:
afbcf7ab 1396 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 1397 case KVM_CAP_VCPU_EVENTS:
018d00d2
ZX		 1398 r = 1;
1399 break;
542472b5
LV		 1400 case KVM_CAP_COALESCED_MMIO:
1401 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1402 break;
774ead3a
AK		 1403 case KVM_CAP_VAPIC:
1404 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1405 break;
f725230a
AK		 1406 case KVM_CAP_NR_VCPUS:
1407 r = KVM_MAX_VCPUS;
1408 break;
a988b910
AK		 1409 case KVM_CAP_NR_MEMSLOTS:
1410 r = KVM_MEMORY_SLOTS;
1411 break;
a68a6a72
MT		 1412 case KVM_CAP_PV_MMU: /* obsolete */
1413 r = 0;
2f333bcb 1414 break;
62c476c7 1415 case KVM_CAP_IOMMU:
19de40a8 1416 r = iommu_found();
62c476c7 1417 break;
890ca9ae
HY		 1418 case KVM_CAP_MCE:
1419 r = KVM_MAX_MCE_BANKS;
1420 break;
018d00d2
ZX		 1421 default:
1422 r = 0;
1423 break;
1424 }
1425 return r;
1426
1427}
1428
043405e1
CO		 1429long kvm_arch_dev_ioctl(struct file *filp,
1430 unsigned int ioctl, unsigned long arg)
1431{
1432 void __user *argp = (void __user *)arg;
1433 long r;
1434
1435 switch (ioctl) {
1436 case KVM_GET_MSR_INDEX_LIST: {
1437 struct kvm_msr_list __user *user_msr_list = argp;
1438 struct kvm_msr_list msr_list;
1439 unsigned n;
1440
1441 r = -EFAULT;
1442 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1443 goto out;
1444 n = msr_list.nmsrs;
1445 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1446 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1447 goto out;
1448 r = -E2BIG;
e125e7b6 1449 if (n < msr_list.nmsrs)
043405e1
CO		 1450 goto out;
1451 r = -EFAULT;
1452 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1453 num_msrs_to_save * sizeof(u32)))
1454 goto out;
e125e7b6 1455 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 1456 &emulated_msrs,
1457 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1458 goto out;
1459 r = 0;
1460 break;
1461 }
674eea0f
AK		 1462 case KVM_GET_SUPPORTED_CPUID: {
1463 struct kvm_cpuid2 __user *cpuid_arg = argp;
1464 struct kvm_cpuid2 cpuid;
1465
1466 r = -EFAULT;
1467 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1468 goto out;
1469 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 1470 cpuid_arg->entries);
674eea0f
AK		 1471 if (r)
1472 goto out;
1473
1474 r = -EFAULT;
1475 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1476 goto out;
1477 r = 0;
1478 break;
1479 }
890ca9ae
HY		 1480 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
1481 u64 mce_cap;
1482
1483 mce_cap = KVM_MCE_CAP_SUPPORTED;
1484 r = -EFAULT;
1485 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
1486 goto out;
1487 r = 0;
1488 break;
1489 }
043405e1
CO		 1490 default:
1491 r = -EINVAL;
1492 }
1493out:
1494 return r;
1495}
1496
313a3dc7
CO		 1497void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1498{
1499 kvm_x86_ops->vcpu_load(vcpu, cpu);
6b7d7e76
ZA		 1500 if (unlikely(per_cpu(cpu_tsc_khz, cpu) == 0)) {
1501 unsigned long khz = cpufreq_quick_get(cpu);
1502 if (!khz)
1503 khz = tsc_khz;
1504 per_cpu(cpu_tsc_khz, cpu) = khz;
1505 }
c8076604 1506 kvm_request_guest_time_update(vcpu);
313a3dc7
CO		 1507}
1508
1509void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1510{
1511 kvm_x86_ops->vcpu_put(vcpu);
9327fd11 1512 kvm_put_guest_fpu(vcpu);
313a3dc7
CO		 1513}
1514
07716717 1515static int is_efer_nx(void)
313a3dc7 1516{
e286e86e 1517 unsigned long long efer = 0;
313a3dc7 1518
e286e86e 1519 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 1520 return efer & EFER_NX;
1521}
1522
1523static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1524{
1525 int i;
1526 struct kvm_cpuid_entry2 *e, *entry;
1527
313a3dc7 1528 entry = NULL;
ad312c7c
ZX		 1529 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1530 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 1531 if (e->function == 0x80000001) {
1532 entry = e;
1533 break;
1534 }
1535 }
07716717 1536 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 1537 entry->edx &= ~(1 << 20);
1538 printk(KERN_INFO "kvm: guest NX capability removed\n");
1539 }
1540}
1541
07716717 1542/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 1543static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1544 struct kvm_cpuid *cpuid,
1545 struct kvm_cpuid_entry __user *entries)
07716717
DK		 1546{
1547 int r, i;
1548 struct kvm_cpuid_entry *cpuid_entries;
1549
1550 r = -E2BIG;
1551 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1552 goto out;
1553 r = -ENOMEM;
1554 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1555 if (!cpuid_entries)
1556 goto out;
1557 r = -EFAULT;
1558 if (copy_from_user(cpuid_entries, entries,
1559 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1560 goto out_free;
1561 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 1562 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1563 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1564 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1565 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1566 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1567 vcpu->arch.cpuid_entries[i].index = 0;
1568 vcpu->arch.cpuid_entries[i].flags = 0;
1569 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1570 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1571 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1572 }
1573 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 1574 cpuid_fix_nx_cap(vcpu);
1575 r = 0;
fc61b800 1576 kvm_apic_set_version(vcpu);
0e851880 1577 kvm_x86_ops->cpuid_update(vcpu);
07716717
DK		 1578
1579out_free:
1580 vfree(cpuid_entries);
1581out:
1582 return r;
1583}
1584
1585static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1586 struct kvm_cpuid2 *cpuid,
1587 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 1588{
1589 int r;
1590
1591 r = -E2BIG;
1592 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1593 goto out;
1594 r = -EFAULT;
ad312c7c 1595 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 1596 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 1597 goto out;
ad312c7c 1598 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 1599 kvm_apic_set_version(vcpu);
0e851880 1600 kvm_x86_ops->cpuid_update(vcpu);
313a3dc7
CO		 1601 return 0;
1602
1603out:
1604 return r;
1605}
1606
07716717 1607static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1608 struct kvm_cpuid2 *cpuid,
1609 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1610{
1611 int r;
1612
1613 r = -E2BIG;
ad312c7c 1614 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 1615 goto out;
1616 r = -EFAULT;
ad312c7c 1617 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 1618 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1619 goto out;
1620 return 0;
1621
1622out:
ad312c7c 1623 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 1624 return r;
1625}
1626
07716717 1627static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 1628 u32 index)
07716717
DK		 1629{
1630 entry->function = function;
1631 entry->index = index;
1632 cpuid_count(entry->function, entry->index,
19355475 1633 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 1634 entry->flags = 0;
1635}
1636
7faa4ee1
AK		 1637#define F(x) bit(X86_FEATURE_##x)
1638
07716717
DK		 1639static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1640 u32 index, int *nent, int maxnent)
1641{
7faa4ee1 1642 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
344f414f 1643 unsigned f_gbpages = kvm_x86_ops->gb_page_enable() ? F(GBPAGES) : 0;
07716717 1644#ifdef CONFIG_X86_64
7faa4ee1
AK		 1645 unsigned f_lm = F(LM);
1646#else
1647 unsigned f_lm = 0;
07716717 1648#endif
4e47c7a6 1649 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
7faa4ee1
AK		 1650
1651 /* cpuid 1.edx */
1652 const u32 kvm_supported_word0_x86_features =
1653 F(FPU) | F(VME) | F(DE) | F(PSE) |
1654 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1655 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
1656 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1657 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
1658 0 /* Reserved, DS, ACPI */ | F(MMX) |
1659 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
1660 0 /* HTT, TM, Reserved, PBE */;
1661 /* cpuid 0x80000001.edx */
1662 const u32 kvm_supported_word1_x86_features =
1663 F(FPU) | F(VME) | F(DE) | F(PSE) |
1664 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1665 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
1666 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1667 F(PAT) | F(PSE36) | 0 /* Reserved */ |
1668 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
4e47c7a6 1669 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
7faa4ee1
AK		 1670 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
1671 /* cpuid 1.ecx */
1672 const u32 kvm_supported_word4_x86_features =
d149c731
AK		 1673 F(XMM3) | 0 /* Reserved, DTES64, MONITOR */ |
1674 0 /* DS-CPL, VMX, SMX, EST */ |
1675 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
1676 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
1677 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 1678 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
d149c731 1679 0 /* Reserved, XSAVE, OSXSAVE */;
7faa4ee1 1680 /* cpuid 0x80000001.ecx */
07716717 1681 const u32 kvm_supported_word6_x86_features =
7faa4ee1
AK		 1682 F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ |
1683 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
1684 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
1685 0 /* SKINIT */ | 0 /* WDT */;
07716717 1686
19355475 1687 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 1688 get_cpu();
1689 do_cpuid_1_ent(entry, function, index);
1690 ++*nent;
1691
1692 switch (function) {
1693 case 0:
1694 entry->eax = min(entry->eax, (u32)0xb);
1695 break;
1696 case 1:
1697 entry->edx &= kvm_supported_word0_x86_features;
7faa4ee1 1698 entry->ecx &= kvm_supported_word4_x86_features;
0d1de2d9
GN		 1699 /* we support x2apic emulation even if host does not support
1700 * it since we emulate x2apic in software */
1701 entry->ecx |= F(X2APIC);
07716717
DK		 1702 break;
1703 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1704 * may return different values. This forces us to get_cpu() before
1705 * issuing the first command, and also to emulate this annoying behavior
1706 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1707 case 2: {
1708 int t, times = entry->eax & 0xff;
1709
1710 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 1711 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 1712 for (t = 1; t < times && *nent < maxnent; ++t) {
1713 do_cpuid_1_ent(&entry[t], function, 0);
1714 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1715 ++*nent;
1716 }
1717 break;
1718 }
1719 /* function 4 and 0xb have additional index. */
1720 case 4: {
14af3f3c 1721 int i, cache_type;
07716717
DK		 1722
1723 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1724 /* read more entries until cache_type is zero */
14af3f3c
HH		 1725 for (i = 1; *nent < maxnent; ++i) {
1726 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 1727 if (!cache_type)
1728 break;
14af3f3c
HH		 1729 do_cpuid_1_ent(&entry[i], function, i);
1730 entry[i].flags |=
07716717
DK		 1731 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1732 ++*nent;
1733 }
1734 break;
1735 }
1736 case 0xb: {
14af3f3c 1737 int i, level_type;
07716717
DK		 1738
1739 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1740 /* read more entries until level_type is zero */
14af3f3c 1741 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 1742 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 1743 if (!level_type)
1744 break;
14af3f3c
HH		 1745 do_cpuid_1_ent(&entry[i], function, i);
1746 entry[i].flags |=
07716717
DK		 1747 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1748 ++*nent;
1749 }
1750 break;
1751 }
1752 case 0x80000000:
1753 entry->eax = min(entry->eax, 0x8000001a);
1754 break;
1755 case 0x80000001:
1756 entry->edx &= kvm_supported_word1_x86_features;
1757 entry->ecx &= kvm_supported_word6_x86_features;
1758 break;
1759 }
1760 put_cpu();
1761}
1762
7faa4ee1
AK		 1763#undef F
1764
674eea0f 1765static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 1766 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1767{
1768 struct kvm_cpuid_entry2 *cpuid_entries;
1769 int limit, nent = 0, r = -E2BIG;
1770 u32 func;
1771
1772 if (cpuid->nent < 1)
1773 goto out;
6a544355
AK		 1774 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1775 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 1776 r = -ENOMEM;
1777 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
1778 if (!cpuid_entries)
1779 goto out;
1780
1781 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
1782 limit = cpuid_entries[0].eax;
1783 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
1784 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1785 &nent, cpuid->nent);
07716717
DK		 1786 r = -E2BIG;
1787 if (nent >= cpuid->nent)
1788 goto out_free;
1789
1790 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
1791 limit = cpuid_entries[nent - 1].eax;
1792 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
1793 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1794 &nent, cpuid->nent);
cb007648
MM		 1795 r = -E2BIG;
1796 if (nent >= cpuid->nent)
1797 goto out_free;
1798
07716717
DK		 1799 r = -EFAULT;
1800 if (copy_to_user(entries, cpuid_entries,
19355475 1801 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1802 goto out_free;
1803 cpuid->nent = nent;
1804 r = 0;
1805
1806out_free:
1807 vfree(cpuid_entries);
1808out:
1809 return r;
1810}
1811
313a3dc7
CO		 1812static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
1813 struct kvm_lapic_state *s)
1814{
1815 vcpu_load(vcpu);
ad312c7c 1816 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 1817 vcpu_put(vcpu);
1818
1819 return 0;
1820}
1821
1822static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
1823 struct kvm_lapic_state *s)
1824{
1825 vcpu_load(vcpu);
ad312c7c 1826 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 1827 kvm_apic_post_state_restore(vcpu);
cb142eb7 1828 update_cr8_intercept(vcpu);
313a3dc7
CO		 1829 vcpu_put(vcpu);
1830
1831 return 0;
1832}
1833
f77bc6a4
ZX		 1834static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
1835 struct kvm_interrupt *irq)
1836{
1837 if (irq->irq < 0 || irq->irq >= 256)
1838 return -EINVAL;
1839 if (irqchip_in_kernel(vcpu->kvm))
1840 return -ENXIO;
1841 vcpu_load(vcpu);
1842
66fd3f7f 1843 kvm_queue_interrupt(vcpu, irq->irq, false);
f77bc6a4
ZX		 1844
1845 vcpu_put(vcpu);
1846
1847 return 0;
1848}
1849
c4abb7c9
JK		 1850static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
1851{
1852 vcpu_load(vcpu);
1853 kvm_inject_nmi(vcpu);
1854 vcpu_put(vcpu);
1855
1856 return 0;
1857}
1858
b209749f
AK		 1859static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
1860 struct kvm_tpr_access_ctl *tac)
1861{
1862 if (tac->flags)
1863 return -EINVAL;
1864 vcpu->arch.tpr_access_reporting = !!tac->enabled;
1865 return 0;
1866}
1867
890ca9ae
HY		 1868static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
1869 u64 mcg_cap)
1870{
1871 int r;
1872 unsigned bank_num = mcg_cap & 0xff, bank;
1873
1874 r = -EINVAL;
a9e38c3e 1875 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 1876 goto out;
1877 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
1878 goto out;
1879 r = 0;
1880 vcpu->arch.mcg_cap = mcg_cap;
1881 /* Init IA32_MCG_CTL to all 1s */
1882 if (mcg_cap & MCG_CTL_P)
1883 vcpu->arch.mcg_ctl = ~(u64)0;
1884 /* Init IA32_MCi_CTL to all 1s */
1885 for (bank = 0; bank < bank_num; bank++)
1886 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
1887out:
1888 return r;
1889}
1890
1891static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
1892 struct kvm_x86_mce *mce)
1893{
1894 u64 mcg_cap = vcpu->arch.mcg_cap;
1895 unsigned bank_num = mcg_cap & 0xff;
1896 u64 *banks = vcpu->arch.mce_banks;
1897
1898 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
1899 return -EINVAL;
1900 /*
1901 * if IA32_MCG_CTL is not all 1s, the uncorrected error
1902 * reporting is disabled
1903 */
1904 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
1905 vcpu->arch.mcg_ctl != ~(u64)0)
1906 return 0;
1907 banks += 4 * mce->bank;
1908 /*
1909 * if IA32_MCi_CTL is not all 1s, the uncorrected error
1910 * reporting is disabled for the bank
1911 */
1912 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
1913 return 0;
1914 if (mce->status & MCI_STATUS_UC) {
1915 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 1916 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
890ca9ae
HY		 1917 printk(KERN_DEBUG "kvm: set_mce: "
1918 "injects mce exception while "
1919 "previous one is in progress!\n");
1920 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
1921 return 0;
1922 }
1923 if (banks[1] & MCI_STATUS_VAL)
1924 mce->status |= MCI_STATUS_OVER;
1925 banks[2] = mce->addr;
1926 banks[3] = mce->misc;
1927 vcpu->arch.mcg_status = mce->mcg_status;
1928 banks[1] = mce->status;
1929 kvm_queue_exception(vcpu, MC_VECTOR);
1930 } else if (!(banks[1] & MCI_STATUS_VAL)
1931 || !(banks[1] & MCI_STATUS_UC)) {
1932 if (banks[1] & MCI_STATUS_VAL)
1933 mce->status |= MCI_STATUS_OVER;
1934 banks[2] = mce->addr;
1935 banks[3] = mce->misc;
1936 banks[1] = mce->status;
1937 } else
1938 banks[1] |= MCI_STATUS_OVER;
1939 return 0;
1940}
1941
3cfc3092
JK		 1942static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
1943 struct kvm_vcpu_events *events)
1944{
1945 vcpu_load(vcpu);
1946
1947 events->exception.injected = vcpu->arch.exception.pending;
1948 events->exception.nr = vcpu->arch.exception.nr;
1949 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
1950 events->exception.error_code = vcpu->arch.exception.error_code;
1951
1952 events->interrupt.injected = vcpu->arch.interrupt.pending;
1953 events->interrupt.nr = vcpu->arch.interrupt.nr;
1954 events->interrupt.soft = vcpu->arch.interrupt.soft;
1955
1956 events->nmi.injected = vcpu->arch.nmi_injected;
1957 events->nmi.pending = vcpu->arch.nmi_pending;
1958 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
1959
1960 events->sipi_vector = vcpu->arch.sipi_vector;
1961
dab4b911
JK		 1962 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
1963 | KVM_VCPUEVENT_VALID_SIPI_VECTOR);
3cfc3092
JK		 1964
1965 vcpu_put(vcpu);
1966}
1967
1968static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
1969 struct kvm_vcpu_events *events)
1970{
dab4b911
JK		 1971 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
1972 | KVM_VCPUEVENT_VALID_SIPI_VECTOR))
3cfc3092
JK		 1973 return -EINVAL;
1974
1975 vcpu_load(vcpu);
1976
1977 vcpu->arch.exception.pending = events->exception.injected;
1978 vcpu->arch.exception.nr = events->exception.nr;
1979 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
1980 vcpu->arch.exception.error_code = events->exception.error_code;
1981
1982 vcpu->arch.interrupt.pending = events->interrupt.injected;
1983 vcpu->arch.interrupt.nr = events->interrupt.nr;
1984 vcpu->arch.interrupt.soft = events->interrupt.soft;
1985 if (vcpu->arch.interrupt.pending && irqchip_in_kernel(vcpu->kvm))
1986 kvm_pic_clear_isr_ack(vcpu->kvm);
1987
1988 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 1989 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
1990 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 1991 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
1992
dab4b911
JK		 1993 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
1994 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092
JK		 1995
1996 vcpu_put(vcpu);
1997
1998 return 0;
1999}
2000
313a3dc7
CO		 2001long kvm_arch_vcpu_ioctl(struct file *filp,
2002 unsigned int ioctl, unsigned long arg)
2003{
2004 struct kvm_vcpu *vcpu = filp->private_data;
2005 void __user *argp = (void __user *)arg;
2006 int r;
b772ff36 2007 struct kvm_lapic_state *lapic = NULL;
313a3dc7
CO		 2008
2009 switch (ioctl) {
2010 case KVM_GET_LAPIC: {
2204ae3c
MT		 2011 r = -EINVAL;
2012 if (!vcpu->arch.apic)
2013 goto out;
b772ff36 2014 lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2015
b772ff36
DH		 2016 r = -ENOMEM;
2017 if (!lapic)
2018 goto out;
2019 r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic);
313a3dc7
CO		 2020 if (r)
2021 goto out;
2022 r = -EFAULT;
b772ff36 2023 if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2024 goto out;
2025 r = 0;
2026 break;
2027 }
2028 case KVM_SET_LAPIC: {
2204ae3c
MT		 2029 r = -EINVAL;
2030 if (!vcpu->arch.apic)
2031 goto out;
b772ff36
DH		 2032 lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
2033 r = -ENOMEM;
2034 if (!lapic)
2035 goto out;
313a3dc7 2036 r = -EFAULT;
b772ff36 2037 if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 2038 goto out;
b772ff36 2039 r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic);
313a3dc7
CO		 2040 if (r)
2041 goto out;
2042 r = 0;
2043 break;
2044 }
f77bc6a4
ZX		 2045 case KVM_INTERRUPT: {
2046 struct kvm_interrupt irq;
2047
2048 r = -EFAULT;
2049 if (copy_from_user(&irq, argp, sizeof irq))
2050 goto out;
2051 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2052 if (r)
2053 goto out;
2054 r = 0;
2055 break;
2056 }
c4abb7c9
JK		 2057 case KVM_NMI: {
2058 r = kvm_vcpu_ioctl_nmi(vcpu);
2059 if (r)
2060 goto out;
2061 r = 0;
2062 break;
2063 }
313a3dc7
CO		 2064 case KVM_SET_CPUID: {
2065 struct kvm_cpuid __user *cpuid_arg = argp;
2066 struct kvm_cpuid cpuid;
2067
2068 r = -EFAULT;
2069 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2070 goto out;
2071 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2072 if (r)
2073 goto out;
2074 break;
2075 }
07716717
DK		 2076 case KVM_SET_CPUID2: {
2077 struct kvm_cpuid2 __user *cpuid_arg = argp;
2078 struct kvm_cpuid2 cpuid;
2079
2080 r = -EFAULT;
2081 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2082 goto out;
2083 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2084 cpuid_arg->entries);
07716717
DK		 2085 if (r)
2086 goto out;
2087 break;
2088 }
2089 case KVM_GET_CPUID2: {
2090 struct kvm_cpuid2 __user *cpuid_arg = argp;
2091 struct kvm_cpuid2 cpuid;
2092
2093 r = -EFAULT;
2094 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2095 goto out;
2096 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2097 cpuid_arg->entries);
07716717
DK		 2098 if (r)
2099 goto out;
2100 r = -EFAULT;
2101 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2102 goto out;
2103 r = 0;
2104 break;
2105 }
313a3dc7
CO		 2106 case KVM_GET_MSRS:
2107 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2108 break;
2109 case KVM_SET_MSRS:
2110 r = msr_io(vcpu, argp, do_set_msr, 0);
2111 break;
b209749f
AK		 2112 case KVM_TPR_ACCESS_REPORTING: {
2113 struct kvm_tpr_access_ctl tac;
2114
2115 r = -EFAULT;
2116 if (copy_from_user(&tac, argp, sizeof tac))
2117 goto out;
2118 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2119 if (r)
2120 goto out;
2121 r = -EFAULT;
2122 if (copy_to_user(argp, &tac, sizeof tac))
2123 goto out;
2124 r = 0;
2125 break;
2126 };
b93463aa
AK		 2127 case KVM_SET_VAPIC_ADDR: {
2128 struct kvm_vapic_addr va;
2129
2130 r = -EINVAL;
2131 if (!irqchip_in_kernel(vcpu->kvm))
2132 goto out;
2133 r = -EFAULT;
2134 if (copy_from_user(&va, argp, sizeof va))
2135 goto out;
2136 r = 0;
2137 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2138 break;
2139 }
890ca9ae
HY		 2140 case KVM_X86_SETUP_MCE: {
2141 u64 mcg_cap;
2142
2143 r = -EFAULT;
2144 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2145 goto out;
2146 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2147 break;
2148 }
2149 case KVM_X86_SET_MCE: {
2150 struct kvm_x86_mce mce;
2151
2152 r = -EFAULT;
2153 if (copy_from_user(&mce, argp, sizeof mce))
2154 goto out;
2155 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2156 break;
2157 }
3cfc3092
JK		 2158 case KVM_GET_VCPU_EVENTS: {
2159 struct kvm_vcpu_events events;
2160
2161 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2162
2163 r = -EFAULT;
2164 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2165 break;
2166 r = 0;
2167 break;
2168 }
2169 case KVM_SET_VCPU_EVENTS: {
2170 struct kvm_vcpu_events events;
2171
2172 r = -EFAULT;
2173 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2174 break;
2175
2176 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2177 break;
2178 }
313a3dc7
CO		 2179 default:
2180 r = -EINVAL;
2181 }
2182out:
7a6ce84c 2183 kfree(lapic);
313a3dc7
CO		 2184 return r;
2185}
2186
1fe779f8
CO		 2187static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2188{
2189 int ret;
2190
2191 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2192 return -1;
2193 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2194 return ret;
2195}
2196
b927a3ce
SY		 2197static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2198 u64 ident_addr)
2199{
2200 kvm->arch.ept_identity_map_addr = ident_addr;
2201 return 0;
2202}
2203
1fe779f8
CO		 2204static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2205 u32 kvm_nr_mmu_pages)
2206{
2207 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2208 return -EINVAL;
2209
72dc67a6 2210 down_write(&kvm->slots_lock);
7c8a83b7 2211 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 2212
2213 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 2214 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 2215
7c8a83b7 2216 spin_unlock(&kvm->mmu_lock);
72dc67a6 2217 up_write(&kvm->slots_lock);
1fe779f8
CO		 2218 return 0;
2219}
2220
2221static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2222{
f05e70ac 2223 return kvm->arch.n_alloc_mmu_pages;
1fe779f8
CO		 2224}
2225
e9f85cde
ZX		 2226gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
2227{
2228 int i;
2229 struct kvm_mem_alias *alias;
fef9cce0 2230 struct kvm_mem_aliases *aliases = kvm->arch.aliases;
e9f85cde 2231
fef9cce0
MT		 2232 for (i = 0; i < aliases->naliases; ++i) {
2233 alias = &aliases->aliases[i];
e9f85cde
ZX		 2234 if (gfn >= alias->base_gfn
2235 && gfn < alias->base_gfn + alias->npages)
2236 return alias->target_gfn + gfn - alias->base_gfn;
2237 }
2238 return gfn;
2239}
2240
1fe779f8
CO		 2241/*
2242 * Set a new alias region. Aliases map a portion of physical memory into
2243 * another portion. This is useful for memory windows, for example the PC
2244 * VGA region.
2245 */
2246static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
2247 struct kvm_memory_alias *alias)
2248{
2249 int r, n;
2250 struct kvm_mem_alias *p;
fef9cce0 2251 struct kvm_mem_aliases *aliases;
1fe779f8
CO		 2252
2253 r = -EINVAL;
2254 /* General sanity checks */
2255 if (alias->memory_size & (PAGE_SIZE - 1))
2256 goto out;
2257 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
2258 goto out;
2259 if (alias->slot >= KVM_ALIAS_SLOTS)
2260 goto out;
2261 if (alias->guest_phys_addr + alias->memory_size
2262 < alias->guest_phys_addr)
2263 goto out;
2264 if (alias->target_phys_addr + alias->memory_size
2265 < alias->target_phys_addr)
2266 goto out;
2267
72dc67a6 2268 down_write(&kvm->slots_lock);
a1708ce8 2269 spin_lock(&kvm->mmu_lock);
1fe779f8 2270
fef9cce0
MT		 2271 aliases = kvm->arch.aliases;
2272
2273 p = &aliases->aliases[alias->slot];
1fe779f8
CO		 2274 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
2275 p->npages = alias->memory_size >> PAGE_SHIFT;
2276 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
2277
2278 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
fef9cce0 2279 if (aliases->aliases[n - 1].npages)
1fe779f8 2280 break;
fef9cce0 2281 aliases->naliases = n;
1fe779f8 2282
a1708ce8 2283 spin_unlock(&kvm->mmu_lock);
1fe779f8
CO		 2284 kvm_mmu_zap_all(kvm);
2285
72dc67a6 2286 up_write(&kvm->slots_lock);
1fe779f8
CO		 2287
2288 return 0;
2289
2290out:
2291 return r;
2292}
2293
2294static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2295{
2296 int r;
2297
2298 r = 0;
2299 switch (chip->chip_id) {
2300 case KVM_IRQCHIP_PIC_MASTER:
2301 memcpy(&chip->chip.pic,
2302 &pic_irqchip(kvm)->pics[0],
2303 sizeof(struct kvm_pic_state));
2304 break;
2305 case KVM_IRQCHIP_PIC_SLAVE:
2306 memcpy(&chip->chip.pic,
2307 &pic_irqchip(kvm)->pics[1],
2308 sizeof(struct kvm_pic_state));
2309 break;
2310 case KVM_IRQCHIP_IOAPIC:
eba0226b 2311 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2312 break;
2313 default:
2314 r = -EINVAL;
2315 break;
2316 }
2317 return r;
2318}
2319
2320static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2321{
2322 int r;
2323
2324 r = 0;
2325 switch (chip->chip_id) {
2326 case KVM_IRQCHIP_PIC_MASTER:
894a9c55 2327 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2328 memcpy(&pic_irqchip(kvm)->pics[0],
2329 &chip->chip.pic,
2330 sizeof(struct kvm_pic_state));
894a9c55 2331 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2332 break;
2333 case KVM_IRQCHIP_PIC_SLAVE:
894a9c55 2334 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2335 memcpy(&pic_irqchip(kvm)->pics[1],
2336 &chip->chip.pic,
2337 sizeof(struct kvm_pic_state));
894a9c55 2338 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2339 break;
2340 case KVM_IRQCHIP_IOAPIC:
eba0226b 2341 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2342 break;
2343 default:
2344 r = -EINVAL;
2345 break;
2346 }
2347 kvm_pic_update_irq(pic_irqchip(kvm));
2348 return r;
2349}
2350
e0f63cb9
SY		 2351static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2352{
2353 int r = 0;
2354
894a9c55 2355 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2356 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 2357 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2358 return r;
2359}
2360
2361static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2362{
2363 int r = 0;
2364
894a9c55 2365 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2366 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 2367 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
2368 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2369 return r;
2370}
2371
2372static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2373{
2374 int r = 0;
2375
2376 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2377 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
2378 sizeof(ps->channels));
2379 ps->flags = kvm->arch.vpit->pit_state.flags;
2380 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2381 return r;
2382}
2383
2384static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2385{
2386 int r = 0, start = 0;
2387 u32 prev_legacy, cur_legacy;
2388 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2389 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
2390 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
2391 if (!prev_legacy && cur_legacy)
2392 start = 1;
2393 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
2394 sizeof(kvm->arch.vpit->pit_state.channels));
2395 kvm->arch.vpit->pit_state.flags = ps->flags;
2396 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 2397 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2398 return r;
2399}
2400
52d939a0
MT		 2401static int kvm_vm_ioctl_reinject(struct kvm *kvm,
2402 struct kvm_reinject_control *control)
2403{
2404 if (!kvm->arch.vpit)
2405 return -ENXIO;
894a9c55 2406 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 2407 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 2408 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 2409 return 0;
2410}
2411
5bb064dc
ZX		 2412/*
2413 * Get (and clear) the dirty memory log for a memory slot.
2414 */
2415int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
2416 struct kvm_dirty_log *log)
2417{
b050b015 2418 int r, n, i;
5bb064dc 2419 struct kvm_memory_slot *memslot;
b050b015
MT		 2420 unsigned long is_dirty = 0;
2421 unsigned long *dirty_bitmap = NULL;
5bb064dc 2422
72dc67a6 2423 down_write(&kvm->slots_lock);
5bb064dc 2424
b050b015
MT		 2425 r = -EINVAL;
2426 if (log->slot >= KVM_MEMORY_SLOTS)
2427 goto out;
2428
2429 memslot = &kvm->memslots->memslots[log->slot];
2430 r = -ENOENT;
2431 if (!memslot->dirty_bitmap)
2432 goto out;
2433
2434 n = ALIGN(memslot->npages, BITS_PER_LONG) / 8;
2435
2436 r = -ENOMEM;
2437 dirty_bitmap = vmalloc(n);
2438 if (!dirty_bitmap)
5bb064dc 2439 goto out;
b050b015
MT		 2440 memset(dirty_bitmap, 0, n);
2441
2442 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
2443 is_dirty = memslot->dirty_bitmap[i];
5bb064dc
ZX		 2444
2445 /* If nothing is dirty, don't bother messing with page tables. */
2446 if (is_dirty) {
b050b015
MT		 2447 struct kvm_memslots *slots, *old_slots;
2448
7c8a83b7 2449 spin_lock(&kvm->mmu_lock);
5bb064dc 2450 kvm_mmu_slot_remove_write_access(kvm, log->slot);
7c8a83b7 2451 spin_unlock(&kvm->mmu_lock);
b050b015
MT		 2452
2453 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
2454 if (!slots)
2455 goto out_free;
2456
2457 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
2458 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
2459
2460 old_slots = kvm->memslots;
2461 rcu_assign_pointer(kvm->memslots, slots);
2462 synchronize_srcu_expedited(&kvm->srcu);
2463 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
2464 kfree(old_slots);
5bb064dc 2465 }
b050b015 2466
5bb064dc 2467 r = 0;
b050b015
MT		 2468 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n))
2469 r = -EFAULT;
2470out_free:
2471 vfree(dirty_bitmap);
5bb064dc 2472out:
72dc67a6 2473 up_write(&kvm->slots_lock);
5bb064dc
ZX		 2474 return r;
2475}
2476
1fe779f8
CO		 2477long kvm_arch_vm_ioctl(struct file *filp,
2478 unsigned int ioctl, unsigned long arg)
2479{
2480 struct kvm *kvm = filp->private_data;
2481 void __user *argp = (void __user *)arg;
367e1319 2482 int r = -ENOTTY;
f0d66275
DH		 2483 /*
2484 * This union makes it completely explicit to gcc-3.x
2485 * that these two variables' stack usage should be
2486 * combined, not added together.
2487 */
2488 union {
2489 struct kvm_pit_state ps;
e9f42757 2490 struct kvm_pit_state2 ps2;
f0d66275 2491 struct kvm_memory_alias alias;
c5ff41ce 2492 struct kvm_pit_config pit_config;
f0d66275 2493 } u;
1fe779f8
CO		 2494
2495 switch (ioctl) {
2496 case KVM_SET_TSS_ADDR:
2497 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
2498 if (r < 0)
2499 goto out;
2500 break;
b927a3ce
SY		 2501 case KVM_SET_IDENTITY_MAP_ADDR: {
2502 u64 ident_addr;
2503
2504 r = -EFAULT;
2505 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
2506 goto out;
2507 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
2508 if (r < 0)
2509 goto out;
2510 break;
2511 }
1fe779f8
CO		 2512 case KVM_SET_MEMORY_REGION: {
2513 struct kvm_memory_region kvm_mem;
2514 struct kvm_userspace_memory_region kvm_userspace_mem;
2515
2516 r = -EFAULT;
2517 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
2518 goto out;
2519 kvm_userspace_mem.slot = kvm_mem.slot;
2520 kvm_userspace_mem.flags = kvm_mem.flags;
2521 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
2522 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
2523 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
2524 if (r)
2525 goto out;
2526 break;
2527 }
2528 case KVM_SET_NR_MMU_PAGES:
2529 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
2530 if (r)
2531 goto out;
2532 break;
2533 case KVM_GET_NR_MMU_PAGES:
2534 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
2535 break;
f0d66275 2536 case KVM_SET_MEMORY_ALIAS:
1fe779f8 2537 r = -EFAULT;
f0d66275 2538 if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias)))
1fe779f8 2539 goto out;
f0d66275 2540 r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias);
1fe779f8
CO		 2541 if (r)
2542 goto out;
2543 break;
3ddea128
MT		 2544 case KVM_CREATE_IRQCHIP: {
2545 struct kvm_pic *vpic;
2546
2547 mutex_lock(&kvm->lock);
2548 r = -EEXIST;
2549 if (kvm->arch.vpic)
2550 goto create_irqchip_unlock;
1fe779f8 2551 r = -ENOMEM;
3ddea128
MT		 2552 vpic = kvm_create_pic(kvm);
2553 if (vpic) {
1fe779f8
CO		 2554 r = kvm_ioapic_init(kvm);
2555 if (r) {
3ddea128
MT		 2556 kfree(vpic);
2557 goto create_irqchip_unlock;
1fe779f8
CO		 2558 }
2559 } else
3ddea128
MT		 2560 goto create_irqchip_unlock;
2561 smp_wmb();
2562 kvm->arch.vpic = vpic;
2563 smp_wmb();
399ec807
AK		 2564 r = kvm_setup_default_irq_routing(kvm);
2565 if (r) {
3ddea128 2566 mutex_lock(&kvm->irq_lock);
399ec807
AK		 2567 kfree(kvm->arch.vpic);
2568 kfree(kvm->arch.vioapic);
3ddea128
MT		 2569 kvm->arch.vpic = NULL;
2570 kvm->arch.vioapic = NULL;
2571 mutex_unlock(&kvm->irq_lock);
399ec807 2572 }
3ddea128
MT		 2573 create_irqchip_unlock:
2574 mutex_unlock(&kvm->lock);
1fe779f8 2575 break;
3ddea128 2576 }
7837699f 2577 case KVM_CREATE_PIT:
c5ff41ce
JK		 2578 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
2579 goto create_pit;
2580 case KVM_CREATE_PIT2:
2581 r = -EFAULT;
2582 if (copy_from_user(&u.pit_config, argp,
2583 sizeof(struct kvm_pit_config)))
2584 goto out;
2585 create_pit:
108b5669 2586 down_write(&kvm->slots_lock);
269e05e4
AK		 2587 r = -EEXIST;
2588 if (kvm->arch.vpit)
2589 goto create_pit_unlock;
7837699f 2590 r = -ENOMEM;
c5ff41ce 2591 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 2592 if (kvm->arch.vpit)
2593 r = 0;
269e05e4 2594 create_pit_unlock:
108b5669 2595 up_write(&kvm->slots_lock);
7837699f 2596 break;
4925663a 2597 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 2598 case KVM_IRQ_LINE: {
2599 struct kvm_irq_level irq_event;
2600
2601 r = -EFAULT;
2602 if (copy_from_user(&irq_event, argp, sizeof irq_event))
2603 goto out;
2604 if (irqchip_in_kernel(kvm)) {
4925663a 2605 __s32 status;
4925663a
GN		 2606 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
2607 irq_event.irq, irq_event.level);
4925663a
GN		 2608 if (ioctl == KVM_IRQ_LINE_STATUS) {
2609 irq_event.status = status;
2610 if (copy_to_user(argp, &irq_event,
2611 sizeof irq_event))
2612 goto out;
2613 }
1fe779f8
CO		 2614 r = 0;
2615 }
2616 break;
2617 }
2618 case KVM_GET_IRQCHIP: {
2619 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2620 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2621
f0d66275
DH		 2622 r = -ENOMEM;
2623 if (!chip)
1fe779f8 2624 goto out;
f0d66275
DH		 2625 r = -EFAULT;
2626 if (copy_from_user(chip, argp, sizeof *chip))
2627 goto get_irqchip_out;
1fe779f8
CO		 2628 r = -ENXIO;
2629 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2630 goto get_irqchip_out;
2631 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 2632 if (r)
f0d66275 2633 goto get_irqchip_out;
1fe779f8 2634 r = -EFAULT;
f0d66275
DH		 2635 if (copy_to_user(argp, chip, sizeof *chip))
2636 goto get_irqchip_out;
1fe779f8 2637 r = 0;
f0d66275
DH		 2638 get_irqchip_out:
2639 kfree(chip);
2640 if (r)
2641 goto out;
1fe779f8
CO		 2642 break;
2643 }
2644 case KVM_SET_IRQCHIP: {
2645 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2646 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2647
f0d66275
DH		 2648 r = -ENOMEM;
2649 if (!chip)
1fe779f8 2650 goto out;
f0d66275
DH		 2651 r = -EFAULT;
2652 if (copy_from_user(chip, argp, sizeof *chip))
2653 goto set_irqchip_out;
1fe779f8
CO		 2654 r = -ENXIO;
2655 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2656 goto set_irqchip_out;
2657 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 2658 if (r)
f0d66275 2659 goto set_irqchip_out;
1fe779f8 2660 r = 0;
f0d66275
DH		 2661 set_irqchip_out:
2662 kfree(chip);
2663 if (r)
2664 goto out;
1fe779f8
CO		 2665 break;
2666 }
e0f63cb9 2667 case KVM_GET_PIT: {
e0f63cb9 2668 r = -EFAULT;
f0d66275 2669 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2670 goto out;
2671 r = -ENXIO;
2672 if (!kvm->arch.vpit)
2673 goto out;
f0d66275 2674 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 2675 if (r)
2676 goto out;
2677 r = -EFAULT;
f0d66275 2678 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2679 goto out;
2680 r = 0;
2681 break;
2682 }
2683 case KVM_SET_PIT: {
e0f63cb9 2684 r = -EFAULT;
f0d66275 2685 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 2686 goto out;
2687 r = -ENXIO;
2688 if (!kvm->arch.vpit)
2689 goto out;
f0d66275 2690 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 2691 if (r)
2692 goto out;
2693 r = 0;
2694 break;
2695 }
e9f42757
BK		 2696 case KVM_GET_PIT2: {
2697 r = -ENXIO;
2698 if (!kvm->arch.vpit)
2699 goto out;
2700 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
2701 if (r)
2702 goto out;
2703 r = -EFAULT;
2704 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
2705 goto out;
2706 r = 0;
2707 break;
2708 }
2709 case KVM_SET_PIT2: {
2710 r = -EFAULT;
2711 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
2712 goto out;
2713 r = -ENXIO;
2714 if (!kvm->arch.vpit)
2715 goto out;
2716 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
2717 if (r)
2718 goto out;
2719 r = 0;
2720 break;
2721 }
52d939a0
MT		 2722 case KVM_REINJECT_CONTROL: {
2723 struct kvm_reinject_control control;
2724 r = -EFAULT;
2725 if (copy_from_user(&control, argp, sizeof(control)))
2726 goto out;
2727 r = kvm_vm_ioctl_reinject(kvm, &control);
2728 if (r)
2729 goto out;
2730 r = 0;
2731 break;
2732 }
ffde22ac
ES		 2733 case KVM_XEN_HVM_CONFIG: {
2734 r = -EFAULT;
2735 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
2736 sizeof(struct kvm_xen_hvm_config)))
2737 goto out;
2738 r = -EINVAL;
2739 if (kvm->arch.xen_hvm_config.flags)
2740 goto out;
2741 r = 0;
2742 break;
2743 }
afbcf7ab
GC		 2744 case KVM_SET_CLOCK: {
2745 struct timespec now;
2746 struct kvm_clock_data user_ns;
2747 u64 now_ns;
2748 s64 delta;
2749
2750 r = -EFAULT;
2751 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
2752 goto out;
2753
2754 r = -EINVAL;
2755 if (user_ns.flags)
2756 goto out;
2757
2758 r = 0;
2759 ktime_get_ts(&now);
2760 now_ns = timespec_to_ns(&now);
2761 delta = user_ns.clock - now_ns;
2762 kvm->arch.kvmclock_offset = delta;
2763 break;
2764 }
2765 case KVM_GET_CLOCK: {
2766 struct timespec now;
2767 struct kvm_clock_data user_ns;
2768 u64 now_ns;
2769
2770 ktime_get_ts(&now);
2771 now_ns = timespec_to_ns(&now);
2772 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
2773 user_ns.flags = 0;
2774
2775 r = -EFAULT;
2776 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
2777 goto out;
2778 r = 0;
2779 break;
2780 }
2781
1fe779f8
CO		 2782 default:
2783 ;
2784 }
2785out:
2786 return r;
2787}
2788
a16b043c 2789static void kvm_init_msr_list(void)
043405e1
CO		 2790{
2791 u32 dummy[2];
2792 unsigned i, j;
2793
e3267cbb
GC		 2794 /* skip the first msrs in the list. KVM-specific */
2795 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 2796 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
2797 continue;
2798 if (j < i)
2799 msrs_to_save[j] = msrs_to_save[i];
2800 j++;
2801 }
2802 num_msrs_to_save = j;
2803}
2804
bda9020e
MT		 2805static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
2806 const void *v)
bbd9b64e 2807{
bda9020e
MT		 2808 if (vcpu->arch.apic &&
2809 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
2810 return 0;
bbd9b64e 2811
bda9020e 2812 return kvm_io_bus_write(&vcpu->kvm->mmio_bus, addr, len, v);
bbd9b64e
CO		 2813}
2814
bda9020e 2815static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 2816{
bda9020e
MT		 2817 if (vcpu->arch.apic &&
2818 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
2819 return 0;
bbd9b64e 2820
bda9020e 2821 return kvm_io_bus_read(&vcpu->kvm->mmio_bus, addr, len, v);
bbd9b64e
CO		 2822}
2823
cded19f3
HE		 2824static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
2825 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 2826{
2827 void *data = val;
10589a46 2828 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 2829
2830 while (bytes) {
ad312c7c 2831 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e 2832 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 2833 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 2834 int ret;
2835
10589a46
MT		 2836 if (gpa == UNMAPPED_GVA) {
2837 r = X86EMUL_PROPAGATE_FAULT;
2838 goto out;
2839 }
77c2002e 2840 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46
MT		 2841 if (ret < 0) {
2842 r = X86EMUL_UNHANDLEABLE;
2843 goto out;
2844 }
bbd9b64e 2845
77c2002e
IE		 2846 bytes -= toread;
2847 data += toread;
2848 addr += toread;
bbd9b64e 2849 }
10589a46 2850out:
10589a46 2851 return r;
bbd9b64e 2852}
77c2002e 2853
cded19f3
HE		 2854static int kvm_write_guest_virt(gva_t addr, void *val, unsigned int bytes,
2855 struct kvm_vcpu *vcpu)
77c2002e
IE		 2856{
2857 void *data = val;
2858 int r = X86EMUL_CONTINUE;
2859
2860 while (bytes) {
2861 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2862 unsigned offset = addr & (PAGE_SIZE-1);
2863 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
2864 int ret;
2865
2866 if (gpa == UNMAPPED_GVA) {
2867 r = X86EMUL_PROPAGATE_FAULT;
2868 goto out;
2869 }
2870 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
2871 if (ret < 0) {
2872 r = X86EMUL_UNHANDLEABLE;
2873 goto out;
2874 }
2875
2876 bytes -= towrite;
2877 data += towrite;
2878 addr += towrite;
2879 }
2880out:
2881 return r;
2882}
2883
bbd9b64e 2884
bbd9b64e
CO		 2885static int emulator_read_emulated(unsigned long addr,
2886 void *val,
2887 unsigned int bytes,
2888 struct kvm_vcpu *vcpu)
2889{
bbd9b64e
CO		 2890 gpa_t gpa;
2891
2892 if (vcpu->mmio_read_completed) {
2893 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 2894 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
2895 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 2896 vcpu->mmio_read_completed = 0;
2897 return X86EMUL_CONTINUE;
2898 }
2899
ad312c7c 2900 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2901
2902 /* For APIC access vmexit */
2903 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2904 goto mmio;
2905
77c2002e
IE		 2906 if (kvm_read_guest_virt(addr, val, bytes, vcpu)
2907 == X86EMUL_CONTINUE)
bbd9b64e
CO		 2908 return X86EMUL_CONTINUE;
2909 if (gpa == UNMAPPED_GVA)
2910 return X86EMUL_PROPAGATE_FAULT;
2911
2912mmio:
2913 /*
2914 * Is this MMIO handled locally?
2915 */
aec51dc4
AK		 2916 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
2917 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 2918 return X86EMUL_CONTINUE;
2919 }
aec51dc4
AK		 2920
2921 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 2922
2923 vcpu->mmio_needed = 1;
2924 vcpu->mmio_phys_addr = gpa;
2925 vcpu->mmio_size = bytes;
2926 vcpu->mmio_is_write = 0;
2927
2928 return X86EMUL_UNHANDLEABLE;
2929}
2930
3200f405 2931int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 2932 const void *val, int bytes)
bbd9b64e
CO		 2933{
2934 int ret;
2935
2936 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 2937 if (ret < 0)
bbd9b64e 2938 return 0;
ad218f85 2939 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 2940 return 1;
2941}
2942
2943static int emulator_write_emulated_onepage(unsigned long addr,
2944 const void *val,
2945 unsigned int bytes,
2946 struct kvm_vcpu *vcpu)
2947{
10589a46
MT		 2948 gpa_t gpa;
2949
10589a46 2950 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2951
2952 if (gpa == UNMAPPED_GVA) {
c3c91fee 2953 kvm_inject_page_fault(vcpu, addr, 2);
bbd9b64e
CO		 2954 return X86EMUL_PROPAGATE_FAULT;
2955 }
2956
2957 /* For APIC access vmexit */
2958 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2959 goto mmio;
2960
2961 if (emulator_write_phys(vcpu, gpa, val, bytes))
2962 return X86EMUL_CONTINUE;
2963
2964mmio:
aec51dc4 2965 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 2966 /*
2967 * Is this MMIO handled locally?
2968 */
bda9020e 2969 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
bbd9b64e 2970 return X86EMUL_CONTINUE;
bbd9b64e
CO		 2971
2972 vcpu->mmio_needed = 1;
2973 vcpu->mmio_phys_addr = gpa;
2974 vcpu->mmio_size = bytes;
2975 vcpu->mmio_is_write = 1;
2976 memcpy(vcpu->mmio_data, val, bytes);
2977
2978 return X86EMUL_CONTINUE;
2979}
2980
2981int emulator_write_emulated(unsigned long addr,
2982 const void *val,
2983 unsigned int bytes,
2984 struct kvm_vcpu *vcpu)
2985{
2986 /* Crossing a page boundary? */
2987 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
2988 int rc, now;
2989
2990 now = -addr & ~PAGE_MASK;
2991 rc = emulator_write_emulated_onepage(addr, val, now, vcpu);
2992 if (rc != X86EMUL_CONTINUE)
2993 return rc;
2994 addr += now;
2995 val += now;
2996 bytes -= now;
2997 }
2998 return emulator_write_emulated_onepage(addr, val, bytes, vcpu);
2999}
3000EXPORT_SYMBOL_GPL(emulator_write_emulated);
3001
3002static int emulator_cmpxchg_emulated(unsigned long addr,
3003 const void *old,
3004 const void *new,
3005 unsigned int bytes,
3006 struct kvm_vcpu *vcpu)
3007{
9f51e24e 3008 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c
MT		 3009#ifndef CONFIG_X86_64
3010 /* guests cmpxchg8b have to be emulated atomically */
3011 if (bytes == 8) {
10589a46 3012 gpa_t gpa;
2bacc55c 3013 struct page *page;
c0b49b0d 3014 char *kaddr;
2bacc55c
MT		 3015 u64 val;
3016
10589a46
MT		 3017 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
3018
2bacc55c
MT		 3019 if (gpa == UNMAPPED_GVA ||
3020 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3021 goto emul_write;
3022
3023 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3024 goto emul_write;
3025
3026 val = *(u64 *)new;
72dc67a6 3027
2bacc55c 3028 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6 3029
c0b49b0d
AM		 3030 kaddr = kmap_atomic(page, KM_USER0);
3031 set_64bit((u64 *)(kaddr + offset_in_page(gpa)), val);
3032 kunmap_atomic(kaddr, KM_USER0);
2bacc55c
MT		 3033 kvm_release_page_dirty(page);
3034 }
3200f405 3035emul_write:
2bacc55c
MT		 3036#endif
3037
bbd9b64e
CO		 3038 return emulator_write_emulated(addr, new, bytes, vcpu);
3039}
3040
3041static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
3042{
3043 return kvm_x86_ops->get_segment_base(vcpu, seg);
3044}
3045
3046int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
3047{
a7052897 3048 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 3049 return X86EMUL_CONTINUE;
3050}
3051
3052int emulate_clts(struct kvm_vcpu *vcpu)
3053{
ad312c7c 3054 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 & ~X86_CR0_TS);
bbd9b64e
CO		 3055 return X86EMUL_CONTINUE;
3056}
3057
3058int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
3059{
3060 struct kvm_vcpu *vcpu = ctxt->vcpu;
3061
3062 switch (dr) {
3063 case 0 ... 3:
3064 *dest = kvm_x86_ops->get_dr(vcpu, dr);
3065 return X86EMUL_CONTINUE;
3066 default:
b8688d51 3067 pr_unimpl(vcpu, "%s: unexpected dr %u\n", __func__, dr);
bbd9b64e
CO		 3068 return X86EMUL_UNHANDLEABLE;
3069 }
3070}
3071
3072int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
3073{
3074 unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U;
3075 int exception;
3076
3077 kvm_x86_ops->set_dr(ctxt->vcpu, dr, value & mask, &exception);
3078 if (exception) {
3079 /* FIXME: better handling */
3080 return X86EMUL_UNHANDLEABLE;
3081 }
3082 return X86EMUL_CONTINUE;
3083}
3084
3085void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context)
3086{
bbd9b64e 3087 u8 opcodes[4];
5fdbf976 3088 unsigned long rip = kvm_rip_read(vcpu);
bbd9b64e
CO		 3089 unsigned long rip_linear;
3090
f76c710d 3091 if (!printk_ratelimit())
bbd9b64e
CO		 3092 return;
3093
25be4608
GC		 3094 rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS);
3095
77c2002e 3096 kvm_read_guest_virt(rip_linear, (void *)opcodes, 4, vcpu);
bbd9b64e
CO		 3097
3098 printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n",
3099 context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]);
bbd9b64e
CO		 3100}
3101EXPORT_SYMBOL_GPL(kvm_report_emulation_failure);
3102
14af3f3c 3103static struct x86_emulate_ops emulate_ops = {
77c2002e 3104 .read_std = kvm_read_guest_virt,
bbd9b64e
CO		 3105 .read_emulated = emulator_read_emulated,
3106 .write_emulated = emulator_write_emulated,
3107 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3108};
3109
5fdbf976
MT		 3110static void cache_all_regs(struct kvm_vcpu *vcpu)
3111{
3112 kvm_register_read(vcpu, VCPU_REGS_RAX);
3113 kvm_register_read(vcpu, VCPU_REGS_RSP);
3114 kvm_register_read(vcpu, VCPU_REGS_RIP);
3115 vcpu->arch.regs_dirty = ~0;
3116}
3117
bbd9b64e 3118int emulate_instruction(struct kvm_vcpu *vcpu,
bbd9b64e
CO		 3119 unsigned long cr2,
3120 u16 error_code,
571008da 3121 int emulation_type)
bbd9b64e 3122{
310b5d30 3123 int r, shadow_mask;
571008da 3124 struct decode_cache *c;
851ba692 3125 struct kvm_run *run = vcpu->run;
bbd9b64e 3126
26eef70c 3127 kvm_clear_exception_queue(vcpu);
ad312c7c 3128 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976 3129 /*
56e82318 3130 * TODO: fix emulate.c to use guest_read/write_register
5fdbf976
MT		 3131 * instead of direct ->regs accesses, can save hundred cycles
3132 * on Intel for instructions that don't read/change RSP, for
3133 * for example.
3134 */
3135 cache_all_regs(vcpu);
bbd9b64e
CO		 3136
3137 vcpu->mmio_is_write = 0;
ad312c7c 3138 vcpu->arch.pio.string = 0;
bbd9b64e 3139
571008da 3140 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
bbd9b64e
CO		 3141 int cs_db, cs_l;
3142 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
3143
ad312c7c 3144 vcpu->arch.emulate_ctxt.vcpu = vcpu;
91586a3b 3145 vcpu->arch.emulate_ctxt.eflags = kvm_get_rflags(vcpu);
ad312c7c
ZX		 3146 vcpu->arch.emulate_ctxt.mode =
3147 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
bbd9b64e
CO		 3148 ? X86EMUL_MODE_REAL : cs_l
3149 ? X86EMUL_MODE_PROT64 : cs_db
3150 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
3151
ad312c7c 3152 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
571008da 3153
0cb5762e
AP		 3154 /* Only allow emulation of specific instructions on #UD
3155 * (namely VMMCALL, sysenter, sysexit, syscall)*/
571008da 3156 c = &vcpu->arch.emulate_ctxt.decode;
0cb5762e
AP		 3157 if (emulation_type & EMULTYPE_TRAP_UD) {
3158 if (!c->twobyte)
3159 return EMULATE_FAIL;
3160 switch (c->b) {
3161 case 0x01: /* VMMCALL */
3162 if (c->modrm_mod != 3 || c->modrm_rm != 1)
3163 return EMULATE_FAIL;
3164 break;
3165 case 0x34: /* sysenter */
3166 case 0x35: /* sysexit */
3167 if (c->modrm_mod != 0 || c->modrm_rm != 0)
3168 return EMULATE_FAIL;
3169 break;
3170 case 0x05: /* syscall */
3171 if (c->modrm_mod != 0 || c->modrm_rm != 0)
3172 return EMULATE_FAIL;
3173 break;
3174 default:
3175 return EMULATE_FAIL;
3176 }
3177
3178 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
3179 return EMULATE_FAIL;
3180 }
571008da 3181
f2b5756b 3182 ++vcpu->stat.insn_emulation;
bbd9b64e 3183 if (r) {
f2b5756b 3184 ++vcpu->stat.insn_emulation_fail;
bbd9b64e
CO		 3185 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
3186 return EMULATE_DONE;
3187 return EMULATE_FAIL;
3188 }
3189 }
3190
ba8afb6b
GN		 3191 if (emulation_type & EMULTYPE_SKIP) {
3192 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
3193 return EMULATE_DONE;
3194 }
3195
ad312c7c 3196 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
310b5d30
GC		 3197 shadow_mask = vcpu->arch.emulate_ctxt.interruptibility;
3198
3199 if (r == 0)
3200 kvm_x86_ops->set_interrupt_shadow(vcpu, shadow_mask);
bbd9b64e 3201
ad312c7c 3202 if (vcpu->arch.pio.string)
bbd9b64e
CO		 3203 return EMULATE_DO_MMIO;
3204
3205 if ((r || vcpu->mmio_is_write) && run) {
3206 run->exit_reason = KVM_EXIT_MMIO;
3207 run->mmio.phys_addr = vcpu->mmio_phys_addr;
3208 memcpy(run->mmio.data, vcpu->mmio_data, 8);
3209 run->mmio.len = vcpu->mmio_size;
3210 run->mmio.is_write = vcpu->mmio_is_write;
3211 }
3212
3213 if (r) {
3214 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
3215 return EMULATE_DONE;
3216 if (!vcpu->mmio_needed) {
3217 kvm_report_emulation_failure(vcpu, "mmio");
3218 return EMULATE_FAIL;
3219 }
3220 return EMULATE_DO_MMIO;
3221 }
3222
91586a3b 3223 kvm_set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
bbd9b64e
CO		 3224
3225 if (vcpu->mmio_is_write) {
3226 vcpu->mmio_needed = 0;
3227 return EMULATE_DO_MMIO;
3228 }
3229
3230 return EMULATE_DONE;
3231}
3232EXPORT_SYMBOL_GPL(emulate_instruction);
3233
de7d789a
CO		 3234static int pio_copy_data(struct kvm_vcpu *vcpu)
3235{
ad312c7c 3236 void *p = vcpu->arch.pio_data;
0f346074 3237 gva_t q = vcpu->arch.pio.guest_gva;
de7d789a 3238 unsigned bytes;
0f346074 3239 int ret;
de7d789a 3240
ad312c7c
ZX		 3241 bytes = vcpu->arch.pio.size * vcpu->arch.pio.cur_count;
3242 if (vcpu->arch.pio.in)
0f346074 3243 ret = kvm_write_guest_virt(q, p, bytes, vcpu);
de7d789a 3244 else
0f346074
IE		 3245 ret = kvm_read_guest_virt(q, p, bytes, vcpu);
3246 return ret;
de7d789a
CO		 3247}
3248
3249int complete_pio(struct kvm_vcpu *vcpu)
3250{
ad312c7c 3251 struct kvm_pio_request *io = &vcpu->arch.pio;
de7d789a
CO		 3252 long delta;
3253 int r;
5fdbf976 3254 unsigned long val;
de7d789a
CO		 3255
3256 if (!io->string) {
5fdbf976
MT		 3257 if (io->in) {
3258 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
3259 memcpy(&val, vcpu->arch.pio_data, io->size);
3260 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
3261 }
de7d789a
CO		 3262 } else {
3263 if (io->in) {
3264 r = pio_copy_data(vcpu);
5fdbf976 3265 if (r)
de7d789a 3266 return r;
de7d789a
CO		 3267 }
3268
3269 delta = 1;
3270 if (io->rep) {
3271 delta *= io->cur_count;
3272 /*
3273 * The size of the register should really depend on
3274 * current address size.
3275 */
5fdbf976
MT		 3276 val = kvm_register_read(vcpu, VCPU_REGS_RCX);
3277 val -= delta;
3278 kvm_register_write(vcpu, VCPU_REGS_RCX, val);
de7d789a
CO		 3279 }
3280 if (io->down)
3281 delta = -delta;
3282 delta *= io->size;
5fdbf976
MT		 3283 if (io->in) {
3284 val = kvm_register_read(vcpu, VCPU_REGS_RDI);
3285 val += delta;
3286 kvm_register_write(vcpu, VCPU_REGS_RDI, val);
3287 } else {
3288 val = kvm_register_read(vcpu, VCPU_REGS_RSI);
3289 val += delta;
3290 kvm_register_write(vcpu, VCPU_REGS_RSI, val);
3291 }
de7d789a
CO		 3292 }
3293
de7d789a
CO		 3294 io->count -= io->cur_count;
3295 io->cur_count = 0;
3296
3297 return 0;
3298}
3299
bda9020e 3300static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
de7d789a
CO		 3301{
3302 /* TODO: String I/O for in kernel device */
bda9020e 3303 int r;
de7d789a 3304
ad312c7c 3305 if (vcpu->arch.pio.in)
bda9020e
MT		 3306 r = kvm_io_bus_read(&vcpu->kvm->pio_bus, vcpu->arch.pio.port,
3307 vcpu->arch.pio.size, pd);
de7d789a 3308 else
bda9020e
MT		 3309 r = kvm_io_bus_write(&vcpu->kvm->pio_bus, vcpu->arch.pio.port,
3310 vcpu->arch.pio.size, pd);
3311 return r;
de7d789a
CO		 3312}
3313
bda9020e 3314static int pio_string_write(struct kvm_vcpu *vcpu)
de7d789a 3315{
ad312c7c
ZX		 3316 struct kvm_pio_request *io = &vcpu->arch.pio;
3317 void *pd = vcpu->arch.pio_data;
bda9020e 3318 int i, r = 0;
de7d789a 3319
de7d789a 3320 for (i = 0; i < io->cur_count; i++) {
bda9020e
MT		 3321 if (kvm_io_bus_write(&vcpu->kvm->pio_bus,
3322 io->port, io->size, pd)) {
3323 r = -EOPNOTSUPP;
3324 break;
3325 }
de7d789a
CO		 3326 pd += io->size;
3327 }
bda9020e 3328 return r;
de7d789a
CO		 3329}
3330
851ba692 3331int kvm_emulate_pio(struct kvm_vcpu *vcpu, int in, int size, unsigned port)
de7d789a 3332{
5fdbf976 3333 unsigned long val;
de7d789a
CO		 3334
3335 vcpu->run->exit_reason = KVM_EXIT_IO;
3336 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 3337 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 3338 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 3339 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = 1;
3340 vcpu->run->io.port = vcpu->arch.pio.port = port;
3341 vcpu->arch.pio.in = in;
3342 vcpu->arch.pio.string = 0;
3343 vcpu->arch.pio.down = 0;
ad312c7c 3344 vcpu->arch.pio.rep = 0;
de7d789a 3345
229456fc
MT		 3346 trace_kvm_pio(vcpu->run->io.direction == KVM_EXIT_IO_OUT, port,
3347 size, 1);
2714d1d3 3348
5fdbf976
MT		 3349 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
3350 memcpy(vcpu->arch.pio_data, &val, 4);
de7d789a 3351
bda9020e 3352 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
de7d789a
CO		 3353 complete_pio(vcpu);
3354 return 1;
3355 }
3356 return 0;
3357}
3358EXPORT_SYMBOL_GPL(kvm_emulate_pio);
3359
851ba692 3360int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, int in,
de7d789a
CO		 3361 int size, unsigned long count, int down,
3362 gva_t address, int rep, unsigned port)
3363{
3364 unsigned now, in_page;
0f346074 3365 int ret = 0;
de7d789a
CO		 3366
3367 vcpu->run->exit_reason = KVM_EXIT_IO;
3368 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 3369 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 3370 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 3371 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = count;
3372 vcpu->run->io.port = vcpu->arch.pio.port = port;
3373 vcpu->arch.pio.in = in;
3374 vcpu->arch.pio.string = 1;
3375 vcpu->arch.pio.down = down;
ad312c7c 3376 vcpu->arch.pio.rep = rep;
de7d789a 3377
229456fc
MT		 3378 trace_kvm_pio(vcpu->run->io.direction == KVM_EXIT_IO_OUT, port,
3379 size, count);
2714d1d3 3380
de7d789a
CO		 3381 if (!count) {
3382 kvm_x86_ops->skip_emulated_instruction(vcpu);
3383 return 1;
3384 }
3385
3386 if (!down)
3387 in_page = PAGE_SIZE - offset_in_page(address);
3388 else
3389 in_page = offset_in_page(address) + size;
3390 now = min(count, (unsigned long)in_page / size);
0f346074 3391 if (!now)
de7d789a 3392 now = 1;
de7d789a
CO		 3393 if (down) {
3394 /*
3395 * String I/O in reverse. Yuck. Kill the guest, fix later.
3396 */
3397 pr_unimpl(vcpu, "guest string pio down\n");
c1a5d4f9 3398 kvm_inject_gp(vcpu, 0);
de7d789a
CO		 3399 return 1;
3400 }
3401 vcpu->run->io.count = now;
ad312c7c 3402 vcpu->arch.pio.cur_count = now;
de7d789a 3403
ad312c7c 3404 if (vcpu->arch.pio.cur_count == vcpu->arch.pio.count)
de7d789a
CO		 3405 kvm_x86_ops->skip_emulated_instruction(vcpu);
3406
0f346074 3407 vcpu->arch.pio.guest_gva = address;
de7d789a 3408
ad312c7c 3409 if (!vcpu->arch.pio.in) {
de7d789a
CO		 3410 /* string PIO write */
3411 ret = pio_copy_data(vcpu);
0f346074
IE		 3412 if (ret == X86EMUL_PROPAGATE_FAULT) {
3413 kvm_inject_gp(vcpu, 0);
3414 return 1;
3415 }
bda9020e 3416 if (ret == 0 && !pio_string_write(vcpu)) {
de7d789a 3417 complete_pio(vcpu);
ad312c7c 3418 if (vcpu->arch.pio.count == 0)
de7d789a
CO		 3419 ret = 1;
3420 }
bda9020e
MT		 3421 }
3422 /* no string PIO read support yet */
de7d789a
CO		 3423
3424 return ret;
3425}
3426EXPORT_SYMBOL_GPL(kvm_emulate_pio_string);
3427
c8076604
GH		 3428static void bounce_off(void *info)
3429{
3430 /* nothing */
3431}
3432
c8076604
GH		 3433static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
3434 void *data)
3435{
3436 struct cpufreq_freqs *freq = data;
3437 struct kvm *kvm;
3438 struct kvm_vcpu *vcpu;
3439 int i, send_ipi = 0;
3440
c8076604
GH		 3441 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
3442 return 0;
3443 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
3444 return 0;
0cca7907 3445 per_cpu(cpu_tsc_khz, freq->cpu) = freq->new;
c8076604
GH		 3446
3447 spin_lock(&kvm_lock);
3448 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 3449 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 3450 if (vcpu->cpu != freq->cpu)
3451 continue;
3452 if (!kvm_request_guest_time_update(vcpu))
3453 continue;
3454 if (vcpu->cpu != smp_processor_id())
3455 send_ipi++;
3456 }
3457 }
3458 spin_unlock(&kvm_lock);
3459
3460 if (freq->old < freq->new && send_ipi) {
3461 /*
3462 * We upscale the frequency. Must make the guest
3463 * doesn't see old kvmclock values while running with
3464 * the new frequency, otherwise we risk the guest sees
3465 * time go backwards.
3466 *
3467 * In case we update the frequency for another cpu
3468 * (which might be in guest context) send an interrupt
3469 * to kick the cpu out of guest context. Next time
3470 * guest context is entered kvmclock will be updated,
3471 * so the guest will not see stale values.
3472 */
3473 smp_call_function_single(freq->cpu, bounce_off, NULL, 1);
3474 }
3475 return 0;
3476}
3477
3478static struct notifier_block kvmclock_cpufreq_notifier_block = {
3479 .notifier_call = kvmclock_cpufreq_notifier
3480};
3481
b820cc0c
ZA		 3482static void kvm_timer_init(void)
3483{
3484 int cpu;
3485
b820cc0c 3486 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
b820cc0c
ZA		 3487 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
3488 CPUFREQ_TRANSITION_NOTIFIER);
6b7d7e76
ZA		 3489 for_each_online_cpu(cpu) {
3490 unsigned long khz = cpufreq_get(cpu);
3491 if (!khz)
3492 khz = tsc_khz;
3493 per_cpu(cpu_tsc_khz, cpu) = khz;
3494 }
0cca7907
ZA		 3495 } else {
3496 for_each_possible_cpu(cpu)
3497 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
b820cc0c
ZA		 3498 }
3499}
3500
f8c16bba 3501int kvm_arch_init(void *opaque)
043405e1 3502{
b820cc0c 3503 int r;
f8c16bba
ZX		 3504 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
3505
f8c16bba
ZX		 3506 if (kvm_x86_ops) {
3507 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 3508 r = -EEXIST;
3509 goto out;
f8c16bba
ZX		 3510 }
3511
3512 if (!ops->cpu_has_kvm_support()) {
3513 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 3514 r = -EOPNOTSUPP;
3515 goto out;
f8c16bba
ZX		 3516 }
3517 if (ops->disabled_by_bios()) {
3518 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 3519 r = -EOPNOTSUPP;
3520 goto out;
f8c16bba
ZX		 3521 }
3522
97db56ce
AK		 3523 r = kvm_mmu_module_init();
3524 if (r)
3525 goto out;
3526
3527 kvm_init_msr_list();
3528
f8c16bba 3529 kvm_x86_ops = ops;
56c6d28a 3530 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 3531 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
3532 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 3533 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 3534
b820cc0c 3535 kvm_timer_init();
c8076604 3536
f8c16bba 3537 return 0;
56c6d28a
ZX		 3538
3539out:
56c6d28a 3540 return r;
043405e1 3541}
8776e519 3542
f8c16bba
ZX		 3543void kvm_arch_exit(void)
3544{
888d256e
JK		 3545 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
3546 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
3547 CPUFREQ_TRANSITION_NOTIFIER);
f8c16bba 3548 kvm_x86_ops = NULL;
56c6d28a
ZX		 3549 kvm_mmu_module_exit();
3550}
f8c16bba 3551
8776e519
HB		 3552int kvm_emulate_halt(struct kvm_vcpu *vcpu)
3553{
3554 ++vcpu->stat.halt_exits;
3555 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 3556 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 3557 return 1;
3558 } else {
3559 vcpu->run->exit_reason = KVM_EXIT_HLT;
3560 return 0;
3561 }
3562}
3563EXPORT_SYMBOL_GPL(kvm_emulate_halt);
3564
2f333bcb
MT		 3565static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
3566 unsigned long a1)
3567{
3568 if (is_long_mode(vcpu))
3569 return a0;
3570 else
3571 return a0 | ((gpa_t)a1 << 32);
3572}
3573
8776e519
HB		 3574int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
3575{
3576 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 3577 int r = 1;
8776e519 3578
5fdbf976
MT		 3579 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
3580 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
3581 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
3582 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
3583 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 3584
229456fc 3585 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 3586
8776e519
HB		 3587 if (!is_long_mode(vcpu)) {
3588 nr &= 0xFFFFFFFF;
3589 a0 &= 0xFFFFFFFF;
3590 a1 &= 0xFFFFFFFF;
3591 a2 &= 0xFFFFFFFF;
3592 a3 &= 0xFFFFFFFF;
3593 }
3594
07708c4a
JK		 3595 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
3596 ret = -KVM_EPERM;
3597 goto out;
3598 }
3599
8776e519 3600 switch (nr) {
b93463aa
AK		 3601 case KVM_HC_VAPIC_POLL_IRQ:
3602 ret = 0;
3603 break;
2f333bcb
MT		 3604 case KVM_HC_MMU_OP:
3605 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
3606 break;
8776e519
HB		 3607 default:
3608 ret = -KVM_ENOSYS;
3609 break;
3610 }
07708c4a 3611out:
5fdbf976 3612 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 3613 ++vcpu->stat.hypercalls;
2f333bcb 3614 return r;
8776e519
HB		 3615}
3616EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
3617
3618int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
3619{
3620 char instruction[3];
3621 int ret = 0;
5fdbf976 3622 unsigned long rip = kvm_rip_read(vcpu);
8776e519 3623
8776e519
HB		 3624
3625 /*
3626 * Blow out the MMU to ensure that no other VCPU has an active mapping
3627 * to ensure that the updated hypercall appears atomically across all
3628 * VCPUs.
3629 */
3630 kvm_mmu_zap_all(vcpu->kvm);
3631
8776e519 3632 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5fdbf976 3633 if (emulator_write_emulated(rip, instruction, 3, vcpu)
8776e519
HB		 3634 != X86EMUL_CONTINUE)
3635 ret = -EFAULT;
3636
8776e519
HB		 3637 return ret;
3638}
3639
3640static u64 mk_cr_64(u64 curr_cr, u32 new_val)
3641{
3642 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
3643}
3644
3645void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
3646{
3647 struct descriptor_table dt = { limit, base };
3648
3649 kvm_x86_ops->set_gdt(vcpu, &dt);
3650}
3651
3652void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
3653{
3654 struct descriptor_table dt = { limit, base };
3655
3656 kvm_x86_ops->set_idt(vcpu, &dt);
3657}
3658
3659void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw,
3660 unsigned long *rflags)
3661{
2d3ad1f4 3662 kvm_lmsw(vcpu, msw);
91586a3b 3663 *rflags = kvm_get_rflags(vcpu);
8776e519
HB		 3664}
3665
3666unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr)
3667{
54e445ca
JR		 3668 unsigned long value;
3669
8776e519
HB		 3670 switch (cr) {
3671 case 0:
54e445ca
JR		 3672 value = vcpu->arch.cr0;
3673 break;
8776e519 3674 case 2:
54e445ca
JR		 3675 value = vcpu->arch.cr2;
3676 break;
8776e519 3677 case 3:
54e445ca
JR		 3678 value = vcpu->arch.cr3;
3679 break;
8776e519 3680 case 4:
fc78f519 3681 value = kvm_read_cr4(vcpu);
54e445ca 3682 break;
152ff9be 3683 case 8:
54e445ca
JR		 3684 value = kvm_get_cr8(vcpu);
3685 break;
8776e519 3686 default:
b8688d51 3687 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 3688 return 0;
3689 }
54e445ca
JR		 3690
3691 return value;
8776e519
HB		 3692}
3693
3694void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long val,
3695 unsigned long *rflags)
3696{
3697 switch (cr) {
3698 case 0:
2d3ad1f4 3699 kvm_set_cr0(vcpu, mk_cr_64(vcpu->arch.cr0, val));
91586a3b 3700 *rflags = kvm_get_rflags(vcpu);
8776e519
HB		 3701 break;
3702 case 2:
ad312c7c 3703 vcpu->arch.cr2 = val;
8776e519
HB		 3704 break;
3705 case 3:
2d3ad1f4 3706 kvm_set_cr3(vcpu, val);
8776e519
HB		 3707 break;
3708 case 4:
fc78f519 3709 kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
8776e519 3710 break;
152ff9be 3711 case 8:
2d3ad1f4 3712 kvm_set_cr8(vcpu, val & 0xfUL);
152ff9be 3713 break;
8776e519 3714 default:
b8688d51 3715 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 3716 }
3717}
3718
07716717
DK		 3719static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
3720{
ad312c7c
ZX		 3721 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
3722 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 3723
3724 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
3725 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 3726 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 3727 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 3728 if (ej->function == e->function) {
3729 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
3730 return j;
3731 }
3732 }
3733 return 0; /* silence gcc, even though control never reaches here */
3734}
3735
3736/* find an entry with matching function, matching index (if needed), and that
3737 * should be read next (if it's stateful) */
3738static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
3739 u32 function, u32 index)
3740{
3741 if (e->function != function)
3742 return 0;
3743 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
3744 return 0;
3745 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 3746 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 3747 return 0;
3748 return 1;
3749}
3750
d8017474
AG		 3751struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
3752 u32 function, u32 index)
8776e519
HB		 3753{
3754 int i;
d8017474 3755 struct kvm_cpuid_entry2 *best = NULL;
8776e519 3756
ad312c7c 3757 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 3758 struct kvm_cpuid_entry2 *e;
3759
ad312c7c 3760 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 3761 if (is_matching_cpuid_entry(e, function, index)) {
3762 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
3763 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 3764 best = e;
3765 break;
3766 }
3767 /*
3768 * Both basic or both extended?
3769 */
3770 if (((e->function ^ function) & 0x80000000) == 0)
3771 if (!best || e->function > best->function)
3772 best = e;
3773 }
d8017474
AG		 3774 return best;
3775}
0e851880 3776EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
d8017474 3777
82725b20
DE		 3778int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
3779{
3780 struct kvm_cpuid_entry2 *best;
3781
3782 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
3783 if (best)
3784 return best->eax & 0xff;
3785 return 36;
3786}
3787
d8017474
AG		 3788void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
3789{
3790 u32 function, index;
3791 struct kvm_cpuid_entry2 *best;
3792
3793 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
3794 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3795 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
3796 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
3797 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
3798 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
3799 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 3800 if (best) {
5fdbf976
MT		 3801 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
3802 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
3803 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
3804 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 3805 }
8776e519 3806 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 3807 trace_kvm_cpuid(function,
3808 kvm_register_read(vcpu, VCPU_REGS_RAX),
3809 kvm_register_read(vcpu, VCPU_REGS_RBX),
3810 kvm_register_read(vcpu, VCPU_REGS_RCX),
3811 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 3812}
3813EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 3814
b6c7a5dc
HB		 3815/*
3816 * Check if userspace requested an interrupt window, and that the
3817 * interrupt window is open.
3818 *
3819 * No need to exit to userspace if we already have an interrupt queued.
3820 */
851ba692 3821static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 3822{
8061823a 3823 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 3824 vcpu->run->request_interrupt_window &&
5df56646 3825 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 3826}
3827
851ba692 3828static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 3829{
851ba692
AK		 3830 struct kvm_run *kvm_run = vcpu->run;
3831
91586a3b 3832 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 3833 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 3834 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 3835 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 3836 kvm_run->ready_for_interrupt_injection = 1;
4531220b 3837 else
b6c7a5dc 3838 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 3839 kvm_arch_interrupt_allowed(vcpu) &&
3840 !kvm_cpu_has_interrupt(vcpu) &&
3841 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 3842}
3843
b93463aa
AK		 3844static void vapic_enter(struct kvm_vcpu *vcpu)
3845{
3846 struct kvm_lapic *apic = vcpu->arch.apic;
3847 struct page *page;
3848
3849 if (!apic || !apic->vapic_addr)
3850 return;
3851
3852 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 3853
3854 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 3855}
3856
3857static void vapic_exit(struct kvm_vcpu *vcpu)
3858{
3859 struct kvm_lapic *apic = vcpu->arch.apic;
3860
3861 if (!apic || !apic->vapic_addr)
3862 return;
3863
f8b78fa3 3864 down_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 3865 kvm_release_page_dirty(apic->vapic_page);
3866 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f8b78fa3 3867 up_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 3868}
3869
95ba8273
GN		 3870static void update_cr8_intercept(struct kvm_vcpu *vcpu)
3871{
3872 int max_irr, tpr;
3873
3874 if (!kvm_x86_ops->update_cr8_intercept)
3875 return;
3876
88c808fd
AK		 3877 if (!vcpu->arch.apic)
3878 return;
3879
8db3baa2
GN		 3880 if (!vcpu->arch.apic->vapic_addr)
3881 max_irr = kvm_lapic_find_highest_irr(vcpu);
3882 else
3883 max_irr = -1;
95ba8273
GN		 3884
3885 if (max_irr != -1)
3886 max_irr >>= 4;
3887
3888 tpr = kvm_lapic_get_cr8(vcpu);
3889
3890 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
3891}
3892
851ba692 3893static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 3894{
3895 /* try to reinject previous events if any */
b59bb7bd
GN		 3896 if (vcpu->arch.exception.pending) {
3897 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
3898 vcpu->arch.exception.has_error_code,
3899 vcpu->arch.exception.error_code);
3900 return;
3901 }
3902
95ba8273
GN		 3903 if (vcpu->arch.nmi_injected) {
3904 kvm_x86_ops->set_nmi(vcpu);
3905 return;
3906 }
3907
3908 if (vcpu->arch.interrupt.pending) {
66fd3f7f 3909 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 3910 return;
3911 }
3912
3913 /* try to inject new event if pending */
3914 if (vcpu->arch.nmi_pending) {
3915 if (kvm_x86_ops->nmi_allowed(vcpu)) {
3916 vcpu->arch.nmi_pending = false;
3917 vcpu->arch.nmi_injected = true;
3918 kvm_x86_ops->set_nmi(vcpu);
3919 }
3920 } else if (kvm_cpu_has_interrupt(vcpu)) {
3921 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 3922 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
3923 false);
3924 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 3925 }
3926 }
3927}
3928
851ba692 3929static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 3930{
3931 int r;
6a8b1d13 3932 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 3933 vcpu->run->request_interrupt_window;
b6c7a5dc 3934
2e53d63a
MT		 3935 if (vcpu->requests)
3936 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
3937 kvm_mmu_unload(vcpu);
3938
b6c7a5dc
HB		 3939 r = kvm_mmu_reload(vcpu);
3940 if (unlikely(r))
3941 goto out;
3942
2f52d58c
AK		 3943 if (vcpu->requests) {
3944 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
2f599714 3945 __kvm_migrate_timers(vcpu);
c8076604
GH		 3946 if (test_and_clear_bit(KVM_REQ_KVMCLOCK_UPDATE, &vcpu->requests))
3947 kvm_write_guest_time(vcpu);
4731d4c7
MT		 3948 if (test_and_clear_bit(KVM_REQ_MMU_SYNC, &vcpu->requests))
3949 kvm_mmu_sync_roots(vcpu);
d4acf7e7
MT		 3950 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
3951 kvm_x86_ops->tlb_flush(vcpu);
b93463aa
AK		 3952 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
3953 &vcpu->requests)) {
851ba692 3954 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 3955 r = 0;
3956 goto out;
3957 }
71c4dfaf 3958 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
851ba692 3959 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 3960 r = 0;
3961 goto out;
3962 }
2f52d58c 3963 }
b93463aa 3964
b6c7a5dc
HB		 3965 preempt_disable();
3966
3967 kvm_x86_ops->prepare_guest_switch(vcpu);
3968 kvm_load_guest_fpu(vcpu);
3969
3970 local_irq_disable();
3971
32f88400
MT		 3972 clear_bit(KVM_REQ_KICK, &vcpu->requests);
3973 smp_mb__after_clear_bit();
3974
d7690175 3975 if (vcpu->requests || need_resched() || signal_pending(current)) {
c7f0f24b 3976 set_bit(KVM_REQ_KICK, &vcpu->requests);
6c142801
AK		 3977 local_irq_enable();
3978 preempt_enable();
3979 r = 1;
3980 goto out;
3981 }
3982
851ba692 3983 inject_pending_event(vcpu);
b6c7a5dc 3984
6a8b1d13
GN		 3985 /* enable NMI/IRQ window open exits if needed */
3986 if (vcpu->arch.nmi_pending)
3987 kvm_x86_ops->enable_nmi_window(vcpu);
3988 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
3989 kvm_x86_ops->enable_irq_window(vcpu);
3990
95ba8273 3991 if (kvm_lapic_enabled(vcpu)) {
8db3baa2
GN		 3992 update_cr8_intercept(vcpu);
3993 kvm_lapic_sync_to_vapic(vcpu);
95ba8273 3994 }
b93463aa 3995
3200f405
MT		 3996 up_read(&vcpu->kvm->slots_lock);
3997
b6c7a5dc
HB		 3998 kvm_guest_enter();
3999
42dbaa5a 4000 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 4001 set_debugreg(0, 7);
4002 set_debugreg(vcpu->arch.eff_db[0], 0);
4003 set_debugreg(vcpu->arch.eff_db[1], 1);
4004 set_debugreg(vcpu->arch.eff_db[2], 2);
4005 set_debugreg(vcpu->arch.eff_db[3], 3);
4006 }
b6c7a5dc 4007
229456fc 4008 trace_kvm_entry(vcpu->vcpu_id);
851ba692 4009 kvm_x86_ops->run(vcpu);
b6c7a5dc 4010
24f1e32c
FW		 4011 /*
4012 * If the guest has used debug registers, at least dr7
4013 * will be disabled while returning to the host.
4014 * If we don't have active breakpoints in the host, we don't
4015 * care about the messed up debug address registers. But if
4016 * we have some of them active, restore the old state.
4017 */
59d8eb53 4018 if (hw_breakpoint_active())
24f1e32c 4019 hw_breakpoint_restore();
42dbaa5a 4020
32f88400 4021 set_bit(KVM_REQ_KICK, &vcpu->requests);
b6c7a5dc
HB		 4022 local_irq_enable();
4023
4024 ++vcpu->stat.exits;
4025
4026 /*
4027 * We must have an instruction between local_irq_enable() and
4028 * kvm_guest_exit(), so the timer interrupt isn't delayed by
4029 * the interrupt shadow. The stat.exits increment will do nicely.
4030 * But we need to prevent reordering, hence this barrier():
4031 */
4032 barrier();
4033
4034 kvm_guest_exit();
4035
4036 preempt_enable();
4037
3200f405
MT		 4038 down_read(&vcpu->kvm->slots_lock);
4039
b6c7a5dc
HB		 4040 /*
4041 * Profile KVM exit RIPs:
4042 */
4043 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 4044 unsigned long rip = kvm_rip_read(vcpu);
4045 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 4046 }
4047
298101da 4048
b93463aa
AK		 4049 kvm_lapic_sync_from_vapic(vcpu);
4050
851ba692 4051 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 4052out:
4053 return r;
4054}
b6c7a5dc 4055
09cec754 4056
851ba692 4057static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 4058{
4059 int r;
4060
4061 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 4062 pr_debug("vcpu %d received sipi with vector # %x\n",
4063 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 4064 kvm_lapic_reset(vcpu);
5f179287 4065 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 4066 if (r)
4067 return r;
4068 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 4069 }
4070
d7690175
MT		 4071 down_read(&vcpu->kvm->slots_lock);
4072 vapic_enter(vcpu);
4073
4074 r = 1;
4075 while (r > 0) {
af2152f5 4076 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
851ba692 4077 r = vcpu_enter_guest(vcpu);
d7690175
MT		 4078 else {
4079 up_read(&vcpu->kvm->slots_lock);
4080 kvm_vcpu_block(vcpu);
4081 down_read(&vcpu->kvm->slots_lock);
4082 if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests))
09cec754
GN		 4083 {
4084 switch(vcpu->arch.mp_state) {
4085 case KVM_MP_STATE_HALTED:
d7690175 4086 vcpu->arch.mp_state =
09cec754
GN		 4087 KVM_MP_STATE_RUNNABLE;
4088 case KVM_MP_STATE_RUNNABLE:
4089 break;
4090 case KVM_MP_STATE_SIPI_RECEIVED:
4091 default:
4092 r = -EINTR;
4093 break;
4094 }
4095 }
d7690175
MT		 4096 }
4097
09cec754
GN		 4098 if (r <= 0)
4099 break;
4100
4101 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
4102 if (kvm_cpu_has_pending_timer(vcpu))
4103 kvm_inject_pending_timer_irqs(vcpu);
4104
851ba692 4105 if (dm_request_for_irq_injection(vcpu)) {
09cec754 4106 r = -EINTR;
851ba692 4107 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 4108 ++vcpu->stat.request_irq_exits;
4109 }
4110 if (signal_pending(current)) {
4111 r = -EINTR;
851ba692 4112 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 4113 ++vcpu->stat.signal_exits;
4114 }
4115 if (need_resched()) {
4116 up_read(&vcpu->kvm->slots_lock);
4117 kvm_resched(vcpu);
4118 down_read(&vcpu->kvm->slots_lock);
d7690175 4119 }
b6c7a5dc
HB		 4120 }
4121
d7690175 4122 up_read(&vcpu->kvm->slots_lock);
851ba692 4123 post_kvm_run_save(vcpu);
b6c7a5dc 4124
b93463aa
AK		 4125 vapic_exit(vcpu);
4126
b6c7a5dc
HB		 4127 return r;
4128}
4129
4130int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
4131{
4132 int r;
4133 sigset_t sigsaved;
4134
4135 vcpu_load(vcpu);
4136
ac9f6dc0
AK		 4137 if (vcpu->sigset_active)
4138 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
4139
a4535290 4140 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 4141 kvm_vcpu_block(vcpu);
d7690175 4142 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 4143 r = -EAGAIN;
4144 goto out;
b6c7a5dc
HB		 4145 }
4146
b6c7a5dc
HB		 4147 /* re-sync apic's tpr */
4148 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 4149 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 4150
ad312c7c 4151 if (vcpu->arch.pio.cur_count) {
b6c7a5dc
HB		 4152 r = complete_pio(vcpu);
4153 if (r)
4154 goto out;
4155 }
b6c7a5dc
HB		 4156 if (vcpu->mmio_needed) {
4157 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
4158 vcpu->mmio_read_completed = 1;
4159 vcpu->mmio_needed = 0;
3200f405
MT		 4160
4161 down_read(&vcpu->kvm->slots_lock);
851ba692 4162 r = emulate_instruction(vcpu, vcpu->arch.mmio_fault_cr2, 0,
571008da 4163 EMULTYPE_NO_DECODE);
3200f405 4164 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 4165 if (r == EMULATE_DO_MMIO) {
4166 /*
4167 * Read-modify-write. Back to userspace.
4168 */
4169 r = 0;
4170 goto out;
4171 }
4172 }
5fdbf976
MT		 4173 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
4174 kvm_register_write(vcpu, VCPU_REGS_RAX,
4175 kvm_run->hypercall.ret);
b6c7a5dc 4176
851ba692 4177 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 4178
4179out:
4180 if (vcpu->sigset_active)
4181 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
4182
4183 vcpu_put(vcpu);
4184 return r;
4185}
4186
4187int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
4188{
4189 vcpu_load(vcpu);
4190
5fdbf976
MT		 4191 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4192 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4193 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4194 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4195 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4196 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
4197 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4198 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 4199#ifdef CONFIG_X86_64
5fdbf976
MT		 4200 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
4201 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
4202 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
4203 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
4204 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
4205 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
4206 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
4207 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 4208#endif
4209
5fdbf976 4210 regs->rip = kvm_rip_read(vcpu);
91586a3b 4211 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc
HB		 4212
4213 vcpu_put(vcpu);
4214
4215 return 0;
4216}
4217
4218int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
4219{
4220 vcpu_load(vcpu);
4221
5fdbf976
MT		 4222 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
4223 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
4224 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
4225 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
4226 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
4227 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
4228 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
4229 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 4230#ifdef CONFIG_X86_64
5fdbf976
MT		 4231 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
4232 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
4233 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
4234 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
4235 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
4236 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
4237 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
4238 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 4239#endif
4240
5fdbf976 4241 kvm_rip_write(vcpu, regs->rip);
91586a3b 4242 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 4243
b4f14abd
JK		 4244 vcpu->arch.exception.pending = false;
4245
b6c7a5dc
HB		 4246 vcpu_put(vcpu);
4247
4248 return 0;
4249}
4250
3e6e0aab
GT		 4251void kvm_get_segment(struct kvm_vcpu *vcpu,
4252 struct kvm_segment *var, int seg)
b6c7a5dc 4253{
14af3f3c 4254 kvm_x86_ops->get_segment(vcpu, var, seg);
b6c7a5dc
HB		 4255}
4256
4257void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4258{
4259 struct kvm_segment cs;
4260
3e6e0aab 4261 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 4262 *db = cs.db;
4263 *l = cs.l;
4264}
4265EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
4266
4267int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
4268 struct kvm_sregs *sregs)
4269{
4270 struct descriptor_table dt;
b6c7a5dc
HB		 4271
4272 vcpu_load(vcpu);
4273
3e6e0aab
GT		 4274 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
4275 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
4276 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
4277 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
4278 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
4279 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 4280
3e6e0aab
GT		 4281 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
4282 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 4283
4284 kvm_x86_ops->get_idt(vcpu, &dt);
4285 sregs->idt.limit = dt.limit;
4286 sregs->idt.base = dt.base;
4287 kvm_x86_ops->get_gdt(vcpu, &dt);
4288 sregs->gdt.limit = dt.limit;
4289 sregs->gdt.base = dt.base;
4290
ad312c7c
ZX		 4291 sregs->cr0 = vcpu->arch.cr0;
4292 sregs->cr2 = vcpu->arch.cr2;
4293 sregs->cr3 = vcpu->arch.cr3;
fc78f519 4294 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 4295 sregs->cr8 = kvm_get_cr8(vcpu);
ad312c7c 4296 sregs->efer = vcpu->arch.shadow_efer;
b6c7a5dc
HB		 4297 sregs->apic_base = kvm_get_apic_base(vcpu);
4298
923c61bb 4299 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 4300
36752c9b 4301 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 4302 set_bit(vcpu->arch.interrupt.nr,
4303 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 4304
b6c7a5dc
HB		 4305 vcpu_put(vcpu);
4306
4307 return 0;
4308}
4309
62d9f0db
MT		 4310int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
4311 struct kvm_mp_state *mp_state)
4312{
4313 vcpu_load(vcpu);
4314 mp_state->mp_state = vcpu->arch.mp_state;
4315 vcpu_put(vcpu);
4316 return 0;
4317}
4318
4319int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
4320 struct kvm_mp_state *mp_state)
4321{
4322 vcpu_load(vcpu);
4323 vcpu->arch.mp_state = mp_state->mp_state;
4324 vcpu_put(vcpu);
4325 return 0;
4326}
4327
3e6e0aab 4328static void kvm_set_segment(struct kvm_vcpu *vcpu,
b6c7a5dc
HB		 4329 struct kvm_segment *var, int seg)
4330{
14af3f3c 4331 kvm_x86_ops->set_segment(vcpu, var, seg);
b6c7a5dc
HB		 4332}
4333
37817f29
IE		 4334static void seg_desct_to_kvm_desct(struct desc_struct *seg_desc, u16 selector,
4335 struct kvm_segment *kvm_desct)
4336{
46a359e7
AM		 4337 kvm_desct->base = get_desc_base(seg_desc);
4338 kvm_desct->limit = get_desc_limit(seg_desc);
c93cd3a5
MT		 4339 if (seg_desc->g) {
4340 kvm_desct->limit <<= 12;
4341 kvm_desct->limit |= 0xfff;
4342 }
37817f29
IE		 4343 kvm_desct->selector = selector;
4344 kvm_desct->type = seg_desc->type;
4345 kvm_desct->present = seg_desc->p;
4346 kvm_desct->dpl = seg_desc->dpl;
4347 kvm_desct->db = seg_desc->d;
4348 kvm_desct->s = seg_desc->s;
4349 kvm_desct->l = seg_desc->l;
4350 kvm_desct->g = seg_desc->g;
4351 kvm_desct->avl = seg_desc->avl;
4352 if (!selector)
4353 kvm_desct->unusable = 1;
4354 else
4355 kvm_desct->unusable = 0;
4356 kvm_desct->padding = 0;
4357}
4358
b8222ad2
AS		 4359static void get_segment_descriptor_dtable(struct kvm_vcpu *vcpu,
4360 u16 selector,
4361 struct descriptor_table *dtable)
37817f29
IE		 4362{
4363 if (selector & 1 << 2) {
4364 struct kvm_segment kvm_seg;
4365
3e6e0aab 4366 kvm_get_segment(vcpu, &kvm_seg, VCPU_SREG_LDTR);
37817f29
IE		 4367
4368 if (kvm_seg.unusable)
4369 dtable->limit = 0;
4370 else
4371 dtable->limit = kvm_seg.limit;
4372 dtable->base = kvm_seg.base;
4373 }
4374 else
4375 kvm_x86_ops->get_gdt(vcpu, dtable);
4376}
4377
4378/* allowed just for 8 bytes segments */
4379static int load_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4380 struct desc_struct *seg_desc)
4381{
4382 struct descriptor_table dtable;
4383 u16 index = selector >> 3;
4384
b8222ad2 4385 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 4386
4387 if (dtable.limit < index * 8 + 7) {
4388 kvm_queue_exception_e(vcpu, GP_VECTOR, selector & 0xfffc);
4389 return 1;
4390 }
d9048d32 4391 return kvm_read_guest_virt(dtable.base + index*8, seg_desc, sizeof(*seg_desc), vcpu);
37817f29
IE		 4392}
4393
4394/* allowed just for 8 bytes segments */
4395static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4396 struct desc_struct *seg_desc)
4397{
4398 struct descriptor_table dtable;
4399 u16 index = selector >> 3;
4400
b8222ad2 4401 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 4402
4403 if (dtable.limit < index * 8 + 7)
4404 return 1;
d9048d32 4405 return kvm_write_guest_virt(dtable.base + index*8, seg_desc, sizeof(*seg_desc), vcpu);
37817f29
IE		 4406}
4407
abb39119 4408static gpa_t get_tss_base_addr(struct kvm_vcpu *vcpu,
37817f29
IE		 4409 struct desc_struct *seg_desc)
4410{
46a359e7 4411 u32 base_addr = get_desc_base(seg_desc);
37817f29 4412
98899aa0 4413 return vcpu->arch.mmu.gva_to_gpa(vcpu, base_addr);
37817f29
IE		 4414}
4415
37817f29
IE		 4416static u16 get_segment_selector(struct kvm_vcpu *vcpu, int seg)
4417{
4418 struct kvm_segment kvm_seg;
4419
3e6e0aab 4420 kvm_get_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 4421 return kvm_seg.selector;
4422}
4423
4424static int load_segment_descriptor_to_kvm_desct(struct kvm_vcpu *vcpu,
4425 u16 selector,
4426 struct kvm_segment *kvm_seg)
4427{
4428 struct desc_struct seg_desc;
4429
4430 if (load_guest_segment_descriptor(vcpu, selector, &seg_desc))
4431 return 1;
4432 seg_desct_to_kvm_desct(&seg_desc, selector, kvm_seg);
4433 return 0;
4434}
4435
2259e3a7 4436static int kvm_load_realmode_segment(struct kvm_vcpu *vcpu, u16 selector, int seg)
f4bbd9aa
AK		 4437{
4438 struct kvm_segment segvar = {
4439 .base = selector << 4,
4440 .limit = 0xffff,
4441 .selector = selector,
4442 .type = 3,
4443 .present = 1,
4444 .dpl = 3,
4445 .db = 0,
4446 .s = 1,
4447 .l = 0,
4448 .g = 0,
4449 .avl = 0,
4450 .unusable = 0,
4451 };
4452 kvm_x86_ops->set_segment(vcpu, &segvar, seg);
4453 return 0;
4454}
4455
c0c7c04b
AL		 4456static int is_vm86_segment(struct kvm_vcpu *vcpu, int seg)
4457{
4458 return (seg != VCPU_SREG_LDTR) &&
4459 (seg != VCPU_SREG_TR) &&
91586a3b 4460 (kvm_get_rflags(vcpu) & X86_EFLAGS_VM);
c0c7c04b
AL		 4461}
4462
cb84b55f
MT		 4463static void kvm_check_segment_descriptor(struct kvm_vcpu *vcpu, int seg,
4464 u16 selector)
4465{
4466 /* NULL selector is not valid for CS and SS */
4467 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
4468 if (!selector)
4469 kvm_queue_exception_e(vcpu, TS_VECTOR, selector >> 3);
4470}
4471
3e6e0aab
GT		 4472int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4473 int type_bits, int seg)
37817f29
IE		 4474{
4475 struct kvm_segment kvm_seg;
4476
c0c7c04b 4477 if (is_vm86_segment(vcpu, seg) || !(vcpu->arch.cr0 & X86_CR0_PE))
f4bbd9aa 4478 return kvm_load_realmode_segment(vcpu, selector, seg);
37817f29
IE		 4479 if (load_segment_descriptor_to_kvm_desct(vcpu, selector, &kvm_seg))
4480 return 1;
cb84b55f
MT		 4481
4482 kvm_check_segment_descriptor(vcpu, seg, selector);
37817f29
IE		 4483 kvm_seg.type |= type_bits;
4484
4485 if (seg != VCPU_SREG_SS && seg != VCPU_SREG_CS &&
4486 seg != VCPU_SREG_LDTR)
4487 if (!kvm_seg.s)
4488 kvm_seg.unusable = 1;
4489
3e6e0aab 4490 kvm_set_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 4491 return 0;
4492}
4493
4494static void save_state_to_tss32(struct kvm_vcpu *vcpu,
4495 struct tss_segment_32 *tss)
4496{
4497 tss->cr3 = vcpu->arch.cr3;
5fdbf976 4498 tss->eip = kvm_rip_read(vcpu);
91586a3b 4499 tss->eflags = kvm_get_rflags(vcpu);
5fdbf976
MT		 4500 tss->eax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4501 tss->ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4502 tss->edx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4503 tss->ebx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4504 tss->esp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4505 tss->ebp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4506 tss->esi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4507 tss->edi = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 4508 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
4509 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
4510 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
4511 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
4512 tss->fs = get_segment_selector(vcpu, VCPU_SREG_FS);
4513 tss->gs = get_segment_selector(vcpu, VCPU_SREG_GS);
4514 tss->ldt_selector = get_segment_selector(vcpu, VCPU_SREG_LDTR);
37817f29
IE		 4515}
4516
4517static int load_state_from_tss32(struct kvm_vcpu *vcpu,
4518 struct tss_segment_32 *tss)
4519{
4520 kvm_set_cr3(vcpu, tss->cr3);
4521
5fdbf976 4522 kvm_rip_write(vcpu, tss->eip);
91586a3b 4523 kvm_set_rflags(vcpu, tss->eflags | 2);
37817f29 4524
5fdbf976
MT		 4525 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->eax);
4526 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->ecx);
4527 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->edx);
4528 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->ebx);
4529 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->esp);
4530 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->ebp);
4531 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->esi);
4532 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->edi);
37817f29 4533
3e6e0aab 4534 if (kvm_load_segment_descriptor(vcpu, tss->ldt_selector, 0, VCPU_SREG_LDTR))
37817f29
IE		 4535 return 1;
4536
3e6e0aab 4537 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 4538 return 1;
4539
3e6e0aab 4540 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 4541 return 1;
4542
3e6e0aab 4543 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 4544 return 1;
4545
3e6e0aab 4546 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 4547 return 1;
4548
3e6e0aab 4549 if (kvm_load_segment_descriptor(vcpu, tss->fs, 1, VCPU_SREG_FS))
37817f29
IE		 4550 return 1;
4551
3e6e0aab 4552 if (kvm_load_segment_descriptor(vcpu, tss->gs, 1, VCPU_SREG_GS))
37817f29
IE		 4553 return 1;
4554 return 0;
4555}
4556
4557static void save_state_to_tss16(struct kvm_vcpu *vcpu,
4558 struct tss_segment_16 *tss)
4559{
5fdbf976 4560 tss->ip = kvm_rip_read(vcpu);
91586a3b 4561 tss->flag = kvm_get_rflags(vcpu);
5fdbf976
MT		 4562 tss->ax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4563 tss->cx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4564 tss->dx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4565 tss->bx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4566 tss->sp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4567 tss->bp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4568 tss->si = kvm_register_read(vcpu, VCPU_REGS_RSI);
4569 tss->di = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 4570
4571 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
4572 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
4573 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
4574 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
4575 tss->ldt = get_segment_selector(vcpu, VCPU_SREG_LDTR);
37817f29
IE		 4576}
4577
4578static int load_state_from_tss16(struct kvm_vcpu *vcpu,
4579 struct tss_segment_16 *tss)
4580{
5fdbf976 4581 kvm_rip_write(vcpu, tss->ip);
91586a3b 4582 kvm_set_rflags(vcpu, tss->flag | 2);
5fdbf976
MT		 4583 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->ax);
4584 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->cx);
4585 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->dx);
4586 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->bx);
4587 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->sp);
4588 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->bp);
4589 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->si);
4590 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->di);
37817f29 4591
3e6e0aab 4592 if (kvm_load_segment_descriptor(vcpu, tss->ldt, 0, VCPU_SREG_LDTR))
37817f29
IE		 4593 return 1;
4594
3e6e0aab 4595 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 4596 return 1;
4597
3e6e0aab 4598 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 4599 return 1;
4600
3e6e0aab 4601 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 4602 return 1;
4603
3e6e0aab 4604 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 4605 return 1;
4606 return 0;
4607}
4608
8b2cf73c 4609static int kvm_task_switch_16(struct kvm_vcpu *vcpu, u16 tss_selector,
b237ac37
GN		 4610 u16 old_tss_sel, u32 old_tss_base,
4611 struct desc_struct *nseg_desc)
37817f29
IE		 4612{
4613 struct tss_segment_16 tss_segment_16;
4614 int ret = 0;
4615
34198bf8
MT		 4616 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
4617 sizeof tss_segment_16))
37817f29
IE		 4618 goto out;
4619
4620 save_state_to_tss16(vcpu, &tss_segment_16);
37817f29 4621
34198bf8
MT		 4622 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
4623 sizeof tss_segment_16))
37817f29 4624 goto out;
34198bf8
MT		 4625
4626 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
4627 &tss_segment_16, sizeof tss_segment_16))
4628 goto out;
4629
b237ac37
GN		 4630 if (old_tss_sel != 0xffff) {
4631 tss_segment_16.prev_task_link = old_tss_sel;
4632
4633 if (kvm_write_guest(vcpu->kvm,
4634 get_tss_base_addr(vcpu, nseg_desc),
4635 &tss_segment_16.prev_task_link,
4636 sizeof tss_segment_16.prev_task_link))
4637 goto out;
4638 }
4639
37817f29
IE		 4640 if (load_state_from_tss16(vcpu, &tss_segment_16))
4641 goto out;
4642
4643 ret = 1;
4644out:
4645 return ret;
4646}
4647
8b2cf73c 4648static int kvm_task_switch_32(struct kvm_vcpu *vcpu, u16 tss_selector,
b237ac37 4649 u16 old_tss_sel, u32 old_tss_base,
37817f29
IE		 4650 struct desc_struct *nseg_desc)
4651{
4652 struct tss_segment_32 tss_segment_32;
4653 int ret = 0;
4654
34198bf8
MT		 4655 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
4656 sizeof tss_segment_32))
37817f29
IE		 4657 goto out;
4658
4659 save_state_to_tss32(vcpu, &tss_segment_32);
37817f29 4660
34198bf8
MT		 4661 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
4662 sizeof tss_segment_32))
4663 goto out;
4664
4665 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
4666 &tss_segment_32, sizeof tss_segment_32))
37817f29 4667 goto out;
34198bf8 4668
b237ac37
GN		 4669 if (old_tss_sel != 0xffff) {
4670 tss_segment_32.prev_task_link = old_tss_sel;
4671
4672 if (kvm_write_guest(vcpu->kvm,
4673 get_tss_base_addr(vcpu, nseg_desc),
4674 &tss_segment_32.prev_task_link,
4675 sizeof tss_segment_32.prev_task_link))
4676 goto out;
4677 }
4678
37817f29
IE		 4679 if (load_state_from_tss32(vcpu, &tss_segment_32))
4680 goto out;
4681
4682 ret = 1;
4683out:
4684 return ret;
4685}
4686
4687int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason)
4688{
4689 struct kvm_segment tr_seg;
4690 struct desc_struct cseg_desc;
4691 struct desc_struct nseg_desc;
4692 int ret = 0;
34198bf8
MT		 4693 u32 old_tss_base = get_segment_base(vcpu, VCPU_SREG_TR);
4694 u16 old_tss_sel = get_segment_selector(vcpu, VCPU_SREG_TR);
37817f29 4695
34198bf8 4696 old_tss_base = vcpu->arch.mmu.gva_to_gpa(vcpu, old_tss_base);
37817f29 4697
34198bf8
MT		 4698 /* FIXME: Handle errors. Failure to read either TSS or their
4699 * descriptors should generate a pagefault.
4700 */
37817f29
IE		 4701 if (load_guest_segment_descriptor(vcpu, tss_selector, &nseg_desc))
4702 goto out;
4703
34198bf8 4704 if (load_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc))
37817f29
IE		 4705 goto out;
4706
37817f29
IE		 4707 if (reason != TASK_SWITCH_IRET) {
4708 int cpl;
4709
4710 cpl = kvm_x86_ops->get_cpl(vcpu);
4711 if ((tss_selector & 3) > nseg_desc.dpl || cpl > nseg_desc.dpl) {
4712 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
4713 return 1;
4714 }
4715 }
4716
46a359e7 4717 if (!nseg_desc.p || get_desc_limit(&nseg_desc) < 0x67) {
37817f29
IE		 4718 kvm_queue_exception_e(vcpu, TS_VECTOR, tss_selector & 0xfffc);
4719 return 1;
4720 }
4721
4722 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
3fe913e7 4723 cseg_desc.type &= ~(1 << 1); //clear the B flag
34198bf8 4724 save_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc);
37817f29
IE		 4725 }
4726
4727 if (reason == TASK_SWITCH_IRET) {
91586a3b
JK		 4728 u32 eflags = kvm_get_rflags(vcpu);
4729 kvm_set_rflags(vcpu, eflags & ~X86_EFLAGS_NT);
37817f29
IE		 4730 }
4731
b237ac37
GN		 4732 /* set back link to prev task only if NT bit is set in eflags
4733 note that old_tss_sel is not used afetr this point */
4734 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
4735 old_tss_sel = 0xffff;
4736
37817f29 4737 if (nseg_desc.type & 8)
b237ac37
GN		 4738 ret = kvm_task_switch_32(vcpu, tss_selector, old_tss_sel,
4739 old_tss_base, &nseg_desc);
37817f29 4740 else
b237ac37
GN		 4741 ret = kvm_task_switch_16(vcpu, tss_selector, old_tss_sel,
4742 old_tss_base, &nseg_desc);
37817f29
IE		 4743
4744 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) {
91586a3b
JK		 4745 u32 eflags = kvm_get_rflags(vcpu);
4746 kvm_set_rflags(vcpu, eflags | X86_EFLAGS_NT);
37817f29
IE		 4747 }
4748
4749 if (reason != TASK_SWITCH_IRET) {
3fe913e7 4750 nseg_desc.type |= (1 << 1);
37817f29
IE		 4751 save_guest_segment_descriptor(vcpu, tss_selector,
4752 &nseg_desc);
4753 }
4754
4755 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 | X86_CR0_TS);
4756 seg_desct_to_kvm_desct(&nseg_desc, tss_selector, &tr_seg);
4757 tr_seg.type = 11;
3e6e0aab 4758 kvm_set_segment(vcpu, &tr_seg, VCPU_SREG_TR);
37817f29 4759out:
37817f29
IE		 4760 return ret;
4761}
4762EXPORT_SYMBOL_GPL(kvm_task_switch);
4763
b6c7a5dc
HB		 4764int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
4765 struct kvm_sregs *sregs)
4766{
4767 int mmu_reset_needed = 0;
923c61bb 4768 int pending_vec, max_bits;
b6c7a5dc
HB		 4769 struct descriptor_table dt;
4770
4771 vcpu_load(vcpu);
4772
4773 dt.limit = sregs->idt.limit;
4774 dt.base = sregs->idt.base;
4775 kvm_x86_ops->set_idt(vcpu, &dt);
4776 dt.limit = sregs->gdt.limit;
4777 dt.base = sregs->gdt.base;
4778 kvm_x86_ops->set_gdt(vcpu, &dt);
4779
ad312c7c
ZX		 4780 vcpu->arch.cr2 = sregs->cr2;
4781 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
dc7e795e 4782 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 4783
2d3ad1f4 4784 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 4785
ad312c7c 4786 mmu_reset_needed |= vcpu->arch.shadow_efer != sregs->efer;
b6c7a5dc 4787 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 4788 kvm_set_apic_base(vcpu, sregs->apic_base);
4789
ad312c7c 4790 mmu_reset_needed |= vcpu->arch.cr0 != sregs->cr0;
b6c7a5dc 4791 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 4792 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 4793
fc78f519 4794 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 4795 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7c93be44 4796 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
ad312c7c 4797 load_pdptrs(vcpu, vcpu->arch.cr3);
7c93be44
MT		 4798 mmu_reset_needed = 1;
4799 }
b6c7a5dc
HB		 4800
4801 if (mmu_reset_needed)
4802 kvm_mmu_reset_context(vcpu);
4803
923c61bb
GN		 4804 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
4805 pending_vec = find_first_bit(
4806 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
4807 if (pending_vec < max_bits) {
66fd3f7f 4808 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 4809 pr_debug("Set back pending irq %d\n", pending_vec);
4810 if (irqchip_in_kernel(vcpu->kvm))
4811 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 4812 }
4813
3e6e0aab
GT		 4814 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
4815 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
4816 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
4817 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
4818 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
4819 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 4820
3e6e0aab
GT		 4821 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
4822 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 4823
5f0269f5
ME		 4824 update_cr8_intercept(vcpu);
4825
9c3e4aab 4826 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 4827 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab
MT		 4828 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
4829 !(vcpu->arch.cr0 & X86_CR0_PE))
4830 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4831
b6c7a5dc
HB		 4832 vcpu_put(vcpu);
4833
4834 return 0;
4835}
4836
d0bfb940
JK		 4837int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
4838 struct kvm_guest_debug *dbg)
b6c7a5dc 4839{
355be0b9 4840 unsigned long rflags;
ae675ef0 4841 int i, r;
b6c7a5dc
HB		 4842
4843 vcpu_load(vcpu);
4844
4f926bf2
JK		 4845 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
4846 r = -EBUSY;
4847 if (vcpu->arch.exception.pending)
4848 goto unlock_out;
4849 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
4850 kvm_queue_exception(vcpu, DB_VECTOR);
4851 else
4852 kvm_queue_exception(vcpu, BP_VECTOR);
4853 }
4854
91586a3b
JK		 4855 /*
4856 * Read rflags as long as potentially injected trace flags are still
4857 * filtered out.
4858 */
4859 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 4860
4861 vcpu->guest_debug = dbg->control;
4862 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
4863 vcpu->guest_debug = 0;
4864
4865 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 4866 for (i = 0; i < KVM_NR_DB_REGS; ++i)
4867 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
4868 vcpu->arch.switch_db_regs =
4869 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
4870 } else {
4871 for (i = 0; i < KVM_NR_DB_REGS; i++)
4872 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
4873 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
4874 }
4875
94fe45da
JK		 4876 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
4877 vcpu->arch.singlestep_cs =
4878 get_segment_selector(vcpu, VCPU_SREG_CS);
4879 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu);
4880 }
4881
91586a3b
JK		 4882 /*
4883 * Trigger an rflags update that will inject or remove the trace
4884 * flags.
4885 */
4886 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 4887
355be0b9 4888 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 4889
4f926bf2 4890 r = 0;
d0bfb940 4891
4f926bf2 4892unlock_out:
b6c7a5dc
HB		 4893 vcpu_put(vcpu);
4894
4895 return r;
4896}
4897
d0752060
HB		 4898/*
4899 * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
4900 * we have asm/x86/processor.h
4901 */
4902struct fxsave {
4903 u16 cwd;
4904 u16 swd;
4905 u16 twd;
4906 u16 fop;
4907 u64 rip;
4908 u64 rdp;
4909 u32 mxcsr;
4910 u32 mxcsr_mask;
4911 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
4912#ifdef CONFIG_X86_64
4913 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
4914#else
4915 u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
4916#endif
4917};
4918
8b006791
ZX		 4919/*
4920 * Translate a guest virtual address to a guest physical address.
4921 */
4922int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
4923 struct kvm_translation *tr)
4924{
4925 unsigned long vaddr = tr->linear_address;
4926 gpa_t gpa;
4927
4928 vcpu_load(vcpu);
72dc67a6 4929 down_read(&vcpu->kvm->slots_lock);
ad312c7c 4930 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, vaddr);
72dc67a6 4931 up_read(&vcpu->kvm->slots_lock);
8b006791
ZX		 4932 tr->physical_address = gpa;
4933 tr->valid = gpa != UNMAPPED_GVA;
4934 tr->writeable = 1;
4935 tr->usermode = 0;
8b006791
ZX		 4936 vcpu_put(vcpu);
4937
4938 return 0;
4939}
4940
d0752060
HB		 4941int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
4942{
ad312c7c 4943 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 4944
4945 vcpu_load(vcpu);
4946
4947 memcpy(fpu->fpr, fxsave->st_space, 128);
4948 fpu->fcw = fxsave->cwd;
4949 fpu->fsw = fxsave->swd;
4950 fpu->ftwx = fxsave->twd;
4951 fpu->last_opcode = fxsave->fop;
4952 fpu->last_ip = fxsave->rip;
4953 fpu->last_dp = fxsave->rdp;
4954 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
4955
4956 vcpu_put(vcpu);
4957
4958 return 0;
4959}
4960
4961int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
4962{
ad312c7c 4963 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 4964
4965 vcpu_load(vcpu);
4966
4967 memcpy(fxsave->st_space, fpu->fpr, 128);
4968 fxsave->cwd = fpu->fcw;
4969 fxsave->swd = fpu->fsw;
4970 fxsave->twd = fpu->ftwx;
4971 fxsave->fop = fpu->last_opcode;
4972 fxsave->rip = fpu->last_ip;
4973 fxsave->rdp = fpu->last_dp;
4974 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
4975
4976 vcpu_put(vcpu);
4977
4978 return 0;
4979}
4980
4981void fx_init(struct kvm_vcpu *vcpu)
4982{
4983 unsigned after_mxcsr_mask;
4984
bc1a34f1
AA		 4985 /*
4986 * Touch the fpu the first time in non atomic context as if
4987 * this is the first fpu instruction the exception handler
4988 * will fire before the instruction returns and it'll have to
4989 * allocate ram with GFP_KERNEL.
4990 */
4991 if (!used_math())
d6e88aec 4992 kvm_fx_save(&vcpu->arch.host_fx_image);
bc1a34f1 4993
d0752060
HB		 4994 /* Initialize guest FPU by resetting ours and saving into guest's */
4995 preempt_disable();
d6e88aec
AK		 4996 kvm_fx_save(&vcpu->arch.host_fx_image);
4997 kvm_fx_finit();
4998 kvm_fx_save(&vcpu->arch.guest_fx_image);
4999 kvm_fx_restore(&vcpu->arch.host_fx_image);
d0752060
HB		 5000 preempt_enable();
5001
ad312c7c 5002 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 5003 after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
ad312c7c
ZX		 5004 vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
5005 memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
d0752060
HB		 5006 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
5007}
5008EXPORT_SYMBOL_GPL(fx_init);
5009
5010void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5011{
5012 if (!vcpu->fpu_active || vcpu->guest_fpu_loaded)
5013 return;
5014
5015 vcpu->guest_fpu_loaded = 1;
d6e88aec
AK		 5016 kvm_fx_save(&vcpu->arch.host_fx_image);
5017 kvm_fx_restore(&vcpu->arch.guest_fx_image);
d0752060
HB		 5018}
5019EXPORT_SYMBOL_GPL(kvm_load_guest_fpu);
5020
5021void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5022{
5023 if (!vcpu->guest_fpu_loaded)
5024 return;
5025
5026 vcpu->guest_fpu_loaded = 0;
d6e88aec
AK		 5027 kvm_fx_save(&vcpu->arch.guest_fx_image);
5028 kvm_fx_restore(&vcpu->arch.host_fx_image);
f096ed85 5029 ++vcpu->stat.fpu_reload;
d0752060
HB		 5030}
5031EXPORT_SYMBOL_GPL(kvm_put_guest_fpu);
e9b11c17
ZX		 5032
5033void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5034{
7f1ea208
JR		 5035 if (vcpu->arch.time_page) {
5036 kvm_release_page_dirty(vcpu->arch.time_page);
5037 vcpu->arch.time_page = NULL;
5038 }
5039
e9b11c17
ZX		 5040 kvm_x86_ops->vcpu_free(vcpu);
5041}
5042
5043struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5044 unsigned int id)
5045{
26e5215f
AK		 5046 return kvm_x86_ops->vcpu_create(kvm, id);
5047}
e9b11c17 5048
26e5215f
AK		 5049int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5050{
5051 int r;
e9b11c17
ZX		 5052
5053 /* We do fxsave: this must be aligned. */
ad312c7c 5054 BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
e9b11c17 5055
0bed3b56 5056 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 5057 vcpu_load(vcpu);
5058 r = kvm_arch_vcpu_reset(vcpu);
5059 if (r == 0)
5060 r = kvm_mmu_setup(vcpu);
5061 vcpu_put(vcpu);
5062 if (r < 0)
5063 goto free_vcpu;
5064
26e5215f 5065 return 0;
e9b11c17
ZX		 5066free_vcpu:
5067 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 5068 return r;
e9b11c17
ZX		 5069}
5070
d40ccc62 5071void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 5072{
5073 vcpu_load(vcpu);
5074 kvm_mmu_unload(vcpu);
5075 vcpu_put(vcpu);
5076
5077 kvm_x86_ops->vcpu_free(vcpu);
5078}
5079
5080int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
5081{
448fa4a9
JK		 5082 vcpu->arch.nmi_pending = false;
5083 vcpu->arch.nmi_injected = false;
5084
42dbaa5a
JK		 5085 vcpu->arch.switch_db_regs = 0;
5086 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
5087 vcpu->arch.dr6 = DR6_FIXED_1;
5088 vcpu->arch.dr7 = DR7_FIXED_1;
5089
e9b11c17
ZX		 5090 return kvm_x86_ops->vcpu_reset(vcpu);
5091}
5092
10474ae8 5093int kvm_arch_hardware_enable(void *garbage)
e9b11c17 5094{
0cca7907
ZA		 5095 /*
5096 * Since this may be called from a hotplug notifcation,
5097 * we can't get the CPU frequency directly.
5098 */
5099 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5100 int cpu = raw_smp_processor_id();
5101 per_cpu(cpu_tsc_khz, cpu) = 0;
5102 }
18863bdd
AK		 5103
5104 kvm_shared_msr_cpu_online();
5105
10474ae8 5106 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 5107}
5108
5109void kvm_arch_hardware_disable(void *garbage)
5110{
5111 kvm_x86_ops->hardware_disable(garbage);
3548bab5 5112 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 5113}
5114
5115int kvm_arch_hardware_setup(void)
5116{
5117 return kvm_x86_ops->hardware_setup();
5118}
5119
5120void kvm_arch_hardware_unsetup(void)
5121{
5122 kvm_x86_ops->hardware_unsetup();
5123}
5124
5125void kvm_arch_check_processor_compat(void *rtn)
5126{
5127 kvm_x86_ops->check_processor_compatibility(rtn);
5128}
5129
5130int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
5131{
5132 struct page *page;
5133 struct kvm *kvm;
5134 int r;
5135
5136 BUG_ON(vcpu->kvm == NULL);
5137 kvm = vcpu->kvm;
5138
ad312c7c 5139 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c5af89b6 5140 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 5141 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 5142 else
a4535290 5143 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 5144
5145 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
5146 if (!page) {
5147 r = -ENOMEM;
5148 goto fail;
5149 }
ad312c7c 5150 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 5151
5152 r = kvm_mmu_create(vcpu);
5153 if (r < 0)
5154 goto fail_free_pio_data;
5155
5156 if (irqchip_in_kernel(kvm)) {
5157 r = kvm_create_lapic(vcpu);
5158 if (r < 0)
5159 goto fail_mmu_destroy;
5160 }
5161
890ca9ae
HY		 5162 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
5163 GFP_KERNEL);
5164 if (!vcpu->arch.mce_banks) {
5165 r = -ENOMEM;
443c39bc 5166 goto fail_free_lapic;
890ca9ae
HY		 5167 }
5168 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
5169
e9b11c17 5170 return 0;
443c39bc
WY		 5171fail_free_lapic:
5172 kvm_free_lapic(vcpu);
e9b11c17
ZX		 5173fail_mmu_destroy:
5174 kvm_mmu_destroy(vcpu);
5175fail_free_pio_data:
ad312c7c 5176 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 5177fail:
5178 return r;
5179}
5180
5181void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
5182{
36cb93fd 5183 kfree(vcpu->arch.mce_banks);
e9b11c17 5184 kvm_free_lapic(vcpu);
3200f405 5185 down_read(&vcpu->kvm->slots_lock);
e9b11c17 5186 kvm_mmu_destroy(vcpu);
3200f405 5187 up_read(&vcpu->kvm->slots_lock);
ad312c7c 5188 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 5189}
d19a9cd2
ZX		 5190
5191struct kvm *kvm_arch_create_vm(void)
5192{
5193 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
5194
5195 if (!kvm)
5196 return ERR_PTR(-ENOMEM);
5197
fef9cce0
MT		 5198 kvm->arch.aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
5199 if (!kvm->arch.aliases) {
5200 kfree(kvm);
5201 return ERR_PTR(-ENOMEM);
5202 }
5203
f05e70ac 5204 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 5205 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 5206
5550af4d
SY		 5207 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
5208 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
5209
53f658b3
MT		 5210 rdtscll(kvm->arch.vm_init_tsc);
5211
d19a9cd2
ZX		 5212 return kvm;
5213}
5214
5215static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
5216{
5217 vcpu_load(vcpu);
5218 kvm_mmu_unload(vcpu);
5219 vcpu_put(vcpu);
5220}
5221
5222static void kvm_free_vcpus(struct kvm *kvm)
5223{
5224 unsigned int i;
988a2cae 5225 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 5226
5227 /*
5228 * Unpin any mmu pages first.
5229 */
988a2cae
GN		 5230 kvm_for_each_vcpu(i, vcpu, kvm)
5231 kvm_unload_vcpu_mmu(vcpu);
5232 kvm_for_each_vcpu(i, vcpu, kvm)
5233 kvm_arch_vcpu_free(vcpu);
5234
5235 mutex_lock(&kvm->lock);
5236 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
5237 kvm->vcpus[i] = NULL;
d19a9cd2 5238
988a2cae
GN		 5239 atomic_set(&kvm->online_vcpus, 0);
5240 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 5241}
5242
ad8ba2cd
SY		 5243void kvm_arch_sync_events(struct kvm *kvm)
5244{
ba4cef31 5245 kvm_free_all_assigned_devices(kvm);
ad8ba2cd
SY		 5246}
5247
d19a9cd2
ZX		 5248void kvm_arch_destroy_vm(struct kvm *kvm)
5249{
6eb55818 5250 kvm_iommu_unmap_guest(kvm);
7837699f 5251 kvm_free_pit(kvm);
d7deeeb0
ZX		 5252 kfree(kvm->arch.vpic);
5253 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 5254 kvm_free_vcpus(kvm);
5255 kvm_free_physmem(kvm);
3d45830c
AK		 5256 if (kvm->arch.apic_access_page)
5257 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 5258 if (kvm->arch.ept_identity_pagetable)
5259 put_page(kvm->arch.ept_identity_pagetable);
fef9cce0 5260 kfree(kvm->arch.aliases);
d19a9cd2
ZX		 5261 kfree(kvm);
5262}
0de10343 5263
f7784b8e
MT		 5264int kvm_arch_prepare_memory_region(struct kvm *kvm,
5265 struct kvm_memory_slot *memslot,
0de10343 5266 struct kvm_memory_slot old,
f7784b8e 5267 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 5268 int user_alloc)
5269{
f7784b8e 5270 int npages = memslot->npages;
0de10343
ZX		 5271
5272 /*To keep backward compatibility with older userspace,
5273 *x86 needs to hanlde !user_alloc case.
5274 */
5275 if (!user_alloc) {
5276 if (npages && !old.rmap) {
604b38ac
AA		 5277 unsigned long userspace_addr;
5278
72dc67a6 5279 down_write(&current->mm->mmap_sem);
604b38ac
AA		 5280 userspace_addr = do_mmap(NULL, 0,
5281 npages * PAGE_SIZE,
5282 PROT_READ | PROT_WRITE,
acee3c04 5283 MAP_PRIVATE | MAP_ANONYMOUS,
604b38ac 5284 0);
72dc67a6 5285 up_write(&current->mm->mmap_sem);
0de10343 5286
604b38ac
AA		 5287 if (IS_ERR((void *)userspace_addr))
5288 return PTR_ERR((void *)userspace_addr);
5289
604b38ac 5290 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 5291 }
5292 }
5293
f7784b8e
MT		 5294
5295 return 0;
5296}
5297
5298void kvm_arch_commit_memory_region(struct kvm *kvm,
5299 struct kvm_userspace_memory_region *mem,
5300 struct kvm_memory_slot old,
5301 int user_alloc)
5302{
5303
5304 int npages = mem->memory_size >> PAGE_SHIFT;
5305
5306 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
5307 int ret;
5308
5309 down_write(&current->mm->mmap_sem);
5310 ret = do_munmap(current->mm, old.userspace_addr,
5311 old.npages * PAGE_SIZE);
5312 up_write(&current->mm->mmap_sem);
5313 if (ret < 0)
5314 printk(KERN_WARNING
5315 "kvm_vm_ioctl_set_memory_region: "
5316 "failed to munmap memory\n");
5317 }
5318
7c8a83b7 5319 spin_lock(&kvm->mmu_lock);
f05e70ac 5320 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 5321 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
5322 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
5323 }
5324
5325 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 5326 spin_unlock(&kvm->mmu_lock);
0de10343 5327}
1d737c8a 5328
34d4cb8f
MT		 5329void kvm_arch_flush_shadow(struct kvm *kvm)
5330{
5331 kvm_mmu_zap_all(kvm);
8986ecc0 5332 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 5333}
5334
1d737c8a
ZX		 5335int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
5336{
a4535290 5337 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
a1b37100
GN		 5338 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
5339 || vcpu->arch.nmi_pending ||
5340 (kvm_arch_interrupt_allowed(vcpu) &&
5341 kvm_cpu_has_interrupt(vcpu));
1d737c8a 5342}
5736199a 5343
5736199a
ZX		 5344void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
5345{
32f88400
MT		 5346 int me;
5347 int cpu = vcpu->cpu;
5736199a
ZX		 5348
5349 if (waitqueue_active(&vcpu->wq)) {
5350 wake_up_interruptible(&vcpu->wq);
5351 ++vcpu->stat.halt_wakeup;
5352 }
32f88400
MT		 5353
5354 me = get_cpu();
5355 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
5356 if (!test_and_set_bit(KVM_REQ_KICK, &vcpu->requests))
5357 smp_send_reschedule(cpu);
e9571ed5 5358 put_cpu();
5736199a 5359}
78646121
GN		 5360
5361int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
5362{
5363 return kvm_x86_ops->interrupt_allowed(vcpu);
5364}
229456fc 5365
94fe45da
JK		 5366unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
5367{
5368 unsigned long rflags;
5369
5370 rflags = kvm_x86_ops->get_rflags(vcpu);
5371 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5372 rflags &= ~(unsigned long)(X86_EFLAGS_TF | X86_EFLAGS_RF);
5373 return rflags;
5374}
5375EXPORT_SYMBOL_GPL(kvm_get_rflags);
5376
5377void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
5378{
5379 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
5380 vcpu->arch.singlestep_cs ==
5381 get_segment_selector(vcpu, VCPU_SREG_CS) &&
5382 vcpu->arch.singlestep_rip == kvm_rip_read(vcpu))
5383 rflags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
5384 kvm_x86_ops->set_rflags(vcpu, rflags);
5385}
5386EXPORT_SYMBOL_GPL(kvm_set_rflags);
5387
229456fc
MT		 5388EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
5389EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
5390EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
5391EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
5392EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 5393EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 5394EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 5395EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 5396EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 5397EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 5398EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
Linux kernel - Deliverables
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