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6aa8b732 AK |
1 | /****************************************************************************** |
2 | * x86_emulate.c | |
3 | * | |
4 | * Generic x86 (32-bit and 64-bit) instruction decoder and emulator. | |
5 | * | |
6 | * Copyright (c) 2005 Keir Fraser | |
7 | * | |
8 | * Linux coding style, mod r/m decoder, segment base fixes, real-mode | |
dcc0766b | 9 | * privileged instructions: |
6aa8b732 AK |
10 | * |
11 | * Copyright (C) 2006 Qumranet | |
12 | * | |
13 | * Avi Kivity <avi@qumranet.com> | |
14 | * Yaniv Kamay <yaniv@qumranet.com> | |
15 | * | |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | * | |
19 | * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4 | |
20 | */ | |
21 | ||
22 | #ifndef __KERNEL__ | |
23 | #include <stdio.h> | |
24 | #include <stdint.h> | |
25 | #include <public/xen.h> | |
d77c26fc | 26 | #define DPRINTF(_f, _a ...) printf(_f , ## _a) |
6aa8b732 | 27 | #else |
edf88417 | 28 | #include <linux/kvm_host.h> |
6aa8b732 AK |
29 | #define DPRINTF(x...) do {} while (0) |
30 | #endif | |
6aa8b732 | 31 | #include <linux/module.h> |
edf88417 | 32 | #include <asm/kvm_x86_emulate.h> |
6aa8b732 AK |
33 | |
34 | /* | |
35 | * Opcode effective-address decode tables. | |
36 | * Note that we only emulate instructions that have at least one memory | |
37 | * operand (excluding implicit stack references). We assume that stack | |
38 | * references and instruction fetches will never occur in special memory | |
39 | * areas that require emulation. So, for example, 'mov <imm>,<reg>' need | |
40 | * not be handled. | |
41 | */ | |
42 | ||
43 | /* Operand sizes: 8-bit operands or specified/overridden size. */ | |
44 | #define ByteOp (1<<0) /* 8-bit operands. */ | |
45 | /* Destination operand type. */ | |
46 | #define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */ | |
47 | #define DstReg (2<<1) /* Register operand. */ | |
48 | #define DstMem (3<<1) /* Memory operand. */ | |
49 | #define DstMask (3<<1) | |
50 | /* Source operand type. */ | |
51 | #define SrcNone (0<<3) /* No source operand. */ | |
52 | #define SrcImplicit (0<<3) /* Source operand is implicit in the opcode. */ | |
53 | #define SrcReg (1<<3) /* Register operand. */ | |
54 | #define SrcMem (2<<3) /* Memory operand. */ | |
55 | #define SrcMem16 (3<<3) /* Memory operand (16-bit). */ | |
56 | #define SrcMem32 (4<<3) /* Memory operand (32-bit). */ | |
57 | #define SrcImm (5<<3) /* Immediate operand. */ | |
58 | #define SrcImmByte (6<<3) /* 8-bit sign-extended immediate operand. */ | |
59 | #define SrcMask (7<<3) | |
60 | /* Generic ModRM decode. */ | |
61 | #define ModRM (1<<6) | |
62 | /* Destination is only written; never read. */ | |
63 | #define Mov (1<<7) | |
038e51de | 64 | #define BitOp (1<<8) |
c7e75a3d | 65 | #define MemAbs (1<<9) /* Memory operand is absolute displacement */ |
b9fa9d6b | 66 | #define String (1<<10) /* String instruction (rep capable) */ |
6e3d5dfb | 67 | #define Stack (1<<11) /* Stack instruction (push/pop) */ |
e09d082c AK |
68 | #define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */ |
69 | #define GroupDual (1<<15) /* Alternate decoding of mod == 3 */ | |
70 | #define GroupMask 0xff /* Group number stored in bits 0:7 */ | |
6aa8b732 | 71 | |
43bb19cd | 72 | enum { |
1d6ad207 | 73 | Group1_80, Group1_81, Group1_82, Group1_83, |
d95058a1 | 74 | Group1A, Group3_Byte, Group3, Group4, Group5, Group7, |
43bb19cd AK |
75 | }; |
76 | ||
c7e75a3d | 77 | static u16 opcode_table[256] = { |
6aa8b732 AK |
78 | /* 0x00 - 0x07 */ |
79 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, | |
80 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, | |
81 | 0, 0, 0, 0, | |
82 | /* 0x08 - 0x0F */ | |
83 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, | |
84 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, | |
85 | 0, 0, 0, 0, | |
86 | /* 0x10 - 0x17 */ | |
87 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, | |
88 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, | |
89 | 0, 0, 0, 0, | |
90 | /* 0x18 - 0x1F */ | |
91 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, | |
92 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, | |
93 | 0, 0, 0, 0, | |
94 | /* 0x20 - 0x27 */ | |
95 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, | |
96 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, | |
19eb938e | 97 | SrcImmByte, SrcImm, 0, 0, |
6aa8b732 AK |
98 | /* 0x28 - 0x2F */ |
99 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, | |
100 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, | |
101 | 0, 0, 0, 0, | |
102 | /* 0x30 - 0x37 */ | |
103 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, | |
104 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, | |
105 | 0, 0, 0, 0, | |
106 | /* 0x38 - 0x3F */ | |
107 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, | |
108 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, | |
109 | 0, 0, 0, 0, | |
d77a2507 | 110 | /* 0x40 - 0x47 */ |
33615aa9 | 111 | DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, |
d77a2507 | 112 | /* 0x48 - 0x4F */ |
33615aa9 | 113 | DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, |
7f0aaee0 | 114 | /* 0x50 - 0x57 */ |
6e3d5dfb AK |
115 | SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, |
116 | SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, | |
7f0aaee0 | 117 | /* 0x58 - 0x5F */ |
6e3d5dfb AK |
118 | DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack, |
119 | DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack, | |
7d316911 | 120 | /* 0x60 - 0x67 */ |
6aa8b732 | 121 | 0, 0, 0, DstReg | SrcMem32 | ModRM | Mov /* movsxd (x86/64) */ , |
7d316911 NK |
122 | 0, 0, 0, 0, |
123 | /* 0x68 - 0x6F */ | |
6e3d5dfb | 124 | 0, 0, ImplicitOps | Mov | Stack, 0, |
e70669ab LV |
125 | SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* insb, insw/insd */ |
126 | SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* outsb, outsw/outsd */ | |
55bebde4 NK |
127 | /* 0x70 - 0x77 */ |
128 | ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps, | |
129 | ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps, | |
130 | /* 0x78 - 0x7F */ | |
131 | ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps, | |
132 | ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps, | |
6aa8b732 | 133 | /* 0x80 - 0x87 */ |
1d6ad207 AK |
134 | Group | Group1_80, Group | Group1_81, |
135 | Group | Group1_82, Group | Group1_83, | |
6aa8b732 AK |
136 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, |
137 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, | |
138 | /* 0x88 - 0x8F */ | |
139 | ByteOp | DstMem | SrcReg | ModRM | Mov, DstMem | SrcReg | ModRM | Mov, | |
140 | ByteOp | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, | |
43bb19cd | 141 | 0, ModRM | DstReg, 0, Group | Group1A, |
6aa8b732 | 142 | /* 0x90 - 0x9F */ |
6e3d5dfb AK |
143 | 0, 0, 0, 0, 0, 0, 0, 0, |
144 | 0, 0, 0, 0, ImplicitOps | Stack, ImplicitOps | Stack, 0, 0, | |
6aa8b732 | 145 | /* 0xA0 - 0xA7 */ |
c7e75a3d AK |
146 | ByteOp | DstReg | SrcMem | Mov | MemAbs, DstReg | SrcMem | Mov | MemAbs, |
147 | ByteOp | DstMem | SrcReg | Mov | MemAbs, DstMem | SrcReg | Mov | MemAbs, | |
b9fa9d6b AK |
148 | ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String, |
149 | ByteOp | ImplicitOps | String, ImplicitOps | String, | |
6aa8b732 | 150 | /* 0xA8 - 0xAF */ |
b9fa9d6b AK |
151 | 0, 0, ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String, |
152 | ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String, | |
153 | ByteOp | ImplicitOps | String, ImplicitOps | String, | |
6aa8b732 AK |
154 | /* 0xB0 - 0xBF */ |
155 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
156 | /* 0xC0 - 0xC7 */ | |
d9413cd7 | 157 | ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM, |
6e3d5dfb | 158 | 0, ImplicitOps | Stack, 0, 0, |
d9413cd7 | 159 | ByteOp | DstMem | SrcImm | ModRM | Mov, DstMem | SrcImm | ModRM | Mov, |
6aa8b732 AK |
160 | /* 0xC8 - 0xCF */ |
161 | 0, 0, 0, 0, 0, 0, 0, 0, | |
162 | /* 0xD0 - 0xD7 */ | |
163 | ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM, | |
164 | ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM, | |
165 | 0, 0, 0, 0, | |
166 | /* 0xD8 - 0xDF */ | |
167 | 0, 0, 0, 0, 0, 0, 0, 0, | |
098c937b NK |
168 | /* 0xE0 - 0xE7 */ |
169 | 0, 0, 0, 0, 0, 0, 0, 0, | |
170 | /* 0xE8 - 0xEF */ | |
6e3d5dfb AK |
171 | ImplicitOps | Stack, SrcImm|ImplicitOps, 0, SrcImmByte|ImplicitOps, |
172 | 0, 0, 0, 0, | |
6aa8b732 AK |
173 | /* 0xF0 - 0xF7 */ |
174 | 0, 0, 0, 0, | |
7d858a19 | 175 | ImplicitOps, ImplicitOps, Group | Group3_Byte, Group | Group3, |
6aa8b732 | 176 | /* 0xF8 - 0xFF */ |
b284be57 | 177 | ImplicitOps, 0, ImplicitOps, ImplicitOps, |
fd60754e | 178 | 0, 0, Group | Group4, Group | Group5, |
6aa8b732 AK |
179 | }; |
180 | ||
038e51de | 181 | static u16 twobyte_table[256] = { |
6aa8b732 | 182 | /* 0x00 - 0x0F */ |
d95058a1 | 183 | 0, Group | GroupDual | Group7, 0, 0, 0, 0, ImplicitOps, 0, |
651a3e29 | 184 | ImplicitOps, ImplicitOps, 0, 0, 0, ImplicitOps | ModRM, 0, 0, |
6aa8b732 AK |
185 | /* 0x10 - 0x1F */ |
186 | 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0, | |
187 | /* 0x20 - 0x2F */ | |
188 | ModRM | ImplicitOps, ModRM, ModRM | ImplicitOps, ModRM, 0, 0, 0, 0, | |
189 | 0, 0, 0, 0, 0, 0, 0, 0, | |
190 | /* 0x30 - 0x3F */ | |
35f3f286 | 191 | ImplicitOps, 0, ImplicitOps, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
6aa8b732 AK |
192 | /* 0x40 - 0x47 */ |
193 | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, | |
194 | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, | |
195 | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, | |
196 | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, | |
197 | /* 0x48 - 0x4F */ | |
198 | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, | |
199 | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, | |
200 | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, | |
201 | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, | |
202 | /* 0x50 - 0x5F */ | |
203 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
204 | /* 0x60 - 0x6F */ | |
205 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
206 | /* 0x70 - 0x7F */ | |
207 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
208 | /* 0x80 - 0x8F */ | |
bbe9abbd NK |
209 | ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps, |
210 | ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps, | |
211 | ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps, | |
212 | ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps, | |
6aa8b732 AK |
213 | /* 0x90 - 0x9F */ |
214 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
215 | /* 0xA0 - 0xA7 */ | |
038e51de | 216 | 0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, 0, 0, |
6aa8b732 | 217 | /* 0xA8 - 0xAF */ |
038e51de | 218 | 0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, 0, 0, |
6aa8b732 AK |
219 | /* 0xB0 - 0xB7 */ |
220 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, 0, | |
038e51de | 221 | DstMem | SrcReg | ModRM | BitOp, |
6aa8b732 AK |
222 | 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov, |
223 | DstReg | SrcMem16 | ModRM | Mov, | |
224 | /* 0xB8 - 0xBF */ | |
038e51de | 225 | 0, 0, DstMem | SrcImmByte | ModRM, DstMem | SrcReg | ModRM | BitOp, |
6aa8b732 AK |
226 | 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov, |
227 | DstReg | SrcMem16 | ModRM | Mov, | |
228 | /* 0xC0 - 0xCF */ | |
a012e65a SY |
229 | 0, 0, 0, DstMem | SrcReg | ModRM | Mov, 0, 0, 0, ImplicitOps | ModRM, |
230 | 0, 0, 0, 0, 0, 0, 0, 0, | |
6aa8b732 AK |
231 | /* 0xD0 - 0xDF */ |
232 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
233 | /* 0xE0 - 0xEF */ | |
234 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
235 | /* 0xF0 - 0xFF */ | |
236 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 | |
237 | }; | |
238 | ||
e09d082c | 239 | static u16 group_table[] = { |
1d6ad207 AK |
240 | [Group1_80*8] = |
241 | ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM, | |
242 | ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM, | |
243 | ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM, | |
244 | ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM, | |
245 | [Group1_81*8] = | |
246 | DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM, | |
247 | DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM, | |
248 | DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM, | |
249 | DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM, | |
250 | [Group1_82*8] = | |
251 | ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM, | |
252 | ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM, | |
253 | ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM, | |
254 | ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM, | |
255 | [Group1_83*8] = | |
256 | DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM, | |
257 | DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM, | |
258 | DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM, | |
259 | DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM, | |
43bb19cd AK |
260 | [Group1A*8] = |
261 | DstMem | SrcNone | ModRM | Mov | Stack, 0, 0, 0, 0, 0, 0, 0, | |
7d858a19 AK |
262 | [Group3_Byte*8] = |
263 | ByteOp | SrcImm | DstMem | ModRM, 0, | |
264 | ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM, | |
265 | 0, 0, 0, 0, | |
266 | [Group3*8] = | |
267 | DstMem | SrcImm | ModRM | SrcImm, 0, | |
268 | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM, | |
269 | 0, 0, 0, 0, | |
fd60754e AK |
270 | [Group4*8] = |
271 | ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM, | |
272 | 0, 0, 0, 0, 0, 0, | |
273 | [Group5*8] = | |
274 | DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM, 0, 0, | |
275 | SrcMem | ModRM, 0, SrcMem | ModRM | Stack, 0, | |
d95058a1 AK |
276 | [Group7*8] = |
277 | 0, 0, ModRM | SrcMem, ModRM | SrcMem, | |
16286d08 AK |
278 | SrcNone | ModRM | DstMem | Mov, 0, |
279 | SrcMem16 | ModRM | Mov, SrcMem | ModRM | ByteOp, | |
e09d082c AK |
280 | }; |
281 | ||
282 | static u16 group2_table[] = { | |
d95058a1 | 283 | [Group7*8] = |
16286d08 AK |
284 | SrcNone | ModRM, 0, 0, 0, |
285 | SrcNone | ModRM | DstMem | Mov, 0, | |
286 | SrcMem16 | ModRM | Mov, 0, | |
e09d082c AK |
287 | }; |
288 | ||
6aa8b732 AK |
289 | /* EFLAGS bit definitions. */ |
290 | #define EFLG_OF (1<<11) | |
291 | #define EFLG_DF (1<<10) | |
292 | #define EFLG_SF (1<<7) | |
293 | #define EFLG_ZF (1<<6) | |
294 | #define EFLG_AF (1<<4) | |
295 | #define EFLG_PF (1<<2) | |
296 | #define EFLG_CF (1<<0) | |
297 | ||
298 | /* | |
299 | * Instruction emulation: | |
300 | * Most instructions are emulated directly via a fragment of inline assembly | |
301 | * code. This allows us to save/restore EFLAGS and thus very easily pick up | |
302 | * any modified flags. | |
303 | */ | |
304 | ||
05b3e0c2 | 305 | #if defined(CONFIG_X86_64) |
6aa8b732 AK |
306 | #define _LO32 "k" /* force 32-bit operand */ |
307 | #define _STK "%%rsp" /* stack pointer */ | |
308 | #elif defined(__i386__) | |
309 | #define _LO32 "" /* force 32-bit operand */ | |
310 | #define _STK "%%esp" /* stack pointer */ | |
311 | #endif | |
312 | ||
313 | /* | |
314 | * These EFLAGS bits are restored from saved value during emulation, and | |
315 | * any changes are written back to the saved value after emulation. | |
316 | */ | |
317 | #define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF) | |
318 | ||
319 | /* Before executing instruction: restore necessary bits in EFLAGS. */ | |
e934c9c1 AK |
320 | #define _PRE_EFLAGS(_sav, _msk, _tmp) \ |
321 | /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \ | |
322 | "movl %"_sav",%"_LO32 _tmp"; " \ | |
323 | "push %"_tmp"; " \ | |
324 | "push %"_tmp"; " \ | |
325 | "movl %"_msk",%"_LO32 _tmp"; " \ | |
326 | "andl %"_LO32 _tmp",("_STK"); " \ | |
327 | "pushf; " \ | |
328 | "notl %"_LO32 _tmp"; " \ | |
329 | "andl %"_LO32 _tmp",("_STK"); " \ | |
330 | "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \ | |
331 | "pop %"_tmp"; " \ | |
332 | "orl %"_LO32 _tmp",("_STK"); " \ | |
333 | "popf; " \ | |
334 | "pop %"_sav"; " | |
6aa8b732 AK |
335 | |
336 | /* After executing instruction: write-back necessary bits in EFLAGS. */ | |
337 | #define _POST_EFLAGS(_sav, _msk, _tmp) \ | |
338 | /* _sav |= EFLAGS & _msk; */ \ | |
339 | "pushf; " \ | |
340 | "pop %"_tmp"; " \ | |
341 | "andl %"_msk",%"_LO32 _tmp"; " \ | |
342 | "orl %"_LO32 _tmp",%"_sav"; " | |
343 | ||
344 | /* Raw emulation: instruction has two explicit operands. */ | |
345 | #define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \ | |
346 | do { \ | |
347 | unsigned long _tmp; \ | |
348 | \ | |
349 | switch ((_dst).bytes) { \ | |
350 | case 2: \ | |
351 | __asm__ __volatile__ ( \ | |
d77c26fc | 352 | _PRE_EFLAGS("0", "4", "2") \ |
6aa8b732 | 353 | _op"w %"_wx"3,%1; " \ |
d77c26fc | 354 | _POST_EFLAGS("0", "4", "2") \ |
6aa8b732 AK |
355 | : "=m" (_eflags), "=m" ((_dst).val), \ |
356 | "=&r" (_tmp) \ | |
d77c26fc | 357 | : _wy ((_src).val), "i" (EFLAGS_MASK)); \ |
6aa8b732 AK |
358 | break; \ |
359 | case 4: \ | |
360 | __asm__ __volatile__ ( \ | |
d77c26fc | 361 | _PRE_EFLAGS("0", "4", "2") \ |
6aa8b732 | 362 | _op"l %"_lx"3,%1; " \ |
d77c26fc | 363 | _POST_EFLAGS("0", "4", "2") \ |
6aa8b732 AK |
364 | : "=m" (_eflags), "=m" ((_dst).val), \ |
365 | "=&r" (_tmp) \ | |
d77c26fc | 366 | : _ly ((_src).val), "i" (EFLAGS_MASK)); \ |
6aa8b732 AK |
367 | break; \ |
368 | case 8: \ | |
369 | __emulate_2op_8byte(_op, _src, _dst, \ | |
370 | _eflags, _qx, _qy); \ | |
371 | break; \ | |
372 | } \ | |
373 | } while (0) | |
374 | ||
375 | #define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \ | |
376 | do { \ | |
77cd337f | 377 | unsigned long __tmp; \ |
d77c26fc | 378 | switch ((_dst).bytes) { \ |
6aa8b732 AK |
379 | case 1: \ |
380 | __asm__ __volatile__ ( \ | |
d77c26fc | 381 | _PRE_EFLAGS("0", "4", "2") \ |
6aa8b732 | 382 | _op"b %"_bx"3,%1; " \ |
d77c26fc | 383 | _POST_EFLAGS("0", "4", "2") \ |
6aa8b732 | 384 | : "=m" (_eflags), "=m" ((_dst).val), \ |
77cd337f | 385 | "=&r" (__tmp) \ |
d77c26fc | 386 | : _by ((_src).val), "i" (EFLAGS_MASK)); \ |
6aa8b732 AK |
387 | break; \ |
388 | default: \ | |
389 | __emulate_2op_nobyte(_op, _src, _dst, _eflags, \ | |
390 | _wx, _wy, _lx, _ly, _qx, _qy); \ | |
391 | break; \ | |
392 | } \ | |
393 | } while (0) | |
394 | ||
395 | /* Source operand is byte-sized and may be restricted to just %cl. */ | |
396 | #define emulate_2op_SrcB(_op, _src, _dst, _eflags) \ | |
397 | __emulate_2op(_op, _src, _dst, _eflags, \ | |
398 | "b", "c", "b", "c", "b", "c", "b", "c") | |
399 | ||
400 | /* Source operand is byte, word, long or quad sized. */ | |
401 | #define emulate_2op_SrcV(_op, _src, _dst, _eflags) \ | |
402 | __emulate_2op(_op, _src, _dst, _eflags, \ | |
403 | "b", "q", "w", "r", _LO32, "r", "", "r") | |
404 | ||
405 | /* Source operand is word, long or quad sized. */ | |
406 | #define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \ | |
407 | __emulate_2op_nobyte(_op, _src, _dst, _eflags, \ | |
408 | "w", "r", _LO32, "r", "", "r") | |
409 | ||
410 | /* Instruction has only one explicit operand (no source operand). */ | |
411 | #define emulate_1op(_op, _dst, _eflags) \ | |
412 | do { \ | |
413 | unsigned long _tmp; \ | |
414 | \ | |
d77c26fc | 415 | switch ((_dst).bytes) { \ |
6aa8b732 AK |
416 | case 1: \ |
417 | __asm__ __volatile__ ( \ | |
d77c26fc | 418 | _PRE_EFLAGS("0", "3", "2") \ |
6aa8b732 | 419 | _op"b %1; " \ |
d77c26fc | 420 | _POST_EFLAGS("0", "3", "2") \ |
6aa8b732 AK |
421 | : "=m" (_eflags), "=m" ((_dst).val), \ |
422 | "=&r" (_tmp) \ | |
d77c26fc | 423 | : "i" (EFLAGS_MASK)); \ |
6aa8b732 AK |
424 | break; \ |
425 | case 2: \ | |
426 | __asm__ __volatile__ ( \ | |
d77c26fc | 427 | _PRE_EFLAGS("0", "3", "2") \ |
6aa8b732 | 428 | _op"w %1; " \ |
d77c26fc | 429 | _POST_EFLAGS("0", "3", "2") \ |
6aa8b732 AK |
430 | : "=m" (_eflags), "=m" ((_dst).val), \ |
431 | "=&r" (_tmp) \ | |
d77c26fc | 432 | : "i" (EFLAGS_MASK)); \ |
6aa8b732 AK |
433 | break; \ |
434 | case 4: \ | |
435 | __asm__ __volatile__ ( \ | |
d77c26fc | 436 | _PRE_EFLAGS("0", "3", "2") \ |
6aa8b732 | 437 | _op"l %1; " \ |
d77c26fc | 438 | _POST_EFLAGS("0", "3", "2") \ |
6aa8b732 AK |
439 | : "=m" (_eflags), "=m" ((_dst).val), \ |
440 | "=&r" (_tmp) \ | |
d77c26fc | 441 | : "i" (EFLAGS_MASK)); \ |
6aa8b732 AK |
442 | break; \ |
443 | case 8: \ | |
444 | __emulate_1op_8byte(_op, _dst, _eflags); \ | |
445 | break; \ | |
446 | } \ | |
447 | } while (0) | |
448 | ||
449 | /* Emulate an instruction with quadword operands (x86/64 only). */ | |
05b3e0c2 | 450 | #if defined(CONFIG_X86_64) |
6aa8b732 AK |
451 | #define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy) \ |
452 | do { \ | |
453 | __asm__ __volatile__ ( \ | |
d77c26fc | 454 | _PRE_EFLAGS("0", "4", "2") \ |
6aa8b732 | 455 | _op"q %"_qx"3,%1; " \ |
d77c26fc | 456 | _POST_EFLAGS("0", "4", "2") \ |
6aa8b732 | 457 | : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \ |
d77c26fc | 458 | : _qy ((_src).val), "i" (EFLAGS_MASK)); \ |
6aa8b732 AK |
459 | } while (0) |
460 | ||
461 | #define __emulate_1op_8byte(_op, _dst, _eflags) \ | |
462 | do { \ | |
463 | __asm__ __volatile__ ( \ | |
d77c26fc | 464 | _PRE_EFLAGS("0", "3", "2") \ |
6aa8b732 | 465 | _op"q %1; " \ |
d77c26fc | 466 | _POST_EFLAGS("0", "3", "2") \ |
6aa8b732 | 467 | : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \ |
d77c26fc | 468 | : "i" (EFLAGS_MASK)); \ |
6aa8b732 AK |
469 | } while (0) |
470 | ||
471 | #elif defined(__i386__) | |
472 | #define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy) | |
473 | #define __emulate_1op_8byte(_op, _dst, _eflags) | |
474 | #endif /* __i386__ */ | |
475 | ||
476 | /* Fetch next part of the instruction being emulated. */ | |
477 | #define insn_fetch(_type, _size, _eip) \ | |
478 | ({ unsigned long _x; \ | |
62266869 | 479 | rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \ |
d77c26fc | 480 | if (rc != 0) \ |
6aa8b732 AK |
481 | goto done; \ |
482 | (_eip) += (_size); \ | |
483 | (_type)_x; \ | |
484 | }) | |
485 | ||
ddcb2885 HH |
486 | static inline unsigned long ad_mask(struct decode_cache *c) |
487 | { | |
488 | return (1UL << (c->ad_bytes << 3)) - 1; | |
489 | } | |
490 | ||
6aa8b732 | 491 | /* Access/update address held in a register, based on addressing mode. */ |
e4706772 HH |
492 | static inline unsigned long |
493 | address_mask(struct decode_cache *c, unsigned long reg) | |
494 | { | |
495 | if (c->ad_bytes == sizeof(unsigned long)) | |
496 | return reg; | |
497 | else | |
498 | return reg & ad_mask(c); | |
499 | } | |
500 | ||
501 | static inline unsigned long | |
502 | register_address(struct decode_cache *c, unsigned long base, unsigned long reg) | |
503 | { | |
504 | return base + address_mask(c, reg); | |
505 | } | |
506 | ||
7a957275 HH |
507 | static inline void |
508 | register_address_increment(struct decode_cache *c, unsigned long *reg, int inc) | |
509 | { | |
510 | if (c->ad_bytes == sizeof(unsigned long)) | |
511 | *reg += inc; | |
512 | else | |
513 | *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c)); | |
514 | } | |
6aa8b732 | 515 | |
7a957275 HH |
516 | static inline void jmp_rel(struct decode_cache *c, int rel) |
517 | { | |
518 | register_address_increment(c, &c->eip, rel); | |
519 | } | |
098c937b | 520 | |
62266869 AK |
521 | static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt, |
522 | struct x86_emulate_ops *ops, | |
523 | unsigned long linear, u8 *dest) | |
524 | { | |
525 | struct fetch_cache *fc = &ctxt->decode.fetch; | |
526 | int rc; | |
527 | int size; | |
528 | ||
529 | if (linear < fc->start || linear >= fc->end) { | |
530 | size = min(15UL, PAGE_SIZE - offset_in_page(linear)); | |
531 | rc = ops->read_std(linear, fc->data, size, ctxt->vcpu); | |
532 | if (rc) | |
533 | return rc; | |
534 | fc->start = linear; | |
535 | fc->end = linear + size; | |
536 | } | |
537 | *dest = fc->data[linear - fc->start]; | |
538 | return 0; | |
539 | } | |
540 | ||
541 | static int do_insn_fetch(struct x86_emulate_ctxt *ctxt, | |
542 | struct x86_emulate_ops *ops, | |
543 | unsigned long eip, void *dest, unsigned size) | |
544 | { | |
545 | int rc = 0; | |
546 | ||
547 | eip += ctxt->cs_base; | |
548 | while (size--) { | |
549 | rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++); | |
550 | if (rc) | |
551 | return rc; | |
552 | } | |
553 | return 0; | |
554 | } | |
555 | ||
1e3c5cb0 RR |
556 | /* |
557 | * Given the 'reg' portion of a ModRM byte, and a register block, return a | |
558 | * pointer into the block that addresses the relevant register. | |
559 | * @highbyte_regs specifies whether to decode AH,CH,DH,BH. | |
560 | */ | |
561 | static void *decode_register(u8 modrm_reg, unsigned long *regs, | |
562 | int highbyte_regs) | |
6aa8b732 AK |
563 | { |
564 | void *p; | |
565 | ||
566 | p = ®s[modrm_reg]; | |
567 | if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8) | |
568 | p = (unsigned char *)®s[modrm_reg & 3] + 1; | |
569 | return p; | |
570 | } | |
571 | ||
572 | static int read_descriptor(struct x86_emulate_ctxt *ctxt, | |
573 | struct x86_emulate_ops *ops, | |
574 | void *ptr, | |
575 | u16 *size, unsigned long *address, int op_bytes) | |
576 | { | |
577 | int rc; | |
578 | ||
579 | if (op_bytes == 2) | |
580 | op_bytes = 3; | |
581 | *address = 0; | |
cebff02b LV |
582 | rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2, |
583 | ctxt->vcpu); | |
6aa8b732 AK |
584 | if (rc) |
585 | return rc; | |
cebff02b LV |
586 | rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes, |
587 | ctxt->vcpu); | |
6aa8b732 AK |
588 | return rc; |
589 | } | |
590 | ||
bbe9abbd NK |
591 | static int test_cc(unsigned int condition, unsigned int flags) |
592 | { | |
593 | int rc = 0; | |
594 | ||
595 | switch ((condition & 15) >> 1) { | |
596 | case 0: /* o */ | |
597 | rc |= (flags & EFLG_OF); | |
598 | break; | |
599 | case 1: /* b/c/nae */ | |
600 | rc |= (flags & EFLG_CF); | |
601 | break; | |
602 | case 2: /* z/e */ | |
603 | rc |= (flags & EFLG_ZF); | |
604 | break; | |
605 | case 3: /* be/na */ | |
606 | rc |= (flags & (EFLG_CF|EFLG_ZF)); | |
607 | break; | |
608 | case 4: /* s */ | |
609 | rc |= (flags & EFLG_SF); | |
610 | break; | |
611 | case 5: /* p/pe */ | |
612 | rc |= (flags & EFLG_PF); | |
613 | break; | |
614 | case 7: /* le/ng */ | |
615 | rc |= (flags & EFLG_ZF); | |
616 | /* fall through */ | |
617 | case 6: /* l/nge */ | |
618 | rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF)); | |
619 | break; | |
620 | } | |
621 | ||
622 | /* Odd condition identifiers (lsb == 1) have inverted sense. */ | |
623 | return (!!rc ^ (condition & 1)); | |
624 | } | |
625 | ||
3c118e24 AK |
626 | static void decode_register_operand(struct operand *op, |
627 | struct decode_cache *c, | |
3c118e24 AK |
628 | int inhibit_bytereg) |
629 | { | |
33615aa9 | 630 | unsigned reg = c->modrm_reg; |
9f1ef3f8 | 631 | int highbyte_regs = c->rex_prefix == 0; |
33615aa9 AK |
632 | |
633 | if (!(c->d & ModRM)) | |
634 | reg = (c->b & 7) | ((c->rex_prefix & 1) << 3); | |
3c118e24 AK |
635 | op->type = OP_REG; |
636 | if ((c->d & ByteOp) && !inhibit_bytereg) { | |
33615aa9 | 637 | op->ptr = decode_register(reg, c->regs, highbyte_regs); |
3c118e24 AK |
638 | op->val = *(u8 *)op->ptr; |
639 | op->bytes = 1; | |
640 | } else { | |
33615aa9 | 641 | op->ptr = decode_register(reg, c->regs, 0); |
3c118e24 AK |
642 | op->bytes = c->op_bytes; |
643 | switch (op->bytes) { | |
644 | case 2: | |
645 | op->val = *(u16 *)op->ptr; | |
646 | break; | |
647 | case 4: | |
648 | op->val = *(u32 *)op->ptr; | |
649 | break; | |
650 | case 8: | |
651 | op->val = *(u64 *) op->ptr; | |
652 | break; | |
653 | } | |
654 | } | |
655 | op->orig_val = op->val; | |
656 | } | |
657 | ||
1c73ef66 AK |
658 | static int decode_modrm(struct x86_emulate_ctxt *ctxt, |
659 | struct x86_emulate_ops *ops) | |
660 | { | |
661 | struct decode_cache *c = &ctxt->decode; | |
662 | u8 sib; | |
663 | int index_reg = 0, base_reg = 0, scale, rip_relative = 0; | |
664 | int rc = 0; | |
665 | ||
666 | if (c->rex_prefix) { | |
667 | c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */ | |
668 | index_reg = (c->rex_prefix & 2) << 2; /* REX.X */ | |
669 | c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */ | |
670 | } | |
671 | ||
672 | c->modrm = insn_fetch(u8, 1, c->eip); | |
673 | c->modrm_mod |= (c->modrm & 0xc0) >> 6; | |
674 | c->modrm_reg |= (c->modrm & 0x38) >> 3; | |
675 | c->modrm_rm |= (c->modrm & 0x07); | |
676 | c->modrm_ea = 0; | |
677 | c->use_modrm_ea = 1; | |
678 | ||
679 | if (c->modrm_mod == 3) { | |
107d6d2e AK |
680 | c->modrm_ptr = decode_register(c->modrm_rm, |
681 | c->regs, c->d & ByteOp); | |
682 | c->modrm_val = *(unsigned long *)c->modrm_ptr; | |
1c73ef66 AK |
683 | return rc; |
684 | } | |
685 | ||
686 | if (c->ad_bytes == 2) { | |
687 | unsigned bx = c->regs[VCPU_REGS_RBX]; | |
688 | unsigned bp = c->regs[VCPU_REGS_RBP]; | |
689 | unsigned si = c->regs[VCPU_REGS_RSI]; | |
690 | unsigned di = c->regs[VCPU_REGS_RDI]; | |
691 | ||
692 | /* 16-bit ModR/M decode. */ | |
693 | switch (c->modrm_mod) { | |
694 | case 0: | |
695 | if (c->modrm_rm == 6) | |
696 | c->modrm_ea += insn_fetch(u16, 2, c->eip); | |
697 | break; | |
698 | case 1: | |
699 | c->modrm_ea += insn_fetch(s8, 1, c->eip); | |
700 | break; | |
701 | case 2: | |
702 | c->modrm_ea += insn_fetch(u16, 2, c->eip); | |
703 | break; | |
704 | } | |
705 | switch (c->modrm_rm) { | |
706 | case 0: | |
707 | c->modrm_ea += bx + si; | |
708 | break; | |
709 | case 1: | |
710 | c->modrm_ea += bx + di; | |
711 | break; | |
712 | case 2: | |
713 | c->modrm_ea += bp + si; | |
714 | break; | |
715 | case 3: | |
716 | c->modrm_ea += bp + di; | |
717 | break; | |
718 | case 4: | |
719 | c->modrm_ea += si; | |
720 | break; | |
721 | case 5: | |
722 | c->modrm_ea += di; | |
723 | break; | |
724 | case 6: | |
725 | if (c->modrm_mod != 0) | |
726 | c->modrm_ea += bp; | |
727 | break; | |
728 | case 7: | |
729 | c->modrm_ea += bx; | |
730 | break; | |
731 | } | |
732 | if (c->modrm_rm == 2 || c->modrm_rm == 3 || | |
733 | (c->modrm_rm == 6 && c->modrm_mod != 0)) | |
734 | if (!c->override_base) | |
735 | c->override_base = &ctxt->ss_base; | |
736 | c->modrm_ea = (u16)c->modrm_ea; | |
737 | } else { | |
738 | /* 32/64-bit ModR/M decode. */ | |
739 | switch (c->modrm_rm) { | |
740 | case 4: | |
741 | case 12: | |
742 | sib = insn_fetch(u8, 1, c->eip); | |
743 | index_reg |= (sib >> 3) & 7; | |
744 | base_reg |= sib & 7; | |
745 | scale = sib >> 6; | |
746 | ||
747 | switch (base_reg) { | |
748 | case 5: | |
749 | if (c->modrm_mod != 0) | |
750 | c->modrm_ea += c->regs[base_reg]; | |
751 | else | |
752 | c->modrm_ea += | |
753 | insn_fetch(s32, 4, c->eip); | |
754 | break; | |
755 | default: | |
756 | c->modrm_ea += c->regs[base_reg]; | |
757 | } | |
758 | switch (index_reg) { | |
759 | case 4: | |
760 | break; | |
761 | default: | |
762 | c->modrm_ea += c->regs[index_reg] << scale; | |
763 | } | |
764 | break; | |
765 | case 5: | |
766 | if (c->modrm_mod != 0) | |
767 | c->modrm_ea += c->regs[c->modrm_rm]; | |
768 | else if (ctxt->mode == X86EMUL_MODE_PROT64) | |
769 | rip_relative = 1; | |
770 | break; | |
771 | default: | |
772 | c->modrm_ea += c->regs[c->modrm_rm]; | |
773 | break; | |
774 | } | |
775 | switch (c->modrm_mod) { | |
776 | case 0: | |
777 | if (c->modrm_rm == 5) | |
778 | c->modrm_ea += insn_fetch(s32, 4, c->eip); | |
779 | break; | |
780 | case 1: | |
781 | c->modrm_ea += insn_fetch(s8, 1, c->eip); | |
782 | break; | |
783 | case 2: | |
784 | c->modrm_ea += insn_fetch(s32, 4, c->eip); | |
785 | break; | |
786 | } | |
787 | } | |
788 | if (rip_relative) { | |
789 | c->modrm_ea += c->eip; | |
790 | switch (c->d & SrcMask) { | |
791 | case SrcImmByte: | |
792 | c->modrm_ea += 1; | |
793 | break; | |
794 | case SrcImm: | |
795 | if (c->d & ByteOp) | |
796 | c->modrm_ea += 1; | |
797 | else | |
798 | if (c->op_bytes == 8) | |
799 | c->modrm_ea += 4; | |
800 | else | |
801 | c->modrm_ea += c->op_bytes; | |
802 | } | |
803 | } | |
804 | done: | |
805 | return rc; | |
806 | } | |
807 | ||
808 | static int decode_abs(struct x86_emulate_ctxt *ctxt, | |
809 | struct x86_emulate_ops *ops) | |
810 | { | |
811 | struct decode_cache *c = &ctxt->decode; | |
812 | int rc = 0; | |
813 | ||
814 | switch (c->ad_bytes) { | |
815 | case 2: | |
816 | c->modrm_ea = insn_fetch(u16, 2, c->eip); | |
817 | break; | |
818 | case 4: | |
819 | c->modrm_ea = insn_fetch(u32, 4, c->eip); | |
820 | break; | |
821 | case 8: | |
822 | c->modrm_ea = insn_fetch(u64, 8, c->eip); | |
823 | break; | |
824 | } | |
825 | done: | |
826 | return rc; | |
827 | } | |
828 | ||
6aa8b732 | 829 | int |
8b4caf66 | 830 | x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops) |
6aa8b732 | 831 | { |
e4e03ded | 832 | struct decode_cache *c = &ctxt->decode; |
6aa8b732 | 833 | int rc = 0; |
6aa8b732 | 834 | int mode = ctxt->mode; |
e09d082c | 835 | int def_op_bytes, def_ad_bytes, group; |
6aa8b732 AK |
836 | |
837 | /* Shadow copy of register state. Committed on successful emulation. */ | |
6aa8b732 | 838 | |
e4e03ded | 839 | memset(c, 0, sizeof(struct decode_cache)); |
ad312c7c ZX |
840 | c->eip = ctxt->vcpu->arch.rip; |
841 | memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs); | |
6aa8b732 AK |
842 | |
843 | switch (mode) { | |
844 | case X86EMUL_MODE_REAL: | |
845 | case X86EMUL_MODE_PROT16: | |
f21b8bf4 | 846 | def_op_bytes = def_ad_bytes = 2; |
6aa8b732 AK |
847 | break; |
848 | case X86EMUL_MODE_PROT32: | |
f21b8bf4 | 849 | def_op_bytes = def_ad_bytes = 4; |
6aa8b732 | 850 | break; |
05b3e0c2 | 851 | #ifdef CONFIG_X86_64 |
6aa8b732 | 852 | case X86EMUL_MODE_PROT64: |
f21b8bf4 AK |
853 | def_op_bytes = 4; |
854 | def_ad_bytes = 8; | |
6aa8b732 AK |
855 | break; |
856 | #endif | |
857 | default: | |
858 | return -1; | |
859 | } | |
860 | ||
f21b8bf4 AK |
861 | c->op_bytes = def_op_bytes; |
862 | c->ad_bytes = def_ad_bytes; | |
863 | ||
6aa8b732 | 864 | /* Legacy prefixes. */ |
b4c6abfe | 865 | for (;;) { |
e4e03ded | 866 | switch (c->b = insn_fetch(u8, 1, c->eip)) { |
6aa8b732 | 867 | case 0x66: /* operand-size override */ |
f21b8bf4 AK |
868 | /* switch between 2/4 bytes */ |
869 | c->op_bytes = def_op_bytes ^ 6; | |
6aa8b732 AK |
870 | break; |
871 | case 0x67: /* address-size override */ | |
872 | if (mode == X86EMUL_MODE_PROT64) | |
e4e03ded | 873 | /* switch between 4/8 bytes */ |
f21b8bf4 | 874 | c->ad_bytes = def_ad_bytes ^ 12; |
6aa8b732 | 875 | else |
e4e03ded | 876 | /* switch between 2/4 bytes */ |
f21b8bf4 | 877 | c->ad_bytes = def_ad_bytes ^ 6; |
6aa8b732 AK |
878 | break; |
879 | case 0x2e: /* CS override */ | |
e4e03ded | 880 | c->override_base = &ctxt->cs_base; |
6aa8b732 AK |
881 | break; |
882 | case 0x3e: /* DS override */ | |
e4e03ded | 883 | c->override_base = &ctxt->ds_base; |
6aa8b732 AK |
884 | break; |
885 | case 0x26: /* ES override */ | |
e4e03ded | 886 | c->override_base = &ctxt->es_base; |
6aa8b732 AK |
887 | break; |
888 | case 0x64: /* FS override */ | |
e4e03ded | 889 | c->override_base = &ctxt->fs_base; |
6aa8b732 AK |
890 | break; |
891 | case 0x65: /* GS override */ | |
e4e03ded | 892 | c->override_base = &ctxt->gs_base; |
6aa8b732 AK |
893 | break; |
894 | case 0x36: /* SS override */ | |
e4e03ded | 895 | c->override_base = &ctxt->ss_base; |
6aa8b732 | 896 | break; |
b4c6abfe LV |
897 | case 0x40 ... 0x4f: /* REX */ |
898 | if (mode != X86EMUL_MODE_PROT64) | |
899 | goto done_prefixes; | |
33615aa9 | 900 | c->rex_prefix = c->b; |
b4c6abfe | 901 | continue; |
6aa8b732 | 902 | case 0xf0: /* LOCK */ |
e4e03ded | 903 | c->lock_prefix = 1; |
6aa8b732 | 904 | break; |
ae6200ba | 905 | case 0xf2: /* REPNE/REPNZ */ |
90e0a28f GT |
906 | c->rep_prefix = REPNE_PREFIX; |
907 | break; | |
6aa8b732 | 908 | case 0xf3: /* REP/REPE/REPZ */ |
90e0a28f | 909 | c->rep_prefix = REPE_PREFIX; |
6aa8b732 | 910 | break; |
6aa8b732 AK |
911 | default: |
912 | goto done_prefixes; | |
913 | } | |
b4c6abfe LV |
914 | |
915 | /* Any legacy prefix after a REX prefix nullifies its effect. */ | |
916 | ||
33615aa9 | 917 | c->rex_prefix = 0; |
6aa8b732 AK |
918 | } |
919 | ||
920 | done_prefixes: | |
921 | ||
922 | /* REX prefix. */ | |
1c73ef66 | 923 | if (c->rex_prefix) |
33615aa9 | 924 | if (c->rex_prefix & 8) |
e4e03ded | 925 | c->op_bytes = 8; /* REX.W */ |
6aa8b732 AK |
926 | |
927 | /* Opcode byte(s). */ | |
e4e03ded LV |
928 | c->d = opcode_table[c->b]; |
929 | if (c->d == 0) { | |
6aa8b732 | 930 | /* Two-byte opcode? */ |
e4e03ded LV |
931 | if (c->b == 0x0f) { |
932 | c->twobyte = 1; | |
933 | c->b = insn_fetch(u8, 1, c->eip); | |
934 | c->d = twobyte_table[c->b]; | |
6aa8b732 | 935 | } |
e09d082c | 936 | } |
6aa8b732 | 937 | |
e09d082c AK |
938 | if (c->d & Group) { |
939 | group = c->d & GroupMask; | |
940 | c->modrm = insn_fetch(u8, 1, c->eip); | |
941 | --c->eip; | |
942 | ||
943 | group = (group << 3) + ((c->modrm >> 3) & 7); | |
944 | if ((c->d & GroupDual) && (c->modrm >> 6) == 3) | |
945 | c->d = group2_table[group]; | |
946 | else | |
947 | c->d = group_table[group]; | |
948 | } | |
949 | ||
950 | /* Unrecognised? */ | |
951 | if (c->d == 0) { | |
952 | DPRINTF("Cannot emulate %02x\n", c->b); | |
953 | return -1; | |
6aa8b732 AK |
954 | } |
955 | ||
6e3d5dfb AK |
956 | if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack)) |
957 | c->op_bytes = 8; | |
958 | ||
6aa8b732 | 959 | /* ModRM and SIB bytes. */ |
1c73ef66 AK |
960 | if (c->d & ModRM) |
961 | rc = decode_modrm(ctxt, ops); | |
962 | else if (c->d & MemAbs) | |
963 | rc = decode_abs(ctxt, ops); | |
964 | if (rc) | |
965 | goto done; | |
6aa8b732 | 966 | |
c7e75a3d AK |
967 | if (!c->override_base) |
968 | c->override_base = &ctxt->ds_base; | |
969 | if (mode == X86EMUL_MODE_PROT64 && | |
970 | c->override_base != &ctxt->fs_base && | |
971 | c->override_base != &ctxt->gs_base) | |
972 | c->override_base = NULL; | |
973 | ||
974 | if (c->override_base) | |
975 | c->modrm_ea += *c->override_base; | |
976 | ||
977 | if (c->ad_bytes != 8) | |
978 | c->modrm_ea = (u32)c->modrm_ea; | |
6aa8b732 AK |
979 | /* |
980 | * Decode and fetch the source operand: register, memory | |
981 | * or immediate. | |
982 | */ | |
e4e03ded | 983 | switch (c->d & SrcMask) { |
6aa8b732 AK |
984 | case SrcNone: |
985 | break; | |
986 | case SrcReg: | |
9f1ef3f8 | 987 | decode_register_operand(&c->src, c, 0); |
6aa8b732 AK |
988 | break; |
989 | case SrcMem16: | |
e4e03ded | 990 | c->src.bytes = 2; |
6aa8b732 AK |
991 | goto srcmem_common; |
992 | case SrcMem32: | |
e4e03ded | 993 | c->src.bytes = 4; |
6aa8b732 AK |
994 | goto srcmem_common; |
995 | case SrcMem: | |
e4e03ded LV |
996 | c->src.bytes = (c->d & ByteOp) ? 1 : |
997 | c->op_bytes; | |
b85b9ee9 | 998 | /* Don't fetch the address for invlpg: it could be unmapped. */ |
d77c26fc | 999 | if (c->twobyte && c->b == 0x01 && c->modrm_reg == 7) |
b85b9ee9 | 1000 | break; |
d77c26fc | 1001 | srcmem_common: |
4e62417b AJ |
1002 | /* |
1003 | * For instructions with a ModR/M byte, switch to register | |
1004 | * access if Mod = 3. | |
1005 | */ | |
e4e03ded LV |
1006 | if ((c->d & ModRM) && c->modrm_mod == 3) { |
1007 | c->src.type = OP_REG; | |
66b85505 | 1008 | c->src.val = c->modrm_val; |
107d6d2e | 1009 | c->src.ptr = c->modrm_ptr; |
4e62417b AJ |
1010 | break; |
1011 | } | |
e4e03ded | 1012 | c->src.type = OP_MEM; |
6aa8b732 AK |
1013 | break; |
1014 | case SrcImm: | |
e4e03ded LV |
1015 | c->src.type = OP_IMM; |
1016 | c->src.ptr = (unsigned long *)c->eip; | |
1017 | c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
1018 | if (c->src.bytes == 8) | |
1019 | c->src.bytes = 4; | |
6aa8b732 | 1020 | /* NB. Immediates are sign-extended as necessary. */ |
e4e03ded | 1021 | switch (c->src.bytes) { |
6aa8b732 | 1022 | case 1: |
e4e03ded | 1023 | c->src.val = insn_fetch(s8, 1, c->eip); |
6aa8b732 AK |
1024 | break; |
1025 | case 2: | |
e4e03ded | 1026 | c->src.val = insn_fetch(s16, 2, c->eip); |
6aa8b732 AK |
1027 | break; |
1028 | case 4: | |
e4e03ded | 1029 | c->src.val = insn_fetch(s32, 4, c->eip); |
6aa8b732 AK |
1030 | break; |
1031 | } | |
1032 | break; | |
1033 | case SrcImmByte: | |
e4e03ded LV |
1034 | c->src.type = OP_IMM; |
1035 | c->src.ptr = (unsigned long *)c->eip; | |
1036 | c->src.bytes = 1; | |
1037 | c->src.val = insn_fetch(s8, 1, c->eip); | |
6aa8b732 AK |
1038 | break; |
1039 | } | |
1040 | ||
038e51de | 1041 | /* Decode and fetch the destination operand: register or memory. */ |
e4e03ded | 1042 | switch (c->d & DstMask) { |
038e51de AK |
1043 | case ImplicitOps: |
1044 | /* Special instructions do their own operand decoding. */ | |
8b4caf66 | 1045 | return 0; |
038e51de | 1046 | case DstReg: |
9f1ef3f8 | 1047 | decode_register_operand(&c->dst, c, |
3c118e24 | 1048 | c->twobyte && (c->b == 0xb6 || c->b == 0xb7)); |
038e51de AK |
1049 | break; |
1050 | case DstMem: | |
e4e03ded LV |
1051 | if ((c->d & ModRM) && c->modrm_mod == 3) { |
1052 | c->dst.type = OP_REG; | |
66b85505 | 1053 | c->dst.val = c->dst.orig_val = c->modrm_val; |
107d6d2e | 1054 | c->dst.ptr = c->modrm_ptr; |
4e62417b AJ |
1055 | break; |
1056 | } | |
8b4caf66 LV |
1057 | c->dst.type = OP_MEM; |
1058 | break; | |
1059 | } | |
1060 | ||
1061 | done: | |
1062 | return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0; | |
1063 | } | |
1064 | ||
8cdbd2c9 LV |
1065 | static inline void emulate_push(struct x86_emulate_ctxt *ctxt) |
1066 | { | |
1067 | struct decode_cache *c = &ctxt->decode; | |
1068 | ||
1069 | c->dst.type = OP_MEM; | |
1070 | c->dst.bytes = c->op_bytes; | |
1071 | c->dst.val = c->src.val; | |
7a957275 | 1072 | register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes); |
e4706772 | 1073 | c->dst.ptr = (void *) register_address(c, ctxt->ss_base, |
8cdbd2c9 LV |
1074 | c->regs[VCPU_REGS_RSP]); |
1075 | } | |
1076 | ||
1077 | static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt, | |
1078 | struct x86_emulate_ops *ops) | |
1079 | { | |
1080 | struct decode_cache *c = &ctxt->decode; | |
1081 | int rc; | |
1082 | ||
e4706772 | 1083 | rc = ops->read_std(register_address(c, ctxt->ss_base, |
8cdbd2c9 LV |
1084 | c->regs[VCPU_REGS_RSP]), |
1085 | &c->dst.val, c->dst.bytes, ctxt->vcpu); | |
1086 | if (rc != 0) | |
1087 | return rc; | |
1088 | ||
7a957275 | 1089 | register_address_increment(c, &c->regs[VCPU_REGS_RSP], c->dst.bytes); |
8cdbd2c9 LV |
1090 | |
1091 | return 0; | |
1092 | } | |
1093 | ||
05f086f8 | 1094 | static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt) |
8cdbd2c9 | 1095 | { |
05f086f8 | 1096 | struct decode_cache *c = &ctxt->decode; |
8cdbd2c9 LV |
1097 | switch (c->modrm_reg) { |
1098 | case 0: /* rol */ | |
05f086f8 | 1099 | emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1100 | break; |
1101 | case 1: /* ror */ | |
05f086f8 | 1102 | emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1103 | break; |
1104 | case 2: /* rcl */ | |
05f086f8 | 1105 | emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1106 | break; |
1107 | case 3: /* rcr */ | |
05f086f8 | 1108 | emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1109 | break; |
1110 | case 4: /* sal/shl */ | |
1111 | case 6: /* sal/shl */ | |
05f086f8 | 1112 | emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1113 | break; |
1114 | case 5: /* shr */ | |
05f086f8 | 1115 | emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1116 | break; |
1117 | case 7: /* sar */ | |
05f086f8 | 1118 | emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1119 | break; |
1120 | } | |
1121 | } | |
1122 | ||
1123 | static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt, | |
05f086f8 | 1124 | struct x86_emulate_ops *ops) |
8cdbd2c9 LV |
1125 | { |
1126 | struct decode_cache *c = &ctxt->decode; | |
1127 | int rc = 0; | |
1128 | ||
1129 | switch (c->modrm_reg) { | |
1130 | case 0 ... 1: /* test */ | |
05f086f8 | 1131 | emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1132 | break; |
1133 | case 2: /* not */ | |
1134 | c->dst.val = ~c->dst.val; | |
1135 | break; | |
1136 | case 3: /* neg */ | |
05f086f8 | 1137 | emulate_1op("neg", c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1138 | break; |
1139 | default: | |
1140 | DPRINTF("Cannot emulate %02x\n", c->b); | |
1141 | rc = X86EMUL_UNHANDLEABLE; | |
1142 | break; | |
1143 | } | |
8cdbd2c9 LV |
1144 | return rc; |
1145 | } | |
1146 | ||
1147 | static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt, | |
a01af5ec | 1148 | struct x86_emulate_ops *ops) |
8cdbd2c9 LV |
1149 | { |
1150 | struct decode_cache *c = &ctxt->decode; | |
8cdbd2c9 LV |
1151 | |
1152 | switch (c->modrm_reg) { | |
1153 | case 0: /* inc */ | |
05f086f8 | 1154 | emulate_1op("inc", c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1155 | break; |
1156 | case 1: /* dec */ | |
05f086f8 | 1157 | emulate_1op("dec", c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1158 | break; |
1159 | case 4: /* jmp abs */ | |
fd60754e | 1160 | c->eip = c->src.val; |
8cdbd2c9 LV |
1161 | break; |
1162 | case 6: /* push */ | |
fd60754e | 1163 | emulate_push(ctxt); |
8cdbd2c9 | 1164 | break; |
8cdbd2c9 LV |
1165 | } |
1166 | return 0; | |
1167 | } | |
1168 | ||
1169 | static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt, | |
1170 | struct x86_emulate_ops *ops, | |
e8d8d7fe | 1171 | unsigned long memop) |
8cdbd2c9 LV |
1172 | { |
1173 | struct decode_cache *c = &ctxt->decode; | |
1174 | u64 old, new; | |
1175 | int rc; | |
1176 | ||
e8d8d7fe | 1177 | rc = ops->read_emulated(memop, &old, 8, ctxt->vcpu); |
8cdbd2c9 LV |
1178 | if (rc != 0) |
1179 | return rc; | |
1180 | ||
1181 | if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) || | |
1182 | ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) { | |
1183 | ||
1184 | c->regs[VCPU_REGS_RAX] = (u32) (old >> 0); | |
1185 | c->regs[VCPU_REGS_RDX] = (u32) (old >> 32); | |
05f086f8 | 1186 | ctxt->eflags &= ~EFLG_ZF; |
8cdbd2c9 LV |
1187 | |
1188 | } else { | |
1189 | new = ((u64)c->regs[VCPU_REGS_RCX] << 32) | | |
1190 | (u32) c->regs[VCPU_REGS_RBX]; | |
1191 | ||
e8d8d7fe | 1192 | rc = ops->cmpxchg_emulated(memop, &old, &new, 8, ctxt->vcpu); |
8cdbd2c9 LV |
1193 | if (rc != 0) |
1194 | return rc; | |
05f086f8 | 1195 | ctxt->eflags |= EFLG_ZF; |
8cdbd2c9 LV |
1196 | } |
1197 | return 0; | |
1198 | } | |
1199 | ||
1200 | static inline int writeback(struct x86_emulate_ctxt *ctxt, | |
1201 | struct x86_emulate_ops *ops) | |
1202 | { | |
1203 | int rc; | |
1204 | struct decode_cache *c = &ctxt->decode; | |
1205 | ||
1206 | switch (c->dst.type) { | |
1207 | case OP_REG: | |
1208 | /* The 4-byte case *is* correct: | |
1209 | * in 64-bit mode we zero-extend. | |
1210 | */ | |
1211 | switch (c->dst.bytes) { | |
1212 | case 1: | |
1213 | *(u8 *)c->dst.ptr = (u8)c->dst.val; | |
1214 | break; | |
1215 | case 2: | |
1216 | *(u16 *)c->dst.ptr = (u16)c->dst.val; | |
1217 | break; | |
1218 | case 4: | |
1219 | *c->dst.ptr = (u32)c->dst.val; | |
1220 | break; /* 64b: zero-ext */ | |
1221 | case 8: | |
1222 | *c->dst.ptr = c->dst.val; | |
1223 | break; | |
1224 | } | |
1225 | break; | |
1226 | case OP_MEM: | |
1227 | if (c->lock_prefix) | |
1228 | rc = ops->cmpxchg_emulated( | |
1229 | (unsigned long)c->dst.ptr, | |
1230 | &c->dst.orig_val, | |
1231 | &c->dst.val, | |
1232 | c->dst.bytes, | |
1233 | ctxt->vcpu); | |
1234 | else | |
1235 | rc = ops->write_emulated( | |
1236 | (unsigned long)c->dst.ptr, | |
1237 | &c->dst.val, | |
1238 | c->dst.bytes, | |
1239 | ctxt->vcpu); | |
1240 | if (rc != 0) | |
1241 | return rc; | |
a01af5ec LV |
1242 | break; |
1243 | case OP_NONE: | |
1244 | /* no writeback */ | |
1245 | break; | |
8cdbd2c9 LV |
1246 | default: |
1247 | break; | |
1248 | } | |
1249 | return 0; | |
1250 | } | |
1251 | ||
8b4caf66 | 1252 | int |
1be3aa47 | 1253 | x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops) |
8b4caf66 | 1254 | { |
e8d8d7fe | 1255 | unsigned long memop = 0; |
8b4caf66 | 1256 | u64 msr_data; |
3427318f | 1257 | unsigned long saved_eip = 0; |
8b4caf66 | 1258 | struct decode_cache *c = &ctxt->decode; |
1be3aa47 | 1259 | int rc = 0; |
8b4caf66 | 1260 | |
3427318f LV |
1261 | /* Shadow copy of register state. Committed on successful emulation. |
1262 | * NOTE: we can copy them from vcpu as x86_decode_insn() doesn't | |
1263 | * modify them. | |
1264 | */ | |
1265 | ||
ad312c7c | 1266 | memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs); |
3427318f LV |
1267 | saved_eip = c->eip; |
1268 | ||
c7e75a3d | 1269 | if (((c->d & ModRM) && (c->modrm_mod != 3)) || (c->d & MemAbs)) |
e8d8d7fe | 1270 | memop = c->modrm_ea; |
8b4caf66 | 1271 | |
b9fa9d6b AK |
1272 | if (c->rep_prefix && (c->d & String)) { |
1273 | /* All REP prefixes have the same first termination condition */ | |
1274 | if (c->regs[VCPU_REGS_RCX] == 0) { | |
ad312c7c | 1275 | ctxt->vcpu->arch.rip = c->eip; |
b9fa9d6b AK |
1276 | goto done; |
1277 | } | |
1278 | /* The second termination condition only applies for REPE | |
1279 | * and REPNE. Test if the repeat string operation prefix is | |
1280 | * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the | |
1281 | * corresponding termination condition according to: | |
1282 | * - if REPE/REPZ and ZF = 0 then done | |
1283 | * - if REPNE/REPNZ and ZF = 1 then done | |
1284 | */ | |
1285 | if ((c->b == 0xa6) || (c->b == 0xa7) || | |
1286 | (c->b == 0xae) || (c->b == 0xaf)) { | |
1287 | if ((c->rep_prefix == REPE_PREFIX) && | |
1288 | ((ctxt->eflags & EFLG_ZF) == 0)) { | |
ad312c7c | 1289 | ctxt->vcpu->arch.rip = c->eip; |
b9fa9d6b AK |
1290 | goto done; |
1291 | } | |
1292 | if ((c->rep_prefix == REPNE_PREFIX) && | |
1293 | ((ctxt->eflags & EFLG_ZF) == EFLG_ZF)) { | |
ad312c7c | 1294 | ctxt->vcpu->arch.rip = c->eip; |
b9fa9d6b AK |
1295 | goto done; |
1296 | } | |
1297 | } | |
1298 | c->regs[VCPU_REGS_RCX]--; | |
ad312c7c | 1299 | c->eip = ctxt->vcpu->arch.rip; |
b9fa9d6b AK |
1300 | } |
1301 | ||
8b4caf66 | 1302 | if (c->src.type == OP_MEM) { |
e8d8d7fe | 1303 | c->src.ptr = (unsigned long *)memop; |
8b4caf66 | 1304 | c->src.val = 0; |
d77c26fc MD |
1305 | rc = ops->read_emulated((unsigned long)c->src.ptr, |
1306 | &c->src.val, | |
1307 | c->src.bytes, | |
1308 | ctxt->vcpu); | |
1309 | if (rc != 0) | |
8b4caf66 LV |
1310 | goto done; |
1311 | c->src.orig_val = c->src.val; | |
1312 | } | |
1313 | ||
1314 | if ((c->d & DstMask) == ImplicitOps) | |
1315 | goto special_insn; | |
1316 | ||
1317 | ||
1318 | if (c->dst.type == OP_MEM) { | |
e8d8d7fe | 1319 | c->dst.ptr = (unsigned long *)memop; |
8b4caf66 LV |
1320 | c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; |
1321 | c->dst.val = 0; | |
e4e03ded LV |
1322 | if (c->d & BitOp) { |
1323 | unsigned long mask = ~(c->dst.bytes * 8 - 1); | |
df513e2c | 1324 | |
e4e03ded LV |
1325 | c->dst.ptr = (void *)c->dst.ptr + |
1326 | (c->src.val & mask) / 8; | |
038e51de | 1327 | } |
e4e03ded LV |
1328 | if (!(c->d & Mov) && |
1329 | /* optimisation - avoid slow emulated read */ | |
1330 | ((rc = ops->read_emulated((unsigned long)c->dst.ptr, | |
1331 | &c->dst.val, | |
1332 | c->dst.bytes, ctxt->vcpu)) != 0)) | |
038e51de | 1333 | goto done; |
038e51de | 1334 | } |
e4e03ded | 1335 | c->dst.orig_val = c->dst.val; |
038e51de | 1336 | |
018a98db AK |
1337 | special_insn: |
1338 | ||
e4e03ded | 1339 | if (c->twobyte) |
6aa8b732 AK |
1340 | goto twobyte_insn; |
1341 | ||
e4e03ded | 1342 | switch (c->b) { |
6aa8b732 AK |
1343 | case 0x00 ... 0x05: |
1344 | add: /* add */ | |
05f086f8 | 1345 | emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
1346 | break; |
1347 | case 0x08 ... 0x0d: | |
1348 | or: /* or */ | |
05f086f8 | 1349 | emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
1350 | break; |
1351 | case 0x10 ... 0x15: | |
1352 | adc: /* adc */ | |
05f086f8 | 1353 | emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
1354 | break; |
1355 | case 0x18 ... 0x1d: | |
1356 | sbb: /* sbb */ | |
05f086f8 | 1357 | emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 1358 | break; |
19eb938e | 1359 | case 0x20 ... 0x23: |
6aa8b732 | 1360 | and: /* and */ |
05f086f8 | 1361 | emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 1362 | break; |
19eb938e | 1363 | case 0x24: /* and al imm8 */ |
e4e03ded LV |
1364 | c->dst.type = OP_REG; |
1365 | c->dst.ptr = &c->regs[VCPU_REGS_RAX]; | |
1366 | c->dst.val = *(u8 *)c->dst.ptr; | |
1367 | c->dst.bytes = 1; | |
1368 | c->dst.orig_val = c->dst.val; | |
19eb938e NK |
1369 | goto and; |
1370 | case 0x25: /* and ax imm16, or eax imm32 */ | |
e4e03ded LV |
1371 | c->dst.type = OP_REG; |
1372 | c->dst.bytes = c->op_bytes; | |
1373 | c->dst.ptr = &c->regs[VCPU_REGS_RAX]; | |
1374 | if (c->op_bytes == 2) | |
1375 | c->dst.val = *(u16 *)c->dst.ptr; | |
19eb938e | 1376 | else |
e4e03ded LV |
1377 | c->dst.val = *(u32 *)c->dst.ptr; |
1378 | c->dst.orig_val = c->dst.val; | |
19eb938e | 1379 | goto and; |
6aa8b732 AK |
1380 | case 0x28 ... 0x2d: |
1381 | sub: /* sub */ | |
05f086f8 | 1382 | emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
1383 | break; |
1384 | case 0x30 ... 0x35: | |
1385 | xor: /* xor */ | |
05f086f8 | 1386 | emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
1387 | break; |
1388 | case 0x38 ... 0x3d: | |
1389 | cmp: /* cmp */ | |
05f086f8 | 1390 | emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 1391 | break; |
33615aa9 AK |
1392 | case 0x40 ... 0x47: /* inc r16/r32 */ |
1393 | emulate_1op("inc", c->dst, ctxt->eflags); | |
1394 | break; | |
1395 | case 0x48 ... 0x4f: /* dec r16/r32 */ | |
1396 | emulate_1op("dec", c->dst, ctxt->eflags); | |
1397 | break; | |
1398 | case 0x50 ... 0x57: /* push reg */ | |
1399 | c->dst.type = OP_MEM; | |
1400 | c->dst.bytes = c->op_bytes; | |
1401 | c->dst.val = c->src.val; | |
7a957275 | 1402 | register_address_increment(c, &c->regs[VCPU_REGS_RSP], |
33615aa9 AK |
1403 | -c->op_bytes); |
1404 | c->dst.ptr = (void *) register_address( | |
e4706772 | 1405 | c, ctxt->ss_base, c->regs[VCPU_REGS_RSP]); |
33615aa9 AK |
1406 | break; |
1407 | case 0x58 ... 0x5f: /* pop reg */ | |
1408 | pop_instruction: | |
e4706772 | 1409 | if ((rc = ops->read_std(register_address(c, ctxt->ss_base, |
33615aa9 AK |
1410 | c->regs[VCPU_REGS_RSP]), c->dst.ptr, |
1411 | c->op_bytes, ctxt->vcpu)) != 0) | |
1412 | goto done; | |
1413 | ||
7a957275 | 1414 | register_address_increment(c, &c->regs[VCPU_REGS_RSP], |
33615aa9 AK |
1415 | c->op_bytes); |
1416 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
1417 | break; | |
6aa8b732 | 1418 | case 0x63: /* movsxd */ |
8b4caf66 | 1419 | if (ctxt->mode != X86EMUL_MODE_PROT64) |
6aa8b732 | 1420 | goto cannot_emulate; |
e4e03ded | 1421 | c->dst.val = (s32) c->src.val; |
6aa8b732 | 1422 | break; |
018a98db AK |
1423 | case 0x6a: /* push imm8 */ |
1424 | c->src.val = 0L; | |
1425 | c->src.val = insn_fetch(s8, 1, c->eip); | |
1426 | emulate_push(ctxt); | |
1427 | break; | |
1428 | case 0x6c: /* insb */ | |
1429 | case 0x6d: /* insw/insd */ | |
1430 | if (kvm_emulate_pio_string(ctxt->vcpu, NULL, | |
1431 | 1, | |
1432 | (c->d & ByteOp) ? 1 : c->op_bytes, | |
1433 | c->rep_prefix ? | |
e4706772 | 1434 | address_mask(c, c->regs[VCPU_REGS_RCX]) : 1, |
018a98db | 1435 | (ctxt->eflags & EFLG_DF), |
e4706772 | 1436 | register_address(c, ctxt->es_base, |
018a98db AK |
1437 | c->regs[VCPU_REGS_RDI]), |
1438 | c->rep_prefix, | |
1439 | c->regs[VCPU_REGS_RDX]) == 0) { | |
1440 | c->eip = saved_eip; | |
1441 | return -1; | |
1442 | } | |
1443 | return 0; | |
1444 | case 0x6e: /* outsb */ | |
1445 | case 0x6f: /* outsw/outsd */ | |
1446 | if (kvm_emulate_pio_string(ctxt->vcpu, NULL, | |
1447 | 0, | |
1448 | (c->d & ByteOp) ? 1 : c->op_bytes, | |
1449 | c->rep_prefix ? | |
e4706772 | 1450 | address_mask(c, c->regs[VCPU_REGS_RCX]) : 1, |
018a98db | 1451 | (ctxt->eflags & EFLG_DF), |
e4706772 | 1452 | register_address(c, c->override_base ? |
018a98db AK |
1453 | *c->override_base : |
1454 | ctxt->ds_base, | |
1455 | c->regs[VCPU_REGS_RSI]), | |
1456 | c->rep_prefix, | |
1457 | c->regs[VCPU_REGS_RDX]) == 0) { | |
1458 | c->eip = saved_eip; | |
1459 | return -1; | |
1460 | } | |
1461 | return 0; | |
1462 | case 0x70 ... 0x7f: /* jcc (short) */ { | |
1463 | int rel = insn_fetch(s8, 1, c->eip); | |
1464 | ||
1465 | if (test_cc(c->b, ctxt->eflags)) | |
7a957275 | 1466 | jmp_rel(c, rel); |
018a98db AK |
1467 | break; |
1468 | } | |
6aa8b732 | 1469 | case 0x80 ... 0x83: /* Grp1 */ |
e4e03ded | 1470 | switch (c->modrm_reg) { |
6aa8b732 AK |
1471 | case 0: |
1472 | goto add; | |
1473 | case 1: | |
1474 | goto or; | |
1475 | case 2: | |
1476 | goto adc; | |
1477 | case 3: | |
1478 | goto sbb; | |
1479 | case 4: | |
1480 | goto and; | |
1481 | case 5: | |
1482 | goto sub; | |
1483 | case 6: | |
1484 | goto xor; | |
1485 | case 7: | |
1486 | goto cmp; | |
1487 | } | |
1488 | break; | |
1489 | case 0x84 ... 0x85: | |
05f086f8 | 1490 | emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
1491 | break; |
1492 | case 0x86 ... 0x87: /* xchg */ | |
1493 | /* Write back the register source. */ | |
e4e03ded | 1494 | switch (c->dst.bytes) { |
6aa8b732 | 1495 | case 1: |
e4e03ded | 1496 | *(u8 *) c->src.ptr = (u8) c->dst.val; |
6aa8b732 AK |
1497 | break; |
1498 | case 2: | |
e4e03ded | 1499 | *(u16 *) c->src.ptr = (u16) c->dst.val; |
6aa8b732 AK |
1500 | break; |
1501 | case 4: | |
e4e03ded | 1502 | *c->src.ptr = (u32) c->dst.val; |
6aa8b732 AK |
1503 | break; /* 64b reg: zero-extend */ |
1504 | case 8: | |
e4e03ded | 1505 | *c->src.ptr = c->dst.val; |
6aa8b732 AK |
1506 | break; |
1507 | } | |
1508 | /* | |
1509 | * Write back the memory destination with implicit LOCK | |
1510 | * prefix. | |
1511 | */ | |
e4e03ded LV |
1512 | c->dst.val = c->src.val; |
1513 | c->lock_prefix = 1; | |
6aa8b732 | 1514 | break; |
6aa8b732 | 1515 | case 0x88 ... 0x8b: /* mov */ |
7de75248 | 1516 | goto mov; |
7e0b54b1 | 1517 | case 0x8d: /* lea r16/r32, m */ |
f9b7aab3 | 1518 | c->dst.val = c->modrm_ea; |
7e0b54b1 | 1519 | break; |
6aa8b732 | 1520 | case 0x8f: /* pop (sole member of Grp1a) */ |
8cdbd2c9 LV |
1521 | rc = emulate_grp1a(ctxt, ops); |
1522 | if (rc != 0) | |
6aa8b732 | 1523 | goto done; |
6aa8b732 | 1524 | break; |
fd2a7608 | 1525 | case 0x9c: /* pushf */ |
05f086f8 | 1526 | c->src.val = (unsigned long) ctxt->eflags; |
8cdbd2c9 LV |
1527 | emulate_push(ctxt); |
1528 | break; | |
535eabcf | 1529 | case 0x9d: /* popf */ |
05f086f8 | 1530 | c->dst.ptr = (unsigned long *) &ctxt->eflags; |
535eabcf | 1531 | goto pop_instruction; |
018a98db AK |
1532 | case 0xa0 ... 0xa1: /* mov */ |
1533 | c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX]; | |
1534 | c->dst.val = c->src.val; | |
1535 | break; | |
1536 | case 0xa2 ... 0xa3: /* mov */ | |
1537 | c->dst.val = (unsigned long)c->regs[VCPU_REGS_RAX]; | |
1538 | break; | |
6aa8b732 | 1539 | case 0xa4 ... 0xa5: /* movs */ |
e4e03ded LV |
1540 | c->dst.type = OP_MEM; |
1541 | c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
e4706772 | 1542 | c->dst.ptr = (unsigned long *)register_address(c, |
e4e03ded LV |
1543 | ctxt->es_base, |
1544 | c->regs[VCPU_REGS_RDI]); | |
e4706772 | 1545 | if ((rc = ops->read_emulated(register_address(c, |
e4e03ded LV |
1546 | c->override_base ? *c->override_base : |
1547 | ctxt->ds_base, | |
1548 | c->regs[VCPU_REGS_RSI]), | |
1549 | &c->dst.val, | |
1550 | c->dst.bytes, ctxt->vcpu)) != 0) | |
6aa8b732 | 1551 | goto done; |
7a957275 | 1552 | register_address_increment(c, &c->regs[VCPU_REGS_RSI], |
05f086f8 | 1553 | (ctxt->eflags & EFLG_DF) ? -c->dst.bytes |
e4e03ded | 1554 | : c->dst.bytes); |
7a957275 | 1555 | register_address_increment(c, &c->regs[VCPU_REGS_RDI], |
05f086f8 | 1556 | (ctxt->eflags & EFLG_DF) ? -c->dst.bytes |
e4e03ded | 1557 | : c->dst.bytes); |
6aa8b732 AK |
1558 | break; |
1559 | case 0xa6 ... 0xa7: /* cmps */ | |
d7e5117a GT |
1560 | c->src.type = OP_NONE; /* Disable writeback. */ |
1561 | c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
e4706772 | 1562 | c->src.ptr = (unsigned long *)register_address(c, |
d7e5117a GT |
1563 | c->override_base ? *c->override_base : |
1564 | ctxt->ds_base, | |
1565 | c->regs[VCPU_REGS_RSI]); | |
1566 | if ((rc = ops->read_emulated((unsigned long)c->src.ptr, | |
1567 | &c->src.val, | |
1568 | c->src.bytes, | |
1569 | ctxt->vcpu)) != 0) | |
1570 | goto done; | |
1571 | ||
1572 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
1573 | c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
e4706772 | 1574 | c->dst.ptr = (unsigned long *)register_address(c, |
d7e5117a GT |
1575 | ctxt->es_base, |
1576 | c->regs[VCPU_REGS_RDI]); | |
1577 | if ((rc = ops->read_emulated((unsigned long)c->dst.ptr, | |
1578 | &c->dst.val, | |
1579 | c->dst.bytes, | |
1580 | ctxt->vcpu)) != 0) | |
1581 | goto done; | |
1582 | ||
1583 | DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.ptr, c->dst.ptr); | |
1584 | ||
1585 | emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags); | |
1586 | ||
7a957275 | 1587 | register_address_increment(c, &c->regs[VCPU_REGS_RSI], |
d7e5117a GT |
1588 | (ctxt->eflags & EFLG_DF) ? -c->src.bytes |
1589 | : c->src.bytes); | |
7a957275 | 1590 | register_address_increment(c, &c->regs[VCPU_REGS_RDI], |
d7e5117a GT |
1591 | (ctxt->eflags & EFLG_DF) ? -c->dst.bytes |
1592 | : c->dst.bytes); | |
1593 | ||
1594 | break; | |
6aa8b732 | 1595 | case 0xaa ... 0xab: /* stos */ |
e4e03ded LV |
1596 | c->dst.type = OP_MEM; |
1597 | c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
e4706772 | 1598 | c->dst.ptr = (unsigned long *)register_address(c, |
a7e6c88a SY |
1599 | ctxt->es_base, |
1600 | c->regs[VCPU_REGS_RDI]); | |
e4e03ded | 1601 | c->dst.val = c->regs[VCPU_REGS_RAX]; |
7a957275 | 1602 | register_address_increment(c, &c->regs[VCPU_REGS_RDI], |
05f086f8 | 1603 | (ctxt->eflags & EFLG_DF) ? -c->dst.bytes |
e4e03ded | 1604 | : c->dst.bytes); |
6aa8b732 AK |
1605 | break; |
1606 | case 0xac ... 0xad: /* lods */ | |
e4e03ded LV |
1607 | c->dst.type = OP_REG; |
1608 | c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
1609 | c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX]; | |
e4706772 | 1610 | if ((rc = ops->read_emulated(register_address(c, |
a7e6c88a SY |
1611 | c->override_base ? *c->override_base : |
1612 | ctxt->ds_base, | |
1613 | c->regs[VCPU_REGS_RSI]), | |
1614 | &c->dst.val, | |
1615 | c->dst.bytes, | |
1616 | ctxt->vcpu)) != 0) | |
6aa8b732 | 1617 | goto done; |
7a957275 | 1618 | register_address_increment(c, &c->regs[VCPU_REGS_RSI], |
05f086f8 | 1619 | (ctxt->eflags & EFLG_DF) ? -c->dst.bytes |
e4e03ded | 1620 | : c->dst.bytes); |
6aa8b732 AK |
1621 | break; |
1622 | case 0xae ... 0xaf: /* scas */ | |
1623 | DPRINTF("Urk! I don't handle SCAS.\n"); | |
1624 | goto cannot_emulate; | |
018a98db AK |
1625 | case 0xc0 ... 0xc1: |
1626 | emulate_grp2(ctxt); | |
1627 | break; | |
111de5d6 AK |
1628 | case 0xc3: /* ret */ |
1629 | c->dst.ptr = &c->eip; | |
1630 | goto pop_instruction; | |
018a98db AK |
1631 | case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */ |
1632 | mov: | |
1633 | c->dst.val = c->src.val; | |
1634 | break; | |
1635 | case 0xd0 ... 0xd1: /* Grp2 */ | |
1636 | c->src.val = 1; | |
1637 | emulate_grp2(ctxt); | |
1638 | break; | |
1639 | case 0xd2 ... 0xd3: /* Grp2 */ | |
1640 | c->src.val = c->regs[VCPU_REGS_RCX]; | |
1641 | emulate_grp2(ctxt); | |
1642 | break; | |
1a52e051 NK |
1643 | case 0xe8: /* call (near) */ { |
1644 | long int rel; | |
e4e03ded | 1645 | switch (c->op_bytes) { |
1a52e051 | 1646 | case 2: |
e4e03ded | 1647 | rel = insn_fetch(s16, 2, c->eip); |
1a52e051 NK |
1648 | break; |
1649 | case 4: | |
e4e03ded | 1650 | rel = insn_fetch(s32, 4, c->eip); |
1a52e051 | 1651 | break; |
1a52e051 NK |
1652 | default: |
1653 | DPRINTF("Call: Invalid op_bytes\n"); | |
1654 | goto cannot_emulate; | |
1655 | } | |
e4e03ded | 1656 | c->src.val = (unsigned long) c->eip; |
7a957275 | 1657 | jmp_rel(c, rel); |
e4e03ded | 1658 | c->op_bytes = c->ad_bytes; |
8cdbd2c9 LV |
1659 | emulate_push(ctxt); |
1660 | break; | |
1a52e051 NK |
1661 | } |
1662 | case 0xe9: /* jmp rel */ | |
1663 | case 0xeb: /* jmp rel short */ | |
7a957275 | 1664 | jmp_rel(c, c->src.val); |
a01af5ec | 1665 | c->dst.type = OP_NONE; /* Disable writeback. */ |
1a52e051 | 1666 | break; |
111de5d6 | 1667 | case 0xf4: /* hlt */ |
ad312c7c | 1668 | ctxt->vcpu->arch.halt_request = 1; |
111de5d6 AK |
1669 | goto done; |
1670 | case 0xf5: /* cmc */ | |
1671 | /* complement carry flag from eflags reg */ | |
1672 | ctxt->eflags ^= EFLG_CF; | |
1673 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
1674 | break; | |
018a98db AK |
1675 | case 0xf6 ... 0xf7: /* Grp3 */ |
1676 | rc = emulate_grp3(ctxt, ops); | |
1677 | if (rc != 0) | |
1678 | goto done; | |
1679 | break; | |
111de5d6 AK |
1680 | case 0xf8: /* clc */ |
1681 | ctxt->eflags &= ~EFLG_CF; | |
1682 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
1683 | break; | |
1684 | case 0xfa: /* cli */ | |
1685 | ctxt->eflags &= ~X86_EFLAGS_IF; | |
1686 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
1687 | break; | |
1688 | case 0xfb: /* sti */ | |
1689 | ctxt->eflags |= X86_EFLAGS_IF; | |
1690 | c->dst.type = OP_NONE; /* Disable writeback. */ | |
1691 | break; | |
018a98db AK |
1692 | case 0xfe ... 0xff: /* Grp4/Grp5 */ |
1693 | rc = emulate_grp45(ctxt, ops); | |
1694 | if (rc != 0) | |
1695 | goto done; | |
1696 | break; | |
6aa8b732 | 1697 | } |
018a98db AK |
1698 | |
1699 | writeback: | |
1700 | rc = writeback(ctxt, ops); | |
1701 | if (rc != 0) | |
1702 | goto done; | |
1703 | ||
1704 | /* Commit shadow register state. */ | |
ad312c7c ZX |
1705 | memcpy(ctxt->vcpu->arch.regs, c->regs, sizeof c->regs); |
1706 | ctxt->vcpu->arch.rip = c->eip; | |
018a98db AK |
1707 | |
1708 | done: | |
1709 | if (rc == X86EMUL_UNHANDLEABLE) { | |
1710 | c->eip = saved_eip; | |
1711 | return -1; | |
1712 | } | |
1713 | return 0; | |
6aa8b732 AK |
1714 | |
1715 | twobyte_insn: | |
e4e03ded | 1716 | switch (c->b) { |
6aa8b732 | 1717 | case 0x01: /* lgdt, lidt, lmsw */ |
e4e03ded | 1718 | switch (c->modrm_reg) { |
6aa8b732 AK |
1719 | u16 size; |
1720 | unsigned long address; | |
1721 | ||
aca7f966 | 1722 | case 0: /* vmcall */ |
e4e03ded | 1723 | if (c->modrm_mod != 3 || c->modrm_rm != 1) |
aca7f966 AL |
1724 | goto cannot_emulate; |
1725 | ||
7aa81cc0 AL |
1726 | rc = kvm_fix_hypercall(ctxt->vcpu); |
1727 | if (rc) | |
1728 | goto done; | |
1729 | ||
33e3885d AK |
1730 | /* Let the processor re-execute the fixed hypercall */ |
1731 | c->eip = ctxt->vcpu->arch.rip; | |
16286d08 AK |
1732 | /* Disable writeback. */ |
1733 | c->dst.type = OP_NONE; | |
aca7f966 | 1734 | break; |
6aa8b732 | 1735 | case 2: /* lgdt */ |
e4e03ded LV |
1736 | rc = read_descriptor(ctxt, ops, c->src.ptr, |
1737 | &size, &address, c->op_bytes); | |
6aa8b732 AK |
1738 | if (rc) |
1739 | goto done; | |
1740 | realmode_lgdt(ctxt->vcpu, size, address); | |
16286d08 AK |
1741 | /* Disable writeback. */ |
1742 | c->dst.type = OP_NONE; | |
6aa8b732 | 1743 | break; |
aca7f966 | 1744 | case 3: /* lidt/vmmcall */ |
e4e03ded | 1745 | if (c->modrm_mod == 3 && c->modrm_rm == 1) { |
7aa81cc0 AL |
1746 | rc = kvm_fix_hypercall(ctxt->vcpu); |
1747 | if (rc) | |
1748 | goto done; | |
1749 | kvm_emulate_hypercall(ctxt->vcpu); | |
aca7f966 | 1750 | } else { |
e4e03ded | 1751 | rc = read_descriptor(ctxt, ops, c->src.ptr, |
aca7f966 | 1752 | &size, &address, |
e4e03ded | 1753 | c->op_bytes); |
aca7f966 AL |
1754 | if (rc) |
1755 | goto done; | |
1756 | realmode_lidt(ctxt->vcpu, size, address); | |
1757 | } | |
16286d08 AK |
1758 | /* Disable writeback. */ |
1759 | c->dst.type = OP_NONE; | |
6aa8b732 AK |
1760 | break; |
1761 | case 4: /* smsw */ | |
16286d08 AK |
1762 | c->dst.bytes = 2; |
1763 | c->dst.val = realmode_get_cr(ctxt->vcpu, 0); | |
6aa8b732 AK |
1764 | break; |
1765 | case 6: /* lmsw */ | |
16286d08 AK |
1766 | realmode_lmsw(ctxt->vcpu, (u16)c->src.val, |
1767 | &ctxt->eflags); | |
dc7457ea | 1768 | c->dst.type = OP_NONE; |
6aa8b732 AK |
1769 | break; |
1770 | case 7: /* invlpg*/ | |
e8d8d7fe | 1771 | emulate_invlpg(ctxt->vcpu, memop); |
16286d08 AK |
1772 | /* Disable writeback. */ |
1773 | c->dst.type = OP_NONE; | |
6aa8b732 AK |
1774 | break; |
1775 | default: | |
1776 | goto cannot_emulate; | |
1777 | } | |
1778 | break; | |
018a98db AK |
1779 | case 0x06: |
1780 | emulate_clts(ctxt->vcpu); | |
1781 | c->dst.type = OP_NONE; | |
1782 | break; | |
1783 | case 0x08: /* invd */ | |
1784 | case 0x09: /* wbinvd */ | |
1785 | case 0x0d: /* GrpP (prefetch) */ | |
1786 | case 0x18: /* Grp16 (prefetch/nop) */ | |
1787 | c->dst.type = OP_NONE; | |
1788 | break; | |
1789 | case 0x20: /* mov cr, reg */ | |
1790 | if (c->modrm_mod != 3) | |
1791 | goto cannot_emulate; | |
1792 | c->regs[c->modrm_rm] = | |
1793 | realmode_get_cr(ctxt->vcpu, c->modrm_reg); | |
1794 | c->dst.type = OP_NONE; /* no writeback */ | |
1795 | break; | |
6aa8b732 | 1796 | case 0x21: /* mov from dr to reg */ |
e4e03ded | 1797 | if (c->modrm_mod != 3) |
6aa8b732 | 1798 | goto cannot_emulate; |
8cdbd2c9 | 1799 | rc = emulator_get_dr(ctxt, c->modrm_reg, &c->regs[c->modrm_rm]); |
a01af5ec LV |
1800 | if (rc) |
1801 | goto cannot_emulate; | |
1802 | c->dst.type = OP_NONE; /* no writeback */ | |
6aa8b732 | 1803 | break; |
018a98db AK |
1804 | case 0x22: /* mov reg, cr */ |
1805 | if (c->modrm_mod != 3) | |
1806 | goto cannot_emulate; | |
1807 | realmode_set_cr(ctxt->vcpu, | |
1808 | c->modrm_reg, c->modrm_val, &ctxt->eflags); | |
1809 | c->dst.type = OP_NONE; | |
1810 | break; | |
6aa8b732 | 1811 | case 0x23: /* mov from reg to dr */ |
e4e03ded | 1812 | if (c->modrm_mod != 3) |
6aa8b732 | 1813 | goto cannot_emulate; |
e4e03ded LV |
1814 | rc = emulator_set_dr(ctxt, c->modrm_reg, |
1815 | c->regs[c->modrm_rm]); | |
a01af5ec LV |
1816 | if (rc) |
1817 | goto cannot_emulate; | |
1818 | c->dst.type = OP_NONE; /* no writeback */ | |
6aa8b732 | 1819 | break; |
018a98db AK |
1820 | case 0x30: |
1821 | /* wrmsr */ | |
1822 | msr_data = (u32)c->regs[VCPU_REGS_RAX] | |
1823 | | ((u64)c->regs[VCPU_REGS_RDX] << 32); | |
1824 | rc = kvm_set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data); | |
1825 | if (rc) { | |
c1a5d4f9 | 1826 | kvm_inject_gp(ctxt->vcpu, 0); |
ad312c7c | 1827 | c->eip = ctxt->vcpu->arch.rip; |
018a98db AK |
1828 | } |
1829 | rc = X86EMUL_CONTINUE; | |
1830 | c->dst.type = OP_NONE; | |
1831 | break; | |
1832 | case 0x32: | |
1833 | /* rdmsr */ | |
1834 | rc = kvm_get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data); | |
1835 | if (rc) { | |
c1a5d4f9 | 1836 | kvm_inject_gp(ctxt->vcpu, 0); |
ad312c7c | 1837 | c->eip = ctxt->vcpu->arch.rip; |
018a98db AK |
1838 | } else { |
1839 | c->regs[VCPU_REGS_RAX] = (u32)msr_data; | |
1840 | c->regs[VCPU_REGS_RDX] = msr_data >> 32; | |
1841 | } | |
1842 | rc = X86EMUL_CONTINUE; | |
1843 | c->dst.type = OP_NONE; | |
1844 | break; | |
6aa8b732 | 1845 | case 0x40 ... 0x4f: /* cmov */ |
e4e03ded | 1846 | c->dst.val = c->dst.orig_val = c->src.val; |
a01af5ec LV |
1847 | if (!test_cc(c->b, ctxt->eflags)) |
1848 | c->dst.type = OP_NONE; /* no writeback */ | |
6aa8b732 | 1849 | break; |
018a98db AK |
1850 | case 0x80 ... 0x8f: /* jnz rel, etc*/ { |
1851 | long int rel; | |
1852 | ||
1853 | switch (c->op_bytes) { | |
1854 | case 2: | |
1855 | rel = insn_fetch(s16, 2, c->eip); | |
1856 | break; | |
1857 | case 4: | |
1858 | rel = insn_fetch(s32, 4, c->eip); | |
1859 | break; | |
1860 | case 8: | |
1861 | rel = insn_fetch(s64, 8, c->eip); | |
1862 | break; | |
1863 | default: | |
1864 | DPRINTF("jnz: Invalid op_bytes\n"); | |
1865 | goto cannot_emulate; | |
1866 | } | |
1867 | if (test_cc(c->b, ctxt->eflags)) | |
7a957275 | 1868 | jmp_rel(c, rel); |
018a98db AK |
1869 | c->dst.type = OP_NONE; |
1870 | break; | |
1871 | } | |
7de75248 NK |
1872 | case 0xa3: |
1873 | bt: /* bt */ | |
e4f8e039 | 1874 | c->dst.type = OP_NONE; |
e4e03ded LV |
1875 | /* only subword offset */ |
1876 | c->src.val &= (c->dst.bytes << 3) - 1; | |
05f086f8 | 1877 | emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags); |
7de75248 NK |
1878 | break; |
1879 | case 0xab: | |
1880 | bts: /* bts */ | |
e4e03ded LV |
1881 | /* only subword offset */ |
1882 | c->src.val &= (c->dst.bytes << 3) - 1; | |
05f086f8 | 1883 | emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags); |
7de75248 | 1884 | break; |
6aa8b732 AK |
1885 | case 0xb0 ... 0xb1: /* cmpxchg */ |
1886 | /* | |
1887 | * Save real source value, then compare EAX against | |
1888 | * destination. | |
1889 | */ | |
e4e03ded LV |
1890 | c->src.orig_val = c->src.val; |
1891 | c->src.val = c->regs[VCPU_REGS_RAX]; | |
05f086f8 LV |
1892 | emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags); |
1893 | if (ctxt->eflags & EFLG_ZF) { | |
6aa8b732 | 1894 | /* Success: write back to memory. */ |
e4e03ded | 1895 | c->dst.val = c->src.orig_val; |
6aa8b732 AK |
1896 | } else { |
1897 | /* Failure: write the value we saw to EAX. */ | |
e4e03ded LV |
1898 | c->dst.type = OP_REG; |
1899 | c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX]; | |
6aa8b732 AK |
1900 | } |
1901 | break; | |
6aa8b732 AK |
1902 | case 0xb3: |
1903 | btr: /* btr */ | |
e4e03ded LV |
1904 | /* only subword offset */ |
1905 | c->src.val &= (c->dst.bytes << 3) - 1; | |
05f086f8 | 1906 | emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 1907 | break; |
6aa8b732 | 1908 | case 0xb6 ... 0xb7: /* movzx */ |
e4e03ded LV |
1909 | c->dst.bytes = c->op_bytes; |
1910 | c->dst.val = (c->d & ByteOp) ? (u8) c->src.val | |
1911 | : (u16) c->src.val; | |
6aa8b732 | 1912 | break; |
6aa8b732 | 1913 | case 0xba: /* Grp8 */ |
e4e03ded | 1914 | switch (c->modrm_reg & 3) { |
6aa8b732 AK |
1915 | case 0: |
1916 | goto bt; | |
1917 | case 1: | |
1918 | goto bts; | |
1919 | case 2: | |
1920 | goto btr; | |
1921 | case 3: | |
1922 | goto btc; | |
1923 | } | |
1924 | break; | |
7de75248 NK |
1925 | case 0xbb: |
1926 | btc: /* btc */ | |
e4e03ded LV |
1927 | /* only subword offset */ |
1928 | c->src.val &= (c->dst.bytes << 3) - 1; | |
05f086f8 | 1929 | emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags); |
7de75248 | 1930 | break; |
6aa8b732 | 1931 | case 0xbe ... 0xbf: /* movsx */ |
e4e03ded LV |
1932 | c->dst.bytes = c->op_bytes; |
1933 | c->dst.val = (c->d & ByteOp) ? (s8) c->src.val : | |
1934 | (s16) c->src.val; | |
6aa8b732 | 1935 | break; |
a012e65a | 1936 | case 0xc3: /* movnti */ |
e4e03ded LV |
1937 | c->dst.bytes = c->op_bytes; |
1938 | c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val : | |
1939 | (u64) c->src.val; | |
a012e65a | 1940 | break; |
6aa8b732 | 1941 | case 0xc7: /* Grp9 (cmpxchg8b) */ |
e8d8d7fe | 1942 | rc = emulate_grp9(ctxt, ops, memop); |
8cdbd2c9 LV |
1943 | if (rc != 0) |
1944 | goto done; | |
018a98db | 1945 | c->dst.type = OP_NONE; |
8cdbd2c9 | 1946 | break; |
6aa8b732 AK |
1947 | } |
1948 | goto writeback; | |
1949 | ||
1950 | cannot_emulate: | |
e4e03ded | 1951 | DPRINTF("Cannot emulate %02x\n", c->b); |
3427318f | 1952 | c->eip = saved_eip; |
6aa8b732 AK |
1953 | return -1; |
1954 | } |