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KVM: x86: do not execute halted vcpus
[deliverable/linux.git] / arch / x86 / kvm / x86_emulate.c
CommitLineData
6aa8b732
AK		 1/******************************************************************************
2 * x86_emulate.c
3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
12 *
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
20 */
21
22#ifndef __KERNEL__
23#include <stdio.h>
24#include <stdint.h>
25#include <public/xen.h>
d77c26fc 26#define DPRINTF(_f, _a ...) printf(_f , ## _a)
6aa8b732 27#else
edf88417 28#include <linux/kvm_host.h>
5fdbf976 29#include "kvm_cache_regs.h"
6aa8b732
AK		 30#define DPRINTF(x...) do {} while (0)
31#endif
6aa8b732 32#include <linux/module.h>
edf88417 33#include <asm/kvm_x86_emulate.h>
6aa8b732
AK		 34
35/*
36 * Opcode effective-address decode tables.
37 * Note that we only emulate instructions that have at least one memory
38 * operand (excluding implicit stack references). We assume that stack
39 * references and instruction fetches will never occur in special memory
40 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
41 * not be handled.
42 */
43
44/* Operand sizes: 8-bit operands or specified/overridden size. */
45#define ByteOp (1<<0) /* 8-bit operands. */
46/* Destination operand type. */
47#define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
48#define DstReg (2<<1) /* Register operand. */
49#define DstMem (3<<1) /* Memory operand. */
50#define DstMask (3<<1)
51/* Source operand type. */
52#define SrcNone (0<<3) /* No source operand. */
53#define SrcImplicit (0<<3) /* Source operand is implicit in the opcode. */
54#define SrcReg (1<<3) /* Register operand. */
55#define SrcMem (2<<3) /* Memory operand. */
56#define SrcMem16 (3<<3) /* Memory operand (16-bit). */
57#define SrcMem32 (4<<3) /* Memory operand (32-bit). */
58#define SrcImm (5<<3) /* Immediate operand. */
59#define SrcImmByte (6<<3) /* 8-bit sign-extended immediate operand. */
60#define SrcMask (7<<3)
61/* Generic ModRM decode. */
62#define ModRM (1<<6)
63/* Destination is only written; never read. */
64#define Mov (1<<7)
038e51de 65#define BitOp (1<<8)
c7e75a3d 66#define MemAbs (1<<9) /* Memory operand is absolute displacement */
b9fa9d6b 67#define String (1<<10) /* String instruction (rep capable) */
6e3d5dfb 68#define Stack (1<<11) /* Stack instruction (push/pop) */
e09d082c
AK		 69#define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
70#define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
71#define GroupMask 0xff /* Group number stored in bits 0:7 */
6aa8b732 72
43bb19cd 73enum {
1d6ad207 74 Group1_80, Group1_81, Group1_82, Group1_83,
d95058a1 75 Group1A, Group3_Byte, Group3, Group4, Group5, Group7,
43bb19cd
AK		 76};
77
c7e75a3d 78static u16 opcode_table[256] = {
6aa8b732
AK		 79 /* 0x00 - 0x07 */
80 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
81 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
82 0, 0, 0, 0,
83 /* 0x08 - 0x0F */
84 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
85 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
86 0, 0, 0, 0,
87 /* 0x10 - 0x17 */
88 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
89 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
90 0, 0, 0, 0,
91 /* 0x18 - 0x1F */
92 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
93 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
94 0, 0, 0, 0,
95 /* 0x20 - 0x27 */
96 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
97 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
19eb938e 98 SrcImmByte, SrcImm, 0, 0,
6aa8b732
AK		 99 /* 0x28 - 0x2F */
100 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
101 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
102 0, 0, 0, 0,
103 /* 0x30 - 0x37 */
104 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
105 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
106 0, 0, 0, 0,
107 /* 0x38 - 0x3F */
108 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
109 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
110 0, 0, 0, 0,
d77a2507 111 /* 0x40 - 0x47 */
33615aa9 112 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
d77a2507 113 /* 0x48 - 0x4F */
33615aa9 114 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
7f0aaee0 115 /* 0x50 - 0x57 */
6e3d5dfb
AK		 116 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
117 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
7f0aaee0 118 /* 0x58 - 0x5F */
6e3d5dfb
AK		 119 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
120 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
7d316911 121 /* 0x60 - 0x67 */
6aa8b732 122 0, 0, 0, DstReg | SrcMem32 | ModRM | Mov /* movsxd (x86/64) */ ,
7d316911
NK		 123 0, 0, 0, 0,
124 /* 0x68 - 0x6F */
91ed7a0e 125 SrcImm | Mov | Stack, 0, SrcImmByte | Mov | Stack, 0,
e70669ab
LV		 126 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* insb, insw/insd */
127 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* outsb, outsw/outsd */
55bebde4
NK		 128 /* 0x70 - 0x77 */
129 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
130 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
131 /* 0x78 - 0x7F */
132 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
133 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
6aa8b732 134 /* 0x80 - 0x87 */
1d6ad207
AK		 135 Group | Group1_80, Group | Group1_81,
136 Group | Group1_82, Group | Group1_83,
6aa8b732
AK		 137 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
138 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
139 /* 0x88 - 0x8F */
140 ByteOp | DstMem | SrcReg | ModRM | Mov, DstMem | SrcReg | ModRM | Mov,
141 ByteOp | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
38d5bc6d 142 DstMem | SrcReg | ModRM | Mov, ModRM | DstReg,
4257198a 143 DstReg | SrcMem | ModRM | Mov, Group | Group1A,
b13354f8
MG		 144 /* 0x90 - 0x97 */
145 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
146 /* 0x98 - 0x9F */
6e3d5dfb 147 0, 0, 0, 0, ImplicitOps | Stack, ImplicitOps | Stack, 0, 0,
6aa8b732 148 /* 0xA0 - 0xA7 */
c7e75a3d
AK		 149 ByteOp | DstReg | SrcMem | Mov | MemAbs, DstReg | SrcMem | Mov | MemAbs,
150 ByteOp | DstMem | SrcReg | Mov | MemAbs, DstMem | SrcReg | Mov | MemAbs,
b9fa9d6b
AK		 151 ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
152 ByteOp | ImplicitOps | String, ImplicitOps | String,
6aa8b732 153 /* 0xA8 - 0xAF */
b9fa9d6b
AK		 154 0, 0, ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
155 ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
156 ByteOp | ImplicitOps | String, ImplicitOps | String,
a5e2e82b
MG		 157 /* 0xB0 - 0xB7 */
158 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
159 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
160 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
161 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
162 /* 0xB8 - 0xBF */
163 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
164 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
165 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
166 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
6aa8b732 167 /* 0xC0 - 0xC7 */
d9413cd7 168 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM,
6e3d5dfb 169 0, ImplicitOps | Stack, 0, 0,
d9413cd7 170 ByteOp | DstMem | SrcImm | ModRM | Mov, DstMem | SrcImm | ModRM | Mov,
6aa8b732
AK		 171 /* 0xC8 - 0xCF */
172 0, 0, 0, 0, 0, 0, 0, 0,
173 /* 0xD0 - 0xD7 */
174 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
175 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
176 0, 0, 0, 0,
177 /* 0xD8 - 0xDF */
178 0, 0, 0, 0, 0, 0, 0, 0,
098c937b 179 /* 0xE0 - 0xE7 */
a6a3034c
MG		 180 0, 0, 0, 0,
181 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
182 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
098c937b 183 /* 0xE8 - 0xEF */
954cd36f
GT		 184 ImplicitOps | Stack, SrcImm | ImplicitOps,
185 ImplicitOps, SrcImmByte | ImplicitOps,
a6a3034c
MG		 186 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
187 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
6aa8b732
AK		 188 /* 0xF0 - 0xF7 */
189 0, 0, 0, 0,
7d858a19 190 ImplicitOps, ImplicitOps, Group | Group3_Byte, Group | Group3,
6aa8b732 191 /* 0xF8 - 0xFF */
b284be57 192 ImplicitOps, 0, ImplicitOps, ImplicitOps,
fb4616f4 193 ImplicitOps, ImplicitOps, Group | Group4, Group | Group5,
6aa8b732
AK		 194};
195
038e51de 196static u16 twobyte_table[256] = {
6aa8b732 197 /* 0x00 - 0x0F */
d95058a1 198 0, Group | GroupDual | Group7, 0, 0, 0, 0, ImplicitOps, 0,
651a3e29 199 ImplicitOps, ImplicitOps, 0, 0, 0, ImplicitOps | ModRM, 0, 0,
6aa8b732
AK		 200 /* 0x10 - 0x1F */
201 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0,
202 /* 0x20 - 0x2F */
203 ModRM | ImplicitOps, ModRM, ModRM | ImplicitOps, ModRM, 0, 0, 0, 0,
204 0, 0, 0, 0, 0, 0, 0, 0,
205 /* 0x30 - 0x3F */
35f3f286 206 ImplicitOps, 0, ImplicitOps, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 207 /* 0x40 - 0x47 */
208 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
209 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
210 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
211 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
212 /* 0x48 - 0x4F */
213 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
214 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
215 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
216 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
217 /* 0x50 - 0x5F */
218 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
219 /* 0x60 - 0x6F */
220 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
221 /* 0x70 - 0x7F */
222 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
223 /* 0x80 - 0x8F */
bbe9abbd
NK		 224 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
225 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
226 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
227 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
6aa8b732
AK		 228 /* 0x90 - 0x9F */
229 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
230 /* 0xA0 - 0xA7 */
038e51de 231 0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, 0, 0,
6aa8b732 232 /* 0xA8 - 0xAF */
2a7c5b8b 233 0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, ModRM, 0,
6aa8b732
AK		 234 /* 0xB0 - 0xB7 */
235 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, 0,
038e51de 236 DstMem | SrcReg | ModRM | BitOp,
6aa8b732
AK		 237 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
238 DstReg | SrcMem16 | ModRM | Mov,
239 /* 0xB8 - 0xBF */
038e51de 240 0, 0, DstMem | SrcImmByte | ModRM, DstMem | SrcReg | ModRM | BitOp,
6aa8b732
AK		 241 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
242 DstReg | SrcMem16 | ModRM | Mov,
243 /* 0xC0 - 0xCF */
a012e65a
SY		 244 0, 0, 0, DstMem | SrcReg | ModRM | Mov, 0, 0, 0, ImplicitOps | ModRM,
245 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 246 /* 0xD0 - 0xDF */
247 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
248 /* 0xE0 - 0xEF */
249 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
250 /* 0xF0 - 0xFF */
251 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
252};
253
e09d082c 254static u16 group_table[] = {
1d6ad207
AK		 255 [Group1_80*8] =
256 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
257 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
258 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
259 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
260 [Group1_81*8] =
261 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
262 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
263 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
264 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
265 [Group1_82*8] =
266 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
267 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
268 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
269 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
270 [Group1_83*8] =
271 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
272 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
273 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
274 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
43bb19cd
AK		 275 [Group1A*8] =
276 DstMem | SrcNone | ModRM | Mov | Stack, 0, 0, 0, 0, 0, 0, 0,
7d858a19
AK		 277 [Group3_Byte*8] =
278 ByteOp | SrcImm | DstMem | ModRM, 0,
279 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
280 0, 0, 0, 0,
281 [Group3*8] =
41afa025 282 DstMem | SrcImm | ModRM, 0,
6eb06cb2 283 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
7d858a19 284 0, 0, 0, 0,
fd60754e
AK		 285 [Group4*8] =
286 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
287 0, 0, 0, 0, 0, 0,
288 [Group5*8] =
289 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM, 0, 0,
290 SrcMem | ModRM, 0, SrcMem | ModRM | Stack, 0,
d95058a1
AK		 291 [Group7*8] =
292 0, 0, ModRM | SrcMem, ModRM | SrcMem,
16286d08
AK		 293 SrcNone | ModRM | DstMem | Mov, 0,
294 SrcMem16 | ModRM | Mov, SrcMem | ModRM | ByteOp,
e09d082c
AK		 295};
296
297static u16 group2_table[] = {
d95058a1 298 [Group7*8] =
16286d08
AK		 299 SrcNone | ModRM, 0, 0, 0,
300 SrcNone | ModRM | DstMem | Mov, 0,
301 SrcMem16 | ModRM | Mov, 0,
e09d082c
AK		 302};
303
6aa8b732
AK		 304/* EFLAGS bit definitions. */
305#define EFLG_OF (1<<11)
306#define EFLG_DF (1<<10)
307#define EFLG_SF (1<<7)
308#define EFLG_ZF (1<<6)
309#define EFLG_AF (1<<4)
310#define EFLG_PF (1<<2)
311#define EFLG_CF (1<<0)
312
313/*
314 * Instruction emulation:
315 * Most instructions are emulated directly via a fragment of inline assembly
316 * code. This allows us to save/restore EFLAGS and thus very easily pick up
317 * any modified flags.
318 */
319
05b3e0c2 320#if defined(CONFIG_X86_64)
6aa8b732
AK		 321#define _LO32 "k" /* force 32-bit operand */
322#define _STK "%%rsp" /* stack pointer */
323#elif defined(__i386__)
324#define _LO32 "" /* force 32-bit operand */
325#define _STK "%%esp" /* stack pointer */
326#endif
327
328/*
329 * These EFLAGS bits are restored from saved value during emulation, and
330 * any changes are written back to the saved value after emulation.
331 */
332#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
333
334/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 335#define _PRE_EFLAGS(_sav, _msk, _tmp) \
336 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
337 "movl %"_sav",%"_LO32 _tmp"; " \
338 "push %"_tmp"; " \
339 "push %"_tmp"; " \
340 "movl %"_msk",%"_LO32 _tmp"; " \
341 "andl %"_LO32 _tmp",("_STK"); " \
342 "pushf; " \
343 "notl %"_LO32 _tmp"; " \
344 "andl %"_LO32 _tmp",("_STK"); " \
345 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
346 "pop %"_tmp"; " \
347 "orl %"_LO32 _tmp",("_STK"); " \
348 "popf; " \
349 "pop %"_sav"; "
6aa8b732
AK		 350
351/* After executing instruction: write-back necessary bits in EFLAGS. */
352#define _POST_EFLAGS(_sav, _msk, _tmp) \
353 /* _sav |= EFLAGS & _msk; */ \
354 "pushf; " \
355 "pop %"_tmp"; " \
356 "andl %"_msk",%"_LO32 _tmp"; " \
357 "orl %"_LO32 _tmp",%"_sav"; "
358
359/* Raw emulation: instruction has two explicit operands. */
360#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
361 do { \
362 unsigned long _tmp; \
363 \
364 switch ((_dst).bytes) { \
365 case 2: \
366 __asm__ __volatile__ ( \
d77c26fc 367 _PRE_EFLAGS("0", "4", "2") \
6aa8b732 368 _op"w %"_wx"3,%1; " \
d77c26fc 369 _POST_EFLAGS("0", "4", "2") \
6aa8b732
AK		 370 : "=m" (_eflags), "=m" ((_dst).val), \
371 "=&r" (_tmp) \
d77c26fc 372 : _wy ((_src).val), "i" (EFLAGS_MASK)); \
6aa8b732
AK		 373 break; \
374 case 4: \
375 __asm__ __volatile__ ( \
d77c26fc 376 _PRE_EFLAGS("0", "4", "2") \
6aa8b732 377 _op"l %"_lx"3,%1; " \
d77c26fc 378 _POST_EFLAGS("0", "4", "2") \
6aa8b732
AK		 379 : "=m" (_eflags), "=m" ((_dst).val), \
380 "=&r" (_tmp) \
d77c26fc 381 : _ly ((_src).val), "i" (EFLAGS_MASK)); \
6aa8b732
AK		 382 break; \
383 case 8: \
384 __emulate_2op_8byte(_op, _src, _dst, \
385 _eflags, _qx, _qy); \
386 break; \
387 } \
388 } while (0)
389
390#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
391 do { \
77cd337f 392 unsigned long __tmp; \
d77c26fc 393 switch ((_dst).bytes) { \
6aa8b732
AK		 394 case 1: \
395 __asm__ __volatile__ ( \
d77c26fc 396 _PRE_EFLAGS("0", "4", "2") \
6aa8b732 397 _op"b %"_bx"3,%1; " \
d77c26fc 398 _POST_EFLAGS("0", "4", "2") \
6aa8b732 399 : "=m" (_eflags), "=m" ((_dst).val), \
77cd337f 400 "=&r" (__tmp) \
d77c26fc 401 : _by ((_src).val), "i" (EFLAGS_MASK)); \
6aa8b732
AK		 402 break; \
403 default: \
404 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
405 _wx, _wy, _lx, _ly, _qx, _qy); \
406 break; \
407 } \
408 } while (0)
409
410/* Source operand is byte-sized and may be restricted to just %cl. */
411#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
412 __emulate_2op(_op, _src, _dst, _eflags, \
413 "b", "c", "b", "c", "b", "c", "b", "c")
414
415/* Source operand is byte, word, long or quad sized. */
416#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
417 __emulate_2op(_op, _src, _dst, _eflags, \
418 "b", "q", "w", "r", _LO32, "r", "", "r")
419
420/* Source operand is word, long or quad sized. */
421#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
422 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
423 "w", "r", _LO32, "r", "", "r")
424
425/* Instruction has only one explicit operand (no source operand). */
426#define emulate_1op(_op, _dst, _eflags) \
427 do { \
428 unsigned long _tmp; \
429 \
d77c26fc 430 switch ((_dst).bytes) { \
6aa8b732
AK		 431 case 1: \
432 __asm__ __volatile__ ( \
d77c26fc 433 _PRE_EFLAGS("0", "3", "2") \
6aa8b732 434 _op"b %1; " \
d77c26fc 435 _POST_EFLAGS("0", "3", "2") \
6aa8b732
AK		 436 : "=m" (_eflags), "=m" ((_dst).val), \
437 "=&r" (_tmp) \
d77c26fc 438 : "i" (EFLAGS_MASK)); \
6aa8b732
AK		 439 break; \
440 case 2: \
441 __asm__ __volatile__ ( \
d77c26fc 442 _PRE_EFLAGS("0", "3", "2") \
6aa8b732 443 _op"w %1; " \
d77c26fc 444 _POST_EFLAGS("0", "3", "2") \
6aa8b732
AK		 445 : "=m" (_eflags), "=m" ((_dst).val), \
446 "=&r" (_tmp) \
d77c26fc 447 : "i" (EFLAGS_MASK)); \
6aa8b732
AK		 448 break; \
449 case 4: \
450 __asm__ __volatile__ ( \
d77c26fc 451 _PRE_EFLAGS("0", "3", "2") \
6aa8b732 452 _op"l %1; " \
d77c26fc 453 _POST_EFLAGS("0", "3", "2") \
6aa8b732
AK		 454 : "=m" (_eflags), "=m" ((_dst).val), \
455 "=&r" (_tmp) \
d77c26fc 456 : "i" (EFLAGS_MASK)); \
6aa8b732
AK		 457 break; \
458 case 8: \
459 __emulate_1op_8byte(_op, _dst, _eflags); \
460 break; \
461 } \
462 } while (0)
463
464/* Emulate an instruction with quadword operands (x86/64 only). */
05b3e0c2 465#if defined(CONFIG_X86_64)
6aa8b732
AK		 466#define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy) \
467 do { \
468 __asm__ __volatile__ ( \
d77c26fc 469 _PRE_EFLAGS("0", "4", "2") \
6aa8b732 470 _op"q %"_qx"3,%1; " \
d77c26fc 471 _POST_EFLAGS("0", "4", "2") \
6aa8b732 472 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
d77c26fc 473 : _qy ((_src).val), "i" (EFLAGS_MASK)); \
6aa8b732
AK		 474 } while (0)
475
476#define __emulate_1op_8byte(_op, _dst, _eflags) \
477 do { \
478 __asm__ __volatile__ ( \
d77c26fc 479 _PRE_EFLAGS("0", "3", "2") \
6aa8b732 480 _op"q %1; " \
d77c26fc 481 _POST_EFLAGS("0", "3", "2") \
6aa8b732 482 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
d77c26fc 483 : "i" (EFLAGS_MASK)); \
6aa8b732
AK		 484 } while (0)
485
486#elif defined(__i386__)
487#define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy)
488#define __emulate_1op_8byte(_op, _dst, _eflags)
489#endif /* __i386__ */
490
491/* Fetch next part of the instruction being emulated. */
492#define insn_fetch(_type, _size, _eip) \
493({ unsigned long _x; \
62266869 494 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
d77c26fc 495 if (rc != 0) \
6aa8b732
AK		 496 goto done; \
497 (_eip) += (_size); \
498 (_type)_x; \
499})
500
ddcb2885
HH		 501static inline unsigned long ad_mask(struct decode_cache *c)
502{
503 return (1UL << (c->ad_bytes << 3)) - 1;
504}
505
6aa8b732 506/* Access/update address held in a register, based on addressing mode. */
e4706772
HH		 507static inline unsigned long
508address_mask(struct decode_cache *c, unsigned long reg)
509{
510 if (c->ad_bytes == sizeof(unsigned long))
511 return reg;
512 else
513 return reg & ad_mask(c);
514}
515
516static inline unsigned long
517register_address(struct decode_cache *c, unsigned long base, unsigned long reg)
518{
519 return base + address_mask(c, reg);
520}
521
7a957275
HH		 522static inline void
523register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
524{
525 if (c->ad_bytes == sizeof(unsigned long))
526 *reg += inc;
527 else
528 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
529}
6aa8b732 530
7a957275
HH		 531static inline void jmp_rel(struct decode_cache *c, int rel)
532{
533 register_address_increment(c, &c->eip, rel);
534}
098c937b 535
7a5b56df
AK		 536static void set_seg_override(struct decode_cache *c, int seg)
537{
538 c->has_seg_override = true;
539 c->seg_override = seg;
540}
541
542static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
543{
544 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
545 return 0;
546
547 return kvm_x86_ops->get_segment_base(ctxt->vcpu, seg);
548}
549
550static unsigned long seg_override_base(struct x86_emulate_ctxt *ctxt,
551 struct decode_cache *c)
552{
553 if (!c->has_seg_override)
554 return 0;
555
556 return seg_base(ctxt, c->seg_override);
557}
558
559static unsigned long es_base(struct x86_emulate_ctxt *ctxt)
560{
561 return seg_base(ctxt, VCPU_SREG_ES);
562}
563
564static unsigned long ss_base(struct x86_emulate_ctxt *ctxt)
565{
566 return seg_base(ctxt, VCPU_SREG_SS);
567}
568
62266869
AK		 569static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
570 struct x86_emulate_ops *ops,
571 unsigned long linear, u8 *dest)
572{
573 struct fetch_cache *fc = &ctxt->decode.fetch;
574 int rc;
575 int size;
576
577 if (linear < fc->start || linear >= fc->end) {
578 size = min(15UL, PAGE_SIZE - offset_in_page(linear));
579 rc = ops->read_std(linear, fc->data, size, ctxt->vcpu);
580 if (rc)
581 return rc;
582 fc->start = linear;
583 fc->end = linear + size;
584 }
585 *dest = fc->data[linear - fc->start];
586 return 0;
587}
588
589static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
590 struct x86_emulate_ops *ops,
591 unsigned long eip, void *dest, unsigned size)
592{
593 int rc = 0;
594
595 eip += ctxt->cs_base;
596 while (size--) {
597 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
598 if (rc)
599 return rc;
600 }
601 return 0;
602}
603
1e3c5cb0
RR		 604/*
605 * Given the 'reg' portion of a ModRM byte, and a register block, return a
606 * pointer into the block that addresses the relevant register.
607 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
608 */
609static void *decode_register(u8 modrm_reg, unsigned long *regs,
610 int highbyte_regs)
6aa8b732
AK		 611{
612 void *p;
613
614 p = &regs[modrm_reg];
615 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
616 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
617 return p;
618}
619
620static int read_descriptor(struct x86_emulate_ctxt *ctxt,
621 struct x86_emulate_ops *ops,
622 void *ptr,
623 u16 *size, unsigned long *address, int op_bytes)
624{
625 int rc;
626
627 if (op_bytes == 2)
628 op_bytes = 3;
629 *address = 0;
cebff02b
LV		 630 rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2,
631 ctxt->vcpu);
6aa8b732
AK		 632 if (rc)
633 return rc;
cebff02b
LV		 634 rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes,
635 ctxt->vcpu);
6aa8b732
AK		 636 return rc;
637}
638
bbe9abbd
NK		 639static int test_cc(unsigned int condition, unsigned int flags)
640{
641 int rc = 0;
642
643 switch ((condition & 15) >> 1) {
644 case 0: /* o */
645 rc |= (flags & EFLG_OF);
646 break;
647 case 1: /* b/c/nae */
648 rc |= (flags & EFLG_CF);
649 break;
650 case 2: /* z/e */
651 rc |= (flags & EFLG_ZF);
652 break;
653 case 3: /* be/na */
654 rc |= (flags & (EFLG_CF|EFLG_ZF));
655 break;
656 case 4: /* s */
657 rc |= (flags & EFLG_SF);
658 break;
659 case 5: /* p/pe */
660 rc |= (flags & EFLG_PF);
661 break;
662 case 7: /* le/ng */
663 rc |= (flags & EFLG_ZF);
664 /* fall through */
665 case 6: /* l/nge */
666 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
667 break;
668 }
669
670 /* Odd condition identifiers (lsb == 1) have inverted sense. */
671 return (!!rc ^ (condition & 1));
672}
673
3c118e24
AK		 674static void decode_register_operand(struct operand *op,
675 struct decode_cache *c,
3c118e24
AK		 676 int inhibit_bytereg)
677{
33615aa9 678 unsigned reg = c->modrm_reg;
9f1ef3f8 679 int highbyte_regs = c->rex_prefix == 0;
33615aa9
AK		 680
681 if (!(c->d & ModRM))
682 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
3c118e24
AK		 683 op->type = OP_REG;
684 if ((c->d & ByteOp) && !inhibit_bytereg) {
33615aa9 685 op->ptr = decode_register(reg, c->regs, highbyte_regs);
3c118e24
AK		 686 op->val = *(u8 *)op->ptr;
687 op->bytes = 1;
688 } else {
33615aa9 689 op->ptr = decode_register(reg, c->regs, 0);
3c118e24
AK		 690 op->bytes = c->op_bytes;
691 switch (op->bytes) {
692 case 2:
693 op->val = *(u16 *)op->ptr;
694 break;
695 case 4:
696 op->val = *(u32 *)op->ptr;
697 break;
698 case 8:
699 op->val = *(u64 *) op->ptr;
700 break;
701 }
702 }
703 op->orig_val = op->val;
704}
705
1c73ef66
AK		 706static int decode_modrm(struct x86_emulate_ctxt *ctxt,
707 struct x86_emulate_ops *ops)
708{
709 struct decode_cache *c = &ctxt->decode;
710 u8 sib;
f5b4edcd 711 int index_reg = 0, base_reg = 0, scale;
1c73ef66
AK		 712 int rc = 0;
713
714 if (c->rex_prefix) {
715 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
716 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
717 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
718 }
719
720 c->modrm = insn_fetch(u8, 1, c->eip);
721 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
722 c->modrm_reg |= (c->modrm & 0x38) >> 3;
723 c->modrm_rm |= (c->modrm & 0x07);
724 c->modrm_ea = 0;
725 c->use_modrm_ea = 1;
726
727 if (c->modrm_mod == 3) {
107d6d2e
AK		 728 c->modrm_ptr = decode_register(c->modrm_rm,
729 c->regs, c->d & ByteOp);
730 c->modrm_val = *(unsigned long *)c->modrm_ptr;
1c73ef66
AK		 731 return rc;
732 }
733
734 if (c->ad_bytes == 2) {
735 unsigned bx = c->regs[VCPU_REGS_RBX];
736 unsigned bp = c->regs[VCPU_REGS_RBP];
737 unsigned si = c->regs[VCPU_REGS_RSI];
738 unsigned di = c->regs[VCPU_REGS_RDI];
739
740 /* 16-bit ModR/M decode. */
741 switch (c->modrm_mod) {
742 case 0:
743 if (c->modrm_rm == 6)
744 c->modrm_ea += insn_fetch(u16, 2, c->eip);
745 break;
746 case 1:
747 c->modrm_ea += insn_fetch(s8, 1, c->eip);
748 break;
749 case 2:
750 c->modrm_ea += insn_fetch(u16, 2, c->eip);
751 break;
752 }
753 switch (c->modrm_rm) {
754 case 0:
755 c->modrm_ea += bx + si;
756 break;
757 case 1:
758 c->modrm_ea += bx + di;
759 break;
760 case 2:
761 c->modrm_ea += bp + si;
762 break;
763 case 3:
764 c->modrm_ea += bp + di;
765 break;
766 case 4:
767 c->modrm_ea += si;
768 break;
769 case 5:
770 c->modrm_ea += di;
771 break;
772 case 6:
773 if (c->modrm_mod != 0)
774 c->modrm_ea += bp;
775 break;
776 case 7:
777 c->modrm_ea += bx;
778 break;
779 }
780 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
781 (c->modrm_rm == 6 && c->modrm_mod != 0))
7a5b56df
AK		 782 if (!c->has_seg_override)
783 set_seg_override(c, VCPU_SREG_SS);
1c73ef66
AK		 784 c->modrm_ea = (u16)c->modrm_ea;
785 } else {
786 /* 32/64-bit ModR/M decode. */
84411d85 787 if ((c->modrm_rm & 7) == 4) {
1c73ef66
AK		 788 sib = insn_fetch(u8, 1, c->eip);
789 index_reg |= (sib >> 3) & 7;
790 base_reg |= sib & 7;
791 scale = sib >> 6;
792
dc71d0f1
AK		 793 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
794 c->modrm_ea += insn_fetch(s32, 4, c->eip);
795 else
1c73ef66 796 c->modrm_ea += c->regs[base_reg];
dc71d0f1 797 if (index_reg != 4)
1c73ef66 798 c->modrm_ea += c->regs[index_reg] << scale;
84411d85
AK		 799 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
800 if (ctxt->mode == X86EMUL_MODE_PROT64)
f5b4edcd 801 c->rip_relative = 1;
84411d85 802 } else
1c73ef66 803 c->modrm_ea += c->regs[c->modrm_rm];
1c73ef66
AK		 804 switch (c->modrm_mod) {
805 case 0:
806 if (c->modrm_rm == 5)
807 c->modrm_ea += insn_fetch(s32, 4, c->eip);
808 break;
809 case 1:
810 c->modrm_ea += insn_fetch(s8, 1, c->eip);
811 break;
812 case 2:
813 c->modrm_ea += insn_fetch(s32, 4, c->eip);
814 break;
815 }
816 }
1c73ef66
AK		 817done:
818 return rc;
819}
820
821static int decode_abs(struct x86_emulate_ctxt *ctxt,
822 struct x86_emulate_ops *ops)
823{
824 struct decode_cache *c = &ctxt->decode;
825 int rc = 0;
826
827 switch (c->ad_bytes) {
828 case 2:
829 c->modrm_ea = insn_fetch(u16, 2, c->eip);
830 break;
831 case 4:
832 c->modrm_ea = insn_fetch(u32, 4, c->eip);
833 break;
834 case 8:
835 c->modrm_ea = insn_fetch(u64, 8, c->eip);
836 break;
837 }
838done:
839 return rc;
840}
841
6aa8b732 842int
8b4caf66 843x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
6aa8b732 844{
e4e03ded 845 struct decode_cache *c = &ctxt->decode;
6aa8b732 846 int rc = 0;
6aa8b732 847 int mode = ctxt->mode;
e09d082c 848 int def_op_bytes, def_ad_bytes, group;
6aa8b732
AK		 849
850 /* Shadow copy of register state. Committed on successful emulation. */
6aa8b732 851
e4e03ded 852 memset(c, 0, sizeof(struct decode_cache));
5fdbf976 853 c->eip = kvm_rip_read(ctxt->vcpu);
7a5b56df 854 ctxt->cs_base = seg_base(ctxt, VCPU_SREG_CS);
ad312c7c 855 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
6aa8b732
AK		 856
857 switch (mode) {
858 case X86EMUL_MODE_REAL:
859 case X86EMUL_MODE_PROT16:
f21b8bf4 860 def_op_bytes = def_ad_bytes = 2;
6aa8b732
AK		 861 break;
862 case X86EMUL_MODE_PROT32:
f21b8bf4 863 def_op_bytes = def_ad_bytes = 4;
6aa8b732 864 break;
05b3e0c2 865#ifdef CONFIG_X86_64
6aa8b732 866 case X86EMUL_MODE_PROT64:
f21b8bf4
AK		 867 def_op_bytes = 4;
868 def_ad_bytes = 8;
6aa8b732
AK		 869 break;
870#endif
871 default:
872 return -1;
873 }
874
f21b8bf4
AK		 875 c->op_bytes = def_op_bytes;
876 c->ad_bytes = def_ad_bytes;
877
6aa8b732 878 /* Legacy prefixes. */
b4c6abfe 879 for (;;) {
e4e03ded 880 switch (c->b = insn_fetch(u8, 1, c->eip)) {
6aa8b732 881 case 0x66: /* operand-size override */
f21b8bf4
AK		 882 /* switch between 2/4 bytes */
883 c->op_bytes = def_op_bytes ^ 6;
6aa8b732
AK		 884 break;
885 case 0x67: /* address-size override */
886 if (mode == X86EMUL_MODE_PROT64)
e4e03ded 887 /* switch between 4/8 bytes */
f21b8bf4 888 c->ad_bytes = def_ad_bytes ^ 12;
6aa8b732 889 else
e4e03ded 890 /* switch between 2/4 bytes */
f21b8bf4 891 c->ad_bytes = def_ad_bytes ^ 6;
6aa8b732 892 break;
7a5b56df 893 case 0x26: /* ES override */
6aa8b732 894 case 0x2e: /* CS override */
7a5b56df 895 case 0x36: /* SS override */
6aa8b732 896 case 0x3e: /* DS override */
7a5b56df 897 set_seg_override(c, (c->b >> 3) & 3);
6aa8b732
AK		 898 break;
899 case 0x64: /* FS override */
6aa8b732 900 case 0x65: /* GS override */
7a5b56df 901 set_seg_override(c, c->b & 7);
6aa8b732 902 break;
b4c6abfe
LV		 903 case 0x40 ... 0x4f: /* REX */
904 if (mode != X86EMUL_MODE_PROT64)
905 goto done_prefixes;
33615aa9 906 c->rex_prefix = c->b;
b4c6abfe 907 continue;
6aa8b732 908 case 0xf0: /* LOCK */
e4e03ded 909 c->lock_prefix = 1;
6aa8b732 910 break;
ae6200ba 911 case 0xf2: /* REPNE/REPNZ */
90e0a28f
GT		 912 c->rep_prefix = REPNE_PREFIX;
913 break;
6aa8b732 914 case 0xf3: /* REP/REPE/REPZ */
90e0a28f 915 c->rep_prefix = REPE_PREFIX;
6aa8b732 916 break;
6aa8b732
AK		 917 default:
918 goto done_prefixes;
919 }
b4c6abfe
LV		 920
921 /* Any legacy prefix after a REX prefix nullifies its effect. */
922
33615aa9 923 c->rex_prefix = 0;
6aa8b732
AK		 924 }
925
926done_prefixes:
927
928 /* REX prefix. */
1c73ef66 929 if (c->rex_prefix)
33615aa9 930 if (c->rex_prefix & 8)
e4e03ded 931 c->op_bytes = 8; /* REX.W */
6aa8b732
AK		 932
933 /* Opcode byte(s). */
e4e03ded
LV		 934 c->d = opcode_table[c->b];
935 if (c->d == 0) {
6aa8b732 936 /* Two-byte opcode? */
e4e03ded
LV		 937 if (c->b == 0x0f) {
938 c->twobyte = 1;
939 c->b = insn_fetch(u8, 1, c->eip);
940 c->d = twobyte_table[c->b];
6aa8b732 941 }
e09d082c 942 }
6aa8b732 943
e09d082c
AK		 944 if (c->d & Group) {
945 group = c->d & GroupMask;
946 c->modrm = insn_fetch(u8, 1, c->eip);
947 --c->eip;
948
949 group = (group << 3) + ((c->modrm >> 3) & 7);
950 if ((c->d & GroupDual) && (c->modrm >> 6) == 3)
951 c->d = group2_table[group];
952 else
953 c->d = group_table[group];
954 }
955
956 /* Unrecognised? */
957 if (c->d == 0) {
958 DPRINTF("Cannot emulate %02x\n", c->b);
959 return -1;
6aa8b732
AK		 960 }
961
6e3d5dfb
AK		 962 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
963 c->op_bytes = 8;
964
6aa8b732 965 /* ModRM and SIB bytes. */
1c73ef66
AK		 966 if (c->d & ModRM)
967 rc = decode_modrm(ctxt, ops);
968 else if (c->d & MemAbs)
969 rc = decode_abs(ctxt, ops);
970 if (rc)
971 goto done;
6aa8b732 972
7a5b56df
AK		 973 if (!c->has_seg_override)
974 set_seg_override(c, VCPU_SREG_DS);
c7e75a3d 975
7a5b56df
AK		 976 if (!(!c->twobyte && c->b == 0x8d))
977 c->modrm_ea += seg_override_base(ctxt, c);
c7e75a3d
AK		 978
979 if (c->ad_bytes != 8)
980 c->modrm_ea = (u32)c->modrm_ea;
6aa8b732
AK		 981 /*
982 * Decode and fetch the source operand: register, memory
983 * or immediate.
984 */
e4e03ded 985 switch (c->d & SrcMask) {
6aa8b732
AK		 986 case SrcNone:
987 break;
988 case SrcReg:
9f1ef3f8 989 decode_register_operand(&c->src, c, 0);
6aa8b732
AK		 990 break;
991 case SrcMem16:
e4e03ded 992 c->src.bytes = 2;
6aa8b732
AK		 993 goto srcmem_common;
994 case SrcMem32:
e4e03ded 995 c->src.bytes = 4;
6aa8b732
AK		 996 goto srcmem_common;
997 case SrcMem:
e4e03ded
LV		 998 c->src.bytes = (c->d & ByteOp) ? 1 :
999 c->op_bytes;
b85b9ee9 1000 /* Don't fetch the address for invlpg: it could be unmapped. */
d77c26fc 1001 if (c->twobyte && c->b == 0x01 && c->modrm_reg == 7)
b85b9ee9 1002 break;
d77c26fc 1003 srcmem_common:
4e62417b
AJ		 1004 /*
1005 * For instructions with a ModR/M byte, switch to register
1006 * access if Mod = 3.
1007 */
e4e03ded
LV		 1008 if ((c->d & ModRM) && c->modrm_mod == 3) {
1009 c->src.type = OP_REG;
66b85505 1010 c->src.val = c->modrm_val;
107d6d2e 1011 c->src.ptr = c->modrm_ptr;
4e62417b
AJ		 1012 break;
1013 }
e4e03ded 1014 c->src.type = OP_MEM;
6aa8b732
AK		 1015 break;
1016 case SrcImm:
e4e03ded
LV		 1017 c->src.type = OP_IMM;
1018 c->src.ptr = (unsigned long *)c->eip;
1019 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1020 if (c->src.bytes == 8)
1021 c->src.bytes = 4;
6aa8b732 1022 /* NB. Immediates are sign-extended as necessary. */
e4e03ded 1023 switch (c->src.bytes) {
6aa8b732 1024 case 1:
e4e03ded 1025 c->src.val = insn_fetch(s8, 1, c->eip);
6aa8b732
AK		 1026 break;
1027 case 2:
e4e03ded 1028 c->src.val = insn_fetch(s16, 2, c->eip);
6aa8b732
AK		 1029 break;
1030 case 4:
e4e03ded 1031 c->src.val = insn_fetch(s32, 4, c->eip);
6aa8b732
AK		 1032 break;
1033 }
1034 break;
1035 case SrcImmByte:
e4e03ded
LV		 1036 c->src.type = OP_IMM;
1037 c->src.ptr = (unsigned long *)c->eip;
1038 c->src.bytes = 1;
1039 c->src.val = insn_fetch(s8, 1, c->eip);
6aa8b732
AK		 1040 break;
1041 }
1042
038e51de 1043 /* Decode and fetch the destination operand: register or memory. */
e4e03ded 1044 switch (c->d & DstMask) {
038e51de
AK		 1045 case ImplicitOps:
1046 /* Special instructions do their own operand decoding. */
8b4caf66 1047 return 0;
038e51de 1048 case DstReg:
9f1ef3f8 1049 decode_register_operand(&c->dst, c,
3c118e24 1050 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
038e51de
AK		 1051 break;
1052 case DstMem:
e4e03ded 1053 if ((c->d & ModRM) && c->modrm_mod == 3) {
89c69638 1054 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4e03ded 1055 c->dst.type = OP_REG;
66b85505 1056 c->dst.val = c->dst.orig_val = c->modrm_val;
107d6d2e 1057 c->dst.ptr = c->modrm_ptr;
4e62417b
AJ		 1058 break;
1059 }
8b4caf66
LV		 1060 c->dst.type = OP_MEM;
1061 break;
1062 }
1063
f5b4edcd
AK		 1064 if (c->rip_relative)
1065 c->modrm_ea += c->eip;
1066
8b4caf66
LV		 1067done:
1068 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
1069}
1070
8cdbd2c9
LV		 1071static inline void emulate_push(struct x86_emulate_ctxt *ctxt)
1072{
1073 struct decode_cache *c = &ctxt->decode;
1074
1075 c->dst.type = OP_MEM;
1076 c->dst.bytes = c->op_bytes;
1077 c->dst.val = c->src.val;
7a957275 1078 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
7a5b56df 1079 c->dst.ptr = (void *) register_address(c, ss_base(ctxt),
8cdbd2c9
LV		 1080 c->regs[VCPU_REGS_RSP]);
1081}
1082
1083static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
1084 struct x86_emulate_ops *ops)
1085{
1086 struct decode_cache *c = &ctxt->decode;
1087 int rc;
1088
7a5b56df 1089 rc = ops->read_std(register_address(c, ss_base(ctxt),
8cdbd2c9
LV		 1090 c->regs[VCPU_REGS_RSP]),
1091 &c->dst.val, c->dst.bytes, ctxt->vcpu);
1092 if (rc != 0)
1093 return rc;
1094
7a957275 1095 register_address_increment(c, &c->regs[VCPU_REGS_RSP], c->dst.bytes);
8cdbd2c9
LV		 1096
1097 return 0;
1098}
1099
05f086f8 1100static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1101{
05f086f8 1102 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1103 switch (c->modrm_reg) {
1104 case 0: /* rol */
05f086f8 1105 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1106 break;
1107 case 1: /* ror */
05f086f8 1108 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1109 break;
1110 case 2: /* rcl */
05f086f8 1111 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1112 break;
1113 case 3: /* rcr */
05f086f8 1114 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1115 break;
1116 case 4: /* sal/shl */
1117 case 6: /* sal/shl */
05f086f8 1118 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1119 break;
1120 case 5: /* shr */
05f086f8 1121 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1122 break;
1123 case 7: /* sar */
05f086f8 1124 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1125 break;
1126 }
1127}
1128
1129static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
05f086f8 1130 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1131{
1132 struct decode_cache *c = &ctxt->decode;
1133 int rc = 0;
1134
1135 switch (c->modrm_reg) {
1136 case 0 ... 1: /* test */
05f086f8 1137 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1138 break;
1139 case 2: /* not */
1140 c->dst.val = ~c->dst.val;
1141 break;
1142 case 3: /* neg */
05f086f8 1143 emulate_1op("neg", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1144 break;
1145 default:
1146 DPRINTF("Cannot emulate %02x\n", c->b);
1147 rc = X86EMUL_UNHANDLEABLE;
1148 break;
1149 }
8cdbd2c9
LV		 1150 return rc;
1151}
1152
1153static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
a01af5ec 1154 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1155{
1156 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1157
1158 switch (c->modrm_reg) {
1159 case 0: /* inc */
05f086f8 1160 emulate_1op("inc", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1161 break;
1162 case 1: /* dec */
05f086f8 1163 emulate_1op("dec", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1164 break;
1165 case 4: /* jmp abs */
fd60754e 1166 c->eip = c->src.val;
8cdbd2c9
LV		 1167 break;
1168 case 6: /* push */
fd60754e 1169 emulate_push(ctxt);
8cdbd2c9 1170 break;
8cdbd2c9
LV		 1171 }
1172 return 0;
1173}
1174
1175static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
1176 struct x86_emulate_ops *ops,
e8d8d7fe 1177 unsigned long memop)
8cdbd2c9
LV		 1178{
1179 struct decode_cache *c = &ctxt->decode;
1180 u64 old, new;
1181 int rc;
1182
e8d8d7fe 1183 rc = ops->read_emulated(memop, &old, 8, ctxt->vcpu);
8cdbd2c9
LV		 1184 if (rc != 0)
1185 return rc;
1186
1187 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1188 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
1189
1190 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1191 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1192 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9
LV		 1193
1194 } else {
1195 new = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1196 (u32) c->regs[VCPU_REGS_RBX];
1197
e8d8d7fe 1198 rc = ops->cmpxchg_emulated(memop, &old, &new, 8, ctxt->vcpu);
8cdbd2c9
LV		 1199 if (rc != 0)
1200 return rc;
05f086f8 1201 ctxt->eflags |= EFLG_ZF;
8cdbd2c9
LV		 1202 }
1203 return 0;
1204}
1205
1206static inline int writeback(struct x86_emulate_ctxt *ctxt,
1207 struct x86_emulate_ops *ops)
1208{
1209 int rc;
1210 struct decode_cache *c = &ctxt->decode;
1211
1212 switch (c->dst.type) {
1213 case OP_REG:
1214 /* The 4-byte case *is* correct:
1215 * in 64-bit mode we zero-extend.
1216 */
1217 switch (c->dst.bytes) {
1218 case 1:
1219 *(u8 *)c->dst.ptr = (u8)c->dst.val;
1220 break;
1221 case 2:
1222 *(u16 *)c->dst.ptr = (u16)c->dst.val;
1223 break;
1224 case 4:
1225 *c->dst.ptr = (u32)c->dst.val;
1226 break; /* 64b: zero-ext */
1227 case 8:
1228 *c->dst.ptr = c->dst.val;
1229 break;
1230 }
1231 break;
1232 case OP_MEM:
1233 if (c->lock_prefix)
1234 rc = ops->cmpxchg_emulated(
1235 (unsigned long)c->dst.ptr,
1236 &c->dst.orig_val,
1237 &c->dst.val,
1238 c->dst.bytes,
1239 ctxt->vcpu);
1240 else
1241 rc = ops->write_emulated(
1242 (unsigned long)c->dst.ptr,
1243 &c->dst.val,
1244 c->dst.bytes,
1245 ctxt->vcpu);
1246 if (rc != 0)
1247 return rc;
a01af5ec
LV		 1248 break;
1249 case OP_NONE:
1250 /* no writeback */
1251 break;
8cdbd2c9
LV		 1252 default:
1253 break;
1254 }
1255 return 0;
1256}
1257
8b4caf66 1258int
1be3aa47 1259x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8b4caf66 1260{
e8d8d7fe 1261 unsigned long memop = 0;
8b4caf66 1262 u64 msr_data;
3427318f 1263 unsigned long saved_eip = 0;
8b4caf66 1264 struct decode_cache *c = &ctxt->decode;
a6a3034c
MG		 1265 unsigned int port;
1266 int io_dir_in;
1be3aa47 1267 int rc = 0;
8b4caf66 1268
3427318f
LV		 1269 /* Shadow copy of register state. Committed on successful emulation.
1270 * NOTE: we can copy them from vcpu as x86_decode_insn() doesn't
1271 * modify them.
1272 */
1273
ad312c7c 1274 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
3427318f
LV		 1275 saved_eip = c->eip;
1276
c7e75a3d 1277 if (((c->d & ModRM) && (c->modrm_mod != 3)) || (c->d & MemAbs))
e8d8d7fe 1278 memop = c->modrm_ea;
8b4caf66 1279
b9fa9d6b
AK		 1280 if (c->rep_prefix && (c->d & String)) {
1281 /* All REP prefixes have the same first termination condition */
1282 if (c->regs[VCPU_REGS_RCX] == 0) {
5fdbf976 1283 kvm_rip_write(ctxt->vcpu, c->eip);
b9fa9d6b
AK		 1284 goto done;
1285 }
1286 /* The second termination condition only applies for REPE
1287 * and REPNE. Test if the repeat string operation prefix is
1288 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
1289 * corresponding termination condition according to:
1290 * - if REPE/REPZ and ZF = 0 then done
1291 * - if REPNE/REPNZ and ZF = 1 then done
1292 */
1293 if ((c->b == 0xa6) || (c->b == 0xa7) ||
1294 (c->b == 0xae) || (c->b == 0xaf)) {
1295 if ((c->rep_prefix == REPE_PREFIX) &&
1296 ((ctxt->eflags & EFLG_ZF) == 0)) {
5fdbf976 1297 kvm_rip_write(ctxt->vcpu, c->eip);
b9fa9d6b
AK		 1298 goto done;
1299 }
1300 if ((c->rep_prefix == REPNE_PREFIX) &&
1301 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF)) {
5fdbf976 1302 kvm_rip_write(ctxt->vcpu, c->eip);
b9fa9d6b
AK		 1303 goto done;
1304 }
1305 }
1306 c->regs[VCPU_REGS_RCX]--;
5fdbf976 1307 c->eip = kvm_rip_read(ctxt->vcpu);
b9fa9d6b
AK		 1308 }
1309
8b4caf66 1310 if (c->src.type == OP_MEM) {
e8d8d7fe 1311 c->src.ptr = (unsigned long *)memop;
8b4caf66 1312 c->src.val = 0;
d77c26fc
MD		 1313 rc = ops->read_emulated((unsigned long)c->src.ptr,
1314 &c->src.val,
1315 c->src.bytes,
1316 ctxt->vcpu);
1317 if (rc != 0)
8b4caf66
LV		 1318 goto done;
1319 c->src.orig_val = c->src.val;
1320 }
1321
1322 if ((c->d & DstMask) == ImplicitOps)
1323 goto special_insn;
1324
1325
1326 if (c->dst.type == OP_MEM) {
e8d8d7fe 1327 c->dst.ptr = (unsigned long *)memop;
8b4caf66
LV		 1328 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1329 c->dst.val = 0;
e4e03ded
LV		 1330 if (c->d & BitOp) {
1331 unsigned long mask = ~(c->dst.bytes * 8 - 1);
df513e2c 1332
e4e03ded
LV		 1333 c->dst.ptr = (void *)c->dst.ptr +
1334 (c->src.val & mask) / 8;
038e51de 1335 }
e4e03ded
LV		 1336 if (!(c->d & Mov) &&
1337 /* optimisation - avoid slow emulated read */
1338 ((rc = ops->read_emulated((unsigned long)c->dst.ptr,
1339 &c->dst.val,
1340 c->dst.bytes, ctxt->vcpu)) != 0))
038e51de 1341 goto done;
038e51de 1342 }
e4e03ded 1343 c->dst.orig_val = c->dst.val;
038e51de 1344
018a98db
AK		 1345special_insn:
1346
e4e03ded 1347 if (c->twobyte)
6aa8b732
AK		 1348 goto twobyte_insn;
1349
e4e03ded 1350 switch (c->b) {
6aa8b732
AK		 1351 case 0x00 ... 0x05:
1352 add: /* add */
05f086f8 1353 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1354 break;
1355 case 0x08 ... 0x0d:
1356 or: /* or */
05f086f8 1357 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1358 break;
1359 case 0x10 ... 0x15:
1360 adc: /* adc */
05f086f8 1361 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1362 break;
1363 case 0x18 ... 0x1d:
1364 sbb: /* sbb */
05f086f8 1365 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
6aa8b732 1366 break;
19eb938e 1367 case 0x20 ... 0x23:
6aa8b732 1368 and: /* and */
05f086f8 1369 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
6aa8b732 1370 break;
19eb938e 1371 case 0x24: /* and al imm8 */
e4e03ded
LV		 1372 c->dst.type = OP_REG;
1373 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
1374 c->dst.val = *(u8 *)c->dst.ptr;
1375 c->dst.bytes = 1;
1376 c->dst.orig_val = c->dst.val;
19eb938e
NK		 1377 goto and;
1378 case 0x25: /* and ax imm16, or eax imm32 */
e4e03ded
LV		 1379 c->dst.type = OP_REG;
1380 c->dst.bytes = c->op_bytes;
1381 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
1382 if (c->op_bytes == 2)
1383 c->dst.val = *(u16 *)c->dst.ptr;
19eb938e 1384 else
e4e03ded
LV		 1385 c->dst.val = *(u32 *)c->dst.ptr;
1386 c->dst.orig_val = c->dst.val;
19eb938e 1387 goto and;
6aa8b732
AK		 1388 case 0x28 ... 0x2d:
1389 sub: /* sub */
05f086f8 1390 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1391 break;
1392 case 0x30 ... 0x35:
1393 xor: /* xor */
05f086f8 1394 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1395 break;
1396 case 0x38 ... 0x3d:
1397 cmp: /* cmp */
05f086f8 1398 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
6aa8b732 1399 break;
33615aa9
AK		 1400 case 0x40 ... 0x47: /* inc r16/r32 */
1401 emulate_1op("inc", c->dst, ctxt->eflags);
1402 break;
1403 case 0x48 ... 0x4f: /* dec r16/r32 */
1404 emulate_1op("dec", c->dst, ctxt->eflags);
1405 break;
1406 case 0x50 ... 0x57: /* push reg */
1407 c->dst.type = OP_MEM;
1408 c->dst.bytes = c->op_bytes;
1409 c->dst.val = c->src.val;
7a957275 1410 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
33615aa9
AK		 1411 -c->op_bytes);
1412 c->dst.ptr = (void *) register_address(
7a5b56df 1413 c, ss_base(ctxt), c->regs[VCPU_REGS_RSP]);
33615aa9
AK		 1414 break;
1415 case 0x58 ... 0x5f: /* pop reg */
1416 pop_instruction:
7a5b56df 1417 if ((rc = ops->read_std(register_address(c, ss_base(ctxt),
33615aa9
AK		 1418 c->regs[VCPU_REGS_RSP]), c->dst.ptr,
1419 c->op_bytes, ctxt->vcpu)) != 0)
1420 goto done;
1421
7a957275 1422 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
33615aa9
AK		 1423 c->op_bytes);
1424 c->dst.type = OP_NONE; /* Disable writeback. */
1425 break;
6aa8b732 1426 case 0x63: /* movsxd */
8b4caf66 1427 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 1428 goto cannot_emulate;
e4e03ded 1429 c->dst.val = (s32) c->src.val;
6aa8b732 1430 break;
91ed7a0e 1431 case 0x68: /* push imm */
018a98db 1432 case 0x6a: /* push imm8 */
018a98db
AK		 1433 emulate_push(ctxt);
1434 break;
1435 case 0x6c: /* insb */
1436 case 0x6d: /* insw/insd */
1437 if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
1438 1,
1439 (c->d & ByteOp) ? 1 : c->op_bytes,
1440 c->rep_prefix ?
e4706772 1441 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1,
018a98db 1442 (ctxt->eflags & EFLG_DF),
7a5b56df 1443 register_address(c, es_base(ctxt),
018a98db
AK		 1444 c->regs[VCPU_REGS_RDI]),
1445 c->rep_prefix,
1446 c->regs[VCPU_REGS_RDX]) == 0) {
1447 c->eip = saved_eip;
1448 return -1;
1449 }
1450 return 0;
1451 case 0x6e: /* outsb */
1452 case 0x6f: /* outsw/outsd */
1453 if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
1454 0,
1455 (c->d & ByteOp) ? 1 : c->op_bytes,
1456 c->rep_prefix ?
e4706772 1457 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1,
018a98db 1458 (ctxt->eflags & EFLG_DF),
7a5b56df
AK		 1459 register_address(c,
1460 seg_override_base(ctxt, c),
018a98db
AK		 1461 c->regs[VCPU_REGS_RSI]),
1462 c->rep_prefix,
1463 c->regs[VCPU_REGS_RDX]) == 0) {
1464 c->eip = saved_eip;
1465 return -1;
1466 }
1467 return 0;
1468 case 0x70 ... 0x7f: /* jcc (short) */ {
1469 int rel = insn_fetch(s8, 1, c->eip);
1470
1471 if (test_cc(c->b, ctxt->eflags))
7a957275 1472 jmp_rel(c, rel);
018a98db
AK		 1473 break;
1474 }
6aa8b732 1475 case 0x80 ... 0x83: /* Grp1 */
e4e03ded 1476 switch (c->modrm_reg) {
6aa8b732
AK		 1477 case 0:
1478 goto add;
1479 case 1:
1480 goto or;
1481 case 2:
1482 goto adc;
1483 case 3:
1484 goto sbb;
1485 case 4:
1486 goto and;
1487 case 5:
1488 goto sub;
1489 case 6:
1490 goto xor;
1491 case 7:
1492 goto cmp;
1493 }
1494 break;
1495 case 0x84 ... 0x85:
05f086f8 1496 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1497 break;
1498 case 0x86 ... 0x87: /* xchg */
b13354f8 1499 xchg:
6aa8b732 1500 /* Write back the register source. */
e4e03ded 1501 switch (c->dst.bytes) {
6aa8b732 1502 case 1:
e4e03ded 1503 *(u8 *) c->src.ptr = (u8) c->dst.val;
6aa8b732
AK		 1504 break;
1505 case 2:
e4e03ded 1506 *(u16 *) c->src.ptr = (u16) c->dst.val;
6aa8b732
AK		 1507 break;
1508 case 4:
e4e03ded 1509 *c->src.ptr = (u32) c->dst.val;
6aa8b732
AK		 1510 break; /* 64b reg: zero-extend */
1511 case 8:
e4e03ded 1512 *c->src.ptr = c->dst.val;
6aa8b732
AK		 1513 break;
1514 }
1515 /*
1516 * Write back the memory destination with implicit LOCK
1517 * prefix.
1518 */
e4e03ded
LV		 1519 c->dst.val = c->src.val;
1520 c->lock_prefix = 1;
6aa8b732 1521 break;
6aa8b732 1522 case 0x88 ... 0x8b: /* mov */
7de75248 1523 goto mov;
38d5bc6d
GT		 1524 case 0x8c: { /* mov r/m, sreg */
1525 struct kvm_segment segreg;
1526
1527 if (c->modrm_reg <= 5)
1528 kvm_get_segment(ctxt->vcpu, &segreg, c->modrm_reg);
1529 else {
1530 printk(KERN_INFO "0x8c: Invalid segreg in modrm byte 0x%02x\n",
1531 c->modrm);
1532 goto cannot_emulate;
1533 }
1534 c->dst.val = segreg.selector;
1535 break;
1536 }
7e0b54b1 1537 case 0x8d: /* lea r16/r32, m */
f9b7aab3 1538 c->dst.val = c->modrm_ea;
7e0b54b1 1539 break;
4257198a
GT		 1540 case 0x8e: { /* mov seg, r/m16 */
1541 uint16_t sel;
1542 int type_bits;
1543 int err;
1544
1545 sel = c->src.val;
1546 if (c->modrm_reg <= 5) {
1547 type_bits = (c->modrm_reg == 1) ? 9 : 1;
1548 err = kvm_load_segment_descriptor(ctxt->vcpu, sel,
1549 type_bits, c->modrm_reg);
1550 } else {
1551 printk(KERN_INFO "Invalid segreg in modrm byte 0x%02x\n",
1552 c->modrm);
1553 goto cannot_emulate;
1554 }
1555
1556 if (err < 0)
1557 goto cannot_emulate;
1558
1559 c->dst.type = OP_NONE; /* Disable writeback. */
1560 break;
1561 }
6aa8b732 1562 case 0x8f: /* pop (sole member of Grp1a) */
8cdbd2c9
LV		 1563 rc = emulate_grp1a(ctxt, ops);
1564 if (rc != 0)
6aa8b732 1565 goto done;
6aa8b732 1566 break;
b13354f8
MG		 1567 case 0x90: /* nop / xchg r8,rax */
1568 if (!(c->rex_prefix & 1)) { /* nop */
1569 c->dst.type = OP_NONE;
1570 break;
1571 }
1572 case 0x91 ... 0x97: /* xchg reg,rax */
1573 c->src.type = c->dst.type = OP_REG;
1574 c->src.bytes = c->dst.bytes = c->op_bytes;
1575 c->src.ptr = (unsigned long *) &c->regs[VCPU_REGS_RAX];
1576 c->src.val = *(c->src.ptr);
1577 goto xchg;
fd2a7608 1578 case 0x9c: /* pushf */
05f086f8 1579 c->src.val = (unsigned long) ctxt->eflags;
8cdbd2c9
LV		 1580 emulate_push(ctxt);
1581 break;
535eabcf 1582 case 0x9d: /* popf */
05f086f8 1583 c->dst.ptr = (unsigned long *) &ctxt->eflags;
535eabcf 1584 goto pop_instruction;
018a98db
AK		 1585 case 0xa0 ... 0xa1: /* mov */
1586 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
1587 c->dst.val = c->src.val;
1588 break;
1589 case 0xa2 ... 0xa3: /* mov */
1590 c->dst.val = (unsigned long)c->regs[VCPU_REGS_RAX];
1591 break;
6aa8b732 1592 case 0xa4 ... 0xa5: /* movs */
e4e03ded
LV		 1593 c->dst.type = OP_MEM;
1594 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 1595 c->dst.ptr = (unsigned long *)register_address(c,
7a5b56df 1596 es_base(ctxt),
e4e03ded 1597 c->regs[VCPU_REGS_RDI]);
e4706772 1598 if ((rc = ops->read_emulated(register_address(c,
7a5b56df 1599 seg_override_base(ctxt, c),
e4e03ded
LV		 1600 c->regs[VCPU_REGS_RSI]),
1601 &c->dst.val,
1602 c->dst.bytes, ctxt->vcpu)) != 0)
6aa8b732 1603 goto done;
7a957275 1604 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
05f086f8 1605 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1606 : c->dst.bytes);
7a957275 1607 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
05f086f8 1608 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1609 : c->dst.bytes);
6aa8b732
AK		 1610 break;
1611 case 0xa6 ... 0xa7: /* cmps */
d7e5117a
GT		 1612 c->src.type = OP_NONE; /* Disable writeback. */
1613 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 1614 c->src.ptr = (unsigned long *)register_address(c,
7a5b56df 1615 seg_override_base(ctxt, c),
d7e5117a
GT		 1616 c->regs[VCPU_REGS_RSI]);
1617 if ((rc = ops->read_emulated((unsigned long)c->src.ptr,
1618 &c->src.val,
1619 c->src.bytes,
1620 ctxt->vcpu)) != 0)
1621 goto done;
1622
1623 c->dst.type = OP_NONE; /* Disable writeback. */
1624 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 1625 c->dst.ptr = (unsigned long *)register_address(c,
7a5b56df 1626 es_base(ctxt),
d7e5117a
GT		 1627 c->regs[VCPU_REGS_RDI]);
1628 if ((rc = ops->read_emulated((unsigned long)c->dst.ptr,
1629 &c->dst.val,
1630 c->dst.bytes,
1631 ctxt->vcpu)) != 0)
1632 goto done;
1633
1634 DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.ptr, c->dst.ptr);
1635
1636 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
1637
7a957275 1638 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
d7e5117a
GT		 1639 (ctxt->eflags & EFLG_DF) ? -c->src.bytes
1640 : c->src.bytes);
7a957275 1641 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
d7e5117a
GT		 1642 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
1643 : c->dst.bytes);
1644
1645 break;
6aa8b732 1646 case 0xaa ... 0xab: /* stos */
e4e03ded
LV		 1647 c->dst.type = OP_MEM;
1648 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 1649 c->dst.ptr = (unsigned long *)register_address(c,
7a5b56df 1650 es_base(ctxt),
a7e6c88a 1651 c->regs[VCPU_REGS_RDI]);
e4e03ded 1652 c->dst.val = c->regs[VCPU_REGS_RAX];
7a957275 1653 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
05f086f8 1654 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1655 : c->dst.bytes);
6aa8b732
AK		 1656 break;
1657 case 0xac ... 0xad: /* lods */
e4e03ded
LV		 1658 c->dst.type = OP_REG;
1659 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1660 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
e4706772 1661 if ((rc = ops->read_emulated(register_address(c,
7a5b56df 1662 seg_override_base(ctxt, c),
a7e6c88a
SY		 1663 c->regs[VCPU_REGS_RSI]),
1664 &c->dst.val,
1665 c->dst.bytes,
1666 ctxt->vcpu)) != 0)
6aa8b732 1667 goto done;
7a957275 1668 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
05f086f8 1669 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1670 : c->dst.bytes);
6aa8b732
AK		 1671 break;
1672 case 0xae ... 0xaf: /* scas */
1673 DPRINTF("Urk! I don't handle SCAS.\n");
1674 goto cannot_emulate;
a5e2e82b 1675 case 0xb0 ... 0xbf: /* mov r, imm */
615ac125 1676 goto mov;
018a98db
AK		 1677 case 0xc0 ... 0xc1:
1678 emulate_grp2(ctxt);
1679 break;
111de5d6
AK		 1680 case 0xc3: /* ret */
1681 c->dst.ptr = &c->eip;
1682 goto pop_instruction;
018a98db
AK		 1683 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
1684 mov:
1685 c->dst.val = c->src.val;
1686 break;
1687 case 0xd0 ... 0xd1: /* Grp2 */
1688 c->src.val = 1;
1689 emulate_grp2(ctxt);
1690 break;
1691 case 0xd2 ... 0xd3: /* Grp2 */
1692 c->src.val = c->regs[VCPU_REGS_RCX];
1693 emulate_grp2(ctxt);
1694 break;
a6a3034c
MG		 1695 case 0xe4: /* inb */
1696 case 0xe5: /* in */
1697 port = insn_fetch(u8, 1, c->eip);
1698 io_dir_in = 1;
1699 goto do_io;
1700 case 0xe6: /* outb */
1701 case 0xe7: /* out */
1702 port = insn_fetch(u8, 1, c->eip);
1703 io_dir_in = 0;
1704 goto do_io;
1a52e051
NK		 1705 case 0xe8: /* call (near) */ {
1706 long int rel;
e4e03ded 1707 switch (c->op_bytes) {
1a52e051 1708 case 2:
e4e03ded 1709 rel = insn_fetch(s16, 2, c->eip);
1a52e051
NK		 1710 break;
1711 case 4:
e4e03ded 1712 rel = insn_fetch(s32, 4, c->eip);
1a52e051 1713 break;
1a52e051
NK		 1714 default:
1715 DPRINTF("Call: Invalid op_bytes\n");
1716 goto cannot_emulate;
1717 }
e4e03ded 1718 c->src.val = (unsigned long) c->eip;
7a957275 1719 jmp_rel(c, rel);
e4e03ded 1720 c->op_bytes = c->ad_bytes;
8cdbd2c9
LV		 1721 emulate_push(ctxt);
1722 break;
1a52e051
NK		 1723 }
1724 case 0xe9: /* jmp rel */
954cd36f
GT		 1725 goto jmp;
1726 case 0xea: /* jmp far */ {
1727 uint32_t eip;
1728 uint16_t sel;
1729
1730 switch (c->op_bytes) {
1731 case 2:
1732 eip = insn_fetch(u16, 2, c->eip);
1733 break;
1734 case 4:
1735 eip = insn_fetch(u32, 4, c->eip);
1736 break;
1737 default:
1738 DPRINTF("jmp far: Invalid op_bytes\n");
1739 goto cannot_emulate;
1740 }
1741 sel = insn_fetch(u16, 2, c->eip);
1742 if (kvm_load_segment_descriptor(ctxt->vcpu, sel, 9, VCPU_SREG_CS) < 0) {
1743 DPRINTF("jmp far: Failed to load CS descriptor\n");
1744 goto cannot_emulate;
1745 }
1746
1747 c->eip = eip;
1748 break;
1749 }
1750 case 0xeb:
1751 jmp: /* jmp rel short */
7a957275 1752 jmp_rel(c, c->src.val);
a01af5ec 1753 c->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 1754 break;
a6a3034c
MG		 1755 case 0xec: /* in al,dx */
1756 case 0xed: /* in (e/r)ax,dx */
1757 port = c->regs[VCPU_REGS_RDX];
1758 io_dir_in = 1;
1759 goto do_io;
1760 case 0xee: /* out al,dx */
1761 case 0xef: /* out (e/r)ax,dx */
1762 port = c->regs[VCPU_REGS_RDX];
1763 io_dir_in = 0;
1764 do_io: if (kvm_emulate_pio(ctxt->vcpu, NULL, io_dir_in,
1765 (c->d & ByteOp) ? 1 : c->op_bytes,
1766 port) != 0) {
1767 c->eip = saved_eip;
1768 goto cannot_emulate;
1769 }
1770 return 0;
111de5d6 1771 case 0xf4: /* hlt */
ad312c7c 1772 ctxt->vcpu->arch.halt_request = 1;
19fdfa0d 1773 break;
111de5d6
AK		 1774 case 0xf5: /* cmc */
1775 /* complement carry flag from eflags reg */
1776 ctxt->eflags ^= EFLG_CF;
1777 c->dst.type = OP_NONE; /* Disable writeback. */
1778 break;
018a98db
AK		 1779 case 0xf6 ... 0xf7: /* Grp3 */
1780 rc = emulate_grp3(ctxt, ops);
1781 if (rc != 0)
1782 goto done;
1783 break;
111de5d6
AK		 1784 case 0xf8: /* clc */
1785 ctxt->eflags &= ~EFLG_CF;
1786 c->dst.type = OP_NONE; /* Disable writeback. */
1787 break;
1788 case 0xfa: /* cli */
1789 ctxt->eflags &= ~X86_EFLAGS_IF;
1790 c->dst.type = OP_NONE; /* Disable writeback. */
1791 break;
1792 case 0xfb: /* sti */
1793 ctxt->eflags |= X86_EFLAGS_IF;
1794 c->dst.type = OP_NONE; /* Disable writeback. */
1795 break;
fb4616f4
MG		 1796 case 0xfc: /* cld */
1797 ctxt->eflags &= ~EFLG_DF;
1798 c->dst.type = OP_NONE; /* Disable writeback. */
1799 break;
1800 case 0xfd: /* std */
1801 ctxt->eflags |= EFLG_DF;
1802 c->dst.type = OP_NONE; /* Disable writeback. */
1803 break;
018a98db
AK		 1804 case 0xfe ... 0xff: /* Grp4/Grp5 */
1805 rc = emulate_grp45(ctxt, ops);
1806 if (rc != 0)
1807 goto done;
1808 break;
6aa8b732 1809 }
018a98db
AK		 1810
1811writeback:
1812 rc = writeback(ctxt, ops);
1813 if (rc != 0)
1814 goto done;
1815
1816 /* Commit shadow register state. */
ad312c7c 1817 memcpy(ctxt->vcpu->arch.regs, c->regs, sizeof c->regs);
5fdbf976 1818 kvm_rip_write(ctxt->vcpu, c->eip);
018a98db
AK		 1819
1820done:
1821 if (rc == X86EMUL_UNHANDLEABLE) {
1822 c->eip = saved_eip;
1823 return -1;
1824 }
1825 return 0;
6aa8b732
AK		 1826
1827twobyte_insn:
e4e03ded 1828 switch (c->b) {
6aa8b732 1829 case 0x01: /* lgdt, lidt, lmsw */
e4e03ded 1830 switch (c->modrm_reg) {
6aa8b732
AK		 1831 u16 size;
1832 unsigned long address;
1833
aca7f966 1834 case 0: /* vmcall */
e4e03ded 1835 if (c->modrm_mod != 3 || c->modrm_rm != 1)
aca7f966
AL		 1836 goto cannot_emulate;
1837
7aa81cc0
AL		 1838 rc = kvm_fix_hypercall(ctxt->vcpu);
1839 if (rc)
1840 goto done;
1841
33e3885d 1842 /* Let the processor re-execute the fixed hypercall */
5fdbf976 1843 c->eip = kvm_rip_read(ctxt->vcpu);
16286d08
AK		 1844 /* Disable writeback. */
1845 c->dst.type = OP_NONE;
aca7f966 1846 break;
6aa8b732 1847 case 2: /* lgdt */
e4e03ded
LV		 1848 rc = read_descriptor(ctxt, ops, c->src.ptr,
1849 &size, &address, c->op_bytes);
6aa8b732
AK		 1850 if (rc)
1851 goto done;
1852 realmode_lgdt(ctxt->vcpu, size, address);
16286d08
AK		 1853 /* Disable writeback. */
1854 c->dst.type = OP_NONE;
6aa8b732 1855 break;
aca7f966 1856 case 3: /* lidt/vmmcall */
e4e03ded 1857 if (c->modrm_mod == 3 && c->modrm_rm == 1) {
7aa81cc0
AL		 1858 rc = kvm_fix_hypercall(ctxt->vcpu);
1859 if (rc)
1860 goto done;
1861 kvm_emulate_hypercall(ctxt->vcpu);
aca7f966 1862 } else {
e4e03ded 1863 rc = read_descriptor(ctxt, ops, c->src.ptr,
aca7f966 1864 &size, &address,
e4e03ded 1865 c->op_bytes);
aca7f966
AL		 1866 if (rc)
1867 goto done;
1868 realmode_lidt(ctxt->vcpu, size, address);
1869 }
16286d08
AK		 1870 /* Disable writeback. */
1871 c->dst.type = OP_NONE;
6aa8b732
AK		 1872 break;
1873 case 4: /* smsw */
16286d08
AK		 1874 c->dst.bytes = 2;
1875 c->dst.val = realmode_get_cr(ctxt->vcpu, 0);
6aa8b732
AK		 1876 break;
1877 case 6: /* lmsw */
16286d08
AK		 1878 realmode_lmsw(ctxt->vcpu, (u16)c->src.val,
1879 &ctxt->eflags);
dc7457ea 1880 c->dst.type = OP_NONE;
6aa8b732
AK		 1881 break;
1882 case 7: /* invlpg*/
e8d8d7fe 1883 emulate_invlpg(ctxt->vcpu, memop);
16286d08
AK		 1884 /* Disable writeback. */
1885 c->dst.type = OP_NONE;
6aa8b732
AK		 1886 break;
1887 default:
1888 goto cannot_emulate;
1889 }
1890 break;
018a98db
AK		 1891 case 0x06:
1892 emulate_clts(ctxt->vcpu);
1893 c->dst.type = OP_NONE;
1894 break;
1895 case 0x08: /* invd */
1896 case 0x09: /* wbinvd */
1897 case 0x0d: /* GrpP (prefetch) */
1898 case 0x18: /* Grp16 (prefetch/nop) */
1899 c->dst.type = OP_NONE;
1900 break;
1901 case 0x20: /* mov cr, reg */
1902 if (c->modrm_mod != 3)
1903 goto cannot_emulate;
1904 c->regs[c->modrm_rm] =
1905 realmode_get_cr(ctxt->vcpu, c->modrm_reg);
1906 c->dst.type = OP_NONE; /* no writeback */
1907 break;
6aa8b732 1908 case 0x21: /* mov from dr to reg */
e4e03ded 1909 if (c->modrm_mod != 3)
6aa8b732 1910 goto cannot_emulate;
8cdbd2c9 1911 rc = emulator_get_dr(ctxt, c->modrm_reg, &c->regs[c->modrm_rm]);
a01af5ec
LV		 1912 if (rc)
1913 goto cannot_emulate;
1914 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 1915 break;
018a98db
AK		 1916 case 0x22: /* mov reg, cr */
1917 if (c->modrm_mod != 3)
1918 goto cannot_emulate;
1919 realmode_set_cr(ctxt->vcpu,
1920 c->modrm_reg, c->modrm_val, &ctxt->eflags);
1921 c->dst.type = OP_NONE;
1922 break;
6aa8b732 1923 case 0x23: /* mov from reg to dr */
e4e03ded 1924 if (c->modrm_mod != 3)
6aa8b732 1925 goto cannot_emulate;
e4e03ded
LV		 1926 rc = emulator_set_dr(ctxt, c->modrm_reg,
1927 c->regs[c->modrm_rm]);
a01af5ec
LV		 1928 if (rc)
1929 goto cannot_emulate;
1930 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 1931 break;
018a98db
AK		 1932 case 0x30:
1933 /* wrmsr */
1934 msr_data = (u32)c->regs[VCPU_REGS_RAX]
1935 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
1936 rc = kvm_set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data);
1937 if (rc) {
c1a5d4f9 1938 kvm_inject_gp(ctxt->vcpu, 0);
5fdbf976 1939 c->eip = kvm_rip_read(ctxt->vcpu);
018a98db
AK		 1940 }
1941 rc = X86EMUL_CONTINUE;
1942 c->dst.type = OP_NONE;
1943 break;
1944 case 0x32:
1945 /* rdmsr */
1946 rc = kvm_get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data);
1947 if (rc) {
c1a5d4f9 1948 kvm_inject_gp(ctxt->vcpu, 0);
5fdbf976 1949 c->eip = kvm_rip_read(ctxt->vcpu);
018a98db
AK		 1950 } else {
1951 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
1952 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
1953 }
1954 rc = X86EMUL_CONTINUE;
1955 c->dst.type = OP_NONE;
1956 break;
6aa8b732 1957 case 0x40 ... 0x4f: /* cmov */
e4e03ded 1958 c->dst.val = c->dst.orig_val = c->src.val;
a01af5ec
LV		 1959 if (!test_cc(c->b, ctxt->eflags))
1960 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 1961 break;
018a98db
AK		 1962 case 0x80 ... 0x8f: /* jnz rel, etc*/ {
1963 long int rel;
1964
1965 switch (c->op_bytes) {
1966 case 2:
1967 rel = insn_fetch(s16, 2, c->eip);
1968 break;
1969 case 4:
1970 rel = insn_fetch(s32, 4, c->eip);
1971 break;
1972 case 8:
1973 rel = insn_fetch(s64, 8, c->eip);
1974 break;
1975 default:
1976 DPRINTF("jnz: Invalid op_bytes\n");
1977 goto cannot_emulate;
1978 }
1979 if (test_cc(c->b, ctxt->eflags))
7a957275 1980 jmp_rel(c, rel);
018a98db
AK		 1981 c->dst.type = OP_NONE;
1982 break;
1983 }
7de75248
NK		 1984 case 0xa3:
1985 bt: /* bt */
e4f8e039 1986 c->dst.type = OP_NONE;
e4e03ded
LV		 1987 /* only subword offset */
1988 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 1989 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
7de75248
NK		 1990 break;
1991 case 0xab:
1992 bts: /* bts */
e4e03ded
LV		 1993 /* only subword offset */
1994 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 1995 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
7de75248 1996 break;
2a7c5b8b
GC		 1997 case 0xae: /* clflush */
1998 break;
6aa8b732
AK		 1999 case 0xb0 ... 0xb1: /* cmpxchg */
2000 /*
2001 * Save real source value, then compare EAX against
2002 * destination.
2003 */
e4e03ded
LV		 2004 c->src.orig_val = c->src.val;
2005 c->src.val = c->regs[VCPU_REGS_RAX];
05f086f8
LV		 2006 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
2007 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 2008 /* Success: write back to memory. */
e4e03ded 2009 c->dst.val = c->src.orig_val;
6aa8b732
AK		 2010 } else {
2011 /* Failure: write the value we saw to EAX. */
e4e03ded
LV		 2012 c->dst.type = OP_REG;
2013 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 2014 }
2015 break;
6aa8b732
AK		 2016 case 0xb3:
2017 btr: /* btr */
e4e03ded
LV		 2018 /* only subword offset */
2019 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 2020 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
6aa8b732 2021 break;
6aa8b732 2022 case 0xb6 ... 0xb7: /* movzx */
e4e03ded
LV		 2023 c->dst.bytes = c->op_bytes;
2024 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
2025 : (u16) c->src.val;
6aa8b732 2026 break;
6aa8b732 2027 case 0xba: /* Grp8 */
e4e03ded 2028 switch (c->modrm_reg & 3) {
6aa8b732
AK		 2029 case 0:
2030 goto bt;
2031 case 1:
2032 goto bts;
2033 case 2:
2034 goto btr;
2035 case 3:
2036 goto btc;
2037 }
2038 break;
7de75248
NK		 2039 case 0xbb:
2040 btc: /* btc */
e4e03ded
LV		 2041 /* only subword offset */
2042 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 2043 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
7de75248 2044 break;
6aa8b732 2045 case 0xbe ... 0xbf: /* movsx */
e4e03ded
LV		 2046 c->dst.bytes = c->op_bytes;
2047 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
2048 (s16) c->src.val;
6aa8b732 2049 break;
a012e65a 2050 case 0xc3: /* movnti */
e4e03ded
LV		 2051 c->dst.bytes = c->op_bytes;
2052 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
2053 (u64) c->src.val;
a012e65a 2054 break;
6aa8b732 2055 case 0xc7: /* Grp9 (cmpxchg8b) */
e8d8d7fe 2056 rc = emulate_grp9(ctxt, ops, memop);
8cdbd2c9
LV		 2057 if (rc != 0)
2058 goto done;
018a98db 2059 c->dst.type = OP_NONE;
8cdbd2c9 2060 break;
6aa8b732
AK		 2061 }
2062 goto writeback;
2063
2064cannot_emulate:
e4e03ded 2065 DPRINTF("Cannot emulate %02x\n", c->b);
3427318f 2066 c->eip = saved_eip;
6aa8b732
AK		 2067 return -1;
2068}
Linux kernel - Deliverables
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