Commit | Line | Data |
---|---|---|
9f4c815c IM |
1 | /* |
2 | * Copyright 2002 Andi Kleen, SuSE Labs. | |
1da177e4 | 3 | * Thanks to Ben LaHaise for precious feedback. |
9f4c815c | 4 | */ |
1da177e4 | 5 | #include <linux/highmem.h> |
8192206d | 6 | #include <linux/bootmem.h> |
1da177e4 | 7 | #include <linux/module.h> |
9f4c815c | 8 | #include <linux/sched.h> |
1da177e4 | 9 | #include <linux/slab.h> |
9f4c815c | 10 | #include <linux/mm.h> |
76ebd054 | 11 | #include <linux/interrupt.h> |
ee7ae7a1 TG |
12 | #include <linux/seq_file.h> |
13 | #include <linux/debugfs.h> | |
9f4c815c | 14 | |
950f9d95 | 15 | #include <asm/e820.h> |
1da177e4 LT |
16 | #include <asm/processor.h> |
17 | #include <asm/tlbflush.h> | |
f8af095d | 18 | #include <asm/sections.h> |
9f4c815c IM |
19 | #include <asm/uaccess.h> |
20 | #include <asm/pgalloc.h> | |
c31c7d48 | 21 | #include <asm/proto.h> |
1219333d | 22 | #include <asm/pat.h> |
1da177e4 | 23 | |
9df84993 IM |
24 | /* |
25 | * The current flushing context - we pass it instead of 5 arguments: | |
26 | */ | |
72e458df | 27 | struct cpa_data { |
d75586ad | 28 | unsigned long *vaddr; |
72e458df TG |
29 | pgprot_t mask_set; |
30 | pgprot_t mask_clr; | |
65e074df | 31 | int numpages; |
d75586ad | 32 | int flags; |
c31c7d48 | 33 | unsigned long pfn; |
c9caa02c | 34 | unsigned force_split : 1; |
d75586ad | 35 | int curpage; |
72e458df TG |
36 | }; |
37 | ||
ad5ca55f SS |
38 | /* |
39 | * Serialize cpa() (for !DEBUG_PAGEALLOC which uses large identity mappings) | |
40 | * using cpa_lock. So that we don't allow any other cpu, with stale large tlb | |
41 | * entries change the page attribute in parallel to some other cpu | |
42 | * splitting a large page entry along with changing the attribute. | |
43 | */ | |
44 | static DEFINE_SPINLOCK(cpa_lock); | |
45 | ||
d75586ad SL |
46 | #define CPA_FLUSHTLB 1 |
47 | #define CPA_ARRAY 2 | |
48 | ||
65280e61 | 49 | #ifdef CONFIG_PROC_FS |
ce0c0e50 AK |
50 | static unsigned long direct_pages_count[PG_LEVEL_NUM]; |
51 | ||
65280e61 | 52 | void update_page_count(int level, unsigned long pages) |
ce0c0e50 | 53 | { |
ce0c0e50 | 54 | unsigned long flags; |
65280e61 | 55 | |
ce0c0e50 AK |
56 | /* Protect against CPA */ |
57 | spin_lock_irqsave(&pgd_lock, flags); | |
58 | direct_pages_count[level] += pages; | |
59 | spin_unlock_irqrestore(&pgd_lock, flags); | |
65280e61 TG |
60 | } |
61 | ||
62 | static void split_page_count(int level) | |
63 | { | |
64 | direct_pages_count[level]--; | |
65 | direct_pages_count[level - 1] += PTRS_PER_PTE; | |
66 | } | |
67 | ||
68 | int arch_report_meminfo(char *page) | |
69 | { | |
a06de630 HD |
70 | int n = sprintf(page, "DirectMap4k: %8lu kB\n", |
71 | direct_pages_count[PG_LEVEL_4K] << 2); | |
72 | #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE) | |
73 | n += sprintf(page + n, "DirectMap2M: %8lu kB\n", | |
74 | direct_pages_count[PG_LEVEL_2M] << 11); | |
75 | #else | |
76 | n += sprintf(page + n, "DirectMap4M: %8lu kB\n", | |
77 | direct_pages_count[PG_LEVEL_2M] << 12); | |
78 | #endif | |
65280e61 | 79 | #ifdef CONFIG_X86_64 |
a06de630 HD |
80 | if (direct_gbpages) |
81 | n += sprintf(page + n, "DirectMap1G: %8lu kB\n", | |
82 | direct_pages_count[PG_LEVEL_1G] << 20); | |
ce0c0e50 | 83 | #endif |
65280e61 | 84 | return n; |
ce0c0e50 | 85 | } |
65280e61 TG |
86 | #else |
87 | static inline void split_page_count(int level) { } | |
88 | #endif | |
ce0c0e50 | 89 | |
c31c7d48 TG |
90 | #ifdef CONFIG_X86_64 |
91 | ||
92 | static inline unsigned long highmap_start_pfn(void) | |
93 | { | |
94 | return __pa(_text) >> PAGE_SHIFT; | |
95 | } | |
96 | ||
97 | static inline unsigned long highmap_end_pfn(void) | |
98 | { | |
15ae2d76 | 99 | return __pa(roundup((unsigned long)_end, PMD_SIZE)) >> PAGE_SHIFT; |
c31c7d48 TG |
100 | } |
101 | ||
102 | #endif | |
103 | ||
92cb54a3 IM |
104 | #ifdef CONFIG_DEBUG_PAGEALLOC |
105 | # define debug_pagealloc 1 | |
106 | #else | |
107 | # define debug_pagealloc 0 | |
108 | #endif | |
109 | ||
ed724be6 AV |
110 | static inline int |
111 | within(unsigned long addr, unsigned long start, unsigned long end) | |
687c4825 | 112 | { |
ed724be6 AV |
113 | return addr >= start && addr < end; |
114 | } | |
115 | ||
d7c8f21a TG |
116 | /* |
117 | * Flushing functions | |
118 | */ | |
cd8ddf1a | 119 | |
cd8ddf1a TG |
120 | /** |
121 | * clflush_cache_range - flush a cache range with clflush | |
122 | * @addr: virtual start address | |
123 | * @size: number of bytes to flush | |
124 | * | |
125 | * clflush is an unordered instruction which needs fencing with mfence | |
126 | * to avoid ordering issues. | |
127 | */ | |
4c61afcd | 128 | void clflush_cache_range(void *vaddr, unsigned int size) |
d7c8f21a | 129 | { |
4c61afcd | 130 | void *vend = vaddr + size - 1; |
d7c8f21a | 131 | |
cd8ddf1a | 132 | mb(); |
4c61afcd IM |
133 | |
134 | for (; vaddr < vend; vaddr += boot_cpu_data.x86_clflush_size) | |
135 | clflush(vaddr); | |
136 | /* | |
137 | * Flush any possible final partial cacheline: | |
138 | */ | |
139 | clflush(vend); | |
140 | ||
cd8ddf1a | 141 | mb(); |
d7c8f21a TG |
142 | } |
143 | ||
af1e6844 | 144 | static void __cpa_flush_all(void *arg) |
d7c8f21a | 145 | { |
6bb8383b AK |
146 | unsigned long cache = (unsigned long)arg; |
147 | ||
d7c8f21a TG |
148 | /* |
149 | * Flush all to work around Errata in early athlons regarding | |
150 | * large page flushing. | |
151 | */ | |
152 | __flush_tlb_all(); | |
153 | ||
6bb8383b | 154 | if (cache && boot_cpu_data.x86_model >= 4) |
d7c8f21a TG |
155 | wbinvd(); |
156 | } | |
157 | ||
6bb8383b | 158 | static void cpa_flush_all(unsigned long cache) |
d7c8f21a TG |
159 | { |
160 | BUG_ON(irqs_disabled()); | |
161 | ||
15c8b6c1 | 162 | on_each_cpu(__cpa_flush_all, (void *) cache, 1); |
d7c8f21a TG |
163 | } |
164 | ||
57a6a46a TG |
165 | static void __cpa_flush_range(void *arg) |
166 | { | |
57a6a46a TG |
167 | /* |
168 | * We could optimize that further and do individual per page | |
169 | * tlb invalidates for a low number of pages. Caveat: we must | |
170 | * flush the high aliases on 64bit as well. | |
171 | */ | |
172 | __flush_tlb_all(); | |
57a6a46a TG |
173 | } |
174 | ||
6bb8383b | 175 | static void cpa_flush_range(unsigned long start, int numpages, int cache) |
57a6a46a | 176 | { |
4c61afcd IM |
177 | unsigned int i, level; |
178 | unsigned long addr; | |
179 | ||
57a6a46a | 180 | BUG_ON(irqs_disabled()); |
4c61afcd | 181 | WARN_ON(PAGE_ALIGN(start) != start); |
57a6a46a | 182 | |
15c8b6c1 | 183 | on_each_cpu(__cpa_flush_range, NULL, 1); |
57a6a46a | 184 | |
6bb8383b AK |
185 | if (!cache) |
186 | return; | |
187 | ||
3b233e52 TG |
188 | /* |
189 | * We only need to flush on one CPU, | |
190 | * clflush is a MESI-coherent instruction that | |
191 | * will cause all other CPUs to flush the same | |
192 | * cachelines: | |
193 | */ | |
4c61afcd IM |
194 | for (i = 0, addr = start; i < numpages; i++, addr += PAGE_SIZE) { |
195 | pte_t *pte = lookup_address(addr, &level); | |
196 | ||
197 | /* | |
198 | * Only flush present addresses: | |
199 | */ | |
7bfb72e8 | 200 | if (pte && (pte_val(*pte) & _PAGE_PRESENT)) |
4c61afcd IM |
201 | clflush_cache_range((void *) addr, PAGE_SIZE); |
202 | } | |
57a6a46a TG |
203 | } |
204 | ||
d75586ad SL |
205 | static void cpa_flush_array(unsigned long *start, int numpages, int cache) |
206 | { | |
207 | unsigned int i, level; | |
208 | unsigned long *addr; | |
209 | ||
210 | BUG_ON(irqs_disabled()); | |
211 | ||
212 | on_each_cpu(__cpa_flush_range, NULL, 1); | |
213 | ||
214 | if (!cache) | |
215 | return; | |
216 | ||
217 | /* 4M threshold */ | |
218 | if (numpages >= 1024) { | |
219 | if (boot_cpu_data.x86_model >= 4) | |
220 | wbinvd(); | |
221 | return; | |
222 | } | |
223 | /* | |
224 | * We only need to flush on one CPU, | |
225 | * clflush is a MESI-coherent instruction that | |
226 | * will cause all other CPUs to flush the same | |
227 | * cachelines: | |
228 | */ | |
229 | for (i = 0, addr = start; i < numpages; i++, addr++) { | |
230 | pte_t *pte = lookup_address(*addr, &level); | |
231 | ||
232 | /* | |
233 | * Only flush present addresses: | |
234 | */ | |
235 | if (pte && (pte_val(*pte) & _PAGE_PRESENT)) | |
236 | clflush_cache_range((void *) *addr, PAGE_SIZE); | |
237 | } | |
238 | } | |
239 | ||
ed724be6 AV |
240 | /* |
241 | * Certain areas of memory on x86 require very specific protection flags, | |
242 | * for example the BIOS area or kernel text. Callers don't always get this | |
243 | * right (again, ioremap() on BIOS memory is not uncommon) so this function | |
244 | * checks and fixes these known static required protection bits. | |
245 | */ | |
c31c7d48 TG |
246 | static inline pgprot_t static_protections(pgprot_t prot, unsigned long address, |
247 | unsigned long pfn) | |
ed724be6 AV |
248 | { |
249 | pgprot_t forbidden = __pgprot(0); | |
250 | ||
687c4825 | 251 | /* |
ed724be6 AV |
252 | * The BIOS area between 640k and 1Mb needs to be executable for |
253 | * PCI BIOS based config access (CONFIG_PCI_GOBIOS) support. | |
687c4825 | 254 | */ |
c31c7d48 | 255 | if (within(pfn, BIOS_BEGIN >> PAGE_SHIFT, BIOS_END >> PAGE_SHIFT)) |
ed724be6 AV |
256 | pgprot_val(forbidden) |= _PAGE_NX; |
257 | ||
258 | /* | |
259 | * The kernel text needs to be executable for obvious reasons | |
c31c7d48 TG |
260 | * Does not cover __inittext since that is gone later on. On |
261 | * 64bit we do not enforce !NX on the low mapping | |
ed724be6 AV |
262 | */ |
263 | if (within(address, (unsigned long)_text, (unsigned long)_etext)) | |
264 | pgprot_val(forbidden) |= _PAGE_NX; | |
cc0f21bb | 265 | |
cc0f21bb | 266 | /* |
c31c7d48 TG |
267 | * The .rodata section needs to be read-only. Using the pfn |
268 | * catches all aliases. | |
cc0f21bb | 269 | */ |
c31c7d48 TG |
270 | if (within(pfn, __pa((unsigned long)__start_rodata) >> PAGE_SHIFT, |
271 | __pa((unsigned long)__end_rodata) >> PAGE_SHIFT)) | |
cc0f21bb | 272 | pgprot_val(forbidden) |= _PAGE_RW; |
ed724be6 AV |
273 | |
274 | prot = __pgprot(pgprot_val(prot) & ~pgprot_val(forbidden)); | |
687c4825 IM |
275 | |
276 | return prot; | |
277 | } | |
278 | ||
9a14aefc TG |
279 | /* |
280 | * Lookup the page table entry for a virtual address. Return a pointer | |
281 | * to the entry and the level of the mapping. | |
282 | * | |
283 | * Note: We return pud and pmd either when the entry is marked large | |
284 | * or when the present bit is not set. Otherwise we would return a | |
285 | * pointer to a nonexisting mapping. | |
286 | */ | |
da7bfc50 | 287 | pte_t *lookup_address(unsigned long address, unsigned int *level) |
9f4c815c | 288 | { |
1da177e4 LT |
289 | pgd_t *pgd = pgd_offset_k(address); |
290 | pud_t *pud; | |
291 | pmd_t *pmd; | |
9f4c815c | 292 | |
30551bb3 TG |
293 | *level = PG_LEVEL_NONE; |
294 | ||
1da177e4 LT |
295 | if (pgd_none(*pgd)) |
296 | return NULL; | |
9df84993 | 297 | |
1da177e4 LT |
298 | pud = pud_offset(pgd, address); |
299 | if (pud_none(*pud)) | |
300 | return NULL; | |
c2f71ee2 AK |
301 | |
302 | *level = PG_LEVEL_1G; | |
303 | if (pud_large(*pud) || !pud_present(*pud)) | |
304 | return (pte_t *)pud; | |
305 | ||
1da177e4 LT |
306 | pmd = pmd_offset(pud, address); |
307 | if (pmd_none(*pmd)) | |
308 | return NULL; | |
30551bb3 TG |
309 | |
310 | *level = PG_LEVEL_2M; | |
9a14aefc | 311 | if (pmd_large(*pmd) || !pmd_present(*pmd)) |
1da177e4 | 312 | return (pte_t *)pmd; |
1da177e4 | 313 | |
30551bb3 | 314 | *level = PG_LEVEL_4K; |
9df84993 | 315 | |
9f4c815c IM |
316 | return pte_offset_kernel(pmd, address); |
317 | } | |
75bb8835 | 318 | EXPORT_SYMBOL_GPL(lookup_address); |
9f4c815c | 319 | |
9df84993 IM |
320 | /* |
321 | * Set the new pmd in all the pgds we know about: | |
322 | */ | |
9a3dc780 | 323 | static void __set_pmd_pte(pte_t *kpte, unsigned long address, pte_t pte) |
9f4c815c | 324 | { |
9f4c815c IM |
325 | /* change init_mm */ |
326 | set_pte_atomic(kpte, pte); | |
44af6c41 | 327 | #ifdef CONFIG_X86_32 |
e4b71dcf | 328 | if (!SHARED_KERNEL_PMD) { |
44af6c41 IM |
329 | struct page *page; |
330 | ||
e3ed910d | 331 | list_for_each_entry(page, &pgd_list, lru) { |
44af6c41 IM |
332 | pgd_t *pgd; |
333 | pud_t *pud; | |
334 | pmd_t *pmd; | |
335 | ||
336 | pgd = (pgd_t *)page_address(page) + pgd_index(address); | |
337 | pud = pud_offset(pgd, address); | |
338 | pmd = pmd_offset(pud, address); | |
339 | set_pte_atomic((pte_t *)pmd, pte); | |
340 | } | |
1da177e4 | 341 | } |
44af6c41 | 342 | #endif |
1da177e4 LT |
343 | } |
344 | ||
9df84993 IM |
345 | static int |
346 | try_preserve_large_page(pte_t *kpte, unsigned long address, | |
347 | struct cpa_data *cpa) | |
65e074df | 348 | { |
c31c7d48 | 349 | unsigned long nextpage_addr, numpages, pmask, psize, flags, addr, pfn; |
65e074df TG |
350 | pte_t new_pte, old_pte, *tmp; |
351 | pgprot_t old_prot, new_prot; | |
fac84939 | 352 | int i, do_split = 1; |
da7bfc50 | 353 | unsigned int level; |
65e074df | 354 | |
c9caa02c AK |
355 | if (cpa->force_split) |
356 | return 1; | |
357 | ||
65e074df TG |
358 | spin_lock_irqsave(&pgd_lock, flags); |
359 | /* | |
360 | * Check for races, another CPU might have split this page | |
361 | * up already: | |
362 | */ | |
363 | tmp = lookup_address(address, &level); | |
364 | if (tmp != kpte) | |
365 | goto out_unlock; | |
366 | ||
367 | switch (level) { | |
368 | case PG_LEVEL_2M: | |
31422c51 AK |
369 | psize = PMD_PAGE_SIZE; |
370 | pmask = PMD_PAGE_MASK; | |
65e074df | 371 | break; |
f07333fd | 372 | #ifdef CONFIG_X86_64 |
65e074df | 373 | case PG_LEVEL_1G: |
5d3c8b21 AK |
374 | psize = PUD_PAGE_SIZE; |
375 | pmask = PUD_PAGE_MASK; | |
f07333fd AK |
376 | break; |
377 | #endif | |
65e074df | 378 | default: |
beaff633 | 379 | do_split = -EINVAL; |
65e074df TG |
380 | goto out_unlock; |
381 | } | |
382 | ||
383 | /* | |
384 | * Calculate the number of pages, which fit into this large | |
385 | * page starting at address: | |
386 | */ | |
387 | nextpage_addr = (address + psize) & pmask; | |
388 | numpages = (nextpage_addr - address) >> PAGE_SHIFT; | |
9b5cf48b RW |
389 | if (numpages < cpa->numpages) |
390 | cpa->numpages = numpages; | |
65e074df TG |
391 | |
392 | /* | |
393 | * We are safe now. Check whether the new pgprot is the same: | |
394 | */ | |
395 | old_pte = *kpte; | |
396 | old_prot = new_prot = pte_pgprot(old_pte); | |
397 | ||
398 | pgprot_val(new_prot) &= ~pgprot_val(cpa->mask_clr); | |
399 | pgprot_val(new_prot) |= pgprot_val(cpa->mask_set); | |
c31c7d48 TG |
400 | |
401 | /* | |
402 | * old_pte points to the large page base address. So we need | |
403 | * to add the offset of the virtual address: | |
404 | */ | |
405 | pfn = pte_pfn(old_pte) + ((address & (psize - 1)) >> PAGE_SHIFT); | |
406 | cpa->pfn = pfn; | |
407 | ||
408 | new_prot = static_protections(new_prot, address, pfn); | |
65e074df | 409 | |
fac84939 TG |
410 | /* |
411 | * We need to check the full range, whether | |
412 | * static_protection() requires a different pgprot for one of | |
413 | * the pages in the range we try to preserve: | |
414 | */ | |
415 | addr = address + PAGE_SIZE; | |
c31c7d48 | 416 | pfn++; |
9b5cf48b | 417 | for (i = 1; i < cpa->numpages; i++, addr += PAGE_SIZE, pfn++) { |
c31c7d48 | 418 | pgprot_t chk_prot = static_protections(new_prot, addr, pfn); |
fac84939 TG |
419 | |
420 | if (pgprot_val(chk_prot) != pgprot_val(new_prot)) | |
421 | goto out_unlock; | |
422 | } | |
423 | ||
65e074df TG |
424 | /* |
425 | * If there are no changes, return. maxpages has been updated | |
426 | * above: | |
427 | */ | |
428 | if (pgprot_val(new_prot) == pgprot_val(old_prot)) { | |
beaff633 | 429 | do_split = 0; |
65e074df TG |
430 | goto out_unlock; |
431 | } | |
432 | ||
433 | /* | |
434 | * We need to change the attributes. Check, whether we can | |
435 | * change the large page in one go. We request a split, when | |
436 | * the address is not aligned and the number of pages is | |
437 | * smaller than the number of pages in the large page. Note | |
438 | * that we limited the number of possible pages already to | |
439 | * the number of pages in the large page. | |
440 | */ | |
9b5cf48b | 441 | if (address == (nextpage_addr - psize) && cpa->numpages == numpages) { |
65e074df TG |
442 | /* |
443 | * The address is aligned and the number of pages | |
444 | * covers the full page. | |
445 | */ | |
446 | new_pte = pfn_pte(pte_pfn(old_pte), canon_pgprot(new_prot)); | |
447 | __set_pmd_pte(kpte, address, new_pte); | |
d75586ad | 448 | cpa->flags |= CPA_FLUSHTLB; |
beaff633 | 449 | do_split = 0; |
65e074df TG |
450 | } |
451 | ||
452 | out_unlock: | |
453 | spin_unlock_irqrestore(&pgd_lock, flags); | |
9df84993 | 454 | |
beaff633 | 455 | return do_split; |
65e074df TG |
456 | } |
457 | ||
7afe15b9 | 458 | static int split_large_page(pte_t *kpte, unsigned long address) |
bb5c2dbd | 459 | { |
7b610eec | 460 | unsigned long flags, pfn, pfninc = 1; |
9df84993 | 461 | unsigned int i, level; |
bb5c2dbd | 462 | pte_t *pbase, *tmp; |
9df84993 | 463 | pgprot_t ref_prot; |
ad5ca55f SS |
464 | struct page *base; |
465 | ||
466 | if (!debug_pagealloc) | |
467 | spin_unlock(&cpa_lock); | |
468 | base = alloc_pages(GFP_KERNEL, 0); | |
469 | if (!debug_pagealloc) | |
470 | spin_lock(&cpa_lock); | |
8311eb84 SS |
471 | if (!base) |
472 | return -ENOMEM; | |
bb5c2dbd | 473 | |
eb5b5f02 | 474 | spin_lock_irqsave(&pgd_lock, flags); |
bb5c2dbd IM |
475 | /* |
476 | * Check for races, another CPU might have split this page | |
477 | * up for us already: | |
478 | */ | |
479 | tmp = lookup_address(address, &level); | |
6ce9fc17 | 480 | if (tmp != kpte) |
bb5c2dbd IM |
481 | goto out_unlock; |
482 | ||
bb5c2dbd | 483 | pbase = (pte_t *)page_address(base); |
6944a9c8 | 484 | paravirt_alloc_pte(&init_mm, page_to_pfn(base)); |
07cf89c0 | 485 | ref_prot = pte_pgprot(pte_clrhuge(*kpte)); |
bb5c2dbd | 486 | |
f07333fd AK |
487 | #ifdef CONFIG_X86_64 |
488 | if (level == PG_LEVEL_1G) { | |
489 | pfninc = PMD_PAGE_SIZE >> PAGE_SHIFT; | |
490 | pgprot_val(ref_prot) |= _PAGE_PSE; | |
f07333fd AK |
491 | } |
492 | #endif | |
493 | ||
63c1dcf4 TG |
494 | /* |
495 | * Get the target pfn from the original entry: | |
496 | */ | |
497 | pfn = pte_pfn(*kpte); | |
f07333fd | 498 | for (i = 0; i < PTRS_PER_PTE; i++, pfn += pfninc) |
63c1dcf4 | 499 | set_pte(&pbase[i], pfn_pte(pfn, ref_prot)); |
bb5c2dbd | 500 | |
ce0c0e50 | 501 | if (address >= (unsigned long)__va(0) && |
f361a450 YL |
502 | address < (unsigned long)__va(max_low_pfn_mapped << PAGE_SHIFT)) |
503 | split_page_count(level); | |
504 | ||
505 | #ifdef CONFIG_X86_64 | |
506 | if (address >= (unsigned long)__va(1UL<<32) && | |
65280e61 TG |
507 | address < (unsigned long)__va(max_pfn_mapped << PAGE_SHIFT)) |
508 | split_page_count(level); | |
f361a450 | 509 | #endif |
ce0c0e50 | 510 | |
bb5c2dbd | 511 | /* |
07cf89c0 | 512 | * Install the new, split up pagetable. Important details here: |
4c881ca1 HY |
513 | * |
514 | * On Intel the NX bit of all levels must be cleared to make a | |
515 | * page executable. See section 4.13.2 of Intel 64 and IA-32 | |
516 | * Architectures Software Developer's Manual). | |
07cf89c0 TG |
517 | * |
518 | * Mark the entry present. The current mapping might be | |
519 | * set to not present, which we preserved above. | |
bb5c2dbd | 520 | */ |
4c881ca1 | 521 | ref_prot = pte_pgprot(pte_mkexec(pte_clrhuge(*kpte))); |
07cf89c0 | 522 | pgprot_val(ref_prot) |= _PAGE_PRESENT; |
9a3dc780 | 523 | __set_pmd_pte(kpte, address, mk_pte(base, ref_prot)); |
bb5c2dbd IM |
524 | base = NULL; |
525 | ||
526 | out_unlock: | |
eb5b5f02 TG |
527 | /* |
528 | * If we dropped out via the lookup_address check under | |
529 | * pgd_lock then stick the page back into the pool: | |
530 | */ | |
8311eb84 SS |
531 | if (base) |
532 | __free_page(base); | |
9a3dc780 | 533 | spin_unlock_irqrestore(&pgd_lock, flags); |
bb5c2dbd | 534 | |
bb5c2dbd IM |
535 | return 0; |
536 | } | |
537 | ||
c31c7d48 | 538 | static int __change_page_attr(struct cpa_data *cpa, int primary) |
9f4c815c | 539 | { |
d75586ad | 540 | unsigned long address; |
da7bfc50 HH |
541 | int do_split, err; |
542 | unsigned int level; | |
c31c7d48 | 543 | pte_t *kpte, old_pte; |
1da177e4 | 544 | |
d75586ad SL |
545 | if (cpa->flags & CPA_ARRAY) |
546 | address = cpa->vaddr[cpa->curpage]; | |
547 | else | |
548 | address = *cpa->vaddr; | |
549 | ||
97f99fed | 550 | repeat: |
f0646e43 | 551 | kpte = lookup_address(address, &level); |
1da177e4 | 552 | if (!kpte) |
d1a4be63 | 553 | return 0; |
c31c7d48 TG |
554 | |
555 | old_pte = *kpte; | |
556 | if (!pte_val(old_pte)) { | |
557 | if (!primary) | |
558 | return 0; | |
875e40b9 | 559 | WARN(1, KERN_WARNING "CPA: called for zero pte. " |
c31c7d48 | 560 | "vaddr = %lx cpa->vaddr = %lx\n", address, |
d75586ad | 561 | *cpa->vaddr); |
1da177e4 | 562 | return -EINVAL; |
c31c7d48 | 563 | } |
9f4c815c | 564 | |
30551bb3 | 565 | if (level == PG_LEVEL_4K) { |
c31c7d48 | 566 | pte_t new_pte; |
626c2c9d | 567 | pgprot_t new_prot = pte_pgprot(old_pte); |
c31c7d48 | 568 | unsigned long pfn = pte_pfn(old_pte); |
86f03989 | 569 | |
72e458df TG |
570 | pgprot_val(new_prot) &= ~pgprot_val(cpa->mask_clr); |
571 | pgprot_val(new_prot) |= pgprot_val(cpa->mask_set); | |
86f03989 | 572 | |
c31c7d48 | 573 | new_prot = static_protections(new_prot, address, pfn); |
86f03989 | 574 | |
626c2c9d AV |
575 | /* |
576 | * We need to keep the pfn from the existing PTE, | |
577 | * after all we're only going to change it's attributes | |
578 | * not the memory it points to | |
579 | */ | |
c31c7d48 TG |
580 | new_pte = pfn_pte(pfn, canon_pgprot(new_prot)); |
581 | cpa->pfn = pfn; | |
f4ae5da0 TG |
582 | /* |
583 | * Do we really change anything ? | |
584 | */ | |
585 | if (pte_val(old_pte) != pte_val(new_pte)) { | |
586 | set_pte_atomic(kpte, new_pte); | |
d75586ad | 587 | cpa->flags |= CPA_FLUSHTLB; |
f4ae5da0 | 588 | } |
9b5cf48b | 589 | cpa->numpages = 1; |
65e074df | 590 | return 0; |
1da177e4 | 591 | } |
65e074df TG |
592 | |
593 | /* | |
594 | * Check, whether we can keep the large page intact | |
595 | * and just change the pte: | |
596 | */ | |
beaff633 | 597 | do_split = try_preserve_large_page(kpte, address, cpa); |
65e074df TG |
598 | /* |
599 | * When the range fits into the existing large page, | |
9b5cf48b | 600 | * return. cp->numpages and cpa->tlbflush have been updated in |
65e074df TG |
601 | * try_large_page: |
602 | */ | |
87f7f8fe IM |
603 | if (do_split <= 0) |
604 | return do_split; | |
65e074df TG |
605 | |
606 | /* | |
607 | * We have to split the large page: | |
608 | */ | |
87f7f8fe IM |
609 | err = split_large_page(kpte, address); |
610 | if (!err) { | |
ad5ca55f SS |
611 | /* |
612 | * Do a global flush tlb after splitting the large page | |
613 | * and before we do the actual change page attribute in the PTE. | |
614 | * | |
615 | * With out this, we violate the TLB application note, that says | |
616 | * "The TLBs may contain both ordinary and large-page | |
617 | * translations for a 4-KByte range of linear addresses. This | |
618 | * may occur if software modifies the paging structures so that | |
619 | * the page size used for the address range changes. If the two | |
620 | * translations differ with respect to page frame or attributes | |
621 | * (e.g., permissions), processor behavior is undefined and may | |
622 | * be implementation-specific." | |
623 | * | |
624 | * We do this global tlb flush inside the cpa_lock, so that we | |
625 | * don't allow any other cpu, with stale tlb entries change the | |
626 | * page attribute in parallel, that also falls into the | |
627 | * just split large page entry. | |
628 | */ | |
629 | flush_tlb_all(); | |
87f7f8fe IM |
630 | goto repeat; |
631 | } | |
beaff633 | 632 | |
87f7f8fe | 633 | return err; |
9f4c815c | 634 | } |
1da177e4 | 635 | |
c31c7d48 TG |
636 | static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias); |
637 | ||
638 | static int cpa_process_alias(struct cpa_data *cpa) | |
1da177e4 | 639 | { |
c31c7d48 | 640 | struct cpa_data alias_cpa; |
f34b439f | 641 | int ret = 0; |
d75586ad | 642 | unsigned long temp_cpa_vaddr, vaddr; |
44af6c41 | 643 | |
965194c1 | 644 | if (cpa->pfn >= max_pfn_mapped) |
c31c7d48 | 645 | return 0; |
626c2c9d | 646 | |
f361a450 | 647 | #ifdef CONFIG_X86_64 |
965194c1 | 648 | if (cpa->pfn >= max_low_pfn_mapped && cpa->pfn < (1UL<<(32-PAGE_SHIFT))) |
f361a450 YL |
649 | return 0; |
650 | #endif | |
f34b439f TG |
651 | /* |
652 | * No need to redo, when the primary call touched the direct | |
653 | * mapping already: | |
654 | */ | |
d75586ad SL |
655 | if (cpa->flags & CPA_ARRAY) |
656 | vaddr = cpa->vaddr[cpa->curpage]; | |
657 | else | |
658 | vaddr = *cpa->vaddr; | |
659 | ||
660 | if (!(within(vaddr, PAGE_OFFSET, | |
f361a450 YL |
661 | PAGE_OFFSET + (max_low_pfn_mapped << PAGE_SHIFT)) |
662 | #ifdef CONFIG_X86_64 | |
d75586ad | 663 | || within(vaddr, PAGE_OFFSET + (1UL<<32), |
f361a450 YL |
664 | PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT)) |
665 | #endif | |
666 | )) { | |
44af6c41 | 667 | |
f34b439f | 668 | alias_cpa = *cpa; |
d75586ad SL |
669 | temp_cpa_vaddr = (unsigned long) __va(cpa->pfn << PAGE_SHIFT); |
670 | alias_cpa.vaddr = &temp_cpa_vaddr; | |
671 | alias_cpa.flags &= ~CPA_ARRAY; | |
672 | ||
f34b439f TG |
673 | |
674 | ret = __change_page_attr_set_clr(&alias_cpa, 0); | |
675 | } | |
44af6c41 | 676 | |
44af6c41 | 677 | #ifdef CONFIG_X86_64 |
c31c7d48 TG |
678 | if (ret) |
679 | return ret; | |
f34b439f TG |
680 | /* |
681 | * No need to redo, when the primary call touched the high | |
682 | * mapping already: | |
683 | */ | |
d75586ad | 684 | if (within(vaddr, (unsigned long) _text, (unsigned long) _end)) |
f34b439f TG |
685 | return 0; |
686 | ||
488fd995 | 687 | /* |
0879750f TG |
688 | * If the physical address is inside the kernel map, we need |
689 | * to touch the high mapped kernel as well: | |
488fd995 | 690 | */ |
c31c7d48 TG |
691 | if (!within(cpa->pfn, highmap_start_pfn(), highmap_end_pfn())) |
692 | return 0; | |
0879750f | 693 | |
c31c7d48 | 694 | alias_cpa = *cpa; |
d75586ad SL |
695 | temp_cpa_vaddr = (cpa->pfn << PAGE_SHIFT) + __START_KERNEL_map - phys_base; |
696 | alias_cpa.vaddr = &temp_cpa_vaddr; | |
697 | alias_cpa.flags &= ~CPA_ARRAY; | |
c31c7d48 TG |
698 | |
699 | /* | |
700 | * The high mapping range is imprecise, so ignore the return value. | |
701 | */ | |
702 | __change_page_attr_set_clr(&alias_cpa, 0); | |
488fd995 | 703 | #endif |
c31c7d48 | 704 | return ret; |
1da177e4 LT |
705 | } |
706 | ||
c31c7d48 | 707 | static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias) |
ff31452b | 708 | { |
65e074df | 709 | int ret, numpages = cpa->numpages; |
ff31452b | 710 | |
65e074df TG |
711 | while (numpages) { |
712 | /* | |
713 | * Store the remaining nr of pages for the large page | |
714 | * preservation check. | |
715 | */ | |
9b5cf48b | 716 | cpa->numpages = numpages; |
d75586ad SL |
717 | /* for array changes, we can't use large page */ |
718 | if (cpa->flags & CPA_ARRAY) | |
719 | cpa->numpages = 1; | |
c31c7d48 | 720 | |
ad5ca55f SS |
721 | if (!debug_pagealloc) |
722 | spin_lock(&cpa_lock); | |
c31c7d48 | 723 | ret = __change_page_attr(cpa, checkalias); |
ad5ca55f SS |
724 | if (!debug_pagealloc) |
725 | spin_unlock(&cpa_lock); | |
ff31452b TG |
726 | if (ret) |
727 | return ret; | |
ff31452b | 728 | |
c31c7d48 TG |
729 | if (checkalias) { |
730 | ret = cpa_process_alias(cpa); | |
731 | if (ret) | |
732 | return ret; | |
733 | } | |
734 | ||
65e074df TG |
735 | /* |
736 | * Adjust the number of pages with the result of the | |
737 | * CPA operation. Either a large page has been | |
738 | * preserved or a single page update happened. | |
739 | */ | |
9b5cf48b RW |
740 | BUG_ON(cpa->numpages > numpages); |
741 | numpages -= cpa->numpages; | |
d75586ad SL |
742 | if (cpa->flags & CPA_ARRAY) |
743 | cpa->curpage++; | |
744 | else | |
745 | *cpa->vaddr += cpa->numpages * PAGE_SIZE; | |
746 | ||
65e074df | 747 | } |
ff31452b TG |
748 | return 0; |
749 | } | |
750 | ||
6bb8383b AK |
751 | static inline int cache_attr(pgprot_t attr) |
752 | { | |
753 | return pgprot_val(attr) & | |
754 | (_PAGE_PAT | _PAGE_PAT_LARGE | _PAGE_PWT | _PAGE_PCD); | |
755 | } | |
756 | ||
d75586ad | 757 | static int change_page_attr_set_clr(unsigned long *addr, int numpages, |
c9caa02c | 758 | pgprot_t mask_set, pgprot_t mask_clr, |
d75586ad | 759 | int force_split, int array) |
ff31452b | 760 | { |
72e458df | 761 | struct cpa_data cpa; |
cacf8906 | 762 | int ret, cache, checkalias; |
331e4065 TG |
763 | |
764 | /* | |
765 | * Check, if we are requested to change a not supported | |
766 | * feature: | |
767 | */ | |
768 | mask_set = canon_pgprot(mask_set); | |
769 | mask_clr = canon_pgprot(mask_clr); | |
c9caa02c | 770 | if (!pgprot_val(mask_set) && !pgprot_val(mask_clr) && !force_split) |
331e4065 TG |
771 | return 0; |
772 | ||
69b1415e | 773 | /* Ensure we are PAGE_SIZE aligned */ |
d75586ad SL |
774 | if (!array) { |
775 | if (*addr & ~PAGE_MASK) { | |
776 | *addr &= PAGE_MASK; | |
777 | /* | |
778 | * People should not be passing in unaligned addresses: | |
779 | */ | |
780 | WARN_ON_ONCE(1); | |
781 | } | |
782 | } else { | |
783 | int i; | |
784 | for (i = 0; i < numpages; i++) { | |
785 | if (addr[i] & ~PAGE_MASK) { | |
786 | addr[i] &= PAGE_MASK; | |
787 | WARN_ON_ONCE(1); | |
788 | } | |
789 | } | |
69b1415e TG |
790 | } |
791 | ||
5843d9a4 NP |
792 | /* Must avoid aliasing mappings in the highmem code */ |
793 | kmap_flush_unused(); | |
794 | ||
db64fe02 NP |
795 | vm_unmap_aliases(); |
796 | ||
72e458df TG |
797 | cpa.vaddr = addr; |
798 | cpa.numpages = numpages; | |
799 | cpa.mask_set = mask_set; | |
800 | cpa.mask_clr = mask_clr; | |
d75586ad SL |
801 | cpa.flags = 0; |
802 | cpa.curpage = 0; | |
c9caa02c | 803 | cpa.force_split = force_split; |
72e458df | 804 | |
d75586ad SL |
805 | if (array) |
806 | cpa.flags |= CPA_ARRAY; | |
807 | ||
af96e443 TG |
808 | /* No alias checking for _NX bit modifications */ |
809 | checkalias = (pgprot_val(mask_set) | pgprot_val(mask_clr)) != _PAGE_NX; | |
810 | ||
811 | ret = __change_page_attr_set_clr(&cpa, checkalias); | |
ff31452b | 812 | |
f4ae5da0 TG |
813 | /* |
814 | * Check whether we really changed something: | |
815 | */ | |
d75586ad | 816 | if (!(cpa.flags & CPA_FLUSHTLB)) |
1ac2f7d5 | 817 | goto out; |
cacf8906 | 818 | |
6bb8383b AK |
819 | /* |
820 | * No need to flush, when we did not set any of the caching | |
821 | * attributes: | |
822 | */ | |
823 | cache = cache_attr(mask_set); | |
824 | ||
57a6a46a TG |
825 | /* |
826 | * On success we use clflush, when the CPU supports it to | |
827 | * avoid the wbindv. If the CPU does not support it and in the | |
af1e6844 | 828 | * error case we fall back to cpa_flush_all (which uses |
57a6a46a TG |
829 | * wbindv): |
830 | */ | |
d75586ad SL |
831 | if (!ret && cpu_has_clflush) { |
832 | if (cpa.flags & CPA_ARRAY) | |
833 | cpa_flush_array(addr, numpages, cache); | |
834 | else | |
835 | cpa_flush_range(*addr, numpages, cache); | |
836 | } else | |
6bb8383b | 837 | cpa_flush_all(cache); |
cacf8906 | 838 | |
76ebd054 | 839 | out: |
ff31452b TG |
840 | return ret; |
841 | } | |
842 | ||
d75586ad SL |
843 | static inline int change_page_attr_set(unsigned long *addr, int numpages, |
844 | pgprot_t mask, int array) | |
75cbade8 | 845 | { |
d75586ad SL |
846 | return change_page_attr_set_clr(addr, numpages, mask, __pgprot(0), 0, |
847 | array); | |
75cbade8 AV |
848 | } |
849 | ||
d75586ad SL |
850 | static inline int change_page_attr_clear(unsigned long *addr, int numpages, |
851 | pgprot_t mask, int array) | |
72932c7a | 852 | { |
d75586ad SL |
853 | return change_page_attr_set_clr(addr, numpages, __pgprot(0), mask, 0, |
854 | array); | |
72932c7a TG |
855 | } |
856 | ||
1219333d | 857 | int _set_memory_uc(unsigned long addr, int numpages) |
72932c7a | 858 | { |
de33c442 SS |
859 | /* |
860 | * for now UC MINUS. see comments in ioremap_nocache() | |
861 | */ | |
d75586ad SL |
862 | return change_page_attr_set(&addr, numpages, |
863 | __pgprot(_PAGE_CACHE_UC_MINUS), 0); | |
75cbade8 | 864 | } |
1219333d | 865 | |
866 | int set_memory_uc(unsigned long addr, int numpages) | |
867 | { | |
de33c442 SS |
868 | /* |
869 | * for now UC MINUS. see comments in ioremap_nocache() | |
870 | */ | |
c15238df | 871 | if (reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE, |
de33c442 | 872 | _PAGE_CACHE_UC_MINUS, NULL)) |
1219333d | 873 | return -EINVAL; |
874 | ||
875 | return _set_memory_uc(addr, numpages); | |
876 | } | |
75cbade8 AV |
877 | EXPORT_SYMBOL(set_memory_uc); |
878 | ||
d75586ad SL |
879 | int set_memory_array_uc(unsigned long *addr, int addrinarray) |
880 | { | |
c5e147cf RH |
881 | unsigned long start; |
882 | unsigned long end; | |
d75586ad SL |
883 | int i; |
884 | /* | |
885 | * for now UC MINUS. see comments in ioremap_nocache() | |
886 | */ | |
887 | for (i = 0; i < addrinarray; i++) { | |
c5e147cf RH |
888 | start = __pa(addr[i]); |
889 | for (end = start + PAGE_SIZE; i < addrinarray - 1; end += PAGE_SIZE) { | |
890 | if (end != __pa(addr[i + 1])) | |
891 | break; | |
892 | i++; | |
893 | } | |
894 | if (reserve_memtype(start, end, _PAGE_CACHE_UC_MINUS, NULL)) | |
d75586ad SL |
895 | goto out; |
896 | } | |
897 | ||
898 | return change_page_attr_set(addr, addrinarray, | |
899 | __pgprot(_PAGE_CACHE_UC_MINUS), 1); | |
900 | out: | |
c5e147cf RH |
901 | for (i = 0; i < addrinarray; i++) { |
902 | unsigned long tmp = __pa(addr[i]); | |
903 | ||
904 | if (tmp == start) | |
905 | break; | |
01de05af | 906 | for (end = tmp + PAGE_SIZE; i < addrinarray - 1; end += PAGE_SIZE) { |
c5e147cf RH |
907 | if (end != __pa(addr[i + 1])) |
908 | break; | |
909 | i++; | |
910 | } | |
911 | free_memtype(tmp, end); | |
912 | } | |
d75586ad SL |
913 | return -EINVAL; |
914 | } | |
915 | EXPORT_SYMBOL(set_memory_array_uc); | |
916 | ||
ef354af4 | 917 | int _set_memory_wc(unsigned long addr, int numpages) |
918 | { | |
d75586ad SL |
919 | return change_page_attr_set(&addr, numpages, |
920 | __pgprot(_PAGE_CACHE_WC), 0); | |
ef354af4 | 921 | } |
922 | ||
923 | int set_memory_wc(unsigned long addr, int numpages) | |
924 | { | |
499f8f84 | 925 | if (!pat_enabled) |
ef354af4 | 926 | return set_memory_uc(addr, numpages); |
927 | ||
c15238df | 928 | if (reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE, |
ef354af4 | 929 | _PAGE_CACHE_WC, NULL)) |
930 | return -EINVAL; | |
931 | ||
932 | return _set_memory_wc(addr, numpages); | |
933 | } | |
934 | EXPORT_SYMBOL(set_memory_wc); | |
935 | ||
1219333d | 936 | int _set_memory_wb(unsigned long addr, int numpages) |
75cbade8 | 937 | { |
d75586ad SL |
938 | return change_page_attr_clear(&addr, numpages, |
939 | __pgprot(_PAGE_CACHE_MASK), 0); | |
75cbade8 | 940 | } |
1219333d | 941 | |
942 | int set_memory_wb(unsigned long addr, int numpages) | |
943 | { | |
c15238df | 944 | free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE); |
1219333d | 945 | |
946 | return _set_memory_wb(addr, numpages); | |
947 | } | |
75cbade8 AV |
948 | EXPORT_SYMBOL(set_memory_wb); |
949 | ||
d75586ad SL |
950 | int set_memory_array_wb(unsigned long *addr, int addrinarray) |
951 | { | |
952 | int i; | |
d75586ad | 953 | |
c5e147cf RH |
954 | for (i = 0; i < addrinarray; i++) { |
955 | unsigned long start = __pa(addr[i]); | |
956 | unsigned long end; | |
957 | ||
958 | for (end = start + PAGE_SIZE; i < addrinarray - 1; end += PAGE_SIZE) { | |
959 | if (end != __pa(addr[i + 1])) | |
960 | break; | |
961 | i++; | |
962 | } | |
963 | free_memtype(start, end); | |
964 | } | |
d75586ad SL |
965 | return change_page_attr_clear(addr, addrinarray, |
966 | __pgprot(_PAGE_CACHE_MASK), 1); | |
967 | } | |
968 | EXPORT_SYMBOL(set_memory_array_wb); | |
969 | ||
75cbade8 AV |
970 | int set_memory_x(unsigned long addr, int numpages) |
971 | { | |
d75586ad | 972 | return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_NX), 0); |
75cbade8 AV |
973 | } |
974 | EXPORT_SYMBOL(set_memory_x); | |
975 | ||
976 | int set_memory_nx(unsigned long addr, int numpages) | |
977 | { | |
d75586ad | 978 | return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_NX), 0); |
75cbade8 AV |
979 | } |
980 | EXPORT_SYMBOL(set_memory_nx); | |
981 | ||
982 | int set_memory_ro(unsigned long addr, int numpages) | |
983 | { | |
d75586ad | 984 | return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_RW), 0); |
75cbade8 | 985 | } |
a03352d2 | 986 | EXPORT_SYMBOL_GPL(set_memory_ro); |
75cbade8 AV |
987 | |
988 | int set_memory_rw(unsigned long addr, int numpages) | |
989 | { | |
d75586ad | 990 | return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_RW), 0); |
75cbade8 | 991 | } |
a03352d2 | 992 | EXPORT_SYMBOL_GPL(set_memory_rw); |
f62d0f00 IM |
993 | |
994 | int set_memory_np(unsigned long addr, int numpages) | |
995 | { | |
d75586ad | 996 | return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_PRESENT), 0); |
f62d0f00 | 997 | } |
75cbade8 | 998 | |
c9caa02c AK |
999 | int set_memory_4k(unsigned long addr, int numpages) |
1000 | { | |
d75586ad SL |
1001 | return change_page_attr_set_clr(&addr, numpages, __pgprot(0), |
1002 | __pgprot(0), 1, 0); | |
c9caa02c AK |
1003 | } |
1004 | ||
75cbade8 AV |
1005 | int set_pages_uc(struct page *page, int numpages) |
1006 | { | |
1007 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1008 | |
d7c8f21a | 1009 | return set_memory_uc(addr, numpages); |
75cbade8 AV |
1010 | } |
1011 | EXPORT_SYMBOL(set_pages_uc); | |
1012 | ||
1013 | int set_pages_wb(struct page *page, int numpages) | |
1014 | { | |
1015 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1016 | |
d7c8f21a | 1017 | return set_memory_wb(addr, numpages); |
75cbade8 AV |
1018 | } |
1019 | EXPORT_SYMBOL(set_pages_wb); | |
1020 | ||
1021 | int set_pages_x(struct page *page, int numpages) | |
1022 | { | |
1023 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1024 | |
d7c8f21a | 1025 | return set_memory_x(addr, numpages); |
75cbade8 AV |
1026 | } |
1027 | EXPORT_SYMBOL(set_pages_x); | |
1028 | ||
1029 | int set_pages_nx(struct page *page, int numpages) | |
1030 | { | |
1031 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1032 | |
d7c8f21a | 1033 | return set_memory_nx(addr, numpages); |
75cbade8 AV |
1034 | } |
1035 | EXPORT_SYMBOL(set_pages_nx); | |
1036 | ||
1037 | int set_pages_ro(struct page *page, int numpages) | |
1038 | { | |
1039 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1040 | |
d7c8f21a | 1041 | return set_memory_ro(addr, numpages); |
75cbade8 | 1042 | } |
75cbade8 AV |
1043 | |
1044 | int set_pages_rw(struct page *page, int numpages) | |
1045 | { | |
1046 | unsigned long addr = (unsigned long)page_address(page); | |
e81d5dc4 | 1047 | |
d7c8f21a | 1048 | return set_memory_rw(addr, numpages); |
78c94aba IM |
1049 | } |
1050 | ||
1da177e4 | 1051 | #ifdef CONFIG_DEBUG_PAGEALLOC |
f62d0f00 IM |
1052 | |
1053 | static int __set_pages_p(struct page *page, int numpages) | |
1054 | { | |
d75586ad SL |
1055 | unsigned long tempaddr = (unsigned long) page_address(page); |
1056 | struct cpa_data cpa = { .vaddr = &tempaddr, | |
72e458df TG |
1057 | .numpages = numpages, |
1058 | .mask_set = __pgprot(_PAGE_PRESENT | _PAGE_RW), | |
d75586ad SL |
1059 | .mask_clr = __pgprot(0), |
1060 | .flags = 0}; | |
72932c7a | 1061 | |
55121b43 SS |
1062 | /* |
1063 | * No alias checking needed for setting present flag. otherwise, | |
1064 | * we may need to break large pages for 64-bit kernel text | |
1065 | * mappings (this adds to complexity if we want to do this from | |
1066 | * atomic context especially). Let's keep it simple! | |
1067 | */ | |
1068 | return __change_page_attr_set_clr(&cpa, 0); | |
f62d0f00 IM |
1069 | } |
1070 | ||
1071 | static int __set_pages_np(struct page *page, int numpages) | |
1072 | { | |
d75586ad SL |
1073 | unsigned long tempaddr = (unsigned long) page_address(page); |
1074 | struct cpa_data cpa = { .vaddr = &tempaddr, | |
72e458df TG |
1075 | .numpages = numpages, |
1076 | .mask_set = __pgprot(0), | |
d75586ad SL |
1077 | .mask_clr = __pgprot(_PAGE_PRESENT | _PAGE_RW), |
1078 | .flags = 0}; | |
72932c7a | 1079 | |
55121b43 SS |
1080 | /* |
1081 | * No alias checking needed for setting not present flag. otherwise, | |
1082 | * we may need to break large pages for 64-bit kernel text | |
1083 | * mappings (this adds to complexity if we want to do this from | |
1084 | * atomic context especially). Let's keep it simple! | |
1085 | */ | |
1086 | return __change_page_attr_set_clr(&cpa, 0); | |
f62d0f00 IM |
1087 | } |
1088 | ||
1da177e4 LT |
1089 | void kernel_map_pages(struct page *page, int numpages, int enable) |
1090 | { | |
1091 | if (PageHighMem(page)) | |
1092 | return; | |
9f4c815c | 1093 | if (!enable) { |
f9b8404c IM |
1094 | debug_check_no_locks_freed(page_address(page), |
1095 | numpages * PAGE_SIZE); | |
9f4c815c | 1096 | } |
de5097c2 | 1097 | |
12d6f21e IM |
1098 | /* |
1099 | * If page allocator is not up yet then do not call c_p_a(): | |
1100 | */ | |
1101 | if (!debug_pagealloc_enabled) | |
1102 | return; | |
1103 | ||
9f4c815c | 1104 | /* |
f8d8406b | 1105 | * The return value is ignored as the calls cannot fail. |
55121b43 SS |
1106 | * Large pages for identity mappings are not used at boot time |
1107 | * and hence no memory allocations during large page split. | |
1da177e4 | 1108 | */ |
f62d0f00 IM |
1109 | if (enable) |
1110 | __set_pages_p(page, numpages); | |
1111 | else | |
1112 | __set_pages_np(page, numpages); | |
9f4c815c IM |
1113 | |
1114 | /* | |
e4b71dcf IM |
1115 | * We should perform an IPI and flush all tlbs, |
1116 | * but that can deadlock->flush only current cpu: | |
1da177e4 LT |
1117 | */ |
1118 | __flush_tlb_all(); | |
ee7ae7a1 TG |
1119 | } |
1120 | ||
8a235efa RW |
1121 | #ifdef CONFIG_HIBERNATION |
1122 | ||
1123 | bool kernel_page_present(struct page *page) | |
1124 | { | |
1125 | unsigned int level; | |
1126 | pte_t *pte; | |
1127 | ||
1128 | if (PageHighMem(page)) | |
1129 | return false; | |
1130 | ||
1131 | pte = lookup_address((unsigned long)page_address(page), &level); | |
1132 | return (pte_val(*pte) & _PAGE_PRESENT); | |
1133 | } | |
1134 | ||
1135 | #endif /* CONFIG_HIBERNATION */ | |
1136 | ||
1137 | #endif /* CONFIG_DEBUG_PAGEALLOC */ | |
d1028a15 AV |
1138 | |
1139 | /* | |
1140 | * The testcases use internal knowledge of the implementation that shouldn't | |
1141 | * be exposed to the rest of the kernel. Include these directly here. | |
1142 | */ | |
1143 | #ifdef CONFIG_CPA_DEBUG | |
1144 | #include "pageattr-test.c" | |
1145 | #endif |