Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /** |
2 | * @file nmi_int.c | |
3 | * | |
adf5ec0b | 4 | * @remark Copyright 2002-2008 OProfile authors |
1da177e4 LT |
5 | * @remark Read the file COPYING |
6 | * | |
7 | * @author John Levon <levon@movementarian.org> | |
adf5ec0b | 8 | * @author Robert Richter <robert.richter@amd.com> |
1da177e4 LT |
9 | */ |
10 | ||
11 | #include <linux/init.h> | |
12 | #include <linux/notifier.h> | |
13 | #include <linux/smp.h> | |
14 | #include <linux/oprofile.h> | |
15 | #include <linux/sysdev.h> | |
16 | #include <linux/slab.h> | |
1cfcea1b | 17 | #include <linux/moduleparam.h> |
1eeb66a1 | 18 | #include <linux/kdebug.h> |
80a8c9ff | 19 | #include <linux/cpu.h> |
1da177e4 LT |
20 | #include <asm/nmi.h> |
21 | #include <asm/msr.h> | |
22 | #include <asm/apic.h> | |
b75f53db | 23 | |
1da177e4 LT |
24 | #include "op_counter.h" |
25 | #include "op_x86_model.h" | |
2fbe7b25 | 26 | |
b75f53db | 27 | static struct op_x86_model_spec const *model; |
d18d00f5 MT |
28 | static DEFINE_PER_CPU(struct op_msrs, cpu_msrs); |
29 | static DEFINE_PER_CPU(unsigned long, saved_lvtpc); | |
2fbe7b25 | 30 | |
1da177e4 LT |
31 | /* 0 == registered but off, 1 == registered and on */ |
32 | static int nmi_enabled = 0; | |
33 | ||
c7c19f8e AB |
34 | static int profile_exceptions_notify(struct notifier_block *self, |
35 | unsigned long val, void *data) | |
1da177e4 | 36 | { |
2fbe7b25 DZ |
37 | struct die_args *args = (struct die_args *)data; |
38 | int ret = NOTIFY_DONE; | |
39 | int cpu = smp_processor_id(); | |
40 | ||
b75f53db | 41 | switch (val) { |
2fbe7b25 | 42 | case DIE_NMI: |
d18d00f5 | 43 | if (model->check_ctrs(args->regs, &per_cpu(cpu_msrs, cpu))) |
2fbe7b25 DZ |
44 | ret = NOTIFY_STOP; |
45 | break; | |
46 | default: | |
47 | break; | |
48 | } | |
49 | return ret; | |
1da177e4 | 50 | } |
2fbe7b25 | 51 | |
b75f53db | 52 | static void nmi_cpu_save_registers(struct op_msrs *msrs) |
1da177e4 LT |
53 | { |
54 | unsigned int const nr_ctrs = model->num_counters; | |
b75f53db CM |
55 | unsigned int const nr_ctrls = model->num_controls; |
56 | struct op_msr *counters = msrs->counters; | |
57 | struct op_msr *controls = msrs->controls; | |
1da177e4 LT |
58 | unsigned int i; |
59 | ||
60 | for (i = 0; i < nr_ctrs; ++i) { | |
b75f53db | 61 | if (counters[i].addr) { |
cb9c448c DZ |
62 | rdmsr(counters[i].addr, |
63 | counters[i].saved.low, | |
64 | counters[i].saved.high); | |
65 | } | |
1da177e4 | 66 | } |
b75f53db | 67 | |
1da177e4 | 68 | for (i = 0; i < nr_ctrls; ++i) { |
b75f53db | 69 | if (controls[i].addr) { |
cb9c448c DZ |
70 | rdmsr(controls[i].addr, |
71 | controls[i].saved.low, | |
72 | controls[i].saved.high); | |
73 | } | |
1da177e4 LT |
74 | } |
75 | } | |
76 | ||
b75f53db | 77 | static void nmi_save_registers(void *dummy) |
1da177e4 LT |
78 | { |
79 | int cpu = smp_processor_id(); | |
d18d00f5 | 80 | struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu); |
1da177e4 LT |
81 | nmi_cpu_save_registers(msrs); |
82 | } | |
83 | ||
1da177e4 LT |
84 | static void free_msrs(void) |
85 | { | |
86 | int i; | |
c8912599 | 87 | for_each_possible_cpu(i) { |
d18d00f5 MT |
88 | kfree(per_cpu(cpu_msrs, i).counters); |
89 | per_cpu(cpu_msrs, i).counters = NULL; | |
90 | kfree(per_cpu(cpu_msrs, i).controls); | |
91 | per_cpu(cpu_msrs, i).controls = NULL; | |
1da177e4 LT |
92 | } |
93 | } | |
94 | ||
1da177e4 LT |
95 | static int allocate_msrs(void) |
96 | { | |
4c168eaf | 97 | int success = 1; |
1da177e4 LT |
98 | size_t controls_size = sizeof(struct op_msr) * model->num_controls; |
99 | size_t counters_size = sizeof(struct op_msr) * model->num_counters; | |
100 | ||
4c168eaf | 101 | int i; |
0939c17c | 102 | for_each_possible_cpu(i) { |
d18d00f5 MT |
103 | per_cpu(cpu_msrs, i).counters = kmalloc(counters_size, |
104 | GFP_KERNEL); | |
105 | if (!per_cpu(cpu_msrs, i).counters) { | |
1da177e4 LT |
106 | success = 0; |
107 | break; | |
108 | } | |
4c168eaf RR |
109 | per_cpu(cpu_msrs, i).controls = kmalloc(controls_size, |
110 | GFP_KERNEL); | |
d18d00f5 | 111 | if (!per_cpu(cpu_msrs, i).controls) { |
1da177e4 LT |
112 | success = 0; |
113 | break; | |
114 | } | |
115 | } | |
116 | ||
117 | if (!success) | |
118 | free_msrs(); | |
119 | ||
120 | return success; | |
121 | } | |
122 | ||
b75f53db | 123 | static void nmi_cpu_setup(void *dummy) |
1da177e4 LT |
124 | { |
125 | int cpu = smp_processor_id(); | |
d18d00f5 | 126 | struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu); |
1da177e4 LT |
127 | spin_lock(&oprofilefs_lock); |
128 | model->setup_ctrs(msrs); | |
129 | spin_unlock(&oprofilefs_lock); | |
d18d00f5 | 130 | per_cpu(saved_lvtpc, cpu) = apic_read(APIC_LVTPC); |
1da177e4 LT |
131 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
132 | } | |
133 | ||
2fbe7b25 DZ |
134 | static struct notifier_block profile_exceptions_nb = { |
135 | .notifier_call = profile_exceptions_notify, | |
136 | .next = NULL, | |
137 | .priority = 0 | |
138 | }; | |
1da177e4 LT |
139 | |
140 | static int nmi_setup(void) | |
141 | { | |
b75f53db | 142 | int err = 0; |
6c977aad | 143 | int cpu; |
2fbe7b25 | 144 | |
1da177e4 LT |
145 | if (!allocate_msrs()) |
146 | return -ENOMEM; | |
147 | ||
b75f53db CM |
148 | err = register_die_notifier(&profile_exceptions_nb); |
149 | if (err) { | |
1da177e4 | 150 | free_msrs(); |
2fbe7b25 | 151 | return err; |
1da177e4 | 152 | } |
2fbe7b25 | 153 | |
4c168eaf | 154 | /* We need to serialize save and setup for HT because the subset |
1da177e4 LT |
155 | * of msrs are distinct for save and setup operations |
156 | */ | |
6c977aad AK |
157 | |
158 | /* Assume saved/restored counters are the same on all CPUs */ | |
d18d00f5 | 159 | model->fill_in_addresses(&per_cpu(cpu_msrs, 0)); |
b75f53db | 160 | for_each_possible_cpu(cpu) { |
0939c17c | 161 | if (cpu != 0) { |
d18d00f5 MT |
162 | memcpy(per_cpu(cpu_msrs, cpu).counters, |
163 | per_cpu(cpu_msrs, 0).counters, | |
0939c17c CW |
164 | sizeof(struct op_msr) * model->num_counters); |
165 | ||
d18d00f5 MT |
166 | memcpy(per_cpu(cpu_msrs, cpu).controls, |
167 | per_cpu(cpu_msrs, 0).controls, | |
0939c17c CW |
168 | sizeof(struct op_msr) * model->num_controls); |
169 | } | |
4c168eaf | 170 | |
6c977aad | 171 | } |
15c8b6c1 JA |
172 | on_each_cpu(nmi_save_registers, NULL, 1); |
173 | on_each_cpu(nmi_cpu_setup, NULL, 1); | |
1da177e4 LT |
174 | nmi_enabled = 1; |
175 | return 0; | |
176 | } | |
177 | ||
4c168eaf | 178 | static void nmi_restore_registers(struct op_msrs *msrs) |
1da177e4 LT |
179 | { |
180 | unsigned int const nr_ctrs = model->num_counters; | |
b75f53db CM |
181 | unsigned int const nr_ctrls = model->num_controls; |
182 | struct op_msr *counters = msrs->counters; | |
183 | struct op_msr *controls = msrs->controls; | |
1da177e4 LT |
184 | unsigned int i; |
185 | ||
186 | for (i = 0; i < nr_ctrls; ++i) { | |
b75f53db | 187 | if (controls[i].addr) { |
cb9c448c DZ |
188 | wrmsr(controls[i].addr, |
189 | controls[i].saved.low, | |
190 | controls[i].saved.high); | |
191 | } | |
1da177e4 | 192 | } |
b75f53db | 193 | |
1da177e4 | 194 | for (i = 0; i < nr_ctrs; ++i) { |
b75f53db | 195 | if (counters[i].addr) { |
cb9c448c DZ |
196 | wrmsr(counters[i].addr, |
197 | counters[i].saved.low, | |
198 | counters[i].saved.high); | |
199 | } | |
1da177e4 LT |
200 | } |
201 | } | |
1da177e4 | 202 | |
b75f53db | 203 | static void nmi_cpu_shutdown(void *dummy) |
1da177e4 LT |
204 | { |
205 | unsigned int v; | |
206 | int cpu = smp_processor_id(); | |
d18d00f5 | 207 | struct op_msrs *msrs = &__get_cpu_var(cpu_msrs); |
b75f53db | 208 | |
1da177e4 LT |
209 | /* restoring APIC_LVTPC can trigger an apic error because the delivery |
210 | * mode and vector nr combination can be illegal. That's by design: on | |
211 | * power on apic lvt contain a zero vector nr which are legal only for | |
212 | * NMI delivery mode. So inhibit apic err before restoring lvtpc | |
213 | */ | |
214 | v = apic_read(APIC_LVTERR); | |
215 | apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); | |
d18d00f5 | 216 | apic_write(APIC_LVTPC, per_cpu(saved_lvtpc, cpu)); |
1da177e4 | 217 | apic_write(APIC_LVTERR, v); |
4c168eaf | 218 | nmi_restore_registers(msrs); |
1da177e4 LT |
219 | } |
220 | ||
1da177e4 LT |
221 | static void nmi_shutdown(void) |
222 | { | |
b61e06f2 AR |
223 | struct op_msrs *msrs; |
224 | ||
1da177e4 | 225 | nmi_enabled = 0; |
15c8b6c1 | 226 | on_each_cpu(nmi_cpu_shutdown, NULL, 1); |
2fbe7b25 | 227 | unregister_die_notifier(&profile_exceptions_nb); |
b61e06f2 | 228 | msrs = &get_cpu_var(cpu_msrs); |
d18d00f5 | 229 | model->shutdown(msrs); |
1da177e4 | 230 | free_msrs(); |
93e1ade5 | 231 | put_cpu_var(cpu_msrs); |
1da177e4 LT |
232 | } |
233 | ||
b75f53db | 234 | static void nmi_cpu_start(void *dummy) |
1da177e4 | 235 | { |
d18d00f5 | 236 | struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs); |
1da177e4 LT |
237 | model->start(msrs); |
238 | } | |
1da177e4 LT |
239 | |
240 | static int nmi_start(void) | |
241 | { | |
15c8b6c1 | 242 | on_each_cpu(nmi_cpu_start, NULL, 1); |
1da177e4 LT |
243 | return 0; |
244 | } | |
b75f53db CM |
245 | |
246 | static void nmi_cpu_stop(void *dummy) | |
1da177e4 | 247 | { |
d18d00f5 | 248 | struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs); |
1da177e4 LT |
249 | model->stop(msrs); |
250 | } | |
b75f53db | 251 | |
1da177e4 LT |
252 | static void nmi_stop(void) |
253 | { | |
15c8b6c1 | 254 | on_each_cpu(nmi_cpu_stop, NULL, 1); |
1da177e4 LT |
255 | } |
256 | ||
1da177e4 LT |
257 | struct op_counter_config counter_config[OP_MAX_COUNTER]; |
258 | ||
b75f53db | 259 | static int nmi_create_files(struct super_block *sb, struct dentry *root) |
1da177e4 LT |
260 | { |
261 | unsigned int i; | |
262 | ||
263 | for (i = 0; i < model->num_counters; ++i) { | |
b75f53db | 264 | struct dentry *dir; |
0c6856f7 | 265 | char buf[4]; |
b75f53db CM |
266 | |
267 | /* quick little hack to _not_ expose a counter if it is not | |
cb9c448c DZ |
268 | * available for use. This should protect userspace app. |
269 | * NOTE: assumes 1:1 mapping here (that counters are organized | |
270 | * sequentially in their struct assignment). | |
271 | */ | |
272 | if (unlikely(!avail_to_resrv_perfctr_nmi_bit(i))) | |
273 | continue; | |
274 | ||
0c6856f7 | 275 | snprintf(buf, sizeof(buf), "%d", i); |
1da177e4 | 276 | dir = oprofilefs_mkdir(sb, root, buf); |
b75f53db CM |
277 | oprofilefs_create_ulong(sb, dir, "enabled", &counter_config[i].enabled); |
278 | oprofilefs_create_ulong(sb, dir, "event", &counter_config[i].event); | |
279 | oprofilefs_create_ulong(sb, dir, "count", &counter_config[i].count); | |
280 | oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask); | |
281 | oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel); | |
282 | oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user); | |
1da177e4 LT |
283 | } |
284 | ||
285 | return 0; | |
286 | } | |
b75f53db | 287 | |
69046d43 RR |
288 | #ifdef CONFIG_SMP |
289 | static int oprofile_cpu_notifier(struct notifier_block *b, unsigned long action, | |
290 | void *data) | |
291 | { | |
292 | int cpu = (unsigned long)data; | |
293 | switch (action) { | |
294 | case CPU_DOWN_FAILED: | |
295 | case CPU_ONLINE: | |
296 | smp_call_function_single(cpu, nmi_cpu_start, NULL, 0); | |
297 | break; | |
298 | case CPU_DOWN_PREPARE: | |
299 | smp_call_function_single(cpu, nmi_cpu_stop, NULL, 1); | |
300 | break; | |
301 | } | |
302 | return NOTIFY_DONE; | |
303 | } | |
304 | ||
305 | static struct notifier_block oprofile_cpu_nb = { | |
306 | .notifier_call = oprofile_cpu_notifier | |
307 | }; | |
308 | #endif | |
309 | ||
310 | #ifdef CONFIG_PM | |
311 | ||
312 | static int nmi_suspend(struct sys_device *dev, pm_message_t state) | |
313 | { | |
314 | /* Only one CPU left, just stop that one */ | |
315 | if (nmi_enabled == 1) | |
316 | nmi_cpu_stop(NULL); | |
317 | return 0; | |
318 | } | |
319 | ||
320 | static int nmi_resume(struct sys_device *dev) | |
321 | { | |
322 | if (nmi_enabled == 1) | |
323 | nmi_cpu_start(NULL); | |
324 | return 0; | |
325 | } | |
326 | ||
327 | static struct sysdev_class oprofile_sysclass = { | |
328 | .name = "oprofile", | |
329 | .resume = nmi_resume, | |
330 | .suspend = nmi_suspend, | |
331 | }; | |
332 | ||
333 | static struct sys_device device_oprofile = { | |
334 | .id = 0, | |
335 | .cls = &oprofile_sysclass, | |
336 | }; | |
337 | ||
338 | static int __init init_sysfs(void) | |
339 | { | |
340 | int error; | |
341 | ||
342 | error = sysdev_class_register(&oprofile_sysclass); | |
343 | if (!error) | |
344 | error = sysdev_register(&device_oprofile); | |
345 | return error; | |
346 | } | |
347 | ||
348 | static void exit_sysfs(void) | |
349 | { | |
350 | sysdev_unregister(&device_oprofile); | |
351 | sysdev_class_unregister(&oprofile_sysclass); | |
352 | } | |
353 | ||
354 | #else | |
355 | #define init_sysfs() do { } while (0) | |
356 | #define exit_sysfs() do { } while (0) | |
357 | #endif /* CONFIG_PM */ | |
358 | ||
1cfcea1b AK |
359 | static int p4force; |
360 | module_param(p4force, int, 0); | |
b75f53db CM |
361 | |
362 | static int __init p4_init(char **cpu_type) | |
1da177e4 LT |
363 | { |
364 | __u8 cpu_model = boot_cpu_data.x86_model; | |
365 | ||
1cfcea1b | 366 | if (!p4force && (cpu_model > 6 || cpu_model == 5)) |
1da177e4 LT |
367 | return 0; |
368 | ||
369 | #ifndef CONFIG_SMP | |
370 | *cpu_type = "i386/p4"; | |
371 | model = &op_p4_spec; | |
372 | return 1; | |
373 | #else | |
374 | switch (smp_num_siblings) { | |
b75f53db CM |
375 | case 1: |
376 | *cpu_type = "i386/p4"; | |
377 | model = &op_p4_spec; | |
378 | return 1; | |
379 | ||
380 | case 2: | |
381 | *cpu_type = "i386/p4-ht"; | |
382 | model = &op_p4_ht2_spec; | |
383 | return 1; | |
1da177e4 LT |
384 | } |
385 | #endif | |
386 | ||
387 | printk(KERN_INFO "oprofile: P4 HyperThreading detected with > 2 threads\n"); | |
388 | printk(KERN_INFO "oprofile: Reverting to timer mode.\n"); | |
389 | return 0; | |
390 | } | |
391 | ||
b75f53db | 392 | static int __init ppro_init(char **cpu_type) |
1da177e4 LT |
393 | { |
394 | __u8 cpu_model = boot_cpu_data.x86_model; | |
395 | ||
4b9f12a3 LT |
396 | switch (cpu_model) { |
397 | case 0 ... 2: | |
398 | *cpu_type = "i386/ppro"; | |
399 | break; | |
400 | case 3 ... 5: | |
401 | *cpu_type = "i386/pii"; | |
402 | break; | |
403 | case 6 ... 8: | |
3d337c65 | 404 | case 10 ... 11: |
4b9f12a3 LT |
405 | *cpu_type = "i386/piii"; |
406 | break; | |
407 | case 9: | |
3d337c65 | 408 | case 13: |
4b9f12a3 LT |
409 | *cpu_type = "i386/p6_mobile"; |
410 | break; | |
4b9f12a3 | 411 | case 14: |
64471ebe | 412 | *cpu_type = "i386/core"; |
4b9f12a3 LT |
413 | break; |
414 | case 15: case 23: | |
415 | *cpu_type = "i386/core_2"; | |
416 | break; | |
4b9f12a3 LT |
417 | default: |
418 | /* Unknown */ | |
1da177e4 | 419 | return 0; |
1da177e4 LT |
420 | } |
421 | ||
422 | model = &op_ppro_spec; | |
423 | return 1; | |
424 | } | |
425 | ||
b9917028 AK |
426 | static int __init arch_perfmon_init(char **cpu_type) |
427 | { | |
428 | if (!cpu_has_arch_perfmon) | |
429 | return 0; | |
430 | *cpu_type = "i386/arch_perfmon"; | |
431 | model = &op_arch_perfmon_spec; | |
432 | arch_perfmon_setup_counters(); | |
433 | return 1; | |
434 | } | |
435 | ||
405ae7d3 | 436 | /* in order to get sysfs right */ |
1da177e4 LT |
437 | static int using_nmi; |
438 | ||
96d0821c | 439 | int __init op_nmi_init(struct oprofile_operations *ops) |
1da177e4 LT |
440 | { |
441 | __u8 vendor = boot_cpu_data.x86_vendor; | |
442 | __u8 family = boot_cpu_data.x86; | |
b9917028 | 443 | char *cpu_type = NULL; |
adf5ec0b | 444 | int ret = 0; |
1da177e4 LT |
445 | |
446 | if (!cpu_has_apic) | |
447 | return -ENODEV; | |
b75f53db | 448 | |
1da177e4 | 449 | switch (vendor) { |
b75f53db CM |
450 | case X86_VENDOR_AMD: |
451 | /* Needs to be at least an Athlon (or hammer in 32bit mode) */ | |
1da177e4 | 452 | |
b75f53db CM |
453 | switch (family) { |
454 | default: | |
455 | return -ENODEV; | |
456 | case 6: | |
6657fe4f | 457 | model = &op_amd_spec; |
b75f53db CM |
458 | cpu_type = "i386/athlon"; |
459 | break; | |
460 | case 0xf: | |
6657fe4f | 461 | model = &op_amd_spec; |
b75f53db CM |
462 | /* Actually it could be i386/hammer too, but give |
463 | user space an consistent name. */ | |
464 | cpu_type = "x86-64/hammer"; | |
465 | break; | |
466 | case 0x10: | |
6657fe4f | 467 | model = &op_amd_spec; |
b75f53db CM |
468 | cpu_type = "x86-64/family10"; |
469 | break; | |
12f2b261 | 470 | case 0x11: |
6657fe4f | 471 | model = &op_amd_spec; |
12f2b261 BK |
472 | cpu_type = "x86-64/family11h"; |
473 | break; | |
b75f53db CM |
474 | } |
475 | break; | |
476 | ||
477 | case X86_VENDOR_INTEL: | |
478 | switch (family) { | |
479 | /* Pentium IV */ | |
480 | case 0xf: | |
b9917028 | 481 | p4_init(&cpu_type); |
1da177e4 | 482 | break; |
b75f53db CM |
483 | |
484 | /* A P6-class processor */ | |
485 | case 6: | |
b9917028 | 486 | ppro_init(&cpu_type); |
1da177e4 LT |
487 | break; |
488 | ||
489 | default: | |
b9917028 | 490 | break; |
b75f53db | 491 | } |
b9917028 AK |
492 | |
493 | if (!cpu_type && !arch_perfmon_init(&cpu_type)) | |
494 | return -ENODEV; | |
b75f53db CM |
495 | break; |
496 | ||
497 | default: | |
498 | return -ENODEV; | |
1da177e4 LT |
499 | } |
500 | ||
80a8c9ff AK |
501 | #ifdef CONFIG_SMP |
502 | register_cpu_notifier(&oprofile_cpu_nb); | |
503 | #endif | |
270d3e1a RR |
504 | /* default values, can be overwritten by model */ |
505 | ops->create_files = nmi_create_files; | |
506 | ops->setup = nmi_setup; | |
507 | ops->shutdown = nmi_shutdown; | |
508 | ops->start = nmi_start; | |
509 | ops->stop = nmi_stop; | |
510 | ops->cpu_type = cpu_type; | |
511 | ||
adf5ec0b RR |
512 | if (model->init) |
513 | ret = model->init(ops); | |
514 | if (ret) | |
515 | return ret; | |
516 | ||
405ae7d3 | 517 | init_sysfs(); |
1da177e4 | 518 | using_nmi = 1; |
1da177e4 LT |
519 | printk(KERN_INFO "oprofile: using NMI interrupt.\n"); |
520 | return 0; | |
521 | } | |
522 | ||
96d0821c | 523 | void op_nmi_exit(void) |
1da177e4 | 524 | { |
80a8c9ff | 525 | if (using_nmi) { |
405ae7d3 | 526 | exit_sysfs(); |
80a8c9ff AK |
527 | #ifdef CONFIG_SMP |
528 | unregister_cpu_notifier(&oprofile_cpu_nb); | |
529 | #endif | |
530 | } | |
adf5ec0b RR |
531 | if (model->exit) |
532 | model->exit(); | |
1da177e4 | 533 | } |