Commit | Line | Data |
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1da177e4 LT |
1 | /** |
2 | * @file nmi_int.c | |
3 | * | |
4d4036e0 | 4 | * @remark Copyright 2002-2009 OProfile authors |
1da177e4 LT |
5 | * @remark Read the file COPYING |
6 | * | |
7 | * @author John Levon <levon@movementarian.org> | |
adf5ec0b | 8 | * @author Robert Richter <robert.richter@amd.com> |
4d4036e0 JY |
9 | * @author Barry Kasindorf <barry.kasindorf@amd.com> |
10 | * @author Jason Yeh <jason.yeh@amd.com> | |
11 | * @author Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> | |
1da177e4 LT |
12 | */ |
13 | ||
14 | #include <linux/init.h> | |
15 | #include <linux/notifier.h> | |
16 | #include <linux/smp.h> | |
17 | #include <linux/oprofile.h> | |
18 | #include <linux/sysdev.h> | |
19 | #include <linux/slab.h> | |
1cfcea1b | 20 | #include <linux/moduleparam.h> |
1eeb66a1 | 21 | #include <linux/kdebug.h> |
80a8c9ff | 22 | #include <linux/cpu.h> |
1da177e4 LT |
23 | #include <asm/nmi.h> |
24 | #include <asm/msr.h> | |
25 | #include <asm/apic.h> | |
b75f53db | 26 | |
1da177e4 LT |
27 | #include "op_counter.h" |
28 | #include "op_x86_model.h" | |
2fbe7b25 | 29 | |
259a83a8 | 30 | static struct op_x86_model_spec *model; |
d18d00f5 MT |
31 | static DEFINE_PER_CPU(struct op_msrs, cpu_msrs); |
32 | static DEFINE_PER_CPU(unsigned long, saved_lvtpc); | |
2fbe7b25 | 33 | |
1da177e4 LT |
34 | /* 0 == registered but off, 1 == registered and on */ |
35 | static int nmi_enabled = 0; | |
36 | ||
4d4036e0 JY |
37 | struct op_counter_config counter_config[OP_MAX_COUNTER]; |
38 | ||
3370d358 RR |
39 | /* common functions */ |
40 | ||
41 | u64 op_x86_get_ctrl(struct op_x86_model_spec const *model, | |
42 | struct op_counter_config *counter_config) | |
43 | { | |
44 | u64 val = 0; | |
45 | u16 event = (u16)counter_config->event; | |
46 | ||
47 | val |= ARCH_PERFMON_EVENTSEL_INT; | |
48 | val |= counter_config->user ? ARCH_PERFMON_EVENTSEL_USR : 0; | |
49 | val |= counter_config->kernel ? ARCH_PERFMON_EVENTSEL_OS : 0; | |
50 | val |= (counter_config->unit_mask & 0xFF) << 8; | |
51 | event &= model->event_mask ? model->event_mask : 0xFF; | |
52 | val |= event & 0xFF; | |
53 | val |= (event & 0x0F00) << 24; | |
54 | ||
55 | return val; | |
56 | } | |
57 | ||
58 | ||
c7c19f8e AB |
59 | static int profile_exceptions_notify(struct notifier_block *self, |
60 | unsigned long val, void *data) | |
1da177e4 | 61 | { |
2fbe7b25 DZ |
62 | struct die_args *args = (struct die_args *)data; |
63 | int ret = NOTIFY_DONE; | |
64 | int cpu = smp_processor_id(); | |
65 | ||
b75f53db | 66 | switch (val) { |
2fbe7b25 | 67 | case DIE_NMI: |
5b75af0a MG |
68 | case DIE_NMI_IPI: |
69 | model->check_ctrs(args->regs, &per_cpu(cpu_msrs, cpu)); | |
70 | ret = NOTIFY_STOP; | |
2fbe7b25 DZ |
71 | break; |
72 | default: | |
73 | break; | |
74 | } | |
75 | return ret; | |
1da177e4 | 76 | } |
2fbe7b25 | 77 | |
b75f53db | 78 | static void nmi_cpu_save_registers(struct op_msrs *msrs) |
1da177e4 | 79 | { |
b75f53db CM |
80 | struct op_msr *counters = msrs->counters; |
81 | struct op_msr *controls = msrs->controls; | |
1da177e4 LT |
82 | unsigned int i; |
83 | ||
1a245c45 | 84 | for (i = 0; i < model->num_counters; ++i) { |
95e74e62 RR |
85 | if (counters[i].addr) |
86 | rdmsrl(counters[i].addr, counters[i].saved); | |
1da177e4 | 87 | } |
b75f53db | 88 | |
1a245c45 | 89 | for (i = 0; i < model->num_controls; ++i) { |
95e74e62 RR |
90 | if (controls[i].addr) |
91 | rdmsrl(controls[i].addr, controls[i].saved); | |
1da177e4 LT |
92 | } |
93 | } | |
94 | ||
b28d1b92 RR |
95 | static void nmi_cpu_start(void *dummy) |
96 | { | |
97 | struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs); | |
98 | model->start(msrs); | |
99 | } | |
100 | ||
101 | static int nmi_start(void) | |
102 | { | |
103 | on_each_cpu(nmi_cpu_start, NULL, 1); | |
104 | return 0; | |
105 | } | |
106 | ||
107 | static void nmi_cpu_stop(void *dummy) | |
108 | { | |
109 | struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs); | |
110 | model->stop(msrs); | |
111 | } | |
112 | ||
113 | static void nmi_stop(void) | |
114 | { | |
115 | on_each_cpu(nmi_cpu_stop, NULL, 1); | |
116 | } | |
117 | ||
d8471ad3 RR |
118 | #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX |
119 | ||
120 | static DEFINE_PER_CPU(int, switch_index); | |
121 | ||
39e97f40 RR |
122 | static inline int has_mux(void) |
123 | { | |
124 | return !!model->switch_ctrl; | |
125 | } | |
126 | ||
d8471ad3 RR |
127 | inline int op_x86_phys_to_virt(int phys) |
128 | { | |
129 | return __get_cpu_var(switch_index) + phys; | |
130 | } | |
131 | ||
61d149d5 RR |
132 | inline int op_x86_virt_to_phys(int virt) |
133 | { | |
134 | return virt % model->num_counters; | |
135 | } | |
136 | ||
6ab82f95 RR |
137 | static void nmi_shutdown_mux(void) |
138 | { | |
139 | int i; | |
39e97f40 RR |
140 | |
141 | if (!has_mux()) | |
142 | return; | |
143 | ||
6ab82f95 RR |
144 | for_each_possible_cpu(i) { |
145 | kfree(per_cpu(cpu_msrs, i).multiplex); | |
146 | per_cpu(cpu_msrs, i).multiplex = NULL; | |
147 | per_cpu(switch_index, i) = 0; | |
148 | } | |
149 | } | |
150 | ||
151 | static int nmi_setup_mux(void) | |
152 | { | |
153 | size_t multiplex_size = | |
154 | sizeof(struct op_msr) * model->num_virt_counters; | |
155 | int i; | |
39e97f40 RR |
156 | |
157 | if (!has_mux()) | |
158 | return 1; | |
159 | ||
6ab82f95 RR |
160 | for_each_possible_cpu(i) { |
161 | per_cpu(cpu_msrs, i).multiplex = | |
162 | kmalloc(multiplex_size, GFP_KERNEL); | |
163 | if (!per_cpu(cpu_msrs, i).multiplex) | |
164 | return 0; | |
165 | } | |
39e97f40 | 166 | |
6ab82f95 RR |
167 | return 1; |
168 | } | |
169 | ||
48fb4b46 RR |
170 | static void nmi_cpu_setup_mux(int cpu, struct op_msrs const * const msrs) |
171 | { | |
172 | int i; | |
173 | struct op_msr *multiplex = msrs->multiplex; | |
174 | ||
39e97f40 RR |
175 | if (!has_mux()) |
176 | return; | |
177 | ||
48fb4b46 RR |
178 | for (i = 0; i < model->num_virt_counters; ++i) { |
179 | if (counter_config[i].enabled) { | |
180 | multiplex[i].saved = -(u64)counter_config[i].count; | |
181 | } else { | |
182 | multiplex[i].addr = 0; | |
183 | multiplex[i].saved = 0; | |
184 | } | |
185 | } | |
186 | ||
187 | per_cpu(switch_index, cpu) = 0; | |
188 | } | |
189 | ||
d0f585dd RR |
190 | static void nmi_cpu_save_mpx_registers(struct op_msrs *msrs) |
191 | { | |
192 | struct op_msr *multiplex = msrs->multiplex; | |
193 | int i; | |
194 | ||
195 | for (i = 0; i < model->num_counters; ++i) { | |
196 | int virt = op_x86_phys_to_virt(i); | |
197 | if (multiplex[virt].addr) | |
198 | rdmsrl(multiplex[virt].addr, multiplex[virt].saved); | |
199 | } | |
200 | } | |
201 | ||
202 | static void nmi_cpu_restore_mpx_registers(struct op_msrs *msrs) | |
203 | { | |
204 | struct op_msr *multiplex = msrs->multiplex; | |
205 | int i; | |
206 | ||
207 | for (i = 0; i < model->num_counters; ++i) { | |
208 | int virt = op_x86_phys_to_virt(i); | |
209 | if (multiplex[virt].addr) | |
210 | wrmsrl(multiplex[virt].addr, multiplex[virt].saved); | |
211 | } | |
212 | } | |
213 | ||
b28d1b92 RR |
214 | static void nmi_cpu_switch(void *dummy) |
215 | { | |
216 | int cpu = smp_processor_id(); | |
217 | int si = per_cpu(switch_index, cpu); | |
218 | struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu); | |
219 | ||
220 | nmi_cpu_stop(NULL); | |
221 | nmi_cpu_save_mpx_registers(msrs); | |
222 | ||
223 | /* move to next set */ | |
224 | si += model->num_counters; | |
d8cc108f | 225 | if ((si >= model->num_virt_counters) || (counter_config[si].count == 0)) |
b28d1b92 RR |
226 | per_cpu(switch_index, cpu) = 0; |
227 | else | |
228 | per_cpu(switch_index, cpu) = si; | |
229 | ||
230 | model->switch_ctrl(model, msrs); | |
231 | nmi_cpu_restore_mpx_registers(msrs); | |
232 | ||
233 | nmi_cpu_start(NULL); | |
234 | } | |
235 | ||
236 | ||
237 | /* | |
238 | * Quick check to see if multiplexing is necessary. | |
239 | * The check should be sufficient since counters are used | |
240 | * in ordre. | |
241 | */ | |
242 | static int nmi_multiplex_on(void) | |
243 | { | |
244 | return counter_config[model->num_counters].count ? 0 : -EINVAL; | |
245 | } | |
246 | ||
247 | static int nmi_switch_event(void) | |
248 | { | |
39e97f40 | 249 | if (!has_mux()) |
b28d1b92 RR |
250 | return -ENOSYS; /* not implemented */ |
251 | if (nmi_multiplex_on() < 0) | |
252 | return -EINVAL; /* not necessary */ | |
253 | ||
254 | on_each_cpu(nmi_cpu_switch, NULL, 1); | |
255 | ||
b28d1b92 RR |
256 | return 0; |
257 | } | |
258 | ||
52805144 RR |
259 | static inline void mux_init(struct oprofile_operations *ops) |
260 | { | |
261 | if (has_mux()) | |
262 | ops->switch_events = nmi_switch_event; | |
263 | } | |
264 | ||
4d015f79 RR |
265 | static void mux_clone(int cpu) |
266 | { | |
267 | if (!has_mux()) | |
268 | return; | |
269 | ||
270 | memcpy(per_cpu(cpu_msrs, cpu).multiplex, | |
271 | per_cpu(cpu_msrs, 0).multiplex, | |
272 | sizeof(struct op_msr) * model->num_virt_counters); | |
273 | } | |
274 | ||
d8471ad3 RR |
275 | #else |
276 | ||
277 | inline int op_x86_phys_to_virt(int phys) { return phys; } | |
61d149d5 | 278 | inline int op_x86_virt_to_phys(int virt) { return virt; } |
6ab82f95 RR |
279 | static inline void nmi_shutdown_mux(void) { } |
280 | static inline int nmi_setup_mux(void) { return 1; } | |
48fb4b46 RR |
281 | static inline void |
282 | nmi_cpu_setup_mux(int cpu, struct op_msrs const * const msrs) { } | |
52805144 | 283 | static inline void mux_init(struct oprofile_operations *ops) { } |
4d015f79 | 284 | static void mux_clone(int cpu) { } |
d8471ad3 RR |
285 | |
286 | #endif | |
287 | ||
1da177e4 LT |
288 | static void free_msrs(void) |
289 | { | |
290 | int i; | |
c8912599 | 291 | for_each_possible_cpu(i) { |
d18d00f5 MT |
292 | kfree(per_cpu(cpu_msrs, i).counters); |
293 | per_cpu(cpu_msrs, i).counters = NULL; | |
294 | kfree(per_cpu(cpu_msrs, i).controls); | |
295 | per_cpu(cpu_msrs, i).controls = NULL; | |
1da177e4 LT |
296 | } |
297 | } | |
298 | ||
1da177e4 LT |
299 | static int allocate_msrs(void) |
300 | { | |
1da177e4 LT |
301 | size_t controls_size = sizeof(struct op_msr) * model->num_controls; |
302 | size_t counters_size = sizeof(struct op_msr) * model->num_counters; | |
303 | ||
4c168eaf | 304 | int i; |
0939c17c | 305 | for_each_possible_cpu(i) { |
d18d00f5 | 306 | per_cpu(cpu_msrs, i).counters = kmalloc(counters_size, |
6ab82f95 RR |
307 | GFP_KERNEL); |
308 | if (!per_cpu(cpu_msrs, i).counters) | |
309 | return 0; | |
4c168eaf | 310 | per_cpu(cpu_msrs, i).controls = kmalloc(controls_size, |
6ab82f95 RR |
311 | GFP_KERNEL); |
312 | if (!per_cpu(cpu_msrs, i).controls) | |
313 | return 0; | |
1da177e4 LT |
314 | } |
315 | ||
6ab82f95 | 316 | return 1; |
1da177e4 LT |
317 | } |
318 | ||
b75f53db | 319 | static void nmi_cpu_setup(void *dummy) |
1da177e4 LT |
320 | { |
321 | int cpu = smp_processor_id(); | |
d18d00f5 | 322 | struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu); |
44ab9a6b | 323 | nmi_cpu_save_registers(msrs); |
1da177e4 | 324 | spin_lock(&oprofilefs_lock); |
ef8828dd | 325 | model->setup_ctrs(model, msrs); |
6bfccd09 | 326 | nmi_cpu_setup_mux(cpu, msrs); |
1da177e4 | 327 | spin_unlock(&oprofilefs_lock); |
d18d00f5 | 328 | per_cpu(saved_lvtpc, cpu) = apic_read(APIC_LVTPC); |
1da177e4 LT |
329 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
330 | } | |
331 | ||
2fbe7b25 DZ |
332 | static struct notifier_block profile_exceptions_nb = { |
333 | .notifier_call = profile_exceptions_notify, | |
334 | .next = NULL, | |
5b75af0a | 335 | .priority = 2 |
2fbe7b25 | 336 | }; |
1da177e4 LT |
337 | |
338 | static int nmi_setup(void) | |
339 | { | |
b75f53db | 340 | int err = 0; |
6c977aad | 341 | int cpu; |
2fbe7b25 | 342 | |
1da177e4 | 343 | if (!allocate_msrs()) |
6ab82f95 RR |
344 | err = -ENOMEM; |
345 | else if (!nmi_setup_mux()) | |
346 | err = -ENOMEM; | |
347 | else | |
348 | err = register_die_notifier(&profile_exceptions_nb); | |
1da177e4 | 349 | |
b75f53db | 350 | if (err) { |
1da177e4 | 351 | free_msrs(); |
6ab82f95 | 352 | nmi_shutdown_mux(); |
2fbe7b25 | 353 | return err; |
1da177e4 | 354 | } |
2fbe7b25 | 355 | |
4c168eaf | 356 | /* We need to serialize save and setup for HT because the subset |
1da177e4 LT |
357 | * of msrs are distinct for save and setup operations |
358 | */ | |
6c977aad AK |
359 | |
360 | /* Assume saved/restored counters are the same on all CPUs */ | |
d18d00f5 | 361 | model->fill_in_addresses(&per_cpu(cpu_msrs, 0)); |
b75f53db | 362 | for_each_possible_cpu(cpu) { |
4d015f79 RR |
363 | if (!cpu) |
364 | continue; | |
365 | ||
366 | memcpy(per_cpu(cpu_msrs, cpu).counters, | |
367 | per_cpu(cpu_msrs, 0).counters, | |
368 | sizeof(struct op_msr) * model->num_counters); | |
369 | ||
370 | memcpy(per_cpu(cpu_msrs, cpu).controls, | |
371 | per_cpu(cpu_msrs, 0).controls, | |
372 | sizeof(struct op_msr) * model->num_controls); | |
373 | ||
374 | mux_clone(cpu); | |
6c977aad | 375 | } |
15c8b6c1 | 376 | on_each_cpu(nmi_cpu_setup, NULL, 1); |
1da177e4 LT |
377 | nmi_enabled = 1; |
378 | return 0; | |
379 | } | |
380 | ||
44ab9a6b | 381 | static void nmi_cpu_restore_registers(struct op_msrs *msrs) |
1da177e4 | 382 | { |
b75f53db CM |
383 | struct op_msr *counters = msrs->counters; |
384 | struct op_msr *controls = msrs->controls; | |
1da177e4 LT |
385 | unsigned int i; |
386 | ||
1a245c45 | 387 | for (i = 0; i < model->num_controls; ++i) { |
95e74e62 RR |
388 | if (controls[i].addr) |
389 | wrmsrl(controls[i].addr, controls[i].saved); | |
1da177e4 | 390 | } |
b75f53db | 391 | |
1a245c45 | 392 | for (i = 0; i < model->num_counters; ++i) { |
95e74e62 RR |
393 | if (counters[i].addr) |
394 | wrmsrl(counters[i].addr, counters[i].saved); | |
1da177e4 LT |
395 | } |
396 | } | |
1da177e4 | 397 | |
b75f53db | 398 | static void nmi_cpu_shutdown(void *dummy) |
1da177e4 LT |
399 | { |
400 | unsigned int v; | |
401 | int cpu = smp_processor_id(); | |
82a22528 | 402 | struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu); |
b75f53db | 403 | |
1da177e4 LT |
404 | /* restoring APIC_LVTPC can trigger an apic error because the delivery |
405 | * mode and vector nr combination can be illegal. That's by design: on | |
406 | * power on apic lvt contain a zero vector nr which are legal only for | |
407 | * NMI delivery mode. So inhibit apic err before restoring lvtpc | |
408 | */ | |
409 | v = apic_read(APIC_LVTERR); | |
410 | apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); | |
d18d00f5 | 411 | apic_write(APIC_LVTPC, per_cpu(saved_lvtpc, cpu)); |
1da177e4 | 412 | apic_write(APIC_LVTERR, v); |
44ab9a6b | 413 | nmi_cpu_restore_registers(msrs); |
1da177e4 LT |
414 | } |
415 | ||
1da177e4 LT |
416 | static void nmi_shutdown(void) |
417 | { | |
b61e06f2 AR |
418 | struct op_msrs *msrs; |
419 | ||
1da177e4 | 420 | nmi_enabled = 0; |
15c8b6c1 | 421 | on_each_cpu(nmi_cpu_shutdown, NULL, 1); |
2fbe7b25 | 422 | unregister_die_notifier(&profile_exceptions_nb); |
6ab82f95 | 423 | nmi_shutdown_mux(); |
b61e06f2 | 424 | msrs = &get_cpu_var(cpu_msrs); |
d18d00f5 | 425 | model->shutdown(msrs); |
1da177e4 | 426 | free_msrs(); |
93e1ade5 | 427 | put_cpu_var(cpu_msrs); |
1da177e4 LT |
428 | } |
429 | ||
b75f53db | 430 | static int nmi_create_files(struct super_block *sb, struct dentry *root) |
1da177e4 LT |
431 | { |
432 | unsigned int i; | |
433 | ||
4d4036e0 | 434 | for (i = 0; i < model->num_virt_counters; ++i) { |
b75f53db | 435 | struct dentry *dir; |
0c6856f7 | 436 | char buf[4]; |
b75f53db CM |
437 | |
438 | /* quick little hack to _not_ expose a counter if it is not | |
cb9c448c DZ |
439 | * available for use. This should protect userspace app. |
440 | * NOTE: assumes 1:1 mapping here (that counters are organized | |
441 | * sequentially in their struct assignment). | |
442 | */ | |
11be1a7b | 443 | if (!avail_to_resrv_perfctr_nmi_bit(op_x86_virt_to_phys(i))) |
cb9c448c DZ |
444 | continue; |
445 | ||
0c6856f7 | 446 | snprintf(buf, sizeof(buf), "%d", i); |
1da177e4 | 447 | dir = oprofilefs_mkdir(sb, root, buf); |
b75f53db CM |
448 | oprofilefs_create_ulong(sb, dir, "enabled", &counter_config[i].enabled); |
449 | oprofilefs_create_ulong(sb, dir, "event", &counter_config[i].event); | |
450 | oprofilefs_create_ulong(sb, dir, "count", &counter_config[i].count); | |
451 | oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask); | |
452 | oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel); | |
453 | oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user); | |
1da177e4 LT |
454 | } |
455 | ||
456 | return 0; | |
457 | } | |
b75f53db | 458 | |
69046d43 RR |
459 | #ifdef CONFIG_SMP |
460 | static int oprofile_cpu_notifier(struct notifier_block *b, unsigned long action, | |
461 | void *data) | |
462 | { | |
463 | int cpu = (unsigned long)data; | |
464 | switch (action) { | |
465 | case CPU_DOWN_FAILED: | |
466 | case CPU_ONLINE: | |
467 | smp_call_function_single(cpu, nmi_cpu_start, NULL, 0); | |
468 | break; | |
469 | case CPU_DOWN_PREPARE: | |
470 | smp_call_function_single(cpu, nmi_cpu_stop, NULL, 1); | |
471 | break; | |
472 | } | |
473 | return NOTIFY_DONE; | |
474 | } | |
475 | ||
476 | static struct notifier_block oprofile_cpu_nb = { | |
477 | .notifier_call = oprofile_cpu_notifier | |
478 | }; | |
479 | #endif | |
480 | ||
481 | #ifdef CONFIG_PM | |
482 | ||
483 | static int nmi_suspend(struct sys_device *dev, pm_message_t state) | |
484 | { | |
485 | /* Only one CPU left, just stop that one */ | |
486 | if (nmi_enabled == 1) | |
487 | nmi_cpu_stop(NULL); | |
488 | return 0; | |
489 | } | |
490 | ||
491 | static int nmi_resume(struct sys_device *dev) | |
492 | { | |
493 | if (nmi_enabled == 1) | |
494 | nmi_cpu_start(NULL); | |
495 | return 0; | |
496 | } | |
497 | ||
498 | static struct sysdev_class oprofile_sysclass = { | |
499 | .name = "oprofile", | |
500 | .resume = nmi_resume, | |
501 | .suspend = nmi_suspend, | |
502 | }; | |
503 | ||
504 | static struct sys_device device_oprofile = { | |
505 | .id = 0, | |
506 | .cls = &oprofile_sysclass, | |
507 | }; | |
508 | ||
509 | static int __init init_sysfs(void) | |
510 | { | |
511 | int error; | |
512 | ||
513 | error = sysdev_class_register(&oprofile_sysclass); | |
514 | if (!error) | |
515 | error = sysdev_register(&device_oprofile); | |
516 | return error; | |
517 | } | |
518 | ||
519 | static void exit_sysfs(void) | |
520 | { | |
521 | sysdev_unregister(&device_oprofile); | |
522 | sysdev_class_unregister(&oprofile_sysclass); | |
523 | } | |
524 | ||
525 | #else | |
526 | #define init_sysfs() do { } while (0) | |
527 | #define exit_sysfs() do { } while (0) | |
528 | #endif /* CONFIG_PM */ | |
529 | ||
b75f53db | 530 | static int __init p4_init(char **cpu_type) |
1da177e4 LT |
531 | { |
532 | __u8 cpu_model = boot_cpu_data.x86_model; | |
533 | ||
1f3d7b60 | 534 | if (cpu_model > 6 || cpu_model == 5) |
1da177e4 LT |
535 | return 0; |
536 | ||
537 | #ifndef CONFIG_SMP | |
538 | *cpu_type = "i386/p4"; | |
539 | model = &op_p4_spec; | |
540 | return 1; | |
541 | #else | |
542 | switch (smp_num_siblings) { | |
b75f53db CM |
543 | case 1: |
544 | *cpu_type = "i386/p4"; | |
545 | model = &op_p4_spec; | |
546 | return 1; | |
547 | ||
548 | case 2: | |
549 | *cpu_type = "i386/p4-ht"; | |
550 | model = &op_p4_ht2_spec; | |
551 | return 1; | |
1da177e4 LT |
552 | } |
553 | #endif | |
554 | ||
555 | printk(KERN_INFO "oprofile: P4 HyperThreading detected with > 2 threads\n"); | |
556 | printk(KERN_INFO "oprofile: Reverting to timer mode.\n"); | |
557 | return 0; | |
558 | } | |
559 | ||
7e4e0bd5 RR |
560 | static int force_arch_perfmon; |
561 | static int force_cpu_type(const char *str, struct kernel_param *kp) | |
562 | { | |
8d7ff4f2 | 563 | if (!strcmp(str, "arch_perfmon")) { |
7e4e0bd5 RR |
564 | force_arch_perfmon = 1; |
565 | printk(KERN_INFO "oprofile: forcing architectural perfmon\n"); | |
566 | } | |
567 | ||
568 | return 0; | |
569 | } | |
570 | module_param_call(cpu_type, force_cpu_type, NULL, NULL, 0); | |
1dcdb5a9 | 571 | |
b75f53db | 572 | static int __init ppro_init(char **cpu_type) |
1da177e4 LT |
573 | { |
574 | __u8 cpu_model = boot_cpu_data.x86_model; | |
259a83a8 | 575 | struct op_x86_model_spec *spec = &op_ppro_spec; /* default */ |
1da177e4 | 576 | |
1dcdb5a9 AK |
577 | if (force_arch_perfmon && cpu_has_arch_perfmon) |
578 | return 0; | |
579 | ||
4b9f12a3 LT |
580 | switch (cpu_model) { |
581 | case 0 ... 2: | |
582 | *cpu_type = "i386/ppro"; | |
583 | break; | |
584 | case 3 ... 5: | |
585 | *cpu_type = "i386/pii"; | |
586 | break; | |
587 | case 6 ... 8: | |
3d337c65 | 588 | case 10 ... 11: |
4b9f12a3 LT |
589 | *cpu_type = "i386/piii"; |
590 | break; | |
591 | case 9: | |
3d337c65 | 592 | case 13: |
4b9f12a3 LT |
593 | *cpu_type = "i386/p6_mobile"; |
594 | break; | |
4b9f12a3 | 595 | case 14: |
64471ebe | 596 | *cpu_type = "i386/core"; |
4b9f12a3 LT |
597 | break; |
598 | case 15: case 23: | |
599 | *cpu_type = "i386/core_2"; | |
600 | break; | |
e83e452b | 601 | case 0x2e: |
6adf406f | 602 | case 26: |
802070f5 | 603 | spec = &op_arch_perfmon_spec; |
6adf406f AK |
604 | *cpu_type = "i386/core_i7"; |
605 | break; | |
606 | case 28: | |
607 | *cpu_type = "i386/atom"; | |
608 | break; | |
4b9f12a3 LT |
609 | default: |
610 | /* Unknown */ | |
1da177e4 | 611 | return 0; |
1da177e4 LT |
612 | } |
613 | ||
802070f5 | 614 | model = spec; |
1da177e4 LT |
615 | return 1; |
616 | } | |
617 | ||
405ae7d3 | 618 | /* in order to get sysfs right */ |
1da177e4 LT |
619 | static int using_nmi; |
620 | ||
96d0821c | 621 | int __init op_nmi_init(struct oprofile_operations *ops) |
1da177e4 LT |
622 | { |
623 | __u8 vendor = boot_cpu_data.x86_vendor; | |
624 | __u8 family = boot_cpu_data.x86; | |
b9917028 | 625 | char *cpu_type = NULL; |
adf5ec0b | 626 | int ret = 0; |
1da177e4 LT |
627 | |
628 | if (!cpu_has_apic) | |
629 | return -ENODEV; | |
b75f53db | 630 | |
1da177e4 | 631 | switch (vendor) { |
b75f53db CM |
632 | case X86_VENDOR_AMD: |
633 | /* Needs to be at least an Athlon (or hammer in 32bit mode) */ | |
1da177e4 | 634 | |
b75f53db | 635 | switch (family) { |
b75f53db | 636 | case 6: |
b75f53db CM |
637 | cpu_type = "i386/athlon"; |
638 | break; | |
639 | case 0xf: | |
d20f24c6 RR |
640 | /* |
641 | * Actually it could be i386/hammer too, but | |
642 | * give user space an consistent name. | |
643 | */ | |
b75f53db CM |
644 | cpu_type = "x86-64/hammer"; |
645 | break; | |
646 | case 0x10: | |
b75f53db CM |
647 | cpu_type = "x86-64/family10"; |
648 | break; | |
12f2b261 | 649 | case 0x11: |
12f2b261 BK |
650 | cpu_type = "x86-64/family11h"; |
651 | break; | |
d20f24c6 RR |
652 | default: |
653 | return -ENODEV; | |
b75f53db | 654 | } |
d20f24c6 | 655 | model = &op_amd_spec; |
b75f53db CM |
656 | break; |
657 | ||
658 | case X86_VENDOR_INTEL: | |
659 | switch (family) { | |
660 | /* Pentium IV */ | |
661 | case 0xf: | |
b9917028 | 662 | p4_init(&cpu_type); |
1da177e4 | 663 | break; |
b75f53db CM |
664 | |
665 | /* A P6-class processor */ | |
666 | case 6: | |
b9917028 | 667 | ppro_init(&cpu_type); |
1da177e4 LT |
668 | break; |
669 | ||
670 | default: | |
b9917028 | 671 | break; |
b75f53db | 672 | } |
b9917028 | 673 | |
e419294e RR |
674 | if (cpu_type) |
675 | break; | |
676 | ||
677 | if (!cpu_has_arch_perfmon) | |
b9917028 | 678 | return -ENODEV; |
e419294e RR |
679 | |
680 | /* use arch perfmon as fallback */ | |
681 | cpu_type = "i386/arch_perfmon"; | |
682 | model = &op_arch_perfmon_spec; | |
b75f53db CM |
683 | break; |
684 | ||
685 | default: | |
686 | return -ENODEV; | |
1da177e4 LT |
687 | } |
688 | ||
80a8c9ff AK |
689 | #ifdef CONFIG_SMP |
690 | register_cpu_notifier(&oprofile_cpu_nb); | |
691 | #endif | |
270d3e1a | 692 | /* default values, can be overwritten by model */ |
6e63ea4b RR |
693 | ops->create_files = nmi_create_files; |
694 | ops->setup = nmi_setup; | |
695 | ops->shutdown = nmi_shutdown; | |
696 | ops->start = nmi_start; | |
697 | ops->stop = nmi_stop; | |
698 | ops->cpu_type = cpu_type; | |
270d3e1a | 699 | |
adf5ec0b RR |
700 | if (model->init) |
701 | ret = model->init(ops); | |
702 | if (ret) | |
703 | return ret; | |
704 | ||
52471c67 RR |
705 | if (!model->num_virt_counters) |
706 | model->num_virt_counters = model->num_counters; | |
707 | ||
52805144 RR |
708 | mux_init(ops); |
709 | ||
405ae7d3 | 710 | init_sysfs(); |
1da177e4 | 711 | using_nmi = 1; |
1da177e4 LT |
712 | printk(KERN_INFO "oprofile: using NMI interrupt.\n"); |
713 | return 0; | |
714 | } | |
715 | ||
96d0821c | 716 | void op_nmi_exit(void) |
1da177e4 | 717 | { |
80a8c9ff | 718 | if (using_nmi) { |
405ae7d3 | 719 | exit_sysfs(); |
80a8c9ff AK |
720 | #ifdef CONFIG_SMP |
721 | unregister_cpu_notifier(&oprofile_cpu_nb); | |
722 | #endif | |
723 | } | |
adf5ec0b RR |
724 | if (model->exit) |
725 | model->exit(); | |
1da177e4 | 726 | } |