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1da177e4 LT |
1 | /* |
2 | * Low-Level PCI Access for i386 machines | |
3 | * | |
4 | * Copyright 1993, 1994 Drew Eckhardt | |
5 | * Visionary Computing | |
6 | * (Unix and Linux consulting and custom programming) | |
7 | * Drew@Colorado.EDU | |
8 | * +1 (303) 786-7975 | |
9 | * | |
10 | * Drew's work was sponsored by: | |
11 | * iX Multiuser Multitasking Magazine | |
12 | * Hannover, Germany | |
13 | * hm@ix.de | |
14 | * | |
15 | * Copyright 1997--2000 Martin Mares <mj@ucw.cz> | |
16 | * | |
17 | * For more information, please consult the following manuals (look at | |
18 | * http://www.pcisig.com/ for how to get them): | |
19 | * | |
20 | * PCI BIOS Specification | |
21 | * PCI Local Bus Specification | |
22 | * PCI to PCI Bridge Specification | |
23 | * PCI System Design Guide | |
24 | * | |
25 | */ | |
26 | ||
27 | #include <linux/types.h> | |
28 | #include <linux/kernel.h> | |
29 | #include <linux/pci.h> | |
30 | #include <linux/init.h> | |
31 | #include <linux/ioport.h> | |
32 | #include <linux/errno.h> | |
03d72aa1 | 33 | #include <linux/bootmem.h> |
34 | ||
35 | #include <asm/pat.h> | |
58f7c988 | 36 | #include <asm/e820.h> |
82487711 | 37 | #include <asm/pci_x86.h> |
1da177e4 | 38 | |
1da177e4 | 39 | |
036fff4c GH |
40 | static int |
41 | skip_isa_ioresource_align(struct pci_dev *dev) { | |
42 | ||
43 | if ((pci_probe & PCI_CAN_SKIP_ISA_ALIGN) && | |
11949255 | 44 | !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA)) |
036fff4c GH |
45 | return 1; |
46 | return 0; | |
47 | } | |
48 | ||
1da177e4 LT |
49 | /* |
50 | * We need to avoid collisions with `mirrored' VGA ports | |
51 | * and other strange ISA hardware, so we always want the | |
52 | * addresses to be allocated in the 0x000-0x0ff region | |
53 | * modulo 0x400. | |
54 | * | |
55 | * Why? Because some silly external IO cards only decode | |
56 | * the low 10 bits of the IO address. The 0x00-0xff region | |
57 | * is reserved for motherboard devices that decode all 16 | |
58 | * bits, so it's ok to allocate at, say, 0x2800-0x28ff, | |
59 | * but we want to try to avoid allocating at 0x2900-0x2bff | |
60 | * which might have be mirrored at 0x0100-0x03ff.. | |
61 | */ | |
62 | void | |
63 | pcibios_align_resource(void *data, struct resource *res, | |
e31dd6e4 | 64 | resource_size_t size, resource_size_t align) |
1da177e4 | 65 | { |
036fff4c GH |
66 | struct pci_dev *dev = data; |
67 | ||
1da177e4 | 68 | if (res->flags & IORESOURCE_IO) { |
e31dd6e4 | 69 | resource_size_t start = res->start; |
1da177e4 | 70 | |
036fff4c GH |
71 | if (skip_isa_ioresource_align(dev)) |
72 | return; | |
1da177e4 LT |
73 | if (start & 0x300) { |
74 | start = (start + 0x3ff) & ~0x3ff; | |
75 | res->start = start; | |
76 | } | |
77 | } | |
78 | } | |
6c00a61e | 79 | EXPORT_SYMBOL(pcibios_align_resource); |
1da177e4 LT |
80 | |
81 | /* | |
82 | * Handle resources of PCI devices. If the world were perfect, we could | |
83 | * just allocate all the resource regions and do nothing more. It isn't. | |
84 | * On the other hand, we cannot just re-allocate all devices, as it would | |
85 | * require us to know lots of host bridge internals. So we attempt to | |
86 | * keep as much of the original configuration as possible, but tweak it | |
87 | * when it's found to be wrong. | |
88 | * | |
89 | * Known BIOS problems we have to work around: | |
90 | * - I/O or memory regions not configured | |
91 | * - regions configured, but not enabled in the command register | |
92 | * - bogus I/O addresses above 64K used | |
93 | * - expansion ROMs left enabled (this may sound harmless, but given | |
94 | * the fact the PCI specs explicitly allow address decoders to be | |
95 | * shared between expansion ROMs and other resource regions, it's | |
96 | * at least dangerous) | |
97 | * | |
98 | * Our solution: | |
99 | * (1) Allocate resources for all buses behind PCI-to-PCI bridges. | |
100 | * This gives us fixed barriers on where we can allocate. | |
101 | * (2) Allocate resources for all enabled devices. If there is | |
102 | * a collision, just mark the resource as unallocated. Also | |
103 | * disable expansion ROMs during this step. | |
104 | * (3) Try to allocate resources for disabled devices. If the | |
105 | * resources were assigned correctly, everything goes well, | |
106 | * if they weren't, they won't disturb allocation of other | |
107 | * resources. | |
108 | * (4) Assign new addresses to resources which were either | |
109 | * not configured at all or misconfigured. If explicitly | |
110 | * requested by the user, configure expansion ROM address | |
111 | * as well. | |
112 | */ | |
113 | ||
114 | static void __init pcibios_allocate_bus_resources(struct list_head *bus_list) | |
115 | { | |
116 | struct pci_bus *bus; | |
117 | struct pci_dev *dev; | |
118 | int idx; | |
119 | struct resource *r, *pr; | |
120 | ||
121 | /* Depth-First Search on bus tree */ | |
122 | list_for_each_entry(bus, bus_list, node) { | |
123 | if ((dev = bus->self)) { | |
7edab2f0 RD |
124 | for (idx = PCI_BRIDGE_RESOURCES; |
125 | idx < PCI_NUM_RESOURCES; idx++) { | |
1da177e4 | 126 | r = &dev->resource[idx]; |
299de034 | 127 | if (!r->flags) |
1da177e4 LT |
128 | continue; |
129 | pr = pci_find_parent_resource(dev, r); | |
7edab2f0 RD |
130 | if (!r->start || !pr || |
131 | request_resource(pr, r) < 0) { | |
011fec74 | 132 | dev_err(&dev->dev, "BAR %d: can't allocate resource\n", idx); |
7edab2f0 RD |
133 | /* |
134 | * Something is wrong with the region. | |
135 | * Invalidate the resource to prevent | |
136 | * child resource allocations in this | |
137 | * range. | |
138 | */ | |
299de034 IK |
139 | r->flags = 0; |
140 | } | |
1da177e4 LT |
141 | } |
142 | } | |
143 | pcibios_allocate_bus_resources(&bus->children); | |
144 | } | |
145 | } | |
146 | ||
147 | static void __init pcibios_allocate_resources(int pass) | |
148 | { | |
149 | struct pci_dev *dev = NULL; | |
150 | int idx, disabled; | |
151 | u16 command; | |
152 | struct resource *r, *pr; | |
153 | ||
154 | for_each_pci_dev(dev) { | |
155 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
7edab2f0 | 156 | for (idx = 0; idx < PCI_ROM_RESOURCE; idx++) { |
1da177e4 LT |
157 | r = &dev->resource[idx]; |
158 | if (r->parent) /* Already allocated */ | |
159 | continue; | |
160 | if (!r->start) /* Address not assigned at all */ | |
161 | continue; | |
162 | if (r->flags & IORESOURCE_IO) | |
163 | disabled = !(command & PCI_COMMAND_IO); | |
164 | else | |
165 | disabled = !(command & PCI_COMMAND_MEMORY); | |
166 | if (pass == disabled) { | |
011fec74 | 167 | dev_dbg(&dev->dev, "resource %#08llx-%#08llx (f=%lx, d=%d, p=%d)\n", |
12c0b20f BH |
168 | (unsigned long long) r->start, |
169 | (unsigned long long) r->end, | |
170 | r->flags, disabled, pass); | |
1da177e4 LT |
171 | pr = pci_find_parent_resource(dev, r); |
172 | if (!pr || request_resource(pr, r) < 0) { | |
011fec74 | 173 | dev_err(&dev->dev, "BAR %d: can't allocate resource\n", idx); |
1da177e4 LT |
174 | /* We'll assign a new address later */ |
175 | r->end -= r->start; | |
176 | r->start = 0; | |
177 | } | |
178 | } | |
179 | } | |
180 | if (!pass) { | |
181 | r = &dev->resource[PCI_ROM_RESOURCE]; | |
182 | if (r->flags & IORESOURCE_ROM_ENABLE) { | |
7edab2f0 RD |
183 | /* Turn the ROM off, leave the resource region, |
184 | * but keep it unregistered. */ | |
1da177e4 | 185 | u32 reg; |
12c0b20f | 186 | dev_dbg(&dev->dev, "disabling ROM\n"); |
1da177e4 | 187 | r->flags &= ~IORESOURCE_ROM_ENABLE; |
7edab2f0 RD |
188 | pci_read_config_dword(dev, |
189 | dev->rom_base_reg, ®); | |
190 | pci_write_config_dword(dev, dev->rom_base_reg, | |
191 | reg & ~PCI_ROM_ADDRESS_ENABLE); | |
1da177e4 LT |
192 | } |
193 | } | |
194 | } | |
195 | } | |
196 | ||
197 | static int __init pcibios_assign_resources(void) | |
198 | { | |
199 | struct pci_dev *dev = NULL; | |
81d4af13 | 200 | struct resource *r, *pr; |
1da177e4 | 201 | |
81d4af13 | 202 | if (!(pci_probe & PCI_ASSIGN_ROMS)) { |
7edab2f0 RD |
203 | /* |
204 | * Try to use BIOS settings for ROMs, otherwise let | |
205 | * pci_assign_unassigned_resources() allocate the new | |
206 | * addresses. | |
207 | */ | |
81d4af13 | 208 | for_each_pci_dev(dev) { |
1da177e4 | 209 | r = &dev->resource[PCI_ROM_RESOURCE]; |
81d4af13 IK |
210 | if (!r->flags || !r->start) |
211 | continue; | |
212 | pr = pci_find_parent_resource(dev, r); | |
213 | if (!pr || request_resource(pr, r) < 0) { | |
214 | r->end -= r->start; | |
215 | r->start = 0; | |
216 | } | |
1da177e4 LT |
217 | } |
218 | } | |
81d4af13 IK |
219 | |
220 | pci_assign_unassigned_resources(); | |
221 | ||
1da177e4 LT |
222 | return 0; |
223 | } | |
224 | ||
225 | void __init pcibios_resource_survey(void) | |
226 | { | |
227 | DBG("PCI: Allocating resources\n"); | |
228 | pcibios_allocate_bus_resources(&pci_root_buses); | |
229 | pcibios_allocate_resources(0); | |
230 | pcibios_allocate_resources(1); | |
a5444d15 IM |
231 | |
232 | e820_reserve_resources_late(); | |
1da177e4 LT |
233 | } |
234 | ||
235 | /** | |
236 | * called in fs_initcall (one below subsys_initcall), | |
237 | * give a chance for motherboard reserve resources | |
238 | */ | |
239 | fs_initcall(pcibios_assign_resources); | |
240 | ||
1da177e4 LT |
241 | /* |
242 | * If we set up a device for bus mastering, we need to check the latency | |
243 | * timer as certain crappy BIOSes forget to set it properly. | |
244 | */ | |
245 | unsigned int pcibios_max_latency = 255; | |
246 | ||
247 | void pcibios_set_master(struct pci_dev *dev) | |
248 | { | |
249 | u8 lat; | |
250 | pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat); | |
251 | if (lat < 16) | |
252 | lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency; | |
253 | else if (lat > pcibios_max_latency) | |
254 | lat = pcibios_max_latency; | |
255 | else | |
256 | return; | |
12c0b20f | 257 | dev_printk(KERN_DEBUG, &dev->dev, "setting latency timer to %d\n", lat); |
1da177e4 LT |
258 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat); |
259 | } | |
260 | ||
03d72aa1 | 261 | static void pci_unmap_page_range(struct vm_area_struct *vma) |
262 | { | |
263 | u64 addr = (u64)vma->vm_pgoff << PAGE_SHIFT; | |
264 | free_memtype(addr, addr + vma->vm_end - vma->vm_start); | |
265 | } | |
266 | ||
267 | static void pci_track_mmap_page_range(struct vm_area_struct *vma) | |
268 | { | |
269 | u64 addr = (u64)vma->vm_pgoff << PAGE_SHIFT; | |
270 | unsigned long flags = pgprot_val(vma->vm_page_prot) | |
271 | & _PAGE_CACHE_MASK; | |
272 | ||
273 | reserve_memtype(addr, addr + vma->vm_end - vma->vm_start, flags, NULL); | |
274 | } | |
275 | ||
276 | static struct vm_operations_struct pci_mmap_ops = { | |
277 | .open = pci_track_mmap_page_range, | |
278 | .close = pci_unmap_page_range, | |
7ae8ed50 | 279 | .access = generic_access_phys, |
03d72aa1 | 280 | }; |
281 | ||
1da177e4 LT |
282 | int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, |
283 | enum pci_mmap_state mmap_state, int write_combine) | |
284 | { | |
285 | unsigned long prot; | |
03d72aa1 | 286 | u64 addr = vma->vm_pgoff << PAGE_SHIFT; |
287 | unsigned long len = vma->vm_end - vma->vm_start; | |
288 | unsigned long flags; | |
289 | unsigned long new_flags; | |
dee7cbb2 | 290 | int retval; |
1da177e4 LT |
291 | |
292 | /* I/O space cannot be accessed via normal processor loads and | |
293 | * stores on this platform. | |
294 | */ | |
295 | if (mmap_state == pci_mmap_io) | |
296 | return -EINVAL; | |
297 | ||
1da177e4 | 298 | prot = pgprot_val(vma->vm_page_prot); |
499f8f84 | 299 | if (pat_enabled && write_combine) |
03d72aa1 | 300 | prot |= _PAGE_CACHE_WC; |
499f8f84 | 301 | else if (pat_enabled || boot_cpu_data.x86 > 3) |
de33c442 SS |
302 | /* |
303 | * ioremap() and ioremap_nocache() defaults to UC MINUS for now. | |
304 | * To avoid attribute conflicts, request UC MINUS here | |
305 | * aswell. | |
306 | */ | |
307 | prot |= _PAGE_CACHE_UC_MINUS; | |
03d72aa1 | 308 | |
1da177e4 LT |
309 | vma->vm_page_prot = __pgprot(prot); |
310 | ||
03d72aa1 | 311 | flags = pgprot_val(vma->vm_page_prot) & _PAGE_CACHE_MASK; |
dee7cbb2 VP |
312 | retval = reserve_memtype(addr, addr + len, flags, &new_flags); |
313 | if (retval) | |
314 | return retval; | |
315 | ||
316 | if (flags != new_flags) { | |
03d72aa1 | 317 | /* |
318 | * Do not fallback to certain memory types with certain | |
319 | * requested type: | |
320 | * - request is uncached, return cannot be write-back | |
321 | * - request is uncached, return cannot be write-combine | |
322 | * - request is write-combine, return cannot be write-back | |
323 | */ | |
de33c442 SS |
324 | if ((flags == _PAGE_CACHE_UC_MINUS && |
325 | (new_flags == _PAGE_CACHE_WB)) || | |
03d72aa1 | 326 | (flags == _PAGE_CACHE_WC && |
327 | new_flags == _PAGE_CACHE_WB)) { | |
328 | free_memtype(addr, addr+len); | |
329 | return -EINVAL; | |
330 | } | |
331 | flags = new_flags; | |
332 | } | |
333 | ||
965194c1 | 334 | if (((vma->vm_pgoff < max_low_pfn_mapped) || |
f361a450 | 335 | (vma->vm_pgoff >= (1UL<<(32 - PAGE_SHIFT)) && |
965194c1 | 336 | vma->vm_pgoff < max_pfn_mapped)) && |
03d72aa1 | 337 | ioremap_change_attr((unsigned long)__va(addr), len, flags)) { |
338 | free_memtype(addr, addr + len); | |
339 | return -EINVAL; | |
340 | } | |
341 | ||
346d3882 MT |
342 | if (io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, |
343 | vma->vm_end - vma->vm_start, | |
344 | vma->vm_page_prot)) | |
1da177e4 LT |
345 | return -EAGAIN; |
346 | ||
03d72aa1 | 347 | vma->vm_ops = &pci_mmap_ops; |
348 | ||
1da177e4 LT |
349 | return 0; |
350 | } |