[deliverable/linux.git] / arch / x86 / pci / i386.c

/*
 *	Low-Level PCI Access for i386 machines
 *
 * Copyright 1993, 1994 Drew Eckhardt
 *      Visionary Computing
 *      (Unix and Linux consulting and custom programming)
 *      Drew@Colorado.EDU
 *      +1 (303) 786-7975
 *
 * Drew's work was sponsored by:
 *	iX Multiuser Multitasking Magazine
 *	Hannover, Germany
 *	hm@ix.de
 *
 * Copyright 1997--2000 Martin Mares <mj@ucw.cz>
 *
 * For more information, please consult the following manuals (look at
 * http://www.pcisig.com/ for how to get them):
 *
 * PCI BIOS Specification
 * PCI Local Bus Specification
 * PCI to PCI Bridge Specification
 * PCI System Design Guide
 *
 */

#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/errno.h>
#include <linux/bootmem.h>

#include <asm/pat.h>

#include "pci.h"

static int
skip_isa_ioresource_align(struct pci_dev *dev) {

	if ((pci_probe & PCI_CAN_SKIP_ISA_ALIGN) &&
	    !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
		return 1;
	return 0;
}

/*
 * We need to avoid collisions with `mirrored' VGA ports
 * and other strange ISA hardware, so we always want the
 * addresses to be allocated in the 0x000-0x0ff region
 * modulo 0x400.
 *
 * Why? Because some silly external IO cards only decode
 * the low 10 bits of the IO address. The 0x00-0xff region
 * is reserved for motherboard devices that decode all 16
 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
 * but we want to try to avoid allocating at 0x2900-0x2bff
 * which might have be mirrored at 0x0100-0x03ff..
 */
void
pcibios_align_resource(void *data, struct resource *res,
			resource_size_t size, resource_size_t align)
{
	struct pci_dev *dev = data;

	if (res->flags & IORESOURCE_IO) {
		resource_size_t start = res->start;

		if (skip_isa_ioresource_align(dev))
			return;
		if (start & 0x300) {
			start = (start + 0x3ff) & ~0x3ff;
			res->start = start;
		}
	}
}
EXPORT_SYMBOL(pcibios_align_resource);

/*
 *  Handle resources of PCI devices.  If the world were perfect, we could
 *  just allocate all the resource regions and do nothing more.  It isn't.
 *  On the other hand, we cannot just re-allocate all devices, as it would
 *  require us to know lots of host bridge internals.  So we attempt to
 *  keep as much of the original configuration as possible, but tweak it
 *  when it's found to be wrong.
 *
 *  Known BIOS problems we have to work around:
 *	- I/O or memory regions not configured
 *	- regions configured, but not enabled in the command register
 *	- bogus I/O addresses above 64K used
 *	- expansion ROMs left enabled (this may sound harmless, but given
 *	  the fact the PCI specs explicitly allow address decoders to be
 *	  shared between expansion ROMs and other resource regions, it's
 *	  at least dangerous)
 *
 *  Our solution:
 *	(1) Allocate resources for all buses behind PCI-to-PCI bridges.
 *	    This gives us fixed barriers on where we can allocate.
 *	(2) Allocate resources for all enabled devices.  If there is
 *	    a collision, just mark the resource as unallocated. Also
 *	    disable expansion ROMs during this step.
 *	(3) Try to allocate resources for disabled devices.  If the
 *	    resources were assigned correctly, everything goes well,
 *	    if they weren't, they won't disturb allocation of other
 *	    resources.
 *	(4) Assign new addresses to resources which were either
 *	    not configured at all or misconfigured.  If explicitly
 *	    requested by the user, configure expansion ROM address
 *	    as well.
 */

static void __init pcibios_allocate_bus_resources(struct list_head *bus_list)
{
	struct pci_bus *bus;
	struct pci_dev *dev;
	int idx;
	struct resource *r, *pr;

	/* Depth-First Search on bus tree */
	list_for_each_entry(bus, bus_list, node) {
		if ((dev = bus->self)) {
			for (idx = PCI_BRIDGE_RESOURCES;
			    idx < PCI_NUM_RESOURCES; idx++) {
				r = &dev->resource[idx];
				if (!r->flags)
					continue;
				pr = pci_find_parent_resource(dev, r);
				if (!r->start || !pr ||
				    request_resource(pr, r) < 0) {
					printk(KERN_ERR "PCI: Cannot allocate "
						"resource region %d "
						"of bridge %s\n",
						idx, pci_name(dev));
					/*
					 * Something is wrong with the region.
					 * Invalidate the resource to prevent
					 * child resource allocations in this
					 * range.
					 */
					r->flags = 0;
				}
			}
		}
		pcibios_allocate_bus_resources(&bus->children);
	}
}

static void __init pcibios_allocate_resources(int pass)
{
	struct pci_dev *dev = NULL;
	int idx, disabled;
	u16 command;
	struct resource *r, *pr;

	for_each_pci_dev(dev) {
		pci_read_config_word(dev, PCI_COMMAND, &command);
		for (idx = 0; idx < PCI_ROM_RESOURCE; idx++) {
			r = &dev->resource[idx];
			if (r->parent)		/* Already allocated */
				continue;
			if (!r->start)		/* Address not assigned at all */
				continue;
			if (r->flags & IORESOURCE_IO)
				disabled = !(command & PCI_COMMAND_IO);
			else
				disabled = !(command & PCI_COMMAND_MEMORY);
			if (pass == disabled) {
				DBG("PCI: Resource %08lx-%08lx "
				    "(f=%lx, d=%d, p=%d)\n",
				    r->start, r->end, r->flags, disabled, pass);
				pr = pci_find_parent_resource(dev, r);
				if (!pr || request_resource(pr, r) < 0) {
					printk(KERN_ERR "PCI: Cannot allocate "
						"resource region %d "
						"of device %s\n",
						idx, pci_name(dev));
					/* We'll assign a new address later */
					r->end -= r->start;
					r->start = 0;
				}
			}
		}
		if (!pass) {
			r = &dev->resource[PCI_ROM_RESOURCE];
			if (r->flags & IORESOURCE_ROM_ENABLE) {
				/* Turn the ROM off, leave the resource region,
				 * but keep it unregistered. */
				u32 reg;
				DBG("PCI: Switching off ROM of %s\n",
					pci_name(dev));
				r->flags &= ~IORESOURCE_ROM_ENABLE;
				pci_read_config_dword(dev,
						dev->rom_base_reg, &reg);
				pci_write_config_dword(dev, dev->rom_base_reg,
						reg & ~PCI_ROM_ADDRESS_ENABLE);
			}
		}
	}
}

static int __init pcibios_assign_resources(void)
{
	struct pci_dev *dev = NULL;
	struct resource *r, *pr;

	if (!(pci_probe & PCI_ASSIGN_ROMS)) {
		/*
		 * Try to use BIOS settings for ROMs, otherwise let
		 * pci_assign_unassigned_resources() allocate the new
		 * addresses.
		 */
		for_each_pci_dev(dev) {
			r = &dev->resource[PCI_ROM_RESOURCE];
			if (!r->flags || !r->start)
				continue;
			pr = pci_find_parent_resource(dev, r);
			if (!pr || request_resource(pr, r) < 0) {
				r->end -= r->start;
				r->start = 0;
			}
		}
	}

	pci_assign_unassigned_resources();

	return 0;
}

void __init pcibios_resource_survey(void)
{
	DBG("PCI: Allocating resources\n");
	pcibios_allocate_bus_resources(&pci_root_buses);
	pcibios_allocate_resources(0);
	pcibios_allocate_resources(1);
}

/**
 * called in fs_initcall (one below subsys_initcall),
 * give a chance for motherboard reserve resources
 */
fs_initcall(pcibios_assign_resources);

/*
 *  If we set up a device for bus mastering, we need to check the latency
 *  timer as certain crappy BIOSes forget to set it properly.
 */
unsigned int pcibios_max_latency = 255;

void pcibios_set_master(struct pci_dev *dev)
{
	u8 lat;
	pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
	if (lat < 16)
		lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
	else if (lat > pcibios_max_latency)
		lat = pcibios_max_latency;
	else
		return;
	printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n",
		pci_name(dev), lat);
	pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
}

static void pci_unmap_page_range(struct vm_area_struct *vma)
{
	u64 addr = (u64)vma->vm_pgoff << PAGE_SHIFT;
	free_memtype(addr, addr + vma->vm_end - vma->vm_start);
}

static void pci_track_mmap_page_range(struct vm_area_struct *vma)
{
	u64 addr = (u64)vma->vm_pgoff << PAGE_SHIFT;
	unsigned long flags = pgprot_val(vma->vm_page_prot)
						& _PAGE_CACHE_MASK;

	reserve_memtype(addr, addr + vma->vm_end - vma->vm_start, flags, NULL);
}

static struct vm_operations_struct pci_mmap_ops = {
	.open  = pci_track_mmap_page_range,
	.close = pci_unmap_page_range,
	.access = generic_access_phys,
};

int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
			enum pci_mmap_state mmap_state, int write_combine)
{
	unsigned long prot;
	u64 addr = vma->vm_pgoff << PAGE_SHIFT;
	unsigned long len = vma->vm_end - vma->vm_start;
	unsigned long flags;
	unsigned long new_flags;
	int retval;

	/* I/O space cannot be accessed via normal processor loads and
	 * stores on this platform.
	 */
	if (mmap_state == pci_mmap_io)
		return -EINVAL;

	prot = pgprot_val(vma->vm_page_prot);
	if (pat_enabled && write_combine)
		prot |= _PAGE_CACHE_WC;
	else if (pat_enabled || boot_cpu_data.x86 > 3)
		/*
		 * ioremap() and ioremap_nocache() defaults to UC MINUS for now.
		 * To avoid attribute conflicts, request UC MINUS here
		 * aswell.
		 */
		prot |= _PAGE_CACHE_UC_MINUS;

	vma->vm_page_prot = __pgprot(prot);

	flags = pgprot_val(vma->vm_page_prot) & _PAGE_CACHE_MASK;
	retval = reserve_memtype(addr, addr + len, flags, &new_flags);
	if (retval)
		return retval;

	if (flags != new_flags) {
		/*
		 * Do not fallback to certain memory types with certain
		 * requested type:
		 * - request is uncached, return cannot be write-back
		 * - request is uncached, return cannot be write-combine
		 * - request is write-combine, return cannot be write-back
		 */
		if ((flags == _PAGE_CACHE_UC_MINUS &&
		     (new_flags == _PAGE_CACHE_WB)) ||
		    (flags == _PAGE_CACHE_WC &&
		     new_flags == _PAGE_CACHE_WB)) {
			free_memtype(addr, addr+len);
			return -EINVAL;
		}
		flags = new_flags;
	}

	if (((vma->vm_pgoff < max_low_pfn_mapped) ||
	     (vma->vm_pgoff >= (1UL<<(32 - PAGE_SHIFT)) &&
	      vma->vm_pgoff < max_pfn_mapped)) &&
	    ioremap_change_attr((unsigned long)__va(addr), len, flags)) {
		free_memtype(addr, addr + len);
		return -EINVAL;
	}

	if (io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
			       vma->vm_end - vma->vm_start,
			       vma->vm_page_prot))
		return -EAGAIN;

	vma->vm_ops = &pci_mmap_ops;

	return 0;
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Low-Level PCI Access for i386 machines
	3	*
	4	* Copyright 1993, 1994 Drew Eckhardt
	5	* Visionary Computing
	6	* (Unix and Linux consulting and custom programming)
	7	* Drew@Colorado.EDU
	8	* +1 (303) 786-7975
	9	*
	10	* Drew's work was sponsored by:
	11	* iX Multiuser Multitasking Magazine
	12	* Hannover, Germany
	13	* hm@ix.de
	14	*
	15	* Copyright 1997--2000 Martin Mares <mj@ucw.cz>
	16	*
	17	* For more information, please consult the following manuals (look at
	18	* http://www.pcisig.com/ for how to get them):
	19	*
	20	* PCI BIOS Specification
	21	* PCI Local Bus Specification
	22	* PCI to PCI Bridge Specification
	23	* PCI System Design Guide
	24	*
	25	*/
	26
	27	#include <linux/types.h>
	28	#include <linux/kernel.h>
	29	#include <linux/pci.h>
	30	#include <linux/init.h>
	31	#include <linux/ioport.h>
	32	#include <linux/errno.h>
03d72aa1	33	#include <linux/bootmem.h>
	34
	35	#include <asm/pat.h>
1da177e4 LT	36
	37	#include "pci.h"
	38
036fff4c GH	39	static int
	40	skip_isa_ioresource_align(struct pci_dev *dev) {
	41
	42	if ((pci_probe & PCI_CAN_SKIP_ISA_ALIGN) &&
11949255	43	!(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
036fff4c GH	44	return 1;
	45	return 0;
	46	}
	47
1da177e4 LT	48	/*
	49	* We need to avoid collisions with `mirrored' VGA ports
	50	* and other strange ISA hardware, so we always want the
	51	* addresses to be allocated in the 0x000-0x0ff region
	52	* modulo 0x400.
	53	*
	54	* Why? Because some silly external IO cards only decode
	55	* the low 10 bits of the IO address. The 0x00-0xff region
	56	* is reserved for motherboard devices that decode all 16
	57	* bits, so it's ok to allocate at, say, 0x2800-0x28ff,
	58	* but we want to try to avoid allocating at 0x2900-0x2bff
	59	* which might have be mirrored at 0x0100-0x03ff..
	60	*/
	61	void
	62	pcibios_align_resource(void data, struct resource res,
e31dd6e4	63	resource_size_t size, resource_size_t align)
1da177e4	64	{
036fff4c GH	65	struct pci_dev *dev = data;
036fff4c GH	66
1da177e4	67	if (res->flags & IORESOURCE_IO) {
e31dd6e4	68	resource_size_t start = res->start;
1da177e4	69
036fff4c GH	70	if (skip_isa_ioresource_align(dev))
036fff4c GH	71	return;
1da177e4 LT	72	if (start & 0x300) {
	73	start = (start + 0x3ff) & ~0x3ff;
	74	res->start = start;
	75	}
	76	}
	77	}
6c00a61e	78	EXPORT_SYMBOL(pcibios_align_resource);
1da177e4 LT	79
	80	/*
	81	* Handle resources of PCI devices. If the world were perfect, we could
	82	* just allocate all the resource regions and do nothing more. It isn't.
	83	* On the other hand, we cannot just re-allocate all devices, as it would
	84	* require us to know lots of host bridge internals. So we attempt to
	85	* keep as much of the original configuration as possible, but tweak it
	86	* when it's found to be wrong.
	87	*
	88	* Known BIOS problems we have to work around:
	89	* - I/O or memory regions not configured
	90	* - regions configured, but not enabled in the command register
	91	* - bogus I/O addresses above 64K used
	92	* - expansion ROMs left enabled (this may sound harmless, but given
	93	* the fact the PCI specs explicitly allow address decoders to be
	94	* shared between expansion ROMs and other resource regions, it's
	95	* at least dangerous)
	96	*
	97	* Our solution:
	98	* (1) Allocate resources for all buses behind PCI-to-PCI bridges.
	99	* This gives us fixed barriers on where we can allocate.
	100	* (2) Allocate resources for all enabled devices. If there is
	101	* a collision, just mark the resource as unallocated. Also
	102	* disable expansion ROMs during this step.
	103	* (3) Try to allocate resources for disabled devices. If the
	104	* resources were assigned correctly, everything goes well,
	105	* if they weren't, they won't disturb allocation of other
	106	* resources.
	107	* (4) Assign new addresses to resources which were either
	108	* not configured at all or misconfigured. If explicitly
	109	* requested by the user, configure expansion ROM address
	110	* as well.
	111	*/
	112
	113	static void __init pcibios_allocate_bus_resources(struct list_head *bus_list)
	114	{
	115	struct pci_bus *bus;
	116	struct pci_dev *dev;
	117	int idx;
	118	struct resource r, pr;
	119
	120	/* Depth-First Search on bus tree */
	121	list_for_each_entry(bus, bus_list, node) {
	122	if ((dev = bus->self)) {
7edab2f0 RD	123	for (idx = PCI_BRIDGE_RESOURCES;
7edab2f0 RD	124	idx < PCI_NUM_RESOURCES; idx++) {
1da177e4	125	r = &dev->resource[idx];
299de034	126	if (!r->flags)
1da177e4 LT	127	continue;
1da177e4 LT	128	pr = pci_find_parent_resource(dev, r);
7edab2f0 RD	129	if (!r->start \|\| !pr \|\|
	130	request_resource(pr, r) < 0) {
	131	printk(KERN_ERR "PCI: Cannot allocate "
	132	"resource region %d "
	133	"of bridge %s\n",
	134	idx, pci_name(dev));
	135	/*
	136	* Something is wrong with the region.
	137	* Invalidate the resource to prevent
	138	* child resource allocations in this
	139	* range.
	140	*/
299de034 IK	141	r->flags = 0;
299de034 IK	142	}
1da177e4 LT	143	}
	144	}
	145	pcibios_allocate_bus_resources(&bus->children);
	146	}
	147	}
	148
	149	static void __init pcibios_allocate_resources(int pass)
	150	{
	151	struct pci_dev *dev = NULL;
	152	int idx, disabled;
	153	u16 command;
	154	struct resource r, pr;
	155
	156	for_each_pci_dev(dev) {
	157	pci_read_config_word(dev, PCI_COMMAND, &command);
7edab2f0	158	for (idx = 0; idx < PCI_ROM_RESOURCE; idx++) {
1da177e4 LT	159	r = &dev->resource[idx];
	160	if (r->parent) /* Already allocated */
	161	continue;
	162	if (!r->start) /* Address not assigned at all */
	163	continue;
	164	if (r->flags & IORESOURCE_IO)
	165	disabled = !(command & PCI_COMMAND_IO);
	166	else
	167	disabled = !(command & PCI_COMMAND_MEMORY);
	168	if (pass == disabled) {
7edab2f0 RD	169	DBG("PCI: Resource %08lx-%08lx "
7edab2f0 RD	170	"(f=%lx, d=%d, p=%d)\n",
1da177e4 LT	171	r->start, r->end, r->flags, disabled, pass);
	172	pr = pci_find_parent_resource(dev, r);
	173	if (!pr \|\| request_resource(pr, r) < 0) {
7edab2f0 RD	174	printk(KERN_ERR "PCI: Cannot allocate "
	175	"resource region %d "
	176	"of device %s\n",
	177	idx, pci_name(dev));
1da177e4 LT	178	/* We'll assign a new address later */
	179	r->end -= r->start;
	180	r->start = 0;
	181	}
	182	}
	183	}
	184	if (!pass) {
	185	r = &dev->resource[PCI_ROM_RESOURCE];
	186	if (r->flags & IORESOURCE_ROM_ENABLE) {
7edab2f0 RD	187	/* Turn the ROM off, leave the resource region,
7edab2f0 RD	188	* but keep it unregistered. */
1da177e4	189	u32 reg;
7edab2f0 RD	190	DBG("PCI: Switching off ROM of %s\n",
7edab2f0 RD	191	pci_name(dev));
1da177e4	192	r->flags &= ~IORESOURCE_ROM_ENABLE;
7edab2f0 RD	193	pci_read_config_dword(dev,
	194	dev->rom_base_reg, &reg);
	195	pci_write_config_dword(dev, dev->rom_base_reg,
	196	reg & ~PCI_ROM_ADDRESS_ENABLE);
1da177e4 LT	197	}
	198	}
	199	}
	200	}
	201
	202	static int __init pcibios_assign_resources(void)
	203	{
	204	struct pci_dev *dev = NULL;
81d4af13	205	struct resource r, pr;
1da177e4	206
81d4af13	207	if (!(pci_probe & PCI_ASSIGN_ROMS)) {
7edab2f0 RD	208	/*
	209	* Try to use BIOS settings for ROMs, otherwise let
	210	* pci_assign_unassigned_resources() allocate the new
	211	* addresses.
	212	*/
81d4af13	213	for_each_pci_dev(dev) {
1da177e4	214	r = &dev->resource[PCI_ROM_RESOURCE];
81d4af13 IK	215	if (!r->flags \|\| !r->start)
	216	continue;
	217	pr = pci_find_parent_resource(dev, r);
	218	if (!pr \|\| request_resource(pr, r) < 0) {
	219	r->end -= r->start;
	220	r->start = 0;
	221	}
1da177e4 LT	222	}
1da177e4 LT	223	}
81d4af13 IK	224
	225	pci_assign_unassigned_resources();
	226
1da177e4 LT	227	return 0;
	228	}
	229
	230	void __init pcibios_resource_survey(void)
	231	{
	232	DBG("PCI: Allocating resources\n");
	233	pcibios_allocate_bus_resources(&pci_root_buses);
	234	pcibios_allocate_resources(0);
	235	pcibios_allocate_resources(1);
	236	}
	237
	238	/**
	239	* called in fs_initcall (one below subsys_initcall),
	240	* give a chance for motherboard reserve resources
	241	*/
	242	fs_initcall(pcibios_assign_resources);
	243
1da177e4 LT	244	/*
	245	* If we set up a device for bus mastering, we need to check the latency
	246	* timer as certain crappy BIOSes forget to set it properly.
	247	*/
	248	unsigned int pcibios_max_latency = 255;
	249
	250	void pcibios_set_master(struct pci_dev *dev)
	251	{
	252	u8 lat;
	253	pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
	254	if (lat < 16)
	255	lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
	256	else if (lat > pcibios_max_latency)
	257	lat = pcibios_max_latency;
	258	else
	259	return;
7edab2f0 RD	260	printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n",
7edab2f0 RD	261	pci_name(dev), lat);
1da177e4 LT	262	pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
	263	}
	264
03d72aa1	265	static void pci_unmap_page_range(struct vm_area_struct *vma)
	266	{
	267	u64 addr = (u64)vma->vm_pgoff << PAGE_SHIFT;
	268	free_memtype(addr, addr + vma->vm_end - vma->vm_start);
	269	}
	270
	271	static void pci_track_mmap_page_range(struct vm_area_struct *vma)
	272	{
	273	u64 addr = (u64)vma->vm_pgoff << PAGE_SHIFT;
	274	unsigned long flags = pgprot_val(vma->vm_page_prot)
	275	& _PAGE_CACHE_MASK;
	276
	277	reserve_memtype(addr, addr + vma->vm_end - vma->vm_start, flags, NULL);
	278	}
	279
	280	static struct vm_operations_struct pci_mmap_ops = {
	281	.open = pci_track_mmap_page_range,
	282	.close = pci_unmap_page_range,
7ae8ed50	283	.access = generic_access_phys,
03d72aa1	284	};
03d72aa1	285
1da177e4 LT	286	int pci_mmap_page_range(struct pci_dev dev, struct vm_area_struct vma,
	287	enum pci_mmap_state mmap_state, int write_combine)
	288	{
	289	unsigned long prot;
03d72aa1	290	u64 addr = vma->vm_pgoff << PAGE_SHIFT;
	291	unsigned long len = vma->vm_end - vma->vm_start;
	292	unsigned long flags;
	293	unsigned long new_flags;
dee7cbb2	294	int retval;
1da177e4 LT	295
	296	/* I/O space cannot be accessed via normal processor loads and
	297	* stores on this platform.
	298	*/
	299	if (mmap_state == pci_mmap_io)
	300	return -EINVAL;
	301
1da177e4	302	prot = pgprot_val(vma->vm_page_prot);
499f8f84	303	if (pat_enabled && write_combine)
03d72aa1	304	prot \|= _PAGE_CACHE_WC;
499f8f84	305	else if (pat_enabled \|\| boot_cpu_data.x86 > 3)
de33c442 SS	306	/*
	307	* ioremap() and ioremap_nocache() defaults to UC MINUS for now.
	308	* To avoid attribute conflicts, request UC MINUS here
	309	* aswell.
	310	*/
	311	prot \|= _PAGE_CACHE_UC_MINUS;
03d72aa1	312
1da177e4 LT	313	vma->vm_page_prot = __pgprot(prot);
1da177e4 LT	314
03d72aa1	315	flags = pgprot_val(vma->vm_page_prot) & _PAGE_CACHE_MASK;
dee7cbb2 VP	316	retval = reserve_memtype(addr, addr + len, flags, &new_flags);
	317	if (retval)
	318	return retval;
	319
	320	if (flags != new_flags) {
03d72aa1	321	/*
	322	* Do not fallback to certain memory types with certain
	323	* requested type:
	324	* - request is uncached, return cannot be write-back
	325	* - request is uncached, return cannot be write-combine
	326	* - request is write-combine, return cannot be write-back
	327	*/
de33c442 SS	328	if ((flags == _PAGE_CACHE_UC_MINUS &&
de33c442 SS	329	(new_flags == _PAGE_CACHE_WB)) \|\|
03d72aa1	330	(flags == _PAGE_CACHE_WC &&
	331	new_flags == _PAGE_CACHE_WB)) {
	332	free_memtype(addr, addr+len);
	333	return -EINVAL;
	334	}
	335	flags = new_flags;
	336	}
	337
965194c1	338	if (((vma->vm_pgoff < max_low_pfn_mapped) \|\|
f361a450	339	(vma->vm_pgoff >= (1UL<<(32 - PAGE_SHIFT)) &&
965194c1	340	vma->vm_pgoff < max_pfn_mapped)) &&
03d72aa1	341	ioremap_change_attr((unsigned long)__va(addr), len, flags)) {
	342	free_memtype(addr, addr + len);
	343	return -EINVAL;
	344	}
	345
346d3882 MT	346	if (io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
	347	vma->vm_end - vma->vm_start,
	348	vma->vm_page_prot))
1da177e4 LT	349	return -EAGAIN;
1da177e4 LT	350
03d72aa1	351	vma->vm_ops = &pci_mmap_ops;
03d72aa1	352
1da177e4 LT	353	return 0;
1da177e4 LT	354	}