[deliverable/linux.git] / arch / x86 / pci / i386.c

/*
 *	Low-Level PCI Access for i386 machines
 *
 * Copyright 1993, 1994 Drew Eckhardt
 *      Visionary Computing
 *      (Unix and Linux consulting and custom programming)
 *      Drew@Colorado.EDU
 *      +1 (303) 786-7975
 *
 * Drew's work was sponsored by:
 *	iX Multiuser Multitasking Magazine
 *	Hannover, Germany
 *	hm@ix.de
 *
 * Copyright 1997--2000 Martin Mares <mj@ucw.cz>
 *
 * For more information, please consult the following manuals (look at
 * http://www.pcisig.com/ for how to get them):
 *
 * PCI BIOS Specification
 * PCI Local Bus Specification
 * PCI to PCI Bridge Specification
 * PCI System Design Guide
 *
 */

#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/export.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/errno.h>
#include <linux/bootmem.h>

#include <asm/pat.h>
#include <asm/e820.h>
#include <asm/pci_x86.h>
#include <asm/io_apic.h>


/*
 * This list of dynamic mappings is for temporarily maintaining
 * original BIOS BAR addresses for possible reinstatement.
 */
struct pcibios_fwaddrmap {
	struct list_head list;
	struct pci_dev *dev;
	resource_size_t fw_addr[DEVICE_COUNT_RESOURCE];
};

static LIST_HEAD(pcibios_fwaddrmappings);
static DEFINE_SPINLOCK(pcibios_fwaddrmap_lock);

/* Must be called with 'pcibios_fwaddrmap_lock' lock held. */
static struct pcibios_fwaddrmap *pcibios_fwaddrmap_lookup(struct pci_dev *dev)
{
	struct pcibios_fwaddrmap *map;

	WARN_ON_SMP(!spin_is_locked(&pcibios_fwaddrmap_lock));

	list_for_each_entry(map, &pcibios_fwaddrmappings, list)
		if (map->dev == dev)
			return map;

	return NULL;
}

static void
pcibios_save_fw_addr(struct pci_dev *dev, int idx, resource_size_t fw_addr)
{
	unsigned long flags;
	struct pcibios_fwaddrmap *map;

	spin_lock_irqsave(&pcibios_fwaddrmap_lock, flags);
	map = pcibios_fwaddrmap_lookup(dev);
	if (!map) {
		spin_unlock_irqrestore(&pcibios_fwaddrmap_lock, flags);
		map = kzalloc(sizeof(*map), GFP_KERNEL);
		if (!map)
			return;

		map->dev = pci_dev_get(dev);
		map->fw_addr[idx] = fw_addr;
		INIT_LIST_HEAD(&map->list);

		spin_lock_irqsave(&pcibios_fwaddrmap_lock, flags);
		list_add_tail(&map->list, &pcibios_fwaddrmappings);
	} else
		map->fw_addr[idx] = fw_addr;
	spin_unlock_irqrestore(&pcibios_fwaddrmap_lock, flags);
}

resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx)
{
	unsigned long flags;
	struct pcibios_fwaddrmap *map;
	resource_size_t fw_addr = 0;

	spin_lock_irqsave(&pcibios_fwaddrmap_lock, flags);
	map = pcibios_fwaddrmap_lookup(dev);
	if (map)
		fw_addr = map->fw_addr[idx];
	spin_unlock_irqrestore(&pcibios_fwaddrmap_lock, flags);

	return fw_addr;
}

static void pcibios_fw_addr_list_del(void)
{
	unsigned long flags;
	struct pcibios_fwaddrmap *entry, *next;

	spin_lock_irqsave(&pcibios_fwaddrmap_lock, flags);
	list_for_each_entry_safe(entry, next, &pcibios_fwaddrmappings, list) {
		list_del(&entry->list);
		pci_dev_put(entry->dev);
		kfree(entry);
	}
	spin_unlock_irqrestore(&pcibios_fwaddrmap_lock, flags);
}

static int
skip_isa_ioresource_align(struct pci_dev *dev) {

	if ((pci_probe & PCI_CAN_SKIP_ISA_ALIGN) &&
	    !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
		return 1;
	return 0;
}

/*
 * We need to avoid collisions with `mirrored' VGA ports
 * and other strange ISA hardware, so we always want the
 * addresses to be allocated in the 0x000-0x0ff region
 * modulo 0x400.
 *
 * Why? Because some silly external IO cards only decode
 * the low 10 bits of the IO address. The 0x00-0xff region
 * is reserved for motherboard devices that decode all 16
 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
 * but we want to try to avoid allocating at 0x2900-0x2bff
 * which might have be mirrored at 0x0100-0x03ff..
 */
resource_size_t
pcibios_align_resource(void *data, const struct resource *res,
			resource_size_t size, resource_size_t align)
{
	struct pci_dev *dev = data;
	resource_size_t start = res->start;

	if (res->flags & IORESOURCE_IO) {
		if (skip_isa_ioresource_align(dev))
			return start;
		if (start & 0x300)
			start = (start + 0x3ff) & ~0x3ff;
	}
	return start;
}
EXPORT_SYMBOL(pcibios_align_resource);

/*
 *  Handle resources of PCI devices.  If the world were perfect, we could
 *  just allocate all the resource regions and do nothing more.  It isn't.
 *  On the other hand, we cannot just re-allocate all devices, as it would
 *  require us to know lots of host bridge internals.  So we attempt to
 *  keep as much of the original configuration as possible, but tweak it
 *  when it's found to be wrong.
 *
 *  Known BIOS problems we have to work around:
 *	- I/O or memory regions not configured
 *	- regions configured, but not enabled in the command register
 *	- bogus I/O addresses above 64K used
 *	- expansion ROMs left enabled (this may sound harmless, but given
 *	  the fact the PCI specs explicitly allow address decoders to be
 *	  shared between expansion ROMs and other resource regions, it's
 *	  at least dangerous)
 *	- bad resource sizes or overlaps with other regions
 *
 *  Our solution:
 *	(1) Allocate resources for all buses behind PCI-to-PCI bridges.
 *	    This gives us fixed barriers on where we can allocate.
 *	(2) Allocate resources for all enabled devices.  If there is
 *	    a collision, just mark the resource as unallocated. Also
 *	    disable expansion ROMs during this step.
 *	(3) Try to allocate resources for disabled devices.  If the
 *	    resources were assigned correctly, everything goes well,
 *	    if they weren't, they won't disturb allocation of other
 *	    resources.
 *	(4) Assign new addresses to resources which were either
 *	    not configured at all or misconfigured.  If explicitly
 *	    requested by the user, configure expansion ROM address
 *	    as well.
 */

static void __init pcibios_allocate_bus_resources(struct list_head *bus_list)
{
	struct pci_bus *bus;
	struct pci_dev *dev;
	int idx;
	struct resource *r;

	/* Depth-First Search on bus tree */
	list_for_each_entry(bus, bus_list, node) {
		if ((dev = bus->self)) {
			for (idx = PCI_BRIDGE_RESOURCES;
			    idx < PCI_NUM_RESOURCES; idx++) {
				r = &dev->resource[idx];
				if (!r->flags)
					continue;
				if (!r->start ||
				    pci_claim_resource(dev, idx) < 0) {
					/*
					 * Something is wrong with the region.
					 * Invalidate the resource to prevent
					 * child resource allocations in this
					 * range.
					 */
					r->start = r->end = 0;
					r->flags = 0;
				}
			}
		}
		pcibios_allocate_bus_resources(&bus->children);
	}
}

struct pci_check_idx_range {
	int start;
	int end;
};

static void __init pcibios_allocate_resources(int pass)
{
	struct pci_dev *dev = NULL;
	int idx, disabled, i;
	u16 command;
	struct resource *r;

	struct pci_check_idx_range idx_range[] = {
		{ PCI_STD_RESOURCES, PCI_STD_RESOURCE_END },
#ifdef CONFIG_PCI_IOV
		{ PCI_IOV_RESOURCES, PCI_IOV_RESOURCE_END },
#endif
	};

	for_each_pci_dev(dev) {
		pci_read_config_word(dev, PCI_COMMAND, &command);
		for (i = 0; i < ARRAY_SIZE(idx_range); i++)
		for (idx = idx_range[i].start; idx <= idx_range[i].end; idx++) {
			r = &dev->resource[idx];
			if (r->parent)		/* Already allocated */
				continue;
			if (!r->start)		/* Address not assigned at all */
				continue;
			if (r->flags & IORESOURCE_IO)
				disabled = !(command & PCI_COMMAND_IO);
			else
				disabled = !(command & PCI_COMMAND_MEMORY);
			if (pass == disabled) {
				dev_dbg(&dev->dev,
					"BAR %d: reserving %pr (d=%d, p=%d)\n",
					idx, r, disabled, pass);
				if (pci_claim_resource(dev, idx) < 0) {
					/* We'll assign a new address later */
					pcibios_save_fw_addr(dev,
							idx, r->start);
					r->end -= r->start;
					r->start = 0;
				}
			}
		}
		if (!pass) {
			r = &dev->resource[PCI_ROM_RESOURCE];
			if (r->flags & IORESOURCE_ROM_ENABLE) {
				/* Turn the ROM off, leave the resource region,
				 * but keep it unregistered. */
				u32 reg;
				dev_dbg(&dev->dev, "disabling ROM %pR\n", r);
				r->flags &= ~IORESOURCE_ROM_ENABLE;
				pci_read_config_dword(dev,
						dev->rom_base_reg, &reg);
				pci_write_config_dword(dev, dev->rom_base_reg,
						reg & ~PCI_ROM_ADDRESS_ENABLE);
			}
		}
	}
}

static int __init pcibios_assign_resources(void)
{
	struct pci_dev *dev = NULL;
	struct resource *r;

	if (!(pci_probe & PCI_ASSIGN_ROMS)) {
		/*
		 * Try to use BIOS settings for ROMs, otherwise let
		 * pci_assign_unassigned_resources() allocate the new
		 * addresses.
		 */
		for_each_pci_dev(dev) {
			r = &dev->resource[PCI_ROM_RESOURCE];
			if (!r->flags || !r->start)
				continue;
			if (pci_claim_resource(dev, PCI_ROM_RESOURCE) < 0) {
				r->end -= r->start;
				r->start = 0;
			}
		}
	}

	pci_assign_unassigned_resources();
	pcibios_fw_addr_list_del();

	return 0;
}

void __init pcibios_resource_survey(void)
{
	DBG("PCI: Allocating resources\n");
	pcibios_allocate_bus_resources(&pci_root_buses);
	pcibios_allocate_resources(0);
	pcibios_allocate_resources(1);

	e820_reserve_resources_late();
	/*
	 * Insert the IO APIC resources after PCI initialization has
	 * occurred to handle IO APICS that are mapped in on a BAR in
	 * PCI space, but before trying to assign unassigned pci res.
	 */
	ioapic_insert_resources();
}

/**
 * called in fs_initcall (one below subsys_initcall),
 * give a chance for motherboard reserve resources
 */
fs_initcall(pcibios_assign_resources);

static const struct vm_operations_struct pci_mmap_ops = {
	.access = generic_access_phys,
};

int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
			enum pci_mmap_state mmap_state, int write_combine)
{
	unsigned long prot;

	/* I/O space cannot be accessed via normal processor loads and
	 * stores on this platform.
	 */
	if (mmap_state == pci_mmap_io)
		return -EINVAL;

	prot = pgprot_val(vma->vm_page_prot);

	/*
 	 * Return error if pat is not enabled and write_combine is requested.
 	 * Caller can followup with UC MINUS request and add a WC mtrr if there
 	 * is a free mtrr slot.
 	 */
	if (!pat_enabled && write_combine)
		return -EINVAL;

	if (pat_enabled && write_combine)
		prot |= _PAGE_CACHE_WC;
	else if (pat_enabled || boot_cpu_data.x86 > 3)
		/*
		 * ioremap() and ioremap_nocache() defaults to UC MINUS for now.
		 * To avoid attribute conflicts, request UC MINUS here
		 * as well.
		 */
		prot |= _PAGE_CACHE_UC_MINUS;

	prot |= _PAGE_IOMAP;	/* creating a mapping for IO */

	vma->vm_page_prot = __pgprot(prot);

	if (io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
			       vma->vm_end - vma->vm_start,
			       vma->vm_page_prot))
		return -EAGAIN;

	vma->vm_ops = &pci_mmap_ops;

	return 0;
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Low-Level PCI Access for i386 machines
	3	*
	4	* Copyright 1993, 1994 Drew Eckhardt
	5	* Visionary Computing
	6	* (Unix and Linux consulting and custom programming)
	7	* Drew@Colorado.EDU
	8	* +1 (303) 786-7975
	9	*
	10	* Drew's work was sponsored by:
	11	* iX Multiuser Multitasking Magazine
	12	* Hannover, Germany
	13	* hm@ix.de
	14	*
	15	* Copyright 1997--2000 Martin Mares <mj@ucw.cz>
	16	*
	17	* For more information, please consult the following manuals (look at
	18	* http://www.pcisig.com/ for how to get them):
	19	*
	20	* PCI BIOS Specification
	21	* PCI Local Bus Specification
	22	* PCI to PCI Bridge Specification
	23	* PCI System Design Guide
	24	*
	25	*/
	26
	27	#include <linux/types.h>
	28	#include <linux/kernel.h>
69c60c88	29	#include <linux/export.h>
1da177e4 LT	30	#include <linux/pci.h>
	31	#include <linux/init.h>
	32	#include <linux/ioport.h>
	33	#include <linux/errno.h>
03d72aa1	34	#include <linux/bootmem.h>
	35
	36	#include <asm/pat.h>
58f7c988	37	#include <asm/e820.h>
82487711	38	#include <asm/pci_x86.h>
857fdc53	39	#include <asm/io_apic.h>
1da177e4	40
1da177e4	41
925845bd MS	42	/*
	43	* This list of dynamic mappings is for temporarily maintaining
	44	* original BIOS BAR addresses for possible reinstatement.
	45	*/
	46	struct pcibios_fwaddrmap {
	47	struct list_head list;
	48	struct pci_dev *dev;
	49	resource_size_t fw_addr[DEVICE_COUNT_RESOURCE];
	50	};
	51
	52	static LIST_HEAD(pcibios_fwaddrmappings);
	53	static DEFINE_SPINLOCK(pcibios_fwaddrmap_lock);
	54
	55	/* Must be called with 'pcibios_fwaddrmap_lock' lock held. */
	56	static struct pcibios_fwaddrmap pcibios_fwaddrmap_lookup(struct pci_dev dev)
	57	{
	58	struct pcibios_fwaddrmap *map;
	59
867aae6e	60	WARN_ON_SMP(!spin_is_locked(&pcibios_fwaddrmap_lock));
63ab387c	61
925845bd MS	62	list_for_each_entry(map, &pcibios_fwaddrmappings, list)
	63	if (map->dev == dev)
	64	return map;
	65
	66	return NULL;
	67	}
	68
	69	static void
	70	pcibios_save_fw_addr(struct pci_dev *dev, int idx, resource_size_t fw_addr)
	71	{
	72	unsigned long flags;
	73	struct pcibios_fwaddrmap *map;
	74
	75	spin_lock_irqsave(&pcibios_fwaddrmap_lock, flags);
	76	map = pcibios_fwaddrmap_lookup(dev);
	77	if (!map) {
	78	spin_unlock_irqrestore(&pcibios_fwaddrmap_lock, flags);
	79	map = kzalloc(sizeof(*map), GFP_KERNEL);
	80	if (!map)
	81	return;
	82
	83	map->dev = pci_dev_get(dev);
	84	map->fw_addr[idx] = fw_addr;
	85	INIT_LIST_HEAD(&map->list);
	86
	87	spin_lock_irqsave(&pcibios_fwaddrmap_lock, flags);
	88	list_add_tail(&map->list, &pcibios_fwaddrmappings);
	89	} else
	90	map->fw_addr[idx] = fw_addr;
	91	spin_unlock_irqrestore(&pcibios_fwaddrmap_lock, flags);
	92	}
	93
	94	resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx)
	95	{
	96	unsigned long flags;
	97	struct pcibios_fwaddrmap *map;
	98	resource_size_t fw_addr = 0;
	99
	100	spin_lock_irqsave(&pcibios_fwaddrmap_lock, flags);
	101	map = pcibios_fwaddrmap_lookup(dev);
	102	if (map)
	103	fw_addr = map->fw_addr[idx];
	104	spin_unlock_irqrestore(&pcibios_fwaddrmap_lock, flags);
	105
	106	return fw_addr;
	107	}
	108
	109	static void pcibios_fw_addr_list_del(void)
	110	{
	111	unsigned long flags;
	112	struct pcibios_fwaddrmap entry, next;
	113
	114	spin_lock_irqsave(&pcibios_fwaddrmap_lock, flags);
	115	list_for_each_entry_safe(entry, next, &pcibios_fwaddrmappings, list) {
	116	list_del(&entry->list);
	117	pci_dev_put(entry->dev);
	118	kfree(entry);
	119	}
	120	spin_unlock_irqrestore(&pcibios_fwaddrmap_lock, flags);
	121	}
	122
036fff4c GH	123	static int
	124	skip_isa_ioresource_align(struct pci_dev *dev) {
	125
	126	if ((pci_probe & PCI_CAN_SKIP_ISA_ALIGN) &&
11949255	127	!(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
036fff4c GH	128	return 1;
	129	return 0;
	130	}
	131
1da177e4 LT	132	/*
	133	* We need to avoid collisions with `mirrored' VGA ports
	134	* and other strange ISA hardware, so we always want the
	135	* addresses to be allocated in the 0x000-0x0ff region
	136	* modulo 0x400.
	137	*
	138	* Why? Because some silly external IO cards only decode
	139	* the low 10 bits of the IO address. The 0x00-0xff region
	140	* is reserved for motherboard devices that decode all 16
	141	* bits, so it's ok to allocate at, say, 0x2800-0x28ff,
	142	* but we want to try to avoid allocating at 0x2900-0x2bff
	143	* which might have be mirrored at 0x0100-0x03ff..
	144	*/
b26b2d49	145	resource_size_t
3b7a17fc	146	pcibios_align_resource(void data, const struct resource res,
e31dd6e4	147	resource_size_t size, resource_size_t align)
1da177e4	148	{
036fff4c	149	struct pci_dev *dev = data;
d14125ec	150	resource_size_t start = res->start;
036fff4c	151
1da177e4	152	if (res->flags & IORESOURCE_IO) {
d14125ec BH	153	if (skip_isa_ioresource_align(dev))
	154	return start;
	155	if (start & 0x300)
	156	start = (start + 0x3ff) & ~0x3ff;
1da177e4	157	}
b26b2d49	158	return start;
1da177e4	159	}
6c00a61e	160	EXPORT_SYMBOL(pcibios_align_resource);
1da177e4 LT	161
	162	/*
	163	* Handle resources of PCI devices. If the world were perfect, we could
	164	* just allocate all the resource regions and do nothing more. It isn't.
	165	* On the other hand, we cannot just re-allocate all devices, as it would
	166	* require us to know lots of host bridge internals. So we attempt to
	167	* keep as much of the original configuration as possible, but tweak it
	168	* when it's found to be wrong.
	169	*
	170	* Known BIOS problems we have to work around:
	171	* - I/O or memory regions not configured
	172	* - regions configured, but not enabled in the command register
	173	* - bogus I/O addresses above 64K used
	174	* - expansion ROMs left enabled (this may sound harmless, but given
	175	* the fact the PCI specs explicitly allow address decoders to be
	176	* shared between expansion ROMs and other resource regions, it's
	177	* at least dangerous)
837c4ef1	178	* - bad resource sizes or overlaps with other regions
1da177e4 LT	179	*
	180	* Our solution:
	181	* (1) Allocate resources for all buses behind PCI-to-PCI bridges.
	182	* This gives us fixed barriers on where we can allocate.
	183	* (2) Allocate resources for all enabled devices. If there is
	184	* a collision, just mark the resource as unallocated. Also
	185	* disable expansion ROMs during this step.
	186	* (3) Try to allocate resources for disabled devices. If the
	187	* resources were assigned correctly, everything goes well,
	188	* if they weren't, they won't disturb allocation of other
	189	* resources.
	190	* (4) Assign new addresses to resources which were either
	191	* not configured at all or misconfigured. If explicitly
	192	* requested by the user, configure expansion ROM address
	193	* as well.
	194	*/
	195
	196	static void __init pcibios_allocate_bus_resources(struct list_head *bus_list)
	197	{
	198	struct pci_bus *bus;
	199	struct pci_dev *dev;
	200	int idx;
a76117df	201	struct resource *r;
1da177e4 LT	202
	203	/* Depth-First Search on bus tree */
	204	list_for_each_entry(bus, bus_list, node) {
	205	if ((dev = bus->self)) {
7edab2f0 RD	206	for (idx = PCI_BRIDGE_RESOURCES;
7edab2f0 RD	207	idx < PCI_NUM_RESOURCES; idx++) {
1da177e4	208	r = &dev->resource[idx];
299de034	209	if (!r->flags)
1da177e4	210	continue;
a76117df MW	211	if (!r->start \|\|
a76117df MW	212	pci_claim_resource(dev, idx) < 0) {
7edab2f0 RD	213	/*
	214	* Something is wrong with the region.
	215	* Invalidate the resource to prevent
	216	* child resource allocations in this
	217	* range.
	218	*/
837c4ef1	219	r->start = r->end = 0;
299de034 IK	220	r->flags = 0;
299de034 IK	221	}
1da177e4 LT	222	}
	223	}
	224	pcibios_allocate_bus_resources(&bus->children);
	225	}
	226	}
	227
575939cf YL	228	struct pci_check_idx_range {
	229	int start;
	230	int end;
	231	};
	232
1da177e4 LT	233	static void __init pcibios_allocate_resources(int pass)
	234	{
	235	struct pci_dev *dev = NULL;
575939cf	236	int idx, disabled, i;
1da177e4	237	u16 command;
a76117df	238	struct resource *r;
1da177e4	239
575939cf YL	240	struct pci_check_idx_range idx_range[] = {
	241	{ PCI_STD_RESOURCES, PCI_STD_RESOURCE_END },
	242	#ifdef CONFIG_PCI_IOV
	243	{ PCI_IOV_RESOURCES, PCI_IOV_RESOURCE_END },
	244	#endif
	245	};
	246
1da177e4 LT	247	for_each_pci_dev(dev) {
1da177e4 LT	248	pci_read_config_word(dev, PCI_COMMAND, &command);
575939cf YL	249	for (i = 0; i < ARRAY_SIZE(idx_range); i++)
575939cf YL	250	for (idx = idx_range[i].start; idx <= idx_range[i].end; idx++) {
1da177e4 LT	251	r = &dev->resource[idx];
	252	if (r->parent) /* Already allocated */
	253	continue;
	254	if (!r->start) /* Address not assigned at all */
	255	continue;
	256	if (r->flags & IORESOURCE_IO)
	257	disabled = !(command & PCI_COMMAND_IO);
	258	else
	259	disabled = !(command & PCI_COMMAND_MEMORY);
	260	if (pass == disabled) {
c7dabef8	261	dev_dbg(&dev->dev,
865df576	262	"BAR %d: reserving %pr (d=%d, p=%d)\n",
c7dabef8	263	idx, r, disabled, pass);
a76117df	264	if (pci_claim_resource(dev, idx) < 0) {
1da177e4	265	/* We'll assign a new address later */
6535943f MS	266	pcibios_save_fw_addr(dev,
6535943f MS	267	idx, r->start);
1da177e4 LT	268	r->end -= r->start;
	269	r->start = 0;
	270	}
	271	}
	272	}
	273	if (!pass) {
	274	r = &dev->resource[PCI_ROM_RESOURCE];
	275	if (r->flags & IORESOURCE_ROM_ENABLE) {
7edab2f0 RD	276	/* Turn the ROM off, leave the resource region,
7edab2f0 RD	277	* but keep it unregistered. */
1da177e4	278	u32 reg;
c7dabef8	279	dev_dbg(&dev->dev, "disabling ROM %pR\n", r);
1da177e4	280	r->flags &= ~IORESOURCE_ROM_ENABLE;
7edab2f0 RD	281	pci_read_config_dword(dev,
	282	dev->rom_base_reg, &reg);
	283	pci_write_config_dword(dev, dev->rom_base_reg,
	284	reg & ~PCI_ROM_ADDRESS_ENABLE);
1da177e4 LT	285	}
	286	}
	287	}
	288	}
	289
	290	static int __init pcibios_assign_resources(void)
	291	{
	292	struct pci_dev *dev = NULL;
a76117df	293	struct resource *r;
1da177e4	294
81d4af13	295	if (!(pci_probe & PCI_ASSIGN_ROMS)) {
7edab2f0 RD	296	/*
	297	* Try to use BIOS settings for ROMs, otherwise let
	298	* pci_assign_unassigned_resources() allocate the new
	299	* addresses.
	300	*/
81d4af13	301	for_each_pci_dev(dev) {
1da177e4	302	r = &dev->resource[PCI_ROM_RESOURCE];
81d4af13 IK	303	if (!r->flags \|\| !r->start)
81d4af13 IK	304	continue;
a76117df	305	if (pci_claim_resource(dev, PCI_ROM_RESOURCE) < 0) {
81d4af13 IK	306	r->end -= r->start;
	307	r->start = 0;
	308	}
1da177e4 LT	309	}
1da177e4 LT	310	}
81d4af13 IK	311
81d4af13 IK	312	pci_assign_unassigned_resources();
6535943f	313	pcibios_fw_addr_list_del();
81d4af13	314
1da177e4 LT	315	return 0;
	316	}
	317
	318	void __init pcibios_resource_survey(void)
	319	{
	320	DBG("PCI: Allocating resources\n");
	321	pcibios_allocate_bus_resources(&pci_root_buses);
	322	pcibios_allocate_resources(0);
	323	pcibios_allocate_resources(1);
a5444d15 IM	324
a5444d15 IM	325	e820_reserve_resources_late();
857fdc53 YL	326	/*
857fdc53 YL	327	* Insert the IO APIC resources after PCI initialization has
0d2eb44f	328	* occurred to handle IO APICS that are mapped in on a BAR in
857fdc53 YL	329	* PCI space, but before trying to assign unassigned pci res.
	330	*/
	331	ioapic_insert_resources();
1da177e4 LT	332	}
	333
	334	/**
	335	* called in fs_initcall (one below subsys_initcall),
	336	* give a chance for motherboard reserve resources
	337	*/
	338	fs_initcall(pcibios_assign_resources);
	339
f0f37e2f	340	static const struct vm_operations_struct pci_mmap_ops = {
7ae8ed50	341	.access = generic_access_phys,
03d72aa1	342	};
03d72aa1	343
1da177e4 LT	344	int pci_mmap_page_range(struct pci_dev dev, struct vm_area_struct vma,
	345	enum pci_mmap_state mmap_state, int write_combine)
	346	{
	347	unsigned long prot;
	348
	349	/* I/O space cannot be accessed via normal processor loads and
	350	* stores on this platform.
	351	*/
	352	if (mmap_state == pci_mmap_io)
	353	return -EINVAL;
	354
1da177e4	355	prot = pgprot_val(vma->vm_page_prot);
2992e545 SS	356
	357	/*
	358	* Return error if pat is not enabled and write_combine is requested.
	359	* Caller can followup with UC MINUS request and add a WC mtrr if there
	360	* is a free mtrr slot.
	361	*/
	362	if (!pat_enabled && write_combine)
	363	return -EINVAL;
	364
499f8f84	365	if (pat_enabled && write_combine)
03d72aa1	366	prot \|= _PAGE_CACHE_WC;
499f8f84	367	else if (pat_enabled \|\| boot_cpu_data.x86 > 3)
de33c442 SS	368	/*
	369	* ioremap() and ioremap_nocache() defaults to UC MINUS for now.
	370	* To avoid attribute conflicts, request UC MINUS here
0d2eb44f	371	* as well.
de33c442 SS	372	*/
de33c442 SS	373	prot \|= _PAGE_CACHE_UC_MINUS;
03d72aa1	374
5ee01f49 JF	375	prot \|= _PAGE_IOMAP; /* creating a mapping for IO */
5ee01f49 JF	376
1da177e4 LT	377	vma->vm_page_prot = __pgprot(prot);
1da177e4 LT	378
346d3882 MT	379	if (io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
	380	vma->vm_end - vma->vm_start,
	381	vma->vm_page_prot))
1da177e4 LT	382	return -EAGAIN;
1da177e4 LT	383
03d72aa1	384	vma->vm_ops = &pci_mmap_ops;
03d72aa1	385
1da177e4 LT	386	return 0;
1da177e4 LT	387	}