[deliverable/linux.git] / arch / x86 / pci / intel_mid_pci.c

/*
 * Intel MID PCI support
 *   Copyright (c) 2008 Intel Corporation
 *     Jesse Barnes <jesse.barnes@intel.com>
 *
 * Moorestown has an interesting PCI implementation:
 *   - configuration space is memory mapped (as defined by MCFG)
 *   - Lincroft devices also have a real, type 1 configuration space
 *   - Early Lincroft silicon has a type 1 access bug that will cause
 *     a hang if non-existent devices are accessed
 *   - some devices have the "fixed BAR" capability, which means
 *     they can't be relocated or modified; check for that during
 *     BAR sizing
 *
 * So, we use the MCFG space for all reads and writes, but also send
 * Lincroft writes to type 1 space.  But only read/write if the device
 * actually exists, otherwise return all 1s for reads and bit bucket
 * the writes.
 */

#include <linux/sched.h>
#include <linux/pci.h>
#include <linux/ioport.h>
#include <linux/init.h>
#include <linux/dmi.h>
#include <linux/acpi.h>
#include <linux/io.h>
#include <linux/smp.h>

#include <asm/segment.h>
#include <asm/pci_x86.h>
#include <asm/hw_irq.h>
#include <asm/io_apic.h>
#include <asm/intel-mid.h>

#define PCIE_CAP_OFFSET	0x100

/* Fixed BAR fields */
#define PCIE_VNDR_CAP_ID_FIXED_BAR 0x00	/* Fixed BAR (TBD) */
#define PCI_FIXED_BAR_0_SIZE	0x04
#define PCI_FIXED_BAR_1_SIZE	0x08
#define PCI_FIXED_BAR_2_SIZE	0x0c
#define PCI_FIXED_BAR_3_SIZE	0x10
#define PCI_FIXED_BAR_4_SIZE	0x14
#define PCI_FIXED_BAR_5_SIZE	0x1c

static int pci_soc_mode;

/**
 * fixed_bar_cap - return the offset of the fixed BAR cap if found
 * @bus: PCI bus
 * @devfn: device in question
 *
 * Look for the fixed BAR cap on @bus and @devfn, returning its offset
 * if found or 0 otherwise.
 */
static int fixed_bar_cap(struct pci_bus *bus, unsigned int devfn)
{
	int pos;
	u32 pcie_cap = 0, cap_data;

	pos = PCIE_CAP_OFFSET;

	if (!raw_pci_ext_ops)
		return 0;

	while (pos) {
		if (raw_pci_ext_ops->read(pci_domain_nr(bus), bus->number,
					  devfn, pos, 4, &pcie_cap))
			return 0;

		if (PCI_EXT_CAP_ID(pcie_cap) == 0x0000 ||
			PCI_EXT_CAP_ID(pcie_cap) == 0xffff)
			break;

		if (PCI_EXT_CAP_ID(pcie_cap) == PCI_EXT_CAP_ID_VNDR) {
			raw_pci_ext_ops->read(pci_domain_nr(bus), bus->number,
					      devfn, pos + 4, 4, &cap_data);
			if ((cap_data & 0xffff) == PCIE_VNDR_CAP_ID_FIXED_BAR)
				return pos;
		}

		pos = PCI_EXT_CAP_NEXT(pcie_cap);
	}

	return 0;
}

static int pci_device_update_fixed(struct pci_bus *bus, unsigned int devfn,
				   int reg, int len, u32 val, int offset)
{
	u32 size;
	unsigned int domain, busnum;
	int bar = (reg - PCI_BASE_ADDRESS_0) >> 2;

	domain = pci_domain_nr(bus);
	busnum = bus->number;

	if (val == ~0 && len == 4) {
		unsigned long decode;

		raw_pci_ext_ops->read(domain, busnum, devfn,
			       offset + 8 + (bar * 4), 4, &size);

		/* Turn the size into a decode pattern for the sizing code */
		if (size) {
			decode = size - 1;
			decode |= decode >> 1;
			decode |= decode >> 2;
			decode |= decode >> 4;
			decode |= decode >> 8;
			decode |= decode >> 16;
			decode++;
			decode = ~(decode - 1);
		} else {
			decode = 0;
		}

		/*
		 * If val is all ones, the core code is trying to size the reg,
		 * so update the mmconfig space with the real size.
		 *
		 * Note: this assumes the fixed size we got is a power of two.
		 */
		return raw_pci_ext_ops->write(domain, busnum, devfn, reg, 4,
				       decode);
	}

	/* This is some other kind of BAR write, so just do it. */
	return raw_pci_ext_ops->write(domain, busnum, devfn, reg, len, val);
}

/**
 * type1_access_ok - check whether to use type 1
 * @bus: bus number
 * @devfn: device & function in question
 *
 * If the bus is on a Lincroft chip and it exists, or is not on a Lincroft at
 * all, the we can go ahead with any reads & writes.  If it's on a Lincroft,
 * but doesn't exist, avoid the access altogether to keep the chip from
 * hanging.
 */
static bool type1_access_ok(unsigned int bus, unsigned int devfn, int reg)
{
	/*
	 * This is a workaround for A0 LNC bug where PCI status register does
	 * not have new CAP bit set. can not be written by SW either.
	 *
	 * PCI header type in real LNC indicates a single function device, this
	 * will prevent probing other devices under the same function in PCI
	 * shim. Therefore, use the header type in shim instead.
	 */
	if (reg >= 0x100 || reg == PCI_STATUS || reg == PCI_HEADER_TYPE)
		return false;
	if (bus == 0 && (devfn == PCI_DEVFN(2, 0)
				|| devfn == PCI_DEVFN(0, 0)
				|| devfn == PCI_DEVFN(3, 0)))
		return true;
	return false; /* Langwell on others */
}

static int pci_read(struct pci_bus *bus, unsigned int devfn, int where,
		    int size, u32 *value)
{
	if (type1_access_ok(bus->number, devfn, where))
		return pci_direct_conf1.read(pci_domain_nr(bus), bus->number,
					devfn, where, size, value);
	return raw_pci_ext_ops->read(pci_domain_nr(bus), bus->number,
			      devfn, where, size, value);
}

static int pci_write(struct pci_bus *bus, unsigned int devfn, int where,
		     int size, u32 value)
{
	int offset;

	/*
	 * On MRST, there is no PCI ROM BAR, this will cause a subsequent read
	 * to ROM BAR return 0 then being ignored.
	 */
	if (where == PCI_ROM_ADDRESS)
		return 0;

	/*
	 * Devices with fixed BARs need special handling:
	 *   - BAR sizing code will save, write ~0, read size, restore
	 *   - so writes to fixed BARs need special handling
	 *   - other writes to fixed BAR devices should go through mmconfig
	 */
	offset = fixed_bar_cap(bus, devfn);
	if (offset &&
	    (where >= PCI_BASE_ADDRESS_0 && where <= PCI_BASE_ADDRESS_5)) {
		return pci_device_update_fixed(bus, devfn, where, size, value,
					       offset);
	}

	/*
	 * On Moorestown update both real & mmconfig space
	 * Note: early Lincroft silicon can't handle type 1 accesses to
	 *       non-existent devices, so just eat the write in that case.
	 */
	if (type1_access_ok(bus->number, devfn, where))
		return pci_direct_conf1.write(pci_domain_nr(bus), bus->number,
					      devfn, where, size, value);
	return raw_pci_ext_ops->write(pci_domain_nr(bus), bus->number, devfn,
			       where, size, value);
}

static int intel_mid_pci_irq_enable(struct pci_dev *dev)
{
	int polarity;

	if (dev->irq_managed && dev->irq > 0)
		return 0;

	if (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_TANGIER)
		polarity = 0; /* active high */
	else
		polarity = 1; /* active low */

	/*
	 * MRST only have IOAPIC, the PCI irq lines are 1:1 mapped to
	 * IOAPIC RTE entries, so we just enable RTE for the device.
	 */
	if (mp_set_gsi_attr(dev->irq, 1, polarity, dev_to_node(&dev->dev)))
		return -EBUSY;
	if (mp_map_gsi_to_irq(dev->irq, IOAPIC_MAP_ALLOC) < 0)
		return -EBUSY;

	dev->irq_managed = 1;

	return 0;
}

static void intel_mid_pci_irq_disable(struct pci_dev *dev)
{
	if (!mp_should_keep_irq(&dev->dev) && dev->irq_managed &&
	    dev->irq > 0) {
		mp_unmap_irq(dev->irq);
		dev->irq_managed = 0;
	}
}

struct pci_ops intel_mid_pci_ops = {
	.read = pci_read,
	.write = pci_write,
};

/**
 * intel_mid_pci_init - installs intel_mid_pci_ops
 *
 * Moorestown has an interesting PCI implementation (see above).
 * Called when the early platform detection installs it.
 */
int __init intel_mid_pci_init(void)
{
	pr_info("Intel MID platform detected, using MID PCI ops\n");
	pci_mmcfg_late_init();
	pcibios_enable_irq = intel_mid_pci_irq_enable;
	pcibios_disable_irq = intel_mid_pci_irq_disable;
	pci_root_ops = intel_mid_pci_ops;
	pci_soc_mode = 1;
	/* Continue with standard init */
	return 1;
}

/*
 * Langwell devices are not true PCI devices; they are not subject to 10 ms
 * d3 to d0 delay required by PCI spec.
 */
static void pci_d3delay_fixup(struct pci_dev *dev)
{
	/*
	 * PCI fixups are effectively decided compile time. If we have a dual
	 * SoC/non-SoC kernel we don't want to mangle d3 on non-SoC devices.
	 */
	if (!pci_soc_mode)
		return;
	/*
	 * True PCI devices in Lincroft should allow type 1 access, the rest
	 * are Langwell fake PCI devices.
	 */
	if (type1_access_ok(dev->bus->number, dev->devfn, PCI_DEVICE_ID))
		return;
	dev->d3_delay = 0;
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_d3delay_fixup);

static void mrst_power_off_unused_dev(struct pci_dev *dev)
{
	pci_set_power_state(dev, PCI_D3hot);
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0801, mrst_power_off_unused_dev);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0809, mrst_power_off_unused_dev);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x080C, mrst_power_off_unused_dev);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0815, mrst_power_off_unused_dev);

/*
 * Langwell devices reside at fixed offsets, don't try to move them.
 */
static void pci_fixed_bar_fixup(struct pci_dev *dev)
{
	unsigned long offset;
	u32 size;
	int i;

	if (!pci_soc_mode)
		return;

	/* Must have extended configuration space */
	if (dev->cfg_size < PCIE_CAP_OFFSET + 4)
		return;

	/* Fixup the BAR sizes for fixed BAR devices and make them unmoveable */
	offset = fixed_bar_cap(dev->bus, dev->devfn);
	if (!offset || PCI_DEVFN(2, 0) == dev->devfn ||
	    PCI_DEVFN(2, 2) == dev->devfn)
		return;

	for (i = 0; i < PCI_ROM_RESOURCE; i++) {
		pci_read_config_dword(dev, offset + 8 + (i * 4), &size);
		dev->resource[i].end = dev->resource[i].start + size - 1;
		dev->resource[i].flags |= IORESOURCE_PCI_FIXED;
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_fixed_bar_fixup);
Commit	Line	Data
a712ffbc	1	/*
05454c26	2	* Intel MID PCI support
a712ffbc JB	3	* Copyright (c) 2008 Intel Corporation
	4	* Jesse Barnes <jesse.barnes@intel.com>
	5	*
	6	* Moorestown has an interesting PCI implementation:
	7	* - configuration space is memory mapped (as defined by MCFG)
	8	* - Lincroft devices also have a real, type 1 configuration space
	9	* - Early Lincroft silicon has a type 1 access bug that will cause
	10	* a hang if non-existent devices are accessed
	11	* - some devices have the "fixed BAR" capability, which means
	12	* they can't be relocated or modified; check for that during
	13	* BAR sizing
	14	*
	15	* So, we use the MCFG space for all reads and writes, but also send
	16	* Lincroft writes to type 1 space. But only read/write if the device
	17	* actually exists, otherwise return all 1s for reads and bit bucket
	18	* the writes.
	19	*/
	20
	21	#include <linux/sched.h>
	22	#include <linux/pci.h>
	23	#include <linux/ioport.h>
	24	#include <linux/init.h>
	25	#include <linux/dmi.h>
7cc24e12 VM	26	#include <linux/acpi.h>
	27	#include <linux/io.h>
	28	#include <linux/smp.h>
a712ffbc	29
a712ffbc	30	#include <asm/segment.h>
a712ffbc JB	31	#include <asm/pci_x86.h>
	32	#include <asm/hw_irq.h>
	33	#include <asm/io_apic.h>
bc20aa48	34	#include <asm/intel-mid.h>
a712ffbc JB	35
	36	#define PCIE_CAP_OFFSET 0x100
	37
	38	/* Fixed BAR fields */
	39	#define PCIE_VNDR_CAP_ID_FIXED_BAR 0x00 /* Fixed BAR (TBD) */
	40	#define PCI_FIXED_BAR_0_SIZE 0x04
	41	#define PCI_FIXED_BAR_1_SIZE 0x08
	42	#define PCI_FIXED_BAR_2_SIZE 0x0c
	43	#define PCI_FIXED_BAR_3_SIZE 0x10
	44	#define PCI_FIXED_BAR_4_SIZE 0x14
	45	#define PCI_FIXED_BAR_5_SIZE 0x1c
	46
7cc24e12	47	static int pci_soc_mode;
823806ff	48
a712ffbc JB	49	/**
	50	* fixed_bar_cap - return the offset of the fixed BAR cap if found
	51	* @bus: PCI bus
	52	* @devfn: device in question
	53	*
	54	* Look for the fixed BAR cap on @bus and @devfn, returning its offset
	55	* if found or 0 otherwise.
	56	*/
	57	static int fixed_bar_cap(struct pci_bus *bus, unsigned int devfn)
	58	{
	59	int pos;
	60	u32 pcie_cap = 0, cap_data;
	61
	62	pos = PCIE_CAP_OFFSET;
c5411382 JP	63
	64	if (!raw_pci_ext_ops)
	65	return 0;
	66
a712ffbc JB	67	while (pos) {
	68	if (raw_pci_ext_ops->read(pci_domain_nr(bus), bus->number,
	69	devfn, pos, 4, &pcie_cap))
	70	return 0;
	71
f82c3d71 JP	72	if (PCI_EXT_CAP_ID(pcie_cap) == 0x0000 \|\|
	73	PCI_EXT_CAP_ID(pcie_cap) == 0xffff)
	74	break;
a712ffbc JB	75
	76	if (PCI_EXT_CAP_ID(pcie_cap) == PCI_EXT_CAP_ID_VNDR) {
	77	raw_pci_ext_ops->read(pci_domain_nr(bus), bus->number,
	78	devfn, pos + 4, 4, &cap_data);
	79	if ((cap_data & 0xffff) == PCIE_VNDR_CAP_ID_FIXED_BAR)
	80	return pos;
	81	}
	82
f82c3d71	83	pos = PCI_EXT_CAP_NEXT(pcie_cap);
a712ffbc JB	84	}
	85
	86	return 0;
	87	}
	88
	89	static int pci_device_update_fixed(struct pci_bus *bus, unsigned int devfn,
	90	int reg, int len, u32 val, int offset)
	91	{
	92	u32 size;
	93	unsigned int domain, busnum;
	94	int bar = (reg - PCI_BASE_ADDRESS_0) >> 2;
	95
	96	domain = pci_domain_nr(bus);
	97	busnum = bus->number;
	98
	99	if (val == ~0 && len == 4) {
	100	unsigned long decode;
	101
	102	raw_pci_ext_ops->read(domain, busnum, devfn,
	103	offset + 8 + (bar * 4), 4, &size);
	104
	105	/* Turn the size into a decode pattern for the sizing code */
	106	if (size) {
	107	decode = size - 1;
	108	decode \|= decode >> 1;
	109	decode \|= decode >> 2;
	110	decode \|= decode >> 4;
	111	decode \|= decode >> 8;
	112	decode \|= decode >> 16;
	113	decode++;
	114	decode = ~(decode - 1);
	115	} else {
e4af4268	116	decode = 0;
a712ffbc JB	117	}
	118
	119	/*
	120	* If val is all ones, the core code is trying to size the reg,
	121	* so update the mmconfig space with the real size.
	122	*
	123	* Note: this assumes the fixed size we got is a power of two.
	124	*/
	125	return raw_pci_ext_ops->write(domain, busnum, devfn, reg, 4,
	126	decode);
	127	}
	128
	129	/* This is some other kind of BAR write, so just do it. */
	130	return raw_pci_ext_ops->write(domain, busnum, devfn, reg, len, val);
	131	}
	132
	133	/**
	134	* type1_access_ok - check whether to use type 1
	135	* @bus: bus number
	136	* @devfn: device & function in question
	137	*
	138	* If the bus is on a Lincroft chip and it exists, or is not on a Lincroft at
	139	* all, the we can go ahead with any reads & writes. If it's on a Lincroft,
	140	* but doesn't exist, avoid the access altogether to keep the chip from
	141	* hanging.
	142	*/
	143	static bool type1_access_ok(unsigned int bus, unsigned int devfn, int reg)
	144	{
7cc24e12 VM	145	/*
7cc24e12 VM	146	* This is a workaround for A0 LNC bug where PCI status register does
a712ffbc JB	147	* not have new CAP bit set. can not be written by SW either.
	148	*
	149	* PCI header type in real LNC indicates a single function device, this
	150	* will prevent probing other devices under the same function in PCI
	151	* shim. Therefore, use the header type in shim instead.
	152	*/
	153	if (reg >= 0x100 \|\| reg == PCI_STATUS \|\| reg == PCI_HEADER_TYPE)
6c21b176	154	return false;
f3f01175 BH	155	if (bus == 0 && (devfn == PCI_DEVFN(2, 0)
	156	\|\| devfn == PCI_DEVFN(0, 0)
	157	\|\| devfn == PCI_DEVFN(3, 0)))
6c21b176 FW	158	return true;
6c21b176 FW	159	return false; /* Langwell on others */
a712ffbc JB	160	}
	161
	162	static int pci_read(struct pci_bus *bus, unsigned int devfn, int where,
	163	int size, u32 *value)
	164	{
	165	if (type1_access_ok(bus->number, devfn, where))
	166	return pci_direct_conf1.read(pci_domain_nr(bus), bus->number,
	167	devfn, where, size, value);
	168	return raw_pci_ext_ops->read(pci_domain_nr(bus), bus->number,
	169	devfn, where, size, value);
	170	}
	171
	172	static int pci_write(struct pci_bus *bus, unsigned int devfn, int where,
	173	int size, u32 value)
	174	{
	175	int offset;
	176
7cc24e12 VM	177	/*
7cc24e12 VM	178	* On MRST, there is no PCI ROM BAR, this will cause a subsequent read
a712ffbc JB	179	* to ROM BAR return 0 then being ignored.
	180	*/
	181	if (where == PCI_ROM_ADDRESS)
	182	return 0;
	183
	184	/*
	185	* Devices with fixed BARs need special handling:
	186	* - BAR sizing code will save, write ~0, read size, restore
	187	* - so writes to fixed BARs need special handling
	188	* - other writes to fixed BAR devices should go through mmconfig
	189	*/
	190	offset = fixed_bar_cap(bus, devfn);
	191	if (offset &&
	192	(where >= PCI_BASE_ADDRESS_0 && where <= PCI_BASE_ADDRESS_5)) {
	193	return pci_device_update_fixed(bus, devfn, where, size, value,
	194	offset);
	195	}
	196
	197	/*
	198	* On Moorestown update both real & mmconfig space
	199	* Note: early Lincroft silicon can't handle type 1 accesses to
	200	* non-existent devices, so just eat the write in that case.
	201	*/
	202	if (type1_access_ok(bus->number, devfn, where))
	203	return pci_direct_conf1.write(pci_domain_nr(bus), bus->number,
	204	devfn, where, size, value);
	205	return raw_pci_ext_ops->write(pci_domain_nr(bus), bus->number, devfn,
	206	where, size, value);
	207	}
	208
712b6aa8	209	static int intel_mid_pci_irq_enable(struct pci_dev *dev)
a712ffbc	210	{
ecc527d5	211	int polarity;
a712ffbc	212
cffe0a2b JL	213	if (dev->irq_managed && dev->irq > 0)
	214	return 0;
	215
ecc527d5 JL	216	if (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_TANGIER)
	217	polarity = 0; /* active high */
	218	else
	219	polarity = 1; /* active low */
a712ffbc	220
7cc24e12 VM	221	/*
7cc24e12 VM	222	* MRST only have IOAPIC, the PCI irq lines are 1:1 mapped to
a712ffbc JB	223	* IOAPIC RTE entries, so we just enable RTE for the device.
a712ffbc JB	224	*/
ecc527d5 JL	225	if (mp_set_gsi_attr(dev->irq, 1, polarity, dev_to_node(&dev->dev)))
ecc527d5 JL	226	return -EBUSY;
1b5d3e00 JL	227	if (mp_map_gsi_to_irq(dev->irq, IOAPIC_MAP_ALLOC) < 0)
	228	return -EBUSY;
	229
cffe0a2b JL	230	dev->irq_managed = 1;
cffe0a2b JL	231
a712ffbc JB	232	return 0;
	233	}
	234
8a3e533d JL	235	static void intel_mid_pci_irq_disable(struct pci_dev *dev)
8a3e533d JL	236	{
cffe0a2b JL	237	if (!mp_should_keep_irq(&dev->dev) && dev->irq_managed &&
cffe0a2b JL	238	dev->irq > 0) {
8a3e533d	239	mp_unmap_irq(dev->irq);
cffe0a2b JL	240	dev->irq_managed = 0;
cffe0a2b JL	241	}
8a3e533d JL	242	}
8a3e533d JL	243
712b6aa8	244	struct pci_ops intel_mid_pci_ops = {
a712ffbc JB	245	.read = pci_read,
	246	.write = pci_write,
	247	};
	248
	249	/**
712b6aa8	250	* intel_mid_pci_init - installs intel_mid_pci_ops
a712ffbc JB	251	*
	252	* Moorestown has an interesting PCI implementation (see above).
	253	* Called when the early platform detection installs it.
	254	*/
712b6aa8	255	int __init intel_mid_pci_init(void)
a712ffbc	256	{
7cc24e12	257	pr_info("Intel MID platform detected, using MID PCI ops\n");
a712ffbc	258	pci_mmcfg_late_init();
712b6aa8	259	pcibios_enable_irq = intel_mid_pci_irq_enable;
8a3e533d	260	pcibios_disable_irq = intel_mid_pci_irq_disable;
712b6aa8	261	pci_root_ops = intel_mid_pci_ops;
823806ff	262	pci_soc_mode = 1;
a712ffbc JB	263	/* Continue with standard init */
	264	return 1;
	265	}
	266
7cc24e12 VM	267	/*
	268	* Langwell devices are not true PCI devices; they are not subject to 10 ms
	269	* d3 to d0 delay required by PCI spec.
990a30c5	270	*/
a18e3690	271	static void pci_d3delay_fixup(struct pci_dev *dev)
990a30c5	272	{
7cc24e12 VM	273	/*
	274	* PCI fixups are effectively decided compile time. If we have a dual
	275	* SoC/non-SoC kernel we don't want to mangle d3 on non-SoC devices.
	276	*/
	277	if (!pci_soc_mode)
	278	return;
	279	/*
	280	* True PCI devices in Lincroft should allow type 1 access, the rest
	281	* are Langwell fake PCI devices.
990a30c5 JP	282	*/
	283	if (type1_access_ok(dev->bus->number, dev->devfn, PCI_DEVICE_ID))
	284	return;
	285	dev->d3_delay = 0;
	286	}
	287	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_d3delay_fixup);
	288
a18e3690	289	static void mrst_power_off_unused_dev(struct pci_dev *dev)
990a30c5	290	{
8497f696	291	pci_set_power_state(dev, PCI_D3hot);
990a30c5 JP	292	}
	293	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0801, mrst_power_off_unused_dev);
	294	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0809, mrst_power_off_unused_dev);
	295	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x080C, mrst_power_off_unused_dev);
990a30c5 JP	296	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0815, mrst_power_off_unused_dev);
990a30c5 JP	297
a712ffbc JB	298	/*
	299	* Langwell devices reside at fixed offsets, don't try to move them.
	300	*/
a18e3690	301	static void pci_fixed_bar_fixup(struct pci_dev *dev)
a712ffbc JB	302	{
	303	unsigned long offset;
	304	u32 size;
	305	int i;
	306
823806ff AC	307	if (!pci_soc_mode)
	308	return;
	309
e9b1d5d0 PA	310	/* Must have extended configuration space */
	311	if (dev->cfg_size < PCIE_CAP_OFFSET + 4)
	312	return;
	313
a712ffbc JB	314	/* Fixup the BAR sizes for fixed BAR devices and make them unmoveable */
	315	offset = fixed_bar_cap(dev->bus, dev->devfn);
	316	if (!offset \|\| PCI_DEVFN(2, 0) == dev->devfn \|\|
	317	PCI_DEVFN(2, 2) == dev->devfn)
	318	return;
	319
	320	for (i = 0; i < PCI_ROM_RESOURCE; i++) {
	321	pci_read_config_dword(dev, offset + 8 + (i * 4), &size);
	322	dev->resource[i].end = dev->resource[i].start + size - 1;
	323	dev->resource[i].flags \|= IORESOURCE_PCI_FIXED;
	324	}
	325	}
	326	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_fixed_bar_fixup);