Commit | Line | Data |
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1da177e4 | 1 | /* |
6d48becd | 2 | * Suspend support specific for i386/x86-64. |
1da177e4 LT |
3 | * |
4 | * Distribute under GPLv2 | |
5 | * | |
cf7700fe | 6 | * Copyright (c) 2007 Rafael J. Wysocki <rjw@sisk.pl> |
a2531293 | 7 | * Copyright (c) 2002 Pavel Machek <pavel@ucw.cz> |
1da177e4 LT |
8 | * Copyright (c) 2001 Patrick Mochel <mochel@osdl.org> |
9 | */ | |
10 | ||
1da177e4 | 11 | #include <linux/suspend.h> |
f6783d20 SL |
12 | #include <linux/smp.h> |
13 | ||
3dd08325 | 14 | #include <asm/pgtable.h> |
f6783d20 | 15 | #include <asm/proto.h> |
3ebad590 | 16 | #include <asm/mtrr.h> |
f6783d20 SL |
17 | #include <asm/page.h> |
18 | #include <asm/mce.h> | |
83b8e28b | 19 | #include <asm/xcr.h> |
a8af7898 | 20 | #include <asm/suspend.h> |
1e350066 | 21 | #include <asm/debugreg.h> |
1da177e4 | 22 | |
833b2ca0 SL |
23 | #ifdef CONFIG_X86_32 |
24 | static struct saved_context saved_context; | |
cae45957 | 25 | |
833b2ca0 SL |
26 | unsigned long saved_context_ebx; |
27 | unsigned long saved_context_esp, saved_context_ebp; | |
28 | unsigned long saved_context_esi, saved_context_edi; | |
29 | unsigned long saved_context_eflags; | |
30 | #else | |
31 | /* CONFIG_X86_64 */ | |
1da177e4 | 32 | struct saved_context saved_context; |
833b2ca0 | 33 | #endif |
1da177e4 | 34 | |
5c9c9bec RW |
35 | /** |
36 | * __save_processor_state - save CPU registers before creating a | |
37 | * hibernation image and before restoring the memory state from it | |
38 | * @ctxt - structure to store the registers contents in | |
39 | * | |
40 | * NOTE: If there is a CPU register the modification of which by the | |
41 | * boot kernel (ie. the kernel used for loading the hibernation image) | |
42 | * might affect the operations of the restored target kernel (ie. the one | |
43 | * saved in the hibernation image), then its contents must be saved by this | |
44 | * function. In other words, if kernel A is hibernated and different | |
45 | * kernel B is used for loading the hibernation image into memory, the | |
46 | * kernel A's __save_processor_state() function must save all registers | |
47 | * needed by kernel A, so that it can operate correctly after the resume | |
48 | * regardless of what kernel B does in the meantime. | |
49 | */ | |
cae45957 | 50 | static void __save_processor_state(struct saved_context *ctxt) |
1da177e4 | 51 | { |
f9ebbe53 SL |
52 | #ifdef CONFIG_X86_32 |
53 | mtrr_save_fixed_ranges(NULL); | |
54 | #endif | |
1da177e4 LT |
55 | kernel_fpu_begin(); |
56 | ||
57 | /* | |
58 | * descriptor tables | |
59 | */ | |
f9ebbe53 SL |
60 | #ifdef CONFIG_X86_32 |
61 | store_gdt(&ctxt->gdt); | |
62 | store_idt(&ctxt->idt); | |
63 | #else | |
64 | /* CONFIG_X86_64 */ | |
9d1c6e7c GOC |
65 | store_gdt((struct desc_ptr *)&ctxt->gdt_limit); |
66 | store_idt((struct desc_ptr *)&ctxt->idt_limit); | |
f9ebbe53 | 67 | #endif |
9d1c6e7c | 68 | store_tr(ctxt->tr); |
1da177e4 LT |
69 | |
70 | /* XMM0..XMM15 should be handled by kernel_fpu_begin(). */ | |
1da177e4 LT |
71 | /* |
72 | * segment registers | |
73 | */ | |
f9ebbe53 SL |
74 | #ifdef CONFIG_X86_32 |
75 | savesegment(es, ctxt->es); | |
76 | savesegment(fs, ctxt->fs); | |
77 | savesegment(gs, ctxt->gs); | |
78 | savesegment(ss, ctxt->ss); | |
79 | #else | |
80 | /* CONFIG_X86_64 */ | |
1da177e4 LT |
81 | asm volatile ("movw %%ds, %0" : "=m" (ctxt->ds)); |
82 | asm volatile ("movw %%es, %0" : "=m" (ctxt->es)); | |
83 | asm volatile ("movw %%fs, %0" : "=m" (ctxt->fs)); | |
84 | asm volatile ("movw %%gs, %0" : "=m" (ctxt->gs)); | |
85 | asm volatile ("movw %%ss, %0" : "=m" (ctxt->ss)); | |
86 | ||
87 | rdmsrl(MSR_FS_BASE, ctxt->fs_base); | |
88 | rdmsrl(MSR_GS_BASE, ctxt->gs_base); | |
89 | rdmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base); | |
3ebad590 | 90 | mtrr_save_fixed_ranges(NULL); |
1da177e4 | 91 | |
f9ebbe53 SL |
92 | rdmsrl(MSR_EFER, ctxt->efer); |
93 | #endif | |
94 | ||
1da177e4 | 95 | /* |
cf7700fe | 96 | * control registers |
1da177e4 | 97 | */ |
f51c9452 GOC |
98 | ctxt->cr0 = read_cr0(); |
99 | ctxt->cr2 = read_cr2(); | |
100 | ctxt->cr3 = read_cr3(); | |
f9ebbe53 SL |
101 | #ifdef CONFIG_X86_32 |
102 | ctxt->cr4 = read_cr4_safe(); | |
103 | #else | |
104 | /* CONFIG_X86_64 */ | |
f51c9452 GOC |
105 | ctxt->cr4 = read_cr4(); |
106 | ctxt->cr8 = read_cr8(); | |
f9ebbe53 | 107 | #endif |
85a0e753 OZ |
108 | ctxt->misc_enable_saved = !rdmsrl_safe(MSR_IA32_MISC_ENABLE, |
109 | &ctxt->misc_enable); | |
1da177e4 LT |
110 | } |
111 | ||
f9ebbe53 | 112 | /* Needed by apm.c */ |
1da177e4 LT |
113 | void save_processor_state(void) |
114 | { | |
115 | __save_processor_state(&saved_context); | |
cd7240c0 | 116 | save_sched_clock_state(); |
1da177e4 | 117 | } |
f9ebbe53 SL |
118 | #ifdef CONFIG_X86_32 |
119 | EXPORT_SYMBOL(save_processor_state); | |
120 | #endif | |
1da177e4 | 121 | |
08967f94 | 122 | static void do_fpu_end(void) |
1da177e4 | 123 | { |
08967f94 | 124 | /* |
3134d04b | 125 | * Restore FPU regs if necessary. |
08967f94 SL |
126 | */ |
127 | kernel_fpu_end(); | |
1da177e4 LT |
128 | } |
129 | ||
3134d04b SL |
130 | static void fix_processor_context(void) |
131 | { | |
132 | int cpu = smp_processor_id(); | |
133 | struct tss_struct *t = &per_cpu(init_tss, cpu); | |
134 | ||
135 | set_tss_desc(cpu, t); /* | |
136 | * This just modifies memory; should not be | |
137 | * necessary. But... This is necessary, because | |
138 | * 386 hardware has concept of busy TSS or some | |
139 | * similar stupidity. | |
140 | */ | |
141 | ||
142 | #ifdef CONFIG_X86_64 | |
143 | get_cpu_gdt_table(cpu)[GDT_ENTRY_TSS].type = 9; | |
144 | ||
145 | syscall_init(); /* This sets MSR_*STAR and related */ | |
146 | #endif | |
147 | load_TR_desc(); /* This does ltr */ | |
148 | load_LDT(¤t->active_mm->context); /* This does lldt */ | |
3134d04b SL |
149 | } |
150 | ||
5c9c9bec RW |
151 | /** |
152 | * __restore_processor_state - restore the contents of CPU registers saved | |
153 | * by __save_processor_state() | |
154 | * @ctxt - structure to load the registers contents from | |
155 | */ | |
cae45957 | 156 | static void __restore_processor_state(struct saved_context *ctxt) |
1da177e4 | 157 | { |
85a0e753 OZ |
158 | if (ctxt->misc_enable_saved) |
159 | wrmsrl(MSR_IA32_MISC_ENABLE, ctxt->misc_enable); | |
1da177e4 LT |
160 | /* |
161 | * control registers | |
162 | */ | |
3134d04b SL |
163 | /* cr4 was introduced in the Pentium CPU */ |
164 | #ifdef CONFIG_X86_32 | |
165 | if (ctxt->cr4) | |
166 | write_cr4(ctxt->cr4); | |
167 | #else | |
168 | /* CONFIG X86_64 */ | |
3c321bce | 169 | wrmsrl(MSR_EFER, ctxt->efer); |
f51c9452 GOC |
170 | write_cr8(ctxt->cr8); |
171 | write_cr4(ctxt->cr4); | |
3134d04b | 172 | #endif |
f51c9452 GOC |
173 | write_cr3(ctxt->cr3); |
174 | write_cr2(ctxt->cr2); | |
175 | write_cr0(ctxt->cr0); | |
1da177e4 | 176 | |
8d783b3e PM |
177 | /* |
178 | * now restore the descriptor tables to their proper values | |
179 | * ltr is done i fix_processor_context(). | |
180 | */ | |
3134d04b SL |
181 | #ifdef CONFIG_X86_32 |
182 | load_gdt(&ctxt->gdt); | |
183 | load_idt(&ctxt->idt); | |
184 | #else | |
185 | /* CONFIG_X86_64 */ | |
9d1c6e7c GOC |
186 | load_gdt((const struct desc_ptr *)&ctxt->gdt_limit); |
187 | load_idt((const struct desc_ptr *)&ctxt->idt_limit); | |
3134d04b | 188 | #endif |
8d783b3e | 189 | |
1da177e4 LT |
190 | /* |
191 | * segment registers | |
192 | */ | |
3134d04b SL |
193 | #ifdef CONFIG_X86_32 |
194 | loadsegment(es, ctxt->es); | |
195 | loadsegment(fs, ctxt->fs); | |
196 | loadsegment(gs, ctxt->gs); | |
197 | loadsegment(ss, ctxt->ss); | |
198 | ||
199 | /* | |
200 | * sysenter MSRs | |
201 | */ | |
202 | if (boot_cpu_has(X86_FEATURE_SEP)) | |
203 | enable_sep_cpu(); | |
204 | #else | |
205 | /* CONFIG_X86_64 */ | |
1da177e4 LT |
206 | asm volatile ("movw %0, %%ds" :: "r" (ctxt->ds)); |
207 | asm volatile ("movw %0, %%es" :: "r" (ctxt->es)); | |
208 | asm volatile ("movw %0, %%fs" :: "r" (ctxt->fs)); | |
209 | load_gs_index(ctxt->gs); | |
210 | asm volatile ("movw %0, %%ss" :: "r" (ctxt->ss)); | |
211 | ||
212 | wrmsrl(MSR_FS_BASE, ctxt->fs_base); | |
213 | wrmsrl(MSR_GS_BASE, ctxt->gs_base); | |
214 | wrmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base); | |
3134d04b | 215 | #endif |
1da177e4 | 216 | |
83b8e28b SS |
217 | /* |
218 | * restore XCR0 for xsave capable cpu's. | |
219 | */ | |
220 | if (cpu_has_xsave) | |
221 | xsetbv(XCR_XFEATURE_ENABLED_MASK, pcntxt_mask); | |
222 | ||
1da177e4 LT |
223 | fix_processor_context(); |
224 | ||
225 | do_fpu_end(); | |
d0af9eed | 226 | mtrr_bp_restore(); |
1da177e4 LT |
227 | } |
228 | ||
3134d04b | 229 | /* Needed by apm.c */ |
1da177e4 LT |
230 | void restore_processor_state(void) |
231 | { | |
232 | __restore_processor_state(&saved_context); | |
cd7240c0 | 233 | restore_sched_clock_state(); |
1da177e4 | 234 | } |
3134d04b SL |
235 | #ifdef CONFIG_X86_32 |
236 | EXPORT_SYMBOL(restore_processor_state); | |
237 | #endif |