Merge tag 'efi-urgent' of git://git.kernel.org/pub/scm/linux/kernel/git/mfleming...
[deliverable/linux.git] / arch / x86 / xen / enlighten.c
CommitLineData
5ead97c8
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1/*
2 * Core of Xen paravirt_ops implementation.
3 *
4 * This file contains the xen_paravirt_ops structure itself, and the
5 * implementations for:
6 * - privileged instructions
7 * - interrupt flags
8 * - segment operations
9 * - booting and setup
10 *
11 * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007
12 */
13
38e20b07 14#include <linux/cpu.h>
5ead97c8
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15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/smp.h>
18#include <linux/preempt.h>
f120f13e 19#include <linux/hardirq.h>
5ead97c8
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20#include <linux/percpu.h>
21#include <linux/delay.h>
22#include <linux/start_kernel.h>
23#include <linux/sched.h>
6cac5a92 24#include <linux/kprobes.h>
5ead97c8
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25#include <linux/bootmem.h>
26#include <linux/module.h>
f4f97b3e
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27#include <linux/mm.h>
28#include <linux/page-flags.h>
29#include <linux/highmem.h>
b8c2d3df 30#include <linux/console.h>
5d990b62 31#include <linux/pci.h>
5a0e3ad6 32#include <linux/gfp.h>
236260b9 33#include <linux/memblock.h>
96f28bc6 34#include <linux/edd.h>
5ead97c8 35
1ccbf534 36#include <xen/xen.h>
0ec53ecf 37#include <xen/events.h>
5ead97c8 38#include <xen/interface/xen.h>
ecbf29cd 39#include <xen/interface/version.h>
5ead97c8
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40#include <xen/interface/physdev.h>
41#include <xen/interface/vcpu.h>
bee6ab53 42#include <xen/interface/memory.h>
f221b04f 43#include <xen/interface/nmi.h>
cef12ee5 44#include <xen/interface/xen-mca.h>
5ead97c8
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45#include <xen/features.h>
46#include <xen/page.h>
38e20b07 47#include <xen/hvm.h>
084a2a4e 48#include <xen/hvc-console.h>
211063dc 49#include <xen/acpi.h>
5ead97c8
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50
51#include <asm/paravirt.h>
7b6aa335 52#include <asm/apic.h>
5ead97c8 53#include <asm/page.h>
b5401a96 54#include <asm/xen/pci.h>
5ead97c8
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55#include <asm/xen/hypercall.h>
56#include <asm/xen/hypervisor.h>
57#include <asm/fixmap.h>
58#include <asm/processor.h>
707ebbc8 59#include <asm/proto.h>
1153968a 60#include <asm/msr-index.h>
6cac5a92 61#include <asm/traps.h>
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62#include <asm/setup.h>
63#include <asm/desc.h>
817a824b 64#include <asm/pgalloc.h>
5ead97c8 65#include <asm/pgtable.h>
f87e4cac 66#include <asm/tlbflush.h>
fefa629a 67#include <asm/reboot.h>
577eebea 68#include <asm/stackprotector.h>
bee6ab53 69#include <asm/hypervisor.h>
f221b04f 70#include <asm/mach_traps.h>
73c154c6 71#include <asm/mwait.h>
76a8df7b 72#include <asm/pci_x86.h>
c79c4982 73#include <asm/pat.h>
73c154c6
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74
75#ifdef CONFIG_ACPI
76#include <linux/acpi.h>
77#include <asm/acpi.h>
78#include <acpi/pdc_intel.h>
79#include <acpi/processor.h>
80#include <xen/interface/platform.h>
81#endif
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82
83#include "xen-ops.h"
3b827c1b 84#include "mmu.h"
f447d56d 85#include "smp.h"
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86#include "multicalls.h"
87
88EXPORT_SYMBOL_GPL(hypercall_page);
89
a520996a
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90/*
91 * Pointer to the xen_vcpu_info structure or
92 * &HYPERVISOR_shared_info->vcpu_info[cpu]. See xen_hvm_init_shared_info
93 * and xen_vcpu_setup for details. By default it points to share_info->vcpu_info
94 * but if the hypervisor supports VCPUOP_register_vcpu_info then it can point
95 * to xen_vcpu_info. The pointer is used in __xen_evtchn_do_upcall to
96 * acknowledge pending events.
97 * Also more subtly it is used by the patched version of irq enable/disable
98 * e.g. xen_irq_enable_direct and xen_iret in PV mode.
99 *
100 * The desire to be able to do those mask/unmask operations as a single
101 * instruction by using the per-cpu offset held in %gs is the real reason
102 * vcpu info is in a per-cpu pointer and the original reason for this
103 * hypercall.
104 *
105 */
5ead97c8 106DEFINE_PER_CPU(struct vcpu_info *, xen_vcpu);
a520996a
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107
108/*
109 * Per CPU pages used if hypervisor supports VCPUOP_register_vcpu_info
110 * hypercall. This can be used both in PV and PVHVM mode. The structure
111 * overrides the default per_cpu(xen_vcpu, cpu) value.
112 */
5ead97c8 113DEFINE_PER_CPU(struct vcpu_info, xen_vcpu_info);
9f79991d 114
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115enum xen_domain_type xen_domain_type = XEN_NATIVE;
116EXPORT_SYMBOL_GPL(xen_domain_type);
117
7e77506a
IC
118unsigned long *machine_to_phys_mapping = (void *)MACH2PHYS_VIRT_START;
119EXPORT_SYMBOL(machine_to_phys_mapping);
ccbcdf7c
JB
120unsigned long machine_to_phys_nr;
121EXPORT_SYMBOL(machine_to_phys_nr);
7e77506a 122
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123struct start_info *xen_start_info;
124EXPORT_SYMBOL_GPL(xen_start_info);
125
a0d695c8 126struct shared_info xen_dummy_shared_info;
60223a32 127
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128void *xen_initial_gdt;
129
bee6ab53 130RESERVE_BRK(shared_info_page_brk, PAGE_SIZE);
38e20b07
SY
131__read_mostly int xen_have_vector_callback;
132EXPORT_SYMBOL_GPL(xen_have_vector_callback);
bee6ab53 133
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134/*
135 * Point at some empty memory to start with. We map the real shared_info
136 * page as soon as fixmap is up and running.
137 */
4648da7c 138struct shared_info *HYPERVISOR_shared_info = &xen_dummy_shared_info;
60223a32
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139
140/*
141 * Flag to determine whether vcpu info placement is available on all
142 * VCPUs. We assume it is to start with, and then set it to zero on
143 * the first failure. This is because it can succeed on some VCPUs
144 * and not others, since it can involve hypervisor memory allocation,
145 * or because the guest failed to guarantee all the appropriate
146 * constraints on all VCPUs (ie buffer can't cross a page boundary).
147 *
148 * Note that any particular CPU may be using a placed vcpu structure,
149 * but we can only optimise if the all are.
150 *
151 * 0: not available, 1: available
152 */
e4d04071 153static int have_vcpu_info_placement = 1;
60223a32 154
1c32cdc6
DV
155struct tls_descs {
156 struct desc_struct desc[3];
157};
158
159/*
160 * Updating the 3 TLS descriptors in the GDT on every task switch is
161 * surprisingly expensive so we avoid updating them if they haven't
162 * changed. Since Xen writes different descriptors than the one
163 * passed in the update_descriptor hypercall we keep shadow copies to
164 * compare against.
165 */
166static DEFINE_PER_CPU(struct tls_descs, shadow_tls_desc);
167
c06ee78d
MR
168static void clamp_max_cpus(void)
169{
170#ifdef CONFIG_SMP
171 if (setup_max_cpus > MAX_VIRT_CPUS)
172 setup_max_cpus = MAX_VIRT_CPUS;
173#endif
174}
175
9c7a7942 176static void xen_vcpu_setup(int cpu)
5ead97c8 177{
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178 struct vcpu_register_vcpu_info info;
179 int err;
180 struct vcpu_info *vcpup;
181
a0d695c8 182 BUG_ON(HYPERVISOR_shared_info == &xen_dummy_shared_info);
60223a32 183
7f1fc268
KRW
184 /*
185 * This path is called twice on PVHVM - first during bootup via
186 * smp_init -> xen_hvm_cpu_notify, and then if the VCPU is being
187 * hotplugged: cpu_up -> xen_hvm_cpu_notify.
188 * As we can only do the VCPUOP_register_vcpu_info once lets
189 * not over-write its result.
190 *
191 * For PV it is called during restore (xen_vcpu_restore) and bootup
192 * (xen_setup_vcpu_info_placement). The hotplug mechanism does not
193 * use this function.
194 */
195 if (xen_hvm_domain()) {
196 if (per_cpu(xen_vcpu, cpu) == &per_cpu(xen_vcpu_info, cpu))
197 return;
198 }
c06ee78d
MR
199 if (cpu < MAX_VIRT_CPUS)
200 per_cpu(xen_vcpu,cpu) = &HYPERVISOR_shared_info->vcpu_info[cpu];
60223a32 201
c06ee78d
MR
202 if (!have_vcpu_info_placement) {
203 if (cpu >= MAX_VIRT_CPUS)
204 clamp_max_cpus();
205 return;
206 }
60223a32 207
c06ee78d 208 vcpup = &per_cpu(xen_vcpu_info, cpu);
9976b39b 209 info.mfn = arbitrary_virt_to_mfn(vcpup);
60223a32
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210 info.offset = offset_in_page(vcpup);
211
60223a32
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212 /* Check to see if the hypervisor will put the vcpu_info
213 structure where we want it, which allows direct access via
a520996a
KRW
214 a percpu-variable.
215 N.B. This hypercall can _only_ be called once per CPU. Subsequent
216 calls will error out with -EINVAL. This is due to the fact that
217 hypervisor has no unregister variant and this hypercall does not
218 allow to over-write info.mfn and info.offset.
219 */
60223a32
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220 err = HYPERVISOR_vcpu_op(VCPUOP_register_vcpu_info, cpu, &info);
221
222 if (err) {
223 printk(KERN_DEBUG "register_vcpu_info failed: err=%d\n", err);
224 have_vcpu_info_placement = 0;
c06ee78d 225 clamp_max_cpus();
60223a32
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226 } else {
227 /* This cpu is using the registered vcpu info, even if
228 later ones fail to. */
229 per_cpu(xen_vcpu, cpu) = vcpup;
60223a32 230 }
5ead97c8
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231}
232
9c7a7942
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233/*
234 * On restore, set the vcpu placement up again.
235 * If it fails, then we're in a bad state, since
236 * we can't back out from using it...
237 */
238void xen_vcpu_restore(void)
239{
3905bb2a 240 int cpu;
9c7a7942 241
9d328a94 242 for_each_possible_cpu(cpu) {
3905bb2a 243 bool other_cpu = (cpu != smp_processor_id());
9d328a94 244 bool is_up = HYPERVISOR_vcpu_op(VCPUOP_is_up, cpu, NULL);
9c7a7942 245
9d328a94 246 if (other_cpu && is_up &&
3905bb2a
JF
247 HYPERVISOR_vcpu_op(VCPUOP_down, cpu, NULL))
248 BUG();
9c7a7942 249
3905bb2a 250 xen_setup_runstate_info(cpu);
9c7a7942 251
3905bb2a 252 if (have_vcpu_info_placement)
9c7a7942 253 xen_vcpu_setup(cpu);
9c7a7942 254
9d328a94 255 if (other_cpu && is_up &&
3905bb2a
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256 HYPERVISOR_vcpu_op(VCPUOP_up, cpu, NULL))
257 BUG();
9c7a7942
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258 }
259}
260
5ead97c8
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261static void __init xen_banner(void)
262{
95c7c23b
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263 unsigned version = HYPERVISOR_xen_version(XENVER_version, NULL);
264 struct xen_extraversion extra;
265 HYPERVISOR_xen_version(XENVER_extraversion, &extra);
266
d285d683
MR
267 pr_info("Booting paravirtualized kernel %son %s\n",
268 xen_feature(XENFEAT_auto_translated_physmap) ?
269 "with PVH extensions " : "", pv_info.name);
95c7c23b
JF
270 printk(KERN_INFO "Xen version: %d.%d%s%s\n",
271 version >> 16, version & 0xffff, extra.extraversion,
e57778a1 272 xen_feature(XENFEAT_mmu_pt_update_preserve_ad) ? " (preserve-AD)" : "");
5ead97c8 273}
394b40f6
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274/* Check if running on Xen version (major, minor) or later */
275bool
276xen_running_on_version_or_later(unsigned int major, unsigned int minor)
277{
278 unsigned int version;
279
280 if (!xen_domain())
281 return false;
282
283 version = HYPERVISOR_xen_version(XENVER_version, NULL);
284 if ((((version >> 16) == major) && ((version & 0xffff) >= minor)) ||
285 ((version >> 16) > major))
286 return true;
287 return false;
288}
5ead97c8 289
5e626254
AP
290#define CPUID_THERM_POWER_LEAF 6
291#define APERFMPERF_PRESENT 0
292
e826fe1b
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293static __read_mostly unsigned int cpuid_leaf1_edx_mask = ~0;
294static __read_mostly unsigned int cpuid_leaf1_ecx_mask = ~0;
295
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KRW
296static __read_mostly unsigned int cpuid_leaf1_ecx_set_mask;
297static __read_mostly unsigned int cpuid_leaf5_ecx_val;
298static __read_mostly unsigned int cpuid_leaf5_edx_val;
299
65ea5b03
PA
300static void xen_cpuid(unsigned int *ax, unsigned int *bx,
301 unsigned int *cx, unsigned int *dx)
5ead97c8 302{
82d64699 303 unsigned maskebx = ~0;
e826fe1b 304 unsigned maskecx = ~0;
5ead97c8 305 unsigned maskedx = ~0;
73c154c6 306 unsigned setecx = 0;
5ead97c8
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307 /*
308 * Mask out inconvenient features, to try and disable as many
309 * unsupported kernel subsystems as possible.
310 */
82d64699
JF
311 switch (*ax) {
312 case 1:
e826fe1b 313 maskecx = cpuid_leaf1_ecx_mask;
73c154c6 314 setecx = cpuid_leaf1_ecx_set_mask;
e826fe1b 315 maskedx = cpuid_leaf1_edx_mask;
82d64699
JF
316 break;
317
73c154c6
KRW
318 case CPUID_MWAIT_LEAF:
319 /* Synthesize the values.. */
320 *ax = 0;
321 *bx = 0;
322 *cx = cpuid_leaf5_ecx_val;
323 *dx = cpuid_leaf5_edx_val;
324 return;
325
5e626254
AP
326 case CPUID_THERM_POWER_LEAF:
327 /* Disabling APERFMPERF for kernel usage */
328 maskecx = ~(1 << APERFMPERF_PRESENT);
329 break;
330
82d64699
JF
331 case 0xb:
332 /* Suppress extended topology stuff */
333 maskebx = 0;
334 break;
e826fe1b 335 }
5ead97c8
JF
336
337 asm(XEN_EMULATE_PREFIX "cpuid"
65ea5b03
PA
338 : "=a" (*ax),
339 "=b" (*bx),
340 "=c" (*cx),
341 "=d" (*dx)
342 : "0" (*ax), "2" (*cx));
e826fe1b 343
82d64699 344 *bx &= maskebx;
e826fe1b 345 *cx &= maskecx;
73c154c6 346 *cx |= setecx;
65ea5b03 347 *dx &= maskedx;
73c154c6 348
5ead97c8
JF
349}
350
73c154c6
KRW
351static bool __init xen_check_mwait(void)
352{
e3aa4e61 353#ifdef CONFIG_ACPI
73c154c6
KRW
354 struct xen_platform_op op = {
355 .cmd = XENPF_set_processor_pminfo,
356 .u.set_pminfo.id = -1,
357 .u.set_pminfo.type = XEN_PM_PDC,
358 };
359 uint32_t buf[3];
360 unsigned int ax, bx, cx, dx;
361 unsigned int mwait_mask;
362
363 /* We need to determine whether it is OK to expose the MWAIT
364 * capability to the kernel to harvest deeper than C3 states from ACPI
365 * _CST using the processor_harvest_xen.c module. For this to work, we
366 * need to gather the MWAIT_LEAF values (which the cstate.c code
367 * checks against). The hypervisor won't expose the MWAIT flag because
368 * it would break backwards compatibility; so we will find out directly
369 * from the hardware and hypercall.
370 */
371 if (!xen_initial_domain())
372 return false;
373
e3aa4e61
LJ
374 /*
375 * When running under platform earlier than Xen4.2, do not expose
376 * mwait, to avoid the risk of loading native acpi pad driver
377 */
378 if (!xen_running_on_version_or_later(4, 2))
379 return false;
380
73c154c6
KRW
381 ax = 1;
382 cx = 0;
383
384 native_cpuid(&ax, &bx, &cx, &dx);
385
386 mwait_mask = (1 << (X86_FEATURE_EST % 32)) |
387 (1 << (X86_FEATURE_MWAIT % 32));
388
389 if ((cx & mwait_mask) != mwait_mask)
390 return false;
391
392 /* We need to emulate the MWAIT_LEAF and for that we need both
393 * ecx and edx. The hypercall provides only partial information.
394 */
395
396 ax = CPUID_MWAIT_LEAF;
397 bx = 0;
398 cx = 0;
399 dx = 0;
400
401 native_cpuid(&ax, &bx, &cx, &dx);
402
403 /* Ask the Hypervisor whether to clear ACPI_PDC_C_C2C3_FFH. If so,
404 * don't expose MWAIT_LEAF and let ACPI pick the IOPORT version of C3.
405 */
406 buf[0] = ACPI_PDC_REVISION_ID;
407 buf[1] = 1;
408 buf[2] = (ACPI_PDC_C_CAPABILITY_SMP | ACPI_PDC_EST_CAPABILITY_SWSMP);
409
410 set_xen_guest_handle(op.u.set_pminfo.pdc, buf);
411
412 if ((HYPERVISOR_dom0_op(&op) == 0) &&
413 (buf[2] & (ACPI_PDC_C_C1_FFH | ACPI_PDC_C_C2C3_FFH))) {
414 cpuid_leaf5_ecx_val = cx;
415 cpuid_leaf5_edx_val = dx;
416 }
417 return true;
418#else
419 return false;
420#endif
421}
ad3062a0 422static void __init xen_init_cpuid_mask(void)
e826fe1b
JF
423{
424 unsigned int ax, bx, cx, dx;
947ccf9c 425 unsigned int xsave_mask;
e826fe1b
JF
426
427 cpuid_leaf1_edx_mask =
cef12ee5 428 ~((1 << X86_FEATURE_MTRR) | /* disable MTRR */
e826fe1b
JF
429 (1 << X86_FEATURE_ACC)); /* thermal monitoring */
430
431 if (!xen_initial_domain())
432 cpuid_leaf1_edx_mask &=
6efa20e4 433 ~((1 << X86_FEATURE_ACPI)); /* disable ACPI */
4ea9b9ac
ZD
434
435 cpuid_leaf1_ecx_mask &= ~(1 << (X86_FEATURE_X2APIC % 32));
436
947ccf9c 437 ax = 1;
5e287830 438 cx = 0;
d285d683 439 cpuid(1, &ax, &bx, &cx, &dx);
e826fe1b 440
947ccf9c
SH
441 xsave_mask =
442 (1 << (X86_FEATURE_XSAVE % 32)) |
443 (1 << (X86_FEATURE_OSXSAVE % 32));
444
445 /* Xen will set CR4.OSXSAVE if supported and not disabled by force */
446 if ((cx & xsave_mask) != xsave_mask)
447 cpuid_leaf1_ecx_mask &= ~xsave_mask; /* disable XSAVE & OSXSAVE */
73c154c6
KRW
448 if (xen_check_mwait())
449 cpuid_leaf1_ecx_set_mask = (1 << (X86_FEATURE_MWAIT % 32));
e826fe1b
JF
450}
451
5ead97c8
JF
452static void xen_set_debugreg(int reg, unsigned long val)
453{
454 HYPERVISOR_set_debugreg(reg, val);
455}
456
457static unsigned long xen_get_debugreg(int reg)
458{
459 return HYPERVISOR_get_debugreg(reg);
460}
461
224101ed 462static void xen_end_context_switch(struct task_struct *next)
5ead97c8 463{
5ead97c8 464 xen_mc_flush();
224101ed 465 paravirt_end_context_switch(next);
5ead97c8
JF
466}
467
468static unsigned long xen_store_tr(void)
469{
470 return 0;
471}
472
a05d2eba 473/*
cef43bf6
JF
474 * Set the page permissions for a particular virtual address. If the
475 * address is a vmalloc mapping (or other non-linear mapping), then
476 * find the linear mapping of the page and also set its protections to
477 * match.
a05d2eba
JF
478 */
479static void set_aliased_prot(void *v, pgprot_t prot)
480{
481 int level;
482 pte_t *ptep;
483 pte_t pte;
484 unsigned long pfn;
485 struct page *page;
486
487 ptep = lookup_address((unsigned long)v, &level);
488 BUG_ON(ptep == NULL);
489
490 pfn = pte_pfn(*ptep);
491 page = pfn_to_page(pfn);
492
493 pte = pfn_pte(pfn, prot);
494
495 if (HYPERVISOR_update_va_mapping((unsigned long)v, pte, 0))
496 BUG();
497
498 if (!PageHighMem(page)) {
499 void *av = __va(PFN_PHYS(pfn));
500
501 if (av != v)
502 if (HYPERVISOR_update_va_mapping((unsigned long)av, pte, 0))
503 BUG();
504 } else
505 kmap_flush_unused();
506}
507
38ffbe66
JF
508static void xen_alloc_ldt(struct desc_struct *ldt, unsigned entries)
509{
a05d2eba 510 const unsigned entries_per_page = PAGE_SIZE / LDT_ENTRY_SIZE;
38ffbe66
JF
511 int i;
512
a05d2eba
JF
513 for(i = 0; i < entries; i += entries_per_page)
514 set_aliased_prot(ldt + i, PAGE_KERNEL_RO);
38ffbe66
JF
515}
516
517static void xen_free_ldt(struct desc_struct *ldt, unsigned entries)
518{
a05d2eba 519 const unsigned entries_per_page = PAGE_SIZE / LDT_ENTRY_SIZE;
38ffbe66
JF
520 int i;
521
a05d2eba
JF
522 for(i = 0; i < entries; i += entries_per_page)
523 set_aliased_prot(ldt + i, PAGE_KERNEL);
38ffbe66
JF
524}
525
5ead97c8
JF
526static void xen_set_ldt(const void *addr, unsigned entries)
527{
5ead97c8
JF
528 struct mmuext_op *op;
529 struct multicall_space mcs = xen_mc_entry(sizeof(*op));
530
ab78f7ad
JF
531 trace_xen_cpu_set_ldt(addr, entries);
532
5ead97c8
JF
533 op = mcs.args;
534 op->cmd = MMUEXT_SET_LDT;
4dbf7af6 535 op->arg1.linear_addr = (unsigned long)addr;
5ead97c8
JF
536 op->arg2.nr_ents = entries;
537
538 MULTI_mmuext_op(mcs.mc, op, 1, NULL, DOMID_SELF);
539
540 xen_mc_issue(PARAVIRT_LAZY_CPU);
541}
542
6b68f01b 543static void xen_load_gdt(const struct desc_ptr *dtr)
5ead97c8 544{
5ead97c8
JF
545 unsigned long va = dtr->address;
546 unsigned int size = dtr->size + 1;
547 unsigned pages = (size + PAGE_SIZE - 1) / PAGE_SIZE;
3ce5fa7e 548 unsigned long frames[pages];
5ead97c8 549 int f;
5ead97c8 550
577eebea
JF
551 /*
552 * A GDT can be up to 64k in size, which corresponds to 8192
553 * 8-byte entries, or 16 4k pages..
554 */
5ead97c8
JF
555
556 BUG_ON(size > 65536);
557 BUG_ON(va & ~PAGE_MASK);
558
5ead97c8 559 for (f = 0; va < dtr->address + size; va += PAGE_SIZE, f++) {
6ed6bf42 560 int level;
577eebea 561 pte_t *ptep;
6ed6bf42
JF
562 unsigned long pfn, mfn;
563 void *virt;
564
577eebea
JF
565 /*
566 * The GDT is per-cpu and is in the percpu data area.
567 * That can be virtually mapped, so we need to do a
568 * page-walk to get the underlying MFN for the
569 * hypercall. The page can also be in the kernel's
570 * linear range, so we need to RO that mapping too.
571 */
572 ptep = lookup_address(va, &level);
6ed6bf42
JF
573 BUG_ON(ptep == NULL);
574
575 pfn = pte_pfn(*ptep);
576 mfn = pfn_to_mfn(pfn);
577 virt = __va(PFN_PHYS(pfn));
578
579 frames[f] = mfn;
9976b39b 580
5ead97c8 581 make_lowmem_page_readonly((void *)va);
6ed6bf42 582 make_lowmem_page_readonly(virt);
5ead97c8
JF
583 }
584
3ce5fa7e
JF
585 if (HYPERVISOR_set_gdt(frames, size / sizeof(struct desc_struct)))
586 BUG();
5ead97c8
JF
587}
588
577eebea
JF
589/*
590 * load_gdt for early boot, when the gdt is only mapped once
591 */
ad3062a0 592static void __init xen_load_gdt_boot(const struct desc_ptr *dtr)
577eebea
JF
593{
594 unsigned long va = dtr->address;
595 unsigned int size = dtr->size + 1;
596 unsigned pages = (size + PAGE_SIZE - 1) / PAGE_SIZE;
597 unsigned long frames[pages];
598 int f;
599
600 /*
601 * A GDT can be up to 64k in size, which corresponds to 8192
602 * 8-byte entries, or 16 4k pages..
603 */
604
605 BUG_ON(size > 65536);
606 BUG_ON(va & ~PAGE_MASK);
607
608 for (f = 0; va < dtr->address + size; va += PAGE_SIZE, f++) {
609 pte_t pte;
610 unsigned long pfn, mfn;
611
612 pfn = virt_to_pfn(va);
613 mfn = pfn_to_mfn(pfn);
614
615 pte = pfn_pte(pfn, PAGE_KERNEL_RO);
616
617 if (HYPERVISOR_update_va_mapping((unsigned long)va, pte, 0))
618 BUG();
619
620 frames[f] = mfn;
621 }
622
623 if (HYPERVISOR_set_gdt(frames, size / sizeof(struct desc_struct)))
624 BUG();
625}
626
59290362
DV
627static inline bool desc_equal(const struct desc_struct *d1,
628 const struct desc_struct *d2)
629{
630 return d1->a == d2->a && d1->b == d2->b;
631}
632
5ead97c8
JF
633static void load_TLS_descriptor(struct thread_struct *t,
634 unsigned int cpu, unsigned int i)
635{
1c32cdc6
DV
636 struct desc_struct *shadow = &per_cpu(shadow_tls_desc, cpu).desc[i];
637 struct desc_struct *gdt;
638 xmaddr_t maddr;
639 struct multicall_space mc;
640
641 if (desc_equal(shadow, &t->tls_array[i]))
642 return;
643
644 *shadow = t->tls_array[i];
645
646 gdt = get_cpu_gdt_table(cpu);
647 maddr = arbitrary_virt_to_machine(&gdt[GDT_ENTRY_TLS_MIN+i]);
648 mc = __xen_mc_entry(0);
5ead97c8
JF
649
650 MULTI_update_descriptor(mc.mc, maddr.maddr, t->tls_array[i]);
651}
652
653static void xen_load_tls(struct thread_struct *t, unsigned int cpu)
654{
8b84ad94 655 /*
ccbeed3a
TH
656 * XXX sleazy hack: If we're being called in a lazy-cpu zone
657 * and lazy gs handling is enabled, it means we're in a
658 * context switch, and %gs has just been saved. This means we
659 * can zero it out to prevent faults on exit from the
660 * hypervisor if the next process has no %gs. Either way, it
661 * has been saved, and the new value will get loaded properly.
662 * This will go away as soon as Xen has been modified to not
663 * save/restore %gs for normal hypercalls.
8a95408e
EH
664 *
665 * On x86_64, this hack is not used for %gs, because gs points
666 * to KERNEL_GS_BASE (and uses it for PDA references), so we
667 * must not zero %gs on x86_64
668 *
669 * For x86_64, we need to zero %fs, otherwise we may get an
670 * exception between the new %fs descriptor being loaded and
671 * %fs being effectively cleared at __switch_to().
8b84ad94 672 */
8a95408e
EH
673 if (paravirt_get_lazy_mode() == PARAVIRT_LAZY_CPU) {
674#ifdef CONFIG_X86_32
ccbeed3a 675 lazy_load_gs(0);
8a95408e
EH
676#else
677 loadsegment(fs, 0);
678#endif
679 }
680
681 xen_mc_batch();
682
683 load_TLS_descriptor(t, cpu, 0);
684 load_TLS_descriptor(t, cpu, 1);
685 load_TLS_descriptor(t, cpu, 2);
686
687 xen_mc_issue(PARAVIRT_LAZY_CPU);
5ead97c8
JF
688}
689
a8fc1089
EH
690#ifdef CONFIG_X86_64
691static void xen_load_gs_index(unsigned int idx)
692{
693 if (HYPERVISOR_set_segment_base(SEGBASE_GS_USER_SEL, idx))
694 BUG();
5ead97c8 695}
a8fc1089 696#endif
5ead97c8
JF
697
698static void xen_write_ldt_entry(struct desc_struct *dt, int entrynum,
75b8bb3e 699 const void *ptr)
5ead97c8 700{
cef43bf6 701 xmaddr_t mach_lp = arbitrary_virt_to_machine(&dt[entrynum]);
75b8bb3e 702 u64 entry = *(u64 *)ptr;
5ead97c8 703
ab78f7ad
JF
704 trace_xen_cpu_write_ldt_entry(dt, entrynum, entry);
705
f120f13e
JF
706 preempt_disable();
707
5ead97c8
JF
708 xen_mc_flush();
709 if (HYPERVISOR_update_descriptor(mach_lp.maddr, entry))
710 BUG();
f120f13e
JF
711
712 preempt_enable();
5ead97c8
JF
713}
714
e176d367 715static int cvt_gate_to_trap(int vector, const gate_desc *val,
5ead97c8
JF
716 struct trap_info *info)
717{
6cac5a92
JF
718 unsigned long addr;
719
6d02c426 720 if (val->type != GATE_TRAP && val->type != GATE_INTERRUPT)
5ead97c8
JF
721 return 0;
722
723 info->vector = vector;
6cac5a92
JF
724
725 addr = gate_offset(*val);
726#ifdef CONFIG_X86_64
b80119bb
JF
727 /*
728 * Look for known traps using IST, and substitute them
729 * appropriately. The debugger ones are the only ones we care
05e36006
LJ
730 * about. Xen will handle faults like double_fault,
731 * so we should never see them. Warn if
b80119bb
JF
732 * there's an unexpected IST-using fault handler.
733 */
6cac5a92
JF
734 if (addr == (unsigned long)debug)
735 addr = (unsigned long)xen_debug;
736 else if (addr == (unsigned long)int3)
737 addr = (unsigned long)xen_int3;
738 else if (addr == (unsigned long)stack_segment)
739 addr = (unsigned long)xen_stack_segment;
6efa20e4 740 else if (addr == (unsigned long)double_fault) {
b80119bb
JF
741 /* Don't need to handle these */
742 return 0;
743#ifdef CONFIG_X86_MCE
744 } else if (addr == (unsigned long)machine_check) {
05e36006
LJ
745 /*
746 * when xen hypervisor inject vMCE to guest,
747 * use native mce handler to handle it
748 */
749 ;
b80119bb 750#endif
6efa20e4
KRW
751 } else if (addr == (unsigned long)nmi)
752 /*
753 * Use the native version as well.
754 */
755 ;
756 else {
b80119bb
JF
757 /* Some other trap using IST? */
758 if (WARN_ON(val->ist != 0))
759 return 0;
760 }
6cac5a92
JF
761#endif /* CONFIG_X86_64 */
762 info->address = addr;
763
e176d367
EH
764 info->cs = gate_segment(*val);
765 info->flags = val->dpl;
5ead97c8 766 /* interrupt gates clear IF */
6d02c426
JF
767 if (val->type == GATE_INTERRUPT)
768 info->flags |= 1 << 2;
5ead97c8
JF
769
770 return 1;
771}
772
773/* Locations of each CPU's IDT */
6b68f01b 774static DEFINE_PER_CPU(struct desc_ptr, idt_desc);
5ead97c8
JF
775
776/* Set an IDT entry. If the entry is part of the current IDT, then
777 also update Xen. */
8d947344 778static void xen_write_idt_entry(gate_desc *dt, int entrynum, const gate_desc *g)
5ead97c8 779{
5ead97c8 780 unsigned long p = (unsigned long)&dt[entrynum];
f120f13e
JF
781 unsigned long start, end;
782
ab78f7ad
JF
783 trace_xen_cpu_write_idt_entry(dt, entrynum, g);
784
f120f13e
JF
785 preempt_disable();
786
780f36d8
CL
787 start = __this_cpu_read(idt_desc.address);
788 end = start + __this_cpu_read(idt_desc.size) + 1;
5ead97c8
JF
789
790 xen_mc_flush();
791
8d947344 792 native_write_idt_entry(dt, entrynum, g);
5ead97c8
JF
793
794 if (p >= start && (p + 8) <= end) {
795 struct trap_info info[2];
796
797 info[1].address = 0;
798
e176d367 799 if (cvt_gate_to_trap(entrynum, g, &info[0]))
5ead97c8
JF
800 if (HYPERVISOR_set_trap_table(info))
801 BUG();
802 }
f120f13e
JF
803
804 preempt_enable();
5ead97c8
JF
805}
806
6b68f01b 807static void xen_convert_trap_info(const struct desc_ptr *desc,
f87e4cac 808 struct trap_info *traps)
5ead97c8 809{
5ead97c8
JF
810 unsigned in, out, count;
811
e176d367 812 count = (desc->size+1) / sizeof(gate_desc);
5ead97c8
JF
813 BUG_ON(count > 256);
814
5ead97c8 815 for (in = out = 0; in < count; in++) {
e176d367 816 gate_desc *entry = (gate_desc*)(desc->address) + in;
5ead97c8 817
e176d367 818 if (cvt_gate_to_trap(in, entry, &traps[out]))
5ead97c8
JF
819 out++;
820 }
821 traps[out].address = 0;
f87e4cac
JF
822}
823
824void xen_copy_trap_info(struct trap_info *traps)
825{
89cbc767 826 const struct desc_ptr *desc = this_cpu_ptr(&idt_desc);
f87e4cac
JF
827
828 xen_convert_trap_info(desc, traps);
f87e4cac
JF
829}
830
831/* Load a new IDT into Xen. In principle this can be per-CPU, so we
832 hold a spinlock to protect the static traps[] array (static because
833 it avoids allocation, and saves stack space). */
6b68f01b 834static void xen_load_idt(const struct desc_ptr *desc)
f87e4cac
JF
835{
836 static DEFINE_SPINLOCK(lock);
837 static struct trap_info traps[257];
f87e4cac 838
ab78f7ad
JF
839 trace_xen_cpu_load_idt(desc);
840
f87e4cac
JF
841 spin_lock(&lock);
842
89cbc767 843 memcpy(this_cpu_ptr(&idt_desc), desc, sizeof(idt_desc));
f120f13e 844
f87e4cac 845 xen_convert_trap_info(desc, traps);
5ead97c8
JF
846
847 xen_mc_flush();
848 if (HYPERVISOR_set_trap_table(traps))
849 BUG();
850
851 spin_unlock(&lock);
852}
853
854/* Write a GDT descriptor entry. Ignore LDT descriptors, since
855 they're handled differently. */
856static void xen_write_gdt_entry(struct desc_struct *dt, int entry,
014b15be 857 const void *desc, int type)
5ead97c8 858{
ab78f7ad
JF
859 trace_xen_cpu_write_gdt_entry(dt, entry, desc, type);
860
f120f13e
JF
861 preempt_disable();
862
014b15be
GOC
863 switch (type) {
864 case DESC_LDT:
865 case DESC_TSS:
5ead97c8
JF
866 /* ignore */
867 break;
868
869 default: {
9976b39b 870 xmaddr_t maddr = arbitrary_virt_to_machine(&dt[entry]);
5ead97c8
JF
871
872 xen_mc_flush();
014b15be 873 if (HYPERVISOR_update_descriptor(maddr.maddr, *(u64 *)desc))
5ead97c8
JF
874 BUG();
875 }
876
877 }
f120f13e
JF
878
879 preempt_enable();
5ead97c8
JF
880}
881
577eebea
JF
882/*
883 * Version of write_gdt_entry for use at early boot-time needed to
884 * update an entry as simply as possible.
885 */
ad3062a0 886static void __init xen_write_gdt_entry_boot(struct desc_struct *dt, int entry,
577eebea
JF
887 const void *desc, int type)
888{
ab78f7ad
JF
889 trace_xen_cpu_write_gdt_entry(dt, entry, desc, type);
890
577eebea
JF
891 switch (type) {
892 case DESC_LDT:
893 case DESC_TSS:
894 /* ignore */
895 break;
896
897 default: {
898 xmaddr_t maddr = virt_to_machine(&dt[entry]);
899
900 if (HYPERVISOR_update_descriptor(maddr.maddr, *(u64 *)desc))
901 dt[entry] = *(struct desc_struct *)desc;
902 }
903
904 }
905}
906
faca6227 907static void xen_load_sp0(struct tss_struct *tss,
a05d2eba 908 struct thread_struct *thread)
5ead97c8 909{
ab78f7ad
JF
910 struct multicall_space mcs;
911
912 mcs = xen_mc_entry(0);
faca6227 913 MULTI_stack_switch(mcs.mc, __KERNEL_DS, thread->sp0);
5ead97c8 914 xen_mc_issue(PARAVIRT_LAZY_CPU);
8ef46a67 915 tss->x86_tss.sp0 = thread->sp0;
5ead97c8
JF
916}
917
918static void xen_set_iopl_mask(unsigned mask)
919{
920 struct physdev_set_iopl set_iopl;
921
922 /* Force the change at ring 0. */
923 set_iopl.iopl = (mask == 0) ? 1 : (mask >> 12) & 3;
924 HYPERVISOR_physdev_op(PHYSDEVOP_set_iopl, &set_iopl);
925}
926
927static void xen_io_delay(void)
928{
929}
930
7b1333aa
JF
931static void xen_clts(void)
932{
933 struct multicall_space mcs;
934
935 mcs = xen_mc_entry(0);
936
937 MULTI_fpu_taskswitch(mcs.mc, 0);
938
939 xen_mc_issue(PARAVIRT_LAZY_CPU);
940}
941
a789ed5f
JF
942static DEFINE_PER_CPU(unsigned long, xen_cr0_value);
943
944static unsigned long xen_read_cr0(void)
945{
2113f469 946 unsigned long cr0 = this_cpu_read(xen_cr0_value);
a789ed5f
JF
947
948 if (unlikely(cr0 == 0)) {
949 cr0 = native_read_cr0();
2113f469 950 this_cpu_write(xen_cr0_value, cr0);
a789ed5f
JF
951 }
952
953 return cr0;
954}
955
7b1333aa
JF
956static void xen_write_cr0(unsigned long cr0)
957{
958 struct multicall_space mcs;
959
2113f469 960 this_cpu_write(xen_cr0_value, cr0);
a789ed5f 961
7b1333aa
JF
962 /* Only pay attention to cr0.TS; everything else is
963 ignored. */
964 mcs = xen_mc_entry(0);
965
966 MULTI_fpu_taskswitch(mcs.mc, (cr0 & X86_CR0_TS) != 0);
967
968 xen_mc_issue(PARAVIRT_LAZY_CPU);
969}
970
5ead97c8
JF
971static void xen_write_cr4(unsigned long cr4)
972{
2956a351
JF
973 cr4 &= ~X86_CR4_PGE;
974 cr4 &= ~X86_CR4_PSE;
975
976 native_write_cr4(cr4);
5ead97c8 977}
1a7bbda5
KRW
978#ifdef CONFIG_X86_64
979static inline unsigned long xen_read_cr8(void)
980{
981 return 0;
982}
983static inline void xen_write_cr8(unsigned long val)
984{
985 BUG_ON(val);
986}
987#endif
31795b47
BO
988
989static u64 xen_read_msr_safe(unsigned int msr, int *err)
990{
991 u64 val;
992
993 val = native_read_msr_safe(msr, err);
994 switch (msr) {
995 case MSR_IA32_APICBASE:
996#ifdef CONFIG_X86_X2APIC
997 if (!(cpuid_ecx(1) & (1 << (X86_FEATURE_X2APIC & 31))))
998#endif
999 val &= ~X2APIC_ENABLE;
1000 break;
1001 }
1002 return val;
1003}
1004
1153968a
JF
1005static int xen_write_msr_safe(unsigned int msr, unsigned low, unsigned high)
1006{
1007 int ret;
1008
1009 ret = 0;
1010
f63c2f24 1011 switch (msr) {
1153968a
JF
1012#ifdef CONFIG_X86_64
1013 unsigned which;
1014 u64 base;
1015
1016 case MSR_FS_BASE: which = SEGBASE_FS; goto set;
1017 case MSR_KERNEL_GS_BASE: which = SEGBASE_GS_USER; goto set;
1018 case MSR_GS_BASE: which = SEGBASE_GS_KERNEL; goto set;
1019
1020 set:
1021 base = ((u64)high << 32) | low;
1022 if (HYPERVISOR_set_segment_base(which, base) != 0)
0cc0213e 1023 ret = -EIO;
1153968a
JF
1024 break;
1025#endif
d89961e2
JF
1026
1027 case MSR_STAR:
1028 case MSR_CSTAR:
1029 case MSR_LSTAR:
1030 case MSR_SYSCALL_MASK:
1031 case MSR_IA32_SYSENTER_CS:
1032 case MSR_IA32_SYSENTER_ESP:
1033 case MSR_IA32_SYSENTER_EIP:
1034 /* Fast syscall setup is all done in hypercalls, so
1035 these are all ignored. Stub them out here to stop
1036 Xen console noise. */
41f2e477 1037
1153968a
JF
1038 default:
1039 ret = native_write_msr_safe(msr, low, high);
1040 }
1041
1042 return ret;
1043}
1044
0e91398f 1045void xen_setup_shared_info(void)
5ead97c8
JF
1046{
1047 if (!xen_feature(XENFEAT_auto_translated_physmap)) {
15664f96
JF
1048 set_fixmap(FIX_PARAVIRT_BOOTMAP,
1049 xen_start_info->shared_info);
1050
1051 HYPERVISOR_shared_info =
1052 (struct shared_info *)fix_to_virt(FIX_PARAVIRT_BOOTMAP);
5ead97c8
JF
1053 } else
1054 HYPERVISOR_shared_info =
1055 (struct shared_info *)__va(xen_start_info->shared_info);
1056
2e8fe719
JF
1057#ifndef CONFIG_SMP
1058 /* In UP this is as good a place as any to set up shared info */
1059 xen_setup_vcpu_info_placement();
1060#endif
d5edbc1f
JF
1061
1062 xen_setup_mfn_list_list();
2e8fe719
JF
1063}
1064
5f054e31 1065/* This is called once we have the cpu_possible_mask */
0e91398f 1066void xen_setup_vcpu_info_placement(void)
60223a32
JF
1067{
1068 int cpu;
1069
1070 for_each_possible_cpu(cpu)
1071 xen_vcpu_setup(cpu);
1072
1073 /* xen_vcpu_setup managed to place the vcpu_info within the
2771374d
MR
1074 * percpu area for all cpus, so make use of it. Note that for
1075 * PVH we want to use native IRQ mechanism. */
1076 if (have_vcpu_info_placement && !xen_pvh_domain()) {
ecb93d1c
JF
1077 pv_irq_ops.save_fl = __PV_IS_CALLEE_SAVE(xen_save_fl_direct);
1078 pv_irq_ops.restore_fl = __PV_IS_CALLEE_SAVE(xen_restore_fl_direct);
1079 pv_irq_ops.irq_disable = __PV_IS_CALLEE_SAVE(xen_irq_disable_direct);
1080 pv_irq_ops.irq_enable = __PV_IS_CALLEE_SAVE(xen_irq_enable_direct);
93b1eab3 1081 pv_mmu_ops.read_cr2 = xen_read_cr2_direct;
60223a32 1082 }
5ead97c8
JF
1083}
1084
ab144f5e
AK
1085static unsigned xen_patch(u8 type, u16 clobbers, void *insnbuf,
1086 unsigned long addr, unsigned len)
6487673b
JF
1087{
1088 char *start, *end, *reloc;
1089 unsigned ret;
1090
1091 start = end = reloc = NULL;
1092
93b1eab3
JF
1093#define SITE(op, x) \
1094 case PARAVIRT_PATCH(op.x): \
6487673b
JF
1095 if (have_vcpu_info_placement) { \
1096 start = (char *)xen_##x##_direct; \
1097 end = xen_##x##_direct_end; \
1098 reloc = xen_##x##_direct_reloc; \
1099 } \
1100 goto patch_site
1101
1102 switch (type) {
93b1eab3
JF
1103 SITE(pv_irq_ops, irq_enable);
1104 SITE(pv_irq_ops, irq_disable);
1105 SITE(pv_irq_ops, save_fl);
1106 SITE(pv_irq_ops, restore_fl);
6487673b
JF
1107#undef SITE
1108
1109 patch_site:
1110 if (start == NULL || (end-start) > len)
1111 goto default_patch;
1112
ab144f5e 1113 ret = paravirt_patch_insns(insnbuf, len, start, end);
6487673b
JF
1114
1115 /* Note: because reloc is assigned from something that
1116 appears to be an array, gcc assumes it's non-null,
1117 but doesn't know its relationship with start and
1118 end. */
1119 if (reloc > start && reloc < end) {
1120 int reloc_off = reloc - start;
ab144f5e
AK
1121 long *relocp = (long *)(insnbuf + reloc_off);
1122 long delta = start - (char *)addr;
6487673b
JF
1123
1124 *relocp += delta;
1125 }
1126 break;
1127
1128 default_patch:
1129 default:
ab144f5e
AK
1130 ret = paravirt_patch_default(type, clobbers, insnbuf,
1131 addr, len);
6487673b
JF
1132 break;
1133 }
1134
1135 return ret;
1136}
1137
ad3062a0 1138static const struct pv_info xen_info __initconst = {
5ead97c8
JF
1139 .paravirt_enabled = 1,
1140 .shared_kernel_pmd = 0,
1141
318f5a2a
AL
1142#ifdef CONFIG_X86_64
1143 .extra_user_64bit_cs = FLAT_USER_CS64,
1144#endif
1145
5ead97c8 1146 .name = "Xen",
93b1eab3 1147};
5ead97c8 1148
ad3062a0 1149static const struct pv_init_ops xen_init_ops __initconst = {
6487673b 1150 .patch = xen_patch,
93b1eab3 1151};
5ead97c8 1152
ad3062a0 1153static const struct pv_cpu_ops xen_cpu_ops __initconst = {
5ead97c8
JF
1154 .cpuid = xen_cpuid,
1155
1156 .set_debugreg = xen_set_debugreg,
1157 .get_debugreg = xen_get_debugreg,
1158
7b1333aa 1159 .clts = xen_clts,
5ead97c8 1160
a789ed5f 1161 .read_cr0 = xen_read_cr0,
7b1333aa 1162 .write_cr0 = xen_write_cr0,
5ead97c8 1163
5ead97c8
JF
1164 .read_cr4 = native_read_cr4,
1165 .read_cr4_safe = native_read_cr4_safe,
1166 .write_cr4 = xen_write_cr4,
1167
1a7bbda5
KRW
1168#ifdef CONFIG_X86_64
1169 .read_cr8 = xen_read_cr8,
1170 .write_cr8 = xen_write_cr8,
1171#endif
1172
5ead97c8
JF
1173 .wbinvd = native_wbinvd,
1174
31795b47 1175 .read_msr = xen_read_msr_safe,
1153968a 1176 .write_msr = xen_write_msr_safe,
1ab46fd3 1177
5ead97c8
JF
1178 .read_tsc = native_read_tsc,
1179 .read_pmc = native_read_pmc,
1180
cd0608e7
KRW
1181 .read_tscp = native_read_tscp,
1182
81e103f1 1183 .iret = xen_iret,
6fcac6d3
JF
1184#ifdef CONFIG_X86_64
1185 .usergs_sysret32 = xen_sysret32,
1186 .usergs_sysret64 = xen_sysret64,
aac82d31
AL
1187#else
1188 .irq_enable_sysexit = xen_sysexit,
6fcac6d3 1189#endif
5ead97c8
JF
1190
1191 .load_tr_desc = paravirt_nop,
1192 .set_ldt = xen_set_ldt,
1193 .load_gdt = xen_load_gdt,
1194 .load_idt = xen_load_idt,
1195 .load_tls = xen_load_tls,
a8fc1089
EH
1196#ifdef CONFIG_X86_64
1197 .load_gs_index = xen_load_gs_index,
1198#endif
5ead97c8 1199
38ffbe66
JF
1200 .alloc_ldt = xen_alloc_ldt,
1201 .free_ldt = xen_free_ldt,
1202
5ead97c8
JF
1203 .store_idt = native_store_idt,
1204 .store_tr = xen_store_tr,
1205
1206 .write_ldt_entry = xen_write_ldt_entry,
1207 .write_gdt_entry = xen_write_gdt_entry,
1208 .write_idt_entry = xen_write_idt_entry,
faca6227 1209 .load_sp0 = xen_load_sp0,
5ead97c8
JF
1210
1211 .set_iopl_mask = xen_set_iopl_mask,
1212 .io_delay = xen_io_delay,
1213
952d1d70
JF
1214 /* Xen takes care of %gs when switching to usermode for us */
1215 .swapgs = paravirt_nop,
1216
224101ed
JF
1217 .start_context_switch = paravirt_start_context_switch,
1218 .end_context_switch = xen_end_context_switch,
93b1eab3
JF
1219};
1220
ad3062a0 1221static const struct pv_apic_ops xen_apic_ops __initconst = {
5ead97c8 1222#ifdef CONFIG_X86_LOCAL_APIC
5ead97c8
JF
1223 .startup_ipi_hook = paravirt_nop,
1224#endif
93b1eab3
JF
1225};
1226
fefa629a
JF
1227static void xen_reboot(int reason)
1228{
349c709f
JF
1229 struct sched_shutdown r = { .reason = reason };
1230
349c709f 1231 if (HYPERVISOR_sched_op(SCHEDOP_shutdown, &r))
fefa629a
JF
1232 BUG();
1233}
1234
1235static void xen_restart(char *msg)
1236{
1237 xen_reboot(SHUTDOWN_reboot);
1238}
1239
1240static void xen_emergency_restart(void)
1241{
1242 xen_reboot(SHUTDOWN_reboot);
1243}
1244
1245static void xen_machine_halt(void)
1246{
1247 xen_reboot(SHUTDOWN_poweroff);
1248}
1249
b2abe506
TG
1250static void xen_machine_power_off(void)
1251{
1252 if (pm_power_off)
1253 pm_power_off();
1254 xen_reboot(SHUTDOWN_poweroff);
1255}
1256
fefa629a
JF
1257static void xen_crash_shutdown(struct pt_regs *regs)
1258{
1259 xen_reboot(SHUTDOWN_crash);
1260}
1261
f09f6d19
DD
1262static int
1263xen_panic_event(struct notifier_block *this, unsigned long event, void *ptr)
1264{
086748e5 1265 xen_reboot(SHUTDOWN_crash);
f09f6d19
DD
1266 return NOTIFY_DONE;
1267}
1268
1269static struct notifier_block xen_panic_block = {
1270 .notifier_call= xen_panic_event,
bc5eb201 1271 .priority = INT_MIN
f09f6d19
DD
1272};
1273
1274int xen_panic_handler_init(void)
1275{
1276 atomic_notifier_chain_register(&panic_notifier_list, &xen_panic_block);
1277 return 0;
1278}
1279
ad3062a0 1280static const struct machine_ops xen_machine_ops __initconst = {
fefa629a
JF
1281 .restart = xen_restart,
1282 .halt = xen_machine_halt,
b2abe506 1283 .power_off = xen_machine_power_off,
fefa629a
JF
1284 .shutdown = xen_machine_halt,
1285 .crash_shutdown = xen_crash_shutdown,
1286 .emergency_restart = xen_emergency_restart,
1287};
1288
f221b04f
JB
1289static unsigned char xen_get_nmi_reason(void)
1290{
1291 unsigned char reason = 0;
1292
1293 /* Construct a value which looks like it came from port 0x61. */
1294 if (test_bit(_XEN_NMIREASON_io_error,
1295 &HYPERVISOR_shared_info->arch.nmi_reason))
1296 reason |= NMI_REASON_IOCHK;
1297 if (test_bit(_XEN_NMIREASON_pci_serr,
1298 &HYPERVISOR_shared_info->arch.nmi_reason))
1299 reason |= NMI_REASON_SERR;
1300
1301 return reason;
1302}
1303
96f28bc6
DV
1304static void __init xen_boot_params_init_edd(void)
1305{
1306#if IS_ENABLED(CONFIG_EDD)
1307 struct xen_platform_op op;
1308 struct edd_info *edd_info;
1309 u32 *mbr_signature;
1310 unsigned nr;
1311 int ret;
1312
1313 edd_info = boot_params.eddbuf;
1314 mbr_signature = boot_params.edd_mbr_sig_buffer;
1315
1316 op.cmd = XENPF_firmware_info;
1317
1318 op.u.firmware_info.type = XEN_FW_DISK_INFO;
1319 for (nr = 0; nr < EDDMAXNR; nr++) {
1320 struct edd_info *info = edd_info + nr;
1321
1322 op.u.firmware_info.index = nr;
1323 info->params.length = sizeof(info->params);
1324 set_xen_guest_handle(op.u.firmware_info.u.disk_info.edd_params,
1325 &info->params);
1326 ret = HYPERVISOR_dom0_op(&op);
1327 if (ret)
1328 break;
1329
1330#define C(x) info->x = op.u.firmware_info.u.disk_info.x
1331 C(device);
1332 C(version);
1333 C(interface_support);
1334 C(legacy_max_cylinder);
1335 C(legacy_max_head);
1336 C(legacy_sectors_per_track);
1337#undef C
1338 }
1339 boot_params.eddbuf_entries = nr;
1340
1341 op.u.firmware_info.type = XEN_FW_DISK_MBR_SIGNATURE;
1342 for (nr = 0; nr < EDD_MBR_SIG_MAX; nr++) {
1343 op.u.firmware_info.index = nr;
1344 ret = HYPERVISOR_dom0_op(&op);
1345 if (ret)
1346 break;
1347 mbr_signature[nr] = op.u.firmware_info.u.disk_mbr_signature.mbr_signature;
1348 }
1349 boot_params.edd_mbr_sig_buf_entries = nr;
1350#endif
1351}
1352
577eebea
JF
1353/*
1354 * Set up the GDT and segment registers for -fstack-protector. Until
1355 * we do this, we have to be careful not to call any stack-protected
1356 * function, which is most of the kernel.
5840c84b
MR
1357 *
1358 * Note, that it is __ref because the only caller of this after init
1359 * is PVH which is not going to use xen_load_gdt_boot or other
1360 * __init functions.
577eebea 1361 */
c9f6e997 1362static void __ref xen_setup_gdt(int cpu)
577eebea 1363{
8d656bbe
MR
1364 if (xen_feature(XENFEAT_auto_translated_physmap)) {
1365#ifdef CONFIG_X86_64
1366 unsigned long dummy;
1367
5840c84b
MR
1368 load_percpu_segment(cpu); /* We need to access per-cpu area */
1369 switch_to_new_gdt(cpu); /* GDT and GS set */
8d656bbe
MR
1370
1371 /* We are switching of the Xen provided GDT to our HVM mode
1372 * GDT. The new GDT has __KERNEL_CS with CS.L = 1
1373 * and we are jumping to reload it.
1374 */
1375 asm volatile ("pushq %0\n"
1376 "leaq 1f(%%rip),%0\n"
1377 "pushq %0\n"
1378 "lretq\n"
1379 "1:\n"
1380 : "=&r" (dummy) : "0" (__KERNEL_CS));
1381
1382 /*
1383 * While not needed, we also set the %es, %ds, and %fs
1384 * to zero. We don't care about %ss as it is NULL.
1385 * Strictly speaking this is not needed as Xen zeros those
1386 * out (and also MSR_FS_BASE, MSR_GS_BASE, MSR_KERNEL_GS_BASE)
1387 *
1388 * Linux zeros them in cpu_init() and in secondary_startup_64
1389 * (for BSP).
1390 */
1391 loadsegment(es, 0);
1392 loadsegment(ds, 0);
1393 loadsegment(fs, 0);
1394#else
1395 /* PVH: TODO Implement. */
1396 BUG();
1397#endif
1398 return; /* PVH does not need any PV GDT ops. */
1399 }
577eebea
JF
1400 pv_cpu_ops.write_gdt_entry = xen_write_gdt_entry_boot;
1401 pv_cpu_ops.load_gdt = xen_load_gdt_boot;
1402
1403 setup_stack_canary_segment(0);
1404 switch_to_new_gdt(0);
1405
1406 pv_cpu_ops.write_gdt_entry = xen_write_gdt_entry;
1407 pv_cpu_ops.load_gdt = xen_load_gdt;
1408}
1409
a2ef5dc2 1410#ifdef CONFIG_XEN_PVH
c9f6e997
RPM
1411/*
1412 * A PV guest starts with default flags that are not set for PVH, set them
1413 * here asap.
1414 */
1415static void xen_pvh_set_cr_flags(int cpu)
1416{
1417
1418 /* Some of these are setup in 'secondary_startup_64'. The others:
1419 * X86_CR0_TS, X86_CR0_PE, X86_CR0_ET are set by Xen for HVM guests
1420 * (which PVH shared codepaths), while X86_CR0_PG is for PVH. */
1421 write_cr0(read_cr0() | X86_CR0_MP | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM);
afca5013
MR
1422
1423 if (!cpu)
1424 return;
1425 /*
1426 * For BSP, PSE PGE are set in probe_page_size_mask(), for APs
21c4cd10 1427 * set them here. For all, OSFXSR OSXMMEXCPT are set in fpu__init_cpu().
afca5013
MR
1428 */
1429 if (cpu_has_pse)
375074cc 1430 cr4_set_bits_and_update_boot(X86_CR4_PSE);
afca5013
MR
1431
1432 if (cpu_has_pge)
375074cc 1433 cr4_set_bits_and_update_boot(X86_CR4_PGE);
c9f6e997
RPM
1434}
1435
1436/*
1437 * Note, that it is ref - because the only caller of this after init
1438 * is PVH which is not going to use xen_load_gdt_boot or other
1439 * __init functions.
1440 */
1441void __ref xen_pvh_secondary_vcpu_init(int cpu)
1442{
1443 xen_setup_gdt(cpu);
1444 xen_pvh_set_cr_flags(cpu);
1445}
1446
d285d683
MR
1447static void __init xen_pvh_early_guest_init(void)
1448{
1449 if (!xen_feature(XENFEAT_auto_translated_physmap))
1450 return;
1451
c9f6e997
RPM
1452 if (!xen_feature(XENFEAT_hvm_callback_vector))
1453 return;
1454
1455 xen_have_vector_callback = 1;
a2ef5dc2
MR
1456
1457 xen_pvh_early_cpu_init(0, false);
c9f6e997 1458 xen_pvh_set_cr_flags(0);
d285d683
MR
1459
1460#ifdef CONFIG_X86_32
1461 BUG(); /* PVH: Implement proper support. */
1462#endif
1463}
a2ef5dc2 1464#endif /* CONFIG_XEN_PVH */
d285d683 1465
5ead97c8 1466/* First C function to be called on Xen boot */
2605fc21 1467asmlinkage __visible void __init xen_start_kernel(void)
5ead97c8 1468{
ec35a69c 1469 struct physdev_set_iopl set_iopl;
d1e9abd6 1470 unsigned long initrd_start = 0;
9cd25aac 1471 u64 pat;
ec35a69c 1472 int rc;
5ead97c8
JF
1473
1474 if (!xen_start_info)
1475 return;
1476
6e833587
JF
1477 xen_domain_type = XEN_PV_DOMAIN;
1478
d285d683 1479 xen_setup_features();
a2ef5dc2 1480#ifdef CONFIG_XEN_PVH
d285d683 1481 xen_pvh_early_guest_init();
a2ef5dc2 1482#endif
7e77506a
IC
1483 xen_setup_machphys_mapping();
1484
5ead97c8 1485 /* Install Xen paravirt ops */
93b1eab3
JF
1486 pv_info = xen_info;
1487 pv_init_ops = xen_init_ops;
93b1eab3 1488 pv_apic_ops = xen_apic_ops;
f221b04f 1489 if (!xen_pvh_domain()) {
d285d683 1490 pv_cpu_ops = xen_cpu_ops;
93b1eab3 1491
f221b04f
JB
1492 x86_platform.get_nmi_reason = xen_get_nmi_reason;
1493 }
1494
abacaadc
DV
1495 if (xen_feature(XENFEAT_auto_translated_physmap))
1496 x86_init.resources.memory_setup = xen_auto_xlated_memory_setup;
1497 else
1498 x86_init.resources.memory_setup = xen_memory_setup;
42bbdb43 1499 x86_init.oem.arch_setup = xen_arch_setup;
6f30c1ac 1500 x86_init.oem.banner = xen_banner;
845b3944 1501
409771d2 1502 xen_init_time_ops();
93b1eab3 1503
ce2eef33 1504 /*
577eebea 1505 * Set up some pagetable state before starting to set any ptes.
ce2eef33 1506 */
577eebea 1507
973df35e
JF
1508 xen_init_mmu_ops();
1509
577eebea
JF
1510 /* Prevent unwanted bits from being set in PTEs. */
1511 __supported_pte_mask &= ~_PAGE_GLOBAL;
577eebea 1512
817a824b
IC
1513 /*
1514 * Prevent page tables from being allocated in highmem, even
1515 * if CONFIG_HIGHPTE is enabled.
1516 */
1517 __userpte_alloc_gfp &= ~__GFP_HIGHMEM;
1518
b75fe4e5 1519 /* Work out if we support NX */
4763ed4d 1520 x86_configure_nx();
b75fe4e5 1521
577eebea 1522 /* Get mfn list */
696fd7c5 1523 xen_build_dynamic_phys_to_machine();
577eebea
JF
1524
1525 /*
1526 * Set up kernel GDT and segment registers, mainly so that
1527 * -fstack-protector code can be executed.
1528 */
5840c84b 1529 xen_setup_gdt(0);
0d1edf46 1530
ce2eef33 1531 xen_init_irq_ops();
e826fe1b
JF
1532 xen_init_cpuid_mask();
1533
94a8c3c2 1534#ifdef CONFIG_X86_LOCAL_APIC
ad66dd34 1535 /*
94a8c3c2 1536 * set up the basic apic ops.
ad66dd34 1537 */
feb44f1f 1538 xen_init_apic();
ad66dd34 1539#endif
93b1eab3 1540
e57778a1
JF
1541 if (xen_feature(XENFEAT_mmu_pt_update_preserve_ad)) {
1542 pv_mmu_ops.ptep_modify_prot_start = xen_ptep_modify_prot_start;
1543 pv_mmu_ops.ptep_modify_prot_commit = xen_ptep_modify_prot_commit;
1544 }
1545
fefa629a
JF
1546 machine_ops = xen_machine_ops;
1547
38341432
JF
1548 /*
1549 * The only reliable way to retain the initial address of the
1550 * percpu gdt_page is to remember it here, so we can go and
1551 * mark it RW later, when the initial percpu area is freed.
1552 */
1553 xen_initial_gdt = &per_cpu(gdt_page, 0);
795f99b6 1554
a9e7062d 1555 xen_smp_init();
5ead97c8 1556
c1f5db1a
IC
1557#ifdef CONFIG_ACPI_NUMA
1558 /*
1559 * The pages we from Xen are not related to machine pages, so
1560 * any NUMA information the kernel tries to get from ACPI will
1561 * be meaningless. Prevent it from trying.
1562 */
1563 acpi_numa = -1;
c79c4982 1564#endif
60223a32 1565 /* Don't do the full vcpu_info placement stuff until we have a
2e8fe719 1566 possible map and a non-dummy shared_info. */
60223a32 1567 per_cpu(xen_vcpu, 0) = &HYPERVISOR_shared_info->vcpu_info[0];
5ead97c8 1568
55d80856 1569 local_irq_disable();
2ce802f6 1570 early_boot_irqs_disabled = true;
55d80856 1571
084a2a4e 1572 xen_raw_console_write("mapping kernel into physical memory\n");
3699aad0 1573 xen_setup_kernel_pagetable((pgd_t *)xen_start_info->pt_base, xen_start_info->nr_pages);
5ead97c8 1574
47591df5
JG
1575 /*
1576 * Modify the cache mode translation tables to match Xen's PAT
1577 * configuration.
1578 */
9cd25aac
BP
1579 rdmsrl(MSR_IA32_CR_PAT, pat);
1580 pat_init_cache_modes(pat);
47591df5 1581
5ead97c8
JF
1582 /* keep using Xen gdt for now; no urgent need to change it */
1583
e68266b7 1584#ifdef CONFIG_X86_32
93b1eab3 1585 pv_info.kernel_rpl = 1;
5ead97c8 1586 if (xen_feature(XENFEAT_supervisor_mode_kernel))
93b1eab3 1587 pv_info.kernel_rpl = 0;
e68266b7
IC
1588#else
1589 pv_info.kernel_rpl = 0;
1590#endif
5ead97c8 1591 /* set the limit of our address space */
fb1d8404 1592 xen_reserve_top();
5ead97c8 1593
d285d683
MR
1594 /* PVH: runs at default kernel iopl of 0 */
1595 if (!xen_pvh_domain()) {
1596 /*
1597 * We used to do this in xen_arch_setup, but that is too late
1598 * on AMD were early_cpu_init (run before ->arch_setup()) calls
1599 * early_amd_init which pokes 0xcf8 port.
1600 */
1601 set_iopl.iopl = 1;
1602 rc = HYPERVISOR_physdev_op(PHYSDEVOP_set_iopl, &set_iopl);
1603 if (rc != 0)
1604 xen_raw_printk("physdev_op failed %d\n", rc);
1605 }
ec35a69c 1606
7d087b68 1607#ifdef CONFIG_X86_32
5ead97c8
JF
1608 /* set up basic CPUID stuff */
1609 cpu_detect(&new_cpu_data);
60e019eb 1610 set_cpu_cap(&new_cpu_data, X86_FEATURE_FPU);
d560bc61 1611 new_cpu_data.wp_works_ok = 1;
5ead97c8 1612 new_cpu_data.x86_capability[0] = cpuid_edx(1);
7d087b68 1613#endif
5ead97c8 1614
d1e9abd6
JG
1615 if (xen_start_info->mod_start) {
1616 if (xen_start_info->flags & SIF_MOD_START_PFN)
1617 initrd_start = PFN_PHYS(xen_start_info->mod_start);
1618 else
1619 initrd_start = __pa(xen_start_info->mod_start);
1620 }
1621
5ead97c8 1622 /* Poke various useful things into boot_params */
30c82645 1623 boot_params.hdr.type_of_loader = (9 << 4) | 0;
d1e9abd6 1624 boot_params.hdr.ramdisk_image = initrd_start;
30c82645 1625 boot_params.hdr.ramdisk_size = xen_start_info->mod_len;
b7c3c5c1 1626 boot_params.hdr.cmd_line_ptr = __pa(xen_start_info->cmd_line);
5ead97c8 1627
6e833587 1628 if (!xen_initial_domain()) {
83abc70a 1629 add_preferred_console("xenboot", 0, NULL);
9e124fe1 1630 add_preferred_console("tty", 0, NULL);
b8c2d3df 1631 add_preferred_console("hvc", 0, NULL);
b5401a96
AN
1632 if (pci_xen)
1633 x86_init.pci.arch_init = pci_xen_init;
5d990b62 1634 } else {
c2419b4a
JF
1635 const struct dom0_vga_console_info *info =
1636 (void *)((char *)xen_start_info +
1637 xen_start_info->console.dom0.info_off);
ffb8b233
KRW
1638 struct xen_platform_op op = {
1639 .cmd = XENPF_firmware_info,
1640 .interface_version = XENPF_INTERFACE_VERSION,
1641 .u.firmware_info.type = XEN_FW_KBD_SHIFT_FLAGS,
1642 };
c2419b4a
JF
1643
1644 xen_init_vga(info, xen_start_info->console.dom0.info_size);
1645 xen_start_info->console.domU.mfn = 0;
1646 xen_start_info->console.domU.evtchn = 0;
1647
ffb8b233
KRW
1648 if (HYPERVISOR_dom0_op(&op) == 0)
1649 boot_params.kbd_status = op.u.firmware_info.u.kbd_shift_flags;
1650
5d990b62
CW
1651 /* Make sure ACS will be enabled */
1652 pci_request_acs();
211063dc
KRW
1653
1654 xen_acpi_sleep_register();
bd49940a
KRW
1655
1656 /* Avoid searching for BIOS MP tables */
1657 x86_init.mpparse.find_smp_config = x86_init_noop;
1658 x86_init.mpparse.get_smp_config = x86_init_uint_noop;
96f28bc6
DV
1659
1660 xen_boot_params_init_edd();
9e124fe1 1661 }
76a8df7b
DV
1662#ifdef CONFIG_PCI
1663 /* PCI BIOS service won't work from a PV guest. */
1664 pci_probe &= ~PCI_PROBE_BIOS;
1665#endif
084a2a4e
JF
1666 xen_raw_console_write("about to get started...\n");
1667
499d19b8
JF
1668 xen_setup_runstate_info(0);
1669
c7341d6a 1670 xen_efi_init();
be81c8a1 1671
5ead97c8 1672 /* Start the world */
f5d36de0 1673#ifdef CONFIG_X86_32
f0d43100 1674 i386_start_kernel();
f5d36de0 1675#else
5054daa2 1676 cr4_init_shadow(); /* 32b kernel does this in i386_start_kernel() */
084a2a4e 1677 x86_64_start_reservations((char *)__pa_symbol(&boot_params));
f5d36de0 1678#endif
5ead97c8 1679}
bee6ab53 1680
e9daff24 1681void __ref xen_hvm_init_shared_info(void)
bee6ab53 1682{
e9daff24 1683 int cpu;
bee6ab53 1684 struct xen_add_to_physmap xatp;
e9daff24 1685 static struct shared_info *shared_info_page = 0;
bee6ab53 1686
e9daff24
KRW
1687 if (!shared_info_page)
1688 shared_info_page = (struct shared_info *)
1689 extend_brk(PAGE_SIZE, PAGE_SIZE);
bee6ab53
SY
1690 xatp.domid = DOMID_SELF;
1691 xatp.idx = 0;
1692 xatp.space = XENMAPSPACE_shared_info;
e9daff24 1693 xatp.gpfn = __pa(shared_info_page) >> PAGE_SHIFT;
bee6ab53
SY
1694 if (HYPERVISOR_memory_op(XENMEM_add_to_physmap, &xatp))
1695 BUG();
1696
e9daff24 1697 HYPERVISOR_shared_info = (struct shared_info *)shared_info_page;
bee6ab53 1698
016b6f5f
SS
1699 /* xen_vcpu is a pointer to the vcpu_info struct in the shared_info
1700 * page, we use it in the event channel upcall and in some pvclock
1701 * related functions. We don't need the vcpu_info placement
1702 * optimizations because we don't use any pv_mmu or pv_irq op on
e9daff24
KRW
1703 * HVM.
1704 * When xen_hvm_init_shared_info is run at boot time only vcpu 0 is
1705 * online but xen_hvm_init_shared_info is run at resume time too and
1706 * in that case multiple vcpus might be online. */
1707 for_each_online_cpu(cpu) {
d5b17dbf
KRW
1708 /* Leave it to be NULL. */
1709 if (cpu >= MAX_VIRT_CPUS)
1710 continue;
016b6f5f
SS
1711 per_cpu(xen_vcpu, cpu) = &HYPERVISOR_shared_info->vcpu_info[cpu];
1712 }
bee6ab53
SY
1713}
1714
e9daff24 1715#ifdef CONFIG_XEN_PVHVM
4ff2d062
OH
1716static void __init init_hvm_pv_info(void)
1717{
e9daff24 1718 int major, minor;
5eb65be2 1719 uint32_t eax, ebx, ecx, edx, pages, msr, base;
4ff2d062
OH
1720 u64 pfn;
1721
1722 base = xen_cpuid_base();
e9daff24
KRW
1723 cpuid(base + 1, &eax, &ebx, &ecx, &edx);
1724
1725 major = eax >> 16;
1726 minor = eax & 0xffff;
1727 printk(KERN_INFO "Xen version %d.%d.\n", major, minor);
1728
4ff2d062
OH
1729 cpuid(base + 2, &pages, &msr, &ecx, &edx);
1730
1731 pfn = __pa(hypercall_page);
1732 wrmsr_safe(msr, (u32)pfn, (u32)(pfn >> 32));
1733
1734 xen_setup_features();
1735
1736 pv_info.name = "Xen HVM";
1737
1738 xen_domain_type = XEN_HVM_DOMAIN;
1739}
1740
148f9bb8
PG
1741static int xen_hvm_cpu_notify(struct notifier_block *self, unsigned long action,
1742 void *hcpu)
38e20b07
SY
1743{
1744 int cpu = (long)hcpu;
1745 switch (action) {
1746 case CPU_UP_PREPARE:
90d4f553 1747 xen_vcpu_setup(cpu);
7918c92a 1748 if (xen_have_vector_callback) {
7918c92a
KRW
1749 if (xen_feature(XENFEAT_hvm_safe_pvclock))
1750 xen_setup_timer(cpu);
1751 }
38e20b07
SY
1752 break;
1753 default:
1754 break;
1755 }
1756 return NOTIFY_OK;
1757}
1758
148f9bb8 1759static struct notifier_block xen_hvm_cpu_notifier = {
38e20b07
SY
1760 .notifier_call = xen_hvm_cpu_notify,
1761};
1762
bee6ab53
SY
1763static void __init xen_hvm_guest_init(void)
1764{
a71dbdaa
BO
1765 if (xen_pv_domain())
1766 return;
1767
4ff2d062 1768 init_hvm_pv_info();
bee6ab53 1769
016b6f5f 1770 xen_hvm_init_shared_info();
38e20b07 1771
669b0ae9
VC
1772 xen_panic_handler_init();
1773
38e20b07
SY
1774 if (xen_feature(XENFEAT_hvm_callback_vector))
1775 xen_have_vector_callback = 1;
99bbb3a8 1776 xen_hvm_smp_init();
38e20b07 1777 register_cpu_notifier(&xen_hvm_cpu_notifier);
c1c5413a 1778 xen_unplug_emulated_devices();
38e20b07 1779 x86_init.irqs.intr_init = xen_init_IRQ;
409771d2 1780 xen_hvm_init_time_ops();
59151001 1781 xen_hvm_init_mmu_ops();
bee6ab53 1782}
a71dbdaa 1783#endif
bee6ab53 1784
8d693b91
KRW
1785static bool xen_nopv = false;
1786static __init int xen_parse_nopv(char *arg)
1787{
1788 xen_nopv = true;
1789 return 0;
1790}
1791early_param("xen_nopv", xen_parse_nopv);
1792
a71dbdaa 1793static uint32_t __init xen_platform(void)
bee6ab53 1794{
8d693b91
KRW
1795 if (xen_nopv)
1796 return 0;
1797
9df56f19 1798 return xen_cpuid_base();
bee6ab53
SY
1799}
1800
d9b8ca84
SY
1801bool xen_hvm_need_lapic(void)
1802{
8d693b91
KRW
1803 if (xen_nopv)
1804 return false;
d9b8ca84
SY
1805 if (xen_pv_domain())
1806 return false;
1807 if (!xen_hvm_domain())
1808 return false;
1809 if (xen_feature(XENFEAT_hvm_pirqs) && xen_have_vector_callback)
1810 return false;
1811 return true;
1812}
1813EXPORT_SYMBOL_GPL(xen_hvm_need_lapic);
1814
a71dbdaa
BO
1815static void xen_set_cpu_features(struct cpuinfo_x86 *c)
1816{
1817 if (xen_pv_domain())
1818 clear_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS);
1819}
1820
1821const struct hypervisor_x86 x86_hyper_xen = {
1822 .name = "Xen",
1823 .detect = xen_platform,
1824#ifdef CONFIG_XEN_PVHVM
bee6ab53 1825 .init_platform = xen_hvm_guest_init,
a71dbdaa 1826#endif
4cca6ea0 1827 .x2apic_available = xen_x2apic_para_available,
a71dbdaa 1828 .set_cpu_features = xen_set_cpu_features,
bee6ab53 1829};
a71dbdaa 1830EXPORT_SYMBOL(x86_hyper_xen);
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