Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Local APIC handling, local APIC timers | |
3 | * | |
4 | * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
5 | * | |
6 | * Fixes | |
7 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
8 | * thanks to Eric Gilmore | |
9 | * and Rolf G. Tews | |
10 | * for testing these extensively. | |
11 | * Maciej W. Rozycki : Various updates and fixes. | |
12 | * Mikael Pettersson : Power Management for UP-APIC. | |
13 | * Pavel Machek and | |
14 | * Mikael Pettersson : PM converted to driver model. | |
15 | */ | |
16 | ||
17 | #include <linux/config.h> | |
18 | #include <linux/init.h> | |
19 | ||
20 | #include <linux/mm.h> | |
1da177e4 LT |
21 | #include <linux/delay.h> |
22 | #include <linux/bootmem.h> | |
23 | #include <linux/smp_lock.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/mc146818rtc.h> | |
26 | #include <linux/kernel_stat.h> | |
27 | #include <linux/sysdev.h> | |
d25bf7e5 | 28 | #include <linux/module.h> |
1da177e4 LT |
29 | |
30 | #include <asm/atomic.h> | |
31 | #include <asm/smp.h> | |
32 | #include <asm/mtrr.h> | |
33 | #include <asm/mpspec.h> | |
34 | #include <asm/pgalloc.h> | |
35 | #include <asm/mach_apic.h> | |
75152114 | 36 | #include <asm/nmi.h> |
95833c83 | 37 | #include <asm/idle.h> |
1da177e4 LT |
38 | |
39 | int apic_verbosity; | |
40 | ||
41 | int disable_apic_timer __initdata; | |
42 | ||
d25bf7e5 VP |
43 | /* |
44 | * cpu_mask that denotes the CPUs that needs timer interrupt coming in as | |
45 | * IPIs in place of local APIC timers | |
46 | */ | |
47 | static cpumask_t timer_interrupt_broadcast_ipi_mask; | |
48 | ||
1da177e4 LT |
49 | /* Using APIC to generate smp_local_timer_interrupt? */ |
50 | int using_apic_timer = 0; | |
51 | ||
1da177e4 LT |
52 | static void apic_pm_activate(void); |
53 | ||
54 | void enable_NMI_through_LVT0 (void * dummy) | |
55 | { | |
11a8e778 | 56 | unsigned int v; |
1da177e4 | 57 | |
1da177e4 | 58 | v = APIC_DM_NMI; /* unmask and set to NMI */ |
11a8e778 | 59 | apic_write(APIC_LVT0, v); |
1da177e4 LT |
60 | } |
61 | ||
62 | int get_maxlvt(void) | |
63 | { | |
11a8e778 | 64 | unsigned int v, maxlvt; |
1da177e4 LT |
65 | |
66 | v = apic_read(APIC_LVR); | |
1da177e4 LT |
67 | maxlvt = GET_APIC_MAXLVT(v); |
68 | return maxlvt; | |
69 | } | |
70 | ||
71 | void clear_local_APIC(void) | |
72 | { | |
73 | int maxlvt; | |
74 | unsigned int v; | |
75 | ||
76 | maxlvt = get_maxlvt(); | |
77 | ||
78 | /* | |
79 | * Masking an LVT entry on a P6 can trigger a local APIC error | |
80 | * if the vector is zero. Mask LVTERR first to prevent this. | |
81 | */ | |
82 | if (maxlvt >= 3) { | |
83 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ | |
11a8e778 | 84 | apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); |
1da177e4 LT |
85 | } |
86 | /* | |
87 | * Careful: we have to set masks only first to deassert | |
88 | * any level-triggered sources. | |
89 | */ | |
90 | v = apic_read(APIC_LVTT); | |
11a8e778 | 91 | apic_write(APIC_LVTT, v | APIC_LVT_MASKED); |
1da177e4 | 92 | v = apic_read(APIC_LVT0); |
11a8e778 | 93 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
1da177e4 | 94 | v = apic_read(APIC_LVT1); |
11a8e778 | 95 | apic_write(APIC_LVT1, v | APIC_LVT_MASKED); |
1da177e4 LT |
96 | if (maxlvt >= 4) { |
97 | v = apic_read(APIC_LVTPC); | |
11a8e778 | 98 | apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); |
1da177e4 LT |
99 | } |
100 | ||
101 | /* | |
102 | * Clean APIC state for other OSs: | |
103 | */ | |
11a8e778 AK |
104 | apic_write(APIC_LVTT, APIC_LVT_MASKED); |
105 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
106 | apic_write(APIC_LVT1, APIC_LVT_MASKED); | |
1da177e4 | 107 | if (maxlvt >= 3) |
11a8e778 | 108 | apic_write(APIC_LVTERR, APIC_LVT_MASKED); |
1da177e4 | 109 | if (maxlvt >= 4) |
11a8e778 | 110 | apic_write(APIC_LVTPC, APIC_LVT_MASKED); |
1da177e4 | 111 | v = GET_APIC_VERSION(apic_read(APIC_LVR)); |
5a40b7c2 AK |
112 | apic_write(APIC_ESR, 0); |
113 | apic_read(APIC_ESR); | |
1da177e4 LT |
114 | } |
115 | ||
116 | void __init connect_bsp_APIC(void) | |
117 | { | |
118 | if (pic_mode) { | |
119 | /* | |
120 | * Do not trust the local APIC being empty at bootup. | |
121 | */ | |
122 | clear_local_APIC(); | |
123 | /* | |
124 | * PIC mode, enable APIC mode in the IMCR, i.e. | |
125 | * connect BSP's local APIC to INT and NMI lines. | |
126 | */ | |
127 | apic_printk(APIC_VERBOSE, "leaving PIC mode, enabling APIC mode.\n"); | |
128 | outb(0x70, 0x22); | |
129 | outb(0x01, 0x23); | |
130 | } | |
131 | } | |
132 | ||
208fb931 | 133 | void disconnect_bsp_APIC(int virt_wire_setup) |
1da177e4 LT |
134 | { |
135 | if (pic_mode) { | |
136 | /* | |
137 | * Put the board back into PIC mode (has an effect | |
138 | * only on certain older boards). Note that APIC | |
139 | * interrupts, including IPIs, won't work beyond | |
140 | * this point! The only exception are INIT IPIs. | |
141 | */ | |
142 | apic_printk(APIC_QUIET, "disabling APIC mode, entering PIC mode.\n"); | |
143 | outb(0x70, 0x22); | |
144 | outb(0x00, 0x23); | |
145 | } | |
208fb931 EB |
146 | else { |
147 | /* Go back to Virtual Wire compatibility mode */ | |
148 | unsigned long value; | |
149 | ||
150 | /* For the spurious interrupt use vector F, and enable it */ | |
151 | value = apic_read(APIC_SPIV); | |
152 | value &= ~APIC_VECTOR_MASK; | |
153 | value |= APIC_SPIV_APIC_ENABLED; | |
154 | value |= 0xf; | |
11a8e778 | 155 | apic_write(APIC_SPIV, value); |
208fb931 EB |
156 | |
157 | if (!virt_wire_setup) { | |
158 | /* For LVT0 make it edge triggered, active high, external and enabled */ | |
159 | value = apic_read(APIC_LVT0); | |
160 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
161 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
162 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED ); | |
163 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
164 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); | |
11a8e778 | 165 | apic_write(APIC_LVT0, value); |
208fb931 EB |
166 | } |
167 | else { | |
168 | /* Disable LVT0 */ | |
11a8e778 | 169 | apic_write(APIC_LVT0, APIC_LVT_MASKED); |
208fb931 EB |
170 | } |
171 | ||
172 | /* For LVT1 make it edge triggered, active high, nmi and enabled */ | |
173 | value = apic_read(APIC_LVT1); | |
174 | value &= ~( | |
175 | APIC_MODE_MASK | APIC_SEND_PENDING | | |
176 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
177 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
178 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
179 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); | |
11a8e778 | 180 | apic_write(APIC_LVT1, value); |
208fb931 | 181 | } |
1da177e4 LT |
182 | } |
183 | ||
184 | void disable_local_APIC(void) | |
185 | { | |
186 | unsigned int value; | |
187 | ||
188 | clear_local_APIC(); | |
189 | ||
190 | /* | |
191 | * Disable APIC (implies clearing of registers | |
192 | * for 82489DX!). | |
193 | */ | |
194 | value = apic_read(APIC_SPIV); | |
195 | value &= ~APIC_SPIV_APIC_ENABLED; | |
11a8e778 | 196 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
197 | } |
198 | ||
199 | /* | |
200 | * This is to verify that we're looking at a real local APIC. | |
201 | * Check these against your board if the CPUs aren't getting | |
202 | * started for no apparent reason. | |
203 | */ | |
204 | int __init verify_local_APIC(void) | |
205 | { | |
206 | unsigned int reg0, reg1; | |
207 | ||
208 | /* | |
209 | * The version register is read-only in a real APIC. | |
210 | */ | |
211 | reg0 = apic_read(APIC_LVR); | |
212 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); | |
213 | apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); | |
214 | reg1 = apic_read(APIC_LVR); | |
215 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); | |
216 | ||
217 | /* | |
218 | * The two version reads above should print the same | |
219 | * numbers. If the second one is different, then we | |
220 | * poke at a non-APIC. | |
221 | */ | |
222 | if (reg1 != reg0) | |
223 | return 0; | |
224 | ||
225 | /* | |
226 | * Check if the version looks reasonably. | |
227 | */ | |
228 | reg1 = GET_APIC_VERSION(reg0); | |
229 | if (reg1 == 0x00 || reg1 == 0xff) | |
230 | return 0; | |
231 | reg1 = get_maxlvt(); | |
232 | if (reg1 < 0x02 || reg1 == 0xff) | |
233 | return 0; | |
234 | ||
235 | /* | |
236 | * The ID register is read/write in a real APIC. | |
237 | */ | |
238 | reg0 = apic_read(APIC_ID); | |
239 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); | |
240 | apic_write(APIC_ID, reg0 ^ APIC_ID_MASK); | |
241 | reg1 = apic_read(APIC_ID); | |
242 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1); | |
243 | apic_write(APIC_ID, reg0); | |
244 | if (reg1 != (reg0 ^ APIC_ID_MASK)) | |
245 | return 0; | |
246 | ||
247 | /* | |
248 | * The next two are just to see if we have sane values. | |
249 | * They're only really relevant if we're in Virtual Wire | |
250 | * compatibility mode, but most boxes are anymore. | |
251 | */ | |
252 | reg0 = apic_read(APIC_LVT0); | |
253 | apic_printk(APIC_DEBUG,"Getting LVT0: %x\n", reg0); | |
254 | reg1 = apic_read(APIC_LVT1); | |
255 | apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); | |
256 | ||
257 | return 1; | |
258 | } | |
259 | ||
260 | void __init sync_Arb_IDs(void) | |
261 | { | |
262 | /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */ | |
263 | unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR)); | |
264 | if (ver >= 0x14) /* P4 or higher */ | |
265 | return; | |
266 | ||
267 | /* | |
268 | * Wait for idle. | |
269 | */ | |
270 | apic_wait_icr_idle(); | |
271 | ||
272 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); | |
11a8e778 | 273 | apic_write(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG |
1da177e4 LT |
274 | | APIC_DM_INIT); |
275 | } | |
276 | ||
277 | extern void __error_in_apic_c (void); | |
278 | ||
279 | /* | |
280 | * An initial setup of the virtual wire mode. | |
281 | */ | |
282 | void __init init_bsp_APIC(void) | |
283 | { | |
11a8e778 | 284 | unsigned int value; |
1da177e4 LT |
285 | |
286 | /* | |
287 | * Don't do the setup now if we have a SMP BIOS as the | |
288 | * through-I/O-APIC virtual wire mode might be active. | |
289 | */ | |
290 | if (smp_found_config || !cpu_has_apic) | |
291 | return; | |
292 | ||
293 | value = apic_read(APIC_LVR); | |
1da177e4 LT |
294 | |
295 | /* | |
296 | * Do not trust the local APIC being empty at bootup. | |
297 | */ | |
298 | clear_local_APIC(); | |
299 | ||
300 | /* | |
301 | * Enable APIC. | |
302 | */ | |
303 | value = apic_read(APIC_SPIV); | |
304 | value &= ~APIC_VECTOR_MASK; | |
305 | value |= APIC_SPIV_APIC_ENABLED; | |
306 | value |= APIC_SPIV_FOCUS_DISABLED; | |
307 | value |= SPURIOUS_APIC_VECTOR; | |
11a8e778 | 308 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
309 | |
310 | /* | |
311 | * Set up the virtual wire mode. | |
312 | */ | |
11a8e778 | 313 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 | 314 | value = APIC_DM_NMI; |
11a8e778 | 315 | apic_write(APIC_LVT1, value); |
1da177e4 LT |
316 | } |
317 | ||
e6982c67 | 318 | void __cpuinit setup_local_APIC (void) |
1da177e4 | 319 | { |
11a8e778 | 320 | unsigned int value, maxlvt; |
1da177e4 | 321 | |
1da177e4 | 322 | value = apic_read(APIC_LVR); |
1da177e4 LT |
323 | |
324 | if ((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f) | |
325 | __error_in_apic_c(); | |
326 | ||
327 | /* | |
328 | * Double-check whether this APIC is really registered. | |
329 | * This is meaningless in clustered apic mode, so we skip it. | |
330 | */ | |
331 | if (!apic_id_registered()) | |
332 | BUG(); | |
333 | ||
334 | /* | |
335 | * Intel recommends to set DFR, LDR and TPR before enabling | |
336 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
337 | * document number 292116). So here it goes... | |
338 | */ | |
339 | init_apic_ldr(); | |
340 | ||
341 | /* | |
342 | * Set Task Priority to 'accept all'. We never change this | |
343 | * later on. | |
344 | */ | |
345 | value = apic_read(APIC_TASKPRI); | |
346 | value &= ~APIC_TPRI_MASK; | |
11a8e778 | 347 | apic_write(APIC_TASKPRI, value); |
1da177e4 LT |
348 | |
349 | /* | |
350 | * Now that we are all set up, enable the APIC | |
351 | */ | |
352 | value = apic_read(APIC_SPIV); | |
353 | value &= ~APIC_VECTOR_MASK; | |
354 | /* | |
355 | * Enable APIC | |
356 | */ | |
357 | value |= APIC_SPIV_APIC_ENABLED; | |
358 | ||
359 | /* | |
360 | * Some unknown Intel IO/APIC (or APIC) errata is biting us with | |
361 | * certain networking cards. If high frequency interrupts are | |
362 | * happening on a particular IOAPIC pin, plus the IOAPIC routing | |
363 | * entry is masked/unmasked at a high rate as well then sooner or | |
364 | * later IOAPIC line gets 'stuck', no more interrupts are received | |
365 | * from the device. If focus CPU is disabled then the hang goes | |
366 | * away, oh well :-( | |
367 | * | |
368 | * [ This bug can be reproduced easily with a level-triggered | |
369 | * PCI Ne2000 networking cards and PII/PIII processors, dual | |
370 | * BX chipset. ] | |
371 | */ | |
372 | /* | |
373 | * Actually disabling the focus CPU check just makes the hang less | |
374 | * frequent as it makes the interrupt distributon model be more | |
375 | * like LRU than MRU (the short-term load is more even across CPUs). | |
376 | * See also the comment in end_level_ioapic_irq(). --macro | |
377 | */ | |
378 | #if 1 | |
379 | /* Enable focus processor (bit==0) */ | |
380 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
381 | #else | |
382 | /* Disable focus processor (bit==1) */ | |
383 | value |= APIC_SPIV_FOCUS_DISABLED; | |
384 | #endif | |
385 | /* | |
386 | * Set spurious IRQ vector | |
387 | */ | |
388 | value |= SPURIOUS_APIC_VECTOR; | |
11a8e778 | 389 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
390 | |
391 | /* | |
392 | * Set up LVT0, LVT1: | |
393 | * | |
394 | * set up through-local-APIC on the BP's LINT0. This is not | |
395 | * strictly necessary in pure symmetric-IO mode, but sometimes | |
396 | * we delegate interrupts to the 8259A. | |
397 | */ | |
398 | /* | |
399 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro | |
400 | */ | |
401 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; | |
402 | if (!smp_processor_id() && (pic_mode || !value)) { | |
403 | value = APIC_DM_EXTINT; | |
404 | apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", smp_processor_id()); | |
405 | } else { | |
406 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; | |
407 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", smp_processor_id()); | |
408 | } | |
11a8e778 | 409 | apic_write(APIC_LVT0, value); |
1da177e4 LT |
410 | |
411 | /* | |
412 | * only the BP should see the LINT1 NMI signal, obviously. | |
413 | */ | |
414 | if (!smp_processor_id()) | |
415 | value = APIC_DM_NMI; | |
416 | else | |
417 | value = APIC_DM_NMI | APIC_LVT_MASKED; | |
11a8e778 | 418 | apic_write(APIC_LVT1, value); |
1da177e4 | 419 | |
61c11341 | 420 | { |
1da177e4 LT |
421 | unsigned oldvalue; |
422 | maxlvt = get_maxlvt(); | |
1da177e4 LT |
423 | oldvalue = apic_read(APIC_ESR); |
424 | value = ERROR_APIC_VECTOR; // enables sending errors | |
11a8e778 | 425 | apic_write(APIC_LVTERR, value); |
1da177e4 LT |
426 | /* |
427 | * spec says clear errors after enabling vector. | |
428 | */ | |
429 | if (maxlvt > 3) | |
430 | apic_write(APIC_ESR, 0); | |
431 | value = apic_read(APIC_ESR); | |
432 | if (value != oldvalue) | |
433 | apic_printk(APIC_VERBOSE, | |
434 | "ESR value after enabling vector: %08x, after %08x\n", | |
435 | oldvalue, value); | |
1da177e4 LT |
436 | } |
437 | ||
438 | nmi_watchdog_default(); | |
439 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
440 | setup_apic_nmi_watchdog(); | |
441 | apic_pm_activate(); | |
442 | } | |
443 | ||
444 | #ifdef CONFIG_PM | |
445 | ||
446 | static struct { | |
447 | /* 'active' is true if the local APIC was enabled by us and | |
448 | not the BIOS; this signifies that we are also responsible | |
449 | for disabling it before entering apm/acpi suspend */ | |
450 | int active; | |
451 | /* r/w apic fields */ | |
452 | unsigned int apic_id; | |
453 | unsigned int apic_taskpri; | |
454 | unsigned int apic_ldr; | |
455 | unsigned int apic_dfr; | |
456 | unsigned int apic_spiv; | |
457 | unsigned int apic_lvtt; | |
458 | unsigned int apic_lvtpc; | |
459 | unsigned int apic_lvt0; | |
460 | unsigned int apic_lvt1; | |
461 | unsigned int apic_lvterr; | |
462 | unsigned int apic_tmict; | |
463 | unsigned int apic_tdcr; | |
464 | unsigned int apic_thmr; | |
465 | } apic_pm_state; | |
466 | ||
0b9c33a7 | 467 | static int lapic_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 LT |
468 | { |
469 | unsigned long flags; | |
470 | ||
471 | if (!apic_pm_state.active) | |
472 | return 0; | |
473 | ||
474 | apic_pm_state.apic_id = apic_read(APIC_ID); | |
475 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); | |
476 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); | |
477 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); | |
478 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); | |
479 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); | |
480 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); | |
481 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); | |
482 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); | |
483 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); | |
484 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); | |
485 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); | |
486 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); | |
487 | local_save_flags(flags); | |
488 | local_irq_disable(); | |
489 | disable_local_APIC(); | |
490 | local_irq_restore(flags); | |
491 | return 0; | |
492 | } | |
493 | ||
494 | static int lapic_resume(struct sys_device *dev) | |
495 | { | |
496 | unsigned int l, h; | |
497 | unsigned long flags; | |
498 | ||
499 | if (!apic_pm_state.active) | |
500 | return 0; | |
501 | ||
502 | /* XXX: Pavel needs this for S3 resume, but can't explain why */ | |
503 | set_fixmap_nocache(FIX_APIC_BASE, APIC_DEFAULT_PHYS_BASE); | |
504 | ||
505 | local_irq_save(flags); | |
506 | rdmsr(MSR_IA32_APICBASE, l, h); | |
507 | l &= ~MSR_IA32_APICBASE_BASE; | |
508 | l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE; | |
509 | wrmsr(MSR_IA32_APICBASE, l, h); | |
510 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); | |
511 | apic_write(APIC_ID, apic_pm_state.apic_id); | |
512 | apic_write(APIC_DFR, apic_pm_state.apic_dfr); | |
513 | apic_write(APIC_LDR, apic_pm_state.apic_ldr); | |
514 | apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); | |
515 | apic_write(APIC_SPIV, apic_pm_state.apic_spiv); | |
516 | apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); | |
517 | apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); | |
518 | apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); | |
519 | apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); | |
520 | apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); | |
521 | apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); | |
522 | apic_write(APIC_TMICT, apic_pm_state.apic_tmict); | |
523 | apic_write(APIC_ESR, 0); | |
524 | apic_read(APIC_ESR); | |
525 | apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); | |
526 | apic_write(APIC_ESR, 0); | |
527 | apic_read(APIC_ESR); | |
528 | local_irq_restore(flags); | |
529 | return 0; | |
530 | } | |
531 | ||
532 | static struct sysdev_class lapic_sysclass = { | |
533 | set_kset_name("lapic"), | |
534 | .resume = lapic_resume, | |
535 | .suspend = lapic_suspend, | |
536 | }; | |
537 | ||
538 | static struct sys_device device_lapic = { | |
539 | .id = 0, | |
540 | .cls = &lapic_sysclass, | |
541 | }; | |
542 | ||
e6982c67 | 543 | static void __cpuinit apic_pm_activate(void) |
1da177e4 LT |
544 | { |
545 | apic_pm_state.active = 1; | |
546 | } | |
547 | ||
548 | static int __init init_lapic_sysfs(void) | |
549 | { | |
550 | int error; | |
551 | if (!cpu_has_apic) | |
552 | return 0; | |
553 | /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ | |
554 | error = sysdev_class_register(&lapic_sysclass); | |
555 | if (!error) | |
556 | error = sysdev_register(&device_lapic); | |
557 | return error; | |
558 | } | |
559 | device_initcall(init_lapic_sysfs); | |
560 | ||
561 | #else /* CONFIG_PM */ | |
562 | ||
563 | static void apic_pm_activate(void) { } | |
564 | ||
565 | #endif /* CONFIG_PM */ | |
566 | ||
567 | static int __init apic_set_verbosity(char *str) | |
568 | { | |
569 | if (strcmp("debug", str) == 0) | |
570 | apic_verbosity = APIC_DEBUG; | |
571 | else if (strcmp("verbose", str) == 0) | |
572 | apic_verbosity = APIC_VERBOSE; | |
573 | else | |
574 | printk(KERN_WARNING "APIC Verbosity level %s not recognised" | |
575 | " use apic=verbose or apic=debug", str); | |
576 | ||
577 | return 0; | |
578 | } | |
579 | ||
580 | __setup("apic=", apic_set_verbosity); | |
581 | ||
582 | /* | |
583 | * Detect and enable local APICs on non-SMP boards. | |
584 | * Original code written by Keir Fraser. | |
585 | * On AMD64 we trust the BIOS - if it says no APIC it is likely | |
586 | * not correctly set up (usually the APIC timer won't work etc.) | |
587 | */ | |
588 | ||
589 | static int __init detect_init_APIC (void) | |
590 | { | |
591 | if (!cpu_has_apic) { | |
592 | printk(KERN_INFO "No local APIC present\n"); | |
593 | return -1; | |
594 | } | |
595 | ||
596 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
597 | boot_cpu_id = 0; | |
598 | return 0; | |
599 | } | |
600 | ||
601 | void __init init_apic_mappings(void) | |
602 | { | |
603 | unsigned long apic_phys; | |
604 | ||
605 | /* | |
606 | * If no local APIC can be found then set up a fake all | |
607 | * zeroes page to simulate the local APIC and another | |
608 | * one for the IO-APIC. | |
609 | */ | |
610 | if (!smp_found_config && detect_init_APIC()) { | |
611 | apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); | |
612 | apic_phys = __pa(apic_phys); | |
613 | } else | |
614 | apic_phys = mp_lapic_addr; | |
615 | ||
616 | set_fixmap_nocache(FIX_APIC_BASE, apic_phys); | |
617 | apic_printk(APIC_VERBOSE,"mapped APIC to %16lx (%16lx)\n", APIC_BASE, apic_phys); | |
618 | ||
619 | /* | |
620 | * Fetch the APIC ID of the BSP in case we have a | |
621 | * default configuration (or the MP table is broken). | |
622 | */ | |
1d3fbbf9 | 623 | boot_cpu_id = GET_APIC_ID(apic_read(APIC_ID)); |
1da177e4 LT |
624 | |
625 | #ifdef CONFIG_X86_IO_APIC | |
626 | { | |
627 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
628 | int i; | |
629 | ||
630 | for (i = 0; i < nr_ioapics; i++) { | |
631 | if (smp_found_config) { | |
632 | ioapic_phys = mp_ioapics[i].mpc_apicaddr; | |
633 | } else { | |
634 | ioapic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); | |
635 | ioapic_phys = __pa(ioapic_phys); | |
636 | } | |
637 | set_fixmap_nocache(idx, ioapic_phys); | |
638 | apic_printk(APIC_VERBOSE,"mapped IOAPIC to %016lx (%016lx)\n", | |
639 | __fix_to_virt(idx), ioapic_phys); | |
640 | idx++; | |
641 | } | |
642 | } | |
643 | #endif | |
644 | } | |
645 | ||
646 | /* | |
647 | * This function sets up the local APIC timer, with a timeout of | |
648 | * 'clocks' APIC bus clock. During calibration we actually call | |
649 | * this function twice on the boot CPU, once with a bogus timeout | |
650 | * value, second time for real. The other (noncalibrating) CPUs | |
651 | * call this function only once, with the real, calibrated value. | |
652 | * | |
653 | * We do reads before writes even if unnecessary, to get around the | |
654 | * P5 APIC double write bug. | |
655 | */ | |
656 | ||
657 | #define APIC_DIVISOR 16 | |
658 | ||
659 | static void __setup_APIC_LVTT(unsigned int clocks) | |
660 | { | |
661 | unsigned int lvtt_value, tmp_value, ver; | |
d25bf7e5 | 662 | int cpu = smp_processor_id(); |
1da177e4 LT |
663 | |
664 | ver = GET_APIC_VERSION(apic_read(APIC_LVR)); | |
665 | lvtt_value = APIC_LVT_TIMER_PERIODIC | LOCAL_TIMER_VECTOR; | |
d25bf7e5 VP |
666 | |
667 | if (cpu_isset(cpu, timer_interrupt_broadcast_ipi_mask)) | |
668 | lvtt_value |= APIC_LVT_MASKED; | |
669 | ||
11a8e778 | 670 | apic_write(APIC_LVTT, lvtt_value); |
1da177e4 LT |
671 | |
672 | /* | |
673 | * Divide PICLK by 16 | |
674 | */ | |
675 | tmp_value = apic_read(APIC_TDCR); | |
11a8e778 | 676 | apic_write(APIC_TDCR, (tmp_value |
1da177e4 LT |
677 | & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
678 | | APIC_TDR_DIV_16); | |
679 | ||
11a8e778 | 680 | apic_write(APIC_TMICT, clocks/APIC_DIVISOR); |
1da177e4 LT |
681 | } |
682 | ||
683 | static void setup_APIC_timer(unsigned int clocks) | |
684 | { | |
685 | unsigned long flags; | |
686 | ||
687 | local_irq_save(flags); | |
688 | ||
1da177e4 LT |
689 | /* wait for irq slice */ |
690 | if (vxtime.hpet_address) { | |
691 | int trigger = hpet_readl(HPET_T0_CMP); | |
692 | while (hpet_readl(HPET_COUNTER) >= trigger) | |
693 | /* do nothing */ ; | |
694 | while (hpet_readl(HPET_COUNTER) < trigger) | |
695 | /* do nothing */ ; | |
696 | } else { | |
697 | int c1, c2; | |
698 | outb_p(0x00, 0x43); | |
699 | c2 = inb_p(0x40); | |
700 | c2 |= inb_p(0x40) << 8; | |
11a8e778 | 701 | do { |
1da177e4 LT |
702 | c1 = c2; |
703 | outb_p(0x00, 0x43); | |
704 | c2 = inb_p(0x40); | |
705 | c2 |= inb_p(0x40) << 8; | |
706 | } while (c2 - c1 < 300); | |
707 | } | |
708 | ||
709 | __setup_APIC_LVTT(clocks); | |
710 | ||
711 | local_irq_restore(flags); | |
712 | } | |
713 | ||
714 | /* | |
715 | * In this function we calibrate APIC bus clocks to the external | |
716 | * timer. Unfortunately we cannot use jiffies and the timer irq | |
717 | * to calibrate, since some later bootup code depends on getting | |
718 | * the first irq? Ugh. | |
719 | * | |
720 | * We want to do the calibration only once since we | |
721 | * want to have local timer irqs syncron. CPUs connected | |
722 | * by the same APIC bus have the very same bus frequency. | |
723 | * And we want to have irqs off anyways, no accidental | |
724 | * APIC irq that way. | |
725 | */ | |
726 | ||
727 | #define TICK_COUNT 100000000 | |
728 | ||
729 | static int __init calibrate_APIC_clock(void) | |
730 | { | |
731 | int apic, apic_start, tsc, tsc_start; | |
732 | int result; | |
733 | /* | |
734 | * Put whatever arbitrary (but long enough) timeout | |
735 | * value into the APIC clock, we just want to get the | |
736 | * counter running for calibration. | |
737 | */ | |
738 | __setup_APIC_LVTT(1000000000); | |
739 | ||
740 | apic_start = apic_read(APIC_TMCCT); | |
741 | rdtscl(tsc_start); | |
742 | ||
743 | do { | |
744 | apic = apic_read(APIC_TMCCT); | |
745 | rdtscl(tsc); | |
746 | } while ((tsc - tsc_start) < TICK_COUNT && (apic - apic_start) < TICK_COUNT); | |
747 | ||
748 | result = (apic_start - apic) * 1000L * cpu_khz / (tsc - tsc_start); | |
749 | ||
750 | printk(KERN_INFO "Detected %d.%03d MHz APIC timer.\n", | |
751 | result / 1000 / 1000, result / 1000 % 1000); | |
752 | ||
753 | return result * APIC_DIVISOR / HZ; | |
754 | } | |
755 | ||
756 | static unsigned int calibration_result; | |
757 | ||
758 | void __init setup_boot_APIC_clock (void) | |
759 | { | |
760 | if (disable_apic_timer) { | |
761 | printk(KERN_INFO "Disabling APIC timer\n"); | |
762 | return; | |
763 | } | |
764 | ||
765 | printk(KERN_INFO "Using local APIC timer interrupts.\n"); | |
766 | using_apic_timer = 1; | |
767 | ||
768 | local_irq_disable(); | |
769 | ||
770 | calibration_result = calibrate_APIC_clock(); | |
771 | /* | |
772 | * Now set up the timer for real. | |
773 | */ | |
774 | setup_APIC_timer(calibration_result); | |
775 | ||
776 | local_irq_enable(); | |
777 | } | |
778 | ||
e6982c67 | 779 | void __cpuinit setup_secondary_APIC_clock(void) |
1da177e4 LT |
780 | { |
781 | local_irq_disable(); /* FIXME: Do we need this? --RR */ | |
782 | setup_APIC_timer(calibration_result); | |
783 | local_irq_enable(); | |
784 | } | |
785 | ||
d25bf7e5 | 786 | void disable_APIC_timer(void) |
1da177e4 LT |
787 | { |
788 | if (using_apic_timer) { | |
789 | unsigned long v; | |
790 | ||
791 | v = apic_read(APIC_LVTT); | |
11a8e778 | 792 | apic_write(APIC_LVTT, v | APIC_LVT_MASKED); |
1da177e4 LT |
793 | } |
794 | } | |
795 | ||
796 | void enable_APIC_timer(void) | |
797 | { | |
d25bf7e5 VP |
798 | int cpu = smp_processor_id(); |
799 | ||
800 | if (using_apic_timer && | |
801 | !cpu_isset(cpu, timer_interrupt_broadcast_ipi_mask)) { | |
1da177e4 LT |
802 | unsigned long v; |
803 | ||
804 | v = apic_read(APIC_LVTT); | |
11a8e778 | 805 | apic_write(APIC_LVTT, v & ~APIC_LVT_MASKED); |
1da177e4 LT |
806 | } |
807 | } | |
808 | ||
d25bf7e5 VP |
809 | void switch_APIC_timer_to_ipi(void *cpumask) |
810 | { | |
811 | cpumask_t mask = *(cpumask_t *)cpumask; | |
812 | int cpu = smp_processor_id(); | |
813 | ||
814 | if (cpu_isset(cpu, mask) && | |
815 | !cpu_isset(cpu, timer_interrupt_broadcast_ipi_mask)) { | |
816 | disable_APIC_timer(); | |
817 | cpu_set(cpu, timer_interrupt_broadcast_ipi_mask); | |
818 | } | |
819 | } | |
820 | EXPORT_SYMBOL(switch_APIC_timer_to_ipi); | |
821 | ||
822 | void smp_send_timer_broadcast_ipi(void) | |
823 | { | |
824 | cpumask_t mask; | |
825 | ||
826 | cpus_and(mask, cpu_online_map, timer_interrupt_broadcast_ipi_mask); | |
827 | if (!cpus_empty(mask)) { | |
828 | send_IPI_mask(mask, LOCAL_TIMER_VECTOR); | |
829 | } | |
830 | } | |
831 | ||
832 | void switch_ipi_to_APIC_timer(void *cpumask) | |
833 | { | |
834 | cpumask_t mask = *(cpumask_t *)cpumask; | |
835 | int cpu = smp_processor_id(); | |
836 | ||
837 | if (cpu_isset(cpu, mask) && | |
838 | cpu_isset(cpu, timer_interrupt_broadcast_ipi_mask)) { | |
839 | cpu_clear(cpu, timer_interrupt_broadcast_ipi_mask); | |
840 | enable_APIC_timer(); | |
841 | } | |
842 | } | |
843 | EXPORT_SYMBOL(switch_ipi_to_APIC_timer); | |
844 | ||
1da177e4 LT |
845 | int setup_profiling_timer(unsigned int multiplier) |
846 | { | |
5a07a30c | 847 | return -EINVAL; |
1da177e4 LT |
848 | } |
849 | ||
89b831ef JS |
850 | #ifdef CONFIG_X86_MCE_AMD |
851 | void setup_threshold_lvt(unsigned long lvt_off) | |
852 | { | |
853 | unsigned int v = 0; | |
854 | unsigned long reg = (lvt_off << 4) + 0x500; | |
855 | v |= THRESHOLD_APIC_VECTOR; | |
856 | apic_write(reg, v); | |
857 | } | |
858 | #endif /* CONFIG_X86_MCE_AMD */ | |
859 | ||
1da177e4 LT |
860 | #undef APIC_DIVISOR |
861 | ||
862 | /* | |
863 | * Local timer interrupt handler. It does both profiling and | |
864 | * process statistics/rescheduling. | |
865 | * | |
866 | * We do profiling in every local tick, statistics/rescheduling | |
867 | * happen only every 'profiling multiplier' ticks. The default | |
868 | * multiplier is 1 and it can be changed by writing the new multiplier | |
869 | * value into /proc/profile. | |
870 | */ | |
871 | ||
872 | void smp_local_timer_interrupt(struct pt_regs *regs) | |
873 | { | |
1da177e4 | 874 | profile_tick(CPU_PROFILING, regs); |
1da177e4 | 875 | #ifdef CONFIG_SMP |
5a07a30c | 876 | update_process_times(user_mode(regs)); |
1da177e4 | 877 | #endif |
1da177e4 LT |
878 | /* |
879 | * We take the 'long' return path, and there every subsystem | |
880 | * grabs the appropriate locks (kernel lock/ irq lock). | |
881 | * | |
882 | * we might want to decouple profiling from the 'long path', | |
883 | * and do the profiling totally in assembly. | |
884 | * | |
885 | * Currently this isn't too much of an issue (performance wise), | |
886 | * we can take more than 100K local irqs per second on a 100 MHz P5. | |
887 | */ | |
888 | } | |
889 | ||
890 | /* | |
891 | * Local APIC timer interrupt. This is the most natural way for doing | |
892 | * local interrupts, but local timer interrupts can be emulated by | |
893 | * broadcast interrupts too. [in case the hw doesn't support APIC timers] | |
894 | * | |
895 | * [ if a single-CPU system runs an SMP kernel then we call the local | |
896 | * interrupt as well. Thus we cannot inline the local irq ... ] | |
897 | */ | |
898 | void smp_apic_timer_interrupt(struct pt_regs *regs) | |
899 | { | |
900 | /* | |
901 | * the NMI deadlock-detector uses this. | |
902 | */ | |
903 | add_pda(apic_timer_irqs, 1); | |
904 | ||
905 | /* | |
906 | * NOTE! We'd better ACK the irq immediately, | |
907 | * because timer handling can be slow. | |
908 | */ | |
909 | ack_APIC_irq(); | |
910 | /* | |
911 | * update_process_times() expects us to have done irq_enter(). | |
912 | * Besides, if we don't timer interrupts ignore the global | |
913 | * interrupt lock, which is the WrongThing (tm) to do. | |
914 | */ | |
95833c83 | 915 | exit_idle(); |
1da177e4 LT |
916 | irq_enter(); |
917 | smp_local_timer_interrupt(regs); | |
918 | irq_exit(); | |
919 | } | |
920 | ||
921 | /* | |
922 | * oem_force_hpet_timer -- force HPET mode for some boxes. | |
923 | * | |
924 | * Thus far, the major user of this is IBM's Summit2 series: | |
925 | * | |
926 | * Clustered boxes may have unsynced TSC problems if they are | |
927 | * multi-chassis. Use available data to take a good guess. | |
928 | * If in doubt, go HPET. | |
929 | */ | |
930 | __init int oem_force_hpet_timer(void) | |
931 | { | |
932 | int i, clusters, zeros; | |
933 | unsigned id; | |
934 | DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS); | |
935 | ||
376ec33f | 936 | bitmap_zero(clustermap, NUM_APIC_CLUSTERS); |
1da177e4 LT |
937 | |
938 | for (i = 0; i < NR_CPUS; i++) { | |
939 | id = bios_cpu_apicid[i]; | |
940 | if (id != BAD_APICID) | |
941 | __set_bit(APIC_CLUSTERID(id), clustermap); | |
942 | } | |
943 | ||
944 | /* Problem: Partially populated chassis may not have CPUs in some of | |
945 | * the APIC clusters they have been allocated. Only present CPUs have | |
946 | * bios_cpu_apicid entries, thus causing zeroes in the bitmap. Since | |
947 | * clusters are allocated sequentially, count zeros only if they are | |
948 | * bounded by ones. | |
949 | */ | |
950 | clusters = 0; | |
951 | zeros = 0; | |
952 | for (i = 0; i < NUM_APIC_CLUSTERS; i++) { | |
953 | if (test_bit(i, clustermap)) { | |
954 | clusters += 1 + zeros; | |
955 | zeros = 0; | |
956 | } else | |
957 | ++zeros; | |
958 | } | |
959 | ||
960 | /* | |
961 | * If clusters > 2, then should be multi-chassis. Return 1 for HPET. | |
962 | * Else return 0 to use TSC. | |
963 | * May have to revisit this when multi-core + hyperthreaded CPUs come | |
964 | * out, but AFAIK this will work even for them. | |
965 | */ | |
966 | return (clusters > 2); | |
967 | } | |
968 | ||
969 | /* | |
970 | * This interrupt should _never_ happen with our APIC/SMP architecture | |
971 | */ | |
972 | asmlinkage void smp_spurious_interrupt(void) | |
973 | { | |
974 | unsigned int v; | |
95833c83 | 975 | exit_idle(); |
1da177e4 LT |
976 | irq_enter(); |
977 | /* | |
978 | * Check if this really is a spurious interrupt and ACK it | |
979 | * if it is a vectored one. Just in case... | |
980 | * Spurious interrupts should not be ACKed. | |
981 | */ | |
982 | v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); | |
983 | if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) | |
984 | ack_APIC_irq(); | |
985 | ||
986 | #if 0 | |
987 | static unsigned long last_warning; | |
988 | static unsigned long skipped; | |
989 | ||
990 | /* see sw-dev-man vol 3, chapter 7.4.13.5 */ | |
991 | if (time_before(last_warning+30*HZ,jiffies)) { | |
992 | printk(KERN_INFO "spurious APIC interrupt on CPU#%d, %ld skipped.\n", | |
993 | smp_processor_id(), skipped); | |
994 | last_warning = jiffies; | |
995 | skipped = 0; | |
996 | } else { | |
997 | skipped++; | |
998 | } | |
999 | #endif | |
1000 | irq_exit(); | |
1001 | } | |
1002 | ||
1003 | /* | |
1004 | * This interrupt should never happen with our APIC/SMP architecture | |
1005 | */ | |
1006 | ||
1007 | asmlinkage void smp_error_interrupt(void) | |
1008 | { | |
1009 | unsigned int v, v1; | |
1010 | ||
95833c83 | 1011 | exit_idle(); |
1da177e4 LT |
1012 | irq_enter(); |
1013 | /* First tickle the hardware, only then report what went on. -- REW */ | |
1014 | v = apic_read(APIC_ESR); | |
1015 | apic_write(APIC_ESR, 0); | |
1016 | v1 = apic_read(APIC_ESR); | |
1017 | ack_APIC_irq(); | |
1018 | atomic_inc(&irq_err_count); | |
1019 | ||
1020 | /* Here is what the APIC error bits mean: | |
1021 | 0: Send CS error | |
1022 | 1: Receive CS error | |
1023 | 2: Send accept error | |
1024 | 3: Receive accept error | |
1025 | 4: Reserved | |
1026 | 5: Send illegal vector | |
1027 | 6: Received illegal vector | |
1028 | 7: Illegal register address | |
1029 | */ | |
1030 | printk (KERN_DEBUG "APIC error on CPU%d: %02x(%02x)\n", | |
1031 | smp_processor_id(), v , v1); | |
1032 | irq_exit(); | |
1033 | } | |
1034 | ||
1035 | int disable_apic; | |
1036 | ||
1037 | /* | |
1038 | * This initializes the IO-APIC and APIC hardware if this is | |
1039 | * a UP kernel. | |
1040 | */ | |
1041 | int __init APIC_init_uniprocessor (void) | |
1042 | { | |
1043 | if (disable_apic) { | |
1044 | printk(KERN_INFO "Apic disabled\n"); | |
1045 | return -1; | |
1046 | } | |
1047 | if (!cpu_has_apic) { | |
1048 | disable_apic = 1; | |
1049 | printk(KERN_INFO "Apic disabled by BIOS\n"); | |
1050 | return -1; | |
1051 | } | |
1052 | ||
1053 | verify_local_APIC(); | |
1054 | ||
1055 | connect_bsp_APIC(); | |
1056 | ||
357e11d4 | 1057 | phys_cpu_present_map = physid_mask_of_physid(boot_cpu_id); |
11a8e778 | 1058 | apic_write(APIC_ID, SET_APIC_ID(boot_cpu_id)); |
1da177e4 LT |
1059 | |
1060 | setup_local_APIC(); | |
1061 | ||
1062 | #ifdef CONFIG_X86_IO_APIC | |
1063 | if (smp_found_config && !skip_ioapic_setup && nr_ioapics) | |
1064 | setup_IO_APIC(); | |
1065 | else | |
1066 | nr_ioapics = 0; | |
1067 | #endif | |
1068 | setup_boot_APIC_clock(); | |
75152114 | 1069 | check_nmi_watchdog(); |
1da177e4 LT |
1070 | return 0; |
1071 | } | |
1072 | ||
1073 | static __init int setup_disableapic(char *str) | |
1074 | { | |
1075 | disable_apic = 1; | |
1076 | return 0; | |
1077 | } | |
1078 | ||
1079 | static __init int setup_nolapic(char *str) | |
1080 | { | |
1081 | disable_apic = 1; | |
1082 | return 0; | |
1083 | } | |
1084 | ||
1085 | static __init int setup_noapictimer(char *str) | |
1086 | { | |
1087 | disable_apic_timer = 1; | |
1088 | return 0; | |
1089 | } | |
1090 | ||
1091 | /* dummy parsing: see setup.c */ | |
1092 | ||
1093 | __setup("disableapic", setup_disableapic); | |
1094 | __setup("nolapic", setup_nolapic); /* same as disableapic, for compatibility */ | |
1095 | ||
1096 | __setup("noapictimer", setup_noapictimer); | |
1097 | ||
1098 | /* no "lapic" flag - we only use the lapic when the BIOS tells us so. */ |