Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * x86 SMP booting functions | |
3 | * | |
4 | * (c) 1995 Alan Cox, Building #3 <alan@redhat.com> | |
5 | * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
6 | * Copyright 2001 Andi Kleen, SuSE Labs. | |
7 | * | |
8 | * Much of the core SMP work is based on previous work by Thomas Radke, to | |
9 | * whom a great many thanks are extended. | |
10 | * | |
11 | * Thanks to Intel for making available several different Pentium, | |
12 | * Pentium Pro and Pentium-II/Xeon MP machines. | |
13 | * Original development of Linux SMP code supported by Caldera. | |
14 | * | |
a8ab26fe | 15 | * This code is released under the GNU General Public License version 2 |
1da177e4 LT |
16 | * |
17 | * Fixes | |
18 | * Felix Koop : NR_CPUS used properly | |
19 | * Jose Renau : Handle single CPU case. | |
20 | * Alan Cox : By repeated request 8) - Total BogoMIP report. | |
21 | * Greg Wright : Fix for kernel stacks panic. | |
22 | * Erich Boleyn : MP v1.4 and additional changes. | |
23 | * Matthias Sattler : Changes for 2.1 kernel map. | |
24 | * Michel Lespinasse : Changes for 2.1 kernel map. | |
25 | * Michael Chastain : Change trampoline.S to gnu as. | |
26 | * Alan Cox : Dumb bug: 'B' step PPro's are fine | |
27 | * Ingo Molnar : Added APIC timers, based on code | |
28 | * from Jose Renau | |
29 | * Ingo Molnar : various cleanups and rewrites | |
30 | * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. | |
31 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs | |
32 | * Andi Kleen : Changed for SMP boot into long mode. | |
a8ab26fe AK |
33 | * Rusty Russell : Hacked into shape for new "hotplug" boot process. |
34 | * Andi Kleen : Converted to new state machine. | |
35 | * Various cleanups. | |
36 | * Probably mostly hotplug CPU ready now. | |
76e4f660 | 37 | * Ashok Raj : CPU hotplug support |
1da177e4 LT |
38 | */ |
39 | ||
a8ab26fe | 40 | |
1da177e4 LT |
41 | #include <linux/config.h> |
42 | #include <linux/init.h> | |
43 | ||
44 | #include <linux/mm.h> | |
45 | #include <linux/kernel_stat.h> | |
46 | #include <linux/smp_lock.h> | |
47 | #include <linux/irq.h> | |
48 | #include <linux/bootmem.h> | |
49 | #include <linux/thread_info.h> | |
50 | #include <linux/module.h> | |
51 | ||
52 | #include <linux/delay.h> | |
53 | #include <linux/mc146818rtc.h> | |
54 | #include <asm/mtrr.h> | |
55 | #include <asm/pgalloc.h> | |
56 | #include <asm/desc.h> | |
57 | #include <asm/kdebug.h> | |
58 | #include <asm/tlbflush.h> | |
59 | #include <asm/proto.h> | |
75152114 | 60 | #include <asm/nmi.h> |
1da177e4 LT |
61 | |
62 | /* Number of siblings per CPU package */ | |
63 | int smp_num_siblings = 1; | |
64 | /* Package ID of each logical CPU */ | |
6c231b7b RT |
65 | u8 phys_proc_id[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = BAD_APICID }; |
66 | u8 cpu_core_id[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = BAD_APICID }; | |
1da177e4 | 67 | EXPORT_SYMBOL(phys_proc_id); |
3dd9d514 | 68 | EXPORT_SYMBOL(cpu_core_id); |
1da177e4 LT |
69 | |
70 | /* Bitmask of currently online CPUs */ | |
6c231b7b | 71 | cpumask_t cpu_online_map __read_mostly; |
1da177e4 | 72 | |
a8ab26fe AK |
73 | EXPORT_SYMBOL(cpu_online_map); |
74 | ||
75 | /* | |
76 | * Private maps to synchronize booting between AP and BP. | |
77 | * Probably not needed anymore, but it makes for easier debugging. -AK | |
78 | */ | |
1da177e4 LT |
79 | cpumask_t cpu_callin_map; |
80 | cpumask_t cpu_callout_map; | |
a8ab26fe AK |
81 | |
82 | cpumask_t cpu_possible_map; | |
83 | EXPORT_SYMBOL(cpu_possible_map); | |
1da177e4 LT |
84 | |
85 | /* Per CPU bogomips and other parameters */ | |
86 | struct cpuinfo_x86 cpu_data[NR_CPUS] __cacheline_aligned; | |
87 | ||
a8ab26fe AK |
88 | /* Set when the idlers are all forked */ |
89 | int smp_threads_ready; | |
90 | ||
6c231b7b RT |
91 | cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly; |
92 | cpumask_t cpu_core_map[NR_CPUS] __read_mostly; | |
2df9fa36 | 93 | EXPORT_SYMBOL(cpu_core_map); |
1da177e4 LT |
94 | |
95 | /* | |
96 | * Trampoline 80x86 program as an array. | |
97 | */ | |
98 | ||
a8ab26fe AK |
99 | extern unsigned char trampoline_data[]; |
100 | extern unsigned char trampoline_end[]; | |
1da177e4 | 101 | |
76e4f660 AR |
102 | /* State of each CPU */ |
103 | DEFINE_PER_CPU(int, cpu_state) = { 0 }; | |
104 | ||
105 | /* | |
106 | * Store all idle threads, this can be reused instead of creating | |
107 | * a new thread. Also avoids complicated thread destroy functionality | |
108 | * for idle threads. | |
109 | */ | |
110 | struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ; | |
111 | ||
112 | #define get_idle_for_cpu(x) (idle_thread_array[(x)]) | |
113 | #define set_idle_for_cpu(x,p) (idle_thread_array[(x)] = (p)) | |
114 | ||
1da177e4 LT |
115 | /* |
116 | * Currently trivial. Write the real->protected mode | |
117 | * bootstrap into the page concerned. The caller | |
118 | * has made sure it's suitably aligned. | |
119 | */ | |
120 | ||
a8ab26fe | 121 | static unsigned long __cpuinit setup_trampoline(void) |
1da177e4 LT |
122 | { |
123 | void *tramp = __va(SMP_TRAMPOLINE_BASE); | |
124 | memcpy(tramp, trampoline_data, trampoline_end - trampoline_data); | |
125 | return virt_to_phys(tramp); | |
126 | } | |
127 | ||
128 | /* | |
129 | * The bootstrap kernel entry code has set these up. Save them for | |
130 | * a given CPU | |
131 | */ | |
132 | ||
a8ab26fe | 133 | static void __cpuinit smp_store_cpu_info(int id) |
1da177e4 LT |
134 | { |
135 | struct cpuinfo_x86 *c = cpu_data + id; | |
136 | ||
137 | *c = boot_cpu_data; | |
138 | identify_cpu(c); | |
dda50e71 | 139 | print_cpu_info(c); |
1da177e4 LT |
140 | } |
141 | ||
142 | /* | |
dda50e71 AK |
143 | * New Funky TSC sync algorithm borrowed from IA64. |
144 | * Main advantage is that it doesn't reset the TSCs fully and | |
145 | * in general looks more robust and it works better than my earlier | |
146 | * attempts. I believe it was written by David Mosberger. Some minor | |
147 | * adjustments for x86-64 by me -AK | |
1da177e4 | 148 | * |
dda50e71 AK |
149 | * Original comment reproduced below. |
150 | * | |
151 | * Synchronize TSC of the current (slave) CPU with the TSC of the | |
152 | * MASTER CPU (normally the time-keeper CPU). We use a closed loop to | |
153 | * eliminate the possibility of unaccounted-for errors (such as | |
154 | * getting a machine check in the middle of a calibration step). The | |
155 | * basic idea is for the slave to ask the master what itc value it has | |
156 | * and to read its own itc before and after the master responds. Each | |
157 | * iteration gives us three timestamps: | |
158 | * | |
159 | * slave master | |
160 | * | |
161 | * t0 ---\ | |
162 | * ---\ | |
163 | * ---> | |
164 | * tm | |
165 | * /--- | |
166 | * /--- | |
167 | * t1 <--- | |
168 | * | |
169 | * | |
170 | * The goal is to adjust the slave's TSC such that tm falls exactly | |
171 | * half-way between t0 and t1. If we achieve this, the clocks are | |
172 | * synchronized provided the interconnect between the slave and the | |
173 | * master is symmetric. Even if the interconnect were asymmetric, we | |
174 | * would still know that the synchronization error is smaller than the | |
175 | * roundtrip latency (t0 - t1). | |
176 | * | |
177 | * When the interconnect is quiet and symmetric, this lets us | |
178 | * synchronize the TSC to within one or two cycles. However, we can | |
179 | * only *guarantee* that the synchronization is accurate to within a | |
180 | * round-trip time, which is typically in the range of several hundred | |
181 | * cycles (e.g., ~500 cycles). In practice, this means that the TSCs | |
182 | * are usually almost perfectly synchronized, but we shouldn't assume | |
183 | * that the accuracy is much better than half a micro second or so. | |
184 | * | |
185 | * [there are other errors like the latency of RDTSC and of the | |
186 | * WRMSR. These can also account to hundreds of cycles. So it's | |
187 | * probably worse. It claims 153 cycles error on a dual Opteron, | |
188 | * but I suspect the numbers are actually somewhat worse -AK] | |
1da177e4 LT |
189 | */ |
190 | ||
dda50e71 AK |
191 | #define MASTER 0 |
192 | #define SLAVE (SMP_CACHE_BYTES/8) | |
193 | ||
194 | /* Intentionally don't use cpu_relax() while TSC synchronization | |
195 | because we don't want to go into funky power save modi or cause | |
196 | hypervisors to schedule us away. Going to sleep would likely affect | |
197 | latency and low latency is the primary objective here. -AK */ | |
198 | #define no_cpu_relax() barrier() | |
199 | ||
a8ab26fe | 200 | static __cpuinitdata DEFINE_SPINLOCK(tsc_sync_lock); |
dda50e71 AK |
201 | static volatile __cpuinitdata unsigned long go[SLAVE + 1]; |
202 | static int notscsync __cpuinitdata; | |
203 | ||
204 | #undef DEBUG_TSC_SYNC | |
1da177e4 | 205 | |
dda50e71 AK |
206 | #define NUM_ROUNDS 64 /* magic value */ |
207 | #define NUM_ITERS 5 /* likewise */ | |
1da177e4 | 208 | |
dda50e71 AK |
209 | /* Callback on boot CPU */ |
210 | static __cpuinit void sync_master(void *arg) | |
1da177e4 | 211 | { |
dda50e71 AK |
212 | unsigned long flags, i; |
213 | ||
dda50e71 AK |
214 | go[MASTER] = 0; |
215 | ||
216 | local_irq_save(flags); | |
217 | { | |
218 | for (i = 0; i < NUM_ROUNDS*NUM_ITERS; ++i) { | |
219 | while (!go[MASTER]) | |
220 | no_cpu_relax(); | |
221 | go[MASTER] = 0; | |
222 | rdtscll(go[SLAVE]); | |
223 | } | |
224 | } | |
225 | local_irq_restore(flags); | |
a8ab26fe | 226 | } |
1da177e4 | 227 | |
a8ab26fe | 228 | /* |
dda50e71 AK |
229 | * Return the number of cycles by which our tsc differs from the tsc |
230 | * on the master (time-keeper) CPU. A positive number indicates our | |
231 | * tsc is ahead of the master, negative that it is behind. | |
a8ab26fe | 232 | */ |
dda50e71 AK |
233 | static inline long |
234 | get_delta(long *rt, long *master) | |
a8ab26fe | 235 | { |
dda50e71 AK |
236 | unsigned long best_t0 = 0, best_t1 = ~0UL, best_tm = 0; |
237 | unsigned long tcenter, t0, t1, tm; | |
238 | int i; | |
a8ab26fe | 239 | |
dda50e71 AK |
240 | for (i = 0; i < NUM_ITERS; ++i) { |
241 | rdtscll(t0); | |
242 | go[MASTER] = 1; | |
243 | while (!(tm = go[SLAVE])) | |
244 | no_cpu_relax(); | |
245 | go[SLAVE] = 0; | |
246 | rdtscll(t1); | |
247 | ||
248 | if (t1 - t0 < best_t1 - best_t0) | |
249 | best_t0 = t0, best_t1 = t1, best_tm = tm; | |
250 | } | |
251 | ||
252 | *rt = best_t1 - best_t0; | |
253 | *master = best_tm - best_t0; | |
254 | ||
255 | /* average best_t0 and best_t1 without overflow: */ | |
256 | tcenter = (best_t0/2 + best_t1/2); | |
257 | if (best_t0 % 2 + best_t1 % 2 == 2) | |
258 | ++tcenter; | |
259 | return tcenter - best_tm; | |
1da177e4 LT |
260 | } |
261 | ||
3d483f47 | 262 | static __cpuinit void sync_tsc(unsigned int master) |
1da177e4 | 263 | { |
dda50e71 AK |
264 | int i, done = 0; |
265 | long delta, adj, adjust_latency = 0; | |
266 | unsigned long flags, rt, master_time_stamp, bound; | |
44456d37 | 267 | #ifdef DEBUG_TSC_SYNC |
dda50e71 AK |
268 | static struct syncdebug { |
269 | long rt; /* roundtrip time */ | |
270 | long master; /* master's timestamp */ | |
271 | long diff; /* difference between midpoint and master's timestamp */ | |
272 | long lat; /* estimate of tsc adjustment latency */ | |
273 | } t[NUM_ROUNDS] __cpuinitdata; | |
274 | #endif | |
275 | ||
3d483f47 EB |
276 | printk(KERN_INFO "CPU %d: Syncing TSC to CPU %u.\n", |
277 | smp_processor_id(), master); | |
278 | ||
dda50e71 AK |
279 | go[MASTER] = 1; |
280 | ||
3d483f47 EB |
281 | /* It is dangerous to broadcast IPI as cpus are coming up, |
282 | * as they may not be ready to accept them. So since | |
283 | * we only need to send the ipi to the boot cpu direct | |
284 | * the message, and avoid the race. | |
285 | */ | |
286 | smp_call_function_single(master, sync_master, NULL, 1, 0); | |
dda50e71 AK |
287 | |
288 | while (go[MASTER]) /* wait for master to be ready */ | |
289 | no_cpu_relax(); | |
290 | ||
291 | spin_lock_irqsave(&tsc_sync_lock, flags); | |
292 | { | |
293 | for (i = 0; i < NUM_ROUNDS; ++i) { | |
294 | delta = get_delta(&rt, &master_time_stamp); | |
295 | if (delta == 0) { | |
296 | done = 1; /* let's lock on to this... */ | |
297 | bound = rt; | |
298 | } | |
299 | ||
300 | if (!done) { | |
301 | unsigned long t; | |
302 | if (i > 0) { | |
303 | adjust_latency += -delta; | |
304 | adj = -delta + adjust_latency/4; | |
305 | } else | |
306 | adj = -delta; | |
307 | ||
308 | rdtscll(t); | |
309 | wrmsrl(MSR_IA32_TSC, t + adj); | |
310 | } | |
44456d37 | 311 | #ifdef DEBUG_TSC_SYNC |
dda50e71 AK |
312 | t[i].rt = rt; |
313 | t[i].master = master_time_stamp; | |
314 | t[i].diff = delta; | |
315 | t[i].lat = adjust_latency/4; | |
316 | #endif | |
317 | } | |
318 | } | |
319 | spin_unlock_irqrestore(&tsc_sync_lock, flags); | |
320 | ||
44456d37 | 321 | #ifdef DEBUG_TSC_SYNC |
dda50e71 AK |
322 | for (i = 0; i < NUM_ROUNDS; ++i) |
323 | printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n", | |
324 | t[i].rt, t[i].master, t[i].diff, t[i].lat); | |
325 | #endif | |
326 | ||
327 | printk(KERN_INFO | |
328 | "CPU %d: synchronized TSC with CPU %u (last diff %ld cycles, " | |
329 | "maxerr %lu cycles)\n", | |
3d483f47 | 330 | smp_processor_id(), master, delta, rt); |
a8ab26fe | 331 | } |
1da177e4 | 332 | |
dda50e71 | 333 | static void __cpuinit tsc_sync_wait(void) |
a8ab26fe | 334 | { |
dda50e71 | 335 | if (notscsync || !cpu_has_tsc) |
a8ab26fe | 336 | return; |
349188f6 | 337 | sync_tsc(0); |
a8ab26fe | 338 | } |
1da177e4 | 339 | |
dda50e71 | 340 | static __init int notscsync_setup(char *s) |
a8ab26fe | 341 | { |
dda50e71 AK |
342 | notscsync = 1; |
343 | return 0; | |
1da177e4 | 344 | } |
dda50e71 | 345 | __setup("notscsync", notscsync_setup); |
1da177e4 | 346 | |
a8ab26fe | 347 | static atomic_t init_deasserted __cpuinitdata; |
1da177e4 | 348 | |
a8ab26fe AK |
349 | /* |
350 | * Report back to the Boot Processor. | |
351 | * Running on AP. | |
352 | */ | |
353 | void __cpuinit smp_callin(void) | |
1da177e4 LT |
354 | { |
355 | int cpuid, phys_id; | |
356 | unsigned long timeout; | |
357 | ||
358 | /* | |
359 | * If waken up by an INIT in an 82489DX configuration | |
360 | * we may get here before an INIT-deassert IPI reaches | |
361 | * our local APIC. We have to wait for the IPI or we'll | |
362 | * lock up on an APIC access. | |
363 | */ | |
a8ab26fe AK |
364 | while (!atomic_read(&init_deasserted)) |
365 | cpu_relax(); | |
1da177e4 LT |
366 | |
367 | /* | |
368 | * (This works even if the APIC is not enabled.) | |
369 | */ | |
370 | phys_id = GET_APIC_ID(apic_read(APIC_ID)); | |
371 | cpuid = smp_processor_id(); | |
372 | if (cpu_isset(cpuid, cpu_callin_map)) { | |
373 | panic("smp_callin: phys CPU#%d, CPU#%d already present??\n", | |
374 | phys_id, cpuid); | |
375 | } | |
376 | Dprintk("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id); | |
377 | ||
378 | /* | |
379 | * STARTUP IPIs are fragile beasts as they might sometimes | |
380 | * trigger some glue motherboard logic. Complete APIC bus | |
381 | * silence for 1 second, this overestimates the time the | |
382 | * boot CPU is spending to send the up to 2 STARTUP IPIs | |
383 | * by a factor of two. This should be enough. | |
384 | */ | |
385 | ||
386 | /* | |
387 | * Waiting 2s total for startup (udelay is not yet working) | |
388 | */ | |
389 | timeout = jiffies + 2*HZ; | |
390 | while (time_before(jiffies, timeout)) { | |
391 | /* | |
392 | * Has the boot CPU finished it's STARTUP sequence? | |
393 | */ | |
394 | if (cpu_isset(cpuid, cpu_callout_map)) | |
395 | break; | |
a8ab26fe | 396 | cpu_relax(); |
1da177e4 LT |
397 | } |
398 | ||
399 | if (!time_before(jiffies, timeout)) { | |
400 | panic("smp_callin: CPU%d started up but did not get a callout!\n", | |
401 | cpuid); | |
402 | } | |
403 | ||
404 | /* | |
405 | * the boot CPU has finished the init stage and is spinning | |
406 | * on callin_map until we finish. We are free to set up this | |
407 | * CPU, first the APIC. (this is probably redundant on most | |
408 | * boards) | |
409 | */ | |
410 | ||
411 | Dprintk("CALLIN, before setup_local_APIC().\n"); | |
412 | setup_local_APIC(); | |
413 | ||
1da177e4 LT |
414 | /* |
415 | * Get our bogomips. | |
416 | */ | |
417 | calibrate_delay(); | |
418 | Dprintk("Stack at about %p\n",&cpuid); | |
419 | ||
420 | disable_APIC_timer(); | |
421 | ||
422 | /* | |
423 | * Save our processor parameters | |
424 | */ | |
425 | smp_store_cpu_info(cpuid); | |
426 | ||
1da177e4 LT |
427 | /* |
428 | * Allow the master to continue. | |
429 | */ | |
430 | cpu_set(cpuid, cpu_callin_map); | |
1da177e4 LT |
431 | } |
432 | ||
cb0cd8d4 AR |
433 | static inline void set_cpu_sibling_map(int cpu) |
434 | { | |
435 | int i; | |
436 | ||
437 | if (smp_num_siblings > 1) { | |
438 | for_each_cpu(i) { | |
439 | if (cpu_core_id[cpu] == cpu_core_id[i]) { | |
440 | cpu_set(i, cpu_sibling_map[cpu]); | |
441 | cpu_set(cpu, cpu_sibling_map[i]); | |
442 | } | |
443 | } | |
444 | } else { | |
445 | cpu_set(cpu, cpu_sibling_map[cpu]); | |
446 | } | |
447 | ||
448 | if (current_cpu_data.x86_num_cores > 1) { | |
449 | for_each_cpu(i) { | |
450 | if (phys_proc_id[cpu] == phys_proc_id[i]) { | |
451 | cpu_set(i, cpu_core_map[cpu]); | |
452 | cpu_set(cpu, cpu_core_map[i]); | |
453 | } | |
454 | } | |
455 | } else { | |
456 | cpu_core_map[cpu] = cpu_sibling_map[cpu]; | |
457 | } | |
458 | } | |
459 | ||
1da177e4 | 460 | /* |
a8ab26fe | 461 | * Setup code on secondary processor (after comming out of the trampoline) |
1da177e4 | 462 | */ |
a8ab26fe | 463 | void __cpuinit start_secondary(void) |
1da177e4 LT |
464 | { |
465 | /* | |
466 | * Dont put anything before smp_callin(), SMP | |
467 | * booting is too fragile that we want to limit the | |
468 | * things done here to the most necessary things. | |
469 | */ | |
470 | cpu_init(); | |
471 | smp_callin(); | |
472 | ||
473 | /* otherwise gcc will move up the smp_processor_id before the cpu_init */ | |
474 | barrier(); | |
475 | ||
1da177e4 LT |
476 | Dprintk("cpu %d: setting up apic clock\n", smp_processor_id()); |
477 | setup_secondary_APIC_clock(); | |
478 | ||
a8ab26fe | 479 | Dprintk("cpu %d: enabling apic timer\n", smp_processor_id()); |
1da177e4 LT |
480 | |
481 | if (nmi_watchdog == NMI_IO_APIC) { | |
482 | disable_8259A_irq(0); | |
483 | enable_NMI_through_LVT0(NULL); | |
484 | enable_8259A_irq(0); | |
485 | } | |
486 | ||
a8ab26fe | 487 | enable_APIC_timer(); |
1da177e4 | 488 | |
cb0cd8d4 AR |
489 | /* |
490 | * The sibling maps must be set before turing the online map on for | |
491 | * this cpu | |
492 | */ | |
493 | set_cpu_sibling_map(smp_processor_id()); | |
494 | ||
1eecd73c AK |
495 | /* |
496 | * Wait for TSC sync to not schedule things before. | |
497 | * We still process interrupts, which could see an inconsistent | |
498 | * time in that window unfortunately. | |
499 | * Do this here because TSC sync has global unprotected state. | |
500 | */ | |
501 | tsc_sync_wait(); | |
502 | ||
884d9e40 AR |
503 | /* |
504 | * We need to hold call_lock, so there is no inconsistency | |
505 | * between the time smp_call_function() determines number of | |
506 | * IPI receipients, and the time when the determination is made | |
507 | * for which cpus receive the IPI in genapic_flat.c. Holding this | |
508 | * lock helps us to not include this cpu in a currently in progress | |
509 | * smp_call_function(). | |
510 | */ | |
511 | lock_ipi_call_lock(); | |
512 | ||
1da177e4 | 513 | /* |
a8ab26fe | 514 | * Allow the master to continue. |
1da177e4 | 515 | */ |
1da177e4 | 516 | cpu_set(smp_processor_id(), cpu_online_map); |
884d9e40 AR |
517 | per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; |
518 | unlock_ipi_call_lock(); | |
519 | ||
1da177e4 LT |
520 | cpu_idle(); |
521 | } | |
522 | ||
a8ab26fe | 523 | extern volatile unsigned long init_rsp; |
1da177e4 LT |
524 | extern void (*initial_code)(void); |
525 | ||
44456d37 | 526 | #ifdef APIC_DEBUG |
a8ab26fe | 527 | static void inquire_remote_apic(int apicid) |
1da177e4 LT |
528 | { |
529 | unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; | |
530 | char *names[] = { "ID", "VERSION", "SPIV" }; | |
531 | int timeout, status; | |
532 | ||
533 | printk(KERN_INFO "Inquiring remote APIC #%d...\n", apicid); | |
534 | ||
535 | for (i = 0; i < sizeof(regs) / sizeof(*regs); i++) { | |
536 | printk("... APIC #%d %s: ", apicid, names[i]); | |
537 | ||
538 | /* | |
539 | * Wait for idle. | |
540 | */ | |
541 | apic_wait_icr_idle(); | |
542 | ||
543 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(apicid)); | |
544 | apic_write_around(APIC_ICR, APIC_DM_REMRD | regs[i]); | |
545 | ||
546 | timeout = 0; | |
547 | do { | |
548 | udelay(100); | |
549 | status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; | |
550 | } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); | |
551 | ||
552 | switch (status) { | |
553 | case APIC_ICR_RR_VALID: | |
554 | status = apic_read(APIC_RRR); | |
555 | printk("%08x\n", status); | |
556 | break; | |
557 | default: | |
558 | printk("failed\n"); | |
559 | } | |
560 | } | |
561 | } | |
562 | #endif | |
563 | ||
a8ab26fe AK |
564 | /* |
565 | * Kick the secondary to wake up. | |
566 | */ | |
567 | static int __cpuinit wakeup_secondary_via_INIT(int phys_apicid, unsigned int start_rip) | |
1da177e4 LT |
568 | { |
569 | unsigned long send_status = 0, accept_status = 0; | |
570 | int maxlvt, timeout, num_starts, j; | |
571 | ||
572 | Dprintk("Asserting INIT.\n"); | |
573 | ||
574 | /* | |
575 | * Turn INIT on target chip | |
576 | */ | |
577 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); | |
578 | ||
579 | /* | |
580 | * Send IPI | |
581 | */ | |
582 | apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT | |
583 | | APIC_DM_INIT); | |
584 | ||
585 | Dprintk("Waiting for send to finish...\n"); | |
586 | timeout = 0; | |
587 | do { | |
588 | Dprintk("+"); | |
589 | udelay(100); | |
590 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
591 | } while (send_status && (timeout++ < 1000)); | |
592 | ||
593 | mdelay(10); | |
594 | ||
595 | Dprintk("Deasserting INIT.\n"); | |
596 | ||
597 | /* Target chip */ | |
598 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); | |
599 | ||
600 | /* Send IPI */ | |
601 | apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT); | |
602 | ||
603 | Dprintk("Waiting for send to finish...\n"); | |
604 | timeout = 0; | |
605 | do { | |
606 | Dprintk("+"); | |
607 | udelay(100); | |
608 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
609 | } while (send_status && (timeout++ < 1000)); | |
610 | ||
611 | atomic_set(&init_deasserted, 1); | |
612 | ||
613 | /* | |
614 | * Should we send STARTUP IPIs ? | |
615 | * | |
616 | * Determine this based on the APIC version. | |
617 | * If we don't have an integrated APIC, don't send the STARTUP IPIs. | |
618 | */ | |
619 | if (APIC_INTEGRATED(apic_version[phys_apicid])) | |
620 | num_starts = 2; | |
621 | else | |
622 | num_starts = 0; | |
623 | ||
624 | /* | |
625 | * Run STARTUP IPI loop. | |
626 | */ | |
627 | Dprintk("#startup loops: %d.\n", num_starts); | |
628 | ||
629 | maxlvt = get_maxlvt(); | |
630 | ||
631 | for (j = 1; j <= num_starts; j++) { | |
632 | Dprintk("Sending STARTUP #%d.\n",j); | |
633 | apic_read_around(APIC_SPIV); | |
634 | apic_write(APIC_ESR, 0); | |
635 | apic_read(APIC_ESR); | |
636 | Dprintk("After apic_write.\n"); | |
637 | ||
638 | /* | |
639 | * STARTUP IPI | |
640 | */ | |
641 | ||
642 | /* Target chip */ | |
643 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); | |
644 | ||
645 | /* Boot on the stack */ | |
646 | /* Kick the second */ | |
647 | apic_write_around(APIC_ICR, APIC_DM_STARTUP | |
648 | | (start_rip >> 12)); | |
649 | ||
650 | /* | |
651 | * Give the other CPU some time to accept the IPI. | |
652 | */ | |
653 | udelay(300); | |
654 | ||
655 | Dprintk("Startup point 1.\n"); | |
656 | ||
657 | Dprintk("Waiting for send to finish...\n"); | |
658 | timeout = 0; | |
659 | do { | |
660 | Dprintk("+"); | |
661 | udelay(100); | |
662 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
663 | } while (send_status && (timeout++ < 1000)); | |
664 | ||
665 | /* | |
666 | * Give the other CPU some time to accept the IPI. | |
667 | */ | |
668 | udelay(200); | |
669 | /* | |
670 | * Due to the Pentium erratum 3AP. | |
671 | */ | |
672 | if (maxlvt > 3) { | |
673 | apic_read_around(APIC_SPIV); | |
674 | apic_write(APIC_ESR, 0); | |
675 | } | |
676 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
677 | if (send_status || accept_status) | |
678 | break; | |
679 | } | |
680 | Dprintk("After Startup.\n"); | |
681 | ||
682 | if (send_status) | |
683 | printk(KERN_ERR "APIC never delivered???\n"); | |
684 | if (accept_status) | |
685 | printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); | |
686 | ||
687 | return (send_status | accept_status); | |
688 | } | |
689 | ||
76e4f660 AR |
690 | struct create_idle { |
691 | struct task_struct *idle; | |
692 | struct completion done; | |
693 | int cpu; | |
694 | }; | |
695 | ||
696 | void do_fork_idle(void *_c_idle) | |
697 | { | |
698 | struct create_idle *c_idle = _c_idle; | |
699 | ||
700 | c_idle->idle = fork_idle(c_idle->cpu); | |
701 | complete(&c_idle->done); | |
702 | } | |
703 | ||
a8ab26fe AK |
704 | /* |
705 | * Boot one CPU. | |
706 | */ | |
707 | static int __cpuinit do_boot_cpu(int cpu, int apicid) | |
1da177e4 | 708 | { |
1da177e4 | 709 | unsigned long boot_error; |
a8ab26fe | 710 | int timeout; |
1da177e4 | 711 | unsigned long start_rip; |
76e4f660 AR |
712 | struct create_idle c_idle = { |
713 | .cpu = cpu, | |
714 | .done = COMPLETION_INITIALIZER(c_idle.done), | |
715 | }; | |
716 | DECLARE_WORK(work, do_fork_idle, &c_idle); | |
717 | ||
718 | c_idle.idle = get_idle_for_cpu(cpu); | |
719 | ||
720 | if (c_idle.idle) { | |
721 | c_idle.idle->thread.rsp = (unsigned long) (((struct pt_regs *) | |
722 | (THREAD_SIZE + (unsigned long) c_idle.idle->thread_info)) - 1); | |
723 | init_idle(c_idle.idle, cpu); | |
724 | goto do_rest; | |
725 | } | |
726 | ||
1da177e4 | 727 | /* |
76e4f660 AR |
728 | * During cold boot process, keventd thread is not spun up yet. |
729 | * When we do cpu hot-add, we create idle threads on the fly, we should | |
730 | * not acquire any attributes from the calling context. Hence the clean | |
731 | * way to create kernel_threads() is to do that from keventd(). | |
732 | * We do the current_is_keventd() due to the fact that ACPI notifier | |
733 | * was also queuing to keventd() and when the caller is already running | |
734 | * in context of keventd(), we would end up with locking up the keventd | |
735 | * thread. | |
1da177e4 | 736 | */ |
76e4f660 AR |
737 | if (!keventd_up() || current_is_keventd()) |
738 | work.func(work.data); | |
739 | else { | |
740 | schedule_work(&work); | |
741 | wait_for_completion(&c_idle.done); | |
742 | } | |
743 | ||
744 | if (IS_ERR(c_idle.idle)) { | |
a8ab26fe | 745 | printk("failed fork for CPU %d\n", cpu); |
76e4f660 | 746 | return PTR_ERR(c_idle.idle); |
a8ab26fe | 747 | } |
1da177e4 | 748 | |
76e4f660 AR |
749 | set_idle_for_cpu(cpu, c_idle.idle); |
750 | ||
751 | do_rest: | |
752 | ||
753 | cpu_pda[cpu].pcurrent = c_idle.idle; | |
1da177e4 LT |
754 | |
755 | start_rip = setup_trampoline(); | |
756 | ||
76e4f660 | 757 | init_rsp = c_idle.idle->thread.rsp; |
1da177e4 LT |
758 | per_cpu(init_tss,cpu).rsp0 = init_rsp; |
759 | initial_code = start_secondary; | |
76e4f660 | 760 | clear_ti_thread_flag(c_idle.idle->thread_info, TIF_FORK); |
1da177e4 | 761 | |
de04f322 AK |
762 | printk(KERN_INFO "Booting processor %d/%d APIC 0x%x\n", cpu, |
763 | cpus_weight(cpu_present_map), | |
764 | apicid); | |
1da177e4 LT |
765 | |
766 | /* | |
767 | * This grunge runs the startup process for | |
768 | * the targeted processor. | |
769 | */ | |
770 | ||
771 | atomic_set(&init_deasserted, 0); | |
772 | ||
773 | Dprintk("Setting warm reset code and vector.\n"); | |
774 | ||
775 | CMOS_WRITE(0xa, 0xf); | |
776 | local_flush_tlb(); | |
777 | Dprintk("1.\n"); | |
778 | *((volatile unsigned short *) phys_to_virt(0x469)) = start_rip >> 4; | |
779 | Dprintk("2.\n"); | |
780 | *((volatile unsigned short *) phys_to_virt(0x467)) = start_rip & 0xf; | |
781 | Dprintk("3.\n"); | |
782 | ||
783 | /* | |
784 | * Be paranoid about clearing APIC errors. | |
785 | */ | |
786 | if (APIC_INTEGRATED(apic_version[apicid])) { | |
787 | apic_read_around(APIC_SPIV); | |
788 | apic_write(APIC_ESR, 0); | |
789 | apic_read(APIC_ESR); | |
790 | } | |
791 | ||
792 | /* | |
793 | * Status is now clean | |
794 | */ | |
795 | boot_error = 0; | |
796 | ||
797 | /* | |
798 | * Starting actual IPI sequence... | |
799 | */ | |
a8ab26fe | 800 | boot_error = wakeup_secondary_via_INIT(apicid, start_rip); |
1da177e4 LT |
801 | |
802 | if (!boot_error) { | |
803 | /* | |
804 | * allow APs to start initializing. | |
805 | */ | |
806 | Dprintk("Before Callout %d.\n", cpu); | |
807 | cpu_set(cpu, cpu_callout_map); | |
808 | Dprintk("After Callout %d.\n", cpu); | |
809 | ||
810 | /* | |
811 | * Wait 5s total for a response | |
812 | */ | |
813 | for (timeout = 0; timeout < 50000; timeout++) { | |
814 | if (cpu_isset(cpu, cpu_callin_map)) | |
815 | break; /* It has booted */ | |
816 | udelay(100); | |
817 | } | |
818 | ||
819 | if (cpu_isset(cpu, cpu_callin_map)) { | |
820 | /* number CPUs logically, starting from 1 (BSP is 0) */ | |
1da177e4 LT |
821 | Dprintk("CPU has booted.\n"); |
822 | } else { | |
823 | boot_error = 1; | |
824 | if (*((volatile unsigned char *)phys_to_virt(SMP_TRAMPOLINE_BASE)) | |
825 | == 0xA5) | |
826 | /* trampoline started but...? */ | |
827 | printk("Stuck ??\n"); | |
828 | else | |
829 | /* trampoline code not run */ | |
830 | printk("Not responding.\n"); | |
44456d37 | 831 | #ifdef APIC_DEBUG |
1da177e4 LT |
832 | inquire_remote_apic(apicid); |
833 | #endif | |
834 | } | |
835 | } | |
836 | if (boot_error) { | |
837 | cpu_clear(cpu, cpu_callout_map); /* was set here (do_boot_cpu()) */ | |
838 | clear_bit(cpu, &cpu_initialized); /* was set by cpu_init() */ | |
a8ab26fe AK |
839 | cpu_clear(cpu, cpu_present_map); |
840 | cpu_clear(cpu, cpu_possible_map); | |
1da177e4 LT |
841 | x86_cpu_to_apicid[cpu] = BAD_APICID; |
842 | x86_cpu_to_log_apicid[cpu] = BAD_APICID; | |
a8ab26fe | 843 | return -EIO; |
1da177e4 | 844 | } |
a8ab26fe AK |
845 | |
846 | return 0; | |
1da177e4 LT |
847 | } |
848 | ||
a8ab26fe AK |
849 | cycles_t cacheflush_time; |
850 | unsigned long cache_decay_ticks; | |
851 | ||
1da177e4 | 852 | /* |
a8ab26fe | 853 | * Cleanup possible dangling ends... |
1da177e4 | 854 | */ |
a8ab26fe | 855 | static __cpuinit void smp_cleanup_boot(void) |
1da177e4 | 856 | { |
a8ab26fe AK |
857 | /* |
858 | * Paranoid: Set warm reset code and vector here back | |
859 | * to default values. | |
860 | */ | |
861 | CMOS_WRITE(0, 0xf); | |
1da177e4 | 862 | |
a8ab26fe AK |
863 | /* |
864 | * Reset trampoline flag | |
865 | */ | |
866 | *((volatile int *) phys_to_virt(0x467)) = 0; | |
1da177e4 | 867 | |
a8ab26fe | 868 | #ifndef CONFIG_HOTPLUG_CPU |
1da177e4 | 869 | /* |
a8ab26fe AK |
870 | * Free pages reserved for SMP bootup. |
871 | * When you add hotplug CPU support later remove this | |
872 | * Note there is more work to be done for later CPU bootup. | |
1da177e4 | 873 | */ |
1da177e4 | 874 | |
a8ab26fe AK |
875 | free_page((unsigned long) __va(PAGE_SIZE)); |
876 | free_page((unsigned long) __va(SMP_TRAMPOLINE_BASE)); | |
877 | #endif | |
878 | } | |
879 | ||
880 | /* | |
881 | * Fall back to non SMP mode after errors. | |
882 | * | |
883 | * RED-PEN audit/test this more. I bet there is more state messed up here. | |
884 | */ | |
e6982c67 | 885 | static __init void disable_smp(void) |
a8ab26fe AK |
886 | { |
887 | cpu_present_map = cpumask_of_cpu(0); | |
888 | cpu_possible_map = cpumask_of_cpu(0); | |
889 | if (smp_found_config) | |
890 | phys_cpu_present_map = physid_mask_of_physid(boot_cpu_id); | |
891 | else | |
892 | phys_cpu_present_map = physid_mask_of_physid(0); | |
893 | cpu_set(0, cpu_sibling_map[0]); | |
894 | cpu_set(0, cpu_core_map[0]); | |
895 | } | |
896 | ||
897 | /* | |
898 | * Handle user cpus=... parameter. | |
899 | */ | |
e6982c67 | 900 | static __init void enforce_max_cpus(unsigned max_cpus) |
a8ab26fe AK |
901 | { |
902 | int i, k; | |
903 | k = 0; | |
904 | for (i = 0; i < NR_CPUS; i++) { | |
905 | if (!cpu_possible(i)) | |
906 | continue; | |
907 | if (++k > max_cpus) { | |
908 | cpu_clear(i, cpu_possible_map); | |
909 | cpu_clear(i, cpu_present_map); | |
910 | } | |
911 | } | |
912 | } | |
1da177e4 | 913 | |
61b1b2d0 AK |
914 | #ifdef CONFIG_HOTPLUG_CPU |
915 | /* | |
916 | * cpu_possible_map should be static, it cannot change as cpu's | |
917 | * are onlined, or offlined. The reason is per-cpu data-structures | |
918 | * are allocated by some modules at init time, and dont expect to | |
919 | * do this dynamically on cpu arrival/departure. | |
920 | * cpu_present_map on the other hand can change dynamically. | |
921 | * In case when cpu_hotplug is not compiled, then we resort to current | |
922 | * behaviour, which is cpu_possible == cpu_present. | |
923 | * If cpu-hotplug is supported, then we need to preallocate for all | |
924 | * those NR_CPUS, hence cpu_possible_map represents entire NR_CPUS range. | |
925 | * - Ashok Raj | |
926 | */ | |
927 | static void prefill_possible_map(void) | |
928 | { | |
929 | int i; | |
930 | for (i = 0; i < NR_CPUS; i++) | |
931 | cpu_set(i, cpu_possible_map); | |
932 | } | |
933 | #endif | |
934 | ||
a8ab26fe AK |
935 | /* |
936 | * Various sanity checks. | |
937 | */ | |
e6982c67 | 938 | static int __init smp_sanity_check(unsigned max_cpus) |
a8ab26fe | 939 | { |
1da177e4 LT |
940 | if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { |
941 | printk("weird, boot CPU (#%d) not listed by the BIOS.\n", | |
942 | hard_smp_processor_id()); | |
943 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); | |
944 | } | |
945 | ||
946 | /* | |
947 | * If we couldn't find an SMP configuration at boot time, | |
948 | * get out of here now! | |
949 | */ | |
950 | if (!smp_found_config) { | |
951 | printk(KERN_NOTICE "SMP motherboard not detected.\n"); | |
a8ab26fe | 952 | disable_smp(); |
1da177e4 LT |
953 | if (APIC_init_uniprocessor()) |
954 | printk(KERN_NOTICE "Local APIC not detected." | |
955 | " Using dummy APIC emulation.\n"); | |
a8ab26fe | 956 | return -1; |
1da177e4 LT |
957 | } |
958 | ||
959 | /* | |
960 | * Should not be necessary because the MP table should list the boot | |
961 | * CPU too, but we do it for the sake of robustness anyway. | |
962 | */ | |
963 | if (!physid_isset(boot_cpu_id, phys_cpu_present_map)) { | |
964 | printk(KERN_NOTICE "weird, boot CPU (#%d) not listed by the BIOS.\n", | |
965 | boot_cpu_id); | |
966 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); | |
967 | } | |
968 | ||
969 | /* | |
970 | * If we couldn't find a local APIC, then get out of here now! | |
971 | */ | |
972 | if (APIC_INTEGRATED(apic_version[boot_cpu_id]) && !cpu_has_apic) { | |
973 | printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n", | |
974 | boot_cpu_id); | |
975 | printk(KERN_ERR "... forcing use of dummy APIC emulation. (tell your hw vendor)\n"); | |
a8ab26fe AK |
976 | nr_ioapics = 0; |
977 | return -1; | |
1da177e4 LT |
978 | } |
979 | ||
1da177e4 LT |
980 | /* |
981 | * If SMP should be disabled, then really disable it! | |
982 | */ | |
983 | if (!max_cpus) { | |
1da177e4 | 984 | printk(KERN_INFO "SMP mode deactivated, forcing use of dummy APIC emulation.\n"); |
a8ab26fe AK |
985 | nr_ioapics = 0; |
986 | return -1; | |
1da177e4 LT |
987 | } |
988 | ||
a8ab26fe AK |
989 | return 0; |
990 | } | |
1da177e4 | 991 | |
a8ab26fe AK |
992 | /* |
993 | * Prepare for SMP bootup. The MP table or ACPI has been read | |
994 | * earlier. Just do some sanity checking here and enable APIC mode. | |
995 | */ | |
e6982c67 | 996 | void __init smp_prepare_cpus(unsigned int max_cpus) |
a8ab26fe | 997 | { |
a8ab26fe AK |
998 | nmi_watchdog_default(); |
999 | current_cpu_data = boot_cpu_data; | |
1000 | current_thread_info()->cpu = 0; /* needed? */ | |
1da177e4 | 1001 | |
a8ab26fe | 1002 | enforce_max_cpus(max_cpus); |
1da177e4 | 1003 | |
61b1b2d0 AK |
1004 | #ifdef CONFIG_HOTPLUG_CPU |
1005 | prefill_possible_map(); | |
1006 | #endif | |
1da177e4 | 1007 | |
a8ab26fe AK |
1008 | if (smp_sanity_check(max_cpus) < 0) { |
1009 | printk(KERN_INFO "SMP disabled\n"); | |
1010 | disable_smp(); | |
1011 | return; | |
1da177e4 LT |
1012 | } |
1013 | ||
a8ab26fe | 1014 | |
1da177e4 | 1015 | /* |
a8ab26fe | 1016 | * Switch from PIC to APIC mode. |
1da177e4 | 1017 | */ |
a8ab26fe AK |
1018 | connect_bsp_APIC(); |
1019 | setup_local_APIC(); | |
1da177e4 | 1020 | |
a8ab26fe AK |
1021 | if (GET_APIC_ID(apic_read(APIC_ID)) != boot_cpu_id) { |
1022 | panic("Boot APIC ID in local APIC unexpected (%d vs %d)", | |
1023 | GET_APIC_ID(apic_read(APIC_ID)), boot_cpu_id); | |
1024 | /* Or can we switch back to PIC here? */ | |
1da177e4 | 1025 | } |
1da177e4 LT |
1026 | |
1027 | /* | |
a8ab26fe | 1028 | * Now start the IO-APICs |
1da177e4 LT |
1029 | */ |
1030 | if (!skip_ioapic_setup && nr_ioapics) | |
1031 | setup_IO_APIC(); | |
1032 | else | |
1033 | nr_ioapics = 0; | |
1034 | ||
1da177e4 | 1035 | /* |
a8ab26fe | 1036 | * Set up local APIC timer on boot CPU. |
1da177e4 | 1037 | */ |
1da177e4 | 1038 | |
a8ab26fe | 1039 | setup_boot_APIC_clock(); |
1da177e4 LT |
1040 | } |
1041 | ||
a8ab26fe AK |
1042 | /* |
1043 | * Early setup to make printk work. | |
1044 | */ | |
1045 | void __init smp_prepare_boot_cpu(void) | |
1da177e4 | 1046 | { |
a8ab26fe AK |
1047 | int me = smp_processor_id(); |
1048 | cpu_set(me, cpu_online_map); | |
1049 | cpu_set(me, cpu_callout_map); | |
cb0cd8d4 AR |
1050 | cpu_set(0, cpu_sibling_map[0]); |
1051 | cpu_set(0, cpu_core_map[0]); | |
884d9e40 | 1052 | per_cpu(cpu_state, me) = CPU_ONLINE; |
1da177e4 LT |
1053 | } |
1054 | ||
a8ab26fe AK |
1055 | /* |
1056 | * Entry point to boot a CPU. | |
a8ab26fe AK |
1057 | */ |
1058 | int __cpuinit __cpu_up(unsigned int cpu) | |
1da177e4 | 1059 | { |
a8ab26fe AK |
1060 | int err; |
1061 | int apicid = cpu_present_to_apicid(cpu); | |
1da177e4 | 1062 | |
a8ab26fe | 1063 | WARN_ON(irqs_disabled()); |
1da177e4 | 1064 | |
a8ab26fe AK |
1065 | Dprintk("++++++++++++++++++++=_---CPU UP %u\n", cpu); |
1066 | ||
1067 | if (apicid == BAD_APICID || apicid == boot_cpu_id || | |
1068 | !physid_isset(apicid, phys_cpu_present_map)) { | |
1069 | printk("__cpu_up: bad cpu %d\n", cpu); | |
1070 | return -EINVAL; | |
1071 | } | |
a8ab26fe | 1072 | |
76e4f660 AR |
1073 | /* |
1074 | * Already booted CPU? | |
1075 | */ | |
1076 | if (cpu_isset(cpu, cpu_callin_map)) { | |
1077 | Dprintk("do_boot_cpu %d Already started\n", cpu); | |
1078 | return -ENOSYS; | |
1079 | } | |
1080 | ||
884d9e40 | 1081 | per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; |
a8ab26fe AK |
1082 | /* Boot it! */ |
1083 | err = do_boot_cpu(cpu, apicid); | |
1084 | if (err < 0) { | |
a8ab26fe AK |
1085 | Dprintk("do_boot_cpu failed %d\n", err); |
1086 | return err; | |
1da177e4 | 1087 | } |
a8ab26fe | 1088 | |
1da177e4 LT |
1089 | /* Unleash the CPU! */ |
1090 | Dprintk("waiting for cpu %d\n", cpu); | |
1091 | ||
1da177e4 | 1092 | while (!cpu_isset(cpu, cpu_online_map)) |
a8ab26fe | 1093 | cpu_relax(); |
76e4f660 AR |
1094 | err = 0; |
1095 | ||
1096 | return err; | |
1da177e4 LT |
1097 | } |
1098 | ||
a8ab26fe AK |
1099 | /* |
1100 | * Finish the SMP boot. | |
1101 | */ | |
e6982c67 | 1102 | void __init smp_cpus_done(unsigned int max_cpus) |
1da177e4 | 1103 | { |
76e4f660 | 1104 | #ifndef CONFIG_HOTPLUG_CPU |
a8ab26fe | 1105 | zap_low_mappings(); |
76e4f660 | 1106 | #endif |
a8ab26fe AK |
1107 | smp_cleanup_boot(); |
1108 | ||
1da177e4 LT |
1109 | #ifdef CONFIG_X86_IO_APIC |
1110 | setup_ioapic_dest(); | |
1111 | #endif | |
1da177e4 | 1112 | |
a8ab26fe | 1113 | time_init_gtod(); |
75152114 AK |
1114 | |
1115 | check_nmi_watchdog(); | |
a8ab26fe | 1116 | } |
76e4f660 AR |
1117 | |
1118 | #ifdef CONFIG_HOTPLUG_CPU | |
1119 | ||
cb0cd8d4 | 1120 | static void remove_siblinginfo(int cpu) |
76e4f660 AR |
1121 | { |
1122 | int sibling; | |
1123 | ||
1124 | for_each_cpu_mask(sibling, cpu_sibling_map[cpu]) | |
1125 | cpu_clear(cpu, cpu_sibling_map[sibling]); | |
1126 | for_each_cpu_mask(sibling, cpu_core_map[cpu]) | |
1127 | cpu_clear(cpu, cpu_core_map[sibling]); | |
1128 | cpus_clear(cpu_sibling_map[cpu]); | |
1129 | cpus_clear(cpu_core_map[cpu]); | |
1130 | phys_proc_id[cpu] = BAD_APICID; | |
1131 | cpu_core_id[cpu] = BAD_APICID; | |
1132 | } | |
1133 | ||
1134 | void remove_cpu_from_maps(void) | |
1135 | { | |
1136 | int cpu = smp_processor_id(); | |
1137 | ||
1138 | cpu_clear(cpu, cpu_callout_map); | |
1139 | cpu_clear(cpu, cpu_callin_map); | |
1140 | clear_bit(cpu, &cpu_initialized); /* was set by cpu_init() */ | |
1141 | } | |
1142 | ||
1143 | int __cpu_disable(void) | |
1144 | { | |
1145 | int cpu = smp_processor_id(); | |
1146 | ||
1147 | /* | |
1148 | * Perhaps use cpufreq to drop frequency, but that could go | |
1149 | * into generic code. | |
1150 | * | |
1151 | * We won't take down the boot processor on i386 due to some | |
1152 | * interrupts only being able to be serviced by the BSP. | |
1153 | * Especially so if we're not using an IOAPIC -zwane | |
1154 | */ | |
1155 | if (cpu == 0) | |
1156 | return -EBUSY; | |
1157 | ||
1158 | disable_APIC_timer(); | |
1159 | ||
1160 | /* | |
1161 | * HACK: | |
1162 | * Allow any queued timer interrupts to get serviced | |
1163 | * This is only a temporary solution until we cleanup | |
1164 | * fixup_irqs as we do for IA64. | |
1165 | */ | |
1166 | local_irq_enable(); | |
1167 | mdelay(1); | |
1168 | ||
1169 | local_irq_disable(); | |
1170 | remove_siblinginfo(cpu); | |
1171 | ||
1172 | /* It's now safe to remove this processor from the online map */ | |
1173 | cpu_clear(cpu, cpu_online_map); | |
1174 | remove_cpu_from_maps(); | |
1175 | fixup_irqs(cpu_online_map); | |
1176 | return 0; | |
1177 | } | |
1178 | ||
1179 | void __cpu_die(unsigned int cpu) | |
1180 | { | |
1181 | /* We don't do anything here: idle task is faking death itself. */ | |
1182 | unsigned int i; | |
1183 | ||
1184 | for (i = 0; i < 10; i++) { | |
1185 | /* They ack this in play_dead by setting CPU_DEAD */ | |
884d9e40 AR |
1186 | if (per_cpu(cpu_state, cpu) == CPU_DEAD) { |
1187 | printk ("CPU %d is now offline\n", cpu); | |
76e4f660 | 1188 | return; |
884d9e40 | 1189 | } |
ef6e5253 | 1190 | msleep(100); |
76e4f660 AR |
1191 | } |
1192 | printk(KERN_ERR "CPU %u didn't die...\n", cpu); | |
1193 | } | |
1194 | ||
1195 | #else /* ... !CONFIG_HOTPLUG_CPU */ | |
1196 | ||
1197 | int __cpu_disable(void) | |
1198 | { | |
1199 | return -ENOSYS; | |
1200 | } | |
1201 | ||
1202 | void __cpu_die(unsigned int cpu) | |
1203 | { | |
1204 | /* We said "no" in __cpu_disable */ | |
1205 | BUG(); | |
1206 | } | |
1207 | #endif /* CONFIG_HOTPLUG_CPU */ |