Commit | Line | Data |
---|---|---|
173d6681 CZ |
1 | /* |
2 | * include/asm-xtensa/cacheasm.h | |
3 | * | |
4 | * This file is subject to the terms and conditions of the GNU General Public | |
5 | * License. See the file "COPYING" in the main directory of this archive | |
6 | * for more details. | |
7 | * | |
8 | * Copyright (C) 2006 Tensilica Inc. | |
9 | */ | |
10 | ||
11 | #include <asm/cache.h> | |
12 | #include <asm/asmmacro.h> | |
13 | #include <linux/stringify.h> | |
14 | ||
15 | /* | |
16 | * Define cache functions as macros here so that they can be used | |
17 | * by the kernel and boot loader. We should consider moving them to a | |
18 | * library that can be linked by both. | |
19 | * | |
20 | * Locking | |
21 | * | |
22 | * ___unlock_dcache_all | |
23 | * ___unlock_icache_all | |
24 | * | |
25 | * Flush and invaldating | |
26 | * | |
27 | * ___flush_invalidate_dcache_{all|range|page} | |
28 | * ___flush_dcache_{all|range|page} | |
29 | * ___invalidate_dcache_{all|range|page} | |
30 | * ___invalidate_icache_{all|range|page} | |
31 | * | |
32 | */ | |
33 | ||
34 | .macro __loop_cache_all ar at insn size line_width | |
35 | ||
36 | movi \ar, 0 | |
37 | ||
38 | __loopi \ar, \at, \size, (4 << (\line_width)) | |
39 | \insn \ar, 0 << (\line_width) | |
40 | \insn \ar, 1 << (\line_width) | |
41 | \insn \ar, 2 << (\line_width) | |
42 | \insn \ar, 3 << (\line_width) | |
43 | __endla \ar, \at, 4 << (\line_width) | |
44 | ||
45 | .endm | |
46 | ||
47 | ||
48 | .macro __loop_cache_range ar as at insn line_width | |
49 | ||
50 | extui \at, \ar, 0, \line_width | |
51 | add \as, \as, \at | |
52 | ||
53 | __loops \ar, \as, \at, \line_width | |
54 | \insn \ar, 0 | |
55 | __endla \ar, \at, (1 << (\line_width)) | |
56 | ||
57 | .endm | |
58 | ||
59 | ||
60 | .macro __loop_cache_page ar at insn line_width | |
61 | ||
62 | __loopi \ar, \at, PAGE_SIZE, 4 << (\line_width) | |
63 | \insn \ar, 0 << (\line_width) | |
64 | \insn \ar, 1 << (\line_width) | |
65 | \insn \ar, 2 << (\line_width) | |
66 | \insn \ar, 3 << (\line_width) | |
67 | __endla \ar, \at, 4 << (\line_width) | |
68 | ||
69 | .endm | |
70 | ||
71 | ||
72 | #if XCHAL_DCACHE_LINE_LOCKABLE | |
73 | ||
74 | .macro ___unlock_dcache_all ar at | |
75 | ||
01618bde | 76 | #if XCHAL_DCACHE_SIZE |
173d6681 | 77 | __loop_cache_all \ar \at diu XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH |
01618bde | 78 | #endif |
173d6681 CZ |
79 | |
80 | .endm | |
81 | ||
82 | #endif | |
83 | ||
84 | #if XCHAL_ICACHE_LINE_LOCKABLE | |
85 | ||
86 | .macro ___unlock_icache_all ar at | |
87 | ||
88 | __loop_cache_all \ar \at iiu XCHAL_ICACHE_SIZE XCHAL_ICACHE_LINEWIDTH | |
89 | ||
90 | .endm | |
91 | #endif | |
92 | ||
93 | .macro ___flush_invalidate_dcache_all ar at | |
94 | ||
01618bde | 95 | #if XCHAL_DCACHE_SIZE |
173d6681 | 96 | __loop_cache_all \ar \at diwbi XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH |
01618bde | 97 | #endif |
173d6681 CZ |
98 | |
99 | .endm | |
100 | ||
101 | ||
102 | .macro ___flush_dcache_all ar at | |
103 | ||
01618bde | 104 | #if XCHAL_DCACHE_SIZE |
173d6681 | 105 | __loop_cache_all \ar \at diwb XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH |
01618bde | 106 | #endif |
173d6681 CZ |
107 | |
108 | .endm | |
109 | ||
110 | ||
111 | .macro ___invalidate_dcache_all ar at | |
112 | ||
01618bde | 113 | #if XCHAL_DCACHE_SIZE |
173d6681 CZ |
114 | __loop_cache_all \ar \at dii __stringify(DCACHE_WAY_SIZE) \ |
115 | XCHAL_DCACHE_LINEWIDTH | |
01618bde | 116 | #endif |
173d6681 CZ |
117 | |
118 | .endm | |
119 | ||
120 | ||
121 | .macro ___invalidate_icache_all ar at | |
122 | ||
01618bde | 123 | #if XCHAL_ICACHE_SIZE |
173d6681 CZ |
124 | __loop_cache_all \ar \at iii __stringify(ICACHE_WAY_SIZE) \ |
125 | XCHAL_ICACHE_LINEWIDTH | |
01618bde | 126 | #endif |
173d6681 CZ |
127 | |
128 | .endm | |
129 | ||
130 | ||
131 | ||
132 | .macro ___flush_invalidate_dcache_range ar as at | |
133 | ||
01618bde | 134 | #if XCHAL_DCACHE_SIZE |
173d6681 | 135 | __loop_cache_range \ar \as \at dhwbi XCHAL_DCACHE_LINEWIDTH |
01618bde | 136 | #endif |
173d6681 CZ |
137 | |
138 | .endm | |
139 | ||
140 | ||
141 | .macro ___flush_dcache_range ar as at | |
142 | ||
01618bde | 143 | #if XCHAL_DCACHE_SIZE |
173d6681 | 144 | __loop_cache_range \ar \as \at dhwb XCHAL_DCACHE_LINEWIDTH |
01618bde | 145 | #endif |
173d6681 CZ |
146 | |
147 | .endm | |
148 | ||
149 | ||
150 | .macro ___invalidate_dcache_range ar as at | |
151 | ||
01618bde | 152 | #if XCHAL_DCACHE_SIZE |
173d6681 | 153 | __loop_cache_range \ar \as \at dhi XCHAL_DCACHE_LINEWIDTH |
01618bde | 154 | #endif |
173d6681 CZ |
155 | |
156 | .endm | |
157 | ||
158 | ||
159 | .macro ___invalidate_icache_range ar as at | |
160 | ||
01618bde | 161 | #if XCHAL_ICACHE_SIZE |
173d6681 | 162 | __loop_cache_range \ar \as \at ihi XCHAL_ICACHE_LINEWIDTH |
01618bde | 163 | #endif |
173d6681 CZ |
164 | |
165 | .endm | |
166 | ||
167 | ||
168 | ||
169 | .macro ___flush_invalidate_dcache_page ar as | |
170 | ||
01618bde | 171 | #if XCHAL_DCACHE_SIZE |
173d6681 | 172 | __loop_cache_page \ar \as dhwbi XCHAL_DCACHE_LINEWIDTH |
01618bde | 173 | #endif |
173d6681 CZ |
174 | |
175 | .endm | |
176 | ||
177 | ||
178 | .macro ___flush_dcache_page ar as | |
179 | ||
01618bde | 180 | #if XCHAL_DCACHE_SIZE |
173d6681 | 181 | __loop_cache_page \ar \as dhwb XCHAL_DCACHE_LINEWIDTH |
01618bde | 182 | #endif |
173d6681 CZ |
183 | |
184 | .endm | |
185 | ||
186 | ||
187 | .macro ___invalidate_dcache_page ar as | |
188 | ||
01618bde | 189 | #if XCHAL_DCACHE_SIZE |
173d6681 | 190 | __loop_cache_page \ar \as dhi XCHAL_DCACHE_LINEWIDTH |
01618bde | 191 | #endif |
173d6681 CZ |
192 | |
193 | .endm | |
194 | ||
195 | ||
196 | .macro ___invalidate_icache_page ar as | |
197 | ||
01618bde | 198 | #if XCHAL_ICACHE_SIZE |
173d6681 | 199 | __loop_cache_page \ar \as ihi XCHAL_ICACHE_LINEWIDTH |
01618bde | 200 | #endif |
173d6681 CZ |
201 | |
202 | .endm |