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9a8fd558 | 1 | /* |
9a8fd558 CZ |
2 | * This file is subject to the terms and conditions of the GNU General Public |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
f615136c | 6 | * (C) 2001 - 2013 Tensilica Inc. |
9a8fd558 CZ |
7 | */ |
8 | ||
9 | #ifndef _XTENSA_CACHEFLUSH_H | |
10 | #define _XTENSA_CACHEFLUSH_H | |
11 | ||
9a8fd558 CZ |
12 | #include <linux/mm.h> |
13 | #include <asm/processor.h> | |
14 | #include <asm/page.h> | |
15 | ||
16 | /* | |
6656920b | 17 | * Lo-level routines for cache flushing. |
9a8fd558 CZ |
18 | * |
19 | * invalidate data or instruction cache: | |
20 | * | |
21 | * __invalidate_icache_all() | |
22 | * __invalidate_icache_page(adr) | |
23 | * __invalidate_dcache_page(adr) | |
24 | * __invalidate_icache_range(from,size) | |
25 | * __invalidate_dcache_range(from,size) | |
26 | * | |
27 | * flush data cache: | |
28 | * | |
29 | * __flush_dcache_page(adr) | |
30 | * | |
31 | * flush and invalidate data cache: | |
32 | * | |
33 | * __flush_invalidate_dcache_all() | |
34 | * __flush_invalidate_dcache_page(adr) | |
35 | * __flush_invalidate_dcache_range(from,size) | |
6656920b CZ |
36 | * |
37 | * specials for cache aliasing: | |
38 | * | |
39 | * __flush_invalidate_dcache_page_alias(vaddr,paddr) | |
a91902db | 40 | * __invalidate_dcache_page_alias(vaddr,paddr) |
6656920b | 41 | * __invalidate_icache_page_alias(vaddr,paddr) |
9a8fd558 CZ |
42 | */ |
43 | ||
6656920b | 44 | extern void __invalidate_dcache_all(void); |
9a8fd558 | 45 | extern void __invalidate_icache_all(void); |
9a8fd558 CZ |
46 | extern void __invalidate_dcache_page(unsigned long); |
47 | extern void __invalidate_icache_page(unsigned long); | |
48 | extern void __invalidate_icache_range(unsigned long, unsigned long); | |
49 | extern void __invalidate_dcache_range(unsigned long, unsigned long); | |
50 | ||
51 | #if XCHAL_DCACHE_IS_WRITEBACK | |
6656920b | 52 | extern void __flush_invalidate_dcache_all(void); |
9a8fd558 | 53 | extern void __flush_dcache_page(unsigned long); |
6656920b | 54 | extern void __flush_dcache_range(unsigned long, unsigned long); |
9a8fd558 CZ |
55 | extern void __flush_invalidate_dcache_page(unsigned long); |
56 | extern void __flush_invalidate_dcache_range(unsigned long, unsigned long); | |
57 | #else | |
6656920b CZ |
58 | # define __flush_dcache_range(p,s) do { } while(0) |
59 | # define __flush_dcache_page(p) do { } while(0) | |
60 | # define __flush_invalidate_dcache_page(p) __invalidate_dcache_page(p) | |
61 | # define __flush_invalidate_dcache_range(p,s) __invalidate_dcache_range(p,s) | |
62 | #endif | |
63 | ||
e5083a63 | 64 | #if defined(CONFIG_MMU) && (DCACHE_WAY_SIZE > PAGE_SIZE) |
6656920b | 65 | extern void __flush_invalidate_dcache_page_alias(unsigned long, unsigned long); |
a91902db | 66 | extern void __invalidate_dcache_page_alias(unsigned long, unsigned long); |
e5083a63 JW |
67 | #else |
68 | static inline void __flush_invalidate_dcache_page_alias(unsigned long virt, | |
69 | unsigned long phys) { } | |
6656920b | 70 | #endif |
e5083a63 | 71 | #if defined(CONFIG_MMU) && (ICACHE_WAY_SIZE > PAGE_SIZE) |
6656920b | 72 | extern void __invalidate_icache_page_alias(unsigned long, unsigned long); |
9f8fcf38 | 73 | #else |
e5083a63 JW |
74 | static inline void __invalidate_icache_page_alias(unsigned long virt, |
75 | unsigned long phys) { } | |
9a8fd558 CZ |
76 | #endif |
77 | ||
78 | /* | |
79 | * We have physically tagged caches - nothing to do here - | |
80 | * unless we have cache aliasing. | |
81 | * | |
82 | * Pages can get remapped. Because this might change the 'color' of that page, | |
83 | * we have to flush the cache before the PTE is changed. | |
84 | * (see also Documentation/cachetlb.txt) | |
85 | */ | |
86 | ||
f615136c MF |
87 | #if (DCACHE_WAY_SIZE > PAGE_SIZE) || defined(CONFIG_SMP) |
88 | ||
89 | #ifdef CONFIG_SMP | |
90 | void flush_cache_all(void); | |
91 | void flush_cache_range(struct vm_area_struct*, ulong, ulong); | |
92 | void flush_icache_range(unsigned long start, unsigned long end); | |
93 | void flush_cache_page(struct vm_area_struct*, | |
94 | unsigned long, unsigned long); | |
95 | #else | |
96 | #define flush_cache_all local_flush_cache_all | |
97 | #define flush_cache_range local_flush_cache_range | |
98 | #define flush_icache_range local_flush_icache_range | |
99 | #define flush_cache_page local_flush_cache_page | |
100 | #endif | |
9a8fd558 | 101 | |
f615136c | 102 | #define local_flush_cache_all() \ |
6656920b CZ |
103 | do { \ |
104 | __flush_invalidate_dcache_all(); \ | |
105 | __invalidate_icache_all(); \ | |
106 | } while (0) | |
9a8fd558 | 107 | |
6656920b CZ |
108 | #define flush_cache_mm(mm) flush_cache_all() |
109 | #define flush_cache_dup_mm(mm) flush_cache_mm(mm) | |
9a8fd558 | 110 | |
6656920b CZ |
111 | #define flush_cache_vmap(start,end) flush_cache_all() |
112 | #define flush_cache_vunmap(start,end) flush_cache_all() | |
9a8fd558 | 113 | |
2d4dc890 | 114 | #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1 |
6656920b | 115 | extern void flush_dcache_page(struct page*); |
f615136c MF |
116 | |
117 | void local_flush_cache_range(struct vm_area_struct *vma, | |
118 | unsigned long start, unsigned long end); | |
119 | void local_flush_cache_page(struct vm_area_struct *vma, | |
120 | unsigned long address, unsigned long pfn); | |
9a8fd558 CZ |
121 | |
122 | #else | |
123 | ||
124 | #define flush_cache_all() do { } while (0) | |
125 | #define flush_cache_mm(mm) do { } while (0) | |
ec8c0446 | 126 | #define flush_cache_dup_mm(mm) do { } while (0) |
9a8fd558 CZ |
127 | |
128 | #define flush_cache_vmap(start,end) do { } while (0) | |
129 | #define flush_cache_vunmap(start,end) do { } while (0) | |
130 | ||
91e08063 | 131 | #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0 |
9a8fd558 CZ |
132 | #define flush_dcache_page(page) do { } while (0) |
133 | ||
f615136c MF |
134 | #define flush_icache_range local_flush_icache_range |
135 | #define flush_cache_page(vma, addr, pfn) do { } while (0) | |
136 | #define flush_cache_range(vma, start, end) do { } while (0) | |
9a8fd558 CZ |
137 | |
138 | #endif | |
139 | ||
6656920b | 140 | /* Ensure consistency between data and instruction cache. */ |
f615136c | 141 | #define local_flush_icache_range(start, end) \ |
6656920b CZ |
142 | do { \ |
143 | __flush_dcache_range(start, (end) - (start)); \ | |
144 | __invalidate_icache_range(start,(end) - (start)); \ | |
145 | } while (0) | |
9a8fd558 CZ |
146 | |
147 | /* This is not required, see Documentation/cachetlb.txt */ | |
6656920b | 148 | #define flush_icache_page(vma,page) do { } while (0) |
9a8fd558 CZ |
149 | |
150 | #define flush_dcache_mmap_lock(mapping) do { } while (0) | |
151 | #define flush_dcache_mmap_unlock(mapping) do { } while (0) | |
152 | ||
6656920b | 153 | #if (DCACHE_WAY_SIZE > PAGE_SIZE) |
9a8fd558 | 154 | |
6656920b CZ |
155 | extern void copy_to_user_page(struct vm_area_struct*, struct page*, |
156 | unsigned long, void*, const void*, unsigned long); | |
157 | extern void copy_from_user_page(struct vm_area_struct*, struct page*, | |
158 | unsigned long, void*, const void*, unsigned long); | |
159 | ||
160 | #else | |
161 | ||
162 | #define copy_to_user_page(vma, page, vaddr, dst, src, len) \ | |
163 | do { \ | |
164 | memcpy(dst, src, len); \ | |
165 | __flush_dcache_range((unsigned long) dst, len); \ | |
166 | __invalidate_icache_range((unsigned long) dst, len); \ | |
167 | } while (0) | |
9a8fd558 CZ |
168 | |
169 | #define copy_from_user_page(vma, page, vaddr, dst, src, len) \ | |
170 | memcpy(dst, src, len) | |
171 | ||
6656920b | 172 | #endif |
9a8fd558 | 173 | |
bd974240 OS |
174 | #define XTENSA_CACHEBLK_LOG2 29 |
175 | #define XTENSA_CACHEBLK_SIZE (1 << XTENSA_CACHEBLK_LOG2) | |
176 | #define XTENSA_CACHEBLK_MASK (7 << XTENSA_CACHEBLK_LOG2) | |
177 | ||
178 | #if XCHAL_HAVE_CACHEATTR | |
179 | static inline u32 xtensa_get_cacheattr(void) | |
180 | { | |
181 | u32 r; | |
bc5378fc | 182 | asm volatile(" rsr %0, cacheattr" : "=a"(r)); |
bd974240 OS |
183 | return r; |
184 | } | |
185 | ||
186 | static inline u32 xtensa_get_dtlb1(u32 addr) | |
187 | { | |
188 | u32 r = addr & XTENSA_CACHEBLK_MASK; | |
189 | return r | ((xtensa_get_cacheattr() >> (r >> (XTENSA_CACHEBLK_LOG2-2))) | |
190 | & 0xF); | |
191 | } | |
192 | #else | |
193 | static inline u32 xtensa_get_dtlb1(u32 addr) | |
194 | { | |
195 | u32 r; | |
196 | asm volatile(" rdtlb1 %0, %1" : "=a"(r) : "a"(addr)); | |
197 | asm volatile(" dsync"); | |
198 | return r; | |
199 | } | |
200 | ||
201 | static inline u32 xtensa_get_cacheattr(void) | |
202 | { | |
203 | u32 r = 0; | |
204 | u32 a = 0; | |
205 | do { | |
206 | a -= XTENSA_CACHEBLK_SIZE; | |
207 | r = (r << 4) | (xtensa_get_dtlb1(a) & 0xF); | |
208 | } while (a); | |
209 | return r; | |
210 | } | |
211 | #endif | |
212 | ||
213 | static inline int xtensa_need_flush_dma_source(u32 addr) | |
214 | { | |
215 | return (xtensa_get_dtlb1(addr) & ((1 << XCHAL_CA_BITS) - 1)) >= 4; | |
216 | } | |
217 | ||
218 | static inline int xtensa_need_invalidate_dma_destination(u32 addr) | |
219 | { | |
220 | return (xtensa_get_dtlb1(addr) & ((1 << XCHAL_CA_BITS) - 1)) != 2; | |
221 | } | |
222 | ||
223 | static inline void flush_dcache_unaligned(u32 addr, u32 size) | |
224 | { | |
225 | u32 cnt; | |
226 | if (size) { | |
227 | cnt = (size + ((XCHAL_DCACHE_LINESIZE - 1) & addr) | |
228 | + XCHAL_DCACHE_LINESIZE - 1) / XCHAL_DCACHE_LINESIZE; | |
229 | while (cnt--) { | |
230 | asm volatile(" dhwb %0, 0" : : "a"(addr)); | |
231 | addr += XCHAL_DCACHE_LINESIZE; | |
232 | } | |
233 | asm volatile(" dsync"); | |
234 | } | |
235 | } | |
236 | ||
237 | static inline void invalidate_dcache_unaligned(u32 addr, u32 size) | |
238 | { | |
239 | int cnt; | |
240 | if (size) { | |
241 | asm volatile(" dhwbi %0, 0 ;" : : "a"(addr)); | |
242 | cnt = (size + ((XCHAL_DCACHE_LINESIZE - 1) & addr) | |
243 | - XCHAL_DCACHE_LINESIZE - 1) / XCHAL_DCACHE_LINESIZE; | |
244 | while (cnt-- > 0) { | |
245 | asm volatile(" dhi %0, %1" : : "a"(addr), | |
246 | "n"(XCHAL_DCACHE_LINESIZE)); | |
247 | addr += XCHAL_DCACHE_LINESIZE; | |
248 | } | |
249 | asm volatile(" dhwbi %0, %1" : : "a"(addr), | |
250 | "n"(XCHAL_DCACHE_LINESIZE)); | |
251 | asm volatile(" dsync"); | |
252 | } | |
253 | } | |
254 | ||
255 | static inline void flush_invalidate_dcache_unaligned(u32 addr, u32 size) | |
256 | { | |
257 | u32 cnt; | |
258 | if (size) { | |
259 | cnt = (size + ((XCHAL_DCACHE_LINESIZE - 1) & addr) | |
260 | + XCHAL_DCACHE_LINESIZE - 1) / XCHAL_DCACHE_LINESIZE; | |
261 | while (cnt--) { | |
262 | asm volatile(" dhwbi %0, 0" : : "a"(addr)); | |
263 | addr += XCHAL_DCACHE_LINESIZE; | |
264 | } | |
265 | asm volatile(" dsync"); | |
266 | } | |
267 | } | |
268 | ||
9a8fd558 | 269 | #endif /* _XTENSA_CACHEFLUSH_H */ |