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5a0015d6 CZ |
1 | /* |
2 | * arch/xtensa/kernel/entry.S | |
3 | * | |
4 | * Low-level exception handling | |
5 | * | |
6 | * This file is subject to the terms and conditions of the GNU General Public | |
7 | * License. See the file "COPYING" in the main directory of this archive | |
8 | * for more details. | |
9 | * | |
2d1c645c | 10 | * Copyright (C) 2004 - 2008 by Tensilica Inc. |
5a0015d6 CZ |
11 | * |
12 | * Chris Zankel <chris@zankel.net> | |
13 | * | |
14 | */ | |
15 | ||
16 | #include <linux/linkage.h> | |
0013a854 | 17 | #include <asm/asm-offsets.h> |
5a0015d6 | 18 | #include <asm/processor.h> |
4573e398 | 19 | #include <asm/coprocessor.h> |
5a0015d6 CZ |
20 | #include <asm/thread_info.h> |
21 | #include <asm/uaccess.h> | |
22 | #include <asm/unistd.h> | |
23 | #include <asm/ptrace.h> | |
24 | #include <asm/current.h> | |
25 | #include <asm/pgtable.h> | |
26 | #include <asm/page.h> | |
27 | #include <asm/signal.h> | |
173d6681 | 28 | #include <asm/tlbflush.h> |
367b8112 | 29 | #include <variant/tie-asm.h> |
5a0015d6 CZ |
30 | |
31 | /* Unimplemented features. */ | |
32 | ||
5a0015d6 | 33 | #undef KERNEL_STACK_OVERFLOW_CHECK |
5a0015d6 CZ |
34 | |
35 | /* Not well tested. | |
36 | * | |
37 | * - fast_coprocessor | |
38 | */ | |
39 | ||
40 | /* | |
41 | * Macro to find first bit set in WINDOWBASE from the left + 1 | |
42 | * | |
43 | * 100....0 -> 1 | |
44 | * 010....0 -> 2 | |
45 | * 000....1 -> WSBITS | |
46 | */ | |
47 | ||
48 | .macro ffs_ws bit mask | |
49 | ||
50 | #if XCHAL_HAVE_NSA | |
51 | nsau \bit, \mask # 32-WSBITS ... 31 (32 iff 0) | |
52 | addi \bit, \bit, WSBITS - 32 + 1 # uppest bit set -> return 1 | |
53 | #else | |
54 | movi \bit, WSBITS | |
55 | #if WSBITS > 16 | |
56 | _bltui \mask, 0x10000, 99f | |
57 | addi \bit, \bit, -16 | |
58 | extui \mask, \mask, 16, 16 | |
59 | #endif | |
60 | #if WSBITS > 8 | |
61 | 99: _bltui \mask, 0x100, 99f | |
62 | addi \bit, \bit, -8 | |
63 | srli \mask, \mask, 8 | |
64 | #endif | |
65 | 99: _bltui \mask, 0x10, 99f | |
66 | addi \bit, \bit, -4 | |
67 | srli \mask, \mask, 4 | |
68 | 99: _bltui \mask, 0x4, 99f | |
69 | addi \bit, \bit, -2 | |
70 | srli \mask, \mask, 2 | |
71 | 99: _bltui \mask, 0x2, 99f | |
72 | addi \bit, \bit, -1 | |
73 | 99: | |
74 | ||
75 | #endif | |
76 | .endm | |
77 | ||
78 | /* ----------------- DEFAULT FIRST LEVEL EXCEPTION HANDLERS ----------------- */ | |
79 | ||
80 | /* | |
81 | * First-level exception handler for user exceptions. | |
82 | * Save some special registers, extra states and all registers in the AR | |
83 | * register file that were in use in the user task, and jump to the common | |
84 | * exception code. | |
85 | * We save SAR (used to calculate WMASK), and WB and WS (we don't have to | |
86 | * save them for kernel exceptions). | |
87 | * | |
88 | * Entry condition for user_exception: | |
89 | * | |
90 | * a0: trashed, original value saved on stack (PT_AREG0) | |
91 | * a1: a1 | |
92 | * a2: new stack pointer, original value in depc | |
99d5040e | 93 | * a3: a3 |
5a0015d6 | 94 | * depc: a2, original value saved on stack (PT_DEPC) |
99d5040e | 95 | * excsave1: dispatch table |
5a0015d6 CZ |
96 | * |
97 | * PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC | |
98 | * < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception | |
99 | * | |
100 | * Entry condition for _user_exception: | |
101 | * | |
102 | * a0-a3 and depc have been saved to PT_AREG0...PT_AREG3 and PT_DEPC | |
103 | * excsave has been restored, and | |
104 | * stack pointer (a1) has been set. | |
105 | * | |
3ad2f3fb | 106 | * Note: _user_exception might be at an odd address. Don't use call0..call12 |
5a0015d6 CZ |
107 | */ |
108 | ||
109 | ENTRY(user_exception) | |
110 | ||
99d5040e | 111 | /* Save a1, a2, a3, and set SP. */ |
5a0015d6 | 112 | |
bc5378fc | 113 | rsr a0, depc |
5a0015d6 CZ |
114 | s32i a1, a2, PT_AREG1 |
115 | s32i a0, a2, PT_AREG2 | |
116 | s32i a3, a2, PT_AREG3 | |
117 | mov a1, a2 | |
118 | ||
119 | .globl _user_exception | |
120 | _user_exception: | |
121 | ||
122 | /* Save SAR and turn off single stepping */ | |
123 | ||
124 | movi a2, 0 | |
bc5378fc MF |
125 | rsr a3, sar |
126 | xsr a2, icountlevel | |
5a0015d6 | 127 | s32i a3, a1, PT_SAR |
29c4dfd9 | 128 | s32i a2, a1, PT_ICOUNTLEVEL |
5a0015d6 | 129 | |
c50842df CZ |
130 | #if XCHAL_HAVE_THREADPTR |
131 | rur a2, threadptr | |
132 | s32i a2, a1, PT_THREADPTR | |
133 | #endif | |
134 | ||
5a0015d6 CZ |
135 | /* Rotate ws so that the current windowbase is at bit0. */ |
136 | /* Assume ws = xxwww1yyyy. Rotate ws right, so that a2 = yyyyxxwww1 */ | |
137 | ||
bc5378fc MF |
138 | rsr a2, windowbase |
139 | rsr a3, windowstart | |
5a0015d6 CZ |
140 | ssr a2 |
141 | s32i a2, a1, PT_WINDOWBASE | |
142 | s32i a3, a1, PT_WINDOWSTART | |
143 | slli a2, a3, 32-WSBITS | |
144 | src a2, a3, a2 | |
145 | srli a2, a2, 32-WSBITS | |
146 | s32i a2, a1, PT_WMASK # needed for restoring registers | |
147 | ||
148 | /* Save only live registers. */ | |
149 | ||
150 | _bbsi.l a2, 1, 1f | |
151 | s32i a4, a1, PT_AREG4 | |
152 | s32i a5, a1, PT_AREG5 | |
153 | s32i a6, a1, PT_AREG6 | |
154 | s32i a7, a1, PT_AREG7 | |
155 | _bbsi.l a2, 2, 1f | |
156 | s32i a8, a1, PT_AREG8 | |
157 | s32i a9, a1, PT_AREG9 | |
158 | s32i a10, a1, PT_AREG10 | |
159 | s32i a11, a1, PT_AREG11 | |
160 | _bbsi.l a2, 3, 1f | |
161 | s32i a12, a1, PT_AREG12 | |
162 | s32i a13, a1, PT_AREG13 | |
163 | s32i a14, a1, PT_AREG14 | |
164 | s32i a15, a1, PT_AREG15 | |
165 | _bnei a2, 1, 1f # only one valid frame? | |
166 | ||
167 | /* Only one valid frame, skip saving regs. */ | |
168 | ||
169 | j 2f | |
170 | ||
171 | /* Save the remaining registers. | |
172 | * We have to save all registers up to the first '1' from | |
173 | * the right, except the current frame (bit 0). | |
174 | * Assume a2 is: 001001000110001 | |
6656920b | 175 | * All register frames starting from the top field to the marked '1' |
5a0015d6 CZ |
176 | * must be saved. |
177 | */ | |
178 | ||
179 | 1: addi a3, a2, -1 # eliminate '1' in bit 0: yyyyxxww0 | |
180 | neg a3, a3 # yyyyxxww0 -> YYYYXXWW1+1 | |
181 | and a3, a3, a2 # max. only one bit is set | |
182 | ||
183 | /* Find number of frames to save */ | |
184 | ||
185 | ffs_ws a0, a3 # number of frames to the '1' from left | |
186 | ||
187 | /* Store information into WMASK: | |
188 | * bits 0..3: xxx1 masked lower 4 bits of the rotated windowstart, | |
189 | * bits 4...: number of valid 4-register frames | |
190 | */ | |
191 | ||
192 | slli a3, a0, 4 # number of frames to save in bits 8..4 | |
193 | extui a2, a2, 0, 4 # mask for the first 16 registers | |
194 | or a2, a3, a2 | |
195 | s32i a2, a1, PT_WMASK # needed when we restore the reg-file | |
196 | ||
197 | /* Save 4 registers at a time */ | |
198 | ||
199 | 1: rotw -1 | |
200 | s32i a0, a5, PT_AREG_END - 16 | |
201 | s32i a1, a5, PT_AREG_END - 12 | |
202 | s32i a2, a5, PT_AREG_END - 8 | |
203 | s32i a3, a5, PT_AREG_END - 4 | |
204 | addi a0, a4, -1 | |
205 | addi a1, a5, -16 | |
206 | _bnez a0, 1b | |
207 | ||
208 | /* WINDOWBASE still in SAR! */ | |
209 | ||
bc5378fc | 210 | rsr a2, sar # original WINDOWBASE |
5a0015d6 CZ |
211 | movi a3, 1 |
212 | ssl a2 | |
213 | sll a3, a3 | |
bc5378fc MF |
214 | wsr a3, windowstart # set corresponding WINDOWSTART bit |
215 | wsr a2, windowbase # and WINDOWSTART | |
5a0015d6 CZ |
216 | rsync |
217 | ||
218 | /* We are back to the original stack pointer (a1) */ | |
219 | ||
c658eac6 | 220 | 2: /* Now, jump to the common exception handler. */ |
5a0015d6 CZ |
221 | |
222 | j common_exception | |
223 | ||
d1538c46 | 224 | ENDPROC(user_exception) |
5a0015d6 CZ |
225 | |
226 | /* | |
227 | * First-level exit handler for kernel exceptions | |
228 | * Save special registers and the live window frame. | |
229 | * Note: Even though we changes the stack pointer, we don't have to do a | |
230 | * MOVSP here, as we do that when we return from the exception. | |
231 | * (See comment in the kernel exception exit code) | |
232 | * | |
233 | * Entry condition for kernel_exception: | |
234 | * | |
235 | * a0: trashed, original value saved on stack (PT_AREG0) | |
236 | * a1: a1 | |
237 | * a2: new stack pointer, original in DEPC | |
99d5040e | 238 | * a3: a3 |
5a0015d6 | 239 | * depc: a2, original value saved on stack (PT_DEPC) |
99d5040e | 240 | * excsave_1: dispatch table |
5a0015d6 CZ |
241 | * |
242 | * PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC | |
243 | * < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception | |
244 | * | |
245 | * Entry condition for _kernel_exception: | |
246 | * | |
247 | * a0-a3 and depc have been saved to PT_AREG0...PT_AREG3 and PT_DEPC | |
248 | * excsave has been restored, and | |
249 | * stack pointer (a1) has been set. | |
250 | * | |
3ad2f3fb | 251 | * Note: _kernel_exception might be at an odd address. Don't use call0..call12 |
5a0015d6 CZ |
252 | */ |
253 | ||
254 | ENTRY(kernel_exception) | |
255 | ||
99d5040e | 256 | /* Save a1, a2, a3, and set SP. */ |
5a0015d6 | 257 | |
bc5378fc | 258 | rsr a0, depc # get a2 |
5a0015d6 CZ |
259 | s32i a1, a2, PT_AREG1 |
260 | s32i a0, a2, PT_AREG2 | |
261 | s32i a3, a2, PT_AREG3 | |
262 | mov a1, a2 | |
263 | ||
264 | .globl _kernel_exception | |
265 | _kernel_exception: | |
266 | ||
267 | /* Save SAR and turn off single stepping */ | |
268 | ||
269 | movi a2, 0 | |
bc5378fc MF |
270 | rsr a3, sar |
271 | xsr a2, icountlevel | |
5a0015d6 | 272 | s32i a3, a1, PT_SAR |
29c4dfd9 | 273 | s32i a2, a1, PT_ICOUNTLEVEL |
5a0015d6 CZ |
274 | |
275 | /* Rotate ws so that the current windowbase is at bit0. */ | |
276 | /* Assume ws = xxwww1yyyy. Rotate ws right, so that a2 = yyyyxxwww1 */ | |
277 | ||
bc5378fc MF |
278 | rsr a2, windowbase # don't need to save these, we only |
279 | rsr a3, windowstart # need shifted windowstart: windowmask | |
5a0015d6 CZ |
280 | ssr a2 |
281 | slli a2, a3, 32-WSBITS | |
282 | src a2, a3, a2 | |
283 | srli a2, a2, 32-WSBITS | |
284 | s32i a2, a1, PT_WMASK # needed for kernel_exception_exit | |
285 | ||
286 | /* Save only the live window-frame */ | |
287 | ||
288 | _bbsi.l a2, 1, 1f | |
289 | s32i a4, a1, PT_AREG4 | |
290 | s32i a5, a1, PT_AREG5 | |
291 | s32i a6, a1, PT_AREG6 | |
292 | s32i a7, a1, PT_AREG7 | |
293 | _bbsi.l a2, 2, 1f | |
294 | s32i a8, a1, PT_AREG8 | |
295 | s32i a9, a1, PT_AREG9 | |
296 | s32i a10, a1, PT_AREG10 | |
297 | s32i a11, a1, PT_AREG11 | |
298 | _bbsi.l a2, 3, 1f | |
299 | s32i a12, a1, PT_AREG12 | |
300 | s32i a13, a1, PT_AREG13 | |
301 | s32i a14, a1, PT_AREG14 | |
302 | s32i a15, a1, PT_AREG15 | |
303 | ||
304 | 1: | |
305 | ||
306 | #ifdef KERNEL_STACK_OVERFLOW_CHECK | |
307 | ||
308 | /* Stack overflow check, for debugging */ | |
309 | extui a2, a1, TASK_SIZE_BITS,XX | |
310 | movi a3, SIZE?? | |
311 | _bge a2, a3, out_of_stack_panic | |
312 | ||
313 | #endif | |
314 | ||
315 | /* | |
316 | * This is the common exception handler. | |
317 | * We get here from the user exception handler or simply by falling through | |
318 | * from the kernel exception handler. | |
319 | * Save the remaining special registers, switch to kernel mode, and jump | |
320 | * to the second-level exception handler. | |
321 | * | |
322 | */ | |
323 | ||
324 | common_exception: | |
325 | ||
29c4dfd9 | 326 | /* Save some registers, disable loops and clear the syscall flag. */ |
5a0015d6 | 327 | |
bc5378fc MF |
328 | rsr a2, debugcause |
329 | rsr a3, epc1 | |
5a0015d6 CZ |
330 | s32i a2, a1, PT_DEBUGCAUSE |
331 | s32i a3, a1, PT_PC | |
332 | ||
29c4dfd9 | 333 | movi a2, -1 |
bc5378fc | 334 | rsr a3, excvaddr |
29c4dfd9 | 335 | s32i a2, a1, PT_SYSCALL |
5a0015d6 CZ |
336 | movi a2, 0 |
337 | s32i a3, a1, PT_EXCVADDR | |
bc5378fc | 338 | xsr a2, lcount |
5a0015d6 CZ |
339 | s32i a2, a1, PT_LCOUNT |
340 | ||
341 | /* It is now save to restore the EXC_TABLE_FIXUP variable. */ | |
342 | ||
bc5378fc | 343 | rsr a0, exccause |
5a0015d6 | 344 | movi a3, 0 |
bc5378fc | 345 | rsr a2, excsave1 |
5a0015d6 CZ |
346 | s32i a0, a1, PT_EXCCAUSE |
347 | s32i a3, a2, EXC_TABLE_FIXUP | |
348 | ||
349 | /* All unrecoverable states are saved on stack, now, and a1 is valid, | |
350 | * so we can allow exceptions and interrupts (*) again. | |
351 | * Set PS(EXCM = 0, UM = 0, RING = 0, OWB = 0, WOE = 1, INTLEVEL = X) | |
352 | * | |
895666a9 MF |
353 | * (*) We only allow interrupts if they were previously enabled and |
354 | * we're not handling an IRQ | |
5a0015d6 CZ |
355 | */ |
356 | ||
bc5378fc | 357 | rsr a3, ps |
895666a9 MF |
358 | addi a0, a0, -EXCCAUSE_LEVEL1_INTERRUPT |
359 | movi a2, LOCKLEVEL | |
2d1c645c MG |
360 | extui a3, a3, PS_INTLEVEL_SHIFT, PS_INTLEVEL_WIDTH |
361 | # a3 = PS.INTLEVEL | |
895666a9 | 362 | moveqz a3, a2, a0 # a3 = LOCKLEVEL iff interrupt |
173d6681 | 363 | movi a2, 1 << PS_WOE_BIT |
5a0015d6 | 364 | or a3, a3, a2 |
bc5378fc MF |
365 | rsr a0, exccause |
366 | xsr a3, ps | |
5a0015d6 CZ |
367 | |
368 | s32i a3, a1, PT_PS # save ps | |
369 | ||
bc5378fc | 370 | /* Save lbeg, lend */ |
5a0015d6 | 371 | |
bc5378fc MF |
372 | rsr a2, lbeg |
373 | rsr a3, lend | |
5a0015d6 CZ |
374 | s32i a2, a1, PT_LBEG |
375 | s32i a3, a1, PT_LEND | |
376 | ||
733536b8 MF |
377 | /* Save SCOMPARE1 */ |
378 | ||
379 | #if XCHAL_HAVE_S32C1I | |
380 | rsr a2, scompare1 | |
381 | s32i a2, a1, PT_SCOMPARE1 | |
382 | #endif | |
383 | ||
c658eac6 CZ |
384 | /* Save optional registers. */ |
385 | ||
386 | save_xtregs_opt a1 a2 a4 a5 a6 a7 PT_XTREGS_OPT | |
387 | ||
c92931b2 MF |
388 | #ifdef CONFIG_TRACE_IRQFLAGS |
389 | l32i a4, a1, PT_DEPC | |
390 | /* Double exception means we came here with an exception | |
391 | * while PS.EXCM was set, i.e. interrupts disabled. | |
392 | */ | |
393 | bgeui a4, VALID_DOUBLE_EXCEPTION_ADDRESS, 1f | |
394 | l32i a4, a1, PT_EXCCAUSE | |
395 | bnei a4, EXCCAUSE_LEVEL1_INTERRUPT, 1f | |
396 | /* We came here with an interrupt means interrupts were enabled | |
397 | * and we've just disabled them. | |
398 | */ | |
399 | movi a4, trace_hardirqs_off | |
400 | callx4 a4 | |
401 | 1: | |
402 | #endif | |
403 | ||
5a0015d6 CZ |
404 | /* Go to second-level dispatcher. Set up parameters to pass to the |
405 | * exception handler and call the exception handler. | |
406 | */ | |
407 | ||
99d5040e | 408 | rsr a4, excsave1 |
5a0015d6 CZ |
409 | mov a6, a1 # pass stack frame |
410 | mov a7, a0 # pass EXCCAUSE | |
411 | addx4 a4, a0, a4 | |
412 | l32i a4, a4, EXC_TABLE_DEFAULT # load handler | |
413 | ||
414 | /* Call the second-level handler */ | |
415 | ||
416 | callx4 a4 | |
417 | ||
418 | /* Jump here for exception exit */ | |
e6ffe17e | 419 | .global common_exception_return |
5a0015d6 CZ |
420 | common_exception_return: |
421 | ||
c92931b2 | 422 | 1: |
aea8e7c8 | 423 | rsil a2, LOCKLEVEL |
c92931b2 | 424 | |
5a0015d6 CZ |
425 | /* Jump if we are returning from kernel exceptions. */ |
426 | ||
aea8e7c8 | 427 | l32i a3, a1, PT_PS |
16c5becf MF |
428 | GET_THREAD_INFO(a2, a1) |
429 | l32i a4, a2, TI_FLAGS | |
430 | _bbci.l a3, PS_UM_BIT, 6f | |
5a0015d6 CZ |
431 | |
432 | /* Specific to a user exception exit: | |
433 | * We need to check some flags for signal handling and rescheduling, | |
434 | * and have to restore WB and WS, extra states, and all registers | |
435 | * in the register file that were in use in the user task. | |
e1088430 | 436 | * Note that we don't disable interrupts here. |
5a0015d6 CZ |
437 | */ |
438 | ||
5a0015d6 | 439 | _bbsi.l a4, TIF_NEED_RESCHED, 3f |
a53bb24e | 440 | _bbsi.l a4, TIF_NOTIFY_RESUME, 2f |
a99e07ee | 441 | _bbci.l a4, TIF_SIGPENDING, 5f |
5a0015d6 | 442 | |
a53bb24e | 443 | 2: l32i a4, a1, PT_DEPC |
5a0015d6 | 444 | bgeui a4, VALID_DOUBLE_EXCEPTION_ADDRESS, 4f |
5a0015d6 | 445 | |
e1088430 CZ |
446 | /* Call do_signal() */ |
447 | ||
aea8e7c8 | 448 | rsil a2, 0 |
a53bb24e | 449 | movi a4, do_notify_resume # int do_notify_resume(struct pt_regs*) |
5a0015d6 | 450 | mov a6, a1 |
5a0015d6 CZ |
451 | callx4 a4 |
452 | j 1b | |
453 | ||
e1088430 | 454 | 3: /* Reschedule */ |
5a0015d6 | 455 | |
aea8e7c8 | 456 | rsil a2, 0 |
5a0015d6 CZ |
457 | movi a4, schedule # void schedule (void) |
458 | callx4 a4 | |
459 | j 1b | |
460 | ||
16c5becf MF |
461 | #ifdef CONFIG_PREEMPT |
462 | 6: | |
463 | _bbci.l a4, TIF_NEED_RESCHED, 4f | |
464 | ||
465 | /* Check current_thread_info->preempt_count */ | |
466 | ||
467 | l32i a4, a2, TI_PRE_COUNT | |
468 | bnez a4, 4f | |
469 | movi a4, preempt_schedule_irq | |
470 | callx4 a4 | |
471 | j 1b | |
472 | #endif | |
473 | ||
a99e07ee MF |
474 | 5: |
475 | #ifdef CONFIG_DEBUG_TLB_SANITY | |
476 | l32i a4, a1, PT_DEPC | |
477 | bgeui a4, VALID_DOUBLE_EXCEPTION_ADDRESS, 4f | |
478 | movi a4, check_tlb_sanity | |
479 | callx4 a4 | |
480 | #endif | |
16c5becf | 481 | 6: |
aea8e7c8 MF |
482 | 4: |
483 | #ifdef CONFIG_TRACE_IRQFLAGS | |
484 | l32i a4, a1, PT_DEPC | |
485 | /* Double exception means we came here with an exception | |
486 | * while PS.EXCM was set, i.e. interrupts disabled. | |
487 | */ | |
488 | bgeui a4, VALID_DOUBLE_EXCEPTION_ADDRESS, 1f | |
489 | l32i a4, a1, PT_EXCCAUSE | |
490 | bnei a4, EXCCAUSE_LEVEL1_INTERRUPT, 1f | |
491 | /* We came here with an interrupt means interrupts were enabled | |
492 | * and we'll reenable them on return. | |
493 | */ | |
494 | movi a4, trace_hardirqs_on | |
495 | callx4 a4 | |
496 | 1: | |
497 | #endif | |
498 | /* Restore optional registers. */ | |
e1088430 CZ |
499 | |
500 | load_xtregs_opt a1 a2 a4 a5 a6 a7 PT_XTREGS_OPT | |
5a0015d6 | 501 | |
733536b8 MF |
502 | /* Restore SCOMPARE1 */ |
503 | ||
504 | #if XCHAL_HAVE_S32C1I | |
505 | l32i a2, a1, PT_SCOMPARE1 | |
506 | wsr a2, scompare1 | |
507 | #endif | |
bc5378fc | 508 | wsr a3, ps /* disable interrupts */ |
e1088430 CZ |
509 | |
510 | _bbci.l a3, PS_UM_BIT, kernel_exception_exit | |
511 | ||
512 | user_exception_exit: | |
513 | ||
514 | /* Restore the state of the task and return from the exception. */ | |
5a0015d6 | 515 | |
5a0015d6 CZ |
516 | /* Switch to the user thread WINDOWBASE. Save SP temporarily in DEPC */ |
517 | ||
518 | l32i a2, a1, PT_WINDOWBASE | |
519 | l32i a3, a1, PT_WINDOWSTART | |
bc5378fc MF |
520 | wsr a1, depc # use DEPC as temp storage |
521 | wsr a3, windowstart # restore WINDOWSTART | |
5a0015d6 | 522 | ssr a2 # preserve user's WB in the SAR |
bc5378fc | 523 | wsr a2, windowbase # switch to user's saved WB |
5a0015d6 | 524 | rsync |
bc5378fc | 525 | rsr a1, depc # restore stack pointer |
5a0015d6 CZ |
526 | l32i a2, a1, PT_WMASK # register frames saved (in bits 4...9) |
527 | rotw -1 # we restore a4..a7 | |
528 | _bltui a6, 16, 1f # only have to restore current window? | |
529 | ||
530 | /* The working registers are a0 and a3. We are restoring to | |
531 | * a4..a7. Be careful not to destroy what we have just restored. | |
532 | * Note: wmask has the format YYYYM: | |
533 | * Y: number of registers saved in groups of 4 | |
534 | * M: 4 bit mask of first 16 registers | |
535 | */ | |
536 | ||
537 | mov a2, a6 | |
538 | mov a3, a5 | |
539 | ||
540 | 2: rotw -1 # a0..a3 become a4..a7 | |
541 | addi a3, a7, -4*4 # next iteration | |
542 | addi a2, a6, -16 # decrementing Y in WMASK | |
543 | l32i a4, a3, PT_AREG_END + 0 | |
544 | l32i a5, a3, PT_AREG_END + 4 | |
545 | l32i a6, a3, PT_AREG_END + 8 | |
546 | l32i a7, a3, PT_AREG_END + 12 | |
547 | _bgeui a2, 16, 2b | |
548 | ||
549 | /* Clear unrestored registers (don't leak anything to user-land */ | |
550 | ||
bc5378fc MF |
551 | 1: rsr a0, windowbase |
552 | rsr a3, sar | |
5a0015d6 CZ |
553 | sub a3, a0, a3 |
554 | beqz a3, 2f | |
555 | extui a3, a3, 0, WBBITS | |
556 | ||
557 | 1: rotw -1 | |
558 | addi a3, a7, -1 | |
559 | movi a4, 0 | |
560 | movi a5, 0 | |
561 | movi a6, 0 | |
562 | movi a7, 0 | |
563 | bgei a3, 1, 1b | |
564 | ||
565 | /* We are back were we were when we started. | |
566 | * Note: a2 still contains WMASK (if we've returned to the original | |
567 | * frame where we had loaded a2), or at least the lower 4 bits | |
568 | * (if we have restored WSBITS-1 frames). | |
569 | */ | |
570 | ||
c50842df CZ |
571 | #if XCHAL_HAVE_THREADPTR |
572 | l32i a3, a1, PT_THREADPTR | |
573 | wur a3, threadptr | |
574 | #endif | |
575 | ||
5a0015d6 CZ |
576 | 2: j common_exception_exit |
577 | ||
578 | /* This is the kernel exception exit. | |
579 | * We avoided to do a MOVSP when we entered the exception, but we | |
580 | * have to do it here. | |
581 | */ | |
582 | ||
583 | kernel_exception_exit: | |
584 | ||
5a0015d6 CZ |
585 | /* Check if we have to do a movsp. |
586 | * | |
587 | * We only have to do a movsp if the previous window-frame has | |
588 | * been spilled to the *temporary* exception stack instead of the | |
589 | * task's stack. This is the case if the corresponding bit in | |
590 | * WINDOWSTART for the previous window-frame was set before | |
591 | * (not spilled) but is zero now (spilled). | |
592 | * If this bit is zero, all other bits except the one for the | |
593 | * current window frame are also zero. So, we can use a simple test: | |
594 | * 'and' WINDOWSTART and WINDOWSTART-1: | |
595 | * | |
596 | * (XXXXXX1[0]* - 1) AND XXXXXX1[0]* = XXXXXX0[0]* | |
597 | * | |
598 | * The result is zero only if one bit was set. | |
599 | * | |
600 | * (Note: We might have gone through several task switches before | |
601 | * we come back to the current task, so WINDOWBASE might be | |
602 | * different from the time the exception occurred.) | |
603 | */ | |
604 | ||
605 | /* Test WINDOWSTART before and after the exception. | |
606 | * We actually have WMASK, so we only have to test if it is 1 or not. | |
607 | */ | |
608 | ||
609 | l32i a2, a1, PT_WMASK | |
610 | _beqi a2, 1, common_exception_exit # Spilled before exception,jump | |
611 | ||
612 | /* Test WINDOWSTART now. If spilled, do the movsp */ | |
613 | ||
bc5378fc | 614 | rsr a3, windowstart |
5a0015d6 CZ |
615 | addi a0, a3, -1 |
616 | and a3, a3, a0 | |
617 | _bnez a3, common_exception_exit | |
618 | ||
619 | /* Do a movsp (we returned from a call4, so we have at least a0..a7) */ | |
620 | ||
621 | addi a0, a1, -16 | |
622 | l32i a3, a0, 0 | |
623 | l32i a4, a0, 4 | |
624 | s32i a3, a1, PT_SIZE+0 | |
625 | s32i a4, a1, PT_SIZE+4 | |
626 | l32i a3, a0, 8 | |
627 | l32i a4, a0, 12 | |
628 | s32i a3, a1, PT_SIZE+8 | |
629 | s32i a4, a1, PT_SIZE+12 | |
630 | ||
631 | /* Common exception exit. | |
632 | * We restore the special register and the current window frame, and | |
633 | * return from the exception. | |
634 | * | |
635 | * Note: We expect a2 to hold PT_WMASK | |
636 | */ | |
637 | ||
638 | common_exception_exit: | |
639 | ||
c658eac6 CZ |
640 | /* Restore address registers. */ |
641 | ||
5a0015d6 CZ |
642 | _bbsi.l a2, 1, 1f |
643 | l32i a4, a1, PT_AREG4 | |
644 | l32i a5, a1, PT_AREG5 | |
645 | l32i a6, a1, PT_AREG6 | |
646 | l32i a7, a1, PT_AREG7 | |
647 | _bbsi.l a2, 2, 1f | |
648 | l32i a8, a1, PT_AREG8 | |
649 | l32i a9, a1, PT_AREG9 | |
650 | l32i a10, a1, PT_AREG10 | |
651 | l32i a11, a1, PT_AREG11 | |
652 | _bbsi.l a2, 3, 1f | |
653 | l32i a12, a1, PT_AREG12 | |
654 | l32i a13, a1, PT_AREG13 | |
655 | l32i a14, a1, PT_AREG14 | |
656 | l32i a15, a1, PT_AREG15 | |
657 | ||
658 | /* Restore PC, SAR */ | |
659 | ||
660 | 1: l32i a2, a1, PT_PC | |
661 | l32i a3, a1, PT_SAR | |
bc5378fc MF |
662 | wsr a2, epc1 |
663 | wsr a3, sar | |
5a0015d6 CZ |
664 | |
665 | /* Restore LBEG, LEND, LCOUNT */ | |
666 | ||
667 | l32i a2, a1, PT_LBEG | |
668 | l32i a3, a1, PT_LEND | |
bc5378fc | 669 | wsr a2, lbeg |
5a0015d6 | 670 | l32i a2, a1, PT_LCOUNT |
bc5378fc MF |
671 | wsr a3, lend |
672 | wsr a2, lcount | |
5a0015d6 | 673 | |
29c4dfd9 CZ |
674 | /* We control single stepping through the ICOUNTLEVEL register. */ |
675 | ||
676 | l32i a2, a1, PT_ICOUNTLEVEL | |
677 | movi a3, -2 | |
bc5378fc MF |
678 | wsr a2, icountlevel |
679 | wsr a3, icount | |
29c4dfd9 | 680 | |
5a0015d6 CZ |
681 | /* Check if it was double exception. */ |
682 | ||
683 | l32i a0, a1, PT_DEPC | |
684 | l32i a3, a1, PT_AREG3 | |
685 | l32i a2, a1, PT_AREG2 | |
895666a9 | 686 | _bgeui a0, VALID_DOUBLE_EXCEPTION_ADDRESS, 1f |
5a0015d6 CZ |
687 | |
688 | /* Restore a0...a3 and return */ | |
689 | ||
690 | l32i a0, a1, PT_AREG0 | |
691 | l32i a1, a1, PT_AREG1 | |
895666a9 | 692 | rfe |
5a0015d6 | 693 | |
895666a9 | 694 | 1: wsr a0, depc |
5a0015d6 CZ |
695 | l32i a0, a1, PT_AREG0 |
696 | l32i a1, a1, PT_AREG1 | |
895666a9 | 697 | rfde |
5a0015d6 | 698 | |
d1538c46 CZ |
699 | ENDPROC(kernel_exception) |
700 | ||
5a0015d6 CZ |
701 | /* |
702 | * Debug exception handler. | |
703 | * | |
704 | * Currently, we don't support KGDB, so only user application can be debugged. | |
705 | * | |
706 | * When we get here, a0 is trashed and saved to excsave[debuglevel] | |
707 | */ | |
708 | ||
709 | ENTRY(debug_exception) | |
710 | ||
bc5378fc | 711 | rsr a0, SREG_EPS + XCHAL_DEBUGLEVEL |
173d6681 | 712 | bbsi.l a0, PS_EXCM_BIT, 1f # exception mode |
5a0015d6 | 713 | |
bc5378fc | 714 | /* Set EPC1 and EXCCAUSE */ |
5a0015d6 | 715 | |
bc5378fc MF |
716 | wsr a2, depc # save a2 temporarily |
717 | rsr a2, SREG_EPC + XCHAL_DEBUGLEVEL | |
718 | wsr a2, epc1 | |
5a0015d6 CZ |
719 | |
720 | movi a2, EXCCAUSE_MAPPED_DEBUG | |
bc5378fc | 721 | wsr a2, exccause |
5a0015d6 CZ |
722 | |
723 | /* Restore PS to the value before the debug exc but with PS.EXCM set.*/ | |
724 | ||
173d6681 | 725 | movi a2, 1 << PS_EXCM_BIT |
5a0015d6 CZ |
726 | or a2, a0, a2 |
727 | movi a0, debug_exception # restore a3, debug jump vector | |
bc5378fc MF |
728 | wsr a2, ps |
729 | xsr a0, SREG_EXCSAVE + XCHAL_DEBUGLEVEL | |
5a0015d6 CZ |
730 | |
731 | /* Switch to kernel/user stack, restore jump vector, and save a0 */ | |
732 | ||
173d6681 | 733 | bbsi.l a2, PS_UM_BIT, 2f # jump if user mode |
5a0015d6 CZ |
734 | |
735 | addi a2, a1, -16-PT_SIZE # assume kernel stack | |
736 | s32i a0, a2, PT_AREG0 | |
737 | movi a0, 0 | |
738 | s32i a1, a2, PT_AREG1 | |
739 | s32i a0, a2, PT_DEPC # mark it as a regular exception | |
bc5378fc | 740 | xsr a0, depc |
5a0015d6 CZ |
741 | s32i a3, a2, PT_AREG3 |
742 | s32i a0, a2, PT_AREG2 | |
743 | mov a1, a2 | |
744 | j _kernel_exception | |
745 | ||
bc5378fc | 746 | 2: rsr a2, excsave1 |
5a0015d6 CZ |
747 | l32i a2, a2, EXC_TABLE_KSTK # load kernel stack pointer |
748 | s32i a0, a2, PT_AREG0 | |
749 | movi a0, 0 | |
750 | s32i a1, a2, PT_AREG1 | |
751 | s32i a0, a2, PT_DEPC | |
bc5378fc | 752 | xsr a0, depc |
5a0015d6 CZ |
753 | s32i a3, a2, PT_AREG3 |
754 | s32i a0, a2, PT_AREG2 | |
755 | mov a1, a2 | |
756 | j _user_exception | |
757 | ||
758 | /* Debug exception while in exception mode. */ | |
759 | 1: j 1b // FIXME!! | |
760 | ||
d1538c46 | 761 | ENDPROC(debug_exception) |
5a0015d6 CZ |
762 | |
763 | /* | |
764 | * We get here in case of an unrecoverable exception. | |
765 | * The only thing we can do is to be nice and print a panic message. | |
766 | * We only produce a single stack frame for panic, so ??? | |
767 | * | |
768 | * | |
769 | * Entry conditions: | |
770 | * | |
771 | * - a0 contains the caller address; original value saved in excsave1. | |
772 | * - the original a0 contains a valid return address (backtrace) or 0. | |
773 | * - a2 contains a valid stackpointer | |
774 | * | |
775 | * Notes: | |
776 | * | |
777 | * - If the stack pointer could be invalid, the caller has to setup a | |
778 | * dummy stack pointer (e.g. the stack of the init_task) | |
779 | * | |
780 | * - If the return address could be invalid, the caller has to set it | |
781 | * to 0, so the backtrace would stop. | |
782 | * | |
783 | */ | |
784 | .align 4 | |
785 | unrecoverable_text: | |
786 | .ascii "Unrecoverable error in exception handler\0" | |
787 | ||
788 | ENTRY(unrecoverable_exception) | |
789 | ||
790 | movi a0, 1 | |
791 | movi a1, 0 | |
792 | ||
bc5378fc MF |
793 | wsr a0, windowstart |
794 | wsr a1, windowbase | |
5a0015d6 CZ |
795 | rsync |
796 | ||
2d1c645c | 797 | movi a1, (1 << PS_WOE_BIT) | LOCKLEVEL |
bc5378fc | 798 | wsr a1, ps |
5a0015d6 CZ |
799 | rsync |
800 | ||
801 | movi a1, init_task | |
802 | movi a0, 0 | |
803 | addi a1, a1, PT_REGS_OFFSET | |
804 | ||
805 | movi a4, panic | |
806 | movi a6, unrecoverable_text | |
807 | ||
808 | callx4 a4 | |
809 | ||
810 | 1: j 1b | |
811 | ||
d1538c46 | 812 | ENDPROC(unrecoverable_exception) |
5a0015d6 CZ |
813 | |
814 | /* -------------------------- FAST EXCEPTION HANDLERS ----------------------- */ | |
815 | ||
816 | /* | |
817 | * Fast-handler for alloca exceptions | |
818 | * | |
819 | * The ALLOCA handler is entered when user code executes the MOVSP | |
820 | * instruction and the caller's frame is not in the register file. | |
5a0015d6 | 821 | * |
fff96d69 MF |
822 | * This algorithm was taken from the Ross Morley's RTOS Porting Layer: |
823 | * | |
824 | * /home/ross/rtos/porting/XtensaRTOS-PortingLayer-20090507/xtensa_vectors.S | |
825 | * | |
826 | * It leverages the existing window spill/fill routines and their support for | |
827 | * double exceptions. The 'movsp' instruction will only cause an exception if | |
828 | * the next window needs to be loaded. In fact this ALLOCA exception may be | |
829 | * replaced at some point by changing the hardware to do a underflow exception | |
830 | * of the proper size instead. | |
831 | * | |
832 | * This algorithm simply backs out the register changes started by the user | |
833 | * excpetion handler, makes it appear that we have started a window underflow | |
834 | * by rotating the window back and then setting the old window base (OWB) in | |
835 | * the 'ps' register with the rolled back window base. The 'movsp' instruction | |
836 | * will be re-executed and this time since the next window frames is in the | |
837 | * active AR registers it won't cause an exception. | |
838 | * | |
839 | * If the WindowUnderflow code gets a TLB miss the page will get mapped | |
840 | * the the partial windeowUnderflow will be handeled in the double exception | |
841 | * handler. | |
5a0015d6 CZ |
842 | * |
843 | * Entry condition: | |
844 | * | |
845 | * a0: trashed, original value saved on stack (PT_AREG0) | |
846 | * a1: a1 | |
847 | * a2: new stack pointer, original in DEPC | |
99d5040e | 848 | * a3: a3 |
5a0015d6 | 849 | * depc: a2, original value saved on stack (PT_DEPC) |
99d5040e | 850 | * excsave_1: dispatch table |
5a0015d6 CZ |
851 | * |
852 | * PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC | |
853 | * < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception | |
854 | */ | |
855 | ||
5a0015d6 | 856 | ENTRY(fast_alloca) |
fff96d69 MF |
857 | rsr a0, windowbase |
858 | rotw -1 | |
859 | rsr a2, ps | |
860 | extui a3, a2, PS_OWB_SHIFT, PS_OWB_WIDTH | |
861 | xor a3, a3, a4 | |
862 | l32i a4, a6, PT_AREG0 | |
863 | l32i a1, a6, PT_DEPC | |
864 | rsr a6, depc | |
865 | wsr a1, depc | |
866 | slli a3, a3, PS_OWB_SHIFT | |
867 | xor a2, a2, a3 | |
868 | wsr a2, ps | |
869 | rsync | |
5a0015d6 | 870 | |
fff96d69 MF |
871 | _bbci.l a4, 31, 4f |
872 | rotw -1 | |
873 | _bbci.l a8, 30, 8f | |
874 | rotw -1 | |
875 | j _WindowUnderflow12 | |
876 | 8: j _WindowUnderflow8 | |
877 | 4: j _WindowUnderflow4 | |
d1538c46 | 878 | ENDPROC(fast_alloca) |
5a0015d6 CZ |
879 | |
880 | /* | |
881 | * fast system calls. | |
882 | * | |
883 | * WARNING: The kernel doesn't save the entire user context before | |
884 | * handling a fast system call. These functions are small and short, | |
885 | * usually offering some functionality not available to user tasks. | |
886 | * | |
887 | * BE CAREFUL TO PRESERVE THE USER'S CONTEXT. | |
888 | * | |
889 | * Entry condition: | |
890 | * | |
891 | * a0: trashed, original value saved on stack (PT_AREG0) | |
892 | * a1: a1 | |
893 | * a2: new stack pointer, original in DEPC | |
99d5040e | 894 | * a3: a3 |
5a0015d6 | 895 | * depc: a2, original value saved on stack (PT_DEPC) |
99d5040e | 896 | * excsave_1: dispatch table |
5a0015d6 CZ |
897 | */ |
898 | ||
899 | ENTRY(fast_syscall_kernel) | |
900 | ||
901 | /* Skip syscall. */ | |
902 | ||
bc5378fc | 903 | rsr a0, epc1 |
5a0015d6 | 904 | addi a0, a0, 3 |
bc5378fc | 905 | wsr a0, epc1 |
5a0015d6 CZ |
906 | |
907 | l32i a0, a2, PT_DEPC | |
908 | bgeui a0, VALID_DOUBLE_EXCEPTION_ADDRESS, fast_syscall_unrecoverable | |
909 | ||
bc5378fc | 910 | rsr a0, depc # get syscall-nr |
5a0015d6 | 911 | _beqz a0, fast_syscall_spill_registers |
fc4fb2ad | 912 | _beqi a0, __NR_xtensa, fast_syscall_xtensa |
5a0015d6 CZ |
913 | |
914 | j kernel_exception | |
915 | ||
d1538c46 CZ |
916 | ENDPROC(fast_syscall_kernel) |
917 | ||
5a0015d6 CZ |
918 | ENTRY(fast_syscall_user) |
919 | ||
920 | /* Skip syscall. */ | |
921 | ||
bc5378fc | 922 | rsr a0, epc1 |
5a0015d6 | 923 | addi a0, a0, 3 |
bc5378fc | 924 | wsr a0, epc1 |
5a0015d6 CZ |
925 | |
926 | l32i a0, a2, PT_DEPC | |
927 | bgeui a0, VALID_DOUBLE_EXCEPTION_ADDRESS, fast_syscall_unrecoverable | |
928 | ||
bc5378fc | 929 | rsr a0, depc # get syscall-nr |
5a0015d6 | 930 | _beqz a0, fast_syscall_spill_registers |
fc4fb2ad | 931 | _beqi a0, __NR_xtensa, fast_syscall_xtensa |
5a0015d6 CZ |
932 | |
933 | j user_exception | |
934 | ||
d1538c46 CZ |
935 | ENDPROC(fast_syscall_user) |
936 | ||
5a0015d6 CZ |
937 | ENTRY(fast_syscall_unrecoverable) |
938 | ||
c4c4594b | 939 | /* Restore all states. */ |
5a0015d6 | 940 | |
c4c4594b CZ |
941 | l32i a0, a2, PT_AREG0 # restore a0 |
942 | xsr a2, depc # restore a2, depc | |
5a0015d6 | 943 | |
c4c4594b CZ |
944 | wsr a0, excsave1 |
945 | movi a0, unrecoverable_exception | |
946 | callx0 a0 | |
5a0015d6 | 947 | |
d1538c46 | 948 | ENDPROC(fast_syscall_unrecoverable) |
5a0015d6 CZ |
949 | |
950 | /* | |
951 | * sysxtensa syscall handler | |
952 | * | |
fc4fb2ad CZ |
953 | * int sysxtensa (SYS_XTENSA_ATOMIC_SET, ptr, val, unused); |
954 | * int sysxtensa (SYS_XTENSA_ATOMIC_ADD, ptr, val, unused); | |
955 | * int sysxtensa (SYS_XTENSA_ATOMIC_EXG_ADD, ptr, val, unused); | |
956 | * int sysxtensa (SYS_XTENSA_ATOMIC_CMP_SWP, ptr, oldval, newval); | |
957 | * a2 a6 a3 a4 a5 | |
5a0015d6 CZ |
958 | * |
959 | * Entry condition: | |
960 | * | |
fc4fb2ad | 961 | * a0: a2 (syscall-nr), original value saved on stack (PT_AREG0) |
5a0015d6 | 962 | * a1: a1 |
fc4fb2ad | 963 | * a2: new stack pointer, original in a0 and DEPC |
99d5040e | 964 | * a3: a3 |
fc4fb2ad | 965 | * a4..a15: unchanged |
5a0015d6 | 966 | * depc: a2, original value saved on stack (PT_DEPC) |
99d5040e | 967 | * excsave_1: dispatch table |
5a0015d6 CZ |
968 | * |
969 | * PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC | |
970 | * < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception | |
971 | * | |
972 | * Note: we don't have to save a2; a2 holds the return value | |
973 | * | |
974 | * We use the two macros TRY and CATCH: | |
975 | * | |
976 | * TRY adds an entry to the __ex_table fixup table for the immediately | |
977 | * following instruction. | |
978 | * | |
25985edc | 979 | * CATCH catches any exception that occurred at one of the preceding TRY |
5a0015d6 CZ |
980 | * statements and continues from there |
981 | * | |
982 | * Usage TRY l32i a0, a1, 0 | |
983 | * <other code> | |
984 | * done: rfe | |
985 | * CATCH <set return code> | |
986 | * j done | |
987 | */ | |
988 | ||
989 | #define TRY \ | |
990 | .section __ex_table, "a"; \ | |
991 | .word 66f, 67f; \ | |
992 | .text; \ | |
993 | 66: | |
994 | ||
995 | #define CATCH \ | |
996 | 67: | |
997 | ||
fc4fb2ad | 998 | ENTRY(fast_syscall_xtensa) |
5a0015d6 | 999 | |
fc4fb2ad | 1000 | s32i a7, a2, PT_AREG7 # we need an additional register |
5a0015d6 | 1001 | movi a7, 4 # sizeof(unsigned int) |
fc4fb2ad | 1002 | access_ok a3, a7, a0, a2, .Leac # a0: scratch reg, a2: sp |
5a0015d6 | 1003 | |
fc4fb2ad CZ |
1004 | addi a6, a6, -1 # assuming SYS_XTENSA_ATOMIC_SET = 1 |
1005 | _bgeui a6, SYS_XTENSA_COUNT - 1, .Lill | |
1006 | _bnei a6, SYS_XTENSA_ATOMIC_CMP_SWP - 1, .Lnswp | |
5a0015d6 | 1007 | |
fc4fb2ad | 1008 | /* Fall through for ATOMIC_CMP_SWP. */ |
5a0015d6 CZ |
1009 | |
1010 | .Lswp: /* Atomic compare and swap */ | |
1011 | ||
fc4fb2ad CZ |
1012 | TRY l32i a0, a3, 0 # read old value |
1013 | bne a0, a4, 1f # same as old value? jump | |
1014 | TRY s32i a5, a3, 0 # different, modify value | |
1015 | l32i a7, a2, PT_AREG7 # restore a7 | |
1016 | l32i a0, a2, PT_AREG0 # restore a0 | |
1017 | movi a2, 1 # and return 1 | |
1018 | addi a6, a6, 1 # restore a6 (really necessary?) | |
1019 | rfe | |
5a0015d6 | 1020 | |
fc4fb2ad CZ |
1021 | 1: l32i a7, a2, PT_AREG7 # restore a7 |
1022 | l32i a0, a2, PT_AREG0 # restore a0 | |
1023 | movi a2, 0 # return 0 (note that we cannot set | |
1024 | addi a6, a6, 1 # restore a6 (really necessary?) | |
1025 | rfe | |
5a0015d6 | 1026 | |
fc4fb2ad | 1027 | .Lnswp: /* Atomic set, add, and exg_add. */ |
5a0015d6 | 1028 | |
fc4fb2ad CZ |
1029 | TRY l32i a7, a3, 0 # orig |
1030 | add a0, a4, a7 # + arg | |
1031 | moveqz a0, a4, a6 # set | |
1032 | TRY s32i a0, a3, 0 # write new value | |
5a0015d6 | 1033 | |
fc4fb2ad | 1034 | mov a0, a2 |
5a0015d6 | 1035 | mov a2, a7 |
fc4fb2ad CZ |
1036 | l32i a7, a0, PT_AREG7 # restore a7 |
1037 | l32i a0, a0, PT_AREG0 # restore a0 | |
1038 | addi a6, a6, 1 # restore a6 (really necessary?) | |
5a0015d6 CZ |
1039 | rfe |
1040 | ||
1041 | CATCH | |
fc4fb2ad CZ |
1042 | .Leac: l32i a7, a2, PT_AREG7 # restore a7 |
1043 | l32i a0, a2, PT_AREG0 # restore a0 | |
1044 | movi a2, -EFAULT | |
1045 | rfe | |
1046 | ||
1047 | .Lill: l32i a7, a2, PT_AREG0 # restore a7 | |
1048 | l32i a0, a2, PT_AREG0 # restore a0 | |
1049 | movi a2, -EINVAL | |
1050 | rfe | |
1051 | ||
d1538c46 | 1052 | ENDPROC(fast_syscall_xtensa) |
5a0015d6 CZ |
1053 | |
1054 | ||
1055 | /* fast_syscall_spill_registers. | |
1056 | * | |
1057 | * Entry condition: | |
1058 | * | |
1059 | * a0: trashed, original value saved on stack (PT_AREG0) | |
1060 | * a1: a1 | |
1061 | * a2: new stack pointer, original in DEPC | |
99d5040e | 1062 | * a3: a3 |
5a0015d6 | 1063 | * depc: a2, original value saved on stack (PT_DEPC) |
99d5040e | 1064 | * excsave_1: dispatch table |
5a0015d6 CZ |
1065 | * |
1066 | * Note: We assume the stack pointer is EXC_TABLE_KSTK in the fixup handler. | |
5a0015d6 CZ |
1067 | */ |
1068 | ||
1069 | ENTRY(fast_syscall_spill_registers) | |
1070 | ||
1071 | /* Register a FIXUP handler (pass current wb as a parameter) */ | |
1072 | ||
99d5040e | 1073 | xsr a3, excsave1 |
5a0015d6 CZ |
1074 | movi a0, fast_syscall_spill_registers_fixup |
1075 | s32i a0, a3, EXC_TABLE_FIXUP | |
bc5378fc | 1076 | rsr a0, windowbase |
5a0015d6 | 1077 | s32i a0, a3, EXC_TABLE_PARAM |
99d5040e | 1078 | xsr a3, excsave1 # restore a3 and excsave_1 |
5a0015d6 | 1079 | |
99d5040e | 1080 | /* Save a3, a4 and SAR on stack. */ |
5a0015d6 | 1081 | |
bc5378fc | 1082 | rsr a0, sar |
5a0015d6 | 1083 | s32i a3, a2, PT_AREG3 |
6b5a1f74 | 1084 | s32i a0, a2, PT_SAR |
5a0015d6 | 1085 | |
6b5a1f74 | 1086 | /* The spill routine might clobber a4, a7, a8, a11, a12, and a15. */ |
5a0015d6 | 1087 | |
6b5a1f74 | 1088 | s32i a4, a2, PT_AREG4 |
c658eac6 | 1089 | s32i a7, a2, PT_AREG7 |
6b5a1f74 | 1090 | s32i a8, a2, PT_AREG8 |
c658eac6 | 1091 | s32i a11, a2, PT_AREG11 |
6b5a1f74 | 1092 | s32i a12, a2, PT_AREG12 |
c658eac6 | 1093 | s32i a15, a2, PT_AREG15 |
5a0015d6 | 1094 | |
6b5a1f74 CZ |
1095 | /* |
1096 | * Rotate ws so that the current windowbase is at bit 0. | |
1097 | * Assume ws = xxxwww1yy (www1 current window frame). | |
1098 | * Rotate ws right so that a4 = yyxxxwww1. | |
1099 | */ | |
1100 | ||
1101 | rsr a0, windowbase | |
1102 | rsr a3, windowstart # a3 = xxxwww1yy | |
1103 | ssr a0 # holds WB | |
1104 | slli a0, a3, WSBITS | |
1105 | or a3, a3, a0 # a3 = xxxwww1yyxxxwww1yy | |
1106 | srl a3, a3 # a3 = 00xxxwww1yyxxxwww1 | |
1107 | ||
1108 | /* We are done if there are no more than the current register frame. */ | |
1109 | ||
1110 | extui a3, a3, 1, WSBITS-1 # a3 = 0yyxxxwww | |
1111 | movi a0, (1 << (WSBITS-1)) | |
1112 | _beqz a3, .Lnospill # only one active frame? jump | |
1113 | ||
1114 | /* We want 1 at the top, so that we return to the current windowbase */ | |
1115 | ||
1116 | or a3, a3, a0 # 1yyxxxwww | |
1117 | ||
1118 | /* Skip empty frames - get 'oldest' WINDOWSTART-bit. */ | |
1119 | ||
1120 | wsr a3, windowstart # save shifted windowstart | |
1121 | neg a0, a3 | |
1122 | and a3, a0, a3 # first bit set from right: 000010000 | |
1123 | ||
1124 | ffs_ws a0, a3 # a0: shifts to skip empty frames | |
1125 | movi a3, WSBITS | |
1126 | sub a0, a3, a0 # WSBITS-a0:number of 0-bits from right | |
1127 | ssr a0 # save in SAR for later. | |
1128 | ||
1129 | rsr a3, windowbase | |
1130 | add a3, a3, a0 | |
1131 | wsr a3, windowbase | |
1132 | rsync | |
1133 | ||
1134 | rsr a3, windowstart | |
1135 | srl a3, a3 # shift windowstart | |
1136 | ||
1137 | /* WB is now just one frame below the oldest frame in the register | |
1138 | window. WS is shifted so the oldest frame is in bit 0, thus, WB | |
1139 | and WS differ by one 4-register frame. */ | |
1140 | ||
1141 | /* Save frames. Depending what call was used (call4, call8, call12), | |
1142 | * we have to save 4,8. or 12 registers. | |
1143 | */ | |
1144 | ||
1145 | ||
1146 | .Lloop: _bbsi.l a3, 1, .Lc4 | |
1147 | _bbci.l a3, 2, .Lc12 | |
1148 | ||
1149 | .Lc8: s32e a4, a13, -16 | |
1150 | l32e a4, a5, -12 | |
1151 | s32e a8, a4, -32 | |
1152 | s32e a5, a13, -12 | |
1153 | s32e a6, a13, -8 | |
1154 | s32e a7, a13, -4 | |
1155 | s32e a9, a4, -28 | |
1156 | s32e a10, a4, -24 | |
1157 | s32e a11, a4, -20 | |
1158 | srli a11, a3, 2 # shift windowbase by 2 | |
1159 | rotw 2 | |
1160 | _bnei a3, 1, .Lloop | |
1161 | j .Lexit | |
1162 | ||
1163 | .Lc4: s32e a4, a9, -16 | |
1164 | s32e a5, a9, -12 | |
1165 | s32e a6, a9, -8 | |
1166 | s32e a7, a9, -4 | |
1167 | ||
1168 | srli a7, a3, 1 | |
1169 | rotw 1 | |
1170 | _bnei a3, 1, .Lloop | |
1171 | j .Lexit | |
1172 | ||
1173 | .Lc12: _bbci.l a3, 3, .Linvalid_mask # bit 2 shouldn't be zero! | |
1174 | ||
1175 | /* 12-register frame (call12) */ | |
1176 | ||
1177 | l32e a0, a5, -12 | |
1178 | s32e a8, a0, -48 | |
1179 | mov a8, a0 | |
1180 | ||
1181 | s32e a9, a8, -44 | |
1182 | s32e a10, a8, -40 | |
1183 | s32e a11, a8, -36 | |
1184 | s32e a12, a8, -32 | |
1185 | s32e a13, a8, -28 | |
1186 | s32e a14, a8, -24 | |
1187 | s32e a15, a8, -20 | |
1188 | srli a15, a3, 3 | |
1189 | ||
1190 | /* The stack pointer for a4..a7 is out of reach, so we rotate the | |
1191 | * window, grab the stackpointer, and rotate back. | |
1192 | * Alternatively, we could also use the following approach, but that | |
1193 | * makes the fixup routine much more complicated: | |
1194 | * rotw 1 | |
1195 | * s32e a0, a13, -16 | |
1196 | * ... | |
1197 | * rotw 2 | |
1198 | */ | |
1199 | ||
1200 | rotw 1 | |
1201 | mov a4, a13 | |
1202 | rotw -1 | |
1203 | ||
1204 | s32e a4, a8, -16 | |
1205 | s32e a5, a8, -12 | |
1206 | s32e a6, a8, -8 | |
1207 | s32e a7, a8, -4 | |
1208 | ||
1209 | rotw 3 | |
1210 | ||
1211 | _beqi a3, 1, .Lexit | |
1212 | j .Lloop | |
1213 | ||
1214 | .Lexit: | |
1215 | ||
1216 | /* Done. Do the final rotation and set WS */ | |
1217 | ||
1218 | rotw 1 | |
1219 | rsr a3, windowbase | |
1220 | ssl a3 | |
1221 | movi a3, 1 | |
1222 | sll a3, a3 | |
1223 | wsr a3, windowstart | |
1224 | .Lnospill: | |
5a0015d6 CZ |
1225 | |
1226 | /* Advance PC, restore registers and SAR, and return from exception. */ | |
1227 | ||
6b5a1f74 | 1228 | l32i a3, a2, PT_SAR |
5a0015d6 | 1229 | l32i a0, a2, PT_AREG0 |
bc5378fc | 1230 | wsr a3, sar |
5a0015d6 CZ |
1231 | l32i a3, a2, PT_AREG3 |
1232 | ||
1233 | /* Restore clobbered registers. */ | |
1234 | ||
6b5a1f74 | 1235 | l32i a4, a2, PT_AREG4 |
c658eac6 | 1236 | l32i a7, a2, PT_AREG7 |
6b5a1f74 | 1237 | l32i a8, a2, PT_AREG8 |
c658eac6 | 1238 | l32i a11, a2, PT_AREG11 |
6b5a1f74 | 1239 | l32i a12, a2, PT_AREG12 |
c658eac6 | 1240 | l32i a15, a2, PT_AREG15 |
5a0015d6 CZ |
1241 | |
1242 | movi a2, 0 | |
1243 | rfe | |
1244 | ||
6b5a1f74 CZ |
1245 | .Linvalid_mask: |
1246 | ||
1247 | /* We get here because of an unrecoverable error in the window | |
1248 | * registers, so set up a dummy frame and kill the user application. | |
1249 | * Note: We assume EXC_TABLE_KSTK contains a valid stack pointer. | |
1250 | */ | |
1251 | ||
1252 | movi a0, 1 | |
1253 | movi a1, 0 | |
1254 | ||
1255 | wsr a0, windowstart | |
1256 | wsr a1, windowbase | |
1257 | rsync | |
1258 | ||
1259 | movi a0, 0 | |
1260 | ||
1261 | rsr a3, excsave1 | |
1262 | l32i a1, a3, EXC_TABLE_KSTK | |
1263 | ||
1264 | movi a4, (1 << PS_WOE_BIT) | LOCKLEVEL | |
1265 | wsr a4, ps | |
1266 | rsync | |
1267 | ||
1268 | movi a6, SIGSEGV | |
1269 | movi a4, do_exit | |
1270 | callx4 a4 | |
1271 | ||
1272 | /* shouldn't return, so panic */ | |
1273 | ||
1274 | wsr a0, excsave1 | |
1275 | movi a0, unrecoverable_exception | |
1276 | callx0 a0 # should not return | |
1277 | 1: j 1b | |
1278 | ||
1279 | ||
d1538c46 CZ |
1280 | ENDPROC(fast_syscall_spill_registers) |
1281 | ||
5a0015d6 CZ |
1282 | /* Fixup handler. |
1283 | * | |
1284 | * We get here if the spill routine causes an exception, e.g. tlb miss. | |
1285 | * We basically restore WINDOWBASE and WINDOWSTART to the condition when | |
1286 | * we entered the spill routine and jump to the user exception handler. | |
1287 | * | |
3251f1e2 MF |
1288 | * Note that we only need to restore the bits in windowstart that have not |
1289 | * been spilled yet by the _spill_register routine. Luckily, a3 contains a | |
1290 | * rotated windowstart with only those bits set for frames that haven't been | |
1291 | * spilled yet. Because a3 is rotated such that bit 0 represents the register | |
1292 | * frame for the current windowbase - 1, we need to rotate a3 left by the | |
1293 | * value of the current windowbase + 1 and move it to windowstart. | |
1294 | * | |
5a0015d6 CZ |
1295 | * a0: value of depc, original value in depc |
1296 | * a2: trashed, original value in EXC_TABLE_DOUBLE_SAVE | |
1297 | * a3: exctable, original value in excsave1 | |
1298 | */ | |
1299 | ||
244066f4 | 1300 | ENTRY(fast_syscall_spill_registers_fixup) |
5a0015d6 | 1301 | |
bc5378fc MF |
1302 | rsr a2, windowbase # get current windowbase (a2 is saved) |
1303 | xsr a0, depc # restore depc and a0 | |
5a0015d6 CZ |
1304 | ssl a2 # set shift (32 - WB) |
1305 | ||
1306 | /* We need to make sure the current registers (a0-a3) are preserved. | |
1307 | * To do this, we simply set the bit for the current window frame | |
1308 | * in WS, so that the exception handlers save them to the task stack. | |
3251f1e2 MF |
1309 | * |
1310 | * Note: we use a3 to set the windowbase, so we take a special care | |
1311 | * of it, saving it in the original _spill_registers frame across | |
1312 | * the exception handler call. | |
5a0015d6 CZ |
1313 | */ |
1314 | ||
99d5040e | 1315 | xsr a3, excsave1 # get spill-mask |
244066f4 | 1316 | slli a3, a3, 1 # shift left by one |
3251f1e2 | 1317 | addi a3, a3, 1 # set the bit for the current window frame |
5a0015d6 | 1318 | |
244066f4 MF |
1319 | slli a2, a3, 32-WSBITS |
1320 | src a2, a3, a2 # a2 = xxwww1yyxxxwww1yy...... | |
bc5378fc | 1321 | wsr a2, windowstart # set corrected windowstart |
5a0015d6 | 1322 | |
244066f4 MF |
1323 | srli a3, a3, 1 |
1324 | rsr a2, excsave1 | |
1325 | l32i a2, a2, EXC_TABLE_DOUBLE_SAVE # restore a2 | |
1326 | xsr a2, excsave1 | |
1327 | s32i a3, a2, EXC_TABLE_DOUBLE_SAVE # save a3 | |
1328 | l32i a3, a2, EXC_TABLE_PARAM # original WB (in user task) | |
1329 | xsr a2, excsave1 | |
5a0015d6 CZ |
1330 | |
1331 | /* Return to the original (user task) WINDOWBASE. | |
1332 | * We leave the following frame behind: | |
1333 | * a0, a1, a2 same | |
244066f4 | 1334 | * a3: trashed (saved in EXC_TABLE_DOUBLE_SAVE) |
5a0015d6 | 1335 | * depc: depc (we have to return to that address) |
244066f4 | 1336 | * excsave_1: exctable |
5a0015d6 CZ |
1337 | */ |
1338 | ||
bc5378fc | 1339 | wsr a3, windowbase |
5a0015d6 CZ |
1340 | rsync |
1341 | ||
1342 | /* We are now in the original frame when we entered _spill_registers: | |
1343 | * a0: return address | |
1344 | * a1: used, stack pointer | |
1345 | * a2: kernel stack pointer | |
244066f4 | 1346 | * a3: available |
5a0015d6 | 1347 | * depc: exception address |
244066f4 | 1348 | * excsave: exctable |
5a0015d6 CZ |
1349 | * Note: This frame might be the same as above. |
1350 | */ | |
1351 | ||
5a0015d6 CZ |
1352 | /* Setup stack pointer. */ |
1353 | ||
1354 | addi a2, a2, -PT_USER_SIZE | |
1355 | s32i a0, a2, PT_AREG0 | |
1356 | ||
1357 | /* Make sure we return to this fixup handler. */ | |
1358 | ||
1359 | movi a3, fast_syscall_spill_registers_fixup_return | |
1360 | s32i a3, a2, PT_DEPC # setup depc | |
1361 | ||
1362 | /* Jump to the exception handler. */ | |
1363 | ||
99d5040e | 1364 | rsr a3, excsave1 |
bc5378fc | 1365 | rsr a0, exccause |
c4c4594b CZ |
1366 | addx4 a0, a0, a3 # find entry in table |
1367 | l32i a0, a0, EXC_TABLE_FAST_USER # load handler | |
244066f4 | 1368 | l32i a3, a3, EXC_TABLE_DOUBLE_SAVE |
c4c4594b | 1369 | jx a0 |
5a0015d6 | 1370 | |
244066f4 MF |
1371 | ENDPROC(fast_syscall_spill_registers_fixup) |
1372 | ||
1373 | ENTRY(fast_syscall_spill_registers_fixup_return) | |
5a0015d6 CZ |
1374 | |
1375 | /* When we return here, all registers have been restored (a2: DEPC) */ | |
1376 | ||
bc5378fc | 1377 | wsr a2, depc # exception address |
5a0015d6 CZ |
1378 | |
1379 | /* Restore fixup handler. */ | |
1380 | ||
244066f4 MF |
1381 | rsr a2, excsave1 |
1382 | s32i a3, a2, EXC_TABLE_DOUBLE_SAVE | |
1383 | movi a3, fast_syscall_spill_registers_fixup | |
1384 | s32i a3, a2, EXC_TABLE_FIXUP | |
1385 | rsr a3, windowbase | |
1386 | s32i a3, a2, EXC_TABLE_PARAM | |
1387 | l32i a2, a2, EXC_TABLE_KSTK | |
5a0015d6 | 1388 | |
5a0015d6 CZ |
1389 | /* Load WB at the time the exception occurred. */ |
1390 | ||
bc5378fc | 1391 | rsr a3, sar # WB is still in SAR |
5a0015d6 | 1392 | neg a3, a3 |
bc5378fc | 1393 | wsr a3, windowbase |
5a0015d6 CZ |
1394 | rsync |
1395 | ||
244066f4 MF |
1396 | rsr a3, excsave1 |
1397 | l32i a3, a3, EXC_TABLE_DOUBLE_SAVE | |
1398 | ||
5a0015d6 CZ |
1399 | rfde |
1400 | ||
244066f4 | 1401 | ENDPROC(fast_syscall_spill_registers_fixup_return) |
5a0015d6 | 1402 | |
e5083a63 | 1403 | #ifdef CONFIG_MMU |
5a0015d6 CZ |
1404 | /* |
1405 | * We should never get here. Bail out! | |
1406 | */ | |
1407 | ||
1408 | ENTRY(fast_second_level_miss_double_kernel) | |
1409 | ||
1410 | 1: movi a0, unrecoverable_exception | |
1411 | callx0 a0 # should not return | |
1412 | 1: j 1b | |
1413 | ||
d1538c46 CZ |
1414 | ENDPROC(fast_second_level_miss_double_kernel) |
1415 | ||
5a0015d6 CZ |
1416 | /* First-level entry handler for user, kernel, and double 2nd-level |
1417 | * TLB miss exceptions. Note that for now, user and kernel miss | |
1418 | * exceptions share the same entry point and are handled identically. | |
1419 | * | |
1420 | * An old, less-efficient C version of this function used to exist. | |
1421 | * We include it below, interleaved as comments, for reference. | |
1422 | * | |
1423 | * Entry condition: | |
1424 | * | |
1425 | * a0: trashed, original value saved on stack (PT_AREG0) | |
1426 | * a1: a1 | |
1427 | * a2: new stack pointer, original in DEPC | |
99d5040e | 1428 | * a3: a3 |
5a0015d6 | 1429 | * depc: a2, original value saved on stack (PT_DEPC) |
99d5040e | 1430 | * excsave_1: dispatch table |
5a0015d6 CZ |
1431 | * |
1432 | * PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC | |
1433 | * < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception | |
1434 | */ | |
1435 | ||
1436 | ENTRY(fast_second_level_miss) | |
1437 | ||
99d5040e | 1438 | /* Save a1 and a3. Note: we don't expect a double exception. */ |
5a0015d6 CZ |
1439 | |
1440 | s32i a1, a2, PT_AREG1 | |
99d5040e | 1441 | s32i a3, a2, PT_AREG3 |
5a0015d6 CZ |
1442 | |
1443 | /* We need to map the page of PTEs for the user task. Find | |
1444 | * the pointer to that page. Also, it's possible for tsk->mm | |
1445 | * to be NULL while tsk->active_mm is nonzero if we faulted on | |
1446 | * a vmalloc address. In that rare case, we must use | |
1447 | * active_mm instead to avoid a fault in this handler. See | |
1448 | * | |
1449 | * http://mail.nl.linux.org/linux-mm/2002-08/msg00258.html | |
1450 | * (or search Internet on "mm vs. active_mm") | |
1451 | * | |
1452 | * if (!mm) | |
1453 | * mm = tsk->active_mm; | |
1454 | * pgd = pgd_offset (mm, regs->excvaddr); | |
1455 | * pmd = pmd_offset (pgd, regs->excvaddr); | |
1456 | * pmdval = *pmd; | |
1457 | */ | |
1458 | ||
1459 | GET_CURRENT(a1,a2) | |
1460 | l32i a0, a1, TASK_MM # tsk->mm | |
1461 | beqz a0, 9f | |
1462 | ||
bc5378fc | 1463 | 8: rsr a3, excvaddr # fault address |
01858d1b | 1464 | _PGD_OFFSET(a0, a3, a1) |
5a0015d6 | 1465 | l32i a0, a0, 0 # read pmdval |
5a0015d6 CZ |
1466 | beqz a0, 2f |
1467 | ||
1468 | /* Read ptevaddr and convert to top of page-table page. | |
1469 | * | |
1470 | * vpnval = read_ptevaddr_register() & PAGE_MASK; | |
1471 | * vpnval += DTLB_WAY_PGTABLE; | |
1472 | * pteval = mk_pte (virt_to_page(pmd_val(pmdval)), PAGE_KERNEL); | |
1473 | * write_dtlb_entry (pteval, vpnval); | |
1474 | * | |
1475 | * The messy computation for 'pteval' above really simplifies | |
1476 | * into the following: | |
1477 | * | |
6656920b | 1478 | * pteval = ((pmdval - PAGE_OFFSET) & PAGE_MASK) | PAGE_DIRECTORY |
5a0015d6 CZ |
1479 | */ |
1480 | ||
39070cb8 | 1481 | movi a1, (-PAGE_OFFSET) & 0xffffffff |
5a0015d6 CZ |
1482 | add a0, a0, a1 # pmdval - PAGE_OFFSET |
1483 | extui a1, a0, 0, PAGE_SHIFT # ... & PAGE_MASK | |
1484 | xor a0, a0, a1 | |
1485 | ||
01858d1b | 1486 | movi a1, _PAGE_DIRECTORY |
5a0015d6 CZ |
1487 | or a0, a0, a1 # ... | PAGE_DIRECTORY |
1488 | ||
01858d1b | 1489 | /* |
6656920b | 1490 | * We utilize all three wired-ways (7-9) to hold pmd translations. |
01858d1b CZ |
1491 | * Memory regions are mapped to the DTLBs according to bits 28 and 29. |
1492 | * This allows to map the three most common regions to three different | |
1493 | * DTLBs: | |
1494 | * 0,1 -> way 7 program (0040.0000) and virtual (c000.0000) | |
1495 | * 2 -> way 8 shared libaries (2000.0000) | |
1496 | * 3 -> way 0 stack (3000.0000) | |
1497 | */ | |
1498 | ||
1499 | extui a3, a3, 28, 2 # addr. bit 28 and 29 0,1,2,3 | |
bc5378fc | 1500 | rsr a1, ptevaddr |
01858d1b | 1501 | addx2 a3, a3, a3 # -> 0,3,6,9 |
5a0015d6 | 1502 | srli a1, a1, PAGE_SHIFT |
01858d1b | 1503 | extui a3, a3, 2, 2 # -> 0,0,1,2 |
5a0015d6 | 1504 | slli a1, a1, PAGE_SHIFT # ptevaddr & PAGE_MASK |
01858d1b CZ |
1505 | addi a3, a3, DTLB_WAY_PGD |
1506 | add a1, a1, a3 # ... + way_number | |
5a0015d6 | 1507 | |
01858d1b | 1508 | 3: wdtlb a0, a1 |
5a0015d6 CZ |
1509 | dsync |
1510 | ||
1511 | /* Exit critical section. */ | |
1512 | ||
99d5040e | 1513 | 4: rsr a3, excsave1 |
5a0015d6 CZ |
1514 | movi a0, 0 |
1515 | s32i a0, a3, EXC_TABLE_FIXUP | |
1516 | ||
1517 | /* Restore the working registers, and return. */ | |
1518 | ||
1519 | l32i a0, a2, PT_AREG0 | |
1520 | l32i a1, a2, PT_AREG1 | |
99d5040e | 1521 | l32i a3, a2, PT_AREG3 |
5a0015d6 | 1522 | l32i a2, a2, PT_DEPC |
5a0015d6 CZ |
1523 | |
1524 | bgeui a2, VALID_DOUBLE_EXCEPTION_ADDRESS, 1f | |
1525 | ||
1526 | /* Restore excsave1 and return. */ | |
1527 | ||
bc5378fc | 1528 | rsr a2, depc |
5a0015d6 CZ |
1529 | rfe |
1530 | ||
1531 | /* Return from double exception. */ | |
1532 | ||
bc5378fc | 1533 | 1: xsr a2, depc |
5a0015d6 CZ |
1534 | esync |
1535 | rfde | |
1536 | ||
1537 | 9: l32i a0, a1, TASK_ACTIVE_MM # unlikely case mm == 0 | |
1538 | j 8b | |
1539 | ||
6656920b CZ |
1540 | #if (DCACHE_WAY_SIZE > PAGE_SIZE) |
1541 | ||
1542 | 2: /* Special case for cache aliasing. | |
1543 | * We (should) only get here if a clear_user_page, copy_user_page | |
1544 | * or the aliased cache flush functions got preemptively interrupted | |
1545 | * by another task. Re-establish temporary mapping to the | |
1546 | * TLBTEMP_BASE areas. | |
1547 | */ | |
1548 | ||
1549 | /* We shouldn't be in a double exception */ | |
1550 | ||
1551 | l32i a0, a2, PT_DEPC | |
1552 | bgeui a0, VALID_DOUBLE_EXCEPTION_ADDRESS, 2f | |
1553 | ||
1554 | /* Make sure the exception originated in the special functions */ | |
1555 | ||
1556 | movi a0, __tlbtemp_mapping_start | |
bc5378fc | 1557 | rsr a3, epc1 |
6656920b CZ |
1558 | bltu a3, a0, 2f |
1559 | movi a0, __tlbtemp_mapping_end | |
1560 | bgeu a3, a0, 2f | |
1561 | ||
1562 | /* Check if excvaddr was in one of the TLBTEMP_BASE areas. */ | |
1563 | ||
1564 | movi a3, TLBTEMP_BASE_1 | |
bc5378fc | 1565 | rsr a0, excvaddr |
6656920b CZ |
1566 | bltu a0, a3, 2f |
1567 | ||
1568 | addi a1, a0, -(2 << (DCACHE_ALIAS_ORDER + PAGE_SHIFT)) | |
1569 | bgeu a1, a3, 2f | |
1570 | ||
1571 | /* Check if we have to restore an ITLB mapping. */ | |
1572 | ||
1573 | movi a1, __tlbtemp_mapping_itlb | |
bc5378fc | 1574 | rsr a3, epc1 |
6656920b CZ |
1575 | sub a3, a3, a1 |
1576 | ||
1577 | /* Calculate VPN */ | |
1578 | ||
1579 | movi a1, PAGE_MASK | |
1580 | and a1, a1, a0 | |
1581 | ||
1582 | /* Jump for ITLB entry */ | |
1583 | ||
1584 | bgez a3, 1f | |
1585 | ||
1586 | /* We can use up to two TLBTEMP areas, one for src and one for dst. */ | |
1587 | ||
1588 | extui a3, a0, PAGE_SHIFT + DCACHE_ALIAS_ORDER, 1 | |
1589 | add a1, a3, a1 | |
1590 | ||
1591 | /* PPN is in a6 for the first TLBTEMP area and in a7 for the second. */ | |
1592 | ||
1593 | mov a0, a6 | |
1594 | movnez a0, a7, a3 | |
1595 | j 3b | |
1596 | ||
1597 | /* ITLB entry. We only use dst in a6. */ | |
1598 | ||
1599 | 1: witlb a6, a1 | |
1600 | isync | |
1601 | j 4b | |
1602 | ||
1603 | ||
1604 | #endif // DCACHE_WAY_SIZE > PAGE_SIZE | |
1605 | ||
1606 | ||
5a0015d6 CZ |
1607 | 2: /* Invalid PGD, default exception handling */ |
1608 | ||
bc5378fc | 1609 | rsr a1, depc |
5a0015d6 | 1610 | s32i a1, a2, PT_AREG2 |
5a0015d6 CZ |
1611 | mov a1, a2 |
1612 | ||
bc5378fc | 1613 | rsr a2, ps |
173d6681 | 1614 | bbsi.l a2, PS_UM_BIT, 1f |
5a0015d6 CZ |
1615 | j _kernel_exception |
1616 | 1: j _user_exception | |
1617 | ||
d1538c46 | 1618 | ENDPROC(fast_second_level_miss) |
5a0015d6 CZ |
1619 | |
1620 | /* | |
1621 | * StoreProhibitedException | |
1622 | * | |
1623 | * Update the pte and invalidate the itlb mapping for this pte. | |
1624 | * | |
1625 | * Entry condition: | |
1626 | * | |
1627 | * a0: trashed, original value saved on stack (PT_AREG0) | |
1628 | * a1: a1 | |
1629 | * a2: new stack pointer, original in DEPC | |
99d5040e | 1630 | * a3: a3 |
5a0015d6 | 1631 | * depc: a2, original value saved on stack (PT_DEPC) |
99d5040e | 1632 | * excsave_1: dispatch table |
5a0015d6 CZ |
1633 | * |
1634 | * PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC | |
1635 | * < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception | |
1636 | */ | |
1637 | ||
1638 | ENTRY(fast_store_prohibited) | |
1639 | ||
99d5040e | 1640 | /* Save a1 and a3. */ |
5a0015d6 CZ |
1641 | |
1642 | s32i a1, a2, PT_AREG1 | |
99d5040e | 1643 | s32i a3, a2, PT_AREG3 |
5a0015d6 CZ |
1644 | |
1645 | GET_CURRENT(a1,a2) | |
1646 | l32i a0, a1, TASK_MM # tsk->mm | |
1647 | beqz a0, 9f | |
1648 | ||
bc5378fc | 1649 | 8: rsr a1, excvaddr # fault address |
99d5040e | 1650 | _PGD_OFFSET(a0, a1, a3) |
5a0015d6 | 1651 | l32i a0, a0, 0 |
5a0015d6 CZ |
1652 | beqz a0, 2f |
1653 | ||
51fc41a9 MF |
1654 | /* |
1655 | * Note that we test _PAGE_WRITABLE_BIT only if PTE is present | |
1656 | * and is not PAGE_NONE. See pgtable.h for possible PTE layouts. | |
1657 | */ | |
01858d1b | 1658 | |
99d5040e MF |
1659 | _PTE_OFFSET(a0, a1, a3) |
1660 | l32i a3, a0, 0 # read pteval | |
51fc41a9 | 1661 | movi a1, _PAGE_CA_INVALID |
99d5040e MF |
1662 | ball a3, a1, 2f |
1663 | bbci.l a3, _PAGE_WRITABLE_BIT, 2f | |
5a0015d6 | 1664 | |
01858d1b | 1665 | movi a1, _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_HW_WRITE |
99d5040e | 1666 | or a3, a3, a1 |
bc5378fc | 1667 | rsr a1, excvaddr |
99d5040e | 1668 | s32i a3, a0, 0 |
5a0015d6 CZ |
1669 | |
1670 | /* We need to flush the cache if we have page coloring. */ | |
1671 | #if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK | |
1672 | dhwb a0, 0 | |
1673 | #endif | |
1674 | pdtlb a0, a1 | |
99d5040e | 1675 | wdtlb a3, a0 |
5a0015d6 CZ |
1676 | |
1677 | /* Exit critical section. */ | |
1678 | ||
1679 | movi a0, 0 | |
99d5040e | 1680 | rsr a3, excsave1 |
5a0015d6 CZ |
1681 | s32i a0, a3, EXC_TABLE_FIXUP |
1682 | ||
1683 | /* Restore the working registers, and return. */ | |
1684 | ||
99d5040e | 1685 | l32i a3, a2, PT_AREG3 |
5a0015d6 CZ |
1686 | l32i a1, a2, PT_AREG1 |
1687 | l32i a0, a2, PT_AREG0 | |
1688 | l32i a2, a2, PT_DEPC | |
1689 | ||
5a0015d6 CZ |
1690 | bgeui a2, VALID_DOUBLE_EXCEPTION_ADDRESS, 1f |
1691 | ||
bc5378fc | 1692 | rsr a2, depc |
5a0015d6 CZ |
1693 | rfe |
1694 | ||
1695 | /* Double exception. Restore FIXUP handler and return. */ | |
1696 | ||
bc5378fc | 1697 | 1: xsr a2, depc |
5a0015d6 CZ |
1698 | esync |
1699 | rfde | |
1700 | ||
1701 | 9: l32i a0, a1, TASK_ACTIVE_MM # unlikely case mm == 0 | |
1702 | j 8b | |
1703 | ||
1704 | 2: /* If there was a problem, handle fault in C */ | |
1705 | ||
99d5040e MF |
1706 | rsr a3, depc # still holds a2 |
1707 | s32i a3, a2, PT_AREG2 | |
5a0015d6 CZ |
1708 | mov a1, a2 |
1709 | ||
bc5378fc | 1710 | rsr a2, ps |
173d6681 | 1711 | bbsi.l a2, PS_UM_BIT, 1f |
5a0015d6 CZ |
1712 | j _kernel_exception |
1713 | 1: j _user_exception | |
d1538c46 CZ |
1714 | |
1715 | ENDPROC(fast_store_prohibited) | |
1716 | ||
e5083a63 | 1717 | #endif /* CONFIG_MMU */ |
5a0015d6 | 1718 | |
fc4fb2ad CZ |
1719 | /* |
1720 | * System Calls. | |
1721 | * | |
1722 | * void system_call (struct pt_regs* regs, int exccause) | |
1723 | * a2 a3 | |
1724 | */ | |
1725 | ||
1726 | ENTRY(system_call) | |
d1538c46 | 1727 | |
fc4fb2ad CZ |
1728 | entry a1, 32 |
1729 | ||
1730 | /* regs->syscall = regs->areg[2] */ | |
1731 | ||
1732 | l32i a3, a2, PT_AREG2 | |
1733 | mov a6, a2 | |
1734 | movi a4, do_syscall_trace_enter | |
1735 | s32i a3, a2, PT_SYSCALL | |
1736 | callx4 a4 | |
1737 | ||
1738 | /* syscall = sys_call_table[syscall_nr] */ | |
1739 | ||
1740 | movi a4, sys_call_table; | |
1741 | movi a5, __NR_syscall_count | |
1742 | movi a6, -ENOSYS | |
1743 | bgeu a3, a5, 1f | |
1744 | ||
1745 | addx4 a4, a3, a4 | |
1746 | l32i a4, a4, 0 | |
1747 | movi a5, sys_ni_syscall; | |
1748 | beq a4, a5, 1f | |
1749 | ||
1750 | /* Load args: arg0 - arg5 are passed via regs. */ | |
1751 | ||
1752 | l32i a6, a2, PT_AREG6 | |
1753 | l32i a7, a2, PT_AREG3 | |
1754 | l32i a8, a2, PT_AREG4 | |
1755 | l32i a9, a2, PT_AREG5 | |
1756 | l32i a10, a2, PT_AREG8 | |
1757 | l32i a11, a2, PT_AREG9 | |
1758 | ||
1759 | /* Pass one additional argument to the syscall: pt_regs (on stack) */ | |
1760 | s32i a2, a1, 0 | |
1761 | ||
1762 | callx4 a4 | |
1763 | ||
1764 | 1: /* regs->areg[2] = return_value */ | |
1765 | ||
1766 | s32i a6, a2, PT_AREG2 | |
1767 | movi a4, do_syscall_trace_leave | |
1768 | mov a6, a2 | |
1769 | callx4 a4 | |
1770 | retw | |
1771 | ||
d1538c46 CZ |
1772 | ENDPROC(system_call) |
1773 | ||
e2fd1374 MF |
1774 | /* |
1775 | * Spill live registers on the kernel stack macro. | |
1776 | * | |
1777 | * Entry condition: ps.woe is set, ps.excm is cleared | |
1778 | * Exit condition: windowstart has single bit set | |
1779 | * May clobber: a12, a13 | |
1780 | */ | |
1781 | .macro spill_registers_kernel | |
1782 | ||
1783 | #if XCHAL_NUM_AREGS > 16 | |
1784 | call12 1f | |
1785 | _j 2f | |
1786 | retw | |
1787 | .align 4 | |
1788 | 1: | |
1789 | _entry a1, 48 | |
1790 | addi a12, a0, 3 | |
1791 | #if XCHAL_NUM_AREGS > 32 | |
1792 | .rept (XCHAL_NUM_AREGS - 32) / 12 | |
1793 | _entry a1, 48 | |
1794 | mov a12, a0 | |
1795 | .endr | |
1796 | #endif | |
1797 | _entry a1, 48 | |
1798 | #if XCHAL_NUM_AREGS % 12 == 0 | |
1799 | mov a8, a8 | |
1800 | #elif XCHAL_NUM_AREGS % 12 == 4 | |
1801 | mov a12, a12 | |
1802 | #elif XCHAL_NUM_AREGS % 12 == 8 | |
1803 | mov a4, a4 | |
1804 | #endif | |
1805 | retw | |
1806 | 2: | |
1807 | #else | |
1808 | mov a12, a12 | |
1809 | #endif | |
1810 | .endm | |
fc4fb2ad | 1811 | |
5a0015d6 CZ |
1812 | /* |
1813 | * Task switch. | |
1814 | * | |
1815 | * struct task* _switch_to (struct task* prev, struct task* next) | |
1816 | * a2 a2 a3 | |
1817 | */ | |
1818 | ||
1819 | ENTRY(_switch_to) | |
1820 | ||
1821 | entry a1, 16 | |
1822 | ||
e2fd1374 MF |
1823 | mov a10, a2 # preserve 'prev' (a2) |
1824 | mov a11, a3 # and 'next' (a3) | |
5a0015d6 | 1825 | |
c658eac6 CZ |
1826 | l32i a4, a2, TASK_THREAD_INFO |
1827 | l32i a5, a3, TASK_THREAD_INFO | |
5a0015d6 | 1828 | |
e2fd1374 | 1829 | save_xtregs_user a4 a6 a8 a9 a12 a13 THREAD_XTREGS_USER |
5a0015d6 | 1830 | |
e2fd1374 MF |
1831 | s32i a0, a10, THREAD_RA # save return address |
1832 | s32i a1, a10, THREAD_SP # save stack pointer | |
c658eac6 CZ |
1833 | |
1834 | /* Disable ints while we manipulate the stack pointer. */ | |
1835 | ||
e2fd1374 | 1836 | rsil a14, LOCKLEVEL |
bc5378fc | 1837 | rsr a3, excsave1 |
5a0015d6 CZ |
1838 | rsync |
1839 | s32i a3, a3, EXC_TABLE_FIXUP /* enter critical section */ | |
1840 | ||
c658eac6 CZ |
1841 | /* Switch CPENABLE */ |
1842 | ||
1843 | #if (XTENSA_HAVE_COPROCESSORS || XTENSA_HAVE_IO_PORTS) | |
1844 | l32i a3, a5, THREAD_CPENABLE | |
bc5378fc | 1845 | xsr a3, cpenable |
c658eac6 CZ |
1846 | s32i a3, a4, THREAD_CPENABLE |
1847 | #endif | |
1848 | ||
1849 | /* Flush register file. */ | |
1850 | ||
e2fd1374 | 1851 | spill_registers_kernel |
5a0015d6 CZ |
1852 | |
1853 | /* Set kernel stack (and leave critical section) | |
1854 | * Note: It's save to set it here. The stack will not be overwritten | |
1855 | * because the kernel stack will only be loaded again after | |
1856 | * we return from kernel space. | |
1857 | */ | |
1858 | ||
bc5378fc | 1859 | rsr a3, excsave1 # exc_table |
c658eac6 CZ |
1860 | movi a6, 0 |
1861 | addi a7, a5, PT_REGS_OFFSET | |
1862 | s32i a6, a3, EXC_TABLE_FIXUP | |
1863 | s32i a7, a3, EXC_TABLE_KSTK | |
5a0015d6 | 1864 | |
c50842df | 1865 | /* restore context of the task 'next' */ |
5a0015d6 | 1866 | |
e2fd1374 MF |
1867 | l32i a0, a11, THREAD_RA # restore return address |
1868 | l32i a1, a11, THREAD_SP # restore stack pointer | |
c658eac6 | 1869 | |
e2fd1374 | 1870 | load_xtregs_user a5 a6 a8 a9 a12 a13 THREAD_XTREGS_USER |
5a0015d6 | 1871 | |
bc5378fc | 1872 | wsr a14, ps |
e2fd1374 | 1873 | mov a2, a10 # return 'prev' |
5a0015d6 CZ |
1874 | rsync |
1875 | ||
1876 | retw | |
1877 | ||
d1538c46 | 1878 | ENDPROC(_switch_to) |
5a0015d6 CZ |
1879 | |
1880 | ENTRY(ret_from_fork) | |
1881 | ||
1882 | /* void schedule_tail (struct task_struct *prev) | |
1883 | * Note: prev is still in a6 (return value from fake call4 frame) | |
1884 | */ | |
1885 | movi a4, schedule_tail | |
1886 | callx4 a4 | |
1887 | ||
fc4fb2ad CZ |
1888 | movi a4, do_syscall_trace_leave |
1889 | mov a6, a1 | |
5a0015d6 CZ |
1890 | callx4 a4 |
1891 | ||
1892 | j common_exception_return | |
1893 | ||
d1538c46 CZ |
1894 | ENDPROC(ret_from_fork) |
1895 | ||
3306a726 MF |
1896 | /* |
1897 | * Kernel thread creation helper | |
1898 | * On entry, set up by copy_thread: a2 = thread_fn, a3 = thread_fn arg | |
1899 | * left from _switch_to: a6 = prev | |
1900 | */ | |
1901 | ENTRY(ret_from_kernel_thread) | |
1902 | ||
1903 | call4 schedule_tail | |
1904 | mov a6, a3 | |
1905 | callx4 a2 | |
f0a1bf08 | 1906 | j common_exception_return |
3306a726 MF |
1907 | |
1908 | ENDPROC(ret_from_kernel_thread) |