Commit | Line | Data |
---|---|---|
5a0015d6 | 1 | /* |
f30c2269 | 2 | * arch/xtensa/kernel/setup.c |
5a0015d6 CZ |
3 | * |
4 | * This file is subject to the terms and conditions of the GNU General Public | |
5 | * License. See the file "COPYING" in the main directory of this archive | |
6 | * for more details. | |
7 | * | |
8 | * Copyright (C) 1995 Linus Torvalds | |
9 | * Copyright (C) 2001 - 2005 Tensilica Inc. | |
10 | * | |
11 | * Chris Zankel <chris@zankel.net> | |
12 | * Joe Taylor <joe@tensilica.com, joetylr@yahoo.com> | |
13 | * Kevin Chea | |
14 | * Marc Gauthier<marc@tensilica.com> <marc@alumni.uwaterloo.ca> | |
15 | */ | |
16 | ||
5a0015d6 CZ |
17 | #include <linux/errno.h> |
18 | #include <linux/init.h> | |
27ac792c | 19 | #include <linux/mm.h> |
5a0015d6 | 20 | #include <linux/proc_fs.h> |
894673ee | 21 | #include <linux/screen_info.h> |
5a0015d6 CZ |
22 | #include <linux/bootmem.h> |
23 | #include <linux/kernel.h> | |
f615136c | 24 | #include <linux/percpu.h> |
bda8932d | 25 | #include <linux/clk-provider.h> |
f615136c | 26 | #include <linux/cpu.h> |
da844a81 MF |
27 | #include <linux/of_fdt.h> |
28 | #include <linux/of_platform.h> | |
da844a81 | 29 | |
5a0015d6 CZ |
30 | #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE) |
31 | # include <linux/console.h> | |
32 | #endif | |
33 | ||
34 | #ifdef CONFIG_RTC | |
35 | # include <linux/timex.h> | |
36 | #endif | |
37 | ||
38 | #ifdef CONFIG_PROC_FS | |
39 | # include <linux/seq_file.h> | |
40 | #endif | |
41 | ||
5a0015d6 | 42 | #include <asm/bootparam.h> |
c8f3a7dc | 43 | #include <asm/mmu_context.h> |
5a0015d6 CZ |
44 | #include <asm/pgtable.h> |
45 | #include <asm/processor.h> | |
46 | #include <asm/timex.h> | |
47 | #include <asm/platform.h> | |
48 | #include <asm/page.h> | |
49 | #include <asm/setup.h> | |
de4f6e5b | 50 | #include <asm/param.h> |
00273125 | 51 | #include <asm/traps.h> |
f615136c | 52 | #include <asm/smp.h> |
9ba067f9 | 53 | #include <asm/sysmem.h> |
5a0015d6 | 54 | |
5a891ed5 AD |
55 | #include <platform/hardware.h> |
56 | ||
5a0015d6 CZ |
57 | #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE) |
58 | struct screen_info screen_info = { 0, 24, 0, 0, 0, 80, 0, 0, 0, 24, 1, 16}; | |
59 | #endif | |
60 | ||
61 | #ifdef CONFIG_BLK_DEV_FD | |
62 | extern struct fd_ops no_fd_ops; | |
63 | struct fd_ops *fd_ops; | |
64 | #endif | |
65 | ||
5a0015d6 CZ |
66 | extern struct rtc_ops no_rtc_ops; |
67 | struct rtc_ops *rtc_ops; | |
68 | ||
5a0015d6 | 69 | #ifdef CONFIG_BLK_DEV_INITRD |
29eb45a9 RH |
70 | extern unsigned long initrd_start; |
71 | extern unsigned long initrd_end; | |
5a0015d6 CZ |
72 | int initrd_is_mapped = 0; |
73 | extern int initrd_below_start_ok; | |
74 | #endif | |
75 | ||
da844a81 | 76 | #ifdef CONFIG_OF |
da844a81 MF |
77 | void *dtb_start = __dtb_start; |
78 | #endif | |
79 | ||
5a0015d6 CZ |
80 | unsigned char aux_device_present; |
81 | extern unsigned long loops_per_jiffy; | |
82 | ||
83 | /* Command line specified as configuration option. */ | |
84 | ||
d3e9ccea | 85 | static char __initdata command_line[COMMAND_LINE_SIZE]; |
5a0015d6 CZ |
86 | |
87 | #ifdef CONFIG_CMDLINE_BOOL | |
88 | static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE; | |
89 | #endif | |
90 | ||
5a0015d6 CZ |
91 | /* |
92 | * Boot parameter parsing. | |
93 | * | |
94 | * The Xtensa port uses a list of variable-sized tags to pass data to | |
95 | * the kernel. The first tag must be a BP_TAG_FIRST tag for the list | |
96 | * to be recognised. The list is terminated with a zero-sized | |
97 | * BP_TAG_LAST tag. | |
98 | */ | |
99 | ||
100 | typedef struct tagtable { | |
101 | u32 tag; | |
102 | int (*parse)(const bp_tag_t*); | |
103 | } tagtable_t; | |
104 | ||
105 | #define __tagtable(tag, fn) static tagtable_t __tagtable_##fn \ | |
f4349b6e | 106 | __attribute__((used, section(".taglist"))) = { tag, fn } |
5a0015d6 CZ |
107 | |
108 | /* parse current tag */ | |
109 | ||
da844a81 MF |
110 | static int __init parse_tag_mem(const bp_tag_t *tag) |
111 | { | |
9ba067f9 | 112 | struct bp_meminfo *mi = (struct bp_meminfo *)(tag->data); |
da844a81 MF |
113 | |
114 | if (mi->type != MEMORY_TYPE_CONVENTIONAL) | |
115 | return -1; | |
116 | ||
9ba067f9 | 117 | return add_sysmem_bank(mi->start, mi->end); |
da844a81 MF |
118 | } |
119 | ||
5a0015d6 CZ |
120 | __tagtable(BP_TAG_MEMORY, parse_tag_mem); |
121 | ||
122 | #ifdef CONFIG_BLK_DEV_INITRD | |
123 | ||
124 | static int __init parse_tag_initrd(const bp_tag_t* tag) | |
125 | { | |
9ba067f9 MF |
126 | struct bp_meminfo *mi = (struct bp_meminfo *)(tag->data); |
127 | ||
29eb45a9 RH |
128 | initrd_start = (unsigned long)__va(mi->start); |
129 | initrd_end = (unsigned long)__va(mi->end); | |
5a0015d6 CZ |
130 | |
131 | return 0; | |
132 | } | |
133 | ||
134 | __tagtable(BP_TAG_INITRD, parse_tag_initrd); | |
135 | ||
da844a81 MF |
136 | #ifdef CONFIG_OF |
137 | ||
138 | static int __init parse_tag_fdt(const bp_tag_t *tag) | |
139 | { | |
c5a771d0 | 140 | dtb_start = __va(tag->data[0]); |
da844a81 MF |
141 | return 0; |
142 | } | |
143 | ||
144 | __tagtable(BP_TAG_FDT, parse_tag_fdt); | |
145 | ||
da844a81 MF |
146 | #endif /* CONFIG_OF */ |
147 | ||
5a0015d6 CZ |
148 | #endif /* CONFIG_BLK_DEV_INITRD */ |
149 | ||
150 | static int __init parse_tag_cmdline(const bp_tag_t* tag) | |
151 | { | |
da844a81 | 152 | strlcpy(command_line, (char *)(tag->data), COMMAND_LINE_SIZE); |
5a0015d6 CZ |
153 | return 0; |
154 | } | |
155 | ||
156 | __tagtable(BP_TAG_COMMAND_LINE, parse_tag_cmdline); | |
157 | ||
158 | static int __init parse_bootparam(const bp_tag_t* tag) | |
159 | { | |
160 | extern tagtable_t __tagtable_begin, __tagtable_end; | |
161 | tagtable_t *t; | |
162 | ||
163 | /* Boot parameters must start with a BP_TAG_FIRST tag. */ | |
164 | ||
165 | if (tag->id != BP_TAG_FIRST) { | |
166 | printk(KERN_WARNING "Invalid boot parameters!\n"); | |
167 | return 0; | |
168 | } | |
169 | ||
170 | tag = (bp_tag_t*)((unsigned long)tag + sizeof(bp_tag_t) + tag->size); | |
171 | ||
172 | /* Parse all tags. */ | |
173 | ||
174 | while (tag != NULL && tag->id != BP_TAG_LAST) { | |
175 | for (t = &__tagtable_begin; t < &__tagtable_end; t++) { | |
176 | if (tag->id == t->tag) { | |
177 | t->parse(tag); | |
178 | break; | |
179 | } | |
180 | } | |
181 | if (t == &__tagtable_end) | |
182 | printk(KERN_WARNING "Ignoring tag " | |
183 | "0x%08x\n", tag->id); | |
184 | tag = (bp_tag_t*)((unsigned long)(tag + 1) + tag->size); | |
185 | } | |
186 | ||
187 | return 0; | |
188 | } | |
189 | ||
da844a81 | 190 | #ifdef CONFIG_OF |
7745fc1f | 191 | bool __initdata dt_memory_scan = false; |
da844a81 | 192 | |
6cb97111 BS |
193 | #if XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY |
194 | unsigned long xtensa_kio_paddr = XCHAL_KIO_DEFAULT_PADDR; | |
195 | EXPORT_SYMBOL(xtensa_kio_paddr); | |
196 | ||
197 | static int __init xtensa_dt_io_area(unsigned long node, const char *uname, | |
198 | int depth, void *data) | |
199 | { | |
200 | const __be32 *ranges; | |
9d0c4dfe | 201 | int len; |
6cb97111 BS |
202 | |
203 | if (depth > 1) | |
204 | return 0; | |
205 | ||
206 | if (!of_flat_dt_is_compatible(node, "simple-bus")) | |
207 | return 0; | |
208 | ||
209 | ranges = of_get_flat_dt_prop(node, "ranges", &len); | |
210 | if (!ranges) | |
211 | return 1; | |
212 | if (len == 0) | |
213 | return 1; | |
214 | ||
215 | xtensa_kio_paddr = of_read_ulong(ranges+1, 1); | |
216 | /* round down to nearest 256MB boundary */ | |
217 | xtensa_kio_paddr &= 0xf0000000; | |
218 | ||
219 | return 1; | |
220 | } | |
221 | #else | |
222 | static int __init xtensa_dt_io_area(unsigned long node, const char *uname, | |
223 | int depth, void *data) | |
224 | { | |
225 | return 1; | |
226 | } | |
227 | #endif | |
228 | ||
da844a81 MF |
229 | void __init early_init_dt_add_memory_arch(u64 base, u64 size) |
230 | { | |
7745fc1f RH |
231 | if (!dt_memory_scan) |
232 | return; | |
233 | ||
da844a81 | 234 | size &= PAGE_MASK; |
9ba067f9 | 235 | add_sysmem_bank(base, base + size); |
da844a81 MF |
236 | } |
237 | ||
238 | void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align) | |
239 | { | |
240 | return __alloc_bootmem(size, align, 0); | |
241 | } | |
242 | ||
243 | void __init early_init_devtree(void *params) | |
244 | { | |
7745fc1f RH |
245 | if (sysmem.nr_banks == 0) |
246 | dt_memory_scan = true; | |
da844a81 | 247 | |
7745fc1f | 248 | early_init_dt_scan(params); |
6cb97111 | 249 | of_scan_flat_dt(xtensa_dt_io_area, NULL); |
da844a81 | 250 | |
7745fc1f RH |
251 | if (!command_line[0]) |
252 | strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE); | |
da844a81 MF |
253 | } |
254 | ||
da844a81 MF |
255 | static int __init xtensa_device_probe(void) |
256 | { | |
bda8932d | 257 | of_clk_init(NULL); |
f8935f30 | 258 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); |
da844a81 MF |
259 | return 0; |
260 | } | |
261 | ||
262 | device_initcall(xtensa_device_probe); | |
263 | ||
264 | #endif /* CONFIG_OF */ | |
265 | ||
5a0015d6 CZ |
266 | /* |
267 | * Initialize architecture. (Early stage) | |
268 | */ | |
269 | ||
270 | void __init init_arch(bp_tag_t *bp_start) | |
271 | { | |
5a0015d6 CZ |
272 | /* Parse boot parameters */ |
273 | ||
c4c4594b | 274 | if (bp_start) |
da844a81 MF |
275 | parse_bootparam(bp_start); |
276 | ||
277 | #ifdef CONFIG_OF | |
278 | early_init_devtree(dtb_start); | |
279 | #endif | |
5a0015d6 CZ |
280 | |
281 | if (sysmem.nr_banks == 0) { | |
9ba067f9 MF |
282 | add_sysmem_bank(PLATFORM_DEFAULT_MEM_START, |
283 | PLATFORM_DEFAULT_MEM_START + | |
284 | PLATFORM_DEFAULT_MEM_SIZE); | |
5a0015d6 CZ |
285 | } |
286 | ||
da844a81 MF |
287 | #ifdef CONFIG_CMDLINE_BOOL |
288 | if (!command_line[0]) | |
289 | strlcpy(command_line, default_command_line, COMMAND_LINE_SIZE); | |
290 | #endif | |
291 | ||
5a0015d6 CZ |
292 | /* Early hook for platforms */ |
293 | ||
294 | platform_init(bp_start); | |
295 | ||
296 | /* Initialize MMU. */ | |
297 | ||
298 | init_mmu(); | |
299 | } | |
300 | ||
301 | /* | |
302 | * Initialize system. Setup memory and reserve regions. | |
303 | */ | |
304 | ||
305 | extern char _end; | |
306 | extern char _stext; | |
307 | extern char _WindowVectors_text_start; | |
308 | extern char _WindowVectors_text_end; | |
309 | extern char _DebugInterruptVector_literal_start; | |
310 | extern char _DebugInterruptVector_text_end; | |
311 | extern char _KernelExceptionVector_literal_start; | |
312 | extern char _KernelExceptionVector_text_end; | |
313 | extern char _UserExceptionVector_literal_start; | |
314 | extern char _UserExceptionVector_text_end; | |
315 | extern char _DoubleExceptionVector_literal_start; | |
316 | extern char _DoubleExceptionVector_text_end; | |
2d1c645c MG |
317 | #if XCHAL_EXCM_LEVEL >= 2 |
318 | extern char _Level2InterruptVector_text_start; | |
319 | extern char _Level2InterruptVector_text_end; | |
320 | #endif | |
321 | #if XCHAL_EXCM_LEVEL >= 3 | |
322 | extern char _Level3InterruptVector_text_start; | |
323 | extern char _Level3InterruptVector_text_end; | |
324 | #endif | |
325 | #if XCHAL_EXCM_LEVEL >= 4 | |
326 | extern char _Level4InterruptVector_text_start; | |
327 | extern char _Level4InterruptVector_text_end; | |
328 | #endif | |
329 | #if XCHAL_EXCM_LEVEL >= 5 | |
330 | extern char _Level5InterruptVector_text_start; | |
331 | extern char _Level5InterruptVector_text_end; | |
332 | #endif | |
333 | #if XCHAL_EXCM_LEVEL >= 6 | |
334 | extern char _Level6InterruptVector_text_start; | |
335 | extern char _Level6InterruptVector_text_end; | |
336 | #endif | |
337 | ||
5a0015d6 | 338 | |
00273125 MF |
339 | |
340 | #ifdef CONFIG_S32C1I_SELFTEST | |
341 | #if XCHAL_HAVE_S32C1I | |
342 | ||
343 | static int __initdata rcw_word, rcw_probe_pc, rcw_exc; | |
344 | ||
345 | /* | |
346 | * Basic atomic compare-and-swap, that records PC of S32C1I for probing. | |
347 | * | |
348 | * If *v == cmp, set *v = set. Return previous *v. | |
349 | */ | |
350 | static inline int probed_compare_swap(int *v, int cmp, int set) | |
351 | { | |
352 | int tmp; | |
353 | ||
354 | __asm__ __volatile__( | |
355 | " movi %1, 1f\n" | |
356 | " s32i %1, %4, 0\n" | |
357 | " wsr %2, scompare1\n" | |
358 | "1: s32c1i %0, %3, 0\n" | |
359 | : "=a" (set), "=&a" (tmp) | |
360 | : "a" (cmp), "a" (v), "a" (&rcw_probe_pc), "0" (set) | |
361 | : "memory" | |
362 | ); | |
363 | return set; | |
364 | } | |
365 | ||
366 | /* Handle probed exception */ | |
367 | ||
59970753 MF |
368 | static void __init do_probed_exception(struct pt_regs *regs, |
369 | unsigned long exccause) | |
00273125 MF |
370 | { |
371 | if (regs->pc == rcw_probe_pc) { /* exception on s32c1i ? */ | |
372 | regs->pc += 3; /* skip the s32c1i instruction */ | |
373 | rcw_exc = exccause; | |
374 | } else { | |
375 | do_unhandled(regs, exccause); | |
376 | } | |
377 | } | |
378 | ||
379 | /* Simple test of S32C1I (soc bringup assist) */ | |
380 | ||
59970753 | 381 | static int __init check_s32c1i(void) |
00273125 MF |
382 | { |
383 | int n, cause1, cause2; | |
384 | void *handbus, *handdata, *handaddr; /* temporarily saved handlers */ | |
385 | ||
386 | rcw_probe_pc = 0; | |
387 | handbus = trap_set_handler(EXCCAUSE_LOAD_STORE_ERROR, | |
388 | do_probed_exception); | |
389 | handdata = trap_set_handler(EXCCAUSE_LOAD_STORE_DATA_ERROR, | |
390 | do_probed_exception); | |
391 | handaddr = trap_set_handler(EXCCAUSE_LOAD_STORE_ADDR_ERROR, | |
392 | do_probed_exception); | |
393 | ||
394 | /* First try an S32C1I that does not store: */ | |
395 | rcw_exc = 0; | |
396 | rcw_word = 1; | |
397 | n = probed_compare_swap(&rcw_word, 0, 2); | |
398 | cause1 = rcw_exc; | |
399 | ||
400 | /* took exception? */ | |
401 | if (cause1 != 0) { | |
402 | /* unclean exception? */ | |
403 | if (n != 2 || rcw_word != 1) | |
404 | panic("S32C1I exception error"); | |
405 | } else if (rcw_word != 1 || n != 1) { | |
406 | panic("S32C1I compare error"); | |
407 | } | |
408 | ||
409 | /* Then an S32C1I that stores: */ | |
410 | rcw_exc = 0; | |
411 | rcw_word = 0x1234567; | |
412 | n = probed_compare_swap(&rcw_word, 0x1234567, 0xabcde); | |
413 | cause2 = rcw_exc; | |
414 | ||
415 | if (cause2 != 0) { | |
416 | /* unclean exception? */ | |
417 | if (n != 0xabcde || rcw_word != 0x1234567) | |
418 | panic("S32C1I exception error (b)"); | |
419 | } else if (rcw_word != 0xabcde || n != 0x1234567) { | |
420 | panic("S32C1I store error"); | |
421 | } | |
422 | ||
423 | /* Verify consistency of exceptions: */ | |
424 | if (cause1 || cause2) { | |
425 | pr_warn("S32C1I took exception %d, %d\n", cause1, cause2); | |
426 | /* If emulation of S32C1I upon bus error gets implemented, | |
427 | we can get rid of this panic for single core (not SMP) */ | |
428 | panic("S32C1I exceptions not currently supported"); | |
429 | } | |
430 | if (cause1 != cause2) | |
431 | panic("inconsistent S32C1I exceptions"); | |
432 | ||
433 | trap_set_handler(EXCCAUSE_LOAD_STORE_ERROR, handbus); | |
434 | trap_set_handler(EXCCAUSE_LOAD_STORE_DATA_ERROR, handdata); | |
435 | trap_set_handler(EXCCAUSE_LOAD_STORE_ADDR_ERROR, handaddr); | |
59970753 | 436 | return 0; |
00273125 MF |
437 | } |
438 | ||
439 | #else /* XCHAL_HAVE_S32C1I */ | |
440 | ||
441 | /* This condition should not occur with a commercially deployed processor. | |
442 | Display reminder for early engr test or demo chips / FPGA bitstreams */ | |
59970753 | 443 | static int __init check_s32c1i(void) |
00273125 MF |
444 | { |
445 | pr_warn("Processor configuration lacks atomic compare-and-swap support!\n"); | |
59970753 | 446 | return 0; |
00273125 MF |
447 | } |
448 | ||
449 | #endif /* XCHAL_HAVE_S32C1I */ | |
59970753 | 450 | early_initcall(check_s32c1i); |
00273125 MF |
451 | #endif /* CONFIG_S32C1I_SELFTEST */ |
452 | ||
453 | ||
5a0015d6 CZ |
454 | void __init setup_arch(char **cmdline_p) |
455 | { | |
da844a81 | 456 | strlcpy(boot_command_line, command_line, COMMAND_LINE_SIZE); |
5a0015d6 CZ |
457 | *cmdline_p = command_line; |
458 | ||
459 | /* Reserve some memory regions */ | |
460 | ||
461 | #ifdef CONFIG_BLK_DEV_INITRD | |
462 | if (initrd_start < initrd_end) { | |
463 | initrd_is_mapped = mem_reserve(__pa(initrd_start), | |
62327918 | 464 | __pa(initrd_end), 0) == 0; |
5a0015d6 | 465 | initrd_below_start_ok = 1; |
c4c4594b | 466 | } else { |
5a0015d6 CZ |
467 | initrd_start = 0; |
468 | } | |
469 | #endif | |
470 | ||
471 | mem_reserve(__pa(&_stext),__pa(&_end), 1); | |
472 | ||
473 | mem_reserve(__pa(&_WindowVectors_text_start), | |
474 | __pa(&_WindowVectors_text_end), 0); | |
475 | ||
476 | mem_reserve(__pa(&_DebugInterruptVector_literal_start), | |
477 | __pa(&_DebugInterruptVector_text_end), 0); | |
478 | ||
479 | mem_reserve(__pa(&_KernelExceptionVector_literal_start), | |
480 | __pa(&_KernelExceptionVector_text_end), 0); | |
481 | ||
482 | mem_reserve(__pa(&_UserExceptionVector_literal_start), | |
483 | __pa(&_UserExceptionVector_text_end), 0); | |
484 | ||
485 | mem_reserve(__pa(&_DoubleExceptionVector_literal_start), | |
486 | __pa(&_DoubleExceptionVector_text_end), 0); | |
487 | ||
2d1c645c MG |
488 | #if XCHAL_EXCM_LEVEL >= 2 |
489 | mem_reserve(__pa(&_Level2InterruptVector_text_start), | |
490 | __pa(&_Level2InterruptVector_text_end), 0); | |
491 | #endif | |
492 | #if XCHAL_EXCM_LEVEL >= 3 | |
493 | mem_reserve(__pa(&_Level3InterruptVector_text_start), | |
494 | __pa(&_Level3InterruptVector_text_end), 0); | |
495 | #endif | |
496 | #if XCHAL_EXCM_LEVEL >= 4 | |
497 | mem_reserve(__pa(&_Level4InterruptVector_text_start), | |
498 | __pa(&_Level4InterruptVector_text_end), 0); | |
499 | #endif | |
500 | #if XCHAL_EXCM_LEVEL >= 5 | |
501 | mem_reserve(__pa(&_Level5InterruptVector_text_start), | |
502 | __pa(&_Level5InterruptVector_text_end), 0); | |
503 | #endif | |
504 | #if XCHAL_EXCM_LEVEL >= 6 | |
505 | mem_reserve(__pa(&_Level6InterruptVector_text_start), | |
506 | __pa(&_Level6InterruptVector_text_end), 0); | |
507 | #endif | |
508 | ||
06bd2824 | 509 | parse_early_param(); |
5a0015d6 CZ |
510 | bootmem_init(); |
511 | ||
3104021c | 512 | unflatten_and_copy_device_tree(); |
5a0015d6 | 513 | |
da844a81 | 514 | platform_setup(cmdline_p); |
5a0015d6 | 515 | |
f615136c MF |
516 | #ifdef CONFIG_SMP |
517 | smp_init_cpus(); | |
518 | #endif | |
519 | ||
5a0015d6 | 520 | paging_init(); |
e5083a63 | 521 | zones_init(); |
5a0015d6 CZ |
522 | |
523 | #ifdef CONFIG_VT | |
524 | # if defined(CONFIG_VGA_CONSOLE) | |
525 | conswitchp = &vga_con; | |
526 | # elif defined(CONFIG_DUMMY_CONSOLE) | |
527 | conswitchp = &dummy_con; | |
528 | # endif | |
529 | #endif | |
530 | ||
288a60cf | 531 | #ifdef CONFIG_PCI |
5a0015d6 CZ |
532 | platform_pcibios_init(); |
533 | #endif | |
534 | } | |
535 | ||
f615136c MF |
536 | static DEFINE_PER_CPU(struct cpu, cpu_data); |
537 | ||
538 | static int __init topology_init(void) | |
539 | { | |
540 | int i; | |
541 | ||
542 | for_each_possible_cpu(i) { | |
543 | struct cpu *cpu = &per_cpu(cpu_data, i); | |
49b424fe | 544 | cpu->hotpluggable = !!i; |
f615136c MF |
545 | register_cpu(cpu, i); |
546 | } | |
547 | ||
548 | return 0; | |
549 | } | |
550 | subsys_initcall(topology_init); | |
551 | ||
5a0015d6 CZ |
552 | void machine_restart(char * cmd) |
553 | { | |
554 | platform_restart(); | |
555 | } | |
556 | ||
557 | void machine_halt(void) | |
558 | { | |
559 | platform_halt(); | |
560 | while (1); | |
561 | } | |
562 | ||
563 | void machine_power_off(void) | |
564 | { | |
565 | platform_power_off(); | |
566 | while (1); | |
567 | } | |
568 | #ifdef CONFIG_PROC_FS | |
569 | ||
570 | /* | |
571 | * Display some core information through /proc/cpuinfo. | |
572 | */ | |
573 | ||
574 | static int | |
575 | c_show(struct seq_file *f, void *slot) | |
576 | { | |
577 | /* high-level stuff */ | |
f615136c | 578 | seq_printf(f, "CPU count\t: %u\n" |
62518994 | 579 | "CPU list\t: %*pbl\n" |
f615136c MF |
580 | "vendor_id\t: Tensilica\n" |
581 | "model\t\t: Xtensa " XCHAL_HW_VERSION_NAME "\n" | |
582 | "core ID\t\t: " XCHAL_CORE_ID "\n" | |
583 | "build ID\t: 0x%x\n" | |
584 | "byte order\t: %s\n" | |
585 | "cpu MHz\t\t: %lu.%02lu\n" | |
586 | "bogomips\t: %lu.%02lu\n", | |
587 | num_online_cpus(), | |
62518994 | 588 | cpumask_pr_args(cpu_online_mask), |
f615136c MF |
589 | XCHAL_BUILD_UNIQUE_ID, |
590 | XCHAL_HAVE_BE ? "big" : "little", | |
591 | ccount_freq/1000000, | |
592 | (ccount_freq/10000) % 100, | |
593 | loops_per_jiffy/(500000/HZ), | |
594 | (loops_per_jiffy/(5000/HZ)) % 100); | |
5a0015d6 CZ |
595 | |
596 | seq_printf(f,"flags\t\t: " | |
597 | #if XCHAL_HAVE_NMI | |
598 | "nmi " | |
599 | #endif | |
600 | #if XCHAL_HAVE_DEBUG | |
601 | "debug " | |
602 | # if XCHAL_HAVE_OCD | |
603 | "ocd " | |
604 | # endif | |
605 | #endif | |
606 | #if XCHAL_HAVE_DENSITY | |
607 | "density " | |
608 | #endif | |
609 | #if XCHAL_HAVE_BOOLEANS | |
610 | "boolean " | |
611 | #endif | |
612 | #if XCHAL_HAVE_LOOPS | |
613 | "loop " | |
614 | #endif | |
615 | #if XCHAL_HAVE_NSA | |
616 | "nsa " | |
617 | #endif | |
618 | #if XCHAL_HAVE_MINMAX | |
619 | "minmax " | |
620 | #endif | |
621 | #if XCHAL_HAVE_SEXT | |
622 | "sext " | |
623 | #endif | |
624 | #if XCHAL_HAVE_CLAMPS | |
625 | "clamps " | |
626 | #endif | |
627 | #if XCHAL_HAVE_MAC16 | |
628 | "mac16 " | |
629 | #endif | |
630 | #if XCHAL_HAVE_MUL16 | |
631 | "mul16 " | |
632 | #endif | |
633 | #if XCHAL_HAVE_MUL32 | |
634 | "mul32 " | |
635 | #endif | |
636 | #if XCHAL_HAVE_MUL32_HIGH | |
637 | "mul32h " | |
638 | #endif | |
639 | #if XCHAL_HAVE_FP | |
640 | "fpu " | |
2f6ea6a7 MF |
641 | #endif |
642 | #if XCHAL_HAVE_S32C1I | |
643 | "s32c1i " | |
5a0015d6 CZ |
644 | #endif |
645 | "\n"); | |
646 | ||
647 | /* Registers. */ | |
648 | seq_printf(f,"physical aregs\t: %d\n" | |
649 | "misc regs\t: %d\n" | |
650 | "ibreak\t\t: %d\n" | |
651 | "dbreak\t\t: %d\n", | |
652 | XCHAL_NUM_AREGS, | |
653 | XCHAL_NUM_MISC_REGS, | |
654 | XCHAL_NUM_IBREAK, | |
655 | XCHAL_NUM_DBREAK); | |
656 | ||
657 | ||
658 | /* Interrupt. */ | |
659 | seq_printf(f,"num ints\t: %d\n" | |
660 | "ext ints\t: %d\n" | |
661 | "int levels\t: %d\n" | |
662 | "timers\t\t: %d\n" | |
663 | "debug level\t: %d\n", | |
664 | XCHAL_NUM_INTERRUPTS, | |
665 | XCHAL_NUM_EXTINTERRUPTS, | |
666 | XCHAL_NUM_INTLEVELS, | |
667 | XCHAL_NUM_TIMERS, | |
668 | XCHAL_DEBUGLEVEL); | |
669 | ||
5a0015d6 CZ |
670 | /* Cache */ |
671 | seq_printf(f,"icache line size: %d\n" | |
672 | "icache ways\t: %d\n" | |
673 | "icache size\t: %d\n" | |
674 | "icache flags\t: " | |
675 | #if XCHAL_ICACHE_LINE_LOCKABLE | |
415217ef | 676 | "lock " |
5a0015d6 CZ |
677 | #endif |
678 | "\n" | |
679 | "dcache line size: %d\n" | |
680 | "dcache ways\t: %d\n" | |
681 | "dcache size\t: %d\n" | |
682 | "dcache flags\t: " | |
683 | #if XCHAL_DCACHE_IS_WRITEBACK | |
415217ef | 684 | "writeback " |
5a0015d6 CZ |
685 | #endif |
686 | #if XCHAL_DCACHE_LINE_LOCKABLE | |
415217ef | 687 | "lock " |
5a0015d6 CZ |
688 | #endif |
689 | "\n", | |
690 | XCHAL_ICACHE_LINESIZE, | |
691 | XCHAL_ICACHE_WAYS, | |
692 | XCHAL_ICACHE_SIZE, | |
693 | XCHAL_DCACHE_LINESIZE, | |
694 | XCHAL_DCACHE_WAYS, | |
695 | XCHAL_DCACHE_SIZE); | |
696 | ||
5a0015d6 CZ |
697 | return 0; |
698 | } | |
699 | ||
700 | /* | |
701 | * We show only CPU #0 info. | |
702 | */ | |
703 | static void * | |
704 | c_start(struct seq_file *f, loff_t *pos) | |
705 | { | |
f615136c | 706 | return (*pos == 0) ? (void *)1 : NULL; |
5a0015d6 CZ |
707 | } |
708 | ||
709 | static void * | |
710 | c_next(struct seq_file *f, void *v, loff_t *pos) | |
711 | { | |
712 | return NULL; | |
713 | } | |
714 | ||
715 | static void | |
716 | c_stop(struct seq_file *f, void *v) | |
717 | { | |
718 | } | |
719 | ||
03a44825 | 720 | const struct seq_operations cpuinfo_op = |
5a0015d6 | 721 | { |
f615136c MF |
722 | .start = c_start, |
723 | .next = c_next, | |
724 | .stop = c_stop, | |
725 | .show = c_show, | |
5a0015d6 CZ |
726 | }; |
727 | ||
728 | #endif /* CONFIG_PROC_FS */ |