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5a0015d6 CZ |
1 | /* |
2 | * arch/xtensa/kernel/time.c | |
3 | * | |
4 | * Timer and clock support. | |
5 | * | |
6 | * This file is subject to the terms and conditions of the GNU General Public | |
7 | * License. See the file "COPYING" in the main directory of this archive | |
8 | * for more details. | |
9 | * | |
10 | * Copyright (C) 2005 Tensilica Inc. | |
11 | * | |
12 | * Chris Zankel <chris@zankel.net> | |
13 | */ | |
14 | ||
5a0015d6 | 15 | #include <linux/errno.h> |
d43c36dc | 16 | #include <linux/sched.h> |
5a0015d6 | 17 | #include <linux/time.h> |
fcc8f0f8 | 18 | #include <linux/clocksource.h> |
925f5532 | 19 | #include <linux/clockchips.h> |
5a0015d6 CZ |
20 | #include <linux/interrupt.h> |
21 | #include <linux/module.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/irq.h> | |
24 | #include <linux/profile.h> | |
25 | #include <linux/delay.h> | |
2206d5dd | 26 | #include <linux/irqdomain.h> |
e3f43291 | 27 | #include <linux/sched_clock.h> |
5a0015d6 CZ |
28 | |
29 | #include <asm/timex.h> | |
30 | #include <asm/platform.h> | |
31 | ||
e504c4b6 | 32 | unsigned long ccount_freq; /* ccount Hz */ |
45ec8860 | 33 | EXPORT_SYMBOL(ccount_freq); |
5a0015d6 | 34 | |
09378d7c | 35 | static cycle_t ccount_read(struct clocksource *cs) |
fcc8f0f8 JW |
36 | { |
37 | return (cycle_t)get_ccount(); | |
38 | } | |
39 | ||
3ade4f81 | 40 | static u64 notrace ccount_sched_clock_read(void) |
e3f43291 BS |
41 | { |
42 | return get_ccount(); | |
43 | } | |
44 | ||
fcc8f0f8 JW |
45 | static struct clocksource ccount_clocksource = { |
46 | .name = "ccount", | |
47 | .rating = 200, | |
48 | .read = ccount_read, | |
49 | .mask = CLOCKSOURCE_MASK(32), | |
0fb4040e | 50 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
fcc8f0f8 JW |
51 | }; |
52 | ||
925f5532 BS |
53 | static int ccount_timer_set_next_event(unsigned long delta, |
54 | struct clock_event_device *dev); | |
62351531 | 55 | struct ccount_timer { |
925f5532 BS |
56 | struct clock_event_device evt; |
57 | int irq_enabled; | |
62351531 | 58 | char name[24]; |
925f5532 | 59 | }; |
62351531 | 60 | static DEFINE_PER_CPU(struct ccount_timer, ccount_timer); |
925f5532 BS |
61 | |
62 | static int ccount_timer_set_next_event(unsigned long delta, | |
63 | struct clock_event_device *dev) | |
64 | { | |
65 | unsigned long flags, next; | |
66 | int ret = 0; | |
67 | ||
68 | local_irq_save(flags); | |
69 | next = get_ccount() + delta; | |
70 | set_linux_timer(next); | |
71 | if (next - get_ccount() > delta) | |
72 | ret = -ETIME; | |
73 | local_irq_restore(flags); | |
74 | ||
75 | return ret; | |
76 | } | |
77 | ||
8e40fc4b VK |
78 | /* |
79 | * There is no way to disable the timer interrupt at the device level, | |
80 | * only at the intenable register itself. Since enable_irq/disable_irq | |
81 | * calls are nested, we need to make sure that these calls are | |
82 | * balanced. | |
83 | */ | |
84 | static int ccount_timer_shutdown(struct clock_event_device *evt) | |
85 | { | |
86 | struct ccount_timer *timer = | |
87 | container_of(evt, struct ccount_timer, evt); | |
88 | ||
89 | if (timer->irq_enabled) { | |
90 | disable_irq(evt->irq); | |
91 | timer->irq_enabled = 0; | |
92 | } | |
93 | return 0; | |
94 | } | |
95 | ||
96 | static int ccount_timer_set_oneshot(struct clock_event_device *evt) | |
925f5532 | 97 | { |
62351531 MF |
98 | struct ccount_timer *timer = |
99 | container_of(evt, struct ccount_timer, evt); | |
925f5532 | 100 | |
8e40fc4b VK |
101 | if (!timer->irq_enabled) { |
102 | enable_irq(evt->irq); | |
103 | timer->irq_enabled = 1; | |
925f5532 | 104 | } |
8e40fc4b | 105 | return 0; |
925f5532 BS |
106 | } |
107 | ||
fd43fe19 | 108 | static irqreturn_t timer_interrupt(int irq, void *dev_id); |
5a0015d6 CZ |
109 | static struct irqaction timer_irqaction = { |
110 | .handler = timer_interrupt, | |
925f5532 | 111 | .flags = IRQF_TIMER, |
5a0015d6 CZ |
112 | .name = "timer", |
113 | }; | |
114 | ||
62351531 MF |
115 | void local_timer_setup(unsigned cpu) |
116 | { | |
117 | struct ccount_timer *timer = &per_cpu(ccount_timer, cpu); | |
118 | struct clock_event_device *clockevent = &timer->evt; | |
119 | ||
120 | timer->irq_enabled = 1; | |
121 | clockevent->name = timer->name; | |
122 | snprintf(timer->name, sizeof(timer->name), "ccount_clockevent_%u", cpu); | |
123 | clockevent->features = CLOCK_EVT_FEAT_ONESHOT; | |
124 | clockevent->rating = 300; | |
125 | clockevent->set_next_event = ccount_timer_set_next_event; | |
8e40fc4b VK |
126 | clockevent->set_state_shutdown = ccount_timer_shutdown; |
127 | clockevent->set_state_oneshot = ccount_timer_set_oneshot; | |
128 | clockevent->tick_resume = ccount_timer_set_oneshot; | |
62351531 MF |
129 | clockevent->cpumask = cpumask_of(cpu); |
130 | clockevent->irq = irq_create_mapping(NULL, LINUX_TIMER_INT); | |
131 | if (WARN(!clockevent->irq, "error: can't map timer irq")) | |
132 | return; | |
133 | clockevents_config_and_register(clockevent, ccount_freq, | |
134 | 0xf, 0xffffffff); | |
135 | } | |
136 | ||
5a0015d6 CZ |
137 | void __init time_init(void) |
138 | { | |
288a60cf | 139 | #ifdef CONFIG_XTENSA_CALIBRATE_CCOUNT |
5a0015d6 CZ |
140 | printk("Calibrating CPU frequency "); |
141 | platform_calibrate_ccount(); | |
e504c4b6 BS |
142 | printk("%d.%02d MHz\n", (int)ccount_freq/1000000, |
143 | (int)(ccount_freq/10000)%100); | |
fedc21dc BS |
144 | #else |
145 | ccount_freq = CONFIG_XTENSA_CPU_CLOCK*1000000UL; | |
5a0015d6 | 146 | #endif |
8d5e1d8e | 147 | clocksource_register_hz(&ccount_clocksource, ccount_freq); |
62351531 MF |
148 | local_timer_setup(0); |
149 | setup_irq(this_cpu_ptr(&ccount_timer)->evt.irq, &timer_irqaction); | |
3ade4f81 | 150 | sched_clock_register(ccount_sched_clock_read, 32, ccount_freq); |
b087ab7f | 151 | clocksource_of_init(); |
5a0015d6 CZ |
152 | } |
153 | ||
5a0015d6 CZ |
154 | /* |
155 | * The timer interrupt is called HZ times per second. | |
156 | */ | |
157 | ||
62351531 | 158 | irqreturn_t timer_interrupt(int irq, void *dev_id) |
5a0015d6 | 159 | { |
62351531 | 160 | struct clock_event_device *evt = &this_cpu_ptr(&ccount_timer)->evt; |
5a0015d6 | 161 | |
bae07f8a | 162 | set_linux_timer(get_linux_timer()); |
925f5532 | 163 | evt->event_handler(evt); |
5a0015d6 | 164 | |
2b8aea74 | 165 | /* Allow platform to do something useful (Wdog). */ |
2b8aea74 | 166 | platform_heartbeat(); |
5a0015d6 | 167 | |
5a0015d6 CZ |
168 | return IRQ_HANDLED; |
169 | } | |
170 | ||
171 | #ifndef CONFIG_GENERIC_CALIBRATE_DELAY | |
6cb4c159 | 172 | void calibrate_delay(void) |
5a0015d6 | 173 | { |
8d5e1d8e | 174 | loops_per_jiffy = ccount_freq / HZ; |
5a0015d6 CZ |
175 | printk("Calibrating delay loop (skipped)... " |
176 | "%lu.%02lu BogoMIPS preset\n", | |
177 | loops_per_jiffy/(1000000/HZ), | |
178 | (loops_per_jiffy/(10000/HZ)) % 100); | |
179 | } | |
180 | #endif |