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* configure.host: Set HLDFLAGS and SHLIB_CFLAGS for *-dec-osf*
[deliverable/binutils-gdb.git] / bfd / coff-mips.c
CommitLineData
1f29e30b 1/* BFD back-end for MIPS Extended-Coff files.
cba3f8a9 2 Copyright 1990, 91, 92, 93, 94, 95, 1996 Free Software Foundation, Inc.
8fa0d3a0 3 Original version by Per Bothner.
f6409552 4 Full support added by Ian Lance Taylor, ian@cygnus.com.
1327fb29 5
68b70212 6This file is part of BFD, the Binary File Descriptor library.
23b0b558 7
68b70212 8This program is free software; you can redistribute it and/or modify
23b0b558 9it under the terms of the GNU General Public License as published by
68b70212
JG		 10the Free Software Foundation; either version 2 of the License, or
11(at your option) any later version.
23b0b558 12
68b70212 13This program is distributed in the hope that it will be useful,
23b0b558
JG		 14but WITHOUT ANY WARRANTY; without even the implied warranty of
15MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16GNU General Public License for more details.
17
18You should have received a copy of the GNU General Public License
68b70212 19along with this program; if not, write to the Free Software
a5655244 20Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
1327fb29 21
23b0b558 22#include "bfd.h"
dd4646ca 23#include "sysdep.h"
4991ebb9 24#include "bfdlink.h"
1327fb29 25#include "libbfd.h"
dae31cf5
ILT		 26#include "coff/internal.h"
27#include "coff/sym.h"
28#include "coff/symconst.h"
29#include "coff/ecoff.h"
30#include "coff/mips.h"
31#include "libcoff.h"
32#include "libecoff.h"
33\f
34/* Prototypes for static functions. */
c3fe0c41 35
dae31cf5 36static boolean mips_ecoff_bad_format_hook PARAMS ((bfd *abfd, PTR filehdr));
dae31cf5
ILT		 37static void mips_ecoff_swap_reloc_in PARAMS ((bfd *, PTR,
38 struct internal_reloc *));
39static void mips_ecoff_swap_reloc_out PARAMS ((bfd *,
40 const struct internal_reloc *,
41 PTR));
5fa2aaa2
ILT		 42static void mips_adjust_reloc_in PARAMS ((bfd *,
43 const struct internal_reloc *,
44 arelent *));
45static void mips_adjust_reloc_out PARAMS ((bfd *, const arelent *,
46 struct internal_reloc *));
23f44e6f
ILT		 47static bfd_reloc_status_type mips_generic_reloc PARAMS ((bfd *abfd,
48 arelent *reloc,
49 asymbol *symbol,
50 PTR data,
51 asection *section,
4991ebb9
ILT		 52 bfd *output_bfd,
53 char **error));
23f44e6f
ILT		 54static bfd_reloc_status_type mips_refhi_reloc PARAMS ((bfd *abfd,
55 arelent *reloc,
56 asymbol *symbol,
57 PTR data,
58 asection *section,
4991ebb9
ILT		 59 bfd *output_bfd,
60 char **error));
23f44e6f
ILT		 61static bfd_reloc_status_type mips_reflo_reloc PARAMS ((bfd *abfd,
62 arelent *reloc,
63 asymbol *symbol,
64 PTR data,
65 asection *section,
4991ebb9
ILT		 66 bfd *output_bfd,
67 char **error));
23f44e6f
ILT		 68static bfd_reloc_status_type mips_gprel_reloc PARAMS ((bfd *abfd,
69 arelent *reloc,
70 asymbol *symbol,
71 PTR data,
72 asection *section,
4991ebb9
ILT		 73 bfd *output_bfd,
74 char **error));
4f996613
ILT		 75static bfd_reloc_status_type mips_relhi_reloc PARAMS ((bfd *abfd,
76 arelent *reloc,
77 asymbol *symbol,
78 PTR data,
79 asection *section,
80 bfd *output_bfd,
81 char **error));
82static bfd_reloc_status_type mips_rello_reloc PARAMS ((bfd *abfd,
83 arelent *reloc,
84 asymbol *symbol,
85 PTR data,
86 asection *section,
87 bfd *output_bfd,
88 char **error));
dabf906e
ILT		 89static bfd_reloc_status_type mips_switch_reloc PARAMS ((bfd *abfd,
90 arelent *reloc,
91 asymbol *symbol,
92 PTR data,
93 asection *section,
94 bfd *output_bfd,
95 char **error));
4f996613
ILT		 96static void mips_relocate_hi PARAMS ((struct internal_reloc *refhi,
97 struct internal_reloc *reflo,
98 bfd *input_bfd,
99 asection *input_section,
100 bfd_byte *contents,
101 size_t adjust,
102 bfd_vma relocation,
103 boolean pcrel));
4991ebb9
ILT		 104static boolean mips_relocate_section PARAMS ((bfd *, struct bfd_link_info *,
105 bfd *, asection *,
106 bfd_byte *, PTR));
a5655244 107static boolean mips_read_relocs PARAMS ((bfd *, asection *));
a3a33af3
ILT		 108static boolean mips_relax_section PARAMS ((bfd *, asection *,
109 struct bfd_link_info *,
110 boolean *));
111static boolean mips_relax_pcrel16 PARAMS ((struct bfd_link_info *, bfd *,
112 asection *,
113 struct ecoff_link_hash_entry *,
114 bfd_byte *, bfd_vma));
dae31cf5 115\f
dae31cf5
ILT		 116/* ECOFF has COFF sections, but the debugging information is stored in
117 a completely different format. ECOFF targets use some of the
118 swapping routines from coffswap.h, and some of the generic COFF
119 routines in coffgen.c, but, unlike the real COFF targets, do not
120 use coffcode.h itself.
8fa0d3a0 121
dae31cf5 122 Get the generic COFF swapping routines, except for the reloc,
23f44e6f 123 symbol, and lineno ones. Give them ECOFF names. */
dae31cf5
ILT		 124#define MIPSECOFF
125#define NO_COFF_RELOCS
126#define NO_COFF_SYMBOLS
127#define NO_COFF_LINENOS
128#define coff_swap_filehdr_in mips_ecoff_swap_filehdr_in
129#define coff_swap_filehdr_out mips_ecoff_swap_filehdr_out
130#define coff_swap_aouthdr_in mips_ecoff_swap_aouthdr_in
131#define coff_swap_aouthdr_out mips_ecoff_swap_aouthdr_out
132#define coff_swap_scnhdr_in mips_ecoff_swap_scnhdr_in
133#define coff_swap_scnhdr_out mips_ecoff_swap_scnhdr_out
134#include "coffswap.h"
8fa0d3a0 135
dae31cf5
ILT		 136/* Get the ECOFF swapping routines. */
137#define ECOFF_32
138#include "ecoffswap.h"
139\f
23f44e6f 140/* How to process the various relocs types. */
dae31cf5 141
23f44e6f 142static reloc_howto_type mips_howto_table[] =
dae31cf5 143{
23f44e6f
ILT		 144 /* Reloc type 0 is ignored. The reloc reading code ensures that
145 this is a reference to the .abs section, which will cause
146 bfd_perform_relocation to do nothing. */
147 HOWTO (MIPS_R_IGNORE, /* type */
148 0, /* rightshift */
149 0, /* size (0 = byte, 1 = short, 2 = long) */
150 8, /* bitsize */
151 false, /* pc_relative */
152 0, /* bitpos */
153 complain_overflow_dont, /* complain_on_overflow */
154 0, /* special_function */
155 "IGNORE", /* name */
156 false, /* partial_inplace */
157 0, /* src_mask */
158 0, /* dst_mask */
159 false), /* pcrel_offset */
160
161 /* A 16 bit reference to a symbol, normally from a data section. */
162 HOWTO (MIPS_R_REFHALF, /* type */
163 0, /* rightshift */
164 1, /* size (0 = byte, 1 = short, 2 = long) */
165 16, /* bitsize */
166 false, /* pc_relative */
167 0, /* bitpos */
168 complain_overflow_bitfield, /* complain_on_overflow */
169 mips_generic_reloc, /* special_function */
170 "REFHALF", /* name */
171 true, /* partial_inplace */
172 0xffff, /* src_mask */
173 0xffff, /* dst_mask */
174 false), /* pcrel_offset */
175
176 /* A 32 bit reference to a symbol, normally from a data section. */
177 HOWTO (MIPS_R_REFWORD, /* type */
178 0, /* rightshift */
179 2, /* size (0 = byte, 1 = short, 2 = long) */
180 32, /* bitsize */
181 false, /* pc_relative */
182 0, /* bitpos */
183 complain_overflow_bitfield, /* complain_on_overflow */
184 mips_generic_reloc, /* special_function */
185 "REFWORD", /* name */
186 true, /* partial_inplace */
187 0xffffffff, /* src_mask */
188 0xffffffff, /* dst_mask */
189 false), /* pcrel_offset */
190
191 /* A 26 bit absolute jump address. */
192 HOWTO (MIPS_R_JMPADDR, /* type */
193 2, /* rightshift */
194 2, /* size (0 = byte, 1 = short, 2 = long) */
195 26, /* bitsize */
196 false, /* pc_relative */
197 0, /* bitpos */
5fa2aaa2
ILT		 198 complain_overflow_dont, /* complain_on_overflow */
199 /* This needs complex overflow
200 detection, because the upper four
201 bits must match the PC. */
23f44e6f
ILT		 202 mips_generic_reloc, /* special_function */
203 "JMPADDR", /* name */
204 true, /* partial_inplace */
205 0x3ffffff, /* src_mask */
206 0x3ffffff, /* dst_mask */
207 false), /* pcrel_offset */
208
209 /* The high 16 bits of a symbol value. Handled by the function
210 mips_refhi_reloc. */
211 HOWTO (MIPS_R_REFHI, /* type */
212 16, /* rightshift */
213 2, /* size (0 = byte, 1 = short, 2 = long) */
214 16, /* bitsize */
215 false, /* pc_relative */
216 0, /* bitpos */
217 complain_overflow_bitfield, /* complain_on_overflow */
218 mips_refhi_reloc, /* special_function */
219 "REFHI", /* name */
220 true, /* partial_inplace */
221 0xffff, /* src_mask */
222 0xffff, /* dst_mask */
223 false), /* pcrel_offset */
224
225 /* The low 16 bits of a symbol value. */
226 HOWTO (MIPS_R_REFLO, /* type */
227 0, /* rightshift */
228 2, /* size (0 = byte, 1 = short, 2 = long) */
229 16, /* bitsize */
230 false, /* pc_relative */
231 0, /* bitpos */
232 complain_overflow_dont, /* complain_on_overflow */
233 mips_reflo_reloc, /* special_function */
234 "REFLO", /* name */
235 true, /* partial_inplace */
236 0xffff, /* src_mask */
237 0xffff, /* dst_mask */
238 false), /* pcrel_offset */
239
240 /* A reference to an offset from the gp register. Handled by the
241 function mips_gprel_reloc. */
242 HOWTO (MIPS_R_GPREL, /* type */
243 0, /* rightshift */
244 2, /* size (0 = byte, 1 = short, 2 = long) */
245 16, /* bitsize */
246 false, /* pc_relative */
247 0, /* bitpos */
248 complain_overflow_signed, /* complain_on_overflow */
249 mips_gprel_reloc, /* special_function */
250 "GPREL", /* name */
251 true, /* partial_inplace */
252 0xffff, /* src_mask */
253 0xffff, /* dst_mask */
254 false), /* pcrel_offset */
255
256 /* A reference to a literal using an offset from the gp register.
257 Handled by the function mips_gprel_reloc. */
258 HOWTO (MIPS_R_LITERAL, /* type */
259 0, /* rightshift */
260 2, /* size (0 = byte, 1 = short, 2 = long) */
261 16, /* bitsize */
262 false, /* pc_relative */
263 0, /* bitpos */
264 complain_overflow_signed, /* complain_on_overflow */
265 mips_gprel_reloc, /* special_function */
266 "LITERAL", /* name */
267 true, /* partial_inplace */
268 0xffff, /* src_mask */
269 0xffff, /* dst_mask */
a3a33af3
ILT		 270 false), /* pcrel_offset */
271
4f996613
ILT		 272 { 8 },
273 { 9 },
274 { 10 },
275 { 11 },
276
a3a33af3
ILT		 277 /* This reloc is a Cygnus extension used when generating position
278 independent code for embedded systems. It represents a 16 bit PC
279 relative reloc rightshifted twice as used in the MIPS branch
280 instructions. */
281 HOWTO (MIPS_R_PCREL16, /* type */
282 2, /* rightshift */
283 2, /* size (0 = byte, 1 = short, 2 = long) */
284 16, /* bitsize */
285 true, /* pc_relative */
286 0, /* bitpos */
287 complain_overflow_signed, /* complain_on_overflow */
288 mips_generic_reloc, /* special_function */
289 "PCREL16", /* name */
290 true, /* partial_inplace */
291 0xffff, /* src_mask */
292 0xffff, /* dst_mask */
dabf906e
ILT		 293 true), /* pcrel_offset */
294
4f996613
ILT		 295 /* This reloc is a Cygnus extension used when generating position
296 independent code for embedded systems. It represents the high 16
297 bits of a PC relative reloc. The next reloc must be
298 MIPS_R_RELLO, and the addend is formed from the addends of the
299 two instructions, just as in MIPS_R_REFHI and MIPS_R_REFLO. The
300 final value is actually PC relative to the location of the
301 MIPS_R_RELLO reloc, not the MIPS_R_RELHI reloc. */
302 HOWTO (MIPS_R_RELHI, /* type */
303 16, /* rightshift */
304 2, /* size (0 = byte, 1 = short, 2 = long) */
305 16, /* bitsize */
306 true, /* pc_relative */
307 0, /* bitpos */
308 complain_overflow_bitfield, /* complain_on_overflow */
309 mips_relhi_reloc, /* special_function */
310 "RELHI", /* name */
311 true, /* partial_inplace */
312 0xffff, /* src_mask */
313 0xffff, /* dst_mask */
314 true), /* pcrel_offset */
315
316 /* This reloc is a Cygnus extension used when generating position
317 independent code for embedded systems. It represents the low 16
318 bits of a PC relative reloc. */
319 HOWTO (MIPS_R_RELLO, /* type */
320 0, /* rightshift */
321 2, /* size (0 = byte, 1 = short, 2 = long) */
322 16, /* bitsize */
323 true, /* pc_relative */
324 0, /* bitpos */
325 complain_overflow_dont, /* complain_on_overflow */
326 mips_rello_reloc, /* special_function */
327 "RELLO", /* name */
328 true, /* partial_inplace */
329 0xffff, /* src_mask */
330 0xffff, /* dst_mask */
331 true), /* pcrel_offset */
332
333 { 15 },
334 { 16 },
335 { 17 },
336 { 18 },
337 { 19 },
338 { 20 },
339 { 21 },
340
dabf906e
ILT		 341 /* This reloc is a Cygnus extension used when generating position
342 independent code for embedded systems. It represents an entry in
343 a switch table, which is the difference between two symbols in
344 the .text section. The symndx is actually the offset from the
345 reloc address to the subtrahend. See include/coff/mips.h for
346 more details. */
347 HOWTO (MIPS_R_SWITCH, /* type */
348 0, /* rightshift */
349 2, /* size (0 = byte, 1 = short, 2 = long) */
350 32, /* bitsize */
351 true, /* pc_relative */
352 0, /* bitpos */
353 complain_overflow_dont, /* complain_on_overflow */
354 mips_switch_reloc, /* special_function */
355 "SWITCH", /* name */
356 true, /* partial_inplace */
357 0xffffffff, /* src_mask */
358 0xffffffff, /* dst_mask */
a3a33af3 359 true) /* pcrel_offset */
dae31cf5 360};
23f44e6f
ILT		 361
362#define MIPS_HOWTO_COUNT \
363 (sizeof mips_howto_table / sizeof mips_howto_table[0])
a3a33af3
ILT		 364
365/* When the linker is doing relaxing, it may change a external PCREL16
366 reloc. This typically represents an instruction like
367 bal foo
368 We change it to
369 .set noreorder
370 bal $L1
371 lui $at,%hi(foo - $L1)
372 $L1:
373 addiu $at,%lo(foo - $L1)
374 addu $at,$at,$31
375 jalr $at
376 PCREL16_EXPANSION_ADJUSTMENT is the number of bytes this changes the
377 instruction by. */
378
379#define PCREL16_EXPANSION_ADJUSTMENT (4 * 4)
dae31cf5
ILT		 380\f
381/* See whether the magic number matches. */
8fa0d3a0 382
dae31cf5
ILT		 383static boolean
384mips_ecoff_bad_format_hook (abfd, filehdr)
385 bfd *abfd;
386 PTR filehdr;
387{
388 struct internal_filehdr *internal_f = (struct internal_filehdr *) filehdr;
8fa0d3a0 389
5fa2aaa2
ILT		 390 switch (internal_f->f_magic)
391 {
392 case MIPS_MAGIC_1:
393 /* I don't know what endianness this implies. */
394 return true;
c3fe0c41 395
5fa2aaa2
ILT		 396 case MIPS_MAGIC_BIG:
397 case MIPS_MAGIC_BIG2:
398 case MIPS_MAGIC_BIG3:
64d5f5d0 399 return bfd_big_endian (abfd);
c3fe0c41 400
5fa2aaa2
ILT		 401 case MIPS_MAGIC_LITTLE:
402 case MIPS_MAGIC_LITTLE2:
403 case MIPS_MAGIC_LITTLE3:
64d5f5d0 404 return bfd_little_endian (abfd);
23ba15b7 405
5fa2aaa2
ILT		 406 default:
407 return false;
c3fe0c41 408 }
dae31cf5
ILT		 409}
410\f
411/* Reloc handling. MIPS ECOFF relocs are packed into 8 bytes in
412 external form. They use a bit which indicates whether the symbol
413 is external. */
23ba15b7 414
dae31cf5 415/* Swap a reloc in. */
23ba15b7 416
dae31cf5
ILT		 417static void
418mips_ecoff_swap_reloc_in (abfd, ext_ptr, intern)
419 bfd *abfd;
420 PTR ext_ptr;
421 struct internal_reloc *intern;
422{
423 const RELOC *ext = (RELOC *) ext_ptr;
23ba15b7 424
dae31cf5 425 intern->r_vaddr = bfd_h_get_32 (abfd, (bfd_byte *) ext->r_vaddr);
64d5f5d0 426 if (bfd_header_big_endian (abfd))
dae31cf5
ILT		 427 {
428 intern->r_symndx = (((int) ext->r_bits[0]
429 << RELOC_BITS0_SYMNDX_SH_LEFT_BIG)
430 | ((int) ext->r_bits[1]
431 << RELOC_BITS1_SYMNDX_SH_LEFT_BIG)
432 | ((int) ext->r_bits[2]
433 << RELOC_BITS2_SYMNDX_SH_LEFT_BIG));
434 intern->r_type = ((ext->r_bits[3] & RELOC_BITS3_TYPE_BIG)
435 >> RELOC_BITS3_TYPE_SH_BIG);
436 intern->r_extern = (ext->r_bits[3] & RELOC_BITS3_EXTERN_BIG) != 0;
23ba15b7 437 }
dae31cf5 438 else
23ba15b7 439 {
dae31cf5
ILT		 440 intern->r_symndx = (((int) ext->r_bits[0]
441 << RELOC_BITS0_SYMNDX_SH_LEFT_LITTLE)
442 | ((int) ext->r_bits[1]
443 << RELOC_BITS1_SYMNDX_SH_LEFT_LITTLE)
444 | ((int) ext->r_bits[2]
445 << RELOC_BITS2_SYMNDX_SH_LEFT_LITTLE));
4f996613
ILT		 446 intern->r_type = (((ext->r_bits[3] & RELOC_BITS3_TYPE_LITTLE)
447 >> RELOC_BITS3_TYPE_SH_LITTLE)
448 | ((ext->r_bits[3] & RELOC_BITS3_TYPEHI_LITTLE)
449 << RELOC_BITS3_TYPEHI_SH_LITTLE));
dae31cf5 450 intern->r_extern = (ext->r_bits[3] & RELOC_BITS3_EXTERN_LITTLE) != 0;
23ba15b7 451 }
dabf906e 452
4f996613
ILT		 453 /* If this is a MIPS_R_SWITCH reloc, or an internal MIPS_R_RELHI or
454 MIPS_R_RELLO reloc, r_symndx is actually the offset from the
455 reloc address to the base of the difference (see
dabf906e
ILT		 456 include/coff/mips.h for more details). We copy symndx into the
457 r_offset field so as not to confuse ecoff_slurp_reloc_table in
458 ecoff.c. In adjust_reloc_in we then copy r_offset into the reloc
459 addend. */
4f996613
ILT		 460 if (intern->r_type == MIPS_R_SWITCH
461 || (! intern->r_extern
462 && (intern->r_type == MIPS_R_RELLO
463 || intern->r_type == MIPS_R_RELHI)))
dabf906e
ILT		 464 {
465 BFD_ASSERT (! intern->r_extern);
466 intern->r_offset = intern->r_symndx;
4f996613
ILT		 467 if (intern->r_offset & 0x800000)
468 intern->r_offset -= 0x1000000;
dabf906e
ILT		 469 intern->r_symndx = RELOC_SECTION_TEXT;
470 }
c3fe0c41
ILT		 471}
472
dae31cf5 473/* Swap a reloc out. */
c3fe0c41 474
dae31cf5
ILT		 475static void
476mips_ecoff_swap_reloc_out (abfd, intern, dst)
f6409552 477 bfd *abfd;
dae31cf5
ILT		 478 const struct internal_reloc *intern;
479 PTR dst;
c3fe0c41 480{
dae31cf5 481 RELOC *ext = (RELOC *) dst;
dabf906e 482 long r_symndx;
c3fe0c41 483
5fa2aaa2
ILT		 484 BFD_ASSERT (intern->r_extern
485 || (intern->r_symndx >= 0 && intern->r_symndx <= 12));
486
4f996613
ILT		 487 /* If this is a MIPS_R_SWITCH reloc, or an internal MIPS_R_RELLO or
488 MIPS_R_RELHI reloc, we actually want to write the contents of
489 r_offset out as the symbol index. This undoes the change made by
490 mips_ecoff_swap_reloc_in. */
491 if (intern->r_type != MIPS_R_SWITCH
492 && (intern->r_extern
493 || (intern->r_type != MIPS_R_RELHI
494 && intern->r_type != MIPS_R_RELLO)))
dabf906e
ILT		 495 r_symndx = intern->r_symndx;
496 else
497 {
498 BFD_ASSERT (intern->r_symndx == RELOC_SECTION_TEXT);
4f996613 499 r_symndx = intern->r_offset & 0xffffff;
dabf906e
ILT		 500 }
501
dae31cf5 502 bfd_h_put_32 (abfd, intern->r_vaddr, (bfd_byte *) ext->r_vaddr);
64d5f5d0 503 if (bfd_header_big_endian (abfd))
c3fe0c41 504 {
dabf906e
ILT		 505 ext->r_bits[0] = r_symndx >> RELOC_BITS0_SYMNDX_SH_LEFT_BIG;
506 ext->r_bits[1] = r_symndx >> RELOC_BITS1_SYMNDX_SH_LEFT_BIG;
507 ext->r_bits[2] = r_symndx >> RELOC_BITS2_SYMNDX_SH_LEFT_BIG;
dae31cf5
ILT		 508 ext->r_bits[3] = (((intern->r_type << RELOC_BITS3_TYPE_SH_BIG)
509 & RELOC_BITS3_TYPE_BIG)
510 | (intern->r_extern ? RELOC_BITS3_EXTERN_BIG : 0));
c3fe0c41 511 }
dae31cf5 512 else
c3fe0c41 513 {
dabf906e
ILT		 514 ext->r_bits[0] = r_symndx >> RELOC_BITS0_SYMNDX_SH_LEFT_LITTLE;
515 ext->r_bits[1] = r_symndx >> RELOC_BITS1_SYMNDX_SH_LEFT_LITTLE;
516 ext->r_bits[2] = r_symndx >> RELOC_BITS2_SYMNDX_SH_LEFT_LITTLE;
dae31cf5
ILT		 517 ext->r_bits[3] = (((intern->r_type << RELOC_BITS3_TYPE_SH_LITTLE)
518 & RELOC_BITS3_TYPE_LITTLE)
4f996613
ILT		 519 | ((intern->r_type >> RELOC_BITS3_TYPEHI_SH_LITTLE
520 & RELOC_BITS3_TYPEHI_LITTLE))
dae31cf5 521 | (intern->r_extern ? RELOC_BITS3_EXTERN_LITTLE : 0));
c3fe0c41 522 }
c3fe0c41 523}
23f44e6f
ILT		 524
525/* Finish canonicalizing a reloc. Part of this is generic to all
526 ECOFF targets, and that part is in ecoff.c. The rest is done in
527 this backend routine. It must fill in the howto field. */
528
529static void
5fa2aaa2 530mips_adjust_reloc_in (abfd, intern, rptr)
23f44e6f 531 bfd *abfd;
5fa2aaa2 532 const struct internal_reloc *intern;
23f44e6f
ILT		 533 arelent *rptr;
534{
dabf906e 535 if (intern->r_type > MIPS_R_SWITCH)
23f44e6f
ILT		 536 abort ();
537
538 if (! intern->r_extern
539 && (intern->r_type == MIPS_R_GPREL
540 || intern->r_type == MIPS_R_LITERAL))
cba3f8a9 541 rptr->addend += _bfd_get_gp_value (abfd);
23f44e6f
ILT		 542
543 /* If the type is MIPS_R_IGNORE, make sure this is a reference to
544 the absolute section so that the reloc is ignored. */
545 if (intern->r_type == MIPS_R_IGNORE)
69645d10 546 rptr->sym_ptr_ptr = bfd_abs_section_ptr->symbol_ptr_ptr;
23f44e6f 547
4f996613
ILT		 548 /* If this is a MIPS_R_SWITCH reloc, or an internal MIPS_R_RELHI or
549 MIPS_R_RELLO reloc, we want the addend field of the BFD relocto
550 hold the value which was originally in the symndx field of the
551 internal MIPS ECOFF reloc. This value was copied into
552 intern->r_offset by mips_swap_reloc_in, and here we copy it into
553 the addend field. */
554 if (intern->r_type == MIPS_R_SWITCH
555 || (! intern->r_extern
556 && (intern->r_type == MIPS_R_RELHI
557 || intern->r_type == MIPS_R_RELLO)))
dabf906e
ILT		 558 rptr->addend = intern->r_offset;
559
23f44e6f
ILT		 560 rptr->howto = &mips_howto_table[intern->r_type];
561}
562
5fa2aaa2
ILT		 563/* Make any adjustments needed to a reloc before writing it out. None
564 are needed for MIPS. */
565
566static void
4991ebb9 567mips_adjust_reloc_out (abfd, rel, intern)
5fa2aaa2
ILT		 568 bfd *abfd;
569 const arelent *rel;
570 struct internal_reloc *intern;
571{
4f996613
ILT		 572 /* For a MIPS_R_SWITCH reloc, or an internal MIPS_R_RELHI or
573 MIPS_R_RELLO reloc, we must copy rel->addend into
dabf906e
ILT		 574 intern->r_offset. This will then be written out as the symbol
575 index by mips_ecoff_swap_reloc_out. This operation parallels the
576 action of mips_adjust_reloc_in. */
4f996613
ILT		 577 if (intern->r_type == MIPS_R_SWITCH
578 || (! intern->r_extern
579 && (intern->r_type == MIPS_R_RELHI
580 || intern->r_type == MIPS_R_RELLO)))
dabf906e 581 intern->r_offset = rel->addend;
5fa2aaa2
ILT		 582}
583
23f44e6f
ILT		 584/* ECOFF relocs are either against external symbols, or against
585 sections. If we are producing relocateable output, and the reloc
586 is against an external symbol, and nothing has given us any
587 additional addend, the resulting reloc will also be against the
588 same symbol. In such a case, we don't want to change anything
589 about the way the reloc is handled, since it will all be done at
590 final link time. Rather than put special case code into
591 bfd_perform_relocation, all the reloc types use this howto
592 function. It just short circuits the reloc if producing
593 relocateable output against an external symbol. */
594
595static bfd_reloc_status_type
596mips_generic_reloc (abfd,
597 reloc_entry,
598 symbol,
599 data,
600 input_section,
4991ebb9
ILT		 601 output_bfd,
602 error_message)
23f44e6f
ILT		 603 bfd *abfd;
604 arelent *reloc_entry;
605 asymbol *symbol;
606 PTR data;
607 asection *input_section;
608 bfd *output_bfd;
4991ebb9 609 char **error_message;
23f44e6f
ILT		 610{
611 if (output_bfd != (bfd *) NULL
612 && (symbol->flags & BSF_SECTION_SYM) == 0
613 && reloc_entry->addend == 0)
614 {
615 reloc_entry->address += input_section->output_offset;
616 return bfd_reloc_ok;
617 }
618
619 return bfd_reloc_continue;
620}
621
622/* Do a REFHI relocation. This has to be done in combination with a
623 REFLO reloc, because there is a carry from the REFLO to the REFHI.
624 Here we just save the information we need; we do the actual
625 relocation when we see the REFLO. MIPS ECOFF requires that the
626 REFLO immediately follow the REFHI, so this ought to work. */
627
628static bfd_byte *mips_refhi_addr;
629static bfd_vma mips_refhi_addend;
630
631static bfd_reloc_status_type
632mips_refhi_reloc (abfd,
633 reloc_entry,
634 symbol,
635 data,
636 input_section,
4991ebb9
ILT		 637 output_bfd,
638 error_message)
23f44e6f
ILT		 639 bfd *abfd;
640 arelent *reloc_entry;
641 asymbol *symbol;
642 PTR data;
643 asection *input_section;
644 bfd *output_bfd;
4991ebb9 645 char **error_message;
23f44e6f
ILT		 646{
647 bfd_reloc_status_type ret;
648 bfd_vma relocation;
649
650 /* If we're relocating, and this an external symbol, we don't want
651 to change anything. */
652 if (output_bfd != (bfd *) NULL
653 && (symbol->flags & BSF_SECTION_SYM) == 0
654 && reloc_entry->addend == 0)
655 {
656 reloc_entry->address += input_section->output_offset;
657 return bfd_reloc_ok;
658 }
659
660 ret = bfd_reloc_ok;
69645d10 661 if (bfd_is_und_section (symbol->section)
23f44e6f
ILT		 662 && output_bfd == (bfd *) NULL)
663 ret = bfd_reloc_undefined;
664
665 if (bfd_is_com_section (symbol->section))
666 relocation = 0;
667 else
668 relocation = symbol->value;
669
670 relocation += symbol->section->output_section->vma;
671 relocation += symbol->section->output_offset;
672 relocation += reloc_entry->addend;
673
674 if (reloc_entry->address > input_section->_cooked_size)
675 return bfd_reloc_outofrange;
676
677 /* Save the information, and let REFLO do the actual relocation. */
678 mips_refhi_addr = (bfd_byte *) data + reloc_entry->address;
679 mips_refhi_addend = relocation;
680
681 if (output_bfd != (bfd *) NULL)
682 reloc_entry->address += input_section->output_offset;
683
684 return ret;
685}
686
687/* Do a REFLO relocation. This is a straightforward 16 bit inplace
688 relocation; this function exists in order to do the REFHI
689 relocation described above. */
690
691static bfd_reloc_status_type
692mips_reflo_reloc (abfd,
693 reloc_entry,
694 symbol,
695 data,
696 input_section,
4991ebb9
ILT		 697 output_bfd,
698 error_message)
23f44e6f
ILT		 699 bfd *abfd;
700 arelent *reloc_entry;
701 asymbol *symbol;
702 PTR data;
703 asection *input_section;
704 bfd *output_bfd;
4991ebb9 705 char **error_message;
23f44e6f
ILT		 706{
707 if (mips_refhi_addr != (bfd_byte *) NULL)
708 {
709 unsigned long insn;
710 unsigned long val;
711 unsigned long vallo;
712
713 /* Do the REFHI relocation. Note that we actually don't need to
714 know anything about the REFLO itself, except where to find
715 the low 16 bits of the addend needed by the REFHI. */
716 insn = bfd_get_32 (abfd, mips_refhi_addr);
717 vallo = (bfd_get_32 (abfd, (bfd_byte *) data + reloc_entry->address)
718 & 0xffff);
719 val = ((insn & 0xffff) << 16) + vallo;
720 val += mips_refhi_addend;
721
722 /* The low order 16 bits are always treated as a signed value.
723 Therefore, a negative value in the low order bits requires an
724 adjustment in the high order bits. We need to make this
725 adjustment in two ways: once for the bits we took from the
726 data, and once for the bits we are putting back in to the
727 data. */
728 if ((vallo & 0x8000) != 0)
729 val -= 0x10000;
730 if ((val & 0x8000) != 0)
731 val += 0x10000;
732
733 insn = (insn &~ 0xffff) | ((val >> 16) & 0xffff);
734 bfd_put_32 (abfd, insn, mips_refhi_addr);
735
736 mips_refhi_addr = (bfd_byte *) NULL;
737 }
738
739 /* Now do the REFLO reloc in the usual way. */
740 return mips_generic_reloc (abfd, reloc_entry, symbol, data,
4991ebb9 741 input_section, output_bfd, error_message);
23f44e6f
ILT		 742}
743
744/* Do a GPREL relocation. This is a 16 bit value which must become
745 the offset from the gp register. */
746
747static bfd_reloc_status_type
748mips_gprel_reloc (abfd,
4991ebb9
ILT		 749 reloc_entry,
750 symbol,
751 data,
752 input_section,
753 output_bfd,
754 error_message)
23f44e6f
ILT		 755 bfd *abfd;
756 arelent *reloc_entry;
757 asymbol *symbol;
758 PTR data;
759 asection *input_section;
760 bfd *output_bfd;
4991ebb9 761 char **error_message;
23f44e6f
ILT		 762{
763 boolean relocateable;
764 bfd_vma relocation;
765 unsigned long val;
766 unsigned long insn;
767
768 /* If we're relocating, and this is an external symbol with no
769 addend, we don't want to change anything. We will only have an
770 addend if this is a newly created reloc, not read from an ECOFF
771 file. */
772 if (output_bfd != (bfd *) NULL
773 && (symbol->flags & BSF_SECTION_SYM) == 0
774 && reloc_entry->addend == 0)
775 {
776 reloc_entry->address += input_section->output_offset;
777 return bfd_reloc_ok;
778 }
779
780 if (output_bfd != (bfd *) NULL)
781 relocateable = true;
782 else
783 {
784 relocateable = false;
785 output_bfd = symbol->section->output_section->owner;
786 }
787
69645d10 788 if (bfd_is_und_section (symbol->section)
23f44e6f
ILT		 789 && relocateable == false)
790 return bfd_reloc_undefined;
791
792 /* We have to figure out the gp value, so that we can adjust the
793 symbol value correctly. We look up the symbol _gp in the output
794 BFD. If we can't find it, we're stuck. We cache it in the ECOFF
795 target data. We don't need to adjust the symbol value for an
796 external symbol if we are producing relocateable output. */
cba3f8a9 797 if (_bfd_get_gp_value (output_bfd) == 0
23f44e6f
ILT		 798 && (relocateable == false
799 || (symbol->flags & BSF_SECTION_SYM) != 0))
800 {
801 if (relocateable != false)
802 {
803 /* Make up a value. */
cba3f8a9
ILT		 804 _bfd_set_gp_value (output_bfd,
805 symbol->section->output_section->vma + 0x4000);
23f44e6f
ILT		 806 }
807 else
808 {
809 unsigned int count;
810 asymbol **sym;
811 unsigned int i;
812
813 count = bfd_get_symcount (output_bfd);
814 sym = bfd_get_outsymbols (output_bfd);
815
816 if (sym == (asymbol **) NULL)
817 i = count;
818 else
819 {
820 for (i = 0; i < count; i++, sym++)
821 {
822 register CONST char *name;
823
824 name = bfd_asymbol_name (*sym);
825 if (*name == '_' && strcmp (name, "_gp") == 0)
826 {
cba3f8a9
ILT		 827 _bfd_set_gp_value (output_bfd,
828 bfd_asymbol_value (*sym));
23f44e6f
ILT		 829 break;
830 }
831 }
832 }
833
834 if (i >= count)
835 {
836 /* Only get the error once. */
cba3f8a9 837 _bfd_set_gp_value (output_bfd, 4);
4991ebb9
ILT		 838 *error_message =
839 (char *) "GP relative relocation when _gp not defined";
23f44e6f
ILT		 840 return bfd_reloc_dangerous;
841 }
842 }
843 }
844
845 if (bfd_is_com_section (symbol->section))
846 relocation = 0;
847 else
848 relocation = symbol->value;
849
850 relocation += symbol->section->output_section->vma;
851 relocation += symbol->section->output_offset;
852
853 if (reloc_entry->address > input_section->_cooked_size)
854 return bfd_reloc_outofrange;
855
856 insn = bfd_get_32 (abfd, (bfd_byte *) data + reloc_entry->address);
857
858 /* Set val to the offset into the section or symbol. */
859 val = ((insn & 0xffff) + reloc_entry->addend) & 0xffff;
860 if (val & 0x8000)
861 val -= 0x10000;
862
863 /* Adjust val for the final section location and GP value. If we
864 are producing relocateable output, we don't want to do this for
865 an external symbol. */
866 if (relocateable == false
867 || (symbol->flags & BSF_SECTION_SYM) != 0)
cba3f8a9 868 val += relocation - _bfd_get_gp_value (output_bfd);
23f44e6f
ILT		 869
870 insn = (insn &~ 0xffff) | (val & 0xffff);
871 bfd_put_32 (abfd, insn, (bfd_byte *) data + reloc_entry->address);
872
873 if (relocateable != false)
874 reloc_entry->address += input_section->output_offset;
875
876 /* Make sure it fit in 16 bits. */
877 if (val >= 0x8000 && val < 0xffff8000)
4991ebb9 878 return bfd_reloc_overflow;
23f44e6f
ILT		 879
880 return bfd_reloc_ok;
881}
882
4f996613
ILT		 883/* Do a RELHI relocation. We do this in conjunction with a RELLO
884 reloc, just as REFHI and REFLO are done together. RELHI and RELLO
885 are Cygnus extensions used when generating position independent
886 code for embedded systems. */
887
888static bfd_byte *mips_relhi_addr;
889static bfd_vma mips_relhi_addend;
890
891static bfd_reloc_status_type
892mips_relhi_reloc (abfd,
893 reloc_entry,
894 symbol,
895 data,
896 input_section,
897 output_bfd,
898 error_message)
899 bfd *abfd;
900 arelent *reloc_entry;
901 asymbol *symbol;
902 PTR data;
903 asection *input_section;
904 bfd *output_bfd;
905 char **error_message;
906{
907 bfd_reloc_status_type ret;
908 bfd_vma relocation;
909
910 /* If this is a reloc against a section symbol, then it is correct
911 in the object file. The only time we want to change this case is
912 when we are relaxing, and that is handled entirely by
913 mips_relocate_section and never calls this function. */
914 if ((symbol->flags & BSF_SECTION_SYM) != 0)
915 {
916 if (output_bfd != (bfd *) NULL)
917 reloc_entry->address += input_section->output_offset;
918 return bfd_reloc_ok;
919 }
920
921 /* This is an external symbol. If we're relocating, we don't want
922 to change anything. */
923 if (output_bfd != (bfd *) NULL)
924 {
925 reloc_entry->address += input_section->output_offset;
926 return bfd_reloc_ok;
927 }
928
929 ret = bfd_reloc_ok;
69645d10 930 if (bfd_is_und_section (symbol->section)
4f996613
ILT		 931 && output_bfd == (bfd *) NULL)
932 ret = bfd_reloc_undefined;
933
934 if (bfd_is_com_section (symbol->section))
935 relocation = 0;
936 else
937 relocation = symbol->value;
938
939 relocation += symbol->section->output_section->vma;
940 relocation += symbol->section->output_offset;
941 relocation += reloc_entry->addend;
942
943 if (reloc_entry->address > input_section->_cooked_size)
944 return bfd_reloc_outofrange;
945
946 /* Save the information, and let RELLO do the actual relocation. */
947 mips_relhi_addr = (bfd_byte *) data + reloc_entry->address;
948 mips_relhi_addend = relocation;
949
950 if (output_bfd != (bfd *) NULL)
951 reloc_entry->address += input_section->output_offset;
952
953 return ret;
954}
955
956/* Do a RELLO relocation. This is a straightforward 16 bit PC
957 relative relocation; this function exists in order to do the RELHI
958 relocation described above. */
959
960static bfd_reloc_status_type
961mips_rello_reloc (abfd,
962 reloc_entry,
963 symbol,
964 data,
965 input_section,
966 output_bfd,
967 error_message)
968 bfd *abfd;
969 arelent *reloc_entry;
970 asymbol *symbol;
971 PTR data;
972 asection *input_section;
973 bfd *output_bfd;
974 char **error_message;
975{
976 if (mips_relhi_addr != (bfd_byte *) NULL)
977 {
978 unsigned long insn;
979 unsigned long val;
980 unsigned long vallo;
981
982 /* Do the RELHI relocation. Note that we actually don't need to
983 know anything about the RELLO itself, except where to find
984 the low 16 bits of the addend needed by the RELHI. */
985 insn = bfd_get_32 (abfd, mips_relhi_addr);
986 vallo = (bfd_get_32 (abfd, (bfd_byte *) data + reloc_entry->address)
987 & 0xffff);
988 val = ((insn & 0xffff) << 16) + vallo;
989 val += mips_relhi_addend;
990
991 /* If the symbol is defined, make val PC relative. If the
992 symbol is not defined we don't want to do this, because we
993 don't want the value in the object file to incorporate the
994 address of the reloc. */
69645d10 995 if (! bfd_is_und_section (bfd_get_section (symbol))
4f996613
ILT		 996 && ! bfd_is_com_section (bfd_get_section (symbol)))
997 val -= (input_section->output_section->vma
998 + input_section->output_offset
999 + reloc_entry->address);
1000
1001 /* The low order 16 bits are always treated as a signed value.
1002 Therefore, a negative value in the low order bits requires an
1003 adjustment in the high order bits. We need to make this
1004 adjustment in two ways: once for the bits we took from the
1005 data, and once for the bits we are putting back in to the
1006 data. */
1007 if ((vallo & 0x8000) != 0)
1008 val -= 0x10000;
1009 if ((val & 0x8000) != 0)
1010 val += 0x10000;
1011
1012 insn = (insn &~ 0xffff) | ((val >> 16) & 0xffff);
1013 bfd_put_32 (abfd, insn, mips_relhi_addr);
1014
1015 mips_relhi_addr = (bfd_byte *) NULL;
1016 }
1017
1018 /* If this is a reloc against a section symbol, then it is correct
1019 in the object file. The only time we want to change this case is
1020 when we are relaxing, and that is handled entirely by
1021 mips_relocate_section and never calls this function. */
1022 if ((symbol->flags & BSF_SECTION_SYM) != 0)
1023 {
1024 if (output_bfd != (bfd *) NULL)
1025 reloc_entry->address += input_section->output_offset;
1026 return bfd_reloc_ok;
1027 }
1028
1029 /* bfd_perform_relocation does not handle pcrel_offset relocations
1030 correctly when generating a relocateable file, so handle them
1031 directly here. */
1032 if (output_bfd != (bfd *) NULL)
1033 {
1034 reloc_entry->address += input_section->output_offset;
1035 return bfd_reloc_ok;
1036 }
1037
1038 /* Now do the RELLO reloc in the usual way. */
1039 return mips_generic_reloc (abfd, reloc_entry, symbol, data,
1040 input_section, output_bfd, error_message);
1041}
1042
dabf906e
ILT		 1043/* This is the special function for the MIPS_R_SWITCH reloc. This
1044 special reloc is normally correct in the object file, and only
1045 requires special handling when relaxing. We don't want
1046 bfd_perform_relocation to tamper with it at all. */
1047
1048/*ARGSUSED*/
1049static bfd_reloc_status_type
1050mips_switch_reloc (abfd,
1051 reloc_entry,
1052 symbol,
1053 data,
1054 input_section,
1055 output_bfd,
1056 error_message)
1057 bfd *abfd;
1058 arelent *reloc_entry;
1059 asymbol *symbol;
1060 PTR data;
1061 asection *input_section;
1062 bfd *output_bfd;
1063 char **error_message;
1064{
1065 return bfd_reloc_ok;
1066}
1067
23f44e6f
ILT		 1068/* Get the howto structure for a generic reloc type. */
1069
a5655244 1070static reloc_howto_type *
23f44e6f
ILT		 1071mips_bfd_reloc_type_lookup (abfd, code)
1072 bfd *abfd;
1073 bfd_reloc_code_real_type code;
1074{
1075 int mips_type;
1076
1077 switch (code)
1078 {
1079 case BFD_RELOC_16:
1080 mips_type = MIPS_R_REFHALF;
1081 break;
1082 case BFD_RELOC_32:
f1cca647 1083 case BFD_RELOC_CTOR:
23f44e6f
ILT		 1084 mips_type = MIPS_R_REFWORD;
1085 break;
1086 case BFD_RELOC_MIPS_JMP:
1087 mips_type = MIPS_R_JMPADDR;
1088 break;
1089 case BFD_RELOC_HI16_S:
1090 mips_type = MIPS_R_REFHI;
1091 break;
1092 case BFD_RELOC_LO16:
1093 mips_type = MIPS_R_REFLO;
1094 break;
1095 case BFD_RELOC_MIPS_GPREL:
1096 mips_type = MIPS_R_GPREL;
1097 break;
4991ebb9
ILT		 1098 case BFD_RELOC_MIPS_LITERAL:
1099 mips_type = MIPS_R_LITERAL;
1100 break;
a3a33af3
ILT		 1101 case BFD_RELOC_16_PCREL_S2:
1102 mips_type = MIPS_R_PCREL16;
1103 break;
4f996613
ILT		 1104 case BFD_RELOC_PCREL_HI16_S:
1105 mips_type = MIPS_R_RELHI;
1106 break;
1107 case BFD_RELOC_PCREL_LO16:
1108 mips_type = MIPS_R_RELLO;
1109 break;
dabf906e
ILT		 1110 case BFD_RELOC_GPREL32:
1111 mips_type = MIPS_R_SWITCH;
1112 break;
23f44e6f 1113 default:
a5655244 1114 return (reloc_howto_type *) NULL;
23f44e6f
ILT		 1115 }
1116
1117 return &mips_howto_table[mips_type];
1118}
c3fe0c41 1119\f
4991ebb9 1120/* A helper routine for mips_relocate_section which handles the REFHI
4f996613
ILT		 1121 and RELHI relocations. The REFHI relocation must be followed by a
1122 REFLO relocation (and RELHI by a RELLO), and the addend used is
1123 formed from the addends of both instructions. */
de17306e 1124
4991ebb9 1125static void
4f996613
ILT		 1126mips_relocate_hi (refhi, reflo, input_bfd, input_section, contents, adjust,
1127 relocation, pcrel)
4991ebb9
ILT		 1128 struct internal_reloc *refhi;
1129 struct internal_reloc *reflo;
1130 bfd *input_bfd;
1131 asection *input_section;
1132 bfd_byte *contents;
a3a33af3 1133 size_t adjust;
4991ebb9 1134 bfd_vma relocation;
4f996613 1135 boolean pcrel;
de17306e 1136{
4991ebb9
ILT		 1137 unsigned long insn;
1138 unsigned long val;
1139 unsigned long vallo;
1140
1141 insn = bfd_get_32 (input_bfd,
a3a33af3 1142 contents + adjust + refhi->r_vaddr - input_section->vma);
4991ebb9 1143 vallo = (bfd_get_32 (input_bfd,
a3a33af3 1144 contents + adjust + reflo->r_vaddr - input_section->vma)
4991ebb9
ILT		 1145 & 0xffff);
1146 val = ((insn & 0xffff) << 16) + vallo;
1147 val += relocation;
1148
1149 /* The low order 16 bits are always treated as a signed value.
1150 Therefore, a negative value in the low order bits requires an
1151 adjustment in the high order bits. We need to make this
1152 adjustment in two ways: once for the bits we took from the data,
1153 and once for the bits we are putting back in to the data. */
1154 if ((vallo & 0x8000) != 0)
1155 val -= 0x10000;
4f996613
ILT		 1156
1157 if (pcrel)
1158 val -= (input_section->output_section->vma
1159 + input_section->output_offset
1160 + (reflo->r_vaddr - input_section->vma + adjust));
1161
4991ebb9
ILT		 1162 if ((val & 0x8000) != 0)
1163 val += 0x10000;
de17306e 1164
4991ebb9
ILT		 1165 insn = (insn &~ 0xffff) | ((val >> 16) & 0xffff);
1166 bfd_put_32 (input_bfd, (bfd_vma) insn,
a3a33af3 1167 contents + adjust + refhi->r_vaddr - input_section->vma);
4991ebb9 1168}
de17306e 1169
4991ebb9 1170/* Relocate a section while linking a MIPS ECOFF file. */
de17306e 1171
4991ebb9
ILT		 1172static boolean
1173mips_relocate_section (output_bfd, info, input_bfd, input_section,
1174 contents, external_relocs)
1175 bfd *output_bfd;
1176 struct bfd_link_info *info;
1177 bfd *input_bfd;
1178 asection *input_section;
1179 bfd_byte *contents;
1180 PTR external_relocs;
1181{
1182 asection **symndx_to_section;
1183 struct ecoff_link_hash_entry **sym_hashes;
1184 bfd_vma gp;
1185 boolean gp_undefined;
a3a33af3
ILT		 1186 size_t adjust;
1187 long *offsets;
4991ebb9
ILT		 1188 struct external_reloc *ext_rel;
1189 struct external_reloc *ext_rel_end;
a3a33af3 1190 unsigned int i;
4f996613
ILT		 1191 boolean got_lo;
1192 struct internal_reloc lo_int_rel;
4991ebb9 1193
64d5f5d0
ILT		 1194 BFD_ASSERT (input_bfd->xvec->header_byteorder
1195 == output_bfd->xvec->header_byteorder);
4991ebb9
ILT		 1196
1197 /* We keep a table mapping the symndx found in an internal reloc to
1198 the appropriate section. This is faster than looking up the
1199 section by name each time. */
1200 symndx_to_section = ecoff_data (input_bfd)->symndx_to_section;
1201 if (symndx_to_section == (asection **) NULL)
1202 {
1203 symndx_to_section = ((asection **)
1204 bfd_alloc (input_bfd,
1205 (NUM_RELOC_SECTIONS
1206 * sizeof (asection *))));
9783e04a 1207 if (!symndx_to_section)
a9713b91 1208 return false;
4991ebb9
ILT		 1209
1210 symndx_to_section[RELOC_SECTION_NONE] = NULL;
1211 symndx_to_section[RELOC_SECTION_TEXT] =
1212 bfd_get_section_by_name (input_bfd, ".text");
1213 symndx_to_section[RELOC_SECTION_RDATA] =
1214 bfd_get_section_by_name (input_bfd, ".rdata");
1215 symndx_to_section[RELOC_SECTION_DATA] =
1216 bfd_get_section_by_name (input_bfd, ".data");
1217 symndx_to_section[RELOC_SECTION_SDATA] =
1218 bfd_get_section_by_name (input_bfd, ".sdata");
1219 symndx_to_section[RELOC_SECTION_SBSS] =
1220 bfd_get_section_by_name (input_bfd, ".sbss");
1221 symndx_to_section[RELOC_SECTION_BSS] =
1222 bfd_get_section_by_name (input_bfd, ".bss");
1223 symndx_to_section[RELOC_SECTION_INIT] =
1224 bfd_get_section_by_name (input_bfd, ".init");
1225 symndx_to_section[RELOC_SECTION_LIT8] =
1226 bfd_get_section_by_name (input_bfd, ".lit8");
1227 symndx_to_section[RELOC_SECTION_LIT4] =
1228 bfd_get_section_by_name (input_bfd, ".lit4");
1229 symndx_to_section[RELOC_SECTION_XDATA] = NULL;
1230 symndx_to_section[RELOC_SECTION_PDATA] = NULL;
1231 symndx_to_section[RELOC_SECTION_FINI] =
1232 bfd_get_section_by_name (input_bfd, ".fini");
1233 symndx_to_section[RELOC_SECTION_LITA] = NULL;
1234 symndx_to_section[RELOC_SECTION_ABS] = NULL;
1235
1236 ecoff_data (input_bfd)->symndx_to_section = symndx_to_section;
1237 }
de17306e 1238
4991ebb9 1239 sym_hashes = ecoff_data (input_bfd)->sym_hashes;
de17306e 1240
cba3f8a9 1241 gp = _bfd_get_gp_value (output_bfd);
4991ebb9
ILT		 1242 if (gp == 0)
1243 gp_undefined = true;
1244 else
1245 gp_undefined = false;
de17306e 1246
4f996613 1247 got_lo = false;
de17306e 1248
a3a33af3
ILT		 1249 adjust = 0;
1250
1251 if (ecoff_section_data (input_bfd, input_section) == NULL)
1252 offsets = NULL;
1253 else
1254 offsets = ecoff_section_data (input_bfd, input_section)->offsets;
1255
4991ebb9
ILT		 1256 ext_rel = (struct external_reloc *) external_relocs;
1257 ext_rel_end = ext_rel + input_section->reloc_count;
a3a33af3 1258 for (i = 0; ext_rel < ext_rel_end; ext_rel++, i++)
4991ebb9
ILT		 1259 {
1260 struct internal_reloc int_rel;
4991ebb9
ILT		 1261 bfd_vma addend;
1262 reloc_howto_type *howto;
1263 struct ecoff_link_hash_entry *h = NULL;
1264 asection *s = NULL;
1265 bfd_vma relocation;
1266 bfd_reloc_status_type r;
1267
4f996613 1268 if (! got_lo)
4991ebb9
ILT		 1269 mips_ecoff_swap_reloc_in (input_bfd, (PTR) ext_rel, &int_rel);
1270 else
1271 {
4f996613
ILT		 1272 int_rel = lo_int_rel;
1273 got_lo = false;
4991ebb9 1274 }
de17306e 1275
4991ebb9
ILT		 1276 BFD_ASSERT (int_rel.r_type
1277 < sizeof mips_howto_table / sizeof mips_howto_table[0]);
de17306e 1278
4f996613
ILT		 1279 /* The REFHI and RELHI relocs requires special handling. they
1280 must be followed by a REFLO or RELLO reloc, respectively, and
1281 the addend is formed from both relocs. */
1282 if (int_rel.r_type == MIPS_R_REFHI
1283 || int_rel.r_type == MIPS_R_RELHI)
4991ebb9
ILT		 1284 {
1285 BFD_ASSERT ((ext_rel + 1) < ext_rel_end);
1286 mips_ecoff_swap_reloc_in (input_bfd, (PTR) (ext_rel + 1),
4f996613
ILT		 1287 &lo_int_rel);
1288 BFD_ASSERT ((lo_int_rel.r_type
1289 == (int_rel.r_type == MIPS_R_REFHI
1290 ? MIPS_R_REFLO
1291 : MIPS_R_RELLO))
1292 && int_rel.r_extern == lo_int_rel.r_extern
1293 && int_rel.r_symndx == lo_int_rel.r_symndx);
1294 got_lo = true;
4991ebb9 1295 }
de17306e 1296
4991ebb9 1297 howto = &mips_howto_table[int_rel.r_type];
de17306e 1298
dabf906e
ILT		 1299 /* The SWITCH reloc must be handled specially. This reloc is
1300 marks the location of a difference between two portions of an
1301 object file. The symbol index does not reference a symbol,
1302 but is actually the offset from the reloc to the subtrahend
1303 of the difference. This reloc is correct in the object file,
1304 and needs no further adjustment, unless we are relaxing. If
1305 we are relaxing, we may have to add in an offset. Since no
1306 symbols are involved in this reloc, we handle it completely
1307 here. */
1308 if (int_rel.r_type == MIPS_R_SWITCH)
1309 {
1310 if (offsets != NULL
1311 && offsets[i] != 0)
1312 {
1313 r = _bfd_relocate_contents (howto, input_bfd,
1314 (bfd_vma) offsets[i],
1315 (contents
1316 + adjust
1317 + int_rel.r_vaddr
1318 - input_section->vma));
1319 BFD_ASSERT (r == bfd_reloc_ok);
1320 }
1321
1322 continue;
1323 }
1324
4991ebb9
ILT		 1325 if (int_rel.r_extern)
1326 {
1327 h = sym_hashes[int_rel.r_symndx];
1328 /* If h is NULL, that means that there is a reloc against an
1329 external symbol which we thought was just a debugging
1330 symbol. This should not happen. */
1331 if (h == (struct ecoff_link_hash_entry *) NULL)
1332 abort ();
1333 }
1334 else
1335 {
1336 if (int_rel.r_symndx < 0 || int_rel.r_symndx >= NUM_RELOC_SECTIONS)
1337 s = NULL;
1338 else
1339 s = symndx_to_section[int_rel.r_symndx];
de17306e 1340
4991ebb9
ILT		 1341 if (s == (asection *) NULL)
1342 abort ();
1343 }
de17306e 1344
4991ebb9
ILT		 1345 /* The GPREL reloc uses an addend: the difference in the GP
1346 values. */
f1cca647
ILT		 1347 if (int_rel.r_type != MIPS_R_GPREL
1348 && int_rel.r_type != MIPS_R_LITERAL)
4991ebb9
ILT		 1349 addend = 0;
1350 else
de17306e 1351 {
4991ebb9
ILT		 1352 if (gp_undefined)
1353 {
1354 if (! ((*info->callbacks->reloc_dangerous)
1355 (info, "GP relative relocation when GP not defined",
1356 input_bfd, input_section,
1357 int_rel.r_vaddr - input_section->vma)))
1358 return false;
1359 /* Only give the error once per link. */
cba3f8a9
ILT		 1360 gp = 4;
1361 _bfd_set_gp_value (output_bfd, gp);
4991ebb9
ILT		 1362 gp_undefined = false;
1363 }
1364 if (! int_rel.r_extern)
1365 {
1366 /* This is a relocation against a section. The current
1367 addend in the instruction is the difference between
1368 INPUT_SECTION->vma and the GP value of INPUT_BFD. We
1369 must change this to be the difference between the
1370 final definition (which will end up in RELOCATION)
1371 and the GP value of OUTPUT_BFD (which is in GP). */
1372 addend = ecoff_data (input_bfd)->gp - gp;
1373 }
1374 else if (! info->relocateable
a5655244
ILT		 1375 || h->root.type == bfd_link_hash_defined
1376 || h->root.type == bfd_link_hash_defweak)
4991ebb9 1377 {
a5655244
ILT		 1378 /* This is a relocation against a defined symbol. The
1379 current addend in the instruction is simply the
1380 desired offset into the symbol (normally zero). We
1381 are going to change this into a relocation against a
1382 defined symbol, so we want the instruction to hold
1383 the difference between the final definition of the
1384 symbol (which will end up in RELOCATION) and the GP
1385 value of OUTPUT_BFD (which is in GP). */
4991ebb9
ILT		 1386 addend = - gp;
1387 }
1388 else
1389 {
1390 /* This is a relocation against an undefined or common
1391 symbol. The current addend in the instruction is
1392 simply the desired offset into the symbol (normally
1393 zero). We are generating relocateable output, and we
1394 aren't going to define this symbol, so we just leave
1395 the instruction alone. */
1396 addend = 0;
1397 }
de17306e
ILT		 1398 }
1399
a3a33af3
ILT		 1400 /* If we are relaxing, mips_relax_section may have set
1401 offsets[i] to some value. A value of 1 means we must expand
1402 a PC relative branch into a multi-instruction of sequence,
1403 and any other value is an addend. */
1404 if (offsets != NULL
1405 && offsets[i] != 0)
1406 {
1407 BFD_ASSERT (! info->relocateable);
4f996613
ILT		 1408 BFD_ASSERT (int_rel.r_type == MIPS_R_PCREL16
1409 || int_rel.r_type == MIPS_R_RELHI
1410 || int_rel.r_type == MIPS_R_RELLO);
a3a33af3 1411 if (offsets[i] != 1)
4f996613 1412 addend += offsets[i];
a3a33af3
ILT		 1413 else
1414 {
1415 bfd_byte *here;
1416
4f996613
ILT		 1417 BFD_ASSERT (int_rel.r_extern
1418 && int_rel.r_type == MIPS_R_PCREL16);
a3a33af3
ILT		 1419
1420 /* Move the rest of the instructions up. */
1421 here = (contents
1422 + adjust
1423 + int_rel.r_vaddr
1424 - input_section->vma);
1425 memmove (here + PCREL16_EXPANSION_ADJUSTMENT, here,
a5655244
ILT		 1426 (size_t) (input_section->_raw_size
1427 - (int_rel.r_vaddr - input_section->vma)));
a3a33af3
ILT		 1428
1429 /* Generate the new instructions. */
1430 if (! mips_relax_pcrel16 (info, input_bfd, input_section,
1431 h, here,
1432 (input_section->output_section->vma
1433 + input_section->output_offset
1434 + (int_rel.r_vaddr
1435 - input_section->vma)
1436 + adjust)))
1437 return false;
1438
1439 /* We must adjust everything else up a notch. */
1440 adjust += PCREL16_EXPANSION_ADJUSTMENT;
1441
1442 /* mips_relax_pcrel16 handles all the details of this
1443 relocation. */
1444 continue;
1445 }
1446 }
1447
ac9ed096
ILT		 1448 /* If we are relaxing, and this is a reloc against the .text
1449 segment, we may need to adjust it if some branches have been
1450 expanded. The reloc types which are likely to occur in the
1451 .text section are handled efficiently by mips_relax_section,
1452 and thus do not need to be handled here. */
1453 if (ecoff_data (input_bfd)->debug_info.adjust != NULL
1454 && ! int_rel.r_extern
1455 && int_rel.r_symndx == RELOC_SECTION_TEXT
1456 && (strcmp (bfd_get_section_name (input_bfd, input_section),
1457 ".text") != 0
1458 || (int_rel.r_type != MIPS_R_PCREL16
1459 && int_rel.r_type != MIPS_R_SWITCH
1460 && int_rel.r_type != MIPS_R_RELHI
1461 && int_rel.r_type != MIPS_R_RELLO)))
1462 {
1463 bfd_vma adr;
1464 struct ecoff_value_adjust *a;
1465
1466 /* We need to get the addend so that we know whether we need
1467 to adjust the address. */
1468 BFD_ASSERT (int_rel.r_type == MIPS_R_REFWORD);
1469
1470 adr = bfd_get_32 (input_bfd,
1471 (contents
1472 + adjust
1473 + int_rel.r_vaddr
1474 - input_section->vma));
1475
1476 for (a = ecoff_data (input_bfd)->debug_info.adjust;
1477 a != (struct ecoff_value_adjust *) NULL;
1478 a = a->next)
1479 {
1480 if (adr >= a->start && adr < a->end)
1481 addend += a->adjust;
1482 }
1483 }
1484
4991ebb9
ILT		 1485 if (info->relocateable)
1486 {
1487 /* We are generating relocateable output, and must convert
1488 the existing reloc. */
1489 if (int_rel.r_extern)
1490 {
a5655244
ILT		 1491 if ((h->root.type == bfd_link_hash_defined
1492 || h->root.type == bfd_link_hash_defweak)
1493 && ! bfd_is_abs_section (h->root.u.def.section))
4991ebb9 1494 {
4991ebb9 1495 const char *name;
de17306e 1496
4991ebb9
ILT		 1497 /* This symbol is defined in the output. Convert
1498 the reloc from being against the symbol to being
1499 against the section. */
de17306e 1500
4991ebb9
ILT		 1501 /* Clear the r_extern bit. */
1502 int_rel.r_extern = 0;
de17306e 1503
4991ebb9 1504 /* Compute a new r_symndx value. */
a3a33af3 1505 s = h->root.u.def.section;
4991ebb9 1506 name = bfd_get_section_name (output_bfd,
a3a33af3 1507 s->output_section);
de17306e 1508
4991ebb9
ILT		 1509 int_rel.r_symndx = -1;
1510 switch (name[1])
1511 {
1512 case 'b':
1513 if (strcmp (name, ".bss") == 0)
1514 int_rel.r_symndx = RELOC_SECTION_BSS;
1515 break;
1516 case 'd':
1517 if (strcmp (name, ".data") == 0)
1518 int_rel.r_symndx = RELOC_SECTION_DATA;
1519 break;
1520 case 'f':
1521 if (strcmp (name, ".fini") == 0)
1522 int_rel.r_symndx = RELOC_SECTION_FINI;
1523 break;
1524 case 'i':
1525 if (strcmp (name, ".init") == 0)
1526 int_rel.r_symndx = RELOC_SECTION_INIT;
1527 break;
1528 case 'l':
1529 if (strcmp (name, ".lit8") == 0)
1530 int_rel.r_symndx = RELOC_SECTION_LIT8;
1531 else if (strcmp (name, ".lit4") == 0)
1532 int_rel.r_symndx = RELOC_SECTION_LIT4;
1533 break;
1534 case 'r':
1535 if (strcmp (name, ".rdata") == 0)
1536 int_rel.r_symndx = RELOC_SECTION_RDATA;
1537 break;
1538 case 's':
1539 if (strcmp (name, ".sdata") == 0)
1540 int_rel.r_symndx = RELOC_SECTION_SDATA;
1541 else if (strcmp (name, ".sbss") == 0)
1542 int_rel.r_symndx = RELOC_SECTION_SBSS;
1543 break;
1544 case 't':
1545 if (strcmp (name, ".text") == 0)
1546 int_rel.r_symndx = RELOC_SECTION_TEXT;
1547 break;
1548 }
1549
1550 if (int_rel.r_symndx == -1)
1551 abort ();
1552
1553 /* Add the section VMA and the symbol value. */
1554 relocation = (h->root.u.def.value
a3a33af3
ILT		 1555 + s->output_section->vma
1556 + s->output_offset);
1557
1558 /* For a PC relative relocation, the object file
1559 currently holds just the addend. We must adjust
1560 by the address to get the right value. */
1561 if (howto->pc_relative)
4f996613
ILT		 1562 {
1563 relocation -= int_rel.r_vaddr - input_section->vma;
1564
1565 /* If we are converting a RELHI or RELLO reloc
1566 from being against an external symbol to
1567 being against a section, we must put a
1568 special value into the r_offset field. This
1569 value is the old addend. The r_offset for
1570 both the RELOHI and RELLO relocs are the
1571 same, and we set both when we see RELHI. */
1572 if (int_rel.r_type == MIPS_R_RELHI)
1573 {
1574 long addhi, addlo;
1575
1576 addhi = bfd_get_32 (input_bfd,
1577 (contents
1578 + adjust
1579 + int_rel.r_vaddr
1580 - input_section->vma));
1581 addhi &= 0xffff;
1582 if (addhi & 0x8000)
1583 addhi -= 0x10000;
1584 addhi <<= 16;
1585
1586 addlo = bfd_get_32 (input_bfd,
1587 (contents
1588 + adjust
1589 + lo_int_rel.r_vaddr
1590 - input_section->vma));
1591 addlo &= 0xffff;
1592 if (addlo & 0x8000)
1593 addlo -= 0x10000;
1594
1595 int_rel.r_offset = addhi + addlo;
1596 lo_int_rel.r_offset = int_rel.r_offset;
1597 }
1598 }
a3a33af3
ILT		 1599
1600 h = NULL;
4991ebb9
ILT		 1601 }
1602 else
1603 {
1604 /* Change the symndx value to the right one for the
1605 output BFD. */
1606 int_rel.r_symndx = h->indx;
1607 if (int_rel.r_symndx == -1)
1608 {
1609 /* This symbol is not being written out. */
1610 if (! ((*info->callbacks->unattached_reloc)
1611 (info, h->root.root.string, input_bfd,
1612 input_section,
1613 int_rel.r_vaddr - input_section->vma)))
1614 return false;
1615 int_rel.r_symndx = 0;
1616 }
1617 relocation = 0;
1618 }
1619 }
1620 else
1621 {
1622 /* This is a relocation against a section. Adjust the
1623 value by the amount the section moved. */
1624 relocation = (s->output_section->vma
1625 + s->output_offset
1626 - s->vma);
1627 }
de17306e 1628
4991ebb9 1629 relocation += addend;
ac9ed096 1630 addend = 0;
de17306e 1631
a3a33af3
ILT		 1632 /* Adjust a PC relative relocation by removing the reference
1633 to the original address in the section and including the
4f996613
ILT		 1634 reference to the new address. However, external RELHI
1635 and RELLO relocs are PC relative, but don't include any
1636 reference to the address. The addend is merely an
1637 addend. */
1638 if (howto->pc_relative
1639 && (! int_rel.r_extern
1640 || (int_rel.r_type != MIPS_R_RELHI
1641 && int_rel.r_type != MIPS_R_RELLO)))
a3a33af3
ILT		 1642 relocation -= (input_section->output_section->vma
1643 + input_section->output_offset
1644 - input_section->vma);
1645
4991ebb9
ILT		 1646 /* Adjust the contents. */
1647 if (relocation == 0)
1648 r = bfd_reloc_ok;
1649 else
1650 {
4f996613
ILT		 1651 if (int_rel.r_type != MIPS_R_REFHI
1652 && int_rel.r_type != MIPS_R_RELHI)
4991ebb9
ILT		 1653 r = _bfd_relocate_contents (howto, input_bfd, relocation,
1654 (contents
a3a33af3 1655 + adjust
4991ebb9
ILT		 1656 + int_rel.r_vaddr
1657 - input_section->vma));
1658 else
1659 {
4f996613
ILT		 1660 mips_relocate_hi (&int_rel, &lo_int_rel,
1661 input_bfd, input_section, contents,
1662 adjust, relocation,
1663 int_rel.r_type == MIPS_R_RELHI);
4991ebb9
ILT		 1664 r = bfd_reloc_ok;
1665 }
1666 }
de17306e 1667
4991ebb9
ILT		 1668 /* Adjust the reloc address. */
1669 int_rel.r_vaddr += (input_section->output_section->vma
1670 + input_section->output_offset
1671 - input_section->vma);
de17306e 1672
4991ebb9
ILT		 1673 /* Save the changed reloc information. */
1674 mips_ecoff_swap_reloc_out (input_bfd, &int_rel, (PTR) ext_rel);
1675 }
1676 else
1677 {
1678 /* We are producing a final executable. */
1679 if (int_rel.r_extern)
1680 {
1681 /* This is a reloc against a symbol. */
a5655244
ILT		 1682 if (h->root.type == bfd_link_hash_defined
1683 || h->root.type == bfd_link_hash_defweak)
4991ebb9
ILT		 1684 {
1685 asection *hsec;
de17306e 1686
4991ebb9
ILT		 1687 hsec = h->root.u.def.section;
1688 relocation = (h->root.u.def.value
1689 + hsec->output_section->vma
1690 + hsec->output_offset);
1691 }
1692 else
1693 {
1694 if (! ((*info->callbacks->undefined_symbol)
1695 (info, h->root.root.string, input_bfd,
1696 input_section,
1697 int_rel.r_vaddr - input_section->vma)))
1698 return false;
1699 relocation = 0;
1700 }
1701 }
1702 else
1703 {
1704 /* This is a reloc against a section. */
1705 relocation = (s->output_section->vma
1706 + s->output_offset
1707 - s->vma);
1708
a3a33af3
ILT		 1709 /* A PC relative reloc is already correct in the object
1710 file. Make it look like a pcrel_offset relocation by
1711 adding in the start address. */
4991ebb9 1712 if (howto->pc_relative)
4f996613
ILT		 1713 {
1714 if (int_rel.r_type != MIPS_R_RELHI)
1715 relocation += int_rel.r_vaddr + adjust;
1716 else
1717 relocation += lo_int_rel.r_vaddr + adjust;
1718 }
4991ebb9 1719 }
de17306e 1720
4f996613
ILT		 1721 if (int_rel.r_type != MIPS_R_REFHI
1722 && int_rel.r_type != MIPS_R_RELHI)
4991ebb9
ILT		 1723 r = _bfd_final_link_relocate (howto,
1724 input_bfd,
1725 input_section,
1726 contents,
a3a33af3
ILT		 1727 (int_rel.r_vaddr
1728 - input_section->vma
1729 + adjust),
4991ebb9
ILT		 1730 relocation,
1731 addend);
1732 else
1733 {
4f996613
ILT		 1734 mips_relocate_hi (&int_rel, &lo_int_rel, input_bfd,
1735 input_section, contents, adjust,
1736 relocation,
1737 int_rel.r_type == MIPS_R_RELHI);
4991ebb9
ILT		 1738 r = bfd_reloc_ok;
1739 }
1740 }
1741
ac9ed096
ILT		 1742 /* MIPS_R_JMPADDR requires peculiar overflow detection. The
1743 instruction provides a 28 bit address (the two lower bits are
1744 implicit zeroes) which is combined with the upper four bits
1745 of the instruction address. */
1746 if (r == bfd_reloc_ok
1747 && int_rel.r_type == MIPS_R_JMPADDR
1748 && (((relocation
1749 + addend
1750 + (int_rel.r_extern ? 0 : s->vma))
1751 & 0xf0000000)
1752 != ((input_section->output_section->vma
1753 + input_section->output_offset
1754 + (int_rel.r_vaddr - input_section->vma)
1755 + adjust)
1756 & 0xf0000000)))
1757 r = bfd_reloc_overflow;
1758
4991ebb9
ILT		 1759 if (r != bfd_reloc_ok)
1760 {
1761 switch (r)
1762 {
1763 default:
1764 case bfd_reloc_outofrange:
1765 abort ();
1766 case bfd_reloc_overflow:
1767 {
1768 const char *name;
1769
1770 if (int_rel.r_extern)
1771 name = h->root.root.string;
1772 else
1773 name = bfd_section_name (input_bfd, s);
1774 if (! ((*info->callbacks->reloc_overflow)
1775 (info, name, howto->name, (bfd_vma) 0,
1776 input_bfd, input_section,
1777 int_rel.r_vaddr - input_section->vma)))
1778 return false;
1779 }
1780 break;
1781 }
1782 }
1783 }
1784
1785 return true;
de17306e 1786}
de17306e 1787\f
a5655244
ILT		 1788/* Read in the relocs for a section. */
1789
1790static boolean
1791mips_read_relocs (abfd, sec)
1792 bfd *abfd;
1793 asection *sec;
1794{
1795 struct ecoff_section_tdata *section_tdata;
1796
1797 section_tdata = ecoff_section_data (abfd, sec);
1798 if (section_tdata == (struct ecoff_section_tdata *) NULL)
1799 {
1800 sec->used_by_bfd =
1801 (PTR) bfd_alloc_by_size_t (abfd, sizeof (struct ecoff_section_tdata));
1802 if (sec->used_by_bfd == NULL)
a9713b91 1803 return false;
a5655244
ILT		 1804
1805 section_tdata = ecoff_section_data (abfd, sec);
1806 section_tdata->external_relocs = NULL;
1807 section_tdata->contents = NULL;
1808 section_tdata->offsets = NULL;
1809 }
1810
1811 if (section_tdata->external_relocs == NULL)
1812 {
1813 bfd_size_type external_relocs_size;
1814
1815 external_relocs_size = (ecoff_backend (abfd)->external_reloc_size
1816 * sec->reloc_count);
1817
1818 section_tdata->external_relocs =
1819 (PTR) bfd_alloc (abfd, external_relocs_size);
1820 if (section_tdata->external_relocs == NULL && external_relocs_size != 0)
a9713b91 1821 return false;
a5655244
ILT		 1822
1823 if (bfd_seek (abfd, sec->rel_filepos, SEEK_SET) != 0
1824 || (bfd_read (section_tdata->external_relocs, 1,
1825 external_relocs_size, abfd)
1826 != external_relocs_size))
1827 return false;
1828 }
1829
1830 return true;
1831}
1832
a3a33af3
ILT		 1833/* Relax a section when linking a MIPS ECOFF file. This is used for
1834 embedded PIC code, which always uses PC relative branches which
1835 only have an 18 bit range on MIPS. If a branch is not in range, we
1836 generate a long instruction sequence to compensate. Each time we
1837 find a branch to expand, we have to check all the others again to
1838 make sure they are still in range. This is slow, but it only has
1839 to be done when -relax is passed to the linker.
1840
1841 This routine figures out which branches need to expand; the actual
1842 expansion is done in mips_relocate_section when the section
1843 contents are relocated. The information is stored in the offsets
1844 field of the ecoff_section_tdata structure. An offset of 1 means
1845 that the branch must be expanded into a multi-instruction PC
1846 relative branch (such an offset will only occur for a PC relative
1847 branch to an external symbol). Any other offset must be a multiple
1848 of four, and is the amount to change the branch by (such an offset
1849 will only occur for a PC relative branch within the same section).
1850
1851 We do not modify the section relocs or contents themselves so that
1852 if memory usage becomes an issue we can discard them and read them
1853 again. The only information we must save in memory between this
1854 routine and the mips_relocate_section routine is the table of
1855 offsets. */
1856
1857static boolean
1858mips_relax_section (abfd, sec, info, again)
1859 bfd *abfd;
1860 asection *sec;
1861 struct bfd_link_info *info;
1862 boolean *again;
1863{
1864 struct ecoff_section_tdata *section_tdata;
1865 bfd_byte *contents = NULL;
1866 long *offsets;
1867 struct external_reloc *ext_rel;
1868 struct external_reloc *ext_rel_end;
1869 unsigned int i;
1870
1871 /* Assume we are not going to need another pass. */
1872 *again = false;
1873
1874 /* If we are not generating an ECOFF file, this is much too
1875 confusing to deal with. */
1876 if (info->hash->creator->flavour != bfd_get_flavour (abfd))
1877 return true;
1878
1879 /* If there are no relocs, there is nothing to do. */
1880 if (sec->reloc_count == 0)
1881 return true;
1882
1883 /* We are only interested in PC relative relocs, and why would there
1884 ever be one from anything but the .text section? */
1885 if (strcmp (bfd_get_section_name (abfd, sec), ".text") != 0)
1886 return true;
1887
1888 /* Read in the relocs, if we haven't already got them. */
1889 section_tdata = ecoff_section_data (abfd, sec);
a5655244
ILT		 1890 if (section_tdata == (struct ecoff_section_tdata *) NULL
1891 || section_tdata->external_relocs == NULL)
a3a33af3 1892 {
a5655244 1893 if (! mips_read_relocs (abfd, sec))
a3a33af3 1894 goto error_return;
a5655244
ILT		 1895 section_tdata = ecoff_section_data (abfd, sec);
1896 }
a3a33af3 1897
a5655244
ILT		 1898 if (sec->_cooked_size == 0)
1899 {
a3a33af3
ILT		 1900 /* We must initialize _cooked_size only the first time we are
1901 called. */
1902 sec->_cooked_size = sec->_raw_size;
1903 }
1904
1905 contents = section_tdata->contents;
1906 offsets = section_tdata->offsets;
1907
1908 /* Look for any external PC relative relocs. Internal PC relative
1909 relocs are already correct in the object file, so they certainly
1910 can not overflow. */
1911 ext_rel = (struct external_reloc *) section_tdata->external_relocs;
1912 ext_rel_end = ext_rel + sec->reloc_count;
1913 for (i = 0; ext_rel < ext_rel_end; ext_rel++, i++)
1914 {
1915 struct internal_reloc int_rel;
1916 struct ecoff_link_hash_entry *h;
1917 asection *hsec;
1918 bfd_signed_vma relocation;
1919 struct external_reloc *adj_ext_rel;
1920 unsigned int adj_i;
1921 unsigned long ext_count;
1922 struct ecoff_link_hash_entry **adj_h_ptr;
1923 struct ecoff_link_hash_entry **adj_h_ptr_end;
1924 struct ecoff_value_adjust *adjust;
1925
1926 /* If we have already expanded this reloc, we certainly don't
1927 need to do it again. */
1928 if (offsets != (long *) NULL && offsets[i] == 1)
1929 continue;
1930
1931 /* Quickly check that this reloc is external PCREL16. */
64d5f5d0 1932 if (bfd_header_big_endian (abfd))
a3a33af3
ILT		 1933 {
1934 if ((ext_rel->r_bits[3] & RELOC_BITS3_EXTERN_BIG) == 0
1935 || (((ext_rel->r_bits[3] & RELOC_BITS3_TYPE_BIG)
1936 >> RELOC_BITS3_TYPE_SH_BIG)
1937 != MIPS_R_PCREL16))
1938 continue;
1939 }
1940 else
1941 {
1942 if ((ext_rel->r_bits[3] & RELOC_BITS3_EXTERN_LITTLE) == 0
1943 || (((ext_rel->r_bits[3] & RELOC_BITS3_TYPE_LITTLE)
1944 >> RELOC_BITS3_TYPE_SH_LITTLE)
1945 != MIPS_R_PCREL16))
1946 continue;
1947 }
1948
1949 mips_ecoff_swap_reloc_in (abfd, (PTR) ext_rel, &int_rel);
1950
1951 h = ecoff_data (abfd)->sym_hashes[int_rel.r_symndx];
1952 if (h == (struct ecoff_link_hash_entry *) NULL)
1953 abort ();
1954
a5655244
ILT		 1955 if (h->root.type != bfd_link_hash_defined
1956 && h->root.type != bfd_link_hash_defweak)
a3a33af3
ILT		 1957 {
1958 /* Just ignore undefined symbols. These will presumably
1959 generate an error later in the link. */
1960 continue;
1961 }
1962
1963 /* Get the value of the symbol. */
1964 hsec = h->root.u.def.section;
1965 relocation = (h->root.u.def.value
1966 + hsec->output_section->vma
1967 + hsec->output_offset);
1968
1969 /* Subtract out the current address. */
1970 relocation -= (sec->output_section->vma
1971 + sec->output_offset
1972 + (int_rel.r_vaddr - sec->vma));
1973
1974 /* The addend is stored in the object file. In the normal case
1975 of ``bal symbol'', the addend will be -4. It will only be
1976 different in the case of ``bal symbol+constant''. To avoid
1977 always reading in the section contents, we don't check the
1978 addend in the object file (we could easily check the contents
1979 if we happen to have already read them in, but I fear that
1980 this could be confusing). This means we will screw up if
1981 there is a branch to a symbol that is in range, but added to
1982 a constant which puts it out of range; in such a case the
1983 link will fail with a reloc overflow error. Since the
1984 compiler will never generate such code, it should be easy
1985 enough to work around it by changing the assembly code in the
1986 source file. */
1987 relocation -= 4;
1988
1989 /* Now RELOCATION is the number we want to put in the object
1990 file. See whether it fits. */
1991 if (relocation >= -0x20000 && relocation < 0x20000)
1992 continue;
1993
1994 /* Now that we know this reloc needs work, which will rarely
1995 happen, go ahead and grab the section contents. */
1996 if (contents == (bfd_byte *) NULL)
1997 {
1998 if (info->keep_memory)
1999 contents = (bfd_byte *) bfd_alloc (abfd, sec->_raw_size);
2000 else
58142f10 2001 contents = (bfd_byte *) bfd_malloc ((size_t) sec->_raw_size);
a3a33af3 2002 if (contents == (bfd_byte *) NULL)
58142f10 2003 goto error_return;
a3a33af3
ILT		 2004 if (! bfd_get_section_contents (abfd, sec, (PTR) contents,
2005 (file_ptr) 0, sec->_raw_size))
2006 goto error_return;
2007 if (info->keep_memory)
2008 section_tdata->contents = contents;
2009 }
2010
2011 /* We only support changing the bal instruction. It would be
2012 possible to handle other PC relative branches, but some of
2013 them (the conditional branches) would require a different
2014 length instruction sequence which would complicate both this
2015 routine and mips_relax_pcrel16. It could be written if
2016 somebody felt it were important. Ignoring this reloc will
2017 presumably cause a reloc overflow error later on. */
2018 if (bfd_get_32 (abfd, contents + int_rel.r_vaddr - sec->vma)
2019 != 0x0411ffff) /* bgezal $0,. == bal . */
2020 continue;
2021
2022 /* Bother. We need to expand this reloc, and we will need to
2023 make another relaxation pass since this change may put other
2024 relocs out of range. We need to examine the local branches
2025 and we need to allocate memory to hold the offsets we must
2026 add to them. We also need to adjust the values of all
2027 symbols in the object file following this location. */
2028
2029 sec->_cooked_size += PCREL16_EXPANSION_ADJUSTMENT;
2030 *again = true;
2031
2032 if (offsets == (long *) NULL)
2033 {
2034 size_t size;
2035
2036 size = sec->reloc_count * sizeof (long);
2037 offsets = (long *) bfd_alloc_by_size_t (abfd, size);
2038 if (offsets == (long *) NULL)
a9713b91 2039 goto error_return;
a3a33af3
ILT		 2040 memset (offsets, 0, size);
2041 section_tdata->offsets = offsets;
2042 }
2043
2044 offsets[i] = 1;
2045
4f996613
ILT		 2046 /* Now look for all PC relative references that cross this reloc
2047 and adjust their offsets. */
a3a33af3
ILT		 2048 adj_ext_rel = (struct external_reloc *) section_tdata->external_relocs;
2049 for (adj_i = 0; adj_ext_rel < ext_rel_end; adj_ext_rel++, adj_i++)
2050 {
2051 struct internal_reloc adj_int_rel;
4f996613
ILT		 2052 bfd_vma start, stop;
2053 int change;
a3a33af3
ILT		 2054
2055 mips_ecoff_swap_reloc_in (abfd, (PTR) adj_ext_rel, &adj_int_rel);
2056
4f996613 2057 if (adj_int_rel.r_type == MIPS_R_PCREL16)
dabf906e
ILT		 2058 {
2059 unsigned long insn;
4f996613
ILT		 2060
2061 /* We only care about local references. External ones
2062 will be relocated correctly anyhow. */
2063 if (adj_int_rel.r_extern)
2064 continue;
dabf906e
ILT		 2065
2066 /* We are only interested in a PC relative reloc within
2067 this section. FIXME: Cross section PC relative
2068 relocs may not be handled correctly; does anybody
2069 care? */
2070 if (adj_int_rel.r_symndx != RELOC_SECTION_TEXT)
2071 continue;
a3a33af3 2072
4f996613
ILT		 2073 start = adj_int_rel.r_vaddr;
2074
dabf906e
ILT		 2075 insn = bfd_get_32 (abfd,
2076 contents + adj_int_rel.r_vaddr - sec->vma);
2077
4f996613
ILT		 2078 stop = (insn & 0xffff) << 2;
2079 if ((stop & 0x20000) != 0)
2080 stop -= 0x40000;
2081 stop += adj_int_rel.r_vaddr + 4;
dabf906e 2082 }
4f996613
ILT		 2083 else if (adj_int_rel.r_type == MIPS_R_RELHI)
2084 {
2085 struct internal_reloc rello;
2086 long addhi, addlo;
2087
2088 /* The next reloc must be MIPS_R_RELLO, and we handle
2089 them together. */
2090 BFD_ASSERT (adj_ext_rel + 1 < ext_rel_end);
2091
2092 mips_ecoff_swap_reloc_in (abfd, (PTR) (adj_ext_rel + 1), &rello);
2093
2094 BFD_ASSERT (rello.r_type == MIPS_R_RELLO);
2095
2096 addhi = bfd_get_32 (abfd,
2097 contents + adj_int_rel.r_vaddr - sec->vma);
2098 addhi &= 0xffff;
2099 if (addhi & 0x8000)
2100 addhi -= 0x10000;
2101 addhi <<= 16;
2102
2103 addlo = bfd_get_32 (abfd, contents + rello.r_vaddr - sec->vma);
2104 addlo &= 0xffff;
2105 if (addlo & 0x8000)
2106 addlo -= 0x10000;
2107
2108 if (adj_int_rel.r_extern)
2109 {
2110 /* The value we want here is
2111 sym - RELLOaddr + addend
2112 which we can express as
2113 sym - (RELLOaddr - addend)
2114 Therefore if we are expanding the area between
2115 RELLOaddr and RELLOaddr - addend we must adjust
2116 the addend. This is admittedly ambiguous, since
2117 we might mean (sym + addend) - RELLOaddr, but in
2118 practice we don't, and there is no way to handle
2119 that case correctly since at this point we have
2120 no idea whether any reloc is being expanded
2121 between sym and sym + addend. */
2122 start = rello.r_vaddr - (addhi + addlo);
2123 stop = rello.r_vaddr;
2124 }
2125 else
2126 {
2127 /* An internal RELHI/RELLO pair represents the
2128 difference between two addresses, $LC0 - foo.
2129 The symndx value is actually the difference
2130 between the reloc address and $LC0. This lets us
2131 compute $LC0, and, by considering the addend,
2132 foo. If the reloc we are expanding falls between
2133 those two relocs, we must adjust the addend. At
2134 this point, the symndx value is actually in the
2135 r_offset field, where it was put by
2136 mips_ecoff_swap_reloc_in. */
2137 start = rello.r_vaddr - adj_int_rel.r_offset;
2138 stop = start + addhi + addlo;
2139 }
2140 }
2141 else if (adj_int_rel.r_type == MIPS_R_SWITCH)
dabf906e 2142 {
dabf906e
ILT		 2143 /* A MIPS_R_SWITCH reloc represents a word of the form
2144 .word $L3-$LS12
2145 The value in the object file is correct, assuming the
2146 original value of $L3. The symndx value is actually
2147 the difference between the reloc address and $LS12.
2148 This lets us compute the original value of $LS12 as
2149 vaddr - symndx
2150 and the original value of $L3 as
2151 vaddr - symndx + addend
2152 where addend is the value from the object file. At
2153 this point, the symndx value is actually found in the
2154 r_offset field, since it was moved by
2155 mips_ecoff_swap_reloc_in. */
dabf906e
ILT		 2156 start = adj_int_rel.r_vaddr - adj_int_rel.r_offset;
2157 stop = start + bfd_get_32 (abfd,
2158 (contents
2159 + adj_int_rel.r_vaddr
2160 - sec->vma));
4f996613
ILT		 2161 }
2162 else
2163 continue;
2164
2165 /* If the range expressed by this reloc, which is the
2166 distance between START and STOP crosses the reloc we are
2167 expanding, we must adjust the offset. The sign of the
2168 adjustment depends upon the direction in which the range
2169 crosses the reloc being expanded. */
2170 if (start <= int_rel.r_vaddr && stop > int_rel.r_vaddr)
2171 change = PCREL16_EXPANSION_ADJUSTMENT;
2172 else if (start > int_rel.r_vaddr && stop <= int_rel.r_vaddr)
2173 change = - PCREL16_EXPANSION_ADJUSTMENT;
2174 else
2175 change = 0;
dabf906e 2176
4f996613
ILT		 2177 offsets[adj_i] += change;
2178
2179 if (adj_int_rel.r_type == MIPS_R_RELHI)
2180 {
2181 adj_ext_rel++;
2182 adj_i++;
2183 offsets[adj_i] += change;
dabf906e 2184 }
a3a33af3
ILT		 2185 }
2186
2187 /* Find all symbols in this section defined by this object file
2188 and adjust their values. Note that we decide whether to
2189 adjust the value based on the value stored in the ECOFF EXTR
2190 structure, because the value stored in the hash table may
2191 have been changed by an earlier expanded reloc and thus may
2192 no longer correctly indicate whether the symbol is before or
2193 after the expanded reloc. */
2194 ext_count = ecoff_data (abfd)->debug_info.symbolic_header.iextMax;
2195 adj_h_ptr = ecoff_data (abfd)->sym_hashes;
2196 adj_h_ptr_end = adj_h_ptr + ext_count;
2197 for (; adj_h_ptr < adj_h_ptr_end; adj_h_ptr++)
2198 {
2199 struct ecoff_link_hash_entry *adj_h;
2200
2201 adj_h = *adj_h_ptr;
2202 if (adj_h != (struct ecoff_link_hash_entry *) NULL
a5655244
ILT		 2203 && (adj_h->root.type == bfd_link_hash_defined
2204 || adj_h->root.type == bfd_link_hash_defweak)
a3a33af3
ILT		 2205 && adj_h->root.u.def.section == sec
2206 && adj_h->esym.asym.value > int_rel.r_vaddr)
2207 adj_h->root.u.def.value += PCREL16_EXPANSION_ADJUSTMENT;
2208 }
2209
2210 /* Add an entry to the symbol value adjust list. This is used
2211 by bfd_ecoff_debug_accumulate to adjust the values of
2212 internal symbols and FDR's. */
2213 adjust = ((struct ecoff_value_adjust *)
2214 bfd_alloc (abfd, sizeof (struct ecoff_value_adjust)));
2215 if (adjust == (struct ecoff_value_adjust *) NULL)
a9713b91 2216 goto error_return;
a3a33af3
ILT		 2217
2218 adjust->start = int_rel.r_vaddr;
2219 adjust->end = sec->vma + sec->_raw_size;
2220 adjust->adjust = PCREL16_EXPANSION_ADJUSTMENT;
2221
2222 adjust->next = ecoff_data (abfd)->debug_info.adjust;
2223 ecoff_data (abfd)->debug_info.adjust = adjust;
2224 }
2225
2226 if (contents != (bfd_byte *) NULL && ! info->keep_memory)
2227 free (contents);
2228
2229 return true;
2230
2231 error_return:
2232 if (contents != (bfd_byte *) NULL && ! info->keep_memory)
2233 free (contents);
2234 return false;
2235}
2236
2237/* This routine is called from mips_relocate_section when a PC
2238 relative reloc must be expanded into the five instruction sequence.
2239 It handles all the details of the expansion, including resolving
2240 the reloc. */
2241
2242static boolean
2243mips_relax_pcrel16 (info, input_bfd, input_section, h, location, address)
2244 struct bfd_link_info *info;
2245 bfd *input_bfd;
2246 asection *input_section;
2247 struct ecoff_link_hash_entry *h;
2248 bfd_byte *location;
2249 bfd_vma address;
2250{
2251 bfd_vma relocation;
2252
2253 /* 0x0411ffff is bgezal $0,. == bal . */
2254 BFD_ASSERT (bfd_get_32 (input_bfd, location) == 0x0411ffff);
2255
2256 /* We need to compute the distance between the symbol and the
2257 current address plus eight. */
2258 relocation = (h->root.u.def.value
2259 + h->root.u.def.section->output_section->vma
2260 + h->root.u.def.section->output_offset);
2261 relocation -= address + 8;
2262
2263 /* If the lower half is negative, increment the upper 16 half. */
2264 if ((relocation & 0x8000) != 0)
2265 relocation += 0x10000;
2266
2267 bfd_put_32 (input_bfd, 0x04110001, location); /* bal .+8 */
2268 bfd_put_32 (input_bfd,
2269 0x3c010000 | ((relocation >> 16) & 0xffff), /* lui $at,XX */
2270 location + 4);
2271 bfd_put_32 (input_bfd,
2272 0x24210000 | (relocation & 0xffff), /* addiu $at,$at,XX */
2273 location + 8);
2274 bfd_put_32 (input_bfd, 0x003f0821, location + 12); /* addu $at,$at,$ra */
2275 bfd_put_32 (input_bfd, 0x0020f809, location + 16); /* jalr $at */
2276
2277 return true;
2278}
a5655244
ILT		 2279
2280/* Given a .sdata section and a .rel.sdata in-memory section, store
2281 relocation information into the .rel.sdata section which can be
2282 used at runtime to relocate the section. This is called by the
2283 linker when the --embedded-relocs switch is used. This is called
2284 after the add_symbols entry point has been called for all the
2285 objects, and before the final_link entry point is called. This
2286 function presumes that the object was compiled using
2287 -membedded-pic. */
2288
2289boolean
2290bfd_mips_ecoff_create_embedded_relocs (abfd, info, datasec, relsec, errmsg)
2291 bfd *abfd;
2292 struct bfd_link_info *info;
2293 asection *datasec;
2294 asection *relsec;
2295 char **errmsg;
2296{
2297 struct ecoff_link_hash_entry **sym_hashes;
2298 struct ecoff_section_tdata *section_tdata;
2299 struct external_reloc *ext_rel;
2300 struct external_reloc *ext_rel_end;
2301 bfd_byte *p;
2302
2303 BFD_ASSERT (! info->relocateable);
2304
2305 *errmsg = NULL;
2306
2307 if (datasec->reloc_count == 0)
2308 return true;
2309
2310 sym_hashes = ecoff_data (abfd)->sym_hashes;
2311
2312 if (! mips_read_relocs (abfd, datasec))
2313 return false;
2314
2315 relsec->contents = (bfd_byte *) bfd_alloc (abfd, datasec->reloc_count * 4);
2316 if (relsec->contents == NULL)
a9713b91 2317 return false;
a5655244
ILT		 2318
2319 p = relsec->contents;
2320
2321 section_tdata = ecoff_section_data (abfd, datasec);
2322 ext_rel = (struct external_reloc *) section_tdata->external_relocs;
2323 ext_rel_end = ext_rel + datasec->reloc_count;
2324 for (; ext_rel < ext_rel_end; ext_rel++, p += 4)
2325 {
2326 struct internal_reloc int_rel;
2327 boolean text_relative;
2328
2329 mips_ecoff_swap_reloc_in (abfd, (PTR) ext_rel, &int_rel);
2330
2331 /* We are going to write a four byte word into the runtime reloc
2332 section. The word will be the address in the data section
2333 which must be relocated. This must be on a word boundary,
2334 which means the lower two bits must be zero. We use the
2335 least significant bit to indicate how the value in the data
2336 section must be relocated. A 0 means that the value is
2337 relative to the text section, while a 1 indicates that the
2338 value is relative to the data section. Given that we are
2339 assuming the code was compiled using -membedded-pic, there
2340 should not be any other possibilities. */
2341
2342 /* We can only relocate REFWORD relocs at run time. */
2343 if (int_rel.r_type != MIPS_R_REFWORD)
2344 {
2345 *errmsg = "unsupported reloc type";
2346 bfd_set_error (bfd_error_bad_value);
2347 return false;
2348 }
2349
2350 if (int_rel.r_extern)
2351 {
2352 struct ecoff_link_hash_entry *h;
2353
2354 h = sym_hashes[int_rel.r_symndx];
2355 /* If h is NULL, that means that there is a reloc against an
2356 external symbol which we thought was just a debugging
2357 symbol. This should not happen. */
2358 if (h == (struct ecoff_link_hash_entry *) NULL)
2359 abort ();
2360 if ((h->root.type == bfd_link_hash_defined
2361 || h->root.type == bfd_link_hash_defweak)
2362 && (h->root.u.def.section->flags & SEC_CODE) != 0)
2363 text_relative = true;
2364 else
2365 text_relative = false;
2366 }
2367 else
2368 {
2369 switch (int_rel.r_symndx)
2370 {
2371 case RELOC_SECTION_TEXT:
2372 text_relative = true;
2373 break;
2374 case RELOC_SECTION_SDATA:
2375 case RELOC_SECTION_SBSS:
2376 case RELOC_SECTION_LIT8:
2377 text_relative = false;
2378 break;
2379 default:
2380 /* No other sections should appear in -membedded-pic
2381 code. */
2382 *errmsg = "reloc against unsupported section";
2383 bfd_set_error (bfd_error_bad_value);
2384 return false;
2385 }
2386 }
2387
2388 if ((int_rel.r_offset & 3) != 0)
2389 {
2390 *errmsg = "reloc not properly aligned";
2391 bfd_set_error (bfd_error_bad_value);
2392 return false;
2393 }
2394
2395 bfd_put_32 (abfd,
2396 (int_rel.r_vaddr - datasec->vma + datasec->output_offset
2397 + (text_relative ? 0 : 1)),
2398 p);
2399 }
2400
2401 return true;
2402}
a3a33af3 2403\f
23f44e6f
ILT		 2404/* This is the ECOFF backend structure. The backend field of the
2405 target vector points to this. */
2406
2407static const struct ecoff_backend_data mips_ecoff_backend_data =
2408{
2409 /* COFF backend structure. */
2410 {
9783e04a 2411 (void (*) PARAMS ((bfd *,PTR,int,int,int,int,PTR))) bfd_void, /* aux_in */
23f44e6f
ILT		 2412 (void (*) PARAMS ((bfd *,PTR,PTR))) bfd_void, /* sym_in */
2413 (void (*) PARAMS ((bfd *,PTR,PTR))) bfd_void, /* lineno_in */
9783e04a 2414 (unsigned (*) PARAMS ((bfd *,PTR,int,int,int,int,PTR)))bfd_void,/*aux_out*/
23f44e6f
ILT		 2415 (unsigned (*) PARAMS ((bfd *,PTR,PTR))) bfd_void, /* sym_out */
2416 (unsigned (*) PARAMS ((bfd *,PTR,PTR))) bfd_void, /* lineno_out */
2417 (unsigned (*) PARAMS ((bfd *,PTR,PTR))) bfd_void, /* reloc_out */
2418 mips_ecoff_swap_filehdr_out, mips_ecoff_swap_aouthdr_out,
2419 mips_ecoff_swap_scnhdr_out,
69645d10 2420 FILHSZ, AOUTSZ, SCNHSZ, 0, 0, 0, 0, true,
23f44e6f 2421 mips_ecoff_swap_filehdr_in, mips_ecoff_swap_aouthdr_in,
69645d10
ILT		 2422 mips_ecoff_swap_scnhdr_in, NULL,
2423 mips_ecoff_bad_format_hook, _bfd_ecoff_set_arch_mach_hook,
2424 _bfd_ecoff_mkobject_hook, _bfd_ecoff_styp_to_sec_flags,
aca73687 2425 _bfd_ecoff_set_alignment_hook, _bfd_ecoff_slurp_symbol_table,
cba3f8a9 2426 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL
23f44e6f
ILT		 2427 },
2428 /* Supported architecture. */
2429 bfd_arch_mips,
23f44e6f
ILT		 2430 /* Initial portion of armap string. */
2431 "__________",
23f44e6f
ILT		 2432 /* The page boundary used to align sections in a demand-paged
2433 executable file. E.g., 0x1000. */
2434 0x1000,
5fa2aaa2
ILT		 2435 /* True if the .rdata section is part of the text segment, as on the
2436 Alpha. False if .rdata is part of the data segment, as on the
2437 MIPS. */
2438 false,
23f44e6f
ILT		 2439 /* Bitsize of constructor entries. */
2440 32,
2441 /* Reloc to use for constructor entries. */
2442 &mips_howto_table[MIPS_R_REFWORD],
4991ebb9
ILT		 2443 {
2444 /* Symbol table magic number. */
2445 magicSym,
2446 /* Alignment of debugging information. E.g., 4. */
2447 4,
2448 /* Sizes of external symbolic information. */
2449 sizeof (struct hdr_ext),
2450 sizeof (struct dnr_ext),
2451 sizeof (struct pdr_ext),
2452 sizeof (struct sym_ext),
2453 sizeof (struct opt_ext),
2454 sizeof (struct fdr_ext),
2455 sizeof (struct rfd_ext),
2456 sizeof (struct ext_ext),
2457 /* Functions to swap in external symbolic data. */
2458 ecoff_swap_hdr_in,
2459 ecoff_swap_dnr_in,
2460 ecoff_swap_pdr_in,
2461 ecoff_swap_sym_in,
2462 ecoff_swap_opt_in,
2463 ecoff_swap_fdr_in,
2464 ecoff_swap_rfd_in,
2465 ecoff_swap_ext_in,
75f3ef7a
ILT		 2466 _bfd_ecoff_swap_tir_in,
2467 _bfd_ecoff_swap_rndx_in,
4991ebb9
ILT		 2468 /* Functions to swap out external symbolic data. */
2469 ecoff_swap_hdr_out,
2470 ecoff_swap_dnr_out,
2471 ecoff_swap_pdr_out,
2472 ecoff_swap_sym_out,
2473 ecoff_swap_opt_out,
2474 ecoff_swap_fdr_out,
2475 ecoff_swap_rfd_out,
aac6b32f 2476 ecoff_swap_ext_out,
75f3ef7a
ILT		 2477 _bfd_ecoff_swap_tir_out,
2478 _bfd_ecoff_swap_rndx_out,
aac6b32f 2479 /* Function to read in symbolic data. */
75f3ef7a 2480 _bfd_ecoff_slurp_symbolic_info
4991ebb9 2481 },
23f44e6f
ILT		 2482 /* External reloc size. */
2483 RELSZ,
2484 /* Reloc swapping functions. */
2485 mips_ecoff_swap_reloc_in,
2486 mips_ecoff_swap_reloc_out,
2487 /* Backend reloc tweaking. */
5fa2aaa2 2488 mips_adjust_reloc_in,
4991ebb9
ILT		 2489 mips_adjust_reloc_out,
2490 /* Relocate section contents while linking. */
aca73687
ILT		 2491 mips_relocate_section,
2492 /* Do final adjustments to filehdr and aouthdr. */
64d5f5d0
ILT		 2493 NULL,
2494 /* Read an element from an archive at a given file position. */
2495 _bfd_get_elt_at_filepos
515c4292
ILT		 2496};
2497
23f44e6f 2498/* Looking up a reloc type is MIPS specific. */
75f3ef7a 2499#define _bfd_ecoff_bfd_reloc_type_lookup mips_bfd_reloc_type_lookup
23f44e6f 2500
5fa2aaa2 2501/* Getting relocated section contents is generic. */
75f3ef7a 2502#define _bfd_ecoff_bfd_get_relocated_section_contents \
5fa2aaa2
ILT		 2503 bfd_generic_get_relocated_section_contents
2504
a9713b91
ILT		 2505/* Handling file windows is generic. */
2506#define _bfd_ecoff_get_section_contents_in_window \
2507 _bfd_generic_get_section_contents_in_window
2508
a3a33af3 2509/* Relaxing sections is MIPS specific. */
75f3ef7a 2510#define _bfd_ecoff_bfd_relax_section mips_relax_section
a3a33af3 2511
2f3508ad 2512const bfd_target ecoff_little_vec =
294eaca4
SC		 2513{
2514 "ecoff-littlemips", /* name */
515c4292 2515 bfd_target_ecoff_flavour,
64d5f5d0
ILT		 2516 BFD_ENDIAN_LITTLE, /* data byte order is little */
2517 BFD_ENDIAN_LITTLE, /* header byte order is little */
294eaca4
SC		 2518
2519 (HAS_RELOC | EXEC_P | /* object flags */
2520 HAS_LINENO | HAS_DEBUG |
4991ebb9 2521 HAS_SYMS | HAS_LOCALS | WP_TEXT | D_PAGED),
294eaca4 2522
a5655244 2523 (SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_CODE | SEC_DATA),
294eaca4 2524 0, /* leading underscore */
de17306e 2525 ' ', /* ar_pad_char */
294eaca4 2526 15, /* ar_max_namelen */
23f44e6f
ILT		 2527 bfd_getl64, bfd_getl_signed_64, bfd_putl64,
2528 bfd_getl32, bfd_getl_signed_32, bfd_putl32,
2529 bfd_getl16, bfd_getl_signed_16, bfd_putl16, /* data */
2530 bfd_getl64, bfd_getl_signed_64, bfd_putl64,
2531 bfd_getl32, bfd_getl_signed_32, bfd_putl32,
2532 bfd_getl16, bfd_getl_signed_16, bfd_putl16, /* hdrs */
294eaca4 2533
515c4292 2534 {_bfd_dummy_target, coff_object_p, /* bfd_check_format */
75f3ef7a
ILT		 2535 _bfd_ecoff_archive_p, _bfd_dummy_target},
2536 {bfd_false, _bfd_ecoff_mkobject, /* bfd_set_format */
dae31cf5 2537 _bfd_generic_mkarchive, bfd_false},
75f3ef7a 2538 {bfd_false, _bfd_ecoff_write_object_contents, /* bfd_write_contents */
c3fe0c41 2539 _bfd_write_archive_contents, bfd_false},
6812b607 2540
75f3ef7a
ILT		 2541 BFD_JUMP_TABLE_GENERIC (_bfd_ecoff),
2542 BFD_JUMP_TABLE_COPY (_bfd_ecoff),
6812b607 2543 BFD_JUMP_TABLE_CORE (_bfd_nocore),
75f3ef7a
ILT		 2544 BFD_JUMP_TABLE_ARCHIVE (_bfd_ecoff),
2545 BFD_JUMP_TABLE_SYMBOLS (_bfd_ecoff),
2546 BFD_JUMP_TABLE_RELOCS (_bfd_ecoff),
2547 BFD_JUMP_TABLE_WRITE (_bfd_ecoff),
2548 BFD_JUMP_TABLE_LINK (_bfd_ecoff),
dfc1c006 2549 BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic),
6812b607 2550
23f44e6f 2551 (PTR) &mips_ecoff_backend_data
515c4292 2552};
1327fb29 2553
2f3508ad 2554const bfd_target ecoff_big_vec =
294eaca4
SC		 2555{
2556 "ecoff-bigmips", /* name */
515c4292 2557 bfd_target_ecoff_flavour,
64d5f5d0
ILT		 2558 BFD_ENDIAN_BIG, /* data byte order is big */
2559 BFD_ENDIAN_BIG, /* header byte order is big */
294eaca4
SC		 2560
2561 (HAS_RELOC | EXEC_P | /* object flags */
2562 HAS_LINENO | HAS_DEBUG |
4991ebb9 2563 HAS_SYMS | HAS_LOCALS | WP_TEXT | D_PAGED),
294eaca4 2564
a5655244 2565 (SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_CODE | SEC_DATA),
294eaca4
SC		 2566 0, /* leading underscore */
2567 ' ', /* ar_pad_char */
de17306e 2568 15, /* ar_max_namelen */
23f44e6f
ILT		 2569 bfd_getb64, bfd_getb_signed_64, bfd_putb64,
2570 bfd_getb32, bfd_getb_signed_32, bfd_putb32,
2571 bfd_getb16, bfd_getb_signed_16, bfd_putb16,
2572 bfd_getb64, bfd_getb_signed_64, bfd_putb64,
2573 bfd_getb32, bfd_getb_signed_32, bfd_putb32,
2574 bfd_getb16, bfd_getb_signed_16, bfd_putb16,
294eaca4 2575 {_bfd_dummy_target, coff_object_p, /* bfd_check_format */
75f3ef7a
ILT		 2576 _bfd_ecoff_archive_p, _bfd_dummy_target},
2577 {bfd_false, _bfd_ecoff_mkobject, /* bfd_set_format */
dae31cf5 2578 _bfd_generic_mkarchive, bfd_false},
75f3ef7a 2579 {bfd_false, _bfd_ecoff_write_object_contents, /* bfd_write_contents */
c3fe0c41 2580 _bfd_write_archive_contents, bfd_false},
6812b607 2581
75f3ef7a
ILT		 2582 BFD_JUMP_TABLE_GENERIC (_bfd_ecoff),
2583 BFD_JUMP_TABLE_COPY (_bfd_ecoff),
6812b607 2584 BFD_JUMP_TABLE_CORE (_bfd_nocore),
75f3ef7a
ILT		 2585 BFD_JUMP_TABLE_ARCHIVE (_bfd_ecoff),
2586 BFD_JUMP_TABLE_SYMBOLS (_bfd_ecoff),
2587 BFD_JUMP_TABLE_RELOCS (_bfd_ecoff),
2588 BFD_JUMP_TABLE_WRITE (_bfd_ecoff),
2589 BFD_JUMP_TABLE_LINK (_bfd_ecoff),
dfc1c006 2590 BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic),
6812b607 2591
23f44e6f 2592 (PTR) &mips_ecoff_backend_data
515c4292 2593};
GDB Binutils - Deliverables
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