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* config.sub, config.guess: Update from upstream sources.
[deliverable/binutils-gdb.git] / bfd / coff-sh.c
CommitLineData
c2dcd04e 1/* BFD back-end for Renesas Super-H COFF binaries.
eea6121a 2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
9553c638 3 2003, 2004, 2005 Free Software Foundation, Inc.
252b5132
RH		 4 Contributed by Cygnus Support.
5 Written by Steve Chamberlain, <sac@cygnus.com>.
6 Relaxing code written by Ian Lance Taylor, <ian@cygnus.com>.
7
c2dcd04e 8 This file is part of BFD, the Binary File Descriptor library.
252b5132 9
c2dcd04e
NC		 10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2 of the License, or
13 (at your option) any later version.
252b5132 14
c2dcd04e
NC		 15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
252b5132 19
c2dcd04e
NC		 20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
3e110533 22 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
252b5132
RH		 23
24#include "bfd.h"
25#include "sysdep.h"
993e9275 26#include "libiberty.h"
252b5132
RH		 27#include "libbfd.h"
28#include "bfdlink.h"
29#include "coff/sh.h"
30#include "coff/internal.h"
17505c5c
NC		 31
32#ifdef COFF_WITH_PE
33#include "coff/pe.h"
86033394
NC		 34
35#ifndef COFF_IMAGE_WITH_PE
b34976b6 36static bfd_boolean sh_align_load_span
86033394 37 PARAMS ((bfd *, asection *, bfd_byte *,
b34976b6
AM		 38 bfd_boolean (*) (bfd *, asection *, PTR, bfd_byte *, bfd_vma),
39 PTR, bfd_vma **, bfd_vma *, bfd_vma, bfd_vma, bfd_boolean *));
86033394
NC		 40
41#define _bfd_sh_align_load_span sh_align_load_span
42#endif
17505c5c
NC		 43#endif
44
252b5132
RH		 45#include "libcoff.h"
46
47/* Internal functions. */
48static bfd_reloc_status_type sh_reloc
49 PARAMS ((bfd *, arelent *, asymbol *, PTR, asection *, bfd *, char **));
50static long get_symbol_value PARAMS ((asymbol *));
b34976b6
AM		 51static bfd_boolean sh_relax_section
52 PARAMS ((bfd *, asection *, struct bfd_link_info *, bfd_boolean *));
53static bfd_boolean sh_relax_delete_bytes
252b5132 54 PARAMS ((bfd *, asection *, bfd_vma, int));
86033394 55#ifndef COFF_IMAGE_WITH_PE
252b5132 56static const struct sh_opcode *sh_insn_info PARAMS ((unsigned int));
86033394 57#endif
b34976b6
AM		 58static bfd_boolean sh_align_loads
59 PARAMS ((bfd *, asection *, struct internal_reloc *, bfd_byte *,
60 bfd_boolean *));
61static bfd_boolean sh_swap_insns
252b5132 62 PARAMS ((bfd *, asection *, PTR, bfd_byte *, bfd_vma));
b34976b6 63static bfd_boolean sh_relocate_section
252b5132
RH		 64 PARAMS ((bfd *, struct bfd_link_info *, bfd *, asection *, bfd_byte *,
65 struct internal_reloc *, struct internal_syment *, asection **));
66static bfd_byte *sh_coff_get_relocated_section_contents
67 PARAMS ((bfd *, struct bfd_link_info *, struct bfd_link_order *,
b34976b6 68 bfd_byte *, bfd_boolean, asymbol **));
f4ffd778 69static reloc_howto_type * sh_coff_reloc_type_lookup PARAMS ((bfd *, bfd_reloc_code_real_type));
252b5132 70
17505c5c
NC		 71#ifdef COFF_WITH_PE
72/* Can't build import tables with 2**4 alignment. */
73#define COFF_DEFAULT_SECTION_ALIGNMENT_POWER 2
74#else
252b5132 75/* Default section alignment to 2**4. */
17505c5c
NC		 76#define COFF_DEFAULT_SECTION_ALIGNMENT_POWER 4
77#endif
78
79#ifdef COFF_IMAGE_WITH_PE
80/* Align PE executables. */
81#define COFF_PAGE_SIZE 0x1000
82#endif
252b5132
RH		 83
84/* Generate long file names. */
85#define COFF_LONG_FILENAMES
86
17505c5c 87#ifdef COFF_WITH_PE
b34976b6
AM		 88static bfd_boolean in_reloc_p PARAMS ((bfd *, reloc_howto_type *));
89/* Return TRUE if this relocation should
17505c5c 90 appear in the output .reloc section. */
b34976b6 91static bfd_boolean in_reloc_p (abfd, howto)
17505c5c
NC		 92 bfd * abfd ATTRIBUTE_UNUSED;
93 reloc_howto_type * howto;
94{
95 return ! howto->pc_relative && howto->type != R_SH_IMAGEBASE;
cbfe05c4 96}
17505c5c
NC		 97#endif
98
252b5132
RH		 99/* The supported relocations. There are a lot of relocations defined
100 in coff/internal.h which we do not expect to ever see. */
101static reloc_howto_type sh_coff_howtos[] =
102{
5f771d47
ILT		 103 EMPTY_HOWTO (0),
104 EMPTY_HOWTO (1),
17505c5c
NC		 105#ifdef COFF_WITH_PE
106 /* Windows CE */
107 HOWTO (R_SH_IMM32CE, /* type */
108 0, /* rightshift */
109 2, /* size (0 = byte, 1 = short, 2 = long) */
110 32, /* bitsize */
b34976b6 111 FALSE, /* pc_relative */
17505c5c
NC		 112 0, /* bitpos */
113 complain_overflow_bitfield, /* complain_on_overflow */
114 sh_reloc, /* special_function */
115 "r_imm32ce", /* name */
b34976b6 116 TRUE, /* partial_inplace */
17505c5c
NC		 117 0xffffffff, /* src_mask */
118 0xffffffff, /* dst_mask */
b34976b6 119 FALSE), /* pcrel_offset */
17505c5c 120#else
5f771d47 121 EMPTY_HOWTO (2),
17505c5c 122#endif
5f771d47
ILT		 123 EMPTY_HOWTO (3), /* R_SH_PCREL8 */
124 EMPTY_HOWTO (4), /* R_SH_PCREL16 */
125 EMPTY_HOWTO (5), /* R_SH_HIGH8 */
126 EMPTY_HOWTO (6), /* R_SH_IMM24 */
127 EMPTY_HOWTO (7), /* R_SH_LOW16 */
128 EMPTY_HOWTO (8),
129 EMPTY_HOWTO (9), /* R_SH_PCDISP8BY4 */
252b5132
RH		 130
131 HOWTO (R_SH_PCDISP8BY2, /* type */
132 1, /* rightshift */
133 1, /* size (0 = byte, 1 = short, 2 = long) */
134 8, /* bitsize */
b34976b6 135 TRUE, /* pc_relative */
252b5132
RH		 136 0, /* bitpos */
137 complain_overflow_signed, /* complain_on_overflow */
138 sh_reloc, /* special_function */
139 "r_pcdisp8by2", /* name */
b34976b6 140 TRUE, /* partial_inplace */
252b5132
RH		 141 0xff, /* src_mask */
142 0xff, /* dst_mask */
b34976b6 143 TRUE), /* pcrel_offset */
252b5132 144
5f771d47 145 EMPTY_HOWTO (11), /* R_SH_PCDISP8 */
252b5132
RH		 146
147 HOWTO (R_SH_PCDISP, /* type */
148 1, /* rightshift */
149 1, /* size (0 = byte, 1 = short, 2 = long) */
150 12, /* bitsize */
b34976b6 151 TRUE, /* pc_relative */
252b5132
RH		 152 0, /* bitpos */
153 complain_overflow_signed, /* complain_on_overflow */
154 sh_reloc, /* special_function */
155 "r_pcdisp12by2", /* name */
b34976b6 156 TRUE, /* partial_inplace */
252b5132
RH		 157 0xfff, /* src_mask */
158 0xfff, /* dst_mask */
b34976b6 159 TRUE), /* pcrel_offset */
252b5132 160
5f771d47 161 EMPTY_HOWTO (13),
252b5132
RH		 162
163 HOWTO (R_SH_IMM32, /* type */
164 0, /* rightshift */
165 2, /* size (0 = byte, 1 = short, 2 = long) */
166 32, /* bitsize */
b34976b6 167 FALSE, /* pc_relative */
252b5132
RH		 168 0, /* bitpos */
169 complain_overflow_bitfield, /* complain_on_overflow */
170 sh_reloc, /* special_function */
171 "r_imm32", /* name */
b34976b6 172 TRUE, /* partial_inplace */
252b5132
RH		 173 0xffffffff, /* src_mask */
174 0xffffffff, /* dst_mask */
b34976b6 175 FALSE), /* pcrel_offset */
252b5132 176
5f771d47 177 EMPTY_HOWTO (15),
17505c5c 178#ifdef COFF_WITH_PE
cbfe05c4
KH		 179 HOWTO (R_SH_IMAGEBASE, /* type */
180 0, /* rightshift */
181 2, /* size (0 = byte, 1 = short, 2 = long) */
182 32, /* bitsize */
b34976b6 183 FALSE, /* pc_relative */
cbfe05c4 184 0, /* bitpos */
17505c5c 185 complain_overflow_bitfield, /* complain_on_overflow */
cbfe05c4
KH		 186 sh_reloc, /* special_function */
187 "rva32", /* name */
b34976b6 188 TRUE, /* partial_inplace */
cbfe05c4
KH		 189 0xffffffff, /* src_mask */
190 0xffffffff, /* dst_mask */
b34976b6 191 FALSE), /* pcrel_offset */
17505c5c 192#else
5f771d47 193 EMPTY_HOWTO (16), /* R_SH_IMM8 */
17505c5c 194#endif
5f771d47
ILT		 195 EMPTY_HOWTO (17), /* R_SH_IMM8BY2 */
196 EMPTY_HOWTO (18), /* R_SH_IMM8BY4 */
197 EMPTY_HOWTO (19), /* R_SH_IMM4 */
198 EMPTY_HOWTO (20), /* R_SH_IMM4BY2 */
199 EMPTY_HOWTO (21), /* R_SH_IMM4BY4 */
252b5132
RH		 200
201 HOWTO (R_SH_PCRELIMM8BY2, /* type */
202 1, /* rightshift */
203 1, /* size (0 = byte, 1 = short, 2 = long) */
204 8, /* bitsize */
b34976b6 205 TRUE, /* pc_relative */
252b5132
RH		 206 0, /* bitpos */
207 complain_overflow_unsigned, /* complain_on_overflow */
208 sh_reloc, /* special_function */
209 "r_pcrelimm8by2", /* name */
b34976b6 210 TRUE, /* partial_inplace */
252b5132
RH		 211 0xff, /* src_mask */
212 0xff, /* dst_mask */
b34976b6 213 TRUE), /* pcrel_offset */
252b5132
RH		 214
215 HOWTO (R_SH_PCRELIMM8BY4, /* type */
216 2, /* rightshift */
217 1, /* size (0 = byte, 1 = short, 2 = long) */
218 8, /* bitsize */
b34976b6 219 TRUE, /* pc_relative */
252b5132
RH		 220 0, /* bitpos */
221 complain_overflow_unsigned, /* complain_on_overflow */
222 sh_reloc, /* special_function */
223 "r_pcrelimm8by4", /* name */
b34976b6 224 TRUE, /* partial_inplace */
252b5132
RH		 225 0xff, /* src_mask */
226 0xff, /* dst_mask */
b34976b6 227 TRUE), /* pcrel_offset */
252b5132
RH		 228
229 HOWTO (R_SH_IMM16, /* type */
230 0, /* rightshift */
231 1, /* size (0 = byte, 1 = short, 2 = long) */
232 16, /* bitsize */
b34976b6 233 FALSE, /* pc_relative */
252b5132
RH		 234 0, /* bitpos */
235 complain_overflow_bitfield, /* complain_on_overflow */
236 sh_reloc, /* special_function */
237 "r_imm16", /* name */
b34976b6 238 TRUE, /* partial_inplace */
252b5132
RH		 239 0xffff, /* src_mask */
240 0xffff, /* dst_mask */
b34976b6 241 FALSE), /* pcrel_offset */
252b5132
RH		 242
243 HOWTO (R_SH_SWITCH16, /* type */
244 0, /* rightshift */
245 1, /* size (0 = byte, 1 = short, 2 = long) */
246 16, /* bitsize */
b34976b6 247 FALSE, /* pc_relative */
252b5132
RH		 248 0, /* bitpos */
249 complain_overflow_bitfield, /* complain_on_overflow */
250 sh_reloc, /* special_function */
251 "r_switch16", /* name */
b34976b6 252 TRUE, /* partial_inplace */
252b5132
RH		 253 0xffff, /* src_mask */
254 0xffff, /* dst_mask */
b34976b6 255 FALSE), /* pcrel_offset */
252b5132
RH		 256
257 HOWTO (R_SH_SWITCH32, /* type */
258 0, /* rightshift */
259 2, /* size (0 = byte, 1 = short, 2 = long) */
260 32, /* bitsize */
b34976b6 261 FALSE, /* pc_relative */
252b5132
RH		 262 0, /* bitpos */
263 complain_overflow_bitfield, /* complain_on_overflow */
264 sh_reloc, /* special_function */
265 "r_switch32", /* name */
b34976b6 266 TRUE, /* partial_inplace */
252b5132
RH		 267 0xffffffff, /* src_mask */
268 0xffffffff, /* dst_mask */
b34976b6 269 FALSE), /* pcrel_offset */
252b5132
RH		 270
271 HOWTO (R_SH_USES, /* type */
272 0, /* rightshift */
273 1, /* size (0 = byte, 1 = short, 2 = long) */
274 16, /* bitsize */
b34976b6 275 FALSE, /* pc_relative */
252b5132
RH		 276 0, /* bitpos */
277 complain_overflow_bitfield, /* complain_on_overflow */
278 sh_reloc, /* special_function */
279 "r_uses", /* name */
b34976b6 280 TRUE, /* partial_inplace */
252b5132
RH		 281 0xffff, /* src_mask */
282 0xffff, /* dst_mask */
b34976b6 283 FALSE), /* pcrel_offset */
252b5132
RH		 284
285 HOWTO (R_SH_COUNT, /* type */
286 0, /* rightshift */
287 2, /* size (0 = byte, 1 = short, 2 = long) */
288 32, /* bitsize */
b34976b6 289 FALSE, /* pc_relative */
252b5132
RH		 290 0, /* bitpos */
291 complain_overflow_bitfield, /* complain_on_overflow */
292 sh_reloc, /* special_function */
293 "r_count", /* name */
b34976b6 294 TRUE, /* partial_inplace */
252b5132
RH		 295 0xffffffff, /* src_mask */
296 0xffffffff, /* dst_mask */
b34976b6 297 FALSE), /* pcrel_offset */
252b5132
RH		 298
299 HOWTO (R_SH_ALIGN, /* type */
300 0, /* rightshift */
301 2, /* size (0 = byte, 1 = short, 2 = long) */
302 32, /* bitsize */
b34976b6 303 FALSE, /* pc_relative */
252b5132
RH		 304 0, /* bitpos */
305 complain_overflow_bitfield, /* complain_on_overflow */
306 sh_reloc, /* special_function */
307 "r_align", /* name */
b34976b6 308 TRUE, /* partial_inplace */
252b5132
RH		 309 0xffffffff, /* src_mask */
310 0xffffffff, /* dst_mask */
b34976b6 311 FALSE), /* pcrel_offset */
252b5132
RH		 312
313 HOWTO (R_SH_CODE, /* type */
314 0, /* rightshift */
315 2, /* size (0 = byte, 1 = short, 2 = long) */
316 32, /* bitsize */
b34976b6 317 FALSE, /* pc_relative */
252b5132
RH		 318 0, /* bitpos */
319 complain_overflow_bitfield, /* complain_on_overflow */
320 sh_reloc, /* special_function */
321 "r_code", /* name */
b34976b6 322 TRUE, /* partial_inplace */
252b5132
RH		 323 0xffffffff, /* src_mask */
324 0xffffffff, /* dst_mask */
b34976b6 325 FALSE), /* pcrel_offset */
252b5132
RH		 326
327 HOWTO (R_SH_DATA, /* type */
328 0, /* rightshift */
329 2, /* size (0 = byte, 1 = short, 2 = long) */
330 32, /* bitsize */
b34976b6 331 FALSE, /* pc_relative */
252b5132
RH		 332 0, /* bitpos */
333 complain_overflow_bitfield, /* complain_on_overflow */
334 sh_reloc, /* special_function */
335 "r_data", /* name */
b34976b6 336 TRUE, /* partial_inplace */
252b5132
RH		 337 0xffffffff, /* src_mask */
338 0xffffffff, /* dst_mask */
b34976b6 339 FALSE), /* pcrel_offset */
252b5132
RH		 340
341 HOWTO (R_SH_LABEL, /* type */
342 0, /* rightshift */
343 2, /* size (0 = byte, 1 = short, 2 = long) */
344 32, /* bitsize */
b34976b6 345 FALSE, /* pc_relative */
252b5132
RH		 346 0, /* bitpos */
347 complain_overflow_bitfield, /* complain_on_overflow */
348 sh_reloc, /* special_function */
349 "r_label", /* name */
b34976b6 350 TRUE, /* partial_inplace */
252b5132
RH		 351 0xffffffff, /* src_mask */
352 0xffffffff, /* dst_mask */
b34976b6 353 FALSE), /* pcrel_offset */
252b5132
RH		 354
355 HOWTO (R_SH_SWITCH8, /* type */
356 0, /* rightshift */
357 0, /* size (0 = byte, 1 = short, 2 = long) */
358 8, /* bitsize */
b34976b6 359 FALSE, /* pc_relative */
252b5132
RH		 360 0, /* bitpos */
361 complain_overflow_bitfield, /* complain_on_overflow */
362 sh_reloc, /* special_function */
363 "r_switch8", /* name */
b34976b6 364 TRUE, /* partial_inplace */
252b5132
RH		 365 0xff, /* src_mask */
366 0xff, /* dst_mask */
b34976b6 367 FALSE) /* pcrel_offset */
252b5132
RH		 368};
369
370#define SH_COFF_HOWTO_COUNT (sizeof sh_coff_howtos / sizeof sh_coff_howtos[0])
371
372/* Check for a bad magic number. */
373#define BADMAG(x) SHBADMAG(x)
374
375/* Customize coffcode.h (this is not currently used). */
376#define SH 1
377
378/* FIXME: This should not be set here. */
379#define __A_MAGIC_SET__
380
17505c5c 381#ifndef COFF_WITH_PE
252b5132 382/* Swap the r_offset field in and out. */
dc810e39
AM		 383#define SWAP_IN_RELOC_OFFSET H_GET_32
384#define SWAP_OUT_RELOC_OFFSET H_PUT_32
252b5132
RH		 385
386/* Swap out extra information in the reloc structure. */
387#define SWAP_OUT_RELOC_EXTRA(abfd, src, dst) \
388 do \
389 { \
390 dst->r_stuff[0] = 'S'; \
391 dst->r_stuff[1] = 'C'; \
392 } \
393 while (0)
17505c5c 394#endif
252b5132
RH		 395
396/* Get the value of a symbol, when performing a relocation. */
397
398static long
cbfe05c4 399get_symbol_value (symbol)
252b5132 400 asymbol *symbol;
cbfe05c4 401{
252b5132
RH		 402 bfd_vma relocation;
403
404 if (bfd_is_com_section (symbol->section))
cbfe05c4
KH		 405 relocation = 0;
406 else
252b5132
RH		 407 relocation = (symbol->value +
408 symbol->section->output_section->vma +
409 symbol->section->output_offset);
410
411 return relocation;
412}
413
17505c5c
NC		 414#ifdef COFF_WITH_PE
415/* Convert an rtype to howto for the COFF backend linker.
416 Copied from coff-i386. */
417#define coff_rtype_to_howto coff_sh_rtype_to_howto
f4ffd778 418static reloc_howto_type * coff_sh_rtype_to_howto PARAMS ((bfd *, asection *, struct internal_reloc *, struct coff_link_hash_entry *, struct internal_syment *, bfd_vma *));
17505c5c
NC		 419
420static reloc_howto_type *
421coff_sh_rtype_to_howto (abfd, sec, rel, h, sym, addendp)
86033394 422 bfd * abfd ATTRIBUTE_UNUSED;
17505c5c
NC		 423 asection * sec;
424 struct internal_reloc * rel;
425 struct coff_link_hash_entry * h;
426 struct internal_syment * sym;
427 bfd_vma * addendp;
428{
429 reloc_howto_type * howto;
430
431 howto = sh_coff_howtos + rel->r_type;
432
433 *addendp = 0;
434
435 if (howto->pc_relative)
436 *addendp += sec->vma;
437
438 if (sym != NULL && sym->n_scnum == 0 && sym->n_value != 0)
439 {
440 /* This is a common symbol. The section contents include the
441 size (sym->n_value) as an addend. The relocate_section
442 function will be adding in the final value of the symbol. We
443 need to subtract out the current size in order to get the
444 correct result. */
445 BFD_ASSERT (h != NULL);
446 }
447
448 if (howto->pc_relative)
449 {
450 *addendp -= 4;
451
452 /* If the symbol is defined, then the generic code is going to
453 add back the symbol value in order to cancel out an
454 adjustment it made to the addend. However, we set the addend
455 to 0 at the start of this function. We need to adjust here,
456 to avoid the adjustment the generic code will make. FIXME:
457 This is getting a bit hackish. */
458 if (sym != NULL && sym->n_scnum != 0)
459 *addendp -= sym->n_value;
460 }
461
462 if (rel->r_type == R_SH_IMAGEBASE)
463 *addendp -= pe_data (sec->output_section->owner)->pe_opthdr.ImageBase;
464
465 return howto;
466}
467
993e9275
NC		 468#endif /* COFF_WITH_PE */
469
17505c5c
NC		 470/* This structure is used to map BFD reloc codes to SH PE relocs. */
471struct shcoff_reloc_map
472{
aa066ac8 473 bfd_reloc_code_real_type bfd_reloc_val;
17505c5c
NC		 474 unsigned char shcoff_reloc_val;
475};
476
a9a32010 477#ifdef COFF_WITH_PE
17505c5c
NC		 478/* An array mapping BFD reloc codes to SH PE relocs. */
479static const struct shcoff_reloc_map sh_reloc_map[] =
480{
481 { BFD_RELOC_32, R_SH_IMM32CE },
482 { BFD_RELOC_RVA, R_SH_IMAGEBASE },
483 { BFD_RELOC_CTOR, R_SH_IMM32CE },
484};
a9a32010
DJ		 485#else
486/* An array mapping BFD reloc codes to SH PE relocs. */
487static const struct shcoff_reloc_map sh_reloc_map[] =
488{
489 { BFD_RELOC_32, R_SH_IMM32 },
490 { BFD_RELOC_CTOR, R_SH_IMM32 },
491};
492#endif
17505c5c
NC		 493
494/* Given a BFD reloc code, return the howto structure for the
495 corresponding SH PE reloc. */
496#define coff_bfd_reloc_type_lookup sh_coff_reloc_type_lookup
497
498static reloc_howto_type *
499sh_coff_reloc_type_lookup (abfd, code)
500 bfd * abfd ATTRIBUTE_UNUSED;
501 bfd_reloc_code_real_type code;
502{
503 unsigned int i;
504
993e9275
NC		 505 for (i = ARRAY_SIZE (sh_reloc_map); i--;)
506 if (sh_reloc_map[i].bfd_reloc_val == code)
507 return &sh_coff_howtos[(int) sh_reloc_map[i].shcoff_reloc_val];
17505c5c
NC		 508
509 fprintf (stderr, "SH Error: unknown reloc type %d\n", code);
510 return NULL;
511}
17505c5c 512
252b5132
RH		 513/* This macro is used in coffcode.h to get the howto corresponding to
514 an internal reloc. */
515
516#define RTYPE2HOWTO(relent, internal) \
517 ((relent)->howto = \
518 ((internal)->r_type < SH_COFF_HOWTO_COUNT \
519 ? &sh_coff_howtos[(internal)->r_type] \
520 : (reloc_howto_type *) NULL))
521
522/* This is the same as the macro in coffcode.h, except that it copies
523 r_offset into reloc_entry->addend for some relocs. */
524#define CALC_ADDEND(abfd, ptr, reloc, cache_ptr) \
525 { \
526 coff_symbol_type *coffsym = (coff_symbol_type *) NULL; \
527 if (ptr && bfd_asymbol_bfd (ptr) != abfd) \
528 coffsym = (obj_symbols (abfd) \
529 + (cache_ptr->sym_ptr_ptr - symbols)); \
530 else if (ptr) \
531 coffsym = coff_symbol_from (abfd, ptr); \
532 if (coffsym != (coff_symbol_type *) NULL \
533 && coffsym->native->u.syment.n_scnum == 0) \
534 cache_ptr->addend = 0; \
535 else if (ptr && bfd_asymbol_bfd (ptr) == abfd \
536 && ptr->section != (asection *) NULL) \
537 cache_ptr->addend = - (ptr->section->vma + ptr->value); \
538 else \
539 cache_ptr->addend = 0; \
540 if ((reloc).r_type == R_SH_SWITCH8 \
541 || (reloc).r_type == R_SH_SWITCH16 \
542 || (reloc).r_type == R_SH_SWITCH32 \
543 || (reloc).r_type == R_SH_USES \
544 || (reloc).r_type == R_SH_COUNT \
545 || (reloc).r_type == R_SH_ALIGN) \
546 cache_ptr->addend = (reloc).r_offset; \
547 }
548
549/* This is the howto function for the SH relocations. */
550
551static bfd_reloc_status_type
552sh_reloc (abfd, reloc_entry, symbol_in, data, input_section, output_bfd,
553 error_message)
554 bfd *abfd;
555 arelent *reloc_entry;
556 asymbol *symbol_in;
557 PTR data;
558 asection *input_section;
559 bfd *output_bfd;
5f771d47 560 char **error_message ATTRIBUTE_UNUSED;
252b5132
RH		 561{
562 unsigned long insn;
563 bfd_vma sym_value;
564 unsigned short r_type;
565 bfd_vma addr = reloc_entry->address;
566 bfd_byte *hit_data = addr + (bfd_byte *) data;
567
568 r_type = reloc_entry->howto->type;
569
570 if (output_bfd != NULL)
571 {
572 /* Partial linking--do nothing. */
573 reloc_entry->address += input_section->output_offset;
574 return bfd_reloc_ok;
575 }
576
577 /* Almost all relocs have to do with relaxing. If any work must be
578 done for them, it has been done in sh_relax_section. */
579 if (r_type != R_SH_IMM32
17505c5c
NC		 580#ifdef COFF_WITH_PE
581 && r_type != R_SH_IMM32CE
582 && r_type != R_SH_IMAGEBASE
583#endif
252b5132
RH		 584 && (r_type != R_SH_PCDISP
585 || (symbol_in->flags & BSF_LOCAL) != 0))
586 return bfd_reloc_ok;
587
588 if (symbol_in != NULL
589 && bfd_is_und_section (symbol_in->section))
590 return bfd_reloc_undefined;
591
592 sym_value = get_symbol_value (symbol_in);
593
594 switch (r_type)
595 {
596 case R_SH_IMM32:
17505c5c
NC		 597#ifdef COFF_WITH_PE
598 case R_SH_IMM32CE:
599#endif
252b5132
RH		 600 insn = bfd_get_32 (abfd, hit_data);
601 insn += sym_value + reloc_entry->addend;
dc810e39 602 bfd_put_32 (abfd, (bfd_vma) insn, hit_data);
252b5132 603 break;
17505c5c
NC		 604#ifdef COFF_WITH_PE
605 case R_SH_IMAGEBASE:
606 insn = bfd_get_32 (abfd, hit_data);
dc810e39
AM		 607 insn += sym_value + reloc_entry->addend;
608 insn -= pe_data (input_section->output_section->owner)->pe_opthdr.ImageBase;
609 bfd_put_32 (abfd, (bfd_vma) insn, hit_data);
17505c5c
NC		 610 break;
611#endif
252b5132
RH		 612 case R_SH_PCDISP:
613 insn = bfd_get_16 (abfd, hit_data);
614 sym_value += reloc_entry->addend;
615 sym_value -= (input_section->output_section->vma
616 + input_section->output_offset
617 + addr
618 + 4);
619 sym_value += (insn & 0xfff) << 1;
620 if (insn & 0x800)
621 sym_value -= 0x1000;
622 insn = (insn & 0xf000) | (sym_value & 0xfff);
dc810e39 623 bfd_put_16 (abfd, (bfd_vma) insn, hit_data);
252b5132
RH		 624 if (sym_value < (bfd_vma) -0x1000 || sym_value >= 0x1000)
625 return bfd_reloc_overflow;
626 break;
627 default:
628 abort ();
629 break;
630 }
631
632 return bfd_reloc_ok;
633}
634
875f7f69 635#define coff_bfd_merge_private_bfd_data _bfd_generic_verify_endian_match
252b5132
RH		 636
637/* We can do relaxing. */
638#define coff_bfd_relax_section sh_relax_section
639
640/* We use the special COFF backend linker. */
641#define coff_relocate_section sh_relocate_section
642
643/* When relaxing, we need to use special code to get the relocated
644 section contents. */
645#define coff_bfd_get_relocated_section_contents \
646 sh_coff_get_relocated_section_contents
647
648#include "coffcode.h"
649\f
650/* This function handles relaxing on the SH.
651
652 Function calls on the SH look like this:
653
654 movl L1,r0
655 ...
656 jsr @r0
657 ...
658 L1:
659 .long function
660
661 The compiler and assembler will cooperate to create R_SH_USES
662 relocs on the jsr instructions. The r_offset field of the
663 R_SH_USES reloc is the PC relative offset to the instruction which
664 loads the register (the r_offset field is computed as though it
665 were a jump instruction, so the offset value is actually from four
666 bytes past the instruction). The linker can use this reloc to
667 determine just which function is being called, and thus decide
668 whether it is possible to replace the jsr with a bsr.
669
670 If multiple function calls are all based on a single register load
671 (i.e., the same function is called multiple times), the compiler
672 guarantees that each function call will have an R_SH_USES reloc.
673 Therefore, if the linker is able to convert each R_SH_USES reloc
674 which refers to that address, it can safely eliminate the register
675 load.
676
677 When the assembler creates an R_SH_USES reloc, it examines it to
678 determine which address is being loaded (L1 in the above example).
679 It then counts the number of references to that address, and
680 creates an R_SH_COUNT reloc at that address. The r_offset field of
681 the R_SH_COUNT reloc will be the number of references. If the
682 linker is able to eliminate a register load, it can use the
683 R_SH_COUNT reloc to see whether it can also eliminate the function
684 address.
685
686 SH relaxing also handles another, unrelated, matter. On the SH, if
687 a load or store instruction is not aligned on a four byte boundary,
688 the memory cycle interferes with the 32 bit instruction fetch,
689 causing a one cycle bubble in the pipeline. Therefore, we try to
690 align load and store instructions on four byte boundaries if we
691 can, by swapping them with one of the adjacent instructions. */
692
b34976b6 693static bfd_boolean
252b5132
RH		 694sh_relax_section (abfd, sec, link_info, again)
695 bfd *abfd;
696 asection *sec;
697 struct bfd_link_info *link_info;
b34976b6 698 bfd_boolean *again;
252b5132
RH		 699{
700 struct internal_reloc *internal_relocs;
b34976b6 701 bfd_boolean have_code;
252b5132
RH		 702 struct internal_reloc *irel, *irelend;
703 bfd_byte *contents = NULL;
252b5132 704
b34976b6 705 *again = FALSE;
252b5132 706
1049f94e 707 if (link_info->relocatable
252b5132
RH		 708 || (sec->flags & SEC_RELOC) == 0
709 || sec->reloc_count == 0)
b34976b6 710 return TRUE;
252b5132 711
eea6121a
AM		 712 if (coff_section_data (abfd, sec) == NULL)
713 {
714 bfd_size_type amt = sizeof (struct coff_section_tdata);
715 sec->used_by_bfd = (PTR) bfd_zalloc (abfd, amt);
716 if (sec->used_by_bfd == NULL)
717 return FALSE;
718 }
252b5132
RH		 719
720 internal_relocs = (_bfd_coff_read_internal_relocs
721 (abfd, sec, link_info->keep_memory,
b34976b6 722 (bfd_byte *) NULL, FALSE,
252b5132
RH		 723 (struct internal_reloc *) NULL));
724 if (internal_relocs == NULL)
725 goto error_return;
252b5132 726
b34976b6 727 have_code = FALSE;
252b5132
RH		 728
729 irelend = internal_relocs + sec->reloc_count;
730 for (irel = internal_relocs; irel < irelend; irel++)
731 {
732 bfd_vma laddr, paddr, symval;
733 unsigned short insn;
734 struct internal_reloc *irelfn, *irelscan, *irelcount;
735 struct internal_syment sym;
736 bfd_signed_vma foff;
737
738 if (irel->r_type == R_SH_CODE)
b34976b6 739 have_code = TRUE;
252b5132
RH		 740
741 if (irel->r_type != R_SH_USES)
742 continue;
743
744 /* Get the section contents. */
745 if (contents == NULL)
746 {
eea6121a 747 if (coff_section_data (abfd, sec)->contents != NULL)
252b5132
RH		 748 contents = coff_section_data (abfd, sec)->contents;
749 else
750 {
eea6121a 751 if (!bfd_malloc_and_get_section (abfd, sec, &contents))
252b5132
RH		 752 goto error_return;
753 }
754 }
755
756 /* The r_offset field of the R_SH_USES reloc will point us to
757 the register load. The 4 is because the r_offset field is
758 computed as though it were a jump offset, which are based
759 from 4 bytes after the jump instruction. */
760 laddr = irel->r_vaddr - sec->vma + 4;
761 /* Careful to sign extend the 32-bit offset. */
762 laddr += ((irel->r_offset & 0xffffffff) ^ 0x80000000) - 0x80000000;
eea6121a 763 if (laddr >= sec->size)
252b5132 764 {
d003868e
AM		 765 (*_bfd_error_handler) ("%B: 0x%lx: warning: bad R_SH_USES offset",
766 abfd, (unsigned long) irel->r_vaddr);
252b5132
RH		 767 continue;
768 }
769 insn = bfd_get_16 (abfd, contents + laddr);
770
771 /* If the instruction is not mov.l NN,rN, we don't know what to do. */
772 if ((insn & 0xf000) != 0xd000)
773 {
774 ((*_bfd_error_handler)
d003868e
AM		 775 ("%B: 0x%lx: warning: R_SH_USES points to unrecognized insn 0x%x",
776 abfd, (unsigned long) irel->r_vaddr, insn));
252b5132
RH		 777 continue;
778 }
779
780 /* Get the address from which the register is being loaded. The
781 displacement in the mov.l instruction is quadrupled. It is a
782 displacement from four bytes after the movl instruction, but,
783 before adding in the PC address, two least significant bits
784 of the PC are cleared. We assume that the section is aligned
785 on a four byte boundary. */
786 paddr = insn & 0xff;
787 paddr *= 4;
dc810e39 788 paddr += (laddr + 4) &~ (bfd_vma) 3;
eea6121a 789 if (paddr >= sec->size)
252b5132
RH		 790 {
791 ((*_bfd_error_handler)
d003868e
AM		 792 ("%B: 0x%lx: warning: bad R_SH_USES load offset",
793 abfd, (unsigned long) irel->r_vaddr));
252b5132
RH		 794 continue;
795 }
796
797 /* Get the reloc for the address from which the register is
798 being loaded. This reloc will tell us which function is
799 actually being called. */
800 paddr += sec->vma;
801 for (irelfn = internal_relocs; irelfn < irelend; irelfn++)
802 if (irelfn->r_vaddr == paddr
17505c5c
NC		 803#ifdef COFF_WITH_PE
804 && (irelfn->r_type == R_SH_IMM32
805 || irelfn->r_type == R_SH_IMM32CE
eea6121a 806 || irelfn->r_type == R_SH_IMAGEBASE)
17505c5c
NC		 807
808#else
eea6121a 809 && irelfn->r_type == R_SH_IMM32
17505c5c 810#endif
eea6121a 811 )
252b5132
RH		 812 break;
813 if (irelfn >= irelend)
814 {
815 ((*_bfd_error_handler)
d003868e
AM		 816 ("%B: 0x%lx: warning: could not find expected reloc",
817 abfd, (unsigned long) paddr));
252b5132
RH		 818 continue;
819 }
820
821 /* Get the value of the symbol referred to by the reloc. */
822 if (! _bfd_coff_get_external_symbols (abfd))
823 goto error_return;
824 bfd_coff_swap_sym_in (abfd,
825 ((bfd_byte *) obj_coff_external_syms (abfd)
826 + (irelfn->r_symndx
827 * bfd_coff_symesz (abfd))),
828 &sym);
829 if (sym.n_scnum != 0 && sym.n_scnum != sec->target_index)
830 {
831 ((*_bfd_error_handler)
d003868e
AM		 832 ("%B: 0x%lx: warning: symbol in unexpected section",
833 abfd, (unsigned long) paddr));
252b5132
RH		 834 continue;
835 }
836
837 if (sym.n_sclass != C_EXT)
838 {
839 symval = (sym.n_value
840 - sec->vma
841 + sec->output_section->vma
842 + sec->output_offset);
843 }
844 else
845 {
846 struct coff_link_hash_entry *h;
847
848 h = obj_coff_sym_hashes (abfd)[irelfn->r_symndx];
849 BFD_ASSERT (h != NULL);
850 if (h->root.type != bfd_link_hash_defined
851 && h->root.type != bfd_link_hash_defweak)
852 {
853 /* This appears to be a reference to an undefined
854 symbol. Just ignore it--it will be caught by the
855 regular reloc processing. */
856 continue;
857 }
858
859 symval = (h->root.u.def.value
860 + h->root.u.def.section->output_section->vma
861 + h->root.u.def.section->output_offset);
862 }
863
864 symval += bfd_get_32 (abfd, contents + paddr - sec->vma);
865
866 /* See if this function call can be shortened. */
867 foff = (symval
868 - (irel->r_vaddr
869 - sec->vma
870 + sec->output_section->vma
871 + sec->output_offset
872 + 4));
873 if (foff < -0x1000 || foff >= 0x1000)
874 {
875 /* After all that work, we can't shorten this function call. */
876 continue;
877 }
878
879 /* Shorten the function call. */
880
881 /* For simplicity of coding, we are going to modify the section
882 contents, the section relocs, and the BFD symbol table. We
883 must tell the rest of the code not to free up this
884 information. It would be possible to instead create a table
885 of changes which have to be made, as is done in coff-mips.c;
886 that would be more work, but would require less memory when
887 the linker is run. */
888
252b5132 889 coff_section_data (abfd, sec)->relocs = internal_relocs;
b34976b6 890 coff_section_data (abfd, sec)->keep_relocs = TRUE;
252b5132
RH		 891
892 coff_section_data (abfd, sec)->contents = contents;
b34976b6 893 coff_section_data (abfd, sec)->keep_contents = TRUE;
252b5132 894
b34976b6 895 obj_coff_keep_syms (abfd) = TRUE;
252b5132
RH		 896
897 /* Replace the jsr with a bsr. */
898
899 /* Change the R_SH_USES reloc into an R_SH_PCDISP reloc, and
900 replace the jsr with a bsr. */
901 irel->r_type = R_SH_PCDISP;
902 irel->r_symndx = irelfn->r_symndx;
903 if (sym.n_sclass != C_EXT)
904 {
905 /* If this needs to be changed because of future relaxing,
906 it will be handled here like other internal PCDISP
907 relocs. */
908 bfd_put_16 (abfd,
dc810e39 909 (bfd_vma) 0xb000 | ((foff >> 1) & 0xfff),
252b5132
RH		 910 contents + irel->r_vaddr - sec->vma);
911 }
912 else
913 {
914 /* We can't fully resolve this yet, because the external
915 symbol value may be changed by future relaxing. We let
916 the final link phase handle it. */
dc810e39
AM		 917 bfd_put_16 (abfd, (bfd_vma) 0xb000,
918 contents + irel->r_vaddr - sec->vma);
252b5132
RH		 919 }
920
921 /* See if there is another R_SH_USES reloc referring to the same
922 register load. */
923 for (irelscan = internal_relocs; irelscan < irelend; irelscan++)
924 if (irelscan->r_type == R_SH_USES
925 && laddr == irelscan->r_vaddr - sec->vma + 4 + irelscan->r_offset)
926 break;
927 if (irelscan < irelend)
928 {
929 /* Some other function call depends upon this register load,
930 and we have not yet converted that function call.
931 Indeed, we may never be able to convert it. There is
932 nothing else we can do at this point. */
933 continue;
934 }
935
936 /* Look for a R_SH_COUNT reloc on the location where the
937 function address is stored. Do this before deleting any
938 bytes, to avoid confusion about the address. */
939 for (irelcount = internal_relocs; irelcount < irelend; irelcount++)
940 if (irelcount->r_vaddr == paddr
941 && irelcount->r_type == R_SH_COUNT)
942 break;
943
944 /* Delete the register load. */
945 if (! sh_relax_delete_bytes (abfd, sec, laddr, 2))
946 goto error_return;
947
948 /* That will change things, so, just in case it permits some
949 other function call to come within range, we should relax
950 again. Note that this is not required, and it may be slow. */
b34976b6 951 *again = TRUE;
252b5132
RH		 952
953 /* Now check whether we got a COUNT reloc. */
954 if (irelcount >= irelend)
955 {
956 ((*_bfd_error_handler)
d003868e
AM		 957 ("%B: 0x%lx: warning: could not find expected COUNT reloc",
958 abfd, (unsigned long) paddr));
252b5132
RH		 959 continue;
960 }
961
962 /* The number of uses is stored in the r_offset field. We've
963 just deleted one. */
964 if (irelcount->r_offset == 0)
965 {
d003868e
AM		 966 ((*_bfd_error_handler) ("%B: 0x%lx: warning: bad count",
967 abfd, (unsigned long) paddr));
252b5132
RH		 968 continue;
969 }
970
971 --irelcount->r_offset;
972
973 /* If there are no more uses, we can delete the address. Reload
974 the address from irelfn, in case it was changed by the
975 previous call to sh_relax_delete_bytes. */
976 if (irelcount->r_offset == 0)
977 {
978 if (! sh_relax_delete_bytes (abfd, sec,
979 irelfn->r_vaddr - sec->vma, 4))
980 goto error_return;
981 }
982
983 /* We've done all we can with that function call. */
984 }
985
986 /* Look for load and store instructions that we can align on four
987 byte boundaries. */
988 if (have_code)
989 {
b34976b6 990 bfd_boolean swapped;
252b5132
RH		 991
992 /* Get the section contents. */
993 if (contents == NULL)
994 {
eea6121a 995 if (coff_section_data (abfd, sec)->contents != NULL)
252b5132
RH		 996 contents = coff_section_data (abfd, sec)->contents;
997 else
998 {
eea6121a 999 if (!bfd_malloc_and_get_section (abfd, sec, &contents))
252b5132
RH		 1000 goto error_return;
1001 }
1002 }
1003
1004 if (! sh_align_loads (abfd, sec, internal_relocs, contents, &swapped))
1005 goto error_return;
1006
1007 if (swapped)
1008 {
252b5132 1009 coff_section_data (abfd, sec)->relocs = internal_relocs;
b34976b6 1010 coff_section_data (abfd, sec)->keep_relocs = TRUE;
252b5132
RH		 1011
1012 coff_section_data (abfd, sec)->contents = contents;
b34976b6 1013 coff_section_data (abfd, sec)->keep_contents = TRUE;
252b5132 1014
b34976b6 1015 obj_coff_keep_syms (abfd) = TRUE;
252b5132
RH		 1016 }
1017 }
1018
eea6121a
AM		 1019 if (internal_relocs != NULL
1020 && internal_relocs != coff_section_data (abfd, sec)->relocs)
252b5132 1021 {
eea6121a
AM		 1022 if (! link_info->keep_memory)
1023 free (internal_relocs);
1024 else
1025 coff_section_data (abfd, sec)->relocs = internal_relocs;
252b5132
RH		 1026 }
1027
eea6121a 1028 if (contents != NULL && contents != coff_section_data (abfd, sec)->contents)
252b5132
RH		 1029 {
1030 if (! link_info->keep_memory)
eea6121a 1031 free (contents);
252b5132 1032 else
eea6121a
AM		 1033 /* Cache the section contents for coff_link_input_bfd. */
1034 coff_section_data (abfd, sec)->contents = contents;
252b5132
RH		 1035 }
1036
b34976b6 1037 return TRUE;
252b5132
RH		 1038
1039 error_return:
eea6121a
AM		 1040 if (internal_relocs != NULL
1041 && internal_relocs != coff_section_data (abfd, sec)->relocs)
1042 free (internal_relocs);
1043 if (contents != NULL && contents != coff_section_data (abfd, sec)->contents)
1044 free (contents);
b34976b6 1045 return FALSE;
252b5132
RH		 1046}
1047
1048/* Delete some bytes from a section while relaxing. */
1049
b34976b6 1050static bfd_boolean
252b5132
RH		 1051sh_relax_delete_bytes (abfd, sec, addr, count)
1052 bfd *abfd;
1053 asection *sec;
1054 bfd_vma addr;
1055 int count;
1056{
1057 bfd_byte *contents;
1058 struct internal_reloc *irel, *irelend;
1059 struct internal_reloc *irelalign;
1060 bfd_vma toaddr;
1061 bfd_byte *esym, *esymend;
1062 bfd_size_type symesz;
1063 struct coff_link_hash_entry **sym_hash;
1064 asection *o;
1065
1066 contents = coff_section_data (abfd, sec)->contents;
1067
1068 /* The deletion must stop at the next ALIGN reloc for an aligment
1069 power larger than the number of bytes we are deleting. */
1070
1071 irelalign = NULL;
eea6121a 1072 toaddr = sec->size;
252b5132
RH		 1073
1074 irel = coff_section_data (abfd, sec)->relocs;
1075 irelend = irel + sec->reloc_count;
1076 for (; irel < irelend; irel++)
1077 {
1078 if (irel->r_type == R_SH_ALIGN
1079 && irel->r_vaddr - sec->vma > addr
1080 && count < (1 << irel->r_offset))
1081 {
1082 irelalign = irel;
1083 toaddr = irel->r_vaddr - sec->vma;
1084 break;
1085 }
1086 }
1087
1088 /* Actually delete the bytes. */
dc810e39
AM		 1089 memmove (contents + addr, contents + addr + count,
1090 (size_t) (toaddr - addr - count));
252b5132 1091 if (irelalign == NULL)
eea6121a 1092 sec->size -= count;
252b5132
RH		 1093 else
1094 {
1095 int i;
1096
1097#define NOP_OPCODE (0x0009)
1098
1099 BFD_ASSERT ((count & 1) == 0);
1100 for (i = 0; i < count; i += 2)
dc810e39 1101 bfd_put_16 (abfd, (bfd_vma) NOP_OPCODE, contents + toaddr - count + i);
252b5132
RH		 1102 }
1103
1104 /* Adjust all the relocs. */
1105 for (irel = coff_section_data (abfd, sec)->relocs; irel < irelend; irel++)
1106 {
1107 bfd_vma nraddr, stop;
1108 bfd_vma start = 0;
1109 int insn = 0;
1110 struct internal_syment sym;
1111 int off, adjust, oinsn;
1112 bfd_signed_vma voff = 0;
b34976b6 1113 bfd_boolean overflow;
252b5132
RH		 1114
1115 /* Get the new reloc address. */
1116 nraddr = irel->r_vaddr - sec->vma;
1117 if ((irel->r_vaddr - sec->vma > addr
1118 && irel->r_vaddr - sec->vma < toaddr)
1119 || (irel->r_type == R_SH_ALIGN
1120 && irel->r_vaddr - sec->vma == toaddr))
1121 nraddr -= count;
1122
1123 /* See if this reloc was for the bytes we have deleted, in which
1124 case we no longer care about it. Don't delete relocs which
1125 represent addresses, though. */
1126 if (irel->r_vaddr - sec->vma >= addr
1127 && irel->r_vaddr - sec->vma < addr + count
1128 && irel->r_type != R_SH_ALIGN
1129 && irel->r_type != R_SH_CODE
1130 && irel->r_type != R_SH_DATA
1131 && irel->r_type != R_SH_LABEL)
1132 irel->r_type = R_SH_UNUSED;
1133
1134 /* If this is a PC relative reloc, see if the range it covers
1135 includes the bytes we have deleted. */
1136 switch (irel->r_type)
1137 {
1138 default:
1139 break;
1140
1141 case R_SH_PCDISP8BY2:
1142 case R_SH_PCDISP:
1143 case R_SH_PCRELIMM8BY2:
1144 case R_SH_PCRELIMM8BY4:
1145 start = irel->r_vaddr - sec->vma;
1146 insn = bfd_get_16 (abfd, contents + nraddr);
1147 break;
1148 }
1149
1150 switch (irel->r_type)
1151 {
1152 default:
1153 start = stop = addr;
1154 break;
1155
1156 case R_SH_IMM32:
17505c5c
NC		 1157#ifdef COFF_WITH_PE
1158 case R_SH_IMM32CE:
1159 case R_SH_IMAGEBASE:
1160#endif
252b5132
RH		 1161 /* If this reloc is against a symbol defined in this
1162 section, and the symbol will not be adjusted below, we
1163 must check the addend to see it will put the value in
1164 range to be adjusted, and hence must be changed. */
1165 bfd_coff_swap_sym_in (abfd,
1166 ((bfd_byte *) obj_coff_external_syms (abfd)
1167 + (irel->r_symndx
1168 * bfd_coff_symesz (abfd))),
1169 &sym);
1170 if (sym.n_sclass != C_EXT
1171 && sym.n_scnum == sec->target_index
1172 && ((bfd_vma) sym.n_value <= addr
1173 || (bfd_vma) sym.n_value >= toaddr))
1174 {
1175 bfd_vma val;
1176
1177 val = bfd_get_32 (abfd, contents + nraddr);
1178 val += sym.n_value;
1179 if (val > addr && val < toaddr)
1180 bfd_put_32 (abfd, val - count, contents + nraddr);
1181 }
1182 start = stop = addr;
1183 break;
1184
1185 case R_SH_PCDISP8BY2:
1186 off = insn & 0xff;
1187 if (off & 0x80)
1188 off -= 0x100;
1189 stop = (bfd_vma) ((bfd_signed_vma) start + 4 + off * 2);
1190 break;
1191
1192 case R_SH_PCDISP:
1193 bfd_coff_swap_sym_in (abfd,
1194 ((bfd_byte *) obj_coff_external_syms (abfd)
1195 + (irel->r_symndx
1196 * bfd_coff_symesz (abfd))),
1197 &sym);
1198 if (sym.n_sclass == C_EXT)
1199 start = stop = addr;
1200 else
1201 {
1202 off = insn & 0xfff;
1203 if (off & 0x800)
1204 off -= 0x1000;
1205 stop = (bfd_vma) ((bfd_signed_vma) start + 4 + off * 2);
1206 }
1207 break;
1208
1209 case R_SH_PCRELIMM8BY2:
1210 off = insn & 0xff;
1211 stop = start + 4 + off * 2;
1212 break;
1213
1214 case R_SH_PCRELIMM8BY4:
1215 off = insn & 0xff;
1216 stop = (start &~ (bfd_vma) 3) + 4 + off * 4;
1217 break;
1218
1219 case R_SH_SWITCH8:
1220 case R_SH_SWITCH16:
1221 case R_SH_SWITCH32:
1222 /* These relocs types represent
1223 .word L2-L1
1224 The r_offset field holds the difference between the reloc
1225 address and L1. That is the start of the reloc, and
1226 adding in the contents gives us the top. We must adjust
1227 both the r_offset field and the section contents. */
1228
1229 start = irel->r_vaddr - sec->vma;
1230 stop = (bfd_vma) ((bfd_signed_vma) start - (long) irel->r_offset);
1231
1232 if (start > addr
1233 && start < toaddr
1234 && (stop <= addr || stop >= toaddr))
1235 irel->r_offset += count;
1236 else if (stop > addr
1237 && stop < toaddr
1238 && (start <= addr || start >= toaddr))
1239 irel->r_offset -= count;
1240
1241 start = stop;
1242
1243 if (irel->r_type == R_SH_SWITCH16)
1244 voff = bfd_get_signed_16 (abfd, contents + nraddr);
1245 else if (irel->r_type == R_SH_SWITCH8)
1246 voff = bfd_get_8 (abfd, contents + nraddr);
1247 else
1248 voff = bfd_get_signed_32 (abfd, contents + nraddr);
1249 stop = (bfd_vma) ((bfd_signed_vma) start + voff);
1250
1251 break;
1252
1253 case R_SH_USES:
1254 start = irel->r_vaddr - sec->vma;
1255 stop = (bfd_vma) ((bfd_signed_vma) start
1256 + (long) irel->r_offset
1257 + 4);
1258 break;
1259 }
1260
1261 if (start > addr
1262 && start < toaddr
1263 && (stop <= addr || stop >= toaddr))
1264 adjust = count;
1265 else if (stop > addr
1266 && stop < toaddr
1267 && (start <= addr || start >= toaddr))
1268 adjust = - count;
1269 else
1270 adjust = 0;
1271
1272 if (adjust != 0)
1273 {
1274 oinsn = insn;
b34976b6 1275 overflow = FALSE;
252b5132
RH		 1276 switch (irel->r_type)
1277 {
1278 default:
1279 abort ();
1280 break;
1281
1282 case R_SH_PCDISP8BY2:
1283 case R_SH_PCRELIMM8BY2:
1284 insn += adjust / 2;
1285 if ((oinsn & 0xff00) != (insn & 0xff00))
b34976b6 1286 overflow = TRUE;
dc810e39 1287 bfd_put_16 (abfd, (bfd_vma) insn, contents + nraddr);
252b5132
RH		 1288 break;
1289
1290 case R_SH_PCDISP:
1291 insn += adjust / 2;
1292 if ((oinsn & 0xf000) != (insn & 0xf000))
b34976b6 1293 overflow = TRUE;
dc810e39 1294 bfd_put_16 (abfd, (bfd_vma) insn, contents + nraddr);
252b5132
RH		 1295 break;
1296
1297 case R_SH_PCRELIMM8BY4:
1298 BFD_ASSERT (adjust == count || count >= 4);
1299 if (count >= 4)
1300 insn += adjust / 4;
1301 else
1302 {
1303 if ((irel->r_vaddr & 3) == 0)
1304 ++insn;
1305 }
1306 if ((oinsn & 0xff00) != (insn & 0xff00))
b34976b6 1307 overflow = TRUE;
dc810e39 1308 bfd_put_16 (abfd, (bfd_vma) insn, contents + nraddr);
252b5132
RH		 1309 break;
1310
1311 case R_SH_SWITCH8:
1312 voff += adjust;
1313 if (voff < 0 || voff >= 0xff)
b34976b6 1314 overflow = TRUE;
dc810e39 1315 bfd_put_8 (abfd, (bfd_vma) voff, contents + nraddr);
252b5132
RH		 1316 break;
1317
1318 case R_SH_SWITCH16:
1319 voff += adjust;
1320 if (voff < - 0x8000 || voff >= 0x8000)
b34976b6 1321 overflow = TRUE;
dc810e39 1322 bfd_put_signed_16 (abfd, (bfd_vma) voff, contents + nraddr);
252b5132
RH		 1323 break;
1324
1325 case R_SH_SWITCH32:
1326 voff += adjust;
dc810e39 1327 bfd_put_signed_32 (abfd, (bfd_vma) voff, contents + nraddr);
252b5132
RH		 1328 break;
1329
1330 case R_SH_USES:
1331 irel->r_offset += adjust;
1332 break;
1333 }
1334
1335 if (overflow)
1336 {
1337 ((*_bfd_error_handler)
d003868e
AM		 1338 ("%B: 0x%lx: fatal: reloc overflow while relaxing",
1339 abfd, (unsigned long) irel->r_vaddr));
252b5132 1340 bfd_set_error (bfd_error_bad_value);
b34976b6 1341 return FALSE;
252b5132
RH		 1342 }
1343 }
1344
1345 irel->r_vaddr = nraddr + sec->vma;
1346 }
1347
1348 /* Look through all the other sections. If there contain any IMM32
1349 relocs against internal symbols which we are not going to adjust
1350 below, we may need to adjust the addends. */
1351 for (o = abfd->sections; o != NULL; o = o->next)
1352 {
1353 struct internal_reloc *internal_relocs;
1354 struct internal_reloc *irelscan, *irelscanend;
1355 bfd_byte *ocontents;
1356
1357 if (o == sec
1358 || (o->flags & SEC_RELOC) == 0
1359 || o->reloc_count == 0)
1360 continue;
1361
1362 /* We always cache the relocs. Perhaps, if info->keep_memory is
b34976b6 1363 FALSE, we should free them, if we are permitted to, when we
252b5132
RH		 1364 leave sh_coff_relax_section. */
1365 internal_relocs = (_bfd_coff_read_internal_relocs
b34976b6 1366 (abfd, o, TRUE, (bfd_byte *) NULL, FALSE,
252b5132
RH		 1367 (struct internal_reloc *) NULL));
1368 if (internal_relocs == NULL)
b34976b6 1369 return FALSE;
252b5132
RH		 1370
1371 ocontents = NULL;
1372 irelscanend = internal_relocs + o->reloc_count;
1373 for (irelscan = internal_relocs; irelscan < irelscanend; irelscan++)
1374 {
1375 struct internal_syment sym;
1376
17505c5c
NC		 1377#ifdef COFF_WITH_PE
1378 if (irelscan->r_type != R_SH_IMM32
1379 && irelscan->r_type != R_SH_IMAGEBASE
1380 && irelscan->r_type != R_SH_IMM32CE)
1381#else
252b5132 1382 if (irelscan->r_type != R_SH_IMM32)
17505c5c 1383#endif
252b5132
RH		 1384 continue;
1385
1386 bfd_coff_swap_sym_in (abfd,
1387 ((bfd_byte *) obj_coff_external_syms (abfd)
1388 + (irelscan->r_symndx
1389 * bfd_coff_symesz (abfd))),
1390 &sym);
1391 if (sym.n_sclass != C_EXT
1392 && sym.n_scnum == sec->target_index
1393 && ((bfd_vma) sym.n_value <= addr
1394 || (bfd_vma) sym.n_value >= toaddr))
1395 {
1396 bfd_vma val;
1397
1398 if (ocontents == NULL)
1399 {
1400 if (coff_section_data (abfd, o)->contents != NULL)
1401 ocontents = coff_section_data (abfd, o)->contents;
1402 else
1403 {
eea6121a
AM		 1404 if (!bfd_malloc_and_get_section (abfd, o, &ocontents))
1405 return FALSE;
252b5132 1406 /* We always cache the section contents.
b34976b6 1407 Perhaps, if info->keep_memory is FALSE, we
252b5132
RH		 1408 should free them, if we are permitted to,
1409 when we leave sh_coff_relax_section. */
252b5132
RH		 1410 coff_section_data (abfd, o)->contents = ocontents;
1411 }
1412 }
1413
1414 val = bfd_get_32 (abfd, ocontents + irelscan->r_vaddr - o->vma);
1415 val += sym.n_value;
1416 if (val > addr && val < toaddr)
1417 bfd_put_32 (abfd, val - count,
1418 ocontents + irelscan->r_vaddr - o->vma);
1419
b34976b6 1420 coff_section_data (abfd, o)->keep_contents = TRUE;
252b5132
RH		 1421 }
1422 }
1423 }
1424
1425 /* Adjusting the internal symbols will not work if something has
1426 already retrieved the generic symbols. It would be possible to
1427 make this work by adjusting the generic symbols at the same time.
1428 However, this case should not arise in normal usage. */
1429 if (obj_symbols (abfd) != NULL
1430 || obj_raw_syments (abfd) != NULL)
1431 {
1432 ((*_bfd_error_handler)
d003868e 1433 ("%B: fatal: generic symbols retrieved before relaxing", abfd));
252b5132 1434 bfd_set_error (bfd_error_invalid_operation);
b34976b6 1435 return FALSE;
252b5132
RH		 1436 }
1437
1438 /* Adjust all the symbols. */
1439 sym_hash = obj_coff_sym_hashes (abfd);
1440 symesz = bfd_coff_symesz (abfd);
1441 esym = (bfd_byte *) obj_coff_external_syms (abfd);
1442 esymend = esym + obj_raw_syment_count (abfd) * symesz;
1443 while (esym < esymend)
1444 {
1445 struct internal_syment isym;
1446
1447 bfd_coff_swap_sym_in (abfd, (PTR) esym, (PTR) &isym);
1448
1449 if (isym.n_scnum == sec->target_index
1450 && (bfd_vma) isym.n_value > addr
1451 && (bfd_vma) isym.n_value < toaddr)
1452 {
1453 isym.n_value -= count;
1454
1455 bfd_coff_swap_sym_out (abfd, (PTR) &isym, (PTR) esym);
1456
1457 if (*sym_hash != NULL)
1458 {
1459 BFD_ASSERT ((*sym_hash)->root.type == bfd_link_hash_defined
1460 || (*sym_hash)->root.type == bfd_link_hash_defweak);
1461 BFD_ASSERT ((*sym_hash)->root.u.def.value >= addr
1462 && (*sym_hash)->root.u.def.value < toaddr);
1463 (*sym_hash)->root.u.def.value -= count;
1464 }
1465 }
1466
1467 esym += (isym.n_numaux + 1) * symesz;
1468 sym_hash += isym.n_numaux + 1;
1469 }
1470
1471 /* See if we can move the ALIGN reloc forward. We have adjusted
1472 r_vaddr for it already. */
1473 if (irelalign != NULL)
1474 {
1475 bfd_vma alignto, alignaddr;
1476
1477 alignto = BFD_ALIGN (toaddr, 1 << irelalign->r_offset);
1478 alignaddr = BFD_ALIGN (irelalign->r_vaddr - sec->vma,
1479 1 << irelalign->r_offset);
1480 if (alignto != alignaddr)
1481 {
1482 /* Tail recursion. */
1483 return sh_relax_delete_bytes (abfd, sec, alignaddr,
dc810e39 1484 (int) (alignto - alignaddr));
252b5132
RH		 1485 }
1486 }
1487
b34976b6 1488 return TRUE;
252b5132
RH		 1489}
1490\f
1491/* This is yet another version of the SH opcode table, used to rapidly
1492 get information about a particular instruction. */
1493
1494/* The opcode map is represented by an array of these structures. The
1495 array is indexed by the high order four bits in the instruction. */
1496
1497struct sh_major_opcode
1498{
1499 /* A pointer to the instruction list. This is an array which
1500 contains all the instructions with this major opcode. */
1501 const struct sh_minor_opcode *minor_opcodes;
1502 /* The number of elements in minor_opcodes. */
1503 unsigned short count;
1504};
1505
1506/* This structure holds information for a set of SH opcodes. The
1507 instruction code is anded with the mask value, and the resulting
1508 value is used to search the order opcode list. */
1509
1510struct sh_minor_opcode
1511{
1512 /* The sorted opcode list. */
1513 const struct sh_opcode *opcodes;
1514 /* The number of elements in opcodes. */
1515 unsigned short count;
1516 /* The mask value to use when searching the opcode list. */
1517 unsigned short mask;
1518};
1519
1520/* This structure holds information for an SH instruction. An array
1521 of these structures is sorted in order by opcode. */
1522
1523struct sh_opcode
1524{
1525 /* The code for this instruction, after it has been anded with the
1526 mask value in the sh_major_opcode structure. */
1527 unsigned short opcode;
1528 /* Flags for this instruction. */
86033394 1529 unsigned long flags;
252b5132
RH		 1530};
1531
1532/* Flag which appear in the sh_opcode structure. */
1533
1534/* This instruction loads a value from memory. */
1535#define LOAD (0x1)
1536
1537/* This instruction stores a value to memory. */
1538#define STORE (0x2)
1539
1540/* This instruction is a branch. */
1541#define BRANCH (0x4)
1542
1543/* This instruction has a delay slot. */
1544#define DELAY (0x8)
1545
1546/* This instruction uses the value in the register in the field at
1547 mask 0x0f00 of the instruction. */
1548#define USES1 (0x10)
84dcfba7 1549#define USES1_REG(x) ((x & 0x0f00) >> 8)
252b5132
RH		 1550
1551/* This instruction uses the value in the register in the field at
1552 mask 0x00f0 of the instruction. */
1553#define USES2 (0x20)
84dcfba7 1554#define USES2_REG(x) ((x & 0x00f0) >> 4)
252b5132
RH		 1555
1556/* This instruction uses the value in register 0. */
1557#define USESR0 (0x40)
1558
1559/* This instruction sets the value in the register in the field at
1560 mask 0x0f00 of the instruction. */
1561#define SETS1 (0x80)
84dcfba7 1562#define SETS1_REG(x) ((x & 0x0f00) >> 8)
252b5132
RH		 1563
1564/* This instruction sets the value in the register in the field at
1565 mask 0x00f0 of the instruction. */
1566#define SETS2 (0x100)
84dcfba7 1567#define SETS2_REG(x) ((x & 0x00f0) >> 4)
252b5132
RH		 1568
1569/* This instruction sets register 0. */
1570#define SETSR0 (0x200)
1571
1572/* This instruction sets a special register. */
1573#define SETSSP (0x400)
1574
1575/* This instruction uses a special register. */
1576#define USESSP (0x800)
1577
1578/* This instruction uses the floating point register in the field at
1579 mask 0x0f00 of the instruction. */
1580#define USESF1 (0x1000)
84dcfba7 1581#define USESF1_REG(x) ((x & 0x0f00) >> 8)
252b5132
RH		 1582
1583/* This instruction uses the floating point register in the field at
1584 mask 0x00f0 of the instruction. */
1585#define USESF2 (0x2000)
84dcfba7 1586#define USESF2_REG(x) ((x & 0x00f0) >> 4)
252b5132
RH		 1587
1588/* This instruction uses floating point register 0. */
1589#define USESF0 (0x4000)
1590
1591/* This instruction sets the floating point register in the field at
1592 mask 0x0f00 of the instruction. */
1593#define SETSF1 (0x8000)
84dcfba7 1594#define SETSF1_REG(x) ((x & 0x0f00) >> 8)
252b5132 1595
d4845d57
JR		 1596#define USESAS (0x10000)
1597#define USESAS_REG(x) (((((x) >> 8) - 2) & 3) + 2)
1598#define USESR8 (0x20000)
1599#define SETSAS (0x40000)
1600#define SETSAS_REG(x) USESAS_REG (x)
1601
8d6ad26e
AM		 1602#define MAP(a) a, sizeof a / sizeof a[0]
1603
86033394 1604#ifndef COFF_IMAGE_WITH_PE
b34976b6 1605static bfd_boolean sh_insn_uses_reg
252b5132 1606 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int));
b34976b6 1607static bfd_boolean sh_insn_sets_reg
84dcfba7 1608 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int));
b34976b6 1609static bfd_boolean sh_insn_uses_or_sets_reg
84dcfba7 1610 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int));
b34976b6 1611static bfd_boolean sh_insn_uses_freg
252b5132 1612 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int));
b34976b6 1613static bfd_boolean sh_insn_sets_freg
84dcfba7 1614 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int));
b34976b6 1615static bfd_boolean sh_insn_uses_or_sets_freg
84dcfba7 1616 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int));
b34976b6 1617static bfd_boolean sh_insns_conflict
252b5132
RH		 1618 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int,
1619 const struct sh_opcode *));
b34976b6 1620static bfd_boolean sh_load_use
252b5132
RH		 1621 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int,
1622 const struct sh_opcode *));
252b5132 1623
8d6ad26e 1624/* The opcode maps. */
252b5132
RH		 1625
1626static const struct sh_opcode sh_opcode00[] =
1627{
1628 { 0x0008, SETSSP }, /* clrt */
1629 { 0x0009, 0 }, /* nop */
1630 { 0x000b, BRANCH | DELAY | USESSP }, /* rts */
1631 { 0x0018, SETSSP }, /* sett */
1632 { 0x0019, SETSSP }, /* div0u */
1633 { 0x001b, 0 }, /* sleep */
1634 { 0x0028, SETSSP }, /* clrmac */
1635 { 0x002b, BRANCH | DELAY | SETSSP }, /* rte */
1636 { 0x0038, USESSP | SETSSP }, /* ldtlb */
1637 { 0x0048, SETSSP }, /* clrs */
1638 { 0x0058, SETSSP } /* sets */
1639};
1640
1641static const struct sh_opcode sh_opcode01[] =
1642{
252b5132
RH		 1643 { 0x0003, BRANCH | DELAY | USES1 | SETSSP }, /* bsrf rn */
1644 { 0x000a, SETS1 | USESSP }, /* sts mach,rn */
252b5132 1645 { 0x001a, SETS1 | USESSP }, /* sts macl,rn */
252b5132
RH		 1646 { 0x0023, BRANCH | DELAY | USES1 }, /* braf rn */
1647 { 0x0029, SETS1 | USESSP }, /* movt rn */
1648 { 0x002a, SETS1 | USESSP }, /* sts pr,rn */
d4845d57
JR		 1649 { 0x005a, SETS1 | USESSP }, /* sts fpul,rn */
1650 { 0x006a, SETS1 | USESSP }, /* sts fpscr,rn / sts dsr,rn */
1651 { 0x0083, LOAD | USES1 }, /* pref @rn */
1652 { 0x007a, SETS1 | USESSP }, /* sts a0,rn */
1653 { 0x008a, SETS1 | USESSP }, /* sts x0,rn */
1654 { 0x009a, SETS1 | USESSP }, /* sts x1,rn */
1655 { 0x00aa, SETS1 | USESSP }, /* sts y0,rn */
1656 { 0x00ba, SETS1 | USESSP } /* sts y1,rn */
1657};
1658
252b5132
RH		 1659static const struct sh_opcode sh_opcode02[] =
1660{
d4845d57 1661 { 0x0002, SETS1 | USESSP }, /* stc <special_reg>,rn */
252b5132
RH		 1662 { 0x0004, STORE | USES1 | USES2 | USESR0 }, /* mov.b rm,@(r0,rn) */
1663 { 0x0005, STORE | USES1 | USES2 | USESR0 }, /* mov.w rm,@(r0,rn) */
1664 { 0x0006, STORE | USES1 | USES2 | USESR0 }, /* mov.l rm,@(r0,rn) */
1665 { 0x0007, SETSSP | USES1 | USES2 }, /* mul.l rm,rn */
1666 { 0x000c, LOAD | SETS1 | USES2 | USESR0 }, /* mov.b @(r0,rm),rn */
1667 { 0x000d, LOAD | SETS1 | USES2 | USESR0 }, /* mov.w @(r0,rm),rn */
1668 { 0x000e, LOAD | SETS1 | USES2 | USESR0 }, /* mov.l @(r0,rm),rn */
1669 { 0x000f, LOAD|SETS1|SETS2|SETSSP|USES1|USES2|USESSP }, /* mac.l @rm+,@rn+ */
1670};
1671
1672static const struct sh_minor_opcode sh_opcode0[] =
1673{
1674 { MAP (sh_opcode00), 0xffff },
1675 { MAP (sh_opcode01), 0xf0ff },
1676 { MAP (sh_opcode02), 0xf00f }
1677};
1678
1679static const struct sh_opcode sh_opcode10[] =
1680{
1681 { 0x1000, STORE | USES1 | USES2 } /* mov.l rm,@(disp,rn) */
1682};
1683
1684static const struct sh_minor_opcode sh_opcode1[] =
1685{
1686 { MAP (sh_opcode10), 0xf000 }
1687};
1688
1689static const struct sh_opcode sh_opcode20[] =
1690{
1691 { 0x2000, STORE | USES1 | USES2 }, /* mov.b rm,@rn */
1692 { 0x2001, STORE | USES1 | USES2 }, /* mov.w rm,@rn */
1693 { 0x2002, STORE | USES1 | USES2 }, /* mov.l rm,@rn */
1694 { 0x2004, STORE | SETS1 | USES1 | USES2 }, /* mov.b rm,@-rn */
1695 { 0x2005, STORE | SETS1 | USES1 | USES2 }, /* mov.w rm,@-rn */
1696 { 0x2006, STORE | SETS1 | USES1 | USES2 }, /* mov.l rm,@-rn */
1697 { 0x2007, SETSSP | USES1 | USES2 | USESSP }, /* div0s */
1698 { 0x2008, SETSSP | USES1 | USES2 }, /* tst rm,rn */
1699 { 0x2009, SETS1 | USES1 | USES2 }, /* and rm,rn */
1700 { 0x200a, SETS1 | USES1 | USES2 }, /* xor rm,rn */
1701 { 0x200b, SETS1 | USES1 | USES2 }, /* or rm,rn */
1702 { 0x200c, SETSSP | USES1 | USES2 }, /* cmp/str rm,rn */
1703 { 0x200d, SETS1 | USES1 | USES2 }, /* xtrct rm,rn */
1704 { 0x200e, SETSSP | USES1 | USES2 }, /* mulu.w rm,rn */
1705 { 0x200f, SETSSP | USES1 | USES2 } /* muls.w rm,rn */
1706};
1707
1708static const struct sh_minor_opcode sh_opcode2[] =
1709{
1710 { MAP (sh_opcode20), 0xf00f }
1711};
1712
1713static const struct sh_opcode sh_opcode30[] =
1714{
1715 { 0x3000, SETSSP | USES1 | USES2 }, /* cmp/eq rm,rn */
1716 { 0x3002, SETSSP | USES1 | USES2 }, /* cmp/hs rm,rn */
1717 { 0x3003, SETSSP | USES1 | USES2 }, /* cmp/ge rm,rn */
1718 { 0x3004, SETSSP | USESSP | USES1 | USES2 }, /* div1 rm,rn */
1719 { 0x3005, SETSSP | USES1 | USES2 }, /* dmulu.l rm,rn */
1720 { 0x3006, SETSSP | USES1 | USES2 }, /* cmp/hi rm,rn */
1721 { 0x3007, SETSSP | USES1 | USES2 }, /* cmp/gt rm,rn */
1722 { 0x3008, SETS1 | USES1 | USES2 }, /* sub rm,rn */
1723 { 0x300a, SETS1 | SETSSP | USES1 | USES2 | USESSP }, /* subc rm,rn */
1724 { 0x300b, SETS1 | SETSSP | USES1 | USES2 }, /* subv rm,rn */
1725 { 0x300c, SETS1 | USES1 | USES2 }, /* add rm,rn */
1726 { 0x300d, SETSSP | USES1 | USES2 }, /* dmuls.l rm,rn */
1727 { 0x300e, SETS1 | SETSSP | USES1 | USES2 | USESSP }, /* addc rm,rn */
1728 { 0x300f, SETS1 | SETSSP | USES1 | USES2 } /* addv rm,rn */
1729};
1730
1731static const struct sh_minor_opcode sh_opcode3[] =
1732{
1733 { MAP (sh_opcode30), 0xf00f }
1734};
1735
1736static const struct sh_opcode sh_opcode40[] =
1737{
1738 { 0x4000, SETS1 | SETSSP | USES1 }, /* shll rn */
1739 { 0x4001, SETS1 | SETSSP | USES1 }, /* shlr rn */
1740 { 0x4002, STORE | SETS1 | USES1 | USESSP }, /* sts.l mach,@-rn */
252b5132
RH		 1741 { 0x4004, SETS1 | SETSSP | USES1 }, /* rotl rn */
1742 { 0x4005, SETS1 | SETSSP | USES1 }, /* rotr rn */
1743 { 0x4006, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,mach */
252b5132
RH		 1744 { 0x4008, SETS1 | USES1 }, /* shll2 rn */
1745 { 0x4009, SETS1 | USES1 }, /* shlr2 rn */
1746 { 0x400a, SETSSP | USES1 }, /* lds rm,mach */
1747 { 0x400b, BRANCH | DELAY | USES1 }, /* jsr @rn */
252b5132
RH		 1748 { 0x4010, SETS1 | SETSSP | USES1 }, /* dt rn */
1749 { 0x4011, SETSSP | USES1 }, /* cmp/pz rn */
1750 { 0x4012, STORE | SETS1 | USES1 | USESSP }, /* sts.l macl,@-rn */
d4845d57 1751 { 0x4014, SETSSP | USES1 }, /* setrc rm */
252b5132
RH		 1752 { 0x4015, SETSSP | USES1 }, /* cmp/pl rn */
1753 { 0x4016, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,macl */
252b5132
RH		 1754 { 0x4018, SETS1 | USES1 }, /* shll8 rn */
1755 { 0x4019, SETS1 | USES1 }, /* shlr8 rn */
1756 { 0x401a, SETSSP | USES1 }, /* lds rm,macl */
1757 { 0x401b, LOAD | SETSSP | USES1 }, /* tas.b @rn */
252b5132
RH		 1758 { 0x4020, SETS1 | SETSSP | USES1 }, /* shal rn */
1759 { 0x4021, SETS1 | SETSSP | USES1 }, /* shar rn */
1760 { 0x4022, STORE | SETS1 | USES1 | USESSP }, /* sts.l pr,@-rn */
252b5132
RH		 1761 { 0x4024, SETS1 | SETSSP | USES1 | USESSP }, /* rotcl rn */
1762 { 0x4025, SETS1 | SETSSP | USES1 | USESSP }, /* rotcr rn */
1763 { 0x4026, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,pr */
252b5132
RH		 1764 { 0x4028, SETS1 | USES1 }, /* shll16 rn */
1765 { 0x4029, SETS1 | USES1 }, /* shlr16 rn */
1766 { 0x402a, SETSSP | USES1 }, /* lds rm,pr */
1767 { 0x402b, BRANCH | DELAY | USES1 }, /* jmp @rn */
d4845d57
JR		 1768 { 0x4052, STORE | SETS1 | USES1 | USESSP }, /* sts.l fpul,@-rn */
1769 { 0x4056, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,fpul */
1770 { 0x405a, SETSSP | USES1 }, /* lds.l rm,fpul */
1771 { 0x4062, STORE | SETS1 | USES1 | USESSP }, /* sts.l fpscr / dsr,@-rn */
1772 { 0x4066, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,fpscr / dsr */
1773 { 0x406a, SETSSP | USES1 }, /* lds rm,fpscr / lds rm,dsr */
1774 { 0x4072, STORE | SETS1 | USES1 | USESSP }, /* sts.l a0,@-rn */
1775 { 0x4076, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,a0 */
1776 { 0x407a, SETSSP | USES1 }, /* lds.l rm,a0 */
1777 { 0x4082, STORE | SETS1 | USES1 | USESSP }, /* sts.l x0,@-rn */
1778 { 0x4086, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,x0 */
1779 { 0x408a, SETSSP | USES1 }, /* lds.l rm,x0 */
1780 { 0x4092, STORE | SETS1 | USES1 | USESSP }, /* sts.l x1,@-rn */
1781 { 0x4096, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,x1 */
1782 { 0x409a, SETSSP | USES1 }, /* lds.l rm,x1 */
1783 { 0x40a2, STORE | SETS1 | USES1 | USESSP }, /* sts.l y0,@-rn */
1784 { 0x40a6, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,y0 */
1785 { 0x40aa, SETSSP | USES1 }, /* lds.l rm,y0 */
1786 { 0x40b2, STORE | SETS1 | USES1 | USESSP }, /* sts.l y1,@-rn */
1787 { 0x40b6, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,y1 */
1788 { 0x40ba, SETSSP | USES1 } /* lds.l rm,y1 */
252b5132
RH		 1789};
1790
1791static const struct sh_opcode sh_opcode41[] =
1792{
d4845d57
JR		 1793 { 0x4003, STORE | SETS1 | USES1 | USESSP }, /* stc.l <special_reg>,@-rn */
1794 { 0x4007, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,<special_reg> */
1795 { 0x400c, SETS1 | USES1 | USES2 }, /* shad rm,rn */
1796 { 0x400d, SETS1 | USES1 | USES2 }, /* shld rm,rn */
1797 { 0x400e, SETSSP | USES1 }, /* ldc rm,<special_reg> */
252b5132
RH		 1798 { 0x400f, LOAD|SETS1|SETS2|SETSSP|USES1|USES2|USESSP }, /* mac.w @rm+,@rn+ */
1799};
1800
1801static const struct sh_minor_opcode sh_opcode4[] =
1802{
1803 { MAP (sh_opcode40), 0xf0ff },
d4845d57 1804 { MAP (sh_opcode41), 0xf00f }
252b5132
RH		 1805};
1806
1807static const struct sh_opcode sh_opcode50[] =
1808{
1809 { 0x5000, LOAD | SETS1 | USES2 } /* mov.l @(disp,rm),rn */
1810};
1811
1812static const struct sh_minor_opcode sh_opcode5[] =
1813{
1814 { MAP (sh_opcode50), 0xf000 }
1815};
1816
1817static const struct sh_opcode sh_opcode60[] =
1818{
1819 { 0x6000, LOAD | SETS1 | USES2 }, /* mov.b @rm,rn */
1820 { 0x6001, LOAD | SETS1 | USES2 }, /* mov.w @rm,rn */
1821 { 0x6002, LOAD | SETS1 | USES2 }, /* mov.l @rm,rn */
1822 { 0x6003, SETS1 | USES2 }, /* mov rm,rn */
1823 { 0x6004, LOAD | SETS1 | SETS2 | USES2 }, /* mov.b @rm+,rn */
1824 { 0x6005, LOAD | SETS1 | SETS2 | USES2 }, /* mov.w @rm+,rn */
1825 { 0x6006, LOAD | SETS1 | SETS2 | USES2 }, /* mov.l @rm+,rn */
1826 { 0x6007, SETS1 | USES2 }, /* not rm,rn */
1827 { 0x6008, SETS1 | USES2 }, /* swap.b rm,rn */
1828 { 0x6009, SETS1 | USES2 }, /* swap.w rm,rn */
1829 { 0x600a, SETS1 | SETSSP | USES2 | USESSP }, /* negc rm,rn */
1830 { 0x600b, SETS1 | USES2 }, /* neg rm,rn */
1831 { 0x600c, SETS1 | USES2 }, /* extu.b rm,rn */
1832 { 0x600d, SETS1 | USES2 }, /* extu.w rm,rn */
1833 { 0x600e, SETS1 | USES2 }, /* exts.b rm,rn */
1834 { 0x600f, SETS1 | USES2 } /* exts.w rm,rn */
1835};
1836
1837static const struct sh_minor_opcode sh_opcode6[] =
1838{
1839 { MAP (sh_opcode60), 0xf00f }
1840};
1841
1842static const struct sh_opcode sh_opcode70[] =
1843{
1844 { 0x7000, SETS1 | USES1 } /* add #imm,rn */
1845};
1846
1847static const struct sh_minor_opcode sh_opcode7[] =
1848{
1849 { MAP (sh_opcode70), 0xf000 }
1850};
1851
1852static const struct sh_opcode sh_opcode80[] =
1853{
1854 { 0x8000, STORE | USES2 | USESR0 }, /* mov.b r0,@(disp,rn) */
1855 { 0x8100, STORE | USES2 | USESR0 }, /* mov.w r0,@(disp,rn) */
d4845d57 1856 { 0x8200, SETSSP }, /* setrc #imm */
252b5132
RH		 1857 { 0x8400, LOAD | SETSR0 | USES2 }, /* mov.b @(disp,rm),r0 */
1858 { 0x8500, LOAD | SETSR0 | USES2 }, /* mov.w @(disp,rn),r0 */
1859 { 0x8800, SETSSP | USESR0 }, /* cmp/eq #imm,r0 */
1860 { 0x8900, BRANCH | USESSP }, /* bt label */
1861 { 0x8b00, BRANCH | USESSP }, /* bf label */
d4845d57 1862 { 0x8c00, SETSSP }, /* ldrs @(disp,pc) */
252b5132 1863 { 0x8d00, BRANCH | DELAY | USESSP }, /* bt/s label */
d4845d57 1864 { 0x8e00, SETSSP }, /* ldre @(disp,pc) */
252b5132
RH		 1865 { 0x8f00, BRANCH | DELAY | USESSP } /* bf/s label */
1866};
1867
1868static const struct sh_minor_opcode sh_opcode8[] =
1869{
1870 { MAP (sh_opcode80), 0xff00 }
1871};
1872
1873static const struct sh_opcode sh_opcode90[] =
1874{
1875 { 0x9000, LOAD | SETS1 } /* mov.w @(disp,pc),rn */
1876};
1877
1878static const struct sh_minor_opcode sh_opcode9[] =
1879{
1880 { MAP (sh_opcode90), 0xf000 }
1881};
1882
1883static const struct sh_opcode sh_opcodea0[] =
1884{
1885 { 0xa000, BRANCH | DELAY } /* bra label */
1886};
1887
1888static const struct sh_minor_opcode sh_opcodea[] =
1889{
1890 { MAP (sh_opcodea0), 0xf000 }
1891};
1892
1893static const struct sh_opcode sh_opcodeb0[] =
1894{
1895 { 0xb000, BRANCH | DELAY } /* bsr label */
1896};
1897
1898static const struct sh_minor_opcode sh_opcodeb[] =
1899{
1900 { MAP (sh_opcodeb0), 0xf000 }
1901};
1902
1903static const struct sh_opcode sh_opcodec0[] =
1904{
1905 { 0xc000, STORE | USESR0 | USESSP }, /* mov.b r0,@(disp,gbr) */
1906 { 0xc100, STORE | USESR0 | USESSP }, /* mov.w r0,@(disp,gbr) */
1907 { 0xc200, STORE | USESR0 | USESSP }, /* mov.l r0,@(disp,gbr) */
1908 { 0xc300, BRANCH | USESSP }, /* trapa #imm */
1909 { 0xc400, LOAD | SETSR0 | USESSP }, /* mov.b @(disp,gbr),r0 */
1910 { 0xc500, LOAD | SETSR0 | USESSP }, /* mov.w @(disp,gbr),r0 */
1911 { 0xc600, LOAD | SETSR0 | USESSP }, /* mov.l @(disp,gbr),r0 */
1912 { 0xc700, SETSR0 }, /* mova @(disp,pc),r0 */
1913 { 0xc800, SETSSP | USESR0 }, /* tst #imm,r0 */
1914 { 0xc900, SETSR0 | USESR0 }, /* and #imm,r0 */
1915 { 0xca00, SETSR0 | USESR0 }, /* xor #imm,r0 */
1916 { 0xcb00, SETSR0 | USESR0 }, /* or #imm,r0 */
1917 { 0xcc00, LOAD | SETSSP | USESR0 | USESSP }, /* tst.b #imm,@(r0,gbr) */
1918 { 0xcd00, LOAD | STORE | USESR0 | USESSP }, /* and.b #imm,@(r0,gbr) */
1919 { 0xce00, LOAD | STORE | USESR0 | USESSP }, /* xor.b #imm,@(r0,gbr) */
1920 { 0xcf00, LOAD | STORE | USESR0 | USESSP } /* or.b #imm,@(r0,gbr) */
1921};
1922
1923static const struct sh_minor_opcode sh_opcodec[] =
1924{
1925 { MAP (sh_opcodec0), 0xff00 }
1926};
1927
1928static const struct sh_opcode sh_opcoded0[] =
1929{
1930 { 0xd000, LOAD | SETS1 } /* mov.l @(disp,pc),rn */
1931};
1932
1933static const struct sh_minor_opcode sh_opcoded[] =
1934{
1935 { MAP (sh_opcoded0), 0xf000 }
1936};
1937
1938static const struct sh_opcode sh_opcodee0[] =
1939{
1940 { 0xe000, SETS1 } /* mov #imm,rn */
1941};
1942
1943static const struct sh_minor_opcode sh_opcodee[] =
1944{
1945 { MAP (sh_opcodee0), 0xf000 }
1946};
1947
1948static const struct sh_opcode sh_opcodef0[] =
1949{
1950 { 0xf000, SETSF1 | USESF1 | USESF2 }, /* fadd fm,fn */
1951 { 0xf001, SETSF1 | USESF1 | USESF2 }, /* fsub fm,fn */
1952 { 0xf002, SETSF1 | USESF1 | USESF2 }, /* fmul fm,fn */
1953 { 0xf003, SETSF1 | USESF1 | USESF2 }, /* fdiv fm,fn */
1954 { 0xf004, SETSSP | USESF1 | USESF2 }, /* fcmp/eq fm,fn */
1955 { 0xf005, SETSSP | USESF1 | USESF2 }, /* fcmp/gt fm,fn */
1956 { 0xf006, LOAD | SETSF1 | USES2 | USESR0 }, /* fmov.s @(r0,rm),fn */
1957 { 0xf007, STORE | USES1 | USESF2 | USESR0 }, /* fmov.s fm,@(r0,rn) */
1958 { 0xf008, LOAD | SETSF1 | USES2 }, /* fmov.s @rm,fn */
1959 { 0xf009, LOAD | SETS2 | SETSF1 | USES2 }, /* fmov.s @rm+,fn */
1960 { 0xf00a, STORE | USES1 | USESF2 }, /* fmov.s fm,@rn */
1961 { 0xf00b, STORE | SETS1 | USES1 | USESF2 }, /* fmov.s fm,@-rn */
1962 { 0xf00c, SETSF1 | USESF2 }, /* fmov fm,fn */
1963 { 0xf00e, SETSF1 | USESF1 | USESF2 | USESF0 } /* fmac f0,fm,fn */
1964};
1965
1966static const struct sh_opcode sh_opcodef1[] =
1967{
1968 { 0xf00d, SETSF1 | USESSP }, /* fsts fpul,fn */
1969 { 0xf01d, SETSSP | USESF1 }, /* flds fn,fpul */
1970 { 0xf02d, SETSF1 | USESSP }, /* float fpul,fn */
1971 { 0xf03d, SETSSP | USESF1 }, /* ftrc fn,fpul */
1972 { 0xf04d, SETSF1 | USESF1 }, /* fneg fn */
1973 { 0xf05d, SETSF1 | USESF1 }, /* fabs fn */
1974 { 0xf06d, SETSF1 | USESF1 }, /* fsqrt fn */
1975 { 0xf07d, SETSSP | USESF1 }, /* ftst/nan fn */
1976 { 0xf08d, SETSF1 }, /* fldi0 fn */
1977 { 0xf09d, SETSF1 } /* fldi1 fn */
1978};
1979
1980static const struct sh_minor_opcode sh_opcodef[] =
1981{
1982 { MAP (sh_opcodef0), 0xf00f },
1983 { MAP (sh_opcodef1), 0xf0ff }
1984};
1985
d4845d57 1986static struct sh_major_opcode sh_opcodes[] =
252b5132
RH		 1987{
1988 { MAP (sh_opcode0) },
1989 { MAP (sh_opcode1) },
1990 { MAP (sh_opcode2) },
1991 { MAP (sh_opcode3) },
1992 { MAP (sh_opcode4) },
1993 { MAP (sh_opcode5) },
1994 { MAP (sh_opcode6) },
1995 { MAP (sh_opcode7) },
1996 { MAP (sh_opcode8) },
1997 { MAP (sh_opcode9) },
1998 { MAP (sh_opcodea) },
1999 { MAP (sh_opcodeb) },
2000 { MAP (sh_opcodec) },
2001 { MAP (sh_opcoded) },
2002 { MAP (sh_opcodee) },
2003 { MAP (sh_opcodef) }
2004};
2005
d4845d57
JR		 2006/* The double data transfer / parallel processing insns are not
2007 described here. This will cause sh_align_load_span to leave them alone. */
2008
2009static const struct sh_opcode sh_dsp_opcodef0[] =
2010{
2011 { 0xf400, USESAS | SETSAS | LOAD | SETSSP }, /* movs.x @-as,ds */
2012 { 0xf401, USESAS | SETSAS | STORE | USESSP }, /* movs.x ds,@-as */
2013 { 0xf404, USESAS | LOAD | SETSSP }, /* movs.x @as,ds */
2014 { 0xf405, USESAS | STORE | USESSP }, /* movs.x ds,@as */
2015 { 0xf408, USESAS | SETSAS | LOAD | SETSSP }, /* movs.x @as+,ds */
2016 { 0xf409, USESAS | SETSAS | STORE | USESSP }, /* movs.x ds,@as+ */
2017 { 0xf40c, USESAS | SETSAS | LOAD | SETSSP | USESR8 }, /* movs.x @as+r8,ds */
2018 { 0xf40d, USESAS | SETSAS | STORE | USESSP | USESR8 } /* movs.x ds,@as+r8 */
2019};
2020
2021static const struct sh_minor_opcode sh_dsp_opcodef[] =
2022{
2023 { MAP (sh_dsp_opcodef0), 0xfc0d }
2024};
2025
252b5132
RH		 2026/* Given an instruction, return a pointer to the corresponding
2027 sh_opcode structure. Return NULL if the instruction is not
2028 recognized. */
2029
2030static const struct sh_opcode *
2031sh_insn_info (insn)
2032 unsigned int insn;
2033{
2034 const struct sh_major_opcode *maj;
2035 const struct sh_minor_opcode *min, *minend;
2036
2037 maj = &sh_opcodes[(insn & 0xf000) >> 12];
2038 min = maj->minor_opcodes;
2039 minend = min + maj->count;
2040 for (; min < minend; min++)
2041 {
2042 unsigned int l;
2043 const struct sh_opcode *op, *opend;
2044
2045 l = insn & min->mask;
2046 op = min->opcodes;
2047 opend = op + min->count;
2048
2049 /* Since the opcodes tables are sorted, we could use a binary
2050 search here if the count were above some cutoff value. */
2051 for (; op < opend; op++)
2052 if (op->opcode == l)
2053 return op;
2054 }
2055
cbfe05c4 2056 return NULL;
252b5132
RH		 2057}
2058
84dcfba7
JR		 2059/* See whether an instruction uses or sets a general purpose register */
2060
b34976b6 2061static bfd_boolean
84dcfba7
JR		 2062sh_insn_uses_or_sets_reg (insn, op, reg)
2063 unsigned int insn;
2064 const struct sh_opcode *op;
2065 unsigned int reg;
2066{
2067 if (sh_insn_uses_reg (insn, op, reg))
b34976b6 2068 return TRUE;
84dcfba7
JR		 2069
2070 return sh_insn_sets_reg (insn, op, reg);
2071}
2072
252b5132
RH		 2073/* See whether an instruction uses a general purpose register. */
2074
b34976b6 2075static bfd_boolean
252b5132
RH		 2076sh_insn_uses_reg (insn, op, reg)
2077 unsigned int insn;
2078 const struct sh_opcode *op;
2079 unsigned int reg;
2080{
2081 unsigned int f;
2082
2083 f = op->flags;
2084
2085 if ((f & USES1) != 0
84dcfba7 2086 && USES1_REG (insn) == reg)
b34976b6 2087 return TRUE;
252b5132 2088 if ((f & USES2) != 0
84dcfba7 2089 && USES2_REG (insn) == reg)
b34976b6 2090 return TRUE;
252b5132
RH		 2091 if ((f & USESR0) != 0
2092 && reg == 0)
b34976b6 2093 return TRUE;
d4845d57 2094 if ((f & USESAS) && reg == USESAS_REG (insn))
b34976b6 2095 return TRUE;
d4845d57 2096 if ((f & USESR8) && reg == 8)
b34976b6 2097 return TRUE;
252b5132 2098
b34976b6 2099 return FALSE;
252b5132 2100}
17505c5c 2101
84dcfba7
JR		 2102/* See whether an instruction sets a general purpose register. */
2103
b34976b6 2104static bfd_boolean
84dcfba7
JR		 2105sh_insn_sets_reg (insn, op, reg)
2106 unsigned int insn;
2107 const struct sh_opcode *op;
2108 unsigned int reg;
2109{
2110 unsigned int f;
2111
2112 f = op->flags;
2113
2114 if ((f & SETS1) != 0
2115 && SETS1_REG (insn) == reg)
b34976b6 2116 return TRUE;
84dcfba7
JR		 2117 if ((f & SETS2) != 0
2118 && SETS2_REG (insn) == reg)
b34976b6 2119 return TRUE;
84dcfba7
JR		 2120 if ((f & SETSR0) != 0
2121 && reg == 0)
b34976b6 2122 return TRUE;
d4845d57 2123 if ((f & SETSAS) && reg == SETSAS_REG (insn))
b34976b6 2124 return TRUE;
84dcfba7 2125
b34976b6 2126 return FALSE;
84dcfba7
JR		 2127}
2128
2129/* See whether an instruction uses or sets a floating point register */
2130
b34976b6 2131static bfd_boolean
84dcfba7
JR		 2132sh_insn_uses_or_sets_freg (insn, op, reg)
2133 unsigned int insn;
2134 const struct sh_opcode *op;
2135 unsigned int reg;
2136{
2137 if (sh_insn_uses_freg (insn, op, reg))
b34976b6 2138 return TRUE;
84dcfba7
JR		 2139
2140 return sh_insn_sets_freg (insn, op, reg);
2141}
252b5132
RH		 2142
2143/* See whether an instruction uses a floating point register. */
2144
b34976b6 2145static bfd_boolean
252b5132
RH		 2146sh_insn_uses_freg (insn, op, freg)
2147 unsigned int insn;
2148 const struct sh_opcode *op;
2149 unsigned int freg;
2150{
2151 unsigned int f;
2152
2153 f = op->flags;
2154
2155 /* We can't tell if this is a double-precision insn, so just play safe
2156 and assume that it might be. So not only have we test FREG against
2157 itself, but also even FREG against FREG+1 - if the using insn uses
2158 just the low part of a double precision value - but also an odd
2159 FREG against FREG-1 - if the setting insn sets just the low part
2160 of a double precision value.
2161 So what this all boils down to is that we have to ignore the lowest
2162 bit of the register number. */
cbfe05c4 2163
252b5132 2164 if ((f & USESF1) != 0
84dcfba7 2165 && (USESF1_REG (insn) & 0xe) == (freg & 0xe))
b34976b6 2166 return TRUE;
252b5132 2167 if ((f & USESF2) != 0
84dcfba7 2168 && (USESF2_REG (insn) & 0xe) == (freg & 0xe))
b34976b6 2169 return TRUE;
252b5132
RH		 2170 if ((f & USESF0) != 0
2171 && freg == 0)
b34976b6 2172 return TRUE;
252b5132 2173
b34976b6 2174 return FALSE;
252b5132
RH		 2175}
2176
84dcfba7
JR		 2177/* See whether an instruction sets a floating point register. */
2178
b34976b6 2179static bfd_boolean
84dcfba7
JR		 2180sh_insn_sets_freg (insn, op, freg)
2181 unsigned int insn;
2182 const struct sh_opcode *op;
2183 unsigned int freg;
2184{
2185 unsigned int f;
2186
2187 f = op->flags;
2188
2189 /* We can't tell if this is a double-precision insn, so just play safe
2190 and assume that it might be. So not only have we test FREG against
2191 itself, but also even FREG against FREG+1 - if the using insn uses
2192 just the low part of a double precision value - but also an odd
2193 FREG against FREG-1 - if the setting insn sets just the low part
2194 of a double precision value.
2195 So what this all boils down to is that we have to ignore the lowest
2196 bit of the register number. */
cbfe05c4 2197
84dcfba7
JR		 2198 if ((f & SETSF1) != 0
2199 && (SETSF1_REG (insn) & 0xe) == (freg & 0xe))
b34976b6 2200 return TRUE;
84dcfba7 2201
b34976b6 2202 return FALSE;
84dcfba7
JR		 2203}
2204
252b5132
RH		 2205/* See whether instructions I1 and I2 conflict, assuming I1 comes
2206 before I2. OP1 and OP2 are the corresponding sh_opcode structures.
b34976b6 2207 This should return TRUE if there is a conflict, or FALSE if the
252b5132
RH		 2208 instructions can be swapped safely. */
2209
b34976b6 2210static bfd_boolean
252b5132
RH		 2211sh_insns_conflict (i1, op1, i2, op2)
2212 unsigned int i1;
2213 const struct sh_opcode *op1;
2214 unsigned int i2;
2215 const struct sh_opcode *op2;
2216{
2217 unsigned int f1, f2;
2218
2219 f1 = op1->flags;
2220 f2 = op2->flags;
2221
2222 /* Load of fpscr conflicts with floating point operations.
2223 FIXME: shouldn't test raw opcodes here. */
2224 if (((i1 & 0xf0ff) == 0x4066 && (i2 & 0xf000) == 0xf000)
2225 || ((i2 & 0xf0ff) == 0x4066 && (i1 & 0xf000) == 0xf000))
b34976b6 2226 return TRUE;
252b5132
RH		 2227
2228 if ((f1 & (BRANCH | DELAY)) != 0
2229 || (f2 & (BRANCH | DELAY)) != 0)
b34976b6 2230 return TRUE;
252b5132 2231
84dcfba7
JR		 2232 if (((f1 | f2) & SETSSP)
2233 && (f1 & (SETSSP | USESSP))
2234 && (f2 & (SETSSP | USESSP)))
b34976b6 2235 return TRUE;
252b5132
RH		 2236
2237 if ((f1 & SETS1) != 0
84dcfba7 2238 && sh_insn_uses_or_sets_reg (i2, op2, SETS1_REG (i1)))
b34976b6 2239 return TRUE;
252b5132 2240 if ((f1 & SETS2) != 0
84dcfba7 2241 && sh_insn_uses_or_sets_reg (i2, op2, SETS2_REG (i1)))
b34976b6 2242 return TRUE;
252b5132 2243 if ((f1 & SETSR0) != 0
84dcfba7 2244 && sh_insn_uses_or_sets_reg (i2, op2, 0))
b34976b6 2245 return TRUE;
d4845d57
JR		 2246 if ((f1 & SETSAS)
2247 && sh_insn_uses_or_sets_reg (i2, op2, SETSAS_REG (i1)))
b34976b6 2248 return TRUE;
252b5132 2249 if ((f1 & SETSF1) != 0
84dcfba7 2250 && sh_insn_uses_or_sets_freg (i2, op2, SETSF1_REG (i1)))
b34976b6 2251 return TRUE;
252b5132
RH		 2252
2253 if ((f2 & SETS1) != 0
84dcfba7 2254 && sh_insn_uses_or_sets_reg (i1, op1, SETS1_REG (i2)))
b34976b6 2255 return TRUE;
252b5132 2256 if ((f2 & SETS2) != 0
84dcfba7 2257 && sh_insn_uses_or_sets_reg (i1, op1, SETS2_REG (i2)))
b34976b6 2258 return TRUE;
252b5132 2259 if ((f2 & SETSR0) != 0
84dcfba7 2260 && sh_insn_uses_or_sets_reg (i1, op1, 0))
b34976b6 2261 return TRUE;
d4845d57
JR		 2262 if ((f2 & SETSAS)
2263 && sh_insn_uses_or_sets_reg (i1, op1, SETSAS_REG (i2)))
b34976b6 2264 return TRUE;
252b5132 2265 if ((f2 & SETSF1) != 0
84dcfba7 2266 && sh_insn_uses_or_sets_freg (i1, op1, SETSF1_REG (i2)))
b34976b6 2267 return TRUE;
252b5132
RH		 2268
2269 /* The instructions do not conflict. */
b34976b6 2270 return FALSE;
252b5132
RH		 2271}
2272
2273/* I1 is a load instruction, and I2 is some other instruction. Return
b34976b6 2274 TRUE if I1 loads a register which I2 uses. */
252b5132 2275
b34976b6 2276static bfd_boolean
252b5132
RH		 2277sh_load_use (i1, op1, i2, op2)
2278 unsigned int i1;
2279 const struct sh_opcode *op1;
2280 unsigned int i2;
2281 const struct sh_opcode *op2;
2282{
2283 unsigned int f1;
2284
2285 f1 = op1->flags;
2286
2287 if ((f1 & LOAD) == 0)
b34976b6 2288 return FALSE;
252b5132
RH		 2289
2290 /* If both SETS1 and SETSSP are set, that means a load to a special
2291 register using postincrement addressing mode, which we don't care
2292 about here. */
2293 if ((f1 & SETS1) != 0
2294 && (f1 & SETSSP) == 0
2295 && sh_insn_uses_reg (i2, op2, (i1 & 0x0f00) >> 8))
b34976b6 2296 return TRUE;
252b5132
RH		 2297
2298 if ((f1 & SETSR0) != 0
2299 && sh_insn_uses_reg (i2, op2, 0))
b34976b6 2300 return TRUE;
252b5132
RH		 2301
2302 if ((f1 & SETSF1) != 0
2303 && sh_insn_uses_freg (i2, op2, (i1 & 0x0f00) >> 8))
b34976b6 2304 return TRUE;
252b5132 2305
b34976b6 2306 return FALSE;
252b5132
RH		 2307}
2308
2309/* Try to align loads and stores within a span of memory. This is
2310 called by both the ELF and the COFF sh targets. ABFD and SEC are
2311 the BFD and section we are examining. CONTENTS is the contents of
2312 the section. SWAP is the routine to call to swap two instructions.
2313 RELOCS is a pointer to the internal relocation information, to be
2314 passed to SWAP. PLABEL is a pointer to the current label in a
2315 sorted list of labels; LABEL_END is the end of the list. START and
2316 STOP are the range of memory to examine. If a swap is made,
b34976b6 2317 *PSWAPPED is set to TRUE. */
252b5132 2318
86033394
NC		 2319#ifdef COFF_WITH_PE
2320static
2321#endif
b34976b6 2322bfd_boolean
252b5132
RH		 2323_bfd_sh_align_load_span (abfd, sec, contents, swap, relocs,
2324 plabel, label_end, start, stop, pswapped)
2325 bfd *abfd;
2326 asection *sec;
2327 bfd_byte *contents;
b34976b6 2328 bfd_boolean (*swap) PARAMS ((bfd *, asection *, PTR, bfd_byte *, bfd_vma));
252b5132
RH		 2329 PTR relocs;
2330 bfd_vma **plabel;
2331 bfd_vma *label_end;
2332 bfd_vma start;
2333 bfd_vma stop;
b34976b6 2334 bfd_boolean *pswapped;
252b5132 2335{
d4845d57
JR		 2336 int dsp = (abfd->arch_info->mach == bfd_mach_sh_dsp
2337 || abfd->arch_info->mach == bfd_mach_sh3_dsp);
252b5132
RH		 2338 bfd_vma i;
2339
d4845d57
JR		 2340 /* The SH4 has a Harvard architecture, hence aligning loads is not
2341 desirable. In fact, it is counter-productive, since it interferes
2342 with the schedules generated by the compiler. */
2343 if (abfd->arch_info->mach == bfd_mach_sh4)
b34976b6 2344 return TRUE;
d4845d57
JR		 2345
2346 /* If we are linking sh[3]-dsp code, swap the FPU instructions for DSP
2347 instructions. */
2348 if (dsp)
2349 {
2350 sh_opcodes[0xf].minor_opcodes = sh_dsp_opcodef;
2351 sh_opcodes[0xf].count = sizeof sh_dsp_opcodef / sizeof sh_dsp_opcodef;
2352 }
2353
252b5132
RH		 2354 /* Instructions should be aligned on 2 byte boundaries. */
2355 if ((start & 1) == 1)
2356 ++start;
2357
2358 /* Now look through the unaligned addresses. */
2359 i = start;
2360 if ((i & 2) == 0)
2361 i += 2;
2362 for (; i < stop; i += 4)
2363 {
2364 unsigned int insn;
2365 const struct sh_opcode *op;
2366 unsigned int prev_insn = 0;
2367 const struct sh_opcode *prev_op = NULL;
2368
2369 insn = bfd_get_16 (abfd, contents + i);
2370 op = sh_insn_info (insn);
2371 if (op == NULL
2372 || (op->flags & (LOAD | STORE)) == 0)
2373 continue;
2374
2375 /* This is a load or store which is not on a four byte boundary. */
2376
2377 while (*plabel < label_end && **plabel < i)
2378 ++*plabel;
2379
2380 if (i > start)
2381 {
2382 prev_insn = bfd_get_16 (abfd, contents + i - 2);
d4845d57
JR		 2383 /* If INSN is the field b of a parallel processing insn, it is not
2384 a load / store after all. Note that the test here might mistake
2385 the field_b of a pcopy insn for the starting code of a parallel
2386 processing insn; this might miss a swapping opportunity, but at
2387 least we're on the safe side. */
2388 if (dsp && (prev_insn & 0xfc00) == 0xf800)
2389 continue;
2390
2391 /* Check if prev_insn is actually the field b of a parallel
2392 processing insn. Again, this can give a spurious match
2393 after a pcopy. */
2394 if (dsp && i - 2 > start)
2395 {
2396 unsigned pprev_insn = bfd_get_16 (abfd, contents + i - 4);
cbfe05c4 2397
d4845d57
JR		 2398 if ((pprev_insn & 0xfc00) == 0xf800)
2399 prev_op = NULL;
2400 else
2401 prev_op = sh_insn_info (prev_insn);
2402 }
2403 else
2404 prev_op = sh_insn_info (prev_insn);
252b5132
RH		 2405
2406 /* If the load/store instruction is in a delay slot, we
2407 can't swap. */
2408 if (prev_op == NULL
2409 || (prev_op->flags & DELAY) != 0)
2410 continue;
2411 }
2412 if (i > start
2413 && (*plabel >= label_end || **plabel != i)
2414 && prev_op != NULL
2415 && (prev_op->flags & (LOAD | STORE)) == 0
2416 && ! sh_insns_conflict (prev_insn, prev_op, insn, op))
2417 {
b34976b6 2418 bfd_boolean ok;
252b5132
RH		 2419
2420 /* The load/store instruction does not have a label, and
2421 there is a previous instruction; PREV_INSN is not
2422 itself a load/store instruction, and PREV_INSN and
2423 INSN do not conflict. */
2424
b34976b6 2425 ok = TRUE;
252b5132
RH		 2426
2427 if (i >= start + 4)
2428 {
2429 unsigned int prev2_insn;
2430 const struct sh_opcode *prev2_op;
2431
2432 prev2_insn = bfd_get_16 (abfd, contents + i - 4);
2433 prev2_op = sh_insn_info (prev2_insn);
2434
2435 /* If the instruction before PREV_INSN has a delay
2436 slot--that is, PREV_INSN is in a delay slot--we
2437 can not swap. */
2438 if (prev2_op == NULL
2439 || (prev2_op->flags & DELAY) != 0)
b34976b6 2440 ok = FALSE;
252b5132
RH		 2441
2442 /* If the instruction before PREV_INSN is a load,
2443 and it sets a register which INSN uses, then
2444 putting INSN immediately after PREV_INSN will
2445 cause a pipeline bubble, so there is no point to
2446 making the swap. */
2447 if (ok
2448 && (prev2_op->flags & LOAD) != 0
2449 && sh_load_use (prev2_insn, prev2_op, insn, op))
b34976b6 2450 ok = FALSE;
252b5132
RH		 2451 }
2452
2453 if (ok)
2454 {
2455 if (! (*swap) (abfd, sec, relocs, contents, i - 2))
b34976b6
AM		 2456 return FALSE;
2457 *pswapped = TRUE;
252b5132
RH		 2458 continue;
2459 }
2460 }
2461
2462 while (*plabel < label_end && **plabel < i + 2)
2463 ++*plabel;
2464
2465 if (i + 2 < stop
2466 && (*plabel >= label_end || **plabel != i + 2))
2467 {
2468 unsigned int next_insn;
2469 const struct sh_opcode *next_op;
2470
2471 /* There is an instruction after the load/store
2472 instruction, and it does not have a label. */
2473 next_insn = bfd_get_16 (abfd, contents + i + 2);
2474 next_op = sh_insn_info (next_insn);
2475 if (next_op != NULL
2476 && (next_op->flags & (LOAD | STORE)) == 0
2477 && ! sh_insns_conflict (insn, op, next_insn, next_op))
2478 {
b34976b6 2479 bfd_boolean ok;
252b5132
RH		 2480
2481 /* NEXT_INSN is not itself a load/store instruction,
2482 and it does not conflict with INSN. */
2483
b34976b6 2484 ok = TRUE;
252b5132
RH		 2485
2486 /* If PREV_INSN is a load, and it sets a register
2487 which NEXT_INSN uses, then putting NEXT_INSN
2488 immediately after PREV_INSN will cause a pipeline
2489 bubble, so there is no reason to make this swap. */
2490 if (prev_op != NULL
2491 && (prev_op->flags & LOAD) != 0
2492 && sh_load_use (prev_insn, prev_op, next_insn, next_op))
b34976b6 2493 ok = FALSE;
252b5132
RH		 2494
2495 /* If INSN is a load, and it sets a register which
2496 the insn after NEXT_INSN uses, then doing the
2497 swap will cause a pipeline bubble, so there is no
2498 reason to make the swap. However, if the insn
2499 after NEXT_INSN is itself a load or store
2500 instruction, then it is misaligned, so
2501 optimistically hope that it will be swapped
2502 itself, and just live with the pipeline bubble if
2503 it isn't. */
2504 if (ok
2505 && i + 4 < stop
2506 && (op->flags & LOAD) != 0)
2507 {
2508 unsigned int next2_insn;
2509 const struct sh_opcode *next2_op;
2510
2511 next2_insn = bfd_get_16 (abfd, contents + i + 4);
2512 next2_op = sh_insn_info (next2_insn);
230d6d81
NC		 2513 if (next2_op == NULL
2514 || ((next2_op->flags & (LOAD | STORE)) == 0
2515 && sh_load_use (insn, op, next2_insn, next2_op)))
b34976b6 2516 ok = FALSE;
252b5132
RH		 2517 }
2518
2519 if (ok)
2520 {
2521 if (! (*swap) (abfd, sec, relocs, contents, i))
b34976b6
AM		 2522 return FALSE;
2523 *pswapped = TRUE;
252b5132
RH		 2524 continue;
2525 }
2526 }
2527 }
2528 }
2529
b34976b6 2530 return TRUE;
252b5132 2531}
86033394 2532#endif /* not COFF_IMAGE_WITH_PE */
252b5132
RH		 2533
2534/* Look for loads and stores which we can align to four byte
2535 boundaries. See the longer comment above sh_relax_section for why
2536 this is desirable. This sets *PSWAPPED if some instruction was
2537 swapped. */
2538
b34976b6 2539static bfd_boolean
252b5132
RH		 2540sh_align_loads (abfd, sec, internal_relocs, contents, pswapped)
2541 bfd *abfd;
2542 asection *sec;
2543 struct internal_reloc *internal_relocs;
2544 bfd_byte *contents;
b34976b6 2545 bfd_boolean *pswapped;
252b5132
RH		 2546{
2547 struct internal_reloc *irel, *irelend;
2548 bfd_vma *labels = NULL;
2549 bfd_vma *label, *label_end;
dc810e39 2550 bfd_size_type amt;
252b5132 2551
b34976b6 2552 *pswapped = FALSE;
252b5132
RH		 2553
2554 irelend = internal_relocs + sec->reloc_count;
2555
2556 /* Get all the addresses with labels on them. */
dc810e39
AM		 2557 amt = (bfd_size_type) sec->reloc_count * sizeof (bfd_vma);
2558 labels = (bfd_vma *) bfd_malloc (amt);
252b5132
RH		 2559 if (labels == NULL)
2560 goto error_return;
2561 label_end = labels;
2562 for (irel = internal_relocs; irel < irelend; irel++)
2563 {
2564 if (irel->r_type == R_SH_LABEL)
2565 {
2566 *label_end = irel->r_vaddr - sec->vma;
2567 ++label_end;
2568 }
2569 }
2570
2571 /* Note that the assembler currently always outputs relocs in
2572 address order. If that ever changes, this code will need to sort
2573 the label values and the relocs. */
2574
2575 label = labels;
2576
2577 for (irel = internal_relocs; irel < irelend; irel++)
2578 {
2579 bfd_vma start, stop;
2580
2581 if (irel->r_type != R_SH_CODE)
2582 continue;
2583
2584 start = irel->r_vaddr - sec->vma;
2585
2586 for (irel++; irel < irelend; irel++)
2587 if (irel->r_type == R_SH_DATA)
2588 break;
2589 if (irel < irelend)
2590 stop = irel->r_vaddr - sec->vma;
2591 else
eea6121a 2592 stop = sec->size;
252b5132
RH		 2593
2594 if (! _bfd_sh_align_load_span (abfd, sec, contents, sh_swap_insns,
2595 (PTR) internal_relocs, &label,
2596 label_end, start, stop, pswapped))
2597 goto error_return;
2598 }
2599
2600 free (labels);
2601
b34976b6 2602 return TRUE;
252b5132
RH		 2603
2604 error_return:
2605 if (labels != NULL)
2606 free (labels);
b34976b6 2607 return FALSE;
252b5132
RH		 2608}
2609
2610/* Swap two SH instructions. */
2611
b34976b6 2612static bfd_boolean
252b5132
RH		 2613sh_swap_insns (abfd, sec, relocs, contents, addr)
2614 bfd *abfd;
2615 asection *sec;
2616 PTR relocs;
2617 bfd_byte *contents;
2618 bfd_vma addr;
2619{
2620 struct internal_reloc *internal_relocs = (struct internal_reloc *) relocs;
2621 unsigned short i1, i2;
2622 struct internal_reloc *irel, *irelend;
2623
2624 /* Swap the instructions themselves. */
2625 i1 = bfd_get_16 (abfd, contents + addr);
2626 i2 = bfd_get_16 (abfd, contents + addr + 2);
dc810e39
AM		 2627 bfd_put_16 (abfd, (bfd_vma) i2, contents + addr);
2628 bfd_put_16 (abfd, (bfd_vma) i1, contents + addr + 2);
252b5132
RH		 2629
2630 /* Adjust all reloc addresses. */
2631 irelend = internal_relocs + sec->reloc_count;
2632 for (irel = internal_relocs; irel < irelend; irel++)
2633 {
2634 int type, add;
2635
2636 /* There are a few special types of relocs that we don't want to
2637 adjust. These relocs do not apply to the instruction itself,
2638 but are only associated with the address. */
2639 type = irel->r_type;
2640 if (type == R_SH_ALIGN
2641 || type == R_SH_CODE
2642 || type == R_SH_DATA
2643 || type == R_SH_LABEL)
2644 continue;
2645
2646 /* If an R_SH_USES reloc points to one of the addresses being
2647 swapped, we must adjust it. It would be incorrect to do this
2648 for a jump, though, since we want to execute both
2649 instructions after the jump. (We have avoided swapping
2650 around a label, so the jump will not wind up executing an
2651 instruction it shouldn't). */
2652 if (type == R_SH_USES)
2653 {
2654 bfd_vma off;
2655
2656 off = irel->r_vaddr - sec->vma + 4 + irel->r_offset;
2657 if (off == addr)
2658 irel->r_offset += 2;
2659 else if (off == addr + 2)
2660 irel->r_offset -= 2;
2661 }
2662
2663 if (irel->r_vaddr - sec->vma == addr)
2664 {
2665 irel->r_vaddr += 2;
2666 add = -2;
2667 }
2668 else if (irel->r_vaddr - sec->vma == addr + 2)
2669 {
2670 irel->r_vaddr -= 2;
2671 add = 2;
2672 }
2673 else
2674 add = 0;
2675
2676 if (add != 0)
2677 {
2678 bfd_byte *loc;
2679 unsigned short insn, oinsn;
b34976b6 2680 bfd_boolean overflow;
252b5132
RH		 2681
2682 loc = contents + irel->r_vaddr - sec->vma;
b34976b6 2683 overflow = FALSE;
252b5132
RH		 2684 switch (type)
2685 {
2686 default:
2687 break;
2688
2689 case R_SH_PCDISP8BY2:
2690 case R_SH_PCRELIMM8BY2:
2691 insn = bfd_get_16 (abfd, loc);
2692 oinsn = insn;
2693 insn += add / 2;
2694 if ((oinsn & 0xff00) != (insn & 0xff00))
b34976b6 2695 overflow = TRUE;
dc810e39 2696 bfd_put_16 (abfd, (bfd_vma) insn, loc);
252b5132
RH		 2697 break;
2698
2699 case R_SH_PCDISP:
2700 insn = bfd_get_16 (abfd, loc);
2701 oinsn = insn;
2702 insn += add / 2;
2703 if ((oinsn & 0xf000) != (insn & 0xf000))
b34976b6 2704 overflow = TRUE;
dc810e39 2705 bfd_put_16 (abfd, (bfd_vma) insn, loc);
252b5132
RH		 2706 break;
2707
2708 case R_SH_PCRELIMM8BY4:
2709 /* This reloc ignores the least significant 3 bits of
2710 the program counter before adding in the offset.
2711 This means that if ADDR is at an even address, the
2712 swap will not affect the offset. If ADDR is an at an
2713 odd address, then the instruction will be crossing a
2714 four byte boundary, and must be adjusted. */
2715 if ((addr & 3) != 0)
2716 {
2717 insn = bfd_get_16 (abfd, loc);
2718 oinsn = insn;
2719 insn += add / 2;
2720 if ((oinsn & 0xff00) != (insn & 0xff00))
b34976b6 2721 overflow = TRUE;
dc810e39 2722 bfd_put_16 (abfd, (bfd_vma) insn, loc);
252b5132
RH		 2723 }
2724
2725 break;
2726 }
2727
2728 if (overflow)
2729 {
2730 ((*_bfd_error_handler)
d003868e
AM		 2731 ("%B: 0x%lx: fatal: reloc overflow while relaxing",
2732 abfd, (unsigned long) irel->r_vaddr));
252b5132 2733 bfd_set_error (bfd_error_bad_value);
b34976b6 2734 return FALSE;
252b5132
RH		 2735 }
2736 }
2737 }
2738
b34976b6 2739 return TRUE;
252b5132
RH		 2740}
2741\f
2742/* This is a modification of _bfd_coff_generic_relocate_section, which
2743 will handle SH relaxing. */
2744
b34976b6 2745static bfd_boolean
252b5132
RH		 2746sh_relocate_section (output_bfd, info, input_bfd, input_section, contents,
2747 relocs, syms, sections)
5f771d47 2748 bfd *output_bfd ATTRIBUTE_UNUSED;
252b5132
RH		 2749 struct bfd_link_info *info;
2750 bfd *input_bfd;
2751 asection *input_section;
2752 bfd_byte *contents;
2753 struct internal_reloc *relocs;
2754 struct internal_syment *syms;
2755 asection **sections;
2756{
2757 struct internal_reloc *rel;
2758 struct internal_reloc *relend;
2759
2760 rel = relocs;
2761 relend = rel + input_section->reloc_count;
2762 for (; rel < relend; rel++)
2763 {
2764 long symndx;
2765 struct coff_link_hash_entry *h;
2766 struct internal_syment *sym;
2767 bfd_vma addend;
2768 bfd_vma val;
2769 reloc_howto_type *howto;
2770 bfd_reloc_status_type rstat;
2771
2772 /* Almost all relocs have to do with relaxing. If any work must
2773 be done for them, it has been done in sh_relax_section. */
2774 if (rel->r_type != R_SH_IMM32
17505c5c
NC		 2775#ifdef COFF_WITH_PE
2776 && rel->r_type != R_SH_IMM32CE
2777 && rel->r_type != R_SH_IMAGEBASE
2778#endif
252b5132
RH		 2779 && rel->r_type != R_SH_PCDISP)
2780 continue;
2781
2782 symndx = rel->r_symndx;
2783
2784 if (symndx == -1)
2785 {
2786 h = NULL;
2787 sym = NULL;
2788 }
2789 else
cbfe05c4 2790 {
252b5132
RH		 2791 if (symndx < 0
2792 || (unsigned long) symndx >= obj_raw_syment_count (input_bfd))
2793 {
2794 (*_bfd_error_handler)
d003868e
AM		 2795 ("%B: illegal symbol index %ld in relocs",
2796 input_bfd, symndx);
252b5132 2797 bfd_set_error (bfd_error_bad_value);
b34976b6 2798 return FALSE;
252b5132
RH		 2799 }
2800 h = obj_coff_sym_hashes (input_bfd)[symndx];
2801 sym = syms + symndx;
2802 }
2803
2804 if (sym != NULL && sym->n_scnum != 0)
2805 addend = - sym->n_value;
2806 else
2807 addend = 0;
2808
2809 if (rel->r_type == R_SH_PCDISP)
2810 addend -= 4;
2811
2812 if (rel->r_type >= SH_COFF_HOWTO_COUNT)
2813 howto = NULL;
2814 else
2815 howto = &sh_coff_howtos[rel->r_type];
2816
2817 if (howto == NULL)
2818 {
2819 bfd_set_error (bfd_error_bad_value);
b34976b6 2820 return FALSE;
252b5132
RH		 2821 }
2822
17505c5c
NC		 2823#ifdef COFF_WITH_PE
2824 if (rel->r_type == R_SH_IMAGEBASE)
2825 addend -= pe_data (input_section->output_section->owner)->pe_opthdr.ImageBase;
2826#endif
cbfe05c4 2827
252b5132
RH		 2828 val = 0;
2829
2830 if (h == NULL)
2831 {
2832 asection *sec;
2833
2834 /* There is nothing to do for an internal PCDISP reloc. */
2835 if (rel->r_type == R_SH_PCDISP)
2836 continue;
2837
2838 if (symndx == -1)
2839 {
2840 sec = bfd_abs_section_ptr;
2841 val = 0;
2842 }
2843 else
2844 {
2845 sec = sections[symndx];
2846 val = (sec->output_section->vma
2847 + sec->output_offset
2848 + sym->n_value
2849 - sec->vma);
2850 }
2851 }
2852 else
2853 {
2854 if (h->root.type == bfd_link_hash_defined
2855 || h->root.type == bfd_link_hash_defweak)
2856 {
2857 asection *sec;
2858
2859 sec = h->root.u.def.section;
2860 val = (h->root.u.def.value
2861 + sec->output_section->vma
2862 + sec->output_offset);
2863 }
1049f94e 2864 else if (! info->relocatable)
252b5132
RH		 2865 {
2866 if (! ((*info->callbacks->undefined_symbol)
2867 (info, h->root.root.string, input_bfd, input_section,
b34976b6
AM		 2868 rel->r_vaddr - input_section->vma, TRUE)))
2869 return FALSE;
252b5132
RH		 2870 }
2871 }
2872
2873 rstat = _bfd_final_link_relocate (howto, input_bfd, input_section,
2874 contents,
2875 rel->r_vaddr - input_section->vma,
2876 val, addend);
2877
2878 switch (rstat)
2879 {
2880 default:
2881 abort ();
2882 case bfd_reloc_ok:
2883 break;
2884 case bfd_reloc_overflow:
2885 {
2886 const char *name;
2887 char buf[SYMNMLEN + 1];
2888
2889 if (symndx == -1)
2890 name = "*ABS*";
2891 else if (h != NULL)
dfeffb9f 2892 name = NULL;
252b5132
RH		 2893 else if (sym->_n._n_n._n_zeroes == 0
2894 && sym->_n._n_n._n_offset != 0)
2895 name = obj_coff_strings (input_bfd) + sym->_n._n_n._n_offset;
2896 else
2897 {
2898 strncpy (buf, sym->_n._n_name, SYMNMLEN);
2899 buf[SYMNMLEN] = '\0';
2900 name = buf;
2901 }
2902
2903 if (! ((*info->callbacks->reloc_overflow)
dfeffb9f
L		 2904 (info, (h ? &h->root : NULL), name, howto->name,
2905 (bfd_vma) 0, input_bfd, input_section,
2906 rel->r_vaddr - input_section->vma)))
b34976b6 2907 return FALSE;
252b5132
RH		 2908 }
2909 }
2910 }
2911
b34976b6 2912 return TRUE;
252b5132
RH		 2913}
2914
2915/* This is a version of bfd_generic_get_relocated_section_contents
2916 which uses sh_relocate_section. */
2917
2918static bfd_byte *
2919sh_coff_get_relocated_section_contents (output_bfd, link_info, link_order,
1049f94e 2920 data, relocatable, symbols)
252b5132
RH		 2921 bfd *output_bfd;
2922 struct bfd_link_info *link_info;
2923 struct bfd_link_order *link_order;
2924 bfd_byte *data;
1049f94e 2925 bfd_boolean relocatable;
252b5132
RH		 2926 asymbol **symbols;
2927{
2928 asection *input_section = link_order->u.indirect.section;
2929 bfd *input_bfd = input_section->owner;
2930 asection **sections = NULL;
2931 struct internal_reloc *internal_relocs = NULL;
2932 struct internal_syment *internal_syms = NULL;
2933
2934 /* We only need to handle the case of relaxing, or of having a
2935 particular set of section contents, specially. */
1049f94e 2936 if (relocatable
252b5132
RH		 2937 || coff_section_data (input_bfd, input_section) == NULL
2938 || coff_section_data (input_bfd, input_section)->contents == NULL)
2939 return bfd_generic_get_relocated_section_contents (output_bfd, link_info,
2940 link_order, data,
1049f94e 2941 relocatable,
252b5132
RH		 2942 symbols);
2943
2944 memcpy (data, coff_section_data (input_bfd, input_section)->contents,
eea6121a 2945 (size_t) input_section->size);
252b5132
RH		 2946
2947 if ((input_section->flags & SEC_RELOC) != 0
2948 && input_section->reloc_count > 0)
2949 {
2950 bfd_size_type symesz = bfd_coff_symesz (input_bfd);
2951 bfd_byte *esym, *esymend;
2952 struct internal_syment *isymp;
2953 asection **secpp;
dc810e39 2954 bfd_size_type amt;
252b5132
RH		 2955
2956 if (! _bfd_coff_get_external_symbols (input_bfd))
2957 goto error_return;
2958
2959 internal_relocs = (_bfd_coff_read_internal_relocs
b34976b6
AM		 2960 (input_bfd, input_section, FALSE, (bfd_byte *) NULL,
2961 FALSE, (struct internal_reloc *) NULL));
252b5132
RH		 2962 if (internal_relocs == NULL)
2963 goto error_return;
2964
dc810e39
AM		 2965 amt = obj_raw_syment_count (input_bfd);
2966 amt *= sizeof (struct internal_syment);
2967 internal_syms = (struct internal_syment *) bfd_malloc (amt);
252b5132
RH		 2968 if (internal_syms == NULL)
2969 goto error_return;
2970
dc810e39
AM		 2971 amt = obj_raw_syment_count (input_bfd);
2972 amt *= sizeof (asection *);
2973 sections = (asection **) bfd_malloc (amt);
252b5132
RH		 2974 if (sections == NULL)
2975 goto error_return;
2976
2977 isymp = internal_syms;
2978 secpp = sections;
2979 esym = (bfd_byte *) obj_coff_external_syms (input_bfd);
2980 esymend = esym + obj_raw_syment_count (input_bfd) * symesz;
2981 while (esym < esymend)
2982 {
2983 bfd_coff_swap_sym_in (input_bfd, (PTR) esym, (PTR) isymp);
2984
2985 if (isymp->n_scnum != 0)
2986 *secpp = coff_section_from_bfd_index (input_bfd, isymp->n_scnum);
2987 else
2988 {
2989 if (isymp->n_value == 0)
2990 *secpp = bfd_und_section_ptr;
2991 else
2992 *secpp = bfd_com_section_ptr;
2993 }
2994
2995 esym += (isymp->n_numaux + 1) * symesz;
2996 secpp += isymp->n_numaux + 1;
2997 isymp += isymp->n_numaux + 1;
2998 }
2999
3000 if (! sh_relocate_section (output_bfd, link_info, input_bfd,
3001 input_section, data, internal_relocs,
3002 internal_syms, sections))
3003 goto error_return;
3004
3005 free (sections);
3006 sections = NULL;
3007 free (internal_syms);
3008 internal_syms = NULL;
3009 free (internal_relocs);
3010 internal_relocs = NULL;
3011 }
3012
3013 return data;
3014
3015 error_return:
3016 if (internal_relocs != NULL)
3017 free (internal_relocs);
3018 if (internal_syms != NULL)
3019 free (internal_syms);
3020 if (sections != NULL)
3021 free (sections);
3022 return NULL;
3023}
3024
3025/* The target vectors. */
3026
17505c5c 3027#ifndef TARGET_SHL_SYM
3fa78519 3028CREATE_BIG_COFF_TARGET_VEC (shcoff_vec, "coff-sh", BFD_IS_RELAXABLE, 0, '_', NULL, COFF_SWAP_TABLE)
17505c5c 3029#endif
252b5132 3030
c3c89269
NC		 3031#ifdef TARGET_SHL_SYM
3032#define TARGET_SYM TARGET_SHL_SYM
3033#else
3034#define TARGET_SYM shlcoff_vec
3035#endif
cbfe05c4 3036
c3c89269
NC		 3037#ifndef TARGET_SHL_NAME
3038#define TARGET_SHL_NAME "coff-shl"
3039#endif
252b5132 3040
17505c5c
NC		 3041#ifdef COFF_WITH_PE
3042CREATE_LITTLE_COFF_TARGET_VEC (TARGET_SYM, TARGET_SHL_NAME, BFD_IS_RELAXABLE,
3fa78519 3043 SEC_CODE | SEC_DATA, '_', NULL, COFF_SWAP_TABLE);
17505c5c 3044#else
86033394 3045CREATE_LITTLE_COFF_TARGET_VEC (TARGET_SYM, TARGET_SHL_NAME, BFD_IS_RELAXABLE,
3fa78519 3046 0, '_', NULL, COFF_SWAP_TABLE)
17505c5c 3047#endif
86033394 3048
17505c5c 3049#ifndef TARGET_SHL_SYM
f4ffd778 3050static const bfd_target * coff_small_object_p PARAMS ((bfd *));
b34976b6 3051static bfd_boolean coff_small_new_section_hook PARAMS ((bfd *, asection *));
252b5132
RH		 3052/* Some people want versions of the SH COFF target which do not align
3053 to 16 byte boundaries. We implement that by adding a couple of new
3054 target vectors. These are just like the ones above, but they
3055 change the default section alignment. To generate them in the
3056 assembler, use -small. To use them in the linker, use -b
3057 coff-sh{l}-small and -oformat coff-sh{l}-small.
3058
3059 Yes, this is a horrible hack. A general solution for setting
3060 section alignment in COFF is rather complex. ELF handles this
3061 correctly. */
3062
3063/* Only recognize the small versions if the target was not defaulted.
3064 Otherwise we won't recognize the non default endianness. */
3065
3066static const bfd_target *
3067coff_small_object_p (abfd)
3068 bfd *abfd;
3069{
3070 if (abfd->target_defaulted)
3071 {
3072 bfd_set_error (bfd_error_wrong_format);
3073 return NULL;
3074 }
3075 return coff_object_p (abfd);
3076}
3077
3078/* Set the section alignment for the small versions. */
3079
b34976b6 3080static bfd_boolean
252b5132
RH		 3081coff_small_new_section_hook (abfd, section)
3082 bfd *abfd;
3083 asection *section;
3084{
3085 if (! coff_new_section_hook (abfd, section))
b34976b6 3086 return FALSE;
252b5132
RH		 3087
3088 /* We must align to at least a four byte boundary, because longword
3089 accesses must be on a four byte boundary. */
3090 if (section->alignment_power == COFF_DEFAULT_SECTION_ALIGNMENT_POWER)
3091 section->alignment_power = 2;
3092
b34976b6 3093 return TRUE;
252b5132
RH		 3094}
3095
3096/* This is copied from bfd_coff_std_swap_table so that we can change
3097 the default section alignment power. */
3098
3099static const bfd_coff_backend_data bfd_coff_small_swap_table =
3100{
3101 coff_swap_aux_in, coff_swap_sym_in, coff_swap_lineno_in,
3102 coff_swap_aux_out, coff_swap_sym_out,
3103 coff_swap_lineno_out, coff_swap_reloc_out,
3104 coff_swap_filehdr_out, coff_swap_aouthdr_out,
3105 coff_swap_scnhdr_out,
692b7d62 3106 FILHSZ, AOUTSZ, SCNHSZ, SYMESZ, AUXESZ, RELSZ, LINESZ, FILNMLEN,
252b5132 3107#ifdef COFF_LONG_FILENAMES
b34976b6 3108 TRUE,
252b5132 3109#else
b34976b6 3110 FALSE,
252b5132
RH		 3111#endif
3112#ifdef COFF_LONG_SECTION_NAMES
b34976b6 3113 TRUE,
252b5132 3114#else
b34976b6 3115 FALSE,
252b5132
RH		 3116#endif
3117 2,
ecefdb58 3118#ifdef COFF_FORCE_SYMBOLS_IN_STRINGS
b34976b6 3119 TRUE,
ecefdb58 3120#else
b34976b6 3121 FALSE,
ecefdb58
CP		 3122#endif
3123#ifdef COFF_DEBUG_STRING_WIDE_PREFIX
3124 4,
3125#else
3126 2,
3127#endif
252b5132
RH		 3128 coff_swap_filehdr_in, coff_swap_aouthdr_in, coff_swap_scnhdr_in,
3129 coff_swap_reloc_in, coff_bad_format_hook, coff_set_arch_mach_hook,
3130 coff_mkobject_hook, styp_to_sec_flags, coff_set_alignment_hook,
3131 coff_slurp_symbol_table, symname_in_debug_hook, coff_pointerize_aux_hook,
3132 coff_print_aux, coff_reloc16_extra_cases, coff_reloc16_estimate,
5d54c628 3133 coff_classify_symbol, coff_compute_section_file_positions,
252b5132
RH		 3134 coff_start_final_link, coff_relocate_section, coff_rtype_to_howto,
3135 coff_adjust_symndx, coff_link_add_one_symbol,
3136 coff_link_output_has_begun, coff_final_link_postscript
3137};
3138
3139#define coff_small_close_and_cleanup \
3140 coff_close_and_cleanup
3141#define coff_small_bfd_free_cached_info \
3142 coff_bfd_free_cached_info
3143#define coff_small_get_section_contents \
3144 coff_get_section_contents
3145#define coff_small_get_section_contents_in_window \
3146 coff_get_section_contents_in_window
3147
c3c89269
NC		 3148extern const bfd_target shlcoff_small_vec;
3149
252b5132
RH		 3150const bfd_target shcoff_small_vec =
3151{
3152 "coff-sh-small", /* name */
3153 bfd_target_coff_flavour,
3154 BFD_ENDIAN_BIG, /* data byte order is big */
3155 BFD_ENDIAN_BIG, /* header byte order is big */
3156
3157 (HAS_RELOC | EXEC_P | /* object flags */
3158 HAS_LINENO | HAS_DEBUG |
3159 HAS_SYMS | HAS_LOCALS | WP_TEXT | BFD_IS_RELAXABLE),
3160
3161 (SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_RELOC),
3162 '_', /* leading symbol underscore */
3163 '/', /* ar_pad_char */
3164 15, /* ar_max_namelen */
3165 bfd_getb64, bfd_getb_signed_64, bfd_putb64,
3166 bfd_getb32, bfd_getb_signed_32, bfd_putb32,
3167 bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* data */
3168 bfd_getb64, bfd_getb_signed_64, bfd_putb64,
3169 bfd_getb32, bfd_getb_signed_32, bfd_putb32,
3170 bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* hdrs */
3171
3172 {_bfd_dummy_target, coff_small_object_p, /* bfd_check_format */
3173 bfd_generic_archive_p, _bfd_dummy_target},
3174 {bfd_false, coff_mkobject, _bfd_generic_mkarchive, /* bfd_set_format */
3175 bfd_false},
3176 {bfd_false, coff_write_object_contents, /* bfd_write_contents */
3177 _bfd_write_archive_contents, bfd_false},
3178
3179 BFD_JUMP_TABLE_GENERIC (coff_small),
3180 BFD_JUMP_TABLE_COPY (coff),
3181 BFD_JUMP_TABLE_CORE (_bfd_nocore),
3182 BFD_JUMP_TABLE_ARCHIVE (_bfd_archive_coff),
3183 BFD_JUMP_TABLE_SYMBOLS (coff),
3184 BFD_JUMP_TABLE_RELOCS (coff),
3185 BFD_JUMP_TABLE_WRITE (coff),
3186 BFD_JUMP_TABLE_LINK (coff),
3187 BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic),
3188
c3c89269 3189 & shlcoff_small_vec,
cbfe05c4 3190
252b5132
RH		 3191 (PTR) &bfd_coff_small_swap_table
3192};
3193
3194const bfd_target shlcoff_small_vec =
3195{
3196 "coff-shl-small", /* name */
3197 bfd_target_coff_flavour,
3198 BFD_ENDIAN_LITTLE, /* data byte order is little */
3199 BFD_ENDIAN_LITTLE, /* header byte order is little endian too*/
3200
3201 (HAS_RELOC | EXEC_P | /* object flags */
3202 HAS_LINENO | HAS_DEBUG |
3203 HAS_SYMS | HAS_LOCALS | WP_TEXT | BFD_IS_RELAXABLE),
3204
3205 (SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_RELOC),
3206 '_', /* leading symbol underscore */
3207 '/', /* ar_pad_char */
3208 15, /* ar_max_namelen */
3209 bfd_getl64, bfd_getl_signed_64, bfd_putl64,
3210 bfd_getl32, bfd_getl_signed_32, bfd_putl32,
3211 bfd_getl16, bfd_getl_signed_16, bfd_putl16, /* data */
3212 bfd_getl64, bfd_getl_signed_64, bfd_putl64,
3213 bfd_getl32, bfd_getl_signed_32, bfd_putl32,
3214 bfd_getl16, bfd_getl_signed_16, bfd_putl16, /* hdrs */
3215
3216 {_bfd_dummy_target, coff_small_object_p, /* bfd_check_format */
cbfe05c4 3217 bfd_generic_archive_p, _bfd_dummy_target},
252b5132
RH		 3218 {bfd_false, coff_mkobject, _bfd_generic_mkarchive, /* bfd_set_format */
3219 bfd_false},
3220 {bfd_false, coff_write_object_contents, /* bfd_write_contents */
3221 _bfd_write_archive_contents, bfd_false},
3222
3223 BFD_JUMP_TABLE_GENERIC (coff_small),
3224 BFD_JUMP_TABLE_COPY (coff),
3225 BFD_JUMP_TABLE_CORE (_bfd_nocore),
3226 BFD_JUMP_TABLE_ARCHIVE (_bfd_archive_coff),
3227 BFD_JUMP_TABLE_SYMBOLS (coff),
3228 BFD_JUMP_TABLE_RELOCS (coff),
3229 BFD_JUMP_TABLE_WRITE (coff),
3230 BFD_JUMP_TABLE_LINK (coff),
3231 BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic),
3232
c3c89269 3233 & shcoff_small_vec,
cbfe05c4 3234
252b5132
RH		 3235 (PTR) &bfd_coff_small_swap_table
3236};
17505c5c 3237#endif
GDB Binutils - Deliverables
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