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[deliverable/binutils-gdb.git] / bfd / coff-sh.c
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c2dcd04e 1/* BFD back-end for Renesas Super-H COFF binaries.
2571583a 2 Copyright (C) 1993-2017 Free Software Foundation, Inc.
252b5132
RH		 3 Contributed by Cygnus Support.
4 Written by Steve Chamberlain, <sac@cygnus.com>.
5 Relaxing code written by Ian Lance Taylor, <ian@cygnus.com>.
6
c2dcd04e 7 This file is part of BFD, the Binary File Descriptor library.
252b5132 8
c2dcd04e
NC		 9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
cd123cb7 11 the Free Software Foundation; either version 3 of the License, or
c2dcd04e 12 (at your option) any later version.
252b5132 13
c2dcd04e
NC		 14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
252b5132 18
c2dcd04e
NC		 19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
cd123cb7
NC		 21 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
22 MA 02110-1301, USA. */
252b5132 23
252b5132 24#include "sysdep.h"
3db64b00 25#include "bfd.h"
993e9275 26#include "libiberty.h"
252b5132
RH		 27#include "libbfd.h"
28#include "bfdlink.h"
29#include "coff/sh.h"
30#include "coff/internal.h"
17505c5c 31
799c00e0
NC		 32#undef bfd_pe_print_pdata
33
17505c5c
NC		 34#ifdef COFF_WITH_PE
35#include "coff/pe.h"
86033394
NC		 36
37#ifndef COFF_IMAGE_WITH_PE
b34976b6 38static bfd_boolean sh_align_load_span
2c3fc389
NC		 39 (bfd *, asection *, bfd_byte *,
40 bfd_boolean (*) (bfd *, asection *, void *, bfd_byte *, bfd_vma),
41 void *, bfd_vma **, bfd_vma *, bfd_vma, bfd_vma, bfd_boolean *);
86033394
NC		 42
43#define _bfd_sh_align_load_span sh_align_load_span
44#endif
17505c5c 45
799c00e0
NC		 46#define bfd_pe_print_pdata _bfd_pe_print_ce_compressed_pdata
47
48#else
49
50#define bfd_pe_print_pdata NULL
51
52#endif /* COFF_WITH_PE. */
2b5c217d 53
252b5132
RH		 54#include "libcoff.h"
55
56/* Internal functions. */
252b5132 57
17505c5c
NC		 58#ifdef COFF_WITH_PE
59/* Can't build import tables with 2**4 alignment. */
60#define COFF_DEFAULT_SECTION_ALIGNMENT_POWER 2
61#else
252b5132 62/* Default section alignment to 2**4. */
17505c5c
NC		 63#define COFF_DEFAULT_SECTION_ALIGNMENT_POWER 4
64#endif
65
66#ifdef COFF_IMAGE_WITH_PE
67/* Align PE executables. */
68#define COFF_PAGE_SIZE 0x1000
69#endif
252b5132
RH		 70
71/* Generate long file names. */
72#define COFF_LONG_FILENAMES
73
17505c5c 74#ifdef COFF_WITH_PE
b34976b6 75/* Return TRUE if this relocation should
17505c5c 76 appear in the output .reloc section. */
2c3fc389
NC		 77
78static bfd_boolean
79in_reloc_p (bfd * abfd ATTRIBUTE_UNUSED,
80 reloc_howto_type * howto)
17505c5c
NC		 81{
82 return ! howto->pc_relative && howto->type != R_SH_IMAGEBASE;
cbfe05c4 83}
17505c5c
NC		 84#endif
85
2c3fc389
NC		 86static bfd_reloc_status_type
87sh_reloc (bfd *, arelent *, asymbol *, void *, asection *, bfd *, char **);
88static bfd_boolean
89sh_relocate_section (bfd *, struct bfd_link_info *, bfd *, asection *,
90 bfd_byte *, struct internal_reloc *,
91 struct internal_syment *, asection **);
92static bfd_boolean
93sh_align_loads (bfd *, asection *, struct internal_reloc *,
94 bfd_byte *, bfd_boolean *);
95
252b5132
RH		 96/* The supported relocations. There are a lot of relocations defined
97 in coff/internal.h which we do not expect to ever see. */
98static reloc_howto_type sh_coff_howtos[] =
99{
5f771d47
ILT		 100 EMPTY_HOWTO (0),
101 EMPTY_HOWTO (1),
17505c5c
NC		 102#ifdef COFF_WITH_PE
103 /* Windows CE */
104 HOWTO (R_SH_IMM32CE, /* type */
105 0, /* rightshift */
106 2, /* size (0 = byte, 1 = short, 2 = long) */
107 32, /* bitsize */
b34976b6 108 FALSE, /* pc_relative */
17505c5c
NC		 109 0, /* bitpos */
110 complain_overflow_bitfield, /* complain_on_overflow */
111 sh_reloc, /* special_function */
112 "r_imm32ce", /* name */
b34976b6 113 TRUE, /* partial_inplace */
17505c5c
NC		 114 0xffffffff, /* src_mask */
115 0xffffffff, /* dst_mask */
b34976b6 116 FALSE), /* pcrel_offset */
17505c5c 117#else
5f771d47 118 EMPTY_HOWTO (2),
17505c5c 119#endif
5f771d47
ILT		 120 EMPTY_HOWTO (3), /* R_SH_PCREL8 */
121 EMPTY_HOWTO (4), /* R_SH_PCREL16 */
122 EMPTY_HOWTO (5), /* R_SH_HIGH8 */
123 EMPTY_HOWTO (6), /* R_SH_IMM24 */
124 EMPTY_HOWTO (7), /* R_SH_LOW16 */
125 EMPTY_HOWTO (8),
126 EMPTY_HOWTO (9), /* R_SH_PCDISP8BY4 */
252b5132
RH		 127
128 HOWTO (R_SH_PCDISP8BY2, /* type */
129 1, /* rightshift */
130 1, /* size (0 = byte, 1 = short, 2 = long) */
131 8, /* bitsize */
b34976b6 132 TRUE, /* pc_relative */
252b5132
RH		 133 0, /* bitpos */
134 complain_overflow_signed, /* complain_on_overflow */
135 sh_reloc, /* special_function */
136 "r_pcdisp8by2", /* name */
b34976b6 137 TRUE, /* partial_inplace */
252b5132
RH		 138 0xff, /* src_mask */
139 0xff, /* dst_mask */
b34976b6 140 TRUE), /* pcrel_offset */
252b5132 141
5f771d47 142 EMPTY_HOWTO (11), /* R_SH_PCDISP8 */
252b5132
RH		 143
144 HOWTO (R_SH_PCDISP, /* type */
145 1, /* rightshift */
146 1, /* size (0 = byte, 1 = short, 2 = long) */
147 12, /* bitsize */
b34976b6 148 TRUE, /* pc_relative */
252b5132
RH		 149 0, /* bitpos */
150 complain_overflow_signed, /* complain_on_overflow */
151 sh_reloc, /* special_function */
152 "r_pcdisp12by2", /* name */
b34976b6 153 TRUE, /* partial_inplace */
252b5132
RH		 154 0xfff, /* src_mask */
155 0xfff, /* dst_mask */
b34976b6 156 TRUE), /* pcrel_offset */
252b5132 157
5f771d47 158 EMPTY_HOWTO (13),
252b5132
RH		 159
160 HOWTO (R_SH_IMM32, /* type */
161 0, /* rightshift */
162 2, /* size (0 = byte, 1 = short, 2 = long) */
163 32, /* bitsize */
b34976b6 164 FALSE, /* pc_relative */
252b5132
RH		 165 0, /* bitpos */
166 complain_overflow_bitfield, /* complain_on_overflow */
167 sh_reloc, /* special_function */
168 "r_imm32", /* name */
b34976b6 169 TRUE, /* partial_inplace */
252b5132
RH		 170 0xffffffff, /* src_mask */
171 0xffffffff, /* dst_mask */
b34976b6 172 FALSE), /* pcrel_offset */
252b5132 173
5f771d47 174 EMPTY_HOWTO (15),
17505c5c 175#ifdef COFF_WITH_PE
cbfe05c4
KH		 176 HOWTO (R_SH_IMAGEBASE, /* type */
177 0, /* rightshift */
178 2, /* size (0 = byte, 1 = short, 2 = long) */
179 32, /* bitsize */
b34976b6 180 FALSE, /* pc_relative */
cbfe05c4 181 0, /* bitpos */
17505c5c 182 complain_overflow_bitfield, /* complain_on_overflow */
cbfe05c4
KH		 183 sh_reloc, /* special_function */
184 "rva32", /* name */
b34976b6 185 TRUE, /* partial_inplace */
cbfe05c4
KH		 186 0xffffffff, /* src_mask */
187 0xffffffff, /* dst_mask */
b34976b6 188 FALSE), /* pcrel_offset */
17505c5c 189#else
5f771d47 190 EMPTY_HOWTO (16), /* R_SH_IMM8 */
17505c5c 191#endif
5f771d47
ILT		 192 EMPTY_HOWTO (17), /* R_SH_IMM8BY2 */
193 EMPTY_HOWTO (18), /* R_SH_IMM8BY4 */
194 EMPTY_HOWTO (19), /* R_SH_IMM4 */
195 EMPTY_HOWTO (20), /* R_SH_IMM4BY2 */
196 EMPTY_HOWTO (21), /* R_SH_IMM4BY4 */
252b5132
RH		 197
198 HOWTO (R_SH_PCRELIMM8BY2, /* type */
199 1, /* rightshift */
200 1, /* size (0 = byte, 1 = short, 2 = long) */
201 8, /* bitsize */
b34976b6 202 TRUE, /* pc_relative */
252b5132
RH		 203 0, /* bitpos */
204 complain_overflow_unsigned, /* complain_on_overflow */
205 sh_reloc, /* special_function */
206 "r_pcrelimm8by2", /* name */
b34976b6 207 TRUE, /* partial_inplace */
252b5132
RH		 208 0xff, /* src_mask */
209 0xff, /* dst_mask */
b34976b6 210 TRUE), /* pcrel_offset */
252b5132
RH		 211
212 HOWTO (R_SH_PCRELIMM8BY4, /* type */
213 2, /* rightshift */
214 1, /* size (0 = byte, 1 = short, 2 = long) */
215 8, /* bitsize */
b34976b6 216 TRUE, /* pc_relative */
252b5132
RH		 217 0, /* bitpos */
218 complain_overflow_unsigned, /* complain_on_overflow */
219 sh_reloc, /* special_function */
220 "r_pcrelimm8by4", /* name */
b34976b6 221 TRUE, /* partial_inplace */
252b5132
RH		 222 0xff, /* src_mask */
223 0xff, /* dst_mask */
b34976b6 224 TRUE), /* pcrel_offset */
252b5132
RH		 225
226 HOWTO (R_SH_IMM16, /* type */
227 0, /* rightshift */
228 1, /* size (0 = byte, 1 = short, 2 = long) */
229 16, /* bitsize */
b34976b6 230 FALSE, /* pc_relative */
252b5132
RH		 231 0, /* bitpos */
232 complain_overflow_bitfield, /* complain_on_overflow */
233 sh_reloc, /* special_function */
234 "r_imm16", /* name */
b34976b6 235 TRUE, /* partial_inplace */
252b5132
RH		 236 0xffff, /* src_mask */
237 0xffff, /* dst_mask */
b34976b6 238 FALSE), /* pcrel_offset */
252b5132
RH		 239
240 HOWTO (R_SH_SWITCH16, /* type */
241 0, /* rightshift */
242 1, /* size (0 = byte, 1 = short, 2 = long) */
243 16, /* bitsize */
b34976b6 244 FALSE, /* pc_relative */
252b5132
RH		 245 0, /* bitpos */
246 complain_overflow_bitfield, /* complain_on_overflow */
247 sh_reloc, /* special_function */
248 "r_switch16", /* name */
b34976b6 249 TRUE, /* partial_inplace */
252b5132
RH		 250 0xffff, /* src_mask */
251 0xffff, /* dst_mask */
b34976b6 252 FALSE), /* pcrel_offset */
252b5132
RH		 253
254 HOWTO (R_SH_SWITCH32, /* type */
255 0, /* rightshift */
256 2, /* size (0 = byte, 1 = short, 2 = long) */
257 32, /* bitsize */
b34976b6 258 FALSE, /* pc_relative */
252b5132
RH		 259 0, /* bitpos */
260 complain_overflow_bitfield, /* complain_on_overflow */
261 sh_reloc, /* special_function */
262 "r_switch32", /* name */
b34976b6 263 TRUE, /* partial_inplace */
252b5132
RH		 264 0xffffffff, /* src_mask */
265 0xffffffff, /* dst_mask */
b34976b6 266 FALSE), /* pcrel_offset */
252b5132
RH		 267
268 HOWTO (R_SH_USES, /* type */
269 0, /* rightshift */
270 1, /* size (0 = byte, 1 = short, 2 = long) */
271 16, /* bitsize */
b34976b6 272 FALSE, /* pc_relative */
252b5132
RH		 273 0, /* bitpos */
274 complain_overflow_bitfield, /* complain_on_overflow */
275 sh_reloc, /* special_function */
276 "r_uses", /* name */
b34976b6 277 TRUE, /* partial_inplace */
252b5132
RH		 278 0xffff, /* src_mask */
279 0xffff, /* dst_mask */
b34976b6 280 FALSE), /* pcrel_offset */
252b5132
RH		 281
282 HOWTO (R_SH_COUNT, /* type */
283 0, /* rightshift */
284 2, /* size (0 = byte, 1 = short, 2 = long) */
285 32, /* bitsize */
b34976b6 286 FALSE, /* pc_relative */
252b5132
RH		 287 0, /* bitpos */
288 complain_overflow_bitfield, /* complain_on_overflow */
289 sh_reloc, /* special_function */
290 "r_count", /* name */
b34976b6 291 TRUE, /* partial_inplace */
252b5132
RH		 292 0xffffffff, /* src_mask */
293 0xffffffff, /* dst_mask */
b34976b6 294 FALSE), /* pcrel_offset */
252b5132
RH		 295
296 HOWTO (R_SH_ALIGN, /* type */
297 0, /* rightshift */
298 2, /* size (0 = byte, 1 = short, 2 = long) */
299 32, /* bitsize */
b34976b6 300 FALSE, /* pc_relative */
252b5132
RH		 301 0, /* bitpos */
302 complain_overflow_bitfield, /* complain_on_overflow */
303 sh_reloc, /* special_function */
304 "r_align", /* name */
b34976b6 305 TRUE, /* partial_inplace */
252b5132
RH		 306 0xffffffff, /* src_mask */
307 0xffffffff, /* dst_mask */
b34976b6 308 FALSE), /* pcrel_offset */
252b5132
RH		 309
310 HOWTO (R_SH_CODE, /* type */
311 0, /* rightshift */
312 2, /* size (0 = byte, 1 = short, 2 = long) */
313 32, /* bitsize */
b34976b6 314 FALSE, /* pc_relative */
252b5132
RH		 315 0, /* bitpos */
316 complain_overflow_bitfield, /* complain_on_overflow */
317 sh_reloc, /* special_function */
318 "r_code", /* name */
b34976b6 319 TRUE, /* partial_inplace */
252b5132
RH		 320 0xffffffff, /* src_mask */
321 0xffffffff, /* dst_mask */
b34976b6 322 FALSE), /* pcrel_offset */
252b5132
RH		 323
324 HOWTO (R_SH_DATA, /* type */
325 0, /* rightshift */
326 2, /* size (0 = byte, 1 = short, 2 = long) */
327 32, /* bitsize */
b34976b6 328 FALSE, /* pc_relative */
252b5132
RH		 329 0, /* bitpos */
330 complain_overflow_bitfield, /* complain_on_overflow */
331 sh_reloc, /* special_function */
332 "r_data", /* name */
b34976b6 333 TRUE, /* partial_inplace */
252b5132
RH		 334 0xffffffff, /* src_mask */
335 0xffffffff, /* dst_mask */
b34976b6 336 FALSE), /* pcrel_offset */
252b5132
RH		 337
338 HOWTO (R_SH_LABEL, /* type */
339 0, /* rightshift */
340 2, /* size (0 = byte, 1 = short, 2 = long) */
341 32, /* bitsize */
b34976b6 342 FALSE, /* pc_relative */
252b5132
RH		 343 0, /* bitpos */
344 complain_overflow_bitfield, /* complain_on_overflow */
345 sh_reloc, /* special_function */
346 "r_label", /* name */
b34976b6 347 TRUE, /* partial_inplace */
252b5132
RH		 348 0xffffffff, /* src_mask */
349 0xffffffff, /* dst_mask */
b34976b6 350 FALSE), /* pcrel_offset */
252b5132
RH		 351
352 HOWTO (R_SH_SWITCH8, /* type */
353 0, /* rightshift */
354 0, /* size (0 = byte, 1 = short, 2 = long) */
355 8, /* bitsize */
b34976b6 356 FALSE, /* pc_relative */
252b5132
RH		 357 0, /* bitpos */
358 complain_overflow_bitfield, /* complain_on_overflow */
359 sh_reloc, /* special_function */
360 "r_switch8", /* name */
b34976b6 361 TRUE, /* partial_inplace */
252b5132
RH		 362 0xff, /* src_mask */
363 0xff, /* dst_mask */
b34976b6 364 FALSE) /* pcrel_offset */
252b5132
RH		 365};
366
367#define SH_COFF_HOWTO_COUNT (sizeof sh_coff_howtos / sizeof sh_coff_howtos[0])
368
369/* Check for a bad magic number. */
370#define BADMAG(x) SHBADMAG(x)
371
372/* Customize coffcode.h (this is not currently used). */
373#define SH 1
374
375/* FIXME: This should not be set here. */
376#define __A_MAGIC_SET__
377
17505c5c 378#ifndef COFF_WITH_PE
252b5132 379/* Swap the r_offset field in and out. */
dc810e39
AM		 380#define SWAP_IN_RELOC_OFFSET H_GET_32
381#define SWAP_OUT_RELOC_OFFSET H_PUT_32
252b5132
RH		 382
383/* Swap out extra information in the reloc structure. */
384#define SWAP_OUT_RELOC_EXTRA(abfd, src, dst) \
385 do \
386 { \
387 dst->r_stuff[0] = 'S'; \
388 dst->r_stuff[1] = 'C'; \
389 } \
390 while (0)
17505c5c 391#endif
252b5132
RH		 392
393/* Get the value of a symbol, when performing a relocation. */
394
395static long
2c3fc389 396get_symbol_value (asymbol *symbol)
cbfe05c4 397{
252b5132
RH		 398 bfd_vma relocation;
399
400 if (bfd_is_com_section (symbol->section))
cbfe05c4
KH		 401 relocation = 0;
402 else
252b5132
RH		 403 relocation = (symbol->value +
404 symbol->section->output_section->vma +
405 symbol->section->output_offset);
406
407 return relocation;
408}
409
17505c5c
NC		 410#ifdef COFF_WITH_PE
411/* Convert an rtype to howto for the COFF backend linker.
412 Copied from coff-i386. */
413#define coff_rtype_to_howto coff_sh_rtype_to_howto
2c3fc389 414
17505c5c
NC		 415
416static reloc_howto_type *
2c3fc389
NC		 417coff_sh_rtype_to_howto (bfd * abfd ATTRIBUTE_UNUSED,
418 asection * sec,
419 struct internal_reloc * rel,
420 struct coff_link_hash_entry * h,
421 struct internal_syment * sym,
422 bfd_vma * addendp)
17505c5c
NC		 423{
424 reloc_howto_type * howto;
425
426 howto = sh_coff_howtos + rel->r_type;
427
428 *addendp = 0;
429
430 if (howto->pc_relative)
431 *addendp += sec->vma;
432
433 if (sym != NULL && sym->n_scnum == 0 && sym->n_value != 0)
434 {
435 /* This is a common symbol. The section contents include the
436 size (sym->n_value) as an addend. The relocate_section
437 function will be adding in the final value of the symbol. We
438 need to subtract out the current size in order to get the
439 correct result. */
440 BFD_ASSERT (h != NULL);
441 }
442
443 if (howto->pc_relative)
444 {
445 *addendp -= 4;
446
447 /* If the symbol is defined, then the generic code is going to
448 add back the symbol value in order to cancel out an
449 adjustment it made to the addend. However, we set the addend
450 to 0 at the start of this function. We need to adjust here,
451 to avoid the adjustment the generic code will make. FIXME:
452 This is getting a bit hackish. */
453 if (sym != NULL && sym->n_scnum != 0)
454 *addendp -= sym->n_value;
455 }
456
457 if (rel->r_type == R_SH_IMAGEBASE)
458 *addendp -= pe_data (sec->output_section->owner)->pe_opthdr.ImageBase;
459
460 return howto;
461}
462
993e9275
NC		 463#endif /* COFF_WITH_PE */
464
17505c5c
NC		 465/* This structure is used to map BFD reloc codes to SH PE relocs. */
466struct shcoff_reloc_map
467{
aa066ac8 468 bfd_reloc_code_real_type bfd_reloc_val;
17505c5c
NC		 469 unsigned char shcoff_reloc_val;
470};
471
a9a32010 472#ifdef COFF_WITH_PE
17505c5c
NC		 473/* An array mapping BFD reloc codes to SH PE relocs. */
474static const struct shcoff_reloc_map sh_reloc_map[] =
475{
476 { BFD_RELOC_32, R_SH_IMM32CE },
477 { BFD_RELOC_RVA, R_SH_IMAGEBASE },
478 { BFD_RELOC_CTOR, R_SH_IMM32CE },
479};
a9a32010
DJ		 480#else
481/* An array mapping BFD reloc codes to SH PE relocs. */
482static const struct shcoff_reloc_map sh_reloc_map[] =
483{
484 { BFD_RELOC_32, R_SH_IMM32 },
485 { BFD_RELOC_CTOR, R_SH_IMM32 },
486};
487#endif
17505c5c
NC		 488
489/* Given a BFD reloc code, return the howto structure for the
490 corresponding SH PE reloc. */
491#define coff_bfd_reloc_type_lookup sh_coff_reloc_type_lookup
157090f7 492#define coff_bfd_reloc_name_lookup sh_coff_reloc_name_lookup
17505c5c
NC		 493
494static reloc_howto_type *
2c3fc389
NC		 495sh_coff_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
496 bfd_reloc_code_real_type code)
17505c5c
NC		 497{
498 unsigned int i;
499
993e9275
NC		 500 for (i = ARRAY_SIZE (sh_reloc_map); i--;)
501 if (sh_reloc_map[i].bfd_reloc_val == code)
502 return &sh_coff_howtos[(int) sh_reloc_map[i].shcoff_reloc_val];
17505c5c 503
4eca0228 504 _bfd_error_handler (_("SH Error: unknown reloc type %d"), code);
17505c5c
NC		 505 return NULL;
506}
17505c5c 507
157090f7
AM		 508static reloc_howto_type *
509sh_coff_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
510 const char *r_name)
511{
512 unsigned int i;
513
514 for (i = 0; i < sizeof (sh_coff_howtos) / sizeof (sh_coff_howtos[0]); i++)
515 if (sh_coff_howtos[i].name != NULL
516 && strcasecmp (sh_coff_howtos[i].name, r_name) == 0)
517 return &sh_coff_howtos[i];
518
519 return NULL;
520}
521
252b5132
RH		 522/* This macro is used in coffcode.h to get the howto corresponding to
523 an internal reloc. */
524
525#define RTYPE2HOWTO(relent, internal) \
526 ((relent)->howto = \
527 ((internal)->r_type < SH_COFF_HOWTO_COUNT \
528 ? &sh_coff_howtos[(internal)->r_type] \
529 : (reloc_howto_type *) NULL))
530
531/* This is the same as the macro in coffcode.h, except that it copies
532 r_offset into reloc_entry->addend for some relocs. */
f4943d82
AM		 533#define CALC_ADDEND(abfd, ptr, reloc, cache_ptr) \
534 { \
535 coff_symbol_type *coffsym = (coff_symbol_type *) NULL; \
536 if (ptr && bfd_asymbol_bfd (ptr) != abfd) \
537 coffsym = (obj_symbols (abfd) \
538 + (cache_ptr->sym_ptr_ptr - symbols)); \
539 else if (ptr) \
540 coffsym = coff_symbol_from (ptr); \
541 if (coffsym != (coff_symbol_type *) NULL \
542 && coffsym->native->u.syment.n_scnum == 0) \
543 cache_ptr->addend = 0; \
544 else if (ptr && bfd_asymbol_bfd (ptr) == abfd \
545 && ptr->section != (asection *) NULL) \
546 cache_ptr->addend = - (ptr->section->vma + ptr->value); \
547 else \
548 cache_ptr->addend = 0; \
252b5132
RH		 549 if ((reloc).r_type == R_SH_SWITCH8 \
550 || (reloc).r_type == R_SH_SWITCH16 \
551 || (reloc).r_type == R_SH_SWITCH32 \
552 || (reloc).r_type == R_SH_USES \
553 || (reloc).r_type == R_SH_COUNT \
554 || (reloc).r_type == R_SH_ALIGN) \
555 cache_ptr->addend = (reloc).r_offset; \
556 }
557
558/* This is the howto function for the SH relocations. */
559
560static bfd_reloc_status_type
2c3fc389
NC		 561sh_reloc (bfd * abfd,
562 arelent * reloc_entry,
563 asymbol * symbol_in,
564 void * data,
565 asection * input_section,
566 bfd * output_bfd,
567 char ** error_message ATTRIBUTE_UNUSED)
252b5132
RH		 568{
569 unsigned long insn;
570 bfd_vma sym_value;
571 unsigned short r_type;
572 bfd_vma addr = reloc_entry->address;
573 bfd_byte *hit_data = addr + (bfd_byte *) data;
574
575 r_type = reloc_entry->howto->type;
576
577 if (output_bfd != NULL)
578 {
579 /* Partial linking--do nothing. */
580 reloc_entry->address += input_section->output_offset;
581 return bfd_reloc_ok;
582 }
583
584 /* Almost all relocs have to do with relaxing. If any work must be
585 done for them, it has been done in sh_relax_section. */
586 if (r_type != R_SH_IMM32
17505c5c
NC		 587#ifdef COFF_WITH_PE
588 && r_type != R_SH_IMM32CE
589 && r_type != R_SH_IMAGEBASE
590#endif
252b5132
RH		 591 && (r_type != R_SH_PCDISP
592 || (symbol_in->flags & BSF_LOCAL) != 0))
593 return bfd_reloc_ok;
594
595 if (symbol_in != NULL
596 && bfd_is_und_section (symbol_in->section))
597 return bfd_reloc_undefined;
598
599 sym_value = get_symbol_value (symbol_in);
600
601 switch (r_type)
602 {
603 case R_SH_IMM32:
17505c5c
NC		 604#ifdef COFF_WITH_PE
605 case R_SH_IMM32CE:
606#endif
252b5132
RH		 607 insn = bfd_get_32 (abfd, hit_data);
608 insn += sym_value + reloc_entry->addend;
dc810e39 609 bfd_put_32 (abfd, (bfd_vma) insn, hit_data);
252b5132 610 break;
17505c5c
NC		 611#ifdef COFF_WITH_PE
612 case R_SH_IMAGEBASE:
613 insn = bfd_get_32 (abfd, hit_data);
dc810e39
AM		 614 insn += sym_value + reloc_entry->addend;
615 insn -= pe_data (input_section->output_section->owner)->pe_opthdr.ImageBase;
616 bfd_put_32 (abfd, (bfd_vma) insn, hit_data);
17505c5c
NC		 617 break;
618#endif
252b5132
RH		 619 case R_SH_PCDISP:
620 insn = bfd_get_16 (abfd, hit_data);
621 sym_value += reloc_entry->addend;
622 sym_value -= (input_section->output_section->vma
623 + input_section->output_offset
624 + addr
625 + 4);
626 sym_value += (insn & 0xfff) << 1;
627 if (insn & 0x800)
628 sym_value -= 0x1000;
629 insn = (insn & 0xf000) | (sym_value & 0xfff);
dc810e39 630 bfd_put_16 (abfd, (bfd_vma) insn, hit_data);
252b5132
RH		 631 if (sym_value < (bfd_vma) -0x1000 || sym_value >= 0x1000)
632 return bfd_reloc_overflow;
633 break;
634 default:
635 abort ();
636 break;
637 }
638
639 return bfd_reloc_ok;
640}
641
875f7f69 642#define coff_bfd_merge_private_bfd_data _bfd_generic_verify_endian_match
252b5132
RH		 643
644/* We can do relaxing. */
645#define coff_bfd_relax_section sh_relax_section
646
647/* We use the special COFF backend linker. */
648#define coff_relocate_section sh_relocate_section
649
650/* When relaxing, we need to use special code to get the relocated
651 section contents. */
652#define coff_bfd_get_relocated_section_contents \
653 sh_coff_get_relocated_section_contents
654
655#include "coffcode.h"
656\f
2c3fc389
NC		 657static bfd_boolean
658sh_relax_delete_bytes (bfd *, asection *, bfd_vma, int);
659
252b5132
RH		 660/* This function handles relaxing on the SH.
661
662 Function calls on the SH look like this:
663
664 movl L1,r0
665 ...
666 jsr @r0
667 ...
668 L1:
669 .long function
670
671 The compiler and assembler will cooperate to create R_SH_USES
672 relocs on the jsr instructions. The r_offset field of the
673 R_SH_USES reloc is the PC relative offset to the instruction which
674 loads the register (the r_offset field is computed as though it
675 were a jump instruction, so the offset value is actually from four
676 bytes past the instruction). The linker can use this reloc to
677 determine just which function is being called, and thus decide
678 whether it is possible to replace the jsr with a bsr.
679
680 If multiple function calls are all based on a single register load
681 (i.e., the same function is called multiple times), the compiler
682 guarantees that each function call will have an R_SH_USES reloc.
683 Therefore, if the linker is able to convert each R_SH_USES reloc
684 which refers to that address, it can safely eliminate the register
685 load.
686
687 When the assembler creates an R_SH_USES reloc, it examines it to
688 determine which address is being loaded (L1 in the above example).
689 It then counts the number of references to that address, and
690 creates an R_SH_COUNT reloc at that address. The r_offset field of
691 the R_SH_COUNT reloc will be the number of references. If the
692 linker is able to eliminate a register load, it can use the
693 R_SH_COUNT reloc to see whether it can also eliminate the function
694 address.
695
696 SH relaxing also handles another, unrelated, matter. On the SH, if
697 a load or store instruction is not aligned on a four byte boundary,
698 the memory cycle interferes with the 32 bit instruction fetch,
699 causing a one cycle bubble in the pipeline. Therefore, we try to
700 align load and store instructions on four byte boundaries if we
701 can, by swapping them with one of the adjacent instructions. */
702
b34976b6 703static bfd_boolean
2c3fc389
NC		 704sh_relax_section (bfd *abfd,
705 asection *sec,
706 struct bfd_link_info *link_info,
707 bfd_boolean *again)
252b5132
RH		 708{
709 struct internal_reloc *internal_relocs;
b34976b6 710 bfd_boolean have_code;
252b5132
RH		 711 struct internal_reloc *irel, *irelend;
712 bfd_byte *contents = NULL;
252b5132 713
b34976b6 714 *again = FALSE;
252b5132 715
0e1862bb 716 if (bfd_link_relocatable (link_info)
252b5132
RH		 717 || (sec->flags & SEC_RELOC) == 0
718 || sec->reloc_count == 0)
b34976b6 719 return TRUE;
252b5132 720
eea6121a
AM		 721 if (coff_section_data (abfd, sec) == NULL)
722 {
723 bfd_size_type amt = sizeof (struct coff_section_tdata);
2c3fc389 724 sec->used_by_bfd = bfd_zalloc (abfd, amt);
eea6121a
AM		 725 if (sec->used_by_bfd == NULL)
726 return FALSE;
727 }
252b5132
RH		 728
729 internal_relocs = (_bfd_coff_read_internal_relocs
730 (abfd, sec, link_info->keep_memory,
b34976b6 731 (bfd_byte *) NULL, FALSE,
252b5132
RH		 732 (struct internal_reloc *) NULL));
733 if (internal_relocs == NULL)
734 goto error_return;
252b5132 735
b34976b6 736 have_code = FALSE;
252b5132
RH		 737
738 irelend = internal_relocs + sec->reloc_count;
739 for (irel = internal_relocs; irel < irelend; irel++)
740 {
741 bfd_vma laddr, paddr, symval;
742 unsigned short insn;
743 struct internal_reloc *irelfn, *irelscan, *irelcount;
744 struct internal_syment sym;
745 bfd_signed_vma foff;
746
747 if (irel->r_type == R_SH_CODE)
b34976b6 748 have_code = TRUE;
252b5132
RH		 749
750 if (irel->r_type != R_SH_USES)
751 continue;
752
753 /* Get the section contents. */
754 if (contents == NULL)
755 {
eea6121a 756 if (coff_section_data (abfd, sec)->contents != NULL)
252b5132
RH		 757 contents = coff_section_data (abfd, sec)->contents;
758 else
759 {
eea6121a 760 if (!bfd_malloc_and_get_section (abfd, sec, &contents))
252b5132
RH		 761 goto error_return;
762 }
763 }
764
765 /* The r_offset field of the R_SH_USES reloc will point us to
766 the register load. The 4 is because the r_offset field is
767 computed as though it were a jump offset, which are based
768 from 4 bytes after the jump instruction. */
769 laddr = irel->r_vaddr - sec->vma + 4;
770 /* Careful to sign extend the 32-bit offset. */
771 laddr += ((irel->r_offset & 0xffffffff) ^ 0x80000000) - 0x80000000;
eea6121a 772 if (laddr >= sec->size)
252b5132 773 {
695344c0
NC		 774 /* xgettext: c-format */
775 _bfd_error_handler (_("%B: 0x%lx: warning: bad R_SH_USES offset"),
4eca0228 776 abfd, (unsigned long) irel->r_vaddr);
252b5132
RH		 777 continue;
778 }
779 insn = bfd_get_16 (abfd, contents + laddr);
780
781 /* If the instruction is not mov.l NN,rN, we don't know what to do. */
782 if ((insn & 0xf000) != 0xd000)
783 {
4eca0228 784 _bfd_error_handler
695344c0
NC		 785 /* xgettext: c-format */
786 (_("%B: 0x%lx: warning: R_SH_USES points to unrecognized insn 0x%x"),
4eca0228 787 abfd, (unsigned long) irel->r_vaddr, insn);
252b5132
RH		 788 continue;
789 }
790
791 /* Get the address from which the register is being loaded. The
792 displacement in the mov.l instruction is quadrupled. It is a
793 displacement from four bytes after the movl instruction, but,
794 before adding in the PC address, two least significant bits
795 of the PC are cleared. We assume that the section is aligned
796 on a four byte boundary. */
797 paddr = insn & 0xff;
798 paddr *= 4;
dc810e39 799 paddr += (laddr + 4) &~ (bfd_vma) 3;
eea6121a 800 if (paddr >= sec->size)
252b5132 801 {
4eca0228 802 _bfd_error_handler
695344c0
NC		 803 /* xgettext: c-format */
804 (_("%B: 0x%lx: warning: bad R_SH_USES load offset"),
4eca0228 805 abfd, (unsigned long) irel->r_vaddr);
252b5132
RH		 806 continue;
807 }
808
809 /* Get the reloc for the address from which the register is
810 being loaded. This reloc will tell us which function is
811 actually being called. */
812 paddr += sec->vma;
813 for (irelfn = internal_relocs; irelfn < irelend; irelfn++)
814 if (irelfn->r_vaddr == paddr
17505c5c
NC		 815#ifdef COFF_WITH_PE
816 && (irelfn->r_type == R_SH_IMM32
817 || irelfn->r_type == R_SH_IMM32CE
eea6121a 818 || irelfn->r_type == R_SH_IMAGEBASE)
17505c5c
NC		 819
820#else
eea6121a 821 && irelfn->r_type == R_SH_IMM32
17505c5c 822#endif
eea6121a 823 )
252b5132
RH		 824 break;
825 if (irelfn >= irelend)
826 {
4eca0228 827 _bfd_error_handler
695344c0
NC		 828 /* xgettext: c-format */
829 (_("%B: 0x%lx: warning: could not find expected reloc"),
4eca0228 830 abfd, (unsigned long) paddr);
252b5132
RH		 831 continue;
832 }
833
834 /* Get the value of the symbol referred to by the reloc. */
835 if (! _bfd_coff_get_external_symbols (abfd))
836 goto error_return;
837 bfd_coff_swap_sym_in (abfd,
838 ((bfd_byte *) obj_coff_external_syms (abfd)
839 + (irelfn->r_symndx
840 * bfd_coff_symesz (abfd))),
841 &sym);
842 if (sym.n_scnum != 0 && sym.n_scnum != sec->target_index)
843 {
4eca0228 844 _bfd_error_handler
695344c0
NC		 845 /* xgettext: c-format */
846 (_("%B: 0x%lx: warning: symbol in unexpected section"),
4eca0228 847 abfd, (unsigned long) paddr);
252b5132
RH		 848 continue;
849 }
850
851 if (sym.n_sclass != C_EXT)
852 {
853 symval = (sym.n_value
854 - sec->vma
855 + sec->output_section->vma
856 + sec->output_offset);
857 }
858 else
859 {
860 struct coff_link_hash_entry *h;
861
862 h = obj_coff_sym_hashes (abfd)[irelfn->r_symndx];
863 BFD_ASSERT (h != NULL);
864 if (h->root.type != bfd_link_hash_defined
865 && h->root.type != bfd_link_hash_defweak)
866 {
867 /* This appears to be a reference to an undefined
868 symbol. Just ignore it--it will be caught by the
869 regular reloc processing. */
870 continue;
871 }
872
873 symval = (h->root.u.def.value
874 + h->root.u.def.section->output_section->vma
875 + h->root.u.def.section->output_offset);
876 }
877
878 symval += bfd_get_32 (abfd, contents + paddr - sec->vma);
879
880 /* See if this function call can be shortened. */
881 foff = (symval
882 - (irel->r_vaddr
883 - sec->vma
884 + sec->output_section->vma
885 + sec->output_offset
886 + 4));
887 if (foff < -0x1000 || foff >= 0x1000)
888 {
889 /* After all that work, we can't shorten this function call. */
890 continue;
891 }
892
893 /* Shorten the function call. */
894
895 /* For simplicity of coding, we are going to modify the section
896 contents, the section relocs, and the BFD symbol table. We
897 must tell the rest of the code not to free up this
898 information. It would be possible to instead create a table
899 of changes which have to be made, as is done in coff-mips.c;
900 that would be more work, but would require less memory when
901 the linker is run. */
902
252b5132 903 coff_section_data (abfd, sec)->relocs = internal_relocs;
b34976b6 904 coff_section_data (abfd, sec)->keep_relocs = TRUE;
252b5132
RH		 905
906 coff_section_data (abfd, sec)->contents = contents;
b34976b6 907 coff_section_data (abfd, sec)->keep_contents = TRUE;
252b5132 908
b34976b6 909 obj_coff_keep_syms (abfd) = TRUE;
252b5132
RH		 910
911 /* Replace the jsr with a bsr. */
912
913 /* Change the R_SH_USES reloc into an R_SH_PCDISP reloc, and
914 replace the jsr with a bsr. */
915 irel->r_type = R_SH_PCDISP;
916 irel->r_symndx = irelfn->r_symndx;
917 if (sym.n_sclass != C_EXT)
918 {
919 /* If this needs to be changed because of future relaxing,
920 it will be handled here like other internal PCDISP
921 relocs. */
922 bfd_put_16 (abfd,
dc810e39 923 (bfd_vma) 0xb000 | ((foff >> 1) & 0xfff),
252b5132
RH		 924 contents + irel->r_vaddr - sec->vma);
925 }
926 else
927 {
928 /* We can't fully resolve this yet, because the external
929 symbol value may be changed by future relaxing. We let
930 the final link phase handle it. */
dc810e39
AM		 931 bfd_put_16 (abfd, (bfd_vma) 0xb000,
932 contents + irel->r_vaddr - sec->vma);
252b5132
RH		 933 }
934
935 /* See if there is another R_SH_USES reloc referring to the same
936 register load. */
937 for (irelscan = internal_relocs; irelscan < irelend; irelscan++)
938 if (irelscan->r_type == R_SH_USES
939 && laddr == irelscan->r_vaddr - sec->vma + 4 + irelscan->r_offset)
940 break;
941 if (irelscan < irelend)
942 {
943 /* Some other function call depends upon this register load,
944 and we have not yet converted that function call.
945 Indeed, we may never be able to convert it. There is
946 nothing else we can do at this point. */
947 continue;
948 }
949
950 /* Look for a R_SH_COUNT reloc on the location where the
951 function address is stored. Do this before deleting any
952 bytes, to avoid confusion about the address. */
953 for (irelcount = internal_relocs; irelcount < irelend; irelcount++)
954 if (irelcount->r_vaddr == paddr
955 && irelcount->r_type == R_SH_COUNT)
956 break;
957
958 /* Delete the register load. */
959 if (! sh_relax_delete_bytes (abfd, sec, laddr, 2))
960 goto error_return;
961
962 /* That will change things, so, just in case it permits some
963 other function call to come within range, we should relax
964 again. Note that this is not required, and it may be slow. */
b34976b6 965 *again = TRUE;
252b5132
RH		 966
967 /* Now check whether we got a COUNT reloc. */
968 if (irelcount >= irelend)
969 {
4eca0228 970 _bfd_error_handler
695344c0
NC		 971 /* xgettext: c-format */
972 (_("%B: 0x%lx: warning: could not find expected COUNT reloc"),
4eca0228 973 abfd, (unsigned long) paddr);
252b5132
RH		 974 continue;
975 }
976
977 /* The number of uses is stored in the r_offset field. We've
978 just deleted one. */
979 if (irelcount->r_offset == 0)
980 {
695344c0
NC		 981 /* xgettext: c-format */
982 _bfd_error_handler (_("%B: 0x%lx: warning: bad count"),
4eca0228 983 abfd, (unsigned long) paddr);
252b5132
RH		 984 continue;
985 }
986
987 --irelcount->r_offset;
988
989 /* If there are no more uses, we can delete the address. Reload
990 the address from irelfn, in case it was changed by the
991 previous call to sh_relax_delete_bytes. */
992 if (irelcount->r_offset == 0)
993 {
994 if (! sh_relax_delete_bytes (abfd, sec,
995 irelfn->r_vaddr - sec->vma, 4))
996 goto error_return;
997 }
998
999 /* We've done all we can with that function call. */
1000 }
1001
1002 /* Look for load and store instructions that we can align on four
1003 byte boundaries. */
1004 if (have_code)
1005 {
b34976b6 1006 bfd_boolean swapped;
252b5132
RH		 1007
1008 /* Get the section contents. */
1009 if (contents == NULL)
1010 {
eea6121a 1011 if (coff_section_data (abfd, sec)->contents != NULL)
252b5132
RH		 1012 contents = coff_section_data (abfd, sec)->contents;
1013 else
1014 {
eea6121a 1015 if (!bfd_malloc_and_get_section (abfd, sec, &contents))
252b5132
RH		 1016 goto error_return;
1017 }
1018 }
1019
1020 if (! sh_align_loads (abfd, sec, internal_relocs, contents, &swapped))
1021 goto error_return;
1022
1023 if (swapped)
1024 {
252b5132 1025 coff_section_data (abfd, sec)->relocs = internal_relocs;
b34976b6 1026 coff_section_data (abfd, sec)->keep_relocs = TRUE;
252b5132
RH		 1027
1028 coff_section_data (abfd, sec)->contents = contents;
b34976b6 1029 coff_section_data (abfd, sec)->keep_contents = TRUE;
252b5132 1030
b34976b6 1031 obj_coff_keep_syms (abfd) = TRUE;
252b5132
RH		 1032 }
1033 }
1034
eea6121a
AM		 1035 if (internal_relocs != NULL
1036 && internal_relocs != coff_section_data (abfd, sec)->relocs)
252b5132 1037 {
eea6121a
AM		 1038 if (! link_info->keep_memory)
1039 free (internal_relocs);
1040 else
1041 coff_section_data (abfd, sec)->relocs = internal_relocs;
252b5132
RH		 1042 }
1043
eea6121a 1044 if (contents != NULL && contents != coff_section_data (abfd, sec)->contents)
252b5132
RH		 1045 {
1046 if (! link_info->keep_memory)
eea6121a 1047 free (contents);
252b5132 1048 else
eea6121a
AM		 1049 /* Cache the section contents for coff_link_input_bfd. */
1050 coff_section_data (abfd, sec)->contents = contents;
252b5132
RH		 1051 }
1052
b34976b6 1053 return TRUE;
252b5132
RH		 1054
1055 error_return:
eea6121a
AM		 1056 if (internal_relocs != NULL
1057 && internal_relocs != coff_section_data (abfd, sec)->relocs)
1058 free (internal_relocs);
1059 if (contents != NULL && contents != coff_section_data (abfd, sec)->contents)
1060 free (contents);
b34976b6 1061 return FALSE;
252b5132
RH		 1062}
1063
1064/* Delete some bytes from a section while relaxing. */
1065
b34976b6 1066static bfd_boolean
2c3fc389
NC		 1067sh_relax_delete_bytes (bfd *abfd,
1068 asection *sec,
1069 bfd_vma addr,
1070 int count)
252b5132
RH		 1071{
1072 bfd_byte *contents;
1073 struct internal_reloc *irel, *irelend;
1074 struct internal_reloc *irelalign;
1075 bfd_vma toaddr;
1076 bfd_byte *esym, *esymend;
1077 bfd_size_type symesz;
1078 struct coff_link_hash_entry **sym_hash;
1079 asection *o;
1080
1081 contents = coff_section_data (abfd, sec)->contents;
1082
1083 /* The deletion must stop at the next ALIGN reloc for an aligment
1084 power larger than the number of bytes we are deleting. */
1085
1086 irelalign = NULL;
eea6121a 1087 toaddr = sec->size;
252b5132
RH		 1088
1089 irel = coff_section_data (abfd, sec)->relocs;
1090 irelend = irel + sec->reloc_count;
1091 for (; irel < irelend; irel++)
1092 {
1093 if (irel->r_type == R_SH_ALIGN
1094 && irel->r_vaddr - sec->vma > addr
1095 && count < (1 << irel->r_offset))
1096 {
1097 irelalign = irel;
1098 toaddr = irel->r_vaddr - sec->vma;
1099 break;
1100 }
1101 }
1102
1103 /* Actually delete the bytes. */
dc810e39
AM		 1104 memmove (contents + addr, contents + addr + count,
1105 (size_t) (toaddr - addr - count));
252b5132 1106 if (irelalign == NULL)
eea6121a 1107 sec->size -= count;
252b5132
RH		 1108 else
1109 {
1110 int i;
1111
1112#define NOP_OPCODE (0x0009)
1113
1114 BFD_ASSERT ((count & 1) == 0);
1115 for (i = 0; i < count; i += 2)
dc810e39 1116 bfd_put_16 (abfd, (bfd_vma) NOP_OPCODE, contents + toaddr - count + i);
252b5132
RH		 1117 }
1118
1119 /* Adjust all the relocs. */
1120 for (irel = coff_section_data (abfd, sec)->relocs; irel < irelend; irel++)
1121 {
1122 bfd_vma nraddr, stop;
1123 bfd_vma start = 0;
1124 int insn = 0;
1125 struct internal_syment sym;
1126 int off, adjust, oinsn;
1127 bfd_signed_vma voff = 0;
b34976b6 1128 bfd_boolean overflow;
252b5132
RH		 1129
1130 /* Get the new reloc address. */
1131 nraddr = irel->r_vaddr - sec->vma;
1132 if ((irel->r_vaddr - sec->vma > addr
1133 && irel->r_vaddr - sec->vma < toaddr)
1134 || (irel->r_type == R_SH_ALIGN
1135 && irel->r_vaddr - sec->vma == toaddr))
1136 nraddr -= count;
1137
1138 /* See if this reloc was for the bytes we have deleted, in which
1139 case we no longer care about it. Don't delete relocs which
1140 represent addresses, though. */
1141 if (irel->r_vaddr - sec->vma >= addr
1142 && irel->r_vaddr - sec->vma < addr + count
1143 && irel->r_type != R_SH_ALIGN
1144 && irel->r_type != R_SH_CODE
1145 && irel->r_type != R_SH_DATA
1146 && irel->r_type != R_SH_LABEL)
1147 irel->r_type = R_SH_UNUSED;
1148
1149 /* If this is a PC relative reloc, see if the range it covers
1150 includes the bytes we have deleted. */
1151 switch (irel->r_type)
1152 {
1153 default:
1154 break;
1155
1156 case R_SH_PCDISP8BY2:
1157 case R_SH_PCDISP:
1158 case R_SH_PCRELIMM8BY2:
1159 case R_SH_PCRELIMM8BY4:
1160 start = irel->r_vaddr - sec->vma;
1161 insn = bfd_get_16 (abfd, contents + nraddr);
1162 break;
1163 }
1164
1165 switch (irel->r_type)
1166 {
1167 default:
1168 start = stop = addr;
1169 break;
1170
1171 case R_SH_IMM32:
17505c5c
NC		 1172#ifdef COFF_WITH_PE
1173 case R_SH_IMM32CE:
1174 case R_SH_IMAGEBASE:
1175#endif
252b5132
RH		 1176 /* If this reloc is against a symbol defined in this
1177 section, and the symbol will not be adjusted below, we
1178 must check the addend to see it will put the value in
1179 range to be adjusted, and hence must be changed. */
1180 bfd_coff_swap_sym_in (abfd,
1181 ((bfd_byte *) obj_coff_external_syms (abfd)
1182 + (irel->r_symndx
1183 * bfd_coff_symesz (abfd))),
1184 &sym);
1185 if (sym.n_sclass != C_EXT
1186 && sym.n_scnum == sec->target_index
1187 && ((bfd_vma) sym.n_value <= addr
1188 || (bfd_vma) sym.n_value >= toaddr))
1189 {
1190 bfd_vma val;
1191
1192 val = bfd_get_32 (abfd, contents + nraddr);
1193 val += sym.n_value;
1194 if (val > addr && val < toaddr)
1195 bfd_put_32 (abfd, val - count, contents + nraddr);
1196 }
1197 start = stop = addr;
1198 break;
1199
1200 case R_SH_PCDISP8BY2:
1201 off = insn & 0xff;
1202 if (off & 0x80)
1203 off -= 0x100;
1204 stop = (bfd_vma) ((bfd_signed_vma) start + 4 + off * 2);
1205 break;
1206
1207 case R_SH_PCDISP:
1208 bfd_coff_swap_sym_in (abfd,
1209 ((bfd_byte *) obj_coff_external_syms (abfd)
1210 + (irel->r_symndx
1211 * bfd_coff_symesz (abfd))),
1212 &sym);
1213 if (sym.n_sclass == C_EXT)
1214 start = stop = addr;
1215 else
1216 {
1217 off = insn & 0xfff;
1218 if (off & 0x800)
1219 off -= 0x1000;
1220 stop = (bfd_vma) ((bfd_signed_vma) start + 4 + off * 2);
1221 }
1222 break;
1223
1224 case R_SH_PCRELIMM8BY2:
1225 off = insn & 0xff;
1226 stop = start + 4 + off * 2;
1227 break;
1228
1229 case R_SH_PCRELIMM8BY4:
1230 off = insn & 0xff;
1231 stop = (start &~ (bfd_vma) 3) + 4 + off * 4;
1232 break;
1233
1234 case R_SH_SWITCH8:
1235 case R_SH_SWITCH16:
1236 case R_SH_SWITCH32:
1237 /* These relocs types represent
1238 .word L2-L1
1239 The r_offset field holds the difference between the reloc
1240 address and L1. That is the start of the reloc, and
1241 adding in the contents gives us the top. We must adjust
1242 both the r_offset field and the section contents. */
1243
1244 start = irel->r_vaddr - sec->vma;
1245 stop = (bfd_vma) ((bfd_signed_vma) start - (long) irel->r_offset);
1246
1247 if (start > addr
1248 && start < toaddr
1249 && (stop <= addr || stop >= toaddr))
1250 irel->r_offset += count;
1251 else if (stop > addr
1252 && stop < toaddr
1253 && (start <= addr || start >= toaddr))
1254 irel->r_offset -= count;
1255
1256 start = stop;
1257
1258 if (irel->r_type == R_SH_SWITCH16)
1259 voff = bfd_get_signed_16 (abfd, contents + nraddr);
1260 else if (irel->r_type == R_SH_SWITCH8)
1261 voff = bfd_get_8 (abfd, contents + nraddr);
1262 else
1263 voff = bfd_get_signed_32 (abfd, contents + nraddr);
1264 stop = (bfd_vma) ((bfd_signed_vma) start + voff);
1265
1266 break;
1267
1268 case R_SH_USES:
1269 start = irel->r_vaddr - sec->vma;
1270 stop = (bfd_vma) ((bfd_signed_vma) start
1271 + (long) irel->r_offset
1272 + 4);
1273 break;
1274 }
1275
1276 if (start > addr
1277 && start < toaddr
1278 && (stop <= addr || stop >= toaddr))
1279 adjust = count;
1280 else if (stop > addr
1281 && stop < toaddr
1282 && (start <= addr || start >= toaddr))
1283 adjust = - count;
1284 else
1285 adjust = 0;
1286
1287 if (adjust != 0)
1288 {
1289 oinsn = insn;
b34976b6 1290 overflow = FALSE;
252b5132
RH		 1291 switch (irel->r_type)
1292 {
1293 default:
1294 abort ();
1295 break;
1296
1297 case R_SH_PCDISP8BY2:
1298 case R_SH_PCRELIMM8BY2:
1299 insn += adjust / 2;
1300 if ((oinsn & 0xff00) != (insn & 0xff00))
b34976b6 1301 overflow = TRUE;
dc810e39 1302 bfd_put_16 (abfd, (bfd_vma) insn, contents + nraddr);
252b5132
RH		 1303 break;
1304
1305 case R_SH_PCDISP:
1306 insn += adjust / 2;
1307 if ((oinsn & 0xf000) != (insn & 0xf000))
b34976b6 1308 overflow = TRUE;
dc810e39 1309 bfd_put_16 (abfd, (bfd_vma) insn, contents + nraddr);
252b5132
RH		 1310 break;
1311
1312 case R_SH_PCRELIMM8BY4:
1313 BFD_ASSERT (adjust == count || count >= 4);
1314 if (count >= 4)
1315 insn += adjust / 4;
1316 else
1317 {
1318 if ((irel->r_vaddr & 3) == 0)
1319 ++insn;
1320 }
1321 if ((oinsn & 0xff00) != (insn & 0xff00))
b34976b6 1322 overflow = TRUE;
dc810e39 1323 bfd_put_16 (abfd, (bfd_vma) insn, contents + nraddr);
252b5132
RH		 1324 break;
1325
1326 case R_SH_SWITCH8:
1327 voff += adjust;
1328 if (voff < 0 || voff >= 0xff)
b34976b6 1329 overflow = TRUE;
dc810e39 1330 bfd_put_8 (abfd, (bfd_vma) voff, contents + nraddr);
252b5132
RH		 1331 break;
1332
1333 case R_SH_SWITCH16:
1334 voff += adjust;
1335 if (voff < - 0x8000 || voff >= 0x8000)
b34976b6 1336 overflow = TRUE;
dc810e39 1337 bfd_put_signed_16 (abfd, (bfd_vma) voff, contents + nraddr);
252b5132
RH		 1338 break;
1339
1340 case R_SH_SWITCH32:
1341 voff += adjust;
dc810e39 1342 bfd_put_signed_32 (abfd, (bfd_vma) voff, contents + nraddr);
252b5132
RH		 1343 break;
1344
1345 case R_SH_USES:
1346 irel->r_offset += adjust;
1347 break;
1348 }
1349
1350 if (overflow)
1351 {
4eca0228 1352 _bfd_error_handler
695344c0
NC		 1353 /* xgettext: c-format */
1354 (_("%B: 0x%lx: fatal: reloc overflow while relaxing"),
4eca0228 1355 abfd, (unsigned long) irel->r_vaddr);
252b5132 1356 bfd_set_error (bfd_error_bad_value);
b34976b6 1357 return FALSE;
252b5132
RH		 1358 }
1359 }
1360
1361 irel->r_vaddr = nraddr + sec->vma;
1362 }
1363
1364 /* Look through all the other sections. If there contain any IMM32
1365 relocs against internal symbols which we are not going to adjust
1366 below, we may need to adjust the addends. */
1367 for (o = abfd->sections; o != NULL; o = o->next)
1368 {
1369 struct internal_reloc *internal_relocs;
1370 struct internal_reloc *irelscan, *irelscanend;
1371 bfd_byte *ocontents;
1372
1373 if (o == sec
1374 || (o->flags & SEC_RELOC) == 0
1375 || o->reloc_count == 0)
1376 continue;
1377
1378 /* We always cache the relocs. Perhaps, if info->keep_memory is
b34976b6 1379 FALSE, we should free them, if we are permitted to, when we
252b5132
RH		 1380 leave sh_coff_relax_section. */
1381 internal_relocs = (_bfd_coff_read_internal_relocs
b34976b6 1382 (abfd, o, TRUE, (bfd_byte *) NULL, FALSE,
252b5132
RH		 1383 (struct internal_reloc *) NULL));
1384 if (internal_relocs == NULL)
b34976b6 1385 return FALSE;
252b5132
RH		 1386
1387 ocontents = NULL;
1388 irelscanend = internal_relocs + o->reloc_count;
1389 for (irelscan = internal_relocs; irelscan < irelscanend; irelscan++)
1390 {
1391 struct internal_syment sym;
1392
17505c5c
NC		 1393#ifdef COFF_WITH_PE
1394 if (irelscan->r_type != R_SH_IMM32
1395 && irelscan->r_type != R_SH_IMAGEBASE
1396 && irelscan->r_type != R_SH_IMM32CE)
1397#else
252b5132 1398 if (irelscan->r_type != R_SH_IMM32)
17505c5c 1399#endif
252b5132
RH		 1400 continue;
1401
1402 bfd_coff_swap_sym_in (abfd,
1403 ((bfd_byte *) obj_coff_external_syms (abfd)
1404 + (irelscan->r_symndx
1405 * bfd_coff_symesz (abfd))),
1406 &sym);
1407 if (sym.n_sclass != C_EXT
1408 && sym.n_scnum == sec->target_index
1409 && ((bfd_vma) sym.n_value <= addr
1410 || (bfd_vma) sym.n_value >= toaddr))
1411 {
1412 bfd_vma val;
1413
1414 if (ocontents == NULL)
1415 {
1416 if (coff_section_data (abfd, o)->contents != NULL)
1417 ocontents = coff_section_data (abfd, o)->contents;
1418 else
1419 {
eea6121a
AM		 1420 if (!bfd_malloc_and_get_section (abfd, o, &ocontents))
1421 return FALSE;
252b5132 1422 /* We always cache the section contents.
b34976b6 1423 Perhaps, if info->keep_memory is FALSE, we
252b5132
RH		 1424 should free them, if we are permitted to,
1425 when we leave sh_coff_relax_section. */
252b5132
RH		 1426 coff_section_data (abfd, o)->contents = ocontents;
1427 }
1428 }
1429
1430 val = bfd_get_32 (abfd, ocontents + irelscan->r_vaddr - o->vma);
1431 val += sym.n_value;
1432 if (val > addr && val < toaddr)
1433 bfd_put_32 (abfd, val - count,
1434 ocontents + irelscan->r_vaddr - o->vma);
1435
b34976b6 1436 coff_section_data (abfd, o)->keep_contents = TRUE;
252b5132
RH		 1437 }
1438 }
1439 }
1440
1441 /* Adjusting the internal symbols will not work if something has
1442 already retrieved the generic symbols. It would be possible to
1443 make this work by adjusting the generic symbols at the same time.
1444 However, this case should not arise in normal usage. */
1445 if (obj_symbols (abfd) != NULL
1446 || obj_raw_syments (abfd) != NULL)
1447 {
4eca0228 1448 _bfd_error_handler
695344c0 1449 (_("%B: fatal: generic symbols retrieved before relaxing"), abfd);
252b5132 1450 bfd_set_error (bfd_error_invalid_operation);
b34976b6 1451 return FALSE;
252b5132
RH		 1452 }
1453
1454 /* Adjust all the symbols. */
1455 sym_hash = obj_coff_sym_hashes (abfd);
1456 symesz = bfd_coff_symesz (abfd);
1457 esym = (bfd_byte *) obj_coff_external_syms (abfd);
1458 esymend = esym + obj_raw_syment_count (abfd) * symesz;
1459 while (esym < esymend)
1460 {
1461 struct internal_syment isym;
1462
2c3fc389 1463 bfd_coff_swap_sym_in (abfd, esym, &isym);
252b5132
RH		 1464
1465 if (isym.n_scnum == sec->target_index
1466 && (bfd_vma) isym.n_value > addr
1467 && (bfd_vma) isym.n_value < toaddr)
1468 {
1469 isym.n_value -= count;
1470
2c3fc389 1471 bfd_coff_swap_sym_out (abfd, &isym, esym);
252b5132
RH		 1472
1473 if (*sym_hash != NULL)
1474 {
1475 BFD_ASSERT ((*sym_hash)->root.type == bfd_link_hash_defined
1476 || (*sym_hash)->root.type == bfd_link_hash_defweak);
1477 BFD_ASSERT ((*sym_hash)->root.u.def.value >= addr
1478 && (*sym_hash)->root.u.def.value < toaddr);
1479 (*sym_hash)->root.u.def.value -= count;
1480 }
1481 }
1482
1483 esym += (isym.n_numaux + 1) * symesz;
1484 sym_hash += isym.n_numaux + 1;
1485 }
1486
1487 /* See if we can move the ALIGN reloc forward. We have adjusted
1488 r_vaddr for it already. */
1489 if (irelalign != NULL)
1490 {
1491 bfd_vma alignto, alignaddr;
1492
1493 alignto = BFD_ALIGN (toaddr, 1 << irelalign->r_offset);
1494 alignaddr = BFD_ALIGN (irelalign->r_vaddr - sec->vma,
1495 1 << irelalign->r_offset);
1496 if (alignto != alignaddr)
1497 {
1498 /* Tail recursion. */
1499 return sh_relax_delete_bytes (abfd, sec, alignaddr,
dc810e39 1500 (int) (alignto - alignaddr));
252b5132
RH		 1501 }
1502 }
1503
b34976b6 1504 return TRUE;
252b5132
RH		 1505}
1506\f
1507/* This is yet another version of the SH opcode table, used to rapidly
1508 get information about a particular instruction. */
1509
1510/* The opcode map is represented by an array of these structures. The
1511 array is indexed by the high order four bits in the instruction. */
1512
1513struct sh_major_opcode
1514{
1515 /* A pointer to the instruction list. This is an array which
1516 contains all the instructions with this major opcode. */
1517 const struct sh_minor_opcode *minor_opcodes;
1518 /* The number of elements in minor_opcodes. */
1519 unsigned short count;
1520};
1521
1522/* This structure holds information for a set of SH opcodes. The
1523 instruction code is anded with the mask value, and the resulting
1524 value is used to search the order opcode list. */
1525
1526struct sh_minor_opcode
1527{
1528 /* The sorted opcode list. */
1529 const struct sh_opcode *opcodes;
1530 /* The number of elements in opcodes. */
1531 unsigned short count;
1532 /* The mask value to use when searching the opcode list. */
1533 unsigned short mask;
1534};
1535
1536/* This structure holds information for an SH instruction. An array
1537 of these structures is sorted in order by opcode. */
1538
1539struct sh_opcode
1540{
1541 /* The code for this instruction, after it has been anded with the
1542 mask value in the sh_major_opcode structure. */
1543 unsigned short opcode;
1544 /* Flags for this instruction. */
86033394 1545 unsigned long flags;
252b5132
RH		 1546};
1547
1548/* Flag which appear in the sh_opcode structure. */
1549
1550/* This instruction loads a value from memory. */
1551#define LOAD (0x1)
1552
1553/* This instruction stores a value to memory. */
1554#define STORE (0x2)
1555
1556/* This instruction is a branch. */
1557#define BRANCH (0x4)
1558
1559/* This instruction has a delay slot. */
1560#define DELAY (0x8)
1561
1562/* This instruction uses the value in the register in the field at
1563 mask 0x0f00 of the instruction. */
1564#define USES1 (0x10)
84dcfba7 1565#define USES1_REG(x) ((x & 0x0f00) >> 8)
252b5132
RH		 1566
1567/* This instruction uses the value in the register in the field at
1568 mask 0x00f0 of the instruction. */
1569#define USES2 (0x20)
84dcfba7 1570#define USES2_REG(x) ((x & 0x00f0) >> 4)
252b5132
RH		 1571
1572/* This instruction uses the value in register 0. */
1573#define USESR0 (0x40)
1574
1575/* This instruction sets the value in the register in the field at
1576 mask 0x0f00 of the instruction. */
1577#define SETS1 (0x80)
84dcfba7 1578#define SETS1_REG(x) ((x & 0x0f00) >> 8)
252b5132
RH		 1579
1580/* This instruction sets the value in the register in the field at
1581 mask 0x00f0 of the instruction. */
1582#define SETS2 (0x100)
84dcfba7 1583#define SETS2_REG(x) ((x & 0x00f0) >> 4)
252b5132
RH		 1584
1585/* This instruction sets register 0. */
1586#define SETSR0 (0x200)
1587
1588/* This instruction sets a special register. */
1589#define SETSSP (0x400)
1590
1591/* This instruction uses a special register. */
1592#define USESSP (0x800)
1593
1594/* This instruction uses the floating point register in the field at
1595 mask 0x0f00 of the instruction. */
1596#define USESF1 (0x1000)
84dcfba7 1597#define USESF1_REG(x) ((x & 0x0f00) >> 8)
252b5132
RH		 1598
1599/* This instruction uses the floating point register in the field at
1600 mask 0x00f0 of the instruction. */
1601#define USESF2 (0x2000)
84dcfba7 1602#define USESF2_REG(x) ((x & 0x00f0) >> 4)
252b5132
RH		 1603
1604/* This instruction uses floating point register 0. */
1605#define USESF0 (0x4000)
1606
1607/* This instruction sets the floating point register in the field at
1608 mask 0x0f00 of the instruction. */
1609#define SETSF1 (0x8000)
84dcfba7 1610#define SETSF1_REG(x) ((x & 0x0f00) >> 8)
252b5132 1611
d4845d57
JR		 1612#define USESAS (0x10000)
1613#define USESAS_REG(x) (((((x) >> 8) - 2) & 3) + 2)
1614#define USESR8 (0x20000)
1615#define SETSAS (0x40000)
1616#define SETSAS_REG(x) USESAS_REG (x)
1617
8d6ad26e
AM		 1618#define MAP(a) a, sizeof a / sizeof a[0]
1619
86033394 1620#ifndef COFF_IMAGE_WITH_PE
252b5132 1621
8d6ad26e 1622/* The opcode maps. */
252b5132
RH		 1623
1624static const struct sh_opcode sh_opcode00[] =
1625{
1626 { 0x0008, SETSSP }, /* clrt */
1627 { 0x0009, 0 }, /* nop */
1628 { 0x000b, BRANCH | DELAY | USESSP }, /* rts */
1629 { 0x0018, SETSSP }, /* sett */
1630 { 0x0019, SETSSP }, /* div0u */
1631 { 0x001b, 0 }, /* sleep */
1632 { 0x0028, SETSSP }, /* clrmac */
1633 { 0x002b, BRANCH | DELAY | SETSSP }, /* rte */
1634 { 0x0038, USESSP | SETSSP }, /* ldtlb */
1635 { 0x0048, SETSSP }, /* clrs */
1636 { 0x0058, SETSSP } /* sets */
1637};
1638
1639static const struct sh_opcode sh_opcode01[] =
1640{
252b5132
RH		 1641 { 0x0003, BRANCH | DELAY | USES1 | SETSSP }, /* bsrf rn */
1642 { 0x000a, SETS1 | USESSP }, /* sts mach,rn */
252b5132 1643 { 0x001a, SETS1 | USESSP }, /* sts macl,rn */
252b5132
RH		 1644 { 0x0023, BRANCH | DELAY | USES1 }, /* braf rn */
1645 { 0x0029, SETS1 | USESSP }, /* movt rn */
1646 { 0x002a, SETS1 | USESSP }, /* sts pr,rn */
d4845d57
JR		 1647 { 0x005a, SETS1 | USESSP }, /* sts fpul,rn */
1648 { 0x006a, SETS1 | USESSP }, /* sts fpscr,rn / sts dsr,rn */
1649 { 0x0083, LOAD | USES1 }, /* pref @rn */
1650 { 0x007a, SETS1 | USESSP }, /* sts a0,rn */
1651 { 0x008a, SETS1 | USESSP }, /* sts x0,rn */
1652 { 0x009a, SETS1 | USESSP }, /* sts x1,rn */
1653 { 0x00aa, SETS1 | USESSP }, /* sts y0,rn */
1654 { 0x00ba, SETS1 | USESSP } /* sts y1,rn */
1655};
1656
252b5132
RH		 1657static const struct sh_opcode sh_opcode02[] =
1658{
d4845d57 1659 { 0x0002, SETS1 | USESSP }, /* stc <special_reg>,rn */
252b5132
RH		 1660 { 0x0004, STORE | USES1 | USES2 | USESR0 }, /* mov.b rm,@(r0,rn) */
1661 { 0x0005, STORE | USES1 | USES2 | USESR0 }, /* mov.w rm,@(r0,rn) */
1662 { 0x0006, STORE | USES1 | USES2 | USESR0 }, /* mov.l rm,@(r0,rn) */
1663 { 0x0007, SETSSP | USES1 | USES2 }, /* mul.l rm,rn */
1664 { 0x000c, LOAD | SETS1 | USES2 | USESR0 }, /* mov.b @(r0,rm),rn */
1665 { 0x000d, LOAD | SETS1 | USES2 | USESR0 }, /* mov.w @(r0,rm),rn */
1666 { 0x000e, LOAD | SETS1 | USES2 | USESR0 }, /* mov.l @(r0,rm),rn */
1667 { 0x000f, LOAD|SETS1|SETS2|SETSSP|USES1|USES2|USESSP }, /* mac.l @rm+,@rn+ */
1668};
1669
1670static const struct sh_minor_opcode sh_opcode0[] =
1671{
1672 { MAP (sh_opcode00), 0xffff },
1673 { MAP (sh_opcode01), 0xf0ff },
1674 { MAP (sh_opcode02), 0xf00f }
1675};
1676
1677static const struct sh_opcode sh_opcode10[] =
1678{
1679 { 0x1000, STORE | USES1 | USES2 } /* mov.l rm,@(disp,rn) */
1680};
1681
1682static const struct sh_minor_opcode sh_opcode1[] =
1683{
1684 { MAP (sh_opcode10), 0xf000 }
1685};
1686
1687static const struct sh_opcode sh_opcode20[] =
1688{
1689 { 0x2000, STORE | USES1 | USES2 }, /* mov.b rm,@rn */
1690 { 0x2001, STORE | USES1 | USES2 }, /* mov.w rm,@rn */
1691 { 0x2002, STORE | USES1 | USES2 }, /* mov.l rm,@rn */
1692 { 0x2004, STORE | SETS1 | USES1 | USES2 }, /* mov.b rm,@-rn */
1693 { 0x2005, STORE | SETS1 | USES1 | USES2 }, /* mov.w rm,@-rn */
1694 { 0x2006, STORE | SETS1 | USES1 | USES2 }, /* mov.l rm,@-rn */
1695 { 0x2007, SETSSP | USES1 | USES2 | USESSP }, /* div0s */
1696 { 0x2008, SETSSP | USES1 | USES2 }, /* tst rm,rn */
1697 { 0x2009, SETS1 | USES1 | USES2 }, /* and rm,rn */
1698 { 0x200a, SETS1 | USES1 | USES2 }, /* xor rm,rn */
1699 { 0x200b, SETS1 | USES1 | USES2 }, /* or rm,rn */
1700 { 0x200c, SETSSP | USES1 | USES2 }, /* cmp/str rm,rn */
1701 { 0x200d, SETS1 | USES1 | USES2 }, /* xtrct rm,rn */
1702 { 0x200e, SETSSP | USES1 | USES2 }, /* mulu.w rm,rn */
1703 { 0x200f, SETSSP | USES1 | USES2 } /* muls.w rm,rn */
1704};
1705
1706static const struct sh_minor_opcode sh_opcode2[] =
1707{
1708 { MAP (sh_opcode20), 0xf00f }
1709};
1710
1711static const struct sh_opcode sh_opcode30[] =
1712{
1713 { 0x3000, SETSSP | USES1 | USES2 }, /* cmp/eq rm,rn */
1714 { 0x3002, SETSSP | USES1 | USES2 }, /* cmp/hs rm,rn */
1715 { 0x3003, SETSSP | USES1 | USES2 }, /* cmp/ge rm,rn */
1716 { 0x3004, SETSSP | USESSP | USES1 | USES2 }, /* div1 rm,rn */
1717 { 0x3005, SETSSP | USES1 | USES2 }, /* dmulu.l rm,rn */
1718 { 0x3006, SETSSP | USES1 | USES2 }, /* cmp/hi rm,rn */
1719 { 0x3007, SETSSP | USES1 | USES2 }, /* cmp/gt rm,rn */
1720 { 0x3008, SETS1 | USES1 | USES2 }, /* sub rm,rn */
1721 { 0x300a, SETS1 | SETSSP | USES1 | USES2 | USESSP }, /* subc rm,rn */
1722 { 0x300b, SETS1 | SETSSP | USES1 | USES2 }, /* subv rm,rn */
1723 { 0x300c, SETS1 | USES1 | USES2 }, /* add rm,rn */
1724 { 0x300d, SETSSP | USES1 | USES2 }, /* dmuls.l rm,rn */
1725 { 0x300e, SETS1 | SETSSP | USES1 | USES2 | USESSP }, /* addc rm,rn */
1726 { 0x300f, SETS1 | SETSSP | USES1 | USES2 } /* addv rm,rn */
1727};
1728
1729static const struct sh_minor_opcode sh_opcode3[] =
1730{
1731 { MAP (sh_opcode30), 0xf00f }
1732};
1733
1734static const struct sh_opcode sh_opcode40[] =
1735{
1736 { 0x4000, SETS1 | SETSSP | USES1 }, /* shll rn */
1737 { 0x4001, SETS1 | SETSSP | USES1 }, /* shlr rn */
1738 { 0x4002, STORE | SETS1 | USES1 | USESSP }, /* sts.l mach,@-rn */
252b5132
RH		 1739 { 0x4004, SETS1 | SETSSP | USES1 }, /* rotl rn */
1740 { 0x4005, SETS1 | SETSSP | USES1 }, /* rotr rn */
1741 { 0x4006, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,mach */
252b5132
RH		 1742 { 0x4008, SETS1 | USES1 }, /* shll2 rn */
1743 { 0x4009, SETS1 | USES1 }, /* shlr2 rn */
1744 { 0x400a, SETSSP | USES1 }, /* lds rm,mach */
1745 { 0x400b, BRANCH | DELAY | USES1 }, /* jsr @rn */
252b5132
RH		 1746 { 0x4010, SETS1 | SETSSP | USES1 }, /* dt rn */
1747 { 0x4011, SETSSP | USES1 }, /* cmp/pz rn */
1748 { 0x4012, STORE | SETS1 | USES1 | USESSP }, /* sts.l macl,@-rn */
d4845d57 1749 { 0x4014, SETSSP | USES1 }, /* setrc rm */
252b5132
RH		 1750 { 0x4015, SETSSP | USES1 }, /* cmp/pl rn */
1751 { 0x4016, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,macl */
252b5132
RH		 1752 { 0x4018, SETS1 | USES1 }, /* shll8 rn */
1753 { 0x4019, SETS1 | USES1 }, /* shlr8 rn */
1754 { 0x401a, SETSSP | USES1 }, /* lds rm,macl */
1755 { 0x401b, LOAD | SETSSP | USES1 }, /* tas.b @rn */
252b5132
RH		 1756 { 0x4020, SETS1 | SETSSP | USES1 }, /* shal rn */
1757 { 0x4021, SETS1 | SETSSP | USES1 }, /* shar rn */
1758 { 0x4022, STORE | SETS1 | USES1 | USESSP }, /* sts.l pr,@-rn */
252b5132
RH		 1759 { 0x4024, SETS1 | SETSSP | USES1 | USESSP }, /* rotcl rn */
1760 { 0x4025, SETS1 | SETSSP | USES1 | USESSP }, /* rotcr rn */
1761 { 0x4026, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,pr */
252b5132
RH		 1762 { 0x4028, SETS1 | USES1 }, /* shll16 rn */
1763 { 0x4029, SETS1 | USES1 }, /* shlr16 rn */
1764 { 0x402a, SETSSP | USES1 }, /* lds rm,pr */
1765 { 0x402b, BRANCH | DELAY | USES1 }, /* jmp @rn */
d4845d57
JR		 1766 { 0x4052, STORE | SETS1 | USES1 | USESSP }, /* sts.l fpul,@-rn */
1767 { 0x4056, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,fpul */
1768 { 0x405a, SETSSP | USES1 }, /* lds.l rm,fpul */
1769 { 0x4062, STORE | SETS1 | USES1 | USESSP }, /* sts.l fpscr / dsr,@-rn */
1770 { 0x4066, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,fpscr / dsr */
1771 { 0x406a, SETSSP | USES1 }, /* lds rm,fpscr / lds rm,dsr */
1772 { 0x4072, STORE | SETS1 | USES1 | USESSP }, /* sts.l a0,@-rn */
1773 { 0x4076, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,a0 */
1774 { 0x407a, SETSSP | USES1 }, /* lds.l rm,a0 */
1775 { 0x4082, STORE | SETS1 | USES1 | USESSP }, /* sts.l x0,@-rn */
1776 { 0x4086, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,x0 */
1777 { 0x408a, SETSSP | USES1 }, /* lds.l rm,x0 */
1778 { 0x4092, STORE | SETS1 | USES1 | USESSP }, /* sts.l x1,@-rn */
1779 { 0x4096, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,x1 */
1780 { 0x409a, SETSSP | USES1 }, /* lds.l rm,x1 */
1781 { 0x40a2, STORE | SETS1 | USES1 | USESSP }, /* sts.l y0,@-rn */
1782 { 0x40a6, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,y0 */
1783 { 0x40aa, SETSSP | USES1 }, /* lds.l rm,y0 */
1784 { 0x40b2, STORE | SETS1 | USES1 | USESSP }, /* sts.l y1,@-rn */
1785 { 0x40b6, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,y1 */
1786 { 0x40ba, SETSSP | USES1 } /* lds.l rm,y1 */
252b5132
RH		 1787};
1788
1789static const struct sh_opcode sh_opcode41[] =
1790{
d4845d57
JR		 1791 { 0x4003, STORE | SETS1 | USES1 | USESSP }, /* stc.l <special_reg>,@-rn */
1792 { 0x4007, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,<special_reg> */
1793 { 0x400c, SETS1 | USES1 | USES2 }, /* shad rm,rn */
1794 { 0x400d, SETS1 | USES1 | USES2 }, /* shld rm,rn */
1795 { 0x400e, SETSSP | USES1 }, /* ldc rm,<special_reg> */
252b5132
RH		 1796 { 0x400f, LOAD|SETS1|SETS2|SETSSP|USES1|USES2|USESSP }, /* mac.w @rm+,@rn+ */
1797};
1798
1799static const struct sh_minor_opcode sh_opcode4[] =
1800{
1801 { MAP (sh_opcode40), 0xf0ff },
d4845d57 1802 { MAP (sh_opcode41), 0xf00f }
252b5132
RH		 1803};
1804
1805static const struct sh_opcode sh_opcode50[] =
1806{
1807 { 0x5000, LOAD | SETS1 | USES2 } /* mov.l @(disp,rm),rn */
1808};
1809
1810static const struct sh_minor_opcode sh_opcode5[] =
1811{
1812 { MAP (sh_opcode50), 0xf000 }
1813};
1814
1815static const struct sh_opcode sh_opcode60[] =
1816{
1817 { 0x6000, LOAD | SETS1 | USES2 }, /* mov.b @rm,rn */
1818 { 0x6001, LOAD | SETS1 | USES2 }, /* mov.w @rm,rn */
1819 { 0x6002, LOAD | SETS1 | USES2 }, /* mov.l @rm,rn */
1820 { 0x6003, SETS1 | USES2 }, /* mov rm,rn */
1821 { 0x6004, LOAD | SETS1 | SETS2 | USES2 }, /* mov.b @rm+,rn */
1822 { 0x6005, LOAD | SETS1 | SETS2 | USES2 }, /* mov.w @rm+,rn */
1823 { 0x6006, LOAD | SETS1 | SETS2 | USES2 }, /* mov.l @rm+,rn */
1824 { 0x6007, SETS1 | USES2 }, /* not rm,rn */
1825 { 0x6008, SETS1 | USES2 }, /* swap.b rm,rn */
1826 { 0x6009, SETS1 | USES2 }, /* swap.w rm,rn */
1827 { 0x600a, SETS1 | SETSSP | USES2 | USESSP }, /* negc rm,rn */
1828 { 0x600b, SETS1 | USES2 }, /* neg rm,rn */
1829 { 0x600c, SETS1 | USES2 }, /* extu.b rm,rn */
1830 { 0x600d, SETS1 | USES2 }, /* extu.w rm,rn */
1831 { 0x600e, SETS1 | USES2 }, /* exts.b rm,rn */
1832 { 0x600f, SETS1 | USES2 } /* exts.w rm,rn */
1833};
1834
1835static const struct sh_minor_opcode sh_opcode6[] =
1836{
1837 { MAP (sh_opcode60), 0xf00f }
1838};
1839
1840static const struct sh_opcode sh_opcode70[] =
1841{
1842 { 0x7000, SETS1 | USES1 } /* add #imm,rn */
1843};
1844
1845static const struct sh_minor_opcode sh_opcode7[] =
1846{
1847 { MAP (sh_opcode70), 0xf000 }
1848};
1849
1850static const struct sh_opcode sh_opcode80[] =
1851{
1852 { 0x8000, STORE | USES2 | USESR0 }, /* mov.b r0,@(disp,rn) */
1853 { 0x8100, STORE | USES2 | USESR0 }, /* mov.w r0,@(disp,rn) */
d4845d57 1854 { 0x8200, SETSSP }, /* setrc #imm */
252b5132
RH		 1855 { 0x8400, LOAD | SETSR0 | USES2 }, /* mov.b @(disp,rm),r0 */
1856 { 0x8500, LOAD | SETSR0 | USES2 }, /* mov.w @(disp,rn),r0 */
1857 { 0x8800, SETSSP | USESR0 }, /* cmp/eq #imm,r0 */
1858 { 0x8900, BRANCH | USESSP }, /* bt label */
1859 { 0x8b00, BRANCH | USESSP }, /* bf label */
d4845d57 1860 { 0x8c00, SETSSP }, /* ldrs @(disp,pc) */
252b5132 1861 { 0x8d00, BRANCH | DELAY | USESSP }, /* bt/s label */
d4845d57 1862 { 0x8e00, SETSSP }, /* ldre @(disp,pc) */
252b5132
RH		 1863 { 0x8f00, BRANCH | DELAY | USESSP } /* bf/s label */
1864};
1865
1866static const struct sh_minor_opcode sh_opcode8[] =
1867{
1868 { MAP (sh_opcode80), 0xff00 }
1869};
1870
1871static const struct sh_opcode sh_opcode90[] =
1872{
1873 { 0x9000, LOAD | SETS1 } /* mov.w @(disp,pc),rn */
1874};
1875
1876static const struct sh_minor_opcode sh_opcode9[] =
1877{
1878 { MAP (sh_opcode90), 0xf000 }
1879};
1880
1881static const struct sh_opcode sh_opcodea0[] =
1882{
1883 { 0xa000, BRANCH | DELAY } /* bra label */
1884};
1885
1886static const struct sh_minor_opcode sh_opcodea[] =
1887{
1888 { MAP (sh_opcodea0), 0xf000 }
1889};
1890
1891static const struct sh_opcode sh_opcodeb0[] =
1892{
1893 { 0xb000, BRANCH | DELAY } /* bsr label */
1894};
1895
1896static const struct sh_minor_opcode sh_opcodeb[] =
1897{
1898 { MAP (sh_opcodeb0), 0xf000 }
1899};
1900
1901static const struct sh_opcode sh_opcodec0[] =
1902{
1903 { 0xc000, STORE | USESR0 | USESSP }, /* mov.b r0,@(disp,gbr) */
1904 { 0xc100, STORE | USESR0 | USESSP }, /* mov.w r0,@(disp,gbr) */
1905 { 0xc200, STORE | USESR0 | USESSP }, /* mov.l r0,@(disp,gbr) */
1906 { 0xc300, BRANCH | USESSP }, /* trapa #imm */
1907 { 0xc400, LOAD | SETSR0 | USESSP }, /* mov.b @(disp,gbr),r0 */
1908 { 0xc500, LOAD | SETSR0 | USESSP }, /* mov.w @(disp,gbr),r0 */
1909 { 0xc600, LOAD | SETSR0 | USESSP }, /* mov.l @(disp,gbr),r0 */
1910 { 0xc700, SETSR0 }, /* mova @(disp,pc),r0 */
1911 { 0xc800, SETSSP | USESR0 }, /* tst #imm,r0 */
1912 { 0xc900, SETSR0 | USESR0 }, /* and #imm,r0 */
1913 { 0xca00, SETSR0 | USESR0 }, /* xor #imm,r0 */
1914 { 0xcb00, SETSR0 | USESR0 }, /* or #imm,r0 */
1915 { 0xcc00, LOAD | SETSSP | USESR0 | USESSP }, /* tst.b #imm,@(r0,gbr) */
1916 { 0xcd00, LOAD | STORE | USESR0 | USESSP }, /* and.b #imm,@(r0,gbr) */
1917 { 0xce00, LOAD | STORE | USESR0 | USESSP }, /* xor.b #imm,@(r0,gbr) */
1918 { 0xcf00, LOAD | STORE | USESR0 | USESSP } /* or.b #imm,@(r0,gbr) */
1919};
1920
1921static const struct sh_minor_opcode sh_opcodec[] =
1922{
1923 { MAP (sh_opcodec0), 0xff00 }
1924};
1925
1926static const struct sh_opcode sh_opcoded0[] =
1927{
1928 { 0xd000, LOAD | SETS1 } /* mov.l @(disp,pc),rn */
1929};
1930
1931static const struct sh_minor_opcode sh_opcoded[] =
1932{
1933 { MAP (sh_opcoded0), 0xf000 }
1934};
1935
1936static const struct sh_opcode sh_opcodee0[] =
1937{
1938 { 0xe000, SETS1 } /* mov #imm,rn */
1939};
1940
1941static const struct sh_minor_opcode sh_opcodee[] =
1942{
1943 { MAP (sh_opcodee0), 0xf000 }
1944};
1945
1946static const struct sh_opcode sh_opcodef0[] =
1947{
1948 { 0xf000, SETSF1 | USESF1 | USESF2 }, /* fadd fm,fn */
1949 { 0xf001, SETSF1 | USESF1 | USESF2 }, /* fsub fm,fn */
1950 { 0xf002, SETSF1 | USESF1 | USESF2 }, /* fmul fm,fn */
1951 { 0xf003, SETSF1 | USESF1 | USESF2 }, /* fdiv fm,fn */
1952 { 0xf004, SETSSP | USESF1 | USESF2 }, /* fcmp/eq fm,fn */
1953 { 0xf005, SETSSP | USESF1 | USESF2 }, /* fcmp/gt fm,fn */
1954 { 0xf006, LOAD | SETSF1 | USES2 | USESR0 }, /* fmov.s @(r0,rm),fn */
1955 { 0xf007, STORE | USES1 | USESF2 | USESR0 }, /* fmov.s fm,@(r0,rn) */
1956 { 0xf008, LOAD | SETSF1 | USES2 }, /* fmov.s @rm,fn */
1957 { 0xf009, LOAD | SETS2 | SETSF1 | USES2 }, /* fmov.s @rm+,fn */
1958 { 0xf00a, STORE | USES1 | USESF2 }, /* fmov.s fm,@rn */
1959 { 0xf00b, STORE | SETS1 | USES1 | USESF2 }, /* fmov.s fm,@-rn */
1960 { 0xf00c, SETSF1 | USESF2 }, /* fmov fm,fn */
1961 { 0xf00e, SETSF1 | USESF1 | USESF2 | USESF0 } /* fmac f0,fm,fn */
1962};
1963
1964static const struct sh_opcode sh_opcodef1[] =
1965{
1966 { 0xf00d, SETSF1 | USESSP }, /* fsts fpul,fn */
1967 { 0xf01d, SETSSP | USESF1 }, /* flds fn,fpul */
1968 { 0xf02d, SETSF1 | USESSP }, /* float fpul,fn */
1969 { 0xf03d, SETSSP | USESF1 }, /* ftrc fn,fpul */
1970 { 0xf04d, SETSF1 | USESF1 }, /* fneg fn */
1971 { 0xf05d, SETSF1 | USESF1 }, /* fabs fn */
1972 { 0xf06d, SETSF1 | USESF1 }, /* fsqrt fn */
1973 { 0xf07d, SETSSP | USESF1 }, /* ftst/nan fn */
1974 { 0xf08d, SETSF1 }, /* fldi0 fn */
1975 { 0xf09d, SETSF1 } /* fldi1 fn */
1976};
1977
1978static const struct sh_minor_opcode sh_opcodef[] =
1979{
1980 { MAP (sh_opcodef0), 0xf00f },
1981 { MAP (sh_opcodef1), 0xf0ff }
1982};
1983
d4845d57 1984static struct sh_major_opcode sh_opcodes[] =
252b5132
RH		 1985{
1986 { MAP (sh_opcode0) },
1987 { MAP (sh_opcode1) },
1988 { MAP (sh_opcode2) },
1989 { MAP (sh_opcode3) },
1990 { MAP (sh_opcode4) },
1991 { MAP (sh_opcode5) },
1992 { MAP (sh_opcode6) },
1993 { MAP (sh_opcode7) },
1994 { MAP (sh_opcode8) },
1995 { MAP (sh_opcode9) },
1996 { MAP (sh_opcodea) },
1997 { MAP (sh_opcodeb) },
1998 { MAP (sh_opcodec) },
1999 { MAP (sh_opcoded) },
2000 { MAP (sh_opcodee) },
2001 { MAP (sh_opcodef) }
2002};
2003
d4845d57
JR		 2004/* The double data transfer / parallel processing insns are not
2005 described here. This will cause sh_align_load_span to leave them alone. */
2006
2007static const struct sh_opcode sh_dsp_opcodef0[] =
2008{
2009 { 0xf400, USESAS | SETSAS | LOAD | SETSSP }, /* movs.x @-as,ds */
2010 { 0xf401, USESAS | SETSAS | STORE | USESSP }, /* movs.x ds,@-as */
2011 { 0xf404, USESAS | LOAD | SETSSP }, /* movs.x @as,ds */
2012 { 0xf405, USESAS | STORE | USESSP }, /* movs.x ds,@as */
2013 { 0xf408, USESAS | SETSAS | LOAD | SETSSP }, /* movs.x @as+,ds */
2014 { 0xf409, USESAS | SETSAS | STORE | USESSP }, /* movs.x ds,@as+ */
2015 { 0xf40c, USESAS | SETSAS | LOAD | SETSSP | USESR8 }, /* movs.x @as+r8,ds */
2016 { 0xf40d, USESAS | SETSAS | STORE | USESSP | USESR8 } /* movs.x ds,@as+r8 */
2017};
2018
2019static const struct sh_minor_opcode sh_dsp_opcodef[] =
2020{
2021 { MAP (sh_dsp_opcodef0), 0xfc0d }
2022};
2023
252b5132
RH		 2024/* Given an instruction, return a pointer to the corresponding
2025 sh_opcode structure. Return NULL if the instruction is not
2026 recognized. */
2027
2028static const struct sh_opcode *
2c3fc389 2029sh_insn_info (unsigned int insn)
252b5132
RH		 2030{
2031 const struct sh_major_opcode *maj;
2032 const struct sh_minor_opcode *min, *minend;
2033
2034 maj = &sh_opcodes[(insn & 0xf000) >> 12];
2035 min = maj->minor_opcodes;
2036 minend = min + maj->count;
2037 for (; min < minend; min++)
2038 {
2039 unsigned int l;
2040 const struct sh_opcode *op, *opend;
2041
2042 l = insn & min->mask;
2043 op = min->opcodes;
2044 opend = op + min->count;
2045
2046 /* Since the opcodes tables are sorted, we could use a binary
2047 search here if the count were above some cutoff value. */
2048 for (; op < opend; op++)
2049 if (op->opcode == l)
2050 return op;
2051 }
2052
cbfe05c4 2053 return NULL;
252b5132
RH		 2054}
2055
2056/* See whether an instruction uses a general purpose register. */
2057
b34976b6 2058static bfd_boolean
2c3fc389
NC		 2059sh_insn_uses_reg (unsigned int insn,
2060 const struct sh_opcode *op,
2061 unsigned int reg)
252b5132
RH		 2062{
2063 unsigned int f;
2064
2065 f = op->flags;
2066
2067 if ((f & USES1) != 0
84dcfba7 2068 && USES1_REG (insn) == reg)
b34976b6 2069 return TRUE;
252b5132 2070 if ((f & USES2) != 0
84dcfba7 2071 && USES2_REG (insn) == reg)
b34976b6 2072 return TRUE;
252b5132
RH		 2073 if ((f & USESR0) != 0
2074 && reg == 0)
b34976b6 2075 return TRUE;
d4845d57 2076 if ((f & USESAS) && reg == USESAS_REG (insn))
b34976b6 2077 return TRUE;
d4845d57 2078 if ((f & USESR8) && reg == 8)
b34976b6 2079 return TRUE;
252b5132 2080
b34976b6 2081 return FALSE;
252b5132 2082}
17505c5c 2083
84dcfba7
JR		 2084/* See whether an instruction sets a general purpose register. */
2085
b34976b6 2086static bfd_boolean
2c3fc389
NC		 2087sh_insn_sets_reg (unsigned int insn,
2088 const struct sh_opcode *op,
2089 unsigned int reg)
84dcfba7
JR		 2090{
2091 unsigned int f;
2092
2093 f = op->flags;
2094
2095 if ((f & SETS1) != 0
2096 && SETS1_REG (insn) == reg)
b34976b6 2097 return TRUE;
84dcfba7
JR		 2098 if ((f & SETS2) != 0
2099 && SETS2_REG (insn) == reg)
b34976b6 2100 return TRUE;
84dcfba7
JR		 2101 if ((f & SETSR0) != 0
2102 && reg == 0)
b34976b6 2103 return TRUE;
d4845d57 2104 if ((f & SETSAS) && reg == SETSAS_REG (insn))
b34976b6 2105 return TRUE;
84dcfba7 2106
b34976b6 2107 return FALSE;
84dcfba7
JR		 2108}
2109
2c3fc389 2110/* See whether an instruction uses or sets a general purpose register */
84dcfba7 2111
b34976b6 2112static bfd_boolean
2c3fc389
NC		 2113sh_insn_uses_or_sets_reg (unsigned int insn,
2114 const struct sh_opcode *op,
2115 unsigned int reg)
84dcfba7 2116{
2c3fc389 2117 if (sh_insn_uses_reg (insn, op, reg))
b34976b6 2118 return TRUE;
84dcfba7 2119
2c3fc389 2120 return sh_insn_sets_reg (insn, op, reg);
84dcfba7 2121}
252b5132
RH		 2122
2123/* See whether an instruction uses a floating point register. */
2124
b34976b6 2125static bfd_boolean
2c3fc389
NC		 2126sh_insn_uses_freg (unsigned int insn,
2127 const struct sh_opcode *op,
2128 unsigned int freg)
252b5132
RH		 2129{
2130 unsigned int f;
2131
2132 f = op->flags;
2133
2134 /* We can't tell if this is a double-precision insn, so just play safe
2135 and assume that it might be. So not only have we test FREG against
2136 itself, but also even FREG against FREG+1 - if the using insn uses
2137 just the low part of a double precision value - but also an odd
2138 FREG against FREG-1 - if the setting insn sets just the low part
2139 of a double precision value.
2140 So what this all boils down to is that we have to ignore the lowest
2141 bit of the register number. */
cbfe05c4 2142
252b5132 2143 if ((f & USESF1) != 0
84dcfba7 2144 && (USESF1_REG (insn) & 0xe) == (freg & 0xe))
b34976b6 2145 return TRUE;
252b5132 2146 if ((f & USESF2) != 0
84dcfba7 2147 && (USESF2_REG (insn) & 0xe) == (freg & 0xe))
b34976b6 2148 return TRUE;
252b5132
RH		 2149 if ((f & USESF0) != 0
2150 && freg == 0)
b34976b6 2151 return TRUE;
252b5132 2152
b34976b6 2153 return FALSE;
252b5132
RH		 2154}
2155
84dcfba7
JR		 2156/* See whether an instruction sets a floating point register. */
2157
b34976b6 2158static bfd_boolean
2c3fc389
NC		 2159sh_insn_sets_freg (unsigned int insn,
2160 const struct sh_opcode *op,
2161 unsigned int freg)
84dcfba7
JR		 2162{
2163 unsigned int f;
2164
2165 f = op->flags;
2166
2167 /* We can't tell if this is a double-precision insn, so just play safe
2168 and assume that it might be. So not only have we test FREG against
2169 itself, but also even FREG against FREG+1 - if the using insn uses
2170 just the low part of a double precision value - but also an odd
2171 FREG against FREG-1 - if the setting insn sets just the low part
2172 of a double precision value.
2173 So what this all boils down to is that we have to ignore the lowest
2174 bit of the register number. */
cbfe05c4 2175
84dcfba7
JR		 2176 if ((f & SETSF1) != 0
2177 && (SETSF1_REG (insn) & 0xe) == (freg & 0xe))
b34976b6 2178 return TRUE;
84dcfba7 2179
b34976b6 2180 return FALSE;
84dcfba7
JR		 2181}
2182
2c3fc389
NC		 2183/* See whether an instruction uses or sets a floating point register */
2184
2185static bfd_boolean
2186sh_insn_uses_or_sets_freg (unsigned int insn,
2187 const struct sh_opcode *op,
2188 unsigned int reg)
2189{
2190 if (sh_insn_uses_freg (insn, op, reg))
2191 return TRUE;
2192
2193 return sh_insn_sets_freg (insn, op, reg);
2194}
2195
252b5132
RH		 2196/* See whether instructions I1 and I2 conflict, assuming I1 comes
2197 before I2. OP1 and OP2 are the corresponding sh_opcode structures.
b34976b6 2198 This should return TRUE if there is a conflict, or FALSE if the
252b5132
RH		 2199 instructions can be swapped safely. */
2200
b34976b6 2201static bfd_boolean
2c3fc389
NC		 2202sh_insns_conflict (unsigned int i1,
2203 const struct sh_opcode *op1,
2204 unsigned int i2,
2205 const struct sh_opcode *op2)
252b5132
RH		 2206{
2207 unsigned int f1, f2;
2208
2209 f1 = op1->flags;
2210 f2 = op2->flags;
2211
2212 /* Load of fpscr conflicts with floating point operations.
2213 FIXME: shouldn't test raw opcodes here. */
2214 if (((i1 & 0xf0ff) == 0x4066 && (i2 & 0xf000) == 0xf000)
2215 || ((i2 & 0xf0ff) == 0x4066 && (i1 & 0xf000) == 0xf000))
b34976b6 2216 return TRUE;
252b5132
RH		 2217
2218 if ((f1 & (BRANCH | DELAY)) != 0
2219 || (f2 & (BRANCH | DELAY)) != 0)
b34976b6 2220 return TRUE;
252b5132 2221
84dcfba7
JR		 2222 if (((f1 | f2) & SETSSP)
2223 && (f1 & (SETSSP | USESSP))
2224 && (f2 & (SETSSP | USESSP)))
b34976b6 2225 return TRUE;
252b5132
RH		 2226
2227 if ((f1 & SETS1) != 0
84dcfba7 2228 && sh_insn_uses_or_sets_reg (i2, op2, SETS1_REG (i1)))
b34976b6 2229 return TRUE;
252b5132 2230 if ((f1 & SETS2) != 0
84dcfba7 2231 && sh_insn_uses_or_sets_reg (i2, op2, SETS2_REG (i1)))
b34976b6 2232 return TRUE;
252b5132 2233 if ((f1 & SETSR0) != 0
84dcfba7 2234 && sh_insn_uses_or_sets_reg (i2, op2, 0))
b34976b6 2235 return TRUE;
d4845d57
JR		 2236 if ((f1 & SETSAS)
2237 && sh_insn_uses_or_sets_reg (i2, op2, SETSAS_REG (i1)))
b34976b6 2238 return TRUE;
252b5132 2239 if ((f1 & SETSF1) != 0
84dcfba7 2240 && sh_insn_uses_or_sets_freg (i2, op2, SETSF1_REG (i1)))
b34976b6 2241 return TRUE;
252b5132
RH		 2242
2243 if ((f2 & SETS1) != 0
84dcfba7 2244 && sh_insn_uses_or_sets_reg (i1, op1, SETS1_REG (i2)))
b34976b6 2245 return TRUE;
252b5132 2246 if ((f2 & SETS2) != 0
84dcfba7 2247 && sh_insn_uses_or_sets_reg (i1, op1, SETS2_REG (i2)))
b34976b6 2248 return TRUE;
252b5132 2249 if ((f2 & SETSR0) != 0
84dcfba7 2250 && sh_insn_uses_or_sets_reg (i1, op1, 0))
b34976b6 2251 return TRUE;
d4845d57
JR		 2252 if ((f2 & SETSAS)
2253 && sh_insn_uses_or_sets_reg (i1, op1, SETSAS_REG (i2)))
b34976b6 2254 return TRUE;
252b5132 2255 if ((f2 & SETSF1) != 0
84dcfba7 2256 && sh_insn_uses_or_sets_freg (i1, op1, SETSF1_REG (i2)))
b34976b6 2257 return TRUE;
252b5132
RH		 2258
2259 /* The instructions do not conflict. */
b34976b6 2260 return FALSE;
252b5132
RH		 2261}
2262
2263/* I1 is a load instruction, and I2 is some other instruction. Return
b34976b6 2264 TRUE if I1 loads a register which I2 uses. */
252b5132 2265
b34976b6 2266static bfd_boolean
2c3fc389
NC		 2267sh_load_use (unsigned int i1,
2268 const struct sh_opcode *op1,
2269 unsigned int i2,
2270 const struct sh_opcode *op2)
252b5132
RH		 2271{
2272 unsigned int f1;
2273
2274 f1 = op1->flags;
2275
2276 if ((f1 & LOAD) == 0)
b34976b6 2277 return FALSE;
252b5132
RH		 2278
2279 /* If both SETS1 and SETSSP are set, that means a load to a special
2280 register using postincrement addressing mode, which we don't care
2281 about here. */
2282 if ((f1 & SETS1) != 0
2283 && (f1 & SETSSP) == 0
2284 && sh_insn_uses_reg (i2, op2, (i1 & 0x0f00) >> 8))
b34976b6 2285 return TRUE;
252b5132
RH		 2286
2287 if ((f1 & SETSR0) != 0
2288 && sh_insn_uses_reg (i2, op2, 0))
b34976b6 2289 return TRUE;
252b5132
RH		 2290
2291 if ((f1 & SETSF1) != 0
2292 && sh_insn_uses_freg (i2, op2, (i1 & 0x0f00) >> 8))
b34976b6 2293 return TRUE;
252b5132 2294
b34976b6 2295 return FALSE;
252b5132
RH		 2296}
2297
2298/* Try to align loads and stores within a span of memory. This is
2299 called by both the ELF and the COFF sh targets. ABFD and SEC are
2300 the BFD and section we are examining. CONTENTS is the contents of
2301 the section. SWAP is the routine to call to swap two instructions.
2302 RELOCS is a pointer to the internal relocation information, to be
2303 passed to SWAP. PLABEL is a pointer to the current label in a
2304 sorted list of labels; LABEL_END is the end of the list. START and
2305 STOP are the range of memory to examine. If a swap is made,
b34976b6 2306 *PSWAPPED is set to TRUE. */
252b5132 2307
86033394
NC		 2308#ifdef COFF_WITH_PE
2309static
2310#endif
b34976b6 2311bfd_boolean
2c3fc389
NC		 2312_bfd_sh_align_load_span (bfd *abfd,
2313 asection *sec,
2314 bfd_byte *contents,
2315 bfd_boolean (*swap) (bfd *, asection *, void *, bfd_byte *, bfd_vma),
2316 void * relocs,
2317 bfd_vma **plabel,
2318 bfd_vma *label_end,
2319 bfd_vma start,
2320 bfd_vma stop,
2321 bfd_boolean *pswapped)
252b5132 2322{
d4845d57
JR		 2323 int dsp = (abfd->arch_info->mach == bfd_mach_sh_dsp
2324 || abfd->arch_info->mach == bfd_mach_sh3_dsp);
252b5132
RH		 2325 bfd_vma i;
2326
d4845d57
JR		 2327 /* The SH4 has a Harvard architecture, hence aligning loads is not
2328 desirable. In fact, it is counter-productive, since it interferes
2329 with the schedules generated by the compiler. */
2330 if (abfd->arch_info->mach == bfd_mach_sh4)
b34976b6 2331 return TRUE;
d4845d57
JR		 2332
2333 /* If we are linking sh[3]-dsp code, swap the FPU instructions for DSP
2334 instructions. */
2335 if (dsp)
2336 {
2337 sh_opcodes[0xf].minor_opcodes = sh_dsp_opcodef;
4c0160b8 2338 sh_opcodes[0xf].count = sizeof sh_dsp_opcodef / sizeof sh_dsp_opcodef [0];
d4845d57
JR		 2339 }
2340
252b5132
RH		 2341 /* Instructions should be aligned on 2 byte boundaries. */
2342 if ((start & 1) == 1)
2343 ++start;
2344
2345 /* Now look through the unaligned addresses. */
2346 i = start;
2347 if ((i & 2) == 0)
2348 i += 2;
2349 for (; i < stop; i += 4)
2350 {
2351 unsigned int insn;
2352 const struct sh_opcode *op;
2353 unsigned int prev_insn = 0;
2354 const struct sh_opcode *prev_op = NULL;
2355
2356 insn = bfd_get_16 (abfd, contents + i);
2357 op = sh_insn_info (insn);
2358 if (op == NULL
2359 || (op->flags & (LOAD | STORE)) == 0)
2360 continue;
2361
2362 /* This is a load or store which is not on a four byte boundary. */
2363
2364 while (*plabel < label_end && **plabel < i)
2365 ++*plabel;
2366
2367 if (i > start)
2368 {
2369 prev_insn = bfd_get_16 (abfd, contents + i - 2);
d4845d57
JR		 2370 /* If INSN is the field b of a parallel processing insn, it is not
2371 a load / store after all. Note that the test here might mistake
2372 the field_b of a pcopy insn for the starting code of a parallel
2373 processing insn; this might miss a swapping opportunity, but at
2374 least we're on the safe side. */
2375 if (dsp && (prev_insn & 0xfc00) == 0xf800)
2376 continue;
2377
2378 /* Check if prev_insn is actually the field b of a parallel
2379 processing insn. Again, this can give a spurious match
2380 after a pcopy. */
2381 if (dsp && i - 2 > start)
2382 {
2383 unsigned pprev_insn = bfd_get_16 (abfd, contents + i - 4);
cbfe05c4 2384
d4845d57
JR		 2385 if ((pprev_insn & 0xfc00) == 0xf800)
2386 prev_op = NULL;
2387 else
2388 prev_op = sh_insn_info (prev_insn);
2389 }
2390 else
2391 prev_op = sh_insn_info (prev_insn);
252b5132
RH		 2392
2393 /* If the load/store instruction is in a delay slot, we
2394 can't swap. */
2395 if (prev_op == NULL
2396 || (prev_op->flags & DELAY) != 0)
2397 continue;
2398 }
2399 if (i > start
2400 && (*plabel >= label_end || **plabel != i)
2401 && prev_op != NULL
2402 && (prev_op->flags & (LOAD | STORE)) == 0
2403 && ! sh_insns_conflict (prev_insn, prev_op, insn, op))
2404 {
b34976b6 2405 bfd_boolean ok;
252b5132
RH		 2406
2407 /* The load/store instruction does not have a label, and
2408 there is a previous instruction; PREV_INSN is not
2409 itself a load/store instruction, and PREV_INSN and
2410 INSN do not conflict. */
2411
b34976b6 2412 ok = TRUE;
252b5132
RH		 2413
2414 if (i >= start + 4)
2415 {
2416 unsigned int prev2_insn;
2417 const struct sh_opcode *prev2_op;
2418
2419 prev2_insn = bfd_get_16 (abfd, contents + i - 4);
2420 prev2_op = sh_insn_info (prev2_insn);
2421
2422 /* If the instruction before PREV_INSN has a delay
2423 slot--that is, PREV_INSN is in a delay slot--we
2424 can not swap. */
2425 if (prev2_op == NULL
2426 || (prev2_op->flags & DELAY) != 0)
b34976b6 2427 ok = FALSE;
252b5132
RH		 2428
2429 /* If the instruction before PREV_INSN is a load,
2430 and it sets a register which INSN uses, then
2431 putting INSN immediately after PREV_INSN will
2432 cause a pipeline bubble, so there is no point to
2433 making the swap. */
2434 if (ok
2435 && (prev2_op->flags & LOAD) != 0
2436 && sh_load_use (prev2_insn, prev2_op, insn, op))
b34976b6 2437 ok = FALSE;
252b5132
RH		 2438 }
2439
2440 if (ok)
2441 {
2442 if (! (*swap) (abfd, sec, relocs, contents, i - 2))
b34976b6
AM		 2443 return FALSE;
2444 *pswapped = TRUE;
252b5132
RH		 2445 continue;
2446 }
2447 }
2448
2449 while (*plabel < label_end && **plabel < i + 2)
2450 ++*plabel;
2451
2452 if (i + 2 < stop
2453 && (*plabel >= label_end || **plabel != i + 2))
2454 {
2455 unsigned int next_insn;
2456 const struct sh_opcode *next_op;
2457
2458 /* There is an instruction after the load/store
2459 instruction, and it does not have a label. */
2460 next_insn = bfd_get_16 (abfd, contents + i + 2);
2461 next_op = sh_insn_info (next_insn);
2462 if (next_op != NULL
2463 && (next_op->flags & (LOAD | STORE)) == 0
2464 && ! sh_insns_conflict (insn, op, next_insn, next_op))
2465 {
b34976b6 2466 bfd_boolean ok;
252b5132
RH		 2467
2468 /* NEXT_INSN is not itself a load/store instruction,
2469 and it does not conflict with INSN. */
2470
b34976b6 2471 ok = TRUE;
252b5132
RH		 2472
2473 /* If PREV_INSN is a load, and it sets a register
2474 which NEXT_INSN uses, then putting NEXT_INSN
2475 immediately after PREV_INSN will cause a pipeline
2476 bubble, so there is no reason to make this swap. */
2477 if (prev_op != NULL
2478 && (prev_op->flags & LOAD) != 0
2479 && sh_load_use (prev_insn, prev_op, next_insn, next_op))
b34976b6 2480 ok = FALSE;
252b5132
RH		 2481
2482 /* If INSN is a load, and it sets a register which
2483 the insn after NEXT_INSN uses, then doing the
2484 swap will cause a pipeline bubble, so there is no
2485 reason to make the swap. However, if the insn
2486 after NEXT_INSN is itself a load or store
2487 instruction, then it is misaligned, so
2488 optimistically hope that it will be swapped
2489 itself, and just live with the pipeline bubble if
2490 it isn't. */
2491 if (ok
2492 && i + 4 < stop
2493 && (op->flags & LOAD) != 0)
2494 {
2495 unsigned int next2_insn;
2496 const struct sh_opcode *next2_op;
2497
2498 next2_insn = bfd_get_16 (abfd, contents + i + 4);
2499 next2_op = sh_insn_info (next2_insn);
230d6d81
NC		 2500 if (next2_op == NULL
2501 || ((next2_op->flags & (LOAD | STORE)) == 0
2502 && sh_load_use (insn, op, next2_insn, next2_op)))
b34976b6 2503 ok = FALSE;
252b5132
RH		 2504 }
2505
2506 if (ok)
2507 {
2508 if (! (*swap) (abfd, sec, relocs, contents, i))
b34976b6
AM		 2509 return FALSE;
2510 *pswapped = TRUE;
252b5132
RH		 2511 continue;
2512 }
2513 }
2514 }
2515 }
2516
b34976b6 2517 return TRUE;
252b5132 2518}
86033394 2519#endif /* not COFF_IMAGE_WITH_PE */
252b5132 2520
252b5132
RH		 2521/* Swap two SH instructions. */
2522
b34976b6 2523static bfd_boolean
2c3fc389
NC		 2524sh_swap_insns (bfd * abfd,
2525 asection * sec,
2526 void * relocs,
2527 bfd_byte * contents,
2528 bfd_vma addr)
252b5132
RH		 2529{
2530 struct internal_reloc *internal_relocs = (struct internal_reloc *) relocs;
2531 unsigned short i1, i2;
2532 struct internal_reloc *irel, *irelend;
2533
2534 /* Swap the instructions themselves. */
2535 i1 = bfd_get_16 (abfd, contents + addr);
2536 i2 = bfd_get_16 (abfd, contents + addr + 2);
dc810e39
AM		 2537 bfd_put_16 (abfd, (bfd_vma) i2, contents + addr);
2538 bfd_put_16 (abfd, (bfd_vma) i1, contents + addr + 2);
252b5132
RH		 2539
2540 /* Adjust all reloc addresses. */
2541 irelend = internal_relocs + sec->reloc_count;
2542 for (irel = internal_relocs; irel < irelend; irel++)
2543 {
2544 int type, add;
2545
2546 /* There are a few special types of relocs that we don't want to
2547 adjust. These relocs do not apply to the instruction itself,
2548 but are only associated with the address. */
2549 type = irel->r_type;
2550 if (type == R_SH_ALIGN
2551 || type == R_SH_CODE
2552 || type == R_SH_DATA
2553 || type == R_SH_LABEL)
2554 continue;
2555
2556 /* If an R_SH_USES reloc points to one of the addresses being
2557 swapped, we must adjust it. It would be incorrect to do this
2558 for a jump, though, since we want to execute both
2559 instructions after the jump. (We have avoided swapping
2560 around a label, so the jump will not wind up executing an
2561 instruction it shouldn't). */
2562 if (type == R_SH_USES)
2563 {
2564 bfd_vma off;
2565
2566 off = irel->r_vaddr - sec->vma + 4 + irel->r_offset;
2567 if (off == addr)
2568 irel->r_offset += 2;
2569 else if (off == addr + 2)
2570 irel->r_offset -= 2;
2571 }
2572
2573 if (irel->r_vaddr - sec->vma == addr)
2574 {
2575 irel->r_vaddr += 2;
2576 add = -2;
2577 }
2578 else if (irel->r_vaddr - sec->vma == addr + 2)
2579 {
2580 irel->r_vaddr -= 2;
2581 add = 2;
2582 }
2583 else
2584 add = 0;
2585
2586 if (add != 0)
2587 {
2588 bfd_byte *loc;
2589 unsigned short insn, oinsn;
b34976b6 2590 bfd_boolean overflow;
252b5132
RH		 2591
2592 loc = contents + irel->r_vaddr - sec->vma;
b34976b6 2593 overflow = FALSE;
252b5132
RH		 2594 switch (type)
2595 {
2596 default:
2597 break;
2598
2599 case R_SH_PCDISP8BY2:
2600 case R_SH_PCRELIMM8BY2:
2601 insn = bfd_get_16 (abfd, loc);
2602 oinsn = insn;
2603 insn += add / 2;
2604 if ((oinsn & 0xff00) != (insn & 0xff00))
b34976b6 2605 overflow = TRUE;
dc810e39 2606 bfd_put_16 (abfd, (bfd_vma) insn, loc);
252b5132
RH		 2607 break;
2608
2609 case R_SH_PCDISP:
2610 insn = bfd_get_16 (abfd, loc);
2611 oinsn = insn;
2612 insn += add / 2;
2613 if ((oinsn & 0xf000) != (insn & 0xf000))
b34976b6 2614 overflow = TRUE;
dc810e39 2615 bfd_put_16 (abfd, (bfd_vma) insn, loc);
252b5132
RH		 2616 break;
2617
2618 case R_SH_PCRELIMM8BY4:
2619 /* This reloc ignores the least significant 3 bits of
2620 the program counter before adding in the offset.
2621 This means that if ADDR is at an even address, the
2622 swap will not affect the offset. If ADDR is an at an
2623 odd address, then the instruction will be crossing a
2624 four byte boundary, and must be adjusted. */
2625 if ((addr & 3) != 0)
2626 {
2627 insn = bfd_get_16 (abfd, loc);
2628 oinsn = insn;
2629 insn += add / 2;
2630 if ((oinsn & 0xff00) != (insn & 0xff00))
b34976b6 2631 overflow = TRUE;
dc810e39 2632 bfd_put_16 (abfd, (bfd_vma) insn, loc);
252b5132
RH		 2633 }
2634
2635 break;
2636 }
2637
2638 if (overflow)
2639 {
4eca0228 2640 _bfd_error_handler
695344c0
NC		 2641 /* xgettext: c-format */
2642 (_("%B: 0x%lx: fatal: reloc overflow while relaxing"),
4eca0228 2643 abfd, (unsigned long) irel->r_vaddr);
252b5132 2644 bfd_set_error (bfd_error_bad_value);
b34976b6 2645 return FALSE;
252b5132
RH		 2646 }
2647 }
2648 }
2649
b34976b6 2650 return TRUE;
252b5132 2651}
2c3fc389
NC		 2652
2653/* Look for loads and stores which we can align to four byte
2654 boundaries. See the longer comment above sh_relax_section for why
2655 this is desirable. This sets *PSWAPPED if some instruction was
2656 swapped. */
2657
2658static bfd_boolean
2659sh_align_loads (bfd *abfd,
2660 asection *sec,
2661 struct internal_reloc *internal_relocs,
2662 bfd_byte *contents,
2663 bfd_boolean *pswapped)
2664{
2665 struct internal_reloc *irel, *irelend;
2666 bfd_vma *labels = NULL;
2667 bfd_vma *label, *label_end;
2668 bfd_size_type amt;
2669
2670 *pswapped = FALSE;
2671
2672 irelend = internal_relocs + sec->reloc_count;
2673
2674 /* Get all the addresses with labels on them. */
2675 amt = (bfd_size_type) sec->reloc_count * sizeof (bfd_vma);
2676 labels = (bfd_vma *) bfd_malloc (amt);
2677 if (labels == NULL)
2678 goto error_return;
2679 label_end = labels;
2680 for (irel = internal_relocs; irel < irelend; irel++)
2681 {
2682 if (irel->r_type == R_SH_LABEL)
2683 {
2684 *label_end = irel->r_vaddr - sec->vma;
2685 ++label_end;
2686 }
2687 }
2688
2689 /* Note that the assembler currently always outputs relocs in
2690 address order. If that ever changes, this code will need to sort
2691 the label values and the relocs. */
2692
2693 label = labels;
2694
2695 for (irel = internal_relocs; irel < irelend; irel++)
2696 {
2697 bfd_vma start, stop;
2698
2699 if (irel->r_type != R_SH_CODE)
2700 continue;
2701
2702 start = irel->r_vaddr - sec->vma;
2703
2704 for (irel++; irel < irelend; irel++)
2705 if (irel->r_type == R_SH_DATA)
2706 break;
2707 if (irel < irelend)
2708 stop = irel->r_vaddr - sec->vma;
2709 else
2710 stop = sec->size;
2711
2712 if (! _bfd_sh_align_load_span (abfd, sec, contents, sh_swap_insns,
2713 internal_relocs, &label,
2714 label_end, start, stop, pswapped))
2715 goto error_return;
2716 }
2717
2718 free (labels);
2719
2720 return TRUE;
2721
2722 error_return:
2723 if (labels != NULL)
2724 free (labels);
2725 return FALSE;
2726}
252b5132
RH		 2727\f
2728/* This is a modification of _bfd_coff_generic_relocate_section, which
2729 will handle SH relaxing. */
2730
b34976b6 2731static bfd_boolean
2c3fc389
NC		 2732sh_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
2733 struct bfd_link_info *info,
2734 bfd *input_bfd,
2735 asection *input_section,
2736 bfd_byte *contents,
2737 struct internal_reloc *relocs,
2738 struct internal_syment *syms,
2739 asection **sections)
252b5132
RH		 2740{
2741 struct internal_reloc *rel;
2742 struct internal_reloc *relend;
2743
2744 rel = relocs;
2745 relend = rel + input_section->reloc_count;
2746 for (; rel < relend; rel++)
2747 {
2748 long symndx;
2749 struct coff_link_hash_entry *h;
2750 struct internal_syment *sym;
2751 bfd_vma addend;
2752 bfd_vma val;
2753 reloc_howto_type *howto;
2754 bfd_reloc_status_type rstat;
2755
2756 /* Almost all relocs have to do with relaxing. If any work must
2757 be done for them, it has been done in sh_relax_section. */
2758 if (rel->r_type != R_SH_IMM32
17505c5c
NC		 2759#ifdef COFF_WITH_PE
2760 && rel->r_type != R_SH_IMM32CE
2761 && rel->r_type != R_SH_IMAGEBASE
2762#endif
252b5132
RH		 2763 && rel->r_type != R_SH_PCDISP)
2764 continue;
2765
2766 symndx = rel->r_symndx;
2767
2768 if (symndx == -1)
2769 {
2770 h = NULL;
2771 sym = NULL;
2772 }
2773 else
cbfe05c4 2774 {
252b5132
RH		 2775 if (symndx < 0
2776 || (unsigned long) symndx >= obj_raw_syment_count (input_bfd))
2777 {
4eca0228 2778 _bfd_error_handler
695344c0
NC		 2779 /* xgettext: c-format */
2780 (_("%B: illegal symbol index %ld in relocs"),
d003868e 2781 input_bfd, symndx);
252b5132 2782 bfd_set_error (bfd_error_bad_value);
b34976b6 2783 return FALSE;
252b5132
RH		 2784 }
2785 h = obj_coff_sym_hashes (input_bfd)[symndx];
2786 sym = syms + symndx;
2787 }
2788
2789 if (sym != NULL && sym->n_scnum != 0)
2790 addend = - sym->n_value;
2791 else
2792 addend = 0;
2793
2794 if (rel->r_type == R_SH_PCDISP)
2795 addend -= 4;
2796
2797 if (rel->r_type >= SH_COFF_HOWTO_COUNT)
2798 howto = NULL;
2799 else
2800 howto = &sh_coff_howtos[rel->r_type];
2801
2802 if (howto == NULL)
2803 {
2804 bfd_set_error (bfd_error_bad_value);
b34976b6 2805 return FALSE;
252b5132
RH		 2806 }
2807
17505c5c
NC		 2808#ifdef COFF_WITH_PE
2809 if (rel->r_type == R_SH_IMAGEBASE)
2810 addend -= pe_data (input_section->output_section->owner)->pe_opthdr.ImageBase;
2811#endif
cbfe05c4 2812
252b5132
RH		 2813 val = 0;
2814
2815 if (h == NULL)
2816 {
2817 asection *sec;
2818
2819 /* There is nothing to do for an internal PCDISP reloc. */
2820 if (rel->r_type == R_SH_PCDISP)
2821 continue;
2822
2823 if (symndx == -1)
2824 {
2825 sec = bfd_abs_section_ptr;
2826 val = 0;
2827 }
2828 else
2829 {
2830 sec = sections[symndx];
2831 val = (sec->output_section->vma
2832 + sec->output_offset
2833 + sym->n_value
2834 - sec->vma);
2835 }
2836 }
2837 else
2838 {
2839 if (h->root.type == bfd_link_hash_defined
2840 || h->root.type == bfd_link_hash_defweak)
2841 {
2842 asection *sec;
2843
2844 sec = h->root.u.def.section;
2845 val = (h->root.u.def.value
2846 + sec->output_section->vma
2847 + sec->output_offset);
2848 }
0e1862bb 2849 else if (! bfd_link_relocatable (info))
1a72702b
AM		 2850 (*info->callbacks->undefined_symbol)
2851 (info, h->root.root.string, input_bfd, input_section,
2852 rel->r_vaddr - input_section->vma, TRUE);
252b5132
RH		 2853 }
2854
2855 rstat = _bfd_final_link_relocate (howto, input_bfd, input_section,
2856 contents,
2857 rel->r_vaddr - input_section->vma,
2858 val, addend);
2859
2860 switch (rstat)
2861 {
2862 default:
2863 abort ();
2864 case bfd_reloc_ok:
2865 break;
2866 case bfd_reloc_overflow:
2867 {
2868 const char *name;
2869 char buf[SYMNMLEN + 1];
2870
2871 if (symndx == -1)
2872 name = "*ABS*";
2873 else if (h != NULL)
dfeffb9f 2874 name = NULL;
252b5132
RH		 2875 else if (sym->_n._n_n._n_zeroes == 0
2876 && sym->_n._n_n._n_offset != 0)
2877 name = obj_coff_strings (input_bfd) + sym->_n._n_n._n_offset;
2878 else
2879 {
2880 strncpy (buf, sym->_n._n_name, SYMNMLEN);
2881 buf[SYMNMLEN] = '\0';
2882 name = buf;
2883 }
2884
1a72702b
AM		 2885 (*info->callbacks->reloc_overflow)
2886 (info, (h ? &h->root : NULL), name, howto->name,
2887 (bfd_vma) 0, input_bfd, input_section,
2888 rel->r_vaddr - input_section->vma);
252b5132
RH		 2889 }
2890 }
2891 }
2892
b34976b6 2893 return TRUE;
252b5132
RH		 2894}
2895
2896/* This is a version of bfd_generic_get_relocated_section_contents
2897 which uses sh_relocate_section. */
2898
2899static bfd_byte *
2c3fc389
NC		 2900sh_coff_get_relocated_section_contents (bfd *output_bfd,
2901 struct bfd_link_info *link_info,
2902 struct bfd_link_order *link_order,
2903 bfd_byte *data,
2904 bfd_boolean relocatable,
2905 asymbol **symbols)
252b5132
RH		 2906{
2907 asection *input_section = link_order->u.indirect.section;
2908 bfd *input_bfd = input_section->owner;
2909 asection **sections = NULL;
2910 struct internal_reloc *internal_relocs = NULL;
2911 struct internal_syment *internal_syms = NULL;
2912
2913 /* We only need to handle the case of relaxing, or of having a
2914 particular set of section contents, specially. */
1049f94e 2915 if (relocatable
252b5132
RH		 2916 || coff_section_data (input_bfd, input_section) == NULL
2917 || coff_section_data (input_bfd, input_section)->contents == NULL)
2918 return bfd_generic_get_relocated_section_contents (output_bfd, link_info,
2919 link_order, data,
1049f94e 2920 relocatable,
252b5132
RH		 2921 symbols);
2922
2923 memcpy (data, coff_section_data (input_bfd, input_section)->contents,
eea6121a 2924 (size_t) input_section->size);
252b5132
RH		 2925
2926 if ((input_section->flags & SEC_RELOC) != 0
2927 && input_section->reloc_count > 0)
2928 {
2929 bfd_size_type symesz = bfd_coff_symesz (input_bfd);
2930 bfd_byte *esym, *esymend;
2931 struct internal_syment *isymp;
2932 asection **secpp;
dc810e39 2933 bfd_size_type amt;
252b5132
RH		 2934
2935 if (! _bfd_coff_get_external_symbols (input_bfd))
2936 goto error_return;
2937
2938 internal_relocs = (_bfd_coff_read_internal_relocs
b34976b6
AM		 2939 (input_bfd, input_section, FALSE, (bfd_byte *) NULL,
2940 FALSE, (struct internal_reloc *) NULL));
252b5132
RH		 2941 if (internal_relocs == NULL)
2942 goto error_return;
2943
dc810e39
AM		 2944 amt = obj_raw_syment_count (input_bfd);
2945 amt *= sizeof (struct internal_syment);
2946 internal_syms = (struct internal_syment *) bfd_malloc (amt);
252b5132
RH		 2947 if (internal_syms == NULL)
2948 goto error_return;
2949
dc810e39
AM		 2950 amt = obj_raw_syment_count (input_bfd);
2951 amt *= sizeof (asection *);
2952 sections = (asection **) bfd_malloc (amt);
252b5132
RH		 2953 if (sections == NULL)
2954 goto error_return;
2955
2956 isymp = internal_syms;
2957 secpp = sections;
2958 esym = (bfd_byte *) obj_coff_external_syms (input_bfd);
2959 esymend = esym + obj_raw_syment_count (input_bfd) * symesz;
2960 while (esym < esymend)
2961 {
2c3fc389 2962 bfd_coff_swap_sym_in (input_bfd, esym, isymp);
252b5132
RH		 2963
2964 if (isymp->n_scnum != 0)
2965 *secpp = coff_section_from_bfd_index (input_bfd, isymp->n_scnum);
2966 else
2967 {
2968 if (isymp->n_value == 0)
2969 *secpp = bfd_und_section_ptr;
2970 else
2971 *secpp = bfd_com_section_ptr;
2972 }
2973
2974 esym += (isymp->n_numaux + 1) * symesz;
2975 secpp += isymp->n_numaux + 1;
2976 isymp += isymp->n_numaux + 1;
2977 }
2978
2979 if (! sh_relocate_section (output_bfd, link_info, input_bfd,
2980 input_section, data, internal_relocs,
2981 internal_syms, sections))
2982 goto error_return;
2983
2984 free (sections);
2985 sections = NULL;
2986 free (internal_syms);
2987 internal_syms = NULL;
2988 free (internal_relocs);
2989 internal_relocs = NULL;
2990 }
2991
2992 return data;
2993
2994 error_return:
2995 if (internal_relocs != NULL)
2996 free (internal_relocs);
2997 if (internal_syms != NULL)
2998 free (internal_syms);
2999 if (sections != NULL)
3000 free (sections);
3001 return NULL;
3002}
3003
3004/* The target vectors. */
3005
17505c5c 3006#ifndef TARGET_SHL_SYM
6d00b590 3007CREATE_BIG_COFF_TARGET_VEC (sh_coff_vec, "coff-sh", BFD_IS_RELAXABLE, 0, '_', NULL, COFF_SWAP_TABLE)
17505c5c 3008#endif
252b5132 3009
c3c89269
NC		 3010#ifdef TARGET_SHL_SYM
3011#define TARGET_SYM TARGET_SHL_SYM
3012#else
6d00b590 3013#define TARGET_SYM sh_coff_le_vec
c3c89269 3014#endif
cbfe05c4 3015
c3c89269
NC		 3016#ifndef TARGET_SHL_NAME
3017#define TARGET_SHL_NAME "coff-shl"
3018#endif
252b5132 3019
17505c5c
NC		 3020#ifdef COFF_WITH_PE
3021CREATE_LITTLE_COFF_TARGET_VEC (TARGET_SYM, TARGET_SHL_NAME, BFD_IS_RELAXABLE,
3fa78519 3022 SEC_CODE | SEC_DATA, '_', NULL, COFF_SWAP_TABLE);
17505c5c 3023#else
86033394 3024CREATE_LITTLE_COFF_TARGET_VEC (TARGET_SYM, TARGET_SHL_NAME, BFD_IS_RELAXABLE,
3fa78519 3025 0, '_', NULL, COFF_SWAP_TABLE)
17505c5c 3026#endif
86033394 3027
17505c5c 3028#ifndef TARGET_SHL_SYM
2c3fc389 3029
252b5132
RH		 3030/* Some people want versions of the SH COFF target which do not align
3031 to 16 byte boundaries. We implement that by adding a couple of new
3032 target vectors. These are just like the ones above, but they
3033 change the default section alignment. To generate them in the
3034 assembler, use -small. To use them in the linker, use -b
3035 coff-sh{l}-small and -oformat coff-sh{l}-small.
3036
3037 Yes, this is a horrible hack. A general solution for setting
3038 section alignment in COFF is rather complex. ELF handles this
3039 correctly. */
3040
3041/* Only recognize the small versions if the target was not defaulted.
3042 Otherwise we won't recognize the non default endianness. */
3043
3044static const bfd_target *
2c3fc389 3045coff_small_object_p (bfd *abfd)
252b5132
RH		 3046{
3047 if (abfd->target_defaulted)
3048 {
3049 bfd_set_error (bfd_error_wrong_format);
3050 return NULL;
3051 }
3052 return coff_object_p (abfd);
3053}
3054
3055/* Set the section alignment for the small versions. */
3056
b34976b6 3057static bfd_boolean
2c3fc389 3058coff_small_new_section_hook (bfd *abfd, asection *section)
252b5132
RH		 3059{
3060 if (! coff_new_section_hook (abfd, section))
b34976b6 3061 return FALSE;
252b5132
RH		 3062
3063 /* We must align to at least a four byte boundary, because longword
3064 accesses must be on a four byte boundary. */
3065 if (section->alignment_power == COFF_DEFAULT_SECTION_ALIGNMENT_POWER)
3066 section->alignment_power = 2;
3067
b34976b6 3068 return TRUE;
252b5132
RH		 3069}
3070
3071/* This is copied from bfd_coff_std_swap_table so that we can change
3072 the default section alignment power. */
3073
88183869 3074static bfd_coff_backend_data bfd_coff_small_swap_table =
252b5132
RH		 3075{
3076 coff_swap_aux_in, coff_swap_sym_in, coff_swap_lineno_in,
3077 coff_swap_aux_out, coff_swap_sym_out,
3078 coff_swap_lineno_out, coff_swap_reloc_out,
3079 coff_swap_filehdr_out, coff_swap_aouthdr_out,
3080 coff_swap_scnhdr_out,
692b7d62 3081 FILHSZ, AOUTSZ, SCNHSZ, SYMESZ, AUXESZ, RELSZ, LINESZ, FILNMLEN,
252b5132 3082#ifdef COFF_LONG_FILENAMES
b34976b6 3083 TRUE,
252b5132 3084#else
b34976b6 3085 FALSE,
252b5132 3086#endif
88183869 3087 COFF_DEFAULT_LONG_SECTION_NAMES,
252b5132 3088 2,
ecefdb58 3089#ifdef COFF_FORCE_SYMBOLS_IN_STRINGS
b34976b6 3090 TRUE,
ecefdb58 3091#else
b34976b6 3092 FALSE,
ecefdb58
CP		 3093#endif
3094#ifdef COFF_DEBUG_STRING_WIDE_PREFIX
3095 4,
3096#else
3097 2,
3098#endif
167ad85b 3099 32768,
252b5132
RH		 3100 coff_swap_filehdr_in, coff_swap_aouthdr_in, coff_swap_scnhdr_in,
3101 coff_swap_reloc_in, coff_bad_format_hook, coff_set_arch_mach_hook,
3102 coff_mkobject_hook, styp_to_sec_flags, coff_set_alignment_hook,
3103 coff_slurp_symbol_table, symname_in_debug_hook, coff_pointerize_aux_hook,
3104 coff_print_aux, coff_reloc16_extra_cases, coff_reloc16_estimate,
5d54c628 3105 coff_classify_symbol, coff_compute_section_file_positions,
252b5132
RH		 3106 coff_start_final_link, coff_relocate_section, coff_rtype_to_howto,
3107 coff_adjust_symndx, coff_link_add_one_symbol,
2b5c217d
NC		 3108 coff_link_output_has_begun, coff_final_link_postscript,
3109 bfd_pe_print_pdata
252b5132
RH		 3110};
3111
3112#define coff_small_close_and_cleanup \
3113 coff_close_and_cleanup
3114#define coff_small_bfd_free_cached_info \
3115 coff_bfd_free_cached_info
3116#define coff_small_get_section_contents \
3117 coff_get_section_contents
3118#define coff_small_get_section_contents_in_window \
3119 coff_get_section_contents_in_window
3120
6d00b590 3121extern const bfd_target sh_coff_small_le_vec;
c3c89269 3122
6d00b590 3123const bfd_target sh_coff_small_vec =
252b5132
RH		 3124{
3125 "coff-sh-small", /* name */
3126 bfd_target_coff_flavour,
3127 BFD_ENDIAN_BIG, /* data byte order is big */
3128 BFD_ENDIAN_BIG, /* header byte order is big */
3129
3130 (HAS_RELOC | EXEC_P | /* object flags */
3131 HAS_LINENO | HAS_DEBUG |
3132 HAS_SYMS | HAS_LOCALS | WP_TEXT | BFD_IS_RELAXABLE),
3133
3134 (SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_RELOC),
3135 '_', /* leading symbol underscore */
3136 '/', /* ar_pad_char */
3137 15, /* ar_max_namelen */
0aabe54e 3138 0, /* match priority. */
252b5132
RH		 3139 bfd_getb64, bfd_getb_signed_64, bfd_putb64,
3140 bfd_getb32, bfd_getb_signed_32, bfd_putb32,
3141 bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* data */
3142 bfd_getb64, bfd_getb_signed_64, bfd_putb64,
3143 bfd_getb32, bfd_getb_signed_32, bfd_putb32,
3144 bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* hdrs */
3145
3146 {_bfd_dummy_target, coff_small_object_p, /* bfd_check_format */
3147 bfd_generic_archive_p, _bfd_dummy_target},
3148 {bfd_false, coff_mkobject, _bfd_generic_mkarchive, /* bfd_set_format */
3149 bfd_false},
3150 {bfd_false, coff_write_object_contents, /* bfd_write_contents */
3151 _bfd_write_archive_contents, bfd_false},
3152
3153 BFD_JUMP_TABLE_GENERIC (coff_small),
3154 BFD_JUMP_TABLE_COPY (coff),
3155 BFD_JUMP_TABLE_CORE (_bfd_nocore),
3156 BFD_JUMP_TABLE_ARCHIVE (_bfd_archive_coff),
3157 BFD_JUMP_TABLE_SYMBOLS (coff),
3158 BFD_JUMP_TABLE_RELOCS (coff),
3159 BFD_JUMP_TABLE_WRITE (coff),
3160 BFD_JUMP_TABLE_LINK (coff),
3161 BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic),
3162
6d00b590 3163 & sh_coff_small_le_vec,
cbfe05c4 3164
2c3fc389 3165 & bfd_coff_small_swap_table
252b5132
RH		 3166};
3167
6d00b590 3168const bfd_target sh_coff_small_le_vec =
252b5132
RH		 3169{
3170 "coff-shl-small", /* name */
3171 bfd_target_coff_flavour,
3172 BFD_ENDIAN_LITTLE, /* data byte order is little */
3173 BFD_ENDIAN_LITTLE, /* header byte order is little endian too*/
3174
3175 (HAS_RELOC | EXEC_P | /* object flags */
3176 HAS_LINENO | HAS_DEBUG |
3177 HAS_SYMS | HAS_LOCALS | WP_TEXT | BFD_IS_RELAXABLE),
3178
3179 (SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_RELOC),
3180 '_', /* leading symbol underscore */
3181 '/', /* ar_pad_char */
3182 15, /* ar_max_namelen */
0aabe54e 3183 0, /* match priority. */
252b5132
RH		 3184 bfd_getl64, bfd_getl_signed_64, bfd_putl64,
3185 bfd_getl32, bfd_getl_signed_32, bfd_putl32,
3186 bfd_getl16, bfd_getl_signed_16, bfd_putl16, /* data */
3187 bfd_getl64, bfd_getl_signed_64, bfd_putl64,
3188 bfd_getl32, bfd_getl_signed_32, bfd_putl32,
3189 bfd_getl16, bfd_getl_signed_16, bfd_putl16, /* hdrs */
3190
3191 {_bfd_dummy_target, coff_small_object_p, /* bfd_check_format */
cbfe05c4 3192 bfd_generic_archive_p, _bfd_dummy_target},
252b5132
RH		 3193 {bfd_false, coff_mkobject, _bfd_generic_mkarchive, /* bfd_set_format */
3194 bfd_false},
3195 {bfd_false, coff_write_object_contents, /* bfd_write_contents */
3196 _bfd_write_archive_contents, bfd_false},
3197
3198 BFD_JUMP_TABLE_GENERIC (coff_small),
3199 BFD_JUMP_TABLE_COPY (coff),
3200 BFD_JUMP_TABLE_CORE (_bfd_nocore),
3201 BFD_JUMP_TABLE_ARCHIVE (_bfd_archive_coff),
3202 BFD_JUMP_TABLE_SYMBOLS (coff),
3203 BFD_JUMP_TABLE_RELOCS (coff),
3204 BFD_JUMP_TABLE_WRITE (coff),
3205 BFD_JUMP_TABLE_LINK (coff),
3206 BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic),
3207
6d00b590 3208 & sh_coff_small_vec,
cbfe05c4 3209
2c3fc389 3210 & bfd_coff_small_swap_table
252b5132 3211};
17505c5c 3212#endif
GDB Binutils - Deliverables
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