[deliverable/binutils-gdb.git] / bfd / cpu-ia64-opc.c

/* Copyright 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
   Contributed by David Mosberger-Tang <davidm@hpl.hp.com>

This file is part of BFD, the Binary File Descriptor library.

This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */

/* Logically, this code should be part of libopcode but since some of
   the operand insertion/extraction functions help bfd to implement
   relocations, this code is included as part of cpu-ia64.c.  This
   avoids circular dependencies between libopcode and libbfd and also
   obviates the need for applications to link in libopcode when all
   they really want is libbfd.

   --davidm Mon Apr 13 22:14:02 1998 */

#include "../opcodes/ia64-opc.h"

#define NELEMS(a)  ((int) (sizeof (a) / sizeof ((a)[0])))

static const char*
ins_rsvd (const struct ia64_operand *self ATTRIBUTE_UNUSED,
	  ia64_insn value ATTRIBUTE_UNUSED, ia64_insn *code ATTRIBUTE_UNUSED)
{
  return "internal error---this shouldn't happen";
}

static const char*
ext_rsvd (const struct ia64_operand *self ATTRIBUTE_UNUSED,
	  ia64_insn code ATTRIBUTE_UNUSED, ia64_insn *valuep ATTRIBUTE_UNUSED)
{
  return "internal error---this shouldn't happen";
}

static const char*
ins_const (const struct ia64_operand *self ATTRIBUTE_UNUSED,
	   ia64_insn value ATTRIBUTE_UNUSED, ia64_insn *code ATTRIBUTE_UNUSED)
{
  return 0;
}

static const char*
ext_const (const struct ia64_operand *self ATTRIBUTE_UNUSED,
	   ia64_insn code ATTRIBUTE_UNUSED, ia64_insn *valuep ATTRIBUTE_UNUSED)
{
  return 0;
}

static const char*
ins_reg (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
{
  if (value >= 1u << self->field[0].bits)
    return "register number out of range";

  *code |= value << self->field[0].shift;
  return 0;
}

static const char*
ext_reg (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
{
  *valuep = ((code >> self->field[0].shift)
	     & ((1u << self->field[0].bits) - 1));
  return 0;
}

static const char*
ins_immu (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
{
  ia64_insn new = 0;
  int i;

  for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
    {
      new |= ((value & ((((ia64_insn) 1) << self->field[i].bits) - 1))
	      << self->field[i].shift);
      value >>= self->field[i].bits;
    }
  if (value)
    return "integer operand out of range";

  *code |= new;
  return 0;
}

static const char*
ext_immu (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
{
  BFD_HOST_U_64_BIT value = 0;
  int i, bits = 0, total = 0;

  for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
    {
      bits = self->field[i].bits;
      value |= ((code >> self->field[i].shift)
		& ((((BFD_HOST_U_64_BIT) 1) << bits) - 1)) << total;
      total += bits;
    }
  *valuep = value;
  return 0;
}

static const char*
ins_immus8 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
{
  if (value & 0x7)
    return "value not an integer multiple of 8";
  return ins_immu (self, value >> 3, code);
}

static const char*
ext_immus8 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
{
  const char *result;

  result = ext_immu (self, code, valuep);
  if (result)
    return result;

  *valuep = *valuep << 3;
  return 0;
}

static const char*
ins_imms_scaled (const struct ia64_operand *self, ia64_insn value,
		 ia64_insn *code, int scale)
{
  BFD_HOST_64_BIT svalue = value, sign_bit = 0;
  ia64_insn new = 0;
  int i;

  svalue >>= scale;

  for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
    {
      new |= ((svalue & ((((ia64_insn) 1) << self->field[i].bits) - 1))
	      << self->field[i].shift);
      sign_bit = (svalue >> (self->field[i].bits - 1)) & 1;
      svalue >>= self->field[i].bits;
    }
  if ((!sign_bit && svalue != 0) || (sign_bit && svalue != -1))
    return "integer operand out of range";

  *code |= new;
  return 0;
}

static const char*
ext_imms_scaled (const struct ia64_operand *self, ia64_insn code,
		 ia64_insn *valuep, int scale)
{
  int i, bits = 0, total = 0;
  BFD_HOST_64_BIT val = 0, sign;

  for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
    {
      bits = self->field[i].bits;
      val |= ((code >> self->field[i].shift)
	      & ((((BFD_HOST_U_64_BIT) 1) << bits) - 1)) << total;
      total += bits;
    }
  /* sign extend: */
  sign = (BFD_HOST_64_BIT) 1 << (total - 1);
  val = (val ^ sign) - sign;

  *valuep = (val << scale);
  return 0;
}

static const char*
ins_imms (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
{
  return ins_imms_scaled (self, value, code, 0);
}

static const char*
ins_immsu4 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
{
  value = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;

  return ins_imms_scaled (self, value, code, 0);
}

static const char*
ext_imms (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
{
  return ext_imms_scaled (self, code, valuep, 0);
}

static const char*
ins_immsm1 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
{
  --value;
  return ins_imms_scaled (self, value, code, 0);
}

static const char*
ins_immsm1u4 (const struct ia64_operand *self, ia64_insn value,
	      ia64_insn *code)
{
  value = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;

  --value;
  return ins_imms_scaled (self, value, code, 0);
}

static const char*
ext_immsm1 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
{
  const char *res = ext_imms_scaled (self, code, valuep, 0);

  ++*valuep;
  return res;
}

static const char*
ins_imms1 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
{
  return ins_imms_scaled (self, value, code, 1);
}

static const char*
ext_imms1 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
{
  return ext_imms_scaled (self, code, valuep, 1);
}

static const char*
ins_imms4 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
{
  return ins_imms_scaled (self, value, code, 4);
}

static const char*
ext_imms4 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
{
  return ext_imms_scaled (self, code, valuep, 4);
}

static const char*
ins_imms16 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
{
  return ins_imms_scaled (self, value, code, 16);
}

static const char*
ext_imms16 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
{
  return ext_imms_scaled (self, code, valuep, 16);
}

static const char*
ins_cimmu (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
{
  ia64_insn mask = (((ia64_insn) 1) << self->field[0].bits) - 1;
  return ins_immu (self, value ^ mask, code);
}

static const char*
ext_cimmu (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
{
  const char *result;
  ia64_insn mask;

  mask = (((ia64_insn) 1) << self->field[0].bits) - 1;
  result = ext_immu (self, code, valuep);
  if (!result)
    {
      mask = (((ia64_insn) 1) << self->field[0].bits) - 1;
      *valuep ^= mask;
    }
  return result;
}

static const char*
ins_cnt (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
{
  --value;
  if (value >= ((BFD_HOST_U_64_BIT) 1) << self->field[0].bits)
    return "count out of range";

  *code |= value << self->field[0].shift;
  return 0;
}

static const char*
ext_cnt (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
{
  *valuep = ((code >> self->field[0].shift)
	     & ((((BFD_HOST_U_64_BIT) 1) << self->field[0].bits) - 1)) + 1;
  return 0;
}

static const char*
ins_cnt2b (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
{
  --value;

  if (value > 2)
    return "count must be in range 1..3";

  *code |= value << self->field[0].shift;
  return 0;
}

static const char*
ext_cnt2b (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
{
  *valuep = ((code >> self->field[0].shift) & 0x3) + 1;
  return 0;
}

static const char*
ins_cnt2c (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
{
  switch (value)
    {
    case 0:	value = 0; break;
    case 7:	value = 1; break;
    case 15:	value = 2; break;
    case 16:	value = 3; break;
    default:	return "count must be 0, 7, 15, or 16";
    }
  *code |= value << self->field[0].shift;
  return 0;
}

static const char*
ext_cnt2c (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
{
  ia64_insn value;

  value = (code >> self->field[0].shift) & 0x3;
  switch (value)
    {
    case 0: value =  0; break;
    case 1: value =  7; break;
    case 2: value = 15; break;
    case 3: value = 16; break;
    }
  *valuep = value;
  return 0;
}

static const char*
ins_inc3 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
{
  BFD_HOST_64_BIT val = value;
  BFD_HOST_U_64_BIT sign = 0;

  if (val < 0)
    {
      sign = 0x4;
      value = -value;
    }
  switch (value)
    {
    case  1:	value = 3; break;
    case  4:	value = 2; break;
    case  8:	value = 1; break;
    case 16:	value = 0; break;
    default:	return "count must be +/- 1, 4, 8, or 16";
    }
  *code |= (sign | value) << self->field[0].shift;
  return 0;
}

static const char*
ext_inc3 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
{
  BFD_HOST_64_BIT val;
  int negate;

  val = (code >> self->field[0].shift) & 0x7;
  negate = val & 0x4;
  switch (val & 0x3)
    {
    case 0: val = 16; break;
    case 1: val =  8; break;
    case 2: val =  4; break;
    case 3: val =  1; break;
    }
  if (negate)
    val = -val;

  *valuep = val;
  return 0;
}

#define CST	IA64_OPND_CLASS_CST
#define REG	IA64_OPND_CLASS_REG
#define IND	IA64_OPND_CLASS_IND
#define ABS	IA64_OPND_CLASS_ABS
#define REL	IA64_OPND_CLASS_REL

#define SDEC	IA64_OPND_FLAG_DECIMAL_SIGNED
#define UDEC	IA64_OPND_FLAG_DECIMAL_UNSIGNED

const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT] =
  {
    /* constants: */
    { CST, ins_const, ext_const, "NIL",		{{ 0, 0}}, 0, "<none>" },
    { CST, ins_const, ext_const, "ar.csd",	{{ 0, 0}}, 0, "ar.csd" },
    { CST, ins_const, ext_const, "ar.ccv",	{{ 0, 0}}, 0, "ar.ccv" },
    { CST, ins_const, ext_const, "ar.pfs",	{{ 0, 0}}, 0, "ar.pfs" },
    { CST, ins_const, ext_const, "1",		{{ 0, 0}}, 0, "1" },
    { CST, ins_const, ext_const, "8",		{{ 0, 0}}, 0, "8" },
    { CST, ins_const, ext_const, "16",		{{ 0, 0}}, 0, "16" },
    { CST, ins_const, ext_const, "r0",		{{ 0, 0}}, 0, "r0" },
    { CST, ins_const, ext_const, "ip",		{{ 0, 0}}, 0, "ip" },
    { CST, ins_const, ext_const, "pr",		{{ 0, 0}}, 0, "pr" },
    { CST, ins_const, ext_const, "pr.rot",	{{ 0, 0}}, 0, "pr.rot" },
    { CST, ins_const, ext_const, "psr",		{{ 0, 0}}, 0, "psr" },
    { CST, ins_const, ext_const, "psr.l",	{{ 0, 0}}, 0, "psr.l" },
    { CST, ins_const, ext_const, "psr.um",	{{ 0, 0}}, 0, "psr.um" },

    /* register operands: */
    { REG, ins_reg,   ext_reg,	"ar", {{ 7, 20}}, 0,		/* AR3 */
      "an application register" },
    { REG, ins_reg,   ext_reg,	 "b", {{ 3,  6}}, 0,		/* B1 */
      "a branch register" },
    { REG, ins_reg,   ext_reg,	 "b", {{ 3, 13}}, 0,		/* B2 */
      "a branch register"},
    { REG, ins_reg,   ext_reg,	"cr", {{ 7, 20}}, 0,		/* CR */
      "a control register"},
    { REG, ins_reg,   ext_reg,	 "f", {{ 7,  6}}, 0,		/* F1 */
      "a floating-point register" },
    { REG, ins_reg,   ext_reg,	 "f", {{ 7, 13}}, 0,		/* F2 */
      "a floating-point register" },
    { REG, ins_reg,   ext_reg,	 "f", {{ 7, 20}}, 0,		/* F3 */
      "a floating-point register" },
    { REG, ins_reg,   ext_reg,	 "f", {{ 7, 27}}, 0,		/* F4 */
      "a floating-point register" },
    { REG, ins_reg,   ext_reg,	 "p", {{ 6,  6}}, 0,		/* P1 */
      "a predicate register" },
    { REG, ins_reg,   ext_reg,	 "p", {{ 6, 27}}, 0,		/* P2 */
      "a predicate register" },
    { REG, ins_reg,   ext_reg,	 "r", {{ 7,  6}}, 0,		/* R1 */
      "a general register" },
    { REG, ins_reg,   ext_reg,	 "r", {{ 7, 13}}, 0,		/* R2 */
      "a general register" },
    { REG, ins_reg,   ext_reg,	 "r", {{ 7, 20}}, 0,		/* R3 */
      "a general register" },
    { REG, ins_reg,   ext_reg,	 "r", {{ 2, 20}}, 0,		/* R3_2 */
      "a general register r0-r3" },

    /* indirect operands: */
    { IND, ins_reg,   ext_reg,	"cpuid", {{7, 20}}, 0,		/* CPUID_R3 */
      "a cpuid register" },
    { IND, ins_reg,   ext_reg,	"dbr",   {{7, 20}}, 0,		/* DBR_R3 */
      "a dbr register" },
    { IND, ins_reg,   ext_reg,	"dtr",   {{7, 20}}, 0,		/* DTR_R3 */
      "a dtr register" },
    { IND, ins_reg,   ext_reg,	"itr",   {{7, 20}}, 0,		/* ITR_R3 */
      "an itr register" },
    { IND, ins_reg,   ext_reg,	"ibr",   {{7, 20}}, 0,		/* IBR_R3 */
      "an ibr register" },
    { IND, ins_reg,   ext_reg,	"",      {{7, 20}}, 0,		/* MR3 */
      "an indirect memory address" },
    { IND, ins_reg,   ext_reg,	"msr",   {{7, 20}}, 0,		/* MSR_R3 */
      "an msr register" },
    { IND, ins_reg,   ext_reg,	"pkr",   {{7, 20}}, 0,		/* PKR_R3 */
      "a pkr register" },
    { IND, ins_reg,   ext_reg,	"pmc",   {{7, 20}}, 0,		/* PMC_R3 */
      "a pmc register" },
    { IND, ins_reg,   ext_reg,	"pmd",   {{7, 20}}, 0,		/* PMD_R3 */
      "a pmd register" },
    { IND, ins_reg,   ext_reg,	"rr",    {{7, 20}}, 0,		/* RR_R3 */
      "an rr register" },

    /* immediate operands: */
    { ABS, ins_cimmu, ext_cimmu, 0, {{ 5, 20 }}, UDEC,		/* CCNT5 */
      "a 5-bit count (0-31)" },
    { ABS, ins_cnt,   ext_cnt,   0, {{ 2, 27 }}, UDEC,		/* CNT2a */
      "a 2-bit count (1-4)" },
    { ABS, ins_cnt2b, ext_cnt2b, 0, {{ 2, 27 }}, UDEC,		/* CNT2b */
      "a 2-bit count (1-3)" },
    { ABS, ins_cnt2c, ext_cnt2c, 0, {{ 2, 30 }}, UDEC,		/* CNT2c */
      "a count (0, 7, 15, or 16)" },
    { ABS, ins_immu,  ext_immu,  0, {{ 5, 14}}, UDEC,		/* CNT5 */
      "a 5-bit count (0-31)" },
    { ABS, ins_immu,  ext_immu,  0, {{ 6, 27}}, UDEC,		/* CNT6 */
      "a 6-bit count (0-63)" },
    { ABS, ins_cimmu, ext_cimmu, 0, {{ 6, 20}}, UDEC,		/* CPOS6a */
      "a 6-bit bit pos (0-63)" },
    { ABS, ins_cimmu, ext_cimmu, 0, {{ 6, 14}}, UDEC,		/* CPOS6b */
      "a 6-bit bit pos (0-63)" },
    { ABS, ins_cimmu, ext_cimmu, 0, {{ 6, 31}}, UDEC,		/* CPOS6c */
      "a 6-bit bit pos (0-63)" },
    { ABS, ins_imms,  ext_imms,  0, {{ 1, 36}}, SDEC,		/* IMM1 */
      "a 1-bit integer (-1, 0)" },
    { ABS, ins_immu,  ext_immu,  0, {{ 2, 13}}, UDEC,		/* IMMU2 */
      "a 2-bit unsigned (0-3)" },
    { ABS, ins_immu,  ext_immu,  0, {{ 7, 13}}, 0,		/* IMMU7a */
      "a 7-bit unsigned (0-127)" },
    { ABS, ins_immu,  ext_immu,  0, {{ 7, 20}}, 0,		/* IMMU7b */
      "a 7-bit unsigned (0-127)" },
    { ABS, ins_immu,  ext_immu,  0, {{ 7, 13}}, UDEC,		/* SOF */
      "a frame size (register count)" },
    { ABS, ins_immu,  ext_immu,  0, {{ 7, 20}}, UDEC,		/* SOL */
      "a local register count" },
    { ABS, ins_immus8,ext_immus8,0, {{ 4, 27}}, UDEC,		/* SOR */
      "a rotating register count (integer multiple of 8)" },
    { ABS, ins_imms,  ext_imms,  0,				/* IMM8 */
      {{ 7, 13}, { 1, 36}}, SDEC,
      "an 8-bit integer (-128-127)" },
    { ABS, ins_immsu4,  ext_imms,  0,				/* IMM8U4 */
      {{ 7, 13}, { 1, 36}}, SDEC,
      "an 8-bit signed integer for 32-bit unsigned compare (-128-127)" },
    { ABS, ins_immsm1,  ext_immsm1,  0,				/* IMM8M1 */
      {{ 7, 13}, { 1, 36}}, SDEC,
      "an 8-bit integer (-127-128)" },
    { ABS, ins_immsm1u4,  ext_immsm1,  0,			/* IMM8M1U4 */
      {{ 7, 13}, { 1, 36}}, SDEC,
      "an 8-bit integer for 32-bit unsigned compare (-127-(-1),1-128,0x100000000)" },
    { ABS, ins_immsm1,  ext_immsm1,  0,				/* IMM8M1U8 */
      {{ 7, 13}, { 1, 36}}, SDEC,
      "an 8-bit integer for 64-bit unsigned compare (-127-(-1),1-128,0x10000000000000000)" },
    { ABS, ins_immu,  ext_immu,  0, {{ 2, 33}, { 7, 20}}, 0,	/* IMMU9 */
      "a 9-bit unsigned (0-511)" },
    { ABS, ins_imms,  ext_imms,  0,				/* IMM9a */
      {{ 7,  6}, { 1, 27}, { 1, 36}}, SDEC,
      "a 9-bit integer (-256-255)" },
    { ABS, ins_imms,  ext_imms, 0,				/* IMM9b */
      {{ 7, 13}, { 1, 27}, { 1, 36}}, SDEC,
      "a 9-bit integer (-256-255)" },
    { ABS, ins_imms,  ext_imms, 0,				/* IMM14 */
      {{ 7, 13}, { 6, 27}, { 1, 36}}, SDEC,
      "a 14-bit integer (-8192-8191)" },
    { ABS, ins_imms1, ext_imms1, 0,				/* IMM17 */
      {{ 7,  6}, { 8, 24}, { 1, 36}}, 0,
      "a 17-bit integer (-65536-65535)" },
    { ABS, ins_immu,  ext_immu,  0, {{20,  6}, { 1, 36}}, 0,	/* IMMU21 */
      "a 21-bit unsigned" },
    { ABS, ins_imms,  ext_imms,  0,				/* IMM22 */
      {{ 7, 13}, { 9, 27}, { 5, 22}, { 1, 36}}, SDEC,
      "a 22-bit signed integer" },
    { ABS, ins_immu,  ext_immu,  0,				/* IMMU24 */
      {{21,  6}, { 2, 31}, { 1, 36}}, 0,
      "a 24-bit unsigned" },
    { ABS, ins_imms16,ext_imms16,0, {{27,  6}, { 1, 36}}, 0,	/* IMM44 */
      "a 44-bit unsigned (least 16 bits ignored/zeroes)" },
    { ABS, ins_rsvd,  ext_rsvd,	0, {{0,  0}}, 0,		/* IMMU62 */
      "a 62-bit unsigned" },
    { ABS, ins_rsvd,  ext_rsvd,	0, {{0,  0}}, 0,		/* IMMU64 */
      "a 64-bit unsigned" },
    { ABS, ins_inc3,  ext_inc3,  0, {{ 3, 13}}, SDEC,		/* INC3 */
      "an increment (+/- 1, 4, 8, or 16)" },
    { ABS, ins_cnt,   ext_cnt,   0, {{ 4, 27}}, UDEC,		/* LEN4 */
      "a 4-bit length (1-16)" },
    { ABS, ins_cnt,   ext_cnt,   0, {{ 6, 27}}, UDEC,		/* LEN6 */
      "a 6-bit length (1-64)" },
    { ABS, ins_immu,  ext_immu,  0, {{ 4, 20}},	0,		/* MBTYPE4 */
      "a mix type (@rev, @mix, @shuf, @alt, or @brcst)" },
    { ABS, ins_immu,  ext_immu,  0, {{ 8, 20}},	0,		/* MBTYPE8 */
      "an 8-bit mix type" },
    { ABS, ins_immu,  ext_immu,  0, {{ 6, 14}}, UDEC,		/* POS6 */
      "a 6-bit bit pos (0-63)" },
    { REL, ins_imms4, ext_imms4, 0, {{ 7,  6}, { 2, 33}}, 0,	/* TAG13 */
      "a branch tag" },
    { REL, ins_imms4, ext_imms4, 0, {{ 9, 24}}, 0,		/* TAG13b */
      "a branch tag" },
    { REL, ins_imms4, ext_imms4, 0, {{20,  6}, { 1, 36}}, 0,	/* TGT25 */
      "a branch target" },
    { REL, ins_imms4, ext_imms4, 0,				/* TGT25b */
      {{ 7,  6}, {13, 20}, { 1, 36}}, 0,
      "a branch target" },
    { REL, ins_imms4, ext_imms4, 0, {{20, 13}, { 1, 36}}, 0,	/* TGT25c */
      "a branch target" },
    { REL, ins_rsvd, ext_rsvd, 0, {{0, 0}}, 0,                  /* TGT64  */
      "a branch target" },

    { ABS, ins_const, ext_const, 0, {{0, 0}}, 0,		/* LDXMOV */
      "ldxmov target" },
  };
Commit	Line	Data
7898deda	1	/* Copyright 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
800eeca4 JW	2	Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
	3
	4	This file is part of BFD, the Binary File Descriptor library.
	5
	6	This program is free software; you can redistribute it and/or modify
	7	it under the terms of the GNU General Public License as published by
	8	the Free Software Foundation; either version 2 of the License, or
	9	(at your option) any later version.
	10
	11	This program is distributed in the hope that it will be useful,
	12	but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	GNU General Public License for more details.
	15
	16	You should have received a copy of the GNU General Public License
	17	along with this program; if not, write to the Free Software
	18	Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
	19
800eeca4 JW	20	/* Logically, this code should be part of libopcode but since some of
800eeca4 JW	21	the operand insertion/extraction functions help bfd to implement
dc810e39	22	relocations, this code is included as part of cpu-ia64.c. This
800eeca4 JW	23	avoids circular dependencies between libopcode and libbfd and also
	24	obviates the need for applications to link in libopcode when all
	25	they really want is libbfd.
	26
	27	--davidm Mon Apr 13 22:14:02 1998 */
	28
	29	#include "../opcodes/ia64-opc.h"
	30
	31	#define NELEMS(a) ((int) (sizeof (a) / sizeof ((a)[0])))
	32
	33	static const char*
64bf6ae6 JW	34	ins_rsvd (const struct ia64_operand *self ATTRIBUTE_UNUSED,
64bf6ae6 JW	35	ia64_insn value ATTRIBUTE_UNUSED, ia64_insn *code ATTRIBUTE_UNUSED)
800eeca4 JW	36	{
	37	return "internal error---this shouldn't happen";
	38	}
	39
	40	static const char*
64bf6ae6 JW	41	ext_rsvd (const struct ia64_operand *self ATTRIBUTE_UNUSED,
64bf6ae6 JW	42	ia64_insn code ATTRIBUTE_UNUSED, ia64_insn *valuep ATTRIBUTE_UNUSED)
800eeca4 JW	43	{
	44	return "internal error---this shouldn't happen";
	45	}
	46
	47	static const char*
64bf6ae6 JW	48	ins_const (const struct ia64_operand *self ATTRIBUTE_UNUSED,
64bf6ae6 JW	49	ia64_insn value ATTRIBUTE_UNUSED, ia64_insn *code ATTRIBUTE_UNUSED)
800eeca4 JW	50	{
	51	return 0;
	52	}
	53
	54	static const char*
64bf6ae6 JW	55	ext_const (const struct ia64_operand *self ATTRIBUTE_UNUSED,
64bf6ae6 JW	56	ia64_insn code ATTRIBUTE_UNUSED, ia64_insn *valuep ATTRIBUTE_UNUSED)
800eeca4 JW	57	{
	58	return 0;
	59	}
	60
	61	static const char*
	62	ins_reg (const struct ia64_operand self, ia64_insn value, ia64_insn code)
	63	{
	64	if (value >= 1u << self->field[0].bits)
	65	return "register number out of range";
	66
	67	*code \|= value << self->field[0].shift;
	68	return 0;
	69	}
	70
	71	static const char*
	72	ext_reg (const struct ia64_operand self, ia64_insn code, ia64_insn valuep)
	73	{
	74	*valuep = ((code >> self->field[0].shift)
	75	& ((1u << self->field[0].bits) - 1));
	76	return 0;
	77	}
	78
	79	static const char*
	80	ins_immu (const struct ia64_operand self, ia64_insn value, ia64_insn code)
	81	{
	82	ia64_insn new = 0;
	83	int i;
	84
	85	for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
	86	{
	87	new \|= ((value & ((((ia64_insn) 1) << self->field[i].bits) - 1))
	88	<< self->field[i].shift);
	89	value >>= self->field[i].bits;
	90	}
	91	if (value)
	92	return "integer operand out of range";
	93
	94	*code \|= new;
	95	return 0;
	96	}
	97
	98	static const char*
	99	ext_immu (const struct ia64_operand self, ia64_insn code, ia64_insn valuep)
	100	{
	101	BFD_HOST_U_64_BIT value = 0;
	102	int i, bits = 0, total = 0;
	103
	104	for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
	105	{
	106	bits = self->field[i].bits;
	107	value \|= ((code >> self->field[i].shift)
	108	& ((((BFD_HOST_U_64_BIT) 1) << bits) - 1)) << total;
	109	total += bits;
	110	}
	111	*valuep = value;
	112	return 0;
	113	}
	114
	115	static const char*
	116	ins_immus8 (const struct ia64_operand self, ia64_insn value, ia64_insn code)
	117	{
	118	if (value & 0x7)
	119	return "value not an integer multiple of 8";
	120	return ins_immu (self, value >> 3, code);
121	}
122
123	static const char*
124	ext_immus8 (const struct ia64_operand self, ia64_insn code, ia64_insn valuep)
125	{
126	const char *result;
127
128	result = ext_immu (self, code, valuep);
129	if (result)
130	return result;
131
132	valuep = valuep << 3;
133	return 0;
134	}
135
136	static const char*
137	ins_imms_scaled (const struct ia64_operand *self, ia64_insn value,
138	ia64_insn *code, int scale)
139	{
64bf6ae6	140	BFD_HOST_64_BIT svalue = value, sign_bit = 0;
800eeca4 JW	141	ia64_insn new = 0;
	142	int i;
	143
	144	svalue >>= scale;
	145
	146	for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
	147	{
	148	new \|= ((svalue & ((((ia64_insn) 1) << self->field[i].bits) - 1))
	149	<< self->field[i].shift);
	150	sign_bit = (svalue >> (self->field[i].bits - 1)) & 1;
	151	svalue >>= self->field[i].bits;
	152	}
	153	if ((!sign_bit && svalue != 0) \|\| (sign_bit && svalue != -1))
	154	return "integer operand out of range";
	155
	156	*code \|= new;
	157	return 0;
	158	}
	159
	160	static const char*
	161	ext_imms_scaled (const struct ia64_operand *self, ia64_insn code,
	162	ia64_insn *valuep, int scale)
	163	{
113202d6 AM	164	int i, bits = 0, total = 0;
113202d6 AM	165	BFD_HOST_64_BIT val = 0, sign;
800eeca4 JW	166
	167	for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
	168	{
	169	bits = self->field[i].bits;
	170	val \|= ((code >> self->field[i].shift)
	171	& ((((BFD_HOST_U_64_BIT) 1) << bits) - 1)) << total;
	172	total += bits;
	173	}
	174	/* sign extend: */
113202d6 AM	175	sign = (BFD_HOST_64_BIT) 1 << (total - 1);
113202d6 AM	176	val = (val ^ sign) - sign;
800eeca4 JW	177
	178	*valuep = (val << scale);
	179	return 0;
	180	}
	181
	182	static const char*
	183	ins_imms (const struct ia64_operand self, ia64_insn value, ia64_insn code)
	184	{
	185	return ins_imms_scaled (self, value, code, 0);
	186	}
	187
	188	static const char*
	189	ins_immsu4 (const struct ia64_operand self, ia64_insn value, ia64_insn code)
	190	{
113202d6	191	value = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
800eeca4 JW	192
	193	return ins_imms_scaled (self, value, code, 0);
	194	}
	195
	196	static const char*
	197	ext_imms (const struct ia64_operand self, ia64_insn code, ia64_insn valuep)
	198	{
	199	return ext_imms_scaled (self, code, valuep, 0);
	200	}
	201
	202	static const char*
	203	ins_immsm1 (const struct ia64_operand self, ia64_insn value, ia64_insn code)
	204	{
	205	--value;
	206	return ins_imms_scaled (self, value, code, 0);
	207	}
	208
	209	static const char*
	210	ins_immsm1u4 (const struct ia64_operand *self, ia64_insn value,
	211	ia64_insn *code)
	212	{
113202d6	213	value = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
800eeca4 JW	214
	215	--value;
	216	return ins_imms_scaled (self, value, code, 0);
	217	}
	218
	219	static const char*
	220	ext_immsm1 (const struct ia64_operand self, ia64_insn code, ia64_insn valuep)
	221	{
	222	const char *res = ext_imms_scaled (self, code, valuep, 0);
	223
	224	++*valuep;
	225	return res;
	226	}
	227
	228	static const char*
	229	ins_imms1 (const struct ia64_operand self, ia64_insn value, ia64_insn code)
	230	{
	231	return ins_imms_scaled (self, value, code, 1);
	232	}
	233
	234	static const char*
	235	ext_imms1 (const struct ia64_operand self, ia64_insn code, ia64_insn valuep)
	236	{
	237	return ext_imms_scaled (self, code, valuep, 1);
	238	}
	239
	240	static const char*
	241	ins_imms4 (const struct ia64_operand self, ia64_insn value, ia64_insn code)
	242	{
	243	return ins_imms_scaled (self, value, code, 4);
	244	}
	245
	246	static const char*
	247	ext_imms4 (const struct ia64_operand self, ia64_insn code, ia64_insn valuep)
	248	{
	249	return ext_imms_scaled (self, code, valuep, 4);
	250	}
	251
	252	static const char*
	253	ins_imms16 (const struct ia64_operand self, ia64_insn value, ia64_insn code)
	254	{
	255	return ins_imms_scaled (self, value, code, 16);
	256	}
	257
	258	static const char*
	259	ext_imms16 (const struct ia64_operand self, ia64_insn code, ia64_insn valuep)
	260	{
	261	return ext_imms_scaled (self, code, valuep, 16);
	262	}
	263
	264	static const char*
	265	ins_cimmu (const struct ia64_operand self, ia64_insn value, ia64_insn code)
	266	{
	267	ia64_insn mask = (((ia64_insn) 1) << self->field[0].bits) - 1;
	268	return ins_immu (self, value ^ mask, code);
	269	}
	270
	271	static const char*
	272	ext_cimmu (const struct ia64_operand self, ia64_insn code, ia64_insn valuep)
	273	{
	274	const char *result;
	275	ia64_insn mask;
	276
	277	mask = (((ia64_insn) 1) << self->field[0].bits) - 1;
278	result = ext_immu (self, code, valuep);
279	if (!result)
280	{
281	mask = (((ia64_insn) 1) << self->field[0].bits) - 1;
282	*valuep ^= mask;
283	}
284	return result;
285	}
286
287	static const char*
288	ins_cnt (const struct ia64_operand self, ia64_insn value, ia64_insn code)
289	{
290	--value;
291	if (value >= ((BFD_HOST_U_64_BIT) 1) << self->field[0].bits)
292	return "count out of range";
293
294	*code \|= value << self->field[0].shift;
295	return 0;
296	}
297
298	static const char*
299	ext_cnt (const struct ia64_operand self, ia64_insn code, ia64_insn valuep)
300	{
301	*valuep = ((code >> self->field[0].shift)
302	& ((((BFD_HOST_U_64_BIT) 1) << self->field[0].bits) - 1)) + 1;
303	return 0;
304	}
305
306	static const char*
307	ins_cnt2b (const struct ia64_operand self, ia64_insn value, ia64_insn code)
308	{
309	--value;
310
311	if (value > 2)
312	return "count must be in range 1..3";
313
314	*code \|= value << self->field[0].shift;
315	return 0;
316	}
317
318	static const char*
319	ext_cnt2b (const struct ia64_operand self, ia64_insn code, ia64_insn valuep)
320	{
321	*valuep = ((code >> self->field[0].shift) & 0x3) + 1;
322	return 0;
323	}
324
325	static const char*
326	ins_cnt2c (const struct ia64_operand self, ia64_insn value, ia64_insn code)
327	{
328	switch (value)
329	{
330	case 0: value = 0; break;
331	case 7: value = 1; break;
332	case 15: value = 2; break;
333	case 16: value = 3; break;
334	default: return "count must be 0, 7, 15, or 16";
335	}
336	*code \|= value << self->field[0].shift;
337	return 0;
338	}
339
340	static const char*
341	ext_cnt2c (const struct ia64_operand self, ia64_insn code, ia64_insn valuep)
342	{
343	ia64_insn value;
344
345	value = (code >> self->field[0].shift) & 0x3;
346	switch (value)
347	{
348	case 0: value = 0; break;
349	case 1: value = 7; break;
350	case 2: value = 15; break;
351	case 3: value = 16; break;
352	}
353	*valuep = value;
354	return 0;
355	}
356
357	static const char*
358	ins_inc3 (const struct ia64_operand self, ia64_insn value, ia64_insn code)
359	{
360	BFD_HOST_64_BIT val = value;
361	BFD_HOST_U_64_BIT sign = 0;
362
363	if (val < 0)
364	{
365	sign = 0x4;
366	value = -value;
367	}
368	switch (value)
369	{
370	case 1: value = 3; break;
371	case 4: value = 2; break;
372	case 8: value = 1; break;
373	case 16: value = 0; break;
374	default: return "count must be +/- 1, 4, 8, or 16";
375	}
376	*code \|= (sign \| value) << self->field[0].shift;
377	return 0;
378	}
379
380	static const char*
381	ext_inc3 (const struct ia64_operand self, ia64_insn code, ia64_insn valuep)
382	{
383	BFD_HOST_64_BIT val;
384	int negate;
385
386	val = (code >> self->field[0].shift) & 0x7;
387	negate = val & 0x4;
388	switch (val & 0x3)
389	{
390	case 0: val = 16; break;
391	case 1: val = 8; break;
392	case 2: val = 4; break;
393	case 3: val = 1; break;
394	}
395	if (negate)
396	val = -val;
397
398	*valuep = val;
399	return 0;
400	}
401
402	#define CST IA64_OPND_CLASS_CST
403	#define REG IA64_OPND_CLASS_REG
404	#define IND IA64_OPND_CLASS_IND
405	#define ABS IA64_OPND_CLASS_ABS
406	#define REL IA64_OPND_CLASS_REL
407
408	#define SDEC IA64_OPND_FLAG_DECIMAL_SIGNED
409	#define UDEC IA64_OPND_FLAG_DECIMAL_UNSIGNED
410
411	const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT] =
412	{
413	/* constants: */
64bf6ae6	414	{ CST, ins_const, ext_const, "NIL", {{ 0, 0}}, 0, "<none>" },
c10d9d8f	415	{ CST, ins_const, ext_const, "ar.csd", {{ 0, 0}}, 0, "ar.csd" },
64bf6ae6 JW	416	{ CST, ins_const, ext_const, "ar.ccv", {{ 0, 0}}, 0, "ar.ccv" },
	417	{ CST, ins_const, ext_const, "ar.pfs", {{ 0, 0}}, 0, "ar.pfs" },
	418	{ CST, ins_const, ext_const, "1", {{ 0, 0}}, 0, "1" },
87f8eb97	419	{ CST, ins_const, ext_const, "8", {{ 0, 0}}, 0, "8" },
64bf6ae6 JW	420	{ CST, ins_const, ext_const, "16", {{ 0, 0}}, 0, "16" },
	421	{ CST, ins_const, ext_const, "r0", {{ 0, 0}}, 0, "r0" },
	422	{ CST, ins_const, ext_const, "ip", {{ 0, 0}}, 0, "ip" },
	423	{ CST, ins_const, ext_const, "pr", {{ 0, 0}}, 0, "pr" },
	424	{ CST, ins_const, ext_const, "pr.rot", {{ 0, 0}}, 0, "pr.rot" },
	425	{ CST, ins_const, ext_const, "psr", {{ 0, 0}}, 0, "psr" },
	426	{ CST, ins_const, ext_const, "psr.l", {{ 0, 0}}, 0, "psr.l" },
	427	{ CST, ins_const, ext_const, "psr.um", {{ 0, 0}}, 0, "psr.um" },
800eeca4 JW	428
	429	/* register operands: */
	430	{ REG, ins_reg, ext_reg, "ar", {{ 7, 20}}, 0, /* AR3 */
	431	"an application register" },
	432	{ REG, ins_reg, ext_reg, "b", {{ 3, 6}}, 0, /* B1 */
	433	"a branch register" },
	434	{ REG, ins_reg, ext_reg, "b", {{ 3, 13}}, 0, /* B2 */
	435	"a branch register"},
	436	{ REG, ins_reg, ext_reg, "cr", {{ 7, 20}}, 0, /* CR */
	437	"a control register"},
	438	{ REG, ins_reg, ext_reg, "f", {{ 7, 6}}, 0, /* F1 */
	439	"a floating-point register" },
	440	{ REG, ins_reg, ext_reg, "f", {{ 7, 13}}, 0, /* F2 */
	441	"a floating-point register" },
	442	{ REG, ins_reg, ext_reg, "f", {{ 7, 20}}, 0, /* F3 */
	443	"a floating-point register" },
	444	{ REG, ins_reg, ext_reg, "f", {{ 7, 27}}, 0, /* F4 */
	445	"a floating-point register" },
	446	{ REG, ins_reg, ext_reg, "p", {{ 6, 6}}, 0, /* P1 */
	447	"a predicate register" },
	448	{ REG, ins_reg, ext_reg, "p", {{ 6, 27}}, 0, /* P2 */
	449	"a predicate register" },
	450	{ REG, ins_reg, ext_reg, "r", {{ 7, 6}}, 0, /* R1 */
	451	"a general register" },
	452	{ REG, ins_reg, ext_reg, "r", {{ 7, 13}}, 0, /* R2 */
	453	"a general register" },
	454	{ REG, ins_reg, ext_reg, "r", {{ 7, 20}}, 0, /* R3 */
	455	"a general register" },
	456	{ REG, ins_reg, ext_reg, "r", {{ 2, 20}}, 0, /* R3_2 */
	457	"a general register r0-r3" },
	458
	459	/* indirect operands: */
	460	{ IND, ins_reg, ext_reg, "cpuid", {{7, 20}}, 0, /* CPUID_R3 */
	461	"a cpuid register" },
	462	{ IND, ins_reg, ext_reg, "dbr", {{7, 20}}, 0, /* DBR_R3 */
	463	"a dbr register" },
	464	{ IND, ins_reg, ext_reg, "dtr", {{7, 20}}, 0, /* DTR_R3 */
	465	"a dtr register" },
	466	{ IND, ins_reg, ext_reg, "itr", {{7, 20}}, 0, /* ITR_R3 */
	467	"an itr register" },
	468	{ IND, ins_reg, ext_reg, "ibr", {{7, 20}}, 0, /* IBR_R3 */
	469	"an ibr register" },
	470	{ IND, ins_reg, ext_reg, "", {{7, 20}}, 0, /* MR3 */
	471	"an indirect memory address" },
	472	{ IND, ins_reg, ext_reg, "msr", {{7, 20}}, 0, /* MSR_R3 */
	473	"an msr register" },
	474	{ IND, ins_reg, ext_reg, "pkr", {{7, 20}}, 0, /* PKR_R3 */
	475	"a pkr register" },
	476	{ IND, ins_reg, ext_reg, "pmc", {{7, 20}}, 0, /* PMC_R3 */
	477	"a pmc register" },
	478	{ IND, ins_reg, ext_reg, "pmd", {{7, 20}}, 0, /* PMD_R3 */
	479	"a pmd register" },
	480	{ IND, ins_reg, ext_reg, "rr", {{7, 20}}, 0, /* RR_R3 */
	481	"an rr register" },
	482
	483	/* immediate operands: */
	484	{ ABS, ins_cimmu, ext_cimmu, 0, {{ 5, 20 }}, UDEC, /* CCNT5 */
	485	"a 5-bit count (0-31)" },
	486	{ ABS, ins_cnt, ext_cnt, 0, {{ 2, 27 }}, UDEC, /* CNT2a */
	487	"a 2-bit count (1-4)" },
	488	{ ABS, ins_cnt2b, ext_cnt2b, 0, {{ 2, 27 }}, UDEC, /* CNT2b */
	489	"a 2-bit count (1-3)" },
	490	{ ABS, ins_cnt2c, ext_cnt2c, 0, {{ 2, 30 }}, UDEC, /* CNT2c */
	491	"a count (0, 7, 15, or 16)" },
492	{ ABS, ins_immu, ext_immu, 0, {{ 5, 14}}, UDEC, /* CNT5 */
493	"a 5-bit count (0-31)" },
494	{ ABS, ins_immu, ext_immu, 0, {{ 6, 27}}, UDEC, /* CNT6 */
495	"a 6-bit count (0-63)" },
496	{ ABS, ins_cimmu, ext_cimmu, 0, {{ 6, 20}}, UDEC, /* CPOS6a */
497	"a 6-bit bit pos (0-63)" },
498	{ ABS, ins_cimmu, ext_cimmu, 0, {{ 6, 14}}, UDEC, /* CPOS6b */
499	"a 6-bit bit pos (0-63)" },
500	{ ABS, ins_cimmu, ext_cimmu, 0, {{ 6, 31}}, UDEC, /* CPOS6c */
501	"a 6-bit bit pos (0-63)" },
502	{ ABS, ins_imms, ext_imms, 0, {{ 1, 36}}, SDEC, /* IMM1 */
503	"a 1-bit integer (-1, 0)" },
504	{ ABS, ins_immu, ext_immu, 0, {{ 2, 13}}, UDEC, /* IMMU2 */
505	"a 2-bit unsigned (0-3)" },
506	{ ABS, ins_immu, ext_immu, 0, {{ 7, 13}}, 0, /* IMMU7a */
507	"a 7-bit unsigned (0-127)" },
508	{ ABS, ins_immu, ext_immu, 0, {{ 7, 20}}, 0, /* IMMU7b */
509	"a 7-bit unsigned (0-127)" },
510	{ ABS, ins_immu, ext_immu, 0, {{ 7, 13}}, UDEC, /* SOF */
511	"a frame size (register count)" },
512	{ ABS, ins_immu, ext_immu, 0, {{ 7, 20}}, UDEC, /* SOL */
513	"a local register count" },
514	{ ABS, ins_immus8,ext_immus8,0, {{ 4, 27}}, UDEC, /* SOR */
515	"a rotating register count (integer multiple of 8)" },
516	{ ABS, ins_imms, ext_imms, 0, /* IMM8 */
517	{{ 7, 13}, { 1, 36}}, SDEC,
518	"an 8-bit integer (-128-127)" },
519	{ ABS, ins_immsu4, ext_imms, 0, /* IMM8U4 */
520	{{ 7, 13}, { 1, 36}}, SDEC,
521	"an 8-bit signed integer for 32-bit unsigned compare (-128-127)" },
522	{ ABS, ins_immsm1, ext_immsm1, 0, /* IMM8M1 */
523	{{ 7, 13}, { 1, 36}}, SDEC,
524	"an 8-bit integer (-127-128)" },
525	{ ABS, ins_immsm1u4, ext_immsm1, 0, /* IMM8M1U4 */
526	{{ 7, 13}, { 1, 36}}, SDEC,
527	"an 8-bit integer for 32-bit unsigned compare (-127-(-1),1-128,0x100000000)" },
528	{ ABS, ins_immsm1, ext_immsm1, 0, /* IMM8M1U8 */
529	{{ 7, 13}, { 1, 36}}, SDEC,
530	"an 8-bit integer for 64-bit unsigned compare (-127-(-1),1-128,0x10000000000000000)" },
531	{ ABS, ins_immu, ext_immu, 0, {{ 2, 33}, { 7, 20}}, 0, /* IMMU9 */
532	"a 9-bit unsigned (0-511)" },
533	{ ABS, ins_imms, ext_imms, 0, /* IMM9a */
534	{{ 7, 6}, { 1, 27}, { 1, 36}}, SDEC,
535	"a 9-bit integer (-256-255)" },
536	{ ABS, ins_imms, ext_imms, 0, /* IMM9b */
537	{{ 7, 13}, { 1, 27}, { 1, 36}}, SDEC,
538	"a 9-bit integer (-256-255)" },
539	{ ABS, ins_imms, ext_imms, 0, /* IMM14 */
540	{{ 7, 13}, { 6, 27}, { 1, 36}}, SDEC,
541	"a 14-bit integer (-8192-8191)" },
542	{ ABS, ins_imms1, ext_imms1, 0, /* IMM17 */
543	{{ 7, 6}, { 8, 24}, { 1, 36}}, 0,
544	"a 17-bit integer (-65536-65535)" },
545	{ ABS, ins_immu, ext_immu, 0, {{20, 6}, { 1, 36}}, 0, /* IMMU21 */
546	"a 21-bit unsigned" },
547	{ ABS, ins_imms, ext_imms, 0, /* IMM22 */
548	{{ 7, 13}, { 9, 27}, { 5, 22}, { 1, 36}}, SDEC,
87f8eb97	549	"a 22-bit signed integer" },
800eeca4 JW	550	{ ABS, ins_immu, ext_immu, 0, /* IMMU24 */
	551	{{21, 6}, { 2, 31}, { 1, 36}}, 0,
	552	"a 24-bit unsigned" },
	553	{ ABS, ins_imms16,ext_imms16,0, {{27, 6}, { 1, 36}}, 0, /* IMM44 */
	554	"a 44-bit unsigned (least 16 bits ignored/zeroes)" },
	555	{ ABS, ins_rsvd, ext_rsvd, 0, {{0, 0}}, 0, /* IMMU62 */
71f6b586	556	"a 62-bit unsigned" },
800eeca4 JW	557	{ ABS, ins_rsvd, ext_rsvd, 0, {{0, 0}}, 0, /* IMMU64 */
	558	"a 64-bit unsigned" },
	559	{ ABS, ins_inc3, ext_inc3, 0, {{ 3, 13}}, SDEC, /* INC3 */
	560	"an increment (+/- 1, 4, 8, or 16)" },
	561	{ ABS, ins_cnt, ext_cnt, 0, {{ 4, 27}}, UDEC, /* LEN4 */
	562	"a 4-bit length (1-16)" },
	563	{ ABS, ins_cnt, ext_cnt, 0, {{ 6, 27}}, UDEC, /* LEN6 */
	564	"a 6-bit length (1-64)" },
	565	{ ABS, ins_immu, ext_immu, 0, {{ 4, 20}}, 0, /* MBTYPE4 */
	566	"a mix type (@rev, @mix, @shuf, @alt, or @brcst)" },
	567	{ ABS, ins_immu, ext_immu, 0, {{ 8, 20}}, 0, /* MBTYPE8 */
	568	"an 8-bit mix type" },
	569	{ ABS, ins_immu, ext_immu, 0, {{ 6, 14}}, UDEC, /* POS6 */
	570	"a 6-bit bit pos (0-63)" },
	571	{ REL, ins_imms4, ext_imms4, 0, {{ 7, 6}, { 2, 33}}, 0, /* TAG13 */
	572	"a branch tag" },
	573	{ REL, ins_imms4, ext_imms4, 0, {{ 9, 24}}, 0, /* TAG13b */
	574	"a branch tag" },
	575	{ REL, ins_imms4, ext_imms4, 0, {{20, 6}, { 1, 36}}, 0, /* TGT25 */
	576	"a branch target" },
	577	{ REL, ins_imms4, ext_imms4, 0, /* TGT25b */
	578	{{ 7, 6}, {13, 20}, { 1, 36}}, 0,
	579	"a branch target" },
	580	{ REL, ins_imms4, ext_imms4, 0, {{20, 13}, { 1, 36}}, 0, /* TGT25c */
71f6b586 KH	581	"a branch target" },
71f6b586 KH	582	{ REL, ins_rsvd, ext_rsvd, 0, {{0, 0}}, 0, /* TGT64 */
800eeca4	583	"a branch target" },
a823923b RH	584
	585	{ ABS, ins_const, ext_const, 0, {{0, 0}}, 0, /* LDXMOV */
	586	"ldxmov target" },
800eeca4	587	};