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[deliverable/binutils-gdb.git] / bfd / elf32-arm.c
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252b5132 1/* 32-bit ELF support for ARM
b3adc24a 2 Copyright (C) 1998-2020 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of BFD, the Binary File Descriptor library.
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
cd123cb7 8 the Free Software Foundation; either version 3 of the License, or
252b5132
RH		 9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
cd123cb7
NC		 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
252b5132 20
6e6718a3 21#include "sysdep.h"
2468f9c9
PB		 22#include <limits.h>
23
3db64b00 24#include "bfd.h"
00a97672 25#include "libiberty.h"
7f266840
DJ		 26#include "libbfd.h"
27#include "elf-bfd.h"
b38cadfb 28#include "elf-nacl.h"
00a97672 29#include "elf-vxworks.h"
ee065d83 30#include "elf/arm.h"
f37164d7
AM		 31#include "elf32-arm.h"
32#include "cpu-arm.h"
7f266840 33
00a97672
RS		 34/* Return the relocation section associated with NAME. HTAB is the
35 bfd's elf32_arm_link_hash_entry. */
36#define RELOC_SECTION(HTAB, NAME) \
37 ((HTAB)->use_rel ? ".rel" NAME : ".rela" NAME)
38
39/* Return size of a relocation entry. HTAB is the bfd's
40 elf32_arm_link_hash_entry. */
41#define RELOC_SIZE(HTAB) \
42 ((HTAB)->use_rel \
43 ? sizeof (Elf32_External_Rel) \
44 : sizeof (Elf32_External_Rela))
45
46/* Return function to swap relocations in. HTAB is the bfd's
47 elf32_arm_link_hash_entry. */
48#define SWAP_RELOC_IN(HTAB) \
49 ((HTAB)->use_rel \
50 ? bfd_elf32_swap_reloc_in \
51 : bfd_elf32_swap_reloca_in)
52
53/* Return function to swap relocations out. HTAB is the bfd's
54 elf32_arm_link_hash_entry. */
55#define SWAP_RELOC_OUT(HTAB) \
56 ((HTAB)->use_rel \
57 ? bfd_elf32_swap_reloc_out \
58 : bfd_elf32_swap_reloca_out)
59
f3185997 60#define elf_info_to_howto NULL
07d6d2b8 61#define elf_info_to_howto_rel elf32_arm_info_to_howto
7f266840
DJ		 62
63#define ARM_ELF_ABI_VERSION 0
64#define ARM_ELF_OS_ABI_VERSION ELFOSABI_ARM
65
79f08007
YZ		 66/* The Adjusted Place, as defined by AAELF. */
67#define Pa(X) ((X) & 0xfffffffc)
68
3e6b1042
DJ		 69static bfd_boolean elf32_arm_write_section (bfd *output_bfd,
70 struct bfd_link_info *link_info,
71 asection *sec,
72 bfd_byte *contents);
73
7f266840
DJ		 74/* Note: code such as elf32_arm_reloc_type_lookup expect to use e.g.
75 R_ARM_PC24 as an index into this, and find the R_ARM_PC24 HOWTO
76 in that slot. */
77
c19d1205 78static reloc_howto_type elf32_arm_howto_table_1[] =
7f266840 79{
8029a119 80 /* No relocation. */
7f266840
DJ		 81 HOWTO (R_ARM_NONE, /* type */
82 0, /* rightshift */
6346d5ca 83 3, /* size (0 = byte, 1 = short, 2 = long) */
7f266840
DJ		 84 0, /* bitsize */
85 FALSE, /* pc_relative */
86 0, /* bitpos */
87 complain_overflow_dont,/* complain_on_overflow */
88 bfd_elf_generic_reloc, /* special_function */
89 "R_ARM_NONE", /* name */
90 FALSE, /* partial_inplace */
91 0, /* src_mask */
92 0, /* dst_mask */
93 FALSE), /* pcrel_offset */
94
95 HOWTO (R_ARM_PC24, /* type */
96 2, /* rightshift */
97 2, /* size (0 = byte, 1 = short, 2 = long) */
98 24, /* bitsize */
99 TRUE, /* pc_relative */
100 0, /* bitpos */
101 complain_overflow_signed,/* complain_on_overflow */
102 bfd_elf_generic_reloc, /* special_function */
103 "R_ARM_PC24", /* name */
104 FALSE, /* partial_inplace */
105 0x00ffffff, /* src_mask */
106 0x00ffffff, /* dst_mask */
107 TRUE), /* pcrel_offset */
108
109 /* 32 bit absolute */
110 HOWTO (R_ARM_ABS32, /* type */
111 0, /* rightshift */
112 2, /* size (0 = byte, 1 = short, 2 = long) */
113 32, /* bitsize */
114 FALSE, /* pc_relative */
115 0, /* bitpos */
116 complain_overflow_bitfield,/* complain_on_overflow */
117 bfd_elf_generic_reloc, /* special_function */
118 "R_ARM_ABS32", /* name */
119 FALSE, /* partial_inplace */
120 0xffffffff, /* src_mask */
121 0xffffffff, /* dst_mask */
122 FALSE), /* pcrel_offset */
123
124 /* standard 32bit pc-relative reloc */
125 HOWTO (R_ARM_REL32, /* type */
126 0, /* rightshift */
127 2, /* size (0 = byte, 1 = short, 2 = long) */
128 32, /* bitsize */
129 TRUE, /* pc_relative */
130 0, /* bitpos */
131 complain_overflow_bitfield,/* complain_on_overflow */
132 bfd_elf_generic_reloc, /* special_function */
133 "R_ARM_REL32", /* name */
134 FALSE, /* partial_inplace */
135 0xffffffff, /* src_mask */
136 0xffffffff, /* dst_mask */
137 TRUE), /* pcrel_offset */
138
c19d1205 139 /* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */
4962c51a 140 HOWTO (R_ARM_LDR_PC_G0, /* type */
7f266840
DJ		 141 0, /* rightshift */
142 0, /* size (0 = byte, 1 = short, 2 = long) */
4962c51a
MS		 143 32, /* bitsize */
144 TRUE, /* pc_relative */
7f266840 145 0, /* bitpos */
4962c51a 146 complain_overflow_dont,/* complain_on_overflow */
7f266840 147 bfd_elf_generic_reloc, /* special_function */
4962c51a 148 "R_ARM_LDR_PC_G0", /* name */
7f266840 149 FALSE, /* partial_inplace */
4962c51a
MS		 150 0xffffffff, /* src_mask */
151 0xffffffff, /* dst_mask */
152 TRUE), /* pcrel_offset */
7f266840
DJ		 153
154 /* 16 bit absolute */
155 HOWTO (R_ARM_ABS16, /* type */
156 0, /* rightshift */
157 1, /* size (0 = byte, 1 = short, 2 = long) */
158 16, /* bitsize */
159 FALSE, /* pc_relative */
160 0, /* bitpos */
161 complain_overflow_bitfield,/* complain_on_overflow */
162 bfd_elf_generic_reloc, /* special_function */
163 "R_ARM_ABS16", /* name */
164 FALSE, /* partial_inplace */
165 0x0000ffff, /* src_mask */
166 0x0000ffff, /* dst_mask */
167 FALSE), /* pcrel_offset */
168
169 /* 12 bit absolute */
170 HOWTO (R_ARM_ABS12, /* type */
171 0, /* rightshift */
172 2, /* size (0 = byte, 1 = short, 2 = long) */
173 12, /* bitsize */
174 FALSE, /* pc_relative */
175 0, /* bitpos */
176 complain_overflow_bitfield,/* complain_on_overflow */
177 bfd_elf_generic_reloc, /* special_function */
178 "R_ARM_ABS12", /* name */
179 FALSE, /* partial_inplace */
00a97672
RS		 180 0x00000fff, /* src_mask */
181 0x00000fff, /* dst_mask */
7f266840
DJ		 182 FALSE), /* pcrel_offset */
183
184 HOWTO (R_ARM_THM_ABS5, /* type */
185 6, /* rightshift */
186 1, /* size (0 = byte, 1 = short, 2 = long) */
187 5, /* bitsize */
188 FALSE, /* pc_relative */
189 0, /* bitpos */
190 complain_overflow_bitfield,/* complain_on_overflow */
191 bfd_elf_generic_reloc, /* special_function */
192 "R_ARM_THM_ABS5", /* name */
193 FALSE, /* partial_inplace */
194 0x000007e0, /* src_mask */
195 0x000007e0, /* dst_mask */
196 FALSE), /* pcrel_offset */
197
198 /* 8 bit absolute */
199 HOWTO (R_ARM_ABS8, /* type */
200 0, /* rightshift */
201 0, /* size (0 = byte, 1 = short, 2 = long) */
202 8, /* bitsize */
203 FALSE, /* pc_relative */
204 0, /* bitpos */
205 complain_overflow_bitfield,/* complain_on_overflow */
206 bfd_elf_generic_reloc, /* special_function */
207 "R_ARM_ABS8", /* name */
208 FALSE, /* partial_inplace */
209 0x000000ff, /* src_mask */
210 0x000000ff, /* dst_mask */
211 FALSE), /* pcrel_offset */
212
213 HOWTO (R_ARM_SBREL32, /* type */
214 0, /* rightshift */
215 2, /* size (0 = byte, 1 = short, 2 = long) */
216 32, /* bitsize */
217 FALSE, /* pc_relative */
218 0, /* bitpos */
219 complain_overflow_dont,/* complain_on_overflow */
220 bfd_elf_generic_reloc, /* special_function */
221 "R_ARM_SBREL32", /* name */
222 FALSE, /* partial_inplace */
223 0xffffffff, /* src_mask */
224 0xffffffff, /* dst_mask */
225 FALSE), /* pcrel_offset */
226
c19d1205 227 HOWTO (R_ARM_THM_CALL, /* type */
7f266840
DJ		 228 1, /* rightshift */
229 2, /* size (0 = byte, 1 = short, 2 = long) */
f6ebfac0 230 24, /* bitsize */
7f266840
DJ		 231 TRUE, /* pc_relative */
232 0, /* bitpos */
233 complain_overflow_signed,/* complain_on_overflow */
234 bfd_elf_generic_reloc, /* special_function */
c19d1205 235 "R_ARM_THM_CALL", /* name */
7f266840 236 FALSE, /* partial_inplace */
7f6ab9f8
AM		 237 0x07ff2fff, /* src_mask */
238 0x07ff2fff, /* dst_mask */
7f266840
DJ		 239 TRUE), /* pcrel_offset */
240
07d6d2b8 241 HOWTO (R_ARM_THM_PC8, /* type */
7f266840
DJ		 242 1, /* rightshift */
243 1, /* size (0 = byte, 1 = short, 2 = long) */
244 8, /* bitsize */
245 TRUE, /* pc_relative */
246 0, /* bitpos */
247 complain_overflow_signed,/* complain_on_overflow */
248 bfd_elf_generic_reloc, /* special_function */
249 "R_ARM_THM_PC8", /* name */
250 FALSE, /* partial_inplace */
251 0x000000ff, /* src_mask */
252 0x000000ff, /* dst_mask */
253 TRUE), /* pcrel_offset */
254
c19d1205 255 HOWTO (R_ARM_BREL_ADJ, /* type */
7f266840
DJ		 256 1, /* rightshift */
257 1, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 258 32, /* bitsize */
259 FALSE, /* pc_relative */
7f266840
DJ		 260 0, /* bitpos */
261 complain_overflow_signed,/* complain_on_overflow */
262 bfd_elf_generic_reloc, /* special_function */
c19d1205 263 "R_ARM_BREL_ADJ", /* name */
7f266840 264 FALSE, /* partial_inplace */
c19d1205
ZW		 265 0xffffffff, /* src_mask */
266 0xffffffff, /* dst_mask */
267 FALSE), /* pcrel_offset */
7f266840 268
0855e32b 269 HOWTO (R_ARM_TLS_DESC, /* type */
7f266840 270 0, /* rightshift */
0855e32b
NS		 271 2, /* size (0 = byte, 1 = short, 2 = long) */
272 32, /* bitsize */
7f266840
DJ		 273 FALSE, /* pc_relative */
274 0, /* bitpos */
0855e32b 275 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 276 bfd_elf_generic_reloc, /* special_function */
0855e32b 277 "R_ARM_TLS_DESC", /* name */
7f266840 278 FALSE, /* partial_inplace */
0855e32b
NS		 279 0xffffffff, /* src_mask */
280 0xffffffff, /* dst_mask */
7f266840
DJ		 281 FALSE), /* pcrel_offset */
282
283 HOWTO (R_ARM_THM_SWI8, /* type */
284 0, /* rightshift */
285 0, /* size (0 = byte, 1 = short, 2 = long) */
286 0, /* bitsize */
287 FALSE, /* pc_relative */
288 0, /* bitpos */
289 complain_overflow_signed,/* complain_on_overflow */
290 bfd_elf_generic_reloc, /* special_function */
291 "R_ARM_SWI8", /* name */
292 FALSE, /* partial_inplace */
293 0x00000000, /* src_mask */
294 0x00000000, /* dst_mask */
295 FALSE), /* pcrel_offset */
296
297 /* BLX instruction for the ARM. */
298 HOWTO (R_ARM_XPC25, /* type */
299 2, /* rightshift */
300 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 301 24, /* bitsize */
7f266840
DJ		 302 TRUE, /* pc_relative */
303 0, /* bitpos */
304 complain_overflow_signed,/* complain_on_overflow */
305 bfd_elf_generic_reloc, /* special_function */
306 "R_ARM_XPC25", /* name */
307 FALSE, /* partial_inplace */
308 0x00ffffff, /* src_mask */
309 0x00ffffff, /* dst_mask */
310 TRUE), /* pcrel_offset */
311
312 /* BLX instruction for the Thumb. */
313 HOWTO (R_ARM_THM_XPC22, /* type */
314 2, /* rightshift */
315 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 316 24, /* bitsize */
7f266840
DJ		 317 TRUE, /* pc_relative */
318 0, /* bitpos */
319 complain_overflow_signed,/* complain_on_overflow */
320 bfd_elf_generic_reloc, /* special_function */
321 "R_ARM_THM_XPC22", /* name */
322 FALSE, /* partial_inplace */
7f6ab9f8
AM		 323 0x07ff2fff, /* src_mask */
324 0x07ff2fff, /* dst_mask */
7f266840
DJ		 325 TRUE), /* pcrel_offset */
326
ba93b8ac 327 /* Dynamic TLS relocations. */
7f266840 328
ba93b8ac 329 HOWTO (R_ARM_TLS_DTPMOD32, /* type */
07d6d2b8
AM		 330 0, /* rightshift */
331 2, /* size (0 = byte, 1 = short, 2 = long) */
332 32, /* bitsize */
333 FALSE, /* pc_relative */
334 0, /* bitpos */
99059e56
RM		 335 complain_overflow_bitfield,/* complain_on_overflow */
336 bfd_elf_generic_reloc, /* special_function */
337 "R_ARM_TLS_DTPMOD32", /* name */
338 TRUE, /* partial_inplace */
339 0xffffffff, /* src_mask */
340 0xffffffff, /* dst_mask */
07d6d2b8 341 FALSE), /* pcrel_offset */
7f266840 342
ba93b8ac 343 HOWTO (R_ARM_TLS_DTPOFF32, /* type */
07d6d2b8
AM		 344 0, /* rightshift */
345 2, /* size (0 = byte, 1 = short, 2 = long) */
346 32, /* bitsize */
347 FALSE, /* pc_relative */
348 0, /* bitpos */
99059e56
RM		 349 complain_overflow_bitfield,/* complain_on_overflow */
350 bfd_elf_generic_reloc, /* special_function */
351 "R_ARM_TLS_DTPOFF32", /* name */
352 TRUE, /* partial_inplace */
353 0xffffffff, /* src_mask */
354 0xffffffff, /* dst_mask */
07d6d2b8 355 FALSE), /* pcrel_offset */
7f266840 356
ba93b8ac 357 HOWTO (R_ARM_TLS_TPOFF32, /* type */
07d6d2b8
AM		 358 0, /* rightshift */
359 2, /* size (0 = byte, 1 = short, 2 = long) */
360 32, /* bitsize */
361 FALSE, /* pc_relative */
362 0, /* bitpos */
99059e56
RM		 363 complain_overflow_bitfield,/* complain_on_overflow */
364 bfd_elf_generic_reloc, /* special_function */
365 "R_ARM_TLS_TPOFF32", /* name */
366 TRUE, /* partial_inplace */
367 0xffffffff, /* src_mask */
368 0xffffffff, /* dst_mask */
07d6d2b8 369 FALSE), /* pcrel_offset */
7f266840
DJ		 370
371 /* Relocs used in ARM Linux */
372
373 HOWTO (R_ARM_COPY, /* type */
07d6d2b8
AM		 374 0, /* rightshift */
375 2, /* size (0 = byte, 1 = short, 2 = long) */
376 32, /* bitsize */
377 FALSE, /* pc_relative */
378 0, /* bitpos */
99059e56
RM		 379 complain_overflow_bitfield,/* complain_on_overflow */
380 bfd_elf_generic_reloc, /* special_function */
381 "R_ARM_COPY", /* name */
382 TRUE, /* partial_inplace */
383 0xffffffff, /* src_mask */
384 0xffffffff, /* dst_mask */
07d6d2b8 385 FALSE), /* pcrel_offset */
7f266840
DJ		 386
387 HOWTO (R_ARM_GLOB_DAT, /* type */
07d6d2b8
AM		 388 0, /* rightshift */
389 2, /* size (0 = byte, 1 = short, 2 = long) */
390 32, /* bitsize */
391 FALSE, /* pc_relative */
392 0, /* bitpos */
99059e56
RM		 393 complain_overflow_bitfield,/* complain_on_overflow */
394 bfd_elf_generic_reloc, /* special_function */
395 "R_ARM_GLOB_DAT", /* name */
396 TRUE, /* partial_inplace */
397 0xffffffff, /* src_mask */
398 0xffffffff, /* dst_mask */
07d6d2b8 399 FALSE), /* pcrel_offset */
7f266840
DJ		 400
401 HOWTO (R_ARM_JUMP_SLOT, /* type */
07d6d2b8
AM		 402 0, /* rightshift */
403 2, /* size (0 = byte, 1 = short, 2 = long) */
404 32, /* bitsize */
405 FALSE, /* pc_relative */
406 0, /* bitpos */
99059e56
RM		 407 complain_overflow_bitfield,/* complain_on_overflow */
408 bfd_elf_generic_reloc, /* special_function */
409 "R_ARM_JUMP_SLOT", /* name */
410 TRUE, /* partial_inplace */
411 0xffffffff, /* src_mask */
412 0xffffffff, /* dst_mask */
07d6d2b8 413 FALSE), /* pcrel_offset */
7f266840
DJ		 414
415 HOWTO (R_ARM_RELATIVE, /* type */
07d6d2b8
AM		 416 0, /* rightshift */
417 2, /* size (0 = byte, 1 = short, 2 = long) */
418 32, /* bitsize */
419 FALSE, /* pc_relative */
420 0, /* bitpos */
99059e56
RM		 421 complain_overflow_bitfield,/* complain_on_overflow */
422 bfd_elf_generic_reloc, /* special_function */
423 "R_ARM_RELATIVE", /* name */
424 TRUE, /* partial_inplace */
425 0xffffffff, /* src_mask */
426 0xffffffff, /* dst_mask */
07d6d2b8 427 FALSE), /* pcrel_offset */
7f266840 428
c19d1205 429 HOWTO (R_ARM_GOTOFF32, /* type */
07d6d2b8
AM		 430 0, /* rightshift */
431 2, /* size (0 = byte, 1 = short, 2 = long) */
432 32, /* bitsize */
433 FALSE, /* pc_relative */
434 0, /* bitpos */
99059e56
RM		 435 complain_overflow_bitfield,/* complain_on_overflow */
436 bfd_elf_generic_reloc, /* special_function */
437 "R_ARM_GOTOFF32", /* name */
438 TRUE, /* partial_inplace */
439 0xffffffff, /* src_mask */
440 0xffffffff, /* dst_mask */
07d6d2b8 441 FALSE), /* pcrel_offset */
7f266840
DJ		 442
443 HOWTO (R_ARM_GOTPC, /* type */
07d6d2b8
AM		 444 0, /* rightshift */
445 2, /* size (0 = byte, 1 = short, 2 = long) */
446 32, /* bitsize */
99059e56 447 TRUE, /* pc_relative */
07d6d2b8 448 0, /* bitpos */
99059e56
RM		 449 complain_overflow_bitfield,/* complain_on_overflow */
450 bfd_elf_generic_reloc, /* special_function */
451 "R_ARM_GOTPC", /* name */
452 TRUE, /* partial_inplace */
453 0xffffffff, /* src_mask */
454 0xffffffff, /* dst_mask */
455 TRUE), /* pcrel_offset */
7f266840
DJ		 456
457 HOWTO (R_ARM_GOT32, /* type */
07d6d2b8
AM		 458 0, /* rightshift */
459 2, /* size (0 = byte, 1 = short, 2 = long) */
460 32, /* bitsize */
99059e56 461 FALSE, /* pc_relative */
07d6d2b8 462 0, /* bitpos */
99059e56
RM		 463 complain_overflow_bitfield,/* complain_on_overflow */
464 bfd_elf_generic_reloc, /* special_function */
465 "R_ARM_GOT32", /* name */
466 TRUE, /* partial_inplace */
467 0xffffffff, /* src_mask */
468 0xffffffff, /* dst_mask */
469 FALSE), /* pcrel_offset */
7f266840
DJ		 470
471 HOWTO (R_ARM_PLT32, /* type */
07d6d2b8
AM		 472 2, /* rightshift */
473 2, /* size (0 = byte, 1 = short, 2 = long) */
474 24, /* bitsize */
99059e56 475 TRUE, /* pc_relative */
07d6d2b8 476 0, /* bitpos */
99059e56
RM		 477 complain_overflow_bitfield,/* complain_on_overflow */
478 bfd_elf_generic_reloc, /* special_function */
479 "R_ARM_PLT32", /* name */
480 FALSE, /* partial_inplace */
481 0x00ffffff, /* src_mask */
482 0x00ffffff, /* dst_mask */
483 TRUE), /* pcrel_offset */
7f266840
DJ		 484
485 HOWTO (R_ARM_CALL, /* type */
486 2, /* rightshift */
487 2, /* size (0 = byte, 1 = short, 2 = long) */
488 24, /* bitsize */
489 TRUE, /* pc_relative */
490 0, /* bitpos */
491 complain_overflow_signed,/* complain_on_overflow */
492 bfd_elf_generic_reloc, /* special_function */
493 "R_ARM_CALL", /* name */
494 FALSE, /* partial_inplace */
495 0x00ffffff, /* src_mask */
496 0x00ffffff, /* dst_mask */
497 TRUE), /* pcrel_offset */
498
499 HOWTO (R_ARM_JUMP24, /* type */
500 2, /* rightshift */
501 2, /* size (0 = byte, 1 = short, 2 = long) */
502 24, /* bitsize */
503 TRUE, /* pc_relative */
504 0, /* bitpos */
505 complain_overflow_signed,/* complain_on_overflow */
506 bfd_elf_generic_reloc, /* special_function */
507 "R_ARM_JUMP24", /* name */
508 FALSE, /* partial_inplace */
509 0x00ffffff, /* src_mask */
510 0x00ffffff, /* dst_mask */
511 TRUE), /* pcrel_offset */
512
c19d1205
ZW		 513 HOWTO (R_ARM_THM_JUMP24, /* type */
514 1, /* rightshift */
515 2, /* size (0 = byte, 1 = short, 2 = long) */
516 24, /* bitsize */
517 TRUE, /* pc_relative */
7f266840 518 0, /* bitpos */
c19d1205 519 complain_overflow_signed,/* complain_on_overflow */
7f266840 520 bfd_elf_generic_reloc, /* special_function */
c19d1205 521 "R_ARM_THM_JUMP24", /* name */
7f266840 522 FALSE, /* partial_inplace */
c19d1205
ZW		 523 0x07ff2fff, /* src_mask */
524 0x07ff2fff, /* dst_mask */
525 TRUE), /* pcrel_offset */
7f266840 526
c19d1205 527 HOWTO (R_ARM_BASE_ABS, /* type */
7f266840 528 0, /* rightshift */
c19d1205
ZW		 529 2, /* size (0 = byte, 1 = short, 2 = long) */
530 32, /* bitsize */
7f266840
DJ		 531 FALSE, /* pc_relative */
532 0, /* bitpos */
533 complain_overflow_dont,/* complain_on_overflow */
534 bfd_elf_generic_reloc, /* special_function */
c19d1205 535 "R_ARM_BASE_ABS", /* name */
7f266840 536 FALSE, /* partial_inplace */
c19d1205
ZW		 537 0xffffffff, /* src_mask */
538 0xffffffff, /* dst_mask */
7f266840
DJ		 539 FALSE), /* pcrel_offset */
540
541 HOWTO (R_ARM_ALU_PCREL7_0, /* type */
542 0, /* rightshift */
543 2, /* size (0 = byte, 1 = short, 2 = long) */
544 12, /* bitsize */
545 TRUE, /* pc_relative */
546 0, /* bitpos */
547 complain_overflow_dont,/* complain_on_overflow */
548 bfd_elf_generic_reloc, /* special_function */
549 "R_ARM_ALU_PCREL_7_0", /* name */
550 FALSE, /* partial_inplace */
551 0x00000fff, /* src_mask */
552 0x00000fff, /* dst_mask */
553 TRUE), /* pcrel_offset */
554
555 HOWTO (R_ARM_ALU_PCREL15_8, /* type */
556 0, /* rightshift */
557 2, /* size (0 = byte, 1 = short, 2 = long) */
558 12, /* bitsize */
559 TRUE, /* pc_relative */
560 8, /* bitpos */
561 complain_overflow_dont,/* complain_on_overflow */
562 bfd_elf_generic_reloc, /* special_function */
563 "R_ARM_ALU_PCREL_15_8",/* name */
564 FALSE, /* partial_inplace */
565 0x00000fff, /* src_mask */
566 0x00000fff, /* dst_mask */
567 TRUE), /* pcrel_offset */
568
569 HOWTO (R_ARM_ALU_PCREL23_15, /* type */
570 0, /* rightshift */
571 2, /* size (0 = byte, 1 = short, 2 = long) */
572 12, /* bitsize */
573 TRUE, /* pc_relative */
574 16, /* bitpos */
575 complain_overflow_dont,/* complain_on_overflow */
576 bfd_elf_generic_reloc, /* special_function */
577 "R_ARM_ALU_PCREL_23_15",/* name */
578 FALSE, /* partial_inplace */
579 0x00000fff, /* src_mask */
580 0x00000fff, /* dst_mask */
581 TRUE), /* pcrel_offset */
582
583 HOWTO (R_ARM_LDR_SBREL_11_0, /* type */
584 0, /* rightshift */
585 2, /* size (0 = byte, 1 = short, 2 = long) */
586 12, /* bitsize */
587 FALSE, /* pc_relative */
588 0, /* bitpos */
589 complain_overflow_dont,/* complain_on_overflow */
590 bfd_elf_generic_reloc, /* special_function */
591 "R_ARM_LDR_SBREL_11_0",/* name */
592 FALSE, /* partial_inplace */
593 0x00000fff, /* src_mask */
594 0x00000fff, /* dst_mask */
595 FALSE), /* pcrel_offset */
596
597 HOWTO (R_ARM_ALU_SBREL_19_12, /* type */
598 0, /* rightshift */
599 2, /* size (0 = byte, 1 = short, 2 = long) */
600 8, /* bitsize */
601 FALSE, /* pc_relative */
602 12, /* bitpos */
603 complain_overflow_dont,/* complain_on_overflow */
604 bfd_elf_generic_reloc, /* special_function */
605 "R_ARM_ALU_SBREL_19_12",/* name */
606 FALSE, /* partial_inplace */
607 0x000ff000, /* src_mask */
608 0x000ff000, /* dst_mask */
609 FALSE), /* pcrel_offset */
610
611 HOWTO (R_ARM_ALU_SBREL_27_20, /* type */
612 0, /* rightshift */
613 2, /* size (0 = byte, 1 = short, 2 = long) */
614 8, /* bitsize */
615 FALSE, /* pc_relative */
616 20, /* bitpos */
617 complain_overflow_dont,/* complain_on_overflow */
618 bfd_elf_generic_reloc, /* special_function */
619 "R_ARM_ALU_SBREL_27_20",/* name */
620 FALSE, /* partial_inplace */
621 0x0ff00000, /* src_mask */
622 0x0ff00000, /* dst_mask */
623 FALSE), /* pcrel_offset */
624
625 HOWTO (R_ARM_TARGET1, /* type */
626 0, /* rightshift */
627 2, /* size (0 = byte, 1 = short, 2 = long) */
628 32, /* bitsize */
629 FALSE, /* pc_relative */
630 0, /* bitpos */
631 complain_overflow_dont,/* complain_on_overflow */
632 bfd_elf_generic_reloc, /* special_function */
633 "R_ARM_TARGET1", /* name */
634 FALSE, /* partial_inplace */
635 0xffffffff, /* src_mask */
636 0xffffffff, /* dst_mask */
637 FALSE), /* pcrel_offset */
638
639 HOWTO (R_ARM_ROSEGREL32, /* type */
640 0, /* rightshift */
641 2, /* size (0 = byte, 1 = short, 2 = long) */
642 32, /* bitsize */
643 FALSE, /* pc_relative */
644 0, /* bitpos */
645 complain_overflow_dont,/* complain_on_overflow */
646 bfd_elf_generic_reloc, /* special_function */
647 "R_ARM_ROSEGREL32", /* name */
648 FALSE, /* partial_inplace */
649 0xffffffff, /* src_mask */
650 0xffffffff, /* dst_mask */
651 FALSE), /* pcrel_offset */
652
653 HOWTO (R_ARM_V4BX, /* type */
654 0, /* rightshift */
655 2, /* size (0 = byte, 1 = short, 2 = long) */
656 32, /* bitsize */
657 FALSE, /* pc_relative */
658 0, /* bitpos */
659 complain_overflow_dont,/* complain_on_overflow */
660 bfd_elf_generic_reloc, /* special_function */
661 "R_ARM_V4BX", /* name */
662 FALSE, /* partial_inplace */
663 0xffffffff, /* src_mask */
664 0xffffffff, /* dst_mask */
665 FALSE), /* pcrel_offset */
666
667 HOWTO (R_ARM_TARGET2, /* type */
668 0, /* rightshift */
669 2, /* size (0 = byte, 1 = short, 2 = long) */
670 32, /* bitsize */
671 FALSE, /* pc_relative */
672 0, /* bitpos */
673 complain_overflow_signed,/* complain_on_overflow */
674 bfd_elf_generic_reloc, /* special_function */
675 "R_ARM_TARGET2", /* name */
676 FALSE, /* partial_inplace */
677 0xffffffff, /* src_mask */
678 0xffffffff, /* dst_mask */
679 TRUE), /* pcrel_offset */
680
681 HOWTO (R_ARM_PREL31, /* type */
682 0, /* rightshift */
683 2, /* size (0 = byte, 1 = short, 2 = long) */
684 31, /* bitsize */
685 TRUE, /* pc_relative */
686 0, /* bitpos */
687 complain_overflow_signed,/* complain_on_overflow */
688 bfd_elf_generic_reloc, /* special_function */
689 "R_ARM_PREL31", /* name */
690 FALSE, /* partial_inplace */
691 0x7fffffff, /* src_mask */
692 0x7fffffff, /* dst_mask */
693 TRUE), /* pcrel_offset */
c19d1205
ZW		 694
695 HOWTO (R_ARM_MOVW_ABS_NC, /* type */
696 0, /* rightshift */
697 2, /* size (0 = byte, 1 = short, 2 = long) */
698 16, /* bitsize */
699 FALSE, /* pc_relative */
700 0, /* bitpos */
701 complain_overflow_dont,/* complain_on_overflow */
702 bfd_elf_generic_reloc, /* special_function */
703 "R_ARM_MOVW_ABS_NC", /* name */
704 FALSE, /* partial_inplace */
39623e12
PB		 705 0x000f0fff, /* src_mask */
706 0x000f0fff, /* dst_mask */
c19d1205
ZW		 707 FALSE), /* pcrel_offset */
708
709 HOWTO (R_ARM_MOVT_ABS, /* type */
710 0, /* rightshift */
711 2, /* size (0 = byte, 1 = short, 2 = long) */
712 16, /* bitsize */
713 FALSE, /* pc_relative */
714 0, /* bitpos */
715 complain_overflow_bitfield,/* complain_on_overflow */
716 bfd_elf_generic_reloc, /* special_function */
717 "R_ARM_MOVT_ABS", /* name */
718 FALSE, /* partial_inplace */
39623e12
PB		 719 0x000f0fff, /* src_mask */
720 0x000f0fff, /* dst_mask */
c19d1205
ZW		 721 FALSE), /* pcrel_offset */
722
723 HOWTO (R_ARM_MOVW_PREL_NC, /* type */
724 0, /* rightshift */
725 2, /* size (0 = byte, 1 = short, 2 = long) */
726 16, /* bitsize */
727 TRUE, /* pc_relative */
728 0, /* bitpos */
729 complain_overflow_dont,/* complain_on_overflow */
730 bfd_elf_generic_reloc, /* special_function */
731 "R_ARM_MOVW_PREL_NC", /* name */
732 FALSE, /* partial_inplace */
39623e12
PB		 733 0x000f0fff, /* src_mask */
734 0x000f0fff, /* dst_mask */
c19d1205
ZW		 735 TRUE), /* pcrel_offset */
736
737 HOWTO (R_ARM_MOVT_PREL, /* type */
738 0, /* rightshift */
739 2, /* size (0 = byte, 1 = short, 2 = long) */
740 16, /* bitsize */
741 TRUE, /* pc_relative */
742 0, /* bitpos */
743 complain_overflow_bitfield,/* complain_on_overflow */
744 bfd_elf_generic_reloc, /* special_function */
745 "R_ARM_MOVT_PREL", /* name */
746 FALSE, /* partial_inplace */
39623e12
PB		 747 0x000f0fff, /* src_mask */
748 0x000f0fff, /* dst_mask */
c19d1205
ZW		 749 TRUE), /* pcrel_offset */
750
751 HOWTO (R_ARM_THM_MOVW_ABS_NC, /* type */
752 0, /* rightshift */
753 2, /* size (0 = byte, 1 = short, 2 = long) */
754 16, /* bitsize */
755 FALSE, /* pc_relative */
756 0, /* bitpos */
757 complain_overflow_dont,/* complain_on_overflow */
758 bfd_elf_generic_reloc, /* special_function */
759 "R_ARM_THM_MOVW_ABS_NC",/* name */
760 FALSE, /* partial_inplace */
761 0x040f70ff, /* src_mask */
762 0x040f70ff, /* dst_mask */
763 FALSE), /* pcrel_offset */
764
765 HOWTO (R_ARM_THM_MOVT_ABS, /* type */
766 0, /* rightshift */
767 2, /* size (0 = byte, 1 = short, 2 = long) */
768 16, /* bitsize */
769 FALSE, /* pc_relative */
770 0, /* bitpos */
771 complain_overflow_bitfield,/* complain_on_overflow */
772 bfd_elf_generic_reloc, /* special_function */
773 "R_ARM_THM_MOVT_ABS", /* name */
774 FALSE, /* partial_inplace */
775 0x040f70ff, /* src_mask */
776 0x040f70ff, /* dst_mask */
777 FALSE), /* pcrel_offset */
778
779 HOWTO (R_ARM_THM_MOVW_PREL_NC,/* type */
780 0, /* rightshift */
781 2, /* size (0 = byte, 1 = short, 2 = long) */
782 16, /* bitsize */
783 TRUE, /* pc_relative */
784 0, /* bitpos */
785 complain_overflow_dont,/* complain_on_overflow */
786 bfd_elf_generic_reloc, /* special_function */
787 "R_ARM_THM_MOVW_PREL_NC",/* name */
788 FALSE, /* partial_inplace */
789 0x040f70ff, /* src_mask */
790 0x040f70ff, /* dst_mask */
791 TRUE), /* pcrel_offset */
792
793 HOWTO (R_ARM_THM_MOVT_PREL, /* type */
794 0, /* rightshift */
795 2, /* size (0 = byte, 1 = short, 2 = long) */
796 16, /* bitsize */
797 TRUE, /* pc_relative */
798 0, /* bitpos */
799 complain_overflow_bitfield,/* complain_on_overflow */
800 bfd_elf_generic_reloc, /* special_function */
801 "R_ARM_THM_MOVT_PREL", /* name */
802 FALSE, /* partial_inplace */
803 0x040f70ff, /* src_mask */
804 0x040f70ff, /* dst_mask */
805 TRUE), /* pcrel_offset */
806
807 HOWTO (R_ARM_THM_JUMP19, /* type */
808 1, /* rightshift */
809 2, /* size (0 = byte, 1 = short, 2 = long) */
810 19, /* bitsize */
811 TRUE, /* pc_relative */
812 0, /* bitpos */
813 complain_overflow_signed,/* complain_on_overflow */
814 bfd_elf_generic_reloc, /* special_function */
815 "R_ARM_THM_JUMP19", /* name */
816 FALSE, /* partial_inplace */
817 0x043f2fff, /* src_mask */
818 0x043f2fff, /* dst_mask */
819 TRUE), /* pcrel_offset */
820
821 HOWTO (R_ARM_THM_JUMP6, /* type */
822 1, /* rightshift */
823 1, /* size (0 = byte, 1 = short, 2 = long) */
824 6, /* bitsize */
825 TRUE, /* pc_relative */
826 0, /* bitpos */
827 complain_overflow_unsigned,/* complain_on_overflow */
828 bfd_elf_generic_reloc, /* special_function */
829 "R_ARM_THM_JUMP6", /* name */
830 FALSE, /* partial_inplace */
831 0x02f8, /* src_mask */
832 0x02f8, /* dst_mask */
833 TRUE), /* pcrel_offset */
834
835 /* These are declared as 13-bit signed relocations because we can
836 address -4095 .. 4095(base) by altering ADDW to SUBW or vice
837 versa. */
838 HOWTO (R_ARM_THM_ALU_PREL_11_0,/* type */
839 0, /* rightshift */
840 2, /* size (0 = byte, 1 = short, 2 = long) */
841 13, /* bitsize */
842 TRUE, /* pc_relative */
843 0, /* bitpos */
2cab6cc3 844 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 845 bfd_elf_generic_reloc, /* special_function */
846 "R_ARM_THM_ALU_PREL_11_0",/* name */
847 FALSE, /* partial_inplace */
2cab6cc3
MS		 848 0xffffffff, /* src_mask */
849 0xffffffff, /* dst_mask */
c19d1205
ZW		 850 TRUE), /* pcrel_offset */
851
852 HOWTO (R_ARM_THM_PC12, /* type */
853 0, /* rightshift */
854 2, /* size (0 = byte, 1 = short, 2 = long) */
855 13, /* bitsize */
856 TRUE, /* pc_relative */
857 0, /* bitpos */
2cab6cc3 858 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 859 bfd_elf_generic_reloc, /* special_function */
860 "R_ARM_THM_PC12", /* name */
861 FALSE, /* partial_inplace */
2cab6cc3
MS		 862 0xffffffff, /* src_mask */
863 0xffffffff, /* dst_mask */
c19d1205
ZW		 864 TRUE), /* pcrel_offset */
865
866 HOWTO (R_ARM_ABS32_NOI, /* type */
867 0, /* rightshift */
868 2, /* size (0 = byte, 1 = short, 2 = long) */
869 32, /* bitsize */
870 FALSE, /* pc_relative */
871 0, /* bitpos */
872 complain_overflow_dont,/* complain_on_overflow */
873 bfd_elf_generic_reloc, /* special_function */
874 "R_ARM_ABS32_NOI", /* name */
875 FALSE, /* partial_inplace */
876 0xffffffff, /* src_mask */
877 0xffffffff, /* dst_mask */
878 FALSE), /* pcrel_offset */
879
880 HOWTO (R_ARM_REL32_NOI, /* type */
881 0, /* rightshift */
882 2, /* size (0 = byte, 1 = short, 2 = long) */
883 32, /* bitsize */
884 TRUE, /* pc_relative */
885 0, /* bitpos */
886 complain_overflow_dont,/* complain_on_overflow */
887 bfd_elf_generic_reloc, /* special_function */
888 "R_ARM_REL32_NOI", /* name */
889 FALSE, /* partial_inplace */
890 0xffffffff, /* src_mask */
891 0xffffffff, /* dst_mask */
892 FALSE), /* pcrel_offset */
7f266840 893
4962c51a
MS		 894 /* Group relocations. */
895
896 HOWTO (R_ARM_ALU_PC_G0_NC, /* type */
897 0, /* rightshift */
898 2, /* size (0 = byte, 1 = short, 2 = long) */
899 32, /* bitsize */
900 TRUE, /* pc_relative */
901 0, /* bitpos */
902 complain_overflow_dont,/* complain_on_overflow */
903 bfd_elf_generic_reloc, /* special_function */
904 "R_ARM_ALU_PC_G0_NC", /* name */
905 FALSE, /* partial_inplace */
906 0xffffffff, /* src_mask */
907 0xffffffff, /* dst_mask */
908 TRUE), /* pcrel_offset */
909
07d6d2b8 910 HOWTO (R_ARM_ALU_PC_G0, /* type */
4962c51a
MS		 911 0, /* rightshift */
912 2, /* size (0 = byte, 1 = short, 2 = long) */
913 32, /* bitsize */
914 TRUE, /* pc_relative */
915 0, /* bitpos */
916 complain_overflow_dont,/* complain_on_overflow */
917 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 918 "R_ARM_ALU_PC_G0", /* name */
4962c51a
MS		 919 FALSE, /* partial_inplace */
920 0xffffffff, /* src_mask */
921 0xffffffff, /* dst_mask */
922 TRUE), /* pcrel_offset */
923
924 HOWTO (R_ARM_ALU_PC_G1_NC, /* type */
925 0, /* rightshift */
926 2, /* size (0 = byte, 1 = short, 2 = long) */
927 32, /* bitsize */
928 TRUE, /* pc_relative */
929 0, /* bitpos */
930 complain_overflow_dont,/* complain_on_overflow */
931 bfd_elf_generic_reloc, /* special_function */
932 "R_ARM_ALU_PC_G1_NC", /* name */
933 FALSE, /* partial_inplace */
934 0xffffffff, /* src_mask */
935 0xffffffff, /* dst_mask */
936 TRUE), /* pcrel_offset */
937
07d6d2b8 938 HOWTO (R_ARM_ALU_PC_G1, /* type */
4962c51a
MS		 939 0, /* rightshift */
940 2, /* size (0 = byte, 1 = short, 2 = long) */
941 32, /* bitsize */
942 TRUE, /* pc_relative */
943 0, /* bitpos */
944 complain_overflow_dont,/* complain_on_overflow */
945 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 946 "R_ARM_ALU_PC_G1", /* name */
4962c51a
MS		 947 FALSE, /* partial_inplace */
948 0xffffffff, /* src_mask */
949 0xffffffff, /* dst_mask */
950 TRUE), /* pcrel_offset */
951
07d6d2b8 952 HOWTO (R_ARM_ALU_PC_G2, /* type */
4962c51a
MS		 953 0, /* rightshift */
954 2, /* size (0 = byte, 1 = short, 2 = long) */
955 32, /* bitsize */
956 TRUE, /* pc_relative */
957 0, /* bitpos */
958 complain_overflow_dont,/* complain_on_overflow */
959 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 960 "R_ARM_ALU_PC_G2", /* name */
4962c51a
MS		 961 FALSE, /* partial_inplace */
962 0xffffffff, /* src_mask */
963 0xffffffff, /* dst_mask */
964 TRUE), /* pcrel_offset */
965
07d6d2b8 966 HOWTO (R_ARM_LDR_PC_G1, /* type */
4962c51a
MS		 967 0, /* rightshift */
968 2, /* size (0 = byte, 1 = short, 2 = long) */
969 32, /* bitsize */
970 TRUE, /* pc_relative */
971 0, /* bitpos */
972 complain_overflow_dont,/* complain_on_overflow */
973 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 974 "R_ARM_LDR_PC_G1", /* name */
4962c51a
MS		 975 FALSE, /* partial_inplace */
976 0xffffffff, /* src_mask */
977 0xffffffff, /* dst_mask */
978 TRUE), /* pcrel_offset */
979
07d6d2b8 980 HOWTO (R_ARM_LDR_PC_G2, /* type */
4962c51a
MS		 981 0, /* rightshift */
982 2, /* size (0 = byte, 1 = short, 2 = long) */
983 32, /* bitsize */
984 TRUE, /* pc_relative */
985 0, /* bitpos */
986 complain_overflow_dont,/* complain_on_overflow */
987 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 988 "R_ARM_LDR_PC_G2", /* name */
4962c51a
MS		 989 FALSE, /* partial_inplace */
990 0xffffffff, /* src_mask */
991 0xffffffff, /* dst_mask */
992 TRUE), /* pcrel_offset */
993
07d6d2b8 994 HOWTO (R_ARM_LDRS_PC_G0, /* type */
4962c51a
MS		 995 0, /* rightshift */
996 2, /* size (0 = byte, 1 = short, 2 = long) */
997 32, /* bitsize */
998 TRUE, /* pc_relative */
999 0, /* bitpos */
1000 complain_overflow_dont,/* complain_on_overflow */
1001 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1002 "R_ARM_LDRS_PC_G0", /* name */
4962c51a
MS		 1003 FALSE, /* partial_inplace */
1004 0xffffffff, /* src_mask */
1005 0xffffffff, /* dst_mask */
1006 TRUE), /* pcrel_offset */
1007
07d6d2b8 1008 HOWTO (R_ARM_LDRS_PC_G1, /* type */
4962c51a
MS		 1009 0, /* rightshift */
1010 2, /* size (0 = byte, 1 = short, 2 = long) */
1011 32, /* bitsize */
1012 TRUE, /* pc_relative */
1013 0, /* bitpos */
1014 complain_overflow_dont,/* complain_on_overflow */
1015 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1016 "R_ARM_LDRS_PC_G1", /* name */
4962c51a
MS		 1017 FALSE, /* partial_inplace */
1018 0xffffffff, /* src_mask */
1019 0xffffffff, /* dst_mask */
1020 TRUE), /* pcrel_offset */
1021
07d6d2b8 1022 HOWTO (R_ARM_LDRS_PC_G2, /* type */
4962c51a
MS		 1023 0, /* rightshift */
1024 2, /* size (0 = byte, 1 = short, 2 = long) */
1025 32, /* bitsize */
1026 TRUE, /* pc_relative */
1027 0, /* bitpos */
1028 complain_overflow_dont,/* complain_on_overflow */
1029 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1030 "R_ARM_LDRS_PC_G2", /* name */
4962c51a
MS		 1031 FALSE, /* partial_inplace */
1032 0xffffffff, /* src_mask */
1033 0xffffffff, /* dst_mask */
1034 TRUE), /* pcrel_offset */
1035
07d6d2b8 1036 HOWTO (R_ARM_LDC_PC_G0, /* type */
4962c51a
MS		 1037 0, /* rightshift */
1038 2, /* size (0 = byte, 1 = short, 2 = long) */
1039 32, /* bitsize */
1040 TRUE, /* pc_relative */
1041 0, /* bitpos */
1042 complain_overflow_dont,/* complain_on_overflow */
1043 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1044 "R_ARM_LDC_PC_G0", /* name */
4962c51a
MS		 1045 FALSE, /* partial_inplace */
1046 0xffffffff, /* src_mask */
1047 0xffffffff, /* dst_mask */
1048 TRUE), /* pcrel_offset */
1049
07d6d2b8 1050 HOWTO (R_ARM_LDC_PC_G1, /* type */
4962c51a
MS		 1051 0, /* rightshift */
1052 2, /* size (0 = byte, 1 = short, 2 = long) */
1053 32, /* bitsize */
1054 TRUE, /* pc_relative */
1055 0, /* bitpos */
1056 complain_overflow_dont,/* complain_on_overflow */
1057 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1058 "R_ARM_LDC_PC_G1", /* name */
4962c51a
MS		 1059 FALSE, /* partial_inplace */
1060 0xffffffff, /* src_mask */
1061 0xffffffff, /* dst_mask */
1062 TRUE), /* pcrel_offset */
1063
07d6d2b8 1064 HOWTO (R_ARM_LDC_PC_G2, /* type */
4962c51a
MS		 1065 0, /* rightshift */
1066 2, /* size (0 = byte, 1 = short, 2 = long) */
1067 32, /* bitsize */
1068 TRUE, /* pc_relative */
1069 0, /* bitpos */
1070 complain_overflow_dont,/* complain_on_overflow */
1071 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1072 "R_ARM_LDC_PC_G2", /* name */
4962c51a
MS		 1073 FALSE, /* partial_inplace */
1074 0xffffffff, /* src_mask */
1075 0xffffffff, /* dst_mask */
1076 TRUE), /* pcrel_offset */
1077
07d6d2b8 1078 HOWTO (R_ARM_ALU_SB_G0_NC, /* type */
4962c51a
MS		 1079 0, /* rightshift */
1080 2, /* size (0 = byte, 1 = short, 2 = long) */
1081 32, /* bitsize */
1082 TRUE, /* pc_relative */
1083 0, /* bitpos */
1084 complain_overflow_dont,/* complain_on_overflow */
1085 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1086 "R_ARM_ALU_SB_G0_NC", /* name */
4962c51a
MS		 1087 FALSE, /* partial_inplace */
1088 0xffffffff, /* src_mask */
1089 0xffffffff, /* dst_mask */
1090 TRUE), /* pcrel_offset */
1091
07d6d2b8 1092 HOWTO (R_ARM_ALU_SB_G0, /* type */
4962c51a
MS		 1093 0, /* rightshift */
1094 2, /* size (0 = byte, 1 = short, 2 = long) */
1095 32, /* bitsize */
1096 TRUE, /* pc_relative */
1097 0, /* bitpos */
1098 complain_overflow_dont,/* complain_on_overflow */
1099 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1100 "R_ARM_ALU_SB_G0", /* name */
4962c51a
MS		 1101 FALSE, /* partial_inplace */
1102 0xffffffff, /* src_mask */
1103 0xffffffff, /* dst_mask */
1104 TRUE), /* pcrel_offset */
1105
07d6d2b8 1106 HOWTO (R_ARM_ALU_SB_G1_NC, /* type */
4962c51a
MS		 1107 0, /* rightshift */
1108 2, /* size (0 = byte, 1 = short, 2 = long) */
1109 32, /* bitsize */
1110 TRUE, /* pc_relative */
1111 0, /* bitpos */
1112 complain_overflow_dont,/* complain_on_overflow */
1113 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1114 "R_ARM_ALU_SB_G1_NC", /* name */
4962c51a
MS		 1115 FALSE, /* partial_inplace */
1116 0xffffffff, /* src_mask */
1117 0xffffffff, /* dst_mask */
1118 TRUE), /* pcrel_offset */
1119
07d6d2b8 1120 HOWTO (R_ARM_ALU_SB_G1, /* type */
4962c51a
MS		 1121 0, /* rightshift */
1122 2, /* size (0 = byte, 1 = short, 2 = long) */
1123 32, /* bitsize */
1124 TRUE, /* pc_relative */
1125 0, /* bitpos */
1126 complain_overflow_dont,/* complain_on_overflow */
1127 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1128 "R_ARM_ALU_SB_G1", /* name */
4962c51a
MS		 1129 FALSE, /* partial_inplace */
1130 0xffffffff, /* src_mask */
1131 0xffffffff, /* dst_mask */
1132 TRUE), /* pcrel_offset */
1133
07d6d2b8 1134 HOWTO (R_ARM_ALU_SB_G2, /* type */
4962c51a
MS		 1135 0, /* rightshift */
1136 2, /* size (0 = byte, 1 = short, 2 = long) */
1137 32, /* bitsize */
1138 TRUE, /* pc_relative */
1139 0, /* bitpos */
1140 complain_overflow_dont,/* complain_on_overflow */
1141 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1142 "R_ARM_ALU_SB_G2", /* name */
4962c51a
MS		 1143 FALSE, /* partial_inplace */
1144 0xffffffff, /* src_mask */
1145 0xffffffff, /* dst_mask */
1146 TRUE), /* pcrel_offset */
1147
07d6d2b8 1148 HOWTO (R_ARM_LDR_SB_G0, /* type */
4962c51a
MS		 1149 0, /* rightshift */
1150 2, /* size (0 = byte, 1 = short, 2 = long) */
1151 32, /* bitsize */
1152 TRUE, /* pc_relative */
1153 0, /* bitpos */
1154 complain_overflow_dont,/* complain_on_overflow */
1155 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1156 "R_ARM_LDR_SB_G0", /* name */
4962c51a
MS		 1157 FALSE, /* partial_inplace */
1158 0xffffffff, /* src_mask */
1159 0xffffffff, /* dst_mask */
1160 TRUE), /* pcrel_offset */
1161
07d6d2b8 1162 HOWTO (R_ARM_LDR_SB_G1, /* type */
4962c51a
MS		 1163 0, /* rightshift */
1164 2, /* size (0 = byte, 1 = short, 2 = long) */
1165 32, /* bitsize */
1166 TRUE, /* pc_relative */
1167 0, /* bitpos */
1168 complain_overflow_dont,/* complain_on_overflow */
1169 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1170 "R_ARM_LDR_SB_G1", /* name */
4962c51a
MS		 1171 FALSE, /* partial_inplace */
1172 0xffffffff, /* src_mask */
1173 0xffffffff, /* dst_mask */
1174 TRUE), /* pcrel_offset */
1175
07d6d2b8 1176 HOWTO (R_ARM_LDR_SB_G2, /* type */
4962c51a
MS		 1177 0, /* rightshift */
1178 2, /* size (0 = byte, 1 = short, 2 = long) */
1179 32, /* bitsize */
1180 TRUE, /* pc_relative */
1181 0, /* bitpos */
1182 complain_overflow_dont,/* complain_on_overflow */
1183 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1184 "R_ARM_LDR_SB_G2", /* name */
4962c51a
MS		 1185 FALSE, /* partial_inplace */
1186 0xffffffff, /* src_mask */
1187 0xffffffff, /* dst_mask */
1188 TRUE), /* pcrel_offset */
1189
07d6d2b8 1190 HOWTO (R_ARM_LDRS_SB_G0, /* type */
4962c51a
MS		 1191 0, /* rightshift */
1192 2, /* size (0 = byte, 1 = short, 2 = long) */
1193 32, /* bitsize */
1194 TRUE, /* pc_relative */
1195 0, /* bitpos */
1196 complain_overflow_dont,/* complain_on_overflow */
1197 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1198 "R_ARM_LDRS_SB_G0", /* name */
4962c51a
MS		 1199 FALSE, /* partial_inplace */
1200 0xffffffff, /* src_mask */
1201 0xffffffff, /* dst_mask */
1202 TRUE), /* pcrel_offset */
1203
07d6d2b8 1204 HOWTO (R_ARM_LDRS_SB_G1, /* type */
4962c51a
MS		 1205 0, /* rightshift */
1206 2, /* size (0 = byte, 1 = short, 2 = long) */
1207 32, /* bitsize */
1208 TRUE, /* pc_relative */
1209 0, /* bitpos */
1210 complain_overflow_dont,/* complain_on_overflow */
1211 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1212 "R_ARM_LDRS_SB_G1", /* name */
4962c51a
MS		 1213 FALSE, /* partial_inplace */
1214 0xffffffff, /* src_mask */
1215 0xffffffff, /* dst_mask */
1216 TRUE), /* pcrel_offset */
1217
07d6d2b8 1218 HOWTO (R_ARM_LDRS_SB_G2, /* type */
4962c51a
MS		 1219 0, /* rightshift */
1220 2, /* size (0 = byte, 1 = short, 2 = long) */
1221 32, /* bitsize */
1222 TRUE, /* pc_relative */
1223 0, /* bitpos */
1224 complain_overflow_dont,/* complain_on_overflow */
1225 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1226 "R_ARM_LDRS_SB_G2", /* name */
4962c51a
MS		 1227 FALSE, /* partial_inplace */
1228 0xffffffff, /* src_mask */
1229 0xffffffff, /* dst_mask */
1230 TRUE), /* pcrel_offset */
1231
07d6d2b8 1232 HOWTO (R_ARM_LDC_SB_G0, /* type */
4962c51a
MS		 1233 0, /* rightshift */
1234 2, /* size (0 = byte, 1 = short, 2 = long) */
1235 32, /* bitsize */
1236 TRUE, /* pc_relative */
1237 0, /* bitpos */
1238 complain_overflow_dont,/* complain_on_overflow */
1239 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1240 "R_ARM_LDC_SB_G0", /* name */
4962c51a
MS		 1241 FALSE, /* partial_inplace */
1242 0xffffffff, /* src_mask */
1243 0xffffffff, /* dst_mask */
1244 TRUE), /* pcrel_offset */
1245
07d6d2b8 1246 HOWTO (R_ARM_LDC_SB_G1, /* type */
4962c51a
MS		 1247 0, /* rightshift */
1248 2, /* size (0 = byte, 1 = short, 2 = long) */
1249 32, /* bitsize */
1250 TRUE, /* pc_relative */
1251 0, /* bitpos */
1252 complain_overflow_dont,/* complain_on_overflow */
1253 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1254 "R_ARM_LDC_SB_G1", /* name */
4962c51a
MS		 1255 FALSE, /* partial_inplace */
1256 0xffffffff, /* src_mask */
1257 0xffffffff, /* dst_mask */
1258 TRUE), /* pcrel_offset */
1259
07d6d2b8 1260 HOWTO (R_ARM_LDC_SB_G2, /* type */
4962c51a
MS		 1261 0, /* rightshift */
1262 2, /* size (0 = byte, 1 = short, 2 = long) */
1263 32, /* bitsize */
1264 TRUE, /* pc_relative */
1265 0, /* bitpos */
1266 complain_overflow_dont,/* complain_on_overflow */
1267 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1268 "R_ARM_LDC_SB_G2", /* name */
4962c51a
MS		 1269 FALSE, /* partial_inplace */
1270 0xffffffff, /* src_mask */
1271 0xffffffff, /* dst_mask */
1272 TRUE), /* pcrel_offset */
1273
1274 /* End of group relocations. */
c19d1205 1275
c19d1205
ZW		 1276 HOWTO (R_ARM_MOVW_BREL_NC, /* type */
1277 0, /* rightshift */
1278 2, /* size (0 = byte, 1 = short, 2 = long) */
1279 16, /* bitsize */
1280 FALSE, /* pc_relative */
1281 0, /* bitpos */
1282 complain_overflow_dont,/* complain_on_overflow */
1283 bfd_elf_generic_reloc, /* special_function */
1284 "R_ARM_MOVW_BREL_NC", /* name */
1285 FALSE, /* partial_inplace */
1286 0x0000ffff, /* src_mask */
1287 0x0000ffff, /* dst_mask */
1288 FALSE), /* pcrel_offset */
1289
1290 HOWTO (R_ARM_MOVT_BREL, /* type */
1291 0, /* rightshift */
1292 2, /* size (0 = byte, 1 = short, 2 = long) */
1293 16, /* bitsize */
1294 FALSE, /* pc_relative */
1295 0, /* bitpos */
1296 complain_overflow_bitfield,/* complain_on_overflow */
1297 bfd_elf_generic_reloc, /* special_function */
1298 "R_ARM_MOVT_BREL", /* name */
1299 FALSE, /* partial_inplace */
1300 0x0000ffff, /* src_mask */
1301 0x0000ffff, /* dst_mask */
1302 FALSE), /* pcrel_offset */
1303
1304 HOWTO (R_ARM_MOVW_BREL, /* type */
1305 0, /* rightshift */
1306 2, /* size (0 = byte, 1 = short, 2 = long) */
1307 16, /* bitsize */
1308 FALSE, /* pc_relative */
1309 0, /* bitpos */
1310 complain_overflow_dont,/* complain_on_overflow */
1311 bfd_elf_generic_reloc, /* special_function */
1312 "R_ARM_MOVW_BREL", /* name */
1313 FALSE, /* partial_inplace */
1314 0x0000ffff, /* src_mask */
1315 0x0000ffff, /* dst_mask */
1316 FALSE), /* pcrel_offset */
1317
1318 HOWTO (R_ARM_THM_MOVW_BREL_NC,/* type */
1319 0, /* rightshift */
1320 2, /* size (0 = byte, 1 = short, 2 = long) */
1321 16, /* bitsize */
1322 FALSE, /* pc_relative */
1323 0, /* bitpos */
1324 complain_overflow_dont,/* complain_on_overflow */
1325 bfd_elf_generic_reloc, /* special_function */
1326 "R_ARM_THM_MOVW_BREL_NC",/* name */
1327 FALSE, /* partial_inplace */
1328 0x040f70ff, /* src_mask */
1329 0x040f70ff, /* dst_mask */
1330 FALSE), /* pcrel_offset */
1331
1332 HOWTO (R_ARM_THM_MOVT_BREL, /* type */
1333 0, /* rightshift */
1334 2, /* size (0 = byte, 1 = short, 2 = long) */
1335 16, /* bitsize */
1336 FALSE, /* pc_relative */
1337 0, /* bitpos */
1338 complain_overflow_bitfield,/* complain_on_overflow */
1339 bfd_elf_generic_reloc, /* special_function */
1340 "R_ARM_THM_MOVT_BREL", /* name */
1341 FALSE, /* partial_inplace */
1342 0x040f70ff, /* src_mask */
1343 0x040f70ff, /* dst_mask */
1344 FALSE), /* pcrel_offset */
1345
1346 HOWTO (R_ARM_THM_MOVW_BREL, /* type */
1347 0, /* rightshift */
1348 2, /* size (0 = byte, 1 = short, 2 = long) */
1349 16, /* bitsize */
1350 FALSE, /* pc_relative */
1351 0, /* bitpos */
1352 complain_overflow_dont,/* complain_on_overflow */
1353 bfd_elf_generic_reloc, /* special_function */
1354 "R_ARM_THM_MOVW_BREL", /* name */
1355 FALSE, /* partial_inplace */
1356 0x040f70ff, /* src_mask */
1357 0x040f70ff, /* dst_mask */
1358 FALSE), /* pcrel_offset */
1359
0855e32b
NS		 1360 HOWTO (R_ARM_TLS_GOTDESC, /* type */
1361 0, /* rightshift */
1362 2, /* size (0 = byte, 1 = short, 2 = long) */
1363 32, /* bitsize */
1364 FALSE, /* pc_relative */
1365 0, /* bitpos */
1366 complain_overflow_bitfield,/* complain_on_overflow */
1367 NULL, /* special_function */
1368 "R_ARM_TLS_GOTDESC", /* name */
1369 TRUE, /* partial_inplace */
1370 0xffffffff, /* src_mask */
1371 0xffffffff, /* dst_mask */
1372 FALSE), /* pcrel_offset */
1373
1374 HOWTO (R_ARM_TLS_CALL, /* type */
1375 0, /* rightshift */
1376 2, /* size (0 = byte, 1 = short, 2 = long) */
1377 24, /* bitsize */
1378 FALSE, /* pc_relative */
1379 0, /* bitpos */
1380 complain_overflow_dont,/* complain_on_overflow */
1381 bfd_elf_generic_reloc, /* special_function */
1382 "R_ARM_TLS_CALL", /* name */
1383 FALSE, /* partial_inplace */
1384 0x00ffffff, /* src_mask */
1385 0x00ffffff, /* dst_mask */
1386 FALSE), /* pcrel_offset */
1387
1388 HOWTO (R_ARM_TLS_DESCSEQ, /* type */
1389 0, /* rightshift */
1390 2, /* size (0 = byte, 1 = short, 2 = long) */
1391 0, /* bitsize */
1392 FALSE, /* pc_relative */
1393 0, /* bitpos */
1394 complain_overflow_bitfield,/* complain_on_overflow */
1395 bfd_elf_generic_reloc, /* special_function */
1396 "R_ARM_TLS_DESCSEQ", /* name */
1397 FALSE, /* partial_inplace */
1398 0x00000000, /* src_mask */
1399 0x00000000, /* dst_mask */
1400 FALSE), /* pcrel_offset */
1401
1402 HOWTO (R_ARM_THM_TLS_CALL, /* type */
1403 0, /* rightshift */
1404 2, /* size (0 = byte, 1 = short, 2 = long) */
1405 24, /* bitsize */
1406 FALSE, /* pc_relative */
1407 0, /* bitpos */
1408 complain_overflow_dont,/* complain_on_overflow */
1409 bfd_elf_generic_reloc, /* special_function */
1410 "R_ARM_THM_TLS_CALL", /* name */
1411 FALSE, /* partial_inplace */
1412 0x07ff07ff, /* src_mask */
1413 0x07ff07ff, /* dst_mask */
1414 FALSE), /* pcrel_offset */
c19d1205
ZW		 1415
1416 HOWTO (R_ARM_PLT32_ABS, /* type */
1417 0, /* rightshift */
1418 2, /* size (0 = byte, 1 = short, 2 = long) */
1419 32, /* bitsize */
1420 FALSE, /* pc_relative */
1421 0, /* bitpos */
1422 complain_overflow_dont,/* complain_on_overflow */
1423 bfd_elf_generic_reloc, /* special_function */
1424 "R_ARM_PLT32_ABS", /* name */
1425 FALSE, /* partial_inplace */
1426 0xffffffff, /* src_mask */
1427 0xffffffff, /* dst_mask */
1428 FALSE), /* pcrel_offset */
1429
1430 HOWTO (R_ARM_GOT_ABS, /* type */
1431 0, /* rightshift */
1432 2, /* size (0 = byte, 1 = short, 2 = long) */
1433 32, /* bitsize */
1434 FALSE, /* pc_relative */
1435 0, /* bitpos */
1436 complain_overflow_dont,/* complain_on_overflow */
1437 bfd_elf_generic_reloc, /* special_function */
1438 "R_ARM_GOT_ABS", /* name */
1439 FALSE, /* partial_inplace */
1440 0xffffffff, /* src_mask */
1441 0xffffffff, /* dst_mask */
1442 FALSE), /* pcrel_offset */
1443
1444 HOWTO (R_ARM_GOT_PREL, /* type */
1445 0, /* rightshift */
1446 2, /* size (0 = byte, 1 = short, 2 = long) */
1447 32, /* bitsize */
1448 TRUE, /* pc_relative */
1449 0, /* bitpos */
1450 complain_overflow_dont, /* complain_on_overflow */
1451 bfd_elf_generic_reloc, /* special_function */
1452 "R_ARM_GOT_PREL", /* name */
1453 FALSE, /* partial_inplace */
1454 0xffffffff, /* src_mask */
1455 0xffffffff, /* dst_mask */
1456 TRUE), /* pcrel_offset */
1457
1458 HOWTO (R_ARM_GOT_BREL12, /* type */
1459 0, /* rightshift */
1460 2, /* size (0 = byte, 1 = short, 2 = long) */
1461 12, /* bitsize */
1462 FALSE, /* pc_relative */
1463 0, /* bitpos */
1464 complain_overflow_bitfield,/* complain_on_overflow */
1465 bfd_elf_generic_reloc, /* special_function */
1466 "R_ARM_GOT_BREL12", /* name */
1467 FALSE, /* partial_inplace */
1468 0x00000fff, /* src_mask */
1469 0x00000fff, /* dst_mask */
1470 FALSE), /* pcrel_offset */
1471
1472 HOWTO (R_ARM_GOTOFF12, /* type */
1473 0, /* rightshift */
1474 2, /* size (0 = byte, 1 = short, 2 = long) */
1475 12, /* bitsize */
1476 FALSE, /* pc_relative */
1477 0, /* bitpos */
1478 complain_overflow_bitfield,/* complain_on_overflow */
1479 bfd_elf_generic_reloc, /* special_function */
1480 "R_ARM_GOTOFF12", /* name */
1481 FALSE, /* partial_inplace */
1482 0x00000fff, /* src_mask */
1483 0x00000fff, /* dst_mask */
1484 FALSE), /* pcrel_offset */
1485
07d6d2b8 1486 EMPTY_HOWTO (R_ARM_GOTRELAX), /* reserved for future GOT-load optimizations */
c19d1205
ZW		 1487
1488 /* GNU extension to record C++ vtable member usage */
07d6d2b8
AM		 1489 HOWTO (R_ARM_GNU_VTENTRY, /* type */
1490 0, /* rightshift */
1491 2, /* size (0 = byte, 1 = short, 2 = long) */
1492 0, /* bitsize */
1493 FALSE, /* pc_relative */
1494 0, /* bitpos */
99059e56 1495 complain_overflow_dont, /* complain_on_overflow */
07d6d2b8
AM		 1496 _bfd_elf_rel_vtable_reloc_fn, /* special_function */
1497 "R_ARM_GNU_VTENTRY", /* name */
1498 FALSE, /* partial_inplace */
1499 0, /* src_mask */
1500 0, /* dst_mask */
1501 FALSE), /* pcrel_offset */
c19d1205
ZW		 1502
1503 /* GNU extension to record C++ vtable hierarchy */
1504 HOWTO (R_ARM_GNU_VTINHERIT, /* type */
07d6d2b8
AM		 1505 0, /* rightshift */
1506 2, /* size (0 = byte, 1 = short, 2 = long) */
1507 0, /* bitsize */
1508 FALSE, /* pc_relative */
1509 0, /* bitpos */
99059e56 1510 complain_overflow_dont, /* complain_on_overflow */
07d6d2b8 1511 NULL, /* special_function */
99059e56 1512 "R_ARM_GNU_VTINHERIT", /* name */
07d6d2b8
AM		 1513 FALSE, /* partial_inplace */
1514 0, /* src_mask */
1515 0, /* dst_mask */
1516 FALSE), /* pcrel_offset */
c19d1205
ZW		 1517
1518 HOWTO (R_ARM_THM_JUMP11, /* type */
1519 1, /* rightshift */
1520 1, /* size (0 = byte, 1 = short, 2 = long) */
1521 11, /* bitsize */
1522 TRUE, /* pc_relative */
1523 0, /* bitpos */
1524 complain_overflow_signed, /* complain_on_overflow */
1525 bfd_elf_generic_reloc, /* special_function */
1526 "R_ARM_THM_JUMP11", /* name */
1527 FALSE, /* partial_inplace */
1528 0x000007ff, /* src_mask */
1529 0x000007ff, /* dst_mask */
1530 TRUE), /* pcrel_offset */
1531
1532 HOWTO (R_ARM_THM_JUMP8, /* type */
1533 1, /* rightshift */
1534 1, /* size (0 = byte, 1 = short, 2 = long) */
1535 8, /* bitsize */
1536 TRUE, /* pc_relative */
1537 0, /* bitpos */
1538 complain_overflow_signed, /* complain_on_overflow */
1539 bfd_elf_generic_reloc, /* special_function */
1540 "R_ARM_THM_JUMP8", /* name */
1541 FALSE, /* partial_inplace */
1542 0x000000ff, /* src_mask */
1543 0x000000ff, /* dst_mask */
1544 TRUE), /* pcrel_offset */
ba93b8ac 1545
c19d1205
ZW		 1546 /* TLS relocations */
1547 HOWTO (R_ARM_TLS_GD32, /* type */
07d6d2b8
AM		 1548 0, /* rightshift */
1549 2, /* size (0 = byte, 1 = short, 2 = long) */
1550 32, /* bitsize */
1551 FALSE, /* pc_relative */
1552 0, /* bitpos */
99059e56
RM		 1553 complain_overflow_bitfield,/* complain_on_overflow */
1554 NULL, /* special_function */
1555 "R_ARM_TLS_GD32", /* name */
1556 TRUE, /* partial_inplace */
1557 0xffffffff, /* src_mask */
1558 0xffffffff, /* dst_mask */
07d6d2b8 1559 FALSE), /* pcrel_offset */
ba93b8ac 1560
ba93b8ac 1561 HOWTO (R_ARM_TLS_LDM32, /* type */
07d6d2b8
AM		 1562 0, /* rightshift */
1563 2, /* size (0 = byte, 1 = short, 2 = long) */
1564 32, /* bitsize */
1565 FALSE, /* pc_relative */
1566 0, /* bitpos */
99059e56
RM		 1567 complain_overflow_bitfield,/* complain_on_overflow */
1568 bfd_elf_generic_reloc, /* special_function */
1569 "R_ARM_TLS_LDM32", /* name */
1570 TRUE, /* partial_inplace */
1571 0xffffffff, /* src_mask */
1572 0xffffffff, /* dst_mask */
07d6d2b8 1573 FALSE), /* pcrel_offset */
ba93b8ac 1574
c19d1205 1575 HOWTO (R_ARM_TLS_LDO32, /* type */
07d6d2b8
AM		 1576 0, /* rightshift */
1577 2, /* size (0 = byte, 1 = short, 2 = long) */
1578 32, /* bitsize */
1579 FALSE, /* pc_relative */
1580 0, /* bitpos */
99059e56
RM		 1581 complain_overflow_bitfield,/* complain_on_overflow */
1582 bfd_elf_generic_reloc, /* special_function */
1583 "R_ARM_TLS_LDO32", /* name */
1584 TRUE, /* partial_inplace */
1585 0xffffffff, /* src_mask */
1586 0xffffffff, /* dst_mask */
07d6d2b8 1587 FALSE), /* pcrel_offset */
ba93b8ac 1588
ba93b8ac 1589 HOWTO (R_ARM_TLS_IE32, /* type */
07d6d2b8
AM		 1590 0, /* rightshift */
1591 2, /* size (0 = byte, 1 = short, 2 = long) */
1592 32, /* bitsize */
1593 FALSE, /* pc_relative */
1594 0, /* bitpos */
99059e56
RM		 1595 complain_overflow_bitfield,/* complain_on_overflow */
1596 NULL, /* special_function */
1597 "R_ARM_TLS_IE32", /* name */
1598 TRUE, /* partial_inplace */
1599 0xffffffff, /* src_mask */
1600 0xffffffff, /* dst_mask */
07d6d2b8 1601 FALSE), /* pcrel_offset */
7f266840 1602
c19d1205 1603 HOWTO (R_ARM_TLS_LE32, /* type */
07d6d2b8
AM		 1604 0, /* rightshift */
1605 2, /* size (0 = byte, 1 = short, 2 = long) */
1606 32, /* bitsize */
1607 FALSE, /* pc_relative */
1608 0, /* bitpos */
99059e56 1609 complain_overflow_bitfield,/* complain_on_overflow */
07d6d2b8 1610 NULL, /* special_function */
99059e56
RM		 1611 "R_ARM_TLS_LE32", /* name */
1612 TRUE, /* partial_inplace */
1613 0xffffffff, /* src_mask */
1614 0xffffffff, /* dst_mask */
07d6d2b8 1615 FALSE), /* pcrel_offset */
7f266840 1616
c19d1205
ZW		 1617 HOWTO (R_ARM_TLS_LDO12, /* type */
1618 0, /* rightshift */
1619 2, /* size (0 = byte, 1 = short, 2 = long) */
1620 12, /* bitsize */
1621 FALSE, /* pc_relative */
7f266840 1622 0, /* bitpos */
c19d1205 1623 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1624 bfd_elf_generic_reloc, /* special_function */
c19d1205 1625 "R_ARM_TLS_LDO12", /* name */
7f266840 1626 FALSE, /* partial_inplace */
c19d1205
ZW		 1627 0x00000fff, /* src_mask */
1628 0x00000fff, /* dst_mask */
1629 FALSE), /* pcrel_offset */
7f266840 1630
c19d1205
ZW		 1631 HOWTO (R_ARM_TLS_LE12, /* type */
1632 0, /* rightshift */
1633 2, /* size (0 = byte, 1 = short, 2 = long) */
1634 12, /* bitsize */
1635 FALSE, /* pc_relative */
7f266840 1636 0, /* bitpos */
c19d1205 1637 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1638 bfd_elf_generic_reloc, /* special_function */
c19d1205 1639 "R_ARM_TLS_LE12", /* name */
7f266840 1640 FALSE, /* partial_inplace */
c19d1205
ZW		 1641 0x00000fff, /* src_mask */
1642 0x00000fff, /* dst_mask */
1643 FALSE), /* pcrel_offset */
7f266840 1644
c19d1205 1645 HOWTO (R_ARM_TLS_IE12GP, /* type */
7f266840
DJ		 1646 0, /* rightshift */
1647 2, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 1648 12, /* bitsize */
1649 FALSE, /* pc_relative */
7f266840 1650 0, /* bitpos */
c19d1205 1651 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1652 bfd_elf_generic_reloc, /* special_function */
c19d1205 1653 "R_ARM_TLS_IE12GP", /* name */
7f266840 1654 FALSE, /* partial_inplace */
c19d1205
ZW		 1655 0x00000fff, /* src_mask */
1656 0x00000fff, /* dst_mask */
1657 FALSE), /* pcrel_offset */
0855e32b 1658
34e77a92 1659 /* 112-127 private relocations. */
0855e32b
NS		 1660 EMPTY_HOWTO (112),
1661 EMPTY_HOWTO (113),
1662 EMPTY_HOWTO (114),
1663 EMPTY_HOWTO (115),
1664 EMPTY_HOWTO (116),
1665 EMPTY_HOWTO (117),
1666 EMPTY_HOWTO (118),
1667 EMPTY_HOWTO (119),
1668 EMPTY_HOWTO (120),
1669 EMPTY_HOWTO (121),
1670 EMPTY_HOWTO (122),
1671 EMPTY_HOWTO (123),
1672 EMPTY_HOWTO (124),
1673 EMPTY_HOWTO (125),
1674 EMPTY_HOWTO (126),
1675 EMPTY_HOWTO (127),
34e77a92
RS		 1676
1677 /* R_ARM_ME_TOO, obsolete. */
0855e32b
NS		 1678 EMPTY_HOWTO (128),
1679
1680 HOWTO (R_ARM_THM_TLS_DESCSEQ, /* type */
1681 0, /* rightshift */
1682 1, /* size (0 = byte, 1 = short, 2 = long) */
1683 0, /* bitsize */
1684 FALSE, /* pc_relative */
1685 0, /* bitpos */
1686 complain_overflow_bitfield,/* complain_on_overflow */
1687 bfd_elf_generic_reloc, /* special_function */
1688 "R_ARM_THM_TLS_DESCSEQ",/* name */
1689 FALSE, /* partial_inplace */
1690 0x00000000, /* src_mask */
1691 0x00000000, /* dst_mask */
1692 FALSE), /* pcrel_offset */
72d98d16
MG		 1693 EMPTY_HOWTO (130),
1694 EMPTY_HOWTO (131),
1695 HOWTO (R_ARM_THM_ALU_ABS_G0_NC,/* type. */
1696 0, /* rightshift. */
1697 1, /* size (0 = byte, 1 = short, 2 = long). */
1698 16, /* bitsize. */
1699 FALSE, /* pc_relative. */
1700 0, /* bitpos. */
1701 complain_overflow_bitfield,/* complain_on_overflow. */
1702 bfd_elf_generic_reloc, /* special_function. */
1703 "R_ARM_THM_ALU_ABS_G0_NC",/* name. */
1704 FALSE, /* partial_inplace. */
1705 0x00000000, /* src_mask. */
1706 0x00000000, /* dst_mask. */
1707 FALSE), /* pcrel_offset. */
1708 HOWTO (R_ARM_THM_ALU_ABS_G1_NC,/* type. */
1709 0, /* rightshift. */
1710 1, /* size (0 = byte, 1 = short, 2 = long). */
1711 16, /* bitsize. */
1712 FALSE, /* pc_relative. */
1713 0, /* bitpos. */
1714 complain_overflow_bitfield,/* complain_on_overflow. */
1715 bfd_elf_generic_reloc, /* special_function. */
1716 "R_ARM_THM_ALU_ABS_G1_NC",/* name. */
1717 FALSE, /* partial_inplace. */
1718 0x00000000, /* src_mask. */
1719 0x00000000, /* dst_mask. */
1720 FALSE), /* pcrel_offset. */
1721 HOWTO (R_ARM_THM_ALU_ABS_G2_NC,/* type. */
1722 0, /* rightshift. */
1723 1, /* size (0 = byte, 1 = short, 2 = long). */
1724 16, /* bitsize. */
1725 FALSE, /* pc_relative. */
1726 0, /* bitpos. */
1727 complain_overflow_bitfield,/* complain_on_overflow. */
1728 bfd_elf_generic_reloc, /* special_function. */
1729 "R_ARM_THM_ALU_ABS_G2_NC",/* name. */
1730 FALSE, /* partial_inplace. */
1731 0x00000000, /* src_mask. */
1732 0x00000000, /* dst_mask. */
1733 FALSE), /* pcrel_offset. */
1734 HOWTO (R_ARM_THM_ALU_ABS_G3_NC,/* type. */
1735 0, /* rightshift. */
1736 1, /* size (0 = byte, 1 = short, 2 = long). */
1737 16, /* bitsize. */
1738 FALSE, /* pc_relative. */
1739 0, /* bitpos. */
1740 complain_overflow_bitfield,/* complain_on_overflow. */
1741 bfd_elf_generic_reloc, /* special_function. */
1742 "R_ARM_THM_ALU_ABS_G3_NC",/* name. */
1743 FALSE, /* partial_inplace. */
1744 0x00000000, /* src_mask. */
1745 0x00000000, /* dst_mask. */
1746 FALSE), /* pcrel_offset. */
e5d6e09e
AV		 1747 /* Relocations for Armv8.1-M Mainline. */
1748 HOWTO (R_ARM_THM_BF16, /* type. */
1749 0, /* rightshift. */
1750 1, /* size (0 = byte, 1 = short, 2 = long). */
1751 16, /* bitsize. */
1752 TRUE, /* pc_relative. */
1753 0, /* bitpos. */
1754 complain_overflow_dont,/* do not complain_on_overflow. */
1755 bfd_elf_generic_reloc, /* special_function. */
1756 "R_ARM_THM_BF16", /* name. */
1757 FALSE, /* partial_inplace. */
1758 0x001f0ffe, /* src_mask. */
1759 0x001f0ffe, /* dst_mask. */
1760 TRUE), /* pcrel_offset. */
1889da70
AV		 1761 HOWTO (R_ARM_THM_BF12, /* type. */
1762 0, /* rightshift. */
1763 1, /* size (0 = byte, 1 = short, 2 = long). */
1764 12, /* bitsize. */
1765 TRUE, /* pc_relative. */
1766 0, /* bitpos. */
1767 complain_overflow_dont,/* do not complain_on_overflow. */
1768 bfd_elf_generic_reloc, /* special_function. */
1769 "R_ARM_THM_BF12", /* name. */
1770 FALSE, /* partial_inplace. */
1771 0x00010ffe, /* src_mask. */
1772 0x00010ffe, /* dst_mask. */
1773 TRUE), /* pcrel_offset. */
1caf72a5
AV		 1774 HOWTO (R_ARM_THM_BF18, /* type. */
1775 0, /* rightshift. */
1776 1, /* size (0 = byte, 1 = short, 2 = long). */
1777 18, /* bitsize. */
1778 TRUE, /* pc_relative. */
1779 0, /* bitpos. */
1780 complain_overflow_dont,/* do not complain_on_overflow. */
1781 bfd_elf_generic_reloc, /* special_function. */
1782 "R_ARM_THM_BF18", /* name. */
1783 FALSE, /* partial_inplace. */
1784 0x007f0ffe, /* src_mask. */
1785 0x007f0ffe, /* dst_mask. */
1786 TRUE), /* pcrel_offset. */
c19d1205
ZW		 1787};
1788
34e77a92 1789/* 160 onwards: */
5c5a4843 1790static reloc_howto_type elf32_arm_howto_table_2[8] =
34e77a92
RS		 1791{
1792 HOWTO (R_ARM_IRELATIVE, /* type */
07d6d2b8
AM		 1793 0, /* rightshift */
1794 2, /* size (0 = byte, 1 = short, 2 = long) */
1795 32, /* bitsize */
1796 FALSE, /* pc_relative */
1797 0, /* bitpos */
99059e56
RM		 1798 complain_overflow_bitfield,/* complain_on_overflow */
1799 bfd_elf_generic_reloc, /* special_function */
1800 "R_ARM_IRELATIVE", /* name */
1801 TRUE, /* partial_inplace */
1802 0xffffffff, /* src_mask */
1803 0xffffffff, /* dst_mask */
188fd7ae
CL		 1804 FALSE), /* pcrel_offset */
1805 HOWTO (R_ARM_GOTFUNCDESC, /* type */
1806 0, /* rightshift */
1807 2, /* size (0 = byte, 1 = short, 2 = long) */
1808 32, /* bitsize */
1809 FALSE, /* pc_relative */
1810 0, /* bitpos */
1811 complain_overflow_bitfield,/* complain_on_overflow */
1812 bfd_elf_generic_reloc, /* special_function */
1813 "R_ARM_GOTFUNCDESC", /* name */
1814 FALSE, /* partial_inplace */
1815 0, /* src_mask */
1816 0xffffffff, /* dst_mask */
1817 FALSE), /* pcrel_offset */
1818 HOWTO (R_ARM_GOTOFFFUNCDESC, /* type */
1819 0, /* rightshift */
1820 2, /* size (0 = byte, 1 = short, 2 = long) */
1821 32, /* bitsize */
1822 FALSE, /* pc_relative */
1823 0, /* bitpos */
1824 complain_overflow_bitfield,/* complain_on_overflow */
1825 bfd_elf_generic_reloc, /* special_function */
1826 "R_ARM_GOTOFFFUNCDESC",/* name */
1827 FALSE, /* partial_inplace */
1828 0, /* src_mask */
1829 0xffffffff, /* dst_mask */
1830 FALSE), /* pcrel_offset */
1831 HOWTO (R_ARM_FUNCDESC, /* type */
1832 0, /* rightshift */
1833 2, /* size (0 = byte, 1 = short, 2 = long) */
1834 32, /* bitsize */
1835 FALSE, /* pc_relative */
1836 0, /* bitpos */
1837 complain_overflow_bitfield,/* complain_on_overflow */
1838 bfd_elf_generic_reloc, /* special_function */
1839 "R_ARM_FUNCDESC", /* name */
1840 FALSE, /* partial_inplace */
1841 0, /* src_mask */
1842 0xffffffff, /* dst_mask */
1843 FALSE), /* pcrel_offset */
1844 HOWTO (R_ARM_FUNCDESC_VALUE, /* type */
1845 0, /* rightshift */
1846 2, /* size (0 = byte, 1 = short, 2 = long) */
1847 64, /* bitsize */
1848 FALSE, /* pc_relative */
1849 0, /* bitpos */
1850 complain_overflow_bitfield,/* complain_on_overflow */
1851 bfd_elf_generic_reloc, /* special_function */
1852 "R_ARM_FUNCDESC_VALUE",/* name */
1853 FALSE, /* partial_inplace */
1854 0, /* src_mask */
1855 0xffffffff, /* dst_mask */
1856 FALSE), /* pcrel_offset */
5c5a4843
CL		 1857 HOWTO (R_ARM_TLS_GD32_FDPIC, /* type */
1858 0, /* rightshift */
1859 2, /* size (0 = byte, 1 = short, 2 = long) */
1860 32, /* bitsize */
1861 FALSE, /* pc_relative */
1862 0, /* bitpos */
1863 complain_overflow_bitfield,/* complain_on_overflow */
1864 bfd_elf_generic_reloc, /* special_function */
1865 "R_ARM_TLS_GD32_FDPIC",/* name */
1866 FALSE, /* partial_inplace */
1867 0, /* src_mask */
1868 0xffffffff, /* dst_mask */
1869 FALSE), /* pcrel_offset */
1870 HOWTO (R_ARM_TLS_LDM32_FDPIC, /* type */
1871 0, /* rightshift */
1872 2, /* size (0 = byte, 1 = short, 2 = long) */
1873 32, /* bitsize */
1874 FALSE, /* pc_relative */
1875 0, /* bitpos */
1876 complain_overflow_bitfield,/* complain_on_overflow */
1877 bfd_elf_generic_reloc, /* special_function */
1878 "R_ARM_TLS_LDM32_FDPIC",/* name */
1879 FALSE, /* partial_inplace */
1880 0, /* src_mask */
1881 0xffffffff, /* dst_mask */
1882 FALSE), /* pcrel_offset */
1883 HOWTO (R_ARM_TLS_IE32_FDPIC, /* type */
1884 0, /* rightshift */
1885 2, /* size (0 = byte, 1 = short, 2 = long) */
1886 32, /* bitsize */
1887 FALSE, /* pc_relative */
1888 0, /* bitpos */
1889 complain_overflow_bitfield,/* complain_on_overflow */
1890 bfd_elf_generic_reloc, /* special_function */
1891 "R_ARM_TLS_IE32_FDPIC",/* name */
1892 FALSE, /* partial_inplace */
1893 0, /* src_mask */
1894 0xffffffff, /* dst_mask */
1895 FALSE), /* pcrel_offset */
34e77a92 1896};
c19d1205 1897
34e77a92
RS		 1898/* 249-255 extended, currently unused, relocations: */
1899static reloc_howto_type elf32_arm_howto_table_3[4] =
7f266840
DJ		 1900{
1901 HOWTO (R_ARM_RREL32, /* type */
1902 0, /* rightshift */
1903 0, /* size (0 = byte, 1 = short, 2 = long) */
1904 0, /* bitsize */
1905 FALSE, /* pc_relative */
1906 0, /* bitpos */
1907 complain_overflow_dont,/* complain_on_overflow */
1908 bfd_elf_generic_reloc, /* special_function */
1909 "R_ARM_RREL32", /* name */
1910 FALSE, /* partial_inplace */
1911 0, /* src_mask */
1912 0, /* dst_mask */
1913 FALSE), /* pcrel_offset */
1914
1915 HOWTO (R_ARM_RABS32, /* type */
1916 0, /* rightshift */
1917 0, /* size (0 = byte, 1 = short, 2 = long) */
1918 0, /* bitsize */
1919 FALSE, /* pc_relative */
1920 0, /* bitpos */
1921 complain_overflow_dont,/* complain_on_overflow */
1922 bfd_elf_generic_reloc, /* special_function */
1923 "R_ARM_RABS32", /* name */
1924 FALSE, /* partial_inplace */
1925 0, /* src_mask */
1926 0, /* dst_mask */
1927 FALSE), /* pcrel_offset */
1928
1929 HOWTO (R_ARM_RPC24, /* type */
1930 0, /* rightshift */
1931 0, /* size (0 = byte, 1 = short, 2 = long) */
1932 0, /* bitsize */
1933 FALSE, /* pc_relative */
1934 0, /* bitpos */
1935 complain_overflow_dont,/* complain_on_overflow */
1936 bfd_elf_generic_reloc, /* special_function */
1937 "R_ARM_RPC24", /* name */
1938 FALSE, /* partial_inplace */
1939 0, /* src_mask */
1940 0, /* dst_mask */
1941 FALSE), /* pcrel_offset */
1942
1943 HOWTO (R_ARM_RBASE, /* type */
1944 0, /* rightshift */
1945 0, /* size (0 = byte, 1 = short, 2 = long) */
1946 0, /* bitsize */
1947 FALSE, /* pc_relative */
1948 0, /* bitpos */
1949 complain_overflow_dont,/* complain_on_overflow */
1950 bfd_elf_generic_reloc, /* special_function */
1951 "R_ARM_RBASE", /* name */
1952 FALSE, /* partial_inplace */
1953 0, /* src_mask */
1954 0, /* dst_mask */
1955 FALSE) /* pcrel_offset */
1956};
1957
1958static reloc_howto_type *
1959elf32_arm_howto_from_type (unsigned int r_type)
1960{
906e58ca 1961 if (r_type < ARRAY_SIZE (elf32_arm_howto_table_1))
c19d1205 1962 return &elf32_arm_howto_table_1[r_type];
ba93b8ac 1963
188fd7ae
CL		 1964 if (r_type >= R_ARM_IRELATIVE
1965 && r_type < R_ARM_IRELATIVE + ARRAY_SIZE (elf32_arm_howto_table_2))
34e77a92
RS		 1966 return &elf32_arm_howto_table_2[r_type - R_ARM_IRELATIVE];
1967
c19d1205 1968 if (r_type >= R_ARM_RREL32
34e77a92
RS		 1969 && r_type < R_ARM_RREL32 + ARRAY_SIZE (elf32_arm_howto_table_3))
1970 return &elf32_arm_howto_table_3[r_type - R_ARM_RREL32];
7f266840 1971
c19d1205 1972 return NULL;
7f266840
DJ		 1973}
1974
f3185997
NC		 1975static bfd_boolean
1976elf32_arm_info_to_howto (bfd * abfd, arelent * bfd_reloc,
7f266840
DJ		 1977 Elf_Internal_Rela * elf_reloc)
1978{
1979 unsigned int r_type;
1980
1981 r_type = ELF32_R_TYPE (elf_reloc->r_info);
f3185997
NC		 1982 if ((bfd_reloc->howto = elf32_arm_howto_from_type (r_type)) == NULL)
1983 {
1984 /* xgettext:c-format */
1985 _bfd_error_handler (_("%pB: unsupported relocation type %#x"),
1986 abfd, r_type);
1987 bfd_set_error (bfd_error_bad_value);
1988 return FALSE;
1989 }
1990 return TRUE;
7f266840
DJ		 1991}
1992
1993struct elf32_arm_reloc_map
1994 {
1995 bfd_reloc_code_real_type bfd_reloc_val;
07d6d2b8 1996 unsigned char elf_reloc_val;
7f266840
DJ		 1997 };
1998
1999/* All entries in this list must also be present in elf32_arm_howto_table. */
2000static const struct elf32_arm_reloc_map elf32_arm_reloc_map[] =
2001 {
07d6d2b8 2002 {BFD_RELOC_NONE, R_ARM_NONE},
7f266840 2003 {BFD_RELOC_ARM_PCREL_BRANCH, R_ARM_PC24},
39b41c9c
PB		 2004 {BFD_RELOC_ARM_PCREL_CALL, R_ARM_CALL},
2005 {BFD_RELOC_ARM_PCREL_JUMP, R_ARM_JUMP24},
07d6d2b8
AM		 2006 {BFD_RELOC_ARM_PCREL_BLX, R_ARM_XPC25},
2007 {BFD_RELOC_THUMB_PCREL_BLX, R_ARM_THM_XPC22},
2008 {BFD_RELOC_32, R_ARM_ABS32},
2009 {BFD_RELOC_32_PCREL, R_ARM_REL32},
2010 {BFD_RELOC_8, R_ARM_ABS8},
2011 {BFD_RELOC_16, R_ARM_ABS16},
2012 {BFD_RELOC_ARM_OFFSET_IMM, R_ARM_ABS12},
7f266840 2013 {BFD_RELOC_ARM_THUMB_OFFSET, R_ARM_THM_ABS5},
c19d1205
ZW		 2014 {BFD_RELOC_THUMB_PCREL_BRANCH25, R_ARM_THM_JUMP24},
2015 {BFD_RELOC_THUMB_PCREL_BRANCH23, R_ARM_THM_CALL},
2016 {BFD_RELOC_THUMB_PCREL_BRANCH12, R_ARM_THM_JUMP11},
2017 {BFD_RELOC_THUMB_PCREL_BRANCH20, R_ARM_THM_JUMP19},
2018 {BFD_RELOC_THUMB_PCREL_BRANCH9, R_ARM_THM_JUMP8},
2019 {BFD_RELOC_THUMB_PCREL_BRANCH7, R_ARM_THM_JUMP6},
07d6d2b8
AM		 2020 {BFD_RELOC_ARM_GLOB_DAT, R_ARM_GLOB_DAT},
2021 {BFD_RELOC_ARM_JUMP_SLOT, R_ARM_JUMP_SLOT},
2022 {BFD_RELOC_ARM_RELATIVE, R_ARM_RELATIVE},
2023 {BFD_RELOC_ARM_GOTOFF, R_ARM_GOTOFF32},
2024 {BFD_RELOC_ARM_GOTPC, R_ARM_GOTPC},
2025 {BFD_RELOC_ARM_GOT_PREL, R_ARM_GOT_PREL},
2026 {BFD_RELOC_ARM_GOT32, R_ARM_GOT32},
2027 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
7f266840
DJ		 2028 {BFD_RELOC_ARM_TARGET1, R_ARM_TARGET1},
2029 {BFD_RELOC_ARM_ROSEGREL32, R_ARM_ROSEGREL32},
2030 {BFD_RELOC_ARM_SBREL32, R_ARM_SBREL32},
2031 {BFD_RELOC_ARM_PREL31, R_ARM_PREL31},
ba93b8ac 2032 {BFD_RELOC_ARM_TARGET2, R_ARM_TARGET2},
07d6d2b8
AM		 2033 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
2034 {BFD_RELOC_ARM_TLS_GOTDESC, R_ARM_TLS_GOTDESC},
2035 {BFD_RELOC_ARM_TLS_CALL, R_ARM_TLS_CALL},
0855e32b 2036 {BFD_RELOC_ARM_THM_TLS_CALL, R_ARM_THM_TLS_CALL},
07d6d2b8 2037 {BFD_RELOC_ARM_TLS_DESCSEQ, R_ARM_TLS_DESCSEQ},
0855e32b 2038 {BFD_RELOC_ARM_THM_TLS_DESCSEQ, R_ARM_THM_TLS_DESCSEQ},
07d6d2b8 2039 {BFD_RELOC_ARM_TLS_DESC, R_ARM_TLS_DESC},
ba93b8ac
DJ		 2040 {BFD_RELOC_ARM_TLS_GD32, R_ARM_TLS_GD32},
2041 {BFD_RELOC_ARM_TLS_LDO32, R_ARM_TLS_LDO32},
2042 {BFD_RELOC_ARM_TLS_LDM32, R_ARM_TLS_LDM32},
2043 {BFD_RELOC_ARM_TLS_DTPMOD32, R_ARM_TLS_DTPMOD32},
2044 {BFD_RELOC_ARM_TLS_DTPOFF32, R_ARM_TLS_DTPOFF32},
07d6d2b8
AM		 2045 {BFD_RELOC_ARM_TLS_TPOFF32, R_ARM_TLS_TPOFF32},
2046 {BFD_RELOC_ARM_TLS_IE32, R_ARM_TLS_IE32},
2047 {BFD_RELOC_ARM_TLS_LE32, R_ARM_TLS_LE32},
2048 {BFD_RELOC_ARM_IRELATIVE, R_ARM_IRELATIVE},
188fd7ae
CL		 2049 {BFD_RELOC_ARM_GOTFUNCDESC, R_ARM_GOTFUNCDESC},
2050 {BFD_RELOC_ARM_GOTOFFFUNCDESC, R_ARM_GOTOFFFUNCDESC},
2051 {BFD_RELOC_ARM_FUNCDESC, R_ARM_FUNCDESC},
2052 {BFD_RELOC_ARM_FUNCDESC_VALUE, R_ARM_FUNCDESC_VALUE},
5c5a4843
CL		 2053 {BFD_RELOC_ARM_TLS_GD32_FDPIC, R_ARM_TLS_GD32_FDPIC},
2054 {BFD_RELOC_ARM_TLS_LDM32_FDPIC, R_ARM_TLS_LDM32_FDPIC},
2055 {BFD_RELOC_ARM_TLS_IE32_FDPIC, R_ARM_TLS_IE32_FDPIC},
c19d1205
ZW		 2056 {BFD_RELOC_VTABLE_INHERIT, R_ARM_GNU_VTINHERIT},
2057 {BFD_RELOC_VTABLE_ENTRY, R_ARM_GNU_VTENTRY},
b6895b4f
PB		 2058 {BFD_RELOC_ARM_MOVW, R_ARM_MOVW_ABS_NC},
2059 {BFD_RELOC_ARM_MOVT, R_ARM_MOVT_ABS},
2060 {BFD_RELOC_ARM_MOVW_PCREL, R_ARM_MOVW_PREL_NC},
2061 {BFD_RELOC_ARM_MOVT_PCREL, R_ARM_MOVT_PREL},
2062 {BFD_RELOC_ARM_THUMB_MOVW, R_ARM_THM_MOVW_ABS_NC},
2063 {BFD_RELOC_ARM_THUMB_MOVT, R_ARM_THM_MOVT_ABS},
2064 {BFD_RELOC_ARM_THUMB_MOVW_PCREL, R_ARM_THM_MOVW_PREL_NC},
2065 {BFD_RELOC_ARM_THUMB_MOVT_PCREL, R_ARM_THM_MOVT_PREL},
4962c51a
MS		 2066 {BFD_RELOC_ARM_ALU_PC_G0_NC, R_ARM_ALU_PC_G0_NC},
2067 {BFD_RELOC_ARM_ALU_PC_G0, R_ARM_ALU_PC_G0},
2068 {BFD_RELOC_ARM_ALU_PC_G1_NC, R_ARM_ALU_PC_G1_NC},
2069 {BFD_RELOC_ARM_ALU_PC_G1, R_ARM_ALU_PC_G1},
2070 {BFD_RELOC_ARM_ALU_PC_G2, R_ARM_ALU_PC_G2},
2071 {BFD_RELOC_ARM_LDR_PC_G0, R_ARM_LDR_PC_G0},
2072 {BFD_RELOC_ARM_LDR_PC_G1, R_ARM_LDR_PC_G1},
2073 {BFD_RELOC_ARM_LDR_PC_G2, R_ARM_LDR_PC_G2},
2074 {BFD_RELOC_ARM_LDRS_PC_G0, R_ARM_LDRS_PC_G0},
2075 {BFD_RELOC_ARM_LDRS_PC_G1, R_ARM_LDRS_PC_G1},
2076 {BFD_RELOC_ARM_LDRS_PC_G2, R_ARM_LDRS_PC_G2},
2077 {BFD_RELOC_ARM_LDC_PC_G0, R_ARM_LDC_PC_G0},
2078 {BFD_RELOC_ARM_LDC_PC_G1, R_ARM_LDC_PC_G1},
2079 {BFD_RELOC_ARM_LDC_PC_G2, R_ARM_LDC_PC_G2},
2080 {BFD_RELOC_ARM_ALU_SB_G0_NC, R_ARM_ALU_SB_G0_NC},
2081 {BFD_RELOC_ARM_ALU_SB_G0, R_ARM_ALU_SB_G0},
2082 {BFD_RELOC_ARM_ALU_SB_G1_NC, R_ARM_ALU_SB_G1_NC},
2083 {BFD_RELOC_ARM_ALU_SB_G1, R_ARM_ALU_SB_G1},
2084 {BFD_RELOC_ARM_ALU_SB_G2, R_ARM_ALU_SB_G2},
2085 {BFD_RELOC_ARM_LDR_SB_G0, R_ARM_LDR_SB_G0},
2086 {BFD_RELOC_ARM_LDR_SB_G1, R_ARM_LDR_SB_G1},
2087 {BFD_RELOC_ARM_LDR_SB_G2, R_ARM_LDR_SB_G2},
2088 {BFD_RELOC_ARM_LDRS_SB_G0, R_ARM_LDRS_SB_G0},
2089 {BFD_RELOC_ARM_LDRS_SB_G1, R_ARM_LDRS_SB_G1},
2090 {BFD_RELOC_ARM_LDRS_SB_G2, R_ARM_LDRS_SB_G2},
2091 {BFD_RELOC_ARM_LDC_SB_G0, R_ARM_LDC_SB_G0},
2092 {BFD_RELOC_ARM_LDC_SB_G1, R_ARM_LDC_SB_G1},
845b51d6 2093 {BFD_RELOC_ARM_LDC_SB_G2, R_ARM_LDC_SB_G2},
72d98d16
MG		 2094 {BFD_RELOC_ARM_V4BX, R_ARM_V4BX},
2095 {BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC, R_ARM_THM_ALU_ABS_G3_NC},
2096 {BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC, R_ARM_THM_ALU_ABS_G2_NC},
2097 {BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC, R_ARM_THM_ALU_ABS_G1_NC},
e5d6e09e 2098 {BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC, R_ARM_THM_ALU_ABS_G0_NC},
1caf72a5 2099 {BFD_RELOC_ARM_THUMB_BF17, R_ARM_THM_BF16},
1889da70 2100 {BFD_RELOC_ARM_THUMB_BF13, R_ARM_THM_BF12},
1caf72a5 2101 {BFD_RELOC_ARM_THUMB_BF19, R_ARM_THM_BF18}
7f266840
DJ		 2102 };
2103
2104static reloc_howto_type *
f1c71a59
ZW		 2105elf32_arm_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
2106 bfd_reloc_code_real_type code)
7f266840
DJ		 2107{
2108 unsigned int i;
8029a119 2109
906e58ca 2110 for (i = 0; i < ARRAY_SIZE (elf32_arm_reloc_map); i ++)
c19d1205
ZW		 2111 if (elf32_arm_reloc_map[i].bfd_reloc_val == code)
2112 return elf32_arm_howto_from_type (elf32_arm_reloc_map[i].elf_reloc_val);
7f266840 2113
c19d1205 2114 return NULL;
7f266840
DJ		 2115}
2116
157090f7
AM		 2117static reloc_howto_type *
2118elf32_arm_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
2119 const char *r_name)
2120{
2121 unsigned int i;
2122
906e58ca 2123 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_1); i++)
157090f7
AM		 2124 if (elf32_arm_howto_table_1[i].name != NULL
2125 && strcasecmp (elf32_arm_howto_table_1[i].name, r_name) == 0)
2126 return &elf32_arm_howto_table_1[i];
2127
906e58ca 2128 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_2); i++)
157090f7
AM		 2129 if (elf32_arm_howto_table_2[i].name != NULL
2130 && strcasecmp (elf32_arm_howto_table_2[i].name, r_name) == 0)
2131 return &elf32_arm_howto_table_2[i];
2132
34e77a92
RS		 2133 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_3); i++)
2134 if (elf32_arm_howto_table_3[i].name != NULL
2135 && strcasecmp (elf32_arm_howto_table_3[i].name, r_name) == 0)
2136 return &elf32_arm_howto_table_3[i];
2137
157090f7
AM		 2138 return NULL;
2139}
2140
906e58ca
NC		 2141/* Support for core dump NOTE sections. */
2142
7f266840 2143static bfd_boolean
f1c71a59 2144elf32_arm_nabi_grok_prstatus (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2145{
2146 int offset;
2147 size_t size;
2148
2149 switch (note->descsz)
2150 {
2151 default:
2152 return FALSE;
2153
8029a119 2154 case 148: /* Linux/ARM 32-bit. */
7f266840 2155 /* pr_cursig */
228e534f 2156 elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12);
7f266840
DJ		 2157
2158 /* pr_pid */
228e534f 2159 elf_tdata (abfd)->core->lwpid = bfd_get_32 (abfd, note->descdata + 24);
7f266840
DJ		 2160
2161 /* pr_reg */
2162 offset = 72;
2163 size = 72;
2164
2165 break;
2166 }
2167
2168 /* Make a ".reg/999" section. */
2169 return _bfd_elfcore_make_pseudosection (abfd, ".reg",
2170 size, note->descpos + offset);
2171}
2172
2173static bfd_boolean
f1c71a59 2174elf32_arm_nabi_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2175{
2176 switch (note->descsz)
2177 {
2178 default:
2179 return FALSE;
2180
8029a119 2181 case 124: /* Linux/ARM elf_prpsinfo. */
228e534f 2182 elf_tdata (abfd)->core->pid
4395ee08 2183 = bfd_get_32 (abfd, note->descdata + 12);
228e534f 2184 elf_tdata (abfd)->core->program
7f266840 2185 = _bfd_elfcore_strndup (abfd, note->descdata + 28, 16);
228e534f 2186 elf_tdata (abfd)->core->command
7f266840
DJ		 2187 = _bfd_elfcore_strndup (abfd, note->descdata + 44, 80);
2188 }
2189
2190 /* Note that for some reason, a spurious space is tacked
2191 onto the end of the args in some (at least one anyway)
2192 implementations, so strip it off if it exists. */
7f266840 2193 {
228e534f 2194 char *command = elf_tdata (abfd)->core->command;
7f266840
DJ		 2195 int n = strlen (command);
2196
2197 if (0 < n && command[n - 1] == ' ')
2198 command[n - 1] = '\0';
2199 }
2200
2201 return TRUE;
2202}
2203
1f20dca5
UW		 2204static char *
2205elf32_arm_nabi_write_core_note (bfd *abfd, char *buf, int *bufsiz,
2206 int note_type, ...)
2207{
2208 switch (note_type)
2209 {
2210 default:
2211 return NULL;
2212
2213 case NT_PRPSINFO:
2214 {
602f1657 2215 char data[124] ATTRIBUTE_NONSTRING;
1f20dca5
UW		 2216 va_list ap;
2217
2218 va_start (ap, note_type);
2219 memset (data, 0, sizeof (data));
2220 strncpy (data + 28, va_arg (ap, const char *), 16);
be3e27bb 2221#if GCC_VERSION == 8000 || GCC_VERSION == 8001
95da9854 2222 DIAGNOSTIC_PUSH;
be3e27bb 2223 /* GCC 8.0 and 8.1 warn about 80 equals destination size with
95da9854
L		 2224 -Wstringop-truncation:
2225 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85643
2226 */
95da9854
L		 2227 DIAGNOSTIC_IGNORE_STRINGOP_TRUNCATION;
2228#endif
1f20dca5 2229 strncpy (data + 44, va_arg (ap, const char *), 80);
be3e27bb 2230#if GCC_VERSION == 8000 || GCC_VERSION == 8001
95da9854 2231 DIAGNOSTIC_POP;
fe75810f 2232#endif
1f20dca5
UW		 2233 va_end (ap);
2234
2235 return elfcore_write_note (abfd, buf, bufsiz,
2236 "CORE", note_type, data, sizeof (data));
2237 }
2238
2239 case NT_PRSTATUS:
2240 {
2241 char data[148];
2242 va_list ap;
2243 long pid;
2244 int cursig;
2245 const void *greg;
2246
2247 va_start (ap, note_type);
2248 memset (data, 0, sizeof (data));
2249 pid = va_arg (ap, long);
2250 bfd_put_32 (abfd, pid, data + 24);
2251 cursig = va_arg (ap, int);
2252 bfd_put_16 (abfd, cursig, data + 12);
2253 greg = va_arg (ap, const void *);
2254 memcpy (data + 72, greg, 72);
2255 va_end (ap);
2256
2257 return elfcore_write_note (abfd, buf, bufsiz,
2258 "CORE", note_type, data, sizeof (data));
2259 }
2260 }
2261}
2262
07d6d2b8
AM		 2263#define TARGET_LITTLE_SYM arm_elf32_le_vec
2264#define TARGET_LITTLE_NAME "elf32-littlearm"
2265#define TARGET_BIG_SYM arm_elf32_be_vec
2266#define TARGET_BIG_NAME "elf32-bigarm"
7f266840
DJ		 2267
2268#define elf_backend_grok_prstatus elf32_arm_nabi_grok_prstatus
2269#define elf_backend_grok_psinfo elf32_arm_nabi_grok_psinfo
1f20dca5 2270#define elf_backend_write_core_note elf32_arm_nabi_write_core_note
7f266840 2271
252b5132
RH		 2272typedef unsigned long int insn32;
2273typedef unsigned short int insn16;
2274
3a4a14e9
PB		 2275/* In lieu of proper flags, assume all EABIv4 or later objects are
2276 interworkable. */
57e8b36a 2277#define INTERWORK_FLAG(abfd) \
3a4a14e9 2278 (EF_ARM_EABI_VERSION (elf_elfheader (abfd)->e_flags) >= EF_ARM_EABI_VER4 \
3e6b1042
DJ		 2279 || (elf_elfheader (abfd)->e_flags & EF_ARM_INTERWORK) \
2280 || ((abfd)->flags & BFD_LINKER_CREATED))
9b485d32 2281
252b5132
RH		 2282/* The linker script knows the section names for placement.
2283 The entry_names are used to do simple name mangling on the stubs.
2284 Given a function name, and its type, the stub can be found. The
9b485d32 2285 name can be changed. The only requirement is the %s be present. */
252b5132
RH		 2286#define THUMB2ARM_GLUE_SECTION_NAME ".glue_7t"
2287#define THUMB2ARM_GLUE_ENTRY_NAME "__%s_from_thumb"
2288
2289#define ARM2THUMB_GLUE_SECTION_NAME ".glue_7"
2290#define ARM2THUMB_GLUE_ENTRY_NAME "__%s_from_arm"
2291
c7b8f16e
JB		 2292#define VFP11_ERRATUM_VENEER_SECTION_NAME ".vfp11_veneer"
2293#define VFP11_ERRATUM_VENEER_ENTRY_NAME "__vfp11_veneer_%x"
2294
a504d23a
LA		 2295#define STM32L4XX_ERRATUM_VENEER_SECTION_NAME ".text.stm32l4xx_veneer"
2296#define STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "__stm32l4xx_veneer_%x"
2297
845b51d6
PB		 2298#define ARM_BX_GLUE_SECTION_NAME ".v4_bx"
2299#define ARM_BX_GLUE_ENTRY_NAME "__bx_r%d"
2300
7413f23f
DJ		 2301#define STUB_ENTRY_NAME "__%s_veneer"
2302
4ba2ef8f
TP		 2303#define CMSE_PREFIX "__acle_se_"
2304
4d83e8d9
CL		 2305#define CMSE_STUB_NAME ".gnu.sgstubs"
2306
252b5132
RH		 2307/* The name of the dynamic interpreter. This is put in the .interp
2308 section. */
2309#define ELF_DYNAMIC_INTERPRETER "/usr/lib/ld.so.1"
2310
cb10292c
CL		 2311/* FDPIC default stack size. */
2312#define DEFAULT_STACK_SIZE 0x8000
2313
0855e32b 2314static const unsigned long tls_trampoline [] =
b38cadfb
NC		 2315{
2316 0xe08e0000, /* add r0, lr, r0 */
2317 0xe5901004, /* ldr r1, [r0,#4] */
2318 0xe12fff11, /* bx r1 */
2319};
0855e32b
NS		 2320
2321static const unsigned long dl_tlsdesc_lazy_trampoline [] =
b38cadfb
NC		 2322{
2323 0xe52d2004, /* push {r2} */
2324 0xe59f200c, /* ldr r2, [pc, #3f - . - 8] */
2325 0xe59f100c, /* ldr r1, [pc, #4f - . - 8] */
2326 0xe79f2002, /* 1: ldr r2, [pc, r2] */
2327 0xe081100f, /* 2: add r1, pc */
2328 0xe12fff12, /* bx r2 */
2329 0x00000014, /* 3: .word _GLOBAL_OFFSET_TABLE_ - 1b - 8
99059e56 2330 + dl_tlsdesc_lazy_resolver(GOT) */
b38cadfb
NC		 2331 0x00000018, /* 4: .word _GLOBAL_OFFSET_TABLE_ - 2b - 8 */
2332};
0855e32b 2333
b4e87f2c
TC		 2334/* NOTE: [Thumb nop sequence]
2335 When adding code that transitions from Thumb to Arm the instruction that
2336 should be used for the alignment padding should be 0xe7fd (b .-2) instead of
2337 a nop for performance reasons. */
2338
7801f98f
CL		 2339/* ARM FDPIC PLT entry. */
2340/* The last 5 words contain PLT lazy fragment code and data. */
2341static const bfd_vma elf32_arm_fdpic_plt_entry [] =
2342 {
2343 0xe59fc008, /* ldr r12, .L1 */
2344 0xe08cc009, /* add r12, r12, r9 */
2345 0xe59c9004, /* ldr r9, [r12, #4] */
2346 0xe59cf000, /* ldr pc, [r12] */
2347 0x00000000, /* L1. .word foo(GOTOFFFUNCDESC) */
2348 0x00000000, /* L1. .word foo(funcdesc_value_reloc_offset) */
2349 0xe51fc00c, /* ldr r12, [pc, #-12] */
2350 0xe92d1000, /* push {r12} */
2351 0xe599c004, /* ldr r12, [r9, #4] */
2352 0xe599f000, /* ldr pc, [r9] */
2353 };
2354
59029f57
CL		 2355/* Thumb FDPIC PLT entry. */
2356/* The last 5 words contain PLT lazy fragment code and data. */
2357static const bfd_vma elf32_arm_fdpic_thumb_plt_entry [] =
2358 {
2359 0xc00cf8df, /* ldr.w r12, .L1 */
2360 0x0c09eb0c, /* add.w r12, r12, r9 */
2361 0x9004f8dc, /* ldr.w r9, [r12, #4] */
2362 0xf000f8dc, /* ldr.w pc, [r12] */
2363 0x00000000, /* .L1 .word foo(GOTOFFFUNCDESC) */
2364 0x00000000, /* .L2 .word foo(funcdesc_value_reloc_offset) */
2365 0xc008f85f, /* ldr.w r12, .L2 */
2366 0xcd04f84d, /* push {r12} */
2367 0xc004f8d9, /* ldr.w r12, [r9, #4] */
2368 0xf000f8d9, /* ldr.w pc, [r9] */
2369 };
2370
5e681ec4
PB		 2371#ifdef FOUR_WORD_PLT
2372
252b5132
RH		 2373/* The first entry in a procedure linkage table looks like
2374 this. It is set up so that any shared library function that is
59f2c4e7 2375 called before the relocation has been set up calls the dynamic
9b485d32 2376 linker first. */
e5a52504 2377static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2378{
2379 0xe52de004, /* str lr, [sp, #-4]! */
2380 0xe59fe010, /* ldr lr, [pc, #16] */
2381 0xe08fe00e, /* add lr, pc, lr */
2382 0xe5bef008, /* ldr pc, [lr, #8]! */
2383};
5e681ec4
PB		 2384
2385/* Subsequent entries in a procedure linkage table look like
2386 this. */
e5a52504 2387static const bfd_vma elf32_arm_plt_entry [] =
b38cadfb
NC		 2388{
2389 0xe28fc600, /* add ip, pc, #NN */
2390 0xe28cca00, /* add ip, ip, #NN */
2391 0xe5bcf000, /* ldr pc, [ip, #NN]! */
2392 0x00000000, /* unused */
2393};
5e681ec4 2394
eed94f8f 2395#else /* not FOUR_WORD_PLT */
5e681ec4 2396
5e681ec4
PB		 2397/* The first entry in a procedure linkage table looks like
2398 this. It is set up so that any shared library function that is
2399 called before the relocation has been set up calls the dynamic
2400 linker first. */
e5a52504 2401static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb 2402{
07d6d2b8
AM		 2403 0xe52de004, /* str lr, [sp, #-4]! */
2404 0xe59fe004, /* ldr lr, [pc, #4] */
2405 0xe08fe00e, /* add lr, pc, lr */
2406 0xe5bef008, /* ldr pc, [lr, #8]! */
2407 0x00000000, /* &GOT[0] - . */
b38cadfb 2408};
252b5132 2409
1db37fe6
YG		 2410/* By default subsequent entries in a procedure linkage table look like
2411 this. Offsets that don't fit into 28 bits will cause link error. */
2412static const bfd_vma elf32_arm_plt_entry_short [] =
b38cadfb
NC		 2413{
2414 0xe28fc600, /* add ip, pc, #0xNN00000 */
2415 0xe28cca00, /* add ip, ip, #0xNN000 */
2416 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2417};
5e681ec4 2418
1db37fe6
YG		 2419/* When explicitly asked, we'll use this "long" entry format
2420 which can cope with arbitrary displacements. */
2421static const bfd_vma elf32_arm_plt_entry_long [] =
2422{
07d6d2b8
AM		 2423 0xe28fc200, /* add ip, pc, #0xN0000000 */
2424 0xe28cc600, /* add ip, ip, #0xNN00000 */
1db37fe6
YG		 2425 0xe28cca00, /* add ip, ip, #0xNN000 */
2426 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2427};
2428
2429static bfd_boolean elf32_arm_use_long_plt_entry = FALSE;
2430
eed94f8f
NC		 2431#endif /* not FOUR_WORD_PLT */
2432
2433/* The first entry in a procedure linkage table looks like this.
2434 It is set up so that any shared library function that is called before the
2435 relocation has been set up calls the dynamic linker first. */
2436static const bfd_vma elf32_thumb2_plt0_entry [] =
2437{
2438 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2439 an instruction maybe encoded to one or two array elements. */
07d6d2b8
AM		 2440 0xf8dfb500, /* push {lr} */
2441 0x44fee008, /* ldr.w lr, [pc, #8] */
2442 /* add lr, pc */
eed94f8f 2443 0xff08f85e, /* ldr.w pc, [lr, #8]! */
07d6d2b8 2444 0x00000000, /* &GOT[0] - . */
eed94f8f
NC		 2445};
2446
2447/* Subsequent entries in a procedure linkage table for thumb only target
2448 look like this. */
2449static const bfd_vma elf32_thumb2_plt_entry [] =
2450{
2451 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2452 an instruction maybe encoded to one or two array elements. */
07d6d2b8
AM		 2453 0x0c00f240, /* movw ip, #0xNNNN */
2454 0x0c00f2c0, /* movt ip, #0xNNNN */
2455 0xf8dc44fc, /* add ip, pc */
b4e87f2c
TC		 2456 0xe7fdf000 /* ldr.w pc, [ip] */
2457 /* b .-2 */
eed94f8f 2458};
252b5132 2459
00a97672
RS		 2460/* The format of the first entry in the procedure linkage table
2461 for a VxWorks executable. */
2462static const bfd_vma elf32_arm_vxworks_exec_plt0_entry[] =
b38cadfb 2463{
07d6d2b8
AM		 2464 0xe52dc008, /* str ip,[sp,#-8]! */
2465 0xe59fc000, /* ldr ip,[pc] */
2466 0xe59cf008, /* ldr pc,[ip,#8] */
2467 0x00000000, /* .long _GLOBAL_OFFSET_TABLE_ */
b38cadfb 2468};
00a97672
RS		 2469
2470/* The format of subsequent entries in a VxWorks executable. */
2471static const bfd_vma elf32_arm_vxworks_exec_plt_entry[] =
b38cadfb 2472{
07d6d2b8
AM		 2473 0xe59fc000, /* ldr ip,[pc] */
2474 0xe59cf000, /* ldr pc,[ip] */
2475 0x00000000, /* .long @got */
2476 0xe59fc000, /* ldr ip,[pc] */
2477 0xea000000, /* b _PLT */
2478 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
b38cadfb 2479};
00a97672
RS		 2480
2481/* The format of entries in a VxWorks shared library. */
2482static const bfd_vma elf32_arm_vxworks_shared_plt_entry[] =
b38cadfb 2483{
07d6d2b8
AM		 2484 0xe59fc000, /* ldr ip,[pc] */
2485 0xe79cf009, /* ldr pc,[ip,r9] */
2486 0x00000000, /* .long @got */
2487 0xe59fc000, /* ldr ip,[pc] */
2488 0xe599f008, /* ldr pc,[r9,#8] */
2489 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
b38cadfb 2490};
00a97672 2491
b7693d02
DJ		 2492/* An initial stub used if the PLT entry is referenced from Thumb code. */
2493#define PLT_THUMB_STUB_SIZE 4
2494static const bfd_vma elf32_arm_plt_thumb_stub [] =
b38cadfb
NC		 2495{
2496 0x4778, /* bx pc */
b4e87f2c 2497 0xe7fd /* b .-2 */
b38cadfb 2498};
b7693d02 2499
e5a52504
MM		 2500/* The entries in a PLT when using a DLL-based target with multiple
2501 address spaces. */
906e58ca 2502static const bfd_vma elf32_arm_symbian_plt_entry [] =
b38cadfb 2503{
07d6d2b8
AM		 2504 0xe51ff004, /* ldr pc, [pc, #-4] */
2505 0x00000000, /* dcd R_ARM_GLOB_DAT(X) */
b38cadfb
NC		 2506};
2507
2508/* The first entry in a procedure linkage table looks like
2509 this. It is set up so that any shared library function that is
2510 called before the relocation has been set up calls the dynamic
2511 linker first. */
2512static const bfd_vma elf32_arm_nacl_plt0_entry [] =
2513{
2514 /* First bundle: */
2515 0xe300c000, /* movw ip, #:lower16:&GOT[2]-.+8 */
2516 0xe340c000, /* movt ip, #:upper16:&GOT[2]-.+8 */
2517 0xe08cc00f, /* add ip, ip, pc */
2518 0xe52dc008, /* str ip, [sp, #-8]! */
2519 /* Second bundle: */
edccdf7c
RM		 2520 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2521 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2522 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2523 0xe12fff1c, /* bx ip */
b38cadfb 2524 /* Third bundle: */
edccdf7c
RM		 2525 0xe320f000, /* nop */
2526 0xe320f000, /* nop */
2527 0xe320f000, /* nop */
b38cadfb
NC		 2528 /* .Lplt_tail: */
2529 0xe50dc004, /* str ip, [sp, #-4] */
2530 /* Fourth bundle: */
edccdf7c
RM		 2531 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2532 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2533 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2534 0xe12fff1c, /* bx ip */
b38cadfb
NC		 2535};
2536#define ARM_NACL_PLT_TAIL_OFFSET (11 * 4)
2537
2538/* Subsequent entries in a procedure linkage table look like this. */
2539static const bfd_vma elf32_arm_nacl_plt_entry [] =
2540{
2541 0xe300c000, /* movw ip, #:lower16:&GOT[n]-.+8 */
2542 0xe340c000, /* movt ip, #:upper16:&GOT[n]-.+8 */
2543 0xe08cc00f, /* add ip, ip, pc */
2544 0xea000000, /* b .Lplt_tail */
2545};
e5a52504 2546
906e58ca
NC		 2547#define ARM_MAX_FWD_BRANCH_OFFSET ((((1 << 23) - 1) << 2) + 8)
2548#define ARM_MAX_BWD_BRANCH_OFFSET ((-((1 << 23) << 2)) + 8)
2549#define THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) -2 + 4)
2550#define THM_MAX_BWD_BRANCH_OFFSET (-(1 << 22) + 4)
2551#define THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 2) + 4)
2552#define THM2_MAX_BWD_BRANCH_OFFSET (-(1 << 24) + 4)
c5423981
TG		 2553#define THM2_MAX_FWD_COND_BRANCH_OFFSET (((1 << 20) -2) + 4)
2554#define THM2_MAX_BWD_COND_BRANCH_OFFSET (-(1 << 20) + 4)
906e58ca 2555
461a49ca 2556enum stub_insn_type
b38cadfb
NC		 2557{
2558 THUMB16_TYPE = 1,
2559 THUMB32_TYPE,
2560 ARM_TYPE,
2561 DATA_TYPE
2562};
461a49ca 2563
48229727
JB		 2564#define THUMB16_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 0}
2565/* A bit of a hack. A Thumb conditional branch, in which the proper condition
2566 is inserted in arm_build_one_stub(). */
2567#define THUMB16_BCOND_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 1}
2568#define THUMB32_INSN(X) {(X), THUMB32_TYPE, R_ARM_NONE, 0}
d5a67c02
AV		 2569#define THUMB32_MOVT(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVT_ABS, 0}
2570#define THUMB32_MOVW(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVW_ABS_NC, 0}
48229727
JB		 2571#define THUMB32_B_INSN(X, Z) {(X), THUMB32_TYPE, R_ARM_THM_JUMP24, (Z)}
2572#define ARM_INSN(X) {(X), ARM_TYPE, R_ARM_NONE, 0}
2573#define ARM_REL_INSN(X, Z) {(X), ARM_TYPE, R_ARM_JUMP24, (Z)}
2574#define DATA_WORD(X,Y,Z) {(X), DATA_TYPE, (Y), (Z)}
461a49ca
DJ		 2575
2576typedef struct
2577{
07d6d2b8 2578 bfd_vma data;
b38cadfb 2579 enum stub_insn_type type;
07d6d2b8
AM		 2580 unsigned int r_type;
2581 int reloc_addend;
461a49ca
DJ		 2582} insn_sequence;
2583
b4e87f2c
TC		 2584/* See note [Thumb nop sequence] when adding a veneer. */
2585
fea2b4d6
CL		 2586/* Arm/Thumb -> Arm/Thumb long branch stub. On V5T and above, use blx
2587 to reach the stub if necessary. */
461a49ca 2588static const insn_sequence elf32_arm_stub_long_branch_any_any[] =
b38cadfb 2589{
07d6d2b8 2590 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
b38cadfb
NC		 2591 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2592};
906e58ca 2593
fea2b4d6
CL		 2594/* V4T Arm -> Thumb long branch stub. Used on V4T where blx is not
2595 available. */
461a49ca 2596static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb[] =
b38cadfb 2597{
07d6d2b8
AM		 2598 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2599 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2600 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2601};
906e58ca 2602
d3626fb0 2603/* Thumb -> Thumb long branch stub. Used on M-profile architectures. */
461a49ca 2604static const insn_sequence elf32_arm_stub_long_branch_thumb_only[] =
b38cadfb 2605{
07d6d2b8
AM		 2606 THUMB16_INSN (0xb401), /* push {r0} */
2607 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2608 THUMB16_INSN (0x4684), /* mov ip, r0 */
2609 THUMB16_INSN (0xbc01), /* pop {r0} */
2610 THUMB16_INSN (0x4760), /* bx ip */
2611 THUMB16_INSN (0xbf00), /* nop */
b38cadfb
NC		 2612 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2613};
906e58ca 2614
80c135e5
TP		 2615/* Thumb -> Thumb long branch stub in thumb2 encoding. Used on armv7. */
2616static const insn_sequence elf32_arm_stub_long_branch_thumb2_only[] =
2617{
07d6d2b8 2618 THUMB32_INSN (0xf85ff000), /* ldr.w pc, [pc, #-0] */
80c135e5
TP		 2619 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(x) */
2620};
2621
d5a67c02
AV		 2622/* Thumb -> Thumb long branch stub. Used for PureCode sections on Thumb2
2623 M-profile architectures. */
2624static const insn_sequence elf32_arm_stub_long_branch_thumb2_only_pure[] =
2625{
2626 THUMB32_MOVW (0xf2400c00), /* mov.w ip, R_ARM_MOVW_ABS_NC */
2627 THUMB32_MOVT (0xf2c00c00), /* movt ip, R_ARM_MOVT_ABS << 16 */
07d6d2b8 2628 THUMB16_INSN (0x4760), /* bx ip */
d5a67c02
AV		 2629};
2630
d3626fb0
CL		 2631/* V4T Thumb -> Thumb long branch stub. Using the stack is not
2632 allowed. */
2633static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb[] =
b38cadfb 2634{
07d6d2b8 2635 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2636 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8
AM		 2637 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2638 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2639 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2640};
d3626fb0 2641
fea2b4d6
CL		 2642/* V4T Thumb -> ARM long branch stub. Used on V4T where blx is not
2643 available. */
461a49ca 2644static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm[] =
b38cadfb 2645{
07d6d2b8 2646 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2647 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8 2648 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
b38cadfb
NC		 2649 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2650};
906e58ca 2651
fea2b4d6
CL		 2652/* V4T Thumb -> ARM short branch stub. Shorter variant of the above
2653 one, when the destination is close enough. */
461a49ca 2654static const insn_sequence elf32_arm_stub_short_branch_v4t_thumb_arm[] =
b38cadfb 2655{
07d6d2b8 2656 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2657 THUMB16_INSN (0xe7fd), /* b .-2 */
b38cadfb
NC		 2658 ARM_REL_INSN (0xea000000, -8), /* b (X-8) */
2659};
c820be07 2660
cf3eccff 2661/* ARM/Thumb -> ARM long branch stub, PIC. On V5T and above, use
fea2b4d6 2662 blx to reach the stub if necessary. */
cf3eccff 2663static const insn_sequence elf32_arm_stub_long_branch_any_arm_pic[] =
b38cadfb 2664{
07d6d2b8
AM		 2665 ARM_INSN (0xe59fc000), /* ldr ip, [pc] */
2666 ARM_INSN (0xe08ff00c), /* add pc, pc, ip */
b38cadfb
NC		 2667 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
2668};
906e58ca 2669
cf3eccff
DJ		 2670/* ARM/Thumb -> Thumb long branch stub, PIC. On V5T and above, use
2671 blx to reach the stub if necessary. We can not add into pc;
2672 it is not guaranteed to mode switch (different in ARMv6 and
2673 ARMv7). */
2674static const insn_sequence elf32_arm_stub_long_branch_any_thumb_pic[] =
b38cadfb 2675{
07d6d2b8
AM		 2676 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2677 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2678 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2679 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2680};
cf3eccff 2681
ebe24dd4
CL		 2682/* V4T ARM -> ARM long branch stub, PIC. */
2683static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb_pic[] =
b38cadfb 2684{
07d6d2b8
AM		 2685 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2686 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2687 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2688 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2689};
ebe24dd4
CL		 2690
2691/* V4T Thumb -> ARM long branch stub, PIC. */
2692static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm_pic[] =
b38cadfb 2693{
07d6d2b8 2694 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2695 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8
AM		 2696 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2697 ARM_INSN (0xe08cf00f), /* add pc, ip, pc */
b38cadfb
NC		 2698 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
2699};
ebe24dd4 2700
d3626fb0
CL		 2701/* Thumb -> Thumb long branch stub, PIC. Used on M-profile
2702 architectures. */
ebe24dd4 2703static const insn_sequence elf32_arm_stub_long_branch_thumb_only_pic[] =
b38cadfb 2704{
07d6d2b8
AM		 2705 THUMB16_INSN (0xb401), /* push {r0} */
2706 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2707 THUMB16_INSN (0x46fc), /* mov ip, pc */
2708 THUMB16_INSN (0x4484), /* add ip, r0 */
2709 THUMB16_INSN (0xbc01), /* pop {r0} */
2710 THUMB16_INSN (0x4760), /* bx ip */
b38cadfb
NC		 2711 DATA_WORD (0, R_ARM_REL32, 4), /* dcd R_ARM_REL32(X) */
2712};
ebe24dd4 2713
d3626fb0
CL		 2714/* V4T Thumb -> Thumb long branch stub, PIC. Using the stack is not
2715 allowed. */
2716static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb_pic[] =
b38cadfb 2717{
07d6d2b8 2718 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2719 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8
AM		 2720 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2721 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2722 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2723 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2724};
d3626fb0 2725
0855e32b
NS		 2726/* Thumb2/ARM -> TLS trampoline. Lowest common denominator, which is a
2727 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2728static const insn_sequence elf32_arm_stub_long_branch_any_tls_pic[] =
2729{
07d6d2b8
AM		 2730 ARM_INSN (0xe59f1000), /* ldr r1, [pc] */
2731 ARM_INSN (0xe08ff001), /* add pc, pc, r1 */
b38cadfb 2732 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
0855e32b
NS		 2733};
2734
2735/* V4T Thumb -> TLS trampoline. lowest common denominator, which is a
2736 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2737static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_tls_pic[] =
2738{
07d6d2b8 2739 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2740 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8
AM		 2741 ARM_INSN (0xe59f1000), /* ldr r1, [pc, #0] */
2742 ARM_INSN (0xe081f00f), /* add pc, r1, pc */
b38cadfb 2743 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
0855e32b
NS		 2744};
2745
7a89b94e
NC		 2746/* NaCl ARM -> ARM long branch stub. */
2747static const insn_sequence elf32_arm_stub_long_branch_arm_nacl[] =
2748{
2749 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2750 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
07d6d2b8
AM		 2751 ARM_INSN (0xe12fff1c), /* bx ip */
2752 ARM_INSN (0xe320f000), /* nop */
2753 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2754 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2755 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2756 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
7a89b94e
NC		 2757};
2758
2759/* NaCl ARM -> ARM long branch stub, PIC. */
2760static const insn_sequence elf32_arm_stub_long_branch_arm_nacl_pic[] =
2761{
2762 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
07d6d2b8 2763 ARM_INSN (0xe08cc00f), /* add ip, ip, pc */
7a89b94e 2764 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
07d6d2b8
AM		 2765 ARM_INSN (0xe12fff1c), /* bx ip */
2766 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2767 DATA_WORD (0, R_ARM_REL32, 8), /* dcd R_ARM_REL32(X+8) */
2768 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2769 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
7a89b94e
NC		 2770};
2771
4ba2ef8f
TP		 2772/* Stub used for transition to secure state (aka SG veneer). */
2773static const insn_sequence elf32_arm_stub_cmse_branch_thumb_only[] =
2774{
2775 THUMB32_INSN (0xe97fe97f), /* sg. */
2776 THUMB32_B_INSN (0xf000b800, -4), /* b.w original_branch_dest. */
2777};
2778
7a89b94e 2779
48229727
JB		 2780/* Cortex-A8 erratum-workaround stubs. */
2781
2782/* Stub used for conditional branches (which may be beyond +/-1MB away, so we
2783 can't use a conditional branch to reach this stub). */
2784
2785static const insn_sequence elf32_arm_stub_a8_veneer_b_cond[] =
b38cadfb 2786{
07d6d2b8 2787 THUMB16_BCOND_INSN (0xd001), /* b<cond>.n true. */
b38cadfb
NC		 2788 THUMB32_B_INSN (0xf000b800, -4), /* b.w insn_after_original_branch. */
2789 THUMB32_B_INSN (0xf000b800, -4) /* true: b.w original_branch_dest. */
2790};
48229727
JB		 2791
2792/* Stub used for b.w and bl.w instructions. */
2793
2794static const insn_sequence elf32_arm_stub_a8_veneer_b[] =
b38cadfb
NC		 2795{
2796 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2797};
48229727
JB		 2798
2799static const insn_sequence elf32_arm_stub_a8_veneer_bl[] =
b38cadfb
NC		 2800{
2801 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2802};
48229727
JB		 2803
2804/* Stub used for Thumb-2 blx.w instructions. We modified the original blx.w
2805 instruction (which switches to ARM mode) to point to this stub. Jump to the
2806 real destination using an ARM-mode branch. */
2807
2808static const insn_sequence elf32_arm_stub_a8_veneer_blx[] =
b38cadfb
NC		 2809{
2810 ARM_REL_INSN (0xea000000, -8) /* b original_branch_dest. */
2811};
48229727 2812
9553db3c
NC		 2813/* For each section group there can be a specially created linker section
2814 to hold the stubs for that group. The name of the stub section is based
2815 upon the name of another section within that group with the suffix below
2816 applied.
2817
2818 PR 13049: STUB_SUFFIX used to be ".stub", but this allowed the user to
2819 create what appeared to be a linker stub section when it actually
2820 contained user code/data. For example, consider this fragment:
b38cadfb 2821
9553db3c
NC		 2822 const char * stubborn_problems[] = { "np" };
2823
2824 If this is compiled with "-fPIC -fdata-sections" then gcc produces a
2825 section called:
2826
2827 .data.rel.local.stubborn_problems
2828
2829 This then causes problems in arm32_arm_build_stubs() as it triggers:
2830
2831 // Ignore non-stub sections.
2832 if (!strstr (stub_sec->name, STUB_SUFFIX))
2833 continue;
2834
2835 And so the section would be ignored instead of being processed. Hence
2836 the change in definition of STUB_SUFFIX to a name that cannot be a valid
2837 C identifier. */
2838#define STUB_SUFFIX ".__stub"
906e58ca 2839
738a79f6
CL		 2840/* One entry per long/short branch stub defined above. */
2841#define DEF_STUBS \
2842 DEF_STUB(long_branch_any_any) \
2843 DEF_STUB(long_branch_v4t_arm_thumb) \
2844 DEF_STUB(long_branch_thumb_only) \
2845 DEF_STUB(long_branch_v4t_thumb_thumb) \
2846 DEF_STUB(long_branch_v4t_thumb_arm) \
2847 DEF_STUB(short_branch_v4t_thumb_arm) \
2848 DEF_STUB(long_branch_any_arm_pic) \
2849 DEF_STUB(long_branch_any_thumb_pic) \
2850 DEF_STUB(long_branch_v4t_thumb_thumb_pic) \
2851 DEF_STUB(long_branch_v4t_arm_thumb_pic) \
2852 DEF_STUB(long_branch_v4t_thumb_arm_pic) \
48229727 2853 DEF_STUB(long_branch_thumb_only_pic) \
0855e32b
NS		 2854 DEF_STUB(long_branch_any_tls_pic) \
2855 DEF_STUB(long_branch_v4t_thumb_tls_pic) \
7a89b94e
NC		 2856 DEF_STUB(long_branch_arm_nacl) \
2857 DEF_STUB(long_branch_arm_nacl_pic) \
4ba2ef8f 2858 DEF_STUB(cmse_branch_thumb_only) \
48229727
JB		 2859 DEF_STUB(a8_veneer_b_cond) \
2860 DEF_STUB(a8_veneer_b) \
2861 DEF_STUB(a8_veneer_bl) \
80c135e5
TP		 2862 DEF_STUB(a8_veneer_blx) \
2863 DEF_STUB(long_branch_thumb2_only) \
d5a67c02 2864 DEF_STUB(long_branch_thumb2_only_pure)
738a79f6
CL		 2865
2866#define DEF_STUB(x) arm_stub_##x,
b38cadfb
NC		 2867enum elf32_arm_stub_type
2868{
906e58ca 2869 arm_stub_none,
738a79f6 2870 DEF_STUBS
4f4faa4d 2871 max_stub_type
738a79f6
CL		 2872};
2873#undef DEF_STUB
2874
8d9d9490
TP		 2875/* Note the first a8_veneer type. */
2876const unsigned arm_stub_a8_veneer_lwm = arm_stub_a8_veneer_b_cond;
2877
738a79f6
CL		 2878typedef struct
2879{
d3ce72d0 2880 const insn_sequence* template_sequence;
738a79f6
CL		 2881 int template_size;
2882} stub_def;
2883
2884#define DEF_STUB(x) {elf32_arm_stub_##x, ARRAY_SIZE(elf32_arm_stub_##x)},
b38cadfb
NC		 2885static const stub_def stub_definitions[] =
2886{
738a79f6
CL		 2887 {NULL, 0},
2888 DEF_STUBS
906e58ca
NC		 2889};
2890
2891struct elf32_arm_stub_hash_entry
2892{
2893 /* Base hash table entry structure. */
2894 struct bfd_hash_entry root;
2895
2896 /* The stub section. */
2897 asection *stub_sec;
2898
2899 /* Offset within stub_sec of the beginning of this stub. */
2900 bfd_vma stub_offset;
2901
2902 /* Given the symbol's value and its section we can determine its final
2903 value when building the stubs (so the stub knows where to jump). */
2904 bfd_vma target_value;
2905 asection *target_section;
2906
8d9d9490
TP		 2907 /* Same as above but for the source of the branch to the stub. Used for
2908 Cortex-A8 erratum workaround to patch it to branch to the stub. As
2909 such, source section does not need to be recorded since Cortex-A8 erratum
2910 workaround stubs are only generated when both source and target are in the
2911 same section. */
2912 bfd_vma source_value;
48229727
JB		 2913
2914 /* The instruction which caused this stub to be generated (only valid for
2915 Cortex-A8 erratum workaround stubs at present). */
2916 unsigned long orig_insn;
2917
461a49ca 2918 /* The stub type. */
906e58ca 2919 enum elf32_arm_stub_type stub_type;
461a49ca
DJ		 2920 /* Its encoding size in bytes. */
2921 int stub_size;
2922 /* Its template. */
2923 const insn_sequence *stub_template;
2924 /* The size of the template (number of entries). */
2925 int stub_template_size;
906e58ca
NC		 2926
2927 /* The symbol table entry, if any, that this was derived from. */
2928 struct elf32_arm_link_hash_entry *h;
2929
35fc36a8
RS		 2930 /* Type of branch. */
2931 enum arm_st_branch_type branch_type;
906e58ca
NC		 2932
2933 /* Where this stub is being called from, or, in the case of combined
2934 stub sections, the first input section in the group. */
2935 asection *id_sec;
7413f23f
DJ		 2936
2937 /* The name for the local symbol at the start of this stub. The
2938 stub name in the hash table has to be unique; this does not, so
2939 it can be friendlier. */
2940 char *output_name;
906e58ca
NC		 2941};
2942
e489d0ae
PB		 2943/* Used to build a map of a section. This is required for mixed-endian
2944 code/data. */
2945
2946typedef struct elf32_elf_section_map
2947{
2948 bfd_vma vma;
2949 char type;
2950}
2951elf32_arm_section_map;
2952
c7b8f16e
JB		 2953/* Information about a VFP11 erratum veneer, or a branch to such a veneer. */
2954
2955typedef enum
2956{
2957 VFP11_ERRATUM_BRANCH_TO_ARM_VENEER,
2958 VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER,
2959 VFP11_ERRATUM_ARM_VENEER,
2960 VFP11_ERRATUM_THUMB_VENEER
2961}
2962elf32_vfp11_erratum_type;
2963
2964typedef struct elf32_vfp11_erratum_list
2965{
2966 struct elf32_vfp11_erratum_list *next;
2967 bfd_vma vma;
2968 union
2969 {
2970 struct
2971 {
2972 struct elf32_vfp11_erratum_list *veneer;
2973 unsigned int vfp_insn;
2974 } b;
2975 struct
2976 {
2977 struct elf32_vfp11_erratum_list *branch;
2978 unsigned int id;
2979 } v;
2980 } u;
2981 elf32_vfp11_erratum_type type;
2982}
2983elf32_vfp11_erratum_list;
2984
a504d23a
LA		 2985/* Information about a STM32L4XX erratum veneer, or a branch to such a
2986 veneer. */
2987typedef enum
2988{
2989 STM32L4XX_ERRATUM_BRANCH_TO_VENEER,
2990 STM32L4XX_ERRATUM_VENEER
2991}
2992elf32_stm32l4xx_erratum_type;
2993
2994typedef struct elf32_stm32l4xx_erratum_list
2995{
2996 struct elf32_stm32l4xx_erratum_list *next;
2997 bfd_vma vma;
2998 union
2999 {
3000 struct
3001 {
3002 struct elf32_stm32l4xx_erratum_list *veneer;
3003 unsigned int insn;
3004 } b;
3005 struct
3006 {
3007 struct elf32_stm32l4xx_erratum_list *branch;
3008 unsigned int id;
3009 } v;
3010 } u;
3011 elf32_stm32l4xx_erratum_type type;
3012}
3013elf32_stm32l4xx_erratum_list;
3014
2468f9c9
PB		 3015typedef enum
3016{
3017 DELETE_EXIDX_ENTRY,
3018 INSERT_EXIDX_CANTUNWIND_AT_END
3019}
3020arm_unwind_edit_type;
3021
3022/* A (sorted) list of edits to apply to an unwind table. */
3023typedef struct arm_unwind_table_edit
3024{
3025 arm_unwind_edit_type type;
3026 /* Note: we sometimes want to insert an unwind entry corresponding to a
3027 section different from the one we're currently writing out, so record the
3028 (text) section this edit relates to here. */
3029 asection *linked_section;
3030 unsigned int index;
3031 struct arm_unwind_table_edit *next;
3032}
3033arm_unwind_table_edit;
3034
8e3de13a 3035typedef struct _arm_elf_section_data
e489d0ae 3036{
2468f9c9 3037 /* Information about mapping symbols. */
e489d0ae 3038 struct bfd_elf_section_data elf;
8e3de13a 3039 unsigned int mapcount;
c7b8f16e 3040 unsigned int mapsize;
e489d0ae 3041 elf32_arm_section_map *map;
2468f9c9 3042 /* Information about CPU errata. */
c7b8f16e
JB		 3043 unsigned int erratumcount;
3044 elf32_vfp11_erratum_list *erratumlist;
a504d23a
LA		 3045 unsigned int stm32l4xx_erratumcount;
3046 elf32_stm32l4xx_erratum_list *stm32l4xx_erratumlist;
491d01d3 3047 unsigned int additional_reloc_count;
2468f9c9
PB		 3048 /* Information about unwind tables. */
3049 union
3050 {
3051 /* Unwind info attached to a text section. */
3052 struct
3053 {
3054 asection *arm_exidx_sec;
3055 } text;
3056
3057 /* Unwind info attached to an .ARM.exidx section. */
3058 struct
3059 {
3060 arm_unwind_table_edit *unwind_edit_list;
3061 arm_unwind_table_edit *unwind_edit_tail;
3062 } exidx;
3063 } u;
8e3de13a
NC		 3064}
3065_arm_elf_section_data;
e489d0ae
PB		 3066
3067#define elf32_arm_section_data(sec) \
8e3de13a 3068 ((_arm_elf_section_data *) elf_section_data (sec))
e489d0ae 3069
48229727
JB		 3070/* A fix which might be required for Cortex-A8 Thumb-2 branch/TLB erratum.
3071 These fixes are subject to a relaxation procedure (in elf32_arm_size_stubs),
3072 so may be created multiple times: we use an array of these entries whilst
3073 relaxing which we can refresh easily, then create stubs for each potentially
3074 erratum-triggering instruction once we've settled on a solution. */
3075
b38cadfb
NC		 3076struct a8_erratum_fix
3077{
48229727
JB		 3078 bfd *input_bfd;
3079 asection *section;
3080 bfd_vma offset;
8d9d9490 3081 bfd_vma target_offset;
48229727
JB		 3082 unsigned long orig_insn;
3083 char *stub_name;
3084 enum elf32_arm_stub_type stub_type;
35fc36a8 3085 enum arm_st_branch_type branch_type;
48229727
JB		 3086};
3087
3088/* A table of relocs applied to branches which might trigger Cortex-A8
3089 erratum. */
3090
b38cadfb
NC		 3091struct a8_erratum_reloc
3092{
48229727
JB		 3093 bfd_vma from;
3094 bfd_vma destination;
92750f34
DJ		 3095 struct elf32_arm_link_hash_entry *hash;
3096 const char *sym_name;
48229727 3097 unsigned int r_type;
35fc36a8 3098 enum arm_st_branch_type branch_type;
48229727
JB		 3099 bfd_boolean non_a8_stub;
3100};
3101
ba93b8ac
DJ		 3102/* The size of the thread control block. */
3103#define TCB_SIZE 8
3104
34e77a92
RS		 3105/* ARM-specific information about a PLT entry, over and above the usual
3106 gotplt_union. */
b38cadfb
NC		 3107struct arm_plt_info
3108{
34e77a92
RS		 3109 /* We reference count Thumb references to a PLT entry separately,
3110 so that we can emit the Thumb trampoline only if needed. */
3111 bfd_signed_vma thumb_refcount;
3112
3113 /* Some references from Thumb code may be eliminated by BL->BLX
3114 conversion, so record them separately. */
3115 bfd_signed_vma maybe_thumb_refcount;
3116
3117 /* How many of the recorded PLT accesses were from non-call relocations.
3118 This information is useful when deciding whether anything takes the
3119 address of an STT_GNU_IFUNC PLT. A value of 0 means that all
3120 non-call references to the function should resolve directly to the
3121 real runtime target. */
3122 unsigned int noncall_refcount;
3123
3124 /* Since PLT entries have variable size if the Thumb prologue is
3125 used, we need to record the index into .got.plt instead of
3126 recomputing it from the PLT offset. */
3127 bfd_signed_vma got_offset;
3128};
3129
3130/* Information about an .iplt entry for a local STT_GNU_IFUNC symbol. */
b38cadfb
NC		 3131struct arm_local_iplt_info
3132{
34e77a92
RS		 3133 /* The information that is usually found in the generic ELF part of
3134 the hash table entry. */
3135 union gotplt_union root;
3136
3137 /* The information that is usually found in the ARM-specific part of
3138 the hash table entry. */
3139 struct arm_plt_info arm;
3140
3141 /* A list of all potential dynamic relocations against this symbol. */
3142 struct elf_dyn_relocs *dyn_relocs;
3143};
3144
e8b09b87
CL		 3145/* Structure to handle FDPIC support for local functions. */
3146struct fdpic_local {
3147 unsigned int funcdesc_cnt;
3148 unsigned int gotofffuncdesc_cnt;
3149 int funcdesc_offset;
3150};
3151
0ffa91dd 3152struct elf_arm_obj_tdata
ba93b8ac
DJ		 3153{
3154 struct elf_obj_tdata root;
3155
3156 /* tls_type for each local got entry. */
3157 char *local_got_tls_type;
ee065d83 3158
0855e32b
NS		 3159 /* GOTPLT entries for TLS descriptors. */
3160 bfd_vma *local_tlsdesc_gotent;
3161
34e77a92
RS		 3162 /* Information for local symbols that need entries in .iplt. */
3163 struct arm_local_iplt_info **local_iplt;
3164
bf21ed78
MS		 3165 /* Zero to warn when linking objects with incompatible enum sizes. */
3166 int no_enum_size_warning;
a9dc9481
JM		 3167
3168 /* Zero to warn when linking objects with incompatible wchar_t sizes. */
3169 int no_wchar_size_warning;
e8b09b87
CL		 3170
3171 /* Maintains FDPIC counters and funcdesc info. */
3172 struct fdpic_local *local_fdpic_cnts;
ba93b8ac
DJ		 3173};
3174
0ffa91dd
NC		 3175#define elf_arm_tdata(bfd) \
3176 ((struct elf_arm_obj_tdata *) (bfd)->tdata.any)
ba93b8ac 3177
0ffa91dd
NC		 3178#define elf32_arm_local_got_tls_type(bfd) \
3179 (elf_arm_tdata (bfd)->local_got_tls_type)
3180
0855e32b
NS		 3181#define elf32_arm_local_tlsdesc_gotent(bfd) \
3182 (elf_arm_tdata (bfd)->local_tlsdesc_gotent)
3183
34e77a92
RS		 3184#define elf32_arm_local_iplt(bfd) \
3185 (elf_arm_tdata (bfd)->local_iplt)
3186
e8b09b87
CL		 3187#define elf32_arm_local_fdpic_cnts(bfd) \
3188 (elf_arm_tdata (bfd)->local_fdpic_cnts)
3189
0ffa91dd
NC		 3190#define is_arm_elf(bfd) \
3191 (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
3192 && elf_tdata (bfd) != NULL \
4dfe6ac6 3193 && elf_object_id (bfd) == ARM_ELF_DATA)
ba93b8ac
DJ		 3194
3195static bfd_boolean
3196elf32_arm_mkobject (bfd *abfd)
3197{
0ffa91dd 3198 return bfd_elf_allocate_object (abfd, sizeof (struct elf_arm_obj_tdata),
4dfe6ac6 3199 ARM_ELF_DATA);
ba93b8ac
DJ		 3200}
3201
ba93b8ac
DJ		 3202#define elf32_arm_hash_entry(ent) ((struct elf32_arm_link_hash_entry *)(ent))
3203
e8b09b87
CL		 3204/* Structure to handle FDPIC support for extern functions. */
3205struct fdpic_global {
3206 unsigned int gotofffuncdesc_cnt;
3207 unsigned int gotfuncdesc_cnt;
3208 unsigned int funcdesc_cnt;
3209 int funcdesc_offset;
3210 int gotfuncdesc_offset;
3211};
3212
ba96a88f 3213/* Arm ELF linker hash entry. */
252b5132 3214struct elf32_arm_link_hash_entry
b38cadfb
NC		 3215{
3216 struct elf_link_hash_entry root;
252b5132 3217
b38cadfb
NC		 3218 /* Track dynamic relocs copied for this symbol. */
3219 struct elf_dyn_relocs *dyn_relocs;
b7693d02 3220
b38cadfb
NC		 3221 /* ARM-specific PLT information. */
3222 struct arm_plt_info plt;
ba93b8ac
DJ		 3223
3224#define GOT_UNKNOWN 0
3225#define GOT_NORMAL 1
3226#define GOT_TLS_GD 2
3227#define GOT_TLS_IE 4
0855e32b
NS		 3228#define GOT_TLS_GDESC 8
3229#define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLS_GDESC))
b38cadfb 3230 unsigned int tls_type : 8;
34e77a92 3231
b38cadfb
NC		 3232 /* True if the symbol's PLT entry is in .iplt rather than .plt. */
3233 unsigned int is_iplt : 1;
34e77a92 3234
b38cadfb 3235 unsigned int unused : 23;
a4fd1a8e 3236
b38cadfb
NC		 3237 /* Offset of the GOTPLT entry reserved for the TLS descriptor,
3238 starting at the end of the jump table. */
3239 bfd_vma tlsdesc_got;
0855e32b 3240
b38cadfb
NC		 3241 /* The symbol marking the real symbol location for exported thumb
3242 symbols with Arm stubs. */
3243 struct elf_link_hash_entry *export_glue;
906e58ca 3244
b38cadfb 3245 /* A pointer to the most recently used stub hash entry against this
8029a119 3246 symbol. */
b38cadfb 3247 struct elf32_arm_stub_hash_entry *stub_cache;
e8b09b87
CL		 3248
3249 /* Counter for FDPIC relocations against this symbol. */
3250 struct fdpic_global fdpic_cnts;
b38cadfb 3251};
252b5132 3252
252b5132 3253/* Traverse an arm ELF linker hash table. */
252b5132
RH		 3254#define elf32_arm_link_hash_traverse(table, func, info) \
3255 (elf_link_hash_traverse \
3256 (&(table)->root, \
b7693d02 3257 (bfd_boolean (*) (struct elf_link_hash_entry *, void *)) (func), \
252b5132
RH		 3258 (info)))
3259
3260/* Get the ARM elf linker hash table from a link_info structure. */
3261#define elf32_arm_hash_table(info) \
4dfe6ac6
NC		 3262 (elf_hash_table_id ((struct elf_link_hash_table *) ((info)->hash)) \
3263 == ARM_ELF_DATA ? ((struct elf32_arm_link_hash_table *) ((info)->hash)) : NULL)
252b5132 3264
906e58ca
NC		 3265#define arm_stub_hash_lookup(table, string, create, copy) \
3266 ((struct elf32_arm_stub_hash_entry *) \
3267 bfd_hash_lookup ((table), (string), (create), (copy)))
3268
21d799b5
NC		 3269/* Array to keep track of which stub sections have been created, and
3270 information on stub grouping. */
3271struct map_stub
3272{
3273 /* This is the section to which stubs in the group will be
3274 attached. */
3275 asection *link_sec;
3276 /* The stub section. */
3277 asection *stub_sec;
3278};
3279
0855e32b
NS		 3280#define elf32_arm_compute_jump_table_size(htab) \
3281 ((htab)->next_tls_desc_index * 4)
3282
9b485d32 3283/* ARM ELF linker hash table. */
252b5132 3284struct elf32_arm_link_hash_table
906e58ca
NC		 3285{
3286 /* The main hash table. */
3287 struct elf_link_hash_table root;
252b5132 3288
906e58ca
NC		 3289 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
3290 bfd_size_type thumb_glue_size;
252b5132 3291
906e58ca
NC		 3292 /* The size in bytes of the section containing the ARM-to-Thumb glue. */
3293 bfd_size_type arm_glue_size;
252b5132 3294
906e58ca
NC		 3295 /* The size in bytes of section containing the ARMv4 BX veneers. */
3296 bfd_size_type bx_glue_size;
845b51d6 3297
906e58ca
NC		 3298 /* Offsets of ARMv4 BX veneers. Bit1 set if present, and Bit0 set when
3299 veneer has been populated. */
3300 bfd_vma bx_glue_offset[15];
845b51d6 3301
906e58ca
NC		 3302 /* The size in bytes of the section containing glue for VFP11 erratum
3303 veneers. */
3304 bfd_size_type vfp11_erratum_glue_size;
c7b8f16e 3305
a504d23a
LA		 3306 /* The size in bytes of the section containing glue for STM32L4XX erratum
3307 veneers. */
3308 bfd_size_type stm32l4xx_erratum_glue_size;
3309
48229727
JB		 3310 /* A table of fix locations for Cortex-A8 Thumb-2 branch/TLB erratum. This
3311 holds Cortex-A8 erratum fix locations between elf32_arm_size_stubs() and
3312 elf32_arm_write_section(). */
3313 struct a8_erratum_fix *a8_erratum_fixes;
3314 unsigned int num_a8_erratum_fixes;
3315
906e58ca
NC		 3316 /* An arbitrary input BFD chosen to hold the glue sections. */
3317 bfd * bfd_of_glue_owner;
ba96a88f 3318
906e58ca
NC		 3319 /* Nonzero to output a BE8 image. */
3320 int byteswap_code;
e489d0ae 3321
906e58ca
NC		 3322 /* Zero if R_ARM_TARGET1 means R_ARM_ABS32.
3323 Nonzero if R_ARM_TARGET1 means R_ARM_REL32. */
3324 int target1_is_rel;
9c504268 3325
906e58ca
NC		 3326 /* The relocation to use for R_ARM_TARGET2 relocations. */
3327 int target2_reloc;
eb043451 3328
906e58ca
NC		 3329 /* 0 = Ignore R_ARM_V4BX.
3330 1 = Convert BX to MOV PC.
3331 2 = Generate v4 interworing stubs. */
3332 int fix_v4bx;
319850b4 3333
48229727
JB		 3334 /* Whether we should fix the Cortex-A8 Thumb-2 branch/TLB erratum. */
3335 int fix_cortex_a8;
3336
2de70689
MGD		 3337 /* Whether we should fix the ARM1176 BLX immediate issue. */
3338 int fix_arm1176;
3339
906e58ca
NC		 3340 /* Nonzero if the ARM/Thumb BLX instructions are available for use. */
3341 int use_blx;
33bfe774 3342
906e58ca
NC		 3343 /* What sort of code sequences we should look for which may trigger the
3344 VFP11 denorm erratum. */
3345 bfd_arm_vfp11_fix vfp11_fix;
c7b8f16e 3346
906e58ca
NC		 3347 /* Global counter for the number of fixes we have emitted. */
3348 int num_vfp11_fixes;
c7b8f16e 3349
a504d23a
LA		 3350 /* What sort of code sequences we should look for which may trigger the
3351 STM32L4XX erratum. */
3352 bfd_arm_stm32l4xx_fix stm32l4xx_fix;
3353
3354 /* Global counter for the number of fixes we have emitted. */
3355 int num_stm32l4xx_fixes;
3356
906e58ca
NC		 3357 /* Nonzero to force PIC branch veneers. */
3358 int pic_veneer;
27e55c4d 3359
906e58ca
NC		 3360 /* The number of bytes in the initial entry in the PLT. */
3361 bfd_size_type plt_header_size;
e5a52504 3362
906e58ca
NC		 3363 /* The number of bytes in the subsequent PLT etries. */
3364 bfd_size_type plt_entry_size;
e5a52504 3365
906e58ca
NC		 3366 /* True if the target system is VxWorks. */
3367 int vxworks_p;
00a97672 3368
906e58ca
NC		 3369 /* True if the target system is Symbian OS. */
3370 int symbian_p;
e5a52504 3371
b38cadfb
NC		 3372 /* True if the target system is Native Client. */
3373 int nacl_p;
3374
906e58ca 3375 /* True if the target uses REL relocations. */
f3185997 3376 bfd_boolean use_rel;
4e7fd91e 3377
54ddd295
TP		 3378 /* Nonzero if import library must be a secure gateway import library
3379 as per ARMv8-M Security Extensions. */
3380 int cmse_implib;
3381
0955507f
TP		 3382 /* The import library whose symbols' address must remain stable in
3383 the import library generated. */
3384 bfd *in_implib_bfd;
3385
0855e32b
NS		 3386 /* The index of the next unused R_ARM_TLS_DESC slot in .rel.plt. */
3387 bfd_vma next_tls_desc_index;
3388
3389 /* How many R_ARM_TLS_DESC relocations were generated so far. */
3390 bfd_vma num_tls_desc;
3391
906e58ca
NC		 3392 /* The (unloaded but important) VxWorks .rela.plt.unloaded section. */
3393 asection *srelplt2;
00a97672 3394
0855e32b
NS		 3395 /* The offset into splt of the PLT entry for the TLS descriptor
3396 resolver. Special values are 0, if not necessary (or not found
3397 to be necessary yet), and -1 if needed but not determined
3398 yet. */
3399 bfd_vma dt_tlsdesc_plt;
3400
3401 /* The offset into sgot of the GOT entry used by the PLT entry
3402 above. */
b38cadfb 3403 bfd_vma dt_tlsdesc_got;
0855e32b
NS		 3404
3405 /* Offset in .plt section of tls_arm_trampoline. */
3406 bfd_vma tls_trampoline;
3407
5c5a4843 3408 /* Data for R_ARM_TLS_LDM32/R_ARM_TLS_LDM32_FDPIC relocations. */
906e58ca
NC		 3409 union
3410 {
3411 bfd_signed_vma refcount;
3412 bfd_vma offset;
3413 } tls_ldm_got;
b7693d02 3414
87d72d41
AM		 3415 /* Small local sym cache. */
3416 struct sym_cache sym_cache;
906e58ca
NC		 3417
3418 /* For convenience in allocate_dynrelocs. */
3419 bfd * obfd;
3420
0855e32b
NS		 3421 /* The amount of space used by the reserved portion of the sgotplt
3422 section, plus whatever space is used by the jump slots. */
3423 bfd_vma sgotplt_jump_table_size;
3424
906e58ca
NC		 3425 /* The stub hash table. */
3426 struct bfd_hash_table stub_hash_table;
3427
3428 /* Linker stub bfd. */
3429 bfd *stub_bfd;
3430
3431 /* Linker call-backs. */
6bde4c52
TP		 3432 asection * (*add_stub_section) (const char *, asection *, asection *,
3433 unsigned int);
906e58ca
NC		 3434 void (*layout_sections_again) (void);
3435
3436 /* Array to keep track of which stub sections have been created, and
3437 information on stub grouping. */
21d799b5 3438 struct map_stub *stub_group;
906e58ca 3439
4ba2ef8f
TP		 3440 /* Input stub section holding secure gateway veneers. */
3441 asection *cmse_stub_sec;
3442
0955507f
TP		 3443 /* Offset in cmse_stub_sec where new SG veneers (not in input import library)
3444 start to be allocated. */
3445 bfd_vma new_cmse_stub_offset;
3446
fe33d2fa 3447 /* Number of elements in stub_group. */
7292b3ac 3448 unsigned int top_id;
fe33d2fa 3449
906e58ca
NC		 3450 /* Assorted information used by elf32_arm_size_stubs. */
3451 unsigned int bfd_count;
7292b3ac 3452 unsigned int top_index;
906e58ca 3453 asection **input_list;
617a5ada
CL		 3454
3455 /* True if the target system uses FDPIC. */
3456 int fdpic_p;
e8b09b87
CL		 3457
3458 /* Fixup section. Used for FDPIC. */
3459 asection *srofixup;
906e58ca 3460};
252b5132 3461
e8b09b87
CL		 3462/* Add an FDPIC read-only fixup. */
3463static void
3464arm_elf_add_rofixup (bfd *output_bfd, asection *srofixup, bfd_vma offset)
3465{
3466 bfd_vma fixup_offset;
3467
3468 fixup_offset = srofixup->reloc_count++ * 4;
3469 BFD_ASSERT (fixup_offset < srofixup->size);
3470 bfd_put_32 (output_bfd, offset, srofixup->contents + fixup_offset);
3471}
3472
a504d23a
LA		 3473static inline int
3474ctz (unsigned int mask)
3475{
3476#if GCC_VERSION >= 3004
3477 return __builtin_ctz (mask);
3478#else
3479 unsigned int i;
3480
3481 for (i = 0; i < 8 * sizeof (mask); i++)
3482 {
3483 if (mask & 0x1)
3484 break;
3485 mask = (mask >> 1);
3486 }
3487 return i;
3488#endif
3489}
3490
3491static inline int
b25e998d 3492elf32_arm_popcount (unsigned int mask)
a504d23a
LA		 3493{
3494#if GCC_VERSION >= 3004
3495 return __builtin_popcount (mask);
3496#else
b25e998d
CG		 3497 unsigned int i;
3498 int sum = 0;
a504d23a
LA		 3499
3500 for (i = 0; i < 8 * sizeof (mask); i++)
3501 {
3502 if (mask & 0x1)
3503 sum++;
3504 mask = (mask >> 1);
3505 }
3506 return sum;
3507#endif
3508}
3509
e8b09b87
CL		 3510static void elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
3511 asection *sreloc, Elf_Internal_Rela *rel);
3512
3513static void
3514arm_elf_fill_funcdesc(bfd *output_bfd,
3515 struct bfd_link_info *info,
3516 int *funcdesc_offset,
3517 int dynindx,
3518 int offset,
3519 bfd_vma addr,
3520 bfd_vma dynreloc_value,
3521 bfd_vma seg)
3522{
3523 if ((*funcdesc_offset & 1) == 0)
3524 {
3525 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
3526 asection *sgot = globals->root.sgot;
3527
3528 if (bfd_link_pic(info))
3529 {
3530 asection *srelgot = globals->root.srelgot;
3531 Elf_Internal_Rela outrel;
3532
3533 outrel.r_info = ELF32_R_INFO (dynindx, R_ARM_FUNCDESC_VALUE);
3534 outrel.r_offset = sgot->output_section->vma + sgot->output_offset + offset;
3535 outrel.r_addend = 0;
3536
3537 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
3538 bfd_put_32 (output_bfd, addr, sgot->contents + offset);
3539 bfd_put_32 (output_bfd, seg, sgot->contents + offset + 4);
3540 }
3541 else
3542 {
3543 struct elf_link_hash_entry *hgot = globals->root.hgot;
3544 bfd_vma got_value = hgot->root.u.def.value
3545 + hgot->root.u.def.section->output_section->vma
3546 + hgot->root.u.def.section->output_offset;
3547
3548 arm_elf_add_rofixup(output_bfd, globals->srofixup,
3549 sgot->output_section->vma + sgot->output_offset
3550 + offset);
3551 arm_elf_add_rofixup(output_bfd, globals->srofixup,
3552 sgot->output_section->vma + sgot->output_offset
3553 + offset + 4);
3554 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + offset);
3555 bfd_put_32 (output_bfd, got_value, sgot->contents + offset + 4);
3556 }
3557 *funcdesc_offset |= 1;
3558 }
3559}
3560
780a67af
NC		 3561/* Create an entry in an ARM ELF linker hash table. */
3562
3563static struct bfd_hash_entry *
57e8b36a 3564elf32_arm_link_hash_newfunc (struct bfd_hash_entry * entry,
99059e56
RM		 3565 struct bfd_hash_table * table,
3566 const char * string)
780a67af
NC		 3567{
3568 struct elf32_arm_link_hash_entry * ret =
3569 (struct elf32_arm_link_hash_entry *) entry;
3570
3571 /* Allocate the structure if it has not already been allocated by a
3572 subclass. */
906e58ca 3573 if (ret == NULL)
21d799b5 3574 ret = (struct elf32_arm_link_hash_entry *)
99059e56 3575 bfd_hash_allocate (table, sizeof (struct elf32_arm_link_hash_entry));
57e8b36a 3576 if (ret == NULL)
780a67af
NC		 3577 return (struct bfd_hash_entry *) ret;
3578
3579 /* Call the allocation method of the superclass. */
3580 ret = ((struct elf32_arm_link_hash_entry *)
3581 _bfd_elf_link_hash_newfunc ((struct bfd_hash_entry *) ret,
3582 table, string));
57e8b36a 3583 if (ret != NULL)
b7693d02 3584 {
0bdcacaf 3585 ret->dyn_relocs = NULL;
ba93b8ac 3586 ret->tls_type = GOT_UNKNOWN;
0855e32b 3587 ret->tlsdesc_got = (bfd_vma) -1;
34e77a92
RS		 3588 ret->plt.thumb_refcount = 0;
3589 ret->plt.maybe_thumb_refcount = 0;
3590 ret->plt.noncall_refcount = 0;
3591 ret->plt.got_offset = -1;
3592 ret->is_iplt = FALSE;
a4fd1a8e 3593 ret->export_glue = NULL;
906e58ca
NC		 3594
3595 ret->stub_cache = NULL;
e8b09b87
CL		 3596
3597 ret->fdpic_cnts.gotofffuncdesc_cnt = 0;
3598 ret->fdpic_cnts.gotfuncdesc_cnt = 0;
3599 ret->fdpic_cnts.funcdesc_cnt = 0;
3600 ret->fdpic_cnts.funcdesc_offset = -1;
3601 ret->fdpic_cnts.gotfuncdesc_offset = -1;
b7693d02 3602 }
780a67af
NC		 3603
3604 return (struct bfd_hash_entry *) ret;
3605}
3606
34e77a92
RS		 3607/* Ensure that we have allocated bookkeeping structures for ABFD's local
3608 symbols. */
3609
3610static bfd_boolean
3611elf32_arm_allocate_local_sym_info (bfd *abfd)
3612{
3613 if (elf_local_got_refcounts (abfd) == NULL)
3614 {
3615 bfd_size_type num_syms;
3616 bfd_size_type size;
3617 char *data;
3618
3619 num_syms = elf_tdata (abfd)->symtab_hdr.sh_info;
3620 size = num_syms * (sizeof (bfd_signed_vma)
3621 + sizeof (struct arm_local_iplt_info *)
3622 + sizeof (bfd_vma)
e8b09b87
CL		 3623 + sizeof (char)
3624 + sizeof (struct fdpic_local));
34e77a92
RS		 3625 data = bfd_zalloc (abfd, size);
3626 if (data == NULL)
3627 return FALSE;
3628
e8b09b87
CL		 3629 elf32_arm_local_fdpic_cnts (abfd) = (struct fdpic_local *) data;
3630 data += num_syms * sizeof (struct fdpic_local);
3631
34e77a92
RS		 3632 elf_local_got_refcounts (abfd) = (bfd_signed_vma *) data;
3633 data += num_syms * sizeof (bfd_signed_vma);
3634
3635 elf32_arm_local_iplt (abfd) = (struct arm_local_iplt_info **) data;
3636 data += num_syms * sizeof (struct arm_local_iplt_info *);
3637
3638 elf32_arm_local_tlsdesc_gotent (abfd) = (bfd_vma *) data;
3639 data += num_syms * sizeof (bfd_vma);
3640
3641 elf32_arm_local_got_tls_type (abfd) = data;
3642 }
3643 return TRUE;
3644}
3645
3646/* Return the .iplt information for local symbol R_SYMNDX, which belongs
3647 to input bfd ABFD. Create the information if it doesn't already exist.
3648 Return null if an allocation fails. */
3649
3650static struct arm_local_iplt_info *
3651elf32_arm_create_local_iplt (bfd *abfd, unsigned long r_symndx)
3652{
3653 struct arm_local_iplt_info **ptr;
3654
3655 if (!elf32_arm_allocate_local_sym_info (abfd))
3656 return NULL;
3657
3658 BFD_ASSERT (r_symndx < elf_tdata (abfd)->symtab_hdr.sh_info);
3659 ptr = &elf32_arm_local_iplt (abfd)[r_symndx];
3660 if (*ptr == NULL)
3661 *ptr = bfd_zalloc (abfd, sizeof (**ptr));
3662 return *ptr;
3663}
3664
3665/* Try to obtain PLT information for the symbol with index R_SYMNDX
3666 in ABFD's symbol table. If the symbol is global, H points to its
3667 hash table entry, otherwise H is null.
3668
3669 Return true if the symbol does have PLT information. When returning
3670 true, point *ROOT_PLT at the target-independent reference count/offset
3671 union and *ARM_PLT at the ARM-specific information. */
3672
3673static bfd_boolean
4ba2ef8f
TP		 3674elf32_arm_get_plt_info (bfd *abfd, struct elf32_arm_link_hash_table *globals,
3675 struct elf32_arm_link_hash_entry *h,
34e77a92
RS		 3676 unsigned long r_symndx, union gotplt_union **root_plt,
3677 struct arm_plt_info **arm_plt)
3678{
3679 struct arm_local_iplt_info *local_iplt;
3680
4ba2ef8f
TP		 3681 if (globals->root.splt == NULL && globals->root.iplt == NULL)
3682 return FALSE;
3683
34e77a92
RS		 3684 if (h != NULL)
3685 {
3686 *root_plt = &h->root.plt;
3687 *arm_plt = &h->plt;
3688 return TRUE;
3689 }
3690
3691 if (elf32_arm_local_iplt (abfd) == NULL)
3692 return FALSE;
3693
3694 local_iplt = elf32_arm_local_iplt (abfd)[r_symndx];
3695 if (local_iplt == NULL)
3696 return FALSE;
3697
3698 *root_plt = &local_iplt->root;
3699 *arm_plt = &local_iplt->arm;
3700 return TRUE;
3701}
3702
59029f57
CL		 3703static bfd_boolean using_thumb_only (struct elf32_arm_link_hash_table *globals);
3704
34e77a92
RS		 3705/* Return true if the PLT described by ARM_PLT requires a Thumb stub
3706 before it. */
3707
3708static bfd_boolean
3709elf32_arm_plt_needs_thumb_stub_p (struct bfd_link_info *info,
3710 struct arm_plt_info *arm_plt)
3711{
3712 struct elf32_arm_link_hash_table *htab;
3713
3714 htab = elf32_arm_hash_table (info);
59029f57
CL		 3715
3716 return (!using_thumb_only(htab) && (arm_plt->thumb_refcount != 0
3717 || (!htab->use_blx && arm_plt->maybe_thumb_refcount != 0)));
34e77a92
RS		 3718}
3719
3720/* Return a pointer to the head of the dynamic reloc list that should
3721 be used for local symbol ISYM, which is symbol number R_SYMNDX in
3722 ABFD's symbol table. Return null if an error occurs. */
3723
3724static struct elf_dyn_relocs **
3725elf32_arm_get_local_dynreloc_list (bfd *abfd, unsigned long r_symndx,
3726 Elf_Internal_Sym *isym)
3727{
3728 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC)
3729 {
3730 struct arm_local_iplt_info *local_iplt;
3731
3732 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
3733 if (local_iplt == NULL)
3734 return NULL;
3735 return &local_iplt->dyn_relocs;
3736 }
3737 else
3738 {
3739 /* Track dynamic relocs needed for local syms too.
3740 We really need local syms available to do this
3741 easily. Oh well. */
3742 asection *s;
3743 void *vpp;
3744
3745 s = bfd_section_from_elf_index (abfd, isym->st_shndx);
3746 if (s == NULL)
3747 abort ();
3748
3749 vpp = &elf_section_data (s)->local_dynrel;
3750 return (struct elf_dyn_relocs **) vpp;
3751 }
3752}
3753
906e58ca
NC		 3754/* Initialize an entry in the stub hash table. */
3755
3756static struct bfd_hash_entry *
3757stub_hash_newfunc (struct bfd_hash_entry *entry,
3758 struct bfd_hash_table *table,
3759 const char *string)
3760{
3761 /* Allocate the structure if it has not already been allocated by a
3762 subclass. */
3763 if (entry == NULL)
3764 {
21d799b5 3765 entry = (struct bfd_hash_entry *)
99059e56 3766 bfd_hash_allocate (table, sizeof (struct elf32_arm_stub_hash_entry));
906e58ca
NC		 3767 if (entry == NULL)
3768 return entry;
3769 }
3770
3771 /* Call the allocation method of the superclass. */
3772 entry = bfd_hash_newfunc (entry, table, string);
3773 if (entry != NULL)
3774 {
3775 struct elf32_arm_stub_hash_entry *eh;
3776
3777 /* Initialize the local fields. */
3778 eh = (struct elf32_arm_stub_hash_entry *) entry;
3779 eh->stub_sec = NULL;
0955507f 3780 eh->stub_offset = (bfd_vma) -1;
8d9d9490 3781 eh->source_value = 0;
906e58ca
NC		 3782 eh->target_value = 0;
3783 eh->target_section = NULL;
cedfb179 3784 eh->orig_insn = 0;
906e58ca 3785 eh->stub_type = arm_stub_none;
461a49ca
DJ		 3786 eh->stub_size = 0;
3787 eh->stub_template = NULL;
0955507f 3788 eh->stub_template_size = -1;
906e58ca
NC		 3789 eh->h = NULL;
3790 eh->id_sec = NULL;
d8d2f433 3791 eh->output_name = NULL;
906e58ca
NC		 3792 }
3793
3794 return entry;
3795}
3796
00a97672 3797/* Create .got, .gotplt, and .rel(a).got sections in DYNOBJ, and set up
5e681ec4
PB		 3798 shortcuts to them in our hash table. */
3799
3800static bfd_boolean
57e8b36a 3801create_got_section (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3802{
3803 struct elf32_arm_link_hash_table *htab;
3804
e5a52504 3805 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3806 if (htab == NULL)
3807 return FALSE;
3808
e5a52504
MM		 3809 /* BPABI objects never have a GOT, or associated sections. */
3810 if (htab->symbian_p)
3811 return TRUE;
3812
5e681ec4
PB		 3813 if (! _bfd_elf_create_got_section (dynobj, info))
3814 return FALSE;
3815
e8b09b87
CL		 3816 /* Also create .rofixup. */
3817 if (htab->fdpic_p)
3818 {
3819 htab->srofixup = bfd_make_section_with_flags (dynobj, ".rofixup",
3820 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS
3821 | SEC_IN_MEMORY | SEC_LINKER_CREATED | SEC_READONLY));
fd361982
AM		 3822 if (htab->srofixup == NULL
3823 || !bfd_set_section_alignment (htab->srofixup, 2))
e8b09b87
CL		 3824 return FALSE;
3825 }
3826
5e681ec4
PB		 3827 return TRUE;
3828}
3829
34e77a92
RS		 3830/* Create the .iplt, .rel(a).iplt and .igot.plt sections. */
3831
3832static bfd_boolean
3833create_ifunc_sections (struct bfd_link_info *info)
3834{
3835 struct elf32_arm_link_hash_table *htab;
3836 const struct elf_backend_data *bed;
3837 bfd *dynobj;
3838 asection *s;
3839 flagword flags;
b38cadfb 3840
34e77a92
RS		 3841 htab = elf32_arm_hash_table (info);
3842 dynobj = htab->root.dynobj;
3843 bed = get_elf_backend_data (dynobj);
3844 flags = bed->dynamic_sec_flags;
3845
3846 if (htab->root.iplt == NULL)
3847 {
3d4d4302
AM		 3848 s = bfd_make_section_anyway_with_flags (dynobj, ".iplt",
3849 flags | SEC_READONLY | SEC_CODE);
34e77a92 3850 if (s == NULL
fd361982 3851 || !bfd_set_section_alignment (s, bed->plt_alignment))
34e77a92
RS		 3852 return FALSE;
3853 htab->root.iplt = s;
3854 }
3855
3856 if (htab->root.irelplt == NULL)
3857 {
3d4d4302
AM		 3858 s = bfd_make_section_anyway_with_flags (dynobj,
3859 RELOC_SECTION (htab, ".iplt"),
3860 flags | SEC_READONLY);
34e77a92 3861 if (s == NULL
fd361982 3862 || !bfd_set_section_alignment (s, bed->s->log_file_align))
34e77a92
RS		 3863 return FALSE;
3864 htab->root.irelplt = s;
3865 }
3866
3867 if (htab->root.igotplt == NULL)
3868 {
3d4d4302 3869 s = bfd_make_section_anyway_with_flags (dynobj, ".igot.plt", flags);
34e77a92 3870 if (s == NULL
fd361982 3871 || !bfd_set_section_alignment (s, bed->s->log_file_align))
34e77a92
RS		 3872 return FALSE;
3873 htab->root.igotplt = s;
3874 }
3875 return TRUE;
3876}
3877
eed94f8f
NC		 3878/* Determine if we're dealing with a Thumb only architecture. */
3879
3880static bfd_boolean
3881using_thumb_only (struct elf32_arm_link_hash_table *globals)
3882{
2fd158eb
TP		 3883 int arch;
3884 int profile = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3885 Tag_CPU_arch_profile);
eed94f8f 3886
2fd158eb
TP		 3887 if (profile)
3888 return profile == 'M';
eed94f8f 3889
2fd158eb 3890 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
eed94f8f 3891
60a019a0 3892 /* Force return logic to be reviewed for each new architecture. */
031254f2 3893 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
60a019a0 3894
2fd158eb
TP		 3895 if (arch == TAG_CPU_ARCH_V6_M
3896 || arch == TAG_CPU_ARCH_V6S_M
3897 || arch == TAG_CPU_ARCH_V7E_M
3898 || arch == TAG_CPU_ARCH_V8M_BASE
031254f2
AV		 3899 || arch == TAG_CPU_ARCH_V8M_MAIN
3900 || arch == TAG_CPU_ARCH_V8_1M_MAIN)
2fd158eb 3901 return TRUE;
eed94f8f 3902
2fd158eb 3903 return FALSE;
eed94f8f
NC		 3904}
3905
3906/* Determine if we're dealing with a Thumb-2 object. */
3907
3908static bfd_boolean
3909using_thumb2 (struct elf32_arm_link_hash_table *globals)
3910{
60a019a0
TP		 3911 int arch;
3912 int thumb_isa = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3913 Tag_THUMB_ISA_use);
3914
3915 if (thumb_isa)
3916 return thumb_isa == 2;
3917
3918 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3919
3920 /* Force return logic to be reviewed for each new architecture. */
031254f2 3921 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
60a019a0
TP		 3922
3923 return (arch == TAG_CPU_ARCH_V6T2
3924 || arch == TAG_CPU_ARCH_V7
3925 || arch == TAG_CPU_ARCH_V7E_M
3926 || arch == TAG_CPU_ARCH_V8
bff0500d 3927 || arch == TAG_CPU_ARCH_V8R
031254f2
AV		 3928 || arch == TAG_CPU_ARCH_V8M_MAIN
3929 || arch == TAG_CPU_ARCH_V8_1M_MAIN);
eed94f8f
NC		 3930}
3931
5e866f5a
TP		 3932/* Determine whether Thumb-2 BL instruction is available. */
3933
3934static bfd_boolean
3935using_thumb2_bl (struct elf32_arm_link_hash_table *globals)
3936{
3937 int arch =
3938 bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3939
3940 /* Force return logic to be reviewed for each new architecture. */
031254f2 3941 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
5e866f5a
TP		 3942
3943 /* Architecture was introduced after ARMv6T2 (eg. ARMv6-M). */
3944 return (arch == TAG_CPU_ARCH_V6T2
3945 || arch >= TAG_CPU_ARCH_V7);
3946}
3947
00a97672
RS		 3948/* Create .plt, .rel(a).plt, .got, .got.plt, .rel(a).got, .dynbss, and
3949 .rel(a).bss sections in DYNOBJ, and set up shortcuts to them in our
5e681ec4
PB		 3950 hash table. */
3951
3952static bfd_boolean
57e8b36a 3953elf32_arm_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3954{
3955 struct elf32_arm_link_hash_table *htab;
3956
3957 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3958 if (htab == NULL)
3959 return FALSE;
3960
362d30a1 3961 if (!htab->root.sgot && !create_got_section (dynobj, info))
5e681ec4
PB		 3962 return FALSE;
3963
3964 if (!_bfd_elf_create_dynamic_sections (dynobj, info))
3965 return FALSE;
3966
00a97672
RS		 3967 if (htab->vxworks_p)
3968 {
3969 if (!elf_vxworks_create_dynamic_sections (dynobj, info, &htab->srelplt2))
3970 return FALSE;
3971
0e1862bb 3972 if (bfd_link_pic (info))
00a97672
RS		 3973 {
3974 htab->plt_header_size = 0;
3975 htab->plt_entry_size
3976 = 4 * ARRAY_SIZE (elf32_arm_vxworks_shared_plt_entry);
3977 }
3978 else
3979 {
3980 htab->plt_header_size
3981 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt0_entry);
3982 htab->plt_entry_size
3983 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt_entry);
3984 }
aebf9be7
NC		 3985
3986 if (elf_elfheader (dynobj))
3987 elf_elfheader (dynobj)->e_ident[EI_CLASS] = ELFCLASS32;
00a97672 3988 }
eed94f8f
NC		 3989 else
3990 {
3991 /* PR ld/16017
3992 Test for thumb only architectures. Note - we cannot just call
3993 using_thumb_only() as the attributes in the output bfd have not been
3994 initialised at this point, so instead we use the input bfd. */
3995 bfd * saved_obfd = htab->obfd;
3996
3997 htab->obfd = dynobj;
3998 if (using_thumb_only (htab))
3999 {
4000 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
4001 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
4002 }
4003 htab->obfd = saved_obfd;
4004 }
5e681ec4 4005
7801f98f
CL		 4006 if (htab->fdpic_p) {
4007 htab->plt_header_size = 0;
4008 if (info->flags & DF_BIND_NOW)
4009 htab->plt_entry_size = 4 * (ARRAY_SIZE(elf32_arm_fdpic_plt_entry) - 5);
4010 else
4011 htab->plt_entry_size = 4 * ARRAY_SIZE(elf32_arm_fdpic_plt_entry);
4012 }
4013
362d30a1
RS		 4014 if (!htab->root.splt
4015 || !htab->root.srelplt
9d19e4fd
AM		 4016 || !htab->root.sdynbss
4017 || (!bfd_link_pic (info) && !htab->root.srelbss))
5e681ec4
PB		 4018 abort ();
4019
4020 return TRUE;
4021}
4022
906e58ca
NC		 4023/* Copy the extra info we tack onto an elf_link_hash_entry. */
4024
4025static void
4026elf32_arm_copy_indirect_symbol (struct bfd_link_info *info,
4027 struct elf_link_hash_entry *dir,
4028 struct elf_link_hash_entry *ind)
4029{
4030 struct elf32_arm_link_hash_entry *edir, *eind;
4031
4032 edir = (struct elf32_arm_link_hash_entry *) dir;
4033 eind = (struct elf32_arm_link_hash_entry *) ind;
4034
0bdcacaf 4035 if (eind->dyn_relocs != NULL)
906e58ca 4036 {
0bdcacaf 4037 if (edir->dyn_relocs != NULL)
906e58ca 4038 {
0bdcacaf
RS		 4039 struct elf_dyn_relocs **pp;
4040 struct elf_dyn_relocs *p;
906e58ca
NC		 4041
4042 /* Add reloc counts against the indirect sym to the direct sym
4043 list. Merge any entries against the same section. */
0bdcacaf 4044 for (pp = &eind->dyn_relocs; (p = *pp) != NULL; )
906e58ca 4045 {
0bdcacaf 4046 struct elf_dyn_relocs *q;
906e58ca 4047
0bdcacaf
RS		 4048 for (q = edir->dyn_relocs; q != NULL; q = q->next)
4049 if (q->sec == p->sec)
906e58ca
NC		 4050 {
4051 q->pc_count += p->pc_count;
4052 q->count += p->count;
4053 *pp = p->next;
4054 break;
4055 }
4056 if (q == NULL)
4057 pp = &p->next;
4058 }
0bdcacaf 4059 *pp = edir->dyn_relocs;
906e58ca
NC		 4060 }
4061
0bdcacaf
RS		 4062 edir->dyn_relocs = eind->dyn_relocs;
4063 eind->dyn_relocs = NULL;
906e58ca
NC		 4064 }
4065
4066 if (ind->root.type == bfd_link_hash_indirect)
4067 {
4068 /* Copy over PLT info. */
34e77a92
RS		 4069 edir->plt.thumb_refcount += eind->plt.thumb_refcount;
4070 eind->plt.thumb_refcount = 0;
4071 edir->plt.maybe_thumb_refcount += eind->plt.maybe_thumb_refcount;
4072 eind->plt.maybe_thumb_refcount = 0;
4073 edir->plt.noncall_refcount += eind->plt.noncall_refcount;
4074 eind->plt.noncall_refcount = 0;
4075
e8b09b87
CL		 4076 /* Copy FDPIC counters. */
4077 edir->fdpic_cnts.gotofffuncdesc_cnt += eind->fdpic_cnts.gotofffuncdesc_cnt;
4078 edir->fdpic_cnts.gotfuncdesc_cnt += eind->fdpic_cnts.gotfuncdesc_cnt;
4079 edir->fdpic_cnts.funcdesc_cnt += eind->fdpic_cnts.funcdesc_cnt;
4080
34e77a92
RS		 4081 /* We should only allocate a function to .iplt once the final
4082 symbol information is known. */
4083 BFD_ASSERT (!eind->is_iplt);
906e58ca
NC		 4084
4085 if (dir->got.refcount <= 0)
4086 {
4087 edir->tls_type = eind->tls_type;
4088 eind->tls_type = GOT_UNKNOWN;
4089 }
4090 }
4091
4092 _bfd_elf_link_hash_copy_indirect (info, dir, ind);
4093}
4094
68faa637
AM		 4095/* Destroy an ARM elf linker hash table. */
4096
4097static void
d495ab0d 4098elf32_arm_link_hash_table_free (bfd *obfd)
68faa637
AM		 4099{
4100 struct elf32_arm_link_hash_table *ret
d495ab0d 4101 = (struct elf32_arm_link_hash_table *) obfd->link.hash;
68faa637
AM		 4102
4103 bfd_hash_table_free (&ret->stub_hash_table);
d495ab0d 4104 _bfd_elf_link_hash_table_free (obfd);
68faa637
AM		 4105}
4106
906e58ca
NC		 4107/* Create an ARM elf linker hash table. */
4108
4109static struct bfd_link_hash_table *
4110elf32_arm_link_hash_table_create (bfd *abfd)
4111{
4112 struct elf32_arm_link_hash_table *ret;
986f0783 4113 size_t amt = sizeof (struct elf32_arm_link_hash_table);
906e58ca 4114
7bf52ea2 4115 ret = (struct elf32_arm_link_hash_table *) bfd_zmalloc (amt);
906e58ca
NC		 4116 if (ret == NULL)
4117 return NULL;
4118
4119 if (!_bfd_elf_link_hash_table_init (& ret->root, abfd,
4120 elf32_arm_link_hash_newfunc,
4dfe6ac6
NC		 4121 sizeof (struct elf32_arm_link_hash_entry),
4122 ARM_ELF_DATA))
906e58ca
NC		 4123 {
4124 free (ret);
4125 return NULL;
4126 }
4127
906e58ca 4128 ret->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
a504d23a 4129 ret->stm32l4xx_fix = BFD_ARM_STM32L4XX_FIX_NONE;
906e58ca
NC		 4130#ifdef FOUR_WORD_PLT
4131 ret->plt_header_size = 16;
4132 ret->plt_entry_size = 16;
4133#else
4134 ret->plt_header_size = 20;
1db37fe6 4135 ret->plt_entry_size = elf32_arm_use_long_plt_entry ? 16 : 12;
906e58ca 4136#endif
f3185997 4137 ret->use_rel = TRUE;
906e58ca 4138 ret->obfd = abfd;
617a5ada 4139 ret->fdpic_p = 0;
906e58ca
NC		 4140
4141 if (!bfd_hash_table_init (&ret->stub_hash_table, stub_hash_newfunc,
4142 sizeof (struct elf32_arm_stub_hash_entry)))
4143 {
d495ab0d 4144 _bfd_elf_link_hash_table_free (abfd);
906e58ca
NC		 4145 return NULL;
4146 }
d495ab0d 4147 ret->root.root.hash_table_free = elf32_arm_link_hash_table_free;
906e58ca
NC		 4148
4149 return &ret->root.root;
4150}
4151
cd1dac3d
DG		 4152/* Determine what kind of NOPs are available. */
4153
4154static bfd_boolean
4155arch_has_arm_nop (struct elf32_arm_link_hash_table *globals)
4156{
4157 const int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
4158 Tag_CPU_arch);
cd1dac3d 4159
60a019a0 4160 /* Force return logic to be reviewed for each new architecture. */
031254f2 4161 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
60a019a0
TP		 4162
4163 return (arch == TAG_CPU_ARCH_V6T2
4164 || arch == TAG_CPU_ARCH_V6K
4165 || arch == TAG_CPU_ARCH_V7
bff0500d
TP		 4166 || arch == TAG_CPU_ARCH_V8
4167 || arch == TAG_CPU_ARCH_V8R);
cd1dac3d
DG		 4168}
4169
f4ac8484
DJ		 4170static bfd_boolean
4171arm_stub_is_thumb (enum elf32_arm_stub_type stub_type)
4172{
4173 switch (stub_type)
4174 {
fea2b4d6 4175 case arm_stub_long_branch_thumb_only:
80c135e5 4176 case arm_stub_long_branch_thumb2_only:
d5a67c02 4177 case arm_stub_long_branch_thumb2_only_pure:
fea2b4d6
CL		 4178 case arm_stub_long_branch_v4t_thumb_arm:
4179 case arm_stub_short_branch_v4t_thumb_arm:
ebe24dd4 4180 case arm_stub_long_branch_v4t_thumb_arm_pic:
12352d3f 4181 case arm_stub_long_branch_v4t_thumb_tls_pic:
ebe24dd4 4182 case arm_stub_long_branch_thumb_only_pic:
4ba2ef8f 4183 case arm_stub_cmse_branch_thumb_only:
f4ac8484
DJ		 4184 return TRUE;
4185 case arm_stub_none:
4186 BFD_FAIL ();
4187 return FALSE;
4188 break;
4189 default:
4190 return FALSE;
4191 }
4192}
4193
906e58ca
NC		 4194/* Determine the type of stub needed, if any, for a call. */
4195
4196static enum elf32_arm_stub_type
4197arm_type_of_stub (struct bfd_link_info *info,
4198 asection *input_sec,
4199 const Elf_Internal_Rela *rel,
34e77a92 4200 unsigned char st_type,
35fc36a8 4201 enum arm_st_branch_type *actual_branch_type,
906e58ca 4202 struct elf32_arm_link_hash_entry *hash,
c820be07
NC		 4203 bfd_vma destination,
4204 asection *sym_sec,
4205 bfd *input_bfd,
4206 const char *name)
906e58ca
NC		 4207{
4208 bfd_vma location;
4209 bfd_signed_vma branch_offset;
4210 unsigned int r_type;
4211 struct elf32_arm_link_hash_table * globals;
5e866f5a 4212 bfd_boolean thumb2, thumb2_bl, thumb_only;
906e58ca 4213 enum elf32_arm_stub_type stub_type = arm_stub_none;
5fa9e92f 4214 int use_plt = 0;
35fc36a8 4215 enum arm_st_branch_type branch_type = *actual_branch_type;
34e77a92
RS		 4216 union gotplt_union *root_plt;
4217 struct arm_plt_info *arm_plt;
d5a67c02
AV		 4218 int arch;
4219 int thumb2_movw;
906e58ca 4220
35fc36a8 4221 if (branch_type == ST_BRANCH_LONG)
da5938a2
NC		 4222 return stub_type;
4223
906e58ca 4224 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 4225 if (globals == NULL)
4226 return stub_type;
906e58ca
NC		 4227
4228 thumb_only = using_thumb_only (globals);
906e58ca 4229 thumb2 = using_thumb2 (globals);
5e866f5a 4230 thumb2_bl = using_thumb2_bl (globals);
906e58ca 4231
d5a67c02
AV		 4232 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
4233
4234 /* True for architectures that implement the thumb2 movw instruction. */
4235 thumb2_movw = thumb2 || (arch == TAG_CPU_ARCH_V8M_BASE);
4236
906e58ca
NC		 4237 /* Determine where the call point is. */
4238 location = (input_sec->output_offset
4239 + input_sec->output_section->vma
4240 + rel->r_offset);
4241
906e58ca
NC		 4242 r_type = ELF32_R_TYPE (rel->r_info);
4243
39f21624
NC		 4244 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
4245 are considering a function call relocation. */
c5423981 4246 if (thumb_only && (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
07d6d2b8 4247 || r_type == R_ARM_THM_JUMP19)
39f21624
NC		 4248 && branch_type == ST_BRANCH_TO_ARM)
4249 branch_type = ST_BRANCH_TO_THUMB;
4250
34e77a92
RS		 4251 /* For TLS call relocs, it is the caller's responsibility to provide
4252 the address of the appropriate trampoline. */
4253 if (r_type != R_ARM_TLS_CALL
4254 && r_type != R_ARM_THM_TLS_CALL
4ba2ef8f
TP		 4255 && elf32_arm_get_plt_info (input_bfd, globals, hash,
4256 ELF32_R_SYM (rel->r_info), &root_plt,
4257 &arm_plt)
34e77a92 4258 && root_plt->offset != (bfd_vma) -1)
5fa9e92f 4259 {
34e77a92 4260 asection *splt;
fe33d2fa 4261
34e77a92
RS		 4262 if (hash == NULL || hash->is_iplt)
4263 splt = globals->root.iplt;
4264 else
4265 splt = globals->root.splt;
4266 if (splt != NULL)
b38cadfb 4267 {
34e77a92
RS		 4268 use_plt = 1;
4269
4270 /* Note when dealing with PLT entries: the main PLT stub is in
4271 ARM mode, so if the branch is in Thumb mode, another
4272 Thumb->ARM stub will be inserted later just before the ARM
2df2751d
CL		 4273 PLT stub. If a long branch stub is needed, we'll add a
4274 Thumb->Arm one and branch directly to the ARM PLT entry.
4275 Here, we have to check if a pre-PLT Thumb->ARM stub
4276 is needed and if it will be close enough. */
34e77a92
RS		 4277
4278 destination = (splt->output_section->vma
4279 + splt->output_offset
4280 + root_plt->offset);
4281 st_type = STT_FUNC;
2df2751d
CL		 4282
4283 /* Thumb branch/call to PLT: it can become a branch to ARM
4284 or to Thumb. We must perform the same checks and
4285 corrections as in elf32_arm_final_link_relocate. */
4286 if ((r_type == R_ARM_THM_CALL)
4287 || (r_type == R_ARM_THM_JUMP24))
4288 {
4289 if (globals->use_blx
4290 && r_type == R_ARM_THM_CALL
4291 && !thumb_only)
4292 {
4293 /* If the Thumb BLX instruction is available, convert
4294 the BL to a BLX instruction to call the ARM-mode
4295 PLT entry. */
4296 branch_type = ST_BRANCH_TO_ARM;
4297 }
4298 else
4299 {
4300 if (!thumb_only)
4301 /* Target the Thumb stub before the ARM PLT entry. */
4302 destination -= PLT_THUMB_STUB_SIZE;
4303 branch_type = ST_BRANCH_TO_THUMB;
4304 }
4305 }
4306 else
4307 {
4308 branch_type = ST_BRANCH_TO_ARM;
4309 }
34e77a92 4310 }
5fa9e92f 4311 }
34e77a92
RS		 4312 /* Calls to STT_GNU_IFUNC symbols should go through a PLT. */
4313 BFD_ASSERT (st_type != STT_GNU_IFUNC);
906e58ca 4314
fe33d2fa
CL		 4315 branch_offset = (bfd_signed_vma)(destination - location);
4316
0855e32b 4317 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
c5423981 4318 || r_type == R_ARM_THM_TLS_CALL || r_type == R_ARM_THM_JUMP19)
906e58ca 4319 {
5fa9e92f
CL		 4320 /* Handle cases where:
4321 - this call goes too far (different Thumb/Thumb2 max
99059e56 4322 distance)
155d87d7 4323 - it's a Thumb->Arm call and blx is not available, or it's a
99059e56
RM		 4324 Thumb->Arm branch (not bl). A stub is needed in this case,
4325 but only if this call is not through a PLT entry. Indeed,
695344c0 4326 PLT stubs handle mode switching already. */
5e866f5a 4327 if ((!thumb2_bl
906e58ca
NC		 4328 && (branch_offset > THM_MAX_FWD_BRANCH_OFFSET
4329 || (branch_offset < THM_MAX_BWD_BRANCH_OFFSET)))
5e866f5a 4330 || (thumb2_bl
906e58ca
NC		 4331 && (branch_offset > THM2_MAX_FWD_BRANCH_OFFSET
4332 || (branch_offset < THM2_MAX_BWD_BRANCH_OFFSET)))
c5423981
TG		 4333 || (thumb2
4334 && (branch_offset > THM2_MAX_FWD_COND_BRANCH_OFFSET
4335 || (branch_offset < THM2_MAX_BWD_COND_BRANCH_OFFSET))
4336 && (r_type == R_ARM_THM_JUMP19))
35fc36a8 4337 || (branch_type == ST_BRANCH_TO_ARM
0855e32b
NS		 4338 && (((r_type == R_ARM_THM_CALL
4339 || r_type == R_ARM_THM_TLS_CALL) && !globals->use_blx)
c5423981 4340 || (r_type == R_ARM_THM_JUMP24)
07d6d2b8 4341 || (r_type == R_ARM_THM_JUMP19))
5fa9e92f 4342 && !use_plt))
906e58ca 4343 {
2df2751d
CL		 4344 /* If we need to insert a Thumb-Thumb long branch stub to a
4345 PLT, use one that branches directly to the ARM PLT
4346 stub. If we pretended we'd use the pre-PLT Thumb->ARM
4347 stub, undo this now. */
695344c0
NC		 4348 if ((branch_type == ST_BRANCH_TO_THUMB) && use_plt && !thumb_only)
4349 {
4350 branch_type = ST_BRANCH_TO_ARM;
4351 branch_offset += PLT_THUMB_STUB_SIZE;
4352 }
2df2751d 4353
35fc36a8 4354 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4355 {
4356 /* Thumb to thumb. */
4357 if (!thumb_only)
4358 {
d5a67c02 4359 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4360 _bfd_error_handler
871b3ab2 4361 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4362 " section with SHF_ARM_PURECODE section"
4363 " attribute is only supported for M-profile"
90b6238f 4364 " targets that implement the movw instruction"),
10463f39 4365 input_bfd, input_sec);
d5a67c02 4366
0e1862bb 4367 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4368 /* PIC stubs. */
155d87d7 4369 ? ((globals->use_blx
9553db3c 4370 && (r_type == R_ARM_THM_CALL))
155d87d7
CL		 4371 /* V5T and above. Stub starts with ARM code, so
4372 we must be able to switch mode before
4373 reaching it, which is only possible for 'bl'
4374 (ie R_ARM_THM_CALL relocation). */
cf3eccff 4375 ? arm_stub_long_branch_any_thumb_pic
ebe24dd4 4376 /* On V4T, use Thumb code only. */
d3626fb0 4377 : arm_stub_long_branch_v4t_thumb_thumb_pic)
c2b4a39d
CL		 4378
4379 /* non-PIC stubs. */
155d87d7 4380 : ((globals->use_blx
9553db3c 4381 && (r_type == R_ARM_THM_CALL))
c2b4a39d
CL		 4382 /* V5T and above. */
4383 ? arm_stub_long_branch_any_any
4384 /* V4T. */
d3626fb0 4385 : arm_stub_long_branch_v4t_thumb_thumb);
906e58ca
NC		 4386 }
4387 else
4388 {
d5a67c02
AV		 4389 if (thumb2_movw && (input_sec->flags & SEC_ELF_PURECODE))
4390 stub_type = arm_stub_long_branch_thumb2_only_pure;
4391 else
4392 {
4393 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4394 _bfd_error_handler
871b3ab2 4395 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4396 " section with SHF_ARM_PURECODE section"
4397 " attribute is only supported for M-profile"
90b6238f 4398 " targets that implement the movw instruction"),
10463f39 4399 input_bfd, input_sec);
d5a67c02
AV		 4400
4401 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
4402 /* PIC stub. */
4403 ? arm_stub_long_branch_thumb_only_pic
4404 /* non-PIC stub. */
4405 : (thumb2 ? arm_stub_long_branch_thumb2_only
4406 : arm_stub_long_branch_thumb_only);
4407 }
906e58ca
NC		 4408 }
4409 }
4410 else
4411 {
d5a67c02 4412 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4413 _bfd_error_handler
871b3ab2 4414 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4415 " section with SHF_ARM_PURECODE section"
4416 " attribute is only supported" " for M-profile"
90b6238f 4417 " targets that implement the movw instruction"),
10463f39 4418 input_bfd, input_sec);
d5a67c02 4419
906e58ca 4420 /* Thumb to arm. */
c820be07
NC		 4421 if (sym_sec != NULL
4422 && sym_sec->owner != NULL
4423 && !INTERWORK_FLAG (sym_sec->owner))
4424 {
4eca0228 4425 _bfd_error_handler
90b6238f
AM		 4426 (_("%pB(%s): warning: interworking not enabled;"
4427 " first occurrence: %pB: %s call to %s"),
4428 sym_sec->owner, name, input_bfd, "Thumb", "ARM");
c820be07
NC		 4429 }
4430
0855e32b 4431 stub_type =
0e1862bb 4432 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4433 /* PIC stubs. */
0855e32b 4434 ? (r_type == R_ARM_THM_TLS_CALL
6a631e86 4435 /* TLS PIC stubs. */
0855e32b
NS		 4436 ? (globals->use_blx ? arm_stub_long_branch_any_tls_pic
4437 : arm_stub_long_branch_v4t_thumb_tls_pic)
4438 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
4439 /* V5T PIC and above. */
4440 ? arm_stub_long_branch_any_arm_pic
4441 /* V4T PIC stub. */
4442 : arm_stub_long_branch_v4t_thumb_arm_pic))
c2b4a39d
CL		 4443
4444 /* non-PIC stubs. */
0855e32b 4445 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
c2b4a39d
CL		 4446 /* V5T and above. */
4447 ? arm_stub_long_branch_any_any
4448 /* V4T. */
4449 : arm_stub_long_branch_v4t_thumb_arm);
c820be07
NC		 4450
4451 /* Handle v4t short branches. */
fea2b4d6 4452 if ((stub_type == arm_stub_long_branch_v4t_thumb_arm)
c820be07
NC		 4453 && (branch_offset <= THM_MAX_FWD_BRANCH_OFFSET)
4454 && (branch_offset >= THM_MAX_BWD_BRANCH_OFFSET))
fea2b4d6 4455 stub_type = arm_stub_short_branch_v4t_thumb_arm;
906e58ca
NC		 4456 }
4457 }
4458 }
fe33d2fa
CL		 4459 else if (r_type == R_ARM_CALL
4460 || r_type == R_ARM_JUMP24
0855e32b
NS		 4461 || r_type == R_ARM_PLT32
4462 || r_type == R_ARM_TLS_CALL)
906e58ca 4463 {
d5a67c02 4464 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4465 _bfd_error_handler
871b3ab2 4466 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4467 " section with SHF_ARM_PURECODE section"
4468 " attribute is only supported for M-profile"
90b6238f 4469 " targets that implement the movw instruction"),
10463f39 4470 input_bfd, input_sec);
35fc36a8 4471 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4472 {
4473 /* Arm to thumb. */
c820be07
NC		 4474
4475 if (sym_sec != NULL
4476 && sym_sec->owner != NULL
4477 && !INTERWORK_FLAG (sym_sec->owner))
4478 {
4eca0228 4479 _bfd_error_handler
90b6238f
AM		 4480 (_("%pB(%s): warning: interworking not enabled;"
4481 " first occurrence: %pB: %s call to %s"),
4482 sym_sec->owner, name, input_bfd, "ARM", "Thumb");
c820be07
NC		 4483 }
4484
4485 /* We have an extra 2-bytes reach because of
4486 the mode change (bit 24 (H) of BLX encoding). */
4116d8d7
PB		 4487 if (branch_offset > (ARM_MAX_FWD_BRANCH_OFFSET + 2)
4488 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET)
0855e32b 4489 || (r_type == R_ARM_CALL && !globals->use_blx)
4116d8d7
PB		 4490 || (r_type == R_ARM_JUMP24)
4491 || (r_type == R_ARM_PLT32))
906e58ca 4492 {
0e1862bb 4493 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4494 /* PIC stubs. */
ebe24dd4
CL		 4495 ? ((globals->use_blx)
4496 /* V5T and above. */
4497 ? arm_stub_long_branch_any_thumb_pic
4498 /* V4T stub. */
4499 : arm_stub_long_branch_v4t_arm_thumb_pic)
4500
c2b4a39d
CL		 4501 /* non-PIC stubs. */
4502 : ((globals->use_blx)
4503 /* V5T and above. */
4504 ? arm_stub_long_branch_any_any
4505 /* V4T. */
4506 : arm_stub_long_branch_v4t_arm_thumb);
906e58ca
NC		 4507 }
4508 }
4509 else
4510 {
4511 /* Arm to arm. */
4512 if (branch_offset > ARM_MAX_FWD_BRANCH_OFFSET
4513 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET))
4514 {
0855e32b 4515 stub_type =
0e1862bb 4516 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4517 /* PIC stubs. */
0855e32b 4518 ? (r_type == R_ARM_TLS_CALL
6a631e86 4519 /* TLS PIC Stub. */
0855e32b 4520 ? arm_stub_long_branch_any_tls_pic
7a89b94e
NC		 4521 : (globals->nacl_p
4522 ? arm_stub_long_branch_arm_nacl_pic
4523 : arm_stub_long_branch_any_arm_pic))
c2b4a39d 4524 /* non-PIC stubs. */
7a89b94e
NC		 4525 : (globals->nacl_p
4526 ? arm_stub_long_branch_arm_nacl
4527 : arm_stub_long_branch_any_any);
906e58ca
NC		 4528 }
4529 }
4530 }
4531
fe33d2fa
CL		 4532 /* If a stub is needed, record the actual destination type. */
4533 if (stub_type != arm_stub_none)
35fc36a8 4534 *actual_branch_type = branch_type;
fe33d2fa 4535
906e58ca
NC		 4536 return stub_type;
4537}
4538
4539/* Build a name for an entry in the stub hash table. */
4540
4541static char *
4542elf32_arm_stub_name (const asection *input_section,
4543 const asection *sym_sec,
4544 const struct elf32_arm_link_hash_entry *hash,
fe33d2fa
CL		 4545 const Elf_Internal_Rela *rel,
4546 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4547{
4548 char *stub_name;
4549 bfd_size_type len;
4550
4551 if (hash)
4552 {
fe33d2fa 4553 len = 8 + 1 + strlen (hash->root.root.root.string) + 1 + 8 + 1 + 2 + 1;
21d799b5 4554 stub_name = (char *) bfd_malloc (len);
906e58ca 4555 if (stub_name != NULL)
fe33d2fa 4556 sprintf (stub_name, "%08x_%s+%x_%d",
906e58ca
NC		 4557 input_section->id & 0xffffffff,
4558 hash->root.root.root.string,
fe33d2fa
CL		 4559 (int) rel->r_addend & 0xffffffff,
4560 (int) stub_type);
906e58ca
NC		 4561 }
4562 else
4563 {
fe33d2fa 4564 len = 8 + 1 + 8 + 1 + 8 + 1 + 8 + 1 + 2 + 1;
21d799b5 4565 stub_name = (char *) bfd_malloc (len);
906e58ca 4566 if (stub_name != NULL)
fe33d2fa 4567 sprintf (stub_name, "%08x_%x:%x+%x_%d",
906e58ca
NC		 4568 input_section->id & 0xffffffff,
4569 sym_sec->id & 0xffffffff,
0855e32b
NS		 4570 ELF32_R_TYPE (rel->r_info) == R_ARM_TLS_CALL
4571 || ELF32_R_TYPE (rel->r_info) == R_ARM_THM_TLS_CALL
4572 ? 0 : (int) ELF32_R_SYM (rel->r_info) & 0xffffffff,
fe33d2fa
CL		 4573 (int) rel->r_addend & 0xffffffff,
4574 (int) stub_type);
906e58ca
NC		 4575 }
4576
4577 return stub_name;
4578}
4579
4580/* Look up an entry in the stub hash. Stub entries are cached because
4581 creating the stub name takes a bit of time. */
4582
4583static struct elf32_arm_stub_hash_entry *
4584elf32_arm_get_stub_entry (const asection *input_section,
4585 const asection *sym_sec,
4586 struct elf_link_hash_entry *hash,
4587 const Elf_Internal_Rela *rel,
fe33d2fa
CL		 4588 struct elf32_arm_link_hash_table *htab,
4589 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4590{
4591 struct elf32_arm_stub_hash_entry *stub_entry;
4592 struct elf32_arm_link_hash_entry *h = (struct elf32_arm_link_hash_entry *) hash;
4593 const asection *id_sec;
4594
4595 if ((input_section->flags & SEC_CODE) == 0)
4596 return NULL;
4597
4d83e8d9
CL		 4598 /* If the input section is the CMSE stubs one and it needs a long
4599 branch stub to reach it's final destination, give up with an
4600 error message: this is not supported. See PR ld/24709. */
4601 if (!strncmp (input_section->name, CMSE_STUB_NAME, strlen(CMSE_STUB_NAME)))
4602 {
4603 bfd *output_bfd = htab->obfd;
4604 asection *out_sec = bfd_get_section_by_name (output_bfd, CMSE_STUB_NAME);
4605
4606 _bfd_error_handler (_("ERROR: CMSE stub (%s section) too far "
4607 "(%#" PRIx64 ") from destination (%#" PRIx64 ")"),
4608 CMSE_STUB_NAME,
4609 (uint64_t)out_sec->output_section->vma
4610 + out_sec->output_offset,
4611 (uint64_t)sym_sec->output_section->vma
4612 + sym_sec->output_offset
4613 + h->root.root.u.def.value);
4614 /* Exit, rather than leave incompletely processed
4615 relocations. */
4616 xexit(1);
4617 }
4618
906e58ca
NC		 4619 /* If this input section is part of a group of sections sharing one
4620 stub section, then use the id of the first section in the group.
4621 Stub names need to include a section id, as there may well be
4622 more than one stub used to reach say, printf, and we need to
4623 distinguish between them. */
c2abbbeb 4624 BFD_ASSERT (input_section->id <= htab->top_id);
906e58ca
NC		 4625 id_sec = htab->stub_group[input_section->id].link_sec;
4626
4627 if (h != NULL && h->stub_cache != NULL
4628 && h->stub_cache->h == h
fe33d2fa
CL		 4629 && h->stub_cache->id_sec == id_sec
4630 && h->stub_cache->stub_type == stub_type)
906e58ca
NC		 4631 {
4632 stub_entry = h->stub_cache;
4633 }
4634 else
4635 {
4636 char *stub_name;
4637
fe33d2fa 4638 stub_name = elf32_arm_stub_name (id_sec, sym_sec, h, rel, stub_type);
906e58ca
NC		 4639 if (stub_name == NULL)
4640 return NULL;
4641
4642 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table,
4643 stub_name, FALSE, FALSE);
4644 if (h != NULL)
4645 h->stub_cache = stub_entry;
4646
4647 free (stub_name);
4648 }
4649
4650 return stub_entry;
4651}
4652
daa4adae
TP		 4653/* Whether veneers of type STUB_TYPE require to be in a dedicated output
4654 section. */
4655
4656static bfd_boolean
4657arm_dedicated_stub_output_section_required (enum elf32_arm_stub_type stub_type)
4658{
4659 if (stub_type >= max_stub_type)
4660 abort (); /* Should be unreachable. */
4661
4ba2ef8f
TP		 4662 switch (stub_type)
4663 {
4664 case arm_stub_cmse_branch_thumb_only:
4665 return TRUE;
4666
4667 default:
4668 return FALSE;
4669 }
4670
4671 abort (); /* Should be unreachable. */
daa4adae
TP		 4672}
4673
4674/* Required alignment (as a power of 2) for the dedicated section holding
4675 veneers of type STUB_TYPE, or 0 if veneers of this type are interspersed
4676 with input sections. */
4677
4678static int
4679arm_dedicated_stub_output_section_required_alignment
4680 (enum elf32_arm_stub_type stub_type)
4681{
4682 if (stub_type >= max_stub_type)
4683 abort (); /* Should be unreachable. */
4684
4ba2ef8f
TP		 4685 switch (stub_type)
4686 {
4687 /* Vectors of Secure Gateway veneers must be aligned on 32byte
4688 boundary. */
4689 case arm_stub_cmse_branch_thumb_only:
4690 return 5;
4691
4692 default:
4693 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4694 return 0;
4695 }
4696
4697 abort (); /* Should be unreachable. */
daa4adae
TP		 4698}
4699
4700/* Name of the dedicated output section to put veneers of type STUB_TYPE, or
4701 NULL if veneers of this type are interspersed with input sections. */
4702
4703static const char *
4704arm_dedicated_stub_output_section_name (enum elf32_arm_stub_type stub_type)
4705{
4706 if (stub_type >= max_stub_type)
4707 abort (); /* Should be unreachable. */
4708
4ba2ef8f
TP		 4709 switch (stub_type)
4710 {
4711 case arm_stub_cmse_branch_thumb_only:
4d83e8d9 4712 return CMSE_STUB_NAME;
4ba2ef8f
TP		 4713
4714 default:
4715 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4716 return NULL;
4717 }
4718
4719 abort (); /* Should be unreachable. */
daa4adae
TP		 4720}
4721
4722/* If veneers of type STUB_TYPE should go in a dedicated output section,
4723 returns the address of the hash table field in HTAB holding a pointer to the
4724 corresponding input section. Otherwise, returns NULL. */
4725
4726static asection **
4ba2ef8f
TP		 4727arm_dedicated_stub_input_section_ptr (struct elf32_arm_link_hash_table *htab,
4728 enum elf32_arm_stub_type stub_type)
daa4adae
TP		 4729{
4730 if (stub_type >= max_stub_type)
4731 abort (); /* Should be unreachable. */
4732
4ba2ef8f
TP		 4733 switch (stub_type)
4734 {
4735 case arm_stub_cmse_branch_thumb_only:
4736 return &htab->cmse_stub_sec;
4737
4738 default:
4739 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4740 return NULL;
4741 }
4742
4743 abort (); /* Should be unreachable. */
daa4adae
TP		 4744}
4745
4746/* Find or create a stub section to contain a stub of type STUB_TYPE. SECTION
4747 is the section that branch into veneer and can be NULL if stub should go in
4748 a dedicated output section. Returns a pointer to the stub section, and the
4749 section to which the stub section will be attached (in *LINK_SEC_P).
48229727 4750 LINK_SEC_P may be NULL. */
906e58ca 4751
48229727
JB		 4752static asection *
4753elf32_arm_create_or_find_stub_sec (asection **link_sec_p, asection *section,
daa4adae
TP		 4754 struct elf32_arm_link_hash_table *htab,
4755 enum elf32_arm_stub_type stub_type)
906e58ca 4756{
daa4adae
TP		 4757 asection *link_sec, *out_sec, **stub_sec_p;
4758 const char *stub_sec_prefix;
4759 bfd_boolean dedicated_output_section =
4760 arm_dedicated_stub_output_section_required (stub_type);
4761 int align;
906e58ca 4762
daa4adae 4763 if (dedicated_output_section)
906e58ca 4764 {
daa4adae
TP		 4765 bfd *output_bfd = htab->obfd;
4766 const char *out_sec_name =
4767 arm_dedicated_stub_output_section_name (stub_type);
4768 link_sec = NULL;
4769 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
4770 stub_sec_prefix = out_sec_name;
4771 align = arm_dedicated_stub_output_section_required_alignment (stub_type);
4772 out_sec = bfd_get_section_by_name (output_bfd, out_sec_name);
4773 if (out_sec == NULL)
906e58ca 4774 {
90b6238f 4775 _bfd_error_handler (_("no address assigned to the veneers output "
4eca0228 4776 "section %s"), out_sec_name);
daa4adae 4777 return NULL;
906e58ca 4778 }
daa4adae
TP		 4779 }
4780 else
4781 {
c2abbbeb 4782 BFD_ASSERT (section->id <= htab->top_id);
daa4adae
TP		 4783 link_sec = htab->stub_group[section->id].link_sec;
4784 BFD_ASSERT (link_sec != NULL);
4785 stub_sec_p = &htab->stub_group[section->id].stub_sec;
4786 if (*stub_sec_p == NULL)
4787 stub_sec_p = &htab->stub_group[link_sec->id].stub_sec;
4788 stub_sec_prefix = link_sec->name;
4789 out_sec = link_sec->output_section;
4790 align = htab->nacl_p ? 4 : 3;
906e58ca 4791 }
b38cadfb 4792
daa4adae
TP		 4793 if (*stub_sec_p == NULL)
4794 {
4795 size_t namelen;
4796 bfd_size_type len;
4797 char *s_name;
4798
4799 namelen = strlen (stub_sec_prefix);
4800 len = namelen + sizeof (STUB_SUFFIX);
4801 s_name = (char *) bfd_alloc (htab->stub_bfd, len);
4802 if (s_name == NULL)
4803 return NULL;
4804
4805 memcpy (s_name, stub_sec_prefix, namelen);
4806 memcpy (s_name + namelen, STUB_SUFFIX, sizeof (STUB_SUFFIX));
4807 *stub_sec_p = (*htab->add_stub_section) (s_name, out_sec, link_sec,
4808 align);
4809 if (*stub_sec_p == NULL)
4810 return NULL;
4811
4812 out_sec->flags |= SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_CODE
4813 | SEC_HAS_CONTENTS | SEC_RELOC | SEC_IN_MEMORY
4814 | SEC_KEEP;
4815 }
4816
4817 if (!dedicated_output_section)
4818 htab->stub_group[section->id].stub_sec = *stub_sec_p;
4819
48229727
JB		 4820 if (link_sec_p)
4821 *link_sec_p = link_sec;
b38cadfb 4822
daa4adae 4823 return *stub_sec_p;
48229727
JB		 4824}
4825
4826/* Add a new stub entry to the stub hash. Not all fields of the new
4827 stub entry are initialised. */
4828
4829static struct elf32_arm_stub_hash_entry *
daa4adae
TP		 4830elf32_arm_add_stub (const char *stub_name, asection *section,
4831 struct elf32_arm_link_hash_table *htab,
4832 enum elf32_arm_stub_type stub_type)
48229727
JB		 4833{
4834 asection *link_sec;
4835 asection *stub_sec;
4836 struct elf32_arm_stub_hash_entry *stub_entry;
4837
daa4adae
TP		 4838 stub_sec = elf32_arm_create_or_find_stub_sec (&link_sec, section, htab,
4839 stub_type);
48229727
JB		 4840 if (stub_sec == NULL)
4841 return NULL;
906e58ca
NC		 4842
4843 /* Enter this entry into the linker stub hash table. */
4844 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
4845 TRUE, FALSE);
4846 if (stub_entry == NULL)
4847 {
6bde4c52
TP		 4848 if (section == NULL)
4849 section = stub_sec;
871b3ab2 4850 _bfd_error_handler (_("%pB: cannot create stub entry %s"),
4eca0228 4851 section->owner, stub_name);
906e58ca
NC		 4852 return NULL;
4853 }
4854
4855 stub_entry->stub_sec = stub_sec;
0955507f 4856 stub_entry->stub_offset = (bfd_vma) -1;
906e58ca
NC		 4857 stub_entry->id_sec = link_sec;
4858
906e58ca
NC		 4859 return stub_entry;
4860}
4861
4862/* Store an Arm insn into an output section not processed by
4863 elf32_arm_write_section. */
4864
4865static void
8029a119
NC		 4866put_arm_insn (struct elf32_arm_link_hash_table * htab,
4867 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4868{
4869 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4870 bfd_putl32 (val, ptr);
4871 else
4872 bfd_putb32 (val, ptr);
4873}
4874
4875/* Store a 16-bit Thumb insn into an output section not processed by
4876 elf32_arm_write_section. */
4877
4878static void
8029a119
NC		 4879put_thumb_insn (struct elf32_arm_link_hash_table * htab,
4880 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4881{
4882 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4883 bfd_putl16 (val, ptr);
4884 else
4885 bfd_putb16 (val, ptr);
4886}
4887
a504d23a
LA		 4888/* Store a Thumb2 insn into an output section not processed by
4889 elf32_arm_write_section. */
4890
4891static void
4892put_thumb2_insn (struct elf32_arm_link_hash_table * htab,
b98e6871 4893 bfd * output_bfd, bfd_vma val, bfd_byte * ptr)
a504d23a
LA		 4894{
4895 /* T2 instructions are 16-bit streamed. */
4896 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4897 {
4898 bfd_putl16 ((val >> 16) & 0xffff, ptr);
4899 bfd_putl16 ((val & 0xffff), ptr + 2);
4900 }
4901 else
4902 {
4903 bfd_putb16 ((val >> 16) & 0xffff, ptr);
4904 bfd_putb16 ((val & 0xffff), ptr + 2);
4905 }
4906}
4907
0855e32b
NS		 4908/* If it's possible to change R_TYPE to a more efficient access
4909 model, return the new reloc type. */
4910
4911static unsigned
b38cadfb 4912elf32_arm_tls_transition (struct bfd_link_info *info, int r_type,
0855e32b
NS		 4913 struct elf_link_hash_entry *h)
4914{
4915 int is_local = (h == NULL);
4916
9cb09e33 4917 if (bfd_link_dll (info)
0e1862bb 4918 || (h && h->root.type == bfd_link_hash_undefweak))
0855e32b
NS		 4919 return r_type;
4920
b38cadfb 4921 /* We do not support relaxations for Old TLS models. */
0855e32b
NS		 4922 switch (r_type)
4923 {
4924 case R_ARM_TLS_GOTDESC:
4925 case R_ARM_TLS_CALL:
4926 case R_ARM_THM_TLS_CALL:
4927 case R_ARM_TLS_DESCSEQ:
4928 case R_ARM_THM_TLS_DESCSEQ:
4929 return is_local ? R_ARM_TLS_LE32 : R_ARM_TLS_IE32;
4930 }
4931
4932 return r_type;
4933}
4934
48229727
JB		 4935static bfd_reloc_status_type elf32_arm_final_link_relocate
4936 (reloc_howto_type *, bfd *, bfd *, asection *, bfd_byte *,
4937 Elf_Internal_Rela *, bfd_vma, struct bfd_link_info *, asection *,
34e77a92
RS		 4938 const char *, unsigned char, enum arm_st_branch_type,
4939 struct elf_link_hash_entry *, bfd_boolean *, char **);
48229727 4940
4563a860
JB		 4941static unsigned int
4942arm_stub_required_alignment (enum elf32_arm_stub_type stub_type)
4943{
4944 switch (stub_type)
4945 {
4946 case arm_stub_a8_veneer_b_cond:
4947 case arm_stub_a8_veneer_b:
4948 case arm_stub_a8_veneer_bl:
4949 return 2;
4950
4951 case arm_stub_long_branch_any_any:
4952 case arm_stub_long_branch_v4t_arm_thumb:
4953 case arm_stub_long_branch_thumb_only:
80c135e5 4954 case arm_stub_long_branch_thumb2_only:
d5a67c02 4955 case arm_stub_long_branch_thumb2_only_pure:
4563a860
JB		 4956 case arm_stub_long_branch_v4t_thumb_thumb:
4957 case arm_stub_long_branch_v4t_thumb_arm:
4958 case arm_stub_short_branch_v4t_thumb_arm:
4959 case arm_stub_long_branch_any_arm_pic:
4960 case arm_stub_long_branch_any_thumb_pic:
4961 case arm_stub_long_branch_v4t_thumb_thumb_pic:
4962 case arm_stub_long_branch_v4t_arm_thumb_pic:
4963 case arm_stub_long_branch_v4t_thumb_arm_pic:
4964 case arm_stub_long_branch_thumb_only_pic:
0855e32b
NS		 4965 case arm_stub_long_branch_any_tls_pic:
4966 case arm_stub_long_branch_v4t_thumb_tls_pic:
4ba2ef8f 4967 case arm_stub_cmse_branch_thumb_only:
4563a860
JB		 4968 case arm_stub_a8_veneer_blx:
4969 return 4;
b38cadfb 4970
7a89b94e
NC		 4971 case arm_stub_long_branch_arm_nacl:
4972 case arm_stub_long_branch_arm_nacl_pic:
4973 return 16;
4974
4563a860
JB		 4975 default:
4976 abort (); /* Should be unreachable. */
4977 }
4978}
4979
4f4faa4d
TP		 4980/* Returns whether stubs of type STUB_TYPE take over the symbol they are
4981 veneering (TRUE) or have their own symbol (FALSE). */
4982
4983static bfd_boolean
4984arm_stub_sym_claimed (enum elf32_arm_stub_type stub_type)
4985{
4986 if (stub_type >= max_stub_type)
4987 abort (); /* Should be unreachable. */
4988
4ba2ef8f
TP		 4989 switch (stub_type)
4990 {
4991 case arm_stub_cmse_branch_thumb_only:
4992 return TRUE;
4993
4994 default:
4995 return FALSE;
4996 }
4997
4998 abort (); /* Should be unreachable. */
4f4faa4d
TP		 4999}
5000
d7c5bd02
TP		 5001/* Returns the padding needed for the dedicated section used stubs of type
5002 STUB_TYPE. */
5003
5004static int
5005arm_dedicated_stub_section_padding (enum elf32_arm_stub_type stub_type)
5006{
5007 if (stub_type >= max_stub_type)
5008 abort (); /* Should be unreachable. */
5009
4ba2ef8f
TP		 5010 switch (stub_type)
5011 {
5012 case arm_stub_cmse_branch_thumb_only:
5013 return 32;
5014
5015 default:
5016 return 0;
5017 }
5018
5019 abort (); /* Should be unreachable. */
d7c5bd02
TP		 5020}
5021
0955507f
TP		 5022/* If veneers of type STUB_TYPE should go in a dedicated output section,
5023 returns the address of the hash table field in HTAB holding the offset at
5024 which new veneers should be layed out in the stub section. */
5025
5026static bfd_vma*
5027arm_new_stubs_start_offset_ptr (struct elf32_arm_link_hash_table *htab,
5028 enum elf32_arm_stub_type stub_type)
5029{
5030 switch (stub_type)
5031 {
5032 case arm_stub_cmse_branch_thumb_only:
5033 return &htab->new_cmse_stub_offset;
5034
5035 default:
5036 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
5037 return NULL;
5038 }
5039}
5040
906e58ca
NC		 5041static bfd_boolean
5042arm_build_one_stub (struct bfd_hash_entry *gen_entry,
5043 void * in_arg)
5044{
7a89b94e 5045#define MAXRELOCS 3
0955507f 5046 bfd_boolean removed_sg_veneer;
906e58ca 5047 struct elf32_arm_stub_hash_entry *stub_entry;
4dfe6ac6 5048 struct elf32_arm_link_hash_table *globals;
906e58ca 5049 struct bfd_link_info *info;
906e58ca
NC		 5050 asection *stub_sec;
5051 bfd *stub_bfd;
906e58ca
NC		 5052 bfd_byte *loc;
5053 bfd_vma sym_value;
5054 int template_size;
5055 int size;
d3ce72d0 5056 const insn_sequence *template_sequence;
906e58ca 5057 int i;
48229727
JB		 5058 int stub_reloc_idx[MAXRELOCS] = {-1, -1};
5059 int stub_reloc_offset[MAXRELOCS] = {0, 0};
5060 int nrelocs = 0;
0955507f 5061 int just_allocated = 0;
906e58ca
NC		 5062
5063 /* Massage our args to the form they really have. */
5064 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
5065 info = (struct bfd_link_info *) in_arg;
5066
abf874aa
CL		 5067 /* Fail if the target section could not be assigned to an output
5068 section. The user should fix his linker script. */
5069 if (stub_entry->target_section->output_section == NULL
5070 && info->non_contiguous_regions)
53215f21
CL		 5071 info->callbacks->einfo (_("%F%P: Could not assign '%pA' to an output section. "
5072 "Retry without --enable-non-contiguous-regions.\n"),
5073 stub_entry->target_section);
abf874aa 5074
906e58ca 5075 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 5076 if (globals == NULL)
5077 return FALSE;
906e58ca 5078
906e58ca
NC		 5079 stub_sec = stub_entry->stub_sec;
5080
4dfe6ac6 5081 if ((globals->fix_cortex_a8 < 0)
4563a860
JB		 5082 != (arm_stub_required_alignment (stub_entry->stub_type) == 2))
5083 /* We have to do less-strictly-aligned fixes last. */
eb7c4339 5084 return TRUE;
fe33d2fa 5085
0955507f
TP		 5086 /* Assign a slot at the end of section if none assigned yet. */
5087 if (stub_entry->stub_offset == (bfd_vma) -1)
5088 {
5089 stub_entry->stub_offset = stub_sec->size;
5090 just_allocated = 1;
5091 }
906e58ca
NC		 5092 loc = stub_sec->contents + stub_entry->stub_offset;
5093
5094 stub_bfd = stub_sec->owner;
5095
906e58ca
NC		 5096 /* This is the address of the stub destination. */
5097 sym_value = (stub_entry->target_value
5098 + stub_entry->target_section->output_offset
5099 + stub_entry->target_section->output_section->vma);
5100
d3ce72d0 5101 template_sequence = stub_entry->stub_template;
461a49ca 5102 template_size = stub_entry->stub_template_size;
906e58ca
NC		 5103
5104 size = 0;
461a49ca 5105 for (i = 0; i < template_size; i++)
906e58ca 5106 {
d3ce72d0 5107 switch (template_sequence[i].type)
461a49ca
DJ		 5108 {
5109 case THUMB16_TYPE:
48229727 5110 {
d3ce72d0
NC		 5111 bfd_vma data = (bfd_vma) template_sequence[i].data;
5112 if (template_sequence[i].reloc_addend != 0)
48229727 5113 {
99059e56
RM		 5114 /* We've borrowed the reloc_addend field to mean we should
5115 insert a condition code into this (Thumb-1 branch)
5116 instruction. See THUMB16_BCOND_INSN. */
5117 BFD_ASSERT ((data & 0xff00) == 0xd000);
5118 data |= ((stub_entry->orig_insn >> 22) & 0xf) << 8;
48229727 5119 }
fe33d2fa 5120 bfd_put_16 (stub_bfd, data, loc + size);
48229727
JB		 5121 size += 2;
5122 }
461a49ca 5123 break;
906e58ca 5124
48229727 5125 case THUMB32_TYPE:
fe33d2fa
CL		 5126 bfd_put_16 (stub_bfd,
5127 (template_sequence[i].data >> 16) & 0xffff,
5128 loc + size);
5129 bfd_put_16 (stub_bfd, template_sequence[i].data & 0xffff,
5130 loc + size + 2);
99059e56
RM		 5131 if (template_sequence[i].r_type != R_ARM_NONE)
5132 {
5133 stub_reloc_idx[nrelocs] = i;
5134 stub_reloc_offset[nrelocs++] = size;
5135 }
5136 size += 4;
5137 break;
48229727 5138
461a49ca 5139 case ARM_TYPE:
fe33d2fa
CL		 5140 bfd_put_32 (stub_bfd, template_sequence[i].data,
5141 loc + size);
461a49ca
DJ		 5142 /* Handle cases where the target is encoded within the
5143 instruction. */
d3ce72d0 5144 if (template_sequence[i].r_type == R_ARM_JUMP24)
461a49ca 5145 {
48229727
JB		 5146 stub_reloc_idx[nrelocs] = i;
5147 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 5148 }
5149 size += 4;
5150 break;
5151
5152 case DATA_TYPE:
d3ce72d0 5153 bfd_put_32 (stub_bfd, template_sequence[i].data, loc + size);
48229727
JB		 5154 stub_reloc_idx[nrelocs] = i;
5155 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 5156 size += 4;
5157 break;
5158
5159 default:
5160 BFD_FAIL ();
5161 return FALSE;
5162 }
906e58ca 5163 }
461a49ca 5164
0955507f
TP		 5165 if (just_allocated)
5166 stub_sec->size += size;
906e58ca 5167
461a49ca
DJ		 5168 /* Stub size has already been computed in arm_size_one_stub. Check
5169 consistency. */
5170 BFD_ASSERT (size == stub_entry->stub_size);
5171
906e58ca 5172 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
35fc36a8 5173 if (stub_entry->branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 5174 sym_value |= 1;
5175
0955507f
TP		 5176 /* Assume non empty slots have at least one and at most MAXRELOCS entries
5177 to relocate in each stub. */
5178 removed_sg_veneer =
5179 (size == 0 && stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
5180 BFD_ASSERT (removed_sg_veneer || (nrelocs != 0 && nrelocs <= MAXRELOCS));
c820be07 5181
48229727 5182 for (i = 0; i < nrelocs; i++)
8d9d9490
TP		 5183 {
5184 Elf_Internal_Rela rel;
5185 bfd_boolean unresolved_reloc;
5186 char *error_message;
5187 bfd_vma points_to =
5188 sym_value + template_sequence[stub_reloc_idx[i]].reloc_addend;
5189
5190 rel.r_offset = stub_entry->stub_offset + stub_reloc_offset[i];
5191 rel.r_info = ELF32_R_INFO (0,
5192 template_sequence[stub_reloc_idx[i]].r_type);
5193 rel.r_addend = 0;
5194
5195 if (stub_entry->stub_type == arm_stub_a8_veneer_b_cond && i == 0)
5196 /* The first relocation in the elf32_arm_stub_a8_veneer_b_cond[]
5197 template should refer back to the instruction after the original
5198 branch. We use target_section as Cortex-A8 erratum workaround stubs
5199 are only generated when both source and target are in the same
5200 section. */
5201 points_to = stub_entry->target_section->output_section->vma
5202 + stub_entry->target_section->output_offset
5203 + stub_entry->source_value;
5204
5205 elf32_arm_final_link_relocate (elf32_arm_howto_from_type
5206 (template_sequence[stub_reloc_idx[i]].r_type),
5207 stub_bfd, info->output_bfd, stub_sec, stub_sec->contents, &rel,
5208 points_to, info, stub_entry->target_section, "", STT_FUNC,
5209 stub_entry->branch_type,
5210 (struct elf_link_hash_entry *) stub_entry->h, &unresolved_reloc,
5211 &error_message);
5212 }
906e58ca
NC		 5213
5214 return TRUE;
48229727 5215#undef MAXRELOCS
906e58ca
NC		 5216}
5217
48229727
JB		 5218/* Calculate the template, template size and instruction size for a stub.
5219 Return value is the instruction size. */
906e58ca 5220
48229727
JB		 5221static unsigned int
5222find_stub_size_and_template (enum elf32_arm_stub_type stub_type,
5223 const insn_sequence **stub_template,
5224 int *stub_template_size)
906e58ca 5225{
d3ce72d0 5226 const insn_sequence *template_sequence = NULL;
48229727
JB		 5227 int template_size = 0, i;
5228 unsigned int size;
906e58ca 5229
d3ce72d0 5230 template_sequence = stub_definitions[stub_type].template_sequence;
2a229407
AM		 5231 if (stub_template)
5232 *stub_template = template_sequence;
5233
48229727 5234 template_size = stub_definitions[stub_type].template_size;
2a229407
AM		 5235 if (stub_template_size)
5236 *stub_template_size = template_size;
906e58ca
NC		 5237
5238 size = 0;
461a49ca
DJ		 5239 for (i = 0; i < template_size; i++)
5240 {
d3ce72d0 5241 switch (template_sequence[i].type)
461a49ca
DJ		 5242 {
5243 case THUMB16_TYPE:
5244 size += 2;
5245 break;
5246
5247 case ARM_TYPE:
48229727 5248 case THUMB32_TYPE:
461a49ca
DJ		 5249 case DATA_TYPE:
5250 size += 4;
5251 break;
5252
5253 default:
5254 BFD_FAIL ();
2a229407 5255 return 0;
461a49ca
DJ		 5256 }
5257 }
5258
48229727
JB		 5259 return size;
5260}
5261
5262/* As above, but don't actually build the stub. Just bump offset so
5263 we know stub section sizes. */
5264
5265static bfd_boolean
5266arm_size_one_stub (struct bfd_hash_entry *gen_entry,
c7e2358a 5267 void *in_arg ATTRIBUTE_UNUSED)
48229727
JB		 5268{
5269 struct elf32_arm_stub_hash_entry *stub_entry;
d3ce72d0 5270 const insn_sequence *template_sequence;
48229727
JB		 5271 int template_size, size;
5272
5273 /* Massage our args to the form they really have. */
5274 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
48229727
JB		 5275
5276 BFD_ASSERT((stub_entry->stub_type > arm_stub_none)
5277 && stub_entry->stub_type < ARRAY_SIZE(stub_definitions));
5278
d3ce72d0 5279 size = find_stub_size_and_template (stub_entry->stub_type, &template_sequence,
48229727
JB		 5280 &template_size);
5281
0955507f
TP		 5282 /* Initialized to -1. Null size indicates an empty slot full of zeros. */
5283 if (stub_entry->stub_template_size)
5284 {
5285 stub_entry->stub_size = size;
5286 stub_entry->stub_template = template_sequence;
5287 stub_entry->stub_template_size = template_size;
5288 }
5289
5290 /* Already accounted for. */
5291 if (stub_entry->stub_offset != (bfd_vma) -1)
5292 return TRUE;
461a49ca 5293
906e58ca
NC		 5294 size = (size + 7) & ~7;
5295 stub_entry->stub_sec->size += size;
461a49ca 5296
906e58ca
NC		 5297 return TRUE;
5298}
5299
5300/* External entry points for sizing and building linker stubs. */
5301
5302/* Set up various things so that we can make a list of input sections
5303 for each output section included in the link. Returns -1 on error,
5304 0 when no stubs will be needed, and 1 on success. */
5305
5306int
5307elf32_arm_setup_section_lists (bfd *output_bfd,
5308 struct bfd_link_info *info)
5309{
5310 bfd *input_bfd;
5311 unsigned int bfd_count;
7292b3ac 5312 unsigned int top_id, top_index;
906e58ca
NC		 5313 asection *section;
5314 asection **input_list, **list;
986f0783 5315 size_t amt;
906e58ca
NC		 5316 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5317
4dfe6ac6
NC		 5318 if (htab == NULL)
5319 return 0;
906e58ca
NC		 5320 if (! is_elf_hash_table (htab))
5321 return 0;
5322
5323 /* Count the number of input BFDs and find the top input section id. */
5324 for (input_bfd = info->input_bfds, bfd_count = 0, top_id = 0;
5325 input_bfd != NULL;
c72f2fb2 5326 input_bfd = input_bfd->link.next)
906e58ca
NC		 5327 {
5328 bfd_count += 1;
5329 for (section = input_bfd->sections;
5330 section != NULL;
5331 section = section->next)
5332 {
5333 if (top_id < section->id)
5334 top_id = section->id;
5335 }
5336 }
5337 htab->bfd_count = bfd_count;
5338
5339 amt = sizeof (struct map_stub) * (top_id + 1);
21d799b5 5340 htab->stub_group = (struct map_stub *) bfd_zmalloc (amt);
906e58ca
NC		 5341 if (htab->stub_group == NULL)
5342 return -1;
fe33d2fa 5343 htab->top_id = top_id;
906e58ca
NC		 5344
5345 /* We can't use output_bfd->section_count here to find the top output
5346 section index as some sections may have been removed, and
5347 _bfd_strip_section_from_output doesn't renumber the indices. */
5348 for (section = output_bfd->sections, top_index = 0;
5349 section != NULL;
5350 section = section->next)
5351 {
5352 if (top_index < section->index)
5353 top_index = section->index;
5354 }
5355
5356 htab->top_index = top_index;
5357 amt = sizeof (asection *) * (top_index + 1);
21d799b5 5358 input_list = (asection **) bfd_malloc (amt);
906e58ca
NC		 5359 htab->input_list = input_list;
5360 if (input_list == NULL)
5361 return -1;
5362
5363 /* For sections we aren't interested in, mark their entries with a
5364 value we can check later. */
5365 list = input_list + top_index;
5366 do
5367 *list = bfd_abs_section_ptr;
5368 while (list-- != input_list);
5369
5370 for (section = output_bfd->sections;
5371 section != NULL;
5372 section = section->next)
5373 {
5374 if ((section->flags & SEC_CODE) != 0)
5375 input_list[section->index] = NULL;
5376 }
5377
5378 return 1;
5379}
5380
5381/* The linker repeatedly calls this function for each input section,
5382 in the order that input sections are linked into output sections.
5383 Build lists of input sections to determine groupings between which
5384 we may insert linker stubs. */
5385
5386void
5387elf32_arm_next_input_section (struct bfd_link_info *info,
5388 asection *isec)
5389{
5390 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5391
4dfe6ac6
NC		 5392 if (htab == NULL)
5393 return;
5394
906e58ca
NC		 5395 if (isec->output_section->index <= htab->top_index)
5396 {
5397 asection **list = htab->input_list + isec->output_section->index;
5398
a7470592 5399 if (*list != bfd_abs_section_ptr && (isec->flags & SEC_CODE) != 0)
906e58ca
NC		 5400 {
5401 /* Steal the link_sec pointer for our list. */
5402#define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
5403 /* This happens to make the list in reverse order,
07d72278 5404 which we reverse later. */
906e58ca
NC		 5405 PREV_SEC (isec) = *list;
5406 *list = isec;
5407 }
5408 }
5409}
5410
5411/* See whether we can group stub sections together. Grouping stub
5412 sections may result in fewer stubs. More importantly, we need to
07d72278 5413 put all .init* and .fini* stubs at the end of the .init or
906e58ca
NC		 5414 .fini output sections respectively, because glibc splits the
5415 _init and _fini functions into multiple parts. Putting a stub in
5416 the middle of a function is not a good idea. */
5417
5418static void
5419group_sections (struct elf32_arm_link_hash_table *htab,
5420 bfd_size_type stub_group_size,
07d72278 5421 bfd_boolean stubs_always_after_branch)
906e58ca 5422{
07d72278 5423 asection **list = htab->input_list;
906e58ca
NC		 5424
5425 do
5426 {
5427 asection *tail = *list;
07d72278 5428 asection *head;
906e58ca
NC		 5429
5430 if (tail == bfd_abs_section_ptr)
5431 continue;
5432
07d72278
DJ		 5433 /* Reverse the list: we must avoid placing stubs at the
5434 beginning of the section because the beginning of the text
5435 section may be required for an interrupt vector in bare metal
5436 code. */
5437#define NEXT_SEC PREV_SEC
e780aef2
CL		 5438 head = NULL;
5439 while (tail != NULL)
99059e56
RM		 5440 {
5441 /* Pop from tail. */
5442 asection *item = tail;
5443 tail = PREV_SEC (item);
e780aef2 5444
99059e56
RM		 5445 /* Push on head. */
5446 NEXT_SEC (item) = head;
5447 head = item;
5448 }
07d72278
DJ		 5449
5450 while (head != NULL)
906e58ca
NC		 5451 {
5452 asection *curr;
07d72278 5453 asection *next;
e780aef2
CL		 5454 bfd_vma stub_group_start = head->output_offset;
5455 bfd_vma end_of_next;
906e58ca 5456
07d72278 5457 curr = head;
e780aef2 5458 while (NEXT_SEC (curr) != NULL)
8cd931b7 5459 {
e780aef2
CL		 5460 next = NEXT_SEC (curr);
5461 end_of_next = next->output_offset + next->size;
5462 if (end_of_next - stub_group_start >= stub_group_size)
5463 /* End of NEXT is too far from start, so stop. */
8cd931b7 5464 break;
e780aef2
CL		 5465 /* Add NEXT to the group. */
5466 curr = next;
8cd931b7 5467 }
906e58ca 5468
07d72278 5469 /* OK, the size from the start to the start of CURR is less
906e58ca 5470 than stub_group_size and thus can be handled by one stub
07d72278 5471 section. (Or the head section is itself larger than
906e58ca
NC		 5472 stub_group_size, in which case we may be toast.)
5473 We should really be keeping track of the total size of
5474 stubs added here, as stubs contribute to the final output
7fb9f789 5475 section size. */
906e58ca
NC		 5476 do
5477 {
07d72278 5478 next = NEXT_SEC (head);
906e58ca 5479 /* Set up this stub group. */
07d72278 5480 htab->stub_group[head->id].link_sec = curr;
906e58ca 5481 }
07d72278 5482 while (head != curr && (head = next) != NULL);
906e58ca
NC		 5483
5484 /* But wait, there's more! Input sections up to stub_group_size
07d72278
DJ		 5485 bytes after the stub section can be handled by it too. */
5486 if (!stubs_always_after_branch)
906e58ca 5487 {
e780aef2
CL		 5488 stub_group_start = curr->output_offset + curr->size;
5489
8cd931b7 5490 while (next != NULL)
906e58ca 5491 {
e780aef2
CL		 5492 end_of_next = next->output_offset + next->size;
5493 if (end_of_next - stub_group_start >= stub_group_size)
5494 /* End of NEXT is too far from stubs, so stop. */
8cd931b7 5495 break;
e780aef2 5496 /* Add NEXT to the stub group. */
07d72278
DJ		 5497 head = next;
5498 next = NEXT_SEC (head);
5499 htab->stub_group[head->id].link_sec = curr;
906e58ca
NC		 5500 }
5501 }
07d72278 5502 head = next;
906e58ca
NC		 5503 }
5504 }
07d72278 5505 while (list++ != htab->input_list + htab->top_index);
906e58ca
NC		 5506
5507 free (htab->input_list);
5508#undef PREV_SEC
07d72278 5509#undef NEXT_SEC
906e58ca
NC		 5510}
5511
48229727
JB		 5512/* Comparison function for sorting/searching relocations relating to Cortex-A8
5513 erratum fix. */
5514
5515static int
5516a8_reloc_compare (const void *a, const void *b)
5517{
21d799b5
NC		 5518 const struct a8_erratum_reloc *ra = (const struct a8_erratum_reloc *) a;
5519 const struct a8_erratum_reloc *rb = (const struct a8_erratum_reloc *) b;
48229727
JB		 5520
5521 if (ra->from < rb->from)
5522 return -1;
5523 else if (ra->from > rb->from)
5524 return 1;
5525 else
5526 return 0;
5527}
5528
5529static struct elf_link_hash_entry *find_thumb_glue (struct bfd_link_info *,
5530 const char *, char **);
5531
5532/* Helper function to scan code for sequences which might trigger the Cortex-A8
5533 branch/TLB erratum. Fill in the table described by A8_FIXES_P,
81694485 5534 NUM_A8_FIXES_P, A8_FIX_TABLE_SIZE_P. Returns true if an error occurs, false
48229727
JB		 5535 otherwise. */
5536
81694485
NC		 5537static bfd_boolean
5538cortex_a8_erratum_scan (bfd *input_bfd,
5539 struct bfd_link_info *info,
48229727
JB		 5540 struct a8_erratum_fix **a8_fixes_p,
5541 unsigned int *num_a8_fixes_p,
5542 unsigned int *a8_fix_table_size_p,
5543 struct a8_erratum_reloc *a8_relocs,
eb7c4339
NS		 5544 unsigned int num_a8_relocs,
5545 unsigned prev_num_a8_fixes,
5546 bfd_boolean *stub_changed_p)
48229727
JB		 5547{
5548 asection *section;
5549 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5550 struct a8_erratum_fix *a8_fixes = *a8_fixes_p;
5551 unsigned int num_a8_fixes = *num_a8_fixes_p;
5552 unsigned int a8_fix_table_size = *a8_fix_table_size_p;
5553
4dfe6ac6
NC		 5554 if (htab == NULL)
5555 return FALSE;
5556
48229727
JB		 5557 for (section = input_bfd->sections;
5558 section != NULL;
5559 section = section->next)
5560 {
5561 bfd_byte *contents = NULL;
5562 struct _arm_elf_section_data *sec_data;
5563 unsigned int span;
5564 bfd_vma base_vma;
5565
5566 if (elf_section_type (section) != SHT_PROGBITS
99059e56
RM		 5567 || (elf_section_flags (section) & SHF_EXECINSTR) == 0
5568 || (section->flags & SEC_EXCLUDE) != 0
5569 || (section->sec_info_type == SEC_INFO_TYPE_JUST_SYMS)
5570 || (section->output_section == bfd_abs_section_ptr))
5571 continue;
48229727
JB		 5572
5573 base_vma = section->output_section->vma + section->output_offset;
5574
5575 if (elf_section_data (section)->this_hdr.contents != NULL)
99059e56 5576 contents = elf_section_data (section)->this_hdr.contents;
48229727 5577 else if (! bfd_malloc_and_get_section (input_bfd, section, &contents))
99059e56 5578 return TRUE;
48229727
JB		 5579
5580 sec_data = elf32_arm_section_data (section);
5581
5582 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 5583 {
5584 unsigned int span_start = sec_data->map[span].vma;
5585 unsigned int span_end = (span == sec_data->mapcount - 1)
5586 ? section->size : sec_data->map[span + 1].vma;
5587 unsigned int i;
5588 char span_type = sec_data->map[span].type;
5589 bfd_boolean last_was_32bit = FALSE, last_was_branch = FALSE;
5590
5591 if (span_type != 't')
5592 continue;
5593
5594 /* Span is entirely within a single 4KB region: skip scanning. */
5595 if (((base_vma + span_start) & ~0xfff)
48229727 5596 == ((base_vma + span_end) & ~0xfff))
99059e56
RM		 5597 continue;
5598
5599 /* Scan for 32-bit Thumb-2 branches which span two 4K regions, where:
5600
5601 * The opcode is BLX.W, BL.W, B.W, Bcc.W
5602 * The branch target is in the same 4KB region as the
5603 first half of the branch.
5604 * The instruction before the branch is a 32-bit
5605 length non-branch instruction. */
5606 for (i = span_start; i < span_end;)
5607 {
5608 unsigned int insn = bfd_getl16 (&contents[i]);
5609 bfd_boolean insn_32bit = FALSE, is_blx = FALSE, is_b = FALSE;
48229727
JB		 5610 bfd_boolean is_bl = FALSE, is_bcc = FALSE, is_32bit_branch;
5611
99059e56
RM		 5612 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
5613 insn_32bit = TRUE;
48229727
JB		 5614
5615 if (insn_32bit)
99059e56
RM		 5616 {
5617 /* Load the rest of the insn (in manual-friendly order). */
5618 insn = (insn << 16) | bfd_getl16 (&contents[i + 2]);
5619
5620 /* Encoding T4: B<c>.W. */
5621 is_b = (insn & 0xf800d000) == 0xf0009000;
5622 /* Encoding T1: BL<c>.W. */
5623 is_bl = (insn & 0xf800d000) == 0xf000d000;
5624 /* Encoding T2: BLX<c>.W. */
5625 is_blx = (insn & 0xf800d000) == 0xf000c000;
48229727
JB		 5626 /* Encoding T3: B<c>.W (not permitted in IT block). */
5627 is_bcc = (insn & 0xf800d000) == 0xf0008000
5628 && (insn & 0x07f00000) != 0x03800000;
5629 }
5630
5631 is_32bit_branch = is_b || is_bl || is_blx || is_bcc;
fe33d2fa 5632
99059e56 5633 if (((base_vma + i) & 0xfff) == 0xffe
81694485
NC		 5634 && insn_32bit
5635 && is_32bit_branch
5636 && last_was_32bit
5637 && ! last_was_branch)
99059e56
RM		 5638 {
5639 bfd_signed_vma offset = 0;
5640 bfd_boolean force_target_arm = FALSE;
48229727 5641 bfd_boolean force_target_thumb = FALSE;
99059e56
RM		 5642 bfd_vma target;
5643 enum elf32_arm_stub_type stub_type = arm_stub_none;
5644 struct a8_erratum_reloc key, *found;
5645 bfd_boolean use_plt = FALSE;
48229727 5646
99059e56
RM		 5647 key.from = base_vma + i;
5648 found = (struct a8_erratum_reloc *)
5649 bsearch (&key, a8_relocs, num_a8_relocs,
5650 sizeof (struct a8_erratum_reloc),
5651 &a8_reloc_compare);
48229727
JB		 5652
5653 if (found)
5654 {
5655 char *error_message = NULL;
5656 struct elf_link_hash_entry *entry;
5657
5658 /* We don't care about the error returned from this
99059e56 5659 function, only if there is glue or not. */
48229727
JB		 5660 entry = find_thumb_glue (info, found->sym_name,
5661 &error_message);
5662
5663 if (entry)
5664 found->non_a8_stub = TRUE;
5665
92750f34 5666 /* Keep a simpler condition, for the sake of clarity. */
362d30a1 5667 if (htab->root.splt != NULL && found->hash != NULL
92750f34
DJ		 5668 && found->hash->root.plt.offset != (bfd_vma) -1)
5669 use_plt = TRUE;
5670
5671 if (found->r_type == R_ARM_THM_CALL)
5672 {
35fc36a8
RS		 5673 if (found->branch_type == ST_BRANCH_TO_ARM
5674 || use_plt)
92750f34
DJ		 5675 force_target_arm = TRUE;
5676 else
5677 force_target_thumb = TRUE;
5678 }
48229727
JB		 5679 }
5680
99059e56 5681 /* Check if we have an offending branch instruction. */
48229727
JB		 5682
5683 if (found && found->non_a8_stub)
5684 /* We've already made a stub for this instruction, e.g.
5685 it's a long branch or a Thumb->ARM stub. Assume that
5686 stub will suffice to work around the A8 erratum (see
5687 setting of always_after_branch above). */
5688 ;
99059e56
RM		 5689 else if (is_bcc)
5690 {
5691 offset = (insn & 0x7ff) << 1;
5692 offset |= (insn & 0x3f0000) >> 4;
5693 offset |= (insn & 0x2000) ? 0x40000 : 0;
5694 offset |= (insn & 0x800) ? 0x80000 : 0;
5695 offset |= (insn & 0x4000000) ? 0x100000 : 0;
5696 if (offset & 0x100000)
5697 offset |= ~ ((bfd_signed_vma) 0xfffff);
5698 stub_type = arm_stub_a8_veneer_b_cond;
5699 }
5700 else if (is_b || is_bl || is_blx)
5701 {
5702 int s = (insn & 0x4000000) != 0;
5703 int j1 = (insn & 0x2000) != 0;
5704 int j2 = (insn & 0x800) != 0;
5705 int i1 = !(j1 ^ s);
5706 int i2 = !(j2 ^ s);
5707
5708 offset = (insn & 0x7ff) << 1;
5709 offset |= (insn & 0x3ff0000) >> 4;
5710 offset |= i2 << 22;
5711 offset |= i1 << 23;
5712 offset |= s << 24;
5713 if (offset & 0x1000000)
5714 offset |= ~ ((bfd_signed_vma) 0xffffff);
5715
5716 if (is_blx)
5717 offset &= ~ ((bfd_signed_vma) 3);
5718
5719 stub_type = is_blx ? arm_stub_a8_veneer_blx :
5720 is_bl ? arm_stub_a8_veneer_bl : arm_stub_a8_veneer_b;
5721 }
5722
5723 if (stub_type != arm_stub_none)
5724 {
5725 bfd_vma pc_for_insn = base_vma + i + 4;
48229727
JB		 5726
5727 /* The original instruction is a BL, but the target is
99059e56 5728 an ARM instruction. If we were not making a stub,
48229727
JB		 5729 the BL would have been converted to a BLX. Use the
5730 BLX stub instead in that case. */
5731 if (htab->use_blx && force_target_arm
5732 && stub_type == arm_stub_a8_veneer_bl)
5733 {
5734 stub_type = arm_stub_a8_veneer_blx;
5735 is_blx = TRUE;
5736 is_bl = FALSE;
5737 }
5738 /* Conversely, if the original instruction was
5739 BLX but the target is Thumb mode, use the BL
5740 stub. */
5741 else if (force_target_thumb
5742 && stub_type == arm_stub_a8_veneer_blx)
5743 {
5744 stub_type = arm_stub_a8_veneer_bl;
5745 is_blx = FALSE;
5746 is_bl = TRUE;
5747 }
5748
99059e56
RM		 5749 if (is_blx)
5750 pc_for_insn &= ~ ((bfd_vma) 3);
48229727 5751
99059e56
RM		 5752 /* If we found a relocation, use the proper destination,
5753 not the offset in the (unrelocated) instruction.
48229727
JB		 5754 Note this is always done if we switched the stub type
5755 above. */
99059e56
RM		 5756 if (found)
5757 offset =
81694485 5758 (bfd_signed_vma) (found->destination - pc_for_insn);
48229727 5759
99059e56
RM		 5760 /* If the stub will use a Thumb-mode branch to a
5761 PLT target, redirect it to the preceding Thumb
5762 entry point. */
5763 if (stub_type != arm_stub_a8_veneer_blx && use_plt)
5764 offset -= PLT_THUMB_STUB_SIZE;
7d24e6a6 5765
99059e56 5766 target = pc_for_insn + offset;
48229727 5767
99059e56
RM		 5768 /* The BLX stub is ARM-mode code. Adjust the offset to
5769 take the different PC value (+8 instead of +4) into
48229727 5770 account. */
99059e56
RM		 5771 if (stub_type == arm_stub_a8_veneer_blx)
5772 offset += 4;
5773
5774 if (((base_vma + i) & ~0xfff) == (target & ~0xfff))
5775 {
5776 char *stub_name = NULL;
5777
5778 if (num_a8_fixes == a8_fix_table_size)
5779 {
5780 a8_fix_table_size *= 2;
5781 a8_fixes = (struct a8_erratum_fix *)
5782 bfd_realloc (a8_fixes,
5783 sizeof (struct a8_erratum_fix)
5784 * a8_fix_table_size);
5785 }
48229727 5786
eb7c4339
NS		 5787 if (num_a8_fixes < prev_num_a8_fixes)
5788 {
5789 /* If we're doing a subsequent scan,
5790 check if we've found the same fix as
5791 before, and try and reuse the stub
5792 name. */
5793 stub_name = a8_fixes[num_a8_fixes].stub_name;
5794 if ((a8_fixes[num_a8_fixes].section != section)
5795 || (a8_fixes[num_a8_fixes].offset != i))
5796 {
5797 free (stub_name);
5798 stub_name = NULL;
5799 *stub_changed_p = TRUE;
5800 }
5801 }
5802
5803 if (!stub_name)
5804 {
21d799b5 5805 stub_name = (char *) bfd_malloc (8 + 1 + 8 + 1);
eb7c4339
NS		 5806 if (stub_name != NULL)
5807 sprintf (stub_name, "%x:%x", section->id, i);
5808 }
48229727 5809
99059e56
RM		 5810 a8_fixes[num_a8_fixes].input_bfd = input_bfd;
5811 a8_fixes[num_a8_fixes].section = section;
5812 a8_fixes[num_a8_fixes].offset = i;
8d9d9490
TP		 5813 a8_fixes[num_a8_fixes].target_offset =
5814 target - base_vma;
99059e56
RM		 5815 a8_fixes[num_a8_fixes].orig_insn = insn;
5816 a8_fixes[num_a8_fixes].stub_name = stub_name;
5817 a8_fixes[num_a8_fixes].stub_type = stub_type;
5818 a8_fixes[num_a8_fixes].branch_type =
35fc36a8 5819 is_blx ? ST_BRANCH_TO_ARM : ST_BRANCH_TO_THUMB;
48229727 5820
99059e56
RM		 5821 num_a8_fixes++;
5822 }
5823 }
5824 }
48229727 5825
99059e56
RM		 5826 i += insn_32bit ? 4 : 2;
5827 last_was_32bit = insn_32bit;
48229727 5828 last_was_branch = is_32bit_branch;
99059e56
RM		 5829 }
5830 }
48229727
JB		 5831
5832 if (elf_section_data (section)->this_hdr.contents == NULL)
99059e56 5833 free (contents);
48229727 5834 }
fe33d2fa 5835
48229727
JB		 5836 *a8_fixes_p = a8_fixes;
5837 *num_a8_fixes_p = num_a8_fixes;
5838 *a8_fix_table_size_p = a8_fix_table_size;
fe33d2fa 5839
81694485 5840 return FALSE;
48229727
JB		 5841}
5842
b715f643
TP		 5843/* Create or update a stub entry depending on whether the stub can already be
5844 found in HTAB. The stub is identified by:
5845 - its type STUB_TYPE
5846 - its source branch (note that several can share the same stub) whose
5847 section and relocation (if any) are given by SECTION and IRELA
5848 respectively
5849 - its target symbol whose input section, hash, name, value and branch type
5850 are given in SYM_SEC, HASH, SYM_NAME, SYM_VALUE and BRANCH_TYPE
5851 respectively
5852
5853 If found, the value of the stub's target symbol is updated from SYM_VALUE
5854 and *NEW_STUB is set to FALSE. Otherwise, *NEW_STUB is set to
5855 TRUE and the stub entry is initialized.
5856
0955507f
TP		 5857 Returns the stub that was created or updated, or NULL if an error
5858 occurred. */
b715f643 5859
0955507f 5860static struct elf32_arm_stub_hash_entry *
b715f643
TP		 5861elf32_arm_create_stub (struct elf32_arm_link_hash_table *htab,
5862 enum elf32_arm_stub_type stub_type, asection *section,
5863 Elf_Internal_Rela *irela, asection *sym_sec,
5864 struct elf32_arm_link_hash_entry *hash, char *sym_name,
5865 bfd_vma sym_value, enum arm_st_branch_type branch_type,
5866 bfd_boolean *new_stub)
5867{
5868 const asection *id_sec;
5869 char *stub_name;
5870 struct elf32_arm_stub_hash_entry *stub_entry;
5871 unsigned int r_type;
4f4faa4d 5872 bfd_boolean sym_claimed = arm_stub_sym_claimed (stub_type);
b715f643
TP		 5873
5874 BFD_ASSERT (stub_type != arm_stub_none);
5875 *new_stub = FALSE;
5876
4f4faa4d
TP		 5877 if (sym_claimed)
5878 stub_name = sym_name;
5879 else
5880 {
5881 BFD_ASSERT (irela);
5882 BFD_ASSERT (section);
c2abbbeb 5883 BFD_ASSERT (section->id <= htab->top_id);
b715f643 5884
4f4faa4d
TP		 5885 /* Support for grouping stub sections. */
5886 id_sec = htab->stub_group[section->id].link_sec;
b715f643 5887
4f4faa4d
TP		 5888 /* Get the name of this stub. */
5889 stub_name = elf32_arm_stub_name (id_sec, sym_sec, hash, irela,
5890 stub_type);
5891 if (!stub_name)
0955507f 5892 return NULL;
4f4faa4d 5893 }
b715f643
TP		 5894
5895 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name, FALSE,
5896 FALSE);
5897 /* The proper stub has already been created, just update its value. */
5898 if (stub_entry != NULL)
5899 {
4f4faa4d
TP		 5900 if (!sym_claimed)
5901 free (stub_name);
b715f643 5902 stub_entry->target_value = sym_value;
0955507f 5903 return stub_entry;
b715f643
TP		 5904 }
5905
daa4adae 5906 stub_entry = elf32_arm_add_stub (stub_name, section, htab, stub_type);
b715f643
TP		 5907 if (stub_entry == NULL)
5908 {
4f4faa4d
TP		 5909 if (!sym_claimed)
5910 free (stub_name);
0955507f 5911 return NULL;
b715f643
TP		 5912 }
5913
5914 stub_entry->target_value = sym_value;
5915 stub_entry->target_section = sym_sec;
5916 stub_entry->stub_type = stub_type;
5917 stub_entry->h = hash;
5918 stub_entry->branch_type = branch_type;
5919
4f4faa4d
TP		 5920 if (sym_claimed)
5921 stub_entry->output_name = sym_name;
5922 else
b715f643 5923 {
4f4faa4d
TP		 5924 if (sym_name == NULL)
5925 sym_name = "unnamed";
5926 stub_entry->output_name = (char *)
5927 bfd_alloc (htab->stub_bfd, sizeof (THUMB2ARM_GLUE_ENTRY_NAME)
5928 + strlen (sym_name));
5929 if (stub_entry->output_name == NULL)
5930 {
5931 free (stub_name);
0955507f 5932 return NULL;
4f4faa4d 5933 }
b715f643 5934
4f4faa4d
TP		 5935 /* For historical reasons, use the existing names for ARM-to-Thumb and
5936 Thumb-to-ARM stubs. */
5937 r_type = ELF32_R_TYPE (irela->r_info);
5938 if ((r_type == (unsigned int) R_ARM_THM_CALL
5939 || r_type == (unsigned int) R_ARM_THM_JUMP24
5940 || r_type == (unsigned int) R_ARM_THM_JUMP19)
5941 && branch_type == ST_BRANCH_TO_ARM)
5942 sprintf (stub_entry->output_name, THUMB2ARM_GLUE_ENTRY_NAME, sym_name);
5943 else if ((r_type == (unsigned int) R_ARM_CALL
5944 || r_type == (unsigned int) R_ARM_JUMP24)
5945 && branch_type == ST_BRANCH_TO_THUMB)
5946 sprintf (stub_entry->output_name, ARM2THUMB_GLUE_ENTRY_NAME, sym_name);
5947 else
5948 sprintf (stub_entry->output_name, STUB_ENTRY_NAME, sym_name);
5949 }
b715f643
TP		 5950
5951 *new_stub = TRUE;
0955507f 5952 return stub_entry;
b715f643
TP		 5953}
5954
4ba2ef8f
TP		 5955/* Scan symbols in INPUT_BFD to identify secure entry functions needing a
5956 gateway veneer to transition from non secure to secure state and create them
5957 accordingly.
5958
5959 "ARMv8-M Security Extensions: Requirements on Development Tools" document
5960 defines the conditions that govern Secure Gateway veneer creation for a
5961 given symbol <SYM> as follows:
5962 - it has function type
5963 - it has non local binding
5964 - a symbol named __acle_se_<SYM> (called special symbol) exists with the
5965 same type, binding and value as <SYM> (called normal symbol).
5966 An entry function can handle secure state transition itself in which case
5967 its special symbol would have a different value from the normal symbol.
5968
5969 OUT_ATTR gives the output attributes, SYM_HASHES the symbol index to hash
5970 entry mapping while HTAB gives the name to hash entry mapping.
0955507f
TP		 5971 *CMSE_STUB_CREATED is increased by the number of secure gateway veneer
5972 created.
4ba2ef8f 5973
0955507f 5974 The return value gives whether a stub failed to be allocated. */
4ba2ef8f
TP		 5975
5976static bfd_boolean
5977cmse_scan (bfd *input_bfd, struct elf32_arm_link_hash_table *htab,
5978 obj_attribute *out_attr, struct elf_link_hash_entry **sym_hashes,
0955507f 5979 int *cmse_stub_created)
4ba2ef8f
TP		 5980{
5981 const struct elf_backend_data *bed;
5982 Elf_Internal_Shdr *symtab_hdr;
5983 unsigned i, j, sym_count, ext_start;
5984 Elf_Internal_Sym *cmse_sym, *local_syms;
5985 struct elf32_arm_link_hash_entry *hash, *cmse_hash = NULL;
5986 enum arm_st_branch_type branch_type;
5987 char *sym_name, *lsym_name;
5988 bfd_vma sym_value;
5989 asection *section;
0955507f
TP		 5990 struct elf32_arm_stub_hash_entry *stub_entry;
5991 bfd_boolean is_v8m, new_stub, cmse_invalid, ret = TRUE;
4ba2ef8f
TP		 5992
5993 bed = get_elf_backend_data (input_bfd);
5994 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
5995 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
5996 ext_start = symtab_hdr->sh_info;
5997 is_v8m = (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
5998 && out_attr[Tag_CPU_arch_profile].i == 'M');
5999
6000 local_syms = (Elf_Internal_Sym *) symtab_hdr->contents;
6001 if (local_syms == NULL)
6002 local_syms = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
6003 symtab_hdr->sh_info, 0, NULL, NULL,
6004 NULL);
6005 if (symtab_hdr->sh_info && local_syms == NULL)
6006 return FALSE;
6007
6008 /* Scan symbols. */
6009 for (i = 0; i < sym_count; i++)
6010 {
6011 cmse_invalid = FALSE;
6012
6013 if (i < ext_start)
6014 {
6015 cmse_sym = &local_syms[i];
4ba2ef8f
TP		 6016 sym_name = bfd_elf_string_from_elf_section (input_bfd,
6017 symtab_hdr->sh_link,
6018 cmse_sym->st_name);
baf46cd7
AM		 6019 if (!sym_name || !CONST_STRNEQ (sym_name, CMSE_PREFIX))
6020 continue;
6021
4ba2ef8f
TP		 6022 /* Special symbol with local binding. */
6023 cmse_invalid = TRUE;
6024 }
6025 else
6026 {
6027 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
6028 sym_name = (char *) cmse_hash->root.root.root.string;
baf46cd7 6029 if (!CONST_STRNEQ (sym_name, CMSE_PREFIX))
4ba2ef8f
TP		 6030 continue;
6031
6032 /* Special symbol has incorrect binding or type. */
6033 if ((cmse_hash->root.root.type != bfd_link_hash_defined
6034 && cmse_hash->root.root.type != bfd_link_hash_defweak)
6035 || cmse_hash->root.type != STT_FUNC)
6036 cmse_invalid = TRUE;
6037 }
6038
6039 if (!is_v8m)
6040 {
90b6238f
AM		 6041 _bfd_error_handler (_("%pB: special symbol `%s' only allowed for "
6042 "ARMv8-M architecture or later"),
4eca0228 6043 input_bfd, sym_name);
4ba2ef8f
TP		 6044 is_v8m = TRUE; /* Avoid multiple warning. */
6045 ret = FALSE;
6046 }
6047
6048 if (cmse_invalid)
6049 {
90b6238f
AM		 6050 _bfd_error_handler (_("%pB: invalid special symbol `%s'; it must be"
6051 " a global or weak function symbol"),
4eca0228 6052 input_bfd, sym_name);
4ba2ef8f
TP		 6053 ret = FALSE;
6054 if (i < ext_start)
6055 continue;
6056 }
6057
6058 sym_name += strlen (CMSE_PREFIX);
6059 hash = (struct elf32_arm_link_hash_entry *)
6060 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
6061
6062 /* No associated normal symbol or it is neither global nor weak. */
6063 if (!hash
6064 || (hash->root.root.type != bfd_link_hash_defined
6065 && hash->root.root.type != bfd_link_hash_defweak)
6066 || hash->root.type != STT_FUNC)
6067 {
6068 /* Initialize here to avoid warning about use of possibly
6069 uninitialized variable. */
6070 j = 0;
6071
6072 if (!hash)
6073 {
6074 /* Searching for a normal symbol with local binding. */
6075 for (; j < ext_start; j++)
6076 {
6077 lsym_name =
6078 bfd_elf_string_from_elf_section (input_bfd,
6079 symtab_hdr->sh_link,
6080 local_syms[j].st_name);
6081 if (!strcmp (sym_name, lsym_name))
6082 break;
6083 }
6084 }
6085
6086 if (hash || j < ext_start)
6087 {
4eca0228 6088 _bfd_error_handler
90b6238f
AM		 6089 (_("%pB: invalid standard symbol `%s'; it must be "
6090 "a global or weak function symbol"),
6091 input_bfd, sym_name);
4ba2ef8f
TP		 6092 }
6093 else
4eca0228 6094 _bfd_error_handler
90b6238f 6095 (_("%pB: absent standard symbol `%s'"), input_bfd, sym_name);
4ba2ef8f
TP		 6096 ret = FALSE;
6097 if (!hash)
6098 continue;
6099 }
6100
6101 sym_value = hash->root.root.u.def.value;
6102 section = hash->root.root.u.def.section;
6103
6104 if (cmse_hash->root.root.u.def.section != section)
6105 {
4eca0228 6106 _bfd_error_handler
90b6238f 6107 (_("%pB: `%s' and its special symbol are in different sections"),
4ba2ef8f
TP		 6108 input_bfd, sym_name);
6109 ret = FALSE;
6110 }
6111 if (cmse_hash->root.root.u.def.value != sym_value)
6112 continue; /* Ignore: could be an entry function starting with SG. */
6113
6114 /* If this section is a link-once section that will be discarded, then
6115 don't create any stubs. */
6116 if (section->output_section == NULL)
6117 {
4eca0228 6118 _bfd_error_handler
90b6238f 6119 (_("%pB: entry function `%s' not output"), input_bfd, sym_name);
4ba2ef8f
TP		 6120 continue;
6121 }
6122
6123 if (hash->root.size == 0)
6124 {
4eca0228 6125 _bfd_error_handler
90b6238f 6126 (_("%pB: entry function `%s' is empty"), input_bfd, sym_name);
4ba2ef8f
TP		 6127 ret = FALSE;
6128 }
6129
6130 if (!ret)
6131 continue;
6132 branch_type = ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
0955507f 6133 stub_entry
4ba2ef8f
TP		 6134 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
6135 NULL, NULL, section, hash, sym_name,
6136 sym_value, branch_type, &new_stub);
6137
0955507f 6138 if (stub_entry == NULL)
4ba2ef8f
TP		 6139 ret = FALSE;
6140 else
6141 {
6142 BFD_ASSERT (new_stub);
0955507f 6143 (*cmse_stub_created)++;
4ba2ef8f
TP		 6144 }
6145 }
6146
6147 if (!symtab_hdr->contents)
6148 free (local_syms);
6149 return ret;
6150}
6151
0955507f
TP		 6152/* Return TRUE iff a symbol identified by its linker HASH entry is a secure
6153 code entry function, ie can be called from non secure code without using a
6154 veneer. */
6155
6156static bfd_boolean
6157cmse_entry_fct_p (struct elf32_arm_link_hash_entry *hash)
6158{
42484486 6159 bfd_byte contents[4];
0955507f
TP		 6160 uint32_t first_insn;
6161 asection *section;
6162 file_ptr offset;
6163 bfd *abfd;
6164
6165 /* Defined symbol of function type. */
6166 if (hash->root.root.type != bfd_link_hash_defined
6167 && hash->root.root.type != bfd_link_hash_defweak)
6168 return FALSE;
6169 if (hash->root.type != STT_FUNC)
6170 return FALSE;
6171
6172 /* Read first instruction. */
6173 section = hash->root.root.u.def.section;
6174 abfd = section->owner;
6175 offset = hash->root.root.u.def.value - section->vma;
42484486
TP		 6176 if (!bfd_get_section_contents (abfd, section, contents, offset,
6177 sizeof (contents)))
0955507f
TP		 6178 return FALSE;
6179
42484486
TP		 6180 first_insn = bfd_get_32 (abfd, contents);
6181
6182 /* Starts by SG instruction. */
0955507f
TP		 6183 return first_insn == 0xe97fe97f;
6184}
6185
6186/* Output the name (in symbol table) of the veneer GEN_ENTRY if it is a new
6187 secure gateway veneers (ie. the veneers was not in the input import library)
6188 and there is no output import library (GEN_INFO->out_implib_bfd is NULL. */
6189
6190static bfd_boolean
6191arm_list_new_cmse_stub (struct bfd_hash_entry *gen_entry, void *gen_info)
6192{
6193 struct elf32_arm_stub_hash_entry *stub_entry;
6194 struct bfd_link_info *info;
6195
6196 /* Massage our args to the form they really have. */
6197 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
6198 info = (struct bfd_link_info *) gen_info;
6199
6200 if (info->out_implib_bfd)
6201 return TRUE;
6202
6203 if (stub_entry->stub_type != arm_stub_cmse_branch_thumb_only)
6204 return TRUE;
6205
6206 if (stub_entry->stub_offset == (bfd_vma) -1)
4eca0228 6207 _bfd_error_handler (" %s", stub_entry->output_name);
0955507f
TP		 6208
6209 return TRUE;
6210}
6211
6212/* Set offset of each secure gateway veneers so that its address remain
6213 identical to the one in the input import library referred by
6214 HTAB->in_implib_bfd. A warning is issued for veneers that disappeared
6215 (present in input import library but absent from the executable being
6216 linked) or if new veneers appeared and there is no output import library
6217 (INFO->out_implib_bfd is NULL and *CMSE_STUB_CREATED is bigger than the
6218 number of secure gateway veneers found in the input import library.
6219
6220 The function returns whether an error occurred. If no error occurred,
6221 *CMSE_STUB_CREATED gives the number of SG veneers created by both cmse_scan
6222 and this function and HTAB->new_cmse_stub_offset is set to the biggest
6223 veneer observed set for new veneers to be layed out after. */
6224
6225static bfd_boolean
6226set_cmse_veneer_addr_from_implib (struct bfd_link_info *info,
6227 struct elf32_arm_link_hash_table *htab,
6228 int *cmse_stub_created)
6229{
6230 long symsize;
6231 char *sym_name;
6232 flagword flags;
6233 long i, symcount;
6234 bfd *in_implib_bfd;
6235 asection *stub_out_sec;
6236 bfd_boolean ret = TRUE;
6237 Elf_Internal_Sym *intsym;
6238 const char *out_sec_name;
6239 bfd_size_type cmse_stub_size;
6240 asymbol **sympp = NULL, *sym;
6241 struct elf32_arm_link_hash_entry *hash;
6242 const insn_sequence *cmse_stub_template;
6243 struct elf32_arm_stub_hash_entry *stub_entry;
6244 int cmse_stub_template_size, new_cmse_stubs_created = *cmse_stub_created;
6245 bfd_vma veneer_value, stub_offset, next_cmse_stub_offset;
6246 bfd_vma cmse_stub_array_start = (bfd_vma) -1, cmse_stub_sec_vma = 0;
6247
6248 /* No input secure gateway import library. */
6249 if (!htab->in_implib_bfd)
6250 return TRUE;
6251
6252 in_implib_bfd = htab->in_implib_bfd;
6253 if (!htab->cmse_implib)
6254 {
871b3ab2 6255 _bfd_error_handler (_("%pB: --in-implib only supported for Secure "
90b6238f 6256 "Gateway import libraries"), in_implib_bfd);
0955507f
TP		 6257 return FALSE;
6258 }
6259
6260 /* Get symbol table size. */
6261 symsize = bfd_get_symtab_upper_bound (in_implib_bfd);
6262 if (symsize < 0)
6263 return FALSE;
6264
6265 /* Read in the input secure gateway import library's symbol table. */
9a733151
AM		 6266 sympp = (asymbol **) bfd_malloc (symsize);
6267 if (sympp == NULL)
6268 return FALSE;
6269
0955507f
TP		 6270 symcount = bfd_canonicalize_symtab (in_implib_bfd, sympp);
6271 if (symcount < 0)
6272 {
6273 ret = FALSE;
6274 goto free_sym_buf;
6275 }
6276
6277 htab->new_cmse_stub_offset = 0;
6278 cmse_stub_size =
6279 find_stub_size_and_template (arm_stub_cmse_branch_thumb_only,
6280 &cmse_stub_template,
6281 &cmse_stub_template_size);
6282 out_sec_name =
6283 arm_dedicated_stub_output_section_name (arm_stub_cmse_branch_thumb_only);
6284 stub_out_sec =
6285 bfd_get_section_by_name (htab->obfd, out_sec_name);
6286 if (stub_out_sec != NULL)
6287 cmse_stub_sec_vma = stub_out_sec->vma;
6288
6289 /* Set addresses of veneers mentionned in input secure gateway import
6290 library's symbol table. */
6291 for (i = 0; i < symcount; i++)
6292 {
6293 sym = sympp[i];
6294 flags = sym->flags;
6295 sym_name = (char *) bfd_asymbol_name (sym);
6296 intsym = &((elf_symbol_type *) sym)->internal_elf_sym;
6297
6298 if (sym->section != bfd_abs_section_ptr
6299 || !(flags & (BSF_GLOBAL | BSF_WEAK))
6300 || (flags & BSF_FUNCTION) != BSF_FUNCTION
6301 || (ARM_GET_SYM_BRANCH_TYPE (intsym->st_target_internal)
6302 != ST_BRANCH_TO_THUMB))
6303 {
90b6238f
AM		 6304 _bfd_error_handler (_("%pB: invalid import library entry: `%s'; "
6305 "symbol should be absolute, global and "
6306 "refer to Thumb functions"),
4eca0228 6307 in_implib_bfd, sym_name);
0955507f
TP		 6308 ret = FALSE;
6309 continue;
6310 }
6311
6312 veneer_value = bfd_asymbol_value (sym);
6313 stub_offset = veneer_value - cmse_stub_sec_vma;
6314 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, sym_name,
6315 FALSE, FALSE);
6316 hash = (struct elf32_arm_link_hash_entry *)
6317 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
6318
6319 /* Stub entry should have been created by cmse_scan or the symbol be of
6320 a secure function callable from non secure code. */
6321 if (!stub_entry && !hash)
6322 {
6323 bfd_boolean new_stub;
6324
4eca0228 6325 _bfd_error_handler
90b6238f 6326 (_("entry function `%s' disappeared from secure code"), sym_name);
0955507f
TP		 6327 hash = (struct elf32_arm_link_hash_entry *)
6328 elf_link_hash_lookup (&(htab)->root, sym_name, TRUE, TRUE, TRUE);
6329 stub_entry
6330 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
6331 NULL, NULL, bfd_abs_section_ptr, hash,
6332 sym_name, veneer_value,
6333 ST_BRANCH_TO_THUMB, &new_stub);
6334 if (stub_entry == NULL)
6335 ret = FALSE;
6336 else
6337 {
6338 BFD_ASSERT (new_stub);
6339 new_cmse_stubs_created++;
6340 (*cmse_stub_created)++;
6341 }
6342 stub_entry->stub_template_size = stub_entry->stub_size = 0;
6343 stub_entry->stub_offset = stub_offset;
6344 }
6345 /* Symbol found is not callable from non secure code. */
6346 else if (!stub_entry)
6347 {
6348 if (!cmse_entry_fct_p (hash))
6349 {
90b6238f 6350 _bfd_error_handler (_("`%s' refers to a non entry function"),
4eca0228 6351 sym_name);
0955507f
TP		 6352 ret = FALSE;
6353 }
6354 continue;
6355 }
6356 else
6357 {
6358 /* Only stubs for SG veneers should have been created. */
6359 BFD_ASSERT (stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
6360
6361 /* Check visibility hasn't changed. */
6362 if (!!(flags & BSF_GLOBAL)
6363 != (hash->root.root.type == bfd_link_hash_defined))
4eca0228 6364 _bfd_error_handler
90b6238f 6365 (_("%pB: visibility of symbol `%s' has changed"), in_implib_bfd,
0955507f
TP		 6366 sym_name);
6367
6368 stub_entry->stub_offset = stub_offset;
6369 }
6370
6371 /* Size should match that of a SG veneer. */
6372 if (intsym->st_size != cmse_stub_size)
6373 {
90b6238f 6374 _bfd_error_handler (_("%pB: incorrect size for symbol `%s'"),
4eca0228 6375 in_implib_bfd, sym_name);
0955507f
TP		 6376 ret = FALSE;
6377 }
6378
6379 /* Previous veneer address is before current SG veneer section. */
6380 if (veneer_value < cmse_stub_sec_vma)
6381 {
6382 /* Avoid offset underflow. */
6383 if (stub_entry)
6384 stub_entry->stub_offset = 0;
6385 stub_offset = 0;
6386 ret = FALSE;
6387 }
6388
6389 /* Complain if stub offset not a multiple of stub size. */
6390 if (stub_offset % cmse_stub_size)
6391 {
4eca0228 6392 _bfd_error_handler
90b6238f
AM		 6393 (_("offset of veneer for entry function `%s' not a multiple of "
6394 "its size"), sym_name);
0955507f
TP		 6395 ret = FALSE;
6396 }
6397
6398 if (!ret)
6399 continue;
6400
6401 new_cmse_stubs_created--;
6402 if (veneer_value < cmse_stub_array_start)
6403 cmse_stub_array_start = veneer_value;
6404 next_cmse_stub_offset = stub_offset + ((cmse_stub_size + 7) & ~7);
6405 if (next_cmse_stub_offset > htab->new_cmse_stub_offset)
6406 htab->new_cmse_stub_offset = next_cmse_stub_offset;
6407 }
6408
6409 if (!info->out_implib_bfd && new_cmse_stubs_created != 0)
6410 {
6411 BFD_ASSERT (new_cmse_stubs_created > 0);
4eca0228 6412 _bfd_error_handler
0955507f
TP		 6413 (_("new entry function(s) introduced but no output import library "
6414 "specified:"));
6415 bfd_hash_traverse (&htab->stub_hash_table, arm_list_new_cmse_stub, info);
6416 }
6417
6418 if (cmse_stub_array_start != cmse_stub_sec_vma)
6419 {
4eca0228 6420 _bfd_error_handler
90b6238f 6421 (_("start address of `%s' is different from previous link"),
0955507f
TP		 6422 out_sec_name);
6423 ret = FALSE;
6424 }
6425
dc1e8a47 6426 free_sym_buf:
0955507f
TP		 6427 free (sympp);
6428 return ret;
6429}
6430
906e58ca
NC		 6431/* Determine and set the size of the stub section for a final link.
6432
6433 The basic idea here is to examine all the relocations looking for
6434 PC-relative calls to a target that is unreachable with a "bl"
6435 instruction. */
6436
6437bfd_boolean
6438elf32_arm_size_stubs (bfd *output_bfd,
6439 bfd *stub_bfd,
6440 struct bfd_link_info *info,
6441 bfd_signed_vma group_size,
7a89b94e 6442 asection * (*add_stub_section) (const char *, asection *,
6bde4c52 6443 asection *,
7a89b94e 6444 unsigned int),
906e58ca
NC		 6445 void (*layout_sections_again) (void))
6446{
0955507f 6447 bfd_boolean ret = TRUE;
4ba2ef8f 6448 obj_attribute *out_attr;
0955507f 6449 int cmse_stub_created = 0;
906e58ca 6450 bfd_size_type stub_group_size;
4ba2ef8f 6451 bfd_boolean m_profile, stubs_always_after_branch, first_veneer_scan = TRUE;
906e58ca 6452 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
48229727 6453 struct a8_erratum_fix *a8_fixes = NULL;
eb7c4339 6454 unsigned int num_a8_fixes = 0, a8_fix_table_size = 10;
48229727
JB		 6455 struct a8_erratum_reloc *a8_relocs = NULL;
6456 unsigned int num_a8_relocs = 0, a8_reloc_table_size = 10, i;
6457
4dfe6ac6
NC		 6458 if (htab == NULL)
6459 return FALSE;
6460
48229727
JB		 6461 if (htab->fix_cortex_a8)
6462 {
21d799b5 6463 a8_fixes = (struct a8_erratum_fix *)
99059e56 6464 bfd_zmalloc (sizeof (struct a8_erratum_fix) * a8_fix_table_size);
21d799b5 6465 a8_relocs = (struct a8_erratum_reloc *)
99059e56 6466 bfd_zmalloc (sizeof (struct a8_erratum_reloc) * a8_reloc_table_size);
48229727 6467 }
906e58ca
NC		 6468
6469 /* Propagate mach to stub bfd, because it may not have been
6470 finalized when we created stub_bfd. */
6471 bfd_set_arch_mach (stub_bfd, bfd_get_arch (output_bfd),
6472 bfd_get_mach (output_bfd));
6473
6474 /* Stash our params away. */
6475 htab->stub_bfd = stub_bfd;
6476 htab->add_stub_section = add_stub_section;
6477 htab->layout_sections_again = layout_sections_again;
07d72278 6478 stubs_always_after_branch = group_size < 0;
48229727 6479
4ba2ef8f
TP		 6480 out_attr = elf_known_obj_attributes_proc (output_bfd);
6481 m_profile = out_attr[Tag_CPU_arch_profile].i == 'M';
0955507f 6482
48229727
JB		 6483 /* The Cortex-A8 erratum fix depends on stubs not being in the same 4K page
6484 as the first half of a 32-bit branch straddling two 4K pages. This is a
6485 crude way of enforcing that. */
6486 if (htab->fix_cortex_a8)
6487 stubs_always_after_branch = 1;
6488
906e58ca
NC		 6489 if (group_size < 0)
6490 stub_group_size = -group_size;
6491 else
6492 stub_group_size = group_size;
6493
6494 if (stub_group_size == 1)
6495 {
6496 /* Default values. */
6497 /* Thumb branch range is +-4MB has to be used as the default
6498 maximum size (a given section can contain both ARM and Thumb
6499 code, so the worst case has to be taken into account).
6500
6501 This value is 24K less than that, which allows for 2025
6502 12-byte stubs. If we exceed that, then we will fail to link.
6503 The user will have to relink with an explicit group size
6504 option. */
6505 stub_group_size = 4170000;
6506 }
6507
07d72278 6508 group_sections (htab, stub_group_size, stubs_always_after_branch);
906e58ca 6509
3ae046cc
NS		 6510 /* If we're applying the cortex A8 fix, we need to determine the
6511 program header size now, because we cannot change it later --
6512 that could alter section placements. Notice the A8 erratum fix
6513 ends up requiring the section addresses to remain unchanged
6514 modulo the page size. That's something we cannot represent
6515 inside BFD, and we don't want to force the section alignment to
6516 be the page size. */
6517 if (htab->fix_cortex_a8)
6518 (*htab->layout_sections_again) ();
6519
906e58ca
NC		 6520 while (1)
6521 {
6522 bfd *input_bfd;
6523 unsigned int bfd_indx;
6524 asection *stub_sec;
d7c5bd02 6525 enum elf32_arm_stub_type stub_type;
eb7c4339
NS		 6526 bfd_boolean stub_changed = FALSE;
6527 unsigned prev_num_a8_fixes = num_a8_fixes;
906e58ca 6528
48229727 6529 num_a8_fixes = 0;
906e58ca
NC		 6530 for (input_bfd = info->input_bfds, bfd_indx = 0;
6531 input_bfd != NULL;
c72f2fb2 6532 input_bfd = input_bfd->link.next, bfd_indx++)
906e58ca
NC		 6533 {
6534 Elf_Internal_Shdr *symtab_hdr;
6535 asection *section;
6536 Elf_Internal_Sym *local_syms = NULL;
6537
73d5efd7
AM		 6538 if (!is_arm_elf (input_bfd))
6539 continue;
6540 if ((input_bfd->flags & DYNAMIC) != 0
6541 && (elf_sym_hashes (input_bfd) == NULL
6542 || (elf_dyn_lib_class (input_bfd) & DYN_AS_NEEDED) != 0))
99059e56 6543 continue;
adbcc655 6544
48229727
JB		 6545 num_a8_relocs = 0;
6546
906e58ca
NC		 6547 /* We'll need the symbol table in a second. */
6548 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
6549 if (symtab_hdr->sh_info == 0)
6550 continue;
6551
4ba2ef8f
TP		 6552 /* Limit scan of symbols to object file whose profile is
6553 Microcontroller to not hinder performance in the general case. */
6554 if (m_profile && first_veneer_scan)
6555 {
6556 struct elf_link_hash_entry **sym_hashes;
6557
6558 sym_hashes = elf_sym_hashes (input_bfd);
6559 if (!cmse_scan (input_bfd, htab, out_attr, sym_hashes,
0955507f 6560 &cmse_stub_created))
4ba2ef8f 6561 goto error_ret_free_local;
0955507f
TP		 6562
6563 if (cmse_stub_created != 0)
6564 stub_changed = TRUE;
4ba2ef8f
TP		 6565 }
6566
906e58ca
NC		 6567 /* Walk over each section attached to the input bfd. */
6568 for (section = input_bfd->sections;
6569 section != NULL;
6570 section = section->next)
6571 {
6572 Elf_Internal_Rela *internal_relocs, *irelaend, *irela;
6573
6574 /* If there aren't any relocs, then there's nothing more
6575 to do. */
6576 if ((section->flags & SEC_RELOC) == 0
6577 || section->reloc_count == 0
6578 || (section->flags & SEC_CODE) == 0)
6579 continue;
6580
6581 /* If this section is a link-once section that will be
6582 discarded, then don't create any stubs. */
6583 if (section->output_section == NULL
6584 || section->output_section->owner != output_bfd)
6585 continue;
6586
6587 /* Get the relocs. */
6588 internal_relocs
6589 = _bfd_elf_link_read_relocs (input_bfd, section, NULL,
6590 NULL, info->keep_memory);
6591 if (internal_relocs == NULL)
6592 goto error_ret_free_local;
6593
6594 /* Now examine each relocation. */
6595 irela = internal_relocs;
6596 irelaend = irela + section->reloc_count;
6597 for (; irela < irelaend; irela++)
6598 {
6599 unsigned int r_type, r_indx;
906e58ca
NC		 6600 asection *sym_sec;
6601 bfd_vma sym_value;
6602 bfd_vma destination;
6603 struct elf32_arm_link_hash_entry *hash;
7413f23f 6604 const char *sym_name;
34e77a92 6605 unsigned char st_type;
35fc36a8 6606 enum arm_st_branch_type branch_type;
48229727 6607 bfd_boolean created_stub = FALSE;
906e58ca
NC		 6608
6609 r_type = ELF32_R_TYPE (irela->r_info);
6610 r_indx = ELF32_R_SYM (irela->r_info);
6611
6612 if (r_type >= (unsigned int) R_ARM_max)
6613 {
6614 bfd_set_error (bfd_error_bad_value);
6615 error_ret_free_internal:
6616 if (elf_section_data (section)->relocs == NULL)
6617 free (internal_relocs);
15dd01b1
TP		 6618 /* Fall through. */
6619 error_ret_free_local:
6620 if (local_syms != NULL
6621 && (symtab_hdr->contents
6622 != (unsigned char *) local_syms))
6623 free (local_syms);
6624 return FALSE;
906e58ca 6625 }
b38cadfb 6626
0855e32b
NS		 6627 hash = NULL;
6628 if (r_indx >= symtab_hdr->sh_info)
6629 hash = elf32_arm_hash_entry
6630 (elf_sym_hashes (input_bfd)
6631 [r_indx - symtab_hdr->sh_info]);
b38cadfb 6632
0855e32b
NS		 6633 /* Only look for stubs on branch instructions, or
6634 non-relaxed TLSCALL */
906e58ca 6635 if ((r_type != (unsigned int) R_ARM_CALL)
155d87d7
CL		 6636 && (r_type != (unsigned int) R_ARM_THM_CALL)
6637 && (r_type != (unsigned int) R_ARM_JUMP24)
48229727
JB		 6638 && (r_type != (unsigned int) R_ARM_THM_JUMP19)
6639 && (r_type != (unsigned int) R_ARM_THM_XPC22)
155d87d7 6640 && (r_type != (unsigned int) R_ARM_THM_JUMP24)
0855e32b
NS		 6641 && (r_type != (unsigned int) R_ARM_PLT32)
6642 && !((r_type == (unsigned int) R_ARM_TLS_CALL
6643 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6644 && r_type == elf32_arm_tls_transition
6645 (info, r_type, &hash->root)
6646 && ((hash ? hash->tls_type
6647 : (elf32_arm_local_got_tls_type
6648 (input_bfd)[r_indx]))
6649 & GOT_TLS_GDESC) != 0))
906e58ca
NC		 6650 continue;
6651
6652 /* Now determine the call target, its name, value,
6653 section. */
6654 sym_sec = NULL;
6655 sym_value = 0;
6656 destination = 0;
7413f23f 6657 sym_name = NULL;
b38cadfb 6658
0855e32b
NS		 6659 if (r_type == (unsigned int) R_ARM_TLS_CALL
6660 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6661 {
6662 /* A non-relaxed TLS call. The target is the
6663 plt-resident trampoline and nothing to do
6664 with the symbol. */
6665 BFD_ASSERT (htab->tls_trampoline > 0);
6666 sym_sec = htab->root.splt;
6667 sym_value = htab->tls_trampoline;
6668 hash = 0;
34e77a92 6669 st_type = STT_FUNC;
35fc36a8 6670 branch_type = ST_BRANCH_TO_ARM;
0855e32b
NS		 6671 }
6672 else if (!hash)
906e58ca
NC		 6673 {
6674 /* It's a local symbol. */
6675 Elf_Internal_Sym *sym;
906e58ca
NC		 6676
6677 if (local_syms == NULL)
6678 {
6679 local_syms
6680 = (Elf_Internal_Sym *) symtab_hdr->contents;
6681 if (local_syms == NULL)
6682 local_syms
6683 = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
6684 symtab_hdr->sh_info, 0,
6685 NULL, NULL, NULL);
6686 if (local_syms == NULL)
6687 goto error_ret_free_internal;
6688 }
6689
6690 sym = local_syms + r_indx;
f6d250ce
TS		 6691 if (sym->st_shndx == SHN_UNDEF)
6692 sym_sec = bfd_und_section_ptr;
6693 else if (sym->st_shndx == SHN_ABS)
6694 sym_sec = bfd_abs_section_ptr;
6695 else if (sym->st_shndx == SHN_COMMON)
6696 sym_sec = bfd_com_section_ptr;
6697 else
6698 sym_sec =
6699 bfd_section_from_elf_index (input_bfd, sym->st_shndx);
6700
ffcb4889
NS		 6701 if (!sym_sec)
6702 /* This is an undefined symbol. It can never
6a631e86 6703 be resolved. */
ffcb4889 6704 continue;
fe33d2fa 6705
906e58ca
NC		 6706 if (ELF_ST_TYPE (sym->st_info) != STT_SECTION)
6707 sym_value = sym->st_value;
6708 destination = (sym_value + irela->r_addend
6709 + sym_sec->output_offset
6710 + sym_sec->output_section->vma);
34e77a92 6711 st_type = ELF_ST_TYPE (sym->st_info);
39d911fc
TP		 6712 branch_type =
6713 ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
7413f23f
DJ		 6714 sym_name
6715 = bfd_elf_string_from_elf_section (input_bfd,
6716 symtab_hdr->sh_link,
6717 sym->st_name);
906e58ca
NC		 6718 }
6719 else
6720 {
6721 /* It's an external symbol. */
906e58ca
NC		 6722 while (hash->root.root.type == bfd_link_hash_indirect
6723 || hash->root.root.type == bfd_link_hash_warning)
6724 hash = ((struct elf32_arm_link_hash_entry *)
6725 hash->root.root.u.i.link);
6726
6727 if (hash->root.root.type == bfd_link_hash_defined
6728 || hash->root.root.type == bfd_link_hash_defweak)
6729 {
6730 sym_sec = hash->root.root.u.def.section;
6731 sym_value = hash->root.root.u.def.value;
022f8312
CL		 6732
6733 struct elf32_arm_link_hash_table *globals =
6734 elf32_arm_hash_table (info);
6735
6736 /* For a destination in a shared library,
6737 use the PLT stub as target address to
6738 decide whether a branch stub is
6739 needed. */
4dfe6ac6 6740 if (globals != NULL
362d30a1 6741 && globals->root.splt != NULL
4dfe6ac6 6742 && hash != NULL
022f8312
CL		 6743 && hash->root.plt.offset != (bfd_vma) -1)
6744 {
362d30a1 6745 sym_sec = globals->root.splt;
022f8312
CL		 6746 sym_value = hash->root.plt.offset;
6747 if (sym_sec->output_section != NULL)
6748 destination = (sym_value
6749 + sym_sec->output_offset
6750 + sym_sec->output_section->vma);
6751 }
6752 else if (sym_sec->output_section != NULL)
906e58ca
NC		 6753 destination = (sym_value + irela->r_addend
6754 + sym_sec->output_offset
6755 + sym_sec->output_section->vma);
6756 }
69c5861e
CL		 6757 else if ((hash->root.root.type == bfd_link_hash_undefined)
6758 || (hash->root.root.type == bfd_link_hash_undefweak))
6759 {
6760 /* For a shared library, use the PLT stub as
6761 target address to decide whether a long
6762 branch stub is needed.
6763 For absolute code, they cannot be handled. */
6764 struct elf32_arm_link_hash_table *globals =
6765 elf32_arm_hash_table (info);
6766
4dfe6ac6 6767 if (globals != NULL
362d30a1 6768 && globals->root.splt != NULL
4dfe6ac6 6769 && hash != NULL
69c5861e
CL		 6770 && hash->root.plt.offset != (bfd_vma) -1)
6771 {
362d30a1 6772 sym_sec = globals->root.splt;
69c5861e
CL		 6773 sym_value = hash->root.plt.offset;
6774 if (sym_sec->output_section != NULL)
6775 destination = (sym_value
6776 + sym_sec->output_offset
6777 + sym_sec->output_section->vma);
6778 }
6779 else
6780 continue;
6781 }
906e58ca
NC		 6782 else
6783 {
6784 bfd_set_error (bfd_error_bad_value);
6785 goto error_ret_free_internal;
6786 }
34e77a92 6787 st_type = hash->root.type;
39d911fc
TP		 6788 branch_type =
6789 ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
7413f23f 6790 sym_name = hash->root.root.root.string;
906e58ca
NC		 6791 }
6792
48229727 6793 do
7413f23f 6794 {
b715f643 6795 bfd_boolean new_stub;
0955507f 6796 struct elf32_arm_stub_hash_entry *stub_entry;
b715f643 6797
48229727
JB		 6798 /* Determine what (if any) linker stub is needed. */
6799 stub_type = arm_type_of_stub (info, section, irela,
34e77a92
RS		 6800 st_type, &branch_type,
6801 hash, destination, sym_sec,
48229727
JB		 6802 input_bfd, sym_name);
6803 if (stub_type == arm_stub_none)
6804 break;
6805
48229727
JB		 6806 /* We've either created a stub for this reloc already,
6807 or we are about to. */
0955507f 6808 stub_entry =
b715f643
TP		 6809 elf32_arm_create_stub (htab, stub_type, section, irela,
6810 sym_sec, hash,
6811 (char *) sym_name, sym_value,
6812 branch_type, &new_stub);
7413f23f 6813
0955507f 6814 created_stub = stub_entry != NULL;
b715f643
TP		 6815 if (!created_stub)
6816 goto error_ret_free_internal;
6817 else if (!new_stub)
6818 break;
99059e56 6819 else
b715f643 6820 stub_changed = TRUE;
99059e56
RM		 6821 }
6822 while (0);
6823
6824 /* Look for relocations which might trigger Cortex-A8
6825 erratum. */
6826 if (htab->fix_cortex_a8
6827 && (r_type == (unsigned int) R_ARM_THM_JUMP24
6828 || r_type == (unsigned int) R_ARM_THM_JUMP19
6829 || r_type == (unsigned int) R_ARM_THM_CALL
6830 || r_type == (unsigned int) R_ARM_THM_XPC22))
6831 {
6832 bfd_vma from = section->output_section->vma
6833 + section->output_offset
6834 + irela->r_offset;
6835
6836 if ((from & 0xfff) == 0xffe)
6837 {
6838 /* Found a candidate. Note we haven't checked the
6839 destination is within 4K here: if we do so (and
6840 don't create an entry in a8_relocs) we can't tell
6841 that a branch should have been relocated when
6842 scanning later. */
6843 if (num_a8_relocs == a8_reloc_table_size)
6844 {
6845 a8_reloc_table_size *= 2;
6846 a8_relocs = (struct a8_erratum_reloc *)
6847 bfd_realloc (a8_relocs,
6848 sizeof (struct a8_erratum_reloc)
6849 * a8_reloc_table_size);
6850 }
6851
6852 a8_relocs[num_a8_relocs].from = from;
6853 a8_relocs[num_a8_relocs].destination = destination;
6854 a8_relocs[num_a8_relocs].r_type = r_type;
6855 a8_relocs[num_a8_relocs].branch_type = branch_type;
6856 a8_relocs[num_a8_relocs].sym_name = sym_name;
6857 a8_relocs[num_a8_relocs].non_a8_stub = created_stub;
6858 a8_relocs[num_a8_relocs].hash = hash;
6859
6860 num_a8_relocs++;
6861 }
6862 }
906e58ca
NC		 6863 }
6864
99059e56
RM		 6865 /* We're done with the internal relocs, free them. */
6866 if (elf_section_data (section)->relocs == NULL)
6867 free (internal_relocs);
6868 }
48229727 6869
99059e56 6870 if (htab->fix_cortex_a8)
48229727 6871 {
99059e56
RM		 6872 /* Sort relocs which might apply to Cortex-A8 erratum. */
6873 qsort (a8_relocs, num_a8_relocs,
eb7c4339 6874 sizeof (struct a8_erratum_reloc),
99059e56 6875 &a8_reloc_compare);
48229727 6876
99059e56
RM		 6877 /* Scan for branches which might trigger Cortex-A8 erratum. */
6878 if (cortex_a8_erratum_scan (input_bfd, info, &a8_fixes,
48229727 6879 &num_a8_fixes, &a8_fix_table_size,
eb7c4339
NS		 6880 a8_relocs, num_a8_relocs,
6881 prev_num_a8_fixes, &stub_changed)
6882 != 0)
48229727 6883 goto error_ret_free_local;
5e681ec4 6884 }
7f991970
AM		 6885
6886 if (local_syms != NULL
6887 && symtab_hdr->contents != (unsigned char *) local_syms)
6888 {
6889 if (!info->keep_memory)
6890 free (local_syms);
6891 else
6892 symtab_hdr->contents = (unsigned char *) local_syms;
6893 }
5e681ec4
PB		 6894 }
6895
0955507f
TP		 6896 if (first_veneer_scan
6897 && !set_cmse_veneer_addr_from_implib (info, htab,
6898 &cmse_stub_created))
6899 ret = FALSE;
6900
eb7c4339 6901 if (prev_num_a8_fixes != num_a8_fixes)
99059e56 6902 stub_changed = TRUE;
48229727 6903
906e58ca
NC		 6904 if (!stub_changed)
6905 break;
5e681ec4 6906
906e58ca
NC		 6907 /* OK, we've added some stubs. Find out the new size of the
6908 stub sections. */
6909 for (stub_sec = htab->stub_bfd->sections;
6910 stub_sec != NULL;
6911 stub_sec = stub_sec->next)
3e6b1042
DJ		 6912 {
6913 /* Ignore non-stub sections. */
6914 if (!strstr (stub_sec->name, STUB_SUFFIX))
6915 continue;
6916
6917 stub_sec->size = 0;
6918 }
b34b2d70 6919
0955507f
TP		 6920 /* Add new SG veneers after those already in the input import
6921 library. */
6922 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6923 stub_type++)
6924 {
6925 bfd_vma *start_offset_p;
6926 asection **stub_sec_p;
6927
6928 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
6929 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6930 if (start_offset_p == NULL)
6931 continue;
6932
6933 BFD_ASSERT (stub_sec_p != NULL);
6934 if (*stub_sec_p != NULL)
6935 (*stub_sec_p)->size = *start_offset_p;
6936 }
6937
d7c5bd02 6938 /* Compute stub section size, considering padding. */
906e58ca 6939 bfd_hash_traverse (&htab->stub_hash_table, arm_size_one_stub, htab);
d7c5bd02
TP		 6940 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6941 stub_type++)
6942 {
6943 int size, padding;
6944 asection **stub_sec_p;
6945
6946 padding = arm_dedicated_stub_section_padding (stub_type);
6947 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6948 /* Skip if no stub input section or no stub section padding
6949 required. */
6950 if ((stub_sec_p != NULL && *stub_sec_p == NULL) || padding == 0)
6951 continue;
6952 /* Stub section padding required but no dedicated section. */
6953 BFD_ASSERT (stub_sec_p);
6954
6955 size = (*stub_sec_p)->size;
6956 size = (size + padding - 1) & ~(padding - 1);
6957 (*stub_sec_p)->size = size;
6958 }
906e58ca 6959
48229727
JB		 6960 /* Add Cortex-A8 erratum veneers to stub section sizes too. */
6961 if (htab->fix_cortex_a8)
99059e56
RM		 6962 for (i = 0; i < num_a8_fixes; i++)
6963 {
48229727 6964 stub_sec = elf32_arm_create_or_find_stub_sec (NULL,
daa4adae 6965 a8_fixes[i].section, htab, a8_fixes[i].stub_type);
48229727
JB		 6966
6967 if (stub_sec == NULL)
7f991970 6968 return FALSE;
48229727 6969
99059e56
RM		 6970 stub_sec->size
6971 += find_stub_size_and_template (a8_fixes[i].stub_type, NULL,
6972 NULL);
6973 }
48229727
JB		 6974
6975
906e58ca
NC		 6976 /* Ask the linker to do its stuff. */
6977 (*htab->layout_sections_again) ();
4ba2ef8f 6978 first_veneer_scan = FALSE;
ba93b8ac
DJ		 6979 }
6980
48229727
JB		 6981 /* Add stubs for Cortex-A8 erratum fixes now. */
6982 if (htab->fix_cortex_a8)
6983 {
6984 for (i = 0; i < num_a8_fixes; i++)
99059e56
RM		 6985 {
6986 struct elf32_arm_stub_hash_entry *stub_entry;
6987 char *stub_name = a8_fixes[i].stub_name;
6988 asection *section = a8_fixes[i].section;
6989 unsigned int section_id = a8_fixes[i].section->id;
6990 asection *link_sec = htab->stub_group[section_id].link_sec;
6991 asection *stub_sec = htab->stub_group[section_id].stub_sec;
6992 const insn_sequence *template_sequence;
6993 int template_size, size = 0;
6994
6995 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
6996 TRUE, FALSE);
6997 if (stub_entry == NULL)
6998 {
871b3ab2 6999 _bfd_error_handler (_("%pB: cannot create stub entry %s"),
4eca0228 7000 section->owner, stub_name);
99059e56
RM		 7001 return FALSE;
7002 }
7003
7004 stub_entry->stub_sec = stub_sec;
0955507f 7005 stub_entry->stub_offset = (bfd_vma) -1;
99059e56
RM		 7006 stub_entry->id_sec = link_sec;
7007 stub_entry->stub_type = a8_fixes[i].stub_type;
8d9d9490 7008 stub_entry->source_value = a8_fixes[i].offset;
99059e56 7009 stub_entry->target_section = a8_fixes[i].section;
8d9d9490 7010 stub_entry->target_value = a8_fixes[i].target_offset;
99059e56 7011 stub_entry->orig_insn = a8_fixes[i].orig_insn;
35fc36a8 7012 stub_entry->branch_type = a8_fixes[i].branch_type;
48229727 7013
99059e56
RM		 7014 size = find_stub_size_and_template (a8_fixes[i].stub_type,
7015 &template_sequence,
7016 &template_size);
48229727 7017
99059e56
RM		 7018 stub_entry->stub_size = size;
7019 stub_entry->stub_template = template_sequence;
7020 stub_entry->stub_template_size = template_size;
7021 }
48229727
JB		 7022
7023 /* Stash the Cortex-A8 erratum fix array for use later in
99059e56 7024 elf32_arm_write_section(). */
48229727
JB		 7025 htab->a8_erratum_fixes = a8_fixes;
7026 htab->num_a8_erratum_fixes = num_a8_fixes;
7027 }
7028 else
7029 {
7030 htab->a8_erratum_fixes = NULL;
7031 htab->num_a8_erratum_fixes = 0;
7032 }
0955507f 7033 return ret;
5e681ec4
PB		 7034}
7035
906e58ca
NC		 7036/* Build all the stubs associated with the current output file. The
7037 stubs are kept in a hash table attached to the main linker hash
7038 table. We also set up the .plt entries for statically linked PIC
7039 functions here. This function is called via arm_elf_finish in the
7040 linker. */
252b5132 7041
906e58ca
NC		 7042bfd_boolean
7043elf32_arm_build_stubs (struct bfd_link_info *info)
252b5132 7044{
906e58ca
NC		 7045 asection *stub_sec;
7046 struct bfd_hash_table *table;
0955507f 7047 enum elf32_arm_stub_type stub_type;
906e58ca 7048 struct elf32_arm_link_hash_table *htab;
252b5132 7049
906e58ca 7050 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 7051 if (htab == NULL)
7052 return FALSE;
252b5132 7053
906e58ca
NC		 7054 for (stub_sec = htab->stub_bfd->sections;
7055 stub_sec != NULL;
7056 stub_sec = stub_sec->next)
252b5132 7057 {
906e58ca
NC		 7058 bfd_size_type size;
7059
8029a119 7060 /* Ignore non-stub sections. */
906e58ca
NC		 7061 if (!strstr (stub_sec->name, STUB_SUFFIX))
7062 continue;
7063
d7c5bd02 7064 /* Allocate memory to hold the linker stubs. Zeroing the stub sections
0955507f
TP		 7065 must at least be done for stub section requiring padding and for SG
7066 veneers to ensure that a non secure code branching to a removed SG
7067 veneer causes an error. */
906e58ca 7068 size = stub_sec->size;
21d799b5 7069 stub_sec->contents = (unsigned char *) bfd_zalloc (htab->stub_bfd, size);
906e58ca
NC		 7070 if (stub_sec->contents == NULL && size != 0)
7071 return FALSE;
0955507f 7072
906e58ca 7073 stub_sec->size = 0;
252b5132
RH		 7074 }
7075
0955507f
TP		 7076 /* Add new SG veneers after those already in the input import library. */
7077 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
7078 {
7079 bfd_vma *start_offset_p;
7080 asection **stub_sec_p;
7081
7082 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
7083 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
7084 if (start_offset_p == NULL)
7085 continue;
7086
7087 BFD_ASSERT (stub_sec_p != NULL);
7088 if (*stub_sec_p != NULL)
7089 (*stub_sec_p)->size = *start_offset_p;
7090 }
7091
906e58ca
NC		 7092 /* Build the stubs as directed by the stub hash table. */
7093 table = &htab->stub_hash_table;
7094 bfd_hash_traverse (table, arm_build_one_stub, info);
eb7c4339
NS		 7095 if (htab->fix_cortex_a8)
7096 {
7097 /* Place the cortex a8 stubs last. */
7098 htab->fix_cortex_a8 = -1;
7099 bfd_hash_traverse (table, arm_build_one_stub, info);
7100 }
252b5132 7101
906e58ca 7102 return TRUE;
252b5132
RH		 7103}
7104
9b485d32
NC		 7105/* Locate the Thumb encoded calling stub for NAME. */
7106
252b5132 7107static struct elf_link_hash_entry *
57e8b36a
NC		 7108find_thumb_glue (struct bfd_link_info *link_info,
7109 const char *name,
f2a9dd69 7110 char **error_message)
252b5132
RH		 7111{
7112 char *tmp_name;
7113 struct elf_link_hash_entry *hash;
7114 struct elf32_arm_link_hash_table *hash_table;
7115
7116 /* We need a pointer to the armelf specific hash table. */
7117 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 7118 if (hash_table == NULL)
7119 return NULL;
252b5132 7120
21d799b5 7121 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 7122 + strlen (THUMB2ARM_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 7123
7124 BFD_ASSERT (tmp_name);
7125
7126 sprintf (tmp_name, THUMB2ARM_GLUE_ENTRY_NAME, name);
7127
7128 hash = elf_link_hash_lookup
b34976b6 7129 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 7130
b1657152 7131 if (hash == NULL
90b6238f
AM		 7132 && asprintf (error_message, _("unable to find %s glue '%s' for '%s'"),
7133 "Thumb", tmp_name, name) == -1)
b1657152 7134 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 7135
7136 free (tmp_name);
7137
7138 return hash;
7139}
7140
9b485d32
NC		 7141/* Locate the ARM encoded calling stub for NAME. */
7142
252b5132 7143static struct elf_link_hash_entry *
57e8b36a
NC		 7144find_arm_glue (struct bfd_link_info *link_info,
7145 const char *name,
f2a9dd69 7146 char **error_message)
252b5132
RH		 7147{
7148 char *tmp_name;
7149 struct elf_link_hash_entry *myh;
7150 struct elf32_arm_link_hash_table *hash_table;
7151
7152 /* We need a pointer to the elfarm specific hash table. */
7153 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 7154 if (hash_table == NULL)
7155 return NULL;
252b5132 7156
21d799b5 7157 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 7158 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 7159 BFD_ASSERT (tmp_name);
7160
7161 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
7162
7163 myh = elf_link_hash_lookup
b34976b6 7164 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 7165
b1657152 7166 if (myh == NULL
90b6238f
AM		 7167 && asprintf (error_message, _("unable to find %s glue '%s' for '%s'"),
7168 "ARM", tmp_name, name) == -1)
b1657152 7169 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 7170
7171 free (tmp_name);
7172
7173 return myh;
7174}
7175
8f6277f5 7176/* ARM->Thumb glue (static images):
252b5132
RH		 7177
7178 .arm
7179 __func_from_arm:
7180 ldr r12, __func_addr
7181 bx r12
7182 __func_addr:
906e58ca 7183 .word func @ behave as if you saw a ARM_32 reloc.
252b5132 7184
26079076
PB		 7185 (v5t static images)
7186 .arm
7187 __func_from_arm:
7188 ldr pc, __func_addr
7189 __func_addr:
906e58ca 7190 .word func @ behave as if you saw a ARM_32 reloc.
26079076 7191
8f6277f5
PB		 7192 (relocatable images)
7193 .arm
7194 __func_from_arm:
7195 ldr r12, __func_offset
7196 add r12, r12, pc
7197 bx r12
7198 __func_offset:
8029a119 7199 .word func - . */
8f6277f5
PB		 7200
7201#define ARM2THUMB_STATIC_GLUE_SIZE 12
252b5132
RH		 7202static const insn32 a2t1_ldr_insn = 0xe59fc000;
7203static const insn32 a2t2_bx_r12_insn = 0xe12fff1c;
7204static const insn32 a2t3_func_addr_insn = 0x00000001;
7205
26079076
PB		 7206#define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
7207static const insn32 a2t1v5_ldr_insn = 0xe51ff004;
7208static const insn32 a2t2v5_func_addr_insn = 0x00000001;
7209
8f6277f5
PB		 7210#define ARM2THUMB_PIC_GLUE_SIZE 16
7211static const insn32 a2t1p_ldr_insn = 0xe59fc004;
7212static const insn32 a2t2p_add_pc_insn = 0xe08cc00f;
7213static const insn32 a2t3p_bx_r12_insn = 0xe12fff1c;
7214
07d6d2b8 7215/* Thumb->ARM: Thumb->(non-interworking aware) ARM
252b5132 7216
07d6d2b8
AM		 7217 .thumb .thumb
7218 .align 2 .align 2
7219 __func_from_thumb: __func_from_thumb:
7220 bx pc push {r6, lr}
7221 nop ldr r6, __func_addr
7222 .arm mov lr, pc
7223 b func bx r6
99059e56
RM		 7224 .arm
7225 ;; back_to_thumb
7226 ldmia r13! {r6, lr}
7227 bx lr
7228 __func_addr:
07d6d2b8 7229 .word func */
252b5132
RH		 7230
7231#define THUMB2ARM_GLUE_SIZE 8
7232static const insn16 t2a1_bx_pc_insn = 0x4778;
7233static const insn16 t2a2_noop_insn = 0x46c0;
7234static const insn32 t2a3_b_insn = 0xea000000;
7235
c7b8f16e 7236#define VFP11_ERRATUM_VENEER_SIZE 8
a504d23a
LA		 7237#define STM32L4XX_ERRATUM_LDM_VENEER_SIZE 16
7238#define STM32L4XX_ERRATUM_VLDM_VENEER_SIZE 24
c7b8f16e 7239
845b51d6
PB		 7240#define ARM_BX_VENEER_SIZE 12
7241static const insn32 armbx1_tst_insn = 0xe3100001;
7242static const insn32 armbx2_moveq_insn = 0x01a0f000;
7243static const insn32 armbx3_bx_insn = 0xe12fff10;
7244
7e392df6 7245#ifndef ELFARM_NABI_C_INCLUDED
8029a119
NC		 7246static void
7247arm_allocate_glue_section_space (bfd * abfd, bfd_size_type size, const char * name)
252b5132
RH		 7248{
7249 asection * s;
8029a119 7250 bfd_byte * contents;
252b5132 7251
8029a119 7252 if (size == 0)
3e6b1042
DJ		 7253 {
7254 /* Do not include empty glue sections in the output. */
7255 if (abfd != NULL)
7256 {
3d4d4302 7257 s = bfd_get_linker_section (abfd, name);
3e6b1042
DJ		 7258 if (s != NULL)
7259 s->flags |= SEC_EXCLUDE;
7260 }
7261 return;
7262 }
252b5132 7263
8029a119 7264 BFD_ASSERT (abfd != NULL);
252b5132 7265
3d4d4302 7266 s = bfd_get_linker_section (abfd, name);
8029a119 7267 BFD_ASSERT (s != NULL);
252b5132 7268
b0f4fbf8 7269 contents = (bfd_byte *) bfd_zalloc (abfd, size);
252b5132 7270
8029a119
NC		 7271 BFD_ASSERT (s->size == size);
7272 s->contents = contents;
7273}
906e58ca 7274
8029a119
NC		 7275bfd_boolean
7276bfd_elf32_arm_allocate_interworking_sections (struct bfd_link_info * info)
7277{
7278 struct elf32_arm_link_hash_table * globals;
906e58ca 7279
8029a119
NC		 7280 globals = elf32_arm_hash_table (info);
7281 BFD_ASSERT (globals != NULL);
906e58ca 7282
8029a119
NC		 7283 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7284 globals->arm_glue_size,
7285 ARM2THUMB_GLUE_SECTION_NAME);
906e58ca 7286
8029a119
NC		 7287 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7288 globals->thumb_glue_size,
7289 THUMB2ARM_GLUE_SECTION_NAME);
252b5132 7290
8029a119
NC		 7291 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7292 globals->vfp11_erratum_glue_size,
7293 VFP11_ERRATUM_VENEER_SECTION_NAME);
845b51d6 7294
a504d23a
LA		 7295 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7296 globals->stm32l4xx_erratum_glue_size,
7297 STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
7298
8029a119
NC		 7299 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7300 globals->bx_glue_size,
845b51d6
PB		 7301 ARM_BX_GLUE_SECTION_NAME);
7302
b34976b6 7303 return TRUE;
252b5132
RH		 7304}
7305
a4fd1a8e 7306/* Allocate space and symbols for calling a Thumb function from Arm mode.
906e58ca
NC		 7307 returns the symbol identifying the stub. */
7308
a4fd1a8e 7309static struct elf_link_hash_entry *
57e8b36a
NC		 7310record_arm_to_thumb_glue (struct bfd_link_info * link_info,
7311 struct elf_link_hash_entry * h)
252b5132
RH		 7312{
7313 const char * name = h->root.root.string;
63b0f745 7314 asection * s;
252b5132
RH		 7315 char * tmp_name;
7316 struct elf_link_hash_entry * myh;
14a793b2 7317 struct bfd_link_hash_entry * bh;
252b5132 7318 struct elf32_arm_link_hash_table * globals;
dc810e39 7319 bfd_vma val;
2f475487 7320 bfd_size_type size;
252b5132
RH		 7321
7322 globals = elf32_arm_hash_table (link_info);
252b5132
RH		 7323 BFD_ASSERT (globals != NULL);
7324 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7325
3d4d4302 7326 s = bfd_get_linker_section
252b5132
RH		 7327 (globals->bfd_of_glue_owner, ARM2THUMB_GLUE_SECTION_NAME);
7328
252b5132
RH		 7329 BFD_ASSERT (s != NULL);
7330
21d799b5 7331 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 7332 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 7333 BFD_ASSERT (tmp_name);
7334
7335 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
7336
7337 myh = elf_link_hash_lookup
b34976b6 7338 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132
RH		 7339
7340 if (myh != NULL)
7341 {
9b485d32 7342 /* We've already seen this guy. */
252b5132 7343 free (tmp_name);
a4fd1a8e 7344 return myh;
252b5132
RH		 7345 }
7346
57e8b36a
NC		 7347 /* The only trick here is using hash_table->arm_glue_size as the value.
7348 Even though the section isn't allocated yet, this is where we will be
3dccd7b7
DJ		 7349 putting it. The +1 on the value marks that the stub has not been
7350 output yet - not that it is a Thumb function. */
14a793b2 7351 bh = NULL;
dc810e39
AM		 7352 val = globals->arm_glue_size + 1;
7353 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
7354 tmp_name, BSF_GLOBAL, s, val,
b34976b6 7355 NULL, TRUE, FALSE, &bh);
252b5132 7356
b7693d02
DJ		 7357 myh = (struct elf_link_hash_entry *) bh;
7358 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7359 myh->forced_local = 1;
7360
252b5132
RH		 7361 free (tmp_name);
7362
0e1862bb
L		 7363 if (bfd_link_pic (link_info)
7364 || globals->root.is_relocatable_executable
27e55c4d 7365 || globals->pic_veneer)
2f475487 7366 size = ARM2THUMB_PIC_GLUE_SIZE;
26079076
PB		 7367 else if (globals->use_blx)
7368 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
8f6277f5 7369 else
2f475487
AM		 7370 size = ARM2THUMB_STATIC_GLUE_SIZE;
7371
7372 s->size += size;
7373 globals->arm_glue_size += size;
252b5132 7374
a4fd1a8e 7375 return myh;
252b5132
RH		 7376}
7377
845b51d6
PB		 7378/* Allocate space for ARMv4 BX veneers. */
7379
7380static void
7381record_arm_bx_glue (struct bfd_link_info * link_info, int reg)
7382{
7383 asection * s;
7384 struct elf32_arm_link_hash_table *globals;
7385 char *tmp_name;
7386 struct elf_link_hash_entry *myh;
7387 struct bfd_link_hash_entry *bh;
7388 bfd_vma val;
7389
7390 /* BX PC does not need a veneer. */
7391 if (reg == 15)
7392 return;
7393
7394 globals = elf32_arm_hash_table (link_info);
845b51d6
PB		 7395 BFD_ASSERT (globals != NULL);
7396 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7397
7398 /* Check if this veneer has already been allocated. */
7399 if (globals->bx_glue_offset[reg])
7400 return;
7401
3d4d4302 7402 s = bfd_get_linker_section
845b51d6
PB		 7403 (globals->bfd_of_glue_owner, ARM_BX_GLUE_SECTION_NAME);
7404
7405 BFD_ASSERT (s != NULL);
7406
7407 /* Add symbol for veneer. */
21d799b5
NC		 7408 tmp_name = (char *)
7409 bfd_malloc ((bfd_size_type) strlen (ARM_BX_GLUE_ENTRY_NAME) + 1);
845b51d6 7410 BFD_ASSERT (tmp_name);
906e58ca 7411
845b51d6 7412 sprintf (tmp_name, ARM_BX_GLUE_ENTRY_NAME, reg);
906e58ca 7413
845b51d6
PB		 7414 myh = elf_link_hash_lookup
7415 (&(globals)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7416
845b51d6 7417 BFD_ASSERT (myh == NULL);
906e58ca 7418
845b51d6
PB		 7419 bh = NULL;
7420 val = globals->bx_glue_size;
7421 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
99059e56
RM		 7422 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7423 NULL, TRUE, FALSE, &bh);
845b51d6
PB		 7424
7425 myh = (struct elf_link_hash_entry *) bh;
7426 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7427 myh->forced_local = 1;
7428
7429 s->size += ARM_BX_VENEER_SIZE;
7430 globals->bx_glue_offset[reg] = globals->bx_glue_size | 2;
7431 globals->bx_glue_size += ARM_BX_VENEER_SIZE;
7432}
7433
7434
c7b8f16e
JB		 7435/* Add an entry to the code/data map for section SEC. */
7436
7437static void
7438elf32_arm_section_map_add (asection *sec, char type, bfd_vma vma)
7439{
7440 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
7441 unsigned int newidx;
906e58ca 7442
c7b8f16e
JB		 7443 if (sec_data->map == NULL)
7444 {
21d799b5 7445 sec_data->map = (elf32_arm_section_map *)
99059e56 7446 bfd_malloc (sizeof (elf32_arm_section_map));
c7b8f16e
JB		 7447 sec_data->mapcount = 0;
7448 sec_data->mapsize = 1;
7449 }
906e58ca 7450
c7b8f16e 7451 newidx = sec_data->mapcount++;
906e58ca 7452
c7b8f16e
JB		 7453 if (sec_data->mapcount > sec_data->mapsize)
7454 {
7455 sec_data->mapsize *= 2;
21d799b5 7456 sec_data->map = (elf32_arm_section_map *)
99059e56
RM		 7457 bfd_realloc_or_free (sec_data->map, sec_data->mapsize
7458 * sizeof (elf32_arm_section_map));
515ef31d
NC		 7459 }
7460
7461 if (sec_data->map)
7462 {
7463 sec_data->map[newidx].vma = vma;
7464 sec_data->map[newidx].type = type;
c7b8f16e 7465 }
c7b8f16e
JB		 7466}
7467
7468
7469/* Record information about a VFP11 denorm-erratum veneer. Only ARM-mode
7470 veneers are handled for now. */
7471
7472static bfd_vma
7473record_vfp11_erratum_veneer (struct bfd_link_info *link_info,
99059e56
RM		 7474 elf32_vfp11_erratum_list *branch,
7475 bfd *branch_bfd,
7476 asection *branch_sec,
7477 unsigned int offset)
c7b8f16e
JB		 7478{
7479 asection *s;
7480 struct elf32_arm_link_hash_table *hash_table;
7481 char *tmp_name;
7482 struct elf_link_hash_entry *myh;
7483 struct bfd_link_hash_entry *bh;
7484 bfd_vma val;
7485 struct _arm_elf_section_data *sec_data;
c7b8f16e 7486 elf32_vfp11_erratum_list *newerr;
906e58ca 7487
c7b8f16e 7488 hash_table = elf32_arm_hash_table (link_info);
c7b8f16e
JB		 7489 BFD_ASSERT (hash_table != NULL);
7490 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
906e58ca 7491
3d4d4302 7492 s = bfd_get_linker_section
c7b8f16e 7493 (hash_table->bfd_of_glue_owner, VFP11_ERRATUM_VENEER_SECTION_NAME);
906e58ca 7494
c7b8f16e 7495 sec_data = elf32_arm_section_data (s);
906e58ca 7496
c7b8f16e 7497 BFD_ASSERT (s != NULL);
906e58ca 7498
21d799b5 7499 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 7500 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
c7b8f16e 7501 BFD_ASSERT (tmp_name);
906e58ca 7502
c7b8f16e
JB		 7503 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
7504 hash_table->num_vfp11_fixes);
906e58ca 7505
c7b8f16e
JB		 7506 myh = elf_link_hash_lookup
7507 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7508
c7b8f16e 7509 BFD_ASSERT (myh == NULL);
906e58ca 7510
c7b8f16e
JB		 7511 bh = NULL;
7512 val = hash_table->vfp11_erratum_glue_size;
7513 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
99059e56
RM		 7514 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7515 NULL, TRUE, FALSE, &bh);
c7b8f16e
JB		 7516
7517 myh = (struct elf_link_hash_entry *) bh;
7518 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7519 myh->forced_local = 1;
7520
7521 /* Link veneer back to calling location. */
c7e2358a 7522 sec_data->erratumcount += 1;
21d799b5
NC		 7523 newerr = (elf32_vfp11_erratum_list *)
7524 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
906e58ca 7525
c7b8f16e
JB		 7526 newerr->type = VFP11_ERRATUM_ARM_VENEER;
7527 newerr->vma = -1;
7528 newerr->u.v.branch = branch;
7529 newerr->u.v.id = hash_table->num_vfp11_fixes;
7530 branch->u.b.veneer = newerr;
7531
7532 newerr->next = sec_data->erratumlist;
7533 sec_data->erratumlist = newerr;
7534
7535 /* A symbol for the return from the veneer. */
7536 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
7537 hash_table->num_vfp11_fixes);
7538
7539 myh = elf_link_hash_lookup
7540 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7541
c7b8f16e
JB		 7542 if (myh != NULL)
7543 abort ();
7544
7545 bh = NULL;
7546 val = offset + 4;
7547 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7548 branch_sec, val, NULL, TRUE, FALSE, &bh);
906e58ca 7549
c7b8f16e
JB		 7550 myh = (struct elf_link_hash_entry *) bh;
7551 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7552 myh->forced_local = 1;
7553
7554 free (tmp_name);
906e58ca 7555
c7b8f16e
JB		 7556 /* Generate a mapping symbol for the veneer section, and explicitly add an
7557 entry for that symbol to the code/data map for the section. */
7558 if (hash_table->vfp11_erratum_glue_size == 0)
7559 {
7560 bh = NULL;
7561 /* FIXME: Creates an ARM symbol. Thumb mode will need attention if it
99059e56 7562 ever requires this erratum fix. */
c7b8f16e
JB		 7563 _bfd_generic_link_add_one_symbol (link_info,
7564 hash_table->bfd_of_glue_owner, "$a",
7565 BSF_LOCAL, s, 0, NULL,
99059e56 7566 TRUE, FALSE, &bh);
c7b8f16e
JB		 7567
7568 myh = (struct elf_link_hash_entry *) bh;
7569 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7570 myh->forced_local = 1;
906e58ca 7571
c7b8f16e 7572 /* The elf32_arm_init_maps function only cares about symbols from input
99059e56
RM		 7573 BFDs. We must make a note of this generated mapping symbol
7574 ourselves so that code byteswapping works properly in
7575 elf32_arm_write_section. */
c7b8f16e
JB		 7576 elf32_arm_section_map_add (s, 'a', 0);
7577 }
906e58ca 7578
c7b8f16e
JB		 7579 s->size += VFP11_ERRATUM_VENEER_SIZE;
7580 hash_table->vfp11_erratum_glue_size += VFP11_ERRATUM_VENEER_SIZE;
7581 hash_table->num_vfp11_fixes++;
906e58ca 7582
c7b8f16e
JB		 7583 /* The offset of the veneer. */
7584 return val;
7585}
7586
a504d23a
LA		 7587/* Record information about a STM32L4XX STM erratum veneer. Only THUMB-mode
7588 veneers need to be handled because used only in Cortex-M. */
7589
7590static bfd_vma
7591record_stm32l4xx_erratum_veneer (struct bfd_link_info *link_info,
7592 elf32_stm32l4xx_erratum_list *branch,
7593 bfd *branch_bfd,
7594 asection *branch_sec,
7595 unsigned int offset,
7596 bfd_size_type veneer_size)
7597{
7598 asection *s;
7599 struct elf32_arm_link_hash_table *hash_table;
7600 char *tmp_name;
7601 struct elf_link_hash_entry *myh;
7602 struct bfd_link_hash_entry *bh;
7603 bfd_vma val;
7604 struct _arm_elf_section_data *sec_data;
7605 elf32_stm32l4xx_erratum_list *newerr;
7606
7607 hash_table = elf32_arm_hash_table (link_info);
7608 BFD_ASSERT (hash_table != NULL);
7609 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
7610
7611 s = bfd_get_linker_section
7612 (hash_table->bfd_of_glue_owner, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
7613
7614 BFD_ASSERT (s != NULL);
7615
7616 sec_data = elf32_arm_section_data (s);
7617
7618 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
7619 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
a504d23a
LA		 7620 BFD_ASSERT (tmp_name);
7621
7622 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
7623 hash_table->num_stm32l4xx_fixes);
7624
7625 myh = elf_link_hash_lookup
7626 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7627
7628 BFD_ASSERT (myh == NULL);
7629
7630 bh = NULL;
7631 val = hash_table->stm32l4xx_erratum_glue_size;
7632 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
7633 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7634 NULL, TRUE, FALSE, &bh);
7635
7636 myh = (struct elf_link_hash_entry *) bh;
7637 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7638 myh->forced_local = 1;
7639
7640 /* Link veneer back to calling location. */
7641 sec_data->stm32l4xx_erratumcount += 1;
7642 newerr = (elf32_stm32l4xx_erratum_list *)
7643 bfd_zmalloc (sizeof (elf32_stm32l4xx_erratum_list));
7644
7645 newerr->type = STM32L4XX_ERRATUM_VENEER;
7646 newerr->vma = -1;
7647 newerr->u.v.branch = branch;
7648 newerr->u.v.id = hash_table->num_stm32l4xx_fixes;
7649 branch->u.b.veneer = newerr;
7650
7651 newerr->next = sec_data->stm32l4xx_erratumlist;
7652 sec_data->stm32l4xx_erratumlist = newerr;
7653
7654 /* A symbol for the return from the veneer. */
7655 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
7656 hash_table->num_stm32l4xx_fixes);
7657
7658 myh = elf_link_hash_lookup
7659 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7660
7661 if (myh != NULL)
7662 abort ();
7663
7664 bh = NULL;
7665 val = offset + 4;
7666 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7667 branch_sec, val, NULL, TRUE, FALSE, &bh);
7668
7669 myh = (struct elf_link_hash_entry *) bh;
7670 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7671 myh->forced_local = 1;
7672
7673 free (tmp_name);
7674
7675 /* Generate a mapping symbol for the veneer section, and explicitly add an
7676 entry for that symbol to the code/data map for the section. */
7677 if (hash_table->stm32l4xx_erratum_glue_size == 0)
7678 {
7679 bh = NULL;
7680 /* Creates a THUMB symbol since there is no other choice. */
7681 _bfd_generic_link_add_one_symbol (link_info,
7682 hash_table->bfd_of_glue_owner, "$t",
7683 BSF_LOCAL, s, 0, NULL,
7684 TRUE, FALSE, &bh);
7685
7686 myh = (struct elf_link_hash_entry *) bh;
7687 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7688 myh->forced_local = 1;
7689
7690 /* The elf32_arm_init_maps function only cares about symbols from input
7691 BFDs. We must make a note of this generated mapping symbol
7692 ourselves so that code byteswapping works properly in
7693 elf32_arm_write_section. */
7694 elf32_arm_section_map_add (s, 't', 0);
7695 }
7696
7697 s->size += veneer_size;
7698 hash_table->stm32l4xx_erratum_glue_size += veneer_size;
7699 hash_table->num_stm32l4xx_fixes++;
7700
7701 /* The offset of the veneer. */
7702 return val;
7703}
7704
8029a119 7705#define ARM_GLUE_SECTION_FLAGS \
3e6b1042
DJ		 7706 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_CODE \
7707 | SEC_READONLY | SEC_LINKER_CREATED)
8029a119
NC		 7708
7709/* Create a fake section for use by the ARM backend of the linker. */
7710
7711static bfd_boolean
7712arm_make_glue_section (bfd * abfd, const char * name)
7713{
7714 asection * sec;
7715
3d4d4302 7716 sec = bfd_get_linker_section (abfd, name);
8029a119
NC		 7717 if (sec != NULL)
7718 /* Already made. */
7719 return TRUE;
7720
3d4d4302 7721 sec = bfd_make_section_anyway_with_flags (abfd, name, ARM_GLUE_SECTION_FLAGS);
8029a119
NC		 7722
7723 if (sec == NULL
fd361982 7724 || !bfd_set_section_alignment (sec, 2))
8029a119
NC		 7725 return FALSE;
7726
7727 /* Set the gc mark to prevent the section from being removed by garbage
7728 collection, despite the fact that no relocs refer to this section. */
7729 sec->gc_mark = 1;
7730
7731 return TRUE;
7732}
7733
1db37fe6
YG		 7734/* Set size of .plt entries. This function is called from the
7735 linker scripts in ld/emultempl/{armelf}.em. */
7736
7737void
7738bfd_elf32_arm_use_long_plt (void)
7739{
7740 elf32_arm_use_long_plt_entry = TRUE;
7741}
7742
8afb0e02
NC		 7743/* Add the glue sections to ABFD. This function is called from the
7744 linker scripts in ld/emultempl/{armelf}.em. */
9b485d32 7745
b34976b6 7746bfd_boolean
57e8b36a
NC		 7747bfd_elf32_arm_add_glue_sections_to_bfd (bfd *abfd,
7748 struct bfd_link_info *info)
252b5132 7749{
a504d23a
LA		 7750 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
7751 bfd_boolean dostm32l4xx = globals
7752 && globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE;
7753 bfd_boolean addglue;
7754
8afb0e02
NC		 7755 /* If we are only performing a partial
7756 link do not bother adding the glue. */
0e1862bb 7757 if (bfd_link_relocatable (info))
b34976b6 7758 return TRUE;
252b5132 7759
a504d23a 7760 addglue = arm_make_glue_section (abfd, ARM2THUMB_GLUE_SECTION_NAME)
8029a119
NC		 7761 && arm_make_glue_section (abfd, THUMB2ARM_GLUE_SECTION_NAME)
7762 && arm_make_glue_section (abfd, VFP11_ERRATUM_VENEER_SECTION_NAME)
7763 && arm_make_glue_section (abfd, ARM_BX_GLUE_SECTION_NAME);
a504d23a
LA		 7764
7765 if (!dostm32l4xx)
7766 return addglue;
7767
7768 return addglue
7769 && arm_make_glue_section (abfd, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
8afb0e02
NC		 7770}
7771
daa4adae
TP		 7772/* Mark output sections of veneers needing a dedicated one with SEC_KEEP. This
7773 ensures they are not marked for deletion by
7774 strip_excluded_output_sections () when veneers are going to be created
7775 later. Not doing so would trigger assert on empty section size in
7776 lang_size_sections_1 (). */
7777
7778void
7779bfd_elf32_arm_keep_private_stub_output_sections (struct bfd_link_info *info)
7780{
7781 enum elf32_arm_stub_type stub_type;
7782
7783 /* If we are only performing a partial
7784 link do not bother adding the glue. */
7785 if (bfd_link_relocatable (info))
7786 return;
7787
7788 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
7789 {
7790 asection *out_sec;
7791 const char *out_sec_name;
7792
7793 if (!arm_dedicated_stub_output_section_required (stub_type))
7794 continue;
7795
7796 out_sec_name = arm_dedicated_stub_output_section_name (stub_type);
7797 out_sec = bfd_get_section_by_name (info->output_bfd, out_sec_name);
7798 if (out_sec != NULL)
7799 out_sec->flags |= SEC_KEEP;
7800 }
7801}
7802
8afb0e02
NC		 7803/* Select a BFD to be used to hold the sections used by the glue code.
7804 This function is called from the linker scripts in ld/emultempl/
8029a119 7805 {armelf/pe}.em. */
8afb0e02 7806
b34976b6 7807bfd_boolean
57e8b36a 7808bfd_elf32_arm_get_bfd_for_interworking (bfd *abfd, struct bfd_link_info *info)
8afb0e02
NC		 7809{
7810 struct elf32_arm_link_hash_table *globals;
7811
7812 /* If we are only performing a partial link
7813 do not bother getting a bfd to hold the glue. */
0e1862bb 7814 if (bfd_link_relocatable (info))
b34976b6 7815 return TRUE;
8afb0e02 7816
b7693d02
DJ		 7817 /* Make sure we don't attach the glue sections to a dynamic object. */
7818 BFD_ASSERT (!(abfd->flags & DYNAMIC));
7819
8afb0e02 7820 globals = elf32_arm_hash_table (info);
8afb0e02
NC		 7821 BFD_ASSERT (globals != NULL);
7822
7823 if (globals->bfd_of_glue_owner != NULL)
b34976b6 7824 return TRUE;
8afb0e02 7825
252b5132
RH		 7826 /* Save the bfd for later use. */
7827 globals->bfd_of_glue_owner = abfd;
cedb70c5 7828
b34976b6 7829 return TRUE;
252b5132
RH		 7830}
7831
906e58ca
NC		 7832static void
7833check_use_blx (struct elf32_arm_link_hash_table *globals)
39b41c9c 7834{
2de70689
MGD		 7835 int cpu_arch;
7836
b38cadfb 7837 cpu_arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
2de70689
MGD		 7838 Tag_CPU_arch);
7839
7840 if (globals->fix_arm1176)
7841 {
7842 if (cpu_arch == TAG_CPU_ARCH_V6T2 || cpu_arch > TAG_CPU_ARCH_V6K)
7843 globals->use_blx = 1;
7844 }
7845 else
7846 {
7847 if (cpu_arch > TAG_CPU_ARCH_V4T)
7848 globals->use_blx = 1;
7849 }
39b41c9c
PB		 7850}
7851
b34976b6 7852bfd_boolean
57e8b36a 7853bfd_elf32_arm_process_before_allocation (bfd *abfd,
d504ffc8 7854 struct bfd_link_info *link_info)
252b5132
RH		 7855{
7856 Elf_Internal_Shdr *symtab_hdr;
6cdc0ccc 7857 Elf_Internal_Rela *internal_relocs = NULL;
252b5132
RH		 7858 Elf_Internal_Rela *irel, *irelend;
7859 bfd_byte *contents = NULL;
252b5132
RH		 7860
7861 asection *sec;
7862 struct elf32_arm_link_hash_table *globals;
7863
7864 /* If we are only performing a partial link do not bother
7865 to construct any glue. */
0e1862bb 7866 if (bfd_link_relocatable (link_info))
b34976b6 7867 return TRUE;
252b5132 7868
39ce1a6a
NC		 7869 /* Here we have a bfd that is to be included on the link. We have a
7870 hook to do reloc rummaging, before section sizes are nailed down. */
252b5132 7871 globals = elf32_arm_hash_table (link_info);
252b5132 7872 BFD_ASSERT (globals != NULL);
39ce1a6a
NC		 7873
7874 check_use_blx (globals);
252b5132 7875
d504ffc8 7876 if (globals->byteswap_code && !bfd_big_endian (abfd))
e489d0ae 7877 {
90b6238f 7878 _bfd_error_handler (_("%pB: BE8 images only valid in big-endian mode"),
d003868e 7879 abfd);
e489d0ae
PB		 7880 return FALSE;
7881 }
f21f3fe0 7882
39ce1a6a
NC		 7883 /* PR 5398: If we have not decided to include any loadable sections in
7884 the output then we will not have a glue owner bfd. This is OK, it
7885 just means that there is nothing else for us to do here. */
7886 if (globals->bfd_of_glue_owner == NULL)
7887 return TRUE;
7888
252b5132
RH		 7889 /* Rummage around all the relocs and map the glue vectors. */
7890 sec = abfd->sections;
7891
7892 if (sec == NULL)
b34976b6 7893 return TRUE;
252b5132
RH		 7894
7895 for (; sec != NULL; sec = sec->next)
7896 {
7897 if (sec->reloc_count == 0)
7898 continue;
7899
2f475487
AM		 7900 if ((sec->flags & SEC_EXCLUDE) != 0)
7901 continue;
7902
0ffa91dd 7903 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 7904
9b485d32 7905 /* Load the relocs. */
6cdc0ccc 7906 internal_relocs
906e58ca 7907 = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, FALSE);
252b5132 7908
6cdc0ccc
AM		 7909 if (internal_relocs == NULL)
7910 goto error_return;
252b5132 7911
6cdc0ccc
AM		 7912 irelend = internal_relocs + sec->reloc_count;
7913 for (irel = internal_relocs; irel < irelend; irel++)
252b5132
RH		 7914 {
7915 long r_type;
7916 unsigned long r_index;
252b5132
RH		 7917
7918 struct elf_link_hash_entry *h;
7919
7920 r_type = ELF32_R_TYPE (irel->r_info);
7921 r_index = ELF32_R_SYM (irel->r_info);
7922
9b485d32 7923 /* These are the only relocation types we care about. */
ba96a88f 7924 if ( r_type != R_ARM_PC24
845b51d6 7925 && (r_type != R_ARM_V4BX || globals->fix_v4bx < 2))
252b5132
RH		 7926 continue;
7927
7928 /* Get the section contents if we haven't done so already. */
7929 if (contents == NULL)
7930 {
7931 /* Get cached copy if it exists. */
7932 if (elf_section_data (sec)->this_hdr.contents != NULL)
7933 contents = elf_section_data (sec)->this_hdr.contents;
7934 else
7935 {
7936 /* Go get them off disk. */
57e8b36a 7937 if (! bfd_malloc_and_get_section (abfd, sec, &contents))
252b5132
RH		 7938 goto error_return;
7939 }
7940 }
7941
845b51d6
PB		 7942 if (r_type == R_ARM_V4BX)
7943 {
7944 int reg;
7945
7946 reg = bfd_get_32 (abfd, contents + irel->r_offset) & 0xf;
7947 record_arm_bx_glue (link_info, reg);
7948 continue;
7949 }
7950
a7c10850 7951 /* If the relocation is not against a symbol it cannot concern us. */
252b5132
RH		 7952 h = NULL;
7953
9b485d32 7954 /* We don't care about local symbols. */
252b5132
RH		 7955 if (r_index < symtab_hdr->sh_info)
7956 continue;
7957
9b485d32 7958 /* This is an external symbol. */
252b5132
RH		 7959 r_index -= symtab_hdr->sh_info;
7960 h = (struct elf_link_hash_entry *)
7961 elf_sym_hashes (abfd)[r_index];
7962
7963 /* If the relocation is against a static symbol it must be within
7964 the current section and so cannot be a cross ARM/Thumb relocation. */
7965 if (h == NULL)
7966 continue;
7967
d504ffc8
DJ		 7968 /* If the call will go through a PLT entry then we do not need
7969 glue. */
362d30a1 7970 if (globals->root.splt != NULL && h->plt.offset != (bfd_vma) -1)
b7693d02
DJ		 7971 continue;
7972
252b5132
RH		 7973 switch (r_type)
7974 {
7975 case R_ARM_PC24:
7976 /* This one is a call from arm code. We need to look up
99059e56
RM		 7977 the target of the call. If it is a thumb target, we
7978 insert glue. */
39d911fc
TP		 7979 if (ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
7980 == ST_BRANCH_TO_THUMB)
252b5132
RH		 7981 record_arm_to_thumb_glue (link_info, h);
7982 break;
7983
252b5132 7984 default:
c6596c5e 7985 abort ();
252b5132
RH		 7986 }
7987 }
6cdc0ccc
AM		 7988
7989 if (contents != NULL
7990 && elf_section_data (sec)->this_hdr.contents != contents)
7991 free (contents);
7992 contents = NULL;
7993
7994 if (internal_relocs != NULL
7995 && elf_section_data (sec)->relocs != internal_relocs)
7996 free (internal_relocs);
7997 internal_relocs = NULL;
252b5132
RH		 7998 }
7999
b34976b6 8000 return TRUE;
9a5aca8c 8001
dc1e8a47 8002 error_return:
6cdc0ccc
AM		 8003 if (contents != NULL
8004 && elf_section_data (sec)->this_hdr.contents != contents)
8005 free (contents);
8006 if (internal_relocs != NULL
8007 && elf_section_data (sec)->relocs != internal_relocs)
8008 free (internal_relocs);
9a5aca8c 8009
b34976b6 8010 return FALSE;
252b5132 8011}
7e392df6 8012#endif
252b5132 8013
eb043451 8014
c7b8f16e
JB		 8015/* Initialise maps of ARM/Thumb/data for input BFDs. */
8016
8017void
8018bfd_elf32_arm_init_maps (bfd *abfd)
8019{
8020 Elf_Internal_Sym *isymbuf;
8021 Elf_Internal_Shdr *hdr;
8022 unsigned int i, localsyms;
8023
af1f4419
NC		 8024 /* PR 7093: Make sure that we are dealing with an arm elf binary. */
8025 if (! is_arm_elf (abfd))
8026 return;
8027
c7b8f16e
JB		 8028 if ((abfd->flags & DYNAMIC) != 0)
8029 return;
8030
0ffa91dd 8031 hdr = & elf_symtab_hdr (abfd);
c7b8f16e
JB		 8032 localsyms = hdr->sh_info;
8033
8034 /* Obtain a buffer full of symbols for this BFD. The hdr->sh_info field
8035 should contain the number of local symbols, which should come before any
8036 global symbols. Mapping symbols are always local. */
8037 isymbuf = bfd_elf_get_elf_syms (abfd, hdr, localsyms, 0, NULL, NULL,
8038 NULL);
8039
8040 /* No internal symbols read? Skip this BFD. */
8041 if (isymbuf == NULL)
8042 return;
8043
8044 for (i = 0; i < localsyms; i++)
8045 {
8046 Elf_Internal_Sym *isym = &isymbuf[i];
8047 asection *sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
8048 const char *name;
906e58ca 8049
c7b8f16e 8050 if (sec != NULL
99059e56
RM		 8051 && ELF_ST_BIND (isym->st_info) == STB_LOCAL)
8052 {
8053 name = bfd_elf_string_from_elf_section (abfd,
8054 hdr->sh_link, isym->st_name);
906e58ca 8055
99059e56 8056 if (bfd_is_arm_special_symbol_name (name,
c7b8f16e 8057 BFD_ARM_SPECIAL_SYM_TYPE_MAP))
99059e56
RM		 8058 elf32_arm_section_map_add (sec, name[1], isym->st_value);
8059 }
c7b8f16e
JB		 8060 }
8061}
8062
8063
48229727
JB		 8064/* Auto-select enabling of Cortex-A8 erratum fix if the user didn't explicitly
8065 say what they wanted. */
8066
8067void
8068bfd_elf32_arm_set_cortex_a8_fix (bfd *obfd, struct bfd_link_info *link_info)
8069{
8070 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8071 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
8072
4dfe6ac6
NC		 8073 if (globals == NULL)
8074 return;
8075
48229727
JB		 8076 if (globals->fix_cortex_a8 == -1)
8077 {
8078 /* Turn on Cortex-A8 erratum workaround for ARMv7-A. */
8079 if (out_attr[Tag_CPU_arch].i == TAG_CPU_ARCH_V7
8080 && (out_attr[Tag_CPU_arch_profile].i == 'A'
8081 || out_attr[Tag_CPU_arch_profile].i == 0))
8082 globals->fix_cortex_a8 = 1;
8083 else
8084 globals->fix_cortex_a8 = 0;
8085 }
8086}
8087
8088
c7b8f16e
JB		 8089void
8090bfd_elf32_arm_set_vfp11_fix (bfd *obfd, struct bfd_link_info *link_info)
8091{
8092 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
104d59d1 8093 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
906e58ca 8094
4dfe6ac6
NC		 8095 if (globals == NULL)
8096 return;
c7b8f16e
JB		 8097 /* We assume that ARMv7+ does not need the VFP11 denorm erratum fix. */
8098 if (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V7)
8099 {
8100 switch (globals->vfp11_fix)
99059e56
RM		 8101 {
8102 case BFD_ARM_VFP11_FIX_DEFAULT:
8103 case BFD_ARM_VFP11_FIX_NONE:
8104 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
8105 break;
8106
8107 default:
8108 /* Give a warning, but do as the user requests anyway. */
871b3ab2 8109 _bfd_error_handler (_("%pB: warning: selected VFP11 erratum "
99059e56
RM		 8110 "workaround is not necessary for target architecture"), obfd);
8111 }
c7b8f16e
JB		 8112 }
8113 else if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_DEFAULT)
8114 /* For earlier architectures, we might need the workaround, but do not
8115 enable it by default. If users is running with broken hardware, they
8116 must enable the erratum fix explicitly. */
8117 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
8118}
8119
a504d23a
LA		 8120void
8121bfd_elf32_arm_set_stm32l4xx_fix (bfd *obfd, struct bfd_link_info *link_info)
8122{
8123 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8124 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
8125
8126 if (globals == NULL)
8127 return;
8128
8129 /* We assume only Cortex-M4 may require the fix. */
8130 if (out_attr[Tag_CPU_arch].i != TAG_CPU_ARCH_V7E_M
8131 || out_attr[Tag_CPU_arch_profile].i != 'M')
8132 {
8133 if (globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE)
8134 /* Give a warning, but do as the user requests anyway. */
4eca0228 8135 _bfd_error_handler
871b3ab2 8136 (_("%pB: warning: selected STM32L4XX erratum "
a504d23a
LA		 8137 "workaround is not necessary for target architecture"), obfd);
8138 }
8139}
c7b8f16e 8140
906e58ca
NC		 8141enum bfd_arm_vfp11_pipe
8142{
c7b8f16e
JB		 8143 VFP11_FMAC,
8144 VFP11_LS,
8145 VFP11_DS,
8146 VFP11_BAD
8147};
8148
8149/* Return a VFP register number. This is encoded as RX:X for single-precision
8150 registers, or X:RX for double-precision registers, where RX is the group of
8151 four bits in the instruction encoding and X is the single extension bit.
8152 RX and X fields are specified using their lowest (starting) bit. The return
8153 value is:
8154
8155 0...31: single-precision registers s0...s31
8156 32...63: double-precision registers d0...d31.
906e58ca 8157
c7b8f16e
JB		 8158 Although X should be zero for VFP11 (encoding d0...d15 only), we might
8159 encounter VFP3 instructions, so we allow the full range for DP registers. */
906e58ca 8160
c7b8f16e
JB		 8161static unsigned int
8162bfd_arm_vfp11_regno (unsigned int insn, bfd_boolean is_double, unsigned int rx,
99059e56 8163 unsigned int x)
c7b8f16e
JB		 8164{
8165 if (is_double)
8166 return (((insn >> rx) & 0xf) | (((insn >> x) & 1) << 4)) + 32;
8167 else
8168 return (((insn >> rx) & 0xf) << 1) | ((insn >> x) & 1);
8169}
8170
8171/* Set bits in *WMASK according to a register number REG as encoded by
8172 bfd_arm_vfp11_regno(). Ignore d16-d31. */
8173
8174static void
8175bfd_arm_vfp11_write_mask (unsigned int *wmask, unsigned int reg)
8176{
8177 if (reg < 32)
8178 *wmask |= 1 << reg;
8179 else if (reg < 48)
8180 *wmask |= 3 << ((reg - 32) * 2);
8181}
8182
8183/* Return TRUE if WMASK overwrites anything in REGS. */
8184
8185static bfd_boolean
8186bfd_arm_vfp11_antidependency (unsigned int wmask, int *regs, int numregs)
8187{
8188 int i;
906e58ca 8189
c7b8f16e
JB		 8190 for (i = 0; i < numregs; i++)
8191 {
8192 unsigned int reg = regs[i];
8193
8194 if (reg < 32 && (wmask & (1 << reg)) != 0)
99059e56 8195 return TRUE;
906e58ca 8196
c7b8f16e
JB		 8197 reg -= 32;
8198
8199 if (reg >= 16)
99059e56 8200 continue;
906e58ca 8201
c7b8f16e 8202 if ((wmask & (3 << (reg * 2))) != 0)
99059e56 8203 return TRUE;
c7b8f16e 8204 }
906e58ca 8205
c7b8f16e
JB		 8206 return FALSE;
8207}
8208
8209/* In this function, we're interested in two things: finding input registers
8210 for VFP data-processing instructions, and finding the set of registers which
8211 arbitrary VFP instructions may write to. We use a 32-bit unsigned int to
8212 hold the written set, so FLDM etc. are easy to deal with (we're only
8213 interested in 32 SP registers or 16 dp registers, due to the VFP version
8214 implemented by the chip in question). DP registers are marked by setting
8215 both SP registers in the write mask). */
8216
8217static enum bfd_arm_vfp11_pipe
8218bfd_arm_vfp11_insn_decode (unsigned int insn, unsigned int *destmask, int *regs,
99059e56 8219 int *numregs)
c7b8f16e 8220{
91d6fa6a 8221 enum bfd_arm_vfp11_pipe vpipe = VFP11_BAD;
c7b8f16e
JB		 8222 bfd_boolean is_double = ((insn & 0xf00) == 0xb00) ? 1 : 0;
8223
8224 if ((insn & 0x0f000e10) == 0x0e000a00) /* A data-processing insn. */
8225 {
8226 unsigned int pqrs;
8227 unsigned int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
8228 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
8229
8230 pqrs = ((insn & 0x00800000) >> 20)
99059e56
RM		 8231 | ((insn & 0x00300000) >> 19)
8232 | ((insn & 0x00000040) >> 6);
c7b8f16e
JB		 8233
8234 switch (pqrs)
99059e56
RM		 8235 {
8236 case 0: /* fmac[sd]. */
8237 case 1: /* fnmac[sd]. */
8238 case 2: /* fmsc[sd]. */
8239 case 3: /* fnmsc[sd]. */
8240 vpipe = VFP11_FMAC;
8241 bfd_arm_vfp11_write_mask (destmask, fd);
8242 regs[0] = fd;
8243 regs[1] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
8244 regs[2] = fm;
8245 *numregs = 3;
8246 break;
8247
8248 case 4: /* fmul[sd]. */
8249 case 5: /* fnmul[sd]. */
8250 case 6: /* fadd[sd]. */
8251 case 7: /* fsub[sd]. */
8252 vpipe = VFP11_FMAC;
8253 goto vfp_binop;
8254
8255 case 8: /* fdiv[sd]. */
8256 vpipe = VFP11_DS;
8257 vfp_binop:
8258 bfd_arm_vfp11_write_mask (destmask, fd);
8259 regs[0] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
8260 regs[1] = fm;
8261 *numregs = 2;
8262 break;
8263
8264 case 15: /* extended opcode. */
8265 {
8266 unsigned int extn = ((insn >> 15) & 0x1e)
8267 | ((insn >> 7) & 1);
8268
8269 switch (extn)
8270 {
8271 case 0: /* fcpy[sd]. */
8272 case 1: /* fabs[sd]. */
8273 case 2: /* fneg[sd]. */
8274 case 8: /* fcmp[sd]. */
8275 case 9: /* fcmpe[sd]. */
8276 case 10: /* fcmpz[sd]. */
8277 case 11: /* fcmpez[sd]. */
8278 case 16: /* fuito[sd]. */
8279 case 17: /* fsito[sd]. */
8280 case 24: /* ftoui[sd]. */
8281 case 25: /* ftouiz[sd]. */
8282 case 26: /* ftosi[sd]. */
8283 case 27: /* ftosiz[sd]. */
8284 /* These instructions will not bounce due to underflow. */
8285 *numregs = 0;
8286 vpipe = VFP11_FMAC;
8287 break;
8288
8289 case 3: /* fsqrt[sd]. */
8290 /* fsqrt cannot underflow, but it can (perhaps) overwrite
8291 registers to cause the erratum in previous instructions. */
8292 bfd_arm_vfp11_write_mask (destmask, fd);
8293 vpipe = VFP11_DS;
8294 break;
8295
8296 case 15: /* fcvt{ds,sd}. */
8297 {
8298 int rnum = 0;
8299
8300 bfd_arm_vfp11_write_mask (destmask, fd);
c7b8f16e
JB		 8301
8302 /* Only FCVTSD can underflow. */
99059e56
RM		 8303 if ((insn & 0x100) != 0)
8304 regs[rnum++] = fm;
c7b8f16e 8305
99059e56 8306 *numregs = rnum;
c7b8f16e 8307
99059e56
RM		 8308 vpipe = VFP11_FMAC;
8309 }
8310 break;
c7b8f16e 8311
99059e56
RM		 8312 default:
8313 return VFP11_BAD;
8314 }
8315 }
8316 break;
c7b8f16e 8317
99059e56
RM		 8318 default:
8319 return VFP11_BAD;
8320 }
c7b8f16e
JB		 8321 }
8322 /* Two-register transfer. */
8323 else if ((insn & 0x0fe00ed0) == 0x0c400a10)
8324 {
8325 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
906e58ca 8326
c7b8f16e
JB		 8327 if ((insn & 0x100000) == 0)
8328 {
99059e56
RM		 8329 if (is_double)
8330 bfd_arm_vfp11_write_mask (destmask, fm);
8331 else
8332 {
8333 bfd_arm_vfp11_write_mask (destmask, fm);
8334 bfd_arm_vfp11_write_mask (destmask, fm + 1);
8335 }
c7b8f16e
JB		 8336 }
8337
91d6fa6a 8338 vpipe = VFP11_LS;
c7b8f16e
JB		 8339 }
8340 else if ((insn & 0x0e100e00) == 0x0c100a00) /* A load insn. */
8341 {
8342 int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
8343 unsigned int puw = ((insn >> 21) & 0x1) | (((insn >> 23) & 3) << 1);
906e58ca 8344
c7b8f16e 8345 switch (puw)
99059e56
RM		 8346 {
8347 case 0: /* Two-reg transfer. We should catch these above. */
8348 abort ();
906e58ca 8349
99059e56
RM		 8350 case 2: /* fldm[sdx]. */
8351 case 3:
8352 case 5:
8353 {
8354 unsigned int i, offset = insn & 0xff;
c7b8f16e 8355
99059e56
RM		 8356 if (is_double)
8357 offset >>= 1;
c7b8f16e 8358
99059e56
RM		 8359 for (i = fd; i < fd + offset; i++)
8360 bfd_arm_vfp11_write_mask (destmask, i);
8361 }
8362 break;
906e58ca 8363
99059e56
RM		 8364 case 4: /* fld[sd]. */
8365 case 6:
8366 bfd_arm_vfp11_write_mask (destmask, fd);
8367 break;
906e58ca 8368
99059e56
RM		 8369 default:
8370 return VFP11_BAD;
8371 }
c7b8f16e 8372
91d6fa6a 8373 vpipe = VFP11_LS;
c7b8f16e
JB		 8374 }
8375 /* Single-register transfer. Note L==0. */
8376 else if ((insn & 0x0f100e10) == 0x0e000a10)
8377 {
8378 unsigned int opcode = (insn >> 21) & 7;
8379 unsigned int fn = bfd_arm_vfp11_regno (insn, is_double, 16, 7);
8380
8381 switch (opcode)
99059e56
RM		 8382 {
8383 case 0: /* fmsr/fmdlr. */
8384 case 1: /* fmdhr. */
8385 /* Mark fmdhr and fmdlr as writing to the whole of the DP
8386 destination register. I don't know if this is exactly right,
8387 but it is the conservative choice. */
8388 bfd_arm_vfp11_write_mask (destmask, fn);
8389 break;
8390
8391 case 7: /* fmxr. */
8392 break;
8393 }
c7b8f16e 8394
91d6fa6a 8395 vpipe = VFP11_LS;
c7b8f16e
JB		 8396 }
8397
91d6fa6a 8398 return vpipe;
c7b8f16e
JB		 8399}
8400
8401
8402static int elf32_arm_compare_mapping (const void * a, const void * b);
8403
8404
8405/* Look for potentially-troublesome code sequences which might trigger the
8406 VFP11 denormal/antidependency erratum. See, e.g., the ARM1136 errata sheet
8407 (available from ARM) for details of the erratum. A short version is
8408 described in ld.texinfo. */
8409
8410bfd_boolean
8411bfd_elf32_arm_vfp11_erratum_scan (bfd *abfd, struct bfd_link_info *link_info)
8412{
8413 asection *sec;
8414 bfd_byte *contents = NULL;
8415 int state = 0;
8416 int regs[3], numregs = 0;
8417 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8418 int use_vector = (globals->vfp11_fix == BFD_ARM_VFP11_FIX_VECTOR);
906e58ca 8419
4dfe6ac6
NC		 8420 if (globals == NULL)
8421 return FALSE;
8422
c7b8f16e
JB		 8423 /* We use a simple FSM to match troublesome VFP11 instruction sequences.
8424 The states transition as follows:
906e58ca 8425
c7b8f16e 8426 0 -> 1 (vector) or 0 -> 2 (scalar)
99059e56
RM		 8427 A VFP FMAC-pipeline instruction has been seen. Fill
8428 regs[0]..regs[numregs-1] with its input operands. Remember this
8429 instruction in 'first_fmac'.
c7b8f16e
JB		 8430
8431 1 -> 2
99059e56
RM		 8432 Any instruction, except for a VFP instruction which overwrites
8433 regs[*].
906e58ca 8434
c7b8f16e
JB		 8435 1 -> 3 [ -> 0 ] or
8436 2 -> 3 [ -> 0 ]
99059e56
RM		 8437 A VFP instruction has been seen which overwrites any of regs[*].
8438 We must make a veneer! Reset state to 0 before examining next
8439 instruction.
906e58ca 8440
c7b8f16e 8441 2 -> 0
99059e56
RM		 8442 If we fail to match anything in state 2, reset to state 0 and reset
8443 the instruction pointer to the instruction after 'first_fmac'.
c7b8f16e
JB		 8444
8445 If the VFP11 vector mode is in use, there must be at least two unrelated
8446 instructions between anti-dependent VFP11 instructions to properly avoid
906e58ca 8447 triggering the erratum, hence the use of the extra state 1. */
c7b8f16e
JB		 8448
8449 /* If we are only performing a partial link do not bother
8450 to construct any glue. */
0e1862bb 8451 if (bfd_link_relocatable (link_info))
c7b8f16e
JB		 8452 return TRUE;
8453
0ffa91dd
NC		 8454 /* Skip if this bfd does not correspond to an ELF image. */
8455 if (! is_arm_elf (abfd))
8456 return TRUE;
906e58ca 8457
c7b8f16e
JB		 8458 /* We should have chosen a fix type by the time we get here. */
8459 BFD_ASSERT (globals->vfp11_fix != BFD_ARM_VFP11_FIX_DEFAULT);
8460
8461 if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_NONE)
8462 return TRUE;
2e6030b9 8463
33a7ffc2
JM		 8464 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8465 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8466 return TRUE;
8467
c7b8f16e
JB		 8468 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8469 {
8470 unsigned int i, span, first_fmac = 0, veneer_of_insn = 0;
8471 struct _arm_elf_section_data *sec_data;
8472
8473 /* If we don't have executable progbits, we're not interested in this
99059e56 8474 section. Also skip if section is to be excluded. */
c7b8f16e 8475 if (elf_section_type (sec) != SHT_PROGBITS
99059e56
RM		 8476 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8477 || (sec->flags & SEC_EXCLUDE) != 0
dbaa2011 8478 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
33a7ffc2 8479 || sec->output_section == bfd_abs_section_ptr
99059e56
RM		 8480 || strcmp (sec->name, VFP11_ERRATUM_VENEER_SECTION_NAME) == 0)
8481 continue;
c7b8f16e
JB		 8482
8483 sec_data = elf32_arm_section_data (sec);
906e58ca 8484
c7b8f16e 8485 if (sec_data->mapcount == 0)
99059e56 8486 continue;
906e58ca 8487
c7b8f16e
JB		 8488 if (elf_section_data (sec)->this_hdr.contents != NULL)
8489 contents = elf_section_data (sec)->this_hdr.contents;
8490 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8491 goto error_return;
8492
8493 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8494 elf32_arm_compare_mapping);
8495
8496 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 8497 {
8498 unsigned int span_start = sec_data->map[span].vma;
8499 unsigned int span_end = (span == sec_data->mapcount - 1)
c7b8f16e 8500 ? sec->size : sec_data->map[span + 1].vma;
99059e56
RM		 8501 char span_type = sec_data->map[span].type;
8502
8503 /* FIXME: Only ARM mode is supported at present. We may need to
8504 support Thumb-2 mode also at some point. */
8505 if (span_type != 'a')
8506 continue;
8507
8508 for (i = span_start; i < span_end;)
8509 {
8510 unsigned int next_i = i + 4;
8511 unsigned int insn = bfd_big_endian (abfd)
13c9c485
AM		 8512 ? (((unsigned) contents[i] << 24)
8513 | (contents[i + 1] << 16)
8514 | (contents[i + 2] << 8)
8515 | contents[i + 3])
8516 : (((unsigned) contents[i + 3] << 24)
8517 | (contents[i + 2] << 16)
8518 | (contents[i + 1] << 8)
8519 | contents[i]);
99059e56
RM		 8520 unsigned int writemask = 0;
8521 enum bfd_arm_vfp11_pipe vpipe;
8522
8523 switch (state)
8524 {
8525 case 0:
8526 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask, regs,
8527 &numregs);
8528 /* I'm assuming the VFP11 erratum can trigger with denorm
8529 operands on either the FMAC or the DS pipeline. This might
8530 lead to slightly overenthusiastic veneer insertion. */
8531 if (vpipe == VFP11_FMAC || vpipe == VFP11_DS)
8532 {
8533 state = use_vector ? 1 : 2;
8534 first_fmac = i;
8535 veneer_of_insn = insn;
8536 }
8537 break;
8538
8539 case 1:
8540 {
8541 int other_regs[3], other_numregs;
8542 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8543 other_regs,
99059e56
RM		 8544 &other_numregs);
8545 if (vpipe != VFP11_BAD
8546 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8547 numregs))
99059e56
RM		 8548 state = 3;
8549 else
8550 state = 2;
8551 }
8552 break;
8553
8554 case 2:
8555 {
8556 int other_regs[3], other_numregs;
8557 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8558 other_regs,
99059e56
RM		 8559 &other_numregs);
8560 if (vpipe != VFP11_BAD
8561 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8562 numregs))
99059e56
RM		 8563 state = 3;
8564 else
8565 {
8566 state = 0;
8567 next_i = first_fmac + 4;
8568 }
8569 }
8570 break;
8571
8572 case 3:
8573 abort (); /* Should be unreachable. */
8574 }
8575
8576 if (state == 3)
8577 {
8578 elf32_vfp11_erratum_list *newerr =(elf32_vfp11_erratum_list *)
8579 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
8580
8581 elf32_arm_section_data (sec)->erratumcount += 1;
8582
8583 newerr->u.b.vfp_insn = veneer_of_insn;
8584
8585 switch (span_type)
8586 {
8587 case 'a':
8588 newerr->type = VFP11_ERRATUM_BRANCH_TO_ARM_VENEER;
8589 break;
8590
8591 default:
8592 abort ();
8593 }
8594
8595 record_vfp11_erratum_veneer (link_info, newerr, abfd, sec,
c7b8f16e
JB		 8596 first_fmac);
8597
99059e56 8598 newerr->vma = -1;
c7b8f16e 8599
99059e56
RM		 8600 newerr->next = sec_data->erratumlist;
8601 sec_data->erratumlist = newerr;
c7b8f16e 8602
99059e56
RM		 8603 state = 0;
8604 }
c7b8f16e 8605
99059e56
RM		 8606 i = next_i;
8607 }
8608 }
906e58ca 8609
c7b8f16e 8610 if (contents != NULL
99059e56
RM		 8611 && elf_section_data (sec)->this_hdr.contents != contents)
8612 free (contents);
c7b8f16e
JB		 8613 contents = NULL;
8614 }
8615
8616 return TRUE;
8617
dc1e8a47 8618 error_return:
c7b8f16e
JB		 8619 if (contents != NULL
8620 && elf_section_data (sec)->this_hdr.contents != contents)
8621 free (contents);
906e58ca 8622
c7b8f16e
JB		 8623 return FALSE;
8624}
8625
8626/* Find virtual-memory addresses for VFP11 erratum veneers and return locations
8627 after sections have been laid out, using specially-named symbols. */
8628
8629void
8630bfd_elf32_arm_vfp11_fix_veneer_locations (bfd *abfd,
8631 struct bfd_link_info *link_info)
8632{
8633 asection *sec;
8634 struct elf32_arm_link_hash_table *globals;
8635 char *tmp_name;
906e58ca 8636
0e1862bb 8637 if (bfd_link_relocatable (link_info))
c7b8f16e 8638 return;
2e6030b9
MS		 8639
8640 /* Skip if this bfd does not correspond to an ELF image. */
0ffa91dd 8641 if (! is_arm_elf (abfd))
2e6030b9
MS		 8642 return;
8643
c7b8f16e 8644 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8645 if (globals == NULL)
8646 return;
906e58ca 8647
21d799b5 8648 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 8649 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
7a0fb7be 8650 BFD_ASSERT (tmp_name);
c7b8f16e
JB		 8651
8652 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8653 {
8654 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8655 elf32_vfp11_erratum_list *errnode = sec_data->erratumlist;
906e58ca 8656
c7b8f16e 8657 for (; errnode != NULL; errnode = errnode->next)
99059e56
RM		 8658 {
8659 struct elf_link_hash_entry *myh;
8660 bfd_vma vma;
8661
8662 switch (errnode->type)
8663 {
8664 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
8665 case VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER:
8666 /* Find veneer symbol. */
8667 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
c7b8f16e
JB		 8668 errnode->u.b.veneer->u.v.id);
8669
99059e56
RM		 8670 myh = elf_link_hash_lookup
8671 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
c7b8f16e 8672
a504d23a 8673 if (myh == NULL)
90b6238f
AM		 8674 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8675 abfd, "VFP11", tmp_name);
a504d23a
LA		 8676
8677 vma = myh->root.u.def.section->output_section->vma
8678 + myh->root.u.def.section->output_offset
8679 + myh->root.u.def.value;
8680
8681 errnode->u.b.veneer->vma = vma;
8682 break;
8683
8684 case VFP11_ERRATUM_ARM_VENEER:
8685 case VFP11_ERRATUM_THUMB_VENEER:
8686 /* Find return location. */
8687 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
8688 errnode->u.v.id);
8689
8690 myh = elf_link_hash_lookup
8691 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8692
8693 if (myh == NULL)
90b6238f
AM		 8694 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8695 abfd, "VFP11", tmp_name);
a504d23a
LA		 8696
8697 vma = myh->root.u.def.section->output_section->vma
8698 + myh->root.u.def.section->output_offset
8699 + myh->root.u.def.value;
8700
8701 errnode->u.v.branch->vma = vma;
8702 break;
8703
8704 default:
8705 abort ();
8706 }
8707 }
8708 }
8709
8710 free (tmp_name);
8711}
8712
8713/* Find virtual-memory addresses for STM32L4XX erratum veneers and
8714 return locations after sections have been laid out, using
8715 specially-named symbols. */
8716
8717void
8718bfd_elf32_arm_stm32l4xx_fix_veneer_locations (bfd *abfd,
8719 struct bfd_link_info *link_info)
8720{
8721 asection *sec;
8722 struct elf32_arm_link_hash_table *globals;
8723 char *tmp_name;
8724
8725 if (bfd_link_relocatable (link_info))
8726 return;
8727
8728 /* Skip if this bfd does not correspond to an ELF image. */
8729 if (! is_arm_elf (abfd))
8730 return;
8731
8732 globals = elf32_arm_hash_table (link_info);
8733 if (globals == NULL)
8734 return;
8735
8736 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
8737 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
7a0fb7be 8738 BFD_ASSERT (tmp_name);
a504d23a
LA		 8739
8740 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8741 {
8742 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8743 elf32_stm32l4xx_erratum_list *errnode = sec_data->stm32l4xx_erratumlist;
8744
8745 for (; errnode != NULL; errnode = errnode->next)
8746 {
8747 struct elf_link_hash_entry *myh;
8748 bfd_vma vma;
8749
8750 switch (errnode->type)
8751 {
8752 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
8753 /* Find veneer symbol. */
8754 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
8755 errnode->u.b.veneer->u.v.id);
8756
8757 myh = elf_link_hash_lookup
8758 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8759
8760 if (myh == NULL)
90b6238f
AM		 8761 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8762 abfd, "STM32L4XX", tmp_name);
a504d23a
LA		 8763
8764 vma = myh->root.u.def.section->output_section->vma
8765 + myh->root.u.def.section->output_offset
8766 + myh->root.u.def.value;
8767
8768 errnode->u.b.veneer->vma = vma;
8769 break;
8770
8771 case STM32L4XX_ERRATUM_VENEER:
8772 /* Find return location. */
8773 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
8774 errnode->u.v.id);
8775
8776 myh = elf_link_hash_lookup
8777 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8778
8779 if (myh == NULL)
90b6238f
AM		 8780 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8781 abfd, "STM32L4XX", tmp_name);
a504d23a
LA		 8782
8783 vma = myh->root.u.def.section->output_section->vma
8784 + myh->root.u.def.section->output_offset
8785 + myh->root.u.def.value;
8786
8787 errnode->u.v.branch->vma = vma;
8788 break;
8789
8790 default:
8791 abort ();
8792 }
8793 }
8794 }
8795
8796 free (tmp_name);
8797}
8798
8799static inline bfd_boolean
8800is_thumb2_ldmia (const insn32 insn)
8801{
8802 /* Encoding T2: LDM<c>.W <Rn>{!},<registers>
8803 1110 - 1000 - 10W1 - rrrr - PM (0) l - llll - llll - llll. */
8804 return (insn & 0xffd02000) == 0xe8900000;
8805}
8806
8807static inline bfd_boolean
8808is_thumb2_ldmdb (const insn32 insn)
8809{
8810 /* Encoding T1: LDMDB<c> <Rn>{!},<registers>
8811 1110 - 1001 - 00W1 - rrrr - PM (0) l - llll - llll - llll. */
8812 return (insn & 0xffd02000) == 0xe9100000;
8813}
8814
8815static inline bfd_boolean
8816is_thumb2_vldm (const insn32 insn)
8817{
8818 /* A6.5 Extension register load or store instruction
8819 A7.7.229
9239bbd3
CM		 8820 We look for SP 32-bit and DP 64-bit registers.
8821 Encoding T1 VLDM{mode}<c> <Rn>{!}, <list>
8822 <list> is consecutive 64-bit registers
8823 1110 - 110P - UDW1 - rrrr - vvvv - 1011 - iiii - iiii
a504d23a
LA		 8824 Encoding T2 VLDM{mode}<c> <Rn>{!}, <list>
8825 <list> is consecutive 32-bit registers
8826 1110 - 110P - UDW1 - rrrr - vvvv - 1010 - iiii - iiii
8827 if P==0 && U==1 && W==1 && Rn=1101 VPOP
8828 if PUW=010 || PUW=011 || PUW=101 VLDM. */
8829 return
9239bbd3
CM		 8830 (((insn & 0xfe100f00) == 0xec100b00) ||
8831 ((insn & 0xfe100f00) == 0xec100a00))
a504d23a
LA		 8832 && /* (IA without !). */
8833 (((((insn << 7) >> 28) & 0xd) == 0x4)
9239bbd3 8834 /* (IA with !), includes VPOP (when reg number is SP). */
a504d23a
LA		 8835 || ((((insn << 7) >> 28) & 0xd) == 0x5)
8836 /* (DB with !). */
8837 || ((((insn << 7) >> 28) & 0xd) == 0x9));
8838}
8839
8840/* STM STM32L4XX erratum : This function assumes that it receives an LDM or
8841 VLDM opcode and:
8842 - computes the number and the mode of memory accesses
8843 - decides if the replacement should be done:
8844 . replaces only if > 8-word accesses
8845 . or (testing purposes only) replaces all accesses. */
8846
8847static bfd_boolean
8848stm32l4xx_need_create_replacing_stub (const insn32 insn,
8849 bfd_arm_stm32l4xx_fix stm32l4xx_fix)
8850{
9239bbd3 8851 int nb_words = 0;
a504d23a
LA		 8852
8853 /* The field encoding the register list is the same for both LDMIA
8854 and LDMDB encodings. */
8855 if (is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn))
b25e998d 8856 nb_words = elf32_arm_popcount (insn & 0x0000ffff);
a504d23a 8857 else if (is_thumb2_vldm (insn))
9239bbd3 8858 nb_words = (insn & 0xff);
a504d23a
LA		 8859
8860 /* DEFAULT mode accounts for the real bug condition situation,
8861 ALL mode inserts stubs for each LDM/VLDM instruction (testing). */
8862 return
9239bbd3 8863 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_DEFAULT) ? nb_words > 8 :
a504d23a
LA		 8864 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_ALL) ? TRUE : FALSE;
8865}
8866
8867/* Look for potentially-troublesome code sequences which might trigger
8868 the STM STM32L4XX erratum. */
8869
8870bfd_boolean
8871bfd_elf32_arm_stm32l4xx_erratum_scan (bfd *abfd,
8872 struct bfd_link_info *link_info)
8873{
8874 asection *sec;
8875 bfd_byte *contents = NULL;
8876 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8877
8878 if (globals == NULL)
8879 return FALSE;
8880
8881 /* If we are only performing a partial link do not bother
8882 to construct any glue. */
8883 if (bfd_link_relocatable (link_info))
8884 return TRUE;
8885
8886 /* Skip if this bfd does not correspond to an ELF image. */
8887 if (! is_arm_elf (abfd))
8888 return TRUE;
8889
8890 if (globals->stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_NONE)
8891 return TRUE;
8892
8893 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8894 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8895 return TRUE;
8896
8897 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8898 {
8899 unsigned int i, span;
8900 struct _arm_elf_section_data *sec_data;
8901
8902 /* If we don't have executable progbits, we're not interested in this
8903 section. Also skip if section is to be excluded. */
8904 if (elf_section_type (sec) != SHT_PROGBITS
8905 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8906 || (sec->flags & SEC_EXCLUDE) != 0
8907 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
8908 || sec->output_section == bfd_abs_section_ptr
8909 || strcmp (sec->name, STM32L4XX_ERRATUM_VENEER_SECTION_NAME) == 0)
8910 continue;
8911
8912 sec_data = elf32_arm_section_data (sec);
c7b8f16e 8913
a504d23a
LA		 8914 if (sec_data->mapcount == 0)
8915 continue;
c7b8f16e 8916
a504d23a
LA		 8917 if (elf_section_data (sec)->this_hdr.contents != NULL)
8918 contents = elf_section_data (sec)->this_hdr.contents;
8919 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8920 goto error_return;
c7b8f16e 8921
a504d23a
LA		 8922 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8923 elf32_arm_compare_mapping);
c7b8f16e 8924
a504d23a
LA		 8925 for (span = 0; span < sec_data->mapcount; span++)
8926 {
8927 unsigned int span_start = sec_data->map[span].vma;
8928 unsigned int span_end = (span == sec_data->mapcount - 1)
8929 ? sec->size : sec_data->map[span + 1].vma;
8930 char span_type = sec_data->map[span].type;
8931 int itblock_current_pos = 0;
c7b8f16e 8932
a504d23a
LA		 8933 /* Only Thumb2 mode need be supported with this CM4 specific
8934 code, we should not encounter any arm mode eg span_type
8935 != 'a'. */
8936 if (span_type != 't')
8937 continue;
c7b8f16e 8938
a504d23a
LA		 8939 for (i = span_start; i < span_end;)
8940 {
8941 unsigned int insn = bfd_get_16 (abfd, &contents[i]);
8942 bfd_boolean insn_32bit = FALSE;
8943 bfd_boolean is_ldm = FALSE;
8944 bfd_boolean is_vldm = FALSE;
8945 bfd_boolean is_not_last_in_it_block = FALSE;
8946
8947 /* The first 16-bits of all 32-bit thumb2 instructions start
8948 with opcode[15..13]=0b111 and the encoded op1 can be anything
8949 except opcode[12..11]!=0b00.
8950 See 32-bit Thumb instruction encoding. */
8951 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
8952 insn_32bit = TRUE;
c7b8f16e 8953
a504d23a
LA		 8954 /* Compute the predicate that tells if the instruction
8955 is concerned by the IT block
8956 - Creates an error if there is a ldm that is not
8957 last in the IT block thus cannot be replaced
8958 - Otherwise we can create a branch at the end of the
8959 IT block, it will be controlled naturally by IT
8960 with the proper pseudo-predicate
8961 - So the only interesting predicate is the one that
8962 tells that we are not on the last item of an IT
8963 block. */
8964 if (itblock_current_pos != 0)
8965 is_not_last_in_it_block = !!--itblock_current_pos;
906e58ca 8966
a504d23a
LA		 8967 if (insn_32bit)
8968 {
8969 /* Load the rest of the insn (in manual-friendly order). */
8970 insn = (insn << 16) | bfd_get_16 (abfd, &contents[i + 2]);
8971 is_ldm = is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn);
8972 is_vldm = is_thumb2_vldm (insn);
8973
8974 /* Veneers are created for (v)ldm depending on
8975 option flags and memory accesses conditions; but
8976 if the instruction is not the last instruction of
8977 an IT block, we cannot create a jump there, so we
8978 bail out. */
5025eb7c
AO		 8979 if ((is_ldm || is_vldm)
8980 && stm32l4xx_need_create_replacing_stub
a504d23a
LA		 8981 (insn, globals->stm32l4xx_fix))
8982 {
8983 if (is_not_last_in_it_block)
8984 {
4eca0228 8985 _bfd_error_handler
695344c0 8986 /* xgettext:c-format */
871b3ab2 8987 (_("%pB(%pA+%#x): error: multiple load detected"
90b6238f
AM		 8988 " in non-last IT block instruction:"
8989 " STM32L4XX veneer cannot be generated; "
8990 "use gcc option -mrestrict-it to generate"
8991 " only one instruction per IT block"),
d42c267e 8992 abfd, sec, i);
a504d23a
LA		 8993 }
8994 else
8995 {
8996 elf32_stm32l4xx_erratum_list *newerr =
8997 (elf32_stm32l4xx_erratum_list *)
8998 bfd_zmalloc
8999 (sizeof (elf32_stm32l4xx_erratum_list));
9000
9001 elf32_arm_section_data (sec)
9002 ->stm32l4xx_erratumcount += 1;
9003 newerr->u.b.insn = insn;
9004 /* We create only thumb branches. */
9005 newerr->type =
9006 STM32L4XX_ERRATUM_BRANCH_TO_VENEER;
9007 record_stm32l4xx_erratum_veneer
9008 (link_info, newerr, abfd, sec,
9009 i,
9010 is_ldm ?
9011 STM32L4XX_ERRATUM_LDM_VENEER_SIZE:
9012 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
9013 newerr->vma = -1;
9014 newerr->next = sec_data->stm32l4xx_erratumlist;
9015 sec_data->stm32l4xx_erratumlist = newerr;
9016 }
9017 }
9018 }
9019 else
9020 {
9021 /* A7.7.37 IT p208
9022 IT blocks are only encoded in T1
9023 Encoding T1: IT{x{y{z}}} <firstcond>
9024 1 0 1 1 - 1 1 1 1 - firstcond - mask
9025 if mask = '0000' then see 'related encodings'
9026 We don't deal with UNPREDICTABLE, just ignore these.
9027 There can be no nested IT blocks so an IT block
9028 is naturally a new one for which it is worth
9029 computing its size. */
5025eb7c
AO		 9030 bfd_boolean is_newitblock = ((insn & 0xff00) == 0xbf00)
9031 && ((insn & 0x000f) != 0x0000);
a504d23a
LA		 9032 /* If we have a new IT block we compute its size. */
9033 if (is_newitblock)
9034 {
9035 /* Compute the number of instructions controlled
9036 by the IT block, it will be used to decide
9037 whether we are inside an IT block or not. */
9038 unsigned int mask = insn & 0x000f;
9039 itblock_current_pos = 4 - ctz (mask);
9040 }
9041 }
9042
9043 i += insn_32bit ? 4 : 2;
99059e56
RM		 9044 }
9045 }
a504d23a
LA		 9046
9047 if (contents != NULL
9048 && elf_section_data (sec)->this_hdr.contents != contents)
9049 free (contents);
9050 contents = NULL;
c7b8f16e 9051 }
906e58ca 9052
a504d23a
LA		 9053 return TRUE;
9054
dc1e8a47 9055 error_return:
a504d23a
LA		 9056 if (contents != NULL
9057 && elf_section_data (sec)->this_hdr.contents != contents)
9058 free (contents);
c7b8f16e 9059
a504d23a
LA		 9060 return FALSE;
9061}
c7b8f16e 9062
eb043451
PB		 9063/* Set target relocation values needed during linking. */
9064
9065void
68c39892 9066bfd_elf32_arm_set_target_params (struct bfd *output_bfd,
bf21ed78 9067 struct bfd_link_info *link_info,
68c39892 9068 struct elf32_arm_params *params)
eb043451
PB		 9069{
9070 struct elf32_arm_link_hash_table *globals;
9071
9072 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 9073 if (globals == NULL)
9074 return;
eb043451 9075
68c39892 9076 globals->target1_is_rel = params->target1_is_rel;
29e9b073
CL		 9077 if (globals->fdpic_p)
9078 globals->target2_reloc = R_ARM_GOT32;
9079 else if (strcmp (params->target2_type, "rel") == 0)
eb043451 9080 globals->target2_reloc = R_ARM_REL32;
68c39892 9081 else if (strcmp (params->target2_type, "abs") == 0)
eeac373a 9082 globals->target2_reloc = R_ARM_ABS32;
68c39892 9083 else if (strcmp (params->target2_type, "got-rel") == 0)
eb043451
PB		 9084 globals->target2_reloc = R_ARM_GOT_PREL;
9085 else
9086 {
90b6238f 9087 _bfd_error_handler (_("invalid TARGET2 relocation type '%s'"),
68c39892 9088 params->target2_type);
eb043451 9089 }
68c39892
TP		 9090 globals->fix_v4bx = params->fix_v4bx;
9091 globals->use_blx |= params->use_blx;
9092 globals->vfp11_fix = params->vfp11_denorm_fix;
9093 globals->stm32l4xx_fix = params->stm32l4xx_fix;
e8b09b87
CL		 9094 if (globals->fdpic_p)
9095 globals->pic_veneer = 1;
9096 else
9097 globals->pic_veneer = params->pic_veneer;
68c39892
TP		 9098 globals->fix_cortex_a8 = params->fix_cortex_a8;
9099 globals->fix_arm1176 = params->fix_arm1176;
9100 globals->cmse_implib = params->cmse_implib;
9101 globals->in_implib_bfd = params->in_implib_bfd;
bf21ed78 9102
0ffa91dd 9103 BFD_ASSERT (is_arm_elf (output_bfd));
68c39892
TP		 9104 elf_arm_tdata (output_bfd)->no_enum_size_warning
9105 = params->no_enum_size_warning;
9106 elf_arm_tdata (output_bfd)->no_wchar_size_warning
9107 = params->no_wchar_size_warning;
eb043451 9108}
eb043451 9109
12a0a0fd 9110/* Replace the target offset of a Thumb bl or b.w instruction. */
252b5132 9111
12a0a0fd
PB		 9112static void
9113insert_thumb_branch (bfd *abfd, long int offset, bfd_byte *insn)
9114{
9115 bfd_vma upper;
9116 bfd_vma lower;
9117 int reloc_sign;
9118
9119 BFD_ASSERT ((offset & 1) == 0);
9120
9121 upper = bfd_get_16 (abfd, insn);
9122 lower = bfd_get_16 (abfd, insn + 2);
9123 reloc_sign = (offset < 0) ? 1 : 0;
9124 upper = (upper & ~(bfd_vma) 0x7ff)
9125 | ((offset >> 12) & 0x3ff)
9126 | (reloc_sign << 10);
906e58ca 9127 lower = (lower & ~(bfd_vma) 0x2fff)
12a0a0fd
PB		 9128 | (((!((offset >> 23) & 1)) ^ reloc_sign) << 13)
9129 | (((!((offset >> 22) & 1)) ^ reloc_sign) << 11)
9130 | ((offset >> 1) & 0x7ff);
9131 bfd_put_16 (abfd, upper, insn);
9132 bfd_put_16 (abfd, lower, insn + 2);
252b5132
RH		 9133}
9134
9b485d32
NC		 9135/* Thumb code calling an ARM function. */
9136
252b5132 9137static int
57e8b36a 9138elf32_thumb_to_arm_stub (struct bfd_link_info * info,
07d6d2b8
AM		 9139 const char * name,
9140 bfd * input_bfd,
9141 bfd * output_bfd,
9142 asection * input_section,
9143 bfd_byte * hit_data,
9144 asection * sym_sec,
9145 bfd_vma offset,
9146 bfd_signed_vma addend,
9147 bfd_vma val,
f2a9dd69 9148 char **error_message)
252b5132 9149{
bcbdc74c 9150 asection * s = 0;
dc810e39 9151 bfd_vma my_offset;
252b5132 9152 long int ret_offset;
bcbdc74c
NC		 9153 struct elf_link_hash_entry * myh;
9154 struct elf32_arm_link_hash_table * globals;
252b5132 9155
f2a9dd69 9156 myh = find_thumb_glue (info, name, error_message);
252b5132 9157 if (myh == NULL)
b34976b6 9158 return FALSE;
252b5132
RH		 9159
9160 globals = elf32_arm_hash_table (info);
252b5132
RH		 9161 BFD_ASSERT (globals != NULL);
9162 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9163
9164 my_offset = myh->root.u.def.value;
9165
3d4d4302
AM		 9166 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9167 THUMB2ARM_GLUE_SECTION_NAME);
252b5132
RH		 9168
9169 BFD_ASSERT (s != NULL);
9170 BFD_ASSERT (s->contents != NULL);
9171 BFD_ASSERT (s->output_section != NULL);
9172
9173 if ((my_offset & 0x01) == 0x01)
9174 {
9175 if (sym_sec != NULL
9176 && sym_sec->owner != NULL
9177 && !INTERWORK_FLAG (sym_sec->owner))
9178 {
4eca0228 9179 _bfd_error_handler
90b6238f
AM		 9180 (_("%pB(%s): warning: interworking not enabled;"
9181 " first occurrence: %pB: %s call to %s"),
9182 sym_sec->owner, name, input_bfd, "Thumb", "ARM");
252b5132 9183
b34976b6 9184 return FALSE;
252b5132
RH		 9185 }
9186
9187 --my_offset;
9188 myh->root.u.def.value = my_offset;
9189
52ab56c2
PB		 9190 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a1_bx_pc_insn,
9191 s->contents + my_offset);
252b5132 9192
52ab56c2
PB		 9193 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a2_noop_insn,
9194 s->contents + my_offset + 2);
252b5132
RH		 9195
9196 ret_offset =
9b485d32
NC		 9197 /* Address of destination of the stub. */
9198 ((bfd_signed_vma) val)
252b5132 9199 - ((bfd_signed_vma)
57e8b36a
NC		 9200 /* Offset from the start of the current section
9201 to the start of the stubs. */
9b485d32
NC		 9202 (s->output_offset
9203 /* Offset of the start of this stub from the start of the stubs. */
9204 + my_offset
9205 /* Address of the start of the current section. */
9206 + s->output_section->vma)
9207 /* The branch instruction is 4 bytes into the stub. */
9208 + 4
9209 /* ARM branches work from the pc of the instruction + 8. */
9210 + 8);
252b5132 9211
52ab56c2
PB		 9212 put_arm_insn (globals, output_bfd,
9213 (bfd_vma) t2a3_b_insn | ((ret_offset >> 2) & 0x00FFFFFF),
9214 s->contents + my_offset + 4);
252b5132
RH		 9215 }
9216
9217 BFD_ASSERT (my_offset <= globals->thumb_glue_size);
9218
427bfd90
NC		 9219 /* Now go back and fix up the original BL insn to point to here. */
9220 ret_offset =
9221 /* Address of where the stub is located. */
9222 (s->output_section->vma + s->output_offset + my_offset)
9223 /* Address of where the BL is located. */
57e8b36a
NC		 9224 - (input_section->output_section->vma + input_section->output_offset
9225 + offset)
427bfd90
NC		 9226 /* Addend in the relocation. */
9227 - addend
9228 /* Biassing for PC-relative addressing. */
9229 - 8;
252b5132 9230
12a0a0fd 9231 insert_thumb_branch (input_bfd, ret_offset, hit_data - input_section->vma);
252b5132 9232
b34976b6 9233 return TRUE;
252b5132
RH		 9234}
9235
a4fd1a8e 9236/* Populate an Arm to Thumb stub. Returns the stub symbol. */
9b485d32 9237
a4fd1a8e
PB		 9238static struct elf_link_hash_entry *
9239elf32_arm_create_thumb_stub (struct bfd_link_info * info,
07d6d2b8
AM		 9240 const char * name,
9241 bfd * input_bfd,
9242 bfd * output_bfd,
9243 asection * sym_sec,
9244 bfd_vma val,
9245 asection * s,
9246 char ** error_message)
252b5132 9247{
dc810e39 9248 bfd_vma my_offset;
252b5132 9249 long int ret_offset;
bcbdc74c
NC		 9250 struct elf_link_hash_entry * myh;
9251 struct elf32_arm_link_hash_table * globals;
252b5132 9252
f2a9dd69 9253 myh = find_arm_glue (info, name, error_message);
252b5132 9254 if (myh == NULL)
a4fd1a8e 9255 return NULL;
252b5132
RH		 9256
9257 globals = elf32_arm_hash_table (info);
252b5132
RH		 9258 BFD_ASSERT (globals != NULL);
9259 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9260
9261 my_offset = myh->root.u.def.value;
252b5132
RH		 9262
9263 if ((my_offset & 0x01) == 0x01)
9264 {
9265 if (sym_sec != NULL
9266 && sym_sec->owner != NULL
9267 && !INTERWORK_FLAG (sym_sec->owner))
9268 {
4eca0228 9269 _bfd_error_handler
90b6238f
AM		 9270 (_("%pB(%s): warning: interworking not enabled;"
9271 " first occurrence: %pB: %s call to %s"),
9272 sym_sec->owner, name, input_bfd, "ARM", "Thumb");
252b5132 9273 }
9b485d32 9274
252b5132
RH		 9275 --my_offset;
9276 myh->root.u.def.value = my_offset;
9277
0e1862bb
L		 9278 if (bfd_link_pic (info)
9279 || globals->root.is_relocatable_executable
27e55c4d 9280 || globals->pic_veneer)
8f6277f5
PB		 9281 {
9282 /* For relocatable objects we can't use absolute addresses,
9283 so construct the address from a relative offset. */
9284 /* TODO: If the offset is small it's probably worth
9285 constructing the address with adds. */
52ab56c2
PB		 9286 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1p_ldr_insn,
9287 s->contents + my_offset);
9288 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2p_add_pc_insn,
9289 s->contents + my_offset + 4);
9290 put_arm_insn (globals, output_bfd, (bfd_vma) a2t3p_bx_r12_insn,
9291 s->contents + my_offset + 8);
8f6277f5
PB		 9292 /* Adjust the offset by 4 for the position of the add,
9293 and 8 for the pipeline offset. */
9294 ret_offset = (val - (s->output_offset
9295 + s->output_section->vma
9296 + my_offset + 12))
9297 | 1;
9298 bfd_put_32 (output_bfd, ret_offset,
9299 s->contents + my_offset + 12);
9300 }
26079076
PB		 9301 else if (globals->use_blx)
9302 {
9303 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1v5_ldr_insn,
9304 s->contents + my_offset);
9305
9306 /* It's a thumb address. Add the low order bit. */
9307 bfd_put_32 (output_bfd, val | a2t2v5_func_addr_insn,
9308 s->contents + my_offset + 4);
9309 }
8f6277f5
PB		 9310 else
9311 {
52ab56c2
PB		 9312 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1_ldr_insn,
9313 s->contents + my_offset);
252b5132 9314
52ab56c2
PB		 9315 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2_bx_r12_insn,
9316 s->contents + my_offset + 4);
252b5132 9317
8f6277f5
PB		 9318 /* It's a thumb address. Add the low order bit. */
9319 bfd_put_32 (output_bfd, val | a2t3_func_addr_insn,
9320 s->contents + my_offset + 8);
8029a119
NC		 9321
9322 my_offset += 12;
8f6277f5 9323 }
252b5132
RH		 9324 }
9325
9326 BFD_ASSERT (my_offset <= globals->arm_glue_size);
9327
a4fd1a8e
PB		 9328 return myh;
9329}
9330
9331/* Arm code calling a Thumb function. */
9332
9333static int
9334elf32_arm_to_thumb_stub (struct bfd_link_info * info,
07d6d2b8
AM		 9335 const char * name,
9336 bfd * input_bfd,
9337 bfd * output_bfd,
9338 asection * input_section,
9339 bfd_byte * hit_data,
9340 asection * sym_sec,
9341 bfd_vma offset,
9342 bfd_signed_vma addend,
9343 bfd_vma val,
f2a9dd69 9344 char **error_message)
a4fd1a8e
PB		 9345{
9346 unsigned long int tmp;
9347 bfd_vma my_offset;
9348 asection * s;
9349 long int ret_offset;
9350 struct elf_link_hash_entry * myh;
9351 struct elf32_arm_link_hash_table * globals;
9352
9353 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 9354 BFD_ASSERT (globals != NULL);
9355 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9356
3d4d4302
AM		 9357 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9358 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 9359 BFD_ASSERT (s != NULL);
9360 BFD_ASSERT (s->contents != NULL);
9361 BFD_ASSERT (s->output_section != NULL);
9362
9363 myh = elf32_arm_create_thumb_stub (info, name, input_bfd, output_bfd,
f2a9dd69 9364 sym_sec, val, s, error_message);
a4fd1a8e
PB		 9365 if (!myh)
9366 return FALSE;
9367
9368 my_offset = myh->root.u.def.value;
252b5132
RH		 9369 tmp = bfd_get_32 (input_bfd, hit_data);
9370 tmp = tmp & 0xFF000000;
9371
9b485d32 9372 /* Somehow these are both 4 too far, so subtract 8. */
dc810e39
AM		 9373 ret_offset = (s->output_offset
9374 + my_offset
9375 + s->output_section->vma
9376 - (input_section->output_offset
9377 + input_section->output_section->vma
9378 + offset + addend)
9379 - 8);
9a5aca8c 9380
252b5132
RH		 9381 tmp = tmp | ((ret_offset >> 2) & 0x00FFFFFF);
9382
dc810e39 9383 bfd_put_32 (output_bfd, (bfd_vma) tmp, hit_data - input_section->vma);
252b5132 9384
b34976b6 9385 return TRUE;
252b5132
RH		 9386}
9387
a4fd1a8e
PB		 9388/* Populate Arm stub for an exported Thumb function. */
9389
9390static bfd_boolean
9391elf32_arm_to_thumb_export_stub (struct elf_link_hash_entry *h, void * inf)
9392{
9393 struct bfd_link_info * info = (struct bfd_link_info *) inf;
9394 asection * s;
9395 struct elf_link_hash_entry * myh;
9396 struct elf32_arm_link_hash_entry *eh;
9397 struct elf32_arm_link_hash_table * globals;
9398 asection *sec;
9399 bfd_vma val;
f2a9dd69 9400 char *error_message;
a4fd1a8e 9401
906e58ca 9402 eh = elf32_arm_hash_entry (h);
a4fd1a8e
PB		 9403 /* Allocate stubs for exported Thumb functions on v4t. */
9404 if (eh->export_glue == NULL)
9405 return TRUE;
9406
9407 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 9408 BFD_ASSERT (globals != NULL);
9409 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9410
3d4d4302
AM		 9411 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9412 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 9413 BFD_ASSERT (s != NULL);
9414 BFD_ASSERT (s->contents != NULL);
9415 BFD_ASSERT (s->output_section != NULL);
9416
9417 sec = eh->export_glue->root.u.def.section;
0eaedd0e
PB		 9418
9419 BFD_ASSERT (sec->output_section != NULL);
9420
a4fd1a8e
PB		 9421 val = eh->export_glue->root.u.def.value + sec->output_offset
9422 + sec->output_section->vma;
8029a119 9423
a4fd1a8e
PB		 9424 myh = elf32_arm_create_thumb_stub (info, h->root.root.string,
9425 h->root.u.def.section->owner,
f2a9dd69
DJ		 9426 globals->obfd, sec, val, s,
9427 &error_message);
a4fd1a8e
PB		 9428 BFD_ASSERT (myh);
9429 return TRUE;
9430}
9431
845b51d6
PB		 9432/* Populate ARMv4 BX veneers. Returns the absolute adress of the veneer. */
9433
9434static bfd_vma
9435elf32_arm_bx_glue (struct bfd_link_info * info, int reg)
9436{
9437 bfd_byte *p;
9438 bfd_vma glue_addr;
9439 asection *s;
9440 struct elf32_arm_link_hash_table *globals;
9441
9442 globals = elf32_arm_hash_table (info);
845b51d6
PB		 9443 BFD_ASSERT (globals != NULL);
9444 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9445
3d4d4302
AM		 9446 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9447 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 9448 BFD_ASSERT (s != NULL);
9449 BFD_ASSERT (s->contents != NULL);
9450 BFD_ASSERT (s->output_section != NULL);
9451
9452 BFD_ASSERT (globals->bx_glue_offset[reg] & 2);
9453
9454 glue_addr = globals->bx_glue_offset[reg] & ~(bfd_vma)3;
9455
9456 if ((globals->bx_glue_offset[reg] & 1) == 0)
9457 {
9458 p = s->contents + glue_addr;
9459 bfd_put_32 (globals->obfd, armbx1_tst_insn + (reg << 16), p);
9460 bfd_put_32 (globals->obfd, armbx2_moveq_insn + reg, p + 4);
9461 bfd_put_32 (globals->obfd, armbx3_bx_insn + reg, p + 8);
9462 globals->bx_glue_offset[reg] |= 1;
9463 }
9464
9465 return glue_addr + s->output_section->vma + s->output_offset;
9466}
9467
a4fd1a8e
PB		 9468/* Generate Arm stubs for exported Thumb symbols. */
9469static void
906e58ca 9470elf32_arm_begin_write_processing (bfd *abfd ATTRIBUTE_UNUSED,
a4fd1a8e
PB		 9471 struct bfd_link_info *link_info)
9472{
9473 struct elf32_arm_link_hash_table * globals;
9474
8029a119
NC		 9475 if (link_info == NULL)
9476 /* Ignore this if we are not called by the ELF backend linker. */
a4fd1a8e
PB		 9477 return;
9478
9479 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 9480 if (globals == NULL)
9481 return;
9482
84c08195
PB		 9483 /* If blx is available then exported Thumb symbols are OK and there is
9484 nothing to do. */
a4fd1a8e
PB		 9485 if (globals->use_blx)
9486 return;
9487
9488 elf_link_hash_traverse (&globals->root, elf32_arm_to_thumb_export_stub,
9489 link_info);
9490}
9491
47beaa6a
RS		 9492/* Reserve space for COUNT dynamic relocations in relocation selection
9493 SRELOC. */
9494
9495static void
9496elf32_arm_allocate_dynrelocs (struct bfd_link_info *info, asection *sreloc,
9497 bfd_size_type count)
9498{
9499 struct elf32_arm_link_hash_table *htab;
9500
9501 htab = elf32_arm_hash_table (info);
9502 BFD_ASSERT (htab->root.dynamic_sections_created);
9503 if (sreloc == NULL)
9504 abort ();
9505 sreloc->size += RELOC_SIZE (htab) * count;
9506}
9507
34e77a92
RS		 9508/* Reserve space for COUNT R_ARM_IRELATIVE relocations. If the link is
9509 dynamic, the relocations should go in SRELOC, otherwise they should
9510 go in the special .rel.iplt section. */
9511
9512static void
9513elf32_arm_allocate_irelocs (struct bfd_link_info *info, asection *sreloc,
9514 bfd_size_type count)
9515{
9516 struct elf32_arm_link_hash_table *htab;
9517
9518 htab = elf32_arm_hash_table (info);
9519 if (!htab->root.dynamic_sections_created)
9520 htab->root.irelplt->size += RELOC_SIZE (htab) * count;
9521 else
9522 {
9523 BFD_ASSERT (sreloc != NULL);
9524 sreloc->size += RELOC_SIZE (htab) * count;
9525 }
9526}
9527
47beaa6a
RS		 9528/* Add relocation REL to the end of relocation section SRELOC. */
9529
9530static void
9531elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
9532 asection *sreloc, Elf_Internal_Rela *rel)
9533{
9534 bfd_byte *loc;
9535 struct elf32_arm_link_hash_table *htab;
9536
9537 htab = elf32_arm_hash_table (info);
34e77a92
RS		 9538 if (!htab->root.dynamic_sections_created
9539 && ELF32_R_TYPE (rel->r_info) == R_ARM_IRELATIVE)
9540 sreloc = htab->root.irelplt;
47beaa6a
RS		 9541 if (sreloc == NULL)
9542 abort ();
9543 loc = sreloc->contents;
9544 loc += sreloc->reloc_count++ * RELOC_SIZE (htab);
9545 if (sreloc->reloc_count * RELOC_SIZE (htab) > sreloc->size)
9546 abort ();
9547 SWAP_RELOC_OUT (htab) (output_bfd, rel, loc);
9548}
9549
34e77a92
RS		 9550/* Allocate room for a PLT entry described by ROOT_PLT and ARM_PLT.
9551 IS_IPLT_ENTRY says whether the entry belongs to .iplt rather than
9552 to .plt. */
9553
9554static void
9555elf32_arm_allocate_plt_entry (struct bfd_link_info *info,
9556 bfd_boolean is_iplt_entry,
9557 union gotplt_union *root_plt,
9558 struct arm_plt_info *arm_plt)
9559{
9560 struct elf32_arm_link_hash_table *htab;
9561 asection *splt;
9562 asection *sgotplt;
9563
9564 htab = elf32_arm_hash_table (info);
9565
9566 if (is_iplt_entry)
9567 {
9568 splt = htab->root.iplt;
9569 sgotplt = htab->root.igotplt;
9570
99059e56
RM		 9571 /* NaCl uses a special first entry in .iplt too. */
9572 if (htab->nacl_p && splt->size == 0)
9573 splt->size += htab->plt_header_size;
9574
34e77a92
RS		 9575 /* Allocate room for an R_ARM_IRELATIVE relocation in .rel.iplt. */
9576 elf32_arm_allocate_irelocs (info, htab->root.irelplt, 1);
9577 }
9578 else
9579 {
9580 splt = htab->root.splt;
9581 sgotplt = htab->root.sgotplt;
9582
7801f98f
CL		 9583 if (htab->fdpic_p)
9584 {
9585 /* Allocate room for R_ARM_FUNCDESC_VALUE. */
9586 /* For lazy binding, relocations will be put into .rel.plt, in
9587 .rel.got otherwise. */
9588 /* FIXME: today we don't support lazy binding so put it in .rel.got */
9589 if (info->flags & DF_BIND_NOW)
9590 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
9591 else
9592 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
9593 }
9594 else
9595 {
9596 /* Allocate room for an R_JUMP_SLOT relocation in .rel.plt. */
9597 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
9598 }
34e77a92
RS		 9599
9600 /* If this is the first .plt entry, make room for the special
9601 first entry. */
9602 if (splt->size == 0)
9603 splt->size += htab->plt_header_size;
9f19ab6d
WN		 9604
9605 htab->next_tls_desc_index++;
34e77a92
RS		 9606 }
9607
9608 /* Allocate the PLT entry itself, including any leading Thumb stub. */
9609 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9610 splt->size += PLT_THUMB_STUB_SIZE;
9611 root_plt->offset = splt->size;
9612 splt->size += htab->plt_entry_size;
9613
9614 if (!htab->symbian_p)
9615 {
9616 /* We also need to make an entry in the .got.plt section, which
9617 will be placed in the .got section by the linker script. */
9f19ab6d
WN		 9618 if (is_iplt_entry)
9619 arm_plt->got_offset = sgotplt->size;
9620 else
9621 arm_plt->got_offset = sgotplt->size - 8 * htab->num_tls_desc;
7801f98f
CL		 9622 if (htab->fdpic_p)
9623 /* Function descriptor takes 64 bits in GOT. */
4b24dd1a 9624 sgotplt->size += 8;
7801f98f
CL		 9625 else
9626 sgotplt->size += 4;
34e77a92
RS		 9627 }
9628}
9629
b38cadfb
NC		 9630static bfd_vma
9631arm_movw_immediate (bfd_vma value)
9632{
9633 return (value & 0x00000fff) | ((value & 0x0000f000) << 4);
9634}
9635
9636static bfd_vma
9637arm_movt_immediate (bfd_vma value)
9638{
9639 return ((value & 0x0fff0000) >> 16) | ((value & 0xf0000000) >> 12);
9640}
9641
34e77a92
RS		 9642/* Fill in a PLT entry and its associated GOT slot. If DYNINDX == -1,
9643 the entry lives in .iplt and resolves to (*SYM_VALUE)().
9644 Otherwise, DYNINDX is the index of the symbol in the dynamic
9645 symbol table and SYM_VALUE is undefined.
9646
9647 ROOT_PLT points to the offset of the PLT entry from the start of its
9648 section (.iplt or .plt). ARM_PLT points to the symbol's ARM-specific
57460bcf 9649 bookkeeping information.
34e77a92 9650
57460bcf
NC		 9651 Returns FALSE if there was a problem. */
9652
9653static bfd_boolean
34e77a92
RS		 9654elf32_arm_populate_plt_entry (bfd *output_bfd, struct bfd_link_info *info,
9655 union gotplt_union *root_plt,
9656 struct arm_plt_info *arm_plt,
9657 int dynindx, bfd_vma sym_value)
9658{
9659 struct elf32_arm_link_hash_table *htab;
9660 asection *sgot;
9661 asection *splt;
9662 asection *srel;
9663 bfd_byte *loc;
9664 bfd_vma plt_index;
9665 Elf_Internal_Rela rel;
9666 bfd_vma plt_header_size;
9667 bfd_vma got_header_size;
9668
9669 htab = elf32_arm_hash_table (info);
9670
9671 /* Pick the appropriate sections and sizes. */
9672 if (dynindx == -1)
9673 {
9674 splt = htab->root.iplt;
9675 sgot = htab->root.igotplt;
9676 srel = htab->root.irelplt;
9677
9678 /* There are no reserved entries in .igot.plt, and no special
9679 first entry in .iplt. */
9680 got_header_size = 0;
9681 plt_header_size = 0;
9682 }
9683 else
9684 {
9685 splt = htab->root.splt;
9686 sgot = htab->root.sgotplt;
9687 srel = htab->root.srelplt;
9688
9689 got_header_size = get_elf_backend_data (output_bfd)->got_header_size;
9690 plt_header_size = htab->plt_header_size;
9691 }
9692 BFD_ASSERT (splt != NULL && srel != NULL);
9693
9694 /* Fill in the entry in the procedure linkage table. */
9695 if (htab->symbian_p)
9696 {
9697 BFD_ASSERT (dynindx >= 0);
9698 put_arm_insn (htab, output_bfd,
9699 elf32_arm_symbian_plt_entry[0],
9700 splt->contents + root_plt->offset);
9701 bfd_put_32 (output_bfd,
9702 elf32_arm_symbian_plt_entry[1],
9703 splt->contents + root_plt->offset + 4);
9704
9705 /* Fill in the entry in the .rel.plt section. */
9706 rel.r_offset = (splt->output_section->vma
9707 + splt->output_offset
9708 + root_plt->offset + 4);
9709 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_GLOB_DAT);
9710
9711 /* Get the index in the procedure linkage table which
9712 corresponds to this symbol. This is the index of this symbol
9713 in all the symbols for which we are making plt entries. The
9714 first entry in the procedure linkage table is reserved. */
9715 plt_index = ((root_plt->offset - plt_header_size)
9716 / htab->plt_entry_size);
9717 }
9718 else
9719 {
9720 bfd_vma got_offset, got_address, plt_address;
9721 bfd_vma got_displacement, initial_got_entry;
9722 bfd_byte * ptr;
9723
9724 BFD_ASSERT (sgot != NULL);
9725
9726 /* Get the offset into the .(i)got.plt table of the entry that
9727 corresponds to this function. */
9728 got_offset = (arm_plt->got_offset & -2);
9729
9730 /* Get the index in the procedure linkage table which
9731 corresponds to this symbol. This is the index of this symbol
9732 in all the symbols for which we are making plt entries.
9733 After the reserved .got.plt entries, all symbols appear in
9734 the same order as in .plt. */
7801f98f 9735 if (htab->fdpic_p)
4b24dd1a
AM		 9736 /* Function descriptor takes 8 bytes. */
9737 plt_index = (got_offset - got_header_size) / 8;
7801f98f 9738 else
4b24dd1a 9739 plt_index = (got_offset - got_header_size) / 4;
34e77a92
RS		 9740
9741 /* Calculate the address of the GOT entry. */
9742 got_address = (sgot->output_section->vma
9743 + sgot->output_offset
9744 + got_offset);
9745
9746 /* ...and the address of the PLT entry. */
9747 plt_address = (splt->output_section->vma
9748 + splt->output_offset
9749 + root_plt->offset);
9750
9751 ptr = splt->contents + root_plt->offset;
0e1862bb 9752 if (htab->vxworks_p && bfd_link_pic (info))
34e77a92
RS		 9753 {
9754 unsigned int i;
9755 bfd_vma val;
9756
9757 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9758 {
9759 val = elf32_arm_vxworks_shared_plt_entry[i];
9760 if (i == 2)
9761 val |= got_address - sgot->output_section->vma;
9762 if (i == 5)
9763 val |= plt_index * RELOC_SIZE (htab);
9764 if (i == 2 || i == 5)
9765 bfd_put_32 (output_bfd, val, ptr);
9766 else
9767 put_arm_insn (htab, output_bfd, val, ptr);
9768 }
9769 }
9770 else if (htab->vxworks_p)
9771 {
9772 unsigned int i;
9773 bfd_vma val;
9774
9775 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9776 {
9777 val = elf32_arm_vxworks_exec_plt_entry[i];
9778 if (i == 2)
9779 val |= got_address;
9780 if (i == 4)
9781 val |= 0xffffff & -((root_plt->offset + i * 4 + 8) >> 2);
9782 if (i == 5)
9783 val |= plt_index * RELOC_SIZE (htab);
9784 if (i == 2 || i == 5)
9785 bfd_put_32 (output_bfd, val, ptr);
9786 else
9787 put_arm_insn (htab, output_bfd, val, ptr);
9788 }
9789
9790 loc = (htab->srelplt2->contents
9791 + (plt_index * 2 + 1) * RELOC_SIZE (htab));
9792
9793 /* Create the .rela.plt.unloaded R_ARM_ABS32 relocation
9794 referencing the GOT for this PLT entry. */
9795 rel.r_offset = plt_address + 8;
9796 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
9797 rel.r_addend = got_offset;
9798 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9799 loc += RELOC_SIZE (htab);
9800
9801 /* Create the R_ARM_ABS32 relocation referencing the
9802 beginning of the PLT for this GOT entry. */
9803 rel.r_offset = got_address;
9804 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
9805 rel.r_addend = 0;
9806 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9807 }
b38cadfb
NC		 9808 else if (htab->nacl_p)
9809 {
9810 /* Calculate the displacement between the PLT slot and the
9811 common tail that's part of the special initial PLT slot. */
6034aab8 9812 int32_t tail_displacement
b38cadfb
NC		 9813 = ((splt->output_section->vma + splt->output_offset
9814 + ARM_NACL_PLT_TAIL_OFFSET)
9815 - (plt_address + htab->plt_entry_size + 4));
9816 BFD_ASSERT ((tail_displacement & 3) == 0);
9817 tail_displacement >>= 2;
9818
9819 BFD_ASSERT ((tail_displacement & 0xff000000) == 0
9820 || (-tail_displacement & 0xff000000) == 0);
9821
9822 /* Calculate the displacement between the PLT slot and the entry
9823 in the GOT. The offset accounts for the value produced by
9824 adding to pc in the penultimate instruction of the PLT stub. */
6034aab8 9825 got_displacement = (got_address
99059e56 9826 - (plt_address + htab->plt_entry_size));
b38cadfb
NC		 9827
9828 /* NaCl does not support interworking at all. */
9829 BFD_ASSERT (!elf32_arm_plt_needs_thumb_stub_p (info, arm_plt));
9830
9831 put_arm_insn (htab, output_bfd,
9832 elf32_arm_nacl_plt_entry[0]
9833 | arm_movw_immediate (got_displacement),
9834 ptr + 0);
9835 put_arm_insn (htab, output_bfd,
9836 elf32_arm_nacl_plt_entry[1]
9837 | arm_movt_immediate (got_displacement),
9838 ptr + 4);
9839 put_arm_insn (htab, output_bfd,
9840 elf32_arm_nacl_plt_entry[2],
9841 ptr + 8);
9842 put_arm_insn (htab, output_bfd,
9843 elf32_arm_nacl_plt_entry[3]
9844 | (tail_displacement & 0x00ffffff),
9845 ptr + 12);
9846 }
7801f98f
CL		 9847 else if (htab->fdpic_p)
9848 {
59029f57
CL		 9849 const bfd_vma *plt_entry = using_thumb_only(htab)
9850 ? elf32_arm_fdpic_thumb_plt_entry
9851 : elf32_arm_fdpic_plt_entry;
9852
7801f98f
CL		 9853 /* Fill-up Thumb stub if needed. */
9854 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9855 {
9856 put_thumb_insn (htab, output_bfd,
9857 elf32_arm_plt_thumb_stub[0], ptr - 4);
9858 put_thumb_insn (htab, output_bfd,
9859 elf32_arm_plt_thumb_stub[1], ptr - 2);
9860 }
59029f57
CL		 9861 /* As we are using 32 bit instructions even for the Thumb
9862 version, we have to use 'put_arm_insn' instead of
9863 'put_thumb_insn'. */
9864 put_arm_insn(htab, output_bfd, plt_entry[0], ptr + 0);
9865 put_arm_insn(htab, output_bfd, plt_entry[1], ptr + 4);
9866 put_arm_insn(htab, output_bfd, plt_entry[2], ptr + 8);
9867 put_arm_insn(htab, output_bfd, plt_entry[3], ptr + 12);
7801f98f
CL		 9868 bfd_put_32 (output_bfd, got_offset, ptr + 16);
9869
9870 if (!(info->flags & DF_BIND_NOW))
9871 {
9872 /* funcdesc_value_reloc_offset. */
9873 bfd_put_32 (output_bfd,
9874 htab->root.srelplt->reloc_count * RELOC_SIZE (htab),
9875 ptr + 20);
59029f57
CL		 9876 put_arm_insn(htab, output_bfd, plt_entry[6], ptr + 24);
9877 put_arm_insn(htab, output_bfd, plt_entry[7], ptr + 28);
9878 put_arm_insn(htab, output_bfd, plt_entry[8], ptr + 32);
9879 put_arm_insn(htab, output_bfd, plt_entry[9], ptr + 36);
7801f98f
CL		 9880 }
9881 }
57460bcf
NC		 9882 else if (using_thumb_only (htab))
9883 {
eed94f8f 9884 /* PR ld/16017: Generate thumb only PLT entries. */
469a3493 9885 if (!using_thumb2 (htab))
eed94f8f
NC		 9886 {
9887 /* FIXME: We ought to be able to generate thumb-1 PLT
9888 instructions... */
90b6238f 9889 _bfd_error_handler (_("%pB: warning: thumb-1 mode PLT generation not currently supported"),
eed94f8f
NC		 9890 output_bfd);
9891 return FALSE;
9892 }
57460bcf 9893
eed94f8f
NC		 9894 /* Calculate the displacement between the PLT slot and the entry in
9895 the GOT. The 12-byte offset accounts for the value produced by
9896 adding to pc in the 3rd instruction of the PLT stub. */
9897 got_displacement = got_address - (plt_address + 12);
9898
9899 /* As we are using 32 bit instructions we have to use 'put_arm_insn'
9900 instead of 'put_thumb_insn'. */
9901 put_arm_insn (htab, output_bfd,
9902 elf32_thumb2_plt_entry[0]
9903 | ((got_displacement & 0x000000ff) << 16)
9904 | ((got_displacement & 0x00000700) << 20)
9905 | ((got_displacement & 0x00000800) >> 1)
9906 | ((got_displacement & 0x0000f000) >> 12),
9907 ptr + 0);
9908 put_arm_insn (htab, output_bfd,
9909 elf32_thumb2_plt_entry[1]
9910 | ((got_displacement & 0x00ff0000) )
9911 | ((got_displacement & 0x07000000) << 4)
9912 | ((got_displacement & 0x08000000) >> 17)
9913 | ((got_displacement & 0xf0000000) >> 28),
9914 ptr + 4);
9915 put_arm_insn (htab, output_bfd,
9916 elf32_thumb2_plt_entry[2],
9917 ptr + 8);
9918 put_arm_insn (htab, output_bfd,
9919 elf32_thumb2_plt_entry[3],
9920 ptr + 12);
57460bcf 9921 }
34e77a92
RS		 9922 else
9923 {
9924 /* Calculate the displacement between the PLT slot and the
9925 entry in the GOT. The eight-byte offset accounts for the
9926 value produced by adding to pc in the first instruction
9927 of the PLT stub. */
9928 got_displacement = got_address - (plt_address + 8);
9929
34e77a92
RS		 9930 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9931 {
9932 put_thumb_insn (htab, output_bfd,
9933 elf32_arm_plt_thumb_stub[0], ptr - 4);
9934 put_thumb_insn (htab, output_bfd,
9935 elf32_arm_plt_thumb_stub[1], ptr - 2);
9936 }
9937
1db37fe6
YG		 9938 if (!elf32_arm_use_long_plt_entry)
9939 {
9940 BFD_ASSERT ((got_displacement & 0xf0000000) == 0);
9941
9942 put_arm_insn (htab, output_bfd,
9943 elf32_arm_plt_entry_short[0]
9944 | ((got_displacement & 0x0ff00000) >> 20),
9945 ptr + 0);
9946 put_arm_insn (htab, output_bfd,
9947 elf32_arm_plt_entry_short[1]
9948 | ((got_displacement & 0x000ff000) >> 12),
9949 ptr+ 4);
9950 put_arm_insn (htab, output_bfd,
9951 elf32_arm_plt_entry_short[2]
9952 | (got_displacement & 0x00000fff),
9953 ptr + 8);
34e77a92 9954#ifdef FOUR_WORD_PLT
1db37fe6 9955 bfd_put_32 (output_bfd, elf32_arm_plt_entry_short[3], ptr + 12);
34e77a92 9956#endif
1db37fe6
YG		 9957 }
9958 else
9959 {
9960 put_arm_insn (htab, output_bfd,
9961 elf32_arm_plt_entry_long[0]
9962 | ((got_displacement & 0xf0000000) >> 28),
9963 ptr + 0);
9964 put_arm_insn (htab, output_bfd,
9965 elf32_arm_plt_entry_long[1]
9966 | ((got_displacement & 0x0ff00000) >> 20),
9967 ptr + 4);
9968 put_arm_insn (htab, output_bfd,
9969 elf32_arm_plt_entry_long[2]
9970 | ((got_displacement & 0x000ff000) >> 12),
9971 ptr+ 8);
9972 put_arm_insn (htab, output_bfd,
9973 elf32_arm_plt_entry_long[3]
9974 | (got_displacement & 0x00000fff),
9975 ptr + 12);
9976 }
34e77a92
RS		 9977 }
9978
9979 /* Fill in the entry in the .rel(a).(i)plt section. */
9980 rel.r_offset = got_address;
9981 rel.r_addend = 0;
9982 if (dynindx == -1)
9983 {
9984 /* .igot.plt entries use IRELATIVE relocations against SYM_VALUE.
9985 The dynamic linker or static executable then calls SYM_VALUE
9986 to determine the correct run-time value of the .igot.plt entry. */
9987 rel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
9988 initial_got_entry = sym_value;
9989 }
9990 else
9991 {
7801f98f
CL		 9992 /* For FDPIC we will have to resolve a R_ARM_FUNCDESC_VALUE
9993 used by PLT entry. */
9994 if (htab->fdpic_p)
9995 {
9996 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_FUNCDESC_VALUE);
9997 initial_got_entry = 0;
9998 }
9999 else
10000 {
10001 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_JUMP_SLOT);
10002 initial_got_entry = (splt->output_section->vma
10003 + splt->output_offset);
10004 }
34e77a92
RS		 10005 }
10006
10007 /* Fill in the entry in the global offset table. */
10008 bfd_put_32 (output_bfd, initial_got_entry,
10009 sgot->contents + got_offset);
7801f98f
CL		 10010
10011 if (htab->fdpic_p && !(info->flags & DF_BIND_NOW))
10012 {
10013 /* Setup initial funcdesc value. */
10014 /* FIXME: we don't support lazy binding because there is a
10015 race condition between both words getting written and
10016 some other thread attempting to read them. The ARM
10017 architecture does not have an atomic 64 bit load/store
10018 instruction that could be used to prevent it; it is
10019 recommended that threaded FDPIC applications run with the
10020 LD_BIND_NOW environment variable set. */
10021 bfd_put_32(output_bfd, plt_address + 0x18,
10022 sgot->contents + got_offset);
10023 bfd_put_32(output_bfd, -1 /*TODO*/,
10024 sgot->contents + got_offset + 4);
10025 }
34e77a92
RS		 10026 }
10027
aba8c3de
WN		 10028 if (dynindx == -1)
10029 elf32_arm_add_dynreloc (output_bfd, info, srel, &rel);
10030 else
10031 {
7801f98f
CL		 10032 if (htab->fdpic_p)
10033 {
10034 /* For FDPIC we put PLT relocationss into .rel.got when not
10035 lazy binding otherwise we put them in .rel.plt. For now,
10036 we don't support lazy binding so put it in .rel.got. */
10037 if (info->flags & DF_BIND_NOW)
10038 elf32_arm_add_dynreloc(output_bfd, info, htab->root.srelgot, &rel);
10039 else
10040 elf32_arm_add_dynreloc(output_bfd, info, htab->root.srelplt, &rel);
10041 }
10042 else
10043 {
10044 loc = srel->contents + plt_index * RELOC_SIZE (htab);
10045 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
10046 }
aba8c3de 10047 }
57460bcf
NC		 10048
10049 return TRUE;
34e77a92
RS		 10050}
10051
eb043451
PB		 10052/* Some relocations map to different relocations depending on the
10053 target. Return the real relocation. */
8029a119 10054
eb043451
PB		 10055static int
10056arm_real_reloc_type (struct elf32_arm_link_hash_table * globals,
10057 int r_type)
10058{
10059 switch (r_type)
10060 {
10061 case R_ARM_TARGET1:
10062 if (globals->target1_is_rel)
10063 return R_ARM_REL32;
10064 else
10065 return R_ARM_ABS32;
10066
10067 case R_ARM_TARGET2:
10068 return globals->target2_reloc;
10069
10070 default:
10071 return r_type;
10072 }
10073}
eb043451 10074
ba93b8ac
DJ		 10075/* Return the base VMA address which should be subtracted from real addresses
10076 when resolving @dtpoff relocation.
10077 This is PT_TLS segment p_vaddr. */
10078
10079static bfd_vma
10080dtpoff_base (struct bfd_link_info *info)
10081{
10082 /* If tls_sec is NULL, we should have signalled an error already. */
10083 if (elf_hash_table (info)->tls_sec == NULL)
10084 return 0;
10085 return elf_hash_table (info)->tls_sec->vma;
10086}
10087
10088/* Return the relocation value for @tpoff relocation
10089 if STT_TLS virtual address is ADDRESS. */
10090
10091static bfd_vma
10092tpoff (struct bfd_link_info *info, bfd_vma address)
10093{
10094 struct elf_link_hash_table *htab = elf_hash_table (info);
10095 bfd_vma base;
10096
10097 /* If tls_sec is NULL, we should have signalled an error already. */
10098 if (htab->tls_sec == NULL)
10099 return 0;
10100 base = align_power ((bfd_vma) TCB_SIZE, htab->tls_sec->alignment_power);
10101 return address - htab->tls_sec->vma + base;
10102}
10103
00a97672
RS		 10104/* Perform an R_ARM_ABS12 relocation on the field pointed to by DATA.
10105 VALUE is the relocation value. */
10106
10107static bfd_reloc_status_type
10108elf32_arm_abs12_reloc (bfd *abfd, void *data, bfd_vma value)
10109{
10110 if (value > 0xfff)
10111 return bfd_reloc_overflow;
10112
10113 value |= bfd_get_32 (abfd, data) & 0xfffff000;
10114 bfd_put_32 (abfd, value, data);
10115 return bfd_reloc_ok;
10116}
10117
0855e32b
NS		 10118/* Handle TLS relaxations. Relaxing is possible for symbols that use
10119 R_ARM_GOTDESC, R_ARM_{,THM_}TLS_CALL or
10120 R_ARM_{,THM_}TLS_DESCSEQ relocations, during a static link.
10121
10122 Return bfd_reloc_ok if we're done, bfd_reloc_continue if the caller
10123 is to then call final_link_relocate. Return other values in the
62672b10
NS		 10124 case of error.
10125
10126 FIXME:When --emit-relocs is in effect, we'll emit relocs describing
10127 the pre-relaxed code. It would be nice if the relocs were updated
10128 to match the optimization. */
0855e32b 10129
b38cadfb 10130static bfd_reloc_status_type
0855e32b 10131elf32_arm_tls_relax (struct elf32_arm_link_hash_table *globals,
b38cadfb 10132 bfd *input_bfd, asection *input_sec, bfd_byte *contents,
0855e32b
NS		 10133 Elf_Internal_Rela *rel, unsigned long is_local)
10134{
10135 unsigned long insn;
b38cadfb 10136
0855e32b
NS		 10137 switch (ELF32_R_TYPE (rel->r_info))
10138 {
10139 default:
10140 return bfd_reloc_notsupported;
b38cadfb 10141
0855e32b
NS		 10142 case R_ARM_TLS_GOTDESC:
10143 if (is_local)
10144 insn = 0;
10145 else
10146 {
10147 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
10148 if (insn & 1)
10149 insn -= 5; /* THUMB */
10150 else
10151 insn -= 8; /* ARM */
10152 }
10153 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
10154 return bfd_reloc_continue;
10155
10156 case R_ARM_THM_TLS_DESCSEQ:
10157 /* Thumb insn. */
10158 insn = bfd_get_16 (input_bfd, contents + rel->r_offset);
10159 if ((insn & 0xff78) == 0x4478) /* add rx, pc */
10160 {
10161 if (is_local)
10162 /* nop */
10163 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
10164 }
10165 else if ((insn & 0xffc0) == 0x6840) /* ldr rx,[ry,#4] */
10166 {
10167 if (is_local)
10168 /* nop */
10169 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
10170 else
10171 /* ldr rx,[ry] */
10172 bfd_put_16 (input_bfd, insn & 0xf83f, contents + rel->r_offset);
10173 }
10174 else if ((insn & 0xff87) == 0x4780) /* blx rx */
10175 {
10176 if (is_local)
10177 /* nop */
10178 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
10179 else
10180 /* mov r0, rx */
10181 bfd_put_16 (input_bfd, 0x4600 | (insn & 0x78),
10182 contents + rel->r_offset);
10183 }
10184 else
10185 {
10186 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
10187 /* It's a 32 bit instruction, fetch the rest of it for
10188 error generation. */
10189 insn = (insn << 16)
10190 | bfd_get_16 (input_bfd, contents + rel->r_offset + 2);
4eca0228 10191 _bfd_error_handler
695344c0 10192 /* xgettext:c-format */
2dcf00ce 10193 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f
AM		 10194 "unexpected %s instruction '%#lx' in TLS trampoline"),
10195 input_bfd, input_sec, (uint64_t) rel->r_offset,
10196 "Thumb", insn);
0855e32b
NS		 10197 return bfd_reloc_notsupported;
10198 }
10199 break;
b38cadfb 10200
0855e32b
NS		 10201 case R_ARM_TLS_DESCSEQ:
10202 /* arm insn. */
10203 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
10204 if ((insn & 0xffff0ff0) == 0xe08f0000) /* add rx,pc,ry */
10205 {
10206 if (is_local)
10207 /* mov rx, ry */
10208 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xffff),
10209 contents + rel->r_offset);
10210 }
10211 else if ((insn & 0xfff00fff) == 0xe5900004) /* ldr rx,[ry,#4]*/
10212 {
10213 if (is_local)
10214 /* nop */
10215 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
10216 else
10217 /* ldr rx,[ry] */
10218 bfd_put_32 (input_bfd, insn & 0xfffff000,
10219 contents + rel->r_offset);
10220 }
10221 else if ((insn & 0xfffffff0) == 0xe12fff30) /* blx rx */
10222 {
10223 if (is_local)
10224 /* nop */
10225 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
10226 else
10227 /* mov r0, rx */
10228 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xf),
10229 contents + rel->r_offset);
10230 }
10231 else
10232 {
4eca0228 10233 _bfd_error_handler
695344c0 10234 /* xgettext:c-format */
2dcf00ce 10235 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f
AM		 10236 "unexpected %s instruction '%#lx' in TLS trampoline"),
10237 input_bfd, input_sec, (uint64_t) rel->r_offset,
10238 "ARM", insn);
0855e32b
NS		 10239 return bfd_reloc_notsupported;
10240 }
10241 break;
10242
10243 case R_ARM_TLS_CALL:
10244 /* GD->IE relaxation, turn the instruction into 'nop' or
10245 'ldr r0, [pc,r0]' */
10246 insn = is_local ? 0xe1a00000 : 0xe79f0000;
10247 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
10248 break;
b38cadfb 10249
0855e32b 10250 case R_ARM_THM_TLS_CALL:
6a631e86 10251 /* GD->IE relaxation. */
0855e32b
NS		 10252 if (!is_local)
10253 /* add r0,pc; ldr r0, [r0] */
10254 insn = 0x44786800;
60a019a0 10255 else if (using_thumb2 (globals))
0855e32b
NS		 10256 /* nop.w */
10257 insn = 0xf3af8000;
10258 else
10259 /* nop; nop */
10260 insn = 0xbf00bf00;
b38cadfb 10261
0855e32b
NS		 10262 bfd_put_16 (input_bfd, insn >> 16, contents + rel->r_offset);
10263 bfd_put_16 (input_bfd, insn & 0xffff, contents + rel->r_offset + 2);
10264 break;
10265 }
10266 return bfd_reloc_ok;
10267}
10268
4962c51a
MS		 10269/* For a given value of n, calculate the value of G_n as required to
10270 deal with group relocations. We return it in the form of an
10271 encoded constant-and-rotation, together with the final residual. If n is
10272 specified as less than zero, then final_residual is filled with the
10273 input value and no further action is performed. */
10274
10275static bfd_vma
10276calculate_group_reloc_mask (bfd_vma value, int n, bfd_vma *final_residual)
10277{
10278 int current_n;
10279 bfd_vma g_n;
10280 bfd_vma encoded_g_n = 0;
10281 bfd_vma residual = value; /* Also known as Y_n. */
10282
10283 for (current_n = 0; current_n <= n; current_n++)
10284 {
10285 int shift;
10286
10287 /* Calculate which part of the value to mask. */
10288 if (residual == 0)
99059e56 10289 shift = 0;
4962c51a 10290 else
99059e56
RM		 10291 {
10292 int msb;
10293
10294 /* Determine the most significant bit in the residual and
10295 align the resulting value to a 2-bit boundary. */
10296 for (msb = 30; msb >= 0; msb -= 2)
10297 if (residual & (3 << msb))
10298 break;
10299
10300 /* The desired shift is now (msb - 6), or zero, whichever
10301 is the greater. */
10302 shift = msb - 6;
10303 if (shift < 0)
10304 shift = 0;
10305 }
4962c51a
MS		 10306
10307 /* Calculate g_n in 32-bit as well as encoded constant+rotation form. */
10308 g_n = residual & (0xff << shift);
10309 encoded_g_n = (g_n >> shift)
99059e56 10310 | ((g_n <= 0xff ? 0 : (32 - shift) / 2) << 8);
4962c51a
MS		 10311
10312 /* Calculate the residual for the next time around. */
10313 residual &= ~g_n;
10314 }
10315
10316 *final_residual = residual;
10317
10318 return encoded_g_n;
10319}
10320
10321/* Given an ARM instruction, determine whether it is an ADD or a SUB.
10322 Returns 1 if it is an ADD, -1 if it is a SUB, and 0 otherwise. */
906e58ca 10323
4962c51a 10324static int
906e58ca 10325identify_add_or_sub (bfd_vma insn)
4962c51a
MS		 10326{
10327 int opcode = insn & 0x1e00000;
10328
10329 if (opcode == 1 << 23) /* ADD */
10330 return 1;
10331
10332 if (opcode == 1 << 22) /* SUB */
10333 return -1;
10334
10335 return 0;
10336}
10337
252b5132 10338/* Perform a relocation as part of a final link. */
9b485d32 10339
252b5132 10340static bfd_reloc_status_type
07d6d2b8
AM		 10341elf32_arm_final_link_relocate (reloc_howto_type * howto,
10342 bfd * input_bfd,
10343 bfd * output_bfd,
10344 asection * input_section,
10345 bfd_byte * contents,
10346 Elf_Internal_Rela * rel,
10347 bfd_vma value,
10348 struct bfd_link_info * info,
10349 asection * sym_sec,
10350 const char * sym_name,
10351 unsigned char st_type,
10352 enum arm_st_branch_type branch_type,
0945cdfd 10353 struct elf_link_hash_entry * h,
07d6d2b8
AM		 10354 bfd_boolean * unresolved_reloc_p,
10355 char ** error_message)
10356{
10357 unsigned long r_type = howto->type;
10358 unsigned long r_symndx;
10359 bfd_byte * hit_data = contents + rel->r_offset;
10360 bfd_vma * local_got_offsets;
10361 bfd_vma * local_tlsdesc_gotents;
10362 asection * sgot;
10363 asection * splt;
10364 asection * sreloc = NULL;
10365 asection * srelgot;
10366 bfd_vma addend;
10367 bfd_signed_vma signed_addend;
10368 unsigned char dynreloc_st_type;
10369 bfd_vma dynreloc_value;
ba96a88f 10370 struct elf32_arm_link_hash_table * globals;
34e77a92 10371 struct elf32_arm_link_hash_entry *eh;
07d6d2b8
AM		 10372 union gotplt_union *root_plt;
10373 struct arm_plt_info *arm_plt;
10374 bfd_vma plt_offset;
10375 bfd_vma gotplt_offset;
10376 bfd_boolean has_iplt_entry;
10377 bfd_boolean resolved_to_zero;
f21f3fe0 10378
9c504268 10379 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 10380 if (globals == NULL)
10381 return bfd_reloc_notsupported;
9c504268 10382
0ffa91dd 10383 BFD_ASSERT (is_arm_elf (input_bfd));
47aeb64c 10384 BFD_ASSERT (howto != NULL);
0ffa91dd
NC		 10385
10386 /* Some relocation types map to different relocations depending on the
9c504268 10387 target. We pick the right one here. */
eb043451 10388 r_type = arm_real_reloc_type (globals, r_type);
0855e32b
NS		 10389
10390 /* It is possible to have linker relaxations on some TLS access
10391 models. Update our information here. */
10392 r_type = elf32_arm_tls_transition (info, r_type, h);
10393
eb043451
PB		 10394 if (r_type != howto->type)
10395 howto = elf32_arm_howto_from_type (r_type);
9c504268 10396
34e77a92 10397 eh = (struct elf32_arm_link_hash_entry *) h;
362d30a1 10398 sgot = globals->root.sgot;
252b5132 10399 local_got_offsets = elf_local_got_offsets (input_bfd);
0855e32b
NS		 10400 local_tlsdesc_gotents = elf32_arm_local_tlsdesc_gotent (input_bfd);
10401
34e77a92
RS		 10402 if (globals->root.dynamic_sections_created)
10403 srelgot = globals->root.srelgot;
10404 else
10405 srelgot = NULL;
10406
252b5132
RH		 10407 r_symndx = ELF32_R_SYM (rel->r_info);
10408
4e7fd91e 10409 if (globals->use_rel)
ba96a88f 10410 {
4e7fd91e
PB		 10411 addend = bfd_get_32 (input_bfd, hit_data) & howto->src_mask;
10412
10413 if (addend & ((howto->src_mask + 1) >> 1))
10414 {
10415 signed_addend = -1;
10416 signed_addend &= ~ howto->src_mask;
10417 signed_addend |= addend;
10418 }
10419 else
10420 signed_addend = addend;
ba96a88f
NC		 10421 }
10422 else
4e7fd91e 10423 addend = signed_addend = rel->r_addend;
f21f3fe0 10424
39f21624
NC		 10425 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
10426 are resolving a function call relocation. */
10427 if (using_thumb_only (globals)
10428 && (r_type == R_ARM_THM_CALL
10429 || r_type == R_ARM_THM_JUMP24)
10430 && branch_type == ST_BRANCH_TO_ARM)
10431 branch_type = ST_BRANCH_TO_THUMB;
10432
34e77a92
RS		 10433 /* Record the symbol information that should be used in dynamic
10434 relocations. */
10435 dynreloc_st_type = st_type;
10436 dynreloc_value = value;
10437 if (branch_type == ST_BRANCH_TO_THUMB)
10438 dynreloc_value |= 1;
10439
10440 /* Find out whether the symbol has a PLT. Set ST_VALUE, BRANCH_TYPE and
10441 VALUE appropriately for relocations that we resolve at link time. */
10442 has_iplt_entry = FALSE;
4ba2ef8f
TP		 10443 if (elf32_arm_get_plt_info (input_bfd, globals, eh, r_symndx, &root_plt,
10444 &arm_plt)
34e77a92
RS		 10445 && root_plt->offset != (bfd_vma) -1)
10446 {
10447 plt_offset = root_plt->offset;
10448 gotplt_offset = arm_plt->got_offset;
10449
10450 if (h == NULL || eh->is_iplt)
10451 {
10452 has_iplt_entry = TRUE;
10453 splt = globals->root.iplt;
10454
10455 /* Populate .iplt entries here, because not all of them will
10456 be seen by finish_dynamic_symbol. The lower bit is set if
10457 we have already populated the entry. */
10458 if (plt_offset & 1)
10459 plt_offset--;
10460 else
10461 {
57460bcf
NC		 10462 if (elf32_arm_populate_plt_entry (output_bfd, info, root_plt, arm_plt,
10463 -1, dynreloc_value))
10464 root_plt->offset |= 1;
10465 else
10466 return bfd_reloc_notsupported;
34e77a92
RS		 10467 }
10468
10469 /* Static relocations always resolve to the .iplt entry. */
10470 st_type = STT_FUNC;
10471 value = (splt->output_section->vma
10472 + splt->output_offset
10473 + plt_offset);
10474 branch_type = ST_BRANCH_TO_ARM;
10475
10476 /* If there are non-call relocations that resolve to the .iplt
10477 entry, then all dynamic ones must too. */
10478 if (arm_plt->noncall_refcount != 0)
10479 {
10480 dynreloc_st_type = st_type;
10481 dynreloc_value = value;
10482 }
10483 }
10484 else
10485 /* We populate the .plt entry in finish_dynamic_symbol. */
10486 splt = globals->root.splt;
10487 }
10488 else
10489 {
10490 splt = NULL;
10491 plt_offset = (bfd_vma) -1;
10492 gotplt_offset = (bfd_vma) -1;
10493 }
10494
95b03e4a
L		 10495 resolved_to_zero = (h != NULL
10496 && UNDEFWEAK_NO_DYNAMIC_RELOC (info, h));
10497
252b5132
RH		 10498 switch (r_type)
10499 {
10500 case R_ARM_NONE:
28a094c2
DJ		 10501 /* We don't need to find a value for this symbol. It's just a
10502 marker. */
10503 *unresolved_reloc_p = FALSE;
252b5132
RH		 10504 return bfd_reloc_ok;
10505
00a97672
RS		 10506 case R_ARM_ABS12:
10507 if (!globals->vxworks_p)
10508 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
1a0670f3 10509 /* Fall through. */
00a97672 10510
252b5132
RH		 10511 case R_ARM_PC24:
10512 case R_ARM_ABS32:
bb224fc3 10513 case R_ARM_ABS32_NOI:
252b5132 10514 case R_ARM_REL32:
bb224fc3 10515 case R_ARM_REL32_NOI:
5b5bb741
PB		 10516 case R_ARM_CALL:
10517 case R_ARM_JUMP24:
dfc5f959 10518 case R_ARM_XPC25:
eb043451 10519 case R_ARM_PREL31:
7359ea65 10520 case R_ARM_PLT32:
7359ea65
DJ		 10521 /* Handle relocations which should use the PLT entry. ABS32/REL32
10522 will use the symbol's value, which may point to a PLT entry, but we
10523 don't need to handle that here. If we created a PLT entry, all
5fa9e92f
CL		 10524 branches in this object should go to it, except if the PLT is too
10525 far away, in which case a long branch stub should be inserted. */
bb224fc3 10526 if ((r_type != R_ARM_ABS32 && r_type != R_ARM_REL32
99059e56 10527 && r_type != R_ARM_ABS32_NOI && r_type != R_ARM_REL32_NOI
155d87d7
CL		 10528 && r_type != R_ARM_CALL
10529 && r_type != R_ARM_JUMP24
10530 && r_type != R_ARM_PLT32)
34e77a92 10531 && plt_offset != (bfd_vma) -1)
7359ea65 10532 {
34e77a92
RS		 10533 /* If we've created a .plt section, and assigned a PLT entry
10534 to this function, it must either be a STT_GNU_IFUNC reference
10535 or not be known to bind locally. In other cases, we should
10536 have cleared the PLT entry by now. */
10537 BFD_ASSERT (has_iplt_entry || !SYMBOL_CALLS_LOCAL (info, h));
7359ea65
DJ		 10538
10539 value = (splt->output_section->vma
10540 + splt->output_offset
34e77a92 10541 + plt_offset);
0945cdfd 10542 *unresolved_reloc_p = FALSE;
7359ea65
DJ		 10543 return _bfd_final_link_relocate (howto, input_bfd, input_section,
10544 contents, rel->r_offset, value,
00a97672 10545 rel->r_addend);
7359ea65
DJ		 10546 }
10547
67687978
PB		 10548 /* When generating a shared object or relocatable executable, these
10549 relocations are copied into the output file to be resolved at
10550 run time. */
0e1862bb 10551 if ((bfd_link_pic (info)
e8b09b87
CL		 10552 || globals->root.is_relocatable_executable
10553 || globals->fdpic_p)
7359ea65 10554 && (input_section->flags & SEC_ALLOC)
4dfe6ac6 10555 && !(globals->vxworks_p
3348747a
NS		 10556 && strcmp (input_section->output_section->name,
10557 ".tls_vars") == 0)
bb224fc3 10558 && ((r_type != R_ARM_REL32 && r_type != R_ARM_REL32_NOI)
ee06dc07 10559 || !SYMBOL_CALLS_LOCAL (info, h))
ca6b5f82
AM		 10560 && !(input_bfd == globals->stub_bfd
10561 && strstr (input_section->name, STUB_SUFFIX))
7359ea65 10562 && (h == NULL
95b03e4a
L		 10563 || (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
10564 && !resolved_to_zero)
7359ea65
DJ		 10565 || h->root.type != bfd_link_hash_undefweak)
10566 && r_type != R_ARM_PC24
5b5bb741
PB		 10567 && r_type != R_ARM_CALL
10568 && r_type != R_ARM_JUMP24
ee06dc07 10569 && r_type != R_ARM_PREL31
7359ea65 10570 && r_type != R_ARM_PLT32)
252b5132 10571 {
947216bf 10572 Elf_Internal_Rela outrel;
b34976b6 10573 bfd_boolean skip, relocate;
e8b09b87 10574 int isrofixup = 0;
f21f3fe0 10575
52db4ec2
JW		 10576 if ((r_type == R_ARM_REL32 || r_type == R_ARM_REL32_NOI)
10577 && !h->def_regular)
10578 {
10579 char *v = _("shared object");
10580
0e1862bb 10581 if (bfd_link_executable (info))
52db4ec2
JW		 10582 v = _("PIE executable");
10583
4eca0228 10584 _bfd_error_handler
871b3ab2 10585 (_("%pB: relocation %s against external or undefined symbol `%s'"
52db4ec2
JW		 10586 " can not be used when making a %s; recompile with -fPIC"), input_bfd,
10587 elf32_arm_howto_table_1[r_type].name, h->root.root.string, v);
10588 return bfd_reloc_notsupported;
10589 }
10590
0945cdfd
DJ		 10591 *unresolved_reloc_p = FALSE;
10592
34e77a92 10593 if (sreloc == NULL && globals->root.dynamic_sections_created)
252b5132 10594 {
83bac4b0
NC		 10595 sreloc = _bfd_elf_get_dynamic_reloc_section (input_bfd, input_section,
10596 ! globals->use_rel);
f21f3fe0 10597
83bac4b0 10598 if (sreloc == NULL)
252b5132 10599 return bfd_reloc_notsupported;
252b5132 10600 }
f21f3fe0 10601
b34976b6
AM		 10602 skip = FALSE;
10603 relocate = FALSE;
f21f3fe0 10604
00a97672 10605 outrel.r_addend = addend;
c629eae0
JJ		 10606 outrel.r_offset =
10607 _bfd_elf_section_offset (output_bfd, info, input_section,
10608 rel->r_offset);
10609 if (outrel.r_offset == (bfd_vma) -1)
b34976b6 10610 skip = TRUE;
0bb2d96a 10611 else if (outrel.r_offset == (bfd_vma) -2)
b34976b6 10612 skip = TRUE, relocate = TRUE;
252b5132
RH		 10613 outrel.r_offset += (input_section->output_section->vma
10614 + input_section->output_offset);
f21f3fe0 10615
252b5132 10616 if (skip)
0bb2d96a 10617 memset (&outrel, 0, sizeof outrel);
5e681ec4
PB		 10618 else if (h != NULL
10619 && h->dynindx != -1
0e1862bb 10620 && (!bfd_link_pic (info)
1dcb9720
JW		 10621 || !(bfd_link_pie (info)
10622 || SYMBOLIC_BIND (info, h))
f5385ebf 10623 || !h->def_regular))
5e681ec4 10624 outrel.r_info = ELF32_R_INFO (h->dynindx, r_type);
252b5132
RH		 10625 else
10626 {
a16385dc
MM		 10627 int symbol;
10628
5e681ec4 10629 /* This symbol is local, or marked to become local. */
e8b09b87
CL		 10630 BFD_ASSERT (r_type == R_ARM_ABS32 || r_type == R_ARM_ABS32_NOI
10631 || (globals->fdpic_p && !bfd_link_pic(info)));
a16385dc 10632 if (globals->symbian_p)
6366ff1e 10633 {
74541ad4
AM		 10634 asection *osec;
10635
6366ff1e
MM		 10636 /* On Symbian OS, the data segment and text segement
10637 can be relocated independently. Therefore, we
10638 must indicate the segment to which this
10639 relocation is relative. The BPABI allows us to
10640 use any symbol in the right segment; we just use
10641 the section symbol as it is convenient. (We
10642 cannot use the symbol given by "h" directly as it
74541ad4
AM		 10643 will not appear in the dynamic symbol table.)
10644
10645 Note that the dynamic linker ignores the section
10646 symbol value, so we don't subtract osec->vma
10647 from the emitted reloc addend. */
10dbd1f3 10648 if (sym_sec)
74541ad4 10649 osec = sym_sec->output_section;
10dbd1f3 10650 else
74541ad4
AM		 10651 osec = input_section->output_section;
10652 symbol = elf_section_data (osec)->dynindx;
10653 if (symbol == 0)
10654 {
10655 struct elf_link_hash_table *htab = elf_hash_table (info);
10656
10657 if ((osec->flags & SEC_READONLY) == 0
10658 && htab->data_index_section != NULL)
10659 osec = htab->data_index_section;
10660 else
10661 osec = htab->text_index_section;
10662 symbol = elf_section_data (osec)->dynindx;
10663 }
6366ff1e
MM		 10664 BFD_ASSERT (symbol != 0);
10665 }
a16385dc
MM		 10666 else
10667 /* On SVR4-ish systems, the dynamic loader cannot
10668 relocate the text and data segments independently,
10669 so the symbol does not matter. */
10670 symbol = 0;
34e77a92
RS		 10671 if (dynreloc_st_type == STT_GNU_IFUNC)
10672 /* We have an STT_GNU_IFUNC symbol that doesn't resolve
10673 to the .iplt entry. Instead, every non-call reference
10674 must use an R_ARM_IRELATIVE relocation to obtain the
10675 correct run-time address. */
10676 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_IRELATIVE);
e8b09b87
CL		 10677 else if (globals->fdpic_p && !bfd_link_pic(info))
10678 isrofixup = 1;
34e77a92
RS		 10679 else
10680 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_RELATIVE);
00a97672
RS		 10681 if (globals->use_rel)
10682 relocate = TRUE;
10683 else
34e77a92 10684 outrel.r_addend += dynreloc_value;
252b5132 10685 }
f21f3fe0 10686
e8b09b87
CL		 10687 if (isrofixup)
10688 arm_elf_add_rofixup(output_bfd, globals->srofixup, outrel.r_offset);
10689 else
10690 elf32_arm_add_dynreloc (output_bfd, info, sreloc, &outrel);
9a5aca8c 10691
f21f3fe0 10692 /* If this reloc is against an external symbol, we do not want to
252b5132 10693 fiddle with the addend. Otherwise, we need to include the symbol
9b485d32 10694 value so that it becomes an addend for the dynamic reloc. */
252b5132
RH		 10695 if (! relocate)
10696 return bfd_reloc_ok;
9a5aca8c 10697
f21f3fe0 10698 return _bfd_final_link_relocate (howto, input_bfd, input_section,
34e77a92
RS		 10699 contents, rel->r_offset,
10700 dynreloc_value, (bfd_vma) 0);
252b5132
RH		 10701 }
10702 else switch (r_type)
10703 {
00a97672
RS		 10704 case R_ARM_ABS12:
10705 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
10706
dfc5f959 10707 case R_ARM_XPC25: /* Arm BLX instruction. */
5b5bb741
PB		 10708 case R_ARM_CALL:
10709 case R_ARM_JUMP24:
8029a119 10710 case R_ARM_PC24: /* Arm B/BL instruction. */
7359ea65 10711 case R_ARM_PLT32:
906e58ca 10712 {
906e58ca
NC		 10713 struct elf32_arm_stub_hash_entry *stub_entry = NULL;
10714
dfc5f959 10715 if (r_type == R_ARM_XPC25)
252b5132 10716 {
dfc5f959
NC		 10717 /* Check for Arm calling Arm function. */
10718 /* FIXME: Should we translate the instruction into a BL
10719 instruction instead ? */
35fc36a8 10720 if (branch_type != ST_BRANCH_TO_THUMB)
4eca0228 10721 _bfd_error_handler
90b6238f
AM		 10722 (_("\%pB: warning: %s BLX instruction targets"
10723 " %s function '%s'"),
10724 input_bfd, "ARM",
10725 "ARM", h ? h->root.root.string : "(local)");
dfc5f959 10726 }
155d87d7 10727 else if (r_type == R_ARM_PC24)
dfc5f959
NC		 10728 {
10729 /* Check for Arm calling Thumb function. */
35fc36a8 10730 if (branch_type == ST_BRANCH_TO_THUMB)
dfc5f959 10731 {
f2a9dd69
DJ		 10732 if (elf32_arm_to_thumb_stub (info, sym_name, input_bfd,
10733 output_bfd, input_section,
10734 hit_data, sym_sec, rel->r_offset,
10735 signed_addend, value,
10736 error_message))
10737 return bfd_reloc_ok;
10738 else
10739 return bfd_reloc_dangerous;
dfc5f959 10740 }
252b5132 10741 }
ba96a88f 10742
906e58ca 10743 /* Check if a stub has to be inserted because the
8029a119 10744 destination is too far or we are changing mode. */
155d87d7
CL		 10745 if ( r_type == R_ARM_CALL
10746 || r_type == R_ARM_JUMP24
10747 || r_type == R_ARM_PLT32)
906e58ca 10748 {
fe33d2fa
CL		 10749 enum elf32_arm_stub_type stub_type = arm_stub_none;
10750 struct elf32_arm_link_hash_entry *hash;
10751
10752 hash = (struct elf32_arm_link_hash_entry *) h;
10753 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 10754 st_type, &branch_type,
10755 hash, value, sym_sec,
fe33d2fa 10756 input_bfd, sym_name);
5fa9e92f 10757
fe33d2fa 10758 if (stub_type != arm_stub_none)
906e58ca
NC		 10759 {
10760 /* The target is out of reach, so redirect the
10761 branch to the local stub for this function. */
906e58ca
NC		 10762 stub_entry = elf32_arm_get_stub_entry (input_section,
10763 sym_sec, h,
fe33d2fa
CL		 10764 rel, globals,
10765 stub_type);
9cd3e4e5
NC		 10766 {
10767 if (stub_entry != NULL)
10768 value = (stub_entry->stub_offset
10769 + stub_entry->stub_sec->output_offset
10770 + stub_entry->stub_sec->output_section->vma);
10771
10772 if (plt_offset != (bfd_vma) -1)
10773 *unresolved_reloc_p = FALSE;
10774 }
906e58ca 10775 }
fe33d2fa
CL		 10776 else
10777 {
10778 /* If the call goes through a PLT entry, make sure to
10779 check distance to the right destination address. */
34e77a92 10780 if (plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 10781 {
10782 value = (splt->output_section->vma
10783 + splt->output_offset
34e77a92 10784 + plt_offset);
fe33d2fa
CL		 10785 *unresolved_reloc_p = FALSE;
10786 /* The PLT entry is in ARM mode, regardless of the
10787 target function. */
35fc36a8 10788 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 10789 }
10790 }
906e58ca
NC		 10791 }
10792
dea514f5
PB		 10793 /* The ARM ELF ABI says that this reloc is computed as: S - P + A
10794 where:
10795 S is the address of the symbol in the relocation.
10796 P is address of the instruction being relocated.
10797 A is the addend (extracted from the instruction) in bytes.
10798
10799 S is held in 'value'.
10800 P is the base address of the section containing the
10801 instruction plus the offset of the reloc into that
10802 section, ie:
10803 (input_section->output_section->vma +
10804 input_section->output_offset +
10805 rel->r_offset).
10806 A is the addend, converted into bytes, ie:
10807 (signed_addend * 4)
10808
10809 Note: None of these operations have knowledge of the pipeline
10810 size of the processor, thus it is up to the assembler to
10811 encode this information into the addend. */
10812 value -= (input_section->output_section->vma
10813 + input_section->output_offset);
10814 value -= rel->r_offset;
4e7fd91e
PB		 10815 if (globals->use_rel)
10816 value += (signed_addend << howto->size);
10817 else
10818 /* RELA addends do not have to be adjusted by howto->size. */
10819 value += signed_addend;
23080146 10820
dcb5e6e6
NC		 10821 signed_addend = value;
10822 signed_addend >>= howto->rightshift;
9a5aca8c 10823
5ab79981 10824 /* A branch to an undefined weak symbol is turned into a jump to
ffcb4889 10825 the next instruction unless a PLT entry will be created.
77b4f08f 10826 Do the same for local undefined symbols (but not for STN_UNDEF).
cd1dac3d
DG		 10827 The jump to the next instruction is optimized as a NOP depending
10828 on the architecture. */
ffcb4889 10829 if (h ? (h->root.type == bfd_link_hash_undefweak
34e77a92 10830 && plt_offset == (bfd_vma) -1)
77b4f08f 10831 : r_symndx != STN_UNDEF && bfd_is_und_section (sym_sec))
5ab79981 10832 {
cd1dac3d
DG		 10833 value = (bfd_get_32 (input_bfd, hit_data) & 0xf0000000);
10834
10835 if (arch_has_arm_nop (globals))
10836 value |= 0x0320f000;
10837 else
10838 value |= 0x01a00000; /* Using pre-UAL nop: mov r0, r0. */
5ab79981
PB		 10839 }
10840 else
59f2c4e7 10841 {
9b485d32 10842 /* Perform a signed range check. */
dcb5e6e6 10843 if ( signed_addend > ((bfd_signed_vma) (howto->dst_mask >> 1))
59f2c4e7
NC		 10844 || signed_addend < - ((bfd_signed_vma) ((howto->dst_mask + 1) >> 1)))
10845 return bfd_reloc_overflow;
9a5aca8c 10846
5ab79981 10847 addend = (value & 2);
39b41c9c 10848
5ab79981
PB		 10849 value = (signed_addend & howto->dst_mask)
10850 | (bfd_get_32 (input_bfd, hit_data) & (~ howto->dst_mask));
39b41c9c 10851
5ab79981
PB		 10852 if (r_type == R_ARM_CALL)
10853 {
155d87d7 10854 /* Set the H bit in the BLX instruction. */
35fc36a8 10855 if (branch_type == ST_BRANCH_TO_THUMB)
155d87d7
CL		 10856 {
10857 if (addend)
10858 value |= (1 << 24);
10859 else
10860 value &= ~(bfd_vma)(1 << 24);
10861 }
10862
5ab79981 10863 /* Select the correct instruction (BL or BLX). */
906e58ca 10864 /* Only if we are not handling a BL to a stub. In this
8029a119 10865 case, mode switching is performed by the stub. */
35fc36a8 10866 if (branch_type == ST_BRANCH_TO_THUMB && !stub_entry)
5ab79981 10867 value |= (1 << 28);
63e1a0fc 10868 else if (stub_entry || branch_type != ST_BRANCH_UNKNOWN)
5ab79981
PB		 10869 {
10870 value &= ~(bfd_vma)(1 << 28);
10871 value |= (1 << 24);
10872 }
39b41c9c
PB		 10873 }
10874 }
906e58ca 10875 }
252b5132 10876 break;
f21f3fe0 10877
252b5132
RH		 10878 case R_ARM_ABS32:
10879 value += addend;
35fc36a8 10880 if (branch_type == ST_BRANCH_TO_THUMB)
252b5132
RH		 10881 value |= 1;
10882 break;
f21f3fe0 10883
bb224fc3
MS		 10884 case R_ARM_ABS32_NOI:
10885 value += addend;
10886 break;
10887
252b5132 10888 case R_ARM_REL32:
a8bc6c78 10889 value += addend;
35fc36a8 10890 if (branch_type == ST_BRANCH_TO_THUMB)
a8bc6c78 10891 value |= 1;
252b5132 10892 value -= (input_section->output_section->vma
62efb346 10893 + input_section->output_offset + rel->r_offset);
252b5132 10894 break;
eb043451 10895
bb224fc3
MS		 10896 case R_ARM_REL32_NOI:
10897 value += addend;
10898 value -= (input_section->output_section->vma
10899 + input_section->output_offset + rel->r_offset);
10900 break;
10901
eb043451
PB		 10902 case R_ARM_PREL31:
10903 value -= (input_section->output_section->vma
10904 + input_section->output_offset + rel->r_offset);
10905 value += signed_addend;
10906 if (! h || h->root.type != bfd_link_hash_undefweak)
10907 {
8029a119 10908 /* Check for overflow. */
eb043451
PB		 10909 if ((value ^ (value >> 1)) & (1 << 30))
10910 return bfd_reloc_overflow;
10911 }
10912 value &= 0x7fffffff;
10913 value |= (bfd_get_32 (input_bfd, hit_data) & 0x80000000);
35fc36a8 10914 if (branch_type == ST_BRANCH_TO_THUMB)
eb043451
PB		 10915 value |= 1;
10916 break;
252b5132 10917 }
f21f3fe0 10918
252b5132
RH		 10919 bfd_put_32 (input_bfd, value, hit_data);
10920 return bfd_reloc_ok;
10921
10922 case R_ARM_ABS8:
fd0fd00c
MJ		 10923 /* PR 16202: Refectch the addend using the correct size. */
10924 if (globals->use_rel)
10925 addend = bfd_get_8 (input_bfd, hit_data);
252b5132 10926 value += addend;
4e67d4ca
DG		 10927
10928 /* There is no way to tell whether the user intended to use a signed or
10929 unsigned addend. When checking for overflow we accept either,
10930 as specified by the AAELF. */
10931 if ((long) value > 0xff || (long) value < -0x80)
252b5132
RH		 10932 return bfd_reloc_overflow;
10933
10934 bfd_put_8 (input_bfd, value, hit_data);
10935 return bfd_reloc_ok;
10936
10937 case R_ARM_ABS16:
fd0fd00c
MJ		 10938 /* PR 16202: Refectch the addend using the correct size. */
10939 if (globals->use_rel)
10940 addend = bfd_get_16 (input_bfd, hit_data);
252b5132
RH		 10941 value += addend;
10942
4e67d4ca
DG		 10943 /* See comment for R_ARM_ABS8. */
10944 if ((long) value > 0xffff || (long) value < -0x8000)
252b5132
RH		 10945 return bfd_reloc_overflow;
10946
10947 bfd_put_16 (input_bfd, value, hit_data);
10948 return bfd_reloc_ok;
10949
252b5132 10950 case R_ARM_THM_ABS5:
9b485d32 10951 /* Support ldr and str instructions for the thumb. */
4e7fd91e
PB		 10952 if (globals->use_rel)
10953 {
10954 /* Need to refetch addend. */
10955 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
10956 /* ??? Need to determine shift amount from operand size. */
10957 addend >>= howto->rightshift;
10958 }
252b5132
RH		 10959 value += addend;
10960
10961 /* ??? Isn't value unsigned? */
10962 if ((long) value > 0x1f || (long) value < -0x10)
10963 return bfd_reloc_overflow;
10964
10965 /* ??? Value needs to be properly shifted into place first. */
10966 value |= bfd_get_16 (input_bfd, hit_data) & 0xf83f;
10967 bfd_put_16 (input_bfd, value, hit_data);
10968 return bfd_reloc_ok;
10969
2cab6cc3
MS		 10970 case R_ARM_THM_ALU_PREL_11_0:
10971 /* Corresponds to: addw.w reg, pc, #offset (and similarly for subw). */
10972 {
10973 bfd_vma insn;
10974 bfd_signed_vma relocation;
10975
10976 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 10977 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 10978
99059e56
RM		 10979 if (globals->use_rel)
10980 {
10981 signed_addend = (insn & 0xff) | ((insn & 0x7000) >> 4)
10982 | ((insn & (1 << 26)) >> 15);
10983 if (insn & 0xf00000)
10984 signed_addend = -signed_addend;
10985 }
2cab6cc3
MS		 10986
10987 relocation = value + signed_addend;
79f08007 10988 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10989 + input_section->output_offset
10990 + rel->r_offset);
2cab6cc3 10991
8c65b54f
CS		 10992 /* PR 21523: Use an absolute value. The user of this reloc will
10993 have already selected an ADD or SUB insn appropriately. */
453f8e1e 10994 value = llabs (relocation);
2cab6cc3 10995
99059e56
RM		 10996 if (value >= 0x1000)
10997 return bfd_reloc_overflow;
2cab6cc3 10998
e645cf40
AG		 10999 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
11000 if (branch_type == ST_BRANCH_TO_THUMB)
11001 value |= 1;
11002
2cab6cc3 11003 insn = (insn & 0xfb0f8f00) | (value & 0xff)
99059e56
RM		 11004 | ((value & 0x700) << 4)
11005 | ((value & 0x800) << 15);
11006 if (relocation < 0)
11007 insn |= 0xa00000;
2cab6cc3
MS		 11008
11009 bfd_put_16 (input_bfd, insn >> 16, hit_data);
11010 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
11011
99059e56 11012 return bfd_reloc_ok;
2cab6cc3
MS		 11013 }
11014
e1ec24c6
NC		 11015 case R_ARM_THM_PC8:
11016 /* PR 10073: This reloc is not generated by the GNU toolchain,
11017 but it is supported for compatibility with third party libraries
11018 generated by other compilers, specifically the ARM/IAR. */
11019 {
11020 bfd_vma insn;
11021 bfd_signed_vma relocation;
11022
11023 insn = bfd_get_16 (input_bfd, hit_data);
11024
99059e56 11025 if (globals->use_rel)
79f08007 11026 addend = ((((insn & 0x00ff) << 2) + 4) & 0x3ff) -4;
e1ec24c6
NC		 11027
11028 relocation = value + addend;
79f08007 11029 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 11030 + input_section->output_offset
11031 + rel->r_offset);
e1ec24c6 11032
b6518b38 11033 value = relocation;
e1ec24c6
NC		 11034
11035 /* We do not check for overflow of this reloc. Although strictly
11036 speaking this is incorrect, it appears to be necessary in order
11037 to work with IAR generated relocs. Since GCC and GAS do not
11038 generate R_ARM_THM_PC8 relocs, the lack of a check should not be
11039 a problem for them. */
11040 value &= 0x3fc;
11041
11042 insn = (insn & 0xff00) | (value >> 2);
11043
11044 bfd_put_16 (input_bfd, insn, hit_data);
11045
99059e56 11046 return bfd_reloc_ok;
e1ec24c6
NC		 11047 }
11048
2cab6cc3
MS		 11049 case R_ARM_THM_PC12:
11050 /* Corresponds to: ldr.w reg, [pc, #offset]. */
11051 {
11052 bfd_vma insn;
11053 bfd_signed_vma relocation;
11054
11055 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 11056 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 11057
99059e56
RM		 11058 if (globals->use_rel)
11059 {
11060 signed_addend = insn & 0xfff;
11061 if (!(insn & (1 << 23)))
11062 signed_addend = -signed_addend;
11063 }
2cab6cc3
MS		 11064
11065 relocation = value + signed_addend;
79f08007 11066 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 11067 + input_section->output_offset
11068 + rel->r_offset);
2cab6cc3 11069
b6518b38 11070 value = relocation;
2cab6cc3 11071
99059e56
RM		 11072 if (value >= 0x1000)
11073 return bfd_reloc_overflow;
2cab6cc3
MS		 11074
11075 insn = (insn & 0xff7ff000) | value;
99059e56
RM		 11076 if (relocation >= 0)
11077 insn |= (1 << 23);
2cab6cc3
MS		 11078
11079 bfd_put_16 (input_bfd, insn >> 16, hit_data);
11080 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
11081
99059e56 11082 return bfd_reloc_ok;
2cab6cc3
MS		 11083 }
11084
dfc5f959 11085 case R_ARM_THM_XPC22:
c19d1205 11086 case R_ARM_THM_CALL:
bd97cb95 11087 case R_ARM_THM_JUMP24:
dfc5f959 11088 /* Thumb BL (branch long instruction). */
252b5132 11089 {
b34976b6 11090 bfd_vma relocation;
99059e56 11091 bfd_vma reloc_sign;
b34976b6
AM		 11092 bfd_boolean overflow = FALSE;
11093 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
11094 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
e95de063
MS		 11095 bfd_signed_vma reloc_signed_max;
11096 bfd_signed_vma reloc_signed_min;
b34976b6 11097 bfd_vma check;
252b5132 11098 bfd_signed_vma signed_check;
e95de063 11099 int bitsize;
cd1dac3d 11100 const int thumb2 = using_thumb2 (globals);
5e866f5a 11101 const int thumb2_bl = using_thumb2_bl (globals);
252b5132 11102
5ab79981 11103 /* A branch to an undefined weak symbol is turned into a jump to
cd1dac3d
DG		 11104 the next instruction unless a PLT entry will be created.
11105 The jump to the next instruction is optimized as a NOP.W for
11106 Thumb-2 enabled architectures. */
19540007 11107 if (h && h->root.type == bfd_link_hash_undefweak
34e77a92 11108 && plt_offset == (bfd_vma) -1)
5ab79981 11109 {
60a019a0 11110 if (thumb2)
cd1dac3d
DG		 11111 {
11112 bfd_put_16 (input_bfd, 0xf3af, hit_data);
11113 bfd_put_16 (input_bfd, 0x8000, hit_data + 2);
11114 }
11115 else
11116 {
11117 bfd_put_16 (input_bfd, 0xe000, hit_data);
11118 bfd_put_16 (input_bfd, 0xbf00, hit_data + 2);
11119 }
5ab79981
PB		 11120 return bfd_reloc_ok;
11121 }
11122
e95de063 11123 /* Fetch the addend. We use the Thumb-2 encoding (backwards compatible
99059e56 11124 with Thumb-1) involving the J1 and J2 bits. */
4e7fd91e
PB		 11125 if (globals->use_rel)
11126 {
99059e56
RM		 11127 bfd_vma s = (upper_insn & (1 << 10)) >> 10;
11128 bfd_vma upper = upper_insn & 0x3ff;
11129 bfd_vma lower = lower_insn & 0x7ff;
e95de063
MS		 11130 bfd_vma j1 = (lower_insn & (1 << 13)) >> 13;
11131 bfd_vma j2 = (lower_insn & (1 << 11)) >> 11;
99059e56
RM		 11132 bfd_vma i1 = j1 ^ s ? 0 : 1;
11133 bfd_vma i2 = j2 ^ s ? 0 : 1;
e95de063 11134
99059e56
RM		 11135 addend = (i1 << 23) | (i2 << 22) | (upper << 12) | (lower << 1);
11136 /* Sign extend. */
11137 addend = (addend | ((s ? 0 : 1) << 24)) - (1 << 24);
e95de063 11138
4e7fd91e
PB		 11139 signed_addend = addend;
11140 }
cb1afa5c 11141
dfc5f959
NC		 11142 if (r_type == R_ARM_THM_XPC22)
11143 {
11144 /* Check for Thumb to Thumb call. */
11145 /* FIXME: Should we translate the instruction into a BL
11146 instruction instead ? */
35fc36a8 11147 if (branch_type == ST_BRANCH_TO_THUMB)
4eca0228 11148 _bfd_error_handler
90b6238f
AM		 11149 (_("%pB: warning: %s BLX instruction targets"
11150 " %s function '%s'"),
11151 input_bfd, "Thumb",
11152 "Thumb", h ? h->root.root.string : "(local)");
dfc5f959
NC		 11153 }
11154 else
252b5132 11155 {
dfc5f959
NC		 11156 /* If it is not a call to Thumb, assume call to Arm.
11157 If it is a call relative to a section name, then it is not a
b7693d02
DJ		 11158 function call at all, but rather a long jump. Calls through
11159 the PLT do not require stubs. */
34e77a92 11160 if (branch_type == ST_BRANCH_TO_ARM && plt_offset == (bfd_vma) -1)
dfc5f959 11161 {
bd97cb95 11162 if (globals->use_blx && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 11163 {
11164 /* Convert BL to BLX. */
11165 lower_insn = (lower_insn & ~0x1000) | 0x0800;
11166 }
155d87d7
CL		 11167 else if (( r_type != R_ARM_THM_CALL)
11168 && (r_type != R_ARM_THM_JUMP24))
8029a119
NC		 11169 {
11170 if (elf32_thumb_to_arm_stub
11171 (info, sym_name, input_bfd, output_bfd, input_section,
11172 hit_data, sym_sec, rel->r_offset, signed_addend, value,
11173 error_message))
11174 return bfd_reloc_ok;
11175 else
11176 return bfd_reloc_dangerous;
11177 }
da5938a2 11178 }
35fc36a8
RS		 11179 else if (branch_type == ST_BRANCH_TO_THUMB
11180 && globals->use_blx
bd97cb95 11181 && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 11182 {
11183 /* Make sure this is a BL. */
11184 lower_insn |= 0x1800;
11185 }
252b5132 11186 }
f21f3fe0 11187
fe33d2fa 11188 enum elf32_arm_stub_type stub_type = arm_stub_none;
155d87d7 11189 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24)
906e58ca
NC		 11190 {
11191 /* Check if a stub has to be inserted because the destination
8029a119 11192 is too far. */
fe33d2fa
CL		 11193 struct elf32_arm_stub_hash_entry *stub_entry;
11194 struct elf32_arm_link_hash_entry *hash;
11195
11196 hash = (struct elf32_arm_link_hash_entry *) h;
11197
11198 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 11199 st_type, &branch_type,
11200 hash, value, sym_sec,
fe33d2fa
CL		 11201 input_bfd, sym_name);
11202
11203 if (stub_type != arm_stub_none)
906e58ca
NC		 11204 {
11205 /* The target is out of reach or we are changing modes, so
11206 redirect the branch to the local stub for this
11207 function. */
11208 stub_entry = elf32_arm_get_stub_entry (input_section,
11209 sym_sec, h,
fe33d2fa
CL		 11210 rel, globals,
11211 stub_type);
906e58ca 11212 if (stub_entry != NULL)
9cd3e4e5
NC		 11213 {
11214 value = (stub_entry->stub_offset
11215 + stub_entry->stub_sec->output_offset
11216 + stub_entry->stub_sec->output_section->vma);
11217
11218 if (plt_offset != (bfd_vma) -1)
11219 *unresolved_reloc_p = FALSE;
11220 }
906e58ca 11221
f4ac8484 11222 /* If this call becomes a call to Arm, force BLX. */
155d87d7 11223 if (globals->use_blx && (r_type == R_ARM_THM_CALL))
f4ac8484
DJ		 11224 {
11225 if ((stub_entry
11226 && !arm_stub_is_thumb (stub_entry->stub_type))
35fc36a8 11227 || branch_type != ST_BRANCH_TO_THUMB)
f4ac8484
DJ		 11228 lower_insn = (lower_insn & ~0x1000) | 0x0800;
11229 }
906e58ca
NC		 11230 }
11231 }
11232
fe33d2fa 11233 /* Handle calls via the PLT. */
34e77a92 11234 if (stub_type == arm_stub_none && plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 11235 {
11236 value = (splt->output_section->vma
11237 + splt->output_offset
34e77a92 11238 + plt_offset);
fe33d2fa 11239
eed94f8f
NC		 11240 if (globals->use_blx
11241 && r_type == R_ARM_THM_CALL
11242 && ! using_thumb_only (globals))
fe33d2fa
CL		 11243 {
11244 /* If the Thumb BLX instruction is available, convert
11245 the BL to a BLX instruction to call the ARM-mode
11246 PLT entry. */
11247 lower_insn = (lower_insn & ~0x1000) | 0x0800;
35fc36a8 11248 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 11249 }
11250 else
11251 {
eed94f8f
NC		 11252 if (! using_thumb_only (globals))
11253 /* Target the Thumb stub before the ARM PLT entry. */
11254 value -= PLT_THUMB_STUB_SIZE;
35fc36a8 11255 branch_type = ST_BRANCH_TO_THUMB;
fe33d2fa
CL		 11256 }
11257 *unresolved_reloc_p = FALSE;
11258 }
11259
ba96a88f 11260 relocation = value + signed_addend;
f21f3fe0 11261
252b5132 11262 relocation -= (input_section->output_section->vma
ba96a88f
NC		 11263 + input_section->output_offset
11264 + rel->r_offset);
9a5aca8c 11265
252b5132
RH		 11266 check = relocation >> howto->rightshift;
11267
11268 /* If this is a signed value, the rightshift just dropped
11269 leading 1 bits (assuming twos complement). */
11270 if ((bfd_signed_vma) relocation >= 0)
11271 signed_check = check;
11272 else
11273 signed_check = check | ~((bfd_vma) -1 >> howto->rightshift);
11274
e95de063
MS		 11275 /* Calculate the permissable maximum and minimum values for
11276 this relocation according to whether we're relocating for
11277 Thumb-2 or not. */
11278 bitsize = howto->bitsize;
5e866f5a 11279 if (!thumb2_bl)
e95de063 11280 bitsize -= 2;
f6ebfac0 11281 reloc_signed_max = (1 << (bitsize - 1)) - 1;
e95de063
MS		 11282 reloc_signed_min = ~reloc_signed_max;
11283
252b5132 11284 /* Assumes two's complement. */
ba96a88f 11285 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
b34976b6 11286 overflow = TRUE;
252b5132 11287
bd97cb95 11288 if ((lower_insn & 0x5000) == 0x4000)
c62e1cc3
NC		 11289 /* For a BLX instruction, make sure that the relocation is rounded up
11290 to a word boundary. This follows the semantics of the instruction
11291 which specifies that bit 1 of the target address will come from bit
11292 1 of the base address. */
11293 relocation = (relocation + 2) & ~ 3;
cb1afa5c 11294
e95de063
MS		 11295 /* Put RELOCATION back into the insn. Assumes two's complement.
11296 We use the Thumb-2 encoding, which is safe even if dealing with
11297 a Thumb-1 instruction by virtue of our overflow check above. */
99059e56 11298 reloc_sign = (signed_check < 0) ? 1 : 0;
e95de063 11299 upper_insn = (upper_insn & ~(bfd_vma) 0x7ff)
99059e56
RM		 11300 | ((relocation >> 12) & 0x3ff)
11301 | (reloc_sign << 10);
906e58ca 11302 lower_insn = (lower_insn & ~(bfd_vma) 0x2fff)
99059e56
RM		 11303 | (((!((relocation >> 23) & 1)) ^ reloc_sign) << 13)
11304 | (((!((relocation >> 22) & 1)) ^ reloc_sign) << 11)
11305 | ((relocation >> 1) & 0x7ff);
c62e1cc3 11306
252b5132
RH		 11307 /* Put the relocated value back in the object file: */
11308 bfd_put_16 (input_bfd, upper_insn, hit_data);
11309 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11310
11311 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
11312 }
11313 break;
11314
c19d1205
ZW		 11315 case R_ARM_THM_JUMP19:
11316 /* Thumb32 conditional branch instruction. */
11317 {
11318 bfd_vma relocation;
11319 bfd_boolean overflow = FALSE;
11320 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
11321 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
a00a1f35
MS		 11322 bfd_signed_vma reloc_signed_max = 0xffffe;
11323 bfd_signed_vma reloc_signed_min = -0x100000;
c19d1205 11324 bfd_signed_vma signed_check;
07d6d2b8 11325 enum elf32_arm_stub_type stub_type = arm_stub_none;
c5423981
TG		 11326 struct elf32_arm_stub_hash_entry *stub_entry;
11327 struct elf32_arm_link_hash_entry *hash;
c19d1205
ZW		 11328
11329 /* Need to refetch the addend, reconstruct the top three bits,
11330 and squish the two 11 bit pieces together. */
11331 if (globals->use_rel)
11332 {
11333 bfd_vma S = (upper_insn & 0x0400) >> 10;
a00a1f35 11334 bfd_vma upper = (upper_insn & 0x003f);
c19d1205
ZW		 11335 bfd_vma J1 = (lower_insn & 0x2000) >> 13;
11336 bfd_vma J2 = (lower_insn & 0x0800) >> 11;
11337 bfd_vma lower = (lower_insn & 0x07ff);
11338
a00a1f35
MS		 11339 upper |= J1 << 6;
11340 upper |= J2 << 7;
11341 upper |= (!S) << 8;
c19d1205
ZW		 11342 upper -= 0x0100; /* Sign extend. */
11343
11344 addend = (upper << 12) | (lower << 1);
11345 signed_addend = addend;
11346 }
11347
bd97cb95 11348 /* Handle calls via the PLT. */
34e77a92 11349 if (plt_offset != (bfd_vma) -1)
bd97cb95
DJ		 11350 {
11351 value = (splt->output_section->vma
11352 + splt->output_offset
34e77a92 11353 + plt_offset);
bd97cb95
DJ		 11354 /* Target the Thumb stub before the ARM PLT entry. */
11355 value -= PLT_THUMB_STUB_SIZE;
11356 *unresolved_reloc_p = FALSE;
11357 }
11358
c5423981
TG		 11359 hash = (struct elf32_arm_link_hash_entry *)h;
11360
11361 stub_type = arm_type_of_stub (info, input_section, rel,
07d6d2b8
AM		 11362 st_type, &branch_type,
11363 hash, value, sym_sec,
11364 input_bfd, sym_name);
c5423981
TG		 11365 if (stub_type != arm_stub_none)
11366 {
11367 stub_entry = elf32_arm_get_stub_entry (input_section,
07d6d2b8
AM		 11368 sym_sec, h,
11369 rel, globals,
11370 stub_type);
c5423981
TG		 11371 if (stub_entry != NULL)
11372 {
07d6d2b8
AM		 11373 value = (stub_entry->stub_offset
11374 + stub_entry->stub_sec->output_offset
11375 + stub_entry->stub_sec->output_section->vma);
c5423981
TG		 11376 }
11377 }
c19d1205 11378
99059e56 11379 relocation = value + signed_addend;
c19d1205
ZW		 11380 relocation -= (input_section->output_section->vma
11381 + input_section->output_offset
11382 + rel->r_offset);
a00a1f35 11383 signed_check = (bfd_signed_vma) relocation;
c19d1205 11384
c19d1205
ZW		 11385 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
11386 overflow = TRUE;
11387
11388 /* Put RELOCATION back into the insn. */
11389 {
11390 bfd_vma S = (relocation & 0x00100000) >> 20;
11391 bfd_vma J2 = (relocation & 0x00080000) >> 19;
11392 bfd_vma J1 = (relocation & 0x00040000) >> 18;
11393 bfd_vma hi = (relocation & 0x0003f000) >> 12;
11394 bfd_vma lo = (relocation & 0x00000ffe) >> 1;
11395
a00a1f35 11396 upper_insn = (upper_insn & 0xfbc0) | (S << 10) | hi;
c19d1205
ZW		 11397 lower_insn = (lower_insn & 0xd000) | (J1 << 13) | (J2 << 11) | lo;
11398 }
11399
11400 /* Put the relocated value back in the object file: */
11401 bfd_put_16 (input_bfd, upper_insn, hit_data);
11402 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11403
11404 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
11405 }
11406
11407 case R_ARM_THM_JUMP11:
11408 case R_ARM_THM_JUMP8:
11409 case R_ARM_THM_JUMP6:
51c5503b
NC		 11410 /* Thumb B (branch) instruction). */
11411 {
6cf9e9fe 11412 bfd_signed_vma relocation;
51c5503b
NC		 11413 bfd_signed_vma reloc_signed_max = (1 << (howto->bitsize - 1)) - 1;
11414 bfd_signed_vma reloc_signed_min = ~ reloc_signed_max;
51c5503b
NC		 11415 bfd_signed_vma signed_check;
11416
c19d1205
ZW		 11417 /* CZB cannot jump backward. */
11418 if (r_type == R_ARM_THM_JUMP6)
11419 reloc_signed_min = 0;
11420
4e7fd91e 11421 if (globals->use_rel)
6cf9e9fe 11422 {
4e7fd91e
PB		 11423 /* Need to refetch addend. */
11424 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
11425 if (addend & ((howto->src_mask + 1) >> 1))
11426 {
11427 signed_addend = -1;
11428 signed_addend &= ~ howto->src_mask;
11429 signed_addend |= addend;
11430 }
11431 else
11432 signed_addend = addend;
11433 /* The value in the insn has been right shifted. We need to
11434 undo this, so that we can perform the address calculation
11435 in terms of bytes. */
11436 signed_addend <<= howto->rightshift;
6cf9e9fe 11437 }
6cf9e9fe 11438 relocation = value + signed_addend;
51c5503b
NC		 11439
11440 relocation -= (input_section->output_section->vma
11441 + input_section->output_offset
11442 + rel->r_offset);
11443
6cf9e9fe
NC		 11444 relocation >>= howto->rightshift;
11445 signed_check = relocation;
c19d1205
ZW		 11446
11447 if (r_type == R_ARM_THM_JUMP6)
11448 relocation = ((relocation & 0x0020) << 4) | ((relocation & 0x001f) << 3);
11449 else
11450 relocation &= howto->dst_mask;
51c5503b 11451 relocation |= (bfd_get_16 (input_bfd, hit_data) & (~ howto->dst_mask));
cedb70c5 11452
51c5503b
NC		 11453 bfd_put_16 (input_bfd, relocation, hit_data);
11454
11455 /* Assumes two's complement. */
11456 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
11457 return bfd_reloc_overflow;
11458
11459 return bfd_reloc_ok;
11460 }
cedb70c5 11461
8375c36b
PB		 11462 case R_ARM_ALU_PCREL7_0:
11463 case R_ARM_ALU_PCREL15_8:
11464 case R_ARM_ALU_PCREL23_15:
11465 {
11466 bfd_vma insn;
11467 bfd_vma relocation;
11468
11469 insn = bfd_get_32 (input_bfd, hit_data);
4e7fd91e
PB		 11470 if (globals->use_rel)
11471 {
11472 /* Extract the addend. */
11473 addend = (insn & 0xff) << ((insn & 0xf00) >> 7);
11474 signed_addend = addend;
11475 }
8375c36b
PB		 11476 relocation = value + signed_addend;
11477
11478 relocation -= (input_section->output_section->vma
11479 + input_section->output_offset
11480 + rel->r_offset);
11481 insn = (insn & ~0xfff)
11482 | ((howto->bitpos << 7) & 0xf00)
11483 | ((relocation >> howto->bitpos) & 0xff);
11484 bfd_put_32 (input_bfd, value, hit_data);
11485 }
11486 return bfd_reloc_ok;
11487
252b5132
RH		 11488 case R_ARM_GNU_VTINHERIT:
11489 case R_ARM_GNU_VTENTRY:
11490 return bfd_reloc_ok;
11491
c19d1205 11492 case R_ARM_GOTOFF32:
252b5132 11493 /* Relocation is relative to the start of the
99059e56 11494 global offset table. */
252b5132
RH		 11495
11496 BFD_ASSERT (sgot != NULL);
11497 if (sgot == NULL)
99059e56 11498 return bfd_reloc_notsupported;
9a5aca8c 11499
cedb70c5 11500 /* If we are addressing a Thumb function, we need to adjust the
ee29b9fb
RE		 11501 address by one, so that attempts to call the function pointer will
11502 correctly interpret it as Thumb code. */
35fc36a8 11503 if (branch_type == ST_BRANCH_TO_THUMB)
ee29b9fb
RE		 11504 value += 1;
11505
252b5132 11506 /* Note that sgot->output_offset is not involved in this
99059e56
RM		 11507 calculation. We always want the start of .got. If we
11508 define _GLOBAL_OFFSET_TABLE in a different way, as is
11509 permitted by the ABI, we might have to change this
11510 calculation. */
252b5132 11511 value -= sgot->output_section->vma;
f21f3fe0 11512 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11513 contents, rel->r_offset, value,
00a97672 11514 rel->r_addend);
252b5132
RH		 11515
11516 case R_ARM_GOTPC:
a7c10850 11517 /* Use global offset table as symbol value. */
252b5132 11518 BFD_ASSERT (sgot != NULL);
f21f3fe0 11519
252b5132 11520 if (sgot == NULL)
99059e56 11521 return bfd_reloc_notsupported;
252b5132 11522
0945cdfd 11523 *unresolved_reloc_p = FALSE;
252b5132 11524 value = sgot->output_section->vma;
f21f3fe0 11525 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11526 contents, rel->r_offset, value,
00a97672 11527 rel->r_addend);
f21f3fe0 11528
252b5132 11529 case R_ARM_GOT32:
eb043451 11530 case R_ARM_GOT_PREL:
252b5132 11531 /* Relocation is to the entry for this symbol in the
99059e56 11532 global offset table. */
252b5132
RH		 11533 if (sgot == NULL)
11534 return bfd_reloc_notsupported;
f21f3fe0 11535
34e77a92
RS		 11536 if (dynreloc_st_type == STT_GNU_IFUNC
11537 && plt_offset != (bfd_vma) -1
11538 && (h == NULL || SYMBOL_REFERENCES_LOCAL (info, h)))
11539 {
11540 /* We have a relocation against a locally-binding STT_GNU_IFUNC
11541 symbol, and the relocation resolves directly to the runtime
11542 target rather than to the .iplt entry. This means that any
11543 .got entry would be the same value as the .igot.plt entry,
11544 so there's no point creating both. */
11545 sgot = globals->root.igotplt;
11546 value = sgot->output_offset + gotplt_offset;
11547 }
11548 else if (h != NULL)
252b5132
RH		 11549 {
11550 bfd_vma off;
f21f3fe0 11551
252b5132
RH		 11552 off = h->got.offset;
11553 BFD_ASSERT (off != (bfd_vma) -1);
b436d854 11554 if ((off & 1) != 0)
252b5132 11555 {
b436d854
RS		 11556 /* We have already processsed one GOT relocation against
11557 this symbol. */
11558 off &= ~1;
11559 if (globals->root.dynamic_sections_created
11560 && !SYMBOL_REFERENCES_LOCAL (info, h))
11561 *unresolved_reloc_p = FALSE;
11562 }
11563 else
11564 {
11565 Elf_Internal_Rela outrel;
e8b09b87 11566 int isrofixup = 0;
b436d854 11567
e8b09b87
CL		 11568 if (((h->dynindx != -1) || globals->fdpic_p)
11569 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 11570 {
11571 /* If the symbol doesn't resolve locally in a static
11572 object, we have an undefined reference. If the
11573 symbol doesn't resolve locally in a dynamic object,
11574 it should be resolved by the dynamic linker. */
11575 if (globals->root.dynamic_sections_created)
11576 {
11577 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_GLOB_DAT);
11578 *unresolved_reloc_p = FALSE;
11579 }
11580 else
11581 outrel.r_info = 0;
11582 outrel.r_addend = 0;
11583 }
252b5132
RH		 11584 else
11585 {
34e77a92 11586 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 11587 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
5025eb7c 11588 else if (bfd_link_pic (info)
7f026732 11589 && !UNDEFWEAK_NO_DYNAMIC_RELOC (info, h))
99059e56
RM		 11590 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
11591 else
2376f038
EB		 11592 {
11593 outrel.r_info = 0;
11594 if (globals->fdpic_p)
11595 isrofixup = 1;
11596 }
34e77a92 11597 outrel.r_addend = dynreloc_value;
b436d854 11598 }
ee29b9fb 11599
b436d854
RS		 11600 /* The GOT entry is initialized to zero by default.
11601 See if we should install a different value. */
11602 if (outrel.r_addend != 0
2376f038 11603 && (globals->use_rel || outrel.r_info == 0))
b436d854
RS		 11604 {
11605 bfd_put_32 (output_bfd, outrel.r_addend,
11606 sgot->contents + off);
11607 outrel.r_addend = 0;
252b5132 11608 }
f21f3fe0 11609
2376f038
EB		 11610 if (isrofixup)
11611 arm_elf_add_rofixup (output_bfd,
11612 elf32_arm_hash_table(info)->srofixup,
11613 sgot->output_section->vma
11614 + sgot->output_offset + off);
11615
11616 else if (outrel.r_info != 0)
b436d854
RS		 11617 {
11618 outrel.r_offset = (sgot->output_section->vma
11619 + sgot->output_offset
11620 + off);
11621 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
11622 }
2376f038 11623
b436d854
RS		 11624 h->got.offset |= 1;
11625 }
252b5132
RH		 11626 value = sgot->output_offset + off;
11627 }
11628 else
11629 {
11630 bfd_vma off;
f21f3fe0 11631
5025eb7c
AO		 11632 BFD_ASSERT (local_got_offsets != NULL
11633 && local_got_offsets[r_symndx] != (bfd_vma) -1);
f21f3fe0 11634
252b5132 11635 off = local_got_offsets[r_symndx];
f21f3fe0 11636
252b5132
RH		 11637 /* The offset must always be a multiple of 4. We use the
11638 least significant bit to record whether we have already
9b485d32 11639 generated the necessary reloc. */
252b5132
RH		 11640 if ((off & 1) != 0)
11641 off &= ~1;
11642 else
11643 {
2376f038
EB		 11644 Elf_Internal_Rela outrel;
11645 int isrofixup = 0;
f21f3fe0 11646
2376f038
EB		 11647 if (dynreloc_st_type == STT_GNU_IFUNC)
11648 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
11649 else if (bfd_link_pic (info))
11650 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
11651 else
252b5132 11652 {
2376f038
EB		 11653 outrel.r_info = 0;
11654 if (globals->fdpic_p)
11655 isrofixup = 1;
11656 }
11657
11658 /* The GOT entry is initialized to zero by default.
11659 See if we should install a different value. */
11660 if (globals->use_rel || outrel.r_info == 0)
11661 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + off);
11662
11663 if (isrofixup)
11664 arm_elf_add_rofixup (output_bfd,
11665 globals->srofixup,
11666 sgot->output_section->vma
11667 + sgot->output_offset + off);
f21f3fe0 11668
2376f038
EB		 11669 else if (outrel.r_info != 0)
11670 {
34e77a92 11671 outrel.r_addend = addend + dynreloc_value;
252b5132 11672 outrel.r_offset = (sgot->output_section->vma
f21f3fe0 11673 + sgot->output_offset
252b5132 11674 + off);
47beaa6a 11675 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
252b5132 11676 }
f21f3fe0 11677
252b5132
RH		 11678 local_got_offsets[r_symndx] |= 1;
11679 }
f21f3fe0 11680
252b5132
RH		 11681 value = sgot->output_offset + off;
11682 }
eb043451
PB		 11683 if (r_type != R_ARM_GOT32)
11684 value += sgot->output_section->vma;
9a5aca8c 11685
f21f3fe0 11686 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11687 contents, rel->r_offset, value,
00a97672 11688 rel->r_addend);
f21f3fe0 11689
ba93b8ac
DJ		 11690 case R_ARM_TLS_LDO32:
11691 value = value - dtpoff_base (info);
11692
11693 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 11694 contents, rel->r_offset, value,
11695 rel->r_addend);
ba93b8ac
DJ		 11696
11697 case R_ARM_TLS_LDM32:
5c5a4843 11698 case R_ARM_TLS_LDM32_FDPIC:
ba93b8ac
DJ		 11699 {
11700 bfd_vma off;
11701
362d30a1 11702 if (sgot == NULL)
ba93b8ac
DJ		 11703 abort ();
11704
11705 off = globals->tls_ldm_got.offset;
11706
11707 if ((off & 1) != 0)
11708 off &= ~1;
11709 else
11710 {
11711 /* If we don't know the module number, create a relocation
11712 for it. */
9cb09e33 11713 if (bfd_link_dll (info))
ba93b8ac
DJ		 11714 {
11715 Elf_Internal_Rela outrel;
ba93b8ac 11716
362d30a1 11717 if (srelgot == NULL)
ba93b8ac
DJ		 11718 abort ();
11719
00a97672 11720 outrel.r_addend = 0;
362d30a1
RS		 11721 outrel.r_offset = (sgot->output_section->vma
11722 + sgot->output_offset + off);
ba93b8ac
DJ		 11723 outrel.r_info = ELF32_R_INFO (0, R_ARM_TLS_DTPMOD32);
11724
00a97672
RS		 11725 if (globals->use_rel)
11726 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11727 sgot->contents + off);
ba93b8ac 11728
47beaa6a 11729 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11730 }
11731 else
362d30a1 11732 bfd_put_32 (output_bfd, 1, sgot->contents + off);
ba93b8ac
DJ		 11733
11734 globals->tls_ldm_got.offset |= 1;
11735 }
11736
5c5a4843 11737 if (r_type == R_ARM_TLS_LDM32_FDPIC)
e8b09b87
CL		 11738 {
11739 bfd_put_32(output_bfd,
11740 globals->root.sgot->output_offset + off,
11741 contents + rel->r_offset);
11742
11743 return bfd_reloc_ok;
11744 }
11745 else
11746 {
11747 value = sgot->output_section->vma + sgot->output_offset + off
11748 - (input_section->output_section->vma
11749 + input_section->output_offset + rel->r_offset);
ba93b8ac 11750
e8b09b87
CL		 11751 return _bfd_final_link_relocate (howto, input_bfd, input_section,
11752 contents, rel->r_offset, value,
11753 rel->r_addend);
11754 }
ba93b8ac
DJ		 11755 }
11756
0855e32b
NS		 11757 case R_ARM_TLS_CALL:
11758 case R_ARM_THM_TLS_CALL:
ba93b8ac 11759 case R_ARM_TLS_GD32:
5c5a4843 11760 case R_ARM_TLS_GD32_FDPIC:
ba93b8ac 11761 case R_ARM_TLS_IE32:
5c5a4843 11762 case R_ARM_TLS_IE32_FDPIC:
0855e32b
NS		 11763 case R_ARM_TLS_GOTDESC:
11764 case R_ARM_TLS_DESCSEQ:
11765 case R_ARM_THM_TLS_DESCSEQ:
ba93b8ac 11766 {
0855e32b
NS		 11767 bfd_vma off, offplt;
11768 int indx = 0;
ba93b8ac
DJ		 11769 char tls_type;
11770
0855e32b 11771 BFD_ASSERT (sgot != NULL);
ba93b8ac 11772
ba93b8ac
DJ		 11773 if (h != NULL)
11774 {
11775 bfd_boolean dyn;
11776 dyn = globals->root.dynamic_sections_created;
0e1862bb
L		 11777 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
11778 bfd_link_pic (info),
11779 h)
11780 && (!bfd_link_pic (info)
ba93b8ac
DJ		 11781 || !SYMBOL_REFERENCES_LOCAL (info, h)))
11782 {
11783 *unresolved_reloc_p = FALSE;
11784 indx = h->dynindx;
11785 }
11786 off = h->got.offset;
0855e32b 11787 offplt = elf32_arm_hash_entry (h)->tlsdesc_got;
ba93b8ac
DJ		 11788 tls_type = ((struct elf32_arm_link_hash_entry *) h)->tls_type;
11789 }
11790 else
11791 {
0855e32b 11792 BFD_ASSERT (local_got_offsets != NULL);
ba93b8ac 11793 off = local_got_offsets[r_symndx];
0855e32b 11794 offplt = local_tlsdesc_gotents[r_symndx];
ba93b8ac
DJ		 11795 tls_type = elf32_arm_local_got_tls_type (input_bfd)[r_symndx];
11796 }
11797
0855e32b 11798 /* Linker relaxations happens from one of the
b38cadfb 11799 R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
0855e32b 11800 if (ELF32_R_TYPE(rel->r_info) != r_type)
b38cadfb 11801 tls_type = GOT_TLS_IE;
0855e32b
NS		 11802
11803 BFD_ASSERT (tls_type != GOT_UNKNOWN);
ba93b8ac
DJ		 11804
11805 if ((off & 1) != 0)
11806 off &= ~1;
11807 else
11808 {
11809 bfd_boolean need_relocs = FALSE;
11810 Elf_Internal_Rela outrel;
ba93b8ac
DJ		 11811 int cur_off = off;
11812
11813 /* The GOT entries have not been initialized yet. Do it
11814 now, and emit any relocations. If both an IE GOT and a
11815 GD GOT are necessary, we emit the GD first. */
11816
9cb09e33 11817 if ((bfd_link_dll (info) || indx != 0)
ba93b8ac 11818 && (h == NULL
95b03e4a
L		 11819 || (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
11820 && !resolved_to_zero)
ba93b8ac
DJ		 11821 || h->root.type != bfd_link_hash_undefweak))
11822 {
11823 need_relocs = TRUE;
0855e32b 11824 BFD_ASSERT (srelgot != NULL);
ba93b8ac
DJ		 11825 }
11826
0855e32b
NS		 11827 if (tls_type & GOT_TLS_GDESC)
11828 {
47beaa6a
RS		 11829 bfd_byte *loc;
11830
0855e32b
NS		 11831 /* We should have relaxed, unless this is an undefined
11832 weak symbol. */
11833 BFD_ASSERT ((h && (h->root.type == bfd_link_hash_undefweak))
9cb09e33 11834 || bfd_link_dll (info));
0855e32b 11835 BFD_ASSERT (globals->sgotplt_jump_table_size + offplt + 8
99059e56 11836 <= globals->root.sgotplt->size);
0855e32b
NS		 11837
11838 outrel.r_addend = 0;
11839 outrel.r_offset = (globals->root.sgotplt->output_section->vma
11840 + globals->root.sgotplt->output_offset
11841 + offplt
11842 + globals->sgotplt_jump_table_size);
b38cadfb 11843
0855e32b
NS		 11844 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DESC);
11845 sreloc = globals->root.srelplt;
11846 loc = sreloc->contents;
11847 loc += globals->next_tls_desc_index++ * RELOC_SIZE (globals);
11848 BFD_ASSERT (loc + RELOC_SIZE (globals)
99059e56 11849 <= sreloc->contents + sreloc->size);
0855e32b
NS		 11850
11851 SWAP_RELOC_OUT (globals) (output_bfd, &outrel, loc);
11852
11853 /* For globals, the first word in the relocation gets
11854 the relocation index and the top bit set, or zero,
11855 if we're binding now. For locals, it gets the
11856 symbol's offset in the tls section. */
99059e56 11857 bfd_put_32 (output_bfd,
0855e32b
NS		 11858 !h ? value - elf_hash_table (info)->tls_sec->vma
11859 : info->flags & DF_BIND_NOW ? 0
11860 : 0x80000000 | ELF32_R_SYM (outrel.r_info),
b38cadfb
NC		 11861 globals->root.sgotplt->contents + offplt
11862 + globals->sgotplt_jump_table_size);
11863
0855e32b 11864 /* Second word in the relocation is always zero. */
99059e56 11865 bfd_put_32 (output_bfd, 0,
b38cadfb
NC		 11866 globals->root.sgotplt->contents + offplt
11867 + globals->sgotplt_jump_table_size + 4);
0855e32b 11868 }
ba93b8ac
DJ		 11869 if (tls_type & GOT_TLS_GD)
11870 {
11871 if (need_relocs)
11872 {
00a97672 11873 outrel.r_addend = 0;
362d30a1
RS		 11874 outrel.r_offset = (sgot->output_section->vma
11875 + sgot->output_offset
00a97672 11876 + cur_off);
ba93b8ac 11877 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DTPMOD32);
ba93b8ac 11878
00a97672
RS		 11879 if (globals->use_rel)
11880 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11881 sgot->contents + cur_off);
00a97672 11882
47beaa6a 11883 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11884
11885 if (indx == 0)
11886 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11887 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11888 else
11889 {
00a97672 11890 outrel.r_addend = 0;
ba93b8ac
DJ		 11891 outrel.r_info = ELF32_R_INFO (indx,
11892 R_ARM_TLS_DTPOFF32);
11893 outrel.r_offset += 4;
00a97672
RS		 11894
11895 if (globals->use_rel)
11896 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11897 sgot->contents + cur_off + 4);
00a97672 11898
47beaa6a
RS		 11899 elf32_arm_add_dynreloc (output_bfd, info,
11900 srelgot, &outrel);
ba93b8ac
DJ		 11901 }
11902 }
11903 else
11904 {
11905 /* If we are not emitting relocations for a
11906 general dynamic reference, then we must be in a
11907 static link or an executable link with the
11908 symbol binding locally. Mark it as belonging
11909 to module 1, the executable. */
11910 bfd_put_32 (output_bfd, 1,
362d30a1 11911 sgot->contents + cur_off);
ba93b8ac 11912 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11913 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11914 }
11915
11916 cur_off += 8;
11917 }
11918
11919 if (tls_type & GOT_TLS_IE)
11920 {
11921 if (need_relocs)
11922 {
00a97672
RS		 11923 if (indx == 0)
11924 outrel.r_addend = value - dtpoff_base (info);
11925 else
11926 outrel.r_addend = 0;
362d30a1
RS		 11927 outrel.r_offset = (sgot->output_section->vma
11928 + sgot->output_offset
ba93b8ac
DJ		 11929 + cur_off);
11930 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_TPOFF32);
11931
00a97672
RS		 11932 if (globals->use_rel)
11933 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11934 sgot->contents + cur_off);
ba93b8ac 11935
47beaa6a 11936 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11937 }
11938 else
11939 bfd_put_32 (output_bfd, tpoff (info, value),
362d30a1 11940 sgot->contents + cur_off);
ba93b8ac
DJ		 11941 cur_off += 4;
11942 }
11943
11944 if (h != NULL)
11945 h->got.offset |= 1;
11946 else
11947 local_got_offsets[r_symndx] |= 1;
11948 }
11949
5c5a4843 11950 if ((tls_type & GOT_TLS_GD) && r_type != R_ARM_TLS_GD32 && r_type != R_ARM_TLS_GD32_FDPIC)
ba93b8ac 11951 off += 8;
0855e32b
NS		 11952 else if (tls_type & GOT_TLS_GDESC)
11953 off = offplt;
11954
11955 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL
11956 || ELF32_R_TYPE(rel->r_info) == R_ARM_THM_TLS_CALL)
11957 {
11958 bfd_signed_vma offset;
12352d3f
PB		 11959 /* TLS stubs are arm mode. The original symbol is a
11960 data object, so branch_type is bogus. */
11961 branch_type = ST_BRANCH_TO_ARM;
0855e32b 11962 enum elf32_arm_stub_type stub_type
34e77a92
RS		 11963 = arm_type_of_stub (info, input_section, rel,
11964 st_type, &branch_type,
0855e32b
NS		 11965 (struct elf32_arm_link_hash_entry *)h,
11966 globals->tls_trampoline, globals->root.splt,
11967 input_bfd, sym_name);
11968
11969 if (stub_type != arm_stub_none)
11970 {
11971 struct elf32_arm_stub_hash_entry *stub_entry
11972 = elf32_arm_get_stub_entry
11973 (input_section, globals->root.splt, 0, rel,
11974 globals, stub_type);
11975 offset = (stub_entry->stub_offset
11976 + stub_entry->stub_sec->output_offset
11977 + stub_entry->stub_sec->output_section->vma);
11978 }
11979 else
11980 offset = (globals->root.splt->output_section->vma
11981 + globals->root.splt->output_offset
11982 + globals->tls_trampoline);
11983
11984 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL)
11985 {
11986 unsigned long inst;
b38cadfb
NC		 11987
11988 offset -= (input_section->output_section->vma
11989 + input_section->output_offset
11990 + rel->r_offset + 8);
0855e32b
NS		 11991
11992 inst = offset >> 2;
11993 inst &= 0x00ffffff;
11994 value = inst | (globals->use_blx ? 0xfa000000 : 0xeb000000);
11995 }
11996 else
11997 {
11998 /* Thumb blx encodes the offset in a complicated
11999 fashion. */
12000 unsigned upper_insn, lower_insn;
12001 unsigned neg;
12002
b38cadfb
NC		 12003 offset -= (input_section->output_section->vma
12004 + input_section->output_offset
0855e32b 12005 + rel->r_offset + 4);
b38cadfb 12006
12352d3f
PB		 12007 if (stub_type != arm_stub_none
12008 && arm_stub_is_thumb (stub_type))
12009 {
12010 lower_insn = 0xd000;
12011 }
12012 else
12013 {
12014 lower_insn = 0xc000;
6a631e86 12015 /* Round up the offset to a word boundary. */
12352d3f
PB		 12016 offset = (offset + 2) & ~2;
12017 }
12018
0855e32b
NS		 12019 neg = offset < 0;
12020 upper_insn = (0xf000
12021 | ((offset >> 12) & 0x3ff)
12022 | (neg << 10));
12352d3f 12023 lower_insn |= (((!((offset >> 23) & 1)) ^ neg) << 13)
0855e32b 12024 | (((!((offset >> 22) & 1)) ^ neg) << 11)
12352d3f 12025 | ((offset >> 1) & 0x7ff);
0855e32b
NS		 12026 bfd_put_16 (input_bfd, upper_insn, hit_data);
12027 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
12028 return bfd_reloc_ok;
12029 }
12030 }
12031 /* These relocations needs special care, as besides the fact
12032 they point somewhere in .gotplt, the addend must be
12033 adjusted accordingly depending on the type of instruction
6a631e86 12034 we refer to. */
0855e32b
NS		 12035 else if ((r_type == R_ARM_TLS_GOTDESC) && (tls_type & GOT_TLS_GDESC))
12036 {
12037 unsigned long data, insn;
12038 unsigned thumb;
b38cadfb 12039
b627f562 12040 data = bfd_get_signed_32 (input_bfd, hit_data);
0855e32b 12041 thumb = data & 1;
b627f562 12042 data &= ~1ul;
b38cadfb 12043
0855e32b
NS		 12044 if (thumb)
12045 {
12046 insn = bfd_get_16 (input_bfd, contents + rel->r_offset - data);
12047 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
12048 insn = (insn << 16)
12049 | bfd_get_16 (input_bfd,
12050 contents + rel->r_offset - data + 2);
12051 if ((insn & 0xf800c000) == 0xf000c000)
12052 /* bl/blx */
12053 value = -6;
12054 else if ((insn & 0xffffff00) == 0x4400)
12055 /* add */
12056 value = -5;
12057 else
12058 {
4eca0228 12059 _bfd_error_handler
695344c0 12060 /* xgettext:c-format */
2dcf00ce 12061 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f 12062 "unexpected %s instruction '%#lx' "
2dcf00ce
AM		 12063 "referenced by TLS_GOTDESC"),
12064 input_bfd, input_section, (uint64_t) rel->r_offset,
90b6238f 12065 "Thumb", insn);
0855e32b
NS		 12066 return bfd_reloc_notsupported;
12067 }
12068 }
12069 else
12070 {
12071 insn = bfd_get_32 (input_bfd, contents + rel->r_offset - data);
12072
12073 switch (insn >> 24)
12074 {
12075 case 0xeb: /* bl */
12076 case 0xfa: /* blx */
12077 value = -4;
12078 break;
12079
12080 case 0xe0: /* add */
12081 value = -8;
12082 break;
b38cadfb 12083
0855e32b 12084 default:
4eca0228 12085 _bfd_error_handler
695344c0 12086 /* xgettext:c-format */
2dcf00ce 12087 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f 12088 "unexpected %s instruction '%#lx' "
2dcf00ce
AM		 12089 "referenced by TLS_GOTDESC"),
12090 input_bfd, input_section, (uint64_t) rel->r_offset,
90b6238f 12091 "ARM", insn);
0855e32b
NS		 12092 return bfd_reloc_notsupported;
12093 }
12094 }
b38cadfb 12095
0855e32b
NS		 12096 value += ((globals->root.sgotplt->output_section->vma
12097 + globals->root.sgotplt->output_offset + off)
12098 - (input_section->output_section->vma
12099 + input_section->output_offset
12100 + rel->r_offset)
12101 + globals->sgotplt_jump_table_size);
12102 }
12103 else
12104 value = ((globals->root.sgot->output_section->vma
12105 + globals->root.sgot->output_offset + off)
12106 - (input_section->output_section->vma
12107 + input_section->output_offset + rel->r_offset));
ba93b8ac 12108
5c5a4843
CL		 12109 if (globals->fdpic_p && (r_type == R_ARM_TLS_GD32_FDPIC ||
12110 r_type == R_ARM_TLS_IE32_FDPIC))
e8b09b87
CL		 12111 {
12112 /* For FDPIC relocations, resolve to the offset of the GOT
12113 entry from the start of GOT. */
12114 bfd_put_32(output_bfd,
12115 globals->root.sgot->output_offset + off,
12116 contents + rel->r_offset);
12117
12118 return bfd_reloc_ok;
12119 }
12120 else
12121 {
12122 return _bfd_final_link_relocate (howto, input_bfd, input_section,
12123 contents, rel->r_offset, value,
12124 rel->r_addend);
12125 }
ba93b8ac
DJ		 12126 }
12127
12128 case R_ARM_TLS_LE32:
3cbc1e5e 12129 if (bfd_link_dll (info))
ba93b8ac 12130 {
4eca0228 12131 _bfd_error_handler
695344c0 12132 /* xgettext:c-format */
2dcf00ce
AM		 12133 (_("%pB(%pA+%#" PRIx64 "): %s relocation not permitted "
12134 "in shared object"),
12135 input_bfd, input_section, (uint64_t) rel->r_offset, howto->name);
46691134 12136 return bfd_reloc_notsupported;
ba93b8ac
DJ		 12137 }
12138 else
12139 value = tpoff (info, value);
906e58ca 12140
ba93b8ac 12141 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 12142 contents, rel->r_offset, value,
12143 rel->r_addend);
ba93b8ac 12144
319850b4
JB		 12145 case R_ARM_V4BX:
12146 if (globals->fix_v4bx)
845b51d6
PB		 12147 {
12148 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
319850b4 12149
845b51d6
PB		 12150 /* Ensure that we have a BX instruction. */
12151 BFD_ASSERT ((insn & 0x0ffffff0) == 0x012fff10);
319850b4 12152
845b51d6
PB		 12153 if (globals->fix_v4bx == 2 && (insn & 0xf) != 0xf)
12154 {
12155 /* Branch to veneer. */
12156 bfd_vma glue_addr;
12157 glue_addr = elf32_arm_bx_glue (info, insn & 0xf);
12158 glue_addr -= input_section->output_section->vma
12159 + input_section->output_offset
12160 + rel->r_offset + 8;
12161 insn = (insn & 0xf0000000) | 0x0a000000
12162 | ((glue_addr >> 2) & 0x00ffffff);
12163 }
12164 else
12165 {
12166 /* Preserve Rm (lowest four bits) and the condition code
12167 (highest four bits). Other bits encode MOV PC,Rm. */
12168 insn = (insn & 0xf000000f) | 0x01a0f000;
12169 }
319850b4 12170
845b51d6
PB		 12171 bfd_put_32 (input_bfd, insn, hit_data);
12172 }
319850b4
JB		 12173 return bfd_reloc_ok;
12174
b6895b4f
PB		 12175 case R_ARM_MOVW_ABS_NC:
12176 case R_ARM_MOVT_ABS:
12177 case R_ARM_MOVW_PREL_NC:
12178 case R_ARM_MOVT_PREL:
92f5d02b
MS		 12179 /* Until we properly support segment-base-relative addressing then
12180 we assume the segment base to be zero, as for the group relocations.
12181 Thus R_ARM_MOVW_BREL_NC has the same semantics as R_ARM_MOVW_ABS_NC
12182 and R_ARM_MOVT_BREL has the same semantics as R_ARM_MOVT_ABS. */
12183 case R_ARM_MOVW_BREL_NC:
12184 case R_ARM_MOVW_BREL:
12185 case R_ARM_MOVT_BREL:
b6895b4f
PB		 12186 {
12187 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
12188
12189 if (globals->use_rel)
12190 {
12191 addend = ((insn >> 4) & 0xf000) | (insn & 0xfff);
39623e12 12192 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 12193 }
92f5d02b 12194
b6895b4f 12195 value += signed_addend;
b6895b4f
PB		 12196
12197 if (r_type == R_ARM_MOVW_PREL_NC || r_type == R_ARM_MOVT_PREL)
12198 value -= (input_section->output_section->vma
12199 + input_section->output_offset + rel->r_offset);
12200
92f5d02b 12201 if (r_type == R_ARM_MOVW_BREL && value >= 0x10000)
99059e56 12202 return bfd_reloc_overflow;
92f5d02b 12203
35fc36a8 12204 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 12205 value |= 1;
12206
12207 if (r_type == R_ARM_MOVT_ABS || r_type == R_ARM_MOVT_PREL
99059e56 12208 || r_type == R_ARM_MOVT_BREL)
b6895b4f
PB		 12209 value >>= 16;
12210
12211 insn &= 0xfff0f000;
12212 insn |= value & 0xfff;
12213 insn |= (value & 0xf000) << 4;
12214 bfd_put_32 (input_bfd, insn, hit_data);
12215 }
12216 return bfd_reloc_ok;
12217
12218 case R_ARM_THM_MOVW_ABS_NC:
12219 case R_ARM_THM_MOVT_ABS:
12220 case R_ARM_THM_MOVW_PREL_NC:
12221 case R_ARM_THM_MOVT_PREL:
92f5d02b
MS		 12222 /* Until we properly support segment-base-relative addressing then
12223 we assume the segment base to be zero, as for the above relocations.
12224 Thus R_ARM_THM_MOVW_BREL_NC has the same semantics as
12225 R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_BREL has the same semantics
12226 as R_ARM_THM_MOVT_ABS. */
12227 case R_ARM_THM_MOVW_BREL_NC:
12228 case R_ARM_THM_MOVW_BREL:
12229 case R_ARM_THM_MOVT_BREL:
b6895b4f
PB		 12230 {
12231 bfd_vma insn;
906e58ca 12232
b6895b4f
PB		 12233 insn = bfd_get_16 (input_bfd, hit_data) << 16;
12234 insn |= bfd_get_16 (input_bfd, hit_data + 2);
12235
12236 if (globals->use_rel)
12237 {
12238 addend = ((insn >> 4) & 0xf000)
12239 | ((insn >> 15) & 0x0800)
12240 | ((insn >> 4) & 0x0700)
07d6d2b8 12241 | (insn & 0x00ff);
39623e12 12242 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 12243 }
92f5d02b 12244
b6895b4f 12245 value += signed_addend;
b6895b4f
PB		 12246
12247 if (r_type == R_ARM_THM_MOVW_PREL_NC || r_type == R_ARM_THM_MOVT_PREL)
12248 value -= (input_section->output_section->vma
12249 + input_section->output_offset + rel->r_offset);
12250
92f5d02b 12251 if (r_type == R_ARM_THM_MOVW_BREL && value >= 0x10000)
99059e56 12252 return bfd_reloc_overflow;
92f5d02b 12253
35fc36a8 12254 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 12255 value |= 1;
12256
12257 if (r_type == R_ARM_THM_MOVT_ABS || r_type == R_ARM_THM_MOVT_PREL
99059e56 12258 || r_type == R_ARM_THM_MOVT_BREL)
b6895b4f
PB		 12259 value >>= 16;
12260
12261 insn &= 0xfbf08f00;
12262 insn |= (value & 0xf000) << 4;
12263 insn |= (value & 0x0800) << 15;
12264 insn |= (value & 0x0700) << 4;
12265 insn |= (value & 0x00ff);
12266
12267 bfd_put_16 (input_bfd, insn >> 16, hit_data);
12268 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
12269 }
12270 return bfd_reloc_ok;
12271
4962c51a
MS		 12272 case R_ARM_ALU_PC_G0_NC:
12273 case R_ARM_ALU_PC_G1_NC:
12274 case R_ARM_ALU_PC_G0:
12275 case R_ARM_ALU_PC_G1:
12276 case R_ARM_ALU_PC_G2:
12277 case R_ARM_ALU_SB_G0_NC:
12278 case R_ARM_ALU_SB_G1_NC:
12279 case R_ARM_ALU_SB_G0:
12280 case R_ARM_ALU_SB_G1:
12281 case R_ARM_ALU_SB_G2:
12282 {
12283 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12284 bfd_vma pc = input_section->output_section->vma
4962c51a 12285 + input_section->output_offset + rel->r_offset;
31a91d61 12286 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12287 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56
RM		 12288 bfd_vma residual;
12289 bfd_vma g_n;
4962c51a 12290 bfd_signed_vma signed_value;
99059e56
RM		 12291 int group = 0;
12292
12293 /* Determine which group of bits to select. */
12294 switch (r_type)
12295 {
12296 case R_ARM_ALU_PC_G0_NC:
12297 case R_ARM_ALU_PC_G0:
12298 case R_ARM_ALU_SB_G0_NC:
12299 case R_ARM_ALU_SB_G0:
12300 group = 0;
12301 break;
12302
12303 case R_ARM_ALU_PC_G1_NC:
12304 case R_ARM_ALU_PC_G1:
12305 case R_ARM_ALU_SB_G1_NC:
12306 case R_ARM_ALU_SB_G1:
12307 group = 1;
12308 break;
12309
12310 case R_ARM_ALU_PC_G2:
12311 case R_ARM_ALU_SB_G2:
12312 group = 2;
12313 break;
12314
12315 default:
12316 abort ();
12317 }
12318
12319 /* If REL, extract the addend from the insn. If RELA, it will
12320 have already been fetched for us. */
4962c51a 12321 if (globals->use_rel)
99059e56
RM		 12322 {
12323 int negative;
12324 bfd_vma constant = insn & 0xff;
12325 bfd_vma rotation = (insn & 0xf00) >> 8;
12326
12327 if (rotation == 0)
12328 signed_addend = constant;
12329 else
12330 {
12331 /* Compensate for the fact that in the instruction, the
12332 rotation is stored in multiples of 2 bits. */
12333 rotation *= 2;
12334
12335 /* Rotate "constant" right by "rotation" bits. */
12336 signed_addend = (constant >> rotation) |
12337 (constant << (8 * sizeof (bfd_vma) - rotation));
12338 }
12339
12340 /* Determine if the instruction is an ADD or a SUB.
12341 (For REL, this determines the sign of the addend.) */
12342 negative = identify_add_or_sub (insn);
12343 if (negative == 0)
12344 {
4eca0228 12345 _bfd_error_handler
695344c0 12346 /* xgettext:c-format */
90b6238f 12347 (_("%pB(%pA+%#" PRIx64 "): only ADD or SUB instructions "
2dcf00ce
AM		 12348 "are allowed for ALU group relocations"),
12349 input_bfd, input_section, (uint64_t) rel->r_offset);
99059e56
RM		 12350 return bfd_reloc_overflow;
12351 }
12352
12353 signed_addend *= negative;
12354 }
4962c51a
MS		 12355
12356 /* Compute the value (X) to go in the place. */
99059e56
RM		 12357 if (r_type == R_ARM_ALU_PC_G0_NC
12358 || r_type == R_ARM_ALU_PC_G1_NC
12359 || r_type == R_ARM_ALU_PC_G0
12360 || r_type == R_ARM_ALU_PC_G1
12361 || r_type == R_ARM_ALU_PC_G2)
12362 /* PC relative. */
12363 signed_value = value - pc + signed_addend;
12364 else
12365 /* Section base relative. */
12366 signed_value = value - sb + signed_addend;
12367
12368 /* If the target symbol is a Thumb function, then set the
12369 Thumb bit in the address. */
35fc36a8 12370 if (branch_type == ST_BRANCH_TO_THUMB)
4962c51a
MS		 12371 signed_value |= 1;
12372
99059e56
RM		 12373 /* Calculate the value of the relevant G_n, in encoded
12374 constant-with-rotation format. */
b6518b38
NC		 12375 g_n = calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12376 group, &residual);
99059e56
RM		 12377
12378 /* Check for overflow if required. */
12379 if ((r_type == R_ARM_ALU_PC_G0
12380 || r_type == R_ARM_ALU_PC_G1
12381 || r_type == R_ARM_ALU_PC_G2
12382 || r_type == R_ARM_ALU_SB_G0
12383 || r_type == R_ARM_ALU_SB_G1
12384 || r_type == R_ARM_ALU_SB_G2) && residual != 0)
12385 {
4eca0228 12386 _bfd_error_handler
695344c0 12387 /* xgettext:c-format */
90b6238f 12388 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12389 "splitting %#" PRIx64 " for group relocation %s"),
12390 input_bfd, input_section, (uint64_t) rel->r_offset,
12391 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12392 howto->name);
99059e56
RM		 12393 return bfd_reloc_overflow;
12394 }
12395
12396 /* Mask out the value and the ADD/SUB part of the opcode; take care
12397 not to destroy the S bit. */
12398 insn &= 0xff1ff000;
12399
12400 /* Set the opcode according to whether the value to go in the
12401 place is negative. */
12402 if (signed_value < 0)
12403 insn |= 1 << 22;
12404 else
12405 insn |= 1 << 23;
12406
12407 /* Encode the offset. */
12408 insn |= g_n;
4962c51a
MS		 12409
12410 bfd_put_32 (input_bfd, insn, hit_data);
12411 }
12412 return bfd_reloc_ok;
12413
12414 case R_ARM_LDR_PC_G0:
12415 case R_ARM_LDR_PC_G1:
12416 case R_ARM_LDR_PC_G2:
12417 case R_ARM_LDR_SB_G0:
12418 case R_ARM_LDR_SB_G1:
12419 case R_ARM_LDR_SB_G2:
12420 {
12421 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12422 bfd_vma pc = input_section->output_section->vma
4962c51a 12423 + input_section->output_offset + rel->r_offset;
31a91d61 12424 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12425 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12426 bfd_vma residual;
4962c51a 12427 bfd_signed_vma signed_value;
99059e56
RM		 12428 int group = 0;
12429
12430 /* Determine which groups of bits to calculate. */
12431 switch (r_type)
12432 {
12433 case R_ARM_LDR_PC_G0:
12434 case R_ARM_LDR_SB_G0:
12435 group = 0;
12436 break;
12437
12438 case R_ARM_LDR_PC_G1:
12439 case R_ARM_LDR_SB_G1:
12440 group = 1;
12441 break;
12442
12443 case R_ARM_LDR_PC_G2:
12444 case R_ARM_LDR_SB_G2:
12445 group = 2;
12446 break;
12447
12448 default:
12449 abort ();
12450 }
12451
12452 /* If REL, extract the addend from the insn. If RELA, it will
12453 have already been fetched for us. */
4962c51a 12454 if (globals->use_rel)
99059e56
RM		 12455 {
12456 int negative = (insn & (1 << 23)) ? 1 : -1;
12457 signed_addend = negative * (insn & 0xfff);
12458 }
4962c51a
MS		 12459
12460 /* Compute the value (X) to go in the place. */
99059e56
RM		 12461 if (r_type == R_ARM_LDR_PC_G0
12462 || r_type == R_ARM_LDR_PC_G1
12463 || r_type == R_ARM_LDR_PC_G2)
12464 /* PC relative. */
12465 signed_value = value - pc + signed_addend;
12466 else
12467 /* Section base relative. */
12468 signed_value = value - sb + signed_addend;
12469
12470 /* Calculate the value of the relevant G_{n-1} to obtain
12471 the residual at that stage. */
b6518b38
NC		 12472 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12473 group - 1, &residual);
99059e56
RM		 12474
12475 /* Check for overflow. */
12476 if (residual >= 0x1000)
12477 {
4eca0228 12478 _bfd_error_handler
695344c0 12479 /* xgettext:c-format */
90b6238f 12480 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12481 "splitting %#" PRIx64 " for group relocation %s"),
12482 input_bfd, input_section, (uint64_t) rel->r_offset,
12483 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12484 howto->name);
99059e56
RM		 12485 return bfd_reloc_overflow;
12486 }
12487
12488 /* Mask out the value and U bit. */
12489 insn &= 0xff7ff000;
12490
12491 /* Set the U bit if the value to go in the place is non-negative. */
12492 if (signed_value >= 0)
12493 insn |= 1 << 23;
12494
12495 /* Encode the offset. */
12496 insn |= residual;
4962c51a
MS		 12497
12498 bfd_put_32 (input_bfd, insn, hit_data);
12499 }
12500 return bfd_reloc_ok;
12501
12502 case R_ARM_LDRS_PC_G0:
12503 case R_ARM_LDRS_PC_G1:
12504 case R_ARM_LDRS_PC_G2:
12505 case R_ARM_LDRS_SB_G0:
12506 case R_ARM_LDRS_SB_G1:
12507 case R_ARM_LDRS_SB_G2:
12508 {
12509 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12510 bfd_vma pc = input_section->output_section->vma
4962c51a 12511 + input_section->output_offset + rel->r_offset;
31a91d61 12512 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12513 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12514 bfd_vma residual;
4962c51a 12515 bfd_signed_vma signed_value;
99059e56
RM		 12516 int group = 0;
12517
12518 /* Determine which groups of bits to calculate. */
12519 switch (r_type)
12520 {
12521 case R_ARM_LDRS_PC_G0:
12522 case R_ARM_LDRS_SB_G0:
12523 group = 0;
12524 break;
12525
12526 case R_ARM_LDRS_PC_G1:
12527 case R_ARM_LDRS_SB_G1:
12528 group = 1;
12529 break;
12530
12531 case R_ARM_LDRS_PC_G2:
12532 case R_ARM_LDRS_SB_G2:
12533 group = 2;
12534 break;
12535
12536 default:
12537 abort ();
12538 }
12539
12540 /* If REL, extract the addend from the insn. If RELA, it will
12541 have already been fetched for us. */
4962c51a 12542 if (globals->use_rel)
99059e56
RM		 12543 {
12544 int negative = (insn & (1 << 23)) ? 1 : -1;
12545 signed_addend = negative * (((insn & 0xf00) >> 4) + (insn & 0xf));
12546 }
4962c51a
MS		 12547
12548 /* Compute the value (X) to go in the place. */
99059e56
RM		 12549 if (r_type == R_ARM_LDRS_PC_G0
12550 || r_type == R_ARM_LDRS_PC_G1
12551 || r_type == R_ARM_LDRS_PC_G2)
12552 /* PC relative. */
12553 signed_value = value - pc + signed_addend;
12554 else
12555 /* Section base relative. */
12556 signed_value = value - sb + signed_addend;
12557
12558 /* Calculate the value of the relevant G_{n-1} to obtain
12559 the residual at that stage. */
b6518b38
NC		 12560 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12561 group - 1, &residual);
99059e56
RM		 12562
12563 /* Check for overflow. */
12564 if (residual >= 0x100)
12565 {
4eca0228 12566 _bfd_error_handler
695344c0 12567 /* xgettext:c-format */
90b6238f 12568 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12569 "splitting %#" PRIx64 " for group relocation %s"),
12570 input_bfd, input_section, (uint64_t) rel->r_offset,
12571 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12572 howto->name);
99059e56
RM		 12573 return bfd_reloc_overflow;
12574 }
12575
12576 /* Mask out the value and U bit. */
12577 insn &= 0xff7ff0f0;
12578
12579 /* Set the U bit if the value to go in the place is non-negative. */
12580 if (signed_value >= 0)
12581 insn |= 1 << 23;
12582
12583 /* Encode the offset. */
12584 insn |= ((residual & 0xf0) << 4) | (residual & 0xf);
4962c51a
MS		 12585
12586 bfd_put_32 (input_bfd, insn, hit_data);
12587 }
12588 return bfd_reloc_ok;
12589
12590 case R_ARM_LDC_PC_G0:
12591 case R_ARM_LDC_PC_G1:
12592 case R_ARM_LDC_PC_G2:
12593 case R_ARM_LDC_SB_G0:
12594 case R_ARM_LDC_SB_G1:
12595 case R_ARM_LDC_SB_G2:
12596 {
12597 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12598 bfd_vma pc = input_section->output_section->vma
4962c51a 12599 + input_section->output_offset + rel->r_offset;
31a91d61 12600 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12601 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12602 bfd_vma residual;
4962c51a 12603 bfd_signed_vma signed_value;
99059e56
RM		 12604 int group = 0;
12605
12606 /* Determine which groups of bits to calculate. */
12607 switch (r_type)
12608 {
12609 case R_ARM_LDC_PC_G0:
12610 case R_ARM_LDC_SB_G0:
12611 group = 0;
12612 break;
12613
12614 case R_ARM_LDC_PC_G1:
12615 case R_ARM_LDC_SB_G1:
12616 group = 1;
12617 break;
12618
12619 case R_ARM_LDC_PC_G2:
12620 case R_ARM_LDC_SB_G2:
12621 group = 2;
12622 break;
12623
12624 default:
12625 abort ();
12626 }
12627
12628 /* If REL, extract the addend from the insn. If RELA, it will
12629 have already been fetched for us. */
4962c51a 12630 if (globals->use_rel)
99059e56
RM		 12631 {
12632 int negative = (insn & (1 << 23)) ? 1 : -1;
12633 signed_addend = negative * ((insn & 0xff) << 2);
12634 }
4962c51a
MS		 12635
12636 /* Compute the value (X) to go in the place. */
99059e56
RM		 12637 if (r_type == R_ARM_LDC_PC_G0
12638 || r_type == R_ARM_LDC_PC_G1
12639 || r_type == R_ARM_LDC_PC_G2)
12640 /* PC relative. */
12641 signed_value = value - pc + signed_addend;
12642 else
12643 /* Section base relative. */
12644 signed_value = value - sb + signed_addend;
12645
12646 /* Calculate the value of the relevant G_{n-1} to obtain
12647 the residual at that stage. */
b6518b38
NC		 12648 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12649 group - 1, &residual);
99059e56
RM		 12650
12651 /* Check for overflow. (The absolute value to go in the place must be
12652 divisible by four and, after having been divided by four, must
12653 fit in eight bits.) */
12654 if ((residual & 0x3) != 0 || residual >= 0x400)
12655 {
4eca0228 12656 _bfd_error_handler
695344c0 12657 /* xgettext:c-format */
90b6238f 12658 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12659 "splitting %#" PRIx64 " for group relocation %s"),
12660 input_bfd, input_section, (uint64_t) rel->r_offset,
12661 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12662 howto->name);
99059e56
RM		 12663 return bfd_reloc_overflow;
12664 }
12665
12666 /* Mask out the value and U bit. */
12667 insn &= 0xff7fff00;
12668
12669 /* Set the U bit if the value to go in the place is non-negative. */
12670 if (signed_value >= 0)
12671 insn |= 1 << 23;
12672
12673 /* Encode the offset. */
12674 insn |= residual >> 2;
4962c51a
MS		 12675
12676 bfd_put_32 (input_bfd, insn, hit_data);
12677 }
12678 return bfd_reloc_ok;
12679
72d98d16
MG		 12680 case R_ARM_THM_ALU_ABS_G0_NC:
12681 case R_ARM_THM_ALU_ABS_G1_NC:
12682 case R_ARM_THM_ALU_ABS_G2_NC:
12683 case R_ARM_THM_ALU_ABS_G3_NC:
12684 {
12685 const int shift_array[4] = {0, 8, 16, 24};
12686 bfd_vma insn = bfd_get_16 (input_bfd, hit_data);
12687 bfd_vma addr = value;
12688 int shift = shift_array[r_type - R_ARM_THM_ALU_ABS_G0_NC];
12689
12690 /* Compute address. */
12691 if (globals->use_rel)
12692 signed_addend = insn & 0xff;
12693 addr += signed_addend;
12694 if (branch_type == ST_BRANCH_TO_THUMB)
12695 addr |= 1;
12696 /* Clean imm8 insn. */
12697 insn &= 0xff00;
12698 /* And update with correct part of address. */
12699 insn |= (addr >> shift) & 0xff;
12700 /* Update insn. */
12701 bfd_put_16 (input_bfd, insn, hit_data);
12702 }
12703
12704 *unresolved_reloc_p = FALSE;
12705 return bfd_reloc_ok;
12706
e8b09b87
CL		 12707 case R_ARM_GOTOFFFUNCDESC:
12708 {
4b24dd1a 12709 if (h == NULL)
e8b09b87
CL		 12710 {
12711 struct fdpic_local *local_fdpic_cnts = elf32_arm_local_fdpic_cnts(input_bfd);
12712 int dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12713 int offset = local_fdpic_cnts[r_symndx].funcdesc_offset & ~1;
12714 bfd_vma addr = dynreloc_value - sym_sec->output_section->vma;
12715 bfd_vma seg = -1;
12716
12717 if (bfd_link_pic(info) && dynindx == 0)
12718 abort();
12719
12720 /* Resolve relocation. */
12721 bfd_put_32(output_bfd, (offset + sgot->output_offset)
12722 , contents + rel->r_offset);
12723 /* Emit R_ARM_FUNCDESC_VALUE or two fixups on funcdesc if
12724 not done yet. */
12725 arm_elf_fill_funcdesc(output_bfd, info,
12726 &local_fdpic_cnts[r_symndx].funcdesc_offset,
12727 dynindx, offset, addr, dynreloc_value, seg);
12728 }
12729 else
12730 {
12731 int dynindx;
12732 int offset = eh->fdpic_cnts.funcdesc_offset & ~1;
12733 bfd_vma addr;
12734 bfd_vma seg = -1;
12735
12736 /* For static binaries, sym_sec can be null. */
12737 if (sym_sec)
12738 {
12739 dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12740 addr = dynreloc_value - sym_sec->output_section->vma;
12741 }
12742 else
12743 {
12744 dynindx = 0;
12745 addr = 0;
12746 }
12747
12748 if (bfd_link_pic(info) && dynindx == 0)
12749 abort();
12750
12751 /* This case cannot occur since funcdesc is allocated by
12752 the dynamic loader so we cannot resolve the relocation. */
12753 if (h->dynindx != -1)
12754 abort();
12755
12756 /* Resolve relocation. */
12757 bfd_put_32(output_bfd, (offset + sgot->output_offset),
12758 contents + rel->r_offset);
12759 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12760 arm_elf_fill_funcdesc(output_bfd, info,
12761 &eh->fdpic_cnts.funcdesc_offset,
12762 dynindx, offset, addr, dynreloc_value, seg);
12763 }
12764 }
12765 *unresolved_reloc_p = FALSE;
12766 return bfd_reloc_ok;
12767
12768 case R_ARM_GOTFUNCDESC:
12769 {
4b24dd1a 12770 if (h != NULL)
e8b09b87
CL		 12771 {
12772 Elf_Internal_Rela outrel;
12773
12774 /* Resolve relocation. */
12775 bfd_put_32(output_bfd, ((eh->fdpic_cnts.gotfuncdesc_offset & ~1)
12776 + sgot->output_offset),
12777 contents + rel->r_offset);
12778 /* Add funcdesc and associated R_ARM_FUNCDESC_VALUE. */
12779 if(h->dynindx == -1)
12780 {
12781 int dynindx;
12782 int offset = eh->fdpic_cnts.funcdesc_offset & ~1;
12783 bfd_vma addr;
12784 bfd_vma seg = -1;
12785
12786 /* For static binaries sym_sec can be null. */
12787 if (sym_sec)
12788 {
12789 dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12790 addr = dynreloc_value - sym_sec->output_section->vma;
12791 }
12792 else
12793 {
12794 dynindx = 0;
12795 addr = 0;
12796 }
12797
12798 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12799 arm_elf_fill_funcdesc(output_bfd, info,
12800 &eh->fdpic_cnts.funcdesc_offset,
12801 dynindx, offset, addr, dynreloc_value, seg);
12802 }
12803
12804 /* Add a dynamic relocation on GOT entry if not already done. */
12805 if ((eh->fdpic_cnts.gotfuncdesc_offset & 1) == 0)
12806 {
12807 if (h->dynindx == -1)
12808 {
12809 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
12810 if (h->root.type == bfd_link_hash_undefweak)
12811 bfd_put_32(output_bfd, 0, sgot->contents
12812 + (eh->fdpic_cnts.gotfuncdesc_offset & ~1));
12813 else
12814 bfd_put_32(output_bfd, sgot->output_section->vma
12815 + sgot->output_offset
12816 + (eh->fdpic_cnts.funcdesc_offset & ~1),
12817 sgot->contents
12818 + (eh->fdpic_cnts.gotfuncdesc_offset & ~1));
12819 }
12820 else
12821 {
12822 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_FUNCDESC);
12823 }
12824 outrel.r_offset = sgot->output_section->vma
12825 + sgot->output_offset
12826 + (eh->fdpic_cnts.gotfuncdesc_offset & ~1);
12827 outrel.r_addend = 0;
12828 if (h->dynindx == -1 && !bfd_link_pic(info))
12829 if (h->root.type == bfd_link_hash_undefweak)
4b24dd1a 12830 arm_elf_add_rofixup(output_bfd, globals->srofixup, -1);
e8b09b87 12831 else
4b24dd1a
AM		 12832 arm_elf_add_rofixup(output_bfd, globals->srofixup,
12833 outrel.r_offset);
e8b09b87
CL		 12834 else
12835 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12836 eh->fdpic_cnts.gotfuncdesc_offset |= 1;
12837 }
12838 }
12839 else
12840 {
12841 /* Such relocation on static function should not have been
12842 emitted by the compiler. */
12843 abort();
12844 }
12845 }
12846 *unresolved_reloc_p = FALSE;
12847 return bfd_reloc_ok;
12848
12849 case R_ARM_FUNCDESC:
12850 {
4b24dd1a 12851 if (h == NULL)
e8b09b87
CL		 12852 {
12853 struct fdpic_local *local_fdpic_cnts = elf32_arm_local_fdpic_cnts(input_bfd);
12854 Elf_Internal_Rela outrel;
12855 int dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12856 int offset = local_fdpic_cnts[r_symndx].funcdesc_offset & ~1;
12857 bfd_vma addr = dynreloc_value - sym_sec->output_section->vma;
12858 bfd_vma seg = -1;
12859
12860 if (bfd_link_pic(info) && dynindx == 0)
12861 abort();
12862
12863 /* Replace static FUNCDESC relocation with a
12864 R_ARM_RELATIVE dynamic relocation or with a rofixup for
12865 executable. */
12866 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
12867 outrel.r_offset = input_section->output_section->vma
12868 + input_section->output_offset + rel->r_offset;
12869 outrel.r_addend = 0;
12870 if (bfd_link_pic(info))
12871 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12872 else
12873 arm_elf_add_rofixup(output_bfd, globals->srofixup, outrel.r_offset);
12874
12875 bfd_put_32 (input_bfd, sgot->output_section->vma
12876 + sgot->output_offset + offset, hit_data);
12877
12878 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12879 arm_elf_fill_funcdesc(output_bfd, info,
12880 &local_fdpic_cnts[r_symndx].funcdesc_offset,
12881 dynindx, offset, addr, dynreloc_value, seg);
12882 }
12883 else
12884 {
12885 if (h->dynindx == -1)
12886 {
12887 int dynindx;
12888 int offset = eh->fdpic_cnts.funcdesc_offset & ~1;
12889 bfd_vma addr;
12890 bfd_vma seg = -1;
12891 Elf_Internal_Rela outrel;
12892
12893 /* For static binaries sym_sec can be null. */
12894 if (sym_sec)
12895 {
12896 dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12897 addr = dynreloc_value - sym_sec->output_section->vma;
12898 }
12899 else
12900 {
12901 dynindx = 0;
12902 addr = 0;
12903 }
12904
12905 if (bfd_link_pic(info) && dynindx == 0)
12906 abort();
12907
12908 /* Replace static FUNCDESC relocation with a
12909 R_ARM_RELATIVE dynamic relocation. */
12910 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
12911 outrel.r_offset = input_section->output_section->vma
12912 + input_section->output_offset + rel->r_offset;
12913 outrel.r_addend = 0;
12914 if (bfd_link_pic(info))
12915 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12916 else
12917 arm_elf_add_rofixup(output_bfd, globals->srofixup, outrel.r_offset);
12918
12919 bfd_put_32 (input_bfd, sgot->output_section->vma
12920 + sgot->output_offset + offset, hit_data);
12921
12922 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12923 arm_elf_fill_funcdesc(output_bfd, info,
12924 &eh->fdpic_cnts.funcdesc_offset,
12925 dynindx, offset, addr, dynreloc_value, seg);
12926 }
12927 else
12928 {
12929 Elf_Internal_Rela outrel;
12930
12931 /* Add a dynamic relocation. */
12932 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_FUNCDESC);
12933 outrel.r_offset = input_section->output_section->vma
12934 + input_section->output_offset + rel->r_offset;
12935 outrel.r_addend = 0;
12936 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12937 }
12938 }
12939 }
12940 *unresolved_reloc_p = FALSE;
12941 return bfd_reloc_ok;
12942
e5d6e09e
AV		 12943 case R_ARM_THM_BF16:
12944 {
12945 bfd_vma relocation;
12946 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
12947 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
12948
12949 if (globals->use_rel)
12950 {
12951 bfd_vma immA = (upper_insn & 0x001f);
12952 bfd_vma immB = (lower_insn & 0x07fe) >> 1;
12953 bfd_vma immC = (lower_insn & 0x0800) >> 11;
12954 addend = (immA << 12);
12955 addend |= (immB << 2);
12956 addend |= (immC << 1);
12957 addend |= 1;
12958 /* Sign extend. */
e6f65e75 12959 signed_addend = (addend & 0x10000) ? addend - (1 << 17) : addend;
e5d6e09e
AV		 12960 }
12961
e6f65e75 12962 relocation = value + signed_addend;
e5d6e09e
AV		 12963 relocation -= (input_section->output_section->vma
12964 + input_section->output_offset
12965 + rel->r_offset);
12966
12967 /* Put RELOCATION back into the insn. */
12968 {
12969 bfd_vma immA = (relocation & 0x0001f000) >> 12;
12970 bfd_vma immB = (relocation & 0x00000ffc) >> 2;
12971 bfd_vma immC = (relocation & 0x00000002) >> 1;
12972
12973 upper_insn = (upper_insn & 0xffe0) | immA;
12974 lower_insn = (lower_insn & 0xf001) | (immC << 11) | (immB << 1);
12975 }
12976
12977 /* Put the relocated value back in the object file: */
12978 bfd_put_16 (input_bfd, upper_insn, hit_data);
12979 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
12980
12981 return bfd_reloc_ok;
12982 }
12983
1889da70
AV		 12984 case R_ARM_THM_BF12:
12985 {
12986 bfd_vma relocation;
12987 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
12988 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
12989
12990 if (globals->use_rel)
12991 {
12992 bfd_vma immA = (upper_insn & 0x0001);
12993 bfd_vma immB = (lower_insn & 0x07fe) >> 1;
12994 bfd_vma immC = (lower_insn & 0x0800) >> 11;
12995 addend = (immA << 12);
12996 addend |= (immB << 2);
12997 addend |= (immC << 1);
12998 addend |= 1;
12999 /* Sign extend. */
13000 addend = (addend & 0x1000) ? addend - (1 << 13) : addend;
e6f65e75 13001 signed_addend = addend;
1889da70
AV		 13002 }
13003
e6f65e75 13004 relocation = value + signed_addend;
1889da70
AV		 13005 relocation -= (input_section->output_section->vma
13006 + input_section->output_offset
13007 + rel->r_offset);
13008
13009 /* Put RELOCATION back into the insn. */
13010 {
13011 bfd_vma immA = (relocation & 0x00001000) >> 12;
13012 bfd_vma immB = (relocation & 0x00000ffc) >> 2;
13013 bfd_vma immC = (relocation & 0x00000002) >> 1;
13014
13015 upper_insn = (upper_insn & 0xfffe) | immA;
13016 lower_insn = (lower_insn & 0xf001) | (immC << 11) | (immB << 1);
13017 }
13018
13019 /* Put the relocated value back in the object file: */
13020 bfd_put_16 (input_bfd, upper_insn, hit_data);
13021 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
13022
13023 return bfd_reloc_ok;
13024 }
13025
1caf72a5
AV		 13026 case R_ARM_THM_BF18:
13027 {
13028 bfd_vma relocation;
13029 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
13030 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
13031
13032 if (globals->use_rel)
13033 {
13034 bfd_vma immA = (upper_insn & 0x007f);
13035 bfd_vma immB = (lower_insn & 0x07fe) >> 1;
13036 bfd_vma immC = (lower_insn & 0x0800) >> 11;
13037 addend = (immA << 12);
13038 addend |= (immB << 2);
13039 addend |= (immC << 1);
13040 addend |= 1;
13041 /* Sign extend. */
13042 addend = (addend & 0x40000) ? addend - (1 << 19) : addend;
e6f65e75 13043 signed_addend = addend;
1caf72a5
AV		 13044 }
13045
e6f65e75 13046 relocation = value + signed_addend;
1caf72a5
AV		 13047 relocation -= (input_section->output_section->vma
13048 + input_section->output_offset
13049 + rel->r_offset);
13050
13051 /* Put RELOCATION back into the insn. */
13052 {
13053 bfd_vma immA = (relocation & 0x0007f000) >> 12;
13054 bfd_vma immB = (relocation & 0x00000ffc) >> 2;
13055 bfd_vma immC = (relocation & 0x00000002) >> 1;
13056
13057 upper_insn = (upper_insn & 0xff80) | immA;
13058 lower_insn = (lower_insn & 0xf001) | (immC << 11) | (immB << 1);
13059 }
13060
13061 /* Put the relocated value back in the object file: */
13062 bfd_put_16 (input_bfd, upper_insn, hit_data);
13063 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
13064
13065 return bfd_reloc_ok;
13066 }
13067
252b5132
RH		 13068 default:
13069 return bfd_reloc_notsupported;
13070 }
13071}
13072
98c1d4aa
NC		 13073/* Add INCREMENT to the reloc (of type HOWTO) at ADDRESS. */
13074static void
07d6d2b8
AM		 13075arm_add_to_rel (bfd * abfd,
13076 bfd_byte * address,
57e8b36a 13077 reloc_howto_type * howto,
07d6d2b8 13078 bfd_signed_vma increment)
98c1d4aa 13079{
98c1d4aa
NC		 13080 bfd_signed_vma addend;
13081
bd97cb95
DJ		 13082 if (howto->type == R_ARM_THM_CALL
13083 || howto->type == R_ARM_THM_JUMP24)
98c1d4aa 13084 {
9a5aca8c
AM		 13085 int upper_insn, lower_insn;
13086 int upper, lower;
98c1d4aa 13087
9a5aca8c
AM		 13088 upper_insn = bfd_get_16 (abfd, address);
13089 lower_insn = bfd_get_16 (abfd, address + 2);
13090 upper = upper_insn & 0x7ff;
13091 lower = lower_insn & 0x7ff;
13092
13093 addend = (upper << 12) | (lower << 1);
ddda4409 13094 addend += increment;
9a5aca8c 13095 addend >>= 1;
98c1d4aa 13096
9a5aca8c
AM		 13097 upper_insn = (upper_insn & 0xf800) | ((addend >> 11) & 0x7ff);
13098 lower_insn = (lower_insn & 0xf800) | (addend & 0x7ff);
13099
dc810e39
AM		 13100 bfd_put_16 (abfd, (bfd_vma) upper_insn, address);
13101 bfd_put_16 (abfd, (bfd_vma) lower_insn, address + 2);
9a5aca8c
AM		 13102 }
13103 else
13104 {
07d6d2b8 13105 bfd_vma contents;
9a5aca8c
AM		 13106
13107 contents = bfd_get_32 (abfd, address);
13108
13109 /* Get the (signed) value from the instruction. */
13110 addend = contents & howto->src_mask;
13111 if (addend & ((howto->src_mask + 1) >> 1))
13112 {
13113 bfd_signed_vma mask;
13114
13115 mask = -1;
13116 mask &= ~ howto->src_mask;
13117 addend |= mask;
13118 }
13119
13120 /* Add in the increment, (which is a byte value). */
13121 switch (howto->type)
13122 {
13123 default:
13124 addend += increment;
13125 break;
13126
13127 case R_ARM_PC24:
c6596c5e 13128 case R_ARM_PLT32:
5b5bb741
PB		 13129 case R_ARM_CALL:
13130 case R_ARM_JUMP24:
9a5aca8c 13131 addend <<= howto->size;
dc810e39 13132 addend += increment;
9a5aca8c
AM		 13133
13134 /* Should we check for overflow here ? */
13135
13136 /* Drop any undesired bits. */
13137 addend >>= howto->rightshift;
13138 break;
13139 }
13140
13141 contents = (contents & ~ howto->dst_mask) | (addend & howto->dst_mask);
13142
13143 bfd_put_32 (abfd, contents, address);
ddda4409 13144 }
98c1d4aa 13145}
252b5132 13146
ba93b8ac
DJ		 13147#define IS_ARM_TLS_RELOC(R_TYPE) \
13148 ((R_TYPE) == R_ARM_TLS_GD32 \
5c5a4843 13149 || (R_TYPE) == R_ARM_TLS_GD32_FDPIC \
ba93b8ac
DJ		 13150 || (R_TYPE) == R_ARM_TLS_LDO32 \
13151 || (R_TYPE) == R_ARM_TLS_LDM32 \
5c5a4843 13152 || (R_TYPE) == R_ARM_TLS_LDM32_FDPIC \
ba93b8ac
DJ		 13153 || (R_TYPE) == R_ARM_TLS_DTPOFF32 \
13154 || (R_TYPE) == R_ARM_TLS_DTPMOD32 \
13155 || (R_TYPE) == R_ARM_TLS_TPOFF32 \
13156 || (R_TYPE) == R_ARM_TLS_LE32 \
0855e32b 13157 || (R_TYPE) == R_ARM_TLS_IE32 \
5c5a4843 13158 || (R_TYPE) == R_ARM_TLS_IE32_FDPIC \
0855e32b
NS		 13159 || IS_ARM_TLS_GNU_RELOC (R_TYPE))
13160
13161/* Specific set of relocations for the gnu tls dialect. */
13162#define IS_ARM_TLS_GNU_RELOC(R_TYPE) \
13163 ((R_TYPE) == R_ARM_TLS_GOTDESC \
13164 || (R_TYPE) == R_ARM_TLS_CALL \
13165 || (R_TYPE) == R_ARM_THM_TLS_CALL \
13166 || (R_TYPE) == R_ARM_TLS_DESCSEQ \
13167 || (R_TYPE) == R_ARM_THM_TLS_DESCSEQ)
ba93b8ac 13168
252b5132 13169/* Relocate an ARM ELF section. */
906e58ca 13170
b34976b6 13171static bfd_boolean
07d6d2b8 13172elf32_arm_relocate_section (bfd * output_bfd,
57e8b36a 13173 struct bfd_link_info * info,
07d6d2b8
AM		 13174 bfd * input_bfd,
13175 asection * input_section,
13176 bfd_byte * contents,
13177 Elf_Internal_Rela * relocs,
13178 Elf_Internal_Sym * local_syms,
13179 asection ** local_sections)
252b5132 13180{
b34976b6
AM		 13181 Elf_Internal_Shdr *symtab_hdr;
13182 struct elf_link_hash_entry **sym_hashes;
13183 Elf_Internal_Rela *rel;
13184 Elf_Internal_Rela *relend;
13185 const char *name;
b32d3aa2 13186 struct elf32_arm_link_hash_table * globals;
252b5132 13187
4e7fd91e 13188 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 13189 if (globals == NULL)
13190 return FALSE;
b491616a 13191
0ffa91dd 13192 symtab_hdr = & elf_symtab_hdr (input_bfd);
252b5132
RH		 13193 sym_hashes = elf_sym_hashes (input_bfd);
13194
13195 rel = relocs;
13196 relend = relocs + input_section->reloc_count;
13197 for (; rel < relend; rel++)
13198 {
07d6d2b8
AM		 13199 int r_type;
13200 reloc_howto_type * howto;
13201 unsigned long r_symndx;
13202 Elf_Internal_Sym * sym;
13203 asection * sec;
252b5132 13204 struct elf_link_hash_entry * h;
07d6d2b8
AM		 13205 bfd_vma relocation;
13206 bfd_reloc_status_type r;
13207 arelent bfd_reloc;
13208 char sym_type;
13209 bfd_boolean unresolved_reloc = FALSE;
f2a9dd69 13210 char *error_message = NULL;
f21f3fe0 13211
252b5132 13212 r_symndx = ELF32_R_SYM (rel->r_info);
ba96a88f 13213 r_type = ELF32_R_TYPE (rel->r_info);
b32d3aa2 13214 r_type = arm_real_reloc_type (globals, r_type);
252b5132 13215
ba96a88f 13216 if ( r_type == R_ARM_GNU_VTENTRY
99059e56
RM		 13217 || r_type == R_ARM_GNU_VTINHERIT)
13218 continue;
252b5132 13219
47aeb64c
NC		 13220 howto = bfd_reloc.howto = elf32_arm_howto_from_type (r_type);
13221
13222 if (howto == NULL)
13223 return _bfd_unrecognized_reloc (input_bfd, input_section, r_type);
252b5132 13224
252b5132
RH		 13225 h = NULL;
13226 sym = NULL;
13227 sec = NULL;
9b485d32 13228
252b5132
RH		 13229 if (r_symndx < symtab_hdr->sh_info)
13230 {
13231 sym = local_syms + r_symndx;
ba93b8ac 13232 sym_type = ELF32_ST_TYPE (sym->st_info);
252b5132 13233 sec = local_sections[r_symndx];
ffcb4889
NS		 13234
13235 /* An object file might have a reference to a local
13236 undefined symbol. This is a daft object file, but we
13237 should at least do something about it. V4BX & NONE
13238 relocations do not use the symbol and are explicitly
77b4f08f
TS		 13239 allowed to use the undefined symbol, so allow those.
13240 Likewise for relocations against STN_UNDEF. */
ffcb4889
NS		 13241 if (r_type != R_ARM_V4BX
13242 && r_type != R_ARM_NONE
77b4f08f 13243 && r_symndx != STN_UNDEF
ffcb4889
NS		 13244 && bfd_is_und_section (sec)
13245 && ELF_ST_BIND (sym->st_info) != STB_WEAK)
1a72702b
AM		 13246 (*info->callbacks->undefined_symbol)
13247 (info, bfd_elf_string_from_elf_section
13248 (input_bfd, symtab_hdr->sh_link, sym->st_name),
13249 input_bfd, input_section,
13250 rel->r_offset, TRUE);
b38cadfb 13251
4e7fd91e 13252 if (globals->use_rel)
f8df10f4 13253 {
4e7fd91e
PB		 13254 relocation = (sec->output_section->vma
13255 + sec->output_offset
13256 + sym->st_value);
0e1862bb 13257 if (!bfd_link_relocatable (info)
ab96bf03
AM		 13258 && (sec->flags & SEC_MERGE)
13259 && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
f8df10f4 13260 {
4e7fd91e
PB		 13261 asection *msec;
13262 bfd_vma addend, value;
13263
39623e12 13264 switch (r_type)
4e7fd91e 13265 {
39623e12
PB		 13266 case R_ARM_MOVW_ABS_NC:
13267 case R_ARM_MOVT_ABS:
13268 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
13269 addend = ((value & 0xf0000) >> 4) | (value & 0xfff);
13270 addend = (addend ^ 0x8000) - 0x8000;
13271 break;
f8df10f4 13272
39623e12
PB		 13273 case R_ARM_THM_MOVW_ABS_NC:
13274 case R_ARM_THM_MOVT_ABS:
13275 value = bfd_get_16 (input_bfd, contents + rel->r_offset)
13276 << 16;
13277 value |= bfd_get_16 (input_bfd,
13278 contents + rel->r_offset + 2);
13279 addend = ((value & 0xf7000) >> 4) | (value & 0xff)
13280 | ((value & 0x04000000) >> 15);
13281 addend = (addend ^ 0x8000) - 0x8000;
13282 break;
f8df10f4 13283
39623e12
PB		 13284 default:
13285 if (howto->rightshift
13286 || (howto->src_mask & (howto->src_mask + 1)))
13287 {
4eca0228 13288 _bfd_error_handler
695344c0 13289 /* xgettext:c-format */
2dcf00ce
AM		 13290 (_("%pB(%pA+%#" PRIx64 "): "
13291 "%s relocation against SEC_MERGE section"),
39623e12 13292 input_bfd, input_section,
2dcf00ce 13293 (uint64_t) rel->r_offset, howto->name);
39623e12
PB		 13294 return FALSE;
13295 }
13296
13297 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
13298
13299 /* Get the (signed) value from the instruction. */
13300 addend = value & howto->src_mask;
13301 if (addend & ((howto->src_mask + 1) >> 1))
13302 {
13303 bfd_signed_vma mask;
13304
13305 mask = -1;
13306 mask &= ~ howto->src_mask;
13307 addend |= mask;
13308 }
13309 break;
4e7fd91e 13310 }
39623e12 13311
4e7fd91e
PB		 13312 msec = sec;
13313 addend =
13314 _bfd_elf_rel_local_sym (output_bfd, sym, &msec, addend)
13315 - relocation;
13316 addend += msec->output_section->vma + msec->output_offset;
39623e12 13317
cc643b88 13318 /* Cases here must match those in the preceding
39623e12
PB		 13319 switch statement. */
13320 switch (r_type)
13321 {
13322 case R_ARM_MOVW_ABS_NC:
13323 case R_ARM_MOVT_ABS:
13324 value = (value & 0xfff0f000) | ((addend & 0xf000) << 4)
13325 | (addend & 0xfff);
13326 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
13327 break;
13328
13329 case R_ARM_THM_MOVW_ABS_NC:
13330 case R_ARM_THM_MOVT_ABS:
13331 value = (value & 0xfbf08f00) | ((addend & 0xf700) << 4)
13332 | (addend & 0xff) | ((addend & 0x0800) << 15);
13333 bfd_put_16 (input_bfd, value >> 16,
13334 contents + rel->r_offset);
13335 bfd_put_16 (input_bfd, value,
13336 contents + rel->r_offset + 2);
13337 break;
13338
13339 default:
13340 value = (value & ~ howto->dst_mask)
13341 | (addend & howto->dst_mask);
13342 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
13343 break;
13344 }
f8df10f4 13345 }
f8df10f4 13346 }
4e7fd91e
PB		 13347 else
13348 relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
252b5132
RH		 13349 }
13350 else
13351 {
62d887d4 13352 bfd_boolean warned, ignored;
560e09e9 13353
b2a8e766
AM		 13354 RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
13355 r_symndx, symtab_hdr, sym_hashes,
13356 h, sec, relocation,
62d887d4 13357 unresolved_reloc, warned, ignored);
ba93b8ac
DJ		 13358
13359 sym_type = h->type;
252b5132
RH		 13360 }
13361
dbaa2011 13362 if (sec != NULL && discarded_section (sec))
e4067dbb 13363 RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
545fd46b 13364 rel, 1, relend, howto, 0, contents);
ab96bf03 13365
0e1862bb 13366 if (bfd_link_relocatable (info))
ab96bf03
AM		 13367 {
13368 /* This is a relocatable link. We don't have to change
13369 anything, unless the reloc is against a section symbol,
13370 in which case we have to adjust according to where the
13371 section symbol winds up in the output section. */
13372 if (sym != NULL && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
13373 {
13374 if (globals->use_rel)
13375 arm_add_to_rel (input_bfd, contents + rel->r_offset,
13376 howto, (bfd_signed_vma) sec->output_offset);
13377 else
13378 rel->r_addend += sec->output_offset;
13379 }
13380 continue;
13381 }
13382
252b5132
RH		 13383 if (h != NULL)
13384 name = h->root.root.string;
13385 else
13386 {
13387 name = (bfd_elf_string_from_elf_section
13388 (input_bfd, symtab_hdr->sh_link, sym->st_name));
13389 if (name == NULL || *name == '\0')
fd361982 13390 name = bfd_section_name (sec);
252b5132 13391 }
f21f3fe0 13392
cf35638d 13393 if (r_symndx != STN_UNDEF
ba93b8ac
DJ		 13394 && r_type != R_ARM_NONE
13395 && (h == NULL
13396 || h->root.type == bfd_link_hash_defined
13397 || h->root.type == bfd_link_hash_defweak)
13398 && IS_ARM_TLS_RELOC (r_type) != (sym_type == STT_TLS))
13399 {
4eca0228 13400 _bfd_error_handler
ba93b8ac 13401 ((sym_type == STT_TLS
695344c0 13402 /* xgettext:c-format */
2dcf00ce 13403 ? _("%pB(%pA+%#" PRIx64 "): %s used with TLS symbol %s")
695344c0 13404 /* xgettext:c-format */
2dcf00ce 13405 : _("%pB(%pA+%#" PRIx64 "): %s used with non-TLS symbol %s")),
ba93b8ac
DJ		 13406 input_bfd,
13407 input_section,
2dcf00ce 13408 (uint64_t) rel->r_offset,
ba93b8ac
DJ		 13409 howto->name,
13410 name);
13411 }
13412
0855e32b 13413 /* We call elf32_arm_final_link_relocate unless we're completely
99059e56
RM		 13414 done, i.e., the relaxation produced the final output we want,
13415 and we won't let anybody mess with it. Also, we have to do
13416 addend adjustments in case of a R_ARM_TLS_GOTDESC relocation
6a631e86 13417 both in relaxed and non-relaxed cases. */
39d911fc
TP		 13418 if ((elf32_arm_tls_transition (info, r_type, h) != (unsigned)r_type)
13419 || (IS_ARM_TLS_GNU_RELOC (r_type)
13420 && !((h ? elf32_arm_hash_entry (h)->tls_type :
13421 elf32_arm_local_got_tls_type (input_bfd)[r_symndx])
13422 & GOT_TLS_GDESC)))
13423 {
13424 r = elf32_arm_tls_relax (globals, input_bfd, input_section,
13425 contents, rel, h == NULL);
13426 /* This may have been marked unresolved because it came from
13427 a shared library. But we've just dealt with that. */
13428 unresolved_reloc = 0;
13429 }
13430 else
13431 r = bfd_reloc_continue;
b38cadfb 13432
39d911fc
TP		 13433 if (r == bfd_reloc_continue)
13434 {
13435 unsigned char branch_type =
13436 h ? ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
13437 : ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
13438
13439 r = elf32_arm_final_link_relocate (howto, input_bfd, output_bfd,
13440 input_section, contents, rel,
13441 relocation, info, sec, name,
13442 sym_type, branch_type, h,
13443 &unresolved_reloc,
13444 &error_message);
13445 }
0945cdfd
DJ		 13446
13447 /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
13448 because such sections are not SEC_ALLOC and thus ld.so will
13449 not process them. */
13450 if (unresolved_reloc
99059e56
RM		 13451 && !((input_section->flags & SEC_DEBUGGING) != 0
13452 && h->def_dynamic)
1d5316ab
AM		 13453 && _bfd_elf_section_offset (output_bfd, info, input_section,
13454 rel->r_offset) != (bfd_vma) -1)
0945cdfd 13455 {
4eca0228 13456 _bfd_error_handler
695344c0 13457 /* xgettext:c-format */
2dcf00ce
AM		 13458 (_("%pB(%pA+%#" PRIx64 "): "
13459 "unresolvable %s relocation against symbol `%s'"),
843fe662
L		 13460 input_bfd,
13461 input_section,
2dcf00ce 13462 (uint64_t) rel->r_offset,
843fe662
L		 13463 howto->name,
13464 h->root.root.string);
0945cdfd
DJ		 13465 return FALSE;
13466 }
252b5132
RH		 13467
13468 if (r != bfd_reloc_ok)
13469 {
252b5132
RH		 13470 switch (r)
13471 {
13472 case bfd_reloc_overflow:
cf919dfd
PB		 13473 /* If the overflowing reloc was to an undefined symbol,
13474 we have already printed one error message and there
13475 is no point complaining again. */
1a72702b
AM		 13476 if (!h || h->root.type != bfd_link_hash_undefined)
13477 (*info->callbacks->reloc_overflow)
13478 (info, (h ? &h->root : NULL), name, howto->name,
13479 (bfd_vma) 0, input_bfd, input_section, rel->r_offset);
252b5132
RH		 13480 break;
13481
13482 case bfd_reloc_undefined:
1a72702b
AM		 13483 (*info->callbacks->undefined_symbol)
13484 (info, name, input_bfd, input_section, rel->r_offset, TRUE);
252b5132
RH		 13485 break;
13486
13487 case bfd_reloc_outofrange:
f2a9dd69 13488 error_message = _("out of range");
252b5132
RH		 13489 goto common_error;
13490
13491 case bfd_reloc_notsupported:
f2a9dd69 13492 error_message = _("unsupported relocation");
252b5132
RH		 13493 goto common_error;
13494
13495 case bfd_reloc_dangerous:
f2a9dd69 13496 /* error_message should already be set. */
252b5132
RH		 13497 goto common_error;
13498
13499 default:
f2a9dd69 13500 error_message = _("unknown error");
8029a119 13501 /* Fall through. */
252b5132
RH		 13502
13503 common_error:
f2a9dd69 13504 BFD_ASSERT (error_message != NULL);
1a72702b
AM		 13505 (*info->callbacks->reloc_dangerous)
13506 (info, error_message, input_bfd, input_section, rel->r_offset);
252b5132
RH		 13507 break;
13508 }
13509 }
13510 }
13511
b34976b6 13512 return TRUE;
252b5132
RH		 13513}
13514
91d6fa6a 13515/* Add a new unwind edit to the list described by HEAD, TAIL. If TINDEX is zero,
2468f9c9 13516 adds the edit to the start of the list. (The list must be built in order of
91d6fa6a 13517 ascending TINDEX: the function's callers are primarily responsible for
2468f9c9
PB		 13518 maintaining that condition). */
13519
13520static void
13521add_unwind_table_edit (arm_unwind_table_edit **head,
13522 arm_unwind_table_edit **tail,
13523 arm_unwind_edit_type type,
13524 asection *linked_section,
91d6fa6a 13525 unsigned int tindex)
2468f9c9 13526{
21d799b5
NC		 13527 arm_unwind_table_edit *new_edit = (arm_unwind_table_edit *)
13528 xmalloc (sizeof (arm_unwind_table_edit));
b38cadfb 13529
2468f9c9
PB		 13530 new_edit->type = type;
13531 new_edit->linked_section = linked_section;
91d6fa6a 13532 new_edit->index = tindex;
b38cadfb 13533
91d6fa6a 13534 if (tindex > 0)
2468f9c9
PB		 13535 {
13536 new_edit->next = NULL;
13537
13538 if (*tail)
13539 (*tail)->next = new_edit;
13540
13541 (*tail) = new_edit;
13542
13543 if (!*head)
13544 (*head) = new_edit;
13545 }
13546 else
13547 {
13548 new_edit->next = *head;
13549
13550 if (!*tail)
13551 *tail = new_edit;
13552
13553 *head = new_edit;
13554 }
13555}
13556
13557static _arm_elf_section_data *get_arm_elf_section_data (asection *);
13558
13559/* Increase the size of EXIDX_SEC by ADJUST bytes. ADJUST mau be negative. */
13560static void
13561adjust_exidx_size(asection *exidx_sec, int adjust)
13562{
13563 asection *out_sec;
13564
13565 if (!exidx_sec->rawsize)
13566 exidx_sec->rawsize = exidx_sec->size;
13567
fd361982 13568 bfd_set_section_size (exidx_sec, exidx_sec->size + adjust);
2468f9c9
PB		 13569 out_sec = exidx_sec->output_section;
13570 /* Adjust size of output section. */
fd361982 13571 bfd_set_section_size (out_sec, out_sec->size +adjust);
2468f9c9
PB		 13572}
13573
13574/* Insert an EXIDX_CANTUNWIND marker at the end of a section. */
13575static void
13576insert_cantunwind_after(asection *text_sec, asection *exidx_sec)
13577{
13578 struct _arm_elf_section_data *exidx_arm_data;
13579
13580 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
13581 add_unwind_table_edit (
13582 &exidx_arm_data->u.exidx.unwind_edit_list,
13583 &exidx_arm_data->u.exidx.unwind_edit_tail,
13584 INSERT_EXIDX_CANTUNWIND_AT_END, text_sec, UINT_MAX);
13585
491d01d3
YU		 13586 exidx_arm_data->additional_reloc_count++;
13587
2468f9c9
PB		 13588 adjust_exidx_size(exidx_sec, 8);
13589}
13590
13591/* Scan .ARM.exidx tables, and create a list describing edits which should be
13592 made to those tables, such that:
b38cadfb 13593
2468f9c9
PB		 13594 1. Regions without unwind data are marked with EXIDX_CANTUNWIND entries.
13595 2. Duplicate entries are merged together (EXIDX_CANTUNWIND, or unwind
99059e56 13596 codes which have been inlined into the index).
2468f9c9 13597
85fdf906
AH		 13598 If MERGE_EXIDX_ENTRIES is false, duplicate entries are not merged.
13599
2468f9c9 13600 The edits are applied when the tables are written
b38cadfb 13601 (in elf32_arm_write_section). */
2468f9c9
PB		 13602
13603bfd_boolean
13604elf32_arm_fix_exidx_coverage (asection **text_section_order,
13605 unsigned int num_text_sections,
85fdf906
AH		 13606 struct bfd_link_info *info,
13607 bfd_boolean merge_exidx_entries)
2468f9c9
PB		 13608{
13609 bfd *inp;
13610 unsigned int last_second_word = 0, i;
13611 asection *last_exidx_sec = NULL;
13612 asection *last_text_sec = NULL;
13613 int last_unwind_type = -1;
13614
13615 /* Walk over all EXIDX sections, and create backlinks from the corrsponding
13616 text sections. */
c72f2fb2 13617 for (inp = info->input_bfds; inp != NULL; inp = inp->link.next)
2468f9c9
PB		 13618 {
13619 asection *sec;
b38cadfb 13620
2468f9c9 13621 for (sec = inp->sections; sec != NULL; sec = sec->next)
99059e56 13622 {
2468f9c9
PB		 13623 struct bfd_elf_section_data *elf_sec = elf_section_data (sec);
13624 Elf_Internal_Shdr *hdr = &elf_sec->this_hdr;
b38cadfb 13625
dec9d5df 13626 if (!hdr || hdr->sh_type != SHT_ARM_EXIDX)
2468f9c9 13627 continue;
b38cadfb 13628
2468f9c9
PB		 13629 if (elf_sec->linked_to)
13630 {
13631 Elf_Internal_Shdr *linked_hdr
99059e56 13632 = &elf_section_data (elf_sec->linked_to)->this_hdr;
2468f9c9 13633 struct _arm_elf_section_data *linked_sec_arm_data
99059e56 13634 = get_arm_elf_section_data (linked_hdr->bfd_section);
2468f9c9
PB		 13635
13636 if (linked_sec_arm_data == NULL)
99059e56 13637 continue;
2468f9c9
PB		 13638
13639 /* Link this .ARM.exidx section back from the text section it
99059e56 13640 describes. */
2468f9c9
PB		 13641 linked_sec_arm_data->u.text.arm_exidx_sec = sec;
13642 }
13643 }
13644 }
13645
13646 /* Walk all text sections in order of increasing VMA. Eilminate duplicate
13647 index table entries (EXIDX_CANTUNWIND and inlined unwind opcodes),
91d6fa6a 13648 and add EXIDX_CANTUNWIND entries for sections with no unwind table data. */
2468f9c9
PB		 13649
13650 for (i = 0; i < num_text_sections; i++)
13651 {
13652 asection *sec = text_section_order[i];
13653 asection *exidx_sec;
13654 struct _arm_elf_section_data *arm_data = get_arm_elf_section_data (sec);
13655 struct _arm_elf_section_data *exidx_arm_data;
13656 bfd_byte *contents = NULL;
13657 int deleted_exidx_bytes = 0;
13658 bfd_vma j;
13659 arm_unwind_table_edit *unwind_edit_head = NULL;
13660 arm_unwind_table_edit *unwind_edit_tail = NULL;
13661 Elf_Internal_Shdr *hdr;
13662 bfd *ibfd;
13663
13664 if (arm_data == NULL)
99059e56 13665 continue;
2468f9c9
PB		 13666
13667 exidx_sec = arm_data->u.text.arm_exidx_sec;
13668 if (exidx_sec == NULL)
13669 {
13670 /* Section has no unwind data. */
13671 if (last_unwind_type == 0 || !last_exidx_sec)
13672 continue;
13673
13674 /* Ignore zero sized sections. */
13675 if (sec->size == 0)
13676 continue;
13677
13678 insert_cantunwind_after(last_text_sec, last_exidx_sec);
13679 last_unwind_type = 0;
13680 continue;
13681 }
13682
22a8f80e
PB		 13683 /* Skip /DISCARD/ sections. */
13684 if (bfd_is_abs_section (exidx_sec->output_section))
13685 continue;
13686
2468f9c9
PB		 13687 hdr = &elf_section_data (exidx_sec)->this_hdr;
13688 if (hdr->sh_type != SHT_ARM_EXIDX)
99059e56 13689 continue;
b38cadfb 13690
2468f9c9
PB		 13691 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
13692 if (exidx_arm_data == NULL)
99059e56 13693 continue;
b38cadfb 13694
2468f9c9 13695 ibfd = exidx_sec->owner;
b38cadfb 13696
2468f9c9
PB		 13697 if (hdr->contents != NULL)
13698 contents = hdr->contents;
13699 else if (! bfd_malloc_and_get_section (ibfd, exidx_sec, &contents))
13700 /* An error? */
13701 continue;
13702
ac06903d
YU		 13703 if (last_unwind_type > 0)
13704 {
13705 unsigned int first_word = bfd_get_32 (ibfd, contents);
13706 /* Add cantunwind if first unwind item does not match section
13707 start. */
13708 if (first_word != sec->vma)
13709 {
13710 insert_cantunwind_after (last_text_sec, last_exidx_sec);
13711 last_unwind_type = 0;
13712 }
13713 }
13714
2468f9c9
PB		 13715 for (j = 0; j < hdr->sh_size; j += 8)
13716 {
13717 unsigned int second_word = bfd_get_32 (ibfd, contents + j + 4);
13718 int unwind_type;
13719 int elide = 0;
13720
13721 /* An EXIDX_CANTUNWIND entry. */
13722 if (second_word == 1)
13723 {
13724 if (last_unwind_type == 0)
13725 elide = 1;
13726 unwind_type = 0;
13727 }
13728 /* Inlined unwinding data. Merge if equal to previous. */
13729 else if ((second_word & 0x80000000) != 0)
13730 {
85fdf906
AH		 13731 if (merge_exidx_entries
13732 && last_second_word == second_word && last_unwind_type == 1)
2468f9c9
PB		 13733 elide = 1;
13734 unwind_type = 1;
13735 last_second_word = second_word;
13736 }
13737 /* Normal table entry. In theory we could merge these too,
13738 but duplicate entries are likely to be much less common. */
13739 else
13740 unwind_type = 2;
13741
491d01d3 13742 if (elide && !bfd_link_relocatable (info))
2468f9c9
PB		 13743 {
13744 add_unwind_table_edit (&unwind_edit_head, &unwind_edit_tail,
13745 DELETE_EXIDX_ENTRY, NULL, j / 8);
13746
13747 deleted_exidx_bytes += 8;
13748 }
13749
13750 last_unwind_type = unwind_type;
13751 }
13752
13753 /* Free contents if we allocated it ourselves. */
13754 if (contents != hdr->contents)
99059e56 13755 free (contents);
2468f9c9
PB		 13756
13757 /* Record edits to be applied later (in elf32_arm_write_section). */
13758 exidx_arm_data->u.exidx.unwind_edit_list = unwind_edit_head;
13759 exidx_arm_data->u.exidx.unwind_edit_tail = unwind_edit_tail;
b38cadfb 13760
2468f9c9
PB		 13761 if (deleted_exidx_bytes > 0)
13762 adjust_exidx_size(exidx_sec, -deleted_exidx_bytes);
13763
13764 last_exidx_sec = exidx_sec;
13765 last_text_sec = sec;
13766 }
13767
13768 /* Add terminating CANTUNWIND entry. */
491d01d3
YU		 13769 if (!bfd_link_relocatable (info) && last_exidx_sec
13770 && last_unwind_type != 0)
2468f9c9
PB		 13771 insert_cantunwind_after(last_text_sec, last_exidx_sec);
13772
13773 return TRUE;
13774}
13775
3e6b1042
DJ		 13776static bfd_boolean
13777elf32_arm_output_glue_section (struct bfd_link_info *info, bfd *obfd,
13778 bfd *ibfd, const char *name)
13779{
13780 asection *sec, *osec;
13781
3d4d4302 13782 sec = bfd_get_linker_section (ibfd, name);
3e6b1042
DJ		 13783 if (sec == NULL || (sec->flags & SEC_EXCLUDE) != 0)
13784 return TRUE;
13785
13786 osec = sec->output_section;
13787 if (elf32_arm_write_section (obfd, info, sec, sec->contents))
13788 return TRUE;
13789
13790 if (! bfd_set_section_contents (obfd, osec, sec->contents,
13791 sec->output_offset, sec->size))
13792 return FALSE;
13793
13794 return TRUE;
13795}
13796
13797static bfd_boolean
13798elf32_arm_final_link (bfd *abfd, struct bfd_link_info *info)
13799{
13800 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
fe33d2fa 13801 asection *sec, *osec;
3e6b1042 13802
4dfe6ac6
NC		 13803 if (globals == NULL)
13804 return FALSE;
13805
3e6b1042
DJ		 13806 /* Invoke the regular ELF backend linker to do all the work. */
13807 if (!bfd_elf_final_link (abfd, info))
13808 return FALSE;
13809
fe33d2fa
CL		 13810 /* Process stub sections (eg BE8 encoding, ...). */
13811 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
7292b3ac 13812 unsigned int i;
cdb21a0a
NS		 13813 for (i=0; i<htab->top_id; i++)
13814 {
13815 sec = htab->stub_group[i].stub_sec;
13816 /* Only process it once, in its link_sec slot. */
13817 if (sec && i == htab->stub_group[i].link_sec->id)
13818 {
13819 osec = sec->output_section;
13820 elf32_arm_write_section (abfd, info, sec, sec->contents);
13821 if (! bfd_set_section_contents (abfd, osec, sec->contents,
13822 sec->output_offset, sec->size))
13823 return FALSE;
13824 }
fe33d2fa 13825 }
fe33d2fa 13826
3e6b1042
DJ		 13827 /* Write out any glue sections now that we have created all the
13828 stubs. */
13829 if (globals->bfd_of_glue_owner != NULL)
13830 {
13831 if (! elf32_arm_output_glue_section (info, abfd,
13832 globals->bfd_of_glue_owner,
13833 ARM2THUMB_GLUE_SECTION_NAME))
13834 return FALSE;
13835
13836 if (! elf32_arm_output_glue_section (info, abfd,
13837 globals->bfd_of_glue_owner,
13838 THUMB2ARM_GLUE_SECTION_NAME))
13839 return FALSE;
13840
13841 if (! elf32_arm_output_glue_section (info, abfd,
13842 globals->bfd_of_glue_owner,
13843 VFP11_ERRATUM_VENEER_SECTION_NAME))
13844 return FALSE;
13845
a504d23a
LA		 13846 if (! elf32_arm_output_glue_section (info, abfd,
13847 globals->bfd_of_glue_owner,
13848 STM32L4XX_ERRATUM_VENEER_SECTION_NAME))
13849 return FALSE;
13850
3e6b1042
DJ		 13851 if (! elf32_arm_output_glue_section (info, abfd,
13852 globals->bfd_of_glue_owner,
13853 ARM_BX_GLUE_SECTION_NAME))
13854 return FALSE;
13855 }
13856
13857 return TRUE;
13858}
13859
5968a7b8
NC		 13860/* Return a best guess for the machine number based on the attributes. */
13861
13862static unsigned int
13863bfd_arm_get_mach_from_attributes (bfd * abfd)
13864{
13865 int arch = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_CPU_arch);
13866
13867 switch (arch)
13868 {
c0c468d5 13869 case TAG_CPU_ARCH_PRE_V4: return bfd_mach_arm_3M;
5968a7b8
NC		 13870 case TAG_CPU_ARCH_V4: return bfd_mach_arm_4;
13871 case TAG_CPU_ARCH_V4T: return bfd_mach_arm_4T;
13872 case TAG_CPU_ARCH_V5T: return bfd_mach_arm_5T;
13873
13874 case TAG_CPU_ARCH_V5TE:
13875 {
13876 char * name;
13877
13878 BFD_ASSERT (Tag_CPU_name < NUM_KNOWN_OBJ_ATTRIBUTES);
13879 name = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_CPU_name].s;
13880
13881 if (name)
13882 {
13883 if (strcmp (name, "IWMMXT2") == 0)
13884 return bfd_mach_arm_iWMMXt2;
13885
13886 if (strcmp (name, "IWMMXT") == 0)
6034aab8 13887 return bfd_mach_arm_iWMMXt;
088ca6c1
NC		 13888
13889 if (strcmp (name, "XSCALE") == 0)
13890 {
13891 int wmmx;
13892
13893 BFD_ASSERT (Tag_WMMX_arch < NUM_KNOWN_OBJ_ATTRIBUTES);
13894 wmmx = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_WMMX_arch].i;
13895 switch (wmmx)
13896 {
13897 case 1: return bfd_mach_arm_iWMMXt;
13898 case 2: return bfd_mach_arm_iWMMXt2;
13899 default: return bfd_mach_arm_XScale;
13900 }
13901 }
5968a7b8
NC		 13902 }
13903
13904 return bfd_mach_arm_5TE;
13905 }
13906
c0c468d5
TP		 13907 case TAG_CPU_ARCH_V5TEJ:
13908 return bfd_mach_arm_5TEJ;
13909 case TAG_CPU_ARCH_V6:
13910 return bfd_mach_arm_6;
13911 case TAG_CPU_ARCH_V6KZ:
13912 return bfd_mach_arm_6KZ;
13913 case TAG_CPU_ARCH_V6T2:
13914 return bfd_mach_arm_6T2;
13915 case TAG_CPU_ARCH_V6K:
13916 return bfd_mach_arm_6K;
13917 case TAG_CPU_ARCH_V7:
13918 return bfd_mach_arm_7;
13919 case TAG_CPU_ARCH_V6_M:
13920 return bfd_mach_arm_6M;
13921 case TAG_CPU_ARCH_V6S_M:
13922 return bfd_mach_arm_6SM;
13923 case TAG_CPU_ARCH_V7E_M:
13924 return bfd_mach_arm_7EM;
13925 case TAG_CPU_ARCH_V8:
13926 return bfd_mach_arm_8;
13927 case TAG_CPU_ARCH_V8R:
13928 return bfd_mach_arm_8R;
13929 case TAG_CPU_ARCH_V8M_BASE:
13930 return bfd_mach_arm_8M_BASE;
13931 case TAG_CPU_ARCH_V8M_MAIN:
13932 return bfd_mach_arm_8M_MAIN;
031254f2
AV		 13933 case TAG_CPU_ARCH_V8_1M_MAIN:
13934 return bfd_mach_arm_8_1M_MAIN;
c0c468d5 13935
5968a7b8 13936 default:
c0c468d5
TP		 13937 /* Force entry to be added for any new known Tag_CPU_arch value. */
13938 BFD_ASSERT (arch > MAX_TAG_CPU_ARCH);
13939
13940 /* Unknown Tag_CPU_arch value. */
5968a7b8
NC		 13941 return bfd_mach_arm_unknown;
13942 }
13943}
13944
c178919b
NC		 13945/* Set the right machine number. */
13946
13947static bfd_boolean
57e8b36a 13948elf32_arm_object_p (bfd *abfd)
c178919b 13949{
5a6c6817 13950 unsigned int mach;
57e8b36a 13951
5a6c6817 13952 mach = bfd_arm_get_mach_from_notes (abfd, ARM_NOTE_SECTION);
c178919b 13953
5968a7b8
NC		 13954 if (mach == bfd_mach_arm_unknown)
13955 {
13956 if (elf_elfheader (abfd)->e_flags & EF_ARM_MAVERICK_FLOAT)
13957 mach = bfd_mach_arm_ep9312;
13958 else
13959 mach = bfd_arm_get_mach_from_attributes (abfd);
13960 }
c178919b 13961
5968a7b8 13962 bfd_default_set_arch_mach (abfd, bfd_arch_arm, mach);
c178919b
NC		 13963 return TRUE;
13964}
13965
fc830a83 13966/* Function to keep ARM specific flags in the ELF header. */
3c9458e9 13967
b34976b6 13968static bfd_boolean
57e8b36a 13969elf32_arm_set_private_flags (bfd *abfd, flagword flags)
252b5132
RH		 13970{
13971 if (elf_flags_init (abfd)
13972 && elf_elfheader (abfd)->e_flags != flags)
13973 {
fc830a83
NC		 13974 if (EF_ARM_EABI_VERSION (flags) == EF_ARM_EABI_UNKNOWN)
13975 {
fd2ec330 13976 if (flags & EF_ARM_INTERWORK)
4eca0228 13977 _bfd_error_handler
90b6238f 13978 (_("warning: not setting interworking flag of %pB since it has already been specified as non-interworking"),
d003868e 13979 abfd);
fc830a83 13980 else
d003868e 13981 _bfd_error_handler
90b6238f 13982 (_("warning: clearing the interworking flag of %pB due to outside request"),
d003868e 13983 abfd);
fc830a83 13984 }
252b5132
RH		 13985 }
13986 else
13987 {
13988 elf_elfheader (abfd)->e_flags = flags;
b34976b6 13989 elf_flags_init (abfd) = TRUE;
252b5132
RH		 13990 }
13991
b34976b6 13992 return TRUE;
252b5132
RH		 13993}
13994
fc830a83 13995/* Copy backend specific data from one object module to another. */
9b485d32 13996
b34976b6 13997static bfd_boolean
57e8b36a 13998elf32_arm_copy_private_bfd_data (bfd *ibfd, bfd *obfd)
252b5132
RH		 13999{
14000 flagword in_flags;
14001 flagword out_flags;
14002
0ffa91dd 14003 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
b34976b6 14004 return TRUE;
252b5132 14005
fc830a83 14006 in_flags = elf_elfheader (ibfd)->e_flags;
252b5132
RH		 14007 out_flags = elf_elfheader (obfd)->e_flags;
14008
fc830a83
NC		 14009 if (elf_flags_init (obfd)
14010 && EF_ARM_EABI_VERSION (out_flags) == EF_ARM_EABI_UNKNOWN
14011 && in_flags != out_flags)
252b5132 14012 {
252b5132 14013 /* Cannot mix APCS26 and APCS32 code. */
fd2ec330 14014 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
b34976b6 14015 return FALSE;
252b5132
RH		 14016
14017 /* Cannot mix float APCS and non-float APCS code. */
fd2ec330 14018 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
b34976b6 14019 return FALSE;
252b5132
RH		 14020
14021 /* If the src and dest have different interworking flags
99059e56 14022 then turn off the interworking bit. */
fd2ec330 14023 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
252b5132 14024 {
fd2ec330 14025 if (out_flags & EF_ARM_INTERWORK)
d003868e 14026 _bfd_error_handler
90b6238f 14027 (_("warning: clearing the interworking flag of %pB because non-interworking code in %pB has been linked with it"),
d003868e 14028 obfd, ibfd);
252b5132 14029
fd2ec330 14030 in_flags &= ~EF_ARM_INTERWORK;
252b5132 14031 }
1006ba19
PB		 14032
14033 /* Likewise for PIC, though don't warn for this case. */
fd2ec330
PB		 14034 if ((in_flags & EF_ARM_PIC) != (out_flags & EF_ARM_PIC))
14035 in_flags &= ~EF_ARM_PIC;
252b5132
RH		 14036 }
14037
14038 elf_elfheader (obfd)->e_flags = in_flags;
b34976b6 14039 elf_flags_init (obfd) = TRUE;
252b5132 14040
e2349352 14041 return _bfd_elf_copy_private_bfd_data (ibfd, obfd);
ee065d83
PB		 14042}
14043
14044/* Values for Tag_ABI_PCS_R9_use. */
14045enum
14046{
14047 AEABI_R9_V6,
14048 AEABI_R9_SB,
14049 AEABI_R9_TLS,
14050 AEABI_R9_unused
14051};
14052
14053/* Values for Tag_ABI_PCS_RW_data. */
14054enum
14055{
14056 AEABI_PCS_RW_data_absolute,
14057 AEABI_PCS_RW_data_PCrel,
14058 AEABI_PCS_RW_data_SBrel,
14059 AEABI_PCS_RW_data_unused
14060};
14061
14062/* Values for Tag_ABI_enum_size. */
14063enum
14064{
14065 AEABI_enum_unused,
14066 AEABI_enum_short,
14067 AEABI_enum_wide,
14068 AEABI_enum_forced_wide
14069};
14070
104d59d1
JM		 14071/* Determine whether an object attribute tag takes an integer, a
14072 string or both. */
906e58ca 14073
104d59d1
JM		 14074static int
14075elf32_arm_obj_attrs_arg_type (int tag)
14076{
14077 if (tag == Tag_compatibility)
3483fe2e 14078 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_STR_VAL;
2d0bb761 14079 else if (tag == Tag_nodefaults)
3483fe2e
AS		 14080 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_NO_DEFAULT;
14081 else if (tag == Tag_CPU_raw_name || tag == Tag_CPU_name)
14082 return ATTR_TYPE_FLAG_STR_VAL;
104d59d1 14083 else if (tag < 32)
3483fe2e 14084 return ATTR_TYPE_FLAG_INT_VAL;
104d59d1 14085 else
3483fe2e 14086 return (tag & 1) != 0 ? ATTR_TYPE_FLAG_STR_VAL : ATTR_TYPE_FLAG_INT_VAL;
104d59d1
JM		 14087}
14088
5aa6ff7c
AS		 14089/* The ABI defines that Tag_conformance should be emitted first, and that
14090 Tag_nodefaults should be second (if either is defined). This sets those
14091 two positions, and bumps up the position of all the remaining tags to
14092 compensate. */
14093static int
14094elf32_arm_obj_attrs_order (int num)
14095{
3de4a297 14096 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE)
5aa6ff7c 14097 return Tag_conformance;
3de4a297 14098 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE + 1)
5aa6ff7c
AS		 14099 return Tag_nodefaults;
14100 if ((num - 2) < Tag_nodefaults)
14101 return num - 2;
14102 if ((num - 1) < Tag_conformance)
14103 return num - 1;
14104 return num;
14105}
14106
e8b36cd1
JM		 14107/* Attribute numbers >=64 (mod 128) can be safely ignored. */
14108static bfd_boolean
14109elf32_arm_obj_attrs_handle_unknown (bfd *abfd, int tag)
14110{
14111 if ((tag & 127) < 64)
14112 {
14113 _bfd_error_handler
90b6238f 14114 (_("%pB: unknown mandatory EABI object attribute %d"),
e8b36cd1
JM		 14115 abfd, tag);
14116 bfd_set_error (bfd_error_bad_value);
14117 return FALSE;
14118 }
14119 else
14120 {
14121 _bfd_error_handler
90b6238f 14122 (_("warning: %pB: unknown EABI object attribute %d"),
e8b36cd1
JM		 14123 abfd, tag);
14124 return TRUE;
14125 }
14126}
14127
91e22acd
AS		 14128/* Read the architecture from the Tag_also_compatible_with attribute, if any.
14129 Returns -1 if no architecture could be read. */
14130
14131static int
14132get_secondary_compatible_arch (bfd *abfd)
14133{
14134 obj_attribute *attr =
14135 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
14136
14137 /* Note: the tag and its argument below are uleb128 values, though
14138 currently-defined values fit in one byte for each. */
14139 if (attr->s
14140 && attr->s[0] == Tag_CPU_arch
14141 && (attr->s[1] & 128) != 128
14142 && attr->s[2] == 0)
14143 return attr->s[1];
14144
14145 /* This tag is "safely ignorable", so don't complain if it looks funny. */
14146 return -1;
14147}
14148
14149/* Set, or unset, the architecture of the Tag_also_compatible_with attribute.
14150 The tag is removed if ARCH is -1. */
14151
8e79c3df 14152static void
91e22acd 14153set_secondary_compatible_arch (bfd *abfd, int arch)
8e79c3df 14154{
91e22acd
AS		 14155 obj_attribute *attr =
14156 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
8e79c3df 14157
91e22acd
AS		 14158 if (arch == -1)
14159 {
14160 attr->s = NULL;
14161 return;
8e79c3df 14162 }
91e22acd
AS		 14163
14164 /* Note: the tag and its argument below are uleb128 values, though
14165 currently-defined values fit in one byte for each. */
14166 if (!attr->s)
21d799b5 14167 attr->s = (char *) bfd_alloc (abfd, 3);
91e22acd
AS		 14168 attr->s[0] = Tag_CPU_arch;
14169 attr->s[1] = arch;
14170 attr->s[2] = '\0';
8e79c3df
CM		 14171}
14172
91e22acd
AS		 14173/* Combine two values for Tag_CPU_arch, taking secondary compatibility tags
14174 into account. */
14175
14176static int
14177tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
14178 int newtag, int secondary_compat)
8e79c3df 14179{
91e22acd
AS		 14180#define T(X) TAG_CPU_ARCH_##X
14181 int tagl, tagh, result;
14182 const int v6t2[] =
14183 {
14184 T(V6T2), /* PRE_V4. */
14185 T(V6T2), /* V4. */
14186 T(V6T2), /* V4T. */
14187 T(V6T2), /* V5T. */
14188 T(V6T2), /* V5TE. */
14189 T(V6T2), /* V5TEJ. */
14190 T(V6T2), /* V6. */
14191 T(V7), /* V6KZ. */
14192 T(V6T2) /* V6T2. */
14193 };
14194 const int v6k[] =
14195 {
14196 T(V6K), /* PRE_V4. */
14197 T(V6K), /* V4. */
14198 T(V6K), /* V4T. */
14199 T(V6K), /* V5T. */
14200 T(V6K), /* V5TE. */
14201 T(V6K), /* V5TEJ. */
14202 T(V6K), /* V6. */
14203 T(V6KZ), /* V6KZ. */
14204 T(V7), /* V6T2. */
14205 T(V6K) /* V6K. */
14206 };
14207 const int v7[] =
14208 {
14209 T(V7), /* PRE_V4. */
14210 T(V7), /* V4. */
14211 T(V7), /* V4T. */
14212 T(V7), /* V5T. */
14213 T(V7), /* V5TE. */
14214 T(V7), /* V5TEJ. */
14215 T(V7), /* V6. */
14216 T(V7), /* V6KZ. */
14217 T(V7), /* V6T2. */
14218 T(V7), /* V6K. */
14219 T(V7) /* V7. */
14220 };
14221 const int v6_m[] =
14222 {
07d6d2b8
AM		 14223 -1, /* PRE_V4. */
14224 -1, /* V4. */
91e22acd
AS		 14225 T(V6K), /* V4T. */
14226 T(V6K), /* V5T. */
14227 T(V6K), /* V5TE. */
14228 T(V6K), /* V5TEJ. */
14229 T(V6K), /* V6. */
14230 T(V6KZ), /* V6KZ. */
14231 T(V7), /* V6T2. */
14232 T(V6K), /* V6K. */
14233 T(V7), /* V7. */
14234 T(V6_M) /* V6_M. */
14235 };
14236 const int v6s_m[] =
14237 {
07d6d2b8
AM		 14238 -1, /* PRE_V4. */
14239 -1, /* V4. */
91e22acd
AS		 14240 T(V6K), /* V4T. */
14241 T(V6K), /* V5T. */
14242 T(V6K), /* V5TE. */
14243 T(V6K), /* V5TEJ. */
14244 T(V6K), /* V6. */
14245 T(V6KZ), /* V6KZ. */
14246 T(V7), /* V6T2. */
14247 T(V6K), /* V6K. */
14248 T(V7), /* V7. */
14249 T(V6S_M), /* V6_M. */
14250 T(V6S_M) /* V6S_M. */
14251 };
9e3c6df6
PB		 14252 const int v7e_m[] =
14253 {
07d6d2b8
AM		 14254 -1, /* PRE_V4. */
14255 -1, /* V4. */
9e3c6df6
PB		 14256 T(V7E_M), /* V4T. */
14257 T(V7E_M), /* V5T. */
14258 T(V7E_M), /* V5TE. */
14259 T(V7E_M), /* V5TEJ. */
14260 T(V7E_M), /* V6. */
14261 T(V7E_M), /* V6KZ. */
14262 T(V7E_M), /* V6T2. */
14263 T(V7E_M), /* V6K. */
14264 T(V7E_M), /* V7. */
14265 T(V7E_M), /* V6_M. */
14266 T(V7E_M), /* V6S_M. */
14267 T(V7E_M) /* V7E_M. */
14268 };
bca38921
MGD		 14269 const int v8[] =
14270 {
14271 T(V8), /* PRE_V4. */
14272 T(V8), /* V4. */
14273 T(V8), /* V4T. */
14274 T(V8), /* V5T. */
14275 T(V8), /* V5TE. */
14276 T(V8), /* V5TEJ. */
14277 T(V8), /* V6. */
14278 T(V8), /* V6KZ. */
14279 T(V8), /* V6T2. */
14280 T(V8), /* V6K. */
14281 T(V8), /* V7. */
14282 T(V8), /* V6_M. */
14283 T(V8), /* V6S_M. */
14284 T(V8), /* V7E_M. */
14285 T(V8) /* V8. */
14286 };
bff0500d
TP		 14287 const int v8r[] =
14288 {
14289 T(V8R), /* PRE_V4. */
14290 T(V8R), /* V4. */
14291 T(V8R), /* V4T. */
14292 T(V8R), /* V5T. */
14293 T(V8R), /* V5TE. */
14294 T(V8R), /* V5TEJ. */
14295 T(V8R), /* V6. */
14296 T(V8R), /* V6KZ. */
14297 T(V8R), /* V6T2. */
14298 T(V8R), /* V6K. */
14299 T(V8R), /* V7. */
14300 T(V8R), /* V6_M. */
14301 T(V8R), /* V6S_M. */
14302 T(V8R), /* V7E_M. */
14303 T(V8), /* V8. */
14304 T(V8R), /* V8R. */
14305 };
2fd158eb
TP		 14306 const int v8m_baseline[] =
14307 {
14308 -1, /* PRE_V4. */
14309 -1, /* V4. */
14310 -1, /* V4T. */
14311 -1, /* V5T. */
14312 -1, /* V5TE. */
14313 -1, /* V5TEJ. */
14314 -1, /* V6. */
14315 -1, /* V6KZ. */
14316 -1, /* V6T2. */
14317 -1, /* V6K. */
14318 -1, /* V7. */
14319 T(V8M_BASE), /* V6_M. */
14320 T(V8M_BASE), /* V6S_M. */
14321 -1, /* V7E_M. */
14322 -1, /* V8. */
bff0500d 14323 -1, /* V8R. */
2fd158eb
TP		 14324 T(V8M_BASE) /* V8-M BASELINE. */
14325 };
14326 const int v8m_mainline[] =
14327 {
14328 -1, /* PRE_V4. */
14329 -1, /* V4. */
14330 -1, /* V4T. */
14331 -1, /* V5T. */
14332 -1, /* V5TE. */
14333 -1, /* V5TEJ. */
14334 -1, /* V6. */
14335 -1, /* V6KZ. */
14336 -1, /* V6T2. */
14337 -1, /* V6K. */
14338 T(V8M_MAIN), /* V7. */
14339 T(V8M_MAIN), /* V6_M. */
14340 T(V8M_MAIN), /* V6S_M. */
14341 T(V8M_MAIN), /* V7E_M. */
14342 -1, /* V8. */
bff0500d 14343 -1, /* V8R. */
2fd158eb
TP		 14344 T(V8M_MAIN), /* V8-M BASELINE. */
14345 T(V8M_MAIN) /* V8-M MAINLINE. */
14346 };
031254f2
AV		 14347 const int v8_1m_mainline[] =
14348 {
14349 -1, /* PRE_V4. */
14350 -1, /* V4. */
14351 -1, /* V4T. */
14352 -1, /* V5T. */
14353 -1, /* V5TE. */
14354 -1, /* V5TEJ. */
14355 -1, /* V6. */
14356 -1, /* V6KZ. */
14357 -1, /* V6T2. */
14358 -1, /* V6K. */
14359 T(V8_1M_MAIN), /* V7. */
14360 T(V8_1M_MAIN), /* V6_M. */
14361 T(V8_1M_MAIN), /* V6S_M. */
14362 T(V8_1M_MAIN), /* V7E_M. */
14363 -1, /* V8. */
14364 -1, /* V8R. */
14365 T(V8_1M_MAIN), /* V8-M BASELINE. */
14366 T(V8_1M_MAIN), /* V8-M MAINLINE. */
14367 -1, /* Unused (18). */
14368 -1, /* Unused (19). */
14369 -1, /* Unused (20). */
14370 T(V8_1M_MAIN) /* V8.1-M MAINLINE. */
14371 };
91e22acd
AS		 14372 const int v4t_plus_v6_m[] =
14373 {
14374 -1, /* PRE_V4. */
14375 -1, /* V4. */
14376 T(V4T), /* V4T. */
14377 T(V5T), /* V5T. */
14378 T(V5TE), /* V5TE. */
14379 T(V5TEJ), /* V5TEJ. */
14380 T(V6), /* V6. */
14381 T(V6KZ), /* V6KZ. */
14382 T(V6T2), /* V6T2. */
14383 T(V6K), /* V6K. */
14384 T(V7), /* V7. */
14385 T(V6_M), /* V6_M. */
14386 T(V6S_M), /* V6S_M. */
9e3c6df6 14387 T(V7E_M), /* V7E_M. */
bca38921 14388 T(V8), /* V8. */
bff0500d 14389 -1, /* V8R. */
2fd158eb
TP		 14390 T(V8M_BASE), /* V8-M BASELINE. */
14391 T(V8M_MAIN), /* V8-M MAINLINE. */
031254f2
AV		 14392 -1, /* Unused (18). */
14393 -1, /* Unused (19). */
14394 -1, /* Unused (20). */
14395 T(V8_1M_MAIN), /* V8.1-M MAINLINE. */
91e22acd
AS		 14396 T(V4T_PLUS_V6_M) /* V4T plus V6_M. */
14397 };
14398 const int *comb[] =
14399 {
14400 v6t2,
14401 v6k,
14402 v7,
14403 v6_m,
14404 v6s_m,
9e3c6df6 14405 v7e_m,
bca38921 14406 v8,
bff0500d 14407 v8r,
2fd158eb
TP		 14408 v8m_baseline,
14409 v8m_mainline,
031254f2
AV		 14410 NULL,
14411 NULL,
14412 NULL,
14413 v8_1m_mainline,
91e22acd
AS		 14414 /* Pseudo-architecture. */
14415 v4t_plus_v6_m
14416 };
14417
14418 /* Check we've not got a higher architecture than we know about. */
14419
9e3c6df6 14420 if (oldtag > MAX_TAG_CPU_ARCH || newtag > MAX_TAG_CPU_ARCH)
91e22acd 14421 {
90b6238f 14422 _bfd_error_handler (_("error: %pB: unknown CPU architecture"), ibfd);
91e22acd
AS		 14423 return -1;
14424 }
14425
14426 /* Override old tag if we have a Tag_also_compatible_with on the output. */
14427
14428 if ((oldtag == T(V6_M) && *secondary_compat_out == T(V4T))
14429 || (oldtag == T(V4T) && *secondary_compat_out == T(V6_M)))
14430 oldtag = T(V4T_PLUS_V6_M);
14431
14432 /* And override the new tag if we have a Tag_also_compatible_with on the
14433 input. */
14434
14435 if ((newtag == T(V6_M) && secondary_compat == T(V4T))
14436 || (newtag == T(V4T) && secondary_compat == T(V6_M)))
14437 newtag = T(V4T_PLUS_V6_M);
14438
14439 tagl = (oldtag < newtag) ? oldtag : newtag;
14440 result = tagh = (oldtag > newtag) ? oldtag : newtag;
14441
14442 /* Architectures before V6KZ add features monotonically. */
14443 if (tagh <= TAG_CPU_ARCH_V6KZ)
14444 return result;
14445
4ed7ed8d 14446 result = comb[tagh - T(V6T2)] ? comb[tagh - T(V6T2)][tagl] : -1;
91e22acd
AS		 14447
14448 /* Use Tag_CPU_arch == V4T and Tag_also_compatible_with (Tag_CPU_arch V6_M)
14449 as the canonical version. */
14450 if (result == T(V4T_PLUS_V6_M))
14451 {
14452 result = T(V4T);
14453 *secondary_compat_out = T(V6_M);
14454 }
14455 else
14456 *secondary_compat_out = -1;
14457
14458 if (result == -1)
14459 {
90b6238f 14460 _bfd_error_handler (_("error: %pB: conflicting CPU architectures %d/%d"),
91e22acd
AS		 14461 ibfd, oldtag, newtag);
14462 return -1;
14463 }
14464
14465 return result;
14466#undef T
8e79c3df
CM		 14467}
14468
ac56ee8f
MGD		 14469/* Query attributes object to see if integer divide instructions may be
14470 present in an object. */
14471static bfd_boolean
14472elf32_arm_attributes_accept_div (const obj_attribute *attr)
14473{
14474 int arch = attr[Tag_CPU_arch].i;
14475 int profile = attr[Tag_CPU_arch_profile].i;
14476
14477 switch (attr[Tag_DIV_use].i)
14478 {
14479 case 0:
14480 /* Integer divide allowed if instruction contained in archetecture. */
14481 if (arch == TAG_CPU_ARCH_V7 && (profile == 'R' || profile == 'M'))
14482 return TRUE;
14483 else if (arch >= TAG_CPU_ARCH_V7E_M)
14484 return TRUE;
14485 else
14486 return FALSE;
14487
14488 case 1:
14489 /* Integer divide explicitly prohibited. */
14490 return FALSE;
14491
14492 default:
14493 /* Unrecognised case - treat as allowing divide everywhere. */
14494 case 2:
14495 /* Integer divide allowed in ARM state. */
14496 return TRUE;
14497 }
14498}
14499
14500/* Query attributes object to see if integer divide instructions are
14501 forbidden to be in the object. This is not the inverse of
14502 elf32_arm_attributes_accept_div. */
14503static bfd_boolean
14504elf32_arm_attributes_forbid_div (const obj_attribute *attr)
14505{
14506 return attr[Tag_DIV_use].i == 1;
14507}
14508
ee065d83
PB		 14509/* Merge EABI object attributes from IBFD into OBFD. Raise an error if there
14510 are conflicting attributes. */
906e58ca 14511
ee065d83 14512static bfd_boolean
50e03d47 14513elf32_arm_merge_eabi_attributes (bfd *ibfd, struct bfd_link_info *info)
ee065d83 14514{
50e03d47 14515 bfd *obfd = info->output_bfd;
104d59d1
JM		 14516 obj_attribute *in_attr;
14517 obj_attribute *out_attr;
ee065d83
PB		 14518 /* Some tags have 0 = don't care, 1 = strong requirement,
14519 2 = weak requirement. */
91e22acd 14520 static const int order_021[3] = {0, 2, 1};
ee065d83 14521 int i;
91e22acd 14522 bfd_boolean result = TRUE;
9274e9de 14523 const char *sec_name = get_elf_backend_data (ibfd)->obj_attrs_section;
ee065d83 14524
3e6b1042
DJ		 14525 /* Skip the linker stubs file. This preserves previous behavior
14526 of accepting unknown attributes in the first input file - but
14527 is that a bug? */
14528 if (ibfd->flags & BFD_LINKER_CREATED)
14529 return TRUE;
14530
9274e9de
TG		 14531 /* Skip any input that hasn't attribute section.
14532 This enables to link object files without attribute section with
14533 any others. */
14534 if (bfd_get_section_by_name (ibfd, sec_name) == NULL)
14535 return TRUE;
14536
104d59d1 14537 if (!elf_known_obj_attributes_proc (obfd)[0].i)
ee065d83
PB		 14538 {
14539 /* This is the first object. Copy the attributes. */
104d59d1 14540 _bfd_elf_copy_obj_attributes (ibfd, obfd);
004ae526 14541
cd21e546
MGD		 14542 out_attr = elf_known_obj_attributes_proc (obfd);
14543
004ae526
PB		 14544 /* Use the Tag_null value to indicate the attributes have been
14545 initialized. */
cd21e546 14546 out_attr[0].i = 1;
004ae526 14547
cd21e546
MGD		 14548 /* We do not output objects with Tag_MPextension_use_legacy - we move
14549 the attribute's value to Tag_MPextension_use. */
14550 if (out_attr[Tag_MPextension_use_legacy].i != 0)
14551 {
14552 if (out_attr[Tag_MPextension_use].i != 0
14553 && out_attr[Tag_MPextension_use_legacy].i
99059e56 14554 != out_attr[Tag_MPextension_use].i)
cd21e546
MGD		 14555 {
14556 _bfd_error_handler
871b3ab2 14557 (_("Error: %pB has both the current and legacy "
cd21e546
MGD		 14558 "Tag_MPextension_use attributes"), ibfd);
14559 result = FALSE;
14560 }
14561
14562 out_attr[Tag_MPextension_use] =
14563 out_attr[Tag_MPextension_use_legacy];
14564 out_attr[Tag_MPextension_use_legacy].type = 0;
14565 out_attr[Tag_MPextension_use_legacy].i = 0;
14566 }
14567
14568 return result;
ee065d83
PB		 14569 }
14570
104d59d1
JM		 14571 in_attr = elf_known_obj_attributes_proc (ibfd);
14572 out_attr = elf_known_obj_attributes_proc (obfd);
ee065d83
PB		 14573 /* This needs to happen before Tag_ABI_FP_number_model is merged. */
14574 if (in_attr[Tag_ABI_VFP_args].i != out_attr[Tag_ABI_VFP_args].i)
14575 {
5c294fee
TG		 14576 /* Ignore mismatches if the object doesn't use floating point or is
14577 floating point ABI independent. */
14578 if (out_attr[Tag_ABI_FP_number_model].i == AEABI_FP_number_model_none
14579 || (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
14580 && out_attr[Tag_ABI_VFP_args].i == AEABI_VFP_args_compatible))
ee065d83 14581 out_attr[Tag_ABI_VFP_args].i = in_attr[Tag_ABI_VFP_args].i;
5c294fee
TG		 14582 else if (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
14583 && in_attr[Tag_ABI_VFP_args].i != AEABI_VFP_args_compatible)
ee065d83
PB		 14584 {
14585 _bfd_error_handler
871b3ab2 14586 (_("error: %pB uses VFP register arguments, %pB does not"),
deddc40b
NS		 14587 in_attr[Tag_ABI_VFP_args].i ? ibfd : obfd,
14588 in_attr[Tag_ABI_VFP_args].i ? obfd : ibfd);
91e22acd 14589 result = FALSE;
ee065d83
PB		 14590 }
14591 }
14592
3de4a297 14593 for (i = LEAST_KNOWN_OBJ_ATTRIBUTE; i < NUM_KNOWN_OBJ_ATTRIBUTES; i++)
ee065d83
PB		 14594 {
14595 /* Merge this attribute with existing attributes. */
14596 switch (i)
14597 {
14598 case Tag_CPU_raw_name:
14599 case Tag_CPU_name:
6a631e86 14600 /* These are merged after Tag_CPU_arch. */
ee065d83
PB		 14601 break;
14602
14603 case Tag_ABI_optimization_goals:
14604 case Tag_ABI_FP_optimization_goals:
14605 /* Use the first value seen. */
14606 break;
14607
14608 case Tag_CPU_arch:
91e22acd
AS		 14609 {
14610 int secondary_compat = -1, secondary_compat_out = -1;
14611 unsigned int saved_out_attr = out_attr[i].i;
70e99720
TG		 14612 int arch_attr;
14613 static const char *name_table[] =
14614 {
91e22acd
AS		 14615 /* These aren't real CPU names, but we can't guess
14616 that from the architecture version alone. */
14617 "Pre v4",
14618 "ARM v4",
14619 "ARM v4T",
14620 "ARM v5T",
14621 "ARM v5TE",
14622 "ARM v5TEJ",
14623 "ARM v6",
14624 "ARM v6KZ",
14625 "ARM v6T2",
14626 "ARM v6K",
14627 "ARM v7",
14628 "ARM v6-M",
bca38921 14629 "ARM v6S-M",
2fd158eb
TP		 14630 "ARM v8",
14631 "",
14632 "ARM v8-M.baseline",
14633 "ARM v8-M.mainline",
91e22acd
AS		 14634 };
14635
14636 /* Merge Tag_CPU_arch and Tag_also_compatible_with. */
14637 secondary_compat = get_secondary_compatible_arch (ibfd);
14638 secondary_compat_out = get_secondary_compatible_arch (obfd);
70e99720
TG		 14639 arch_attr = tag_cpu_arch_combine (ibfd, out_attr[i].i,
14640 &secondary_compat_out,
14641 in_attr[i].i,
14642 secondary_compat);
14643
14644 /* Return with error if failed to merge. */
14645 if (arch_attr == -1)
14646 return FALSE;
14647
14648 out_attr[i].i = arch_attr;
14649
91e22acd
AS		 14650 set_secondary_compatible_arch (obfd, secondary_compat_out);
14651
14652 /* Merge Tag_CPU_name and Tag_CPU_raw_name. */
14653 if (out_attr[i].i == saved_out_attr)
14654 ; /* Leave the names alone. */
14655 else if (out_attr[i].i == in_attr[i].i)
14656 {
14657 /* The output architecture has been changed to match the
14658 input architecture. Use the input names. */
14659 out_attr[Tag_CPU_name].s = in_attr[Tag_CPU_name].s
14660 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_name].s)
14661 : NULL;
14662 out_attr[Tag_CPU_raw_name].s = in_attr[Tag_CPU_raw_name].s
14663 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_raw_name].s)
14664 : NULL;
14665 }
14666 else
14667 {
14668 out_attr[Tag_CPU_name].s = NULL;
14669 out_attr[Tag_CPU_raw_name].s = NULL;
14670 }
14671
14672 /* If we still don't have a value for Tag_CPU_name,
14673 make one up now. Tag_CPU_raw_name remains blank. */
14674 if (out_attr[Tag_CPU_name].s == NULL
14675 && out_attr[i].i < ARRAY_SIZE (name_table))
14676 out_attr[Tag_CPU_name].s =
14677 _bfd_elf_attr_strdup (obfd, name_table[out_attr[i].i]);
14678 }
14679 break;
14680
ee065d83
PB		 14681 case Tag_ARM_ISA_use:
14682 case Tag_THUMB_ISA_use:
ee065d83 14683 case Tag_WMMX_arch:
91e22acd
AS		 14684 case Tag_Advanced_SIMD_arch:
14685 /* ??? Do Advanced_SIMD (NEON) and WMMX conflict? */
ee065d83 14686 case Tag_ABI_FP_rounding:
ee065d83
PB		 14687 case Tag_ABI_FP_exceptions:
14688 case Tag_ABI_FP_user_exceptions:
14689 case Tag_ABI_FP_number_model:
75375b3e 14690 case Tag_FP_HP_extension:
91e22acd
AS		 14691 case Tag_CPU_unaligned_access:
14692 case Tag_T2EE_use:
91e22acd 14693 case Tag_MPextension_use:
a7ad558c 14694 case Tag_MVE_arch:
ee065d83
PB		 14695 /* Use the largest value specified. */
14696 if (in_attr[i].i > out_attr[i].i)
14697 out_attr[i].i = in_attr[i].i;
14698 break;
14699
75375b3e 14700 case Tag_ABI_align_preserved:
91e22acd
AS		 14701 case Tag_ABI_PCS_RO_data:
14702 /* Use the smallest value specified. */
14703 if (in_attr[i].i < out_attr[i].i)
14704 out_attr[i].i = in_attr[i].i;
14705 break;
14706
75375b3e 14707 case Tag_ABI_align_needed:
91e22acd 14708 if ((in_attr[i].i > 0 || out_attr[i].i > 0)
75375b3e
MGD		 14709 && (in_attr[Tag_ABI_align_preserved].i == 0
14710 || out_attr[Tag_ABI_align_preserved].i == 0))
ee065d83 14711 {
91e22acd
AS		 14712 /* This error message should be enabled once all non-conformant
14713 binaries in the toolchain have had the attributes set
14714 properly.
ee065d83 14715 _bfd_error_handler
871b3ab2 14716 (_("error: %pB: 8-byte data alignment conflicts with %pB"),
91e22acd
AS		 14717 obfd, ibfd);
14718 result = FALSE; */
ee065d83 14719 }
91e22acd
AS		 14720 /* Fall through. */
14721 case Tag_ABI_FP_denormal:
14722 case Tag_ABI_PCS_GOT_use:
14723 /* Use the "greatest" from the sequence 0, 2, 1, or the largest
14724 value if greater than 2 (for future-proofing). */
14725 if ((in_attr[i].i > 2 && in_attr[i].i > out_attr[i].i)
14726 || (in_attr[i].i <= 2 && out_attr[i].i <= 2
14727 && order_021[in_attr[i].i] > order_021[out_attr[i].i]))
ee065d83
PB		 14728 out_attr[i].i = in_attr[i].i;
14729 break;
91e22acd 14730
75375b3e
MGD		 14731 case Tag_Virtualization_use:
14732 /* The virtualization tag effectively stores two bits of
14733 information: the intended use of TrustZone (in bit 0), and the
14734 intended use of Virtualization (in bit 1). */
14735 if (out_attr[i].i == 0)
14736 out_attr[i].i = in_attr[i].i;
14737 else if (in_attr[i].i != 0
14738 && in_attr[i].i != out_attr[i].i)
14739 {
14740 if (in_attr[i].i <= 3 && out_attr[i].i <= 3)
14741 out_attr[i].i = 3;
14742 else
14743 {
14744 _bfd_error_handler
871b3ab2
AM		 14745 (_("error: %pB: unable to merge virtualization attributes "
14746 "with %pB"),
75375b3e
MGD		 14747 obfd, ibfd);
14748 result = FALSE;
14749 }
14750 }
14751 break;
91e22acd
AS		 14752
14753 case Tag_CPU_arch_profile:
14754 if (out_attr[i].i != in_attr[i].i)
14755 {
14756 /* 0 will merge with anything.
14757 'A' and 'S' merge to 'A'.
14758 'R' and 'S' merge to 'R'.
99059e56 14759 'M' and 'A|R|S' is an error. */
91e22acd
AS		 14760 if (out_attr[i].i == 0
14761 || (out_attr[i].i == 'S'
14762 && (in_attr[i].i == 'A' || in_attr[i].i == 'R')))
14763 out_attr[i].i = in_attr[i].i;
14764 else if (in_attr[i].i == 0
14765 || (in_attr[i].i == 'S'
14766 && (out_attr[i].i == 'A' || out_attr[i].i == 'R')))
6a631e86 14767 ; /* Do nothing. */
91e22acd
AS		 14768 else
14769 {
14770 _bfd_error_handler
90b6238f 14771 (_("error: %pB: conflicting architecture profiles %c/%c"),
91e22acd
AS		 14772 ibfd,
14773 in_attr[i].i ? in_attr[i].i : '0',
14774 out_attr[i].i ? out_attr[i].i : '0');
14775 result = FALSE;
14776 }
14777 }
14778 break;
15afaa63
TP		 14779
14780 case Tag_DSP_extension:
14781 /* No need to change output value if any of:
14782 - pre (<=) ARMv5T input architecture (do not have DSP)
14783 - M input profile not ARMv7E-M and do not have DSP. */
14784 if (in_attr[Tag_CPU_arch].i <= 3
14785 || (in_attr[Tag_CPU_arch_profile].i == 'M'
14786 && in_attr[Tag_CPU_arch].i != 13
14787 && in_attr[i].i == 0))
14788 ; /* Do nothing. */
14789 /* Output value should be 0 if DSP part of architecture, ie.
14790 - post (>=) ARMv5te architecture output
14791 - A, R or S profile output or ARMv7E-M output architecture. */
14792 else if (out_attr[Tag_CPU_arch].i >= 4
14793 && (out_attr[Tag_CPU_arch_profile].i == 'A'
14794 || out_attr[Tag_CPU_arch_profile].i == 'R'
14795 || out_attr[Tag_CPU_arch_profile].i == 'S'
14796 || out_attr[Tag_CPU_arch].i == 13))
14797 out_attr[i].i = 0;
14798 /* Otherwise, DSP instructions are added and not part of output
14799 architecture. */
14800 else
14801 out_attr[i].i = 1;
14802 break;
14803
75375b3e 14804 case Tag_FP_arch:
62f3b8c8 14805 {
4547cb56
NC		 14806 /* Tag_ABI_HardFP_use is handled along with Tag_FP_arch since
14807 the meaning of Tag_ABI_HardFP_use depends on Tag_FP_arch
14808 when it's 0. It might mean absence of FP hardware if
99654aaf 14809 Tag_FP_arch is zero. */
4547cb56 14810
a715796b 14811#define VFP_VERSION_COUNT 9
62f3b8c8
PB		 14812 static const struct
14813 {
14814 int ver;
14815 int regs;
bca38921 14816 } vfp_versions[VFP_VERSION_COUNT] =
62f3b8c8
PB		 14817 {
14818 {0, 0},
14819 {1, 16},
14820 {2, 16},
14821 {3, 32},
14822 {3, 16},
14823 {4, 32},
bca38921 14824 {4, 16},
a715796b
TG		 14825 {8, 32},
14826 {8, 16}
62f3b8c8
PB		 14827 };
14828 int ver;
14829 int regs;
14830 int newval;
14831
4547cb56
NC		 14832 /* If the output has no requirement about FP hardware,
14833 follow the requirement of the input. */
14834 if (out_attr[i].i == 0)
14835 {
4ec192e6
RE		 14836 /* This assert is still reasonable, we shouldn't
14837 produce the suspicious build attribute
14838 combination (See below for in_attr). */
4547cb56
NC		 14839 BFD_ASSERT (out_attr[Tag_ABI_HardFP_use].i == 0);
14840 out_attr[i].i = in_attr[i].i;
14841 out_attr[Tag_ABI_HardFP_use].i
14842 = in_attr[Tag_ABI_HardFP_use].i;
14843 break;
14844 }
14845 /* If the input has no requirement about FP hardware, do
14846 nothing. */
14847 else if (in_attr[i].i == 0)
14848 {
4ec192e6
RE		 14849 /* We used to assert that Tag_ABI_HardFP_use was
14850 zero here, but we should never assert when
14851 consuming an object file that has suspicious
14852 build attributes. The single precision variant
14853 of 'no FP architecture' is still 'no FP
14854 architecture', so we just ignore the tag in this
14855 case. */
4547cb56
NC		 14856 break;
14857 }
14858
14859 /* Both the input and the output have nonzero Tag_FP_arch.
99654aaf 14860 So Tag_ABI_HardFP_use is implied by Tag_FP_arch when it's zero. */
4547cb56
NC		 14861
14862 /* If both the input and the output have zero Tag_ABI_HardFP_use,
14863 do nothing. */
14864 if (in_attr[Tag_ABI_HardFP_use].i == 0
14865 && out_attr[Tag_ABI_HardFP_use].i == 0)
14866 ;
14867 /* If the input and the output have different Tag_ABI_HardFP_use,
99654aaf 14868 the combination of them is 0 (implied by Tag_FP_arch). */
4547cb56
NC		 14869 else if (in_attr[Tag_ABI_HardFP_use].i
14870 != out_attr[Tag_ABI_HardFP_use].i)
99654aaf 14871 out_attr[Tag_ABI_HardFP_use].i = 0;
4547cb56
NC		 14872
14873 /* Now we can handle Tag_FP_arch. */
14874
bca38921
MGD		 14875 /* Values of VFP_VERSION_COUNT or more aren't defined, so just
14876 pick the biggest. */
14877 if (in_attr[i].i >= VFP_VERSION_COUNT
14878 && in_attr[i].i > out_attr[i].i)
62f3b8c8
PB		 14879 {
14880 out_attr[i] = in_attr[i];
14881 break;
14882 }
14883 /* The output uses the superset of input features
14884 (ISA version) and registers. */
14885 ver = vfp_versions[in_attr[i].i].ver;
14886 if (ver < vfp_versions[out_attr[i].i].ver)
14887 ver = vfp_versions[out_attr[i].i].ver;
14888 regs = vfp_versions[in_attr[i].i].regs;
14889 if (regs < vfp_versions[out_attr[i].i].regs)
14890 regs = vfp_versions[out_attr[i].i].regs;
14891 /* This assumes all possible supersets are also a valid
99059e56 14892 options. */
bca38921 14893 for (newval = VFP_VERSION_COUNT - 1; newval > 0; newval--)
62f3b8c8
PB		 14894 {
14895 if (regs == vfp_versions[newval].regs
14896 && ver == vfp_versions[newval].ver)
14897 break;
14898 }
14899 out_attr[i].i = newval;
14900 }
b1cc4aeb 14901 break;
ee065d83
PB		 14902 case Tag_PCS_config:
14903 if (out_attr[i].i == 0)
14904 out_attr[i].i = in_attr[i].i;
b6009aca 14905 else if (in_attr[i].i != 0 && out_attr[i].i != in_attr[i].i)
ee065d83
PB		 14906 {
14907 /* It's sometimes ok to mix different configs, so this is only
99059e56 14908 a warning. */
ee065d83 14909 _bfd_error_handler
90b6238f 14910 (_("warning: %pB: conflicting platform configuration"), ibfd);
ee065d83
PB		 14911 }
14912 break;
14913 case Tag_ABI_PCS_R9_use:
004ae526
PB		 14914 if (in_attr[i].i != out_attr[i].i
14915 && out_attr[i].i != AEABI_R9_unused
ee065d83
PB		 14916 && in_attr[i].i != AEABI_R9_unused)
14917 {
14918 _bfd_error_handler
90b6238f 14919 (_("error: %pB: conflicting use of R9"), ibfd);
91e22acd 14920 result = FALSE;
ee065d83
PB		 14921 }
14922 if (out_attr[i].i == AEABI_R9_unused)
14923 out_attr[i].i = in_attr[i].i;
14924 break;
14925 case Tag_ABI_PCS_RW_data:
14926 if (in_attr[i].i == AEABI_PCS_RW_data_SBrel
14927 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_SB
14928 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_unused)
14929 {
14930 _bfd_error_handler
871b3ab2 14931 (_("error: %pB: SB relative addressing conflicts with use of R9"),
ee065d83 14932 ibfd);
91e22acd 14933 result = FALSE;
ee065d83
PB		 14934 }
14935 /* Use the smallest value specified. */
14936 if (in_attr[i].i < out_attr[i].i)
14937 out_attr[i].i = in_attr[i].i;
14938 break;
ee065d83 14939 case Tag_ABI_PCS_wchar_t:
a9dc9481
JM		 14940 if (out_attr[i].i && in_attr[i].i && out_attr[i].i != in_attr[i].i
14941 && !elf_arm_tdata (obfd)->no_wchar_size_warning)
ee065d83
PB		 14942 {
14943 _bfd_error_handler
871b3ab2 14944 (_("warning: %pB uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"),
a9dc9481 14945 ibfd, in_attr[i].i, out_attr[i].i);
ee065d83 14946 }
a9dc9481 14947 else if (in_attr[i].i && !out_attr[i].i)
ee065d83
PB		 14948 out_attr[i].i = in_attr[i].i;
14949 break;
ee065d83
PB		 14950 case Tag_ABI_enum_size:
14951 if (in_attr[i].i != AEABI_enum_unused)
14952 {
14953 if (out_attr[i].i == AEABI_enum_unused
14954 || out_attr[i].i == AEABI_enum_forced_wide)
14955 {
14956 /* The existing object is compatible with anything.
14957 Use whatever requirements the new object has. */
14958 out_attr[i].i = in_attr[i].i;
14959 }
14960 else if (in_attr[i].i != AEABI_enum_forced_wide
bf21ed78 14961 && out_attr[i].i != in_attr[i].i
0ffa91dd 14962 && !elf_arm_tdata (obfd)->no_enum_size_warning)
ee065d83 14963 {
91e22acd 14964 static const char *aeabi_enum_names[] =
bf21ed78 14965 { "", "variable-size", "32-bit", "" };
91e22acd
AS		 14966 const char *in_name =
14967 in_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
14968 ? aeabi_enum_names[in_attr[i].i]
14969 : "<unknown>";
14970 const char *out_name =
14971 out_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
14972 ? aeabi_enum_names[out_attr[i].i]
14973 : "<unknown>";
ee065d83 14974 _bfd_error_handler
871b3ab2 14975 (_("warning: %pB uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"),
91e22acd 14976 ibfd, in_name, out_name);
ee065d83
PB		 14977 }
14978 }
14979 break;
14980 case Tag_ABI_VFP_args:
14981 /* Aready done. */
14982 break;
14983 case Tag_ABI_WMMX_args:
14984 if (in_attr[i].i != out_attr[i].i)
14985 {
14986 _bfd_error_handler
871b3ab2 14987 (_("error: %pB uses iWMMXt register arguments, %pB does not"),
ee065d83 14988 ibfd, obfd);
91e22acd 14989 result = FALSE;
ee065d83
PB		 14990 }
14991 break;
7b86a9fa
AS		 14992 case Tag_compatibility:
14993 /* Merged in target-independent code. */
14994 break;
91e22acd 14995 case Tag_ABI_HardFP_use:
4547cb56 14996 /* This is handled along with Tag_FP_arch. */
91e22acd
AS		 14997 break;
14998 case Tag_ABI_FP_16bit_format:
14999 if (in_attr[i].i != 0 && out_attr[i].i != 0)
15000 {
15001 if (in_attr[i].i != out_attr[i].i)
15002 {
15003 _bfd_error_handler
871b3ab2 15004 (_("error: fp16 format mismatch between %pB and %pB"),
91e22acd
AS		 15005 ibfd, obfd);
15006 result = FALSE;
15007 }
15008 }
15009 if (in_attr[i].i != 0)
15010 out_attr[i].i = in_attr[i].i;
15011 break;
7b86a9fa 15012
cd21e546 15013 case Tag_DIV_use:
ac56ee8f
MGD		 15014 /* A value of zero on input means that the divide instruction may
15015 be used if available in the base architecture as specified via
15016 Tag_CPU_arch and Tag_CPU_arch_profile. A value of 1 means that
15017 the user did not want divide instructions. A value of 2
15018 explicitly means that divide instructions were allowed in ARM
15019 and Thumb state. */
15020 if (in_attr[i].i == out_attr[i].i)
15021 /* Do nothing. */ ;
15022 else if (elf32_arm_attributes_forbid_div (in_attr)
15023 && !elf32_arm_attributes_accept_div (out_attr))
15024 out_attr[i].i = 1;
15025 else if (elf32_arm_attributes_forbid_div (out_attr)
15026 && elf32_arm_attributes_accept_div (in_attr))
15027 out_attr[i].i = in_attr[i].i;
15028 else if (in_attr[i].i == 2)
15029 out_attr[i].i = in_attr[i].i;
cd21e546
MGD		 15030 break;
15031
15032 case Tag_MPextension_use_legacy:
15033 /* We don't output objects with Tag_MPextension_use_legacy - we
15034 move the value to Tag_MPextension_use. */
15035 if (in_attr[i].i != 0 && in_attr[Tag_MPextension_use].i != 0)
15036 {
15037 if (in_attr[Tag_MPextension_use].i != in_attr[i].i)
15038 {
15039 _bfd_error_handler
871b3ab2 15040 (_("%pB has both the current and legacy "
b38cadfb 15041 "Tag_MPextension_use attributes"),
cd21e546
MGD		 15042 ibfd);
15043 result = FALSE;
15044 }
15045 }
15046
15047 if (in_attr[i].i > out_attr[Tag_MPextension_use].i)
15048 out_attr[Tag_MPextension_use] = in_attr[i];
15049
15050 break;
15051
91e22acd 15052 case Tag_nodefaults:
2d0bb761
AS		 15053 /* This tag is set if it exists, but the value is unused (and is
15054 typically zero). We don't actually need to do anything here -
15055 the merge happens automatically when the type flags are merged
15056 below. */
91e22acd
AS		 15057 break;
15058 case Tag_also_compatible_with:
15059 /* Already done in Tag_CPU_arch. */
15060 break;
15061 case Tag_conformance:
15062 /* Keep the attribute if it matches. Throw it away otherwise.
15063 No attribute means no claim to conform. */
15064 if (!in_attr[i].s || !out_attr[i].s
15065 || strcmp (in_attr[i].s, out_attr[i].s) != 0)
15066 out_attr[i].s = NULL;
15067 break;
3cfad14c 15068
91e22acd 15069 default:
e8b36cd1
JM		 15070 result
15071 = result && _bfd_elf_merge_unknown_attribute_low (ibfd, obfd, i);
91e22acd
AS		 15072 }
15073
15074 /* If out_attr was copied from in_attr then it won't have a type yet. */
15075 if (in_attr[i].type && !out_attr[i].type)
15076 out_attr[i].type = in_attr[i].type;
ee065d83
PB		 15077 }
15078
104d59d1 15079 /* Merge Tag_compatibility attributes and any common GNU ones. */
50e03d47 15080 if (!_bfd_elf_merge_object_attributes (ibfd, info))
5488d830 15081 return FALSE;
ee065d83 15082
104d59d1 15083 /* Check for any attributes not known on ARM. */
e8b36cd1 15084 result &= _bfd_elf_merge_unknown_attribute_list (ibfd, obfd);
91e22acd 15085
91e22acd 15086 return result;
252b5132
RH		 15087}
15088
3a4a14e9
PB		 15089
15090/* Return TRUE if the two EABI versions are incompatible. */
15091
15092static bfd_boolean
15093elf32_arm_versions_compatible (unsigned iver, unsigned over)
15094{
15095 /* v4 and v5 are the same spec before and after it was released,
15096 so allow mixing them. */
15097 if ((iver == EF_ARM_EABI_VER4 && over == EF_ARM_EABI_VER5)
15098 || (iver == EF_ARM_EABI_VER5 && over == EF_ARM_EABI_VER4))
15099 return TRUE;
15100
15101 return (iver == over);
15102}
15103
252b5132
RH		 15104/* Merge backend specific data from an object file to the output
15105 object file when linking. */
9b485d32 15106
b34976b6 15107static bfd_boolean
50e03d47 15108elf32_arm_merge_private_bfd_data (bfd *, struct bfd_link_info *);
252b5132 15109
9b485d32
NC		 15110/* Display the flags field. */
15111
b34976b6 15112static bfd_boolean
57e8b36a 15113elf32_arm_print_private_bfd_data (bfd *abfd, void * ptr)
252b5132 15114{
fc830a83
NC		 15115 FILE * file = (FILE *) ptr;
15116 unsigned long flags;
252b5132
RH		 15117
15118 BFD_ASSERT (abfd != NULL && ptr != NULL);
15119
15120 /* Print normal ELF private data. */
15121 _bfd_elf_print_private_bfd_data (abfd, ptr);
15122
fc830a83 15123 flags = elf_elfheader (abfd)->e_flags;
9b485d32
NC		 15124 /* Ignore init flag - it may not be set, despite the flags field
15125 containing valid data. */
252b5132 15126
9b485d32 15127 fprintf (file, _("private flags = %lx:"), elf_elfheader (abfd)->e_flags);
252b5132 15128
fc830a83
NC		 15129 switch (EF_ARM_EABI_VERSION (flags))
15130 {
15131 case EF_ARM_EABI_UNKNOWN:
4cc11e76 15132 /* The following flag bits are GNU extensions and not part of the
fc830a83
NC		 15133 official ARM ELF extended ABI. Hence they are only decoded if
15134 the EABI version is not set. */
fd2ec330 15135 if (flags & EF_ARM_INTERWORK)
9b485d32 15136 fprintf (file, _(" [interworking enabled]"));
9a5aca8c 15137
fd2ec330 15138 if (flags & EF_ARM_APCS_26)
6c571f00 15139 fprintf (file, " [APCS-26]");
fc830a83 15140 else
6c571f00 15141 fprintf (file, " [APCS-32]");
9a5aca8c 15142
96a846ea
RE		 15143 if (flags & EF_ARM_VFP_FLOAT)
15144 fprintf (file, _(" [VFP float format]"));
fde78edd
NC		 15145 else if (flags & EF_ARM_MAVERICK_FLOAT)
15146 fprintf (file, _(" [Maverick float format]"));
96a846ea
RE		 15147 else
15148 fprintf (file, _(" [FPA float format]"));
15149
fd2ec330 15150 if (flags & EF_ARM_APCS_FLOAT)
9b485d32 15151 fprintf (file, _(" [floats passed in float registers]"));
9a5aca8c 15152
fd2ec330 15153 if (flags & EF_ARM_PIC)
9b485d32 15154 fprintf (file, _(" [position independent]"));
fc830a83 15155
fd2ec330 15156 if (flags & EF_ARM_NEW_ABI)
9b485d32 15157 fprintf (file, _(" [new ABI]"));
9a5aca8c 15158
fd2ec330 15159 if (flags & EF_ARM_OLD_ABI)
9b485d32 15160 fprintf (file, _(" [old ABI]"));
9a5aca8c 15161
fd2ec330 15162 if (flags & EF_ARM_SOFT_FLOAT)
9b485d32 15163 fprintf (file, _(" [software FP]"));
9a5aca8c 15164
96a846ea
RE		 15165 flags &= ~(EF_ARM_INTERWORK | EF_ARM_APCS_26 | EF_ARM_APCS_FLOAT
15166 | EF_ARM_PIC | EF_ARM_NEW_ABI | EF_ARM_OLD_ABI
fde78edd
NC		 15167 | EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT
15168 | EF_ARM_MAVERICK_FLOAT);
fc830a83 15169 break;
9a5aca8c 15170
fc830a83 15171 case EF_ARM_EABI_VER1:
9b485d32 15172 fprintf (file, _(" [Version1 EABI]"));
9a5aca8c 15173
fc830a83 15174 if (flags & EF_ARM_SYMSARESORTED)
9b485d32 15175 fprintf (file, _(" [sorted symbol table]"));
fc830a83 15176 else
9b485d32 15177 fprintf (file, _(" [unsorted symbol table]"));
9a5aca8c 15178
fc830a83
NC		 15179 flags &= ~ EF_ARM_SYMSARESORTED;
15180 break;
9a5aca8c 15181
fd2ec330
PB		 15182 case EF_ARM_EABI_VER2:
15183 fprintf (file, _(" [Version2 EABI]"));
15184
15185 if (flags & EF_ARM_SYMSARESORTED)
15186 fprintf (file, _(" [sorted symbol table]"));
15187 else
15188 fprintf (file, _(" [unsorted symbol table]"));
15189
15190 if (flags & EF_ARM_DYNSYMSUSESEGIDX)
15191 fprintf (file, _(" [dynamic symbols use segment index]"));
15192
15193 if (flags & EF_ARM_MAPSYMSFIRST)
15194 fprintf (file, _(" [mapping symbols precede others]"));
15195
99e4ae17 15196 flags &= ~(EF_ARM_SYMSARESORTED | EF_ARM_DYNSYMSUSESEGIDX
fd2ec330
PB		 15197 | EF_ARM_MAPSYMSFIRST);
15198 break;
15199
d507cf36
PB		 15200 case EF_ARM_EABI_VER3:
15201 fprintf (file, _(" [Version3 EABI]"));
8cb51566
PB		 15202 break;
15203
15204 case EF_ARM_EABI_VER4:
15205 fprintf (file, _(" [Version4 EABI]"));
3a4a14e9 15206 goto eabi;
d507cf36 15207
3a4a14e9
PB		 15208 case EF_ARM_EABI_VER5:
15209 fprintf (file, _(" [Version5 EABI]"));
3bfcb652
NC		 15210
15211 if (flags & EF_ARM_ABI_FLOAT_SOFT)
15212 fprintf (file, _(" [soft-float ABI]"));
15213
15214 if (flags & EF_ARM_ABI_FLOAT_HARD)
15215 fprintf (file, _(" [hard-float ABI]"));
15216
15217 flags &= ~(EF_ARM_ABI_FLOAT_SOFT | EF_ARM_ABI_FLOAT_HARD);
15218
3a4a14e9 15219 eabi:
d507cf36
PB		 15220 if (flags & EF_ARM_BE8)
15221 fprintf (file, _(" [BE8]"));
15222
15223 if (flags & EF_ARM_LE8)
15224 fprintf (file, _(" [LE8]"));
15225
15226 flags &= ~(EF_ARM_LE8 | EF_ARM_BE8);
15227 break;
15228
fc830a83 15229 default:
9b485d32 15230 fprintf (file, _(" <EABI version unrecognised>"));
fc830a83
NC		 15231 break;
15232 }
252b5132 15233
fc830a83 15234 flags &= ~ EF_ARM_EABIMASK;
252b5132 15235
fc830a83 15236 if (flags & EF_ARM_RELEXEC)
9b485d32 15237 fprintf (file, _(" [relocatable executable]"));
252b5132 15238
18a20338
CL		 15239 if (flags & EF_ARM_PIC)
15240 fprintf (file, _(" [position independent]"));
15241
15242 if (elf_elfheader (abfd)->e_ident[EI_OSABI] == ELFOSABI_ARM_FDPIC)
15243 fprintf (file, _(" [FDPIC ABI supplement]"));
15244
15245 flags &= ~ (EF_ARM_RELEXEC | EF_ARM_PIC);
fc830a83
NC		 15246
15247 if (flags)
9b485d32 15248 fprintf (file, _("<Unrecognised flag bits set>"));
9a5aca8c 15249
252b5132
RH		 15250 fputc ('\n', file);
15251
b34976b6 15252 return TRUE;
252b5132
RH		 15253}
15254
15255static int
57e8b36a 15256elf32_arm_get_symbol_type (Elf_Internal_Sym * elf_sym, int type)
252b5132 15257{
2f0ca46a
NC		 15258 switch (ELF_ST_TYPE (elf_sym->st_info))
15259 {
15260 case STT_ARM_TFUNC:
15261 return ELF_ST_TYPE (elf_sym->st_info);
ce855c42 15262
2f0ca46a
NC		 15263 case STT_ARM_16BIT:
15264 /* If the symbol is not an object, return the STT_ARM_16BIT flag.
15265 This allows us to distinguish between data used by Thumb instructions
15266 and non-data (which is probably code) inside Thumb regions of an
15267 executable. */
1a0eb693 15268 if (type != STT_OBJECT && type != STT_TLS)
2f0ca46a
NC		 15269 return ELF_ST_TYPE (elf_sym->st_info);
15270 break;
9a5aca8c 15271
ce855c42
NC		 15272 default:
15273 break;
2f0ca46a
NC		 15274 }
15275
15276 return type;
252b5132 15277}
f21f3fe0 15278
252b5132 15279static asection *
07adf181
AM		 15280elf32_arm_gc_mark_hook (asection *sec,
15281 struct bfd_link_info *info,
15282 Elf_Internal_Rela *rel,
15283 struct elf_link_hash_entry *h,
15284 Elf_Internal_Sym *sym)
252b5132
RH		 15285{
15286 if (h != NULL)
07adf181 15287 switch (ELF32_R_TYPE (rel->r_info))
252b5132
RH		 15288 {
15289 case R_ARM_GNU_VTINHERIT:
15290 case R_ARM_GNU_VTENTRY:
07adf181
AM		 15291 return NULL;
15292 }
9ad5cbcf 15293
07adf181 15294 return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym);
252b5132
RH		 15295}
15296
780a67af
NC		 15297/* Look through the relocs for a section during the first phase. */
15298
b34976b6 15299static bfd_boolean
57e8b36a
NC		 15300elf32_arm_check_relocs (bfd *abfd, struct bfd_link_info *info,
15301 asection *sec, const Elf_Internal_Rela *relocs)
252b5132 15302{
b34976b6
AM		 15303 Elf_Internal_Shdr *symtab_hdr;
15304 struct elf_link_hash_entry **sym_hashes;
b34976b6
AM		 15305 const Elf_Internal_Rela *rel;
15306 const Elf_Internal_Rela *rel_end;
15307 bfd *dynobj;
5e681ec4 15308 asection *sreloc;
5e681ec4 15309 struct elf32_arm_link_hash_table *htab;
f6e32f6d
RS		 15310 bfd_boolean call_reloc_p;
15311 bfd_boolean may_become_dynamic_p;
15312 bfd_boolean may_need_local_target_p;
ce98a316 15313 unsigned long nsyms;
9a5aca8c 15314
0e1862bb 15315 if (bfd_link_relocatable (info))
b34976b6 15316 return TRUE;
9a5aca8c 15317
0ffa91dd
NC		 15318 BFD_ASSERT (is_arm_elf (abfd));
15319
5e681ec4 15320 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15321 if (htab == NULL)
15322 return FALSE;
15323
5e681ec4 15324 sreloc = NULL;
9a5aca8c 15325
67687978
PB		 15326 /* Create dynamic sections for relocatable executables so that we can
15327 copy relocations. */
15328 if (htab->root.is_relocatable_executable
15329 && ! htab->root.dynamic_sections_created)
15330 {
15331 if (! _bfd_elf_link_create_dynamic_sections (abfd, info))
15332 return FALSE;
15333 }
15334
cbc704f3
RS		 15335 if (htab->root.dynobj == NULL)
15336 htab->root.dynobj = abfd;
34e77a92
RS		 15337 if (!create_ifunc_sections (info))
15338 return FALSE;
cbc704f3
RS		 15339
15340 dynobj = htab->root.dynobj;
15341
0ffa91dd 15342 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 15343 sym_hashes = elf_sym_hashes (abfd);
ce98a316 15344 nsyms = NUM_SHDR_ENTRIES (symtab_hdr);
b38cadfb 15345
252b5132
RH		 15346 rel_end = relocs + sec->reloc_count;
15347 for (rel = relocs; rel < rel_end; rel++)
15348 {
34e77a92 15349 Elf_Internal_Sym *isym;
252b5132 15350 struct elf_link_hash_entry *h;
b7693d02 15351 struct elf32_arm_link_hash_entry *eh;
d42c267e 15352 unsigned int r_symndx;
eb043451 15353 int r_type;
9a5aca8c 15354
252b5132 15355 r_symndx = ELF32_R_SYM (rel->r_info);
eb043451 15356 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 15357 r_type = arm_real_reloc_type (htab, r_type);
ba93b8ac 15358
ce98a316
NC		 15359 if (r_symndx >= nsyms
15360 /* PR 9934: It is possible to have relocations that do not
15361 refer to symbols, thus it is also possible to have an
15362 object file containing relocations but no symbol table. */
cf35638d 15363 && (r_symndx > STN_UNDEF || nsyms > 0))
ba93b8ac 15364 {
871b3ab2 15365 _bfd_error_handler (_("%pB: bad symbol index: %d"), abfd,
4eca0228 15366 r_symndx);
ba93b8ac
DJ		 15367 return FALSE;
15368 }
15369
34e77a92
RS		 15370 h = NULL;
15371 isym = NULL;
15372 if (nsyms > 0)
973a3492 15373 {
34e77a92
RS		 15374 if (r_symndx < symtab_hdr->sh_info)
15375 {
15376 /* A local symbol. */
15377 isym = bfd_sym_from_r_symndx (&htab->sym_cache,
15378 abfd, r_symndx);
15379 if (isym == NULL)
15380 return FALSE;
15381 }
15382 else
15383 {
15384 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
15385 while (h->root.type == bfd_link_hash_indirect
15386 || h->root.type == bfd_link_hash_warning)
15387 h = (struct elf_link_hash_entry *) h->root.u.i.link;
15388 }
973a3492 15389 }
9a5aca8c 15390
b7693d02
DJ		 15391 eh = (struct elf32_arm_link_hash_entry *) h;
15392
f6e32f6d
RS		 15393 call_reloc_p = FALSE;
15394 may_become_dynamic_p = FALSE;
15395 may_need_local_target_p = FALSE;
15396
0855e32b
NS		 15397 /* Could be done earlier, if h were already available. */
15398 r_type = elf32_arm_tls_transition (info, r_type, h);
eb043451 15399 switch (r_type)
99059e56 15400 {
e8b09b87
CL		 15401 case R_ARM_GOTOFFFUNCDESC:
15402 {
15403 if (h == NULL)
15404 {
15405 if (!elf32_arm_allocate_local_sym_info (abfd))
15406 return FALSE;
15407 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].gotofffuncdesc_cnt += 1;
15408 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].funcdesc_offset = -1;
15409 }
15410 else
15411 {
15412 eh->fdpic_cnts.gotofffuncdesc_cnt++;
15413 }
15414 }
15415 break;
15416
15417 case R_ARM_GOTFUNCDESC:
15418 {
15419 if (h == NULL)
15420 {
15421 /* Such a relocation is not supposed to be generated
15422 by gcc on a static function. */
15423 /* Anyway if needed it could be handled. */
15424 abort();
15425 }
15426 else
15427 {
15428 eh->fdpic_cnts.gotfuncdesc_cnt++;
15429 }
15430 }
15431 break;
15432
15433 case R_ARM_FUNCDESC:
15434 {
15435 if (h == NULL)
15436 {
15437 if (!elf32_arm_allocate_local_sym_info (abfd))
15438 return FALSE;
15439 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].funcdesc_cnt += 1;
15440 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].funcdesc_offset = -1;
15441 }
15442 else
15443 {
15444 eh->fdpic_cnts.funcdesc_cnt++;
15445 }
15446 }
15447 break;
15448
5e681ec4 15449 case R_ARM_GOT32:
eb043451 15450 case R_ARM_GOT_PREL:
ba93b8ac 15451 case R_ARM_TLS_GD32:
5c5a4843 15452 case R_ARM_TLS_GD32_FDPIC:
ba93b8ac 15453 case R_ARM_TLS_IE32:
5c5a4843 15454 case R_ARM_TLS_IE32_FDPIC:
0855e32b
NS		 15455 case R_ARM_TLS_GOTDESC:
15456 case R_ARM_TLS_DESCSEQ:
15457 case R_ARM_THM_TLS_DESCSEQ:
15458 case R_ARM_TLS_CALL:
15459 case R_ARM_THM_TLS_CALL:
5e681ec4 15460 /* This symbol requires a global offset table entry. */
ba93b8ac
DJ		 15461 {
15462 int tls_type, old_tls_type;
5e681ec4 15463
ba93b8ac
DJ		 15464 switch (r_type)
15465 {
15466 case R_ARM_TLS_GD32: tls_type = GOT_TLS_GD; break;
5c5a4843 15467 case R_ARM_TLS_GD32_FDPIC: tls_type = GOT_TLS_GD; break;
b38cadfb 15468
ba93b8ac 15469 case R_ARM_TLS_IE32: tls_type = GOT_TLS_IE; break;
5c5a4843 15470 case R_ARM_TLS_IE32_FDPIC: tls_type = GOT_TLS_IE; break;
b38cadfb 15471
0855e32b
NS		 15472 case R_ARM_TLS_GOTDESC:
15473 case R_ARM_TLS_CALL: case R_ARM_THM_TLS_CALL:
15474 case R_ARM_TLS_DESCSEQ: case R_ARM_THM_TLS_DESCSEQ:
15475 tls_type = GOT_TLS_GDESC; break;
b38cadfb 15476
ba93b8ac
DJ		 15477 default: tls_type = GOT_NORMAL; break;
15478 }
252b5132 15479
0e1862bb 15480 if (!bfd_link_executable (info) && (tls_type & GOT_TLS_IE))
eea6dad2
KM		 15481 info->flags |= DF_STATIC_TLS;
15482
ba93b8ac
DJ		 15483 if (h != NULL)
15484 {
15485 h->got.refcount++;
15486 old_tls_type = elf32_arm_hash_entry (h)->tls_type;
15487 }
15488 else
15489 {
ba93b8ac 15490 /* This is a global offset table entry for a local symbol. */
34e77a92
RS		 15491 if (!elf32_arm_allocate_local_sym_info (abfd))
15492 return FALSE;
15493 elf_local_got_refcounts (abfd)[r_symndx] += 1;
ba93b8ac
DJ		 15494 old_tls_type = elf32_arm_local_got_tls_type (abfd) [r_symndx];
15495 }
15496
0855e32b 15497 /* If a variable is accessed with both tls methods, two
99059e56 15498 slots may be created. */
0855e32b
NS		 15499 if (GOT_TLS_GD_ANY_P (old_tls_type)
15500 && GOT_TLS_GD_ANY_P (tls_type))
15501 tls_type |= old_tls_type;
15502
15503 /* We will already have issued an error message if there
15504 is a TLS/non-TLS mismatch, based on the symbol
15505 type. So just combine any TLS types needed. */
ba93b8ac
DJ		 15506 if (old_tls_type != GOT_UNKNOWN && old_tls_type != GOT_NORMAL
15507 && tls_type != GOT_NORMAL)
15508 tls_type |= old_tls_type;
15509
0855e32b 15510 /* If the symbol is accessed in both IE and GDESC
99059e56
RM		 15511 method, we're able to relax. Turn off the GDESC flag,
15512 without messing up with any other kind of tls types
6a631e86 15513 that may be involved. */
0855e32b
NS		 15514 if ((tls_type & GOT_TLS_IE) && (tls_type & GOT_TLS_GDESC))
15515 tls_type &= ~GOT_TLS_GDESC;
15516
ba93b8ac
DJ		 15517 if (old_tls_type != tls_type)
15518 {
15519 if (h != NULL)
15520 elf32_arm_hash_entry (h)->tls_type = tls_type;
15521 else
15522 elf32_arm_local_got_tls_type (abfd) [r_symndx] = tls_type;
15523 }
15524 }
8029a119 15525 /* Fall through. */
ba93b8ac
DJ		 15526
15527 case R_ARM_TLS_LDM32:
5c5a4843
CL		 15528 case R_ARM_TLS_LDM32_FDPIC:
15529 if (r_type == R_ARM_TLS_LDM32 || r_type == R_ARM_TLS_LDM32_FDPIC)
ba93b8ac 15530 htab->tls_ldm_got.refcount++;
8029a119 15531 /* Fall through. */
252b5132 15532
c19d1205 15533 case R_ARM_GOTOFF32:
5e681ec4 15534 case R_ARM_GOTPC:
cbc704f3
RS		 15535 if (htab->root.sgot == NULL
15536 && !create_got_section (htab->root.dynobj, info))
15537 return FALSE;
252b5132
RH		 15538 break;
15539
252b5132 15540 case R_ARM_PC24:
7359ea65 15541 case R_ARM_PLT32:
5b5bb741
PB		 15542 case R_ARM_CALL:
15543 case R_ARM_JUMP24:
eb043451 15544 case R_ARM_PREL31:
c19d1205 15545 case R_ARM_THM_CALL:
bd97cb95
DJ		 15546 case R_ARM_THM_JUMP24:
15547 case R_ARM_THM_JUMP19:
f6e32f6d
RS		 15548 call_reloc_p = TRUE;
15549 may_need_local_target_p = TRUE;
15550 break;
15551
15552 case R_ARM_ABS12:
15553 /* VxWorks uses dynamic R_ARM_ABS12 relocations for
15554 ldr __GOTT_INDEX__ offsets. */
15555 if (!htab->vxworks_p)
15556 {
15557 may_need_local_target_p = TRUE;
15558 break;
15559 }
aebf9be7 15560 else goto jump_over;
9eaff861 15561
f6e32f6d 15562 /* Fall through. */
39623e12 15563
96c23d59
JM		 15564 case R_ARM_MOVW_ABS_NC:
15565 case R_ARM_MOVT_ABS:
15566 case R_ARM_THM_MOVW_ABS_NC:
15567 case R_ARM_THM_MOVT_ABS:
0e1862bb 15568 if (bfd_link_pic (info))
96c23d59 15569 {
4eca0228 15570 _bfd_error_handler
871b3ab2 15571 (_("%pB: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
96c23d59
JM		 15572 abfd, elf32_arm_howto_table_1[r_type].name,
15573 (h) ? h->root.root.string : "a local symbol");
15574 bfd_set_error (bfd_error_bad_value);
15575 return FALSE;
15576 }
15577
15578 /* Fall through. */
39623e12
PB		 15579 case R_ARM_ABS32:
15580 case R_ARM_ABS32_NOI:
aebf9be7 15581 jump_over:
0e1862bb 15582 if (h != NULL && bfd_link_executable (info))
97323ad1
WN		 15583 {
15584 h->pointer_equality_needed = 1;
15585 }
15586 /* Fall through. */
39623e12
PB		 15587 case R_ARM_REL32:
15588 case R_ARM_REL32_NOI:
b6895b4f
PB		 15589 case R_ARM_MOVW_PREL_NC:
15590 case R_ARM_MOVT_PREL:
b6895b4f
PB		 15591 case R_ARM_THM_MOVW_PREL_NC:
15592 case R_ARM_THM_MOVT_PREL:
39623e12 15593
b7693d02 15594 /* Should the interworking branches be listed here? */
e8b09b87
CL		 15595 if ((bfd_link_pic (info) || htab->root.is_relocatable_executable
15596 || htab->fdpic_p)
34e77a92
RS		 15597 && (sec->flags & SEC_ALLOC) != 0)
15598 {
15599 if (h == NULL
469a3493 15600 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 15601 {
15602 /* In shared libraries and relocatable executables,
15603 we treat local relative references as calls;
15604 see the related SYMBOL_CALLS_LOCAL code in
15605 allocate_dynrelocs. */
15606 call_reloc_p = TRUE;
15607 may_need_local_target_p = TRUE;
15608 }
15609 else
15610 /* We are creating a shared library or relocatable
15611 executable, and this is a reloc against a global symbol,
15612 or a non-PC-relative reloc against a local symbol.
15613 We may need to copy the reloc into the output. */
15614 may_become_dynamic_p = TRUE;
15615 }
f6e32f6d
RS		 15616 else
15617 may_need_local_target_p = TRUE;
252b5132
RH		 15618 break;
15619
99059e56
RM		 15620 /* This relocation describes the C++ object vtable hierarchy.
15621 Reconstruct it for later use during GC. */
15622 case R_ARM_GNU_VTINHERIT:
15623 if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset))
15624 return FALSE;
15625 break;
15626
15627 /* This relocation describes which C++ vtable entries are actually
15628 used. Record for later use during GC. */
15629 case R_ARM_GNU_VTENTRY:
a0ea3a14 15630 if (!bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_offset))
99059e56
RM		 15631 return FALSE;
15632 break;
15633 }
f6e32f6d
RS		 15634
15635 if (h != NULL)
15636 {
15637 if (call_reloc_p)
15638 /* We may need a .plt entry if the function this reloc
15639 refers to is in a different object, regardless of the
15640 symbol's type. We can't tell for sure yet, because
15641 something later might force the symbol local. */
15642 h->needs_plt = 1;
15643 else if (may_need_local_target_p)
15644 /* If this reloc is in a read-only section, we might
15645 need a copy reloc. We can't check reliably at this
15646 stage whether the section is read-only, as input
15647 sections have not yet been mapped to output sections.
15648 Tentatively set the flag for now, and correct in
15649 adjust_dynamic_symbol. */
15650 h->non_got_ref = 1;
15651 }
15652
34e77a92
RS		 15653 if (may_need_local_target_p
15654 && (h != NULL || ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC))
f6e32f6d 15655 {
34e77a92
RS		 15656 union gotplt_union *root_plt;
15657 struct arm_plt_info *arm_plt;
15658 struct arm_local_iplt_info *local_iplt;
15659
15660 if (h != NULL)
15661 {
15662 root_plt = &h->plt;
15663 arm_plt = &eh->plt;
15664 }
15665 else
15666 {
15667 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
15668 if (local_iplt == NULL)
15669 return FALSE;
15670 root_plt = &local_iplt->root;
15671 arm_plt = &local_iplt->arm;
15672 }
15673
f6e32f6d
RS		 15674 /* If the symbol is a function that doesn't bind locally,
15675 this relocation will need a PLT entry. */
a8c887dd
NC		 15676 if (root_plt->refcount != -1)
15677 root_plt->refcount += 1;
34e77a92
RS		 15678
15679 if (!call_reloc_p)
15680 arm_plt->noncall_refcount++;
f6e32f6d
RS		 15681
15682 /* It's too early to use htab->use_blx here, so we have to
15683 record possible blx references separately from
15684 relocs that definitely need a thumb stub. */
15685
15686 if (r_type == R_ARM_THM_CALL)
34e77a92 15687 arm_plt->maybe_thumb_refcount += 1;
f6e32f6d
RS		 15688
15689 if (r_type == R_ARM_THM_JUMP24
15690 || r_type == R_ARM_THM_JUMP19)
34e77a92 15691 arm_plt->thumb_refcount += 1;
f6e32f6d
RS		 15692 }
15693
15694 if (may_become_dynamic_p)
15695 {
15696 struct elf_dyn_relocs *p, **head;
15697
15698 /* Create a reloc section in dynobj. */
15699 if (sreloc == NULL)
15700 {
15701 sreloc = _bfd_elf_make_dynamic_reloc_section
15702 (sec, dynobj, 2, abfd, ! htab->use_rel);
15703
15704 if (sreloc == NULL)
15705 return FALSE;
15706
15707 /* BPABI objects never have dynamic relocations mapped. */
15708 if (htab->symbian_p)
15709 {
15710 flagword flags;
15711
fd361982 15712 flags = bfd_section_flags (sreloc);
f6e32f6d 15713 flags &= ~(SEC_LOAD | SEC_ALLOC);
fd361982 15714 bfd_set_section_flags (sreloc, flags);
f6e32f6d
RS		 15715 }
15716 }
15717
15718 /* If this is a global symbol, count the number of
15719 relocations we need for this symbol. */
15720 if (h != NULL)
15721 head = &((struct elf32_arm_link_hash_entry *) h)->dyn_relocs;
15722 else
15723 {
34e77a92
RS		 15724 head = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
15725 if (head == NULL)
f6e32f6d 15726 return FALSE;
f6e32f6d
RS		 15727 }
15728
15729 p = *head;
15730 if (p == NULL || p->sec != sec)
15731 {
986f0783 15732 size_t amt = sizeof *p;
f6e32f6d
RS		 15733
15734 p = (struct elf_dyn_relocs *) bfd_alloc (htab->root.dynobj, amt);
15735 if (p == NULL)
15736 return FALSE;
15737 p->next = *head;
15738 *head = p;
15739 p->sec = sec;
15740 p->count = 0;
15741 p->pc_count = 0;
15742 }
15743
469a3493 15744 if (elf32_arm_howto_from_type (r_type)->pc_relative)
f6e32f6d
RS		 15745 p->pc_count += 1;
15746 p->count += 1;
e8b09b87
CL		 15747 if (h == NULL && htab->fdpic_p && !bfd_link_pic(info)
15748 && r_type != R_ARM_ABS32 && r_type != R_ARM_ABS32_NOI) {
15749 /* Here we only support R_ARM_ABS32 and R_ARM_ABS32_NOI
15750 that will become rofixup. */
15751 /* This is due to the fact that we suppose all will become rofixup. */
15752 fprintf(stderr, "FDPIC does not yet support %d relocation to become dynamic for executable\n", r_type);
15753 _bfd_error_handler
15754 (_("FDPIC does not yet support %s relocation"
15755 " to become dynamic for executable"),
15756 elf32_arm_howto_table_1[r_type].name);
15757 abort();
15758 }
f6e32f6d 15759 }
252b5132 15760 }
f21f3fe0 15761
b34976b6 15762 return TRUE;
252b5132
RH		 15763}
15764
9eaff861
AO		 15765static void
15766elf32_arm_update_relocs (asection *o,
15767 struct bfd_elf_section_reloc_data *reldata)
15768{
15769 void (*swap_in) (bfd *, const bfd_byte *, Elf_Internal_Rela *);
15770 void (*swap_out) (bfd *, const Elf_Internal_Rela *, bfd_byte *);
15771 const struct elf_backend_data *bed;
15772 _arm_elf_section_data *eado;
15773 struct bfd_link_order *p;
15774 bfd_byte *erela_head, *erela;
15775 Elf_Internal_Rela *irela_head, *irela;
15776 Elf_Internal_Shdr *rel_hdr;
15777 bfd *abfd;
15778 unsigned int count;
15779
15780 eado = get_arm_elf_section_data (o);
15781
15782 if (!eado || eado->elf.this_hdr.sh_type != SHT_ARM_EXIDX)
15783 return;
15784
15785 abfd = o->owner;
15786 bed = get_elf_backend_data (abfd);
15787 rel_hdr = reldata->hdr;
15788
15789 if (rel_hdr->sh_entsize == bed->s->sizeof_rel)
15790 {
15791 swap_in = bed->s->swap_reloc_in;
15792 swap_out = bed->s->swap_reloc_out;
15793 }
15794 else if (rel_hdr->sh_entsize == bed->s->sizeof_rela)
15795 {
15796 swap_in = bed->s->swap_reloca_in;
15797 swap_out = bed->s->swap_reloca_out;
15798 }
15799 else
15800 abort ();
15801
15802 erela_head = rel_hdr->contents;
15803 irela_head = (Elf_Internal_Rela *) bfd_zmalloc
15804 ((NUM_SHDR_ENTRIES (rel_hdr) + 1) * sizeof (*irela_head));
15805
15806 erela = erela_head;
15807 irela = irela_head;
15808 count = 0;
15809
15810 for (p = o->map_head.link_order; p; p = p->next)
15811 {
15812 if (p->type == bfd_section_reloc_link_order
15813 || p->type == bfd_symbol_reloc_link_order)
15814 {
15815 (*swap_in) (abfd, erela, irela);
15816 erela += rel_hdr->sh_entsize;
15817 irela++;
15818 count++;
15819 }
15820 else if (p->type == bfd_indirect_link_order)
15821 {
15822 struct bfd_elf_section_reloc_data *input_reldata;
15823 arm_unwind_table_edit *edit_list, *edit_tail;
15824 _arm_elf_section_data *eadi;
15825 bfd_size_type j;
15826 bfd_vma offset;
15827 asection *i;
15828
15829 i = p->u.indirect.section;
15830
15831 eadi = get_arm_elf_section_data (i);
15832 edit_list = eadi->u.exidx.unwind_edit_list;
15833 edit_tail = eadi->u.exidx.unwind_edit_tail;
539300fb 15834 offset = i->output_offset;
9eaff861
AO		 15835
15836 if (eadi->elf.rel.hdr &&
15837 eadi->elf.rel.hdr->sh_entsize == rel_hdr->sh_entsize)
15838 input_reldata = &eadi->elf.rel;
15839 else if (eadi->elf.rela.hdr &&
15840 eadi->elf.rela.hdr->sh_entsize == rel_hdr->sh_entsize)
15841 input_reldata = &eadi->elf.rela;
15842 else
15843 abort ();
15844
15845 if (edit_list)
15846 {
15847 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
15848 {
15849 arm_unwind_table_edit *edit_node, *edit_next;
15850 bfd_vma bias;
c48182bf 15851 bfd_vma reloc_index;
9eaff861
AO		 15852
15853 (*swap_in) (abfd, erela, irela);
c48182bf 15854 reloc_index = (irela->r_offset - offset) / 8;
9eaff861
AO		 15855
15856 bias = 0;
15857 edit_node = edit_list;
15858 for (edit_next = edit_list;
c48182bf 15859 edit_next && edit_next->index <= reloc_index;
9eaff861
AO		 15860 edit_next = edit_node->next)
15861 {
15862 bias++;
15863 edit_node = edit_next;
15864 }
15865
15866 if (edit_node->type != DELETE_EXIDX_ENTRY
c48182bf 15867 || edit_node->index != reloc_index)
9eaff861
AO		 15868 {
15869 irela->r_offset -= bias * 8;
15870 irela++;
15871 count++;
15872 }
15873
15874 erela += rel_hdr->sh_entsize;
15875 }
15876
15877 if (edit_tail->type == INSERT_EXIDX_CANTUNWIND_AT_END)
15878 {
15879 /* New relocation entity. */
15880 asection *text_sec = edit_tail->linked_section;
15881 asection *text_out = text_sec->output_section;
15882 bfd_vma exidx_offset = offset + i->size - 8;
15883
15884 irela->r_addend = 0;
15885 irela->r_offset = exidx_offset;
15886 irela->r_info = ELF32_R_INFO
15887 (text_out->target_index, R_ARM_PREL31);
15888 irela++;
15889 count++;
15890 }
15891 }
15892 else
15893 {
15894 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
15895 {
15896 (*swap_in) (abfd, erela, irela);
15897 erela += rel_hdr->sh_entsize;
15898 irela++;
15899 }
15900
15901 count += NUM_SHDR_ENTRIES (input_reldata->hdr);
15902 }
15903 }
15904 }
15905
15906 reldata->count = count;
15907 rel_hdr->sh_size = count * rel_hdr->sh_entsize;
15908
15909 erela = erela_head;
15910 irela = irela_head;
15911 while (count > 0)
15912 {
15913 (*swap_out) (abfd, irela, erela);
15914 erela += rel_hdr->sh_entsize;
15915 irela++;
15916 count--;
15917 }
15918
15919 free (irela_head);
15920
15921 /* Hashes are no longer valid. */
15922 free (reldata->hashes);
15923 reldata->hashes = NULL;
15924}
15925
6a5bb875 15926/* Unwinding tables are not referenced directly. This pass marks them as
4ba2ef8f
TP		 15927 required if the corresponding code section is marked. Similarly, ARMv8-M
15928 secure entry functions can only be referenced by SG veneers which are
15929 created after the GC process. They need to be marked in case they reside in
15930 their own section (as would be the case if code was compiled with
15931 -ffunction-sections). */
6a5bb875
PB		 15932
15933static bfd_boolean
906e58ca
NC		 15934elf32_arm_gc_mark_extra_sections (struct bfd_link_info *info,
15935 elf_gc_mark_hook_fn gc_mark_hook)
6a5bb875
PB		 15936{
15937 bfd *sub;
15938 Elf_Internal_Shdr **elf_shdrp;
4ba2ef8f
TP		 15939 asection *cmse_sec;
15940 obj_attribute *out_attr;
15941 Elf_Internal_Shdr *symtab_hdr;
15942 unsigned i, sym_count, ext_start;
15943 const struct elf_backend_data *bed;
15944 struct elf_link_hash_entry **sym_hashes;
15945 struct elf32_arm_link_hash_entry *cmse_hash;
15946 bfd_boolean again, is_v8m, first_bfd_browse = TRUE;
bb32413f
SP		 15947 bfd_boolean debug_sec_need_to_be_marked = FALSE;
15948 asection *isec;
6a5bb875 15949
7f6ab9f8
AM		 15950 _bfd_elf_gc_mark_extra_sections (info, gc_mark_hook);
15951
4ba2ef8f
TP		 15952 out_attr = elf_known_obj_attributes_proc (info->output_bfd);
15953 is_v8m = out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
15954 && out_attr[Tag_CPU_arch_profile].i == 'M';
15955
6a5bb875
PB		 15956 /* Marking EH data may cause additional code sections to be marked,
15957 requiring multiple passes. */
15958 again = TRUE;
15959 while (again)
15960 {
15961 again = FALSE;
c72f2fb2 15962 for (sub = info->input_bfds; sub != NULL; sub = sub->link.next)
6a5bb875
PB		 15963 {
15964 asection *o;
15965
0ffa91dd 15966 if (! is_arm_elf (sub))
6a5bb875
PB		 15967 continue;
15968
15969 elf_shdrp = elf_elfsections (sub);
15970 for (o = sub->sections; o != NULL; o = o->next)
15971 {
15972 Elf_Internal_Shdr *hdr;
0ffa91dd 15973
6a5bb875 15974 hdr = &elf_section_data (o)->this_hdr;
4fbb74a6
AM		 15975 if (hdr->sh_type == SHT_ARM_EXIDX
15976 && hdr->sh_link
15977 && hdr->sh_link < elf_numsections (sub)
6a5bb875
PB		 15978 && !o->gc_mark
15979 && elf_shdrp[hdr->sh_link]->bfd_section->gc_mark)
15980 {
15981 again = TRUE;
15982 if (!_bfd_elf_gc_mark (info, o, gc_mark_hook))
15983 return FALSE;
15984 }
15985 }
4ba2ef8f
TP		 15986
15987 /* Mark section holding ARMv8-M secure entry functions. We mark all
15988 of them so no need for a second browsing. */
15989 if (is_v8m && first_bfd_browse)
15990 {
15991 sym_hashes = elf_sym_hashes (sub);
15992 bed = get_elf_backend_data (sub);
15993 symtab_hdr = &elf_tdata (sub)->symtab_hdr;
15994 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
15995 ext_start = symtab_hdr->sh_info;
15996
15997 /* Scan symbols. */
15998 for (i = ext_start; i < sym_count; i++)
15999 {
16000 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
16001
16002 /* Assume it is a special symbol. If not, cmse_scan will
16003 warn about it and user can do something about it. */
baf46cd7
AM		 16004 if (CONST_STRNEQ (cmse_hash->root.root.root.string,
16005 CMSE_PREFIX))
4ba2ef8f
TP		 16006 {
16007 cmse_sec = cmse_hash->root.root.u.def.section;
5025eb7c
AO		 16008 if (!cmse_sec->gc_mark
16009 && !_bfd_elf_gc_mark (info, cmse_sec, gc_mark_hook))
4ba2ef8f 16010 return FALSE;
bb32413f
SP		 16011 /* The debug sections related to these secure entry
16012 functions are marked on enabling below flag. */
16013 debug_sec_need_to_be_marked = TRUE;
4ba2ef8f
TP		 16014 }
16015 }
bb32413f
SP		 16016
16017 if (debug_sec_need_to_be_marked)
16018 {
16019 /* Looping over all the sections of the object file containing
16020 Armv8-M secure entry functions and marking all the debug
16021 sections. */
16022 for (isec = sub->sections; isec != NULL; isec = isec->next)
16023 {
16024 /* If not a debug sections, skip it. */
16025 if (!isec->gc_mark && (isec->flags & SEC_DEBUGGING))
16026 isec->gc_mark = 1 ;
16027 }
16028 debug_sec_need_to_be_marked = FALSE;
16029 }
4ba2ef8f 16030 }
6a5bb875 16031 }
4ba2ef8f 16032 first_bfd_browse = FALSE;
6a5bb875
PB		 16033 }
16034
16035 return TRUE;
16036}
16037
3c9458e9
NC		 16038/* Treat mapping symbols as special target symbols. */
16039
16040static bfd_boolean
16041elf32_arm_is_target_special_symbol (bfd * abfd ATTRIBUTE_UNUSED, asymbol * sym)
16042{
b0796911
PB		 16043 return bfd_is_arm_special_symbol_name (sym->name,
16044 BFD_ARM_SPECIAL_SYM_TYPE_ANY);
3c9458e9
NC		 16045}
16046
e7679060
AM		 16047/* If the ELF symbol SYM might be a function in SEC, return the
16048 function size and set *CODE_OFF to the function's entry point,
16049 otherwise return zero. */
252b5132 16050
e7679060
AM		 16051static bfd_size_type
16052elf32_arm_maybe_function_sym (const asymbol *sym, asection *sec,
16053 bfd_vma *code_off)
16054{
16055 bfd_size_type size;
252b5132 16056
e7679060
AM		 16057 if ((sym->flags & (BSF_SECTION_SYM | BSF_FILE | BSF_OBJECT
16058 | BSF_THREAD_LOCAL | BSF_RELC | BSF_SRELC)) != 0
16059 || sym->section != sec)
16060 return 0;
252b5132 16061
e7679060
AM		 16062 if (!(sym->flags & BSF_SYNTHETIC))
16063 switch (ELF_ST_TYPE (((elf_symbol_type *) sym)->internal_elf_sym.st_info))
16064 {
252b5132
RH		 16065 case STT_FUNC:
16066 case STT_ARM_TFUNC:
9d2da7ca 16067 case STT_NOTYPE:
252b5132 16068 break;
e7679060
AM		 16069 default:
16070 return 0;
16071 }
0367ecfb 16072
e7679060
AM		 16073 if ((sym->flags & BSF_LOCAL)
16074 && bfd_is_arm_special_symbol_name (sym->name,
16075 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
16076 return 0;
0367ecfb 16077
e7679060
AM		 16078 *code_off = sym->value;
16079 size = 0;
16080 if (!(sym->flags & BSF_SYNTHETIC))
16081 size = ((elf_symbol_type *) sym)->internal_elf_sym.st_size;
16082 if (size == 0)
16083 size = 1;
16084 return size;
252b5132
RH		 16085}
16086
4ab527b0 16087static bfd_boolean
07d6d2b8 16088elf32_arm_find_inliner_info (bfd * abfd,
4ab527b0
FF		 16089 const char ** filename_ptr,
16090 const char ** functionname_ptr,
16091 unsigned int * line_ptr)
16092{
16093 bfd_boolean found;
16094 found = _bfd_dwarf2_find_inliner_info (abfd, filename_ptr,
16095 functionname_ptr, line_ptr,
16096 & elf_tdata (abfd)->dwarf2_find_line_info);
16097 return found;
16098}
16099
63c1f59d
AM		 16100/* Find dynamic relocs for H that apply to read-only sections. */
16101
16102static asection *
16103readonly_dynrelocs (struct elf_link_hash_entry *h)
16104{
16105 struct elf_dyn_relocs *p;
16106
16107 for (p = elf32_arm_hash_entry (h)->dyn_relocs; p != NULL; p = p->next)
16108 {
16109 asection *s = p->sec->output_section;
16110
16111 if (s != NULL && (s->flags & SEC_READONLY) != 0)
16112 return p->sec;
16113 }
16114 return NULL;
16115}
16116
252b5132
RH		 16117/* Adjust a symbol defined by a dynamic object and referenced by a
16118 regular object. The current definition is in some section of the
16119 dynamic object, but we're not including those sections. We have to
16120 change the definition to something the rest of the link can
16121 understand. */
16122
b34976b6 16123static bfd_boolean
57e8b36a
NC		 16124elf32_arm_adjust_dynamic_symbol (struct bfd_link_info * info,
16125 struct elf_link_hash_entry * h)
252b5132
RH		 16126{
16127 bfd * dynobj;
5474d94f 16128 asection *s, *srel;
b7693d02 16129 struct elf32_arm_link_hash_entry * eh;
67687978 16130 struct elf32_arm_link_hash_table *globals;
252b5132 16131
67687978 16132 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16133 if (globals == NULL)
16134 return FALSE;
16135
252b5132
RH		 16136 dynobj = elf_hash_table (info)->dynobj;
16137
16138 /* Make sure we know what is going on here. */
16139 BFD_ASSERT (dynobj != NULL
f5385ebf 16140 && (h->needs_plt
34e77a92 16141 || h->type == STT_GNU_IFUNC
60d67dc8 16142 || h->is_weakalias
f5385ebf
AM		 16143 || (h->def_dynamic
16144 && h->ref_regular
16145 && !h->def_regular)));
252b5132 16146
b7693d02
DJ		 16147 eh = (struct elf32_arm_link_hash_entry *) h;
16148
252b5132
RH		 16149 /* If this is a function, put it in the procedure linkage table. We
16150 will fill in the contents of the procedure linkage table later,
16151 when we know the address of the .got section. */
34e77a92 16152 if (h->type == STT_FUNC || h->type == STT_GNU_IFUNC || h->needs_plt)
252b5132 16153 {
34e77a92
RS		 16154 /* Calls to STT_GNU_IFUNC symbols always use a PLT, even if the
16155 symbol binds locally. */
5e681ec4 16156 if (h->plt.refcount <= 0
34e77a92
RS		 16157 || (h->type != STT_GNU_IFUNC
16158 && (SYMBOL_CALLS_LOCAL (info, h)
16159 || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
16160 && h->root.type == bfd_link_hash_undefweak))))
252b5132
RH		 16161 {
16162 /* This case can occur if we saw a PLT32 reloc in an input
5e681ec4
PB		 16163 file, but the symbol was never referred to by a dynamic
16164 object, or if all references were garbage collected. In
16165 such a case, we don't actually need to build a procedure
16166 linkage table, and we can just do a PC24 reloc instead. */
16167 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 16168 eh->plt.thumb_refcount = 0;
16169 eh->plt.maybe_thumb_refcount = 0;
16170 eh->plt.noncall_refcount = 0;
f5385ebf 16171 h->needs_plt = 0;
252b5132
RH		 16172 }
16173
b34976b6 16174 return TRUE;
252b5132 16175 }
5e681ec4 16176 else
b7693d02
DJ		 16177 {
16178 /* It's possible that we incorrectly decided a .plt reloc was
16179 needed for an R_ARM_PC24 or similar reloc to a non-function sym
16180 in check_relocs. We can't decide accurately between function
16181 and non-function syms in check-relocs; Objects loaded later in
16182 the link may change h->type. So fix it now. */
16183 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 16184 eh->plt.thumb_refcount = 0;
16185 eh->plt.maybe_thumb_refcount = 0;
16186 eh->plt.noncall_refcount = 0;
b7693d02 16187 }
252b5132
RH		 16188
16189 /* If this is a weak symbol, and there is a real definition, the
16190 processor independent code will have arranged for us to see the
16191 real definition first, and we can just use the same value. */
60d67dc8 16192 if (h->is_weakalias)
252b5132 16193 {
60d67dc8
AM		 16194 struct elf_link_hash_entry *def = weakdef (h);
16195 BFD_ASSERT (def->root.type == bfd_link_hash_defined);
16196 h->root.u.def.section = def->root.u.def.section;
16197 h->root.u.def.value = def->root.u.def.value;
b34976b6 16198 return TRUE;
252b5132
RH		 16199 }
16200
ba93b8ac
DJ		 16201 /* If there are no non-GOT references, we do not need a copy
16202 relocation. */
16203 if (!h->non_got_ref)
16204 return TRUE;
16205
252b5132
RH		 16206 /* This is a reference to a symbol defined by a dynamic object which
16207 is not a function. */
16208
16209 /* If we are creating a shared library, we must presume that the
16210 only references to the symbol are via the global offset table.
16211 For such cases we need not do anything here; the relocations will
67687978
PB		 16212 be handled correctly by relocate_section. Relocatable executables
16213 can reference data in shared objects directly, so we don't need to
16214 do anything here. */
0e1862bb 16215 if (bfd_link_pic (info) || globals->root.is_relocatable_executable)
b34976b6 16216 return TRUE;
252b5132
RH		 16217
16218 /* We must allocate the symbol in our .dynbss section, which will
16219 become part of the .bss section of the executable. There will be
16220 an entry for this symbol in the .dynsym section. The dynamic
16221 object will contain position independent code, so all references
16222 from the dynamic object to this symbol will go through the global
16223 offset table. The dynamic linker will use the .dynsym entry to
16224 determine the address it must put in the global offset table, so
16225 both the dynamic object and the regular object will refer to the
16226 same memory location for the variable. */
5522f910
NC		 16227 /* If allowed, we must generate a R_ARM_COPY reloc to tell the dynamic
16228 linker to copy the initial value out of the dynamic object and into
16229 the runtime process image. We need to remember the offset into the
00a97672 16230 .rel(a).bss section we are going to use. */
5474d94f
AM		 16231 if ((h->root.u.def.section->flags & SEC_READONLY) != 0)
16232 {
16233 s = globals->root.sdynrelro;
16234 srel = globals->root.sreldynrelro;
16235 }
16236 else
16237 {
16238 s = globals->root.sdynbss;
16239 srel = globals->root.srelbss;
16240 }
5522f910
NC		 16241 if (info->nocopyreloc == 0
16242 && (h->root.u.def.section->flags & SEC_ALLOC) != 0
5522f910 16243 && h->size != 0)
252b5132 16244 {
47beaa6a 16245 elf32_arm_allocate_dynrelocs (info, srel, 1);
f5385ebf 16246 h->needs_copy = 1;
252b5132
RH		 16247 }
16248
6cabe1ea 16249 return _bfd_elf_adjust_dynamic_copy (info, h, s);
252b5132
RH		 16250}
16251
5e681ec4
PB		 16252/* Allocate space in .plt, .got and associated reloc sections for
16253 dynamic relocs. */
16254
16255static bfd_boolean
47beaa6a 16256allocate_dynrelocs_for_symbol (struct elf_link_hash_entry *h, void * inf)
5e681ec4
PB		 16257{
16258 struct bfd_link_info *info;
16259 struct elf32_arm_link_hash_table *htab;
16260 struct elf32_arm_link_hash_entry *eh;
0bdcacaf 16261 struct elf_dyn_relocs *p;
5e681ec4
PB		 16262
16263 if (h->root.type == bfd_link_hash_indirect)
16264 return TRUE;
16265
e6a6bb22
AM		 16266 eh = (struct elf32_arm_link_hash_entry *) h;
16267
5e681ec4
PB		 16268 info = (struct bfd_link_info *) inf;
16269 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16270 if (htab == NULL)
16271 return FALSE;
5e681ec4 16272
34e77a92 16273 if ((htab->root.dynamic_sections_created || h->type == STT_GNU_IFUNC)
5e681ec4
PB		 16274 && h->plt.refcount > 0)
16275 {
16276 /* Make sure this symbol is output as a dynamic symbol.
16277 Undefined weak syms won't yet be marked as dynamic. */
6c699715
RL		 16278 if (h->dynindx == -1 && !h->forced_local
16279 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 16280 {
c152c796 16281 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 16282 return FALSE;
16283 }
16284
34e77a92
RS		 16285 /* If the call in the PLT entry binds locally, the associated
16286 GOT entry should use an R_ARM_IRELATIVE relocation instead of
16287 the usual R_ARM_JUMP_SLOT. Put it in the .iplt section rather
16288 than the .plt section. */
16289 if (h->type == STT_GNU_IFUNC && SYMBOL_CALLS_LOCAL (info, h))
16290 {
16291 eh->is_iplt = 1;
16292 if (eh->plt.noncall_refcount == 0
16293 && SYMBOL_REFERENCES_LOCAL (info, h))
16294 /* All non-call references can be resolved directly.
16295 This means that they can (and in some cases, must)
16296 resolve directly to the run-time target, rather than
16297 to the PLT. That in turns means that any .got entry
16298 would be equal to the .igot.plt entry, so there's
16299 no point having both. */
16300 h->got.refcount = 0;
16301 }
16302
0e1862bb 16303 if (bfd_link_pic (info)
34e77a92 16304 || eh->is_iplt
7359ea65 16305 || WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, 0, h))
5e681ec4 16306 {
34e77a92 16307 elf32_arm_allocate_plt_entry (info, eh->is_iplt, &h->plt, &eh->plt);
b7693d02 16308
5e681ec4
PB		 16309 /* If this symbol is not defined in a regular file, and we are
16310 not generating a shared library, then set the symbol to this
16311 location in the .plt. This is required to make function
16312 pointers compare as equal between the normal executable and
16313 the shared library. */
0e1862bb 16314 if (! bfd_link_pic (info)
f5385ebf 16315 && !h->def_regular)
5e681ec4 16316 {
34e77a92 16317 h->root.u.def.section = htab->root.splt;
5e681ec4 16318 h->root.u.def.value = h->plt.offset;
5e681ec4 16319
67d74e43
DJ		 16320 /* Make sure the function is not marked as Thumb, in case
16321 it is the target of an ABS32 relocation, which will
16322 point to the PLT entry. */
39d911fc 16323 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
67d74e43 16324 }
022f8312 16325
00a97672
RS		 16326 /* VxWorks executables have a second set of relocations for
16327 each PLT entry. They go in a separate relocation section,
16328 which is processed by the kernel loader. */
0e1862bb 16329 if (htab->vxworks_p && !bfd_link_pic (info))
00a97672
RS		 16330 {
16331 /* There is a relocation for the initial PLT entry:
16332 an R_ARM_32 relocation for _GLOBAL_OFFSET_TABLE_. */
16333 if (h->plt.offset == htab->plt_header_size)
47beaa6a 16334 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 1);
00a97672
RS		 16335
16336 /* There are two extra relocations for each subsequent
16337 PLT entry: an R_ARM_32 relocation for the GOT entry,
16338 and an R_ARM_32 relocation for the PLT entry. */
47beaa6a 16339 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 2);
00a97672 16340 }
5e681ec4
PB		 16341 }
16342 else
16343 {
16344 h->plt.offset = (bfd_vma) -1;
f5385ebf 16345 h->needs_plt = 0;
5e681ec4
PB		 16346 }
16347 }
16348 else
16349 {
16350 h->plt.offset = (bfd_vma) -1;
f5385ebf 16351 h->needs_plt = 0;
5e681ec4
PB		 16352 }
16353
0855e32b
NS		 16354 eh = (struct elf32_arm_link_hash_entry *) h;
16355 eh->tlsdesc_got = (bfd_vma) -1;
16356
5e681ec4
PB		 16357 if (h->got.refcount > 0)
16358 {
16359 asection *s;
16360 bfd_boolean dyn;
ba93b8ac
DJ		 16361 int tls_type = elf32_arm_hash_entry (h)->tls_type;
16362 int indx;
5e681ec4
PB		 16363
16364 /* Make sure this symbol is output as a dynamic symbol.
16365 Undefined weak syms won't yet be marked as dynamic. */
e8b09b87 16366 if (htab->root.dynamic_sections_created && h->dynindx == -1 && !h->forced_local
6c699715 16367 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 16368 {
c152c796 16369 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 16370 return FALSE;
16371 }
16372
e5a52504
MM		 16373 if (!htab->symbian_p)
16374 {
362d30a1 16375 s = htab->root.sgot;
e5a52504 16376 h->got.offset = s->size;
ba93b8ac
DJ		 16377
16378 if (tls_type == GOT_UNKNOWN)
16379 abort ();
16380
16381 if (tls_type == GOT_NORMAL)
16382 /* Non-TLS symbols need one GOT slot. */
16383 s->size += 4;
16384 else
16385 {
99059e56
RM		 16386 if (tls_type & GOT_TLS_GDESC)
16387 {
0855e32b 16388 /* R_ARM_TLS_DESC needs 2 GOT slots. */
99059e56 16389 eh->tlsdesc_got
0855e32b
NS		 16390 = (htab->root.sgotplt->size
16391 - elf32_arm_compute_jump_table_size (htab));
99059e56
RM		 16392 htab->root.sgotplt->size += 8;
16393 h->got.offset = (bfd_vma) -2;
34e77a92 16394 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 16395 reloc in the middle of .got.plt. */
99059e56
RM		 16396 htab->num_tls_desc++;
16397 }
0855e32b 16398
ba93b8ac 16399 if (tls_type & GOT_TLS_GD)
0855e32b 16400 {
5c5a4843
CL		 16401 /* R_ARM_TLS_GD32 and R_ARM_TLS_GD32_FDPIC need two
16402 consecutive GOT slots. If the symbol is both GD
16403 and GDESC, got.offset may have been
16404 overwritten. */
0855e32b
NS		 16405 h->got.offset = s->size;
16406 s->size += 8;
16407 }
16408
ba93b8ac 16409 if (tls_type & GOT_TLS_IE)
5c5a4843
CL		 16410 /* R_ARM_TLS_IE32/R_ARM_TLS_IE32_FDPIC need one GOT
16411 slot. */
ba93b8ac
DJ		 16412 s->size += 4;
16413 }
16414
e5a52504 16415 dyn = htab->root.dynamic_sections_created;
ba93b8ac
DJ		 16416
16417 indx = 0;
0e1862bb
L		 16418 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
16419 bfd_link_pic (info),
16420 h)
16421 && (!bfd_link_pic (info)
ba93b8ac
DJ		 16422 || !SYMBOL_REFERENCES_LOCAL (info, h)))
16423 indx = h->dynindx;
16424
16425 if (tls_type != GOT_NORMAL
9cb09e33 16426 && (bfd_link_dll (info) || indx != 0)
ba93b8ac
DJ		 16427 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
16428 || h->root.type != bfd_link_hash_undefweak))
16429 {
16430 if (tls_type & GOT_TLS_IE)
47beaa6a 16431 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 16432
16433 if (tls_type & GOT_TLS_GD)
47beaa6a 16434 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 16435
b38cadfb 16436 if (tls_type & GOT_TLS_GDESC)
0855e32b 16437 {
47beaa6a 16438 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
0855e32b
NS		 16439 /* GDESC needs a trampoline to jump to. */
16440 htab->tls_trampoline = -1;
16441 }
16442
16443 /* Only GD needs it. GDESC just emits one relocation per
16444 2 entries. */
b38cadfb 16445 if ((tls_type & GOT_TLS_GD) && indx != 0)
47beaa6a 16446 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 16447 }
e8b09b87
CL		 16448 else if (((indx != -1) || htab->fdpic_p)
16449 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 16450 {
16451 if (htab->root.dynamic_sections_created)
16452 /* Reserve room for the GOT entry's R_ARM_GLOB_DAT relocation. */
16453 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16454 }
34e77a92
RS		 16455 else if (h->type == STT_GNU_IFUNC
16456 && eh->plt.noncall_refcount == 0)
16457 /* No non-call references resolve the STT_GNU_IFUNC's PLT entry;
16458 they all resolve dynamically instead. Reserve room for the
16459 GOT entry's R_ARM_IRELATIVE relocation. */
16460 elf32_arm_allocate_irelocs (info, htab->root.srelgot, 1);
0e1862bb 16461 else if (bfd_link_pic (info)
7f026732 16462 && !UNDEFWEAK_NO_DYNAMIC_RELOC (info, h))
b436d854 16463 /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
47beaa6a 16464 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
e8b09b87
CL		 16465 else if (htab->fdpic_p && tls_type == GOT_NORMAL)
16466 /* Reserve room for rofixup for FDPIC executable. */
16467 /* TLS relocs do not need space since they are completely
16468 resolved. */
16469 htab->srofixup->size += 4;
e5a52504 16470 }
5e681ec4
PB		 16471 }
16472 else
16473 h->got.offset = (bfd_vma) -1;
16474
e8b09b87
CL		 16475 /* FDPIC support. */
16476 if (eh->fdpic_cnts.gotofffuncdesc_cnt > 0)
16477 {
16478 /* Symbol musn't be exported. */
16479 if (h->dynindx != -1)
16480 abort();
16481
16482 /* We only allocate one function descriptor with its associated relocation. */
16483 if (eh->fdpic_cnts.funcdesc_offset == -1)
16484 {
16485 asection *s = htab->root.sgot;
16486
16487 eh->fdpic_cnts.funcdesc_offset = s->size;
16488 s->size += 8;
16489 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16490 if (bfd_link_pic(info))
16491 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16492 else
16493 htab->srofixup->size += 8;
16494 }
16495 }
16496
16497 if (eh->fdpic_cnts.gotfuncdesc_cnt > 0)
16498 {
16499 asection *s = htab->root.sgot;
16500
16501 if (htab->root.dynamic_sections_created && h->dynindx == -1
16502 && !h->forced_local)
16503 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16504 return FALSE;
16505
16506 if (h->dynindx == -1)
16507 {
16508 /* We only allocate one function descriptor with its associated relocation. q */
16509 if (eh->fdpic_cnts.funcdesc_offset == -1)
16510 {
16511
16512 eh->fdpic_cnts.funcdesc_offset = s->size;
16513 s->size += 8;
16514 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16515 if (bfd_link_pic(info))
16516 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16517 else
16518 htab->srofixup->size += 8;
16519 }
16520 }
16521
16522 /* Add one entry into the GOT and a R_ARM_FUNCDESC or
16523 R_ARM_RELATIVE/rofixup relocation on it. */
16524 eh->fdpic_cnts.gotfuncdesc_offset = s->size;
16525 s->size += 4;
16526 if (h->dynindx == -1 && !bfd_link_pic(info))
4b24dd1a 16527 htab->srofixup->size += 4;
e8b09b87 16528 else
4b24dd1a 16529 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
e8b09b87
CL		 16530 }
16531
16532 if (eh->fdpic_cnts.funcdesc_cnt > 0)
16533 {
16534 if (htab->root.dynamic_sections_created && h->dynindx == -1
16535 && !h->forced_local)
16536 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16537 return FALSE;
16538
16539 if (h->dynindx == -1)
16540 {
16541 /* We only allocate one function descriptor with its associated relocation. */
16542 if (eh->fdpic_cnts.funcdesc_offset == -1)
16543 {
16544 asection *s = htab->root.sgot;
16545
16546 eh->fdpic_cnts.funcdesc_offset = s->size;
16547 s->size += 8;
16548 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16549 if (bfd_link_pic(info))
16550 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16551 else
16552 htab->srofixup->size += 8;
16553 }
16554 }
16555 if (h->dynindx == -1 && !bfd_link_pic(info))
16556 {
16557 /* For FDPIC executable we replace R_ARM_RELATIVE with a rofixup. */
16558 htab->srofixup->size += 4 * eh->fdpic_cnts.funcdesc_cnt;
16559 }
16560 else
16561 {
16562 /* Will need one dynamic reloc per reference. will be either
16563 R_ARM_FUNCDESC or R_ARM_RELATIVE for hidden symbols. */
16564 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot,
16565 eh->fdpic_cnts.funcdesc_cnt);
16566 }
16567 }
16568
a4fd1a8e
PB		 16569 /* Allocate stubs for exported Thumb functions on v4t. */
16570 if (!htab->use_blx && h->dynindx != -1
0eaedd0e 16571 && h->def_regular
39d911fc 16572 && ARM_GET_SYM_BRANCH_TYPE (h->target_internal) == ST_BRANCH_TO_THUMB
a4fd1a8e
PB		 16573 && ELF_ST_VISIBILITY (h->other) == STV_DEFAULT)
16574 {
16575 struct elf_link_hash_entry * th;
16576 struct bfd_link_hash_entry * bh;
16577 struct elf_link_hash_entry * myh;
16578 char name[1024];
16579 asection *s;
16580 bh = NULL;
16581 /* Create a new symbol to regist the real location of the function. */
16582 s = h->root.u.def.section;
906e58ca 16583 sprintf (name, "__real_%s", h->root.root.string);
a4fd1a8e
PB		 16584 _bfd_generic_link_add_one_symbol (info, s->owner,
16585 name, BSF_GLOBAL, s,
16586 h->root.u.def.value,
16587 NULL, TRUE, FALSE, &bh);
16588
16589 myh = (struct elf_link_hash_entry *) bh;
35fc36a8 16590 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
a4fd1a8e 16591 myh->forced_local = 1;
39d911fc 16592 ARM_SET_SYM_BRANCH_TYPE (myh->target_internal, ST_BRANCH_TO_THUMB);
a4fd1a8e
PB		 16593 eh->export_glue = myh;
16594 th = record_arm_to_thumb_glue (info, h);
16595 /* Point the symbol at the stub. */
16596 h->type = ELF_ST_INFO (ELF_ST_BIND (h->type), STT_FUNC);
39d911fc 16597 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
a4fd1a8e
PB		 16598 h->root.u.def.section = th->root.u.def.section;
16599 h->root.u.def.value = th->root.u.def.value & ~1;
16600 }
16601
0bdcacaf 16602 if (eh->dyn_relocs == NULL)
5e681ec4
PB		 16603 return TRUE;
16604
16605 /* In the shared -Bsymbolic case, discard space allocated for
16606 dynamic pc-relative relocs against symbols which turn out to be
16607 defined in regular objects. For the normal shared case, discard
16608 space for pc-relative relocs that have become local due to symbol
16609 visibility changes. */
16610
e8b09b87 16611 if (bfd_link_pic (info) || htab->root.is_relocatable_executable || htab->fdpic_p)
5e681ec4 16612 {
469a3493
RM		 16613 /* Relocs that use pc_count are PC-relative forms, which will appear
16614 on something like ".long foo - ." or "movw REG, foo - .". We want
16615 calls to protected symbols to resolve directly to the function
16616 rather than going via the plt. If people want function pointer
16617 comparisons to work as expected then they should avoid writing
16618 assembly like ".long foo - .". */
ba93b8ac
DJ		 16619 if (SYMBOL_CALLS_LOCAL (info, h))
16620 {
0bdcacaf 16621 struct elf_dyn_relocs **pp;
ba93b8ac 16622
0bdcacaf 16623 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
ba93b8ac
DJ		 16624 {
16625 p->count -= p->pc_count;
16626 p->pc_count = 0;
16627 if (p->count == 0)
16628 *pp = p->next;
16629 else
16630 pp = &p->next;
16631 }
16632 }
16633
4dfe6ac6 16634 if (htab->vxworks_p)
3348747a 16635 {
0bdcacaf 16636 struct elf_dyn_relocs **pp;
3348747a 16637
0bdcacaf 16638 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
3348747a 16639 {
0bdcacaf 16640 if (strcmp (p->sec->output_section->name, ".tls_vars") == 0)
3348747a
NS		 16641 *pp = p->next;
16642 else
16643 pp = &p->next;
16644 }
16645 }
16646
ba93b8ac 16647 /* Also discard relocs on undefined weak syms with non-default
99059e56 16648 visibility. */
0bdcacaf 16649 if (eh->dyn_relocs != NULL
5e681ec4 16650 && h->root.type == bfd_link_hash_undefweak)
22d606e9 16651 {
95b03e4a
L		 16652 if (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
16653 || UNDEFWEAK_NO_DYNAMIC_RELOC (info, h))
0bdcacaf 16654 eh->dyn_relocs = NULL;
22d606e9
AM		 16655
16656 /* Make sure undefined weak symbols are output as a dynamic
16657 symbol in PIEs. */
e8b09b87 16658 else if (htab->root.dynamic_sections_created && h->dynindx == -1
22d606e9
AM		 16659 && !h->forced_local)
16660 {
16661 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16662 return FALSE;
16663 }
16664 }
16665
67687978
PB		 16666 else if (htab->root.is_relocatable_executable && h->dynindx == -1
16667 && h->root.type == bfd_link_hash_new)
16668 {
16669 /* Output absolute symbols so that we can create relocations
16670 against them. For normal symbols we output a relocation
16671 against the section that contains them. */
16672 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16673 return FALSE;
16674 }
16675
5e681ec4
PB		 16676 }
16677 else
16678 {
16679 /* For the non-shared case, discard space for relocs against
16680 symbols which turn out to need copy relocs or are not
16681 dynamic. */
16682
f5385ebf
AM		 16683 if (!h->non_got_ref
16684 && ((h->def_dynamic
16685 && !h->def_regular)
5e681ec4
PB		 16686 || (htab->root.dynamic_sections_created
16687 && (h->root.type == bfd_link_hash_undefweak
16688 || h->root.type == bfd_link_hash_undefined))))
16689 {
16690 /* Make sure this symbol is output as a dynamic symbol.
16691 Undefined weak syms won't yet be marked as dynamic. */
6c699715
RL		 16692 if (h->dynindx == -1 && !h->forced_local
16693 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 16694 {
c152c796 16695 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 16696 return FALSE;
16697 }
16698
16699 /* If that succeeded, we know we'll be keeping all the
16700 relocs. */
16701 if (h->dynindx != -1)
16702 goto keep;
16703 }
16704
0bdcacaf 16705 eh->dyn_relocs = NULL;
5e681ec4
PB		 16706
16707 keep: ;
16708 }
16709
16710 /* Finally, allocate space. */
0bdcacaf 16711 for (p = eh->dyn_relocs; p != NULL; p = p->next)
5e681ec4 16712 {
0bdcacaf 16713 asection *sreloc = elf_section_data (p->sec)->sreloc;
e8b09b87 16714
34e77a92
RS		 16715 if (h->type == STT_GNU_IFUNC
16716 && eh->plt.noncall_refcount == 0
16717 && SYMBOL_REFERENCES_LOCAL (info, h))
16718 elf32_arm_allocate_irelocs (info, sreloc, p->count);
e8b09b87
CL		 16719 else if (h->dynindx != -1 && (!bfd_link_pic(info) || !info->symbolic || !h->def_regular))
16720 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
16721 else if (htab->fdpic_p && !bfd_link_pic(info))
16722 htab->srofixup->size += 4 * p->count;
34e77a92
RS		 16723 else
16724 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
5e681ec4
PB		 16725 }
16726
16727 return TRUE;
16728}
16729
63c1f59d
AM		 16730/* Set DF_TEXTREL if we find any dynamic relocs that apply to
16731 read-only sections. */
08d1f311
DJ		 16732
16733static bfd_boolean
63c1f59d 16734maybe_set_textrel (struct elf_link_hash_entry *h, void *info_p)
08d1f311 16735{
63c1f59d 16736 asection *sec;
08d1f311 16737
63c1f59d
AM		 16738 if (h->root.type == bfd_link_hash_indirect)
16739 return TRUE;
08d1f311 16740
63c1f59d
AM		 16741 sec = readonly_dynrelocs (h);
16742 if (sec != NULL)
16743 {
16744 struct bfd_link_info *info = (struct bfd_link_info *) info_p;
08d1f311 16745
63c1f59d
AM		 16746 info->flags |= DF_TEXTREL;
16747 info->callbacks->minfo
c1c8c1ef 16748 (_("%pB: dynamic relocation against `%pT' in read-only section `%pA'\n"),
63c1f59d 16749 sec->owner, h->root.root.string, sec);
08d1f311 16750
63c1f59d
AM		 16751 /* Not an error, just cut short the traversal. */
16752 return FALSE;
08d1f311 16753 }
cb10292c 16754
08d1f311
DJ		 16755 return TRUE;
16756}
16757
d504ffc8
DJ		 16758void
16759bfd_elf32_arm_set_byteswap_code (struct bfd_link_info *info,
16760 int byteswap_code)
16761{
16762 struct elf32_arm_link_hash_table *globals;
16763
16764 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16765 if (globals == NULL)
16766 return;
16767
d504ffc8
DJ		 16768 globals->byteswap_code = byteswap_code;
16769}
16770
252b5132
RH		 16771/* Set the sizes of the dynamic sections. */
16772
b34976b6 16773static bfd_boolean
57e8b36a
NC		 16774elf32_arm_size_dynamic_sections (bfd * output_bfd ATTRIBUTE_UNUSED,
16775 struct bfd_link_info * info)
252b5132
RH		 16776{
16777 bfd * dynobj;
16778 asection * s;
b34976b6
AM		 16779 bfd_boolean plt;
16780 bfd_boolean relocs;
5e681ec4
PB		 16781 bfd *ibfd;
16782 struct elf32_arm_link_hash_table *htab;
252b5132 16783
5e681ec4 16784 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16785 if (htab == NULL)
16786 return FALSE;
16787
252b5132
RH		 16788 dynobj = elf_hash_table (info)->dynobj;
16789 BFD_ASSERT (dynobj != NULL);
39b41c9c 16790 check_use_blx (htab);
252b5132
RH		 16791
16792 if (elf_hash_table (info)->dynamic_sections_created)
16793 {
16794 /* Set the contents of the .interp section to the interpreter. */
9b8b325a 16795 if (bfd_link_executable (info) && !info->nointerp)
252b5132 16796 {
3d4d4302 16797 s = bfd_get_linker_section (dynobj, ".interp");
252b5132 16798 BFD_ASSERT (s != NULL);
eea6121a 16799 s->size = sizeof ELF_DYNAMIC_INTERPRETER;
252b5132
RH		 16800 s->contents = (unsigned char *) ELF_DYNAMIC_INTERPRETER;
16801 }
16802 }
5e681ec4
PB		 16803
16804 /* Set up .got offsets for local syms, and space for local dynamic
16805 relocs. */
c72f2fb2 16806 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
252b5132 16807 {
5e681ec4
PB		 16808 bfd_signed_vma *local_got;
16809 bfd_signed_vma *end_local_got;
34e77a92 16810 struct arm_local_iplt_info **local_iplt_ptr, *local_iplt;
5e681ec4 16811 char *local_tls_type;
0855e32b 16812 bfd_vma *local_tlsdesc_gotent;
5e681ec4
PB		 16813 bfd_size_type locsymcount;
16814 Elf_Internal_Shdr *symtab_hdr;
16815 asection *srel;
4dfe6ac6 16816 bfd_boolean is_vxworks = htab->vxworks_p;
34e77a92 16817 unsigned int symndx;
e8b09b87 16818 struct fdpic_local *local_fdpic_cnts;
5e681ec4 16819
0ffa91dd 16820 if (! is_arm_elf (ibfd))
5e681ec4
PB		 16821 continue;
16822
16823 for (s = ibfd->sections; s != NULL; s = s->next)
16824 {
0bdcacaf 16825 struct elf_dyn_relocs *p;
5e681ec4 16826
0bdcacaf 16827 for (p = (struct elf_dyn_relocs *)
99059e56 16828 elf_section_data (s)->local_dynrel; p != NULL; p = p->next)
5e681ec4 16829 {
0bdcacaf
RS		 16830 if (!bfd_is_abs_section (p->sec)
16831 && bfd_is_abs_section (p->sec->output_section))
5e681ec4
PB		 16832 {
16833 /* Input section has been discarded, either because
16834 it is a copy of a linkonce section or due to
16835 linker script /DISCARD/, so we'll be discarding
16836 the relocs too. */
16837 }
3348747a 16838 else if (is_vxworks
0bdcacaf 16839 && strcmp (p->sec->output_section->name,
3348747a
NS		 16840 ".tls_vars") == 0)
16841 {
16842 /* Relocations in vxworks .tls_vars sections are
16843 handled specially by the loader. */
16844 }
5e681ec4
PB		 16845 else if (p->count != 0)
16846 {
0bdcacaf 16847 srel = elf_section_data (p->sec)->sreloc;
e8b09b87
CL		 16848 if (htab->fdpic_p && !bfd_link_pic(info))
16849 htab->srofixup->size += 4 * p->count;
16850 else
16851 elf32_arm_allocate_dynrelocs (info, srel, p->count);
0bdcacaf 16852 if ((p->sec->output_section->flags & SEC_READONLY) != 0)
5e681ec4
PB		 16853 info->flags |= DF_TEXTREL;
16854 }
16855 }
16856 }
16857
16858 local_got = elf_local_got_refcounts (ibfd);
16859 if (!local_got)
16860 continue;
16861
0ffa91dd 16862 symtab_hdr = & elf_symtab_hdr (ibfd);
5e681ec4
PB		 16863 locsymcount = symtab_hdr->sh_info;
16864 end_local_got = local_got + locsymcount;
34e77a92 16865 local_iplt_ptr = elf32_arm_local_iplt (ibfd);
ba93b8ac 16866 local_tls_type = elf32_arm_local_got_tls_type (ibfd);
0855e32b 16867 local_tlsdesc_gotent = elf32_arm_local_tlsdesc_gotent (ibfd);
e8b09b87 16868 local_fdpic_cnts = elf32_arm_local_fdpic_cnts (ibfd);
34e77a92 16869 symndx = 0;
362d30a1
RS		 16870 s = htab->root.sgot;
16871 srel = htab->root.srelgot;
0855e32b 16872 for (; local_got < end_local_got;
34e77a92 16873 ++local_got, ++local_iplt_ptr, ++local_tls_type,
e8b09b87 16874 ++local_tlsdesc_gotent, ++symndx, ++local_fdpic_cnts)
5e681ec4 16875 {
0855e32b 16876 *local_tlsdesc_gotent = (bfd_vma) -1;
34e77a92 16877 local_iplt = *local_iplt_ptr;
e8b09b87
CL		 16878
16879 /* FDPIC support. */
16880 if (local_fdpic_cnts->gotofffuncdesc_cnt > 0)
16881 {
16882 if (local_fdpic_cnts->funcdesc_offset == -1)
16883 {
16884 local_fdpic_cnts->funcdesc_offset = s->size;
16885 s->size += 8;
16886
16887 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16888 if (bfd_link_pic(info))
16889 elf32_arm_allocate_dynrelocs (info, srel, 1);
16890 else
16891 htab->srofixup->size += 8;
16892 }
16893 }
16894
16895 if (local_fdpic_cnts->funcdesc_cnt > 0)
16896 {
16897 if (local_fdpic_cnts->funcdesc_offset == -1)
16898 {
16899 local_fdpic_cnts->funcdesc_offset = s->size;
16900 s->size += 8;
16901
16902 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16903 if (bfd_link_pic(info))
16904 elf32_arm_allocate_dynrelocs (info, srel, 1);
16905 else
16906 htab->srofixup->size += 8;
16907 }
16908
16909 /* We will add n R_ARM_RELATIVE relocations or n rofixups. */
16910 if (bfd_link_pic(info))
16911 elf32_arm_allocate_dynrelocs (info, srel, local_fdpic_cnts->funcdesc_cnt);
16912 else
16913 htab->srofixup->size += 4 * local_fdpic_cnts->funcdesc_cnt;
16914 }
16915
34e77a92
RS		 16916 if (local_iplt != NULL)
16917 {
16918 struct elf_dyn_relocs *p;
16919
16920 if (local_iplt->root.refcount > 0)
16921 {
16922 elf32_arm_allocate_plt_entry (info, TRUE,
16923 &local_iplt->root,
16924 &local_iplt->arm);
16925 if (local_iplt->arm.noncall_refcount == 0)
16926 /* All references to the PLT are calls, so all
16927 non-call references can resolve directly to the
16928 run-time target. This means that the .got entry
16929 would be the same as the .igot.plt entry, so there's
16930 no point creating both. */
16931 *local_got = 0;
16932 }
16933 else
16934 {
16935 BFD_ASSERT (local_iplt->arm.noncall_refcount == 0);
16936 local_iplt->root.offset = (bfd_vma) -1;
16937 }
16938
16939 for (p = local_iplt->dyn_relocs; p != NULL; p = p->next)
16940 {
16941 asection *psrel;
16942
16943 psrel = elf_section_data (p->sec)->sreloc;
16944 if (local_iplt->arm.noncall_refcount == 0)
16945 elf32_arm_allocate_irelocs (info, psrel, p->count);
16946 else
16947 elf32_arm_allocate_dynrelocs (info, psrel, p->count);
16948 }
16949 }
5e681ec4
PB		 16950 if (*local_got > 0)
16951 {
34e77a92
RS		 16952 Elf_Internal_Sym *isym;
16953
eea6121a 16954 *local_got = s->size;
ba93b8ac
DJ		 16955 if (*local_tls_type & GOT_TLS_GD)
16956 /* TLS_GD relocs need an 8-byte structure in the GOT. */
16957 s->size += 8;
0855e32b
NS		 16958 if (*local_tls_type & GOT_TLS_GDESC)
16959 {
16960 *local_tlsdesc_gotent = htab->root.sgotplt->size
16961 - elf32_arm_compute_jump_table_size (htab);
16962 htab->root.sgotplt->size += 8;
16963 *local_got = (bfd_vma) -2;
34e77a92 16964 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 16965 reloc in the middle of .got.plt. */
99059e56 16966 htab->num_tls_desc++;
0855e32b 16967 }
ba93b8ac
DJ		 16968 if (*local_tls_type & GOT_TLS_IE)
16969 s->size += 4;
ba93b8ac 16970
0855e32b
NS		 16971 if (*local_tls_type & GOT_NORMAL)
16972 {
16973 /* If the symbol is both GD and GDESC, *local_got
16974 may have been overwritten. */
16975 *local_got = s->size;
16976 s->size += 4;
16977 }
16978
34e77a92
RS		 16979 isym = bfd_sym_from_r_symndx (&htab->sym_cache, ibfd, symndx);
16980 if (isym == NULL)
16981 return FALSE;
16982
16983 /* If all references to an STT_GNU_IFUNC PLT are calls,
16984 then all non-call references, including this GOT entry,
16985 resolve directly to the run-time target. */
16986 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC
16987 && (local_iplt == NULL
16988 || local_iplt->arm.noncall_refcount == 0))
16989 elf32_arm_allocate_irelocs (info, srel, 1);
e8b09b87 16990 else if (bfd_link_pic (info) || output_bfd->flags & DYNAMIC || htab->fdpic_p)
0855e32b 16991 {
e8b09b87 16992 if ((bfd_link_pic (info) && !(*local_tls_type & GOT_TLS_GDESC)))
3064e1ff 16993 elf32_arm_allocate_dynrelocs (info, srel, 1);
e8b09b87
CL		 16994 else if (htab->fdpic_p && *local_tls_type & GOT_NORMAL)
16995 htab->srofixup->size += 4;
99059e56 16996
e8b09b87
CL		 16997 if ((bfd_link_pic (info) || htab->fdpic_p)
16998 && *local_tls_type & GOT_TLS_GDESC)
3064e1ff
JB		 16999 {
17000 elf32_arm_allocate_dynrelocs (info,
17001 htab->root.srelplt, 1);
17002 htab->tls_trampoline = -1;
17003 }
0855e32b 17004 }
5e681ec4
PB		 17005 }
17006 else
17007 *local_got = (bfd_vma) -1;
17008 }
252b5132
RH		 17009 }
17010
ba93b8ac
DJ		 17011 if (htab->tls_ldm_got.refcount > 0)
17012 {
17013 /* Allocate two GOT entries and one dynamic relocation (if necessary)
5c5a4843 17014 for R_ARM_TLS_LDM32/R_ARM_TLS_LDM32_FDPIC relocations. */
362d30a1
RS		 17015 htab->tls_ldm_got.offset = htab->root.sgot->size;
17016 htab->root.sgot->size += 8;
0e1862bb 17017 if (bfd_link_pic (info))
47beaa6a 17018 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 17019 }
17020 else
17021 htab->tls_ldm_got.offset = -1;
17022
e8b09b87
CL		 17023 /* At the very end of the .rofixup section is a pointer to the GOT,
17024 reserve space for it. */
17025 if (htab->fdpic_p && htab->srofixup != NULL)
17026 htab->srofixup->size += 4;
17027
5e681ec4
PB		 17028 /* Allocate global sym .plt and .got entries, and space for global
17029 sym dynamic relocs. */
47beaa6a 17030 elf_link_hash_traverse (& htab->root, allocate_dynrelocs_for_symbol, info);
252b5132 17031
d504ffc8 17032 /* Here we rummage through the found bfds to collect glue information. */
c72f2fb2 17033 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
c7b8f16e 17034 {
0ffa91dd 17035 if (! is_arm_elf (ibfd))
e44a2c9c
AM		 17036 continue;
17037
c7b8f16e
JB		 17038 /* Initialise mapping tables for code/data. */
17039 bfd_elf32_arm_init_maps (ibfd);
906e58ca 17040
c7b8f16e 17041 if (!bfd_elf32_arm_process_before_allocation (ibfd, info)
a504d23a
LA		 17042 || !bfd_elf32_arm_vfp11_erratum_scan (ibfd, info)
17043 || !bfd_elf32_arm_stm32l4xx_erratum_scan (ibfd, info))
90b6238f 17044 _bfd_error_handler (_("errors encountered processing file %pB"), ibfd);
c7b8f16e 17045 }
d504ffc8 17046
3e6b1042
DJ		 17047 /* Allocate space for the glue sections now that we've sized them. */
17048 bfd_elf32_arm_allocate_interworking_sections (info);
17049
0855e32b
NS		 17050 /* For every jump slot reserved in the sgotplt, reloc_count is
17051 incremented. However, when we reserve space for TLS descriptors,
17052 it's not incremented, so in order to compute the space reserved
17053 for them, it suffices to multiply the reloc count by the jump
17054 slot size. */
17055 if (htab->root.srelplt)
17056 htab->sgotplt_jump_table_size = elf32_arm_compute_jump_table_size(htab);
17057
17058 if (htab->tls_trampoline)
17059 {
17060 if (htab->root.splt->size == 0)
17061 htab->root.splt->size += htab->plt_header_size;
b38cadfb 17062
0855e32b
NS		 17063 htab->tls_trampoline = htab->root.splt->size;
17064 htab->root.splt->size += htab->plt_entry_size;
b38cadfb 17065
0855e32b 17066 /* If we're not using lazy TLS relocations, don't generate the
99059e56 17067 PLT and GOT entries they require. */
0855e32b
NS		 17068 if (!(info->flags & DF_BIND_NOW))
17069 {
17070 htab->dt_tlsdesc_got = htab->root.sgot->size;
17071 htab->root.sgot->size += 4;
17072
17073 htab->dt_tlsdesc_plt = htab->root.splt->size;
17074 htab->root.splt->size += 4 * ARRAY_SIZE (dl_tlsdesc_lazy_trampoline);
17075 }
17076 }
17077
252b5132
RH		 17078 /* The check_relocs and adjust_dynamic_symbol entry points have
17079 determined the sizes of the various dynamic sections. Allocate
17080 memory for them. */
b34976b6
AM		 17081 plt = FALSE;
17082 relocs = FALSE;
252b5132
RH		 17083 for (s = dynobj->sections; s != NULL; s = s->next)
17084 {
17085 const char * name;
252b5132
RH		 17086
17087 if ((s->flags & SEC_LINKER_CREATED) == 0)
17088 continue;
17089
17090 /* It's OK to base decisions on the section name, because none
17091 of the dynobj section names depend upon the input files. */
fd361982 17092 name = bfd_section_name (s);
252b5132 17093
34e77a92 17094 if (s == htab->root.splt)
252b5132 17095 {
c456f082
AM		 17096 /* Remember whether there is a PLT. */
17097 plt = s->size != 0;
252b5132 17098 }
0112cd26 17099 else if (CONST_STRNEQ (name, ".rel"))
252b5132 17100 {
c456f082 17101 if (s->size != 0)
252b5132 17102 {
252b5132 17103 /* Remember whether there are any reloc sections other
00a97672 17104 than .rel(a).plt and .rela.plt.unloaded. */
362d30a1 17105 if (s != htab->root.srelplt && s != htab->srelplt2)
b34976b6 17106 relocs = TRUE;
252b5132
RH		 17107
17108 /* We use the reloc_count field as a counter if we need
17109 to copy relocs into the output file. */
17110 s->reloc_count = 0;
17111 }
17112 }
34e77a92
RS		 17113 else if (s != htab->root.sgot
17114 && s != htab->root.sgotplt
17115 && s != htab->root.iplt
17116 && s != htab->root.igotplt
5474d94f 17117 && s != htab->root.sdynbss
e8b09b87
CL		 17118 && s != htab->root.sdynrelro
17119 && s != htab->srofixup)
252b5132
RH		 17120 {
17121 /* It's not one of our sections, so don't allocate space. */
17122 continue;
17123 }
17124
c456f082 17125 if (s->size == 0)
252b5132 17126 {
c456f082 17127 /* If we don't need this section, strip it from the
00a97672
RS		 17128 output file. This is mostly to handle .rel(a).bss and
17129 .rel(a).plt. We must create both sections in
c456f082
AM		 17130 create_dynamic_sections, because they must be created
17131 before the linker maps input sections to output
17132 sections. The linker does that before
17133 adjust_dynamic_symbol is called, and it is that
17134 function which decides whether anything needs to go
17135 into these sections. */
8423293d 17136 s->flags |= SEC_EXCLUDE;
252b5132
RH		 17137 continue;
17138 }
17139
c456f082
AM		 17140 if ((s->flags & SEC_HAS_CONTENTS) == 0)
17141 continue;
17142
252b5132 17143 /* Allocate memory for the section contents. */
21d799b5 17144 s->contents = (unsigned char *) bfd_zalloc (dynobj, s->size);
c456f082 17145 if (s->contents == NULL)
b34976b6 17146 return FALSE;
252b5132
RH		 17147 }
17148
17149 if (elf_hash_table (info)->dynamic_sections_created)
17150 {
17151 /* Add some entries to the .dynamic section. We fill in the
17152 values later, in elf32_arm_finish_dynamic_sections, but we
17153 must add the entries now so that we get the correct size for
17154 the .dynamic section. The DT_DEBUG entry is filled in by the
17155 dynamic linker and used by the debugger. */
dc810e39 17156#define add_dynamic_entry(TAG, VAL) \
5a580b3a 17157 _bfd_elf_add_dynamic_entry (info, TAG, VAL)
dc810e39 17158
0e1862bb 17159 if (bfd_link_executable (info))
252b5132 17160 {
dc810e39 17161 if (!add_dynamic_entry (DT_DEBUG, 0))
b34976b6 17162 return FALSE;
252b5132
RH		 17163 }
17164
17165 if (plt)
17166 {
dc810e39
AM		 17167 if ( !add_dynamic_entry (DT_PLTGOT, 0)
17168 || !add_dynamic_entry (DT_PLTRELSZ, 0)
00a97672
RS		 17169 || !add_dynamic_entry (DT_PLTREL,
17170 htab->use_rel ? DT_REL : DT_RELA)
dc810e39 17171 || !add_dynamic_entry (DT_JMPREL, 0))
b34976b6 17172 return FALSE;
0855e32b 17173
5025eb7c
AO		 17174 if (htab->dt_tlsdesc_plt
17175 && (!add_dynamic_entry (DT_TLSDESC_PLT,0)
17176 || !add_dynamic_entry (DT_TLSDESC_GOT,0)))
b38cadfb 17177 return FALSE;
252b5132
RH		 17178 }
17179
17180 if (relocs)
17181 {
00a97672
RS		 17182 if (htab->use_rel)
17183 {
17184 if (!add_dynamic_entry (DT_REL, 0)
17185 || !add_dynamic_entry (DT_RELSZ, 0)
17186 || !add_dynamic_entry (DT_RELENT, RELOC_SIZE (htab)))
17187 return FALSE;
17188 }
17189 else
17190 {
17191 if (!add_dynamic_entry (DT_RELA, 0)
17192 || !add_dynamic_entry (DT_RELASZ, 0)
17193 || !add_dynamic_entry (DT_RELAENT, RELOC_SIZE (htab)))
17194 return FALSE;
17195 }
252b5132
RH		 17196 }
17197
08d1f311
DJ		 17198 /* If any dynamic relocs apply to a read-only section,
17199 then we need a DT_TEXTREL entry. */
17200 if ((info->flags & DF_TEXTREL) == 0)
63c1f59d 17201 elf_link_hash_traverse (&htab->root, maybe_set_textrel, info);
08d1f311 17202
99e4ae17 17203 if ((info->flags & DF_TEXTREL) != 0)
252b5132 17204 {
dc810e39 17205 if (!add_dynamic_entry (DT_TEXTREL, 0))
b34976b6 17206 return FALSE;
252b5132 17207 }
7a2b07ff
NS		 17208 if (htab->vxworks_p
17209 && !elf_vxworks_add_dynamic_entries (output_bfd, info))
17210 return FALSE;
252b5132 17211 }
8532796c 17212#undef add_dynamic_entry
252b5132 17213
b34976b6 17214 return TRUE;
252b5132
RH		 17215}
17216
0855e32b
NS		 17217/* Size sections even though they're not dynamic. We use it to setup
17218 _TLS_MODULE_BASE_, if needed. */
17219
17220static bfd_boolean
17221elf32_arm_always_size_sections (bfd *output_bfd,
99059e56 17222 struct bfd_link_info *info)
0855e32b
NS		 17223{
17224 asection *tls_sec;
cb10292c
CL		 17225 struct elf32_arm_link_hash_table *htab;
17226
17227 htab = elf32_arm_hash_table (info);
0855e32b 17228
0e1862bb 17229 if (bfd_link_relocatable (info))
0855e32b
NS		 17230 return TRUE;
17231
17232 tls_sec = elf_hash_table (info)->tls_sec;
17233
17234 if (tls_sec)
17235 {
17236 struct elf_link_hash_entry *tlsbase;
17237
17238 tlsbase = elf_link_hash_lookup
17239 (elf_hash_table (info), "_TLS_MODULE_BASE_", TRUE, TRUE, FALSE);
17240
17241 if (tlsbase)
99059e56
RM		 17242 {
17243 struct bfd_link_hash_entry *bh = NULL;
0855e32b 17244 const struct elf_backend_data *bed
99059e56 17245 = get_elf_backend_data (output_bfd);
0855e32b 17246
99059e56 17247 if (!(_bfd_generic_link_add_one_symbol
0855e32b
NS		 17248 (info, output_bfd, "_TLS_MODULE_BASE_", BSF_LOCAL,
17249 tls_sec, 0, NULL, FALSE,
17250 bed->collect, &bh)))
17251 return FALSE;
b38cadfb 17252
99059e56
RM		 17253 tlsbase->type = STT_TLS;
17254 tlsbase = (struct elf_link_hash_entry *)bh;
17255 tlsbase->def_regular = 1;
17256 tlsbase->other = STV_HIDDEN;
17257 (*bed->elf_backend_hide_symbol) (info, tlsbase, TRUE);
0855e32b
NS		 17258 }
17259 }
cb10292c
CL		 17260
17261 if (htab->fdpic_p && !bfd_link_relocatable (info)
17262 && !bfd_elf_stack_segment_size (output_bfd, info,
17263 "__stacksize", DEFAULT_STACK_SIZE))
17264 return FALSE;
17265
0855e32b
NS		 17266 return TRUE;
17267}
17268
252b5132
RH		 17269/* Finish up dynamic symbol handling. We set the contents of various
17270 dynamic sections here. */
17271
b34976b6 17272static bfd_boolean
906e58ca
NC		 17273elf32_arm_finish_dynamic_symbol (bfd * output_bfd,
17274 struct bfd_link_info * info,
17275 struct elf_link_hash_entry * h,
17276 Elf_Internal_Sym * sym)
252b5132 17277{
e5a52504 17278 struct elf32_arm_link_hash_table *htab;
b7693d02 17279 struct elf32_arm_link_hash_entry *eh;
252b5132 17280
e5a52504 17281 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 17282 if (htab == NULL)
17283 return FALSE;
17284
b7693d02 17285 eh = (struct elf32_arm_link_hash_entry *) h;
252b5132
RH		 17286
17287 if (h->plt.offset != (bfd_vma) -1)
17288 {
34e77a92 17289 if (!eh->is_iplt)
e5a52504 17290 {
34e77a92 17291 BFD_ASSERT (h->dynindx != -1);
57460bcf
NC		 17292 if (! elf32_arm_populate_plt_entry (output_bfd, info, &h->plt, &eh->plt,
17293 h->dynindx, 0))
17294 return FALSE;
e5a52504 17295 }
57e8b36a 17296
f5385ebf 17297 if (!h->def_regular)
252b5132
RH		 17298 {
17299 /* Mark the symbol as undefined, rather than as defined in
3a635617 17300 the .plt section. */
252b5132 17301 sym->st_shndx = SHN_UNDEF;
3a635617 17302 /* If the symbol is weak we need to clear the value.
d982ba73
PB		 17303 Otherwise, the PLT entry would provide a definition for
17304 the symbol even if the symbol wasn't defined anywhere,
3a635617
WN		 17305 and so the symbol would never be NULL. Leave the value if
17306 there were any relocations where pointer equality matters
17307 (this is a clue for the dynamic linker, to make function
17308 pointer comparisons work between an application and shared
17309 library). */
97323ad1 17310 if (!h->ref_regular_nonweak || !h->pointer_equality_needed)
d982ba73 17311 sym->st_value = 0;
252b5132 17312 }
34e77a92
RS		 17313 else if (eh->is_iplt && eh->plt.noncall_refcount != 0)
17314 {
17315 /* At least one non-call relocation references this .iplt entry,
17316 so the .iplt entry is the function's canonical address. */
17317 sym->st_info = ELF_ST_INFO (ELF_ST_BIND (sym->st_info), STT_FUNC);
39d911fc 17318 ARM_SET_SYM_BRANCH_TYPE (sym->st_target_internal, ST_BRANCH_TO_ARM);
34e77a92
RS		 17319 sym->st_shndx = (_bfd_elf_section_from_bfd_section
17320 (output_bfd, htab->root.iplt->output_section));
17321 sym->st_value = (h->plt.offset
17322 + htab->root.iplt->output_section->vma
17323 + htab->root.iplt->output_offset);
17324 }
252b5132
RH		 17325 }
17326
f5385ebf 17327 if (h->needs_copy)
252b5132
RH		 17328 {
17329 asection * s;
947216bf 17330 Elf_Internal_Rela rel;
252b5132
RH		 17331
17332 /* This symbol needs a copy reloc. Set it up. */
252b5132
RH		 17333 BFD_ASSERT (h->dynindx != -1
17334 && (h->root.type == bfd_link_hash_defined
17335 || h->root.type == bfd_link_hash_defweak));
17336
00a97672 17337 rel.r_addend = 0;
252b5132
RH		 17338 rel.r_offset = (h->root.u.def.value
17339 + h->root.u.def.section->output_section->vma
17340 + h->root.u.def.section->output_offset);
17341 rel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_COPY);
afbf7e8e 17342 if (h->root.u.def.section == htab->root.sdynrelro)
5474d94f
AM		 17343 s = htab->root.sreldynrelro;
17344 else
17345 s = htab->root.srelbss;
47beaa6a 17346 elf32_arm_add_dynreloc (output_bfd, info, s, &rel);
252b5132
RH		 17347 }
17348
00a97672 17349 /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. On VxWorks,
fac7bd64
CL		 17350 and for FDPIC, the _GLOBAL_OFFSET_TABLE_ symbol is not absolute:
17351 it is relative to the ".got" section. */
9637f6ef 17352 if (h == htab->root.hdynamic
fac7bd64 17353 || (!htab->fdpic_p && !htab->vxworks_p && h == htab->root.hgot))
252b5132
RH		 17354 sym->st_shndx = SHN_ABS;
17355
b34976b6 17356 return TRUE;
252b5132
RH		 17357}
17358
0855e32b
NS		 17359static void
17360arm_put_trampoline (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
17361 void *contents,
17362 const unsigned long *template, unsigned count)
17363{
17364 unsigned ix;
b38cadfb 17365
0855e32b
NS		 17366 for (ix = 0; ix != count; ix++)
17367 {
17368 unsigned long insn = template[ix];
17369
17370 /* Emit mov pc,rx if bx is not permitted. */
17371 if (htab->fix_v4bx == 1 && (insn & 0x0ffffff0) == 0x012fff10)
17372 insn = (insn & 0xf000000f) | 0x01a0f000;
17373 put_arm_insn (htab, output_bfd, insn, (char *)contents + ix*4);
17374 }
17375}
17376
99059e56
RM		 17377/* Install the special first PLT entry for elf32-arm-nacl. Unlike
17378 other variants, NaCl needs this entry in a static executable's
17379 .iplt too. When we're handling that case, GOT_DISPLACEMENT is
17380 zero. For .iplt really only the last bundle is useful, and .iplt
17381 could have a shorter first entry, with each individual PLT entry's
17382 relative branch calculated differently so it targets the last
17383 bundle instead of the instruction before it (labelled .Lplt_tail
17384 above). But it's simpler to keep the size and layout of PLT0
17385 consistent with the dynamic case, at the cost of some dead code at
17386 the start of .iplt and the one dead store to the stack at the start
17387 of .Lplt_tail. */
17388static void
17389arm_nacl_put_plt0 (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
17390 asection *plt, bfd_vma got_displacement)
17391{
17392 unsigned int i;
17393
17394 put_arm_insn (htab, output_bfd,
17395 elf32_arm_nacl_plt0_entry[0]
17396 | arm_movw_immediate (got_displacement),
17397 plt->contents + 0);
17398 put_arm_insn (htab, output_bfd,
17399 elf32_arm_nacl_plt0_entry[1]
17400 | arm_movt_immediate (got_displacement),
17401 plt->contents + 4);
17402
17403 for (i = 2; i < ARRAY_SIZE (elf32_arm_nacl_plt0_entry); ++i)
17404 put_arm_insn (htab, output_bfd,
17405 elf32_arm_nacl_plt0_entry[i],
17406 plt->contents + (i * 4));
17407}
17408
252b5132
RH		 17409/* Finish up the dynamic sections. */
17410
b34976b6 17411static bfd_boolean
57e8b36a 17412elf32_arm_finish_dynamic_sections (bfd * output_bfd, struct bfd_link_info * info)
252b5132
RH		 17413{
17414 bfd * dynobj;
17415 asection * sgot;
17416 asection * sdyn;
4dfe6ac6
NC		 17417 struct elf32_arm_link_hash_table *htab;
17418
17419 htab = elf32_arm_hash_table (info);
17420 if (htab == NULL)
17421 return FALSE;
252b5132
RH		 17422
17423 dynobj = elf_hash_table (info)->dynobj;
17424
362d30a1 17425 sgot = htab->root.sgotplt;
894891db
NC		 17426 /* A broken linker script might have discarded the dynamic sections.
17427 Catch this here so that we do not seg-fault later on. */
17428 if (sgot != NULL && bfd_is_abs_section (sgot->output_section))
17429 return FALSE;
3d4d4302 17430 sdyn = bfd_get_linker_section (dynobj, ".dynamic");
252b5132
RH		 17431
17432 if (elf_hash_table (info)->dynamic_sections_created)
17433 {
17434 asection *splt;
17435 Elf32_External_Dyn *dyncon, *dynconend;
17436
362d30a1 17437 splt = htab->root.splt;
24a1ba0f 17438 BFD_ASSERT (splt != NULL && sdyn != NULL);
cbc704f3 17439 BFD_ASSERT (htab->symbian_p || sgot != NULL);
252b5132
RH		 17440
17441 dyncon = (Elf32_External_Dyn *) sdyn->contents;
eea6121a 17442 dynconend = (Elf32_External_Dyn *) (sdyn->contents + sdyn->size);
9b485d32 17443
252b5132
RH		 17444 for (; dyncon < dynconend; dyncon++)
17445 {
17446 Elf_Internal_Dyn dyn;
17447 const char * name;
17448 asection * s;
17449
17450 bfd_elf32_swap_dyn_in (dynobj, dyncon, &dyn);
17451
17452 switch (dyn.d_tag)
17453 {
229fcec5
MM		 17454 unsigned int type;
17455
252b5132 17456 default:
7a2b07ff
NS		 17457 if (htab->vxworks_p
17458 && elf_vxworks_finish_dynamic_entry (output_bfd, &dyn))
17459 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
252b5132
RH		 17460 break;
17461
229fcec5
MM		 17462 case DT_HASH:
17463 name = ".hash";
17464 goto get_vma_if_bpabi;
17465 case DT_STRTAB:
17466 name = ".dynstr";
17467 goto get_vma_if_bpabi;
17468 case DT_SYMTAB:
17469 name = ".dynsym";
17470 goto get_vma_if_bpabi;
c0042f5d
MM		 17471 case DT_VERSYM:
17472 name = ".gnu.version";
17473 goto get_vma_if_bpabi;
17474 case DT_VERDEF:
17475 name = ".gnu.version_d";
17476 goto get_vma_if_bpabi;
17477 case DT_VERNEED:
17478 name = ".gnu.version_r";
17479 goto get_vma_if_bpabi;
17480
252b5132 17481 case DT_PLTGOT:
4ade44b7 17482 name = htab->symbian_p ? ".got" : ".got.plt";
252b5132
RH		 17483 goto get_vma;
17484 case DT_JMPREL:
00a97672 17485 name = RELOC_SECTION (htab, ".plt");
252b5132 17486 get_vma:
4ade44b7 17487 s = bfd_get_linker_section (dynobj, name);
05456594
NC		 17488 if (s == NULL)
17489 {
4eca0228 17490 _bfd_error_handler
4ade44b7 17491 (_("could not find section %s"), name);
05456594
NC		 17492 bfd_set_error (bfd_error_invalid_operation);
17493 return FALSE;
17494 }
229fcec5 17495 if (!htab->symbian_p)
4ade44b7 17496 dyn.d_un.d_ptr = s->output_section->vma + s->output_offset;
229fcec5
MM		 17497 else
17498 /* In the BPABI, tags in the PT_DYNAMIC section point
17499 at the file offset, not the memory address, for the
17500 convenience of the post linker. */
4ade44b7 17501 dyn.d_un.d_ptr = s->output_section->filepos + s->output_offset;
252b5132
RH		 17502 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17503 break;
17504
229fcec5
MM		 17505 get_vma_if_bpabi:
17506 if (htab->symbian_p)
17507 goto get_vma;
17508 break;
17509
252b5132 17510 case DT_PLTRELSZ:
362d30a1 17511 s = htab->root.srelplt;
252b5132 17512 BFD_ASSERT (s != NULL);
eea6121a 17513 dyn.d_un.d_val = s->size;
252b5132
RH		 17514 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17515 break;
906e58ca 17516
252b5132 17517 case DT_RELSZ:
00a97672 17518 case DT_RELASZ:
229fcec5
MM		 17519 case DT_REL:
17520 case DT_RELA:
229fcec5
MM		 17521 /* In the BPABI, the DT_REL tag must point at the file
17522 offset, not the VMA, of the first relocation
17523 section. So, we use code similar to that in
17524 elflink.c, but do not check for SHF_ALLOC on the
64f52338
AM		 17525 relocation section, since relocation sections are
17526 never allocated under the BPABI. PLT relocs are also
17527 included. */
229fcec5
MM		 17528 if (htab->symbian_p)
17529 {
17530 unsigned int i;
17531 type = ((dyn.d_tag == DT_REL || dyn.d_tag == DT_RELSZ)
17532 ? SHT_REL : SHT_RELA);
17533 dyn.d_un.d_val = 0;
17534 for (i = 1; i < elf_numsections (output_bfd); i++)
17535 {
906e58ca 17536 Elf_Internal_Shdr *hdr
229fcec5
MM		 17537 = elf_elfsections (output_bfd)[i];
17538 if (hdr->sh_type == type)
17539 {
906e58ca 17540 if (dyn.d_tag == DT_RELSZ
229fcec5
MM		 17541 || dyn.d_tag == DT_RELASZ)
17542 dyn.d_un.d_val += hdr->sh_size;
de52dba4
AM		 17543 else if ((ufile_ptr) hdr->sh_offset
17544 <= dyn.d_un.d_val - 1)
229fcec5
MM		 17545 dyn.d_un.d_val = hdr->sh_offset;
17546 }
17547 }
17548 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17549 }
252b5132 17550 break;
88f7bcd5 17551
0855e32b 17552 case DT_TLSDESC_PLT:
99059e56 17553 s = htab->root.splt;
0855e32b
NS		 17554 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
17555 + htab->dt_tlsdesc_plt);
17556 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17557 break;
17558
17559 case DT_TLSDESC_GOT:
99059e56 17560 s = htab->root.sgot;
0855e32b 17561 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
99059e56 17562 + htab->dt_tlsdesc_got);
0855e32b
NS		 17563 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17564 break;
17565
88f7bcd5
NC		 17566 /* Set the bottom bit of DT_INIT/FINI if the
17567 corresponding function is Thumb. */
17568 case DT_INIT:
17569 name = info->init_function;
17570 goto get_sym;
17571 case DT_FINI:
17572 name = info->fini_function;
17573 get_sym:
17574 /* If it wasn't set by elf_bfd_final_link
4cc11e76 17575 then there is nothing to adjust. */
88f7bcd5
NC		 17576 if (dyn.d_un.d_val != 0)
17577 {
17578 struct elf_link_hash_entry * eh;
17579
17580 eh = elf_link_hash_lookup (elf_hash_table (info), name,
b34976b6 17581 FALSE, FALSE, TRUE);
39d911fc
TP		 17582 if (eh != NULL
17583 && ARM_GET_SYM_BRANCH_TYPE (eh->target_internal)
17584 == ST_BRANCH_TO_THUMB)
88f7bcd5
NC		 17585 {
17586 dyn.d_un.d_val |= 1;
b34976b6 17587 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
88f7bcd5
NC		 17588 }
17589 }
17590 break;
252b5132
RH		 17591 }
17592 }
17593
24a1ba0f 17594 /* Fill in the first entry in the procedure linkage table. */
4dfe6ac6 17595 if (splt->size > 0 && htab->plt_header_size)
f7a74f8c 17596 {
00a97672
RS		 17597 const bfd_vma *plt0_entry;
17598 bfd_vma got_address, plt_address, got_displacement;
17599
17600 /* Calculate the addresses of the GOT and PLT. */
17601 got_address = sgot->output_section->vma + sgot->output_offset;
17602 plt_address = splt->output_section->vma + splt->output_offset;
17603
17604 if (htab->vxworks_p)
17605 {
17606 /* The VxWorks GOT is relocated by the dynamic linker.
17607 Therefore, we must emit relocations rather than simply
17608 computing the values now. */
17609 Elf_Internal_Rela rel;
17610
17611 plt0_entry = elf32_arm_vxworks_exec_plt0_entry;
52ab56c2
PB		 17612 put_arm_insn (htab, output_bfd, plt0_entry[0],
17613 splt->contents + 0);
17614 put_arm_insn (htab, output_bfd, plt0_entry[1],
17615 splt->contents + 4);
17616 put_arm_insn (htab, output_bfd, plt0_entry[2],
17617 splt->contents + 8);
00a97672
RS		 17618 bfd_put_32 (output_bfd, got_address, splt->contents + 12);
17619
8029a119 17620 /* Generate a relocation for _GLOBAL_OFFSET_TABLE_. */
00a97672
RS		 17621 rel.r_offset = plt_address + 12;
17622 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
17623 rel.r_addend = 0;
17624 SWAP_RELOC_OUT (htab) (output_bfd, &rel,
17625 htab->srelplt2->contents);
17626 }
b38cadfb 17627 else if (htab->nacl_p)
99059e56
RM		 17628 arm_nacl_put_plt0 (htab, output_bfd, splt,
17629 got_address + 8 - (plt_address + 16));
eed94f8f
NC		 17630 else if (using_thumb_only (htab))
17631 {
17632 got_displacement = got_address - (plt_address + 12);
17633
17634 plt0_entry = elf32_thumb2_plt0_entry;
17635 put_arm_insn (htab, output_bfd, plt0_entry[0],
17636 splt->contents + 0);
17637 put_arm_insn (htab, output_bfd, plt0_entry[1],
17638 splt->contents + 4);
17639 put_arm_insn (htab, output_bfd, plt0_entry[2],
17640 splt->contents + 8);
17641
17642 bfd_put_32 (output_bfd, got_displacement, splt->contents + 12);
17643 }
00a97672
RS		 17644 else
17645 {
17646 got_displacement = got_address - (plt_address + 16);
17647
17648 plt0_entry = elf32_arm_plt0_entry;
52ab56c2
PB		 17649 put_arm_insn (htab, output_bfd, plt0_entry[0],
17650 splt->contents + 0);
17651 put_arm_insn (htab, output_bfd, plt0_entry[1],
17652 splt->contents + 4);
17653 put_arm_insn (htab, output_bfd, plt0_entry[2],
17654 splt->contents + 8);
17655 put_arm_insn (htab, output_bfd, plt0_entry[3],
17656 splt->contents + 12);
5e681ec4 17657
5e681ec4 17658#ifdef FOUR_WORD_PLT
00a97672
RS		 17659 /* The displacement value goes in the otherwise-unused
17660 last word of the second entry. */
17661 bfd_put_32 (output_bfd, got_displacement, splt->contents + 28);
5e681ec4 17662#else
00a97672 17663 bfd_put_32 (output_bfd, got_displacement, splt->contents + 16);
5e681ec4 17664#endif
00a97672 17665 }
f7a74f8c 17666 }
252b5132
RH		 17667
17668 /* UnixWare sets the entsize of .plt to 4, although that doesn't
17669 really seem like the right value. */
74541ad4
AM		 17670 if (splt->output_section->owner == output_bfd)
17671 elf_section_data (splt->output_section)->this_hdr.sh_entsize = 4;
00a97672 17672
0855e32b
NS		 17673 if (htab->dt_tlsdesc_plt)
17674 {
17675 bfd_vma got_address
17676 = sgot->output_section->vma + sgot->output_offset;
17677 bfd_vma gotplt_address = (htab->root.sgot->output_section->vma
17678 + htab->root.sgot->output_offset);
17679 bfd_vma plt_address
17680 = splt->output_section->vma + splt->output_offset;
17681
b38cadfb 17682 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 17683 splt->contents + htab->dt_tlsdesc_plt,
17684 dl_tlsdesc_lazy_trampoline, 6);
17685
17686 bfd_put_32 (output_bfd,
17687 gotplt_address + htab->dt_tlsdesc_got
17688 - (plt_address + htab->dt_tlsdesc_plt)
17689 - dl_tlsdesc_lazy_trampoline[6],
17690 splt->contents + htab->dt_tlsdesc_plt + 24);
17691 bfd_put_32 (output_bfd,
17692 got_address - (plt_address + htab->dt_tlsdesc_plt)
17693 - dl_tlsdesc_lazy_trampoline[7],
17694 splt->contents + htab->dt_tlsdesc_plt + 24 + 4);
17695 }
17696
17697 if (htab->tls_trampoline)
17698 {
b38cadfb 17699 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 17700 splt->contents + htab->tls_trampoline,
17701 tls_trampoline, 3);
17702#ifdef FOUR_WORD_PLT
17703 bfd_put_32 (output_bfd, 0x00000000,
17704 splt->contents + htab->tls_trampoline + 12);
b38cadfb 17705#endif
0855e32b
NS		 17706 }
17707
0e1862bb
L		 17708 if (htab->vxworks_p
17709 && !bfd_link_pic (info)
17710 && htab->root.splt->size > 0)
00a97672
RS		 17711 {
17712 /* Correct the .rel(a).plt.unloaded relocations. They will have
17713 incorrect symbol indexes. */
17714 int num_plts;
eed62c48 17715 unsigned char *p;
00a97672 17716
362d30a1 17717 num_plts = ((htab->root.splt->size - htab->plt_header_size)
00a97672
RS		 17718 / htab->plt_entry_size);
17719 p = htab->srelplt2->contents + RELOC_SIZE (htab);
17720
17721 for (; num_plts; num_plts--)
17722 {
17723 Elf_Internal_Rela rel;
17724
17725 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
17726 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
17727 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
17728 p += RELOC_SIZE (htab);
17729
17730 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
17731 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
17732 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
17733 p += RELOC_SIZE (htab);
17734 }
17735 }
252b5132
RH		 17736 }
17737
99059e56
RM		 17738 if (htab->nacl_p && htab->root.iplt != NULL && htab->root.iplt->size > 0)
17739 /* NaCl uses a special first entry in .iplt too. */
17740 arm_nacl_put_plt0 (htab, output_bfd, htab->root.iplt, 0);
17741
252b5132 17742 /* Fill in the first three entries in the global offset table. */
229fcec5 17743 if (sgot)
252b5132 17744 {
229fcec5
MM		 17745 if (sgot->size > 0)
17746 {
17747 if (sdyn == NULL)
17748 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents);
17749 else
17750 bfd_put_32 (output_bfd,
17751 sdyn->output_section->vma + sdyn->output_offset,
17752 sgot->contents);
17753 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 4);
17754 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 8);
17755 }
252b5132 17756
229fcec5
MM		 17757 elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4;
17758 }
252b5132 17759
e8b09b87
CL		 17760 /* At the very end of the .rofixup section is a pointer to the GOT. */
17761 if (htab->fdpic_p && htab->srofixup != NULL)
17762 {
17763 struct elf_link_hash_entry *hgot = htab->root.hgot;
17764
17765 bfd_vma got_value = hgot->root.u.def.value
17766 + hgot->root.u.def.section->output_section->vma
17767 + hgot->root.u.def.section->output_offset;
17768
17769 arm_elf_add_rofixup(output_bfd, htab->srofixup, got_value);
17770
17771 /* Make sure we allocated and generated the same number of fixups. */
17772 BFD_ASSERT (htab->srofixup->reloc_count * 4 == htab->srofixup->size);
17773 }
17774
b34976b6 17775 return TRUE;
252b5132
RH		 17776}
17777
ed7e9d0b
AM		 17778static bfd_boolean
17779elf32_arm_init_file_header (bfd *abfd, struct bfd_link_info *link_info)
ba96a88f 17780{
9b485d32 17781 Elf_Internal_Ehdr * i_ehdrp; /* ELF file header, internal form. */
e489d0ae 17782 struct elf32_arm_link_hash_table *globals;
ac4c9b04 17783 struct elf_segment_map *m;
ba96a88f 17784
ed7e9d0b
AM		 17785 if (!_bfd_elf_init_file_header (abfd, link_info))
17786 return FALSE;
17787
ba96a88f
NC		 17788 i_ehdrp = elf_elfheader (abfd);
17789
94a3258f
PB		 17790 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_UNKNOWN)
17791 i_ehdrp->e_ident[EI_OSABI] = ELFOSABI_ARM;
ba96a88f 17792 i_ehdrp->e_ident[EI_ABIVERSION] = ARM_ELF_ABI_VERSION;
e489d0ae 17793
93204d3a
PB		 17794 if (link_info)
17795 {
17796 globals = elf32_arm_hash_table (link_info);
4dfe6ac6 17797 if (globals != NULL && globals->byteswap_code)
93204d3a 17798 i_ehdrp->e_flags |= EF_ARM_BE8;
18a20338
CL		 17799
17800 if (globals->fdpic_p)
17801 i_ehdrp->e_ident[EI_OSABI] |= ELFOSABI_ARM_FDPIC;
93204d3a 17802 }
3bfcb652
NC		 17803
17804 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_VER5
17805 && ((i_ehdrp->e_type == ET_DYN) || (i_ehdrp->e_type == ET_EXEC)))
17806 {
17807 int abi = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_ABI_VFP_args);
5c294fee 17808 if (abi == AEABI_VFP_args_vfp)
3bfcb652
NC		 17809 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_HARD;
17810 else
17811 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_SOFT;
17812 }
ac4c9b04
MG		 17813
17814 /* Scan segment to set p_flags attribute if it contains only sections with
f0728ee3 17815 SHF_ARM_PURECODE flag. */
ac4c9b04
MG		 17816 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
17817 {
17818 unsigned int j;
17819
17820 if (m->count == 0)
17821 continue;
17822 for (j = 0; j < m->count; j++)
17823 {
f0728ee3 17824 if (!(elf_section_flags (m->sections[j]) & SHF_ARM_PURECODE))
ac4c9b04
MG		 17825 break;
17826 }
17827 if (j == m->count)
17828 {
17829 m->p_flags = PF_X;
17830 m->p_flags_valid = 1;
17831 }
17832 }
ed7e9d0b 17833 return TRUE;
ba96a88f
NC		 17834}
17835
99e4ae17 17836static enum elf_reloc_type_class
7e612e98
AM		 17837elf32_arm_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UNUSED,
17838 const asection *rel_sec ATTRIBUTE_UNUSED,
17839 const Elf_Internal_Rela *rela)
99e4ae17 17840{
f51e552e 17841 switch ((int) ELF32_R_TYPE (rela->r_info))
99e4ae17
AJ		 17842 {
17843 case R_ARM_RELATIVE:
17844 return reloc_class_relative;
17845 case R_ARM_JUMP_SLOT:
17846 return reloc_class_plt;
17847 case R_ARM_COPY:
17848 return reloc_class_copy;
109575d7
JW		 17849 case R_ARM_IRELATIVE:
17850 return reloc_class_ifunc;
99e4ae17
AJ		 17851 default:
17852 return reloc_class_normal;
17853 }
17854}
17855
e489d0ae 17856static void
cc364be6 17857arm_final_write_processing (bfd *abfd)
e16bb312 17858{
5a6c6817 17859 bfd_arm_update_notes (abfd, ARM_NOTE_SECTION);
e16bb312
NC		 17860}
17861
cc364be6
AM		 17862static bfd_boolean
17863elf32_arm_final_write_processing (bfd *abfd)
06f44071 17864{
cc364be6
AM		 17865 arm_final_write_processing (abfd);
17866 return _bfd_elf_final_write_processing (abfd);
06f44071
AM		 17867}
17868
40a18ebd
NC		 17869/* Return TRUE if this is an unwinding table entry. */
17870
17871static bfd_boolean
17872is_arm_elf_unwind_section_name (bfd * abfd ATTRIBUTE_UNUSED, const char * name)
17873{
0112cd26
NC		 17874 return (CONST_STRNEQ (name, ELF_STRING_ARM_unwind)
17875 || CONST_STRNEQ (name, ELF_STRING_ARM_unwind_once));
40a18ebd
NC		 17876}
17877
17878
17879/* Set the type and flags for an ARM section. We do this by
17880 the section name, which is a hack, but ought to work. */
17881
17882static bfd_boolean
17883elf32_arm_fake_sections (bfd * abfd, Elf_Internal_Shdr * hdr, asection * sec)
17884{
17885 const char * name;
17886
fd361982 17887 name = bfd_section_name (sec);
40a18ebd
NC		 17888
17889 if (is_arm_elf_unwind_section_name (abfd, name))
17890 {
17891 hdr->sh_type = SHT_ARM_EXIDX;
17892 hdr->sh_flags |= SHF_LINK_ORDER;
17893 }
ac4c9b04 17894
f0728ee3
AV		 17895 if (sec->flags & SEC_ELF_PURECODE)
17896 hdr->sh_flags |= SHF_ARM_PURECODE;
ac4c9b04 17897
40a18ebd
NC		 17898 return TRUE;
17899}
17900
6dc132d9
L		 17901/* Handle an ARM specific section when reading an object file. This is
17902 called when bfd_section_from_shdr finds a section with an unknown
17903 type. */
40a18ebd
NC		 17904
17905static bfd_boolean
17906elf32_arm_section_from_shdr (bfd *abfd,
17907 Elf_Internal_Shdr * hdr,
6dc132d9
L		 17908 const char *name,
17909 int shindex)
40a18ebd
NC		 17910{
17911 /* There ought to be a place to keep ELF backend specific flags, but
17912 at the moment there isn't one. We just keep track of the
17913 sections by their name, instead. Fortunately, the ABI gives
17914 names for all the ARM specific sections, so we will probably get
17915 away with this. */
17916 switch (hdr->sh_type)
17917 {
17918 case SHT_ARM_EXIDX:
0951f019
RE		 17919 case SHT_ARM_PREEMPTMAP:
17920 case SHT_ARM_ATTRIBUTES:
40a18ebd
NC		 17921 break;
17922
17923 default:
17924 return FALSE;
17925 }
17926
6dc132d9 17927 if (! _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex))
40a18ebd
NC		 17928 return FALSE;
17929
17930 return TRUE;
17931}
e489d0ae 17932
44444f50
NC		 17933static _arm_elf_section_data *
17934get_arm_elf_section_data (asection * sec)
17935{
47b2e99c
JZ		 17936 if (sec && sec->owner && is_arm_elf (sec->owner))
17937 return elf32_arm_section_data (sec);
44444f50
NC		 17938 else
17939 return NULL;
8e3de13a
NC		 17940}
17941
4e617b1e
PB		 17942typedef struct
17943{
57402f1e 17944 void *flaginfo;
4e617b1e 17945 struct bfd_link_info *info;
91a5743d
PB		 17946 asection *sec;
17947 int sec_shndx;
6e0b88f1
AM		 17948 int (*func) (void *, const char *, Elf_Internal_Sym *,
17949 asection *, struct elf_link_hash_entry *);
4e617b1e
PB		 17950} output_arch_syminfo;
17951
17952enum map_symbol_type
17953{
17954 ARM_MAP_ARM,
17955 ARM_MAP_THUMB,
17956 ARM_MAP_DATA
17957};
17958
17959
7413f23f 17960/* Output a single mapping symbol. */
4e617b1e
PB		 17961
17962static bfd_boolean
7413f23f
DJ		 17963elf32_arm_output_map_sym (output_arch_syminfo *osi,
17964 enum map_symbol_type type,
17965 bfd_vma offset)
4e617b1e
PB		 17966{
17967 static const char *names[3] = {"$a", "$t", "$d"};
4e617b1e
PB		 17968 Elf_Internal_Sym sym;
17969
91a5743d
PB		 17970 sym.st_value = osi->sec->output_section->vma
17971 + osi->sec->output_offset
17972 + offset;
4e617b1e
PB		 17973 sym.st_size = 0;
17974 sym.st_other = 0;
17975 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
91a5743d 17976 sym.st_shndx = osi->sec_shndx;
35fc36a8 17977 sym.st_target_internal = 0;
fe33d2fa 17978 elf32_arm_section_map_add (osi->sec, names[type][1], offset);
57402f1e 17979 return osi->func (osi->flaginfo, names[type], &sym, osi->sec, NULL) == 1;
4e617b1e
PB		 17980}
17981
34e77a92
RS		 17982/* Output mapping symbols for the PLT entry described by ROOT_PLT and ARM_PLT.
17983 IS_IPLT_ENTRY_P says whether the PLT is in .iplt rather than .plt. */
4e617b1e
PB		 17984
17985static bfd_boolean
34e77a92
RS		 17986elf32_arm_output_plt_map_1 (output_arch_syminfo *osi,
17987 bfd_boolean is_iplt_entry_p,
17988 union gotplt_union *root_plt,
17989 struct arm_plt_info *arm_plt)
4e617b1e 17990{
4e617b1e 17991 struct elf32_arm_link_hash_table *htab;
34e77a92 17992 bfd_vma addr, plt_header_size;
4e617b1e 17993
34e77a92 17994 if (root_plt->offset == (bfd_vma) -1)
4e617b1e
PB		 17995 return TRUE;
17996
4dfe6ac6
NC		 17997 htab = elf32_arm_hash_table (osi->info);
17998 if (htab == NULL)
17999 return FALSE;
18000
34e77a92
RS		 18001 if (is_iplt_entry_p)
18002 {
18003 osi->sec = htab->root.iplt;
18004 plt_header_size = 0;
18005 }
18006 else
18007 {
18008 osi->sec = htab->root.splt;
18009 plt_header_size = htab->plt_header_size;
18010 }
18011 osi->sec_shndx = (_bfd_elf_section_from_bfd_section
18012 (osi->info->output_bfd, osi->sec->output_section));
18013
18014 addr = root_plt->offset & -2;
4e617b1e
PB		 18015 if (htab->symbian_p)
18016 {
7413f23f 18017 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 18018 return FALSE;
7413f23f 18019 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 4))
4e617b1e
PB		 18020 return FALSE;
18021 }
18022 else if (htab->vxworks_p)
18023 {
7413f23f 18024 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 18025 return FALSE;
7413f23f 18026 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 8))
4e617b1e 18027 return FALSE;
7413f23f 18028 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr + 12))
4e617b1e 18029 return FALSE;
7413f23f 18030 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 20))
4e617b1e
PB		 18031 return FALSE;
18032 }
b38cadfb
NC		 18033 else if (htab->nacl_p)
18034 {
18035 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
18036 return FALSE;
18037 }
7801f98f
CL		 18038 else if (htab->fdpic_p)
18039 {
59029f57
CL		 18040 enum map_symbol_type type = using_thumb_only(htab)
18041 ? ARM_MAP_THUMB
18042 : ARM_MAP_ARM;
18043
7801f98f 18044 if (elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt))
4b24dd1a
AM		 18045 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
18046 return FALSE;
59029f57 18047 if (!elf32_arm_output_map_sym (osi, type, addr))
4b24dd1a 18048 return FALSE;
7801f98f 18049 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 16))
4b24dd1a 18050 return FALSE;
7801f98f 18051 if (htab->plt_entry_size == 4 * ARRAY_SIZE(elf32_arm_fdpic_plt_entry))
4b24dd1a
AM		 18052 if (!elf32_arm_output_map_sym (osi, type, addr + 24))
18053 return FALSE;
7801f98f 18054 }
eed94f8f
NC		 18055 else if (using_thumb_only (htab))
18056 {
18057 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr))
18058 return FALSE;
6a631e86 18059 }
4e617b1e
PB		 18060 else
18061 {
34e77a92 18062 bfd_boolean thumb_stub_p;
bd97cb95 18063
34e77a92
RS		 18064 thumb_stub_p = elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt);
18065 if (thumb_stub_p)
4e617b1e 18066 {
7413f23f 18067 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
4e617b1e
PB		 18068 return FALSE;
18069 }
18070#ifdef FOUR_WORD_PLT
7413f23f 18071 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 18072 return FALSE;
7413f23f 18073 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 12))
4e617b1e
PB		 18074 return FALSE;
18075#else
906e58ca 18076 /* A three-word PLT with no Thumb thunk contains only Arm code,
4e617b1e
PB		 18077 so only need to output a mapping symbol for the first PLT entry and
18078 entries with thumb thunks. */
34e77a92 18079 if (thumb_stub_p || addr == plt_header_size)
4e617b1e 18080 {
7413f23f 18081 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e
PB		 18082 return FALSE;
18083 }
18084#endif
18085 }
18086
18087 return TRUE;
18088}
18089
34e77a92
RS		 18090/* Output mapping symbols for PLT entries associated with H. */
18091
18092static bfd_boolean
18093elf32_arm_output_plt_map (struct elf_link_hash_entry *h, void *inf)
18094{
18095 output_arch_syminfo *osi = (output_arch_syminfo *) inf;
18096 struct elf32_arm_link_hash_entry *eh;
18097
18098 if (h->root.type == bfd_link_hash_indirect)
18099 return TRUE;
18100
18101 if (h->root.type == bfd_link_hash_warning)
18102 /* When warning symbols are created, they **replace** the "real"
18103 entry in the hash table, thus we never get to see the real
18104 symbol in a hash traversal. So look at it now. */
18105 h = (struct elf_link_hash_entry *) h->root.u.i.link;
18106
18107 eh = (struct elf32_arm_link_hash_entry *) h;
18108 return elf32_arm_output_plt_map_1 (osi, SYMBOL_CALLS_LOCAL (osi->info, h),
18109 &h->plt, &eh->plt);
18110}
18111
4f4faa4d
TP		 18112/* Bind a veneered symbol to its veneer identified by its hash entry
18113 STUB_ENTRY. The veneered location thus loose its symbol. */
18114
18115static void
18116arm_stub_claim_sym (struct elf32_arm_stub_hash_entry *stub_entry)
18117{
18118 struct elf32_arm_link_hash_entry *hash = stub_entry->h;
18119
18120 BFD_ASSERT (hash);
18121 hash->root.root.u.def.section = stub_entry->stub_sec;
18122 hash->root.root.u.def.value = stub_entry->stub_offset;
18123 hash->root.size = stub_entry->stub_size;
18124}
18125
7413f23f
DJ		 18126/* Output a single local symbol for a generated stub. */
18127
18128static bfd_boolean
18129elf32_arm_output_stub_sym (output_arch_syminfo *osi, const char *name,
18130 bfd_vma offset, bfd_vma size)
18131{
7413f23f
DJ		 18132 Elf_Internal_Sym sym;
18133
7413f23f
DJ		 18134 sym.st_value = osi->sec->output_section->vma
18135 + osi->sec->output_offset
18136 + offset;
18137 sym.st_size = size;
18138 sym.st_other = 0;
18139 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
18140 sym.st_shndx = osi->sec_shndx;
35fc36a8 18141 sym.st_target_internal = 0;
57402f1e 18142 return osi->func (osi->flaginfo, name, &sym, osi->sec, NULL) == 1;
7413f23f 18143}
4e617b1e 18144
da5938a2 18145static bfd_boolean
8029a119
NC		 18146arm_map_one_stub (struct bfd_hash_entry * gen_entry,
18147 void * in_arg)
da5938a2
NC		 18148{
18149 struct elf32_arm_stub_hash_entry *stub_entry;
da5938a2
NC		 18150 asection *stub_sec;
18151 bfd_vma addr;
7413f23f 18152 char *stub_name;
9a008db3 18153 output_arch_syminfo *osi;
d3ce72d0 18154 const insn_sequence *template_sequence;
461a49ca
DJ		 18155 enum stub_insn_type prev_type;
18156 int size;
18157 int i;
18158 enum map_symbol_type sym_type;
da5938a2
NC		 18159
18160 /* Massage our args to the form they really have. */
18161 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
9a008db3 18162 osi = (output_arch_syminfo *) in_arg;
da5938a2 18163
da5938a2
NC		 18164 stub_sec = stub_entry->stub_sec;
18165
18166 /* Ensure this stub is attached to the current section being
7413f23f 18167 processed. */
da5938a2
NC		 18168 if (stub_sec != osi->sec)
18169 return TRUE;
18170
7413f23f 18171 addr = (bfd_vma) stub_entry->stub_offset;
d3ce72d0 18172 template_sequence = stub_entry->stub_template;
4f4faa4d
TP		 18173
18174 if (arm_stub_sym_claimed (stub_entry->stub_type))
18175 arm_stub_claim_sym (stub_entry);
18176 else
7413f23f 18177 {
4f4faa4d
TP		 18178 stub_name = stub_entry->output_name;
18179 switch (template_sequence[0].type)
18180 {
18181 case ARM_TYPE:
18182 if (!elf32_arm_output_stub_sym (osi, stub_name, addr,
18183 stub_entry->stub_size))
18184 return FALSE;
18185 break;
18186 case THUMB16_TYPE:
18187 case THUMB32_TYPE:
18188 if (!elf32_arm_output_stub_sym (osi, stub_name, addr | 1,
18189 stub_entry->stub_size))
18190 return FALSE;
18191 break;
18192 default:
18193 BFD_FAIL ();
18194 return 0;
18195 }
7413f23f 18196 }
da5938a2 18197
461a49ca
DJ		 18198 prev_type = DATA_TYPE;
18199 size = 0;
18200 for (i = 0; i < stub_entry->stub_template_size; i++)
18201 {
d3ce72d0 18202 switch (template_sequence[i].type)
461a49ca
DJ		 18203 {
18204 case ARM_TYPE:
18205 sym_type = ARM_MAP_ARM;
18206 break;
18207
18208 case THUMB16_TYPE:
48229727 18209 case THUMB32_TYPE:
461a49ca
DJ		 18210 sym_type = ARM_MAP_THUMB;
18211 break;
18212
18213 case DATA_TYPE:
18214 sym_type = ARM_MAP_DATA;
18215 break;
18216
18217 default:
18218 BFD_FAIL ();
4e31c731 18219 return FALSE;
461a49ca
DJ		 18220 }
18221
d3ce72d0 18222 if (template_sequence[i].type != prev_type)
461a49ca 18223 {
d3ce72d0 18224 prev_type = template_sequence[i].type;
461a49ca
DJ		 18225 if (!elf32_arm_output_map_sym (osi, sym_type, addr + size))
18226 return FALSE;
18227 }
18228
d3ce72d0 18229 switch (template_sequence[i].type)
461a49ca
DJ		 18230 {
18231 case ARM_TYPE:
48229727 18232 case THUMB32_TYPE:
461a49ca
DJ		 18233 size += 4;
18234 break;
18235
18236 case THUMB16_TYPE:
18237 size += 2;
18238 break;
18239
18240 case DATA_TYPE:
18241 size += 4;
18242 break;
18243
18244 default:
18245 BFD_FAIL ();
4e31c731 18246 return FALSE;
461a49ca
DJ		 18247 }
18248 }
18249
da5938a2
NC		 18250 return TRUE;
18251}
18252
33811162
DG		 18253/* Output mapping symbols for linker generated sections,
18254 and for those data-only sections that do not have a
18255 $d. */
4e617b1e
PB		 18256
18257static bfd_boolean
18258elf32_arm_output_arch_local_syms (bfd *output_bfd,
906e58ca 18259 struct bfd_link_info *info,
57402f1e 18260 void *flaginfo,
6e0b88f1
AM		 18261 int (*func) (void *, const char *,
18262 Elf_Internal_Sym *,
18263 asection *,
18264 struct elf_link_hash_entry *))
4e617b1e
PB		 18265{
18266 output_arch_syminfo osi;
18267 struct elf32_arm_link_hash_table *htab;
91a5743d
PB		 18268 bfd_vma offset;
18269 bfd_size_type size;
33811162 18270 bfd *input_bfd;
4e617b1e
PB		 18271
18272 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 18273 if (htab == NULL)
18274 return FALSE;
18275
906e58ca 18276 check_use_blx (htab);
91a5743d 18277
57402f1e 18278 osi.flaginfo = flaginfo;
4e617b1e
PB		 18279 osi.info = info;
18280 osi.func = func;
906e58ca 18281
33811162
DG		 18282 /* Add a $d mapping symbol to data-only sections that
18283 don't have any mapping symbol. This may result in (harmless) redundant
18284 mapping symbols. */
18285 for (input_bfd = info->input_bfds;
18286 input_bfd != NULL;
c72f2fb2 18287 input_bfd = input_bfd->link.next)
33811162
DG		 18288 {
18289 if ((input_bfd->flags & (BFD_LINKER_CREATED | HAS_SYMS)) == HAS_SYMS)
18290 for (osi.sec = input_bfd->sections;
18291 osi.sec != NULL;
18292 osi.sec = osi.sec->next)
18293 {
18294 if (osi.sec->output_section != NULL
f7dd8c79
DJ		 18295 && ((osi.sec->output_section->flags & (SEC_ALLOC | SEC_CODE))
18296 != 0)
33811162
DG		 18297 && (osi.sec->flags & (SEC_HAS_CONTENTS | SEC_LINKER_CREATED))
18298 == SEC_HAS_CONTENTS
18299 && get_arm_elf_section_data (osi.sec) != NULL
501abfe0 18300 && get_arm_elf_section_data (osi.sec)->mapcount == 0
7d500b83
CL		 18301 && osi.sec->size > 0
18302 && (osi.sec->flags & SEC_EXCLUDE) == 0)
33811162
DG		 18303 {
18304 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18305 (output_bfd, osi.sec->output_section);
18306 if (osi.sec_shndx != (int)SHN_BAD)
18307 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 0);
18308 }
18309 }
18310 }
18311
91a5743d
PB		 18312 /* ARM->Thumb glue. */
18313 if (htab->arm_glue_size > 0)
18314 {
3d4d4302
AM		 18315 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
18316 ARM2THUMB_GLUE_SECTION_NAME);
91a5743d
PB		 18317
18318 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18319 (output_bfd, osi.sec->output_section);
0e1862bb 18320 if (bfd_link_pic (info) || htab->root.is_relocatable_executable
91a5743d
PB		 18321 || htab->pic_veneer)
18322 size = ARM2THUMB_PIC_GLUE_SIZE;
18323 else if (htab->use_blx)
18324 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
18325 else
18326 size = ARM2THUMB_STATIC_GLUE_SIZE;
4e617b1e 18327
91a5743d
PB		 18328 for (offset = 0; offset < htab->arm_glue_size; offset += size)
18329 {
7413f23f
DJ		 18330 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset);
18331 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, offset + size - 4);
91a5743d
PB		 18332 }
18333 }
18334
18335 /* Thumb->ARM glue. */
18336 if (htab->thumb_glue_size > 0)
18337 {
3d4d4302
AM		 18338 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
18339 THUMB2ARM_GLUE_SECTION_NAME);
91a5743d
PB		 18340
18341 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18342 (output_bfd, osi.sec->output_section);
18343 size = THUMB2ARM_GLUE_SIZE;
18344
18345 for (offset = 0; offset < htab->thumb_glue_size; offset += size)
18346 {
7413f23f
DJ		 18347 elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, offset);
18348 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset + 4);
91a5743d
PB		 18349 }
18350 }
18351
845b51d6
PB		 18352 /* ARMv4 BX veneers. */
18353 if (htab->bx_glue_size > 0)
18354 {
3d4d4302
AM		 18355 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
18356 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 18357
18358 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18359 (output_bfd, osi.sec->output_section);
18360
7413f23f 18361 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0);
845b51d6
PB		 18362 }
18363
8029a119
NC		 18364 /* Long calls stubs. */
18365 if (htab->stub_bfd && htab->stub_bfd->sections)
18366 {
da5938a2 18367 asection* stub_sec;
8029a119 18368
da5938a2
NC		 18369 for (stub_sec = htab->stub_bfd->sections;
18370 stub_sec != NULL;
8029a119
NC		 18371 stub_sec = stub_sec->next)
18372 {
18373 /* Ignore non-stub sections. */
18374 if (!strstr (stub_sec->name, STUB_SUFFIX))
18375 continue;
da5938a2 18376
8029a119 18377 osi.sec = stub_sec;
da5938a2 18378
8029a119
NC		 18379 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18380 (output_bfd, osi.sec->output_section);
da5938a2 18381
8029a119
NC		 18382 bfd_hash_traverse (&htab->stub_hash_table, arm_map_one_stub, &osi);
18383 }
18384 }
da5938a2 18385
91a5743d 18386 /* Finally, output mapping symbols for the PLT. */
34e77a92 18387 if (htab->root.splt && htab->root.splt->size > 0)
4e617b1e 18388 {
34e77a92
RS		 18389 osi.sec = htab->root.splt;
18390 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
18391 (output_bfd, osi.sec->output_section));
18392
18393 /* Output mapping symbols for the plt header. SymbianOS does not have a
18394 plt header. */
18395 if (htab->vxworks_p)
18396 {
18397 /* VxWorks shared libraries have no PLT header. */
0e1862bb 18398 if (!bfd_link_pic (info))
34e77a92
RS		 18399 {
18400 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
18401 return FALSE;
18402 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
18403 return FALSE;
18404 }
18405 }
b38cadfb
NC		 18406 else if (htab->nacl_p)
18407 {
18408 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
18409 return FALSE;
18410 }
59029f57 18411 else if (using_thumb_only (htab) && !htab->fdpic_p)
eed94f8f
NC		 18412 {
18413 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 0))
18414 return FALSE;
18415 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
18416 return FALSE;
18417 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 16))
18418 return FALSE;
18419 }
e8b09b87 18420 else if (!htab->symbian_p && !htab->fdpic_p)
4e617b1e 18421 {
7413f23f 18422 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
4e617b1e 18423 return FALSE;
34e77a92
RS		 18424#ifndef FOUR_WORD_PLT
18425 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 16))
4e617b1e 18426 return FALSE;
34e77a92 18427#endif
4e617b1e
PB		 18428 }
18429 }
99059e56
RM		 18430 if (htab->nacl_p && htab->root.iplt && htab->root.iplt->size > 0)
18431 {
18432 /* NaCl uses a special first entry in .iplt too. */
18433 osi.sec = htab->root.iplt;
18434 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
18435 (output_bfd, osi.sec->output_section));
18436 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
18437 return FALSE;
18438 }
34e77a92
RS		 18439 if ((htab->root.splt && htab->root.splt->size > 0)
18440 || (htab->root.iplt && htab->root.iplt->size > 0))
4e617b1e 18441 {
34e77a92
RS		 18442 elf_link_hash_traverse (&htab->root, elf32_arm_output_plt_map, &osi);
18443 for (input_bfd = info->input_bfds;
18444 input_bfd != NULL;
c72f2fb2 18445 input_bfd = input_bfd->link.next)
34e77a92
RS		 18446 {
18447 struct arm_local_iplt_info **local_iplt;
18448 unsigned int i, num_syms;
4e617b1e 18449
34e77a92
RS		 18450 local_iplt = elf32_arm_local_iplt (input_bfd);
18451 if (local_iplt != NULL)
18452 {
18453 num_syms = elf_symtab_hdr (input_bfd).sh_info;
18454 for (i = 0; i < num_syms; i++)
18455 if (local_iplt[i] != NULL
18456 && !elf32_arm_output_plt_map_1 (&osi, TRUE,
18457 &local_iplt[i]->root,
18458 &local_iplt[i]->arm))
18459 return FALSE;
18460 }
18461 }
18462 }
0855e32b
NS		 18463 if (htab->dt_tlsdesc_plt != 0)
18464 {
18465 /* Mapping symbols for the lazy tls trampoline. */
18466 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->dt_tlsdesc_plt))
18467 return FALSE;
b38cadfb 18468
0855e32b
NS		 18469 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
18470 htab->dt_tlsdesc_plt + 24))
18471 return FALSE;
18472 }
18473 if (htab->tls_trampoline != 0)
18474 {
18475 /* Mapping symbols for the tls trampoline. */
18476 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->tls_trampoline))
18477 return FALSE;
18478#ifdef FOUR_WORD_PLT
18479 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
18480 htab->tls_trampoline + 12))
18481 return FALSE;
b38cadfb 18482#endif
0855e32b 18483 }
b38cadfb 18484
4e617b1e
PB		 18485 return TRUE;
18486}
18487
54ddd295
TP		 18488/* Filter normal symbols of CMSE entry functions of ABFD to include in
18489 the import library. All SYMCOUNT symbols of ABFD can be examined
18490 from their pointers in SYMS. Pointers of symbols to keep should be
18491 stored continuously at the beginning of that array.
18492
18493 Returns the number of symbols to keep. */
18494
18495static unsigned int
18496elf32_arm_filter_cmse_symbols (bfd *abfd ATTRIBUTE_UNUSED,
18497 struct bfd_link_info *info,
18498 asymbol **syms, long symcount)
18499{
18500 size_t maxnamelen;
18501 char *cmse_name;
18502 long src_count, dst_count = 0;
18503 struct elf32_arm_link_hash_table *htab;
18504
18505 htab = elf32_arm_hash_table (info);
18506 if (!htab->stub_bfd || !htab->stub_bfd->sections)
18507 symcount = 0;
18508
18509 maxnamelen = 128;
18510 cmse_name = (char *) bfd_malloc (maxnamelen);
7a0fb7be
NC		 18511 BFD_ASSERT (cmse_name);
18512
54ddd295
TP		 18513 for (src_count = 0; src_count < symcount; src_count++)
18514 {
18515 struct elf32_arm_link_hash_entry *cmse_hash;
18516 asymbol *sym;
18517 flagword flags;
18518 char *name;
18519 size_t namelen;
18520
18521 sym = syms[src_count];
18522 flags = sym->flags;
18523 name = (char *) bfd_asymbol_name (sym);
18524
18525 if ((flags & BSF_FUNCTION) != BSF_FUNCTION)
18526 continue;
18527 if (!(flags & (BSF_GLOBAL | BSF_WEAK)))
18528 continue;
18529
18530 namelen = strlen (name) + sizeof (CMSE_PREFIX) + 1;
18531 if (namelen > maxnamelen)
18532 {
18533 cmse_name = (char *)
18534 bfd_realloc (cmse_name, namelen);
18535 maxnamelen = namelen;
18536 }
18537 snprintf (cmse_name, maxnamelen, "%s%s", CMSE_PREFIX, name);
18538 cmse_hash = (struct elf32_arm_link_hash_entry *)
18539 elf_link_hash_lookup (&(htab)->root, cmse_name, FALSE, FALSE, TRUE);
18540
18541 if (!cmse_hash
18542 || (cmse_hash->root.root.type != bfd_link_hash_defined
18543 && cmse_hash->root.root.type != bfd_link_hash_defweak)
18544 || cmse_hash->root.type != STT_FUNC)
18545 continue;
18546
54ddd295
TP		 18547 syms[dst_count++] = sym;
18548 }
18549 free (cmse_name);
18550
18551 syms[dst_count] = NULL;
18552
18553 return dst_count;
18554}
18555
18556/* Filter symbols of ABFD to include in the import library. All
18557 SYMCOUNT symbols of ABFD can be examined from their pointers in
18558 SYMS. Pointers of symbols to keep should be stored continuously at
18559 the beginning of that array.
18560
18561 Returns the number of symbols to keep. */
18562
18563static unsigned int
18564elf32_arm_filter_implib_symbols (bfd *abfd ATTRIBUTE_UNUSED,
18565 struct bfd_link_info *info,
18566 asymbol **syms, long symcount)
18567{
18568 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
18569
046734ff
TP		 18570 /* Requirement 8 of "ARM v8-M Security Extensions: Requirements on
18571 Development Tools" (ARM-ECM-0359818) mandates Secure Gateway import
18572 library to be a relocatable object file. */
18573 BFD_ASSERT (!(bfd_get_file_flags (info->out_implib_bfd) & EXEC_P));
54ddd295
TP		 18574 if (globals->cmse_implib)
18575 return elf32_arm_filter_cmse_symbols (abfd, info, syms, symcount);
18576 else
18577 return _bfd_elf_filter_global_symbols (abfd, info, syms, symcount);
18578}
18579
e489d0ae
PB		 18580/* Allocate target specific section data. */
18581
18582static bfd_boolean
18583elf32_arm_new_section_hook (bfd *abfd, asection *sec)
18584{
f592407e
AM		 18585 if (!sec->used_by_bfd)
18586 {
18587 _arm_elf_section_data *sdata;
986f0783 18588 size_t amt = sizeof (*sdata);
e489d0ae 18589
21d799b5 18590 sdata = (_arm_elf_section_data *) bfd_zalloc (abfd, amt);
f592407e
AM		 18591 if (sdata == NULL)
18592 return FALSE;
18593 sec->used_by_bfd = sdata;
18594 }
e489d0ae
PB		 18595
18596 return _bfd_elf_new_section_hook (abfd, sec);
18597}
18598
18599
18600/* Used to order a list of mapping symbols by address. */
18601
18602static int
18603elf32_arm_compare_mapping (const void * a, const void * b)
18604{
7f6a71ff
JM		 18605 const elf32_arm_section_map *amap = (const elf32_arm_section_map *) a;
18606 const elf32_arm_section_map *bmap = (const elf32_arm_section_map *) b;
18607
18608 if (amap->vma > bmap->vma)
18609 return 1;
18610 else if (amap->vma < bmap->vma)
18611 return -1;
18612 else if (amap->type > bmap->type)
18613 /* Ensure results do not depend on the host qsort for objects with
18614 multiple mapping symbols at the same address by sorting on type
18615 after vma. */
18616 return 1;
18617 else if (amap->type < bmap->type)
18618 return -1;
18619 else
18620 return 0;
e489d0ae
PB		 18621}
18622
2468f9c9
PB		 18623/* Add OFFSET to lower 31 bits of ADDR, leaving other bits unmodified. */
18624
18625static unsigned long
18626offset_prel31 (unsigned long addr, bfd_vma offset)
18627{
18628 return (addr & ~0x7ffffffful) | ((addr + offset) & 0x7ffffffful);
18629}
18630
18631/* Copy an .ARM.exidx table entry, adding OFFSET to (applied) PREL31
18632 relocations. */
18633
18634static void
18635copy_exidx_entry (bfd *output_bfd, bfd_byte *to, bfd_byte *from, bfd_vma offset)
18636{
18637 unsigned long first_word = bfd_get_32 (output_bfd, from);
18638 unsigned long second_word = bfd_get_32 (output_bfd, from + 4);
b38cadfb 18639
2468f9c9
PB		 18640 /* High bit of first word is supposed to be zero. */
18641 if ((first_word & 0x80000000ul) == 0)
18642 first_word = offset_prel31 (first_word, offset);
b38cadfb 18643
2468f9c9
PB		 18644 /* If the high bit of the first word is clear, and the bit pattern is not 0x1
18645 (EXIDX_CANTUNWIND), this is an offset to an .ARM.extab entry. */
18646 if ((second_word != 0x1) && ((second_word & 0x80000000ul) == 0))
18647 second_word = offset_prel31 (second_word, offset);
b38cadfb 18648
2468f9c9
PB		 18649 bfd_put_32 (output_bfd, first_word, to);
18650 bfd_put_32 (output_bfd, second_word, to + 4);
18651}
e489d0ae 18652
48229727
JB		 18653/* Data for make_branch_to_a8_stub(). */
18654
b38cadfb
NC		 18655struct a8_branch_to_stub_data
18656{
48229727
JB		 18657 asection *writing_section;
18658 bfd_byte *contents;
18659};
18660
18661
18662/* Helper to insert branches to Cortex-A8 erratum stubs in the right
18663 places for a particular section. */
18664
18665static bfd_boolean
18666make_branch_to_a8_stub (struct bfd_hash_entry *gen_entry,
99059e56 18667 void *in_arg)
48229727
JB		 18668{
18669 struct elf32_arm_stub_hash_entry *stub_entry;
18670 struct a8_branch_to_stub_data *data;
18671 bfd_byte *contents;
18672 unsigned long branch_insn;
18673 bfd_vma veneered_insn_loc, veneer_entry_loc;
18674 bfd_signed_vma branch_offset;
18675 bfd *abfd;
8d9d9490 18676 unsigned int loc;
48229727
JB		 18677
18678 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
18679 data = (struct a8_branch_to_stub_data *) in_arg;
18680
18681 if (stub_entry->target_section != data->writing_section
4563a860 18682 || stub_entry->stub_type < arm_stub_a8_veneer_lwm)
48229727
JB		 18683 return TRUE;
18684
18685 contents = data->contents;
18686
8d9d9490
TP		 18687 /* We use target_section as Cortex-A8 erratum workaround stubs are only
18688 generated when both source and target are in the same section. */
48229727
JB		 18689 veneered_insn_loc = stub_entry->target_section->output_section->vma
18690 + stub_entry->target_section->output_offset
8d9d9490 18691 + stub_entry->source_value;
48229727
JB		 18692
18693 veneer_entry_loc = stub_entry->stub_sec->output_section->vma
18694 + stub_entry->stub_sec->output_offset
18695 + stub_entry->stub_offset;
18696
18697 if (stub_entry->stub_type == arm_stub_a8_veneer_blx)
18698 veneered_insn_loc &= ~3u;
18699
18700 branch_offset = veneer_entry_loc - veneered_insn_loc - 4;
18701
18702 abfd = stub_entry->target_section->owner;
8d9d9490 18703 loc = stub_entry->source_value;
48229727
JB		 18704
18705 /* We attempt to avoid this condition by setting stubs_always_after_branch
18706 in elf32_arm_size_stubs if we've enabled the Cortex-A8 erratum workaround.
18707 This check is just to be on the safe side... */
18708 if ((veneered_insn_loc & ~0xfff) == (veneer_entry_loc & ~0xfff))
18709 {
871b3ab2 18710 _bfd_error_handler (_("%pB: error: Cortex-A8 erratum stub is "
4eca0228 18711 "allocated in unsafe location"), abfd);
48229727
JB		 18712 return FALSE;
18713 }
18714
18715 switch (stub_entry->stub_type)
18716 {
18717 case arm_stub_a8_veneer_b:
18718 case arm_stub_a8_veneer_b_cond:
18719 branch_insn = 0xf0009000;
18720 goto jump24;
18721
18722 case arm_stub_a8_veneer_blx:
18723 branch_insn = 0xf000e800;
18724 goto jump24;
18725
18726 case arm_stub_a8_veneer_bl:
18727 {
18728 unsigned int i1, j1, i2, j2, s;
18729
18730 branch_insn = 0xf000d000;
18731
18732 jump24:
18733 if (branch_offset < -16777216 || branch_offset > 16777214)
18734 {
18735 /* There's not much we can do apart from complain if this
18736 happens. */
871b3ab2 18737 _bfd_error_handler (_("%pB: error: Cortex-A8 erratum stub out "
4eca0228 18738 "of range (input file too large)"), abfd);
48229727
JB		 18739 return FALSE;
18740 }
18741
18742 /* i1 = not(j1 eor s), so:
18743 not i1 = j1 eor s
18744 j1 = (not i1) eor s. */
18745
18746 branch_insn |= (branch_offset >> 1) & 0x7ff;
18747 branch_insn |= ((branch_offset >> 12) & 0x3ff) << 16;
18748 i2 = (branch_offset >> 22) & 1;
18749 i1 = (branch_offset >> 23) & 1;
18750 s = (branch_offset >> 24) & 1;
18751 j1 = (!i1) ^ s;
18752 j2 = (!i2) ^ s;
18753 branch_insn |= j2 << 11;
18754 branch_insn |= j1 << 13;
18755 branch_insn |= s << 26;
18756 }
18757 break;
18758
18759 default:
18760 BFD_FAIL ();
18761 return FALSE;
18762 }
18763
8d9d9490
TP		 18764 bfd_put_16 (abfd, (branch_insn >> 16) & 0xffff, &contents[loc]);
18765 bfd_put_16 (abfd, branch_insn & 0xffff, &contents[loc + 2]);
48229727
JB		 18766
18767 return TRUE;
18768}
18769
a504d23a
LA		 18770/* Beginning of stm32l4xx work-around. */
18771
18772/* Functions encoding instructions necessary for the emission of the
18773 fix-stm32l4xx-629360.
18774 Encoding is extracted from the
18775 ARM (C) Architecture Reference Manual
18776 ARMv7-A and ARMv7-R edition
18777 ARM DDI 0406C.b (ID072512). */
18778
18779static inline bfd_vma
82188b29 18780create_instruction_branch_absolute (int branch_offset)
a504d23a
LA		 18781{
18782 /* A8.8.18 B (A8-334)
18783 B target_address (Encoding T4). */
18784 /* 1111 - 0Sii - iiii - iiii - 10J1 - Jiii - iiii - iiii. */
18785 /* jump offset is: S:I1:I2:imm10:imm11:0. */
18786 /* with : I1 = NOT (J1 EOR S) I2 = NOT (J2 EOR S). */
18787
a504d23a
LA		 18788 int s = ((branch_offset & 0x1000000) >> 24);
18789 int j1 = s ^ !((branch_offset & 0x800000) >> 23);
18790 int j2 = s ^ !((branch_offset & 0x400000) >> 22);
18791
18792 if (branch_offset < -(1 << 24) || branch_offset >= (1 << 24))
18793 BFD_ASSERT (0 && "Error: branch out of range. Cannot create branch.");
18794
18795 bfd_vma patched_inst = 0xf0009000
18796 | s << 26 /* S. */
18797 | (((unsigned long) (branch_offset) >> 12) & 0x3ff) << 16 /* imm10. */
18798 | j1 << 13 /* J1. */
18799 | j2 << 11 /* J2. */
18800 | (((unsigned long) (branch_offset) >> 1) & 0x7ff); /* imm11. */
18801
18802 return patched_inst;
18803}
18804
18805static inline bfd_vma
18806create_instruction_ldmia (int base_reg, int wback, int reg_mask)
18807{
18808 /* A8.8.57 LDM/LDMIA/LDMFD (A8-396)
18809 LDMIA Rn!, {Ra, Rb, Rc, ...} (Encoding T2). */
18810 bfd_vma patched_inst = 0xe8900000
18811 | (/*W=*/wback << 21)
18812 | (base_reg << 16)
18813 | (reg_mask & 0x0000ffff);
18814
18815 return patched_inst;
18816}
18817
18818static inline bfd_vma
18819create_instruction_ldmdb (int base_reg, int wback, int reg_mask)
18820{
18821 /* A8.8.60 LDMDB/LDMEA (A8-402)
18822 LDMDB Rn!, {Ra, Rb, Rc, ...} (Encoding T1). */
18823 bfd_vma patched_inst = 0xe9100000
18824 | (/*W=*/wback << 21)
18825 | (base_reg << 16)
18826 | (reg_mask & 0x0000ffff);
18827
18828 return patched_inst;
18829}
18830
18831static inline bfd_vma
18832create_instruction_mov (int target_reg, int source_reg)
18833{
18834 /* A8.8.103 MOV (register) (A8-486)
18835 MOV Rd, Rm (Encoding T1). */
18836 bfd_vma patched_inst = 0x4600
18837 | (target_reg & 0x7)
18838 | ((target_reg & 0x8) >> 3) << 7
18839 | (source_reg << 3);
18840
18841 return patched_inst;
18842}
18843
18844static inline bfd_vma
18845create_instruction_sub (int target_reg, int source_reg, int value)
18846{
18847 /* A8.8.221 SUB (immediate) (A8-708)
18848 SUB Rd, Rn, #value (Encoding T3). */
18849 bfd_vma patched_inst = 0xf1a00000
18850 | (target_reg << 8)
18851 | (source_reg << 16)
18852 | (/*S=*/0 << 20)
18853 | ((value & 0x800) >> 11) << 26
18854 | ((value & 0x700) >> 8) << 12
18855 | (value & 0x0ff);
18856
18857 return patched_inst;
18858}
18859
18860static inline bfd_vma
9239bbd3 18861create_instruction_vldmia (int base_reg, int is_dp, int wback, int num_words,
a504d23a
LA		 18862 int first_reg)
18863{
18864 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 18865 VLMD{MODE} Rn{!}, {list} (Encoding T1 or T2). */
18866 bfd_vma patched_inst = (is_dp ? 0xec900b00 : 0xec900a00)
a504d23a
LA		 18867 | (/*W=*/wback << 21)
18868 | (base_reg << 16)
9239bbd3
CM		 18869 | (num_words & 0x000000ff)
18870 | (((unsigned)first_reg >> 1) & 0x0000000f) << 12
a504d23a
LA		 18871 | (first_reg & 0x00000001) << 22;
18872
18873 return patched_inst;
18874}
18875
18876static inline bfd_vma
9239bbd3
CM		 18877create_instruction_vldmdb (int base_reg, int is_dp, int num_words,
18878 int first_reg)
a504d23a
LA		 18879{
18880 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 18881 VLMD{MODE} Rn!, {} (Encoding T1 or T2). */
18882 bfd_vma patched_inst = (is_dp ? 0xed300b00 : 0xed300a00)
a504d23a 18883 | (base_reg << 16)
9239bbd3
CM		 18884 | (num_words & 0x000000ff)
18885 | (((unsigned)first_reg >>1 ) & 0x0000000f) << 12
a504d23a
LA		 18886 | (first_reg & 0x00000001) << 22;
18887
18888 return patched_inst;
18889}
18890
18891static inline bfd_vma
18892create_instruction_udf_w (int value)
18893{
18894 /* A8.8.247 UDF (A8-758)
18895 Undefined (Encoding T2). */
18896 bfd_vma patched_inst = 0xf7f0a000
18897 | (value & 0x00000fff)
18898 | (value & 0x000f0000) << 16;
18899
18900 return patched_inst;
18901}
18902
18903static inline bfd_vma
18904create_instruction_udf (int value)
18905{
18906 /* A8.8.247 UDF (A8-758)
18907 Undefined (Encoding T1). */
18908 bfd_vma patched_inst = 0xde00
18909 | (value & 0xff);
18910
18911 return patched_inst;
18912}
18913
18914/* Functions writing an instruction in memory, returning the next
18915 memory position to write to. */
18916
18917static inline bfd_byte *
18918push_thumb2_insn32 (struct elf32_arm_link_hash_table * htab,
18919 bfd * output_bfd, bfd_byte *pt, insn32 insn)
18920{
18921 put_thumb2_insn (htab, output_bfd, insn, pt);
18922 return pt + 4;
18923}
18924
18925static inline bfd_byte *
18926push_thumb2_insn16 (struct elf32_arm_link_hash_table * htab,
18927 bfd * output_bfd, bfd_byte *pt, insn32 insn)
18928{
18929 put_thumb_insn (htab, output_bfd, insn, pt);
18930 return pt + 2;
18931}
18932
18933/* Function filling up a region in memory with T1 and T2 UDFs taking
18934 care of alignment. */
18935
18936static bfd_byte *
18937stm32l4xx_fill_stub_udf (struct elf32_arm_link_hash_table * htab,
07d6d2b8
AM		 18938 bfd * output_bfd,
18939 const bfd_byte * const base_stub_contents,
18940 bfd_byte * const from_stub_contents,
18941 const bfd_byte * const end_stub_contents)
a504d23a
LA		 18942{
18943 bfd_byte *current_stub_contents = from_stub_contents;
18944
18945 /* Fill the remaining of the stub with deterministic contents : UDF
18946 instructions.
18947 Check if realignment is needed on modulo 4 frontier using T1, to
18948 further use T2. */
18949 if ((current_stub_contents < end_stub_contents)
18950 && !((current_stub_contents - base_stub_contents) % 2)
18951 && ((current_stub_contents - base_stub_contents) % 4))
18952 current_stub_contents =
18953 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18954 create_instruction_udf (0));
18955
18956 for (; current_stub_contents < end_stub_contents;)
18957 current_stub_contents =
18958 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18959 create_instruction_udf_w (0));
18960
18961 return current_stub_contents;
18962}
18963
18964/* Functions writing the stream of instructions equivalent to the
18965 derived sequence for ldmia, ldmdb, vldm respectively. */
18966
18967static void
18968stm32l4xx_create_replacing_stub_ldmia (struct elf32_arm_link_hash_table * htab,
18969 bfd * output_bfd,
18970 const insn32 initial_insn,
18971 const bfd_byte *const initial_insn_addr,
18972 bfd_byte *const base_stub_contents)
18973{
18974 int wback = (initial_insn & 0x00200000) >> 21;
18975 int ri, rn = (initial_insn & 0x000F0000) >> 16;
18976 int insn_all_registers = initial_insn & 0x0000ffff;
18977 int insn_low_registers, insn_high_registers;
18978 int usable_register_mask;
b25e998d 18979 int nb_registers = elf32_arm_popcount (insn_all_registers);
a504d23a
LA		 18980 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
18981 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
18982 bfd_byte *current_stub_contents = base_stub_contents;
18983
18984 BFD_ASSERT (is_thumb2_ldmia (initial_insn));
18985
18986 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
18987 smaller than 8 registers load sequences that do not cause the
18988 hardware issue. */
18989 if (nb_registers <= 8)
18990 {
18991 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
18992 current_stub_contents =
18993 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18994 initial_insn);
18995
18996 /* B initial_insn_addr+4. */
18997 if (!restore_pc)
18998 current_stub_contents =
18999 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19000 create_instruction_branch_absolute
82188b29 19001 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19002
19003 /* Fill the remaining of the stub with deterministic contents. */
19004 current_stub_contents =
19005 stm32l4xx_fill_stub_udf (htab, output_bfd,
19006 base_stub_contents, current_stub_contents,
19007 base_stub_contents +
19008 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19009
19010 return;
19011 }
19012
19013 /* - reg_list[13] == 0. */
19014 BFD_ASSERT ((insn_all_registers & (1 << 13))==0);
19015
19016 /* - reg_list[14] & reg_list[15] != 1. */
19017 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
19018
19019 /* - if (wback==1) reg_list[rn] == 0. */
19020 BFD_ASSERT (!wback || !restore_rn);
19021
19022 /* - nb_registers > 8. */
b25e998d 19023 BFD_ASSERT (elf32_arm_popcount (insn_all_registers) > 8);
a504d23a
LA		 19024
19025 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
19026
19027 /* In the following algorithm, we split this wide LDM using 2 LDM insns:
19028 - One with the 7 lowest registers (register mask 0x007F)
19029 This LDM will finally contain between 2 and 7 registers
19030 - One with the 7 highest registers (register mask 0xDF80)
19031 This ldm will finally contain between 2 and 7 registers. */
19032 insn_low_registers = insn_all_registers & 0x007F;
19033 insn_high_registers = insn_all_registers & 0xDF80;
19034
19035 /* A spare register may be needed during this veneer to temporarily
19036 handle the base register. This register will be restored with the
19037 last LDM operation.
19038 The usable register may be any general purpose register (that
19039 excludes PC, SP, LR : register mask is 0x1FFF). */
19040 usable_register_mask = 0x1FFF;
19041
19042 /* Generate the stub function. */
19043 if (wback)
19044 {
19045 /* LDMIA Rn!, {R-low-register-list} : (Encoding T2). */
19046 current_stub_contents =
19047 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19048 create_instruction_ldmia
19049 (rn, /*wback=*/1, insn_low_registers));
19050
19051 /* LDMIA Rn!, {R-high-register-list} : (Encoding T2). */
19052 current_stub_contents =
19053 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19054 create_instruction_ldmia
19055 (rn, /*wback=*/1, insn_high_registers));
19056 if (!restore_pc)
19057 {
19058 /* B initial_insn_addr+4. */
19059 current_stub_contents =
19060 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19061 create_instruction_branch_absolute
82188b29 19062 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19063 }
19064 }
19065 else /* if (!wback). */
19066 {
19067 ri = rn;
19068
19069 /* If Rn is not part of the high-register-list, move it there. */
19070 if (!(insn_high_registers & (1 << rn)))
19071 {
19072 /* Choose a Ri in the high-register-list that will be restored. */
19073 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19074
19075 /* MOV Ri, Rn. */
19076 current_stub_contents =
19077 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19078 create_instruction_mov (ri, rn));
19079 }
19080
19081 /* LDMIA Ri!, {R-low-register-list} : (Encoding T2). */
19082 current_stub_contents =
19083 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19084 create_instruction_ldmia
19085 (ri, /*wback=*/1, insn_low_registers));
19086
19087 /* LDMIA Ri, {R-high-register-list} : (Encoding T2). */
19088 current_stub_contents =
19089 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19090 create_instruction_ldmia
19091 (ri, /*wback=*/0, insn_high_registers));
19092
19093 if (!restore_pc)
19094 {
19095 /* B initial_insn_addr+4. */
19096 current_stub_contents =
19097 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19098 create_instruction_branch_absolute
82188b29 19099 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19100 }
19101 }
19102
19103 /* Fill the remaining of the stub with deterministic contents. */
19104 current_stub_contents =
19105 stm32l4xx_fill_stub_udf (htab, output_bfd,
19106 base_stub_contents, current_stub_contents,
19107 base_stub_contents +
19108 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19109}
19110
19111static void
19112stm32l4xx_create_replacing_stub_ldmdb (struct elf32_arm_link_hash_table * htab,
19113 bfd * output_bfd,
19114 const insn32 initial_insn,
19115 const bfd_byte *const initial_insn_addr,
19116 bfd_byte *const base_stub_contents)
19117{
19118 int wback = (initial_insn & 0x00200000) >> 21;
19119 int ri, rn = (initial_insn & 0x000f0000) >> 16;
19120 int insn_all_registers = initial_insn & 0x0000ffff;
19121 int insn_low_registers, insn_high_registers;
19122 int usable_register_mask;
19123 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
19124 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
b25e998d 19125 int nb_registers = elf32_arm_popcount (insn_all_registers);
a504d23a
LA		 19126 bfd_byte *current_stub_contents = base_stub_contents;
19127
19128 BFD_ASSERT (is_thumb2_ldmdb (initial_insn));
19129
19130 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
19131 smaller than 8 registers load sequences that do not cause the
19132 hardware issue. */
19133 if (nb_registers <= 8)
19134 {
19135 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
19136 current_stub_contents =
19137 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19138 initial_insn);
19139
19140 /* B initial_insn_addr+4. */
19141 current_stub_contents =
19142 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19143 create_instruction_branch_absolute
82188b29 19144 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19145
19146 /* Fill the remaining of the stub with deterministic contents. */
19147 current_stub_contents =
19148 stm32l4xx_fill_stub_udf (htab, output_bfd,
19149 base_stub_contents, current_stub_contents,
19150 base_stub_contents +
19151 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19152
19153 return;
19154 }
19155
19156 /* - reg_list[13] == 0. */
19157 BFD_ASSERT ((insn_all_registers & (1 << 13)) == 0);
19158
19159 /* - reg_list[14] & reg_list[15] != 1. */
19160 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
19161
19162 /* - if (wback==1) reg_list[rn] == 0. */
19163 BFD_ASSERT (!wback || !restore_rn);
19164
19165 /* - nb_registers > 8. */
b25e998d 19166 BFD_ASSERT (elf32_arm_popcount (insn_all_registers) > 8);
a504d23a
LA		 19167
19168 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
19169
19170 /* In the following algorithm, we split this wide LDM using 2 LDM insn:
19171 - One with the 7 lowest registers (register mask 0x007F)
19172 This LDM will finally contain between 2 and 7 registers
19173 - One with the 7 highest registers (register mask 0xDF80)
19174 This ldm will finally contain between 2 and 7 registers. */
19175 insn_low_registers = insn_all_registers & 0x007F;
19176 insn_high_registers = insn_all_registers & 0xDF80;
19177
19178 /* A spare register may be needed during this veneer to temporarily
19179 handle the base register. This register will be restored with
19180 the last LDM operation.
19181 The usable register may be any general purpose register (that excludes
19182 PC, SP, LR : register mask is 0x1FFF). */
19183 usable_register_mask = 0x1FFF;
19184
19185 /* Generate the stub function. */
19186 if (!wback && !restore_pc && !restore_rn)
19187 {
19188 /* Choose a Ri in the low-register-list that will be restored. */
19189 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
19190
19191 /* MOV Ri, Rn. */
19192 current_stub_contents =
19193 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19194 create_instruction_mov (ri, rn));
19195
19196 /* LDMDB Ri!, {R-high-register-list}. */
19197 current_stub_contents =
19198 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19199 create_instruction_ldmdb
19200 (ri, /*wback=*/1, insn_high_registers));
19201
19202 /* LDMDB Ri, {R-low-register-list}. */
19203 current_stub_contents =
19204 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19205 create_instruction_ldmdb
19206 (ri, /*wback=*/0, insn_low_registers));
19207
19208 /* B initial_insn_addr+4. */
19209 current_stub_contents =
19210 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19211 create_instruction_branch_absolute
82188b29 19212 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19213 }
19214 else if (wback && !restore_pc && !restore_rn)
19215 {
19216 /* LDMDB Rn!, {R-high-register-list}. */
19217 current_stub_contents =
19218 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19219 create_instruction_ldmdb
19220 (rn, /*wback=*/1, insn_high_registers));
19221
19222 /* LDMDB Rn!, {R-low-register-list}. */
19223 current_stub_contents =
19224 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19225 create_instruction_ldmdb
19226 (rn, /*wback=*/1, insn_low_registers));
19227
19228 /* B initial_insn_addr+4. */
19229 current_stub_contents =
19230 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19231 create_instruction_branch_absolute
82188b29 19232 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19233 }
19234 else if (!wback && restore_pc && !restore_rn)
19235 {
19236 /* Choose a Ri in the high-register-list that will be restored. */
19237 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19238
19239 /* SUB Ri, Rn, #(4*nb_registers). */
19240 current_stub_contents =
19241 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19242 create_instruction_sub (ri, rn, (4 * nb_registers)));
19243
19244 /* LDMIA Ri!, {R-low-register-list}. */
19245 current_stub_contents =
19246 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19247 create_instruction_ldmia
19248 (ri, /*wback=*/1, insn_low_registers));
19249
19250 /* LDMIA Ri, {R-high-register-list}. */
19251 current_stub_contents =
19252 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19253 create_instruction_ldmia
19254 (ri, /*wback=*/0, insn_high_registers));
19255 }
19256 else if (wback && restore_pc && !restore_rn)
19257 {
19258 /* Choose a Ri in the high-register-list that will be restored. */
19259 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19260
19261 /* SUB Rn, Rn, #(4*nb_registers) */
19262 current_stub_contents =
19263 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19264 create_instruction_sub (rn, rn, (4 * nb_registers)));
19265
19266 /* MOV Ri, Rn. */
19267 current_stub_contents =
19268 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19269 create_instruction_mov (ri, rn));
19270
19271 /* LDMIA Ri!, {R-low-register-list}. */
19272 current_stub_contents =
19273 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19274 create_instruction_ldmia
19275 (ri, /*wback=*/1, insn_low_registers));
19276
19277 /* LDMIA Ri, {R-high-register-list}. */
19278 current_stub_contents =
19279 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19280 create_instruction_ldmia
19281 (ri, /*wback=*/0, insn_high_registers));
19282 }
19283 else if (!wback && !restore_pc && restore_rn)
19284 {
19285 ri = rn;
19286 if (!(insn_low_registers & (1 << rn)))
19287 {
19288 /* Choose a Ri in the low-register-list that will be restored. */
19289 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
19290
19291 /* MOV Ri, Rn. */
19292 current_stub_contents =
19293 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19294 create_instruction_mov (ri, rn));
19295 }
19296
19297 /* LDMDB Ri!, {R-high-register-list}. */
19298 current_stub_contents =
19299 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19300 create_instruction_ldmdb
19301 (ri, /*wback=*/1, insn_high_registers));
19302
19303 /* LDMDB Ri, {R-low-register-list}. */
19304 current_stub_contents =
19305 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19306 create_instruction_ldmdb
19307 (ri, /*wback=*/0, insn_low_registers));
19308
19309 /* B initial_insn_addr+4. */
19310 current_stub_contents =
19311 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19312 create_instruction_branch_absolute
82188b29 19313 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19314 }
19315 else if (!wback && restore_pc && restore_rn)
19316 {
19317 ri = rn;
19318 if (!(insn_high_registers & (1 << rn)))
19319 {
19320 /* Choose a Ri in the high-register-list that will be restored. */
19321 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19322 }
19323
19324 /* SUB Ri, Rn, #(4*nb_registers). */
19325 current_stub_contents =
19326 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19327 create_instruction_sub (ri, rn, (4 * nb_registers)));
19328
19329 /* LDMIA Ri!, {R-low-register-list}. */
19330 current_stub_contents =
19331 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19332 create_instruction_ldmia
19333 (ri, /*wback=*/1, insn_low_registers));
19334
19335 /* LDMIA Ri, {R-high-register-list}. */
19336 current_stub_contents =
19337 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19338 create_instruction_ldmia
19339 (ri, /*wback=*/0, insn_high_registers));
19340 }
19341 else if (wback && restore_rn)
19342 {
19343 /* The assembler should not have accepted to encode this. */
19344 BFD_ASSERT (0 && "Cannot patch an instruction that has an "
19345 "undefined behavior.\n");
19346 }
19347
19348 /* Fill the remaining of the stub with deterministic contents. */
19349 current_stub_contents =
19350 stm32l4xx_fill_stub_udf (htab, output_bfd,
19351 base_stub_contents, current_stub_contents,
19352 base_stub_contents +
19353 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19354
19355}
19356
19357static void
19358stm32l4xx_create_replacing_stub_vldm (struct elf32_arm_link_hash_table * htab,
19359 bfd * output_bfd,
19360 const insn32 initial_insn,
19361 const bfd_byte *const initial_insn_addr,
19362 bfd_byte *const base_stub_contents)
19363{
13c9c485 19364 int num_words = initial_insn & 0xff;
a504d23a
LA		 19365 bfd_byte *current_stub_contents = base_stub_contents;
19366
19367 BFD_ASSERT (is_thumb2_vldm (initial_insn));
19368
19369 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
9239bbd3 19370 smaller than 8 words load sequences that do not cause the
a504d23a 19371 hardware issue. */
9239bbd3 19372 if (num_words <= 8)
a504d23a
LA		 19373 {
19374 /* Untouched instruction. */
19375 current_stub_contents =
19376 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19377 initial_insn);
19378
19379 /* B initial_insn_addr+4. */
19380 current_stub_contents =
19381 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19382 create_instruction_branch_absolute
82188b29 19383 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19384 }
19385 else
19386 {
9eaff861 19387 bfd_boolean is_dp = /* DP encoding. */
9239bbd3 19388 (initial_insn & 0xfe100f00) == 0xec100b00;
a504d23a
LA		 19389 bfd_boolean is_ia_nobang = /* (IA without !). */
19390 (((initial_insn << 7) >> 28) & 0xd) == 0x4;
19391 bfd_boolean is_ia_bang = /* (IA with !) - includes VPOP. */
19392 (((initial_insn << 7) >> 28) & 0xd) == 0x5;
19393 bfd_boolean is_db_bang = /* (DB with !). */
19394 (((initial_insn << 7) >> 28) & 0xd) == 0x9;
9239bbd3 19395 int base_reg = ((unsigned int) initial_insn << 12) >> 28;
a504d23a 19396 /* d = UInt (Vd:D);. */
9239bbd3 19397 int first_reg = ((((unsigned int) initial_insn << 16) >> 28) << 1)
a504d23a
LA		 19398 | (((unsigned int)initial_insn << 9) >> 31);
19399
9239bbd3
CM		 19400 /* Compute the number of 8-words chunks needed to split. */
19401 int chunks = (num_words % 8) ? (num_words / 8 + 1) : (num_words / 8);
a504d23a
LA		 19402 int chunk;
19403
19404 /* The test coverage has been done assuming the following
19405 hypothesis that exactly one of the previous is_ predicates is
19406 true. */
9239bbd3
CM		 19407 BFD_ASSERT ( (is_ia_nobang ^ is_ia_bang ^ is_db_bang)
19408 && !(is_ia_nobang & is_ia_bang & is_db_bang));
a504d23a 19409
9239bbd3 19410 /* We treat the cutting of the words in one pass for all
a504d23a
LA		 19411 cases, then we emit the adjustments:
19412
19413 vldm rx, {...}
19414 -> vldm rx!, {8_words_or_less} for each needed 8_word
19415 -> sub rx, rx, #size (list)
19416
19417 vldm rx!, {...}
19418 -> vldm rx!, {8_words_or_less} for each needed 8_word
19419 This also handles vpop instruction (when rx is sp)
19420
19421 vldmd rx!, {...}
19422 -> vldmb rx!, {8_words_or_less} for each needed 8_word. */
9239bbd3 19423 for (chunk = 0; chunk < chunks; ++chunk)
a504d23a 19424 {
9239bbd3
CM		 19425 bfd_vma new_insn = 0;
19426
a504d23a
LA		 19427 if (is_ia_nobang || is_ia_bang)
19428 {
9239bbd3
CM		 19429 new_insn = create_instruction_vldmia
19430 (base_reg,
19431 is_dp,
19432 /*wback= . */1,
19433 chunks - (chunk + 1) ?
19434 8 : num_words - chunk * 8,
19435 first_reg + chunk * 8);
a504d23a
LA		 19436 }
19437 else if (is_db_bang)
19438 {
9239bbd3
CM		 19439 new_insn = create_instruction_vldmdb
19440 (base_reg,
19441 is_dp,
19442 chunks - (chunk + 1) ?
19443 8 : num_words - chunk * 8,
19444 first_reg + chunk * 8);
a504d23a 19445 }
9239bbd3
CM		 19446
19447 if (new_insn)
19448 current_stub_contents =
19449 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19450 new_insn);
a504d23a
LA		 19451 }
19452
19453 /* Only this case requires the base register compensation
19454 subtract. */
19455 if (is_ia_nobang)
19456 {
19457 current_stub_contents =
19458 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19459 create_instruction_sub
9239bbd3 19460 (base_reg, base_reg, 4*num_words));
a504d23a
LA		 19461 }
19462
19463 /* B initial_insn_addr+4. */
19464 current_stub_contents =
19465 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19466 create_instruction_branch_absolute
82188b29 19467 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19468 }
19469
19470 /* Fill the remaining of the stub with deterministic contents. */
19471 current_stub_contents =
19472 stm32l4xx_fill_stub_udf (htab, output_bfd,
19473 base_stub_contents, current_stub_contents,
19474 base_stub_contents +
19475 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
19476}
19477
19478static void
19479stm32l4xx_create_replacing_stub (struct elf32_arm_link_hash_table * htab,
19480 bfd * output_bfd,
19481 const insn32 wrong_insn,
19482 const bfd_byte *const wrong_insn_addr,
19483 bfd_byte *const stub_contents)
19484{
19485 if (is_thumb2_ldmia (wrong_insn))
19486 stm32l4xx_create_replacing_stub_ldmia (htab, output_bfd,
19487 wrong_insn, wrong_insn_addr,
19488 stub_contents);
19489 else if (is_thumb2_ldmdb (wrong_insn))
19490 stm32l4xx_create_replacing_stub_ldmdb (htab, output_bfd,
19491 wrong_insn, wrong_insn_addr,
19492 stub_contents);
19493 else if (is_thumb2_vldm (wrong_insn))
19494 stm32l4xx_create_replacing_stub_vldm (htab, output_bfd,
19495 wrong_insn, wrong_insn_addr,
19496 stub_contents);
19497}
19498
19499/* End of stm32l4xx work-around. */
19500
19501
e489d0ae
PB		 19502/* Do code byteswapping. Return FALSE afterwards so that the section is
19503 written out as normal. */
19504
19505static bfd_boolean
c7b8f16e 19506elf32_arm_write_section (bfd *output_bfd,
8029a119
NC		 19507 struct bfd_link_info *link_info,
19508 asection *sec,
e489d0ae
PB		 19509 bfd_byte *contents)
19510{
48229727 19511 unsigned int mapcount, errcount;
8e3de13a 19512 _arm_elf_section_data *arm_data;
c7b8f16e 19513 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
e489d0ae 19514 elf32_arm_section_map *map;
c7b8f16e 19515 elf32_vfp11_erratum_list *errnode;
a504d23a 19516 elf32_stm32l4xx_erratum_list *stm32l4xx_errnode;
e489d0ae
PB		 19517 bfd_vma ptr;
19518 bfd_vma end;
c7b8f16e 19519 bfd_vma offset = sec->output_section->vma + sec->output_offset;
e489d0ae 19520 bfd_byte tmp;
48229727 19521 unsigned int i;
57e8b36a 19522
4dfe6ac6
NC		 19523 if (globals == NULL)
19524 return FALSE;
19525
8e3de13a
NC		 19526 /* If this section has not been allocated an _arm_elf_section_data
19527 structure then we cannot record anything. */
19528 arm_data = get_arm_elf_section_data (sec);
19529 if (arm_data == NULL)
19530 return FALSE;
19531
19532 mapcount = arm_data->mapcount;
19533 map = arm_data->map;
c7b8f16e
JB		 19534 errcount = arm_data->erratumcount;
19535
19536 if (errcount != 0)
19537 {
19538 unsigned int endianflip = bfd_big_endian (output_bfd) ? 3 : 0;
19539
19540 for (errnode = arm_data->erratumlist; errnode != 0;
99059e56
RM		 19541 errnode = errnode->next)
19542 {
19543 bfd_vma target = errnode->vma - offset;
19544
19545 switch (errnode->type)
19546 {
19547 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
19548 {
19549 bfd_vma branch_to_veneer;
19550 /* Original condition code of instruction, plus bit mask for
19551 ARM B instruction. */
19552 unsigned int insn = (errnode->u.b.vfp_insn & 0xf0000000)
19553 | 0x0a000000;
c7b8f16e
JB		 19554
19555 /* The instruction is before the label. */
91d6fa6a 19556 target -= 4;
c7b8f16e
JB		 19557
19558 /* Above offset included in -4 below. */
19559 branch_to_veneer = errnode->u.b.veneer->vma
99059e56 19560 - errnode->vma - 4;
c7b8f16e
JB		 19561
19562 if ((signed) branch_to_veneer < -(1 << 25)
19563 || (signed) branch_to_veneer >= (1 << 25))
871b3ab2 19564 _bfd_error_handler (_("%pB: error: VFP11 veneer out of "
4eca0228 19565 "range"), output_bfd);
c7b8f16e 19566
99059e56
RM		 19567 insn |= (branch_to_veneer >> 2) & 0xffffff;
19568 contents[endianflip ^ target] = insn & 0xff;
19569 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
19570 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
19571 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
19572 }
19573 break;
c7b8f16e
JB		 19574
19575 case VFP11_ERRATUM_ARM_VENEER:
99059e56
RM		 19576 {
19577 bfd_vma branch_from_veneer;
19578 unsigned int insn;
c7b8f16e 19579
99059e56
RM		 19580 /* Take size of veneer into account. */
19581 branch_from_veneer = errnode->u.v.branch->vma
19582 - errnode->vma - 12;
c7b8f16e
JB		 19583
19584 if ((signed) branch_from_veneer < -(1 << 25)
19585 || (signed) branch_from_veneer >= (1 << 25))
871b3ab2 19586 _bfd_error_handler (_("%pB: error: VFP11 veneer out of "
4eca0228 19587 "range"), output_bfd);
c7b8f16e 19588
99059e56
RM		 19589 /* Original instruction. */
19590 insn = errnode->u.v.branch->u.b.vfp_insn;
19591 contents[endianflip ^ target] = insn & 0xff;
19592 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
19593 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
19594 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
19595
19596 /* Branch back to insn after original insn. */
19597 insn = 0xea000000 | ((branch_from_veneer >> 2) & 0xffffff);
19598 contents[endianflip ^ (target + 4)] = insn & 0xff;
19599 contents[endianflip ^ (target + 5)] = (insn >> 8) & 0xff;
19600 contents[endianflip ^ (target + 6)] = (insn >> 16) & 0xff;
19601 contents[endianflip ^ (target + 7)] = (insn >> 24) & 0xff;
19602 }
19603 break;
c7b8f16e 19604
99059e56
RM		 19605 default:
19606 abort ();
19607 }
19608 }
c7b8f16e 19609 }
e489d0ae 19610
a504d23a
LA		 19611 if (arm_data->stm32l4xx_erratumcount != 0)
19612 {
19613 for (stm32l4xx_errnode = arm_data->stm32l4xx_erratumlist;
19614 stm32l4xx_errnode != 0;
19615 stm32l4xx_errnode = stm32l4xx_errnode->next)
19616 {
19617 bfd_vma target = stm32l4xx_errnode->vma - offset;
19618
19619 switch (stm32l4xx_errnode->type)
19620 {
19621 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
19622 {
19623 unsigned int insn;
19624 bfd_vma branch_to_veneer =
19625 stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma;
19626
19627 if ((signed) branch_to_veneer < -(1 << 24)
19628 || (signed) branch_to_veneer >= (1 << 24))
19629 {
19630 bfd_vma out_of_range =
19631 ((signed) branch_to_veneer < -(1 << 24)) ?
19632 - branch_to_veneer - (1 << 24) :
19633 ((signed) branch_to_veneer >= (1 << 24)) ?
19634 branch_to_veneer - (1 << 24) : 0;
19635
4eca0228 19636 _bfd_error_handler
2dcf00ce 19637 (_("%pB(%#" PRIx64 "): error: "
90b6238f
AM		 19638 "cannot create STM32L4XX veneer; "
19639 "jump out of range by %" PRId64 " bytes; "
19640 "cannot encode branch instruction"),
a504d23a 19641 output_bfd,
2dcf00ce
AM		 19642 (uint64_t) (stm32l4xx_errnode->vma - 4),
19643 (int64_t) out_of_range);
a504d23a
LA		 19644 continue;
19645 }
19646
19647 insn = create_instruction_branch_absolute
82188b29 19648 (stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma);
a504d23a 19649
a2699ef2
AM		 19650 /* The instruction is before the label. */
19651 target -= 4;
19652
a504d23a
LA		 19653 put_thumb2_insn (globals, output_bfd,
19654 (bfd_vma) insn, contents + target);
19655 }
19656 break;
19657
19658 case STM32L4XX_ERRATUM_VENEER:
19659 {
82188b29
NC		 19660 bfd_byte * veneer;
19661 bfd_byte * veneer_r;
a504d23a
LA		 19662 unsigned int insn;
19663
82188b29
NC		 19664 veneer = contents + target;
19665 veneer_r = veneer
19666 + stm32l4xx_errnode->u.b.veneer->vma
19667 - stm32l4xx_errnode->vma - 4;
a504d23a
LA		 19668
19669 if ((signed) (veneer_r - veneer -
19670 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE >
19671 STM32L4XX_ERRATUM_LDM_VENEER_SIZE ?
19672 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE :
19673 STM32L4XX_ERRATUM_LDM_VENEER_SIZE) < -(1 << 24)
19674 || (signed) (veneer_r - veneer) >= (1 << 24))
19675 {
90b6238f
AM		 19676 _bfd_error_handler (_("%pB: error: cannot create STM32L4XX "
19677 "veneer"), output_bfd);
a504d23a
LA		 19678 continue;
19679 }
19680
19681 /* Original instruction. */
19682 insn = stm32l4xx_errnode->u.v.branch->u.b.insn;
19683
19684 stm32l4xx_create_replacing_stub
19685 (globals, output_bfd, insn, (void*)veneer_r, (void*)veneer);
19686 }
19687 break;
19688
19689 default:
19690 abort ();
19691 }
19692 }
19693 }
19694
2468f9c9
PB		 19695 if (arm_data->elf.this_hdr.sh_type == SHT_ARM_EXIDX)
19696 {
19697 arm_unwind_table_edit *edit_node
99059e56 19698 = arm_data->u.exidx.unwind_edit_list;
2468f9c9 19699 /* Now, sec->size is the size of the section we will write. The original
99059e56 19700 size (before we merged duplicate entries and inserted EXIDX_CANTUNWIND
2468f9c9
PB		 19701 markers) was sec->rawsize. (This isn't the case if we perform no
19702 edits, then rawsize will be zero and we should use size). */
21d799b5 19703 bfd_byte *edited_contents = (bfd_byte *) bfd_malloc (sec->size);
2468f9c9
PB		 19704 unsigned int input_size = sec->rawsize ? sec->rawsize : sec->size;
19705 unsigned int in_index, out_index;
19706 bfd_vma add_to_offsets = 0;
19707
7a0fb7be
NC		 19708 if (edited_contents == NULL)
19709 return FALSE;
2468f9c9 19710 for (in_index = 0, out_index = 0; in_index * 8 < input_size || edit_node;)
99059e56 19711 {
2468f9c9
PB		 19712 if (edit_node)
19713 {
19714 unsigned int edit_index = edit_node->index;
b38cadfb 19715
2468f9c9 19716 if (in_index < edit_index && in_index * 8 < input_size)
99059e56 19717 {
2468f9c9
PB		 19718 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
19719 contents + in_index * 8, add_to_offsets);
19720 out_index++;
19721 in_index++;
19722 }
19723 else if (in_index == edit_index
19724 || (in_index * 8 >= input_size
19725 && edit_index == UINT_MAX))
99059e56 19726 {
2468f9c9
PB		 19727 switch (edit_node->type)
19728 {
19729 case DELETE_EXIDX_ENTRY:
19730 in_index++;
19731 add_to_offsets += 8;
19732 break;
b38cadfb 19733
2468f9c9
PB		 19734 case INSERT_EXIDX_CANTUNWIND_AT_END:
19735 {
99059e56 19736 asection *text_sec = edit_node->linked_section;
2468f9c9
PB		 19737 bfd_vma text_offset = text_sec->output_section->vma
19738 + text_sec->output_offset
19739 + text_sec->size;
19740 bfd_vma exidx_offset = offset + out_index * 8;
99059e56 19741 unsigned long prel31_offset;
2468f9c9
PB		 19742
19743 /* Note: this is meant to be equivalent to an
19744 R_ARM_PREL31 relocation. These synthetic
19745 EXIDX_CANTUNWIND markers are not relocated by the
19746 usual BFD method. */
19747 prel31_offset = (text_offset - exidx_offset)
19748 & 0x7ffffffful;
491d01d3
YU		 19749 if (bfd_link_relocatable (link_info))
19750 {
19751 /* Here relocation for new EXIDX_CANTUNWIND is
19752 created, so there is no need to
19753 adjust offset by hand. */
19754 prel31_offset = text_sec->output_offset
19755 + text_sec->size;
491d01d3 19756 }
2468f9c9
PB		 19757
19758 /* First address we can't unwind. */
19759 bfd_put_32 (output_bfd, prel31_offset,
19760 &edited_contents[out_index * 8]);
19761
19762 /* Code for EXIDX_CANTUNWIND. */
19763 bfd_put_32 (output_bfd, 0x1,
19764 &edited_contents[out_index * 8 + 4]);
19765
19766 out_index++;
19767 add_to_offsets -= 8;
19768 }
19769 break;
19770 }
b38cadfb 19771
2468f9c9
PB		 19772 edit_node = edit_node->next;
19773 }
19774 }
19775 else
19776 {
19777 /* No more edits, copy remaining entries verbatim. */
19778 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
19779 contents + in_index * 8, add_to_offsets);
19780 out_index++;
19781 in_index++;
19782 }
19783 }
19784
19785 if (!(sec->flags & SEC_EXCLUDE) && !(sec->flags & SEC_NEVER_LOAD))
19786 bfd_set_section_contents (output_bfd, sec->output_section,
19787 edited_contents,
19788 (file_ptr) sec->output_offset, sec->size);
19789
19790 return TRUE;
19791 }
19792
48229727
JB		 19793 /* Fix code to point to Cortex-A8 erratum stubs. */
19794 if (globals->fix_cortex_a8)
19795 {
19796 struct a8_branch_to_stub_data data;
19797
19798 data.writing_section = sec;
19799 data.contents = contents;
19800
a504d23a
LA		 19801 bfd_hash_traverse (& globals->stub_hash_table, make_branch_to_a8_stub,
19802 & data);
48229727
JB		 19803 }
19804
e489d0ae
PB		 19805 if (mapcount == 0)
19806 return FALSE;
19807
c7b8f16e 19808 if (globals->byteswap_code)
e489d0ae 19809 {
c7b8f16e 19810 qsort (map, mapcount, sizeof (* map), elf32_arm_compare_mapping);
57e8b36a 19811
c7b8f16e
JB		 19812 ptr = map[0].vma;
19813 for (i = 0; i < mapcount; i++)
99059e56
RM		 19814 {
19815 if (i == mapcount - 1)
c7b8f16e 19816 end = sec->size;
99059e56
RM		 19817 else
19818 end = map[i + 1].vma;
e489d0ae 19819
99059e56 19820 switch (map[i].type)
e489d0ae 19821 {
c7b8f16e
JB		 19822 case 'a':
19823 /* Byte swap code words. */
19824 while (ptr + 3 < end)
99059e56
RM		 19825 {
19826 tmp = contents[ptr];
19827 contents[ptr] = contents[ptr + 3];
19828 contents[ptr + 3] = tmp;
19829 tmp = contents[ptr + 1];
19830 contents[ptr + 1] = contents[ptr + 2];
19831 contents[ptr + 2] = tmp;
19832 ptr += 4;
19833 }
c7b8f16e 19834 break;
e489d0ae 19835
c7b8f16e
JB		 19836 case 't':
19837 /* Byte swap code halfwords. */
19838 while (ptr + 1 < end)
99059e56
RM		 19839 {
19840 tmp = contents[ptr];
19841 contents[ptr] = contents[ptr + 1];
19842 contents[ptr + 1] = tmp;
19843 ptr += 2;
19844 }
c7b8f16e
JB		 19845 break;
19846
19847 case 'd':
19848 /* Leave data alone. */
19849 break;
19850 }
99059e56
RM		 19851 ptr = end;
19852 }
e489d0ae 19853 }
8e3de13a 19854
93204d3a 19855 free (map);
47b2e99c 19856 arm_data->mapcount = -1;
c7b8f16e 19857 arm_data->mapsize = 0;
8e3de13a 19858 arm_data->map = NULL;
8e3de13a 19859
e489d0ae
PB		 19860 return FALSE;
19861}
19862
0beaef2b
PB		 19863/* Mangle thumb function symbols as we read them in. */
19864
8384fb8f 19865static bfd_boolean
0beaef2b
PB		 19866elf32_arm_swap_symbol_in (bfd * abfd,
19867 const void *psrc,
19868 const void *pshn,
19869 Elf_Internal_Sym *dst)
19870{
8384fb8f
AM		 19871 if (!bfd_elf32_swap_symbol_in (abfd, psrc, pshn, dst))
19872 return FALSE;
39d911fc 19873 dst->st_target_internal = 0;
0beaef2b
PB		 19874
19875 /* New EABI objects mark thumb function symbols by setting the low bit of
35fc36a8 19876 the address. */
63e1a0fc
PB		 19877 if (ELF_ST_TYPE (dst->st_info) == STT_FUNC
19878 || ELF_ST_TYPE (dst->st_info) == STT_GNU_IFUNC)
0beaef2b 19879 {
63e1a0fc
PB		 19880 if (dst->st_value & 1)
19881 {
19882 dst->st_value &= ~(bfd_vma) 1;
39d911fc
TP		 19883 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal,
19884 ST_BRANCH_TO_THUMB);
63e1a0fc
PB		 19885 }
19886 else
39d911fc 19887 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_ARM);
35fc36a8
RS		 19888 }
19889 else if (ELF_ST_TYPE (dst->st_info) == STT_ARM_TFUNC)
19890 {
19891 dst->st_info = ELF_ST_INFO (ELF_ST_BIND (dst->st_info), STT_FUNC);
39d911fc 19892 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_THUMB);
0beaef2b 19893 }
35fc36a8 19894 else if (ELF_ST_TYPE (dst->st_info) == STT_SECTION)
39d911fc 19895 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_LONG);
35fc36a8 19896 else
39d911fc 19897 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_UNKNOWN);
35fc36a8 19898
8384fb8f 19899 return TRUE;
0beaef2b
PB		 19900}
19901
19902
19903/* Mangle thumb function symbols as we write them out. */
19904
19905static void
19906elf32_arm_swap_symbol_out (bfd *abfd,
19907 const Elf_Internal_Sym *src,
19908 void *cdst,
19909 void *shndx)
19910{
19911 Elf_Internal_Sym newsym;
19912
19913 /* We convert STT_ARM_TFUNC symbols into STT_FUNC with the low bit
19914 of the address set, as per the new EABI. We do this unconditionally
19915 because objcopy does not set the elf header flags until after
19916 it writes out the symbol table. */
39d911fc 19917 if (ARM_GET_SYM_BRANCH_TYPE (src->st_target_internal) == ST_BRANCH_TO_THUMB)
0beaef2b
PB		 19918 {
19919 newsym = *src;
34e77a92
RS		 19920 if (ELF_ST_TYPE (src->st_info) != STT_GNU_IFUNC)
19921 newsym.st_info = ELF_ST_INFO (ELF_ST_BIND (src->st_info), STT_FUNC);
0fa3dcad 19922 if (newsym.st_shndx != SHN_UNDEF)
99059e56
RM		 19923 {
19924 /* Do this only for defined symbols. At link type, the static
19925 linker will simulate the work of dynamic linker of resolving
19926 symbols and will carry over the thumbness of found symbols to
19927 the output symbol table. It's not clear how it happens, but
19928 the thumbness of undefined symbols can well be different at
19929 runtime, and writing '1' for them will be confusing for users
19930 and possibly for dynamic linker itself.
19931 */
19932 newsym.st_value |= 1;
19933 }
906e58ca 19934
0beaef2b
PB		 19935 src = &newsym;
19936 }
19937 bfd_elf32_swap_symbol_out (abfd, src, cdst, shndx);
19938}
19939
b294bdf8
MM		 19940/* Add the PT_ARM_EXIDX program header. */
19941
19942static bfd_boolean
906e58ca 19943elf32_arm_modify_segment_map (bfd *abfd,
b294bdf8
MM		 19944 struct bfd_link_info *info ATTRIBUTE_UNUSED)
19945{
19946 struct elf_segment_map *m;
19947 asection *sec;
19948
19949 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
19950 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
19951 {
19952 /* If there is already a PT_ARM_EXIDX header, then we do not
19953 want to add another one. This situation arises when running
19954 "strip"; the input binary already has the header. */
12bd6957 19955 m = elf_seg_map (abfd);
b294bdf8
MM		 19956 while (m && m->p_type != PT_ARM_EXIDX)
19957 m = m->next;
19958 if (!m)
19959 {
21d799b5 19960 m = (struct elf_segment_map *)
99059e56 19961 bfd_zalloc (abfd, sizeof (struct elf_segment_map));
b294bdf8
MM		 19962 if (m == NULL)
19963 return FALSE;
19964 m->p_type = PT_ARM_EXIDX;
19965 m->count = 1;
19966 m->sections[0] = sec;
19967
12bd6957
AM		 19968 m->next = elf_seg_map (abfd);
19969 elf_seg_map (abfd) = m;
b294bdf8
MM		 19970 }
19971 }
19972
19973 return TRUE;
19974}
19975
19976/* We may add a PT_ARM_EXIDX program header. */
19977
19978static int
a6b96beb
AM		 19979elf32_arm_additional_program_headers (bfd *abfd,
19980 struct bfd_link_info *info ATTRIBUTE_UNUSED)
b294bdf8
MM		 19981{
19982 asection *sec;
19983
19984 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
19985 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
19986 return 1;
19987 else
19988 return 0;
19989}
19990
34e77a92
RS		 19991/* Hook called by the linker routine which adds symbols from an object
19992 file. */
19993
19994static bfd_boolean
19995elf32_arm_add_symbol_hook (bfd *abfd, struct bfd_link_info *info,
19996 Elf_Internal_Sym *sym, const char **namep,
19997 flagword *flagsp, asection **secp, bfd_vma *valp)
19998{
c792917c
NC		 19999 if (elf32_arm_hash_table (info) == NULL)
20000 return FALSE;
20001
34e77a92
RS		 20002 if (elf32_arm_hash_table (info)->vxworks_p
20003 && !elf_vxworks_add_symbol_hook (abfd, info, sym, namep,
20004 flagsp, secp, valp))
20005 return FALSE;
20006
20007 return TRUE;
20008}
20009
0beaef2b 20010/* We use this to override swap_symbol_in and swap_symbol_out. */
906e58ca
NC		 20011const struct elf_size_info elf32_arm_size_info =
20012{
0beaef2b
PB		 20013 sizeof (Elf32_External_Ehdr),
20014 sizeof (Elf32_External_Phdr),
20015 sizeof (Elf32_External_Shdr),
20016 sizeof (Elf32_External_Rel),
20017 sizeof (Elf32_External_Rela),
20018 sizeof (Elf32_External_Sym),
20019 sizeof (Elf32_External_Dyn),
20020 sizeof (Elf_External_Note),
20021 4,
20022 1,
20023 32, 2,
20024 ELFCLASS32, EV_CURRENT,
20025 bfd_elf32_write_out_phdrs,
20026 bfd_elf32_write_shdrs_and_ehdr,
1489a3a0 20027 bfd_elf32_checksum_contents,
0beaef2b
PB		 20028 bfd_elf32_write_relocs,
20029 elf32_arm_swap_symbol_in,
20030 elf32_arm_swap_symbol_out,
20031 bfd_elf32_slurp_reloc_table,
20032 bfd_elf32_slurp_symbol_table,
20033 bfd_elf32_swap_dyn_in,
20034 bfd_elf32_swap_dyn_out,
20035 bfd_elf32_swap_reloc_in,
20036 bfd_elf32_swap_reloc_out,
20037 bfd_elf32_swap_reloca_in,
20038 bfd_elf32_swap_reloca_out
20039};
20040
685e70ae
VK		 20041static bfd_vma
20042read_code32 (const bfd *abfd, const bfd_byte *addr)
20043{
20044 /* V7 BE8 code is always little endian. */
20045 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
20046 return bfd_getl32 (addr);
20047
20048 return bfd_get_32 (abfd, addr);
20049}
20050
20051static bfd_vma
20052read_code16 (const bfd *abfd, const bfd_byte *addr)
20053{
20054 /* V7 BE8 code is always little endian. */
20055 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
20056 return bfd_getl16 (addr);
20057
20058 return bfd_get_16 (abfd, addr);
20059}
20060
6a631e86
YG		 20061/* Return size of plt0 entry starting at ADDR
20062 or (bfd_vma) -1 if size can not be determined. */
20063
20064static bfd_vma
20065elf32_arm_plt0_size (const bfd *abfd, const bfd_byte *addr)
20066{
20067 bfd_vma first_word;
20068 bfd_vma plt0_size;
20069
685e70ae 20070 first_word = read_code32 (abfd, addr);
6a631e86
YG		 20071
20072 if (first_word == elf32_arm_plt0_entry[0])
20073 plt0_size = 4 * ARRAY_SIZE (elf32_arm_plt0_entry);
20074 else if (first_word == elf32_thumb2_plt0_entry[0])
20075 plt0_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
20076 else
20077 /* We don't yet handle this PLT format. */
20078 return (bfd_vma) -1;
20079
20080 return plt0_size;
20081}
20082
20083/* Return size of plt entry starting at offset OFFSET
20084 of plt section located at address START
20085 or (bfd_vma) -1 if size can not be determined. */
20086
20087static bfd_vma
20088elf32_arm_plt_size (const bfd *abfd, const bfd_byte *start, bfd_vma offset)
20089{
20090 bfd_vma first_insn;
20091 bfd_vma plt_size = 0;
20092 const bfd_byte *addr = start + offset;
20093
20094 /* PLT entry size if fixed on Thumb-only platforms. */
685e70ae 20095 if (read_code32 (abfd, start) == elf32_thumb2_plt0_entry[0])
6a631e86
YG		 20096 return 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
20097
20098 /* Respect Thumb stub if necessary. */
685e70ae 20099 if (read_code16 (abfd, addr) == elf32_arm_plt_thumb_stub[0])
6a631e86
YG		 20100 {
20101 plt_size += 2 * ARRAY_SIZE(elf32_arm_plt_thumb_stub);
20102 }
20103
20104 /* Strip immediate from first add. */
685e70ae 20105 first_insn = read_code32 (abfd, addr + plt_size) & 0xffffff00;
6a631e86
YG		 20106
20107#ifdef FOUR_WORD_PLT
20108 if (first_insn == elf32_arm_plt_entry[0])
20109 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry);
20110#else
20111 if (first_insn == elf32_arm_plt_entry_long[0])
20112 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_long);
20113 else if (first_insn == elf32_arm_plt_entry_short[0])
20114 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_short);
20115#endif
20116 else
20117 /* We don't yet handle this PLT format. */
20118 return (bfd_vma) -1;
20119
20120 return plt_size;
20121}
20122
20123/* Implementation is shamelessly borrowed from _bfd_elf_get_synthetic_symtab. */
20124
20125static long
20126elf32_arm_get_synthetic_symtab (bfd *abfd,
20127 long symcount ATTRIBUTE_UNUSED,
20128 asymbol **syms ATTRIBUTE_UNUSED,
20129 long dynsymcount,
20130 asymbol **dynsyms,
20131 asymbol **ret)
20132{
20133 asection *relplt;
20134 asymbol *s;
20135 arelent *p;
20136 long count, i, n;
20137 size_t size;
20138 Elf_Internal_Shdr *hdr;
20139 char *names;
20140 asection *plt;
20141 bfd_vma offset;
20142 bfd_byte *data;
20143
20144 *ret = NULL;
20145
20146 if ((abfd->flags & (DYNAMIC | EXEC_P)) == 0)
20147 return 0;
20148
20149 if (dynsymcount <= 0)
20150 return 0;
20151
20152 relplt = bfd_get_section_by_name (abfd, ".rel.plt");
20153 if (relplt == NULL)
20154 return 0;
20155
20156 hdr = &elf_section_data (relplt)->this_hdr;
20157 if (hdr->sh_link != elf_dynsymtab (abfd)
20158 || (hdr->sh_type != SHT_REL && hdr->sh_type != SHT_RELA))
20159 return 0;
20160
20161 plt = bfd_get_section_by_name (abfd, ".plt");
20162 if (plt == NULL)
20163 return 0;
20164
20165 if (!elf32_arm_size_info.slurp_reloc_table (abfd, relplt, dynsyms, TRUE))
20166 return -1;
20167
20168 data = plt->contents;
20169 if (data == NULL)
20170 {
20171 if (!bfd_get_full_section_contents(abfd, (asection *) plt, &data) || data == NULL)
20172 return -1;
20173 bfd_cache_section_contents((asection *) plt, data);
20174 }
20175
20176 count = relplt->size / hdr->sh_entsize;
20177 size = count * sizeof (asymbol);
20178 p = relplt->relocation;
20179 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
20180 {
20181 size += strlen ((*p->sym_ptr_ptr)->name) + sizeof ("@plt");
20182 if (p->addend != 0)
20183 size += sizeof ("+0x") - 1 + 8;
20184 }
20185
20186 s = *ret = (asymbol *) bfd_malloc (size);
20187 if (s == NULL)
20188 return -1;
20189
20190 offset = elf32_arm_plt0_size (abfd, data);
20191 if (offset == (bfd_vma) -1)
20192 return -1;
20193
20194 names = (char *) (s + count);
20195 p = relplt->relocation;
20196 n = 0;
20197 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
20198 {
20199 size_t len;
20200
20201 bfd_vma plt_size = elf32_arm_plt_size (abfd, data, offset);
20202 if (plt_size == (bfd_vma) -1)
20203 break;
20204
20205 *s = **p->sym_ptr_ptr;
20206 /* Undefined syms won't have BSF_LOCAL or BSF_GLOBAL set. Since
20207 we are defining a symbol, ensure one of them is set. */
20208 if ((s->flags & BSF_LOCAL) == 0)
20209 s->flags |= BSF_GLOBAL;
20210 s->flags |= BSF_SYNTHETIC;
20211 s->section = plt;
20212 s->value = offset;
20213 s->name = names;
20214 s->udata.p = NULL;
20215 len = strlen ((*p->sym_ptr_ptr)->name);
20216 memcpy (names, (*p->sym_ptr_ptr)->name, len);
20217 names += len;
20218 if (p->addend != 0)
20219 {
20220 char buf[30], *a;
20221
20222 memcpy (names, "+0x", sizeof ("+0x") - 1);
20223 names += sizeof ("+0x") - 1;
20224 bfd_sprintf_vma (abfd, buf, p->addend);
20225 for (a = buf; *a == '0'; ++a)
20226 ;
20227 len = strlen (a);
20228 memcpy (names, a, len);
20229 names += len;
20230 }
20231 memcpy (names, "@plt", sizeof ("@plt"));
20232 names += sizeof ("@plt");
20233 ++s, ++n;
20234 offset += plt_size;
20235 }
20236
20237 return n;
20238}
20239
ac4c9b04 20240static bfd_boolean
8c803a2d 20241elf32_arm_section_flags (const Elf_Internal_Shdr *hdr)
ac4c9b04 20242{
f0728ee3 20243 if (hdr->sh_flags & SHF_ARM_PURECODE)
8c803a2d 20244 hdr->bfd_section->flags |= SEC_ELF_PURECODE;
ac4c9b04
MG		 20245 return TRUE;
20246}
20247
20248static flagword
20249elf32_arm_lookup_section_flags (char *flag_name)
20250{
f0728ee3
AV		 20251 if (!strcmp (flag_name, "SHF_ARM_PURECODE"))
20252 return SHF_ARM_PURECODE;
ac4c9b04
MG		 20253
20254 return SEC_NO_FLAGS;
20255}
20256
491d01d3
YU		 20257static unsigned int
20258elf32_arm_count_additional_relocs (asection *sec)
20259{
20260 struct _arm_elf_section_data *arm_data;
20261 arm_data = get_arm_elf_section_data (sec);
5025eb7c 20262
6342be70 20263 return arm_data == NULL ? 0 : arm_data->additional_reloc_count;
491d01d3
YU		 20264}
20265
5522f910 20266/* Called to set the sh_flags, sh_link and sh_info fields of OSECTION which
9eaff861 20267 has a type >= SHT_LOOS. Returns TRUE if these fields were initialised
5522f910
NC		 20268 FALSE otherwise. ISECTION is the best guess matching section from the
20269 input bfd IBFD, but it might be NULL. */
20270
20271static bfd_boolean
20272elf32_arm_copy_special_section_fields (const bfd *ibfd ATTRIBUTE_UNUSED,
20273 bfd *obfd ATTRIBUTE_UNUSED,
20274 const Elf_Internal_Shdr *isection ATTRIBUTE_UNUSED,
20275 Elf_Internal_Shdr *osection)
20276{
20277 switch (osection->sh_type)
20278 {
20279 case SHT_ARM_EXIDX:
20280 {
20281 Elf_Internal_Shdr **oheaders = elf_elfsections (obfd);
20282 Elf_Internal_Shdr **iheaders = elf_elfsections (ibfd);
20283 unsigned i = 0;
20284
20285 osection->sh_flags = SHF_ALLOC | SHF_LINK_ORDER;
20286 osection->sh_info = 0;
20287
20288 /* The sh_link field must be set to the text section associated with
20289 this index section. Unfortunately the ARM EHABI does not specify
20290 exactly how to determine this association. Our caller does try
20291 to match up OSECTION with its corresponding input section however
20292 so that is a good first guess. */
20293 if (isection != NULL
20294 && osection->bfd_section != NULL
20295 && isection->bfd_section != NULL
20296 && isection->bfd_section->output_section != NULL
20297 && isection->bfd_section->output_section == osection->bfd_section
20298 && iheaders != NULL
20299 && isection->sh_link > 0
20300 && isection->sh_link < elf_numsections (ibfd)
20301 && iheaders[isection->sh_link]->bfd_section != NULL
20302 && iheaders[isection->sh_link]->bfd_section->output_section != NULL
20303 )
20304 {
20305 for (i = elf_numsections (obfd); i-- > 0;)
20306 if (oheaders[i]->bfd_section
20307 == iheaders[isection->sh_link]->bfd_section->output_section)
20308 break;
20309 }
9eaff861 20310
5522f910
NC		 20311 if (i == 0)
20312 {
20313 /* Failing that we have to find a matching section ourselves. If
20314 we had the output section name available we could compare that
20315 with input section names. Unfortunately we don't. So instead
20316 we use a simple heuristic and look for the nearest executable
20317 section before this one. */
20318 for (i = elf_numsections (obfd); i-- > 0;)
20319 if (oheaders[i] == osection)
20320 break;
20321 if (i == 0)
20322 break;
20323
20324 while (i-- > 0)
20325 if (oheaders[i]->sh_type == SHT_PROGBITS
20326 && (oheaders[i]->sh_flags & (SHF_ALLOC | SHF_EXECINSTR))
20327 == (SHF_ALLOC | SHF_EXECINSTR))
20328 break;
20329 }
20330
20331 if (i)
20332 {
20333 osection->sh_link = i;
20334 /* If the text section was part of a group
20335 then the index section should be too. */
20336 if (oheaders[i]->sh_flags & SHF_GROUP)
20337 osection->sh_flags |= SHF_GROUP;
20338 return TRUE;
20339 }
20340 }
20341 break;
20342
20343 case SHT_ARM_PREEMPTMAP:
20344 osection->sh_flags = SHF_ALLOC;
20345 break;
20346
20347 case SHT_ARM_ATTRIBUTES:
20348 case SHT_ARM_DEBUGOVERLAY:
20349 case SHT_ARM_OVERLAYSECTION:
20350 default:
20351 break;
20352 }
20353
20354 return FALSE;
20355}
20356
d691934d
NC		 20357/* Returns TRUE if NAME is an ARM mapping symbol.
20358 Traditionally the symbols $a, $d and $t have been used.
20359 The ARM ELF standard also defines $x (for A64 code). It also allows a
20360 period initiated suffix to be added to the symbol: "$[adtx]\.[:sym_char]+".
20361 Other tools might also produce $b (Thumb BL), $f, $p, $m and $v, but we do
20362 not support them here. $t.x indicates the start of ThumbEE instructions. */
20363
20364static bfd_boolean
20365is_arm_mapping_symbol (const char * name)
20366{
20367 return name != NULL /* Paranoia. */
20368 && name[0] == '$' /* Note: if objcopy --prefix-symbols has been used then
20369 the mapping symbols could have acquired a prefix.
20370 We do not support this here, since such symbols no
20371 longer conform to the ARM ELF ABI. */
20372 && (name[1] == 'a' || name[1] == 'd' || name[1] == 't' || name[1] == 'x')
20373 && (name[2] == 0 || name[2] == '.');
20374 /* FIXME: Strictly speaking the symbol is only a valid mapping symbol if
20375 any characters that follow the period are legal characters for the body
20376 of a symbol's name. For now we just assume that this is the case. */
20377}
20378
fca2a38f
NC		 20379/* Make sure that mapping symbols in object files are not removed via the
20380 "strip --strip-unneeded" tool. These symbols are needed in order to
20381 correctly generate interworking veneers, and for byte swapping code
20382 regions. Once an object file has been linked, it is safe to remove the
20383 symbols as they will no longer be needed. */
20384
20385static void
20386elf32_arm_backend_symbol_processing (bfd *abfd, asymbol *sym)
20387{
20388 if (((abfd->flags & (EXEC_P | DYNAMIC)) == 0)
fca2a38f 20389 && sym->section != bfd_abs_section_ptr
d691934d 20390 && is_arm_mapping_symbol (sym->name))
fca2a38f
NC		 20391 sym->flags |= BSF_KEEP;
20392}
20393
5522f910
NC		 20394#undef elf_backend_copy_special_section_fields
20395#define elf_backend_copy_special_section_fields elf32_arm_copy_special_section_fields
20396
252b5132 20397#define ELF_ARCH bfd_arch_arm
ae95ffa6 20398#define ELF_TARGET_ID ARM_ELF_DATA
252b5132 20399#define ELF_MACHINE_CODE EM_ARM
d0facd1b
NC		 20400#ifdef __QNXTARGET__
20401#define ELF_MAXPAGESIZE 0x1000
20402#else
7572ca89 20403#define ELF_MAXPAGESIZE 0x10000
d0facd1b 20404#endif
b1342370 20405#define ELF_MINPAGESIZE 0x1000
24718e3b 20406#define ELF_COMMONPAGESIZE 0x1000
252b5132 20407
07d6d2b8 20408#define bfd_elf32_mkobject elf32_arm_mkobject
ba93b8ac 20409
99e4ae17
AJ		 20410#define bfd_elf32_bfd_copy_private_bfd_data elf32_arm_copy_private_bfd_data
20411#define bfd_elf32_bfd_merge_private_bfd_data elf32_arm_merge_private_bfd_data
252b5132
RH		 20412#define bfd_elf32_bfd_set_private_flags elf32_arm_set_private_flags
20413#define bfd_elf32_bfd_print_private_bfd_data elf32_arm_print_private_bfd_data
07d6d2b8 20414#define bfd_elf32_bfd_link_hash_table_create elf32_arm_link_hash_table_create
dc810e39 20415#define bfd_elf32_bfd_reloc_type_lookup elf32_arm_reloc_type_lookup
b38cadfb 20416#define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
07d6d2b8 20417#define bfd_elf32_find_inliner_info elf32_arm_find_inliner_info
e489d0ae 20418#define bfd_elf32_new_section_hook elf32_arm_new_section_hook
3c9458e9 20419#define bfd_elf32_bfd_is_target_special_symbol elf32_arm_is_target_special_symbol
3e6b1042 20420#define bfd_elf32_bfd_final_link elf32_arm_final_link
07d6d2b8 20421#define bfd_elf32_get_synthetic_symtab elf32_arm_get_synthetic_symtab
252b5132 20422
07d6d2b8 20423#define elf_backend_get_symbol_type elf32_arm_get_symbol_type
e7679060 20424#define elf_backend_maybe_function_sym elf32_arm_maybe_function_sym
07d6d2b8 20425#define elf_backend_gc_mark_hook elf32_arm_gc_mark_hook
6a5bb875 20426#define elf_backend_gc_mark_extra_sections elf32_arm_gc_mark_extra_sections
07d6d2b8 20427#define elf_backend_check_relocs elf32_arm_check_relocs
9eaff861 20428#define elf_backend_update_relocs elf32_arm_update_relocs
dc810e39 20429#define elf_backend_relocate_section elf32_arm_relocate_section
e489d0ae 20430#define elf_backend_write_section elf32_arm_write_section
252b5132 20431#define elf_backend_adjust_dynamic_symbol elf32_arm_adjust_dynamic_symbol
07d6d2b8 20432#define elf_backend_create_dynamic_sections elf32_arm_create_dynamic_sections
252b5132
RH		 20433#define elf_backend_finish_dynamic_symbol elf32_arm_finish_dynamic_symbol
20434#define elf_backend_finish_dynamic_sections elf32_arm_finish_dynamic_sections
20435#define elf_backend_size_dynamic_sections elf32_arm_size_dynamic_sections
0855e32b 20436#define elf_backend_always_size_sections elf32_arm_always_size_sections
74541ad4 20437#define elf_backend_init_index_section _bfd_elf_init_2_index_sections
ed7e9d0b 20438#define elf_backend_init_file_header elf32_arm_init_file_header
99e4ae17 20439#define elf_backend_reloc_type_class elf32_arm_reloc_type_class
c178919b 20440#define elf_backend_object_p elf32_arm_object_p
07d6d2b8
AM		 20441#define elf_backend_fake_sections elf32_arm_fake_sections
20442#define elf_backend_section_from_shdr elf32_arm_section_from_shdr
20443#define elf_backend_final_write_processing elf32_arm_final_write_processing
20444#define elf_backend_copy_indirect_symbol elf32_arm_copy_indirect_symbol
0beaef2b 20445#define elf_backend_size_info elf32_arm_size_info
b294bdf8 20446#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
07d6d2b8
AM		 20447#define elf_backend_additional_program_headers elf32_arm_additional_program_headers
20448#define elf_backend_output_arch_local_syms elf32_arm_output_arch_local_syms
54ddd295 20449#define elf_backend_filter_implib_symbols elf32_arm_filter_implib_symbols
07d6d2b8 20450#define elf_backend_begin_write_processing elf32_arm_begin_write_processing
34e77a92 20451#define elf_backend_add_symbol_hook elf32_arm_add_symbol_hook
491d01d3 20452#define elf_backend_count_additional_relocs elf32_arm_count_additional_relocs
fca2a38f 20453#define elf_backend_symbol_processing elf32_arm_backend_symbol_processing
906e58ca
NC		 20454
20455#define elf_backend_can_refcount 1
20456#define elf_backend_can_gc_sections 1
20457#define elf_backend_plt_readonly 1
20458#define elf_backend_want_got_plt 1
20459#define elf_backend_want_plt_sym 0
5474d94f 20460#define elf_backend_want_dynrelro 1
906e58ca
NC		 20461#define elf_backend_may_use_rel_p 1
20462#define elf_backend_may_use_rela_p 0
4e7fd91e 20463#define elf_backend_default_use_rela_p 0
64f52338 20464#define elf_backend_dtrel_excludes_plt 1
252b5132 20465
04f7c78d 20466#define elf_backend_got_header_size 12
b68a20d6 20467#define elf_backend_extern_protected_data 1
04f7c78d 20468
07d6d2b8 20469#undef elf_backend_obj_attrs_vendor
906e58ca 20470#define elf_backend_obj_attrs_vendor "aeabi"
07d6d2b8 20471#undef elf_backend_obj_attrs_section
906e58ca 20472#define elf_backend_obj_attrs_section ".ARM.attributes"
07d6d2b8 20473#undef elf_backend_obj_attrs_arg_type
906e58ca 20474#define elf_backend_obj_attrs_arg_type elf32_arm_obj_attrs_arg_type
07d6d2b8 20475#undef elf_backend_obj_attrs_section_type
104d59d1 20476#define elf_backend_obj_attrs_section_type SHT_ARM_ATTRIBUTES
b38cadfb 20477#define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
07d6d2b8 20478#define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
104d59d1 20479
07d6d2b8 20480#undef elf_backend_section_flags
ac4c9b04 20481#define elf_backend_section_flags elf32_arm_section_flags
07d6d2b8
AM		 20482#undef elf_backend_lookup_section_flags_hook
20483#define elf_backend_lookup_section_flags_hook elf32_arm_lookup_section_flags
ac4c9b04 20484
a2f63b2e
MR		 20485#define elf_backend_linux_prpsinfo32_ugid16 TRUE
20486
252b5132 20487#include "elf32-target.h"
7f266840 20488
b38cadfb
NC		 20489/* Native Client targets. */
20490
20491#undef TARGET_LITTLE_SYM
6d00b590 20492#define TARGET_LITTLE_SYM arm_elf32_nacl_le_vec
b38cadfb
NC		 20493#undef TARGET_LITTLE_NAME
20494#define TARGET_LITTLE_NAME "elf32-littlearm-nacl"
20495#undef TARGET_BIG_SYM
6d00b590 20496#define TARGET_BIG_SYM arm_elf32_nacl_be_vec
b38cadfb
NC		 20497#undef TARGET_BIG_NAME
20498#define TARGET_BIG_NAME "elf32-bigarm-nacl"
20499
20500/* Like elf32_arm_link_hash_table_create -- but overrides
20501 appropriately for NaCl. */
20502
20503static struct bfd_link_hash_table *
20504elf32_arm_nacl_link_hash_table_create (bfd *abfd)
20505{
20506 struct bfd_link_hash_table *ret;
20507
20508 ret = elf32_arm_link_hash_table_create (abfd);
20509 if (ret)
20510 {
20511 struct elf32_arm_link_hash_table *htab
20512 = (struct elf32_arm_link_hash_table *) ret;
20513
20514 htab->nacl_p = 1;
20515
20516 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt0_entry);
20517 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt_entry);
20518 }
20519 return ret;
20520}
20521
20522/* Since NaCl doesn't use the ARM-specific unwind format, we don't
20523 really need to use elf32_arm_modify_segment_map. But we do it
20524 anyway just to reduce gratuitous differences with the stock ARM backend. */
20525
20526static bfd_boolean
20527elf32_arm_nacl_modify_segment_map (bfd *abfd, struct bfd_link_info *info)
20528{
20529 return (elf32_arm_modify_segment_map (abfd, info)
20530 && nacl_modify_segment_map (abfd, info));
20531}
20532
cc364be6
AM		 20533static bfd_boolean
20534elf32_arm_nacl_final_write_processing (bfd *abfd)
887badb3 20535{
cc364be6
AM		 20536 arm_final_write_processing (abfd);
20537 return nacl_final_write_processing (abfd);
887badb3
RM		 20538}
20539
6a631e86
YG		 20540static bfd_vma
20541elf32_arm_nacl_plt_sym_val (bfd_vma i, const asection *plt,
20542 const arelent *rel ATTRIBUTE_UNUSED)
20543{
20544 return plt->vma
20545 + 4 * (ARRAY_SIZE (elf32_arm_nacl_plt0_entry) +
20546 i * ARRAY_SIZE (elf32_arm_nacl_plt_entry));
20547}
887badb3 20548
b38cadfb 20549#undef elf32_bed
6a631e86 20550#define elf32_bed elf32_arm_nacl_bed
b38cadfb
NC		 20551#undef bfd_elf32_bfd_link_hash_table_create
20552#define bfd_elf32_bfd_link_hash_table_create \
20553 elf32_arm_nacl_link_hash_table_create
20554#undef elf_backend_plt_alignment
6a631e86 20555#define elf_backend_plt_alignment 4
b38cadfb
NC		 20556#undef elf_backend_modify_segment_map
20557#define elf_backend_modify_segment_map elf32_arm_nacl_modify_segment_map
6d6c25c8
AM		 20558#undef elf_backend_modify_headers
20559#define elf_backend_modify_headers nacl_modify_headers
887badb3
RM		 20560#undef elf_backend_final_write_processing
20561#define elf_backend_final_write_processing elf32_arm_nacl_final_write_processing
6a631e86
YG		 20562#undef bfd_elf32_get_synthetic_symtab
20563#undef elf_backend_plt_sym_val
20564#define elf_backend_plt_sym_val elf32_arm_nacl_plt_sym_val
5522f910 20565#undef elf_backend_copy_special_section_fields
b38cadfb 20566
887badb3
RM		 20567#undef ELF_MINPAGESIZE
20568#undef ELF_COMMONPAGESIZE
20569
b38cadfb
NC		 20570
20571#include "elf32-target.h"
20572
20573/* Reset to defaults. */
20574#undef elf_backend_plt_alignment
20575#undef elf_backend_modify_segment_map
20576#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
6d6c25c8 20577#undef elf_backend_modify_headers
887badb3
RM		 20578#undef elf_backend_final_write_processing
20579#define elf_backend_final_write_processing elf32_arm_final_write_processing
20580#undef ELF_MINPAGESIZE
20581#define ELF_MINPAGESIZE 0x1000
20582#undef ELF_COMMONPAGESIZE
20583#define ELF_COMMONPAGESIZE 0x1000
20584
b38cadfb 20585
617a5ada
CL		 20586/* FDPIC Targets. */
20587
20588#undef TARGET_LITTLE_SYM
20589#define TARGET_LITTLE_SYM arm_elf32_fdpic_le_vec
20590#undef TARGET_LITTLE_NAME
20591#define TARGET_LITTLE_NAME "elf32-littlearm-fdpic"
20592#undef TARGET_BIG_SYM
20593#define TARGET_BIG_SYM arm_elf32_fdpic_be_vec
20594#undef TARGET_BIG_NAME
20595#define TARGET_BIG_NAME "elf32-bigarm-fdpic"
20596#undef elf_match_priority
20597#define elf_match_priority 128
18a20338
CL		 20598#undef ELF_OSABI
20599#define ELF_OSABI ELFOSABI_ARM_FDPIC
617a5ada
CL		 20600
20601/* Like elf32_arm_link_hash_table_create -- but overrides
20602 appropriately for FDPIC. */
20603
20604static struct bfd_link_hash_table *
20605elf32_arm_fdpic_link_hash_table_create (bfd *abfd)
20606{
20607 struct bfd_link_hash_table *ret;
20608
20609 ret = elf32_arm_link_hash_table_create (abfd);
20610 if (ret)
20611 {
20612 struct elf32_arm_link_hash_table *htab = (struct elf32_arm_link_hash_table *) ret;
20613
20614 htab->fdpic_p = 1;
20615 }
20616 return ret;
20617}
20618
e8b09b87
CL		 20619/* We need dynamic symbols for every section, since segments can
20620 relocate independently. */
20621static bfd_boolean
20622elf32_arm_fdpic_omit_section_dynsym (bfd *output_bfd ATTRIBUTE_UNUSED,
20623 struct bfd_link_info *info
20624 ATTRIBUTE_UNUSED,
20625 asection *p ATTRIBUTE_UNUSED)
20626{
20627 switch (elf_section_data (p)->this_hdr.sh_type)
20628 {
20629 case SHT_PROGBITS:
20630 case SHT_NOBITS:
20631 /* If sh_type is yet undecided, assume it could be
20632 SHT_PROGBITS/SHT_NOBITS. */
20633 case SHT_NULL:
20634 return FALSE;
20635
20636 /* There shouldn't be section relative relocations
20637 against any other section. */
20638 default:
20639 return TRUE;
20640 }
20641}
20642
617a5ada
CL		 20643#undef elf32_bed
20644#define elf32_bed elf32_arm_fdpic_bed
20645
20646#undef bfd_elf32_bfd_link_hash_table_create
4b24dd1a 20647#define bfd_elf32_bfd_link_hash_table_create elf32_arm_fdpic_link_hash_table_create
617a5ada 20648
e8b09b87
CL		 20649#undef elf_backend_omit_section_dynsym
20650#define elf_backend_omit_section_dynsym elf32_arm_fdpic_omit_section_dynsym
20651
617a5ada 20652#include "elf32-target.h"
e8b09b87 20653
617a5ada 20654#undef elf_match_priority
18a20338 20655#undef ELF_OSABI
e8b09b87 20656#undef elf_backend_omit_section_dynsym
617a5ada 20657
906e58ca 20658/* VxWorks Targets. */
4e7fd91e 20659
07d6d2b8
AM		 20660#undef TARGET_LITTLE_SYM
20661#define TARGET_LITTLE_SYM arm_elf32_vxworks_le_vec
20662#undef TARGET_LITTLE_NAME
20663#define TARGET_LITTLE_NAME "elf32-littlearm-vxworks"
20664#undef TARGET_BIG_SYM
20665#define TARGET_BIG_SYM arm_elf32_vxworks_be_vec
20666#undef TARGET_BIG_NAME
20667#define TARGET_BIG_NAME "elf32-bigarm-vxworks"
4e7fd91e
PB		 20668
20669/* Like elf32_arm_link_hash_table_create -- but overrides
20670 appropriately for VxWorks. */
906e58ca 20671
4e7fd91e
PB		 20672static struct bfd_link_hash_table *
20673elf32_arm_vxworks_link_hash_table_create (bfd *abfd)
20674{
20675 struct bfd_link_hash_table *ret;
20676
20677 ret = elf32_arm_link_hash_table_create (abfd);
20678 if (ret)
20679 {
20680 struct elf32_arm_link_hash_table *htab
00a97672 20681 = (struct elf32_arm_link_hash_table *) ret;
4e7fd91e 20682 htab->use_rel = 0;
00a97672 20683 htab->vxworks_p = 1;
4e7fd91e
PB		 20684 }
20685 return ret;
906e58ca 20686}
4e7fd91e 20687
cc364be6
AM		 20688static bfd_boolean
20689elf32_arm_vxworks_final_write_processing (bfd *abfd)
00a97672 20690{
cc364be6
AM		 20691 arm_final_write_processing (abfd);
20692 return elf_vxworks_final_write_processing (abfd);
00a97672
RS		 20693}
20694
906e58ca 20695#undef elf32_bed
4e7fd91e
PB		 20696#define elf32_bed elf32_arm_vxworks_bed
20697
906e58ca
NC		 20698#undef bfd_elf32_bfd_link_hash_table_create
20699#define bfd_elf32_bfd_link_hash_table_create elf32_arm_vxworks_link_hash_table_create
906e58ca
NC		 20700#undef elf_backend_final_write_processing
20701#define elf_backend_final_write_processing elf32_arm_vxworks_final_write_processing
20702#undef elf_backend_emit_relocs
9eaff861 20703#define elf_backend_emit_relocs elf_vxworks_emit_relocs
4e7fd91e 20704
906e58ca 20705#undef elf_backend_may_use_rel_p
00a97672 20706#define elf_backend_may_use_rel_p 0
906e58ca 20707#undef elf_backend_may_use_rela_p
00a97672 20708#define elf_backend_may_use_rela_p 1
906e58ca 20709#undef elf_backend_default_use_rela_p
00a97672 20710#define elf_backend_default_use_rela_p 1
906e58ca 20711#undef elf_backend_want_plt_sym
00a97672 20712#define elf_backend_want_plt_sym 1
906e58ca 20713#undef ELF_MAXPAGESIZE
00a97672 20714#define ELF_MAXPAGESIZE 0x1000
4e7fd91e
PB		 20715
20716#include "elf32-target.h"
20717
20718
21d799b5
NC		 20719/* Merge backend specific data from an object file to the output
20720 object file when linking. */
20721
20722static bfd_boolean
50e03d47 20723elf32_arm_merge_private_bfd_data (bfd *ibfd, struct bfd_link_info *info)
21d799b5 20724{
50e03d47 20725 bfd *obfd = info->output_bfd;
21d799b5
NC		 20726 flagword out_flags;
20727 flagword in_flags;
20728 bfd_boolean flags_compatible = TRUE;
20729 asection *sec;
20730
cc643b88 20731 /* Check if we have the same endianness. */
50e03d47 20732 if (! _bfd_generic_verify_endian_match (ibfd, info))
21d799b5
NC		 20733 return FALSE;
20734
20735 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
20736 return TRUE;
20737
50e03d47 20738 if (!elf32_arm_merge_eabi_attributes (ibfd, info))
21d799b5
NC		 20739 return FALSE;
20740
20741 /* The input BFD must have had its flags initialised. */
20742 /* The following seems bogus to me -- The flags are initialized in
20743 the assembler but I don't think an elf_flags_init field is
20744 written into the object. */
20745 /* BFD_ASSERT (elf_flags_init (ibfd)); */
20746
20747 in_flags = elf_elfheader (ibfd)->e_flags;
20748 out_flags = elf_elfheader (obfd)->e_flags;
20749
20750 /* In theory there is no reason why we couldn't handle this. However
20751 in practice it isn't even close to working and there is no real
20752 reason to want it. */
20753 if (EF_ARM_EABI_VERSION (in_flags) >= EF_ARM_EABI_VER4
20754 && !(ibfd->flags & DYNAMIC)
20755 && (in_flags & EF_ARM_BE8))
20756 {
871b3ab2 20757 _bfd_error_handler (_("error: %pB is already in final BE8 format"),
21d799b5
NC		 20758 ibfd);
20759 return FALSE;
20760 }
20761
20762 if (!elf_flags_init (obfd))
20763 {
20764 /* If the input is the default architecture and had the default
20765 flags then do not bother setting the flags for the output
20766 architecture, instead allow future merges to do this. If no
20767 future merges ever set these flags then they will retain their
99059e56
RM		 20768 uninitialised values, which surprise surprise, correspond
20769 to the default values. */
21d799b5
NC		 20770 if (bfd_get_arch_info (ibfd)->the_default
20771 && elf_elfheader (ibfd)->e_flags == 0)
20772 return TRUE;
20773
20774 elf_flags_init (obfd) = TRUE;
20775 elf_elfheader (obfd)->e_flags = in_flags;
20776
20777 if (bfd_get_arch (obfd) == bfd_get_arch (ibfd)
20778 && bfd_get_arch_info (obfd)->the_default)
20779 return bfd_set_arch_mach (obfd, bfd_get_arch (ibfd), bfd_get_mach (ibfd));
20780
20781 return TRUE;
20782 }
20783
20784 /* Determine what should happen if the input ARM architecture
20785 does not match the output ARM architecture. */
20786 if (! bfd_arm_merge_machines (ibfd, obfd))
20787 return FALSE;
20788
20789 /* Identical flags must be compatible. */
20790 if (in_flags == out_flags)
20791 return TRUE;
20792
20793 /* Check to see if the input BFD actually contains any sections. If
20794 not, its flags may not have been initialised either, but it
20795 cannot actually cause any incompatiblity. Do not short-circuit
20796 dynamic objects; their section list may be emptied by
20797 elf_link_add_object_symbols.
20798
20799 Also check to see if there are no code sections in the input.
20800 In this case there is no need to check for code specific flags.
20801 XXX - do we need to worry about floating-point format compatability
20802 in data sections ? */
20803 if (!(ibfd->flags & DYNAMIC))
20804 {
20805 bfd_boolean null_input_bfd = TRUE;
20806 bfd_boolean only_data_sections = TRUE;
20807
20808 for (sec = ibfd->sections; sec != NULL; sec = sec->next)
20809 {
20810 /* Ignore synthetic glue sections. */
20811 if (strcmp (sec->name, ".glue_7")
20812 && strcmp (sec->name, ".glue_7t"))
20813 {
fd361982 20814 if ((bfd_section_flags (sec)
21d799b5
NC		 20815 & (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
20816 == (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
99059e56 20817 only_data_sections = FALSE;
21d799b5
NC		 20818
20819 null_input_bfd = FALSE;
20820 break;
20821 }
20822 }
20823
20824 if (null_input_bfd || only_data_sections)
20825 return TRUE;
20826 }
20827
20828 /* Complain about various flag mismatches. */
20829 if (!elf32_arm_versions_compatible (EF_ARM_EABI_VERSION (in_flags),
20830 EF_ARM_EABI_VERSION (out_flags)))
20831 {
20832 _bfd_error_handler
90b6238f 20833 (_("error: source object %pB has EABI version %d, but target %pB has EABI version %d"),
c08bb8dd
AM		 20834 ibfd, (in_flags & EF_ARM_EABIMASK) >> 24,
20835 obfd, (out_flags & EF_ARM_EABIMASK) >> 24);
21d799b5
NC		 20836 return FALSE;
20837 }
20838
20839 /* Not sure what needs to be checked for EABI versions >= 1. */
20840 /* VxWorks libraries do not use these flags. */
20841 if (get_elf_backend_data (obfd) != &elf32_arm_vxworks_bed
20842 && get_elf_backend_data (ibfd) != &elf32_arm_vxworks_bed
20843 && EF_ARM_EABI_VERSION (in_flags) == EF_ARM_EABI_UNKNOWN)
20844 {
20845 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
20846 {
20847 _bfd_error_handler
871b3ab2 20848 (_("error: %pB is compiled for APCS-%d, whereas target %pB uses APCS-%d"),
c08bb8dd
AM		 20849 ibfd, in_flags & EF_ARM_APCS_26 ? 26 : 32,
20850 obfd, out_flags & EF_ARM_APCS_26 ? 26 : 32);
21d799b5
NC		 20851 flags_compatible = FALSE;
20852 }
20853
20854 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
20855 {
20856 if (in_flags & EF_ARM_APCS_FLOAT)
20857 _bfd_error_handler
871b3ab2 20858 (_("error: %pB passes floats in float registers, whereas %pB passes them in integer registers"),
21d799b5
NC		 20859 ibfd, obfd);
20860 else
20861 _bfd_error_handler
871b3ab2 20862 (_("error: %pB passes floats in integer registers, whereas %pB passes them in float registers"),
21d799b5
NC		 20863 ibfd, obfd);
20864
20865 flags_compatible = FALSE;
20866 }
20867
20868 if ((in_flags & EF_ARM_VFP_FLOAT) != (out_flags & EF_ARM_VFP_FLOAT))
20869 {
20870 if (in_flags & EF_ARM_VFP_FLOAT)
20871 _bfd_error_handler
90b6238f
AM		 20872 (_("error: %pB uses %s instructions, whereas %pB does not"),
20873 ibfd, "VFP", obfd);
21d799b5
NC		 20874 else
20875 _bfd_error_handler
90b6238f
AM		 20876 (_("error: %pB uses %s instructions, whereas %pB does not"),
20877 ibfd, "FPA", obfd);
21d799b5
NC		 20878
20879 flags_compatible = FALSE;
20880 }
20881
20882 if ((in_flags & EF_ARM_MAVERICK_FLOAT) != (out_flags & EF_ARM_MAVERICK_FLOAT))
20883 {
20884 if (in_flags & EF_ARM_MAVERICK_FLOAT)
20885 _bfd_error_handler
90b6238f
AM		 20886 (_("error: %pB uses %s instructions, whereas %pB does not"),
20887 ibfd, "Maverick", obfd);
21d799b5
NC		 20888 else
20889 _bfd_error_handler
90b6238f
AM		 20890 (_("error: %pB does not use %s instructions, whereas %pB does"),
20891 ibfd, "Maverick", obfd);
21d799b5
NC		 20892
20893 flags_compatible = FALSE;
20894 }
20895
20896#ifdef EF_ARM_SOFT_FLOAT
20897 if ((in_flags & EF_ARM_SOFT_FLOAT) != (out_flags & EF_ARM_SOFT_FLOAT))
20898 {
20899 /* We can allow interworking between code that is VFP format
20900 layout, and uses either soft float or integer regs for
20901 passing floating point arguments and results. We already
20902 know that the APCS_FLOAT flags match; similarly for VFP
20903 flags. */
20904 if ((in_flags & EF_ARM_APCS_FLOAT) != 0
20905 || (in_flags & EF_ARM_VFP_FLOAT) == 0)
20906 {
20907 if (in_flags & EF_ARM_SOFT_FLOAT)
20908 _bfd_error_handler
871b3ab2 20909 (_("error: %pB uses software FP, whereas %pB uses hardware FP"),
21d799b5
NC		 20910 ibfd, obfd);
20911 else
20912 _bfd_error_handler
871b3ab2 20913 (_("error: %pB uses hardware FP, whereas %pB uses software FP"),
21d799b5
NC		 20914 ibfd, obfd);
20915
20916 flags_compatible = FALSE;
20917 }
20918 }
20919#endif
20920
20921 /* Interworking mismatch is only a warning. */
20922 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
20923 {
20924 if (in_flags & EF_ARM_INTERWORK)
20925 {
20926 _bfd_error_handler
90b6238f 20927 (_("warning: %pB supports interworking, whereas %pB does not"),
21d799b5
NC		 20928 ibfd, obfd);
20929 }
20930 else
20931 {
20932 _bfd_error_handler
90b6238f 20933 (_("warning: %pB does not support interworking, whereas %pB does"),
21d799b5
NC		 20934 ibfd, obfd);
20935 }
20936 }
20937 }
20938
20939 return flags_compatible;
20940}
20941
20942
906e58ca 20943/* Symbian OS Targets. */
7f266840 20944
07d6d2b8
AM		 20945#undef TARGET_LITTLE_SYM
20946#define TARGET_LITTLE_SYM arm_elf32_symbian_le_vec
20947#undef TARGET_LITTLE_NAME
20948#define TARGET_LITTLE_NAME "elf32-littlearm-symbian"
20949#undef TARGET_BIG_SYM
20950#define TARGET_BIG_SYM arm_elf32_symbian_be_vec
20951#undef TARGET_BIG_NAME
20952#define TARGET_BIG_NAME "elf32-bigarm-symbian"
7f266840
DJ		 20953
20954/* Like elf32_arm_link_hash_table_create -- but overrides
20955 appropriately for Symbian OS. */
906e58ca 20956
7f266840
DJ		 20957static struct bfd_link_hash_table *
20958elf32_arm_symbian_link_hash_table_create (bfd *abfd)
20959{
20960 struct bfd_link_hash_table *ret;
20961
20962 ret = elf32_arm_link_hash_table_create (abfd);
20963 if (ret)
20964 {
20965 struct elf32_arm_link_hash_table *htab
20966 = (struct elf32_arm_link_hash_table *)ret;
20967 /* There is no PLT header for Symbian OS. */
20968 htab->plt_header_size = 0;
95720a86
DJ		 20969 /* The PLT entries are each one instruction and one word. */
20970 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry);
7f266840 20971 htab->symbian_p = 1;
33bfe774
JB		 20972 /* Symbian uses armv5t or above, so use_blx is always true. */
20973 htab->use_blx = 1;
67687978 20974 htab->root.is_relocatable_executable = 1;
7f266840
DJ		 20975 }
20976 return ret;
906e58ca 20977}
7f266840 20978
b35d266b 20979static const struct bfd_elf_special_section
551b43fd 20980elf32_arm_symbian_special_sections[] =
7f266840 20981{
5cd3778d
MM		 20982 /* In a BPABI executable, the dynamic linking sections do not go in
20983 the loadable read-only segment. The post-linker may wish to
20984 refer to these sections, but they are not part of the final
20985 program image. */
07d6d2b8
AM		 20986 { STRING_COMMA_LEN (".dynamic"), 0, SHT_DYNAMIC, 0 },
20987 { STRING_COMMA_LEN (".dynstr"), 0, SHT_STRTAB, 0 },
20988 { STRING_COMMA_LEN (".dynsym"), 0, SHT_DYNSYM, 0 },
20989 { STRING_COMMA_LEN (".got"), 0, SHT_PROGBITS, 0 },
20990 { STRING_COMMA_LEN (".hash"), 0, SHT_HASH, 0 },
5cd3778d
MM		 20991 /* These sections do not need to be writable as the SymbianOS
20992 postlinker will arrange things so that no dynamic relocation is
20993 required. */
07d6d2b8
AM		 20994 { STRING_COMMA_LEN (".init_array"), 0, SHT_INIT_ARRAY, SHF_ALLOC },
20995 { STRING_COMMA_LEN (".fini_array"), 0, SHT_FINI_ARRAY, SHF_ALLOC },
0112cd26 20996 { STRING_COMMA_LEN (".preinit_array"), 0, SHT_PREINIT_ARRAY, SHF_ALLOC },
07d6d2b8 20997 { NULL, 0, 0, 0, 0 }
7f266840
DJ		 20998};
20999
c3c76620 21000static void
906e58ca 21001elf32_arm_symbian_begin_write_processing (bfd *abfd,
a4fd1a8e 21002 struct bfd_link_info *link_info)
c3c76620
MM		 21003{
21004 /* BPABI objects are never loaded directly by an OS kernel; they are
21005 processed by a postlinker first, into an OS-specific format. If
21006 the D_PAGED bit is set on the file, BFD will align segments on
21007 page boundaries, so that an OS can directly map the file. With
21008 BPABI objects, that just results in wasted space. In addition,
21009 because we clear the D_PAGED bit, map_sections_to_segments will
21010 recognize that the program headers should not be mapped into any
21011 loadable segment. */
21012 abfd->flags &= ~D_PAGED;
906e58ca 21013 elf32_arm_begin_write_processing (abfd, link_info);
c3c76620 21014}
7f266840
DJ		 21015
21016static bfd_boolean
906e58ca 21017elf32_arm_symbian_modify_segment_map (bfd *abfd,
b294bdf8 21018 struct bfd_link_info *info)
7f266840
DJ		 21019{
21020 struct elf_segment_map *m;
21021 asection *dynsec;
21022
7f266840
DJ		 21023 /* BPABI shared libraries and executables should have a PT_DYNAMIC
21024 segment. However, because the .dynamic section is not marked
21025 with SEC_LOAD, the generic ELF code will not create such a
21026 segment. */
21027 dynsec = bfd_get_section_by_name (abfd, ".dynamic");
21028 if (dynsec)
21029 {
12bd6957 21030 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
8ded5a0f
AM		 21031 if (m->p_type == PT_DYNAMIC)
21032 break;
21033
21034 if (m == NULL)
21035 {
21036 m = _bfd_elf_make_dynamic_segment (abfd, dynsec);
12bd6957
AM		 21037 m->next = elf_seg_map (abfd);
21038 elf_seg_map (abfd) = m;
8ded5a0f 21039 }
7f266840
DJ		 21040 }
21041
b294bdf8
MM		 21042 /* Also call the generic arm routine. */
21043 return elf32_arm_modify_segment_map (abfd, info);
7f266840
DJ		 21044}
21045
95720a86
DJ		 21046/* Return address for Ith PLT stub in section PLT, for relocation REL
21047 or (bfd_vma) -1 if it should not be included. */
21048
21049static bfd_vma
21050elf32_arm_symbian_plt_sym_val (bfd_vma i, const asection *plt,
21051 const arelent *rel ATTRIBUTE_UNUSED)
21052{
21053 return plt->vma + 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry) * i;
21054}
21055
8029a119 21056#undef elf32_bed
7f266840
DJ		 21057#define elf32_bed elf32_arm_symbian_bed
21058
21059/* The dynamic sections are not allocated on SymbianOS; the postlinker
21060 will process them and then discard them. */
906e58ca 21061#undef ELF_DYNAMIC_SEC_FLAGS
7f266840
DJ		 21062#define ELF_DYNAMIC_SEC_FLAGS \
21063 (SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED)
21064
9eaff861 21065#undef elf_backend_emit_relocs
c3c76620 21066
906e58ca
NC		 21067#undef bfd_elf32_bfd_link_hash_table_create
21068#define bfd_elf32_bfd_link_hash_table_create elf32_arm_symbian_link_hash_table_create
21069#undef elf_backend_special_sections
07d6d2b8 21070#define elf_backend_special_sections elf32_arm_symbian_special_sections
906e58ca
NC		 21071#undef elf_backend_begin_write_processing
21072#define elf_backend_begin_write_processing elf32_arm_symbian_begin_write_processing
21073#undef elf_backend_final_write_processing
21074#define elf_backend_final_write_processing elf32_arm_final_write_processing
21075
21076#undef elf_backend_modify_segment_map
7f266840
DJ		 21077#define elf_backend_modify_segment_map elf32_arm_symbian_modify_segment_map
21078
21079/* There is no .got section for BPABI objects, and hence no header. */
906e58ca 21080#undef elf_backend_got_header_size
7f266840
DJ		 21081#define elf_backend_got_header_size 0
21082
21083/* Similarly, there is no .got.plt section. */
906e58ca 21084#undef elf_backend_want_got_plt
7f266840
DJ		 21085#define elf_backend_want_got_plt 0
21086
906e58ca 21087#undef elf_backend_plt_sym_val
95720a86
DJ		 21088#define elf_backend_plt_sym_val elf32_arm_symbian_plt_sym_val
21089
906e58ca 21090#undef elf_backend_may_use_rel_p
00a97672 21091#define elf_backend_may_use_rel_p 1
906e58ca 21092#undef elf_backend_may_use_rela_p
00a97672 21093#define elf_backend_may_use_rela_p 0
906e58ca 21094#undef elf_backend_default_use_rela_p
00a97672 21095#define elf_backend_default_use_rela_p 0
906e58ca 21096#undef elf_backend_want_plt_sym
00a97672 21097#define elf_backend_want_plt_sym 0
64f52338
AM		 21098#undef elf_backend_dtrel_excludes_plt
21099#define elf_backend_dtrel_excludes_plt 0
906e58ca 21100#undef ELF_MAXPAGESIZE
00a97672 21101#define ELF_MAXPAGESIZE 0x8000
4e7fd91e 21102
7f266840 21103#include "elf32-target.h"
GDB Binutils - Deliverables
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