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[deliverable/binutils-gdb.git] / bfd / elf32-arm.c
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252b5132 1/* 32-bit ELF support for ARM
2571583a 2 Copyright (C) 1998-2017 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of BFD, the Binary File Descriptor library.
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
cd123cb7 8 the Free Software Foundation; either version 3 of the License, or
252b5132
RH		 9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
cd123cb7
NC		 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
252b5132 20
6e6718a3 21#include "sysdep.h"
2468f9c9
PB		 22#include <limits.h>
23
3db64b00 24#include "bfd.h"
6034aab8 25#include "bfd_stdint.h"
00a97672 26#include "libiberty.h"
7f266840
DJ		 27#include "libbfd.h"
28#include "elf-bfd.h"
b38cadfb 29#include "elf-nacl.h"
00a97672 30#include "elf-vxworks.h"
ee065d83 31#include "elf/arm.h"
7f266840 32
00a97672
RS		 33/* Return the relocation section associated with NAME. HTAB is the
34 bfd's elf32_arm_link_hash_entry. */
35#define RELOC_SECTION(HTAB, NAME) \
36 ((HTAB)->use_rel ? ".rel" NAME : ".rela" NAME)
37
38/* Return size of a relocation entry. HTAB is the bfd's
39 elf32_arm_link_hash_entry. */
40#define RELOC_SIZE(HTAB) \
41 ((HTAB)->use_rel \
42 ? sizeof (Elf32_External_Rel) \
43 : sizeof (Elf32_External_Rela))
44
45/* Return function to swap relocations in. HTAB is the bfd's
46 elf32_arm_link_hash_entry. */
47#define SWAP_RELOC_IN(HTAB) \
48 ((HTAB)->use_rel \
49 ? bfd_elf32_swap_reloc_in \
50 : bfd_elf32_swap_reloca_in)
51
52/* Return function to swap relocations out. HTAB is the bfd's
53 elf32_arm_link_hash_entry. */
54#define SWAP_RELOC_OUT(HTAB) \
55 ((HTAB)->use_rel \
56 ? bfd_elf32_swap_reloc_out \
57 : bfd_elf32_swap_reloca_out)
58
7f266840
DJ		 59#define elf_info_to_howto 0
60#define elf_info_to_howto_rel elf32_arm_info_to_howto
61
62#define ARM_ELF_ABI_VERSION 0
63#define ARM_ELF_OS_ABI_VERSION ELFOSABI_ARM
64
79f08007
YZ		 65/* The Adjusted Place, as defined by AAELF. */
66#define Pa(X) ((X) & 0xfffffffc)
67
3e6b1042
DJ		 68static bfd_boolean elf32_arm_write_section (bfd *output_bfd,
69 struct bfd_link_info *link_info,
70 asection *sec,
71 bfd_byte *contents);
72
7f266840
DJ		 73/* Note: code such as elf32_arm_reloc_type_lookup expect to use e.g.
74 R_ARM_PC24 as an index into this, and find the R_ARM_PC24 HOWTO
75 in that slot. */
76
c19d1205 77static reloc_howto_type elf32_arm_howto_table_1[] =
7f266840 78{
8029a119 79 /* No relocation. */
7f266840
DJ		 80 HOWTO (R_ARM_NONE, /* type */
81 0, /* rightshift */
6346d5ca 82 3, /* size (0 = byte, 1 = short, 2 = long) */
7f266840
DJ		 83 0, /* bitsize */
84 FALSE, /* pc_relative */
85 0, /* bitpos */
86 complain_overflow_dont,/* complain_on_overflow */
87 bfd_elf_generic_reloc, /* special_function */
88 "R_ARM_NONE", /* name */
89 FALSE, /* partial_inplace */
90 0, /* src_mask */
91 0, /* dst_mask */
92 FALSE), /* pcrel_offset */
93
94 HOWTO (R_ARM_PC24, /* type */
95 2, /* rightshift */
96 2, /* size (0 = byte, 1 = short, 2 = long) */
97 24, /* bitsize */
98 TRUE, /* pc_relative */
99 0, /* bitpos */
100 complain_overflow_signed,/* complain_on_overflow */
101 bfd_elf_generic_reloc, /* special_function */
102 "R_ARM_PC24", /* name */
103 FALSE, /* partial_inplace */
104 0x00ffffff, /* src_mask */
105 0x00ffffff, /* dst_mask */
106 TRUE), /* pcrel_offset */
107
108 /* 32 bit absolute */
109 HOWTO (R_ARM_ABS32, /* type */
110 0, /* rightshift */
111 2, /* size (0 = byte, 1 = short, 2 = long) */
112 32, /* bitsize */
113 FALSE, /* pc_relative */
114 0, /* bitpos */
115 complain_overflow_bitfield,/* complain_on_overflow */
116 bfd_elf_generic_reloc, /* special_function */
117 "R_ARM_ABS32", /* name */
118 FALSE, /* partial_inplace */
119 0xffffffff, /* src_mask */
120 0xffffffff, /* dst_mask */
121 FALSE), /* pcrel_offset */
122
123 /* standard 32bit pc-relative reloc */
124 HOWTO (R_ARM_REL32, /* type */
125 0, /* rightshift */
126 2, /* size (0 = byte, 1 = short, 2 = long) */
127 32, /* bitsize */
128 TRUE, /* pc_relative */
129 0, /* bitpos */
130 complain_overflow_bitfield,/* complain_on_overflow */
131 bfd_elf_generic_reloc, /* special_function */
132 "R_ARM_REL32", /* name */
133 FALSE, /* partial_inplace */
134 0xffffffff, /* src_mask */
135 0xffffffff, /* dst_mask */
136 TRUE), /* pcrel_offset */
137
c19d1205 138 /* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */
4962c51a 139 HOWTO (R_ARM_LDR_PC_G0, /* type */
7f266840
DJ		 140 0, /* rightshift */
141 0, /* size (0 = byte, 1 = short, 2 = long) */
4962c51a
MS		 142 32, /* bitsize */
143 TRUE, /* pc_relative */
7f266840 144 0, /* bitpos */
4962c51a 145 complain_overflow_dont,/* complain_on_overflow */
7f266840 146 bfd_elf_generic_reloc, /* special_function */
4962c51a 147 "R_ARM_LDR_PC_G0", /* name */
7f266840 148 FALSE, /* partial_inplace */
4962c51a
MS		 149 0xffffffff, /* src_mask */
150 0xffffffff, /* dst_mask */
151 TRUE), /* pcrel_offset */
7f266840
DJ		 152
153 /* 16 bit absolute */
154 HOWTO (R_ARM_ABS16, /* type */
155 0, /* rightshift */
156 1, /* size (0 = byte, 1 = short, 2 = long) */
157 16, /* bitsize */
158 FALSE, /* pc_relative */
159 0, /* bitpos */
160 complain_overflow_bitfield,/* complain_on_overflow */
161 bfd_elf_generic_reloc, /* special_function */
162 "R_ARM_ABS16", /* name */
163 FALSE, /* partial_inplace */
164 0x0000ffff, /* src_mask */
165 0x0000ffff, /* dst_mask */
166 FALSE), /* pcrel_offset */
167
168 /* 12 bit absolute */
169 HOWTO (R_ARM_ABS12, /* type */
170 0, /* rightshift */
171 2, /* size (0 = byte, 1 = short, 2 = long) */
172 12, /* bitsize */
173 FALSE, /* pc_relative */
174 0, /* bitpos */
175 complain_overflow_bitfield,/* complain_on_overflow */
176 bfd_elf_generic_reloc, /* special_function */
177 "R_ARM_ABS12", /* name */
178 FALSE, /* partial_inplace */
00a97672
RS		 179 0x00000fff, /* src_mask */
180 0x00000fff, /* dst_mask */
7f266840
DJ		 181 FALSE), /* pcrel_offset */
182
183 HOWTO (R_ARM_THM_ABS5, /* type */
184 6, /* rightshift */
185 1, /* size (0 = byte, 1 = short, 2 = long) */
186 5, /* bitsize */
187 FALSE, /* pc_relative */
188 0, /* bitpos */
189 complain_overflow_bitfield,/* complain_on_overflow */
190 bfd_elf_generic_reloc, /* special_function */
191 "R_ARM_THM_ABS5", /* name */
192 FALSE, /* partial_inplace */
193 0x000007e0, /* src_mask */
194 0x000007e0, /* dst_mask */
195 FALSE), /* pcrel_offset */
196
197 /* 8 bit absolute */
198 HOWTO (R_ARM_ABS8, /* type */
199 0, /* rightshift */
200 0, /* size (0 = byte, 1 = short, 2 = long) */
201 8, /* bitsize */
202 FALSE, /* pc_relative */
203 0, /* bitpos */
204 complain_overflow_bitfield,/* complain_on_overflow */
205 bfd_elf_generic_reloc, /* special_function */
206 "R_ARM_ABS8", /* name */
207 FALSE, /* partial_inplace */
208 0x000000ff, /* src_mask */
209 0x000000ff, /* dst_mask */
210 FALSE), /* pcrel_offset */
211
212 HOWTO (R_ARM_SBREL32, /* type */
213 0, /* rightshift */
214 2, /* size (0 = byte, 1 = short, 2 = long) */
215 32, /* bitsize */
216 FALSE, /* pc_relative */
217 0, /* bitpos */
218 complain_overflow_dont,/* complain_on_overflow */
219 bfd_elf_generic_reloc, /* special_function */
220 "R_ARM_SBREL32", /* name */
221 FALSE, /* partial_inplace */
222 0xffffffff, /* src_mask */
223 0xffffffff, /* dst_mask */
224 FALSE), /* pcrel_offset */
225
c19d1205 226 HOWTO (R_ARM_THM_CALL, /* type */
7f266840
DJ		 227 1, /* rightshift */
228 2, /* size (0 = byte, 1 = short, 2 = long) */
f6ebfac0 229 24, /* bitsize */
7f266840
DJ		 230 TRUE, /* pc_relative */
231 0, /* bitpos */
232 complain_overflow_signed,/* complain_on_overflow */
233 bfd_elf_generic_reloc, /* special_function */
c19d1205 234 "R_ARM_THM_CALL", /* name */
7f266840 235 FALSE, /* partial_inplace */
7f6ab9f8
AM		 236 0x07ff2fff, /* src_mask */
237 0x07ff2fff, /* dst_mask */
7f266840
DJ		 238 TRUE), /* pcrel_offset */
239
240 HOWTO (R_ARM_THM_PC8, /* type */
241 1, /* rightshift */
242 1, /* size (0 = byte, 1 = short, 2 = long) */
243 8, /* bitsize */
244 TRUE, /* pc_relative */
245 0, /* bitpos */
246 complain_overflow_signed,/* complain_on_overflow */
247 bfd_elf_generic_reloc, /* special_function */
248 "R_ARM_THM_PC8", /* name */
249 FALSE, /* partial_inplace */
250 0x000000ff, /* src_mask */
251 0x000000ff, /* dst_mask */
252 TRUE), /* pcrel_offset */
253
c19d1205 254 HOWTO (R_ARM_BREL_ADJ, /* type */
7f266840
DJ		 255 1, /* rightshift */
256 1, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 257 32, /* bitsize */
258 FALSE, /* pc_relative */
7f266840
DJ		 259 0, /* bitpos */
260 complain_overflow_signed,/* complain_on_overflow */
261 bfd_elf_generic_reloc, /* special_function */
c19d1205 262 "R_ARM_BREL_ADJ", /* name */
7f266840 263 FALSE, /* partial_inplace */
c19d1205
ZW		 264 0xffffffff, /* src_mask */
265 0xffffffff, /* dst_mask */
266 FALSE), /* pcrel_offset */
7f266840 267
0855e32b 268 HOWTO (R_ARM_TLS_DESC, /* type */
7f266840 269 0, /* rightshift */
0855e32b
NS		 270 2, /* size (0 = byte, 1 = short, 2 = long) */
271 32, /* bitsize */
7f266840
DJ		 272 FALSE, /* pc_relative */
273 0, /* bitpos */
0855e32b 274 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 275 bfd_elf_generic_reloc, /* special_function */
0855e32b 276 "R_ARM_TLS_DESC", /* name */
7f266840 277 FALSE, /* partial_inplace */
0855e32b
NS		 278 0xffffffff, /* src_mask */
279 0xffffffff, /* dst_mask */
7f266840
DJ		 280 FALSE), /* pcrel_offset */
281
282 HOWTO (R_ARM_THM_SWI8, /* type */
283 0, /* rightshift */
284 0, /* size (0 = byte, 1 = short, 2 = long) */
285 0, /* bitsize */
286 FALSE, /* pc_relative */
287 0, /* bitpos */
288 complain_overflow_signed,/* complain_on_overflow */
289 bfd_elf_generic_reloc, /* special_function */
290 "R_ARM_SWI8", /* name */
291 FALSE, /* partial_inplace */
292 0x00000000, /* src_mask */
293 0x00000000, /* dst_mask */
294 FALSE), /* pcrel_offset */
295
296 /* BLX instruction for the ARM. */
297 HOWTO (R_ARM_XPC25, /* type */
298 2, /* rightshift */
299 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 300 24, /* bitsize */
7f266840
DJ		 301 TRUE, /* pc_relative */
302 0, /* bitpos */
303 complain_overflow_signed,/* complain_on_overflow */
304 bfd_elf_generic_reloc, /* special_function */
305 "R_ARM_XPC25", /* name */
306 FALSE, /* partial_inplace */
307 0x00ffffff, /* src_mask */
308 0x00ffffff, /* dst_mask */
309 TRUE), /* pcrel_offset */
310
311 /* BLX instruction for the Thumb. */
312 HOWTO (R_ARM_THM_XPC22, /* type */
313 2, /* rightshift */
314 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 315 24, /* bitsize */
7f266840
DJ		 316 TRUE, /* pc_relative */
317 0, /* bitpos */
318 complain_overflow_signed,/* complain_on_overflow */
319 bfd_elf_generic_reloc, /* special_function */
320 "R_ARM_THM_XPC22", /* name */
321 FALSE, /* partial_inplace */
7f6ab9f8
AM		 322 0x07ff2fff, /* src_mask */
323 0x07ff2fff, /* dst_mask */
7f266840
DJ		 324 TRUE), /* pcrel_offset */
325
ba93b8ac 326 /* Dynamic TLS relocations. */
7f266840 327
ba93b8ac 328 HOWTO (R_ARM_TLS_DTPMOD32, /* type */
99059e56
RM		 329 0, /* rightshift */
330 2, /* size (0 = byte, 1 = short, 2 = long) */
331 32, /* bitsize */
332 FALSE, /* pc_relative */
333 0, /* bitpos */
334 complain_overflow_bitfield,/* complain_on_overflow */
335 bfd_elf_generic_reloc, /* special_function */
336 "R_ARM_TLS_DTPMOD32", /* name */
337 TRUE, /* partial_inplace */
338 0xffffffff, /* src_mask */
339 0xffffffff, /* dst_mask */
340 FALSE), /* pcrel_offset */
7f266840 341
ba93b8ac 342 HOWTO (R_ARM_TLS_DTPOFF32, /* type */
99059e56
RM		 343 0, /* rightshift */
344 2, /* size (0 = byte, 1 = short, 2 = long) */
345 32, /* bitsize */
346 FALSE, /* pc_relative */
347 0, /* bitpos */
348 complain_overflow_bitfield,/* complain_on_overflow */
349 bfd_elf_generic_reloc, /* special_function */
350 "R_ARM_TLS_DTPOFF32", /* name */
351 TRUE, /* partial_inplace */
352 0xffffffff, /* src_mask */
353 0xffffffff, /* dst_mask */
354 FALSE), /* pcrel_offset */
7f266840 355
ba93b8ac 356 HOWTO (R_ARM_TLS_TPOFF32, /* type */
99059e56
RM		 357 0, /* rightshift */
358 2, /* size (0 = byte, 1 = short, 2 = long) */
359 32, /* bitsize */
360 FALSE, /* pc_relative */
361 0, /* bitpos */
362 complain_overflow_bitfield,/* complain_on_overflow */
363 bfd_elf_generic_reloc, /* special_function */
364 "R_ARM_TLS_TPOFF32", /* name */
365 TRUE, /* partial_inplace */
366 0xffffffff, /* src_mask */
367 0xffffffff, /* dst_mask */
368 FALSE), /* pcrel_offset */
7f266840
DJ		 369
370 /* Relocs used in ARM Linux */
371
372 HOWTO (R_ARM_COPY, /* type */
99059e56
RM		 373 0, /* rightshift */
374 2, /* size (0 = byte, 1 = short, 2 = long) */
375 32, /* bitsize */
376 FALSE, /* pc_relative */
377 0, /* bitpos */
378 complain_overflow_bitfield,/* complain_on_overflow */
379 bfd_elf_generic_reloc, /* special_function */
380 "R_ARM_COPY", /* name */
381 TRUE, /* partial_inplace */
382 0xffffffff, /* src_mask */
383 0xffffffff, /* dst_mask */
384 FALSE), /* pcrel_offset */
7f266840
DJ		 385
386 HOWTO (R_ARM_GLOB_DAT, /* type */
99059e56
RM		 387 0, /* rightshift */
388 2, /* size (0 = byte, 1 = short, 2 = long) */
389 32, /* bitsize */
390 FALSE, /* pc_relative */
391 0, /* bitpos */
392 complain_overflow_bitfield,/* complain_on_overflow */
393 bfd_elf_generic_reloc, /* special_function */
394 "R_ARM_GLOB_DAT", /* name */
395 TRUE, /* partial_inplace */
396 0xffffffff, /* src_mask */
397 0xffffffff, /* dst_mask */
398 FALSE), /* pcrel_offset */
7f266840
DJ		 399
400 HOWTO (R_ARM_JUMP_SLOT, /* type */
99059e56
RM		 401 0, /* rightshift */
402 2, /* size (0 = byte, 1 = short, 2 = long) */
403 32, /* bitsize */
404 FALSE, /* pc_relative */
405 0, /* bitpos */
406 complain_overflow_bitfield,/* complain_on_overflow */
407 bfd_elf_generic_reloc, /* special_function */
408 "R_ARM_JUMP_SLOT", /* name */
409 TRUE, /* partial_inplace */
410 0xffffffff, /* src_mask */
411 0xffffffff, /* dst_mask */
412 FALSE), /* pcrel_offset */
7f266840
DJ		 413
414 HOWTO (R_ARM_RELATIVE, /* type */
99059e56
RM		 415 0, /* rightshift */
416 2, /* size (0 = byte, 1 = short, 2 = long) */
417 32, /* bitsize */
418 FALSE, /* pc_relative */
419 0, /* bitpos */
420 complain_overflow_bitfield,/* complain_on_overflow */
421 bfd_elf_generic_reloc, /* special_function */
422 "R_ARM_RELATIVE", /* name */
423 TRUE, /* partial_inplace */
424 0xffffffff, /* src_mask */
425 0xffffffff, /* dst_mask */
426 FALSE), /* pcrel_offset */
7f266840 427
c19d1205 428 HOWTO (R_ARM_GOTOFF32, /* type */
99059e56
RM		 429 0, /* rightshift */
430 2, /* size (0 = byte, 1 = short, 2 = long) */
431 32, /* bitsize */
432 FALSE, /* pc_relative */
433 0, /* bitpos */
434 complain_overflow_bitfield,/* complain_on_overflow */
435 bfd_elf_generic_reloc, /* special_function */
436 "R_ARM_GOTOFF32", /* name */
437 TRUE, /* partial_inplace */
438 0xffffffff, /* src_mask */
439 0xffffffff, /* dst_mask */
440 FALSE), /* pcrel_offset */
7f266840
DJ		 441
442 HOWTO (R_ARM_GOTPC, /* type */
99059e56
RM		 443 0, /* rightshift */
444 2, /* size (0 = byte, 1 = short, 2 = long) */
445 32, /* bitsize */
446 TRUE, /* pc_relative */
447 0, /* bitpos */
448 complain_overflow_bitfield,/* complain_on_overflow */
449 bfd_elf_generic_reloc, /* special_function */
450 "R_ARM_GOTPC", /* name */
451 TRUE, /* partial_inplace */
452 0xffffffff, /* src_mask */
453 0xffffffff, /* dst_mask */
454 TRUE), /* pcrel_offset */
7f266840
DJ		 455
456 HOWTO (R_ARM_GOT32, /* type */
99059e56
RM		 457 0, /* rightshift */
458 2, /* size (0 = byte, 1 = short, 2 = long) */
459 32, /* bitsize */
460 FALSE, /* pc_relative */
461 0, /* bitpos */
462 complain_overflow_bitfield,/* complain_on_overflow */
463 bfd_elf_generic_reloc, /* special_function */
464 "R_ARM_GOT32", /* name */
465 TRUE, /* partial_inplace */
466 0xffffffff, /* src_mask */
467 0xffffffff, /* dst_mask */
468 FALSE), /* pcrel_offset */
7f266840
DJ		 469
470 HOWTO (R_ARM_PLT32, /* type */
99059e56
RM		 471 2, /* rightshift */
472 2, /* size (0 = byte, 1 = short, 2 = long) */
473 24, /* bitsize */
474 TRUE, /* pc_relative */
475 0, /* bitpos */
476 complain_overflow_bitfield,/* complain_on_overflow */
477 bfd_elf_generic_reloc, /* special_function */
478 "R_ARM_PLT32", /* name */
479 FALSE, /* partial_inplace */
480 0x00ffffff, /* src_mask */
481 0x00ffffff, /* dst_mask */
482 TRUE), /* pcrel_offset */
7f266840
DJ		 483
484 HOWTO (R_ARM_CALL, /* type */
485 2, /* rightshift */
486 2, /* size (0 = byte, 1 = short, 2 = long) */
487 24, /* bitsize */
488 TRUE, /* pc_relative */
489 0, /* bitpos */
490 complain_overflow_signed,/* complain_on_overflow */
491 bfd_elf_generic_reloc, /* special_function */
492 "R_ARM_CALL", /* name */
493 FALSE, /* partial_inplace */
494 0x00ffffff, /* src_mask */
495 0x00ffffff, /* dst_mask */
496 TRUE), /* pcrel_offset */
497
498 HOWTO (R_ARM_JUMP24, /* type */
499 2, /* rightshift */
500 2, /* size (0 = byte, 1 = short, 2 = long) */
501 24, /* bitsize */
502 TRUE, /* pc_relative */
503 0, /* bitpos */
504 complain_overflow_signed,/* complain_on_overflow */
505 bfd_elf_generic_reloc, /* special_function */
506 "R_ARM_JUMP24", /* name */
507 FALSE, /* partial_inplace */
508 0x00ffffff, /* src_mask */
509 0x00ffffff, /* dst_mask */
510 TRUE), /* pcrel_offset */
511
c19d1205
ZW		 512 HOWTO (R_ARM_THM_JUMP24, /* type */
513 1, /* rightshift */
514 2, /* size (0 = byte, 1 = short, 2 = long) */
515 24, /* bitsize */
516 TRUE, /* pc_relative */
7f266840 517 0, /* bitpos */
c19d1205 518 complain_overflow_signed,/* complain_on_overflow */
7f266840 519 bfd_elf_generic_reloc, /* special_function */
c19d1205 520 "R_ARM_THM_JUMP24", /* name */
7f266840 521 FALSE, /* partial_inplace */
c19d1205
ZW		 522 0x07ff2fff, /* src_mask */
523 0x07ff2fff, /* dst_mask */
524 TRUE), /* pcrel_offset */
7f266840 525
c19d1205 526 HOWTO (R_ARM_BASE_ABS, /* type */
7f266840 527 0, /* rightshift */
c19d1205
ZW		 528 2, /* size (0 = byte, 1 = short, 2 = long) */
529 32, /* bitsize */
7f266840
DJ		 530 FALSE, /* pc_relative */
531 0, /* bitpos */
532 complain_overflow_dont,/* complain_on_overflow */
533 bfd_elf_generic_reloc, /* special_function */
c19d1205 534 "R_ARM_BASE_ABS", /* name */
7f266840 535 FALSE, /* partial_inplace */
c19d1205
ZW		 536 0xffffffff, /* src_mask */
537 0xffffffff, /* dst_mask */
7f266840
DJ		 538 FALSE), /* pcrel_offset */
539
540 HOWTO (R_ARM_ALU_PCREL7_0, /* type */
541 0, /* rightshift */
542 2, /* size (0 = byte, 1 = short, 2 = long) */
543 12, /* bitsize */
544 TRUE, /* pc_relative */
545 0, /* bitpos */
546 complain_overflow_dont,/* complain_on_overflow */
547 bfd_elf_generic_reloc, /* special_function */
548 "R_ARM_ALU_PCREL_7_0", /* name */
549 FALSE, /* partial_inplace */
550 0x00000fff, /* src_mask */
551 0x00000fff, /* dst_mask */
552 TRUE), /* pcrel_offset */
553
554 HOWTO (R_ARM_ALU_PCREL15_8, /* type */
555 0, /* rightshift */
556 2, /* size (0 = byte, 1 = short, 2 = long) */
557 12, /* bitsize */
558 TRUE, /* pc_relative */
559 8, /* bitpos */
560 complain_overflow_dont,/* complain_on_overflow */
561 bfd_elf_generic_reloc, /* special_function */
562 "R_ARM_ALU_PCREL_15_8",/* name */
563 FALSE, /* partial_inplace */
564 0x00000fff, /* src_mask */
565 0x00000fff, /* dst_mask */
566 TRUE), /* pcrel_offset */
567
568 HOWTO (R_ARM_ALU_PCREL23_15, /* type */
569 0, /* rightshift */
570 2, /* size (0 = byte, 1 = short, 2 = long) */
571 12, /* bitsize */
572 TRUE, /* pc_relative */
573 16, /* bitpos */
574 complain_overflow_dont,/* complain_on_overflow */
575 bfd_elf_generic_reloc, /* special_function */
576 "R_ARM_ALU_PCREL_23_15",/* name */
577 FALSE, /* partial_inplace */
578 0x00000fff, /* src_mask */
579 0x00000fff, /* dst_mask */
580 TRUE), /* pcrel_offset */
581
582 HOWTO (R_ARM_LDR_SBREL_11_0, /* type */
583 0, /* rightshift */
584 2, /* size (0 = byte, 1 = short, 2 = long) */
585 12, /* bitsize */
586 FALSE, /* pc_relative */
587 0, /* bitpos */
588 complain_overflow_dont,/* complain_on_overflow */
589 bfd_elf_generic_reloc, /* special_function */
590 "R_ARM_LDR_SBREL_11_0",/* name */
591 FALSE, /* partial_inplace */
592 0x00000fff, /* src_mask */
593 0x00000fff, /* dst_mask */
594 FALSE), /* pcrel_offset */
595
596 HOWTO (R_ARM_ALU_SBREL_19_12, /* type */
597 0, /* rightshift */
598 2, /* size (0 = byte, 1 = short, 2 = long) */
599 8, /* bitsize */
600 FALSE, /* pc_relative */
601 12, /* bitpos */
602 complain_overflow_dont,/* complain_on_overflow */
603 bfd_elf_generic_reloc, /* special_function */
604 "R_ARM_ALU_SBREL_19_12",/* name */
605 FALSE, /* partial_inplace */
606 0x000ff000, /* src_mask */
607 0x000ff000, /* dst_mask */
608 FALSE), /* pcrel_offset */
609
610 HOWTO (R_ARM_ALU_SBREL_27_20, /* type */
611 0, /* rightshift */
612 2, /* size (0 = byte, 1 = short, 2 = long) */
613 8, /* bitsize */
614 FALSE, /* pc_relative */
615 20, /* bitpos */
616 complain_overflow_dont,/* complain_on_overflow */
617 bfd_elf_generic_reloc, /* special_function */
618 "R_ARM_ALU_SBREL_27_20",/* name */
619 FALSE, /* partial_inplace */
620 0x0ff00000, /* src_mask */
621 0x0ff00000, /* dst_mask */
622 FALSE), /* pcrel_offset */
623
624 HOWTO (R_ARM_TARGET1, /* type */
625 0, /* rightshift */
626 2, /* size (0 = byte, 1 = short, 2 = long) */
627 32, /* bitsize */
628 FALSE, /* pc_relative */
629 0, /* bitpos */
630 complain_overflow_dont,/* complain_on_overflow */
631 bfd_elf_generic_reloc, /* special_function */
632 "R_ARM_TARGET1", /* name */
633 FALSE, /* partial_inplace */
634 0xffffffff, /* src_mask */
635 0xffffffff, /* dst_mask */
636 FALSE), /* pcrel_offset */
637
638 HOWTO (R_ARM_ROSEGREL32, /* type */
639 0, /* rightshift */
640 2, /* size (0 = byte, 1 = short, 2 = long) */
641 32, /* bitsize */
642 FALSE, /* pc_relative */
643 0, /* bitpos */
644 complain_overflow_dont,/* complain_on_overflow */
645 bfd_elf_generic_reloc, /* special_function */
646 "R_ARM_ROSEGREL32", /* name */
647 FALSE, /* partial_inplace */
648 0xffffffff, /* src_mask */
649 0xffffffff, /* dst_mask */
650 FALSE), /* pcrel_offset */
651
652 HOWTO (R_ARM_V4BX, /* type */
653 0, /* rightshift */
654 2, /* size (0 = byte, 1 = short, 2 = long) */
655 32, /* bitsize */
656 FALSE, /* pc_relative */
657 0, /* bitpos */
658 complain_overflow_dont,/* complain_on_overflow */
659 bfd_elf_generic_reloc, /* special_function */
660 "R_ARM_V4BX", /* name */
661 FALSE, /* partial_inplace */
662 0xffffffff, /* src_mask */
663 0xffffffff, /* dst_mask */
664 FALSE), /* pcrel_offset */
665
666 HOWTO (R_ARM_TARGET2, /* type */
667 0, /* rightshift */
668 2, /* size (0 = byte, 1 = short, 2 = long) */
669 32, /* bitsize */
670 FALSE, /* pc_relative */
671 0, /* bitpos */
672 complain_overflow_signed,/* complain_on_overflow */
673 bfd_elf_generic_reloc, /* special_function */
674 "R_ARM_TARGET2", /* name */
675 FALSE, /* partial_inplace */
676 0xffffffff, /* src_mask */
677 0xffffffff, /* dst_mask */
678 TRUE), /* pcrel_offset */
679
680 HOWTO (R_ARM_PREL31, /* type */
681 0, /* rightshift */
682 2, /* size (0 = byte, 1 = short, 2 = long) */
683 31, /* bitsize */
684 TRUE, /* pc_relative */
685 0, /* bitpos */
686 complain_overflow_signed,/* complain_on_overflow */
687 bfd_elf_generic_reloc, /* special_function */
688 "R_ARM_PREL31", /* name */
689 FALSE, /* partial_inplace */
690 0x7fffffff, /* src_mask */
691 0x7fffffff, /* dst_mask */
692 TRUE), /* pcrel_offset */
c19d1205
ZW		 693
694 HOWTO (R_ARM_MOVW_ABS_NC, /* type */
695 0, /* rightshift */
696 2, /* size (0 = byte, 1 = short, 2 = long) */
697 16, /* bitsize */
698 FALSE, /* pc_relative */
699 0, /* bitpos */
700 complain_overflow_dont,/* complain_on_overflow */
701 bfd_elf_generic_reloc, /* special_function */
702 "R_ARM_MOVW_ABS_NC", /* name */
703 FALSE, /* partial_inplace */
39623e12
PB		 704 0x000f0fff, /* src_mask */
705 0x000f0fff, /* dst_mask */
c19d1205
ZW		 706 FALSE), /* pcrel_offset */
707
708 HOWTO (R_ARM_MOVT_ABS, /* type */
709 0, /* rightshift */
710 2, /* size (0 = byte, 1 = short, 2 = long) */
711 16, /* bitsize */
712 FALSE, /* pc_relative */
713 0, /* bitpos */
714 complain_overflow_bitfield,/* complain_on_overflow */
715 bfd_elf_generic_reloc, /* special_function */
716 "R_ARM_MOVT_ABS", /* name */
717 FALSE, /* partial_inplace */
39623e12
PB		 718 0x000f0fff, /* src_mask */
719 0x000f0fff, /* dst_mask */
c19d1205
ZW		 720 FALSE), /* pcrel_offset */
721
722 HOWTO (R_ARM_MOVW_PREL_NC, /* type */
723 0, /* rightshift */
724 2, /* size (0 = byte, 1 = short, 2 = long) */
725 16, /* bitsize */
726 TRUE, /* pc_relative */
727 0, /* bitpos */
728 complain_overflow_dont,/* complain_on_overflow */
729 bfd_elf_generic_reloc, /* special_function */
730 "R_ARM_MOVW_PREL_NC", /* name */
731 FALSE, /* partial_inplace */
39623e12
PB		 732 0x000f0fff, /* src_mask */
733 0x000f0fff, /* dst_mask */
c19d1205
ZW		 734 TRUE), /* pcrel_offset */
735
736 HOWTO (R_ARM_MOVT_PREL, /* type */
737 0, /* rightshift */
738 2, /* size (0 = byte, 1 = short, 2 = long) */
739 16, /* bitsize */
740 TRUE, /* pc_relative */
741 0, /* bitpos */
742 complain_overflow_bitfield,/* complain_on_overflow */
743 bfd_elf_generic_reloc, /* special_function */
744 "R_ARM_MOVT_PREL", /* name */
745 FALSE, /* partial_inplace */
39623e12
PB		 746 0x000f0fff, /* src_mask */
747 0x000f0fff, /* dst_mask */
c19d1205
ZW		 748 TRUE), /* pcrel_offset */
749
750 HOWTO (R_ARM_THM_MOVW_ABS_NC, /* type */
751 0, /* rightshift */
752 2, /* size (0 = byte, 1 = short, 2 = long) */
753 16, /* bitsize */
754 FALSE, /* pc_relative */
755 0, /* bitpos */
756 complain_overflow_dont,/* complain_on_overflow */
757 bfd_elf_generic_reloc, /* special_function */
758 "R_ARM_THM_MOVW_ABS_NC",/* name */
759 FALSE, /* partial_inplace */
760 0x040f70ff, /* src_mask */
761 0x040f70ff, /* dst_mask */
762 FALSE), /* pcrel_offset */
763
764 HOWTO (R_ARM_THM_MOVT_ABS, /* type */
765 0, /* rightshift */
766 2, /* size (0 = byte, 1 = short, 2 = long) */
767 16, /* bitsize */
768 FALSE, /* pc_relative */
769 0, /* bitpos */
770 complain_overflow_bitfield,/* complain_on_overflow */
771 bfd_elf_generic_reloc, /* special_function */
772 "R_ARM_THM_MOVT_ABS", /* name */
773 FALSE, /* partial_inplace */
774 0x040f70ff, /* src_mask */
775 0x040f70ff, /* dst_mask */
776 FALSE), /* pcrel_offset */
777
778 HOWTO (R_ARM_THM_MOVW_PREL_NC,/* type */
779 0, /* rightshift */
780 2, /* size (0 = byte, 1 = short, 2 = long) */
781 16, /* bitsize */
782 TRUE, /* pc_relative */
783 0, /* bitpos */
784 complain_overflow_dont,/* complain_on_overflow */
785 bfd_elf_generic_reloc, /* special_function */
786 "R_ARM_THM_MOVW_PREL_NC",/* name */
787 FALSE, /* partial_inplace */
788 0x040f70ff, /* src_mask */
789 0x040f70ff, /* dst_mask */
790 TRUE), /* pcrel_offset */
791
792 HOWTO (R_ARM_THM_MOVT_PREL, /* type */
793 0, /* rightshift */
794 2, /* size (0 = byte, 1 = short, 2 = long) */
795 16, /* bitsize */
796 TRUE, /* pc_relative */
797 0, /* bitpos */
798 complain_overflow_bitfield,/* complain_on_overflow */
799 bfd_elf_generic_reloc, /* special_function */
800 "R_ARM_THM_MOVT_PREL", /* name */
801 FALSE, /* partial_inplace */
802 0x040f70ff, /* src_mask */
803 0x040f70ff, /* dst_mask */
804 TRUE), /* pcrel_offset */
805
806 HOWTO (R_ARM_THM_JUMP19, /* type */
807 1, /* rightshift */
808 2, /* size (0 = byte, 1 = short, 2 = long) */
809 19, /* bitsize */
810 TRUE, /* pc_relative */
811 0, /* bitpos */
812 complain_overflow_signed,/* complain_on_overflow */
813 bfd_elf_generic_reloc, /* special_function */
814 "R_ARM_THM_JUMP19", /* name */
815 FALSE, /* partial_inplace */
816 0x043f2fff, /* src_mask */
817 0x043f2fff, /* dst_mask */
818 TRUE), /* pcrel_offset */
819
820 HOWTO (R_ARM_THM_JUMP6, /* type */
821 1, /* rightshift */
822 1, /* size (0 = byte, 1 = short, 2 = long) */
823 6, /* bitsize */
824 TRUE, /* pc_relative */
825 0, /* bitpos */
826 complain_overflow_unsigned,/* complain_on_overflow */
827 bfd_elf_generic_reloc, /* special_function */
828 "R_ARM_THM_JUMP6", /* name */
829 FALSE, /* partial_inplace */
830 0x02f8, /* src_mask */
831 0x02f8, /* dst_mask */
832 TRUE), /* pcrel_offset */
833
834 /* These are declared as 13-bit signed relocations because we can
835 address -4095 .. 4095(base) by altering ADDW to SUBW or vice
836 versa. */
837 HOWTO (R_ARM_THM_ALU_PREL_11_0,/* type */
838 0, /* rightshift */
839 2, /* size (0 = byte, 1 = short, 2 = long) */
840 13, /* bitsize */
841 TRUE, /* pc_relative */
842 0, /* bitpos */
2cab6cc3 843 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 844 bfd_elf_generic_reloc, /* special_function */
845 "R_ARM_THM_ALU_PREL_11_0",/* name */
846 FALSE, /* partial_inplace */
2cab6cc3
MS		 847 0xffffffff, /* src_mask */
848 0xffffffff, /* dst_mask */
c19d1205
ZW		 849 TRUE), /* pcrel_offset */
850
851 HOWTO (R_ARM_THM_PC12, /* type */
852 0, /* rightshift */
853 2, /* size (0 = byte, 1 = short, 2 = long) */
854 13, /* bitsize */
855 TRUE, /* pc_relative */
856 0, /* bitpos */
2cab6cc3 857 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 858 bfd_elf_generic_reloc, /* special_function */
859 "R_ARM_THM_PC12", /* name */
860 FALSE, /* partial_inplace */
2cab6cc3
MS		 861 0xffffffff, /* src_mask */
862 0xffffffff, /* dst_mask */
c19d1205
ZW		 863 TRUE), /* pcrel_offset */
864
865 HOWTO (R_ARM_ABS32_NOI, /* type */
866 0, /* rightshift */
867 2, /* size (0 = byte, 1 = short, 2 = long) */
868 32, /* bitsize */
869 FALSE, /* pc_relative */
870 0, /* bitpos */
871 complain_overflow_dont,/* complain_on_overflow */
872 bfd_elf_generic_reloc, /* special_function */
873 "R_ARM_ABS32_NOI", /* name */
874 FALSE, /* partial_inplace */
875 0xffffffff, /* src_mask */
876 0xffffffff, /* dst_mask */
877 FALSE), /* pcrel_offset */
878
879 HOWTO (R_ARM_REL32_NOI, /* type */
880 0, /* rightshift */
881 2, /* size (0 = byte, 1 = short, 2 = long) */
882 32, /* bitsize */
883 TRUE, /* pc_relative */
884 0, /* bitpos */
885 complain_overflow_dont,/* complain_on_overflow */
886 bfd_elf_generic_reloc, /* special_function */
887 "R_ARM_REL32_NOI", /* name */
888 FALSE, /* partial_inplace */
889 0xffffffff, /* src_mask */
890 0xffffffff, /* dst_mask */
891 FALSE), /* pcrel_offset */
7f266840 892
4962c51a
MS		 893 /* Group relocations. */
894
895 HOWTO (R_ARM_ALU_PC_G0_NC, /* type */
896 0, /* rightshift */
897 2, /* size (0 = byte, 1 = short, 2 = long) */
898 32, /* bitsize */
899 TRUE, /* pc_relative */
900 0, /* bitpos */
901 complain_overflow_dont,/* complain_on_overflow */
902 bfd_elf_generic_reloc, /* special_function */
903 "R_ARM_ALU_PC_G0_NC", /* name */
904 FALSE, /* partial_inplace */
905 0xffffffff, /* src_mask */
906 0xffffffff, /* dst_mask */
907 TRUE), /* pcrel_offset */
908
909 HOWTO (R_ARM_ALU_PC_G0, /* type */
910 0, /* rightshift */
911 2, /* size (0 = byte, 1 = short, 2 = long) */
912 32, /* bitsize */
913 TRUE, /* pc_relative */
914 0, /* bitpos */
915 complain_overflow_dont,/* complain_on_overflow */
916 bfd_elf_generic_reloc, /* special_function */
917 "R_ARM_ALU_PC_G0", /* name */
918 FALSE, /* partial_inplace */
919 0xffffffff, /* src_mask */
920 0xffffffff, /* dst_mask */
921 TRUE), /* pcrel_offset */
922
923 HOWTO (R_ARM_ALU_PC_G1_NC, /* type */
924 0, /* rightshift */
925 2, /* size (0 = byte, 1 = short, 2 = long) */
926 32, /* bitsize */
927 TRUE, /* pc_relative */
928 0, /* bitpos */
929 complain_overflow_dont,/* complain_on_overflow */
930 bfd_elf_generic_reloc, /* special_function */
931 "R_ARM_ALU_PC_G1_NC", /* name */
932 FALSE, /* partial_inplace */
933 0xffffffff, /* src_mask */
934 0xffffffff, /* dst_mask */
935 TRUE), /* pcrel_offset */
936
937 HOWTO (R_ARM_ALU_PC_G1, /* type */
938 0, /* rightshift */
939 2, /* size (0 = byte, 1 = short, 2 = long) */
940 32, /* bitsize */
941 TRUE, /* pc_relative */
942 0, /* bitpos */
943 complain_overflow_dont,/* complain_on_overflow */
944 bfd_elf_generic_reloc, /* special_function */
945 "R_ARM_ALU_PC_G1", /* name */
946 FALSE, /* partial_inplace */
947 0xffffffff, /* src_mask */
948 0xffffffff, /* dst_mask */
949 TRUE), /* pcrel_offset */
950
951 HOWTO (R_ARM_ALU_PC_G2, /* type */
952 0, /* rightshift */
953 2, /* size (0 = byte, 1 = short, 2 = long) */
954 32, /* bitsize */
955 TRUE, /* pc_relative */
956 0, /* bitpos */
957 complain_overflow_dont,/* complain_on_overflow */
958 bfd_elf_generic_reloc, /* special_function */
959 "R_ARM_ALU_PC_G2", /* name */
960 FALSE, /* partial_inplace */
961 0xffffffff, /* src_mask */
962 0xffffffff, /* dst_mask */
963 TRUE), /* pcrel_offset */
964
965 HOWTO (R_ARM_LDR_PC_G1, /* type */
966 0, /* rightshift */
967 2, /* size (0 = byte, 1 = short, 2 = long) */
968 32, /* bitsize */
969 TRUE, /* pc_relative */
970 0, /* bitpos */
971 complain_overflow_dont,/* complain_on_overflow */
972 bfd_elf_generic_reloc, /* special_function */
973 "R_ARM_LDR_PC_G1", /* name */
974 FALSE, /* partial_inplace */
975 0xffffffff, /* src_mask */
976 0xffffffff, /* dst_mask */
977 TRUE), /* pcrel_offset */
978
979 HOWTO (R_ARM_LDR_PC_G2, /* type */
980 0, /* rightshift */
981 2, /* size (0 = byte, 1 = short, 2 = long) */
982 32, /* bitsize */
983 TRUE, /* pc_relative */
984 0, /* bitpos */
985 complain_overflow_dont,/* complain_on_overflow */
986 bfd_elf_generic_reloc, /* special_function */
987 "R_ARM_LDR_PC_G2", /* name */
988 FALSE, /* partial_inplace */
989 0xffffffff, /* src_mask */
990 0xffffffff, /* dst_mask */
991 TRUE), /* pcrel_offset */
992
993 HOWTO (R_ARM_LDRS_PC_G0, /* type */
994 0, /* rightshift */
995 2, /* size (0 = byte, 1 = short, 2 = long) */
996 32, /* bitsize */
997 TRUE, /* pc_relative */
998 0, /* bitpos */
999 complain_overflow_dont,/* complain_on_overflow */
1000 bfd_elf_generic_reloc, /* special_function */
1001 "R_ARM_LDRS_PC_G0", /* name */
1002 FALSE, /* partial_inplace */
1003 0xffffffff, /* src_mask */
1004 0xffffffff, /* dst_mask */
1005 TRUE), /* pcrel_offset */
1006
1007 HOWTO (R_ARM_LDRS_PC_G1, /* type */
1008 0, /* rightshift */
1009 2, /* size (0 = byte, 1 = short, 2 = long) */
1010 32, /* bitsize */
1011 TRUE, /* pc_relative */
1012 0, /* bitpos */
1013 complain_overflow_dont,/* complain_on_overflow */
1014 bfd_elf_generic_reloc, /* special_function */
1015 "R_ARM_LDRS_PC_G1", /* name */
1016 FALSE, /* partial_inplace */
1017 0xffffffff, /* src_mask */
1018 0xffffffff, /* dst_mask */
1019 TRUE), /* pcrel_offset */
1020
1021 HOWTO (R_ARM_LDRS_PC_G2, /* type */
1022 0, /* rightshift */
1023 2, /* size (0 = byte, 1 = short, 2 = long) */
1024 32, /* bitsize */
1025 TRUE, /* pc_relative */
1026 0, /* bitpos */
1027 complain_overflow_dont,/* complain_on_overflow */
1028 bfd_elf_generic_reloc, /* special_function */
1029 "R_ARM_LDRS_PC_G2", /* name */
1030 FALSE, /* partial_inplace */
1031 0xffffffff, /* src_mask */
1032 0xffffffff, /* dst_mask */
1033 TRUE), /* pcrel_offset */
1034
1035 HOWTO (R_ARM_LDC_PC_G0, /* type */
1036 0, /* rightshift */
1037 2, /* size (0 = byte, 1 = short, 2 = long) */
1038 32, /* bitsize */
1039 TRUE, /* pc_relative */
1040 0, /* bitpos */
1041 complain_overflow_dont,/* complain_on_overflow */
1042 bfd_elf_generic_reloc, /* special_function */
1043 "R_ARM_LDC_PC_G0", /* name */
1044 FALSE, /* partial_inplace */
1045 0xffffffff, /* src_mask */
1046 0xffffffff, /* dst_mask */
1047 TRUE), /* pcrel_offset */
1048
1049 HOWTO (R_ARM_LDC_PC_G1, /* type */
1050 0, /* rightshift */
1051 2, /* size (0 = byte, 1 = short, 2 = long) */
1052 32, /* bitsize */
1053 TRUE, /* pc_relative */
1054 0, /* bitpos */
1055 complain_overflow_dont,/* complain_on_overflow */
1056 bfd_elf_generic_reloc, /* special_function */
1057 "R_ARM_LDC_PC_G1", /* name */
1058 FALSE, /* partial_inplace */
1059 0xffffffff, /* src_mask */
1060 0xffffffff, /* dst_mask */
1061 TRUE), /* pcrel_offset */
1062
1063 HOWTO (R_ARM_LDC_PC_G2, /* type */
1064 0, /* rightshift */
1065 2, /* size (0 = byte, 1 = short, 2 = long) */
1066 32, /* bitsize */
1067 TRUE, /* pc_relative */
1068 0, /* bitpos */
1069 complain_overflow_dont,/* complain_on_overflow */
1070 bfd_elf_generic_reloc, /* special_function */
1071 "R_ARM_LDC_PC_G2", /* name */
1072 FALSE, /* partial_inplace */
1073 0xffffffff, /* src_mask */
1074 0xffffffff, /* dst_mask */
1075 TRUE), /* pcrel_offset */
1076
1077 HOWTO (R_ARM_ALU_SB_G0_NC, /* type */
1078 0, /* rightshift */
1079 2, /* size (0 = byte, 1 = short, 2 = long) */
1080 32, /* bitsize */
1081 TRUE, /* pc_relative */
1082 0, /* bitpos */
1083 complain_overflow_dont,/* complain_on_overflow */
1084 bfd_elf_generic_reloc, /* special_function */
1085 "R_ARM_ALU_SB_G0_NC", /* name */
1086 FALSE, /* partial_inplace */
1087 0xffffffff, /* src_mask */
1088 0xffffffff, /* dst_mask */
1089 TRUE), /* pcrel_offset */
1090
1091 HOWTO (R_ARM_ALU_SB_G0, /* type */
1092 0, /* rightshift */
1093 2, /* size (0 = byte, 1 = short, 2 = long) */
1094 32, /* bitsize */
1095 TRUE, /* pc_relative */
1096 0, /* bitpos */
1097 complain_overflow_dont,/* complain_on_overflow */
1098 bfd_elf_generic_reloc, /* special_function */
1099 "R_ARM_ALU_SB_G0", /* name */
1100 FALSE, /* partial_inplace */
1101 0xffffffff, /* src_mask */
1102 0xffffffff, /* dst_mask */
1103 TRUE), /* pcrel_offset */
1104
1105 HOWTO (R_ARM_ALU_SB_G1_NC, /* type */
1106 0, /* rightshift */
1107 2, /* size (0 = byte, 1 = short, 2 = long) */
1108 32, /* bitsize */
1109 TRUE, /* pc_relative */
1110 0, /* bitpos */
1111 complain_overflow_dont,/* complain_on_overflow */
1112 bfd_elf_generic_reloc, /* special_function */
1113 "R_ARM_ALU_SB_G1_NC", /* name */
1114 FALSE, /* partial_inplace */
1115 0xffffffff, /* src_mask */
1116 0xffffffff, /* dst_mask */
1117 TRUE), /* pcrel_offset */
1118
1119 HOWTO (R_ARM_ALU_SB_G1, /* type */
1120 0, /* rightshift */
1121 2, /* size (0 = byte, 1 = short, 2 = long) */
1122 32, /* bitsize */
1123 TRUE, /* pc_relative */
1124 0, /* bitpos */
1125 complain_overflow_dont,/* complain_on_overflow */
1126 bfd_elf_generic_reloc, /* special_function */
1127 "R_ARM_ALU_SB_G1", /* name */
1128 FALSE, /* partial_inplace */
1129 0xffffffff, /* src_mask */
1130 0xffffffff, /* dst_mask */
1131 TRUE), /* pcrel_offset */
1132
1133 HOWTO (R_ARM_ALU_SB_G2, /* type */
1134 0, /* rightshift */
1135 2, /* size (0 = byte, 1 = short, 2 = long) */
1136 32, /* bitsize */
1137 TRUE, /* pc_relative */
1138 0, /* bitpos */
1139 complain_overflow_dont,/* complain_on_overflow */
1140 bfd_elf_generic_reloc, /* special_function */
1141 "R_ARM_ALU_SB_G2", /* name */
1142 FALSE, /* partial_inplace */
1143 0xffffffff, /* src_mask */
1144 0xffffffff, /* dst_mask */
1145 TRUE), /* pcrel_offset */
1146
1147 HOWTO (R_ARM_LDR_SB_G0, /* type */
1148 0, /* rightshift */
1149 2, /* size (0 = byte, 1 = short, 2 = long) */
1150 32, /* bitsize */
1151 TRUE, /* pc_relative */
1152 0, /* bitpos */
1153 complain_overflow_dont,/* complain_on_overflow */
1154 bfd_elf_generic_reloc, /* special_function */
1155 "R_ARM_LDR_SB_G0", /* name */
1156 FALSE, /* partial_inplace */
1157 0xffffffff, /* src_mask */
1158 0xffffffff, /* dst_mask */
1159 TRUE), /* pcrel_offset */
1160
1161 HOWTO (R_ARM_LDR_SB_G1, /* type */
1162 0, /* rightshift */
1163 2, /* size (0 = byte, 1 = short, 2 = long) */
1164 32, /* bitsize */
1165 TRUE, /* pc_relative */
1166 0, /* bitpos */
1167 complain_overflow_dont,/* complain_on_overflow */
1168 bfd_elf_generic_reloc, /* special_function */
1169 "R_ARM_LDR_SB_G1", /* name */
1170 FALSE, /* partial_inplace */
1171 0xffffffff, /* src_mask */
1172 0xffffffff, /* dst_mask */
1173 TRUE), /* pcrel_offset */
1174
1175 HOWTO (R_ARM_LDR_SB_G2, /* type */
1176 0, /* rightshift */
1177 2, /* size (0 = byte, 1 = short, 2 = long) */
1178 32, /* bitsize */
1179 TRUE, /* pc_relative */
1180 0, /* bitpos */
1181 complain_overflow_dont,/* complain_on_overflow */
1182 bfd_elf_generic_reloc, /* special_function */
1183 "R_ARM_LDR_SB_G2", /* name */
1184 FALSE, /* partial_inplace */
1185 0xffffffff, /* src_mask */
1186 0xffffffff, /* dst_mask */
1187 TRUE), /* pcrel_offset */
1188
1189 HOWTO (R_ARM_LDRS_SB_G0, /* type */
1190 0, /* rightshift */
1191 2, /* size (0 = byte, 1 = short, 2 = long) */
1192 32, /* bitsize */
1193 TRUE, /* pc_relative */
1194 0, /* bitpos */
1195 complain_overflow_dont,/* complain_on_overflow */
1196 bfd_elf_generic_reloc, /* special_function */
1197 "R_ARM_LDRS_SB_G0", /* name */
1198 FALSE, /* partial_inplace */
1199 0xffffffff, /* src_mask */
1200 0xffffffff, /* dst_mask */
1201 TRUE), /* pcrel_offset */
1202
1203 HOWTO (R_ARM_LDRS_SB_G1, /* type */
1204 0, /* rightshift */
1205 2, /* size (0 = byte, 1 = short, 2 = long) */
1206 32, /* bitsize */
1207 TRUE, /* pc_relative */
1208 0, /* bitpos */
1209 complain_overflow_dont,/* complain_on_overflow */
1210 bfd_elf_generic_reloc, /* special_function */
1211 "R_ARM_LDRS_SB_G1", /* name */
1212 FALSE, /* partial_inplace */
1213 0xffffffff, /* src_mask */
1214 0xffffffff, /* dst_mask */
1215 TRUE), /* pcrel_offset */
1216
1217 HOWTO (R_ARM_LDRS_SB_G2, /* type */
1218 0, /* rightshift */
1219 2, /* size (0 = byte, 1 = short, 2 = long) */
1220 32, /* bitsize */
1221 TRUE, /* pc_relative */
1222 0, /* bitpos */
1223 complain_overflow_dont,/* complain_on_overflow */
1224 bfd_elf_generic_reloc, /* special_function */
1225 "R_ARM_LDRS_SB_G2", /* name */
1226 FALSE, /* partial_inplace */
1227 0xffffffff, /* src_mask */
1228 0xffffffff, /* dst_mask */
1229 TRUE), /* pcrel_offset */
1230
1231 HOWTO (R_ARM_LDC_SB_G0, /* type */
1232 0, /* rightshift */
1233 2, /* size (0 = byte, 1 = short, 2 = long) */
1234 32, /* bitsize */
1235 TRUE, /* pc_relative */
1236 0, /* bitpos */
1237 complain_overflow_dont,/* complain_on_overflow */
1238 bfd_elf_generic_reloc, /* special_function */
1239 "R_ARM_LDC_SB_G0", /* name */
1240 FALSE, /* partial_inplace */
1241 0xffffffff, /* src_mask */
1242 0xffffffff, /* dst_mask */
1243 TRUE), /* pcrel_offset */
1244
1245 HOWTO (R_ARM_LDC_SB_G1, /* type */
1246 0, /* rightshift */
1247 2, /* size (0 = byte, 1 = short, 2 = long) */
1248 32, /* bitsize */
1249 TRUE, /* pc_relative */
1250 0, /* bitpos */
1251 complain_overflow_dont,/* complain_on_overflow */
1252 bfd_elf_generic_reloc, /* special_function */
1253 "R_ARM_LDC_SB_G1", /* name */
1254 FALSE, /* partial_inplace */
1255 0xffffffff, /* src_mask */
1256 0xffffffff, /* dst_mask */
1257 TRUE), /* pcrel_offset */
1258
1259 HOWTO (R_ARM_LDC_SB_G2, /* type */
1260 0, /* rightshift */
1261 2, /* size (0 = byte, 1 = short, 2 = long) */
1262 32, /* bitsize */
1263 TRUE, /* pc_relative */
1264 0, /* bitpos */
1265 complain_overflow_dont,/* complain_on_overflow */
1266 bfd_elf_generic_reloc, /* special_function */
1267 "R_ARM_LDC_SB_G2", /* name */
1268 FALSE, /* partial_inplace */
1269 0xffffffff, /* src_mask */
1270 0xffffffff, /* dst_mask */
1271 TRUE), /* pcrel_offset */
1272
1273 /* End of group relocations. */
c19d1205 1274
c19d1205
ZW		 1275 HOWTO (R_ARM_MOVW_BREL_NC, /* type */
1276 0, /* rightshift */
1277 2, /* size (0 = byte, 1 = short, 2 = long) */
1278 16, /* bitsize */
1279 FALSE, /* pc_relative */
1280 0, /* bitpos */
1281 complain_overflow_dont,/* complain_on_overflow */
1282 bfd_elf_generic_reloc, /* special_function */
1283 "R_ARM_MOVW_BREL_NC", /* name */
1284 FALSE, /* partial_inplace */
1285 0x0000ffff, /* src_mask */
1286 0x0000ffff, /* dst_mask */
1287 FALSE), /* pcrel_offset */
1288
1289 HOWTO (R_ARM_MOVT_BREL, /* type */
1290 0, /* rightshift */
1291 2, /* size (0 = byte, 1 = short, 2 = long) */
1292 16, /* bitsize */
1293 FALSE, /* pc_relative */
1294 0, /* bitpos */
1295 complain_overflow_bitfield,/* complain_on_overflow */
1296 bfd_elf_generic_reloc, /* special_function */
1297 "R_ARM_MOVT_BREL", /* name */
1298 FALSE, /* partial_inplace */
1299 0x0000ffff, /* src_mask */
1300 0x0000ffff, /* dst_mask */
1301 FALSE), /* pcrel_offset */
1302
1303 HOWTO (R_ARM_MOVW_BREL, /* type */
1304 0, /* rightshift */
1305 2, /* size (0 = byte, 1 = short, 2 = long) */
1306 16, /* bitsize */
1307 FALSE, /* pc_relative */
1308 0, /* bitpos */
1309 complain_overflow_dont,/* complain_on_overflow */
1310 bfd_elf_generic_reloc, /* special_function */
1311 "R_ARM_MOVW_BREL", /* name */
1312 FALSE, /* partial_inplace */
1313 0x0000ffff, /* src_mask */
1314 0x0000ffff, /* dst_mask */
1315 FALSE), /* pcrel_offset */
1316
1317 HOWTO (R_ARM_THM_MOVW_BREL_NC,/* type */
1318 0, /* rightshift */
1319 2, /* size (0 = byte, 1 = short, 2 = long) */
1320 16, /* bitsize */
1321 FALSE, /* pc_relative */
1322 0, /* bitpos */
1323 complain_overflow_dont,/* complain_on_overflow */
1324 bfd_elf_generic_reloc, /* special_function */
1325 "R_ARM_THM_MOVW_BREL_NC",/* name */
1326 FALSE, /* partial_inplace */
1327 0x040f70ff, /* src_mask */
1328 0x040f70ff, /* dst_mask */
1329 FALSE), /* pcrel_offset */
1330
1331 HOWTO (R_ARM_THM_MOVT_BREL, /* type */
1332 0, /* rightshift */
1333 2, /* size (0 = byte, 1 = short, 2 = long) */
1334 16, /* bitsize */
1335 FALSE, /* pc_relative */
1336 0, /* bitpos */
1337 complain_overflow_bitfield,/* complain_on_overflow */
1338 bfd_elf_generic_reloc, /* special_function */
1339 "R_ARM_THM_MOVT_BREL", /* name */
1340 FALSE, /* partial_inplace */
1341 0x040f70ff, /* src_mask */
1342 0x040f70ff, /* dst_mask */
1343 FALSE), /* pcrel_offset */
1344
1345 HOWTO (R_ARM_THM_MOVW_BREL, /* type */
1346 0, /* rightshift */
1347 2, /* size (0 = byte, 1 = short, 2 = long) */
1348 16, /* bitsize */
1349 FALSE, /* pc_relative */
1350 0, /* bitpos */
1351 complain_overflow_dont,/* complain_on_overflow */
1352 bfd_elf_generic_reloc, /* special_function */
1353 "R_ARM_THM_MOVW_BREL", /* name */
1354 FALSE, /* partial_inplace */
1355 0x040f70ff, /* src_mask */
1356 0x040f70ff, /* dst_mask */
1357 FALSE), /* pcrel_offset */
1358
0855e32b
NS		 1359 HOWTO (R_ARM_TLS_GOTDESC, /* type */
1360 0, /* rightshift */
1361 2, /* size (0 = byte, 1 = short, 2 = long) */
1362 32, /* bitsize */
1363 FALSE, /* pc_relative */
1364 0, /* bitpos */
1365 complain_overflow_bitfield,/* complain_on_overflow */
1366 NULL, /* special_function */
1367 "R_ARM_TLS_GOTDESC", /* name */
1368 TRUE, /* partial_inplace */
1369 0xffffffff, /* src_mask */
1370 0xffffffff, /* dst_mask */
1371 FALSE), /* pcrel_offset */
1372
1373 HOWTO (R_ARM_TLS_CALL, /* type */
1374 0, /* rightshift */
1375 2, /* size (0 = byte, 1 = short, 2 = long) */
1376 24, /* bitsize */
1377 FALSE, /* pc_relative */
1378 0, /* bitpos */
1379 complain_overflow_dont,/* complain_on_overflow */
1380 bfd_elf_generic_reloc, /* special_function */
1381 "R_ARM_TLS_CALL", /* name */
1382 FALSE, /* partial_inplace */
1383 0x00ffffff, /* src_mask */
1384 0x00ffffff, /* dst_mask */
1385 FALSE), /* pcrel_offset */
1386
1387 HOWTO (R_ARM_TLS_DESCSEQ, /* type */
1388 0, /* rightshift */
1389 2, /* size (0 = byte, 1 = short, 2 = long) */
1390 0, /* bitsize */
1391 FALSE, /* pc_relative */
1392 0, /* bitpos */
1393 complain_overflow_bitfield,/* complain_on_overflow */
1394 bfd_elf_generic_reloc, /* special_function */
1395 "R_ARM_TLS_DESCSEQ", /* name */
1396 FALSE, /* partial_inplace */
1397 0x00000000, /* src_mask */
1398 0x00000000, /* dst_mask */
1399 FALSE), /* pcrel_offset */
1400
1401 HOWTO (R_ARM_THM_TLS_CALL, /* type */
1402 0, /* rightshift */
1403 2, /* size (0 = byte, 1 = short, 2 = long) */
1404 24, /* bitsize */
1405 FALSE, /* pc_relative */
1406 0, /* bitpos */
1407 complain_overflow_dont,/* complain_on_overflow */
1408 bfd_elf_generic_reloc, /* special_function */
1409 "R_ARM_THM_TLS_CALL", /* name */
1410 FALSE, /* partial_inplace */
1411 0x07ff07ff, /* src_mask */
1412 0x07ff07ff, /* dst_mask */
1413 FALSE), /* pcrel_offset */
c19d1205
ZW		 1414
1415 HOWTO (R_ARM_PLT32_ABS, /* type */
1416 0, /* rightshift */
1417 2, /* size (0 = byte, 1 = short, 2 = long) */
1418 32, /* bitsize */
1419 FALSE, /* pc_relative */
1420 0, /* bitpos */
1421 complain_overflow_dont,/* complain_on_overflow */
1422 bfd_elf_generic_reloc, /* special_function */
1423 "R_ARM_PLT32_ABS", /* name */
1424 FALSE, /* partial_inplace */
1425 0xffffffff, /* src_mask */
1426 0xffffffff, /* dst_mask */
1427 FALSE), /* pcrel_offset */
1428
1429 HOWTO (R_ARM_GOT_ABS, /* type */
1430 0, /* rightshift */
1431 2, /* size (0 = byte, 1 = short, 2 = long) */
1432 32, /* bitsize */
1433 FALSE, /* pc_relative */
1434 0, /* bitpos */
1435 complain_overflow_dont,/* complain_on_overflow */
1436 bfd_elf_generic_reloc, /* special_function */
1437 "R_ARM_GOT_ABS", /* name */
1438 FALSE, /* partial_inplace */
1439 0xffffffff, /* src_mask */
1440 0xffffffff, /* dst_mask */
1441 FALSE), /* pcrel_offset */
1442
1443 HOWTO (R_ARM_GOT_PREL, /* type */
1444 0, /* rightshift */
1445 2, /* size (0 = byte, 1 = short, 2 = long) */
1446 32, /* bitsize */
1447 TRUE, /* pc_relative */
1448 0, /* bitpos */
1449 complain_overflow_dont, /* complain_on_overflow */
1450 bfd_elf_generic_reloc, /* special_function */
1451 "R_ARM_GOT_PREL", /* name */
1452 FALSE, /* partial_inplace */
1453 0xffffffff, /* src_mask */
1454 0xffffffff, /* dst_mask */
1455 TRUE), /* pcrel_offset */
1456
1457 HOWTO (R_ARM_GOT_BREL12, /* type */
1458 0, /* rightshift */
1459 2, /* size (0 = byte, 1 = short, 2 = long) */
1460 12, /* bitsize */
1461 FALSE, /* pc_relative */
1462 0, /* bitpos */
1463 complain_overflow_bitfield,/* complain_on_overflow */
1464 bfd_elf_generic_reloc, /* special_function */
1465 "R_ARM_GOT_BREL12", /* name */
1466 FALSE, /* partial_inplace */
1467 0x00000fff, /* src_mask */
1468 0x00000fff, /* dst_mask */
1469 FALSE), /* pcrel_offset */
1470
1471 HOWTO (R_ARM_GOTOFF12, /* type */
1472 0, /* rightshift */
1473 2, /* size (0 = byte, 1 = short, 2 = long) */
1474 12, /* bitsize */
1475 FALSE, /* pc_relative */
1476 0, /* bitpos */
1477 complain_overflow_bitfield,/* complain_on_overflow */
1478 bfd_elf_generic_reloc, /* special_function */
1479 "R_ARM_GOTOFF12", /* name */
1480 FALSE, /* partial_inplace */
1481 0x00000fff, /* src_mask */
1482 0x00000fff, /* dst_mask */
1483 FALSE), /* pcrel_offset */
1484
1485 EMPTY_HOWTO (R_ARM_GOTRELAX), /* reserved for future GOT-load optimizations */
1486
1487 /* GNU extension to record C++ vtable member usage */
1488 HOWTO (R_ARM_GNU_VTENTRY, /* type */
99059e56
RM		 1489 0, /* rightshift */
1490 2, /* size (0 = byte, 1 = short, 2 = long) */
1491 0, /* bitsize */
1492 FALSE, /* pc_relative */
1493 0, /* bitpos */
1494 complain_overflow_dont, /* complain_on_overflow */
1495 _bfd_elf_rel_vtable_reloc_fn, /* special_function */
1496 "R_ARM_GNU_VTENTRY", /* name */
1497 FALSE, /* partial_inplace */
1498 0, /* src_mask */
1499 0, /* dst_mask */
1500 FALSE), /* pcrel_offset */
c19d1205
ZW		 1501
1502 /* GNU extension to record C++ vtable hierarchy */
1503 HOWTO (R_ARM_GNU_VTINHERIT, /* type */
99059e56
RM		 1504 0, /* rightshift */
1505 2, /* size (0 = byte, 1 = short, 2 = long) */
1506 0, /* bitsize */
1507 FALSE, /* pc_relative */
1508 0, /* bitpos */
1509 complain_overflow_dont, /* complain_on_overflow */
1510 NULL, /* special_function */
1511 "R_ARM_GNU_VTINHERIT", /* name */
1512 FALSE, /* partial_inplace */
1513 0, /* src_mask */
1514 0, /* dst_mask */
1515 FALSE), /* pcrel_offset */
c19d1205
ZW		 1516
1517 HOWTO (R_ARM_THM_JUMP11, /* type */
1518 1, /* rightshift */
1519 1, /* size (0 = byte, 1 = short, 2 = long) */
1520 11, /* bitsize */
1521 TRUE, /* pc_relative */
1522 0, /* bitpos */
1523 complain_overflow_signed, /* complain_on_overflow */
1524 bfd_elf_generic_reloc, /* special_function */
1525 "R_ARM_THM_JUMP11", /* name */
1526 FALSE, /* partial_inplace */
1527 0x000007ff, /* src_mask */
1528 0x000007ff, /* dst_mask */
1529 TRUE), /* pcrel_offset */
1530
1531 HOWTO (R_ARM_THM_JUMP8, /* type */
1532 1, /* rightshift */
1533 1, /* size (0 = byte, 1 = short, 2 = long) */
1534 8, /* bitsize */
1535 TRUE, /* pc_relative */
1536 0, /* bitpos */
1537 complain_overflow_signed, /* complain_on_overflow */
1538 bfd_elf_generic_reloc, /* special_function */
1539 "R_ARM_THM_JUMP8", /* name */
1540 FALSE, /* partial_inplace */
1541 0x000000ff, /* src_mask */
1542 0x000000ff, /* dst_mask */
1543 TRUE), /* pcrel_offset */
ba93b8ac 1544
c19d1205
ZW		 1545 /* TLS relocations */
1546 HOWTO (R_ARM_TLS_GD32, /* type */
99059e56
RM		 1547 0, /* rightshift */
1548 2, /* size (0 = byte, 1 = short, 2 = long) */
1549 32, /* bitsize */
1550 FALSE, /* pc_relative */
1551 0, /* bitpos */
1552 complain_overflow_bitfield,/* complain_on_overflow */
1553 NULL, /* special_function */
1554 "R_ARM_TLS_GD32", /* name */
1555 TRUE, /* partial_inplace */
1556 0xffffffff, /* src_mask */
1557 0xffffffff, /* dst_mask */
1558 FALSE), /* pcrel_offset */
ba93b8ac 1559
ba93b8ac 1560 HOWTO (R_ARM_TLS_LDM32, /* type */
99059e56
RM		 1561 0, /* rightshift */
1562 2, /* size (0 = byte, 1 = short, 2 = long) */
1563 32, /* bitsize */
1564 FALSE, /* pc_relative */
1565 0, /* bitpos */
1566 complain_overflow_bitfield,/* complain_on_overflow */
1567 bfd_elf_generic_reloc, /* special_function */
1568 "R_ARM_TLS_LDM32", /* name */
1569 TRUE, /* partial_inplace */
1570 0xffffffff, /* src_mask */
1571 0xffffffff, /* dst_mask */
1572 FALSE), /* pcrel_offset */
ba93b8ac 1573
c19d1205 1574 HOWTO (R_ARM_TLS_LDO32, /* type */
99059e56
RM		 1575 0, /* rightshift */
1576 2, /* size (0 = byte, 1 = short, 2 = long) */
1577 32, /* bitsize */
1578 FALSE, /* pc_relative */
1579 0, /* bitpos */
1580 complain_overflow_bitfield,/* complain_on_overflow */
1581 bfd_elf_generic_reloc, /* special_function */
1582 "R_ARM_TLS_LDO32", /* name */
1583 TRUE, /* partial_inplace */
1584 0xffffffff, /* src_mask */
1585 0xffffffff, /* dst_mask */
1586 FALSE), /* pcrel_offset */
ba93b8ac 1587
ba93b8ac 1588 HOWTO (R_ARM_TLS_IE32, /* type */
99059e56
RM		 1589 0, /* rightshift */
1590 2, /* size (0 = byte, 1 = short, 2 = long) */
1591 32, /* bitsize */
1592 FALSE, /* pc_relative */
1593 0, /* bitpos */
1594 complain_overflow_bitfield,/* complain_on_overflow */
1595 NULL, /* special_function */
1596 "R_ARM_TLS_IE32", /* name */
1597 TRUE, /* partial_inplace */
1598 0xffffffff, /* src_mask */
1599 0xffffffff, /* dst_mask */
1600 FALSE), /* pcrel_offset */
7f266840 1601
c19d1205 1602 HOWTO (R_ARM_TLS_LE32, /* type */
99059e56
RM		 1603 0, /* rightshift */
1604 2, /* size (0 = byte, 1 = short, 2 = long) */
1605 32, /* bitsize */
1606 FALSE, /* pc_relative */
1607 0, /* bitpos */
1608 complain_overflow_bitfield,/* complain_on_overflow */
75c11999 1609 NULL, /* special_function */
99059e56
RM		 1610 "R_ARM_TLS_LE32", /* name */
1611 TRUE, /* partial_inplace */
1612 0xffffffff, /* src_mask */
1613 0xffffffff, /* dst_mask */
1614 FALSE), /* pcrel_offset */
7f266840 1615
c19d1205
ZW		 1616 HOWTO (R_ARM_TLS_LDO12, /* type */
1617 0, /* rightshift */
1618 2, /* size (0 = byte, 1 = short, 2 = long) */
1619 12, /* bitsize */
1620 FALSE, /* pc_relative */
7f266840 1621 0, /* bitpos */
c19d1205 1622 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1623 bfd_elf_generic_reloc, /* special_function */
c19d1205 1624 "R_ARM_TLS_LDO12", /* name */
7f266840 1625 FALSE, /* partial_inplace */
c19d1205
ZW		 1626 0x00000fff, /* src_mask */
1627 0x00000fff, /* dst_mask */
1628 FALSE), /* pcrel_offset */
7f266840 1629
c19d1205
ZW		 1630 HOWTO (R_ARM_TLS_LE12, /* type */
1631 0, /* rightshift */
1632 2, /* size (0 = byte, 1 = short, 2 = long) */
1633 12, /* bitsize */
1634 FALSE, /* pc_relative */
7f266840 1635 0, /* bitpos */
c19d1205 1636 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1637 bfd_elf_generic_reloc, /* special_function */
c19d1205 1638 "R_ARM_TLS_LE12", /* name */
7f266840 1639 FALSE, /* partial_inplace */
c19d1205
ZW		 1640 0x00000fff, /* src_mask */
1641 0x00000fff, /* dst_mask */
1642 FALSE), /* pcrel_offset */
7f266840 1643
c19d1205 1644 HOWTO (R_ARM_TLS_IE12GP, /* type */
7f266840
DJ		 1645 0, /* rightshift */
1646 2, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 1647 12, /* bitsize */
1648 FALSE, /* pc_relative */
7f266840 1649 0, /* bitpos */
c19d1205 1650 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1651 bfd_elf_generic_reloc, /* special_function */
c19d1205 1652 "R_ARM_TLS_IE12GP", /* name */
7f266840 1653 FALSE, /* partial_inplace */
c19d1205
ZW		 1654 0x00000fff, /* src_mask */
1655 0x00000fff, /* dst_mask */
1656 FALSE), /* pcrel_offset */
0855e32b 1657
34e77a92 1658 /* 112-127 private relocations. */
0855e32b
NS		 1659 EMPTY_HOWTO (112),
1660 EMPTY_HOWTO (113),
1661 EMPTY_HOWTO (114),
1662 EMPTY_HOWTO (115),
1663 EMPTY_HOWTO (116),
1664 EMPTY_HOWTO (117),
1665 EMPTY_HOWTO (118),
1666 EMPTY_HOWTO (119),
1667 EMPTY_HOWTO (120),
1668 EMPTY_HOWTO (121),
1669 EMPTY_HOWTO (122),
1670 EMPTY_HOWTO (123),
1671 EMPTY_HOWTO (124),
1672 EMPTY_HOWTO (125),
1673 EMPTY_HOWTO (126),
1674 EMPTY_HOWTO (127),
34e77a92
RS		 1675
1676 /* R_ARM_ME_TOO, obsolete. */
0855e32b
NS		 1677 EMPTY_HOWTO (128),
1678
1679 HOWTO (R_ARM_THM_TLS_DESCSEQ, /* type */
1680 0, /* rightshift */
1681 1, /* size (0 = byte, 1 = short, 2 = long) */
1682 0, /* bitsize */
1683 FALSE, /* pc_relative */
1684 0, /* bitpos */
1685 complain_overflow_bitfield,/* complain_on_overflow */
1686 bfd_elf_generic_reloc, /* special_function */
1687 "R_ARM_THM_TLS_DESCSEQ",/* name */
1688 FALSE, /* partial_inplace */
1689 0x00000000, /* src_mask */
1690 0x00000000, /* dst_mask */
1691 FALSE), /* pcrel_offset */
72d98d16
MG		 1692 EMPTY_HOWTO (130),
1693 EMPTY_HOWTO (131),
1694 HOWTO (R_ARM_THM_ALU_ABS_G0_NC,/* type. */
1695 0, /* rightshift. */
1696 1, /* size (0 = byte, 1 = short, 2 = long). */
1697 16, /* bitsize. */
1698 FALSE, /* pc_relative. */
1699 0, /* bitpos. */
1700 complain_overflow_bitfield,/* complain_on_overflow. */
1701 bfd_elf_generic_reloc, /* special_function. */
1702 "R_ARM_THM_ALU_ABS_G0_NC",/* name. */
1703 FALSE, /* partial_inplace. */
1704 0x00000000, /* src_mask. */
1705 0x00000000, /* dst_mask. */
1706 FALSE), /* pcrel_offset. */
1707 HOWTO (R_ARM_THM_ALU_ABS_G1_NC,/* type. */
1708 0, /* rightshift. */
1709 1, /* size (0 = byte, 1 = short, 2 = long). */
1710 16, /* bitsize. */
1711 FALSE, /* pc_relative. */
1712 0, /* bitpos. */
1713 complain_overflow_bitfield,/* complain_on_overflow. */
1714 bfd_elf_generic_reloc, /* special_function. */
1715 "R_ARM_THM_ALU_ABS_G1_NC",/* name. */
1716 FALSE, /* partial_inplace. */
1717 0x00000000, /* src_mask. */
1718 0x00000000, /* dst_mask. */
1719 FALSE), /* pcrel_offset. */
1720 HOWTO (R_ARM_THM_ALU_ABS_G2_NC,/* type. */
1721 0, /* rightshift. */
1722 1, /* size (0 = byte, 1 = short, 2 = long). */
1723 16, /* bitsize. */
1724 FALSE, /* pc_relative. */
1725 0, /* bitpos. */
1726 complain_overflow_bitfield,/* complain_on_overflow. */
1727 bfd_elf_generic_reloc, /* special_function. */
1728 "R_ARM_THM_ALU_ABS_G2_NC",/* name. */
1729 FALSE, /* partial_inplace. */
1730 0x00000000, /* src_mask. */
1731 0x00000000, /* dst_mask. */
1732 FALSE), /* pcrel_offset. */
1733 HOWTO (R_ARM_THM_ALU_ABS_G3_NC,/* type. */
1734 0, /* rightshift. */
1735 1, /* size (0 = byte, 1 = short, 2 = long). */
1736 16, /* bitsize. */
1737 FALSE, /* pc_relative. */
1738 0, /* bitpos. */
1739 complain_overflow_bitfield,/* complain_on_overflow. */
1740 bfd_elf_generic_reloc, /* special_function. */
1741 "R_ARM_THM_ALU_ABS_G3_NC",/* name. */
1742 FALSE, /* partial_inplace. */
1743 0x00000000, /* src_mask. */
1744 0x00000000, /* dst_mask. */
1745 FALSE), /* pcrel_offset. */
c19d1205
ZW		 1746};
1747
34e77a92
RS		 1748/* 160 onwards: */
1749static reloc_howto_type elf32_arm_howto_table_2[1] =
1750{
1751 HOWTO (R_ARM_IRELATIVE, /* type */
99059e56
RM		 1752 0, /* rightshift */
1753 2, /* size (0 = byte, 1 = short, 2 = long) */
1754 32, /* bitsize */
1755 FALSE, /* pc_relative */
1756 0, /* bitpos */
1757 complain_overflow_bitfield,/* complain_on_overflow */
1758 bfd_elf_generic_reloc, /* special_function */
1759 "R_ARM_IRELATIVE", /* name */
1760 TRUE, /* partial_inplace */
1761 0xffffffff, /* src_mask */
1762 0xffffffff, /* dst_mask */
1763 FALSE) /* pcrel_offset */
34e77a92 1764};
c19d1205 1765
34e77a92
RS		 1766/* 249-255 extended, currently unused, relocations: */
1767static reloc_howto_type elf32_arm_howto_table_3[4] =
7f266840
DJ		 1768{
1769 HOWTO (R_ARM_RREL32, /* type */
1770 0, /* rightshift */
1771 0, /* size (0 = byte, 1 = short, 2 = long) */
1772 0, /* bitsize */
1773 FALSE, /* pc_relative */
1774 0, /* bitpos */
1775 complain_overflow_dont,/* complain_on_overflow */
1776 bfd_elf_generic_reloc, /* special_function */
1777 "R_ARM_RREL32", /* name */
1778 FALSE, /* partial_inplace */
1779 0, /* src_mask */
1780 0, /* dst_mask */
1781 FALSE), /* pcrel_offset */
1782
1783 HOWTO (R_ARM_RABS32, /* type */
1784 0, /* rightshift */
1785 0, /* size (0 = byte, 1 = short, 2 = long) */
1786 0, /* bitsize */
1787 FALSE, /* pc_relative */
1788 0, /* bitpos */
1789 complain_overflow_dont,/* complain_on_overflow */
1790 bfd_elf_generic_reloc, /* special_function */
1791 "R_ARM_RABS32", /* name */
1792 FALSE, /* partial_inplace */
1793 0, /* src_mask */
1794 0, /* dst_mask */
1795 FALSE), /* pcrel_offset */
1796
1797 HOWTO (R_ARM_RPC24, /* type */
1798 0, /* rightshift */
1799 0, /* size (0 = byte, 1 = short, 2 = long) */
1800 0, /* bitsize */
1801 FALSE, /* pc_relative */
1802 0, /* bitpos */
1803 complain_overflow_dont,/* complain_on_overflow */
1804 bfd_elf_generic_reloc, /* special_function */
1805 "R_ARM_RPC24", /* name */
1806 FALSE, /* partial_inplace */
1807 0, /* src_mask */
1808 0, /* dst_mask */
1809 FALSE), /* pcrel_offset */
1810
1811 HOWTO (R_ARM_RBASE, /* type */
1812 0, /* rightshift */
1813 0, /* size (0 = byte, 1 = short, 2 = long) */
1814 0, /* bitsize */
1815 FALSE, /* pc_relative */
1816 0, /* bitpos */
1817 complain_overflow_dont,/* complain_on_overflow */
1818 bfd_elf_generic_reloc, /* special_function */
1819 "R_ARM_RBASE", /* name */
1820 FALSE, /* partial_inplace */
1821 0, /* src_mask */
1822 0, /* dst_mask */
1823 FALSE) /* pcrel_offset */
1824};
1825
1826static reloc_howto_type *
1827elf32_arm_howto_from_type (unsigned int r_type)
1828{
906e58ca 1829 if (r_type < ARRAY_SIZE (elf32_arm_howto_table_1))
c19d1205 1830 return &elf32_arm_howto_table_1[r_type];
ba93b8ac 1831
34e77a92
RS		 1832 if (r_type == R_ARM_IRELATIVE)
1833 return &elf32_arm_howto_table_2[r_type - R_ARM_IRELATIVE];
1834
c19d1205 1835 if (r_type >= R_ARM_RREL32
34e77a92
RS		 1836 && r_type < R_ARM_RREL32 + ARRAY_SIZE (elf32_arm_howto_table_3))
1837 return &elf32_arm_howto_table_3[r_type - R_ARM_RREL32];
7f266840 1838
c19d1205 1839 return NULL;
7f266840
DJ		 1840}
1841
1842static void
1843elf32_arm_info_to_howto (bfd * abfd ATTRIBUTE_UNUSED, arelent * bfd_reloc,
1844 Elf_Internal_Rela * elf_reloc)
1845{
1846 unsigned int r_type;
1847
1848 r_type = ELF32_R_TYPE (elf_reloc->r_info);
1849 bfd_reloc->howto = elf32_arm_howto_from_type (r_type);
1850}
1851
1852struct elf32_arm_reloc_map
1853 {
1854 bfd_reloc_code_real_type bfd_reloc_val;
1855 unsigned char elf_reloc_val;
1856 };
1857
1858/* All entries in this list must also be present in elf32_arm_howto_table. */
1859static const struct elf32_arm_reloc_map elf32_arm_reloc_map[] =
1860 {
1861 {BFD_RELOC_NONE, R_ARM_NONE},
1862 {BFD_RELOC_ARM_PCREL_BRANCH, R_ARM_PC24},
39b41c9c
PB		 1863 {BFD_RELOC_ARM_PCREL_CALL, R_ARM_CALL},
1864 {BFD_RELOC_ARM_PCREL_JUMP, R_ARM_JUMP24},
7f266840
DJ		 1865 {BFD_RELOC_ARM_PCREL_BLX, R_ARM_XPC25},
1866 {BFD_RELOC_THUMB_PCREL_BLX, R_ARM_THM_XPC22},
1867 {BFD_RELOC_32, R_ARM_ABS32},
1868 {BFD_RELOC_32_PCREL, R_ARM_REL32},
1869 {BFD_RELOC_8, R_ARM_ABS8},
1870 {BFD_RELOC_16, R_ARM_ABS16},
1871 {BFD_RELOC_ARM_OFFSET_IMM, R_ARM_ABS12},
1872 {BFD_RELOC_ARM_THUMB_OFFSET, R_ARM_THM_ABS5},
c19d1205
ZW		 1873 {BFD_RELOC_THUMB_PCREL_BRANCH25, R_ARM_THM_JUMP24},
1874 {BFD_RELOC_THUMB_PCREL_BRANCH23, R_ARM_THM_CALL},
1875 {BFD_RELOC_THUMB_PCREL_BRANCH12, R_ARM_THM_JUMP11},
1876 {BFD_RELOC_THUMB_PCREL_BRANCH20, R_ARM_THM_JUMP19},
1877 {BFD_RELOC_THUMB_PCREL_BRANCH9, R_ARM_THM_JUMP8},
1878 {BFD_RELOC_THUMB_PCREL_BRANCH7, R_ARM_THM_JUMP6},
7f266840
DJ		 1879 {BFD_RELOC_ARM_GLOB_DAT, R_ARM_GLOB_DAT},
1880 {BFD_RELOC_ARM_JUMP_SLOT, R_ARM_JUMP_SLOT},
1881 {BFD_RELOC_ARM_RELATIVE, R_ARM_RELATIVE},
c19d1205 1882 {BFD_RELOC_ARM_GOTOFF, R_ARM_GOTOFF32},
7f266840 1883 {BFD_RELOC_ARM_GOTPC, R_ARM_GOTPC},
b43420e6 1884 {BFD_RELOC_ARM_GOT_PREL, R_ARM_GOT_PREL},
7f266840
DJ		 1885 {BFD_RELOC_ARM_GOT32, R_ARM_GOT32},
1886 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
1887 {BFD_RELOC_ARM_TARGET1, R_ARM_TARGET1},
1888 {BFD_RELOC_ARM_ROSEGREL32, R_ARM_ROSEGREL32},
1889 {BFD_RELOC_ARM_SBREL32, R_ARM_SBREL32},
1890 {BFD_RELOC_ARM_PREL31, R_ARM_PREL31},
ba93b8ac
DJ		 1891 {BFD_RELOC_ARM_TARGET2, R_ARM_TARGET2},
1892 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
0855e32b
NS		 1893 {BFD_RELOC_ARM_TLS_GOTDESC, R_ARM_TLS_GOTDESC},
1894 {BFD_RELOC_ARM_TLS_CALL, R_ARM_TLS_CALL},
1895 {BFD_RELOC_ARM_THM_TLS_CALL, R_ARM_THM_TLS_CALL},
1896 {BFD_RELOC_ARM_TLS_DESCSEQ, R_ARM_TLS_DESCSEQ},
1897 {BFD_RELOC_ARM_THM_TLS_DESCSEQ, R_ARM_THM_TLS_DESCSEQ},
1898 {BFD_RELOC_ARM_TLS_DESC, R_ARM_TLS_DESC},
ba93b8ac
DJ		 1899 {BFD_RELOC_ARM_TLS_GD32, R_ARM_TLS_GD32},
1900 {BFD_RELOC_ARM_TLS_LDO32, R_ARM_TLS_LDO32},
1901 {BFD_RELOC_ARM_TLS_LDM32, R_ARM_TLS_LDM32},
1902 {BFD_RELOC_ARM_TLS_DTPMOD32, R_ARM_TLS_DTPMOD32},
1903 {BFD_RELOC_ARM_TLS_DTPOFF32, R_ARM_TLS_DTPOFF32},
1904 {BFD_RELOC_ARM_TLS_TPOFF32, R_ARM_TLS_TPOFF32},
1905 {BFD_RELOC_ARM_TLS_IE32, R_ARM_TLS_IE32},
1906 {BFD_RELOC_ARM_TLS_LE32, R_ARM_TLS_LE32},
34e77a92 1907 {BFD_RELOC_ARM_IRELATIVE, R_ARM_IRELATIVE},
c19d1205
ZW		 1908 {BFD_RELOC_VTABLE_INHERIT, R_ARM_GNU_VTINHERIT},
1909 {BFD_RELOC_VTABLE_ENTRY, R_ARM_GNU_VTENTRY},
b6895b4f
PB		 1910 {BFD_RELOC_ARM_MOVW, R_ARM_MOVW_ABS_NC},
1911 {BFD_RELOC_ARM_MOVT, R_ARM_MOVT_ABS},
1912 {BFD_RELOC_ARM_MOVW_PCREL, R_ARM_MOVW_PREL_NC},
1913 {BFD_RELOC_ARM_MOVT_PCREL, R_ARM_MOVT_PREL},
1914 {BFD_RELOC_ARM_THUMB_MOVW, R_ARM_THM_MOVW_ABS_NC},
1915 {BFD_RELOC_ARM_THUMB_MOVT, R_ARM_THM_MOVT_ABS},
1916 {BFD_RELOC_ARM_THUMB_MOVW_PCREL, R_ARM_THM_MOVW_PREL_NC},
1917 {BFD_RELOC_ARM_THUMB_MOVT_PCREL, R_ARM_THM_MOVT_PREL},
4962c51a
MS		 1918 {BFD_RELOC_ARM_ALU_PC_G0_NC, R_ARM_ALU_PC_G0_NC},
1919 {BFD_RELOC_ARM_ALU_PC_G0, R_ARM_ALU_PC_G0},
1920 {BFD_RELOC_ARM_ALU_PC_G1_NC, R_ARM_ALU_PC_G1_NC},
1921 {BFD_RELOC_ARM_ALU_PC_G1, R_ARM_ALU_PC_G1},
1922 {BFD_RELOC_ARM_ALU_PC_G2, R_ARM_ALU_PC_G2},
1923 {BFD_RELOC_ARM_LDR_PC_G0, R_ARM_LDR_PC_G0},
1924 {BFD_RELOC_ARM_LDR_PC_G1, R_ARM_LDR_PC_G1},
1925 {BFD_RELOC_ARM_LDR_PC_G2, R_ARM_LDR_PC_G2},
1926 {BFD_RELOC_ARM_LDRS_PC_G0, R_ARM_LDRS_PC_G0},
1927 {BFD_RELOC_ARM_LDRS_PC_G1, R_ARM_LDRS_PC_G1},
1928 {BFD_RELOC_ARM_LDRS_PC_G2, R_ARM_LDRS_PC_G2},
1929 {BFD_RELOC_ARM_LDC_PC_G0, R_ARM_LDC_PC_G0},
1930 {BFD_RELOC_ARM_LDC_PC_G1, R_ARM_LDC_PC_G1},
1931 {BFD_RELOC_ARM_LDC_PC_G2, R_ARM_LDC_PC_G2},
1932 {BFD_RELOC_ARM_ALU_SB_G0_NC, R_ARM_ALU_SB_G0_NC},
1933 {BFD_RELOC_ARM_ALU_SB_G0, R_ARM_ALU_SB_G0},
1934 {BFD_RELOC_ARM_ALU_SB_G1_NC, R_ARM_ALU_SB_G1_NC},
1935 {BFD_RELOC_ARM_ALU_SB_G1, R_ARM_ALU_SB_G1},
1936 {BFD_RELOC_ARM_ALU_SB_G2, R_ARM_ALU_SB_G2},
1937 {BFD_RELOC_ARM_LDR_SB_G0, R_ARM_LDR_SB_G0},
1938 {BFD_RELOC_ARM_LDR_SB_G1, R_ARM_LDR_SB_G1},
1939 {BFD_RELOC_ARM_LDR_SB_G2, R_ARM_LDR_SB_G2},
1940 {BFD_RELOC_ARM_LDRS_SB_G0, R_ARM_LDRS_SB_G0},
1941 {BFD_RELOC_ARM_LDRS_SB_G1, R_ARM_LDRS_SB_G1},
1942 {BFD_RELOC_ARM_LDRS_SB_G2, R_ARM_LDRS_SB_G2},
1943 {BFD_RELOC_ARM_LDC_SB_G0, R_ARM_LDC_SB_G0},
1944 {BFD_RELOC_ARM_LDC_SB_G1, R_ARM_LDC_SB_G1},
845b51d6 1945 {BFD_RELOC_ARM_LDC_SB_G2, R_ARM_LDC_SB_G2},
72d98d16
MG		 1946 {BFD_RELOC_ARM_V4BX, R_ARM_V4BX},
1947 {BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC, R_ARM_THM_ALU_ABS_G3_NC},
1948 {BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC, R_ARM_THM_ALU_ABS_G2_NC},
1949 {BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC, R_ARM_THM_ALU_ABS_G1_NC},
1950 {BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC, R_ARM_THM_ALU_ABS_G0_NC}
7f266840
DJ		 1951 };
1952
1953static reloc_howto_type *
f1c71a59
ZW		 1954elf32_arm_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
1955 bfd_reloc_code_real_type code)
7f266840
DJ		 1956{
1957 unsigned int i;
8029a119 1958
906e58ca 1959 for (i = 0; i < ARRAY_SIZE (elf32_arm_reloc_map); i ++)
c19d1205
ZW		 1960 if (elf32_arm_reloc_map[i].bfd_reloc_val == code)
1961 return elf32_arm_howto_from_type (elf32_arm_reloc_map[i].elf_reloc_val);
7f266840 1962
c19d1205 1963 return NULL;
7f266840
DJ		 1964}
1965
157090f7
AM		 1966static reloc_howto_type *
1967elf32_arm_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
1968 const char *r_name)
1969{
1970 unsigned int i;
1971
906e58ca 1972 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_1); i++)
157090f7
AM		 1973 if (elf32_arm_howto_table_1[i].name != NULL
1974 && strcasecmp (elf32_arm_howto_table_1[i].name, r_name) == 0)
1975 return &elf32_arm_howto_table_1[i];
1976
906e58ca 1977 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_2); i++)
157090f7
AM		 1978 if (elf32_arm_howto_table_2[i].name != NULL
1979 && strcasecmp (elf32_arm_howto_table_2[i].name, r_name) == 0)
1980 return &elf32_arm_howto_table_2[i];
1981
34e77a92
RS		 1982 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_3); i++)
1983 if (elf32_arm_howto_table_3[i].name != NULL
1984 && strcasecmp (elf32_arm_howto_table_3[i].name, r_name) == 0)
1985 return &elf32_arm_howto_table_3[i];
1986
157090f7
AM		 1987 return NULL;
1988}
1989
906e58ca
NC		 1990/* Support for core dump NOTE sections. */
1991
7f266840 1992static bfd_boolean
f1c71a59 1993elf32_arm_nabi_grok_prstatus (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 1994{
1995 int offset;
1996 size_t size;
1997
1998 switch (note->descsz)
1999 {
2000 default:
2001 return FALSE;
2002
8029a119 2003 case 148: /* Linux/ARM 32-bit. */
7f266840 2004 /* pr_cursig */
228e534f 2005 elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12);
7f266840
DJ		 2006
2007 /* pr_pid */
228e534f 2008 elf_tdata (abfd)->core->lwpid = bfd_get_32 (abfd, note->descdata + 24);
7f266840
DJ		 2009
2010 /* pr_reg */
2011 offset = 72;
2012 size = 72;
2013
2014 break;
2015 }
2016
2017 /* Make a ".reg/999" section. */
2018 return _bfd_elfcore_make_pseudosection (abfd, ".reg",
2019 size, note->descpos + offset);
2020}
2021
2022static bfd_boolean
f1c71a59 2023elf32_arm_nabi_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2024{
2025 switch (note->descsz)
2026 {
2027 default:
2028 return FALSE;
2029
8029a119 2030 case 124: /* Linux/ARM elf_prpsinfo. */
228e534f 2031 elf_tdata (abfd)->core->pid
4395ee08 2032 = bfd_get_32 (abfd, note->descdata + 12);
228e534f 2033 elf_tdata (abfd)->core->program
7f266840 2034 = _bfd_elfcore_strndup (abfd, note->descdata + 28, 16);
228e534f 2035 elf_tdata (abfd)->core->command
7f266840
DJ		 2036 = _bfd_elfcore_strndup (abfd, note->descdata + 44, 80);
2037 }
2038
2039 /* Note that for some reason, a spurious space is tacked
2040 onto the end of the args in some (at least one anyway)
2041 implementations, so strip it off if it exists. */
7f266840 2042 {
228e534f 2043 char *command = elf_tdata (abfd)->core->command;
7f266840
DJ		 2044 int n = strlen (command);
2045
2046 if (0 < n && command[n - 1] == ' ')
2047 command[n - 1] = '\0';
2048 }
2049
2050 return TRUE;
2051}
2052
1f20dca5
UW		 2053static char *
2054elf32_arm_nabi_write_core_note (bfd *abfd, char *buf, int *bufsiz,
2055 int note_type, ...)
2056{
2057 switch (note_type)
2058 {
2059 default:
2060 return NULL;
2061
2062 case NT_PRPSINFO:
2063 {
2064 char data[124];
2065 va_list ap;
2066
2067 va_start (ap, note_type);
2068 memset (data, 0, sizeof (data));
2069 strncpy (data + 28, va_arg (ap, const char *), 16);
2070 strncpy (data + 44, va_arg (ap, const char *), 80);
2071 va_end (ap);
2072
2073 return elfcore_write_note (abfd, buf, bufsiz,
2074 "CORE", note_type, data, sizeof (data));
2075 }
2076
2077 case NT_PRSTATUS:
2078 {
2079 char data[148];
2080 va_list ap;
2081 long pid;
2082 int cursig;
2083 const void *greg;
2084
2085 va_start (ap, note_type);
2086 memset (data, 0, sizeof (data));
2087 pid = va_arg (ap, long);
2088 bfd_put_32 (abfd, pid, data + 24);
2089 cursig = va_arg (ap, int);
2090 bfd_put_16 (abfd, cursig, data + 12);
2091 greg = va_arg (ap, const void *);
2092 memcpy (data + 72, greg, 72);
2093 va_end (ap);
2094
2095 return elfcore_write_note (abfd, buf, bufsiz,
2096 "CORE", note_type, data, sizeof (data));
2097 }
2098 }
2099}
2100
6d00b590 2101#define TARGET_LITTLE_SYM arm_elf32_le_vec
7f266840 2102#define TARGET_LITTLE_NAME "elf32-littlearm"
6d00b590 2103#define TARGET_BIG_SYM arm_elf32_be_vec
7f266840
DJ		 2104#define TARGET_BIG_NAME "elf32-bigarm"
2105
2106#define elf_backend_grok_prstatus elf32_arm_nabi_grok_prstatus
2107#define elf_backend_grok_psinfo elf32_arm_nabi_grok_psinfo
1f20dca5 2108#define elf_backend_write_core_note elf32_arm_nabi_write_core_note
7f266840 2109
252b5132
RH		 2110typedef unsigned long int insn32;
2111typedef unsigned short int insn16;
2112
3a4a14e9
PB		 2113/* In lieu of proper flags, assume all EABIv4 or later objects are
2114 interworkable. */
57e8b36a 2115#define INTERWORK_FLAG(abfd) \
3a4a14e9 2116 (EF_ARM_EABI_VERSION (elf_elfheader (abfd)->e_flags) >= EF_ARM_EABI_VER4 \
3e6b1042
DJ		 2117 || (elf_elfheader (abfd)->e_flags & EF_ARM_INTERWORK) \
2118 || ((abfd)->flags & BFD_LINKER_CREATED))
9b485d32 2119
252b5132
RH		 2120/* The linker script knows the section names for placement.
2121 The entry_names are used to do simple name mangling on the stubs.
2122 Given a function name, and its type, the stub can be found. The
9b485d32 2123 name can be changed. The only requirement is the %s be present. */
252b5132
RH		 2124#define THUMB2ARM_GLUE_SECTION_NAME ".glue_7t"
2125#define THUMB2ARM_GLUE_ENTRY_NAME "__%s_from_thumb"
2126
2127#define ARM2THUMB_GLUE_SECTION_NAME ".glue_7"
2128#define ARM2THUMB_GLUE_ENTRY_NAME "__%s_from_arm"
2129
c7b8f16e
JB		 2130#define VFP11_ERRATUM_VENEER_SECTION_NAME ".vfp11_veneer"
2131#define VFP11_ERRATUM_VENEER_ENTRY_NAME "__vfp11_veneer_%x"
2132
a504d23a
LA		 2133#define STM32L4XX_ERRATUM_VENEER_SECTION_NAME ".text.stm32l4xx_veneer"
2134#define STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "__stm32l4xx_veneer_%x"
2135
845b51d6
PB		 2136#define ARM_BX_GLUE_SECTION_NAME ".v4_bx"
2137#define ARM_BX_GLUE_ENTRY_NAME "__bx_r%d"
2138
7413f23f
DJ		 2139#define STUB_ENTRY_NAME "__%s_veneer"
2140
4ba2ef8f
TP		 2141#define CMSE_PREFIX "__acle_se_"
2142
252b5132
RH		 2143/* The name of the dynamic interpreter. This is put in the .interp
2144 section. */
2145#define ELF_DYNAMIC_INTERPRETER "/usr/lib/ld.so.1"
2146
0855e32b 2147static const unsigned long tls_trampoline [] =
b38cadfb
NC		 2148{
2149 0xe08e0000, /* add r0, lr, r0 */
2150 0xe5901004, /* ldr r1, [r0,#4] */
2151 0xe12fff11, /* bx r1 */
2152};
0855e32b
NS		 2153
2154static const unsigned long dl_tlsdesc_lazy_trampoline [] =
b38cadfb
NC		 2155{
2156 0xe52d2004, /* push {r2} */
2157 0xe59f200c, /* ldr r2, [pc, #3f - . - 8] */
2158 0xe59f100c, /* ldr r1, [pc, #4f - . - 8] */
2159 0xe79f2002, /* 1: ldr r2, [pc, r2] */
2160 0xe081100f, /* 2: add r1, pc */
2161 0xe12fff12, /* bx r2 */
2162 0x00000014, /* 3: .word _GLOBAL_OFFSET_TABLE_ - 1b - 8
99059e56 2163 + dl_tlsdesc_lazy_resolver(GOT) */
b38cadfb
NC		 2164 0x00000018, /* 4: .word _GLOBAL_OFFSET_TABLE_ - 2b - 8 */
2165};
0855e32b 2166
5e681ec4
PB		 2167#ifdef FOUR_WORD_PLT
2168
252b5132
RH		 2169/* The first entry in a procedure linkage table looks like
2170 this. It is set up so that any shared library function that is
59f2c4e7 2171 called before the relocation has been set up calls the dynamic
9b485d32 2172 linker first. */
e5a52504 2173static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2174{
2175 0xe52de004, /* str lr, [sp, #-4]! */
2176 0xe59fe010, /* ldr lr, [pc, #16] */
2177 0xe08fe00e, /* add lr, pc, lr */
2178 0xe5bef008, /* ldr pc, [lr, #8]! */
2179};
5e681ec4
PB		 2180
2181/* Subsequent entries in a procedure linkage table look like
2182 this. */
e5a52504 2183static const bfd_vma elf32_arm_plt_entry [] =
b38cadfb
NC		 2184{
2185 0xe28fc600, /* add ip, pc, #NN */
2186 0xe28cca00, /* add ip, ip, #NN */
2187 0xe5bcf000, /* ldr pc, [ip, #NN]! */
2188 0x00000000, /* unused */
2189};
5e681ec4 2190
eed94f8f 2191#else /* not FOUR_WORD_PLT */
5e681ec4 2192
5e681ec4
PB		 2193/* The first entry in a procedure linkage table looks like
2194 this. It is set up so that any shared library function that is
2195 called before the relocation has been set up calls the dynamic
2196 linker first. */
e5a52504 2197static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2198{
2199 0xe52de004, /* str lr, [sp, #-4]! */
2200 0xe59fe004, /* ldr lr, [pc, #4] */
2201 0xe08fe00e, /* add lr, pc, lr */
2202 0xe5bef008, /* ldr pc, [lr, #8]! */
2203 0x00000000, /* &GOT[0] - . */
2204};
252b5132 2205
1db37fe6
YG		 2206/* By default subsequent entries in a procedure linkage table look like
2207 this. Offsets that don't fit into 28 bits will cause link error. */
2208static const bfd_vma elf32_arm_plt_entry_short [] =
b38cadfb
NC		 2209{
2210 0xe28fc600, /* add ip, pc, #0xNN00000 */
2211 0xe28cca00, /* add ip, ip, #0xNN000 */
2212 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2213};
5e681ec4 2214
1db37fe6
YG		 2215/* When explicitly asked, we'll use this "long" entry format
2216 which can cope with arbitrary displacements. */
2217static const bfd_vma elf32_arm_plt_entry_long [] =
2218{
2219 0xe28fc200, /* add ip, pc, #0xN0000000 */
2220 0xe28cc600, /* add ip, ip, #0xNN00000 */
2221 0xe28cca00, /* add ip, ip, #0xNN000 */
2222 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2223};
2224
2225static bfd_boolean elf32_arm_use_long_plt_entry = FALSE;
2226
eed94f8f
NC		 2227#endif /* not FOUR_WORD_PLT */
2228
2229/* The first entry in a procedure linkage table looks like this.
2230 It is set up so that any shared library function that is called before the
2231 relocation has been set up calls the dynamic linker first. */
2232static const bfd_vma elf32_thumb2_plt0_entry [] =
2233{
2234 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2235 an instruction maybe encoded to one or two array elements. */
2236 0xf8dfb500, /* push {lr} */
2237 0x44fee008, /* ldr.w lr, [pc, #8] */
469a3493 2238 /* add lr, pc */
eed94f8f
NC		 2239 0xff08f85e, /* ldr.w pc, [lr, #8]! */
2240 0x00000000, /* &GOT[0] - . */
2241};
2242
2243/* Subsequent entries in a procedure linkage table for thumb only target
2244 look like this. */
2245static const bfd_vma elf32_thumb2_plt_entry [] =
2246{
2247 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2248 an instruction maybe encoded to one or two array elements. */
2249 0x0c00f240, /* movw ip, #0xNNNN */
2250 0x0c00f2c0, /* movt ip, #0xNNNN */
2251 0xf8dc44fc, /* add ip, pc */
2252 0xbf00f000 /* ldr.w pc, [ip] */
469a3493 2253 /* nop */
eed94f8f 2254};
252b5132 2255
00a97672
RS		 2256/* The format of the first entry in the procedure linkage table
2257 for a VxWorks executable. */
2258static const bfd_vma elf32_arm_vxworks_exec_plt0_entry[] =
b38cadfb
NC		 2259{
2260 0xe52dc008, /* str ip,[sp,#-8]! */
2261 0xe59fc000, /* ldr ip,[pc] */
2262 0xe59cf008, /* ldr pc,[ip,#8] */
2263 0x00000000, /* .long _GLOBAL_OFFSET_TABLE_ */
2264};
00a97672
RS		 2265
2266/* The format of subsequent entries in a VxWorks executable. */
2267static const bfd_vma elf32_arm_vxworks_exec_plt_entry[] =
b38cadfb
NC		 2268{
2269 0xe59fc000, /* ldr ip,[pc] */
2270 0xe59cf000, /* ldr pc,[ip] */
2271 0x00000000, /* .long @got */
2272 0xe59fc000, /* ldr ip,[pc] */
2273 0xea000000, /* b _PLT */
2274 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
2275};
00a97672
RS		 2276
2277/* The format of entries in a VxWorks shared library. */
2278static const bfd_vma elf32_arm_vxworks_shared_plt_entry[] =
b38cadfb
NC		 2279{
2280 0xe59fc000, /* ldr ip,[pc] */
2281 0xe79cf009, /* ldr pc,[ip,r9] */
2282 0x00000000, /* .long @got */
2283 0xe59fc000, /* ldr ip,[pc] */
2284 0xe599f008, /* ldr pc,[r9,#8] */
2285 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
2286};
00a97672 2287
b7693d02
DJ		 2288/* An initial stub used if the PLT entry is referenced from Thumb code. */
2289#define PLT_THUMB_STUB_SIZE 4
2290static const bfd_vma elf32_arm_plt_thumb_stub [] =
b38cadfb
NC		 2291{
2292 0x4778, /* bx pc */
2293 0x46c0 /* nop */
2294};
b7693d02 2295
e5a52504
MM		 2296/* The entries in a PLT when using a DLL-based target with multiple
2297 address spaces. */
906e58ca 2298static const bfd_vma elf32_arm_symbian_plt_entry [] =
b38cadfb
NC		 2299{
2300 0xe51ff004, /* ldr pc, [pc, #-4] */
2301 0x00000000, /* dcd R_ARM_GLOB_DAT(X) */
2302};
2303
2304/* The first entry in a procedure linkage table looks like
2305 this. It is set up so that any shared library function that is
2306 called before the relocation has been set up calls the dynamic
2307 linker first. */
2308static const bfd_vma elf32_arm_nacl_plt0_entry [] =
2309{
2310 /* First bundle: */
2311 0xe300c000, /* movw ip, #:lower16:&GOT[2]-.+8 */
2312 0xe340c000, /* movt ip, #:upper16:&GOT[2]-.+8 */
2313 0xe08cc00f, /* add ip, ip, pc */
2314 0xe52dc008, /* str ip, [sp, #-8]! */
2315 /* Second bundle: */
edccdf7c
RM		 2316 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2317 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2318 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2319 0xe12fff1c, /* bx ip */
b38cadfb 2320 /* Third bundle: */
edccdf7c
RM		 2321 0xe320f000, /* nop */
2322 0xe320f000, /* nop */
2323 0xe320f000, /* nop */
b38cadfb
NC		 2324 /* .Lplt_tail: */
2325 0xe50dc004, /* str ip, [sp, #-4] */
2326 /* Fourth bundle: */
edccdf7c
RM		 2327 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2328 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2329 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2330 0xe12fff1c, /* bx ip */
b38cadfb
NC		 2331};
2332#define ARM_NACL_PLT_TAIL_OFFSET (11 * 4)
2333
2334/* Subsequent entries in a procedure linkage table look like this. */
2335static const bfd_vma elf32_arm_nacl_plt_entry [] =
2336{
2337 0xe300c000, /* movw ip, #:lower16:&GOT[n]-.+8 */
2338 0xe340c000, /* movt ip, #:upper16:&GOT[n]-.+8 */
2339 0xe08cc00f, /* add ip, ip, pc */
2340 0xea000000, /* b .Lplt_tail */
2341};
e5a52504 2342
906e58ca
NC		 2343#define ARM_MAX_FWD_BRANCH_OFFSET ((((1 << 23) - 1) << 2) + 8)
2344#define ARM_MAX_BWD_BRANCH_OFFSET ((-((1 << 23) << 2)) + 8)
2345#define THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) -2 + 4)
2346#define THM_MAX_BWD_BRANCH_OFFSET (-(1 << 22) + 4)
2347#define THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 2) + 4)
2348#define THM2_MAX_BWD_BRANCH_OFFSET (-(1 << 24) + 4)
c5423981
TG		 2349#define THM2_MAX_FWD_COND_BRANCH_OFFSET (((1 << 20) -2) + 4)
2350#define THM2_MAX_BWD_COND_BRANCH_OFFSET (-(1 << 20) + 4)
906e58ca 2351
461a49ca 2352enum stub_insn_type
b38cadfb
NC		 2353{
2354 THUMB16_TYPE = 1,
2355 THUMB32_TYPE,
2356 ARM_TYPE,
2357 DATA_TYPE
2358};
461a49ca 2359
48229727
JB		 2360#define THUMB16_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 0}
2361/* A bit of a hack. A Thumb conditional branch, in which the proper condition
2362 is inserted in arm_build_one_stub(). */
2363#define THUMB16_BCOND_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 1}
2364#define THUMB32_INSN(X) {(X), THUMB32_TYPE, R_ARM_NONE, 0}
d5a67c02
AV		 2365#define THUMB32_MOVT(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVT_ABS, 0}
2366#define THUMB32_MOVW(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVW_ABS_NC, 0}
48229727
JB		 2367#define THUMB32_B_INSN(X, Z) {(X), THUMB32_TYPE, R_ARM_THM_JUMP24, (Z)}
2368#define ARM_INSN(X) {(X), ARM_TYPE, R_ARM_NONE, 0}
2369#define ARM_REL_INSN(X, Z) {(X), ARM_TYPE, R_ARM_JUMP24, (Z)}
2370#define DATA_WORD(X,Y,Z) {(X), DATA_TYPE, (Y), (Z)}
461a49ca
DJ		 2371
2372typedef struct
2373{
b38cadfb
NC		 2374 bfd_vma data;
2375 enum stub_insn_type type;
2376 unsigned int r_type;
2377 int reloc_addend;
461a49ca
DJ		 2378} insn_sequence;
2379
fea2b4d6
CL		 2380/* Arm/Thumb -> Arm/Thumb long branch stub. On V5T and above, use blx
2381 to reach the stub if necessary. */
461a49ca 2382static const insn_sequence elf32_arm_stub_long_branch_any_any[] =
b38cadfb
NC		 2383{
2384 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
2385 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2386};
906e58ca 2387
fea2b4d6
CL		 2388/* V4T Arm -> Thumb long branch stub. Used on V4T where blx is not
2389 available. */
461a49ca 2390static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb[] =
b38cadfb
NC		 2391{
2392 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2393 ARM_INSN (0xe12fff1c), /* bx ip */
2394 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2395};
906e58ca 2396
d3626fb0 2397/* Thumb -> Thumb long branch stub. Used on M-profile architectures. */
461a49ca 2398static const insn_sequence elf32_arm_stub_long_branch_thumb_only[] =
b38cadfb
NC		 2399{
2400 THUMB16_INSN (0xb401), /* push {r0} */
2401 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2402 THUMB16_INSN (0x4684), /* mov ip, r0 */
2403 THUMB16_INSN (0xbc01), /* pop {r0} */
2404 THUMB16_INSN (0x4760), /* bx ip */
2405 THUMB16_INSN (0xbf00), /* nop */
2406 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2407};
906e58ca 2408
80c135e5
TP		 2409/* Thumb -> Thumb long branch stub in thumb2 encoding. Used on armv7. */
2410static const insn_sequence elf32_arm_stub_long_branch_thumb2_only[] =
2411{
2412 THUMB32_INSN (0xf85ff000), /* ldr.w pc, [pc, #-0] */
2413 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(x) */
2414};
2415
d5a67c02
AV		 2416/* Thumb -> Thumb long branch stub. Used for PureCode sections on Thumb2
2417 M-profile architectures. */
2418static const insn_sequence elf32_arm_stub_long_branch_thumb2_only_pure[] =
2419{
2420 THUMB32_MOVW (0xf2400c00), /* mov.w ip, R_ARM_MOVW_ABS_NC */
2421 THUMB32_MOVT (0xf2c00c00), /* movt ip, R_ARM_MOVT_ABS << 16 */
2422 THUMB16_INSN (0x4760), /* bx ip */
2423};
2424
d3626fb0
CL		 2425/* V4T Thumb -> Thumb long branch stub. Using the stack is not
2426 allowed. */
2427static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb[] =
b38cadfb
NC		 2428{
2429 THUMB16_INSN (0x4778), /* bx pc */
2430 THUMB16_INSN (0x46c0), /* nop */
2431 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2432 ARM_INSN (0xe12fff1c), /* bx ip */
2433 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2434};
d3626fb0 2435
fea2b4d6
CL		 2436/* V4T Thumb -> ARM long branch stub. Used on V4T where blx is not
2437 available. */
461a49ca 2438static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm[] =
b38cadfb
NC		 2439{
2440 THUMB16_INSN (0x4778), /* bx pc */
2441 THUMB16_INSN (0x46c0), /* nop */
2442 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
2443 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2444};
906e58ca 2445
fea2b4d6
CL		 2446/* V4T Thumb -> ARM short branch stub. Shorter variant of the above
2447 one, when the destination is close enough. */
461a49ca 2448static const insn_sequence elf32_arm_stub_short_branch_v4t_thumb_arm[] =
b38cadfb
NC		 2449{
2450 THUMB16_INSN (0x4778), /* bx pc */
2451 THUMB16_INSN (0x46c0), /* nop */
2452 ARM_REL_INSN (0xea000000, -8), /* b (X-8) */
2453};
c820be07 2454
cf3eccff 2455/* ARM/Thumb -> ARM long branch stub, PIC. On V5T and above, use
fea2b4d6 2456 blx to reach the stub if necessary. */
cf3eccff 2457static const insn_sequence elf32_arm_stub_long_branch_any_arm_pic[] =
b38cadfb
NC		 2458{
2459 ARM_INSN (0xe59fc000), /* ldr ip, [pc] */
2460 ARM_INSN (0xe08ff00c), /* add pc, pc, ip */
2461 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
2462};
906e58ca 2463
cf3eccff
DJ		 2464/* ARM/Thumb -> Thumb long branch stub, PIC. On V5T and above, use
2465 blx to reach the stub if necessary. We can not add into pc;
2466 it is not guaranteed to mode switch (different in ARMv6 and
2467 ARMv7). */
2468static const insn_sequence elf32_arm_stub_long_branch_any_thumb_pic[] =
b38cadfb
NC		 2469{
2470 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2471 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2472 ARM_INSN (0xe12fff1c), /* bx ip */
2473 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2474};
cf3eccff 2475
ebe24dd4
CL		 2476/* V4T ARM -> ARM long branch stub, PIC. */
2477static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb_pic[] =
b38cadfb
NC		 2478{
2479 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2480 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2481 ARM_INSN (0xe12fff1c), /* bx ip */
2482 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2483};
ebe24dd4
CL		 2484
2485/* V4T Thumb -> ARM long branch stub, PIC. */
2486static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm_pic[] =
b38cadfb
NC		 2487{
2488 THUMB16_INSN (0x4778), /* bx pc */
2489 THUMB16_INSN (0x46c0), /* nop */
2490 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2491 ARM_INSN (0xe08cf00f), /* add pc, ip, pc */
2492 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
2493};
ebe24dd4 2494
d3626fb0
CL		 2495/* Thumb -> Thumb long branch stub, PIC. Used on M-profile
2496 architectures. */
ebe24dd4 2497static const insn_sequence elf32_arm_stub_long_branch_thumb_only_pic[] =
b38cadfb
NC		 2498{
2499 THUMB16_INSN (0xb401), /* push {r0} */
2500 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2501 THUMB16_INSN (0x46fc), /* mov ip, pc */
2502 THUMB16_INSN (0x4484), /* add ip, r0 */
2503 THUMB16_INSN (0xbc01), /* pop {r0} */
2504 THUMB16_INSN (0x4760), /* bx ip */
2505 DATA_WORD (0, R_ARM_REL32, 4), /* dcd R_ARM_REL32(X) */
2506};
ebe24dd4 2507
d3626fb0
CL		 2508/* V4T Thumb -> Thumb long branch stub, PIC. Using the stack is not
2509 allowed. */
2510static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb_pic[] =
b38cadfb
NC		 2511{
2512 THUMB16_INSN (0x4778), /* bx pc */
2513 THUMB16_INSN (0x46c0), /* nop */
2514 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2515 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2516 ARM_INSN (0xe12fff1c), /* bx ip */
2517 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2518};
d3626fb0 2519
0855e32b
NS		 2520/* Thumb2/ARM -> TLS trampoline. Lowest common denominator, which is a
2521 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2522static const insn_sequence elf32_arm_stub_long_branch_any_tls_pic[] =
2523{
b38cadfb
NC		 2524 ARM_INSN (0xe59f1000), /* ldr r1, [pc] */
2525 ARM_INSN (0xe08ff001), /* add pc, pc, r1 */
2526 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
0855e32b
NS		 2527};
2528
2529/* V4T Thumb -> TLS trampoline. lowest common denominator, which is a
2530 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2531static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_tls_pic[] =
2532{
b38cadfb
NC		 2533 THUMB16_INSN (0x4778), /* bx pc */
2534 THUMB16_INSN (0x46c0), /* nop */
2535 ARM_INSN (0xe59f1000), /* ldr r1, [pc, #0] */
2536 ARM_INSN (0xe081f00f), /* add pc, r1, pc */
2537 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
0855e32b
NS		 2538};
2539
7a89b94e
NC		 2540/* NaCl ARM -> ARM long branch stub. */
2541static const insn_sequence elf32_arm_stub_long_branch_arm_nacl[] =
2542{
2543 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2544 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
2545 ARM_INSN (0xe12fff1c), /* bx ip */
2546 ARM_INSN (0xe320f000), /* nop */
2547 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2548 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2549 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2550 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2551};
2552
2553/* NaCl ARM -> ARM long branch stub, PIC. */
2554static const insn_sequence elf32_arm_stub_long_branch_arm_nacl_pic[] =
2555{
2556 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2557 ARM_INSN (0xe08cc00f), /* add ip, ip, pc */
2558 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
2559 ARM_INSN (0xe12fff1c), /* bx ip */
2560 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2561 DATA_WORD (0, R_ARM_REL32, 8), /* dcd R_ARM_REL32(X+8) */
2562 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2563 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2564};
2565
4ba2ef8f
TP		 2566/* Stub used for transition to secure state (aka SG veneer). */
2567static const insn_sequence elf32_arm_stub_cmse_branch_thumb_only[] =
2568{
2569 THUMB32_INSN (0xe97fe97f), /* sg. */
2570 THUMB32_B_INSN (0xf000b800, -4), /* b.w original_branch_dest. */
2571};
2572
7a89b94e 2573
48229727
JB		 2574/* Cortex-A8 erratum-workaround stubs. */
2575
2576/* Stub used for conditional branches (which may be beyond +/-1MB away, so we
2577 can't use a conditional branch to reach this stub). */
2578
2579static const insn_sequence elf32_arm_stub_a8_veneer_b_cond[] =
b38cadfb
NC		 2580{
2581 THUMB16_BCOND_INSN (0xd001), /* b<cond>.n true. */
2582 THUMB32_B_INSN (0xf000b800, -4), /* b.w insn_after_original_branch. */
2583 THUMB32_B_INSN (0xf000b800, -4) /* true: b.w original_branch_dest. */
2584};
48229727
JB		 2585
2586/* Stub used for b.w and bl.w instructions. */
2587
2588static const insn_sequence elf32_arm_stub_a8_veneer_b[] =
b38cadfb
NC		 2589{
2590 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2591};
48229727
JB		 2592
2593static const insn_sequence elf32_arm_stub_a8_veneer_bl[] =
b38cadfb
NC		 2594{
2595 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2596};
48229727
JB		 2597
2598/* Stub used for Thumb-2 blx.w instructions. We modified the original blx.w
2599 instruction (which switches to ARM mode) to point to this stub. Jump to the
2600 real destination using an ARM-mode branch. */
2601
2602static const insn_sequence elf32_arm_stub_a8_veneer_blx[] =
b38cadfb
NC		 2603{
2604 ARM_REL_INSN (0xea000000, -8) /* b original_branch_dest. */
2605};
48229727 2606
9553db3c
NC		 2607/* For each section group there can be a specially created linker section
2608 to hold the stubs for that group. The name of the stub section is based
2609 upon the name of another section within that group with the suffix below
2610 applied.
2611
2612 PR 13049: STUB_SUFFIX used to be ".stub", but this allowed the user to
2613 create what appeared to be a linker stub section when it actually
2614 contained user code/data. For example, consider this fragment:
b38cadfb 2615
9553db3c
NC		 2616 const char * stubborn_problems[] = { "np" };
2617
2618 If this is compiled with "-fPIC -fdata-sections" then gcc produces a
2619 section called:
2620
2621 .data.rel.local.stubborn_problems
2622
2623 This then causes problems in arm32_arm_build_stubs() as it triggers:
2624
2625 // Ignore non-stub sections.
2626 if (!strstr (stub_sec->name, STUB_SUFFIX))
2627 continue;
2628
2629 And so the section would be ignored instead of being processed. Hence
2630 the change in definition of STUB_SUFFIX to a name that cannot be a valid
2631 C identifier. */
2632#define STUB_SUFFIX ".__stub"
906e58ca 2633
738a79f6
CL		 2634/* One entry per long/short branch stub defined above. */
2635#define DEF_STUBS \
2636 DEF_STUB(long_branch_any_any) \
2637 DEF_STUB(long_branch_v4t_arm_thumb) \
2638 DEF_STUB(long_branch_thumb_only) \
2639 DEF_STUB(long_branch_v4t_thumb_thumb) \
2640 DEF_STUB(long_branch_v4t_thumb_arm) \
2641 DEF_STUB(short_branch_v4t_thumb_arm) \
2642 DEF_STUB(long_branch_any_arm_pic) \
2643 DEF_STUB(long_branch_any_thumb_pic) \
2644 DEF_STUB(long_branch_v4t_thumb_thumb_pic) \
2645 DEF_STUB(long_branch_v4t_arm_thumb_pic) \
2646 DEF_STUB(long_branch_v4t_thumb_arm_pic) \
48229727 2647 DEF_STUB(long_branch_thumb_only_pic) \
0855e32b
NS		 2648 DEF_STUB(long_branch_any_tls_pic) \
2649 DEF_STUB(long_branch_v4t_thumb_tls_pic) \
7a89b94e
NC		 2650 DEF_STUB(long_branch_arm_nacl) \
2651 DEF_STUB(long_branch_arm_nacl_pic) \
4ba2ef8f 2652 DEF_STUB(cmse_branch_thumb_only) \
48229727
JB		 2653 DEF_STUB(a8_veneer_b_cond) \
2654 DEF_STUB(a8_veneer_b) \
2655 DEF_STUB(a8_veneer_bl) \
80c135e5
TP		 2656 DEF_STUB(a8_veneer_blx) \
2657 DEF_STUB(long_branch_thumb2_only) \
d5a67c02 2658 DEF_STUB(long_branch_thumb2_only_pure)
738a79f6
CL		 2659
2660#define DEF_STUB(x) arm_stub_##x,
b38cadfb
NC		 2661enum elf32_arm_stub_type
2662{
906e58ca 2663 arm_stub_none,
738a79f6 2664 DEF_STUBS
4f4faa4d 2665 max_stub_type
738a79f6
CL		 2666};
2667#undef DEF_STUB
2668
8d9d9490
TP		 2669/* Note the first a8_veneer type. */
2670const unsigned arm_stub_a8_veneer_lwm = arm_stub_a8_veneer_b_cond;
2671
738a79f6
CL		 2672typedef struct
2673{
d3ce72d0 2674 const insn_sequence* template_sequence;
738a79f6
CL		 2675 int template_size;
2676} stub_def;
2677
2678#define DEF_STUB(x) {elf32_arm_stub_##x, ARRAY_SIZE(elf32_arm_stub_##x)},
b38cadfb
NC		 2679static const stub_def stub_definitions[] =
2680{
738a79f6
CL		 2681 {NULL, 0},
2682 DEF_STUBS
906e58ca
NC		 2683};
2684
2685struct elf32_arm_stub_hash_entry
2686{
2687 /* Base hash table entry structure. */
2688 struct bfd_hash_entry root;
2689
2690 /* The stub section. */
2691 asection *stub_sec;
2692
2693 /* Offset within stub_sec of the beginning of this stub. */
2694 bfd_vma stub_offset;
2695
2696 /* Given the symbol's value and its section we can determine its final
2697 value when building the stubs (so the stub knows where to jump). */
2698 bfd_vma target_value;
2699 asection *target_section;
2700
8d9d9490
TP		 2701 /* Same as above but for the source of the branch to the stub. Used for
2702 Cortex-A8 erratum workaround to patch it to branch to the stub. As
2703 such, source section does not need to be recorded since Cortex-A8 erratum
2704 workaround stubs are only generated when both source and target are in the
2705 same section. */
2706 bfd_vma source_value;
48229727
JB		 2707
2708 /* The instruction which caused this stub to be generated (only valid for
2709 Cortex-A8 erratum workaround stubs at present). */
2710 unsigned long orig_insn;
2711
461a49ca 2712 /* The stub type. */
906e58ca 2713 enum elf32_arm_stub_type stub_type;
461a49ca
DJ		 2714 /* Its encoding size in bytes. */
2715 int stub_size;
2716 /* Its template. */
2717 const insn_sequence *stub_template;
2718 /* The size of the template (number of entries). */
2719 int stub_template_size;
906e58ca
NC		 2720
2721 /* The symbol table entry, if any, that this was derived from. */
2722 struct elf32_arm_link_hash_entry *h;
2723
35fc36a8
RS		 2724 /* Type of branch. */
2725 enum arm_st_branch_type branch_type;
906e58ca
NC		 2726
2727 /* Where this stub is being called from, or, in the case of combined
2728 stub sections, the first input section in the group. */
2729 asection *id_sec;
7413f23f
DJ		 2730
2731 /* The name for the local symbol at the start of this stub. The
2732 stub name in the hash table has to be unique; this does not, so
2733 it can be friendlier. */
2734 char *output_name;
906e58ca
NC		 2735};
2736
e489d0ae
PB		 2737/* Used to build a map of a section. This is required for mixed-endian
2738 code/data. */
2739
2740typedef struct elf32_elf_section_map
2741{
2742 bfd_vma vma;
2743 char type;
2744}
2745elf32_arm_section_map;
2746
c7b8f16e
JB		 2747/* Information about a VFP11 erratum veneer, or a branch to such a veneer. */
2748
2749typedef enum
2750{
2751 VFP11_ERRATUM_BRANCH_TO_ARM_VENEER,
2752 VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER,
2753 VFP11_ERRATUM_ARM_VENEER,
2754 VFP11_ERRATUM_THUMB_VENEER
2755}
2756elf32_vfp11_erratum_type;
2757
2758typedef struct elf32_vfp11_erratum_list
2759{
2760 struct elf32_vfp11_erratum_list *next;
2761 bfd_vma vma;
2762 union
2763 {
2764 struct
2765 {
2766 struct elf32_vfp11_erratum_list *veneer;
2767 unsigned int vfp_insn;
2768 } b;
2769 struct
2770 {
2771 struct elf32_vfp11_erratum_list *branch;
2772 unsigned int id;
2773 } v;
2774 } u;
2775 elf32_vfp11_erratum_type type;
2776}
2777elf32_vfp11_erratum_list;
2778
a504d23a
LA		 2779/* Information about a STM32L4XX erratum veneer, or a branch to such a
2780 veneer. */
2781typedef enum
2782{
2783 STM32L4XX_ERRATUM_BRANCH_TO_VENEER,
2784 STM32L4XX_ERRATUM_VENEER
2785}
2786elf32_stm32l4xx_erratum_type;
2787
2788typedef struct elf32_stm32l4xx_erratum_list
2789{
2790 struct elf32_stm32l4xx_erratum_list *next;
2791 bfd_vma vma;
2792 union
2793 {
2794 struct
2795 {
2796 struct elf32_stm32l4xx_erratum_list *veneer;
2797 unsigned int insn;
2798 } b;
2799 struct
2800 {
2801 struct elf32_stm32l4xx_erratum_list *branch;
2802 unsigned int id;
2803 } v;
2804 } u;
2805 elf32_stm32l4xx_erratum_type type;
2806}
2807elf32_stm32l4xx_erratum_list;
2808
2468f9c9
PB		 2809typedef enum
2810{
2811 DELETE_EXIDX_ENTRY,
2812 INSERT_EXIDX_CANTUNWIND_AT_END
2813}
2814arm_unwind_edit_type;
2815
2816/* A (sorted) list of edits to apply to an unwind table. */
2817typedef struct arm_unwind_table_edit
2818{
2819 arm_unwind_edit_type type;
2820 /* Note: we sometimes want to insert an unwind entry corresponding to a
2821 section different from the one we're currently writing out, so record the
2822 (text) section this edit relates to here. */
2823 asection *linked_section;
2824 unsigned int index;
2825 struct arm_unwind_table_edit *next;
2826}
2827arm_unwind_table_edit;
2828
8e3de13a 2829typedef struct _arm_elf_section_data
e489d0ae 2830{
2468f9c9 2831 /* Information about mapping symbols. */
e489d0ae 2832 struct bfd_elf_section_data elf;
8e3de13a 2833 unsigned int mapcount;
c7b8f16e 2834 unsigned int mapsize;
e489d0ae 2835 elf32_arm_section_map *map;
2468f9c9 2836 /* Information about CPU errata. */
c7b8f16e
JB		 2837 unsigned int erratumcount;
2838 elf32_vfp11_erratum_list *erratumlist;
a504d23a
LA		 2839 unsigned int stm32l4xx_erratumcount;
2840 elf32_stm32l4xx_erratum_list *stm32l4xx_erratumlist;
491d01d3 2841 unsigned int additional_reloc_count;
2468f9c9
PB		 2842 /* Information about unwind tables. */
2843 union
2844 {
2845 /* Unwind info attached to a text section. */
2846 struct
2847 {
2848 asection *arm_exidx_sec;
2849 } text;
2850
2851 /* Unwind info attached to an .ARM.exidx section. */
2852 struct
2853 {
2854 arm_unwind_table_edit *unwind_edit_list;
2855 arm_unwind_table_edit *unwind_edit_tail;
2856 } exidx;
2857 } u;
8e3de13a
NC		 2858}
2859_arm_elf_section_data;
e489d0ae
PB		 2860
2861#define elf32_arm_section_data(sec) \
8e3de13a 2862 ((_arm_elf_section_data *) elf_section_data (sec))
e489d0ae 2863
48229727
JB		 2864/* A fix which might be required for Cortex-A8 Thumb-2 branch/TLB erratum.
2865 These fixes are subject to a relaxation procedure (in elf32_arm_size_stubs),
2866 so may be created multiple times: we use an array of these entries whilst
2867 relaxing which we can refresh easily, then create stubs for each potentially
2868 erratum-triggering instruction once we've settled on a solution. */
2869
b38cadfb
NC		 2870struct a8_erratum_fix
2871{
48229727
JB		 2872 bfd *input_bfd;
2873 asection *section;
2874 bfd_vma offset;
8d9d9490 2875 bfd_vma target_offset;
48229727
JB		 2876 unsigned long orig_insn;
2877 char *stub_name;
2878 enum elf32_arm_stub_type stub_type;
35fc36a8 2879 enum arm_st_branch_type branch_type;
48229727
JB		 2880};
2881
2882/* A table of relocs applied to branches which might trigger Cortex-A8
2883 erratum. */
2884
b38cadfb
NC		 2885struct a8_erratum_reloc
2886{
48229727
JB		 2887 bfd_vma from;
2888 bfd_vma destination;
92750f34
DJ		 2889 struct elf32_arm_link_hash_entry *hash;
2890 const char *sym_name;
48229727 2891 unsigned int r_type;
35fc36a8 2892 enum arm_st_branch_type branch_type;
48229727
JB		 2893 bfd_boolean non_a8_stub;
2894};
2895
ba93b8ac
DJ		 2896/* The size of the thread control block. */
2897#define TCB_SIZE 8
2898
34e77a92
RS		 2899/* ARM-specific information about a PLT entry, over and above the usual
2900 gotplt_union. */
b38cadfb
NC		 2901struct arm_plt_info
2902{
34e77a92
RS		 2903 /* We reference count Thumb references to a PLT entry separately,
2904 so that we can emit the Thumb trampoline only if needed. */
2905 bfd_signed_vma thumb_refcount;
2906
2907 /* Some references from Thumb code may be eliminated by BL->BLX
2908 conversion, so record them separately. */
2909 bfd_signed_vma maybe_thumb_refcount;
2910
2911 /* How many of the recorded PLT accesses were from non-call relocations.
2912 This information is useful when deciding whether anything takes the
2913 address of an STT_GNU_IFUNC PLT. A value of 0 means that all
2914 non-call references to the function should resolve directly to the
2915 real runtime target. */
2916 unsigned int noncall_refcount;
2917
2918 /* Since PLT entries have variable size if the Thumb prologue is
2919 used, we need to record the index into .got.plt instead of
2920 recomputing it from the PLT offset. */
2921 bfd_signed_vma got_offset;
2922};
2923
2924/* Information about an .iplt entry for a local STT_GNU_IFUNC symbol. */
b38cadfb
NC		 2925struct arm_local_iplt_info
2926{
34e77a92
RS		 2927 /* The information that is usually found in the generic ELF part of
2928 the hash table entry. */
2929 union gotplt_union root;
2930
2931 /* The information that is usually found in the ARM-specific part of
2932 the hash table entry. */
2933 struct arm_plt_info arm;
2934
2935 /* A list of all potential dynamic relocations against this symbol. */
2936 struct elf_dyn_relocs *dyn_relocs;
2937};
2938
0ffa91dd 2939struct elf_arm_obj_tdata
ba93b8ac
DJ		 2940{
2941 struct elf_obj_tdata root;
2942
2943 /* tls_type for each local got entry. */
2944 char *local_got_tls_type;
ee065d83 2945
0855e32b
NS		 2946 /* GOTPLT entries for TLS descriptors. */
2947 bfd_vma *local_tlsdesc_gotent;
2948
34e77a92
RS		 2949 /* Information for local symbols that need entries in .iplt. */
2950 struct arm_local_iplt_info **local_iplt;
2951
bf21ed78
MS		 2952 /* Zero to warn when linking objects with incompatible enum sizes. */
2953 int no_enum_size_warning;
a9dc9481
JM		 2954
2955 /* Zero to warn when linking objects with incompatible wchar_t sizes. */
2956 int no_wchar_size_warning;
ba93b8ac
DJ		 2957};
2958
0ffa91dd
NC		 2959#define elf_arm_tdata(bfd) \
2960 ((struct elf_arm_obj_tdata *) (bfd)->tdata.any)
ba93b8ac 2961
0ffa91dd
NC		 2962#define elf32_arm_local_got_tls_type(bfd) \
2963 (elf_arm_tdata (bfd)->local_got_tls_type)
2964
0855e32b
NS		 2965#define elf32_arm_local_tlsdesc_gotent(bfd) \
2966 (elf_arm_tdata (bfd)->local_tlsdesc_gotent)
2967
34e77a92
RS		 2968#define elf32_arm_local_iplt(bfd) \
2969 (elf_arm_tdata (bfd)->local_iplt)
2970
0ffa91dd
NC		 2971#define is_arm_elf(bfd) \
2972 (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
2973 && elf_tdata (bfd) != NULL \
4dfe6ac6 2974 && elf_object_id (bfd) == ARM_ELF_DATA)
ba93b8ac
DJ		 2975
2976static bfd_boolean
2977elf32_arm_mkobject (bfd *abfd)
2978{
0ffa91dd 2979 return bfd_elf_allocate_object (abfd, sizeof (struct elf_arm_obj_tdata),
4dfe6ac6 2980 ARM_ELF_DATA);
ba93b8ac
DJ		 2981}
2982
ba93b8ac
DJ		 2983#define elf32_arm_hash_entry(ent) ((struct elf32_arm_link_hash_entry *)(ent))
2984
ba96a88f 2985/* Arm ELF linker hash entry. */
252b5132 2986struct elf32_arm_link_hash_entry
b38cadfb
NC		 2987{
2988 struct elf_link_hash_entry root;
252b5132 2989
b38cadfb
NC		 2990 /* Track dynamic relocs copied for this symbol. */
2991 struct elf_dyn_relocs *dyn_relocs;
b7693d02 2992
b38cadfb
NC		 2993 /* ARM-specific PLT information. */
2994 struct arm_plt_info plt;
ba93b8ac
DJ		 2995
2996#define GOT_UNKNOWN 0
2997#define GOT_NORMAL 1
2998#define GOT_TLS_GD 2
2999#define GOT_TLS_IE 4
0855e32b
NS		 3000#define GOT_TLS_GDESC 8
3001#define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLS_GDESC))
b38cadfb 3002 unsigned int tls_type : 8;
34e77a92 3003
b38cadfb
NC		 3004 /* True if the symbol's PLT entry is in .iplt rather than .plt. */
3005 unsigned int is_iplt : 1;
34e77a92 3006
b38cadfb 3007 unsigned int unused : 23;
a4fd1a8e 3008
b38cadfb
NC		 3009 /* Offset of the GOTPLT entry reserved for the TLS descriptor,
3010 starting at the end of the jump table. */
3011 bfd_vma tlsdesc_got;
0855e32b 3012
b38cadfb
NC		 3013 /* The symbol marking the real symbol location for exported thumb
3014 symbols with Arm stubs. */
3015 struct elf_link_hash_entry *export_glue;
906e58ca 3016
b38cadfb 3017 /* A pointer to the most recently used stub hash entry against this
8029a119 3018 symbol. */
b38cadfb
NC		 3019 struct elf32_arm_stub_hash_entry *stub_cache;
3020};
252b5132 3021
252b5132 3022/* Traverse an arm ELF linker hash table. */
252b5132
RH		 3023#define elf32_arm_link_hash_traverse(table, func, info) \
3024 (elf_link_hash_traverse \
3025 (&(table)->root, \
b7693d02 3026 (bfd_boolean (*) (struct elf_link_hash_entry *, void *)) (func), \
252b5132
RH		 3027 (info)))
3028
3029/* Get the ARM elf linker hash table from a link_info structure. */
3030#define elf32_arm_hash_table(info) \
4dfe6ac6
NC		 3031 (elf_hash_table_id ((struct elf_link_hash_table *) ((info)->hash)) \
3032 == ARM_ELF_DATA ? ((struct elf32_arm_link_hash_table *) ((info)->hash)) : NULL)
252b5132 3033
906e58ca
NC		 3034#define arm_stub_hash_lookup(table, string, create, copy) \
3035 ((struct elf32_arm_stub_hash_entry *) \
3036 bfd_hash_lookup ((table), (string), (create), (copy)))
3037
21d799b5
NC		 3038/* Array to keep track of which stub sections have been created, and
3039 information on stub grouping. */
3040struct map_stub
3041{
3042 /* This is the section to which stubs in the group will be
3043 attached. */
3044 asection *link_sec;
3045 /* The stub section. */
3046 asection *stub_sec;
3047};
3048
0855e32b
NS		 3049#define elf32_arm_compute_jump_table_size(htab) \
3050 ((htab)->next_tls_desc_index * 4)
3051
9b485d32 3052/* ARM ELF linker hash table. */
252b5132 3053struct elf32_arm_link_hash_table
906e58ca
NC		 3054{
3055 /* The main hash table. */
3056 struct elf_link_hash_table root;
252b5132 3057
906e58ca
NC		 3058 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
3059 bfd_size_type thumb_glue_size;
252b5132 3060
906e58ca
NC		 3061 /* The size in bytes of the section containing the ARM-to-Thumb glue. */
3062 bfd_size_type arm_glue_size;
252b5132 3063
906e58ca
NC		 3064 /* The size in bytes of section containing the ARMv4 BX veneers. */
3065 bfd_size_type bx_glue_size;
845b51d6 3066
906e58ca
NC		 3067 /* Offsets of ARMv4 BX veneers. Bit1 set if present, and Bit0 set when
3068 veneer has been populated. */
3069 bfd_vma bx_glue_offset[15];
845b51d6 3070
906e58ca
NC		 3071 /* The size in bytes of the section containing glue for VFP11 erratum
3072 veneers. */
3073 bfd_size_type vfp11_erratum_glue_size;
c7b8f16e 3074
a504d23a
LA		 3075 /* The size in bytes of the section containing glue for STM32L4XX erratum
3076 veneers. */
3077 bfd_size_type stm32l4xx_erratum_glue_size;
3078
48229727
JB		 3079 /* A table of fix locations for Cortex-A8 Thumb-2 branch/TLB erratum. This
3080 holds Cortex-A8 erratum fix locations between elf32_arm_size_stubs() and
3081 elf32_arm_write_section(). */
3082 struct a8_erratum_fix *a8_erratum_fixes;
3083 unsigned int num_a8_erratum_fixes;
3084
906e58ca
NC		 3085 /* An arbitrary input BFD chosen to hold the glue sections. */
3086 bfd * bfd_of_glue_owner;
ba96a88f 3087
906e58ca
NC		 3088 /* Nonzero to output a BE8 image. */
3089 int byteswap_code;
e489d0ae 3090
906e58ca
NC		 3091 /* Zero if R_ARM_TARGET1 means R_ARM_ABS32.
3092 Nonzero if R_ARM_TARGET1 means R_ARM_REL32. */
3093 int target1_is_rel;
9c504268 3094
906e58ca
NC		 3095 /* The relocation to use for R_ARM_TARGET2 relocations. */
3096 int target2_reloc;
eb043451 3097
906e58ca
NC		 3098 /* 0 = Ignore R_ARM_V4BX.
3099 1 = Convert BX to MOV PC.
3100 2 = Generate v4 interworing stubs. */
3101 int fix_v4bx;
319850b4 3102
48229727
JB		 3103 /* Whether we should fix the Cortex-A8 Thumb-2 branch/TLB erratum. */
3104 int fix_cortex_a8;
3105
2de70689
MGD		 3106 /* Whether we should fix the ARM1176 BLX immediate issue. */
3107 int fix_arm1176;
3108
906e58ca
NC		 3109 /* Nonzero if the ARM/Thumb BLX instructions are available for use. */
3110 int use_blx;
33bfe774 3111
906e58ca
NC		 3112 /* What sort of code sequences we should look for which may trigger the
3113 VFP11 denorm erratum. */
3114 bfd_arm_vfp11_fix vfp11_fix;
c7b8f16e 3115
906e58ca
NC		 3116 /* Global counter for the number of fixes we have emitted. */
3117 int num_vfp11_fixes;
c7b8f16e 3118
a504d23a
LA		 3119 /* What sort of code sequences we should look for which may trigger the
3120 STM32L4XX erratum. */
3121 bfd_arm_stm32l4xx_fix stm32l4xx_fix;
3122
3123 /* Global counter for the number of fixes we have emitted. */
3124 int num_stm32l4xx_fixes;
3125
906e58ca
NC		 3126 /* Nonzero to force PIC branch veneers. */
3127 int pic_veneer;
27e55c4d 3128
906e58ca
NC		 3129 /* The number of bytes in the initial entry in the PLT. */
3130 bfd_size_type plt_header_size;
e5a52504 3131
906e58ca
NC		 3132 /* The number of bytes in the subsequent PLT etries. */
3133 bfd_size_type plt_entry_size;
e5a52504 3134
906e58ca
NC		 3135 /* True if the target system is VxWorks. */
3136 int vxworks_p;
00a97672 3137
906e58ca
NC		 3138 /* True if the target system is Symbian OS. */
3139 int symbian_p;
e5a52504 3140
b38cadfb
NC		 3141 /* True if the target system is Native Client. */
3142 int nacl_p;
3143
906e58ca
NC		 3144 /* True if the target uses REL relocations. */
3145 int use_rel;
4e7fd91e 3146
54ddd295
TP		 3147 /* Nonzero if import library must be a secure gateway import library
3148 as per ARMv8-M Security Extensions. */
3149 int cmse_implib;
3150
0955507f
TP		 3151 /* The import library whose symbols' address must remain stable in
3152 the import library generated. */
3153 bfd *in_implib_bfd;
3154
0855e32b
NS		 3155 /* The index of the next unused R_ARM_TLS_DESC slot in .rel.plt. */
3156 bfd_vma next_tls_desc_index;
3157
3158 /* How many R_ARM_TLS_DESC relocations were generated so far. */
3159 bfd_vma num_tls_desc;
3160
906e58ca
NC		 3161 /* The (unloaded but important) VxWorks .rela.plt.unloaded section. */
3162 asection *srelplt2;
00a97672 3163
0855e32b
NS		 3164 /* The offset into splt of the PLT entry for the TLS descriptor
3165 resolver. Special values are 0, if not necessary (or not found
3166 to be necessary yet), and -1 if needed but not determined
3167 yet. */
3168 bfd_vma dt_tlsdesc_plt;
3169
3170 /* The offset into sgot of the GOT entry used by the PLT entry
3171 above. */
b38cadfb 3172 bfd_vma dt_tlsdesc_got;
0855e32b
NS		 3173
3174 /* Offset in .plt section of tls_arm_trampoline. */
3175 bfd_vma tls_trampoline;
3176
906e58ca
NC		 3177 /* Data for R_ARM_TLS_LDM32 relocations. */
3178 union
3179 {
3180 bfd_signed_vma refcount;
3181 bfd_vma offset;
3182 } tls_ldm_got;
b7693d02 3183
87d72d41
AM		 3184 /* Small local sym cache. */
3185 struct sym_cache sym_cache;
906e58ca
NC		 3186
3187 /* For convenience in allocate_dynrelocs. */
3188 bfd * obfd;
3189
0855e32b
NS		 3190 /* The amount of space used by the reserved portion of the sgotplt
3191 section, plus whatever space is used by the jump slots. */
3192 bfd_vma sgotplt_jump_table_size;
3193
906e58ca
NC		 3194 /* The stub hash table. */
3195 struct bfd_hash_table stub_hash_table;
3196
3197 /* Linker stub bfd. */
3198 bfd *stub_bfd;
3199
3200 /* Linker call-backs. */
6bde4c52
TP		 3201 asection * (*add_stub_section) (const char *, asection *, asection *,
3202 unsigned int);
906e58ca
NC		 3203 void (*layout_sections_again) (void);
3204
3205 /* Array to keep track of which stub sections have been created, and
3206 information on stub grouping. */
21d799b5 3207 struct map_stub *stub_group;
906e58ca 3208
4ba2ef8f
TP		 3209 /* Input stub section holding secure gateway veneers. */
3210 asection *cmse_stub_sec;
3211
0955507f
TP		 3212 /* Offset in cmse_stub_sec where new SG veneers (not in input import library)
3213 start to be allocated. */
3214 bfd_vma new_cmse_stub_offset;
3215
fe33d2fa 3216 /* Number of elements in stub_group. */
7292b3ac 3217 unsigned int top_id;
fe33d2fa 3218
906e58ca
NC		 3219 /* Assorted information used by elf32_arm_size_stubs. */
3220 unsigned int bfd_count;
7292b3ac 3221 unsigned int top_index;
906e58ca
NC		 3222 asection **input_list;
3223};
252b5132 3224
a504d23a
LA		 3225static inline int
3226ctz (unsigned int mask)
3227{
3228#if GCC_VERSION >= 3004
3229 return __builtin_ctz (mask);
3230#else
3231 unsigned int i;
3232
3233 for (i = 0; i < 8 * sizeof (mask); i++)
3234 {
3235 if (mask & 0x1)
3236 break;
3237 mask = (mask >> 1);
3238 }
3239 return i;
3240#endif
3241}
3242
3243static inline int
b25e998d 3244elf32_arm_popcount (unsigned int mask)
a504d23a
LA		 3245{
3246#if GCC_VERSION >= 3004
3247 return __builtin_popcount (mask);
3248#else
b25e998d
CG		 3249 unsigned int i;
3250 int sum = 0;
a504d23a
LA		 3251
3252 for (i = 0; i < 8 * sizeof (mask); i++)
3253 {
3254 if (mask & 0x1)
3255 sum++;
3256 mask = (mask >> 1);
3257 }
3258 return sum;
3259#endif
3260}
3261
780a67af
NC		 3262/* Create an entry in an ARM ELF linker hash table. */
3263
3264static struct bfd_hash_entry *
57e8b36a 3265elf32_arm_link_hash_newfunc (struct bfd_hash_entry * entry,
99059e56
RM		 3266 struct bfd_hash_table * table,
3267 const char * string)
780a67af
NC		 3268{
3269 struct elf32_arm_link_hash_entry * ret =
3270 (struct elf32_arm_link_hash_entry *) entry;
3271
3272 /* Allocate the structure if it has not already been allocated by a
3273 subclass. */
906e58ca 3274 if (ret == NULL)
21d799b5 3275 ret = (struct elf32_arm_link_hash_entry *)
99059e56 3276 bfd_hash_allocate (table, sizeof (struct elf32_arm_link_hash_entry));
57e8b36a 3277 if (ret == NULL)
780a67af
NC		 3278 return (struct bfd_hash_entry *) ret;
3279
3280 /* Call the allocation method of the superclass. */
3281 ret = ((struct elf32_arm_link_hash_entry *)
3282 _bfd_elf_link_hash_newfunc ((struct bfd_hash_entry *) ret,
3283 table, string));
57e8b36a 3284 if (ret != NULL)
b7693d02 3285 {
0bdcacaf 3286 ret->dyn_relocs = NULL;
ba93b8ac 3287 ret->tls_type = GOT_UNKNOWN;
0855e32b 3288 ret->tlsdesc_got = (bfd_vma) -1;
34e77a92
RS		 3289 ret->plt.thumb_refcount = 0;
3290 ret->plt.maybe_thumb_refcount = 0;
3291 ret->plt.noncall_refcount = 0;
3292 ret->plt.got_offset = -1;
3293 ret->is_iplt = FALSE;
a4fd1a8e 3294 ret->export_glue = NULL;
906e58ca
NC		 3295
3296 ret->stub_cache = NULL;
b7693d02 3297 }
780a67af
NC		 3298
3299 return (struct bfd_hash_entry *) ret;
3300}
3301
34e77a92
RS		 3302/* Ensure that we have allocated bookkeeping structures for ABFD's local
3303 symbols. */
3304
3305static bfd_boolean
3306elf32_arm_allocate_local_sym_info (bfd *abfd)
3307{
3308 if (elf_local_got_refcounts (abfd) == NULL)
3309 {
3310 bfd_size_type num_syms;
3311 bfd_size_type size;
3312 char *data;
3313
3314 num_syms = elf_tdata (abfd)->symtab_hdr.sh_info;
3315 size = num_syms * (sizeof (bfd_signed_vma)
3316 + sizeof (struct arm_local_iplt_info *)
3317 + sizeof (bfd_vma)
3318 + sizeof (char));
3319 data = bfd_zalloc (abfd, size);
3320 if (data == NULL)
3321 return FALSE;
3322
3323 elf_local_got_refcounts (abfd) = (bfd_signed_vma *) data;
3324 data += num_syms * sizeof (bfd_signed_vma);
3325
3326 elf32_arm_local_iplt (abfd) = (struct arm_local_iplt_info **) data;
3327 data += num_syms * sizeof (struct arm_local_iplt_info *);
3328
3329 elf32_arm_local_tlsdesc_gotent (abfd) = (bfd_vma *) data;
3330 data += num_syms * sizeof (bfd_vma);
3331
3332 elf32_arm_local_got_tls_type (abfd) = data;
3333 }
3334 return TRUE;
3335}
3336
3337/* Return the .iplt information for local symbol R_SYMNDX, which belongs
3338 to input bfd ABFD. Create the information if it doesn't already exist.
3339 Return null if an allocation fails. */
3340
3341static struct arm_local_iplt_info *
3342elf32_arm_create_local_iplt (bfd *abfd, unsigned long r_symndx)
3343{
3344 struct arm_local_iplt_info **ptr;
3345
3346 if (!elf32_arm_allocate_local_sym_info (abfd))
3347 return NULL;
3348
3349 BFD_ASSERT (r_symndx < elf_tdata (abfd)->symtab_hdr.sh_info);
3350 ptr = &elf32_arm_local_iplt (abfd)[r_symndx];
3351 if (*ptr == NULL)
3352 *ptr = bfd_zalloc (abfd, sizeof (**ptr));
3353 return *ptr;
3354}
3355
3356/* Try to obtain PLT information for the symbol with index R_SYMNDX
3357 in ABFD's symbol table. If the symbol is global, H points to its
3358 hash table entry, otherwise H is null.
3359
3360 Return true if the symbol does have PLT information. When returning
3361 true, point *ROOT_PLT at the target-independent reference count/offset
3362 union and *ARM_PLT at the ARM-specific information. */
3363
3364static bfd_boolean
4ba2ef8f
TP		 3365elf32_arm_get_plt_info (bfd *abfd, struct elf32_arm_link_hash_table *globals,
3366 struct elf32_arm_link_hash_entry *h,
34e77a92
RS		 3367 unsigned long r_symndx, union gotplt_union **root_plt,
3368 struct arm_plt_info **arm_plt)
3369{
3370 struct arm_local_iplt_info *local_iplt;
3371
4ba2ef8f
TP		 3372 if (globals->root.splt == NULL && globals->root.iplt == NULL)
3373 return FALSE;
3374
34e77a92
RS		 3375 if (h != NULL)
3376 {
3377 *root_plt = &h->root.plt;
3378 *arm_plt = &h->plt;
3379 return TRUE;
3380 }
3381
3382 if (elf32_arm_local_iplt (abfd) == NULL)
3383 return FALSE;
3384
3385 local_iplt = elf32_arm_local_iplt (abfd)[r_symndx];
3386 if (local_iplt == NULL)
3387 return FALSE;
3388
3389 *root_plt = &local_iplt->root;
3390 *arm_plt = &local_iplt->arm;
3391 return TRUE;
3392}
3393
3394/* Return true if the PLT described by ARM_PLT requires a Thumb stub
3395 before it. */
3396
3397static bfd_boolean
3398elf32_arm_plt_needs_thumb_stub_p (struct bfd_link_info *info,
3399 struct arm_plt_info *arm_plt)
3400{
3401 struct elf32_arm_link_hash_table *htab;
3402
3403 htab = elf32_arm_hash_table (info);
3404 return (arm_plt->thumb_refcount != 0
3405 || (!htab->use_blx && arm_plt->maybe_thumb_refcount != 0));
3406}
3407
3408/* Return a pointer to the head of the dynamic reloc list that should
3409 be used for local symbol ISYM, which is symbol number R_SYMNDX in
3410 ABFD's symbol table. Return null if an error occurs. */
3411
3412static struct elf_dyn_relocs **
3413elf32_arm_get_local_dynreloc_list (bfd *abfd, unsigned long r_symndx,
3414 Elf_Internal_Sym *isym)
3415{
3416 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC)
3417 {
3418 struct arm_local_iplt_info *local_iplt;
3419
3420 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
3421 if (local_iplt == NULL)
3422 return NULL;
3423 return &local_iplt->dyn_relocs;
3424 }
3425 else
3426 {
3427 /* Track dynamic relocs needed for local syms too.
3428 We really need local syms available to do this
3429 easily. Oh well. */
3430 asection *s;
3431 void *vpp;
3432
3433 s = bfd_section_from_elf_index (abfd, isym->st_shndx);
3434 if (s == NULL)
3435 abort ();
3436
3437 vpp = &elf_section_data (s)->local_dynrel;
3438 return (struct elf_dyn_relocs **) vpp;
3439 }
3440}
3441
906e58ca
NC		 3442/* Initialize an entry in the stub hash table. */
3443
3444static struct bfd_hash_entry *
3445stub_hash_newfunc (struct bfd_hash_entry *entry,
3446 struct bfd_hash_table *table,
3447 const char *string)
3448{
3449 /* Allocate the structure if it has not already been allocated by a
3450 subclass. */
3451 if (entry == NULL)
3452 {
21d799b5 3453 entry = (struct bfd_hash_entry *)
99059e56 3454 bfd_hash_allocate (table, sizeof (struct elf32_arm_stub_hash_entry));
906e58ca
NC		 3455 if (entry == NULL)
3456 return entry;
3457 }
3458
3459 /* Call the allocation method of the superclass. */
3460 entry = bfd_hash_newfunc (entry, table, string);
3461 if (entry != NULL)
3462 {
3463 struct elf32_arm_stub_hash_entry *eh;
3464
3465 /* Initialize the local fields. */
3466 eh = (struct elf32_arm_stub_hash_entry *) entry;
3467 eh->stub_sec = NULL;
0955507f 3468 eh->stub_offset = (bfd_vma) -1;
8d9d9490 3469 eh->source_value = 0;
906e58ca
NC		 3470 eh->target_value = 0;
3471 eh->target_section = NULL;
cedfb179 3472 eh->orig_insn = 0;
906e58ca 3473 eh->stub_type = arm_stub_none;
461a49ca
DJ		 3474 eh->stub_size = 0;
3475 eh->stub_template = NULL;
0955507f 3476 eh->stub_template_size = -1;
906e58ca
NC		 3477 eh->h = NULL;
3478 eh->id_sec = NULL;
d8d2f433 3479 eh->output_name = NULL;
906e58ca
NC		 3480 }
3481
3482 return entry;
3483}
3484
00a97672 3485/* Create .got, .gotplt, and .rel(a).got sections in DYNOBJ, and set up
5e681ec4
PB		 3486 shortcuts to them in our hash table. */
3487
3488static bfd_boolean
57e8b36a 3489create_got_section (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3490{
3491 struct elf32_arm_link_hash_table *htab;
3492
e5a52504 3493 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3494 if (htab == NULL)
3495 return FALSE;
3496
e5a52504
MM		 3497 /* BPABI objects never have a GOT, or associated sections. */
3498 if (htab->symbian_p)
3499 return TRUE;
3500
5e681ec4
PB		 3501 if (! _bfd_elf_create_got_section (dynobj, info))
3502 return FALSE;
3503
5e681ec4
PB		 3504 return TRUE;
3505}
3506
34e77a92
RS		 3507/* Create the .iplt, .rel(a).iplt and .igot.plt sections. */
3508
3509static bfd_boolean
3510create_ifunc_sections (struct bfd_link_info *info)
3511{
3512 struct elf32_arm_link_hash_table *htab;
3513 const struct elf_backend_data *bed;
3514 bfd *dynobj;
3515 asection *s;
3516 flagword flags;
b38cadfb 3517
34e77a92
RS		 3518 htab = elf32_arm_hash_table (info);
3519 dynobj = htab->root.dynobj;
3520 bed = get_elf_backend_data (dynobj);
3521 flags = bed->dynamic_sec_flags;
3522
3523 if (htab->root.iplt == NULL)
3524 {
3d4d4302
AM		 3525 s = bfd_make_section_anyway_with_flags (dynobj, ".iplt",
3526 flags | SEC_READONLY | SEC_CODE);
34e77a92 3527 if (s == NULL
a0f49396 3528 || !bfd_set_section_alignment (dynobj, s, bed->plt_alignment))
34e77a92
RS		 3529 return FALSE;
3530 htab->root.iplt = s;
3531 }
3532
3533 if (htab->root.irelplt == NULL)
3534 {
3d4d4302
AM		 3535 s = bfd_make_section_anyway_with_flags (dynobj,
3536 RELOC_SECTION (htab, ".iplt"),
3537 flags | SEC_READONLY);
34e77a92 3538 if (s == NULL
a0f49396 3539 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
34e77a92
RS		 3540 return FALSE;
3541 htab->root.irelplt = s;
3542 }
3543
3544 if (htab->root.igotplt == NULL)
3545 {
3d4d4302 3546 s = bfd_make_section_anyway_with_flags (dynobj, ".igot.plt", flags);
34e77a92
RS		 3547 if (s == NULL
3548 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
3549 return FALSE;
3550 htab->root.igotplt = s;
3551 }
3552 return TRUE;
3553}
3554
eed94f8f
NC		 3555/* Determine if we're dealing with a Thumb only architecture. */
3556
3557static bfd_boolean
3558using_thumb_only (struct elf32_arm_link_hash_table *globals)
3559{
2fd158eb
TP		 3560 int arch;
3561 int profile = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3562 Tag_CPU_arch_profile);
eed94f8f 3563
2fd158eb
TP		 3564 if (profile)
3565 return profile == 'M';
eed94f8f 3566
2fd158eb 3567 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
eed94f8f 3568
60a019a0
TP		 3569 /* Force return logic to be reviewed for each new architecture. */
3570 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8
3571 || arch == TAG_CPU_ARCH_V8M_BASE
3572 || arch == TAG_CPU_ARCH_V8M_MAIN);
3573
2fd158eb
TP		 3574 if (arch == TAG_CPU_ARCH_V6_M
3575 || arch == TAG_CPU_ARCH_V6S_M
3576 || arch == TAG_CPU_ARCH_V7E_M
3577 || arch == TAG_CPU_ARCH_V8M_BASE
3578 || arch == TAG_CPU_ARCH_V8M_MAIN)
3579 return TRUE;
eed94f8f 3580
2fd158eb 3581 return FALSE;
eed94f8f
NC		 3582}
3583
3584/* Determine if we're dealing with a Thumb-2 object. */
3585
3586static bfd_boolean
3587using_thumb2 (struct elf32_arm_link_hash_table *globals)
3588{
60a019a0
TP		 3589 int arch;
3590 int thumb_isa = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3591 Tag_THUMB_ISA_use);
3592
3593 if (thumb_isa)
3594 return thumb_isa == 2;
3595
3596 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3597
3598 /* Force return logic to be reviewed for each new architecture. */
3599 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8
3600 || arch == TAG_CPU_ARCH_V8M_BASE
3601 || arch == TAG_CPU_ARCH_V8M_MAIN);
3602
3603 return (arch == TAG_CPU_ARCH_V6T2
3604 || arch == TAG_CPU_ARCH_V7
3605 || arch == TAG_CPU_ARCH_V7E_M
3606 || arch == TAG_CPU_ARCH_V8
3607 || arch == TAG_CPU_ARCH_V8M_MAIN);
eed94f8f
NC		 3608}
3609
5e866f5a
TP		 3610/* Determine whether Thumb-2 BL instruction is available. */
3611
3612static bfd_boolean
3613using_thumb2_bl (struct elf32_arm_link_hash_table *globals)
3614{
3615 int arch =
3616 bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3617
3618 /* Force return logic to be reviewed for each new architecture. */
3619 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8
3620 || arch == TAG_CPU_ARCH_V8M_BASE
3621 || arch == TAG_CPU_ARCH_V8M_MAIN);
3622
3623 /* Architecture was introduced after ARMv6T2 (eg. ARMv6-M). */
3624 return (arch == TAG_CPU_ARCH_V6T2
3625 || arch >= TAG_CPU_ARCH_V7);
3626}
3627
00a97672
RS		 3628/* Create .plt, .rel(a).plt, .got, .got.plt, .rel(a).got, .dynbss, and
3629 .rel(a).bss sections in DYNOBJ, and set up shortcuts to them in our
5e681ec4
PB		 3630 hash table. */
3631
3632static bfd_boolean
57e8b36a 3633elf32_arm_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3634{
3635 struct elf32_arm_link_hash_table *htab;
3636
3637 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3638 if (htab == NULL)
3639 return FALSE;
3640
362d30a1 3641 if (!htab->root.sgot && !create_got_section (dynobj, info))
5e681ec4
PB		 3642 return FALSE;
3643
3644 if (!_bfd_elf_create_dynamic_sections (dynobj, info))
3645 return FALSE;
3646
00a97672
RS		 3647 if (htab->vxworks_p)
3648 {
3649 if (!elf_vxworks_create_dynamic_sections (dynobj, info, &htab->srelplt2))
3650 return FALSE;
3651
0e1862bb 3652 if (bfd_link_pic (info))
00a97672
RS		 3653 {
3654 htab->plt_header_size = 0;
3655 htab->plt_entry_size
3656 = 4 * ARRAY_SIZE (elf32_arm_vxworks_shared_plt_entry);
3657 }
3658 else
3659 {
3660 htab->plt_header_size
3661 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt0_entry);
3662 htab->plt_entry_size
3663 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt_entry);
3664 }
aebf9be7
NC		 3665
3666 if (elf_elfheader (dynobj))
3667 elf_elfheader (dynobj)->e_ident[EI_CLASS] = ELFCLASS32;
00a97672 3668 }
eed94f8f
NC		 3669 else
3670 {
3671 /* PR ld/16017
3672 Test for thumb only architectures. Note - we cannot just call
3673 using_thumb_only() as the attributes in the output bfd have not been
3674 initialised at this point, so instead we use the input bfd. */
3675 bfd * saved_obfd = htab->obfd;
3676
3677 htab->obfd = dynobj;
3678 if (using_thumb_only (htab))
3679 {
3680 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
3681 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
3682 }
3683 htab->obfd = saved_obfd;
3684 }
5e681ec4 3685
362d30a1
RS		 3686 if (!htab->root.splt
3687 || !htab->root.srelplt
9d19e4fd
AM		 3688 || !htab->root.sdynbss
3689 || (!bfd_link_pic (info) && !htab->root.srelbss))
5e681ec4
PB		 3690 abort ();
3691
3692 return TRUE;
3693}
3694
906e58ca
NC		 3695/* Copy the extra info we tack onto an elf_link_hash_entry. */
3696
3697static void
3698elf32_arm_copy_indirect_symbol (struct bfd_link_info *info,
3699 struct elf_link_hash_entry *dir,
3700 struct elf_link_hash_entry *ind)
3701{
3702 struct elf32_arm_link_hash_entry *edir, *eind;
3703
3704 edir = (struct elf32_arm_link_hash_entry *) dir;
3705 eind = (struct elf32_arm_link_hash_entry *) ind;
3706
0bdcacaf 3707 if (eind->dyn_relocs != NULL)
906e58ca 3708 {
0bdcacaf 3709 if (edir->dyn_relocs != NULL)
906e58ca 3710 {
0bdcacaf
RS		 3711 struct elf_dyn_relocs **pp;
3712 struct elf_dyn_relocs *p;
906e58ca
NC		 3713
3714 /* Add reloc counts against the indirect sym to the direct sym
3715 list. Merge any entries against the same section. */
0bdcacaf 3716 for (pp = &eind->dyn_relocs; (p = *pp) != NULL; )
906e58ca 3717 {
0bdcacaf 3718 struct elf_dyn_relocs *q;
906e58ca 3719
0bdcacaf
RS		 3720 for (q = edir->dyn_relocs; q != NULL; q = q->next)
3721 if (q->sec == p->sec)
906e58ca
NC		 3722 {
3723 q->pc_count += p->pc_count;
3724 q->count += p->count;
3725 *pp = p->next;
3726 break;
3727 }
3728 if (q == NULL)
3729 pp = &p->next;
3730 }
0bdcacaf 3731 *pp = edir->dyn_relocs;
906e58ca
NC		 3732 }
3733
0bdcacaf
RS		 3734 edir->dyn_relocs = eind->dyn_relocs;
3735 eind->dyn_relocs = NULL;
906e58ca
NC		 3736 }
3737
3738 if (ind->root.type == bfd_link_hash_indirect)
3739 {
3740 /* Copy over PLT info. */
34e77a92
RS		 3741 edir->plt.thumb_refcount += eind->plt.thumb_refcount;
3742 eind->plt.thumb_refcount = 0;
3743 edir->plt.maybe_thumb_refcount += eind->plt.maybe_thumb_refcount;
3744 eind->plt.maybe_thumb_refcount = 0;
3745 edir->plt.noncall_refcount += eind->plt.noncall_refcount;
3746 eind->plt.noncall_refcount = 0;
3747
3748 /* We should only allocate a function to .iplt once the final
3749 symbol information is known. */
3750 BFD_ASSERT (!eind->is_iplt);
906e58ca
NC		 3751
3752 if (dir->got.refcount <= 0)
3753 {
3754 edir->tls_type = eind->tls_type;
3755 eind->tls_type = GOT_UNKNOWN;
3756 }
3757 }
3758
3759 _bfd_elf_link_hash_copy_indirect (info, dir, ind);
3760}
3761
68faa637
AM		 3762/* Destroy an ARM elf linker hash table. */
3763
3764static void
d495ab0d 3765elf32_arm_link_hash_table_free (bfd *obfd)
68faa637
AM		 3766{
3767 struct elf32_arm_link_hash_table *ret
d495ab0d 3768 = (struct elf32_arm_link_hash_table *) obfd->link.hash;
68faa637
AM		 3769
3770 bfd_hash_table_free (&ret->stub_hash_table);
d495ab0d 3771 _bfd_elf_link_hash_table_free (obfd);
68faa637
AM		 3772}
3773
906e58ca
NC		 3774/* Create an ARM elf linker hash table. */
3775
3776static struct bfd_link_hash_table *
3777elf32_arm_link_hash_table_create (bfd *abfd)
3778{
3779 struct elf32_arm_link_hash_table *ret;
3780 bfd_size_type amt = sizeof (struct elf32_arm_link_hash_table);
3781
7bf52ea2 3782 ret = (struct elf32_arm_link_hash_table *) bfd_zmalloc (amt);
906e58ca
NC		 3783 if (ret == NULL)
3784 return NULL;
3785
3786 if (!_bfd_elf_link_hash_table_init (& ret->root, abfd,
3787 elf32_arm_link_hash_newfunc,
4dfe6ac6
NC		 3788 sizeof (struct elf32_arm_link_hash_entry),
3789 ARM_ELF_DATA))
906e58ca
NC		 3790 {
3791 free (ret);
3792 return NULL;
3793 }
3794
906e58ca 3795 ret->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
a504d23a 3796 ret->stm32l4xx_fix = BFD_ARM_STM32L4XX_FIX_NONE;
906e58ca
NC		 3797#ifdef FOUR_WORD_PLT
3798 ret->plt_header_size = 16;
3799 ret->plt_entry_size = 16;
3800#else
3801 ret->plt_header_size = 20;
1db37fe6 3802 ret->plt_entry_size = elf32_arm_use_long_plt_entry ? 16 : 12;
906e58ca 3803#endif
906e58ca 3804 ret->use_rel = 1;
906e58ca 3805 ret->obfd = abfd;
906e58ca
NC		 3806
3807 if (!bfd_hash_table_init (&ret->stub_hash_table, stub_hash_newfunc,
3808 sizeof (struct elf32_arm_stub_hash_entry)))
3809 {
d495ab0d 3810 _bfd_elf_link_hash_table_free (abfd);
906e58ca
NC		 3811 return NULL;
3812 }
d495ab0d 3813 ret->root.root.hash_table_free = elf32_arm_link_hash_table_free;
906e58ca
NC		 3814
3815 return &ret->root.root;
3816}
3817
cd1dac3d
DG		 3818/* Determine what kind of NOPs are available. */
3819
3820static bfd_boolean
3821arch_has_arm_nop (struct elf32_arm_link_hash_table *globals)
3822{
3823 const int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3824 Tag_CPU_arch);
cd1dac3d 3825
60a019a0
TP		 3826 /* Force return logic to be reviewed for each new architecture. */
3827 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8
3828 || arch == TAG_CPU_ARCH_V8M_BASE
3829 || arch == TAG_CPU_ARCH_V8M_MAIN);
3830
3831 return (arch == TAG_CPU_ARCH_V6T2
3832 || arch == TAG_CPU_ARCH_V6K
3833 || arch == TAG_CPU_ARCH_V7
3834 || arch == TAG_CPU_ARCH_V8);
cd1dac3d
DG		 3835}
3836
f4ac8484
DJ		 3837static bfd_boolean
3838arm_stub_is_thumb (enum elf32_arm_stub_type stub_type)
3839{
3840 switch (stub_type)
3841 {
fea2b4d6 3842 case arm_stub_long_branch_thumb_only:
80c135e5 3843 case arm_stub_long_branch_thumb2_only:
d5a67c02 3844 case arm_stub_long_branch_thumb2_only_pure:
fea2b4d6
CL		 3845 case arm_stub_long_branch_v4t_thumb_arm:
3846 case arm_stub_short_branch_v4t_thumb_arm:
ebe24dd4 3847 case arm_stub_long_branch_v4t_thumb_arm_pic:
12352d3f 3848 case arm_stub_long_branch_v4t_thumb_tls_pic:
ebe24dd4 3849 case arm_stub_long_branch_thumb_only_pic:
4ba2ef8f 3850 case arm_stub_cmse_branch_thumb_only:
f4ac8484
DJ		 3851 return TRUE;
3852 case arm_stub_none:
3853 BFD_FAIL ();
3854 return FALSE;
3855 break;
3856 default:
3857 return FALSE;
3858 }
3859}
3860
906e58ca
NC		 3861/* Determine the type of stub needed, if any, for a call. */
3862
3863static enum elf32_arm_stub_type
3864arm_type_of_stub (struct bfd_link_info *info,
3865 asection *input_sec,
3866 const Elf_Internal_Rela *rel,
34e77a92 3867 unsigned char st_type,
35fc36a8 3868 enum arm_st_branch_type *actual_branch_type,
906e58ca 3869 struct elf32_arm_link_hash_entry *hash,
c820be07
NC		 3870 bfd_vma destination,
3871 asection *sym_sec,
3872 bfd *input_bfd,
3873 const char *name)
906e58ca
NC		 3874{
3875 bfd_vma location;
3876 bfd_signed_vma branch_offset;
3877 unsigned int r_type;
3878 struct elf32_arm_link_hash_table * globals;
5e866f5a 3879 bfd_boolean thumb2, thumb2_bl, thumb_only;
906e58ca 3880 enum elf32_arm_stub_type stub_type = arm_stub_none;
5fa9e92f 3881 int use_plt = 0;
35fc36a8 3882 enum arm_st_branch_type branch_type = *actual_branch_type;
34e77a92
RS		 3883 union gotplt_union *root_plt;
3884 struct arm_plt_info *arm_plt;
d5a67c02
AV		 3885 int arch;
3886 int thumb2_movw;
906e58ca 3887
35fc36a8 3888 if (branch_type == ST_BRANCH_LONG)
da5938a2
NC		 3889 return stub_type;
3890
906e58ca 3891 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3892 if (globals == NULL)
3893 return stub_type;
906e58ca
NC		 3894
3895 thumb_only = using_thumb_only (globals);
906e58ca 3896 thumb2 = using_thumb2 (globals);
5e866f5a 3897 thumb2_bl = using_thumb2_bl (globals);
906e58ca 3898
d5a67c02
AV		 3899 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3900
3901 /* True for architectures that implement the thumb2 movw instruction. */
3902 thumb2_movw = thumb2 || (arch == TAG_CPU_ARCH_V8M_BASE);
3903
906e58ca
NC		 3904 /* Determine where the call point is. */
3905 location = (input_sec->output_offset
3906 + input_sec->output_section->vma
3907 + rel->r_offset);
3908
906e58ca
NC		 3909 r_type = ELF32_R_TYPE (rel->r_info);
3910
39f21624
NC		 3911 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
3912 are considering a function call relocation. */
c5423981
TG		 3913 if (thumb_only && (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
3914 || r_type == R_ARM_THM_JUMP19)
39f21624
NC		 3915 && branch_type == ST_BRANCH_TO_ARM)
3916 branch_type = ST_BRANCH_TO_THUMB;
3917
34e77a92
RS		 3918 /* For TLS call relocs, it is the caller's responsibility to provide
3919 the address of the appropriate trampoline. */
3920 if (r_type != R_ARM_TLS_CALL
3921 && r_type != R_ARM_THM_TLS_CALL
4ba2ef8f
TP		 3922 && elf32_arm_get_plt_info (input_bfd, globals, hash,
3923 ELF32_R_SYM (rel->r_info), &root_plt,
3924 &arm_plt)
34e77a92 3925 && root_plt->offset != (bfd_vma) -1)
5fa9e92f 3926 {
34e77a92 3927 asection *splt;
fe33d2fa 3928
34e77a92
RS		 3929 if (hash == NULL || hash->is_iplt)
3930 splt = globals->root.iplt;
3931 else
3932 splt = globals->root.splt;
3933 if (splt != NULL)
b38cadfb 3934 {
34e77a92
RS		 3935 use_plt = 1;
3936
3937 /* Note when dealing with PLT entries: the main PLT stub is in
3938 ARM mode, so if the branch is in Thumb mode, another
3939 Thumb->ARM stub will be inserted later just before the ARM
2df2751d
CL		 3940 PLT stub. If a long branch stub is needed, we'll add a
3941 Thumb->Arm one and branch directly to the ARM PLT entry.
3942 Here, we have to check if a pre-PLT Thumb->ARM stub
3943 is needed and if it will be close enough. */
34e77a92
RS		 3944
3945 destination = (splt->output_section->vma
3946 + splt->output_offset
3947 + root_plt->offset);
3948 st_type = STT_FUNC;
2df2751d
CL		 3949
3950 /* Thumb branch/call to PLT: it can become a branch to ARM
3951 or to Thumb. We must perform the same checks and
3952 corrections as in elf32_arm_final_link_relocate. */
3953 if ((r_type == R_ARM_THM_CALL)
3954 || (r_type == R_ARM_THM_JUMP24))
3955 {
3956 if (globals->use_blx
3957 && r_type == R_ARM_THM_CALL
3958 && !thumb_only)
3959 {
3960 /* If the Thumb BLX instruction is available, convert
3961 the BL to a BLX instruction to call the ARM-mode
3962 PLT entry. */
3963 branch_type = ST_BRANCH_TO_ARM;
3964 }
3965 else
3966 {
3967 if (!thumb_only)
3968 /* Target the Thumb stub before the ARM PLT entry. */
3969 destination -= PLT_THUMB_STUB_SIZE;
3970 branch_type = ST_BRANCH_TO_THUMB;
3971 }
3972 }
3973 else
3974 {
3975 branch_type = ST_BRANCH_TO_ARM;
3976 }
34e77a92 3977 }
5fa9e92f 3978 }
34e77a92
RS		 3979 /* Calls to STT_GNU_IFUNC symbols should go through a PLT. */
3980 BFD_ASSERT (st_type != STT_GNU_IFUNC);
906e58ca 3981
fe33d2fa
CL		 3982 branch_offset = (bfd_signed_vma)(destination - location);
3983
0855e32b 3984 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
c5423981 3985 || r_type == R_ARM_THM_TLS_CALL || r_type == R_ARM_THM_JUMP19)
906e58ca 3986 {
5fa9e92f
CL		 3987 /* Handle cases where:
3988 - this call goes too far (different Thumb/Thumb2 max
99059e56 3989 distance)
155d87d7 3990 - it's a Thumb->Arm call and blx is not available, or it's a
99059e56
RM		 3991 Thumb->Arm branch (not bl). A stub is needed in this case,
3992 but only if this call is not through a PLT entry. Indeed,
695344c0 3993 PLT stubs handle mode switching already. */
5e866f5a 3994 if ((!thumb2_bl
906e58ca
NC		 3995 && (branch_offset > THM_MAX_FWD_BRANCH_OFFSET
3996 || (branch_offset < THM_MAX_BWD_BRANCH_OFFSET)))
5e866f5a 3997 || (thumb2_bl
906e58ca
NC		 3998 && (branch_offset > THM2_MAX_FWD_BRANCH_OFFSET
3999 || (branch_offset < THM2_MAX_BWD_BRANCH_OFFSET)))
c5423981
TG		 4000 || (thumb2
4001 && (branch_offset > THM2_MAX_FWD_COND_BRANCH_OFFSET
4002 || (branch_offset < THM2_MAX_BWD_COND_BRANCH_OFFSET))
4003 && (r_type == R_ARM_THM_JUMP19))
35fc36a8 4004 || (branch_type == ST_BRANCH_TO_ARM
0855e32b
NS		 4005 && (((r_type == R_ARM_THM_CALL
4006 || r_type == R_ARM_THM_TLS_CALL) && !globals->use_blx)
c5423981
TG		 4007 || (r_type == R_ARM_THM_JUMP24)
4008 || (r_type == R_ARM_THM_JUMP19))
5fa9e92f 4009 && !use_plt))
906e58ca 4010 {
2df2751d
CL		 4011 /* If we need to insert a Thumb-Thumb long branch stub to a
4012 PLT, use one that branches directly to the ARM PLT
4013 stub. If we pretended we'd use the pre-PLT Thumb->ARM
4014 stub, undo this now. */
695344c0
NC		 4015 if ((branch_type == ST_BRANCH_TO_THUMB) && use_plt && !thumb_only)
4016 {
4017 branch_type = ST_BRANCH_TO_ARM;
4018 branch_offset += PLT_THUMB_STUB_SIZE;
4019 }
2df2751d 4020
35fc36a8 4021 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4022 {
4023 /* Thumb to thumb. */
4024 if (!thumb_only)
4025 {
d5a67c02 4026 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39
AM		 4027 _bfd_error_handler
4028 (_("%B(%A): warning: long branch veneers used in"
4029 " section with SHF_ARM_PURECODE section"
4030 " attribute is only supported for M-profile"
4031 " targets that implement the movw instruction."),
4032 input_bfd, input_sec);
d5a67c02 4033
0e1862bb 4034 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4035 /* PIC stubs. */
155d87d7 4036 ? ((globals->use_blx
9553db3c 4037 && (r_type == R_ARM_THM_CALL))
155d87d7
CL		 4038 /* V5T and above. Stub starts with ARM code, so
4039 we must be able to switch mode before
4040 reaching it, which is only possible for 'bl'
4041 (ie R_ARM_THM_CALL relocation). */
cf3eccff 4042 ? arm_stub_long_branch_any_thumb_pic
ebe24dd4 4043 /* On V4T, use Thumb code only. */
d3626fb0 4044 : arm_stub_long_branch_v4t_thumb_thumb_pic)
c2b4a39d
CL		 4045
4046 /* non-PIC stubs. */
155d87d7 4047 : ((globals->use_blx
9553db3c 4048 && (r_type == R_ARM_THM_CALL))
c2b4a39d
CL		 4049 /* V5T and above. */
4050 ? arm_stub_long_branch_any_any
4051 /* V4T. */
d3626fb0 4052 : arm_stub_long_branch_v4t_thumb_thumb);
906e58ca
NC		 4053 }
4054 else
4055 {
d5a67c02
AV		 4056 if (thumb2_movw && (input_sec->flags & SEC_ELF_PURECODE))
4057 stub_type = arm_stub_long_branch_thumb2_only_pure;
4058 else
4059 {
4060 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39
AM		 4061 _bfd_error_handler
4062 (_("%B(%A): warning: long branch veneers used in"
4063 " section with SHF_ARM_PURECODE section"
4064 " attribute is only supported for M-profile"
4065 " targets that implement the movw instruction."),
4066 input_bfd, input_sec);
d5a67c02
AV		 4067
4068 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
4069 /* PIC stub. */
4070 ? arm_stub_long_branch_thumb_only_pic
4071 /* non-PIC stub. */
4072 : (thumb2 ? arm_stub_long_branch_thumb2_only
4073 : arm_stub_long_branch_thumb_only);
4074 }
906e58ca
NC		 4075 }
4076 }
4077 else
4078 {
d5a67c02 4079 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39
AM		 4080 _bfd_error_handler
4081 (_("%B(%A): warning: long branch veneers used in"
4082 " section with SHF_ARM_PURECODE section"
4083 " attribute is only supported" " for M-profile"
4084 " targets that implement the movw instruction."),
4085 input_bfd, input_sec);
d5a67c02 4086
906e58ca 4087 /* Thumb to arm. */
c820be07
NC		 4088 if (sym_sec != NULL
4089 && sym_sec->owner != NULL
4090 && !INTERWORK_FLAG (sym_sec->owner))
4091 {
4eca0228 4092 _bfd_error_handler
c820be07
NC		 4093 (_("%B(%s): warning: interworking not enabled.\n"
4094 " first occurrence: %B: Thumb call to ARM"),
c08bb8dd 4095 sym_sec->owner, name, input_bfd);
c820be07
NC		 4096 }
4097
0855e32b 4098 stub_type =
0e1862bb 4099 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4100 /* PIC stubs. */
0855e32b 4101 ? (r_type == R_ARM_THM_TLS_CALL
6a631e86 4102 /* TLS PIC stubs. */
0855e32b
NS		 4103 ? (globals->use_blx ? arm_stub_long_branch_any_tls_pic
4104 : arm_stub_long_branch_v4t_thumb_tls_pic)
4105 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
4106 /* V5T PIC and above. */
4107 ? arm_stub_long_branch_any_arm_pic
4108 /* V4T PIC stub. */
4109 : arm_stub_long_branch_v4t_thumb_arm_pic))
c2b4a39d
CL		 4110
4111 /* non-PIC stubs. */
0855e32b 4112 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
c2b4a39d
CL		 4113 /* V5T and above. */
4114 ? arm_stub_long_branch_any_any
4115 /* V4T. */
4116 : arm_stub_long_branch_v4t_thumb_arm);
c820be07
NC		 4117
4118 /* Handle v4t short branches. */
fea2b4d6 4119 if ((stub_type == arm_stub_long_branch_v4t_thumb_arm)
c820be07
NC		 4120 && (branch_offset <= THM_MAX_FWD_BRANCH_OFFSET)
4121 && (branch_offset >= THM_MAX_BWD_BRANCH_OFFSET))
fea2b4d6 4122 stub_type = arm_stub_short_branch_v4t_thumb_arm;
906e58ca
NC		 4123 }
4124 }
4125 }
fe33d2fa
CL		 4126 else if (r_type == R_ARM_CALL
4127 || r_type == R_ARM_JUMP24
0855e32b
NS		 4128 || r_type == R_ARM_PLT32
4129 || r_type == R_ARM_TLS_CALL)
906e58ca 4130 {
d5a67c02 4131 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39
AM		 4132 _bfd_error_handler
4133 (_("%B(%A): warning: long branch veneers used in"
4134 " section with SHF_ARM_PURECODE section"
4135 " attribute is only supported for M-profile"
4136 " targets that implement the movw instruction."),
4137 input_bfd, input_sec);
35fc36a8 4138 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4139 {
4140 /* Arm to thumb. */
c820be07
NC		 4141
4142 if (sym_sec != NULL
4143 && sym_sec->owner != NULL
4144 && !INTERWORK_FLAG (sym_sec->owner))
4145 {
4eca0228 4146 _bfd_error_handler
c820be07 4147 (_("%B(%s): warning: interworking not enabled.\n"
c2b4a39d 4148 " first occurrence: %B: ARM call to Thumb"),
c820be07
NC		 4149 sym_sec->owner, input_bfd, name);
4150 }
4151
4152 /* We have an extra 2-bytes reach because of
4153 the mode change (bit 24 (H) of BLX encoding). */
4116d8d7
PB		 4154 if (branch_offset > (ARM_MAX_FWD_BRANCH_OFFSET + 2)
4155 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET)
0855e32b 4156 || (r_type == R_ARM_CALL && !globals->use_blx)
4116d8d7
PB		 4157 || (r_type == R_ARM_JUMP24)
4158 || (r_type == R_ARM_PLT32))
906e58ca 4159 {
0e1862bb 4160 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4161 /* PIC stubs. */
ebe24dd4
CL		 4162 ? ((globals->use_blx)
4163 /* V5T and above. */
4164 ? arm_stub_long_branch_any_thumb_pic
4165 /* V4T stub. */
4166 : arm_stub_long_branch_v4t_arm_thumb_pic)
4167
c2b4a39d
CL		 4168 /* non-PIC stubs. */
4169 : ((globals->use_blx)
4170 /* V5T and above. */
4171 ? arm_stub_long_branch_any_any
4172 /* V4T. */
4173 : arm_stub_long_branch_v4t_arm_thumb);
906e58ca
NC		 4174 }
4175 }
4176 else
4177 {
4178 /* Arm to arm. */
4179 if (branch_offset > ARM_MAX_FWD_BRANCH_OFFSET
4180 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET))
4181 {
0855e32b 4182 stub_type =
0e1862bb 4183 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4184 /* PIC stubs. */
0855e32b 4185 ? (r_type == R_ARM_TLS_CALL
6a631e86 4186 /* TLS PIC Stub. */
0855e32b 4187 ? arm_stub_long_branch_any_tls_pic
7a89b94e
NC		 4188 : (globals->nacl_p
4189 ? arm_stub_long_branch_arm_nacl_pic
4190 : arm_stub_long_branch_any_arm_pic))
c2b4a39d 4191 /* non-PIC stubs. */
7a89b94e
NC		 4192 : (globals->nacl_p
4193 ? arm_stub_long_branch_arm_nacl
4194 : arm_stub_long_branch_any_any);
906e58ca
NC		 4195 }
4196 }
4197 }
4198
fe33d2fa
CL		 4199 /* If a stub is needed, record the actual destination type. */
4200 if (stub_type != arm_stub_none)
35fc36a8 4201 *actual_branch_type = branch_type;
fe33d2fa 4202
906e58ca
NC		 4203 return stub_type;
4204}
4205
4206/* Build a name for an entry in the stub hash table. */
4207
4208static char *
4209elf32_arm_stub_name (const asection *input_section,
4210 const asection *sym_sec,
4211 const struct elf32_arm_link_hash_entry *hash,
fe33d2fa
CL		 4212 const Elf_Internal_Rela *rel,
4213 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4214{
4215 char *stub_name;
4216 bfd_size_type len;
4217
4218 if (hash)
4219 {
fe33d2fa 4220 len = 8 + 1 + strlen (hash->root.root.root.string) + 1 + 8 + 1 + 2 + 1;
21d799b5 4221 stub_name = (char *) bfd_malloc (len);
906e58ca 4222 if (stub_name != NULL)
fe33d2fa 4223 sprintf (stub_name, "%08x_%s+%x_%d",
906e58ca
NC		 4224 input_section->id & 0xffffffff,
4225 hash->root.root.root.string,
fe33d2fa
CL		 4226 (int) rel->r_addend & 0xffffffff,
4227 (int) stub_type);
906e58ca
NC		 4228 }
4229 else
4230 {
fe33d2fa 4231 len = 8 + 1 + 8 + 1 + 8 + 1 + 8 + 1 + 2 + 1;
21d799b5 4232 stub_name = (char *) bfd_malloc (len);
906e58ca 4233 if (stub_name != NULL)
fe33d2fa 4234 sprintf (stub_name, "%08x_%x:%x+%x_%d",
906e58ca
NC		 4235 input_section->id & 0xffffffff,
4236 sym_sec->id & 0xffffffff,
0855e32b
NS		 4237 ELF32_R_TYPE (rel->r_info) == R_ARM_TLS_CALL
4238 || ELF32_R_TYPE (rel->r_info) == R_ARM_THM_TLS_CALL
4239 ? 0 : (int) ELF32_R_SYM (rel->r_info) & 0xffffffff,
fe33d2fa
CL		 4240 (int) rel->r_addend & 0xffffffff,
4241 (int) stub_type);
906e58ca
NC		 4242 }
4243
4244 return stub_name;
4245}
4246
4247/* Look up an entry in the stub hash. Stub entries are cached because
4248 creating the stub name takes a bit of time. */
4249
4250static struct elf32_arm_stub_hash_entry *
4251elf32_arm_get_stub_entry (const asection *input_section,
4252 const asection *sym_sec,
4253 struct elf_link_hash_entry *hash,
4254 const Elf_Internal_Rela *rel,
fe33d2fa
CL		 4255 struct elf32_arm_link_hash_table *htab,
4256 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4257{
4258 struct elf32_arm_stub_hash_entry *stub_entry;
4259 struct elf32_arm_link_hash_entry *h = (struct elf32_arm_link_hash_entry *) hash;
4260 const asection *id_sec;
4261
4262 if ((input_section->flags & SEC_CODE) == 0)
4263 return NULL;
4264
4265 /* If this input section is part of a group of sections sharing one
4266 stub section, then use the id of the first section in the group.
4267 Stub names need to include a section id, as there may well be
4268 more than one stub used to reach say, printf, and we need to
4269 distinguish between them. */
c2abbbeb 4270 BFD_ASSERT (input_section->id <= htab->top_id);
906e58ca
NC		 4271 id_sec = htab->stub_group[input_section->id].link_sec;
4272
4273 if (h != NULL && h->stub_cache != NULL
4274 && h->stub_cache->h == h
fe33d2fa
CL		 4275 && h->stub_cache->id_sec == id_sec
4276 && h->stub_cache->stub_type == stub_type)
906e58ca
NC		 4277 {
4278 stub_entry = h->stub_cache;
4279 }
4280 else
4281 {
4282 char *stub_name;
4283
fe33d2fa 4284 stub_name = elf32_arm_stub_name (id_sec, sym_sec, h, rel, stub_type);
906e58ca
NC		 4285 if (stub_name == NULL)
4286 return NULL;
4287
4288 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table,
4289 stub_name, FALSE, FALSE);
4290 if (h != NULL)
4291 h->stub_cache = stub_entry;
4292
4293 free (stub_name);
4294 }
4295
4296 return stub_entry;
4297}
4298
daa4adae
TP		 4299/* Whether veneers of type STUB_TYPE require to be in a dedicated output
4300 section. */
4301
4302static bfd_boolean
4303arm_dedicated_stub_output_section_required (enum elf32_arm_stub_type stub_type)
4304{
4305 if (stub_type >= max_stub_type)
4306 abort (); /* Should be unreachable. */
4307
4ba2ef8f
TP		 4308 switch (stub_type)
4309 {
4310 case arm_stub_cmse_branch_thumb_only:
4311 return TRUE;
4312
4313 default:
4314 return FALSE;
4315 }
4316
4317 abort (); /* Should be unreachable. */
daa4adae
TP		 4318}
4319
4320/* Required alignment (as a power of 2) for the dedicated section holding
4321 veneers of type STUB_TYPE, or 0 if veneers of this type are interspersed
4322 with input sections. */
4323
4324static int
4325arm_dedicated_stub_output_section_required_alignment
4326 (enum elf32_arm_stub_type stub_type)
4327{
4328 if (stub_type >= max_stub_type)
4329 abort (); /* Should be unreachable. */
4330
4ba2ef8f
TP		 4331 switch (stub_type)
4332 {
4333 /* Vectors of Secure Gateway veneers must be aligned on 32byte
4334 boundary. */
4335 case arm_stub_cmse_branch_thumb_only:
4336 return 5;
4337
4338 default:
4339 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4340 return 0;
4341 }
4342
4343 abort (); /* Should be unreachable. */
daa4adae
TP		 4344}
4345
4346/* Name of the dedicated output section to put veneers of type STUB_TYPE, or
4347 NULL if veneers of this type are interspersed with input sections. */
4348
4349static const char *
4350arm_dedicated_stub_output_section_name (enum elf32_arm_stub_type stub_type)
4351{
4352 if (stub_type >= max_stub_type)
4353 abort (); /* Should be unreachable. */
4354
4ba2ef8f
TP		 4355 switch (stub_type)
4356 {
4357 case arm_stub_cmse_branch_thumb_only:
4358 return ".gnu.sgstubs";
4359
4360 default:
4361 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4362 return NULL;
4363 }
4364
4365 abort (); /* Should be unreachable. */
daa4adae
TP		 4366}
4367
4368/* If veneers of type STUB_TYPE should go in a dedicated output section,
4369 returns the address of the hash table field in HTAB holding a pointer to the
4370 corresponding input section. Otherwise, returns NULL. */
4371
4372static asection **
4ba2ef8f
TP		 4373arm_dedicated_stub_input_section_ptr (struct elf32_arm_link_hash_table *htab,
4374 enum elf32_arm_stub_type stub_type)
daa4adae
TP		 4375{
4376 if (stub_type >= max_stub_type)
4377 abort (); /* Should be unreachable. */
4378
4ba2ef8f
TP		 4379 switch (stub_type)
4380 {
4381 case arm_stub_cmse_branch_thumb_only:
4382 return &htab->cmse_stub_sec;
4383
4384 default:
4385 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4386 return NULL;
4387 }
4388
4389 abort (); /* Should be unreachable. */
daa4adae
TP		 4390}
4391
4392/* Find or create a stub section to contain a stub of type STUB_TYPE. SECTION
4393 is the section that branch into veneer and can be NULL if stub should go in
4394 a dedicated output section. Returns a pointer to the stub section, and the
4395 section to which the stub section will be attached (in *LINK_SEC_P).
48229727 4396 LINK_SEC_P may be NULL. */
906e58ca 4397
48229727
JB		 4398static asection *
4399elf32_arm_create_or_find_stub_sec (asection **link_sec_p, asection *section,
daa4adae
TP		 4400 struct elf32_arm_link_hash_table *htab,
4401 enum elf32_arm_stub_type stub_type)
906e58ca 4402{
daa4adae
TP		 4403 asection *link_sec, *out_sec, **stub_sec_p;
4404 const char *stub_sec_prefix;
4405 bfd_boolean dedicated_output_section =
4406 arm_dedicated_stub_output_section_required (stub_type);
4407 int align;
906e58ca 4408
daa4adae 4409 if (dedicated_output_section)
906e58ca 4410 {
daa4adae
TP		 4411 bfd *output_bfd = htab->obfd;
4412 const char *out_sec_name =
4413 arm_dedicated_stub_output_section_name (stub_type);
4414 link_sec = NULL;
4415 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
4416 stub_sec_prefix = out_sec_name;
4417 align = arm_dedicated_stub_output_section_required_alignment (stub_type);
4418 out_sec = bfd_get_section_by_name (output_bfd, out_sec_name);
4419 if (out_sec == NULL)
906e58ca 4420 {
4eca0228
AM		 4421 _bfd_error_handler (_("No address assigned to the veneers output "
4422 "section %s"), out_sec_name);
daa4adae 4423 return NULL;
906e58ca 4424 }
daa4adae
TP		 4425 }
4426 else
4427 {
c2abbbeb 4428 BFD_ASSERT (section->id <= htab->top_id);
daa4adae
TP		 4429 link_sec = htab->stub_group[section->id].link_sec;
4430 BFD_ASSERT (link_sec != NULL);
4431 stub_sec_p = &htab->stub_group[section->id].stub_sec;
4432 if (*stub_sec_p == NULL)
4433 stub_sec_p = &htab->stub_group[link_sec->id].stub_sec;
4434 stub_sec_prefix = link_sec->name;
4435 out_sec = link_sec->output_section;
4436 align = htab->nacl_p ? 4 : 3;
906e58ca 4437 }
b38cadfb 4438
daa4adae
TP		 4439 if (*stub_sec_p == NULL)
4440 {
4441 size_t namelen;
4442 bfd_size_type len;
4443 char *s_name;
4444
4445 namelen = strlen (stub_sec_prefix);
4446 len = namelen + sizeof (STUB_SUFFIX);
4447 s_name = (char *) bfd_alloc (htab->stub_bfd, len);
4448 if (s_name == NULL)
4449 return NULL;
4450
4451 memcpy (s_name, stub_sec_prefix, namelen);
4452 memcpy (s_name + namelen, STUB_SUFFIX, sizeof (STUB_SUFFIX));
4453 *stub_sec_p = (*htab->add_stub_section) (s_name, out_sec, link_sec,
4454 align);
4455 if (*stub_sec_p == NULL)
4456 return NULL;
4457
4458 out_sec->flags |= SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_CODE
4459 | SEC_HAS_CONTENTS | SEC_RELOC | SEC_IN_MEMORY
4460 | SEC_KEEP;
4461 }
4462
4463 if (!dedicated_output_section)
4464 htab->stub_group[section->id].stub_sec = *stub_sec_p;
4465
48229727
JB		 4466 if (link_sec_p)
4467 *link_sec_p = link_sec;
b38cadfb 4468
daa4adae 4469 return *stub_sec_p;
48229727
JB		 4470}
4471
4472/* Add a new stub entry to the stub hash. Not all fields of the new
4473 stub entry are initialised. */
4474
4475static struct elf32_arm_stub_hash_entry *
daa4adae
TP		 4476elf32_arm_add_stub (const char *stub_name, asection *section,
4477 struct elf32_arm_link_hash_table *htab,
4478 enum elf32_arm_stub_type stub_type)
48229727
JB		 4479{
4480 asection *link_sec;
4481 asection *stub_sec;
4482 struct elf32_arm_stub_hash_entry *stub_entry;
4483
daa4adae
TP		 4484 stub_sec = elf32_arm_create_or_find_stub_sec (&link_sec, section, htab,
4485 stub_type);
48229727
JB		 4486 if (stub_sec == NULL)
4487 return NULL;
906e58ca
NC		 4488
4489 /* Enter this entry into the linker stub hash table. */
4490 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
4491 TRUE, FALSE);
4492 if (stub_entry == NULL)
4493 {
6bde4c52
TP		 4494 if (section == NULL)
4495 section = stub_sec;
dae82561 4496 _bfd_error_handler (_("%B: cannot create stub entry %s"),
4eca0228 4497 section->owner, stub_name);
906e58ca
NC		 4498 return NULL;
4499 }
4500
4501 stub_entry->stub_sec = stub_sec;
0955507f 4502 stub_entry->stub_offset = (bfd_vma) -1;
906e58ca
NC		 4503 stub_entry->id_sec = link_sec;
4504
906e58ca
NC		 4505 return stub_entry;
4506}
4507
4508/* Store an Arm insn into an output section not processed by
4509 elf32_arm_write_section. */
4510
4511static void
8029a119
NC		 4512put_arm_insn (struct elf32_arm_link_hash_table * htab,
4513 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4514{
4515 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4516 bfd_putl32 (val, ptr);
4517 else
4518 bfd_putb32 (val, ptr);
4519}
4520
4521/* Store a 16-bit Thumb insn into an output section not processed by
4522 elf32_arm_write_section. */
4523
4524static void
8029a119
NC		 4525put_thumb_insn (struct elf32_arm_link_hash_table * htab,
4526 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4527{
4528 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4529 bfd_putl16 (val, ptr);
4530 else
4531 bfd_putb16 (val, ptr);
4532}
4533
a504d23a
LA		 4534/* Store a Thumb2 insn into an output section not processed by
4535 elf32_arm_write_section. */
4536
4537static void
4538put_thumb2_insn (struct elf32_arm_link_hash_table * htab,
b98e6871 4539 bfd * output_bfd, bfd_vma val, bfd_byte * ptr)
a504d23a
LA		 4540{
4541 /* T2 instructions are 16-bit streamed. */
4542 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4543 {
4544 bfd_putl16 ((val >> 16) & 0xffff, ptr);
4545 bfd_putl16 ((val & 0xffff), ptr + 2);
4546 }
4547 else
4548 {
4549 bfd_putb16 ((val >> 16) & 0xffff, ptr);
4550 bfd_putb16 ((val & 0xffff), ptr + 2);
4551 }
4552}
4553
0855e32b
NS		 4554/* If it's possible to change R_TYPE to a more efficient access
4555 model, return the new reloc type. */
4556
4557static unsigned
b38cadfb 4558elf32_arm_tls_transition (struct bfd_link_info *info, int r_type,
0855e32b
NS		 4559 struct elf_link_hash_entry *h)
4560{
4561 int is_local = (h == NULL);
4562
0e1862bb
L		 4563 if (bfd_link_pic (info)
4564 || (h && h->root.type == bfd_link_hash_undefweak))
0855e32b
NS		 4565 return r_type;
4566
b38cadfb 4567 /* We do not support relaxations for Old TLS models. */
0855e32b
NS		 4568 switch (r_type)
4569 {
4570 case R_ARM_TLS_GOTDESC:
4571 case R_ARM_TLS_CALL:
4572 case R_ARM_THM_TLS_CALL:
4573 case R_ARM_TLS_DESCSEQ:
4574 case R_ARM_THM_TLS_DESCSEQ:
4575 return is_local ? R_ARM_TLS_LE32 : R_ARM_TLS_IE32;
4576 }
4577
4578 return r_type;
4579}
4580
48229727
JB		 4581static bfd_reloc_status_type elf32_arm_final_link_relocate
4582 (reloc_howto_type *, bfd *, bfd *, asection *, bfd_byte *,
4583 Elf_Internal_Rela *, bfd_vma, struct bfd_link_info *, asection *,
34e77a92
RS		 4584 const char *, unsigned char, enum arm_st_branch_type,
4585 struct elf_link_hash_entry *, bfd_boolean *, char **);
48229727 4586
4563a860
JB		 4587static unsigned int
4588arm_stub_required_alignment (enum elf32_arm_stub_type stub_type)
4589{
4590 switch (stub_type)
4591 {
4592 case arm_stub_a8_veneer_b_cond:
4593 case arm_stub_a8_veneer_b:
4594 case arm_stub_a8_veneer_bl:
4595 return 2;
4596
4597 case arm_stub_long_branch_any_any:
4598 case arm_stub_long_branch_v4t_arm_thumb:
4599 case arm_stub_long_branch_thumb_only:
80c135e5 4600 case arm_stub_long_branch_thumb2_only:
d5a67c02 4601 case arm_stub_long_branch_thumb2_only_pure:
4563a860
JB		 4602 case arm_stub_long_branch_v4t_thumb_thumb:
4603 case arm_stub_long_branch_v4t_thumb_arm:
4604 case arm_stub_short_branch_v4t_thumb_arm:
4605 case arm_stub_long_branch_any_arm_pic:
4606 case arm_stub_long_branch_any_thumb_pic:
4607 case arm_stub_long_branch_v4t_thumb_thumb_pic:
4608 case arm_stub_long_branch_v4t_arm_thumb_pic:
4609 case arm_stub_long_branch_v4t_thumb_arm_pic:
4610 case arm_stub_long_branch_thumb_only_pic:
0855e32b
NS		 4611 case arm_stub_long_branch_any_tls_pic:
4612 case arm_stub_long_branch_v4t_thumb_tls_pic:
4ba2ef8f 4613 case arm_stub_cmse_branch_thumb_only:
4563a860
JB		 4614 case arm_stub_a8_veneer_blx:
4615 return 4;
b38cadfb 4616
7a89b94e
NC		 4617 case arm_stub_long_branch_arm_nacl:
4618 case arm_stub_long_branch_arm_nacl_pic:
4619 return 16;
4620
4563a860
JB		 4621 default:
4622 abort (); /* Should be unreachable. */
4623 }
4624}
4625
4f4faa4d
TP		 4626/* Returns whether stubs of type STUB_TYPE take over the symbol they are
4627 veneering (TRUE) or have their own symbol (FALSE). */
4628
4629static bfd_boolean
4630arm_stub_sym_claimed (enum elf32_arm_stub_type stub_type)
4631{
4632 if (stub_type >= max_stub_type)
4633 abort (); /* Should be unreachable. */
4634
4ba2ef8f
TP		 4635 switch (stub_type)
4636 {
4637 case arm_stub_cmse_branch_thumb_only:
4638 return TRUE;
4639
4640 default:
4641 return FALSE;
4642 }
4643
4644 abort (); /* Should be unreachable. */
4f4faa4d
TP		 4645}
4646
d7c5bd02
TP		 4647/* Returns the padding needed for the dedicated section used stubs of type
4648 STUB_TYPE. */
4649
4650static int
4651arm_dedicated_stub_section_padding (enum elf32_arm_stub_type stub_type)
4652{
4653 if (stub_type >= max_stub_type)
4654 abort (); /* Should be unreachable. */
4655
4ba2ef8f
TP		 4656 switch (stub_type)
4657 {
4658 case arm_stub_cmse_branch_thumb_only:
4659 return 32;
4660
4661 default:
4662 return 0;
4663 }
4664
4665 abort (); /* Should be unreachable. */
d7c5bd02
TP		 4666}
4667
0955507f
TP		 4668/* If veneers of type STUB_TYPE should go in a dedicated output section,
4669 returns the address of the hash table field in HTAB holding the offset at
4670 which new veneers should be layed out in the stub section. */
4671
4672static bfd_vma*
4673arm_new_stubs_start_offset_ptr (struct elf32_arm_link_hash_table *htab,
4674 enum elf32_arm_stub_type stub_type)
4675{
4676 switch (stub_type)
4677 {
4678 case arm_stub_cmse_branch_thumb_only:
4679 return &htab->new_cmse_stub_offset;
4680
4681 default:
4682 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4683 return NULL;
4684 }
4685}
4686
906e58ca
NC		 4687static bfd_boolean
4688arm_build_one_stub (struct bfd_hash_entry *gen_entry,
4689 void * in_arg)
4690{
7a89b94e 4691#define MAXRELOCS 3
0955507f 4692 bfd_boolean removed_sg_veneer;
906e58ca 4693 struct elf32_arm_stub_hash_entry *stub_entry;
4dfe6ac6 4694 struct elf32_arm_link_hash_table *globals;
906e58ca 4695 struct bfd_link_info *info;
906e58ca
NC		 4696 asection *stub_sec;
4697 bfd *stub_bfd;
906e58ca
NC		 4698 bfd_byte *loc;
4699 bfd_vma sym_value;
4700 int template_size;
4701 int size;
d3ce72d0 4702 const insn_sequence *template_sequence;
906e58ca 4703 int i;
48229727
JB		 4704 int stub_reloc_idx[MAXRELOCS] = {-1, -1};
4705 int stub_reloc_offset[MAXRELOCS] = {0, 0};
4706 int nrelocs = 0;
0955507f 4707 int just_allocated = 0;
906e58ca
NC		 4708
4709 /* Massage our args to the form they really have. */
4710 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
4711 info = (struct bfd_link_info *) in_arg;
4712
4713 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 4714 if (globals == NULL)
4715 return FALSE;
906e58ca 4716
906e58ca
NC		 4717 stub_sec = stub_entry->stub_sec;
4718
4dfe6ac6 4719 if ((globals->fix_cortex_a8 < 0)
4563a860
JB		 4720 != (arm_stub_required_alignment (stub_entry->stub_type) == 2))
4721 /* We have to do less-strictly-aligned fixes last. */
eb7c4339 4722 return TRUE;
fe33d2fa 4723
0955507f
TP		 4724 /* Assign a slot at the end of section if none assigned yet. */
4725 if (stub_entry->stub_offset == (bfd_vma) -1)
4726 {
4727 stub_entry->stub_offset = stub_sec->size;
4728 just_allocated = 1;
4729 }
906e58ca
NC		 4730 loc = stub_sec->contents + stub_entry->stub_offset;
4731
4732 stub_bfd = stub_sec->owner;
4733
906e58ca
NC		 4734 /* This is the address of the stub destination. */
4735 sym_value = (stub_entry->target_value
4736 + stub_entry->target_section->output_offset
4737 + stub_entry->target_section->output_section->vma);
4738
d3ce72d0 4739 template_sequence = stub_entry->stub_template;
461a49ca 4740 template_size = stub_entry->stub_template_size;
906e58ca
NC		 4741
4742 size = 0;
461a49ca 4743 for (i = 0; i < template_size; i++)
906e58ca 4744 {
d3ce72d0 4745 switch (template_sequence[i].type)
461a49ca
DJ		 4746 {
4747 case THUMB16_TYPE:
48229727 4748 {
d3ce72d0
NC		 4749 bfd_vma data = (bfd_vma) template_sequence[i].data;
4750 if (template_sequence[i].reloc_addend != 0)
48229727 4751 {
99059e56
RM		 4752 /* We've borrowed the reloc_addend field to mean we should
4753 insert a condition code into this (Thumb-1 branch)
4754 instruction. See THUMB16_BCOND_INSN. */
4755 BFD_ASSERT ((data & 0xff00) == 0xd000);
4756 data |= ((stub_entry->orig_insn >> 22) & 0xf) << 8;
48229727 4757 }
fe33d2fa 4758 bfd_put_16 (stub_bfd, data, loc + size);
48229727
JB		 4759 size += 2;
4760 }
461a49ca 4761 break;
906e58ca 4762
48229727 4763 case THUMB32_TYPE:
fe33d2fa
CL		 4764 bfd_put_16 (stub_bfd,
4765 (template_sequence[i].data >> 16) & 0xffff,
4766 loc + size);
4767 bfd_put_16 (stub_bfd, template_sequence[i].data & 0xffff,
4768 loc + size + 2);
99059e56
RM		 4769 if (template_sequence[i].r_type != R_ARM_NONE)
4770 {
4771 stub_reloc_idx[nrelocs] = i;
4772 stub_reloc_offset[nrelocs++] = size;
4773 }
4774 size += 4;
4775 break;
48229727 4776
461a49ca 4777 case ARM_TYPE:
fe33d2fa
CL		 4778 bfd_put_32 (stub_bfd, template_sequence[i].data,
4779 loc + size);
461a49ca
DJ		 4780 /* Handle cases where the target is encoded within the
4781 instruction. */
d3ce72d0 4782 if (template_sequence[i].r_type == R_ARM_JUMP24)
461a49ca 4783 {
48229727
JB		 4784 stub_reloc_idx[nrelocs] = i;
4785 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 4786 }
4787 size += 4;
4788 break;
4789
4790 case DATA_TYPE:
d3ce72d0 4791 bfd_put_32 (stub_bfd, template_sequence[i].data, loc + size);
48229727
JB		 4792 stub_reloc_idx[nrelocs] = i;
4793 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 4794 size += 4;
4795 break;
4796
4797 default:
4798 BFD_FAIL ();
4799 return FALSE;
4800 }
906e58ca 4801 }
461a49ca 4802
0955507f
TP		 4803 if (just_allocated)
4804 stub_sec->size += size;
906e58ca 4805
461a49ca
DJ		 4806 /* Stub size has already been computed in arm_size_one_stub. Check
4807 consistency. */
4808 BFD_ASSERT (size == stub_entry->stub_size);
4809
906e58ca 4810 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
35fc36a8 4811 if (stub_entry->branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4812 sym_value |= 1;
4813
0955507f
TP		 4814 /* Assume non empty slots have at least one and at most MAXRELOCS entries
4815 to relocate in each stub. */
4816 removed_sg_veneer =
4817 (size == 0 && stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
4818 BFD_ASSERT (removed_sg_veneer || (nrelocs != 0 && nrelocs <= MAXRELOCS));
c820be07 4819
48229727 4820 for (i = 0; i < nrelocs; i++)
8d9d9490
TP		 4821 {
4822 Elf_Internal_Rela rel;
4823 bfd_boolean unresolved_reloc;
4824 char *error_message;
4825 bfd_vma points_to =
4826 sym_value + template_sequence[stub_reloc_idx[i]].reloc_addend;
4827
4828 rel.r_offset = stub_entry->stub_offset + stub_reloc_offset[i];
4829 rel.r_info = ELF32_R_INFO (0,
4830 template_sequence[stub_reloc_idx[i]].r_type);
4831 rel.r_addend = 0;
4832
4833 if (stub_entry->stub_type == arm_stub_a8_veneer_b_cond && i == 0)
4834 /* The first relocation in the elf32_arm_stub_a8_veneer_b_cond[]
4835 template should refer back to the instruction after the original
4836 branch. We use target_section as Cortex-A8 erratum workaround stubs
4837 are only generated when both source and target are in the same
4838 section. */
4839 points_to = stub_entry->target_section->output_section->vma
4840 + stub_entry->target_section->output_offset
4841 + stub_entry->source_value;
4842
4843 elf32_arm_final_link_relocate (elf32_arm_howto_from_type
4844 (template_sequence[stub_reloc_idx[i]].r_type),
4845 stub_bfd, info->output_bfd, stub_sec, stub_sec->contents, &rel,
4846 points_to, info, stub_entry->target_section, "", STT_FUNC,
4847 stub_entry->branch_type,
4848 (struct elf_link_hash_entry *) stub_entry->h, &unresolved_reloc,
4849 &error_message);
4850 }
906e58ca
NC		 4851
4852 return TRUE;
48229727 4853#undef MAXRELOCS
906e58ca
NC		 4854}
4855
48229727
JB		 4856/* Calculate the template, template size and instruction size for a stub.
4857 Return value is the instruction size. */
906e58ca 4858
48229727
JB		 4859static unsigned int
4860find_stub_size_and_template (enum elf32_arm_stub_type stub_type,
4861 const insn_sequence **stub_template,
4862 int *stub_template_size)
906e58ca 4863{
d3ce72d0 4864 const insn_sequence *template_sequence = NULL;
48229727
JB		 4865 int template_size = 0, i;
4866 unsigned int size;
906e58ca 4867
d3ce72d0 4868 template_sequence = stub_definitions[stub_type].template_sequence;
2a229407
AM		 4869 if (stub_template)
4870 *stub_template = template_sequence;
4871
48229727 4872 template_size = stub_definitions[stub_type].template_size;
2a229407
AM		 4873 if (stub_template_size)
4874 *stub_template_size = template_size;
906e58ca
NC		 4875
4876 size = 0;
461a49ca
DJ		 4877 for (i = 0; i < template_size; i++)
4878 {
d3ce72d0 4879 switch (template_sequence[i].type)
461a49ca
DJ		 4880 {
4881 case THUMB16_TYPE:
4882 size += 2;
4883 break;
4884
4885 case ARM_TYPE:
48229727 4886 case THUMB32_TYPE:
461a49ca
DJ		 4887 case DATA_TYPE:
4888 size += 4;
4889 break;
4890
4891 default:
4892 BFD_FAIL ();
2a229407 4893 return 0;
461a49ca
DJ		 4894 }
4895 }
4896
48229727
JB		 4897 return size;
4898}
4899
4900/* As above, but don't actually build the stub. Just bump offset so
4901 we know stub section sizes. */
4902
4903static bfd_boolean
4904arm_size_one_stub (struct bfd_hash_entry *gen_entry,
c7e2358a 4905 void *in_arg ATTRIBUTE_UNUSED)
48229727
JB		 4906{
4907 struct elf32_arm_stub_hash_entry *stub_entry;
d3ce72d0 4908 const insn_sequence *template_sequence;
48229727
JB		 4909 int template_size, size;
4910
4911 /* Massage our args to the form they really have. */
4912 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
48229727
JB		 4913
4914 BFD_ASSERT((stub_entry->stub_type > arm_stub_none)
4915 && stub_entry->stub_type < ARRAY_SIZE(stub_definitions));
4916
d3ce72d0 4917 size = find_stub_size_and_template (stub_entry->stub_type, &template_sequence,
48229727
JB		 4918 &template_size);
4919
0955507f
TP		 4920 /* Initialized to -1. Null size indicates an empty slot full of zeros. */
4921 if (stub_entry->stub_template_size)
4922 {
4923 stub_entry->stub_size = size;
4924 stub_entry->stub_template = template_sequence;
4925 stub_entry->stub_template_size = template_size;
4926 }
4927
4928 /* Already accounted for. */
4929 if (stub_entry->stub_offset != (bfd_vma) -1)
4930 return TRUE;
461a49ca 4931
906e58ca
NC		 4932 size = (size + 7) & ~7;
4933 stub_entry->stub_sec->size += size;
461a49ca 4934
906e58ca
NC		 4935 return TRUE;
4936}
4937
4938/* External entry points for sizing and building linker stubs. */
4939
4940/* Set up various things so that we can make a list of input sections
4941 for each output section included in the link. Returns -1 on error,
4942 0 when no stubs will be needed, and 1 on success. */
4943
4944int
4945elf32_arm_setup_section_lists (bfd *output_bfd,
4946 struct bfd_link_info *info)
4947{
4948 bfd *input_bfd;
4949 unsigned int bfd_count;
7292b3ac 4950 unsigned int top_id, top_index;
906e58ca
NC		 4951 asection *section;
4952 asection **input_list, **list;
4953 bfd_size_type amt;
4954 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
4955
4dfe6ac6
NC		 4956 if (htab == NULL)
4957 return 0;
906e58ca
NC		 4958 if (! is_elf_hash_table (htab))
4959 return 0;
4960
4961 /* Count the number of input BFDs and find the top input section id. */
4962 for (input_bfd = info->input_bfds, bfd_count = 0, top_id = 0;
4963 input_bfd != NULL;
c72f2fb2 4964 input_bfd = input_bfd->link.next)
906e58ca
NC		 4965 {
4966 bfd_count += 1;
4967 for (section = input_bfd->sections;
4968 section != NULL;
4969 section = section->next)
4970 {
4971 if (top_id < section->id)
4972 top_id = section->id;
4973 }
4974 }
4975 htab->bfd_count = bfd_count;
4976
4977 amt = sizeof (struct map_stub) * (top_id + 1);
21d799b5 4978 htab->stub_group = (struct map_stub *) bfd_zmalloc (amt);
906e58ca
NC		 4979 if (htab->stub_group == NULL)
4980 return -1;
fe33d2fa 4981 htab->top_id = top_id;
906e58ca
NC		 4982
4983 /* We can't use output_bfd->section_count here to find the top output
4984 section index as some sections may have been removed, and
4985 _bfd_strip_section_from_output doesn't renumber the indices. */
4986 for (section = output_bfd->sections, top_index = 0;
4987 section != NULL;
4988 section = section->next)
4989 {
4990 if (top_index < section->index)
4991 top_index = section->index;
4992 }
4993
4994 htab->top_index = top_index;
4995 amt = sizeof (asection *) * (top_index + 1);
21d799b5 4996 input_list = (asection **) bfd_malloc (amt);
906e58ca
NC		 4997 htab->input_list = input_list;
4998 if (input_list == NULL)
4999 return -1;
5000
5001 /* For sections we aren't interested in, mark their entries with a
5002 value we can check later. */
5003 list = input_list + top_index;
5004 do
5005 *list = bfd_abs_section_ptr;
5006 while (list-- != input_list);
5007
5008 for (section = output_bfd->sections;
5009 section != NULL;
5010 section = section->next)
5011 {
5012 if ((section->flags & SEC_CODE) != 0)
5013 input_list[section->index] = NULL;
5014 }
5015
5016 return 1;
5017}
5018
5019/* The linker repeatedly calls this function for each input section,
5020 in the order that input sections are linked into output sections.
5021 Build lists of input sections to determine groupings between which
5022 we may insert linker stubs. */
5023
5024void
5025elf32_arm_next_input_section (struct bfd_link_info *info,
5026 asection *isec)
5027{
5028 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5029
4dfe6ac6
NC		 5030 if (htab == NULL)
5031 return;
5032
906e58ca
NC		 5033 if (isec->output_section->index <= htab->top_index)
5034 {
5035 asection **list = htab->input_list + isec->output_section->index;
5036
a7470592 5037 if (*list != bfd_abs_section_ptr && (isec->flags & SEC_CODE) != 0)
906e58ca
NC		 5038 {
5039 /* Steal the link_sec pointer for our list. */
5040#define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
5041 /* This happens to make the list in reverse order,
07d72278 5042 which we reverse later. */
906e58ca
NC		 5043 PREV_SEC (isec) = *list;
5044 *list = isec;
5045 }
5046 }
5047}
5048
5049/* See whether we can group stub sections together. Grouping stub
5050 sections may result in fewer stubs. More importantly, we need to
07d72278 5051 put all .init* and .fini* stubs at the end of the .init or
906e58ca
NC		 5052 .fini output sections respectively, because glibc splits the
5053 _init and _fini functions into multiple parts. Putting a stub in
5054 the middle of a function is not a good idea. */
5055
5056static void
5057group_sections (struct elf32_arm_link_hash_table *htab,
5058 bfd_size_type stub_group_size,
07d72278 5059 bfd_boolean stubs_always_after_branch)
906e58ca 5060{
07d72278 5061 asection **list = htab->input_list;
906e58ca
NC		 5062
5063 do
5064 {
5065 asection *tail = *list;
07d72278 5066 asection *head;
906e58ca
NC		 5067
5068 if (tail == bfd_abs_section_ptr)
5069 continue;
5070
07d72278
DJ		 5071 /* Reverse the list: we must avoid placing stubs at the
5072 beginning of the section because the beginning of the text
5073 section may be required for an interrupt vector in bare metal
5074 code. */
5075#define NEXT_SEC PREV_SEC
e780aef2
CL		 5076 head = NULL;
5077 while (tail != NULL)
99059e56
RM		 5078 {
5079 /* Pop from tail. */
5080 asection *item = tail;
5081 tail = PREV_SEC (item);
e780aef2 5082
99059e56
RM		 5083 /* Push on head. */
5084 NEXT_SEC (item) = head;
5085 head = item;
5086 }
07d72278
DJ		 5087
5088 while (head != NULL)
906e58ca
NC		 5089 {
5090 asection *curr;
07d72278 5091 asection *next;
e780aef2
CL		 5092 bfd_vma stub_group_start = head->output_offset;
5093 bfd_vma end_of_next;
906e58ca 5094
07d72278 5095 curr = head;
e780aef2 5096 while (NEXT_SEC (curr) != NULL)
8cd931b7 5097 {
e780aef2
CL		 5098 next = NEXT_SEC (curr);
5099 end_of_next = next->output_offset + next->size;
5100 if (end_of_next - stub_group_start >= stub_group_size)
5101 /* End of NEXT is too far from start, so stop. */
8cd931b7 5102 break;
e780aef2
CL		 5103 /* Add NEXT to the group. */
5104 curr = next;
8cd931b7 5105 }
906e58ca 5106
07d72278 5107 /* OK, the size from the start to the start of CURR is less
906e58ca 5108 than stub_group_size and thus can be handled by one stub
07d72278 5109 section. (Or the head section is itself larger than
906e58ca
NC		 5110 stub_group_size, in which case we may be toast.)
5111 We should really be keeping track of the total size of
5112 stubs added here, as stubs contribute to the final output
7fb9f789 5113 section size. */
906e58ca
NC		 5114 do
5115 {
07d72278 5116 next = NEXT_SEC (head);
906e58ca 5117 /* Set up this stub group. */
07d72278 5118 htab->stub_group[head->id].link_sec = curr;
906e58ca 5119 }
07d72278 5120 while (head != curr && (head = next) != NULL);
906e58ca
NC		 5121
5122 /* But wait, there's more! Input sections up to stub_group_size
07d72278
DJ		 5123 bytes after the stub section can be handled by it too. */
5124 if (!stubs_always_after_branch)
906e58ca 5125 {
e780aef2
CL		 5126 stub_group_start = curr->output_offset + curr->size;
5127
8cd931b7 5128 while (next != NULL)
906e58ca 5129 {
e780aef2
CL		 5130 end_of_next = next->output_offset + next->size;
5131 if (end_of_next - stub_group_start >= stub_group_size)
5132 /* End of NEXT is too far from stubs, so stop. */
8cd931b7 5133 break;
e780aef2 5134 /* Add NEXT to the stub group. */
07d72278
DJ		 5135 head = next;
5136 next = NEXT_SEC (head);
5137 htab->stub_group[head->id].link_sec = curr;
906e58ca
NC		 5138 }
5139 }
07d72278 5140 head = next;
906e58ca
NC		 5141 }
5142 }
07d72278 5143 while (list++ != htab->input_list + htab->top_index);
906e58ca
NC		 5144
5145 free (htab->input_list);
5146#undef PREV_SEC
07d72278 5147#undef NEXT_SEC
906e58ca
NC		 5148}
5149
48229727
JB		 5150/* Comparison function for sorting/searching relocations relating to Cortex-A8
5151 erratum fix. */
5152
5153static int
5154a8_reloc_compare (const void *a, const void *b)
5155{
21d799b5
NC		 5156 const struct a8_erratum_reloc *ra = (const struct a8_erratum_reloc *) a;
5157 const struct a8_erratum_reloc *rb = (const struct a8_erratum_reloc *) b;
48229727
JB		 5158
5159 if (ra->from < rb->from)
5160 return -1;
5161 else if (ra->from > rb->from)
5162 return 1;
5163 else
5164 return 0;
5165}
5166
5167static struct elf_link_hash_entry *find_thumb_glue (struct bfd_link_info *,
5168 const char *, char **);
5169
5170/* Helper function to scan code for sequences which might trigger the Cortex-A8
5171 branch/TLB erratum. Fill in the table described by A8_FIXES_P,
81694485 5172 NUM_A8_FIXES_P, A8_FIX_TABLE_SIZE_P. Returns true if an error occurs, false
48229727
JB		 5173 otherwise. */
5174
81694485
NC		 5175static bfd_boolean
5176cortex_a8_erratum_scan (bfd *input_bfd,
5177 struct bfd_link_info *info,
48229727
JB		 5178 struct a8_erratum_fix **a8_fixes_p,
5179 unsigned int *num_a8_fixes_p,
5180 unsigned int *a8_fix_table_size_p,
5181 struct a8_erratum_reloc *a8_relocs,
eb7c4339
NS		 5182 unsigned int num_a8_relocs,
5183 unsigned prev_num_a8_fixes,
5184 bfd_boolean *stub_changed_p)
48229727
JB		 5185{
5186 asection *section;
5187 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5188 struct a8_erratum_fix *a8_fixes = *a8_fixes_p;
5189 unsigned int num_a8_fixes = *num_a8_fixes_p;
5190 unsigned int a8_fix_table_size = *a8_fix_table_size_p;
5191
4dfe6ac6
NC		 5192 if (htab == NULL)
5193 return FALSE;
5194
48229727
JB		 5195 for (section = input_bfd->sections;
5196 section != NULL;
5197 section = section->next)
5198 {
5199 bfd_byte *contents = NULL;
5200 struct _arm_elf_section_data *sec_data;
5201 unsigned int span;
5202 bfd_vma base_vma;
5203
5204 if (elf_section_type (section) != SHT_PROGBITS
99059e56
RM		 5205 || (elf_section_flags (section) & SHF_EXECINSTR) == 0
5206 || (section->flags & SEC_EXCLUDE) != 0
5207 || (section->sec_info_type == SEC_INFO_TYPE_JUST_SYMS)
5208 || (section->output_section == bfd_abs_section_ptr))
5209 continue;
48229727
JB		 5210
5211 base_vma = section->output_section->vma + section->output_offset;
5212
5213 if (elf_section_data (section)->this_hdr.contents != NULL)
99059e56 5214 contents = elf_section_data (section)->this_hdr.contents;
48229727 5215 else if (! bfd_malloc_and_get_section (input_bfd, section, &contents))
99059e56 5216 return TRUE;
48229727
JB		 5217
5218 sec_data = elf32_arm_section_data (section);
5219
5220 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 5221 {
5222 unsigned int span_start = sec_data->map[span].vma;
5223 unsigned int span_end = (span == sec_data->mapcount - 1)
5224 ? section->size : sec_data->map[span + 1].vma;
5225 unsigned int i;
5226 char span_type = sec_data->map[span].type;
5227 bfd_boolean last_was_32bit = FALSE, last_was_branch = FALSE;
5228
5229 if (span_type != 't')
5230 continue;
5231
5232 /* Span is entirely within a single 4KB region: skip scanning. */
5233 if (((base_vma + span_start) & ~0xfff)
48229727 5234 == ((base_vma + span_end) & ~0xfff))
99059e56
RM		 5235 continue;
5236
5237 /* Scan for 32-bit Thumb-2 branches which span two 4K regions, where:
5238
5239 * The opcode is BLX.W, BL.W, B.W, Bcc.W
5240 * The branch target is in the same 4KB region as the
5241 first half of the branch.
5242 * The instruction before the branch is a 32-bit
5243 length non-branch instruction. */
5244 for (i = span_start; i < span_end;)
5245 {
5246 unsigned int insn = bfd_getl16 (&contents[i]);
5247 bfd_boolean insn_32bit = FALSE, is_blx = FALSE, is_b = FALSE;
48229727
JB		 5248 bfd_boolean is_bl = FALSE, is_bcc = FALSE, is_32bit_branch;
5249
99059e56
RM		 5250 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
5251 insn_32bit = TRUE;
48229727
JB		 5252
5253 if (insn_32bit)
99059e56
RM		 5254 {
5255 /* Load the rest of the insn (in manual-friendly order). */
5256 insn = (insn << 16) | bfd_getl16 (&contents[i + 2]);
5257
5258 /* Encoding T4: B<c>.W. */
5259 is_b = (insn & 0xf800d000) == 0xf0009000;
5260 /* Encoding T1: BL<c>.W. */
5261 is_bl = (insn & 0xf800d000) == 0xf000d000;
5262 /* Encoding T2: BLX<c>.W. */
5263 is_blx = (insn & 0xf800d000) == 0xf000c000;
48229727
JB		 5264 /* Encoding T3: B<c>.W (not permitted in IT block). */
5265 is_bcc = (insn & 0xf800d000) == 0xf0008000
5266 && (insn & 0x07f00000) != 0x03800000;
5267 }
5268
5269 is_32bit_branch = is_b || is_bl || is_blx || is_bcc;
fe33d2fa 5270
99059e56 5271 if (((base_vma + i) & 0xfff) == 0xffe
81694485
NC		 5272 && insn_32bit
5273 && is_32bit_branch
5274 && last_was_32bit
5275 && ! last_was_branch)
99059e56
RM		 5276 {
5277 bfd_signed_vma offset = 0;
5278 bfd_boolean force_target_arm = FALSE;
48229727 5279 bfd_boolean force_target_thumb = FALSE;
99059e56
RM		 5280 bfd_vma target;
5281 enum elf32_arm_stub_type stub_type = arm_stub_none;
5282 struct a8_erratum_reloc key, *found;
5283 bfd_boolean use_plt = FALSE;
48229727 5284
99059e56
RM		 5285 key.from = base_vma + i;
5286 found = (struct a8_erratum_reloc *)
5287 bsearch (&key, a8_relocs, num_a8_relocs,
5288 sizeof (struct a8_erratum_reloc),
5289 &a8_reloc_compare);
48229727
JB		 5290
5291 if (found)
5292 {
5293 char *error_message = NULL;
5294 struct elf_link_hash_entry *entry;
5295
5296 /* We don't care about the error returned from this
99059e56 5297 function, only if there is glue or not. */
48229727
JB		 5298 entry = find_thumb_glue (info, found->sym_name,
5299 &error_message);
5300
5301 if (entry)
5302 found->non_a8_stub = TRUE;
5303
92750f34 5304 /* Keep a simpler condition, for the sake of clarity. */
362d30a1 5305 if (htab->root.splt != NULL && found->hash != NULL
92750f34
DJ		 5306 && found->hash->root.plt.offset != (bfd_vma) -1)
5307 use_plt = TRUE;
5308
5309 if (found->r_type == R_ARM_THM_CALL)
5310 {
35fc36a8
RS		 5311 if (found->branch_type == ST_BRANCH_TO_ARM
5312 || use_plt)
92750f34
DJ		 5313 force_target_arm = TRUE;
5314 else
5315 force_target_thumb = TRUE;
5316 }
48229727
JB		 5317 }
5318
99059e56 5319 /* Check if we have an offending branch instruction. */
48229727
JB		 5320
5321 if (found && found->non_a8_stub)
5322 /* We've already made a stub for this instruction, e.g.
5323 it's a long branch or a Thumb->ARM stub. Assume that
5324 stub will suffice to work around the A8 erratum (see
5325 setting of always_after_branch above). */
5326 ;
99059e56
RM		 5327 else if (is_bcc)
5328 {
5329 offset = (insn & 0x7ff) << 1;
5330 offset |= (insn & 0x3f0000) >> 4;
5331 offset |= (insn & 0x2000) ? 0x40000 : 0;
5332 offset |= (insn & 0x800) ? 0x80000 : 0;
5333 offset |= (insn & 0x4000000) ? 0x100000 : 0;
5334 if (offset & 0x100000)
5335 offset |= ~ ((bfd_signed_vma) 0xfffff);
5336 stub_type = arm_stub_a8_veneer_b_cond;
5337 }
5338 else if (is_b || is_bl || is_blx)
5339 {
5340 int s = (insn & 0x4000000) != 0;
5341 int j1 = (insn & 0x2000) != 0;
5342 int j2 = (insn & 0x800) != 0;
5343 int i1 = !(j1 ^ s);
5344 int i2 = !(j2 ^ s);
5345
5346 offset = (insn & 0x7ff) << 1;
5347 offset |= (insn & 0x3ff0000) >> 4;
5348 offset |= i2 << 22;
5349 offset |= i1 << 23;
5350 offset |= s << 24;
5351 if (offset & 0x1000000)
5352 offset |= ~ ((bfd_signed_vma) 0xffffff);
5353
5354 if (is_blx)
5355 offset &= ~ ((bfd_signed_vma) 3);
5356
5357 stub_type = is_blx ? arm_stub_a8_veneer_blx :
5358 is_bl ? arm_stub_a8_veneer_bl : arm_stub_a8_veneer_b;
5359 }
5360
5361 if (stub_type != arm_stub_none)
5362 {
5363 bfd_vma pc_for_insn = base_vma + i + 4;
48229727
JB		 5364
5365 /* The original instruction is a BL, but the target is
99059e56 5366 an ARM instruction. If we were not making a stub,
48229727
JB		 5367 the BL would have been converted to a BLX. Use the
5368 BLX stub instead in that case. */
5369 if (htab->use_blx && force_target_arm
5370 && stub_type == arm_stub_a8_veneer_bl)
5371 {
5372 stub_type = arm_stub_a8_veneer_blx;
5373 is_blx = TRUE;
5374 is_bl = FALSE;
5375 }
5376 /* Conversely, if the original instruction was
5377 BLX but the target is Thumb mode, use the BL
5378 stub. */
5379 else if (force_target_thumb
5380 && stub_type == arm_stub_a8_veneer_blx)
5381 {
5382 stub_type = arm_stub_a8_veneer_bl;
5383 is_blx = FALSE;
5384 is_bl = TRUE;
5385 }
5386
99059e56
RM		 5387 if (is_blx)
5388 pc_for_insn &= ~ ((bfd_vma) 3);
48229727 5389
99059e56
RM		 5390 /* If we found a relocation, use the proper destination,
5391 not the offset in the (unrelocated) instruction.
48229727
JB		 5392 Note this is always done if we switched the stub type
5393 above. */
99059e56
RM		 5394 if (found)
5395 offset =
81694485 5396 (bfd_signed_vma) (found->destination - pc_for_insn);
48229727 5397
99059e56
RM		 5398 /* If the stub will use a Thumb-mode branch to a
5399 PLT target, redirect it to the preceding Thumb
5400 entry point. */
5401 if (stub_type != arm_stub_a8_veneer_blx && use_plt)
5402 offset -= PLT_THUMB_STUB_SIZE;
7d24e6a6 5403
99059e56 5404 target = pc_for_insn + offset;
48229727 5405
99059e56
RM		 5406 /* The BLX stub is ARM-mode code. Adjust the offset to
5407 take the different PC value (+8 instead of +4) into
48229727 5408 account. */
99059e56
RM		 5409 if (stub_type == arm_stub_a8_veneer_blx)
5410 offset += 4;
5411
5412 if (((base_vma + i) & ~0xfff) == (target & ~0xfff))
5413 {
5414 char *stub_name = NULL;
5415
5416 if (num_a8_fixes == a8_fix_table_size)
5417 {
5418 a8_fix_table_size *= 2;
5419 a8_fixes = (struct a8_erratum_fix *)
5420 bfd_realloc (a8_fixes,
5421 sizeof (struct a8_erratum_fix)
5422 * a8_fix_table_size);
5423 }
48229727 5424
eb7c4339
NS		 5425 if (num_a8_fixes < prev_num_a8_fixes)
5426 {
5427 /* If we're doing a subsequent scan,
5428 check if we've found the same fix as
5429 before, and try and reuse the stub
5430 name. */
5431 stub_name = a8_fixes[num_a8_fixes].stub_name;
5432 if ((a8_fixes[num_a8_fixes].section != section)
5433 || (a8_fixes[num_a8_fixes].offset != i))
5434 {
5435 free (stub_name);
5436 stub_name = NULL;
5437 *stub_changed_p = TRUE;
5438 }
5439 }
5440
5441 if (!stub_name)
5442 {
21d799b5 5443 stub_name = (char *) bfd_malloc (8 + 1 + 8 + 1);
eb7c4339
NS		 5444 if (stub_name != NULL)
5445 sprintf (stub_name, "%x:%x", section->id, i);
5446 }
48229727 5447
99059e56
RM		 5448 a8_fixes[num_a8_fixes].input_bfd = input_bfd;
5449 a8_fixes[num_a8_fixes].section = section;
5450 a8_fixes[num_a8_fixes].offset = i;
8d9d9490
TP		 5451 a8_fixes[num_a8_fixes].target_offset =
5452 target - base_vma;
99059e56
RM		 5453 a8_fixes[num_a8_fixes].orig_insn = insn;
5454 a8_fixes[num_a8_fixes].stub_name = stub_name;
5455 a8_fixes[num_a8_fixes].stub_type = stub_type;
5456 a8_fixes[num_a8_fixes].branch_type =
35fc36a8 5457 is_blx ? ST_BRANCH_TO_ARM : ST_BRANCH_TO_THUMB;
48229727 5458
99059e56
RM		 5459 num_a8_fixes++;
5460 }
5461 }
5462 }
48229727 5463
99059e56
RM		 5464 i += insn_32bit ? 4 : 2;
5465 last_was_32bit = insn_32bit;
48229727 5466 last_was_branch = is_32bit_branch;
99059e56
RM		 5467 }
5468 }
48229727
JB		 5469
5470 if (elf_section_data (section)->this_hdr.contents == NULL)
99059e56 5471 free (contents);
48229727 5472 }
fe33d2fa 5473
48229727
JB		 5474 *a8_fixes_p = a8_fixes;
5475 *num_a8_fixes_p = num_a8_fixes;
5476 *a8_fix_table_size_p = a8_fix_table_size;
fe33d2fa 5477
81694485 5478 return FALSE;
48229727
JB		 5479}
5480
b715f643
TP		 5481/* Create or update a stub entry depending on whether the stub can already be
5482 found in HTAB. The stub is identified by:
5483 - its type STUB_TYPE
5484 - its source branch (note that several can share the same stub) whose
5485 section and relocation (if any) are given by SECTION and IRELA
5486 respectively
5487 - its target symbol whose input section, hash, name, value and branch type
5488 are given in SYM_SEC, HASH, SYM_NAME, SYM_VALUE and BRANCH_TYPE
5489 respectively
5490
5491 If found, the value of the stub's target symbol is updated from SYM_VALUE
5492 and *NEW_STUB is set to FALSE. Otherwise, *NEW_STUB is set to
5493 TRUE and the stub entry is initialized.
5494
0955507f
TP		 5495 Returns the stub that was created or updated, or NULL if an error
5496 occurred. */
b715f643 5497
0955507f 5498static struct elf32_arm_stub_hash_entry *
b715f643
TP		 5499elf32_arm_create_stub (struct elf32_arm_link_hash_table *htab,
5500 enum elf32_arm_stub_type stub_type, asection *section,
5501 Elf_Internal_Rela *irela, asection *sym_sec,
5502 struct elf32_arm_link_hash_entry *hash, char *sym_name,
5503 bfd_vma sym_value, enum arm_st_branch_type branch_type,
5504 bfd_boolean *new_stub)
5505{
5506 const asection *id_sec;
5507 char *stub_name;
5508 struct elf32_arm_stub_hash_entry *stub_entry;
5509 unsigned int r_type;
4f4faa4d 5510 bfd_boolean sym_claimed = arm_stub_sym_claimed (stub_type);
b715f643
TP		 5511
5512 BFD_ASSERT (stub_type != arm_stub_none);
5513 *new_stub = FALSE;
5514
4f4faa4d
TP		 5515 if (sym_claimed)
5516 stub_name = sym_name;
5517 else
5518 {
5519 BFD_ASSERT (irela);
5520 BFD_ASSERT (section);
c2abbbeb 5521 BFD_ASSERT (section->id <= htab->top_id);
b715f643 5522
4f4faa4d
TP		 5523 /* Support for grouping stub sections. */
5524 id_sec = htab->stub_group[section->id].link_sec;
b715f643 5525
4f4faa4d
TP		 5526 /* Get the name of this stub. */
5527 stub_name = elf32_arm_stub_name (id_sec, sym_sec, hash, irela,
5528 stub_type);
5529 if (!stub_name)
0955507f 5530 return NULL;
4f4faa4d 5531 }
b715f643
TP		 5532
5533 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name, FALSE,
5534 FALSE);
5535 /* The proper stub has already been created, just update its value. */
5536 if (stub_entry != NULL)
5537 {
4f4faa4d
TP		 5538 if (!sym_claimed)
5539 free (stub_name);
b715f643 5540 stub_entry->target_value = sym_value;
0955507f 5541 return stub_entry;
b715f643
TP		 5542 }
5543
daa4adae 5544 stub_entry = elf32_arm_add_stub (stub_name, section, htab, stub_type);
b715f643
TP		 5545 if (stub_entry == NULL)
5546 {
4f4faa4d
TP		 5547 if (!sym_claimed)
5548 free (stub_name);
0955507f 5549 return NULL;
b715f643
TP		 5550 }
5551
5552 stub_entry->target_value = sym_value;
5553 stub_entry->target_section = sym_sec;
5554 stub_entry->stub_type = stub_type;
5555 stub_entry->h = hash;
5556 stub_entry->branch_type = branch_type;
5557
4f4faa4d
TP		 5558 if (sym_claimed)
5559 stub_entry->output_name = sym_name;
5560 else
b715f643 5561 {
4f4faa4d
TP		 5562 if (sym_name == NULL)
5563 sym_name = "unnamed";
5564 stub_entry->output_name = (char *)
5565 bfd_alloc (htab->stub_bfd, sizeof (THUMB2ARM_GLUE_ENTRY_NAME)
5566 + strlen (sym_name));
5567 if (stub_entry->output_name == NULL)
5568 {
5569 free (stub_name);
0955507f 5570 return NULL;
4f4faa4d 5571 }
b715f643 5572
4f4faa4d
TP		 5573 /* For historical reasons, use the existing names for ARM-to-Thumb and
5574 Thumb-to-ARM stubs. */
5575 r_type = ELF32_R_TYPE (irela->r_info);
5576 if ((r_type == (unsigned int) R_ARM_THM_CALL
5577 || r_type == (unsigned int) R_ARM_THM_JUMP24
5578 || r_type == (unsigned int) R_ARM_THM_JUMP19)
5579 && branch_type == ST_BRANCH_TO_ARM)
5580 sprintf (stub_entry->output_name, THUMB2ARM_GLUE_ENTRY_NAME, sym_name);
5581 else if ((r_type == (unsigned int) R_ARM_CALL
5582 || r_type == (unsigned int) R_ARM_JUMP24)
5583 && branch_type == ST_BRANCH_TO_THUMB)
5584 sprintf (stub_entry->output_name, ARM2THUMB_GLUE_ENTRY_NAME, sym_name);
5585 else
5586 sprintf (stub_entry->output_name, STUB_ENTRY_NAME, sym_name);
5587 }
b715f643
TP		 5588
5589 *new_stub = TRUE;
0955507f 5590 return stub_entry;
b715f643
TP		 5591}
5592
4ba2ef8f
TP		 5593/* Scan symbols in INPUT_BFD to identify secure entry functions needing a
5594 gateway veneer to transition from non secure to secure state and create them
5595 accordingly.
5596
5597 "ARMv8-M Security Extensions: Requirements on Development Tools" document
5598 defines the conditions that govern Secure Gateway veneer creation for a
5599 given symbol <SYM> as follows:
5600 - it has function type
5601 - it has non local binding
5602 - a symbol named __acle_se_<SYM> (called special symbol) exists with the
5603 same type, binding and value as <SYM> (called normal symbol).
5604 An entry function can handle secure state transition itself in which case
5605 its special symbol would have a different value from the normal symbol.
5606
5607 OUT_ATTR gives the output attributes, SYM_HASHES the symbol index to hash
5608 entry mapping while HTAB gives the name to hash entry mapping.
0955507f
TP		 5609 *CMSE_STUB_CREATED is increased by the number of secure gateway veneer
5610 created.
4ba2ef8f 5611
0955507f 5612 The return value gives whether a stub failed to be allocated. */
4ba2ef8f
TP		 5613
5614static bfd_boolean
5615cmse_scan (bfd *input_bfd, struct elf32_arm_link_hash_table *htab,
5616 obj_attribute *out_attr, struct elf_link_hash_entry **sym_hashes,
0955507f 5617 int *cmse_stub_created)
4ba2ef8f
TP		 5618{
5619 const struct elf_backend_data *bed;
5620 Elf_Internal_Shdr *symtab_hdr;
5621 unsigned i, j, sym_count, ext_start;
5622 Elf_Internal_Sym *cmse_sym, *local_syms;
5623 struct elf32_arm_link_hash_entry *hash, *cmse_hash = NULL;
5624 enum arm_st_branch_type branch_type;
5625 char *sym_name, *lsym_name;
5626 bfd_vma sym_value;
5627 asection *section;
0955507f
TP		 5628 struct elf32_arm_stub_hash_entry *stub_entry;
5629 bfd_boolean is_v8m, new_stub, cmse_invalid, ret = TRUE;
4ba2ef8f
TP		 5630
5631 bed = get_elf_backend_data (input_bfd);
5632 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
5633 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
5634 ext_start = symtab_hdr->sh_info;
5635 is_v8m = (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
5636 && out_attr[Tag_CPU_arch_profile].i == 'M');
5637
5638 local_syms = (Elf_Internal_Sym *) symtab_hdr->contents;
5639 if (local_syms == NULL)
5640 local_syms = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
5641 symtab_hdr->sh_info, 0, NULL, NULL,
5642 NULL);
5643 if (symtab_hdr->sh_info && local_syms == NULL)
5644 return FALSE;
5645
5646 /* Scan symbols. */
5647 for (i = 0; i < sym_count; i++)
5648 {
5649 cmse_invalid = FALSE;
5650
5651 if (i < ext_start)
5652 {
5653 cmse_sym = &local_syms[i];
5654 /* Not a special symbol. */
5655 if (!ARM_GET_SYM_CMSE_SPCL (cmse_sym->st_target_internal))
5656 continue;
5657 sym_name = bfd_elf_string_from_elf_section (input_bfd,
5658 symtab_hdr->sh_link,
5659 cmse_sym->st_name);
5660 /* Special symbol with local binding. */
5661 cmse_invalid = TRUE;
5662 }
5663 else
5664 {
5665 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
5666 sym_name = (char *) cmse_hash->root.root.root.string;
5667
5668 /* Not a special symbol. */
5669 if (!ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
5670 continue;
5671
5672 /* Special symbol has incorrect binding or type. */
5673 if ((cmse_hash->root.root.type != bfd_link_hash_defined
5674 && cmse_hash->root.root.type != bfd_link_hash_defweak)
5675 || cmse_hash->root.type != STT_FUNC)
5676 cmse_invalid = TRUE;
5677 }
5678
5679 if (!is_v8m)
5680 {
4eca0228
AM		 5681 _bfd_error_handler (_("%B: Special symbol `%s' only allowed for "
5682 "ARMv8-M architecture or later."),
5683 input_bfd, sym_name);
4ba2ef8f
TP		 5684 is_v8m = TRUE; /* Avoid multiple warning. */
5685 ret = FALSE;
5686 }
5687
5688 if (cmse_invalid)
5689 {
4eca0228
AM		 5690 _bfd_error_handler (_("%B: invalid special symbol `%s'."),
5691 input_bfd, sym_name);
5692 _bfd_error_handler (_("It must be a global or weak function "
5693 "symbol."));
4ba2ef8f
TP		 5694 ret = FALSE;
5695 if (i < ext_start)
5696 continue;
5697 }
5698
5699 sym_name += strlen (CMSE_PREFIX);
5700 hash = (struct elf32_arm_link_hash_entry *)
5701 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
5702
5703 /* No associated normal symbol or it is neither global nor weak. */
5704 if (!hash
5705 || (hash->root.root.type != bfd_link_hash_defined
5706 && hash->root.root.type != bfd_link_hash_defweak)
5707 || hash->root.type != STT_FUNC)
5708 {
5709 /* Initialize here to avoid warning about use of possibly
5710 uninitialized variable. */
5711 j = 0;
5712
5713 if (!hash)
5714 {
5715 /* Searching for a normal symbol with local binding. */
5716 for (; j < ext_start; j++)
5717 {
5718 lsym_name =
5719 bfd_elf_string_from_elf_section (input_bfd,
5720 symtab_hdr->sh_link,
5721 local_syms[j].st_name);
5722 if (!strcmp (sym_name, lsym_name))
5723 break;
5724 }
5725 }
5726
5727 if (hash || j < ext_start)
5728 {
4eca0228 5729 _bfd_error_handler
4ba2ef8f 5730 (_("%B: invalid standard symbol `%s'."), input_bfd, sym_name);
4eca0228 5731 _bfd_error_handler
4ba2ef8f
TP		 5732 (_("It must be a global or weak function symbol."));
5733 }
5734 else
4eca0228 5735 _bfd_error_handler
4ba2ef8f
TP		 5736 (_("%B: absent standard symbol `%s'."), input_bfd, sym_name);
5737 ret = FALSE;
5738 if (!hash)
5739 continue;
5740 }
5741
5742 sym_value = hash->root.root.u.def.value;
5743 section = hash->root.root.u.def.section;
5744
5745 if (cmse_hash->root.root.u.def.section != section)
5746 {
4eca0228 5747 _bfd_error_handler
4ba2ef8f
TP		 5748 (_("%B: `%s' and its special symbol are in different sections."),
5749 input_bfd, sym_name);
5750 ret = FALSE;
5751 }
5752 if (cmse_hash->root.root.u.def.value != sym_value)
5753 continue; /* Ignore: could be an entry function starting with SG. */
5754
5755 /* If this section is a link-once section that will be discarded, then
5756 don't create any stubs. */
5757 if (section->output_section == NULL)
5758 {
4eca0228 5759 _bfd_error_handler
4ba2ef8f
TP		 5760 (_("%B: entry function `%s' not output."), input_bfd, sym_name);
5761 continue;
5762 }
5763
5764 if (hash->root.size == 0)
5765 {
4eca0228 5766 _bfd_error_handler
4ba2ef8f
TP		 5767 (_("%B: entry function `%s' is empty."), input_bfd, sym_name);
5768 ret = FALSE;
5769 }
5770
5771 if (!ret)
5772 continue;
5773 branch_type = ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
0955507f 5774 stub_entry
4ba2ef8f
TP		 5775 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
5776 NULL, NULL, section, hash, sym_name,
5777 sym_value, branch_type, &new_stub);
5778
0955507f 5779 if (stub_entry == NULL)
4ba2ef8f
TP		 5780 ret = FALSE;
5781 else
5782 {
5783 BFD_ASSERT (new_stub);
0955507f 5784 (*cmse_stub_created)++;
4ba2ef8f
TP		 5785 }
5786 }
5787
5788 if (!symtab_hdr->contents)
5789 free (local_syms);
5790 return ret;
5791}
5792
0955507f
TP		 5793/* Return TRUE iff a symbol identified by its linker HASH entry is a secure
5794 code entry function, ie can be called from non secure code without using a
5795 veneer. */
5796
5797static bfd_boolean
5798cmse_entry_fct_p (struct elf32_arm_link_hash_entry *hash)
5799{
42484486 5800 bfd_byte contents[4];
0955507f
TP		 5801 uint32_t first_insn;
5802 asection *section;
5803 file_ptr offset;
5804 bfd *abfd;
5805
5806 /* Defined symbol of function type. */
5807 if (hash->root.root.type != bfd_link_hash_defined
5808 && hash->root.root.type != bfd_link_hash_defweak)
5809 return FALSE;
5810 if (hash->root.type != STT_FUNC)
5811 return FALSE;
5812
5813 /* Read first instruction. */
5814 section = hash->root.root.u.def.section;
5815 abfd = section->owner;
5816 offset = hash->root.root.u.def.value - section->vma;
42484486
TP		 5817 if (!bfd_get_section_contents (abfd, section, contents, offset,
5818 sizeof (contents)))
0955507f
TP		 5819 return FALSE;
5820
42484486
TP		 5821 first_insn = bfd_get_32 (abfd, contents);
5822
5823 /* Starts by SG instruction. */
0955507f
TP		 5824 return first_insn == 0xe97fe97f;
5825}
5826
5827/* Output the name (in symbol table) of the veneer GEN_ENTRY if it is a new
5828 secure gateway veneers (ie. the veneers was not in the input import library)
5829 and there is no output import library (GEN_INFO->out_implib_bfd is NULL. */
5830
5831static bfd_boolean
5832arm_list_new_cmse_stub (struct bfd_hash_entry *gen_entry, void *gen_info)
5833{
5834 struct elf32_arm_stub_hash_entry *stub_entry;
5835 struct bfd_link_info *info;
5836
5837 /* Massage our args to the form they really have. */
5838 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
5839 info = (struct bfd_link_info *) gen_info;
5840
5841 if (info->out_implib_bfd)
5842 return TRUE;
5843
5844 if (stub_entry->stub_type != arm_stub_cmse_branch_thumb_only)
5845 return TRUE;
5846
5847 if (stub_entry->stub_offset == (bfd_vma) -1)
4eca0228 5848 _bfd_error_handler (" %s", stub_entry->output_name);
0955507f
TP		 5849
5850 return TRUE;
5851}
5852
5853/* Set offset of each secure gateway veneers so that its address remain
5854 identical to the one in the input import library referred by
5855 HTAB->in_implib_bfd. A warning is issued for veneers that disappeared
5856 (present in input import library but absent from the executable being
5857 linked) or if new veneers appeared and there is no output import library
5858 (INFO->out_implib_bfd is NULL and *CMSE_STUB_CREATED is bigger than the
5859 number of secure gateway veneers found in the input import library.
5860
5861 The function returns whether an error occurred. If no error occurred,
5862 *CMSE_STUB_CREATED gives the number of SG veneers created by both cmse_scan
5863 and this function and HTAB->new_cmse_stub_offset is set to the biggest
5864 veneer observed set for new veneers to be layed out after. */
5865
5866static bfd_boolean
5867set_cmse_veneer_addr_from_implib (struct bfd_link_info *info,
5868 struct elf32_arm_link_hash_table *htab,
5869 int *cmse_stub_created)
5870{
5871 long symsize;
5872 char *sym_name;
5873 flagword flags;
5874 long i, symcount;
5875 bfd *in_implib_bfd;
5876 asection *stub_out_sec;
5877 bfd_boolean ret = TRUE;
5878 Elf_Internal_Sym *intsym;
5879 const char *out_sec_name;
5880 bfd_size_type cmse_stub_size;
5881 asymbol **sympp = NULL, *sym;
5882 struct elf32_arm_link_hash_entry *hash;
5883 const insn_sequence *cmse_stub_template;
5884 struct elf32_arm_stub_hash_entry *stub_entry;
5885 int cmse_stub_template_size, new_cmse_stubs_created = *cmse_stub_created;
5886 bfd_vma veneer_value, stub_offset, next_cmse_stub_offset;
5887 bfd_vma cmse_stub_array_start = (bfd_vma) -1, cmse_stub_sec_vma = 0;
5888
5889 /* No input secure gateway import library. */
5890 if (!htab->in_implib_bfd)
5891 return TRUE;
5892
5893 in_implib_bfd = htab->in_implib_bfd;
5894 if (!htab->cmse_implib)
5895 {
4eca0228
AM		 5896 _bfd_error_handler (_("%B: --in-implib only supported for Secure "
5897 "Gateway import libraries."), in_implib_bfd);
0955507f
TP		 5898 return FALSE;
5899 }
5900
5901 /* Get symbol table size. */
5902 symsize = bfd_get_symtab_upper_bound (in_implib_bfd);
5903 if (symsize < 0)
5904 return FALSE;
5905
5906 /* Read in the input secure gateway import library's symbol table. */
5907 sympp = (asymbol **) xmalloc (symsize);
5908 symcount = bfd_canonicalize_symtab (in_implib_bfd, sympp);
5909 if (symcount < 0)
5910 {
5911 ret = FALSE;
5912 goto free_sym_buf;
5913 }
5914
5915 htab->new_cmse_stub_offset = 0;
5916 cmse_stub_size =
5917 find_stub_size_and_template (arm_stub_cmse_branch_thumb_only,
5918 &cmse_stub_template,
5919 &cmse_stub_template_size);
5920 out_sec_name =
5921 arm_dedicated_stub_output_section_name (arm_stub_cmse_branch_thumb_only);
5922 stub_out_sec =
5923 bfd_get_section_by_name (htab->obfd, out_sec_name);
5924 if (stub_out_sec != NULL)
5925 cmse_stub_sec_vma = stub_out_sec->vma;
5926
5927 /* Set addresses of veneers mentionned in input secure gateway import
5928 library's symbol table. */
5929 for (i = 0; i < symcount; i++)
5930 {
5931 sym = sympp[i];
5932 flags = sym->flags;
5933 sym_name = (char *) bfd_asymbol_name (sym);
5934 intsym = &((elf_symbol_type *) sym)->internal_elf_sym;
5935
5936 if (sym->section != bfd_abs_section_ptr
5937 || !(flags & (BSF_GLOBAL | BSF_WEAK))
5938 || (flags & BSF_FUNCTION) != BSF_FUNCTION
5939 || (ARM_GET_SYM_BRANCH_TYPE (intsym->st_target_internal)
5940 != ST_BRANCH_TO_THUMB))
5941 {
4eca0228
AM		 5942 _bfd_error_handler (_("%B: invalid import library entry: `%s'."),
5943 in_implib_bfd, sym_name);
5944 _bfd_error_handler (_("Symbol should be absolute, global and "
5945 "refer to Thumb functions."));
0955507f
TP		 5946 ret = FALSE;
5947 continue;
5948 }
5949
5950 veneer_value = bfd_asymbol_value (sym);
5951 stub_offset = veneer_value - cmse_stub_sec_vma;
5952 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, sym_name,
5953 FALSE, FALSE);
5954 hash = (struct elf32_arm_link_hash_entry *)
5955 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
5956
5957 /* Stub entry should have been created by cmse_scan or the symbol be of
5958 a secure function callable from non secure code. */
5959 if (!stub_entry && !hash)
5960 {
5961 bfd_boolean new_stub;
5962
4eca0228 5963 _bfd_error_handler
0955507f
TP		 5964 (_("Entry function `%s' disappeared from secure code."), sym_name);
5965 hash = (struct elf32_arm_link_hash_entry *)
5966 elf_link_hash_lookup (&(htab)->root, sym_name, TRUE, TRUE, TRUE);
5967 stub_entry
5968 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
5969 NULL, NULL, bfd_abs_section_ptr, hash,
5970 sym_name, veneer_value,
5971 ST_BRANCH_TO_THUMB, &new_stub);
5972 if (stub_entry == NULL)
5973 ret = FALSE;
5974 else
5975 {
5976 BFD_ASSERT (new_stub);
5977 new_cmse_stubs_created++;
5978 (*cmse_stub_created)++;
5979 }
5980 stub_entry->stub_template_size = stub_entry->stub_size = 0;
5981 stub_entry->stub_offset = stub_offset;
5982 }
5983 /* Symbol found is not callable from non secure code. */
5984 else if (!stub_entry)
5985 {
5986 if (!cmse_entry_fct_p (hash))
5987 {
4eca0228
AM		 5988 _bfd_error_handler (_("`%s' refers to a non entry function."),
5989 sym_name);
0955507f
TP		 5990 ret = FALSE;
5991 }
5992 continue;
5993 }
5994 else
5995 {
5996 /* Only stubs for SG veneers should have been created. */
5997 BFD_ASSERT (stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
5998
5999 /* Check visibility hasn't changed. */
6000 if (!!(flags & BSF_GLOBAL)
6001 != (hash->root.root.type == bfd_link_hash_defined))
4eca0228 6002 _bfd_error_handler
0955507f
TP		 6003 (_("%B: visibility of symbol `%s' has changed."), in_implib_bfd,
6004 sym_name);
6005
6006 stub_entry->stub_offset = stub_offset;
6007 }
6008
6009 /* Size should match that of a SG veneer. */
6010 if (intsym->st_size != cmse_stub_size)
6011 {
4eca0228
AM		 6012 _bfd_error_handler (_("%B: incorrect size for symbol `%s'."),
6013 in_implib_bfd, sym_name);
0955507f
TP		 6014 ret = FALSE;
6015 }
6016
6017 /* Previous veneer address is before current SG veneer section. */
6018 if (veneer_value < cmse_stub_sec_vma)
6019 {
6020 /* Avoid offset underflow. */
6021 if (stub_entry)
6022 stub_entry->stub_offset = 0;
6023 stub_offset = 0;
6024 ret = FALSE;
6025 }
6026
6027 /* Complain if stub offset not a multiple of stub size. */
6028 if (stub_offset % cmse_stub_size)
6029 {
4eca0228 6030 _bfd_error_handler
0955507f
TP		 6031 (_("Offset of veneer for entry function `%s' not a multiple of "
6032 "its size."), sym_name);
6033 ret = FALSE;
6034 }
6035
6036 if (!ret)
6037 continue;
6038
6039 new_cmse_stubs_created--;
6040 if (veneer_value < cmse_stub_array_start)
6041 cmse_stub_array_start = veneer_value;
6042 next_cmse_stub_offset = stub_offset + ((cmse_stub_size + 7) & ~7);
6043 if (next_cmse_stub_offset > htab->new_cmse_stub_offset)
6044 htab->new_cmse_stub_offset = next_cmse_stub_offset;
6045 }
6046
6047 if (!info->out_implib_bfd && new_cmse_stubs_created != 0)
6048 {
6049 BFD_ASSERT (new_cmse_stubs_created > 0);
4eca0228 6050 _bfd_error_handler
0955507f
TP		 6051 (_("new entry function(s) introduced but no output import library "
6052 "specified:"));
6053 bfd_hash_traverse (&htab->stub_hash_table, arm_list_new_cmse_stub, info);
6054 }
6055
6056 if (cmse_stub_array_start != cmse_stub_sec_vma)
6057 {
4eca0228 6058 _bfd_error_handler
0955507f
TP		 6059 (_("Start address of `%s' is different from previous link."),
6060 out_sec_name);
6061 ret = FALSE;
6062 }
6063
6064free_sym_buf:
6065 free (sympp);
6066 return ret;
6067}
6068
906e58ca
NC		 6069/* Determine and set the size of the stub section for a final link.
6070
6071 The basic idea here is to examine all the relocations looking for
6072 PC-relative calls to a target that is unreachable with a "bl"
6073 instruction. */
6074
6075bfd_boolean
6076elf32_arm_size_stubs (bfd *output_bfd,
6077 bfd *stub_bfd,
6078 struct bfd_link_info *info,
6079 bfd_signed_vma group_size,
7a89b94e 6080 asection * (*add_stub_section) (const char *, asection *,
6bde4c52 6081 asection *,
7a89b94e 6082 unsigned int),
906e58ca
NC		 6083 void (*layout_sections_again) (void))
6084{
0955507f 6085 bfd_boolean ret = TRUE;
4ba2ef8f 6086 obj_attribute *out_attr;
0955507f 6087 int cmse_stub_created = 0;
906e58ca 6088 bfd_size_type stub_group_size;
4ba2ef8f 6089 bfd_boolean m_profile, stubs_always_after_branch, first_veneer_scan = TRUE;
906e58ca 6090 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
48229727 6091 struct a8_erratum_fix *a8_fixes = NULL;
eb7c4339 6092 unsigned int num_a8_fixes = 0, a8_fix_table_size = 10;
48229727
JB		 6093 struct a8_erratum_reloc *a8_relocs = NULL;
6094 unsigned int num_a8_relocs = 0, a8_reloc_table_size = 10, i;
6095
4dfe6ac6
NC		 6096 if (htab == NULL)
6097 return FALSE;
6098
48229727
JB		 6099 if (htab->fix_cortex_a8)
6100 {
21d799b5 6101 a8_fixes = (struct a8_erratum_fix *)
99059e56 6102 bfd_zmalloc (sizeof (struct a8_erratum_fix) * a8_fix_table_size);
21d799b5 6103 a8_relocs = (struct a8_erratum_reloc *)
99059e56 6104 bfd_zmalloc (sizeof (struct a8_erratum_reloc) * a8_reloc_table_size);
48229727 6105 }
906e58ca
NC		 6106
6107 /* Propagate mach to stub bfd, because it may not have been
6108 finalized when we created stub_bfd. */
6109 bfd_set_arch_mach (stub_bfd, bfd_get_arch (output_bfd),
6110 bfd_get_mach (output_bfd));
6111
6112 /* Stash our params away. */
6113 htab->stub_bfd = stub_bfd;
6114 htab->add_stub_section = add_stub_section;
6115 htab->layout_sections_again = layout_sections_again;
07d72278 6116 stubs_always_after_branch = group_size < 0;
48229727 6117
4ba2ef8f
TP		 6118 out_attr = elf_known_obj_attributes_proc (output_bfd);
6119 m_profile = out_attr[Tag_CPU_arch_profile].i == 'M';
0955507f 6120
48229727
JB		 6121 /* The Cortex-A8 erratum fix depends on stubs not being in the same 4K page
6122 as the first half of a 32-bit branch straddling two 4K pages. This is a
6123 crude way of enforcing that. */
6124 if (htab->fix_cortex_a8)
6125 stubs_always_after_branch = 1;
6126
906e58ca
NC		 6127 if (group_size < 0)
6128 stub_group_size = -group_size;
6129 else
6130 stub_group_size = group_size;
6131
6132 if (stub_group_size == 1)
6133 {
6134 /* Default values. */
6135 /* Thumb branch range is +-4MB has to be used as the default
6136 maximum size (a given section can contain both ARM and Thumb
6137 code, so the worst case has to be taken into account).
6138
6139 This value is 24K less than that, which allows for 2025
6140 12-byte stubs. If we exceed that, then we will fail to link.
6141 The user will have to relink with an explicit group size
6142 option. */
6143 stub_group_size = 4170000;
6144 }
6145
07d72278 6146 group_sections (htab, stub_group_size, stubs_always_after_branch);
906e58ca 6147
3ae046cc
NS		 6148 /* If we're applying the cortex A8 fix, we need to determine the
6149 program header size now, because we cannot change it later --
6150 that could alter section placements. Notice the A8 erratum fix
6151 ends up requiring the section addresses to remain unchanged
6152 modulo the page size. That's something we cannot represent
6153 inside BFD, and we don't want to force the section alignment to
6154 be the page size. */
6155 if (htab->fix_cortex_a8)
6156 (*htab->layout_sections_again) ();
6157
906e58ca
NC		 6158 while (1)
6159 {
6160 bfd *input_bfd;
6161 unsigned int bfd_indx;
6162 asection *stub_sec;
d7c5bd02 6163 enum elf32_arm_stub_type stub_type;
eb7c4339
NS		 6164 bfd_boolean stub_changed = FALSE;
6165 unsigned prev_num_a8_fixes = num_a8_fixes;
906e58ca 6166
48229727 6167 num_a8_fixes = 0;
906e58ca
NC		 6168 for (input_bfd = info->input_bfds, bfd_indx = 0;
6169 input_bfd != NULL;
c72f2fb2 6170 input_bfd = input_bfd->link.next, bfd_indx++)
906e58ca
NC		 6171 {
6172 Elf_Internal_Shdr *symtab_hdr;
6173 asection *section;
6174 Elf_Internal_Sym *local_syms = NULL;
6175
99059e56
RM		 6176 if (!is_arm_elf (input_bfd))
6177 continue;
adbcc655 6178
48229727
JB		 6179 num_a8_relocs = 0;
6180
906e58ca
NC		 6181 /* We'll need the symbol table in a second. */
6182 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
6183 if (symtab_hdr->sh_info == 0)
6184 continue;
6185
4ba2ef8f
TP		 6186 /* Limit scan of symbols to object file whose profile is
6187 Microcontroller to not hinder performance in the general case. */
6188 if (m_profile && first_veneer_scan)
6189 {
6190 struct elf_link_hash_entry **sym_hashes;
6191
6192 sym_hashes = elf_sym_hashes (input_bfd);
6193 if (!cmse_scan (input_bfd, htab, out_attr, sym_hashes,
0955507f 6194 &cmse_stub_created))
4ba2ef8f 6195 goto error_ret_free_local;
0955507f
TP		 6196
6197 if (cmse_stub_created != 0)
6198 stub_changed = TRUE;
4ba2ef8f
TP		 6199 }
6200
906e58ca
NC		 6201 /* Walk over each section attached to the input bfd. */
6202 for (section = input_bfd->sections;
6203 section != NULL;
6204 section = section->next)
6205 {
6206 Elf_Internal_Rela *internal_relocs, *irelaend, *irela;
6207
6208 /* If there aren't any relocs, then there's nothing more
6209 to do. */
6210 if ((section->flags & SEC_RELOC) == 0
6211 || section->reloc_count == 0
6212 || (section->flags & SEC_CODE) == 0)
6213 continue;
6214
6215 /* If this section is a link-once section that will be
6216 discarded, then don't create any stubs. */
6217 if (section->output_section == NULL
6218 || section->output_section->owner != output_bfd)
6219 continue;
6220
6221 /* Get the relocs. */
6222 internal_relocs
6223 = _bfd_elf_link_read_relocs (input_bfd, section, NULL,
6224 NULL, info->keep_memory);
6225 if (internal_relocs == NULL)
6226 goto error_ret_free_local;
6227
6228 /* Now examine each relocation. */
6229 irela = internal_relocs;
6230 irelaend = irela + section->reloc_count;
6231 for (; irela < irelaend; irela++)
6232 {
6233 unsigned int r_type, r_indx;
906e58ca
NC		 6234 asection *sym_sec;
6235 bfd_vma sym_value;
6236 bfd_vma destination;
6237 struct elf32_arm_link_hash_entry *hash;
7413f23f 6238 const char *sym_name;
34e77a92 6239 unsigned char st_type;
35fc36a8 6240 enum arm_st_branch_type branch_type;
48229727 6241 bfd_boolean created_stub = FALSE;
906e58ca
NC		 6242
6243 r_type = ELF32_R_TYPE (irela->r_info);
6244 r_indx = ELF32_R_SYM (irela->r_info);
6245
6246 if (r_type >= (unsigned int) R_ARM_max)
6247 {
6248 bfd_set_error (bfd_error_bad_value);
6249 error_ret_free_internal:
6250 if (elf_section_data (section)->relocs == NULL)
6251 free (internal_relocs);
15dd01b1
TP		 6252 /* Fall through. */
6253 error_ret_free_local:
6254 if (local_syms != NULL
6255 && (symtab_hdr->contents
6256 != (unsigned char *) local_syms))
6257 free (local_syms);
6258 return FALSE;
906e58ca 6259 }
b38cadfb 6260
0855e32b
NS		 6261 hash = NULL;
6262 if (r_indx >= symtab_hdr->sh_info)
6263 hash = elf32_arm_hash_entry
6264 (elf_sym_hashes (input_bfd)
6265 [r_indx - symtab_hdr->sh_info]);
b38cadfb 6266
0855e32b
NS		 6267 /* Only look for stubs on branch instructions, or
6268 non-relaxed TLSCALL */
906e58ca 6269 if ((r_type != (unsigned int) R_ARM_CALL)
155d87d7
CL		 6270 && (r_type != (unsigned int) R_ARM_THM_CALL)
6271 && (r_type != (unsigned int) R_ARM_JUMP24)
48229727
JB		 6272 && (r_type != (unsigned int) R_ARM_THM_JUMP19)
6273 && (r_type != (unsigned int) R_ARM_THM_XPC22)
155d87d7 6274 && (r_type != (unsigned int) R_ARM_THM_JUMP24)
0855e32b
NS		 6275 && (r_type != (unsigned int) R_ARM_PLT32)
6276 && !((r_type == (unsigned int) R_ARM_TLS_CALL
6277 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6278 && r_type == elf32_arm_tls_transition
6279 (info, r_type, &hash->root)
6280 && ((hash ? hash->tls_type
6281 : (elf32_arm_local_got_tls_type
6282 (input_bfd)[r_indx]))
6283 & GOT_TLS_GDESC) != 0))
906e58ca
NC		 6284 continue;
6285
6286 /* Now determine the call target, its name, value,
6287 section. */
6288 sym_sec = NULL;
6289 sym_value = 0;
6290 destination = 0;
7413f23f 6291 sym_name = NULL;
b38cadfb 6292
0855e32b
NS		 6293 if (r_type == (unsigned int) R_ARM_TLS_CALL
6294 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6295 {
6296 /* A non-relaxed TLS call. The target is the
6297 plt-resident trampoline and nothing to do
6298 with the symbol. */
6299 BFD_ASSERT (htab->tls_trampoline > 0);
6300 sym_sec = htab->root.splt;
6301 sym_value = htab->tls_trampoline;
6302 hash = 0;
34e77a92 6303 st_type = STT_FUNC;
35fc36a8 6304 branch_type = ST_BRANCH_TO_ARM;
0855e32b
NS		 6305 }
6306 else if (!hash)
906e58ca
NC		 6307 {
6308 /* It's a local symbol. */
6309 Elf_Internal_Sym *sym;
906e58ca
NC		 6310
6311 if (local_syms == NULL)
6312 {
6313 local_syms
6314 = (Elf_Internal_Sym *) symtab_hdr->contents;
6315 if (local_syms == NULL)
6316 local_syms
6317 = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
6318 symtab_hdr->sh_info, 0,
6319 NULL, NULL, NULL);
6320 if (local_syms == NULL)
6321 goto error_ret_free_internal;
6322 }
6323
6324 sym = local_syms + r_indx;
f6d250ce
TS		 6325 if (sym->st_shndx == SHN_UNDEF)
6326 sym_sec = bfd_und_section_ptr;
6327 else if (sym->st_shndx == SHN_ABS)
6328 sym_sec = bfd_abs_section_ptr;
6329 else if (sym->st_shndx == SHN_COMMON)
6330 sym_sec = bfd_com_section_ptr;
6331 else
6332 sym_sec =
6333 bfd_section_from_elf_index (input_bfd, sym->st_shndx);
6334
ffcb4889
NS		 6335 if (!sym_sec)
6336 /* This is an undefined symbol. It can never
6a631e86 6337 be resolved. */
ffcb4889 6338 continue;
fe33d2fa 6339
906e58ca
NC		 6340 if (ELF_ST_TYPE (sym->st_info) != STT_SECTION)
6341 sym_value = sym->st_value;
6342 destination = (sym_value + irela->r_addend
6343 + sym_sec->output_offset
6344 + sym_sec->output_section->vma);
34e77a92 6345 st_type = ELF_ST_TYPE (sym->st_info);
39d911fc
TP		 6346 branch_type =
6347 ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
7413f23f
DJ		 6348 sym_name
6349 = bfd_elf_string_from_elf_section (input_bfd,
6350 symtab_hdr->sh_link,
6351 sym->st_name);
906e58ca
NC		 6352 }
6353 else
6354 {
6355 /* It's an external symbol. */
906e58ca
NC		 6356 while (hash->root.root.type == bfd_link_hash_indirect
6357 || hash->root.root.type == bfd_link_hash_warning)
6358 hash = ((struct elf32_arm_link_hash_entry *)
6359 hash->root.root.u.i.link);
6360
6361 if (hash->root.root.type == bfd_link_hash_defined
6362 || hash->root.root.type == bfd_link_hash_defweak)
6363 {
6364 sym_sec = hash->root.root.u.def.section;
6365 sym_value = hash->root.root.u.def.value;
022f8312
CL		 6366
6367 struct elf32_arm_link_hash_table *globals =
6368 elf32_arm_hash_table (info);
6369
6370 /* For a destination in a shared library,
6371 use the PLT stub as target address to
6372 decide whether a branch stub is
6373 needed. */
4dfe6ac6 6374 if (globals != NULL
362d30a1 6375 && globals->root.splt != NULL
4dfe6ac6 6376 && hash != NULL
022f8312
CL		 6377 && hash->root.plt.offset != (bfd_vma) -1)
6378 {
362d30a1 6379 sym_sec = globals->root.splt;
022f8312
CL		 6380 sym_value = hash->root.plt.offset;
6381 if (sym_sec->output_section != NULL)
6382 destination = (sym_value
6383 + sym_sec->output_offset
6384 + sym_sec->output_section->vma);
6385 }
6386 else if (sym_sec->output_section != NULL)
906e58ca
NC		 6387 destination = (sym_value + irela->r_addend
6388 + sym_sec->output_offset
6389 + sym_sec->output_section->vma);
6390 }
69c5861e
CL		 6391 else if ((hash->root.root.type == bfd_link_hash_undefined)
6392 || (hash->root.root.type == bfd_link_hash_undefweak))
6393 {
6394 /* For a shared library, use the PLT stub as
6395 target address to decide whether a long
6396 branch stub is needed.
6397 For absolute code, they cannot be handled. */
6398 struct elf32_arm_link_hash_table *globals =
6399 elf32_arm_hash_table (info);
6400
4dfe6ac6 6401 if (globals != NULL
362d30a1 6402 && globals->root.splt != NULL
4dfe6ac6 6403 && hash != NULL
69c5861e
CL		 6404 && hash->root.plt.offset != (bfd_vma) -1)
6405 {
362d30a1 6406 sym_sec = globals->root.splt;
69c5861e
CL		 6407 sym_value = hash->root.plt.offset;
6408 if (sym_sec->output_section != NULL)
6409 destination = (sym_value
6410 + sym_sec->output_offset
6411 + sym_sec->output_section->vma);
6412 }
6413 else
6414 continue;
6415 }
906e58ca
NC		 6416 else
6417 {
6418 bfd_set_error (bfd_error_bad_value);
6419 goto error_ret_free_internal;
6420 }
34e77a92 6421 st_type = hash->root.type;
39d911fc
TP		 6422 branch_type =
6423 ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
7413f23f 6424 sym_name = hash->root.root.root.string;
906e58ca
NC		 6425 }
6426
48229727 6427 do
7413f23f 6428 {
b715f643 6429 bfd_boolean new_stub;
0955507f 6430 struct elf32_arm_stub_hash_entry *stub_entry;
b715f643 6431
48229727
JB		 6432 /* Determine what (if any) linker stub is needed. */
6433 stub_type = arm_type_of_stub (info, section, irela,
34e77a92
RS		 6434 st_type, &branch_type,
6435 hash, destination, sym_sec,
48229727
JB		 6436 input_bfd, sym_name);
6437 if (stub_type == arm_stub_none)
6438 break;
6439
48229727
JB		 6440 /* We've either created a stub for this reloc already,
6441 or we are about to. */
0955507f 6442 stub_entry =
b715f643
TP		 6443 elf32_arm_create_stub (htab, stub_type, section, irela,
6444 sym_sec, hash,
6445 (char *) sym_name, sym_value,
6446 branch_type, &new_stub);
7413f23f 6447
0955507f 6448 created_stub = stub_entry != NULL;
b715f643
TP		 6449 if (!created_stub)
6450 goto error_ret_free_internal;
6451 else if (!new_stub)
6452 break;
99059e56 6453 else
b715f643 6454 stub_changed = TRUE;
99059e56
RM		 6455 }
6456 while (0);
6457
6458 /* Look for relocations which might trigger Cortex-A8
6459 erratum. */
6460 if (htab->fix_cortex_a8
6461 && (r_type == (unsigned int) R_ARM_THM_JUMP24
6462 || r_type == (unsigned int) R_ARM_THM_JUMP19
6463 || r_type == (unsigned int) R_ARM_THM_CALL
6464 || r_type == (unsigned int) R_ARM_THM_XPC22))
6465 {
6466 bfd_vma from = section->output_section->vma
6467 + section->output_offset
6468 + irela->r_offset;
6469
6470 if ((from & 0xfff) == 0xffe)
6471 {
6472 /* Found a candidate. Note we haven't checked the
6473 destination is within 4K here: if we do so (and
6474 don't create an entry in a8_relocs) we can't tell
6475 that a branch should have been relocated when
6476 scanning later. */
6477 if (num_a8_relocs == a8_reloc_table_size)
6478 {
6479 a8_reloc_table_size *= 2;
6480 a8_relocs = (struct a8_erratum_reloc *)
6481 bfd_realloc (a8_relocs,
6482 sizeof (struct a8_erratum_reloc)
6483 * a8_reloc_table_size);
6484 }
6485
6486 a8_relocs[num_a8_relocs].from = from;
6487 a8_relocs[num_a8_relocs].destination = destination;
6488 a8_relocs[num_a8_relocs].r_type = r_type;
6489 a8_relocs[num_a8_relocs].branch_type = branch_type;
6490 a8_relocs[num_a8_relocs].sym_name = sym_name;
6491 a8_relocs[num_a8_relocs].non_a8_stub = created_stub;
6492 a8_relocs[num_a8_relocs].hash = hash;
6493
6494 num_a8_relocs++;
6495 }
6496 }
906e58ca
NC		 6497 }
6498
99059e56
RM		 6499 /* We're done with the internal relocs, free them. */
6500 if (elf_section_data (section)->relocs == NULL)
6501 free (internal_relocs);
6502 }
48229727 6503
99059e56 6504 if (htab->fix_cortex_a8)
48229727 6505 {
99059e56
RM		 6506 /* Sort relocs which might apply to Cortex-A8 erratum. */
6507 qsort (a8_relocs, num_a8_relocs,
eb7c4339 6508 sizeof (struct a8_erratum_reloc),
99059e56 6509 &a8_reloc_compare);
48229727 6510
99059e56
RM		 6511 /* Scan for branches which might trigger Cortex-A8 erratum. */
6512 if (cortex_a8_erratum_scan (input_bfd, info, &a8_fixes,
48229727 6513 &num_a8_fixes, &a8_fix_table_size,
eb7c4339
NS		 6514 a8_relocs, num_a8_relocs,
6515 prev_num_a8_fixes, &stub_changed)
6516 != 0)
48229727 6517 goto error_ret_free_local;
5e681ec4 6518 }
7f991970
AM		 6519
6520 if (local_syms != NULL
6521 && symtab_hdr->contents != (unsigned char *) local_syms)
6522 {
6523 if (!info->keep_memory)
6524 free (local_syms);
6525 else
6526 symtab_hdr->contents = (unsigned char *) local_syms;
6527 }
5e681ec4
PB		 6528 }
6529
0955507f
TP		 6530 if (first_veneer_scan
6531 && !set_cmse_veneer_addr_from_implib (info, htab,
6532 &cmse_stub_created))
6533 ret = FALSE;
6534
eb7c4339 6535 if (prev_num_a8_fixes != num_a8_fixes)
99059e56 6536 stub_changed = TRUE;
48229727 6537
906e58ca
NC		 6538 if (!stub_changed)
6539 break;
5e681ec4 6540
906e58ca
NC		 6541 /* OK, we've added some stubs. Find out the new size of the
6542 stub sections. */
6543 for (stub_sec = htab->stub_bfd->sections;
6544 stub_sec != NULL;
6545 stub_sec = stub_sec->next)
3e6b1042
DJ		 6546 {
6547 /* Ignore non-stub sections. */
6548 if (!strstr (stub_sec->name, STUB_SUFFIX))
6549 continue;
6550
6551 stub_sec->size = 0;
6552 }
b34b2d70 6553
0955507f
TP		 6554 /* Add new SG veneers after those already in the input import
6555 library. */
6556 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6557 stub_type++)
6558 {
6559 bfd_vma *start_offset_p;
6560 asection **stub_sec_p;
6561
6562 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
6563 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6564 if (start_offset_p == NULL)
6565 continue;
6566
6567 BFD_ASSERT (stub_sec_p != NULL);
6568 if (*stub_sec_p != NULL)
6569 (*stub_sec_p)->size = *start_offset_p;
6570 }
6571
d7c5bd02 6572 /* Compute stub section size, considering padding. */
906e58ca 6573 bfd_hash_traverse (&htab->stub_hash_table, arm_size_one_stub, htab);
d7c5bd02
TP		 6574 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6575 stub_type++)
6576 {
6577 int size, padding;
6578 asection **stub_sec_p;
6579
6580 padding = arm_dedicated_stub_section_padding (stub_type);
6581 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6582 /* Skip if no stub input section or no stub section padding
6583 required. */
6584 if ((stub_sec_p != NULL && *stub_sec_p == NULL) || padding == 0)
6585 continue;
6586 /* Stub section padding required but no dedicated section. */
6587 BFD_ASSERT (stub_sec_p);
6588
6589 size = (*stub_sec_p)->size;
6590 size = (size + padding - 1) & ~(padding - 1);
6591 (*stub_sec_p)->size = size;
6592 }
906e58ca 6593
48229727
JB		 6594 /* Add Cortex-A8 erratum veneers to stub section sizes too. */
6595 if (htab->fix_cortex_a8)
99059e56
RM		 6596 for (i = 0; i < num_a8_fixes; i++)
6597 {
48229727 6598 stub_sec = elf32_arm_create_or_find_stub_sec (NULL,
daa4adae 6599 a8_fixes[i].section, htab, a8_fixes[i].stub_type);
48229727
JB		 6600
6601 if (stub_sec == NULL)
7f991970 6602 return FALSE;
48229727 6603
99059e56
RM		 6604 stub_sec->size
6605 += find_stub_size_and_template (a8_fixes[i].stub_type, NULL,
6606 NULL);
6607 }
48229727
JB		 6608
6609
906e58ca
NC		 6610 /* Ask the linker to do its stuff. */
6611 (*htab->layout_sections_again) ();
4ba2ef8f 6612 first_veneer_scan = FALSE;
ba93b8ac
DJ		 6613 }
6614
48229727
JB		 6615 /* Add stubs for Cortex-A8 erratum fixes now. */
6616 if (htab->fix_cortex_a8)
6617 {
6618 for (i = 0; i < num_a8_fixes; i++)
99059e56
RM		 6619 {
6620 struct elf32_arm_stub_hash_entry *stub_entry;
6621 char *stub_name = a8_fixes[i].stub_name;
6622 asection *section = a8_fixes[i].section;
6623 unsigned int section_id = a8_fixes[i].section->id;
6624 asection *link_sec = htab->stub_group[section_id].link_sec;
6625 asection *stub_sec = htab->stub_group[section_id].stub_sec;
6626 const insn_sequence *template_sequence;
6627 int template_size, size = 0;
6628
6629 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
6630 TRUE, FALSE);
6631 if (stub_entry == NULL)
6632 {
dae82561 6633 _bfd_error_handler (_("%B: cannot create stub entry %s"),
4eca0228 6634 section->owner, stub_name);
99059e56
RM		 6635 return FALSE;
6636 }
6637
6638 stub_entry->stub_sec = stub_sec;
0955507f 6639 stub_entry->stub_offset = (bfd_vma) -1;
99059e56
RM		 6640 stub_entry->id_sec = link_sec;
6641 stub_entry->stub_type = a8_fixes[i].stub_type;
8d9d9490 6642 stub_entry->source_value = a8_fixes[i].offset;
99059e56 6643 stub_entry->target_section = a8_fixes[i].section;
8d9d9490 6644 stub_entry->target_value = a8_fixes[i].target_offset;
99059e56 6645 stub_entry->orig_insn = a8_fixes[i].orig_insn;
35fc36a8 6646 stub_entry->branch_type = a8_fixes[i].branch_type;
48229727 6647
99059e56
RM		 6648 size = find_stub_size_and_template (a8_fixes[i].stub_type,
6649 &template_sequence,
6650 &template_size);
48229727 6651
99059e56
RM		 6652 stub_entry->stub_size = size;
6653 stub_entry->stub_template = template_sequence;
6654 stub_entry->stub_template_size = template_size;
6655 }
48229727
JB		 6656
6657 /* Stash the Cortex-A8 erratum fix array for use later in
99059e56 6658 elf32_arm_write_section(). */
48229727
JB		 6659 htab->a8_erratum_fixes = a8_fixes;
6660 htab->num_a8_erratum_fixes = num_a8_fixes;
6661 }
6662 else
6663 {
6664 htab->a8_erratum_fixes = NULL;
6665 htab->num_a8_erratum_fixes = 0;
6666 }
0955507f 6667 return ret;
5e681ec4
PB		 6668}
6669
906e58ca
NC		 6670/* Build all the stubs associated with the current output file. The
6671 stubs are kept in a hash table attached to the main linker hash
6672 table. We also set up the .plt entries for statically linked PIC
6673 functions here. This function is called via arm_elf_finish in the
6674 linker. */
252b5132 6675
906e58ca
NC		 6676bfd_boolean
6677elf32_arm_build_stubs (struct bfd_link_info *info)
252b5132 6678{
906e58ca
NC		 6679 asection *stub_sec;
6680 struct bfd_hash_table *table;
0955507f 6681 enum elf32_arm_stub_type stub_type;
906e58ca 6682 struct elf32_arm_link_hash_table *htab;
252b5132 6683
906e58ca 6684 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 6685 if (htab == NULL)
6686 return FALSE;
252b5132 6687
906e58ca
NC		 6688 for (stub_sec = htab->stub_bfd->sections;
6689 stub_sec != NULL;
6690 stub_sec = stub_sec->next)
252b5132 6691 {
906e58ca
NC		 6692 bfd_size_type size;
6693
8029a119 6694 /* Ignore non-stub sections. */
906e58ca
NC		 6695 if (!strstr (stub_sec->name, STUB_SUFFIX))
6696 continue;
6697
d7c5bd02 6698 /* Allocate memory to hold the linker stubs. Zeroing the stub sections
0955507f
TP		 6699 must at least be done for stub section requiring padding and for SG
6700 veneers to ensure that a non secure code branching to a removed SG
6701 veneer causes an error. */
906e58ca 6702 size = stub_sec->size;
21d799b5 6703 stub_sec->contents = (unsigned char *) bfd_zalloc (htab->stub_bfd, size);
906e58ca
NC		 6704 if (stub_sec->contents == NULL && size != 0)
6705 return FALSE;
0955507f 6706
906e58ca 6707 stub_sec->size = 0;
252b5132
RH		 6708 }
6709
0955507f
TP		 6710 /* Add new SG veneers after those already in the input import library. */
6711 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
6712 {
6713 bfd_vma *start_offset_p;
6714 asection **stub_sec_p;
6715
6716 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
6717 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6718 if (start_offset_p == NULL)
6719 continue;
6720
6721 BFD_ASSERT (stub_sec_p != NULL);
6722 if (*stub_sec_p != NULL)
6723 (*stub_sec_p)->size = *start_offset_p;
6724 }
6725
906e58ca
NC		 6726 /* Build the stubs as directed by the stub hash table. */
6727 table = &htab->stub_hash_table;
6728 bfd_hash_traverse (table, arm_build_one_stub, info);
eb7c4339
NS		 6729 if (htab->fix_cortex_a8)
6730 {
6731 /* Place the cortex a8 stubs last. */
6732 htab->fix_cortex_a8 = -1;
6733 bfd_hash_traverse (table, arm_build_one_stub, info);
6734 }
252b5132 6735
906e58ca 6736 return TRUE;
252b5132
RH		 6737}
6738
9b485d32
NC		 6739/* Locate the Thumb encoded calling stub for NAME. */
6740
252b5132 6741static struct elf_link_hash_entry *
57e8b36a
NC		 6742find_thumb_glue (struct bfd_link_info *link_info,
6743 const char *name,
f2a9dd69 6744 char **error_message)
252b5132
RH		 6745{
6746 char *tmp_name;
6747 struct elf_link_hash_entry *hash;
6748 struct elf32_arm_link_hash_table *hash_table;
6749
6750 /* We need a pointer to the armelf specific hash table. */
6751 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 6752 if (hash_table == NULL)
6753 return NULL;
252b5132 6754
21d799b5 6755 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 6756 + strlen (THUMB2ARM_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 6757
6758 BFD_ASSERT (tmp_name);
6759
6760 sprintf (tmp_name, THUMB2ARM_GLUE_ENTRY_NAME, name);
6761
6762 hash = elf_link_hash_lookup
b34976b6 6763 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 6764
b1657152
AM		 6765 if (hash == NULL
6766 && asprintf (error_message, _("unable to find THUMB glue '%s' for '%s'"),
6767 tmp_name, name) == -1)
6768 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 6769
6770 free (tmp_name);
6771
6772 return hash;
6773}
6774
9b485d32
NC		 6775/* Locate the ARM encoded calling stub for NAME. */
6776
252b5132 6777static struct elf_link_hash_entry *
57e8b36a
NC		 6778find_arm_glue (struct bfd_link_info *link_info,
6779 const char *name,
f2a9dd69 6780 char **error_message)
252b5132
RH		 6781{
6782 char *tmp_name;
6783 struct elf_link_hash_entry *myh;
6784 struct elf32_arm_link_hash_table *hash_table;
6785
6786 /* We need a pointer to the elfarm specific hash table. */
6787 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 6788 if (hash_table == NULL)
6789 return NULL;
252b5132 6790
21d799b5 6791 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 6792 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 6793
6794 BFD_ASSERT (tmp_name);
6795
6796 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
6797
6798 myh = elf_link_hash_lookup
b34976b6 6799 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 6800
b1657152
AM		 6801 if (myh == NULL
6802 && asprintf (error_message, _("unable to find ARM glue '%s' for '%s'"),
6803 tmp_name, name) == -1)
6804 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 6805
6806 free (tmp_name);
6807
6808 return myh;
6809}
6810
8f6277f5 6811/* ARM->Thumb glue (static images):
252b5132
RH		 6812
6813 .arm
6814 __func_from_arm:
6815 ldr r12, __func_addr
6816 bx r12
6817 __func_addr:
906e58ca 6818 .word func @ behave as if you saw a ARM_32 reloc.
252b5132 6819
26079076
PB		 6820 (v5t static images)
6821 .arm
6822 __func_from_arm:
6823 ldr pc, __func_addr
6824 __func_addr:
906e58ca 6825 .word func @ behave as if you saw a ARM_32 reloc.
26079076 6826
8f6277f5
PB		 6827 (relocatable images)
6828 .arm
6829 __func_from_arm:
6830 ldr r12, __func_offset
6831 add r12, r12, pc
6832 bx r12
6833 __func_offset:
8029a119 6834 .word func - . */
8f6277f5
PB		 6835
6836#define ARM2THUMB_STATIC_GLUE_SIZE 12
252b5132
RH		 6837static const insn32 a2t1_ldr_insn = 0xe59fc000;
6838static const insn32 a2t2_bx_r12_insn = 0xe12fff1c;
6839static const insn32 a2t3_func_addr_insn = 0x00000001;
6840
26079076
PB		 6841#define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
6842static const insn32 a2t1v5_ldr_insn = 0xe51ff004;
6843static const insn32 a2t2v5_func_addr_insn = 0x00000001;
6844
8f6277f5
PB		 6845#define ARM2THUMB_PIC_GLUE_SIZE 16
6846static const insn32 a2t1p_ldr_insn = 0xe59fc004;
6847static const insn32 a2t2p_add_pc_insn = 0xe08cc00f;
6848static const insn32 a2t3p_bx_r12_insn = 0xe12fff1c;
6849
9b485d32 6850/* Thumb->ARM: Thumb->(non-interworking aware) ARM
252b5132 6851
8029a119
NC		 6852 .thumb .thumb
6853 .align 2 .align 2
6854 __func_from_thumb: __func_from_thumb:
6855 bx pc push {r6, lr}
6856 nop ldr r6, __func_addr
6857 .arm mov lr, pc
6858 b func bx r6
99059e56
RM		 6859 .arm
6860 ;; back_to_thumb
6861 ldmia r13! {r6, lr}
6862 bx lr
6863 __func_addr:
6864 .word func */
252b5132
RH		 6865
6866#define THUMB2ARM_GLUE_SIZE 8
6867static const insn16 t2a1_bx_pc_insn = 0x4778;
6868static const insn16 t2a2_noop_insn = 0x46c0;
6869static const insn32 t2a3_b_insn = 0xea000000;
6870
c7b8f16e 6871#define VFP11_ERRATUM_VENEER_SIZE 8
a504d23a
LA		 6872#define STM32L4XX_ERRATUM_LDM_VENEER_SIZE 16
6873#define STM32L4XX_ERRATUM_VLDM_VENEER_SIZE 24
c7b8f16e 6874
845b51d6
PB		 6875#define ARM_BX_VENEER_SIZE 12
6876static const insn32 armbx1_tst_insn = 0xe3100001;
6877static const insn32 armbx2_moveq_insn = 0x01a0f000;
6878static const insn32 armbx3_bx_insn = 0xe12fff10;
6879
7e392df6 6880#ifndef ELFARM_NABI_C_INCLUDED
8029a119
NC		 6881static void
6882arm_allocate_glue_section_space (bfd * abfd, bfd_size_type size, const char * name)
252b5132
RH		 6883{
6884 asection * s;
8029a119 6885 bfd_byte * contents;
252b5132 6886
8029a119 6887 if (size == 0)
3e6b1042
DJ		 6888 {
6889 /* Do not include empty glue sections in the output. */
6890 if (abfd != NULL)
6891 {
3d4d4302 6892 s = bfd_get_linker_section (abfd, name);
3e6b1042
DJ		 6893 if (s != NULL)
6894 s->flags |= SEC_EXCLUDE;
6895 }
6896 return;
6897 }
252b5132 6898
8029a119 6899 BFD_ASSERT (abfd != NULL);
252b5132 6900
3d4d4302 6901 s = bfd_get_linker_section (abfd, name);
8029a119 6902 BFD_ASSERT (s != NULL);
252b5132 6903
21d799b5 6904 contents = (bfd_byte *) bfd_alloc (abfd, size);
252b5132 6905
8029a119
NC		 6906 BFD_ASSERT (s->size == size);
6907 s->contents = contents;
6908}
906e58ca 6909
8029a119
NC		 6910bfd_boolean
6911bfd_elf32_arm_allocate_interworking_sections (struct bfd_link_info * info)
6912{
6913 struct elf32_arm_link_hash_table * globals;
906e58ca 6914
8029a119
NC		 6915 globals = elf32_arm_hash_table (info);
6916 BFD_ASSERT (globals != NULL);
906e58ca 6917
8029a119
NC		 6918 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6919 globals->arm_glue_size,
6920 ARM2THUMB_GLUE_SECTION_NAME);
906e58ca 6921
8029a119
NC		 6922 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6923 globals->thumb_glue_size,
6924 THUMB2ARM_GLUE_SECTION_NAME);
252b5132 6925
8029a119
NC		 6926 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6927 globals->vfp11_erratum_glue_size,
6928 VFP11_ERRATUM_VENEER_SECTION_NAME);
845b51d6 6929
a504d23a
LA		 6930 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6931 globals->stm32l4xx_erratum_glue_size,
6932 STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
6933
8029a119
NC		 6934 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6935 globals->bx_glue_size,
845b51d6
PB		 6936 ARM_BX_GLUE_SECTION_NAME);
6937
b34976b6 6938 return TRUE;
252b5132
RH		 6939}
6940
a4fd1a8e 6941/* Allocate space and symbols for calling a Thumb function from Arm mode.
906e58ca
NC		 6942 returns the symbol identifying the stub. */
6943
a4fd1a8e 6944static struct elf_link_hash_entry *
57e8b36a
NC		 6945record_arm_to_thumb_glue (struct bfd_link_info * link_info,
6946 struct elf_link_hash_entry * h)
252b5132
RH		 6947{
6948 const char * name = h->root.root.string;
63b0f745 6949 asection * s;
252b5132
RH		 6950 char * tmp_name;
6951 struct elf_link_hash_entry * myh;
14a793b2 6952 struct bfd_link_hash_entry * bh;
252b5132 6953 struct elf32_arm_link_hash_table * globals;
dc810e39 6954 bfd_vma val;
2f475487 6955 bfd_size_type size;
252b5132
RH		 6956
6957 globals = elf32_arm_hash_table (link_info);
252b5132
RH		 6958 BFD_ASSERT (globals != NULL);
6959 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
6960
3d4d4302 6961 s = bfd_get_linker_section
252b5132
RH		 6962 (globals->bfd_of_glue_owner, ARM2THUMB_GLUE_SECTION_NAME);
6963
252b5132
RH		 6964 BFD_ASSERT (s != NULL);
6965
21d799b5 6966 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 6967 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 6968
6969 BFD_ASSERT (tmp_name);
6970
6971 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
6972
6973 myh = elf_link_hash_lookup
b34976b6 6974 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132
RH		 6975
6976 if (myh != NULL)
6977 {
9b485d32 6978 /* We've already seen this guy. */
252b5132 6979 free (tmp_name);
a4fd1a8e 6980 return myh;
252b5132
RH		 6981 }
6982
57e8b36a
NC		 6983 /* The only trick here is using hash_table->arm_glue_size as the value.
6984 Even though the section isn't allocated yet, this is where we will be
3dccd7b7
DJ		 6985 putting it. The +1 on the value marks that the stub has not been
6986 output yet - not that it is a Thumb function. */
14a793b2 6987 bh = NULL;
dc810e39
AM		 6988 val = globals->arm_glue_size + 1;
6989 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
6990 tmp_name, BSF_GLOBAL, s, val,
b34976b6 6991 NULL, TRUE, FALSE, &bh);
252b5132 6992
b7693d02
DJ		 6993 myh = (struct elf_link_hash_entry *) bh;
6994 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6995 myh->forced_local = 1;
6996
252b5132
RH		 6997 free (tmp_name);
6998
0e1862bb
L		 6999 if (bfd_link_pic (link_info)
7000 || globals->root.is_relocatable_executable
27e55c4d 7001 || globals->pic_veneer)
2f475487 7002 size = ARM2THUMB_PIC_GLUE_SIZE;
26079076
PB		 7003 else if (globals->use_blx)
7004 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
8f6277f5 7005 else
2f475487
AM		 7006 size = ARM2THUMB_STATIC_GLUE_SIZE;
7007
7008 s->size += size;
7009 globals->arm_glue_size += size;
252b5132 7010
a4fd1a8e 7011 return myh;
252b5132
RH		 7012}
7013
845b51d6
PB		 7014/* Allocate space for ARMv4 BX veneers. */
7015
7016static void
7017record_arm_bx_glue (struct bfd_link_info * link_info, int reg)
7018{
7019 asection * s;
7020 struct elf32_arm_link_hash_table *globals;
7021 char *tmp_name;
7022 struct elf_link_hash_entry *myh;
7023 struct bfd_link_hash_entry *bh;
7024 bfd_vma val;
7025
7026 /* BX PC does not need a veneer. */
7027 if (reg == 15)
7028 return;
7029
7030 globals = elf32_arm_hash_table (link_info);
845b51d6
PB		 7031 BFD_ASSERT (globals != NULL);
7032 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7033
7034 /* Check if this veneer has already been allocated. */
7035 if (globals->bx_glue_offset[reg])
7036 return;
7037
3d4d4302 7038 s = bfd_get_linker_section
845b51d6
PB		 7039 (globals->bfd_of_glue_owner, ARM_BX_GLUE_SECTION_NAME);
7040
7041 BFD_ASSERT (s != NULL);
7042
7043 /* Add symbol for veneer. */
21d799b5
NC		 7044 tmp_name = (char *)
7045 bfd_malloc ((bfd_size_type) strlen (ARM_BX_GLUE_ENTRY_NAME) + 1);
906e58ca 7046
845b51d6 7047 BFD_ASSERT (tmp_name);
906e58ca 7048
845b51d6 7049 sprintf (tmp_name, ARM_BX_GLUE_ENTRY_NAME, reg);
906e58ca 7050
845b51d6
PB		 7051 myh = elf_link_hash_lookup
7052 (&(globals)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7053
845b51d6 7054 BFD_ASSERT (myh == NULL);
906e58ca 7055
845b51d6
PB		 7056 bh = NULL;
7057 val = globals->bx_glue_size;
7058 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
99059e56
RM		 7059 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7060 NULL, TRUE, FALSE, &bh);
845b51d6
PB		 7061
7062 myh = (struct elf_link_hash_entry *) bh;
7063 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7064 myh->forced_local = 1;
7065
7066 s->size += ARM_BX_VENEER_SIZE;
7067 globals->bx_glue_offset[reg] = globals->bx_glue_size | 2;
7068 globals->bx_glue_size += ARM_BX_VENEER_SIZE;
7069}
7070
7071
c7b8f16e
JB		 7072/* Add an entry to the code/data map for section SEC. */
7073
7074static void
7075elf32_arm_section_map_add (asection *sec, char type, bfd_vma vma)
7076{
7077 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
7078 unsigned int newidx;
906e58ca 7079
c7b8f16e
JB		 7080 if (sec_data->map == NULL)
7081 {
21d799b5 7082 sec_data->map = (elf32_arm_section_map *)
99059e56 7083 bfd_malloc (sizeof (elf32_arm_section_map));
c7b8f16e
JB		 7084 sec_data->mapcount = 0;
7085 sec_data->mapsize = 1;
7086 }
906e58ca 7087
c7b8f16e 7088 newidx = sec_data->mapcount++;
906e58ca 7089
c7b8f16e
JB		 7090 if (sec_data->mapcount > sec_data->mapsize)
7091 {
7092 sec_data->mapsize *= 2;
21d799b5 7093 sec_data->map = (elf32_arm_section_map *)
99059e56
RM		 7094 bfd_realloc_or_free (sec_data->map, sec_data->mapsize
7095 * sizeof (elf32_arm_section_map));
515ef31d
NC		 7096 }
7097
7098 if (sec_data->map)
7099 {
7100 sec_data->map[newidx].vma = vma;
7101 sec_data->map[newidx].type = type;
c7b8f16e 7102 }
c7b8f16e
JB		 7103}
7104
7105
7106/* Record information about a VFP11 denorm-erratum veneer. Only ARM-mode
7107 veneers are handled for now. */
7108
7109static bfd_vma
7110record_vfp11_erratum_veneer (struct bfd_link_info *link_info,
99059e56
RM		 7111 elf32_vfp11_erratum_list *branch,
7112 bfd *branch_bfd,
7113 asection *branch_sec,
7114 unsigned int offset)
c7b8f16e
JB		 7115{
7116 asection *s;
7117 struct elf32_arm_link_hash_table *hash_table;
7118 char *tmp_name;
7119 struct elf_link_hash_entry *myh;
7120 struct bfd_link_hash_entry *bh;
7121 bfd_vma val;
7122 struct _arm_elf_section_data *sec_data;
c7b8f16e 7123 elf32_vfp11_erratum_list *newerr;
906e58ca 7124
c7b8f16e 7125 hash_table = elf32_arm_hash_table (link_info);
c7b8f16e
JB		 7126 BFD_ASSERT (hash_table != NULL);
7127 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
906e58ca 7128
3d4d4302 7129 s = bfd_get_linker_section
c7b8f16e 7130 (hash_table->bfd_of_glue_owner, VFP11_ERRATUM_VENEER_SECTION_NAME);
906e58ca 7131
c7b8f16e 7132 sec_data = elf32_arm_section_data (s);
906e58ca 7133
c7b8f16e 7134 BFD_ASSERT (s != NULL);
906e58ca 7135
21d799b5 7136 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 7137 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
906e58ca 7138
c7b8f16e 7139 BFD_ASSERT (tmp_name);
906e58ca 7140
c7b8f16e
JB		 7141 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
7142 hash_table->num_vfp11_fixes);
906e58ca 7143
c7b8f16e
JB		 7144 myh = elf_link_hash_lookup
7145 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7146
c7b8f16e 7147 BFD_ASSERT (myh == NULL);
906e58ca 7148
c7b8f16e
JB		 7149 bh = NULL;
7150 val = hash_table->vfp11_erratum_glue_size;
7151 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
99059e56
RM		 7152 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7153 NULL, TRUE, FALSE, &bh);
c7b8f16e
JB		 7154
7155 myh = (struct elf_link_hash_entry *) bh;
7156 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7157 myh->forced_local = 1;
7158
7159 /* Link veneer back to calling location. */
c7e2358a 7160 sec_data->erratumcount += 1;
21d799b5
NC		 7161 newerr = (elf32_vfp11_erratum_list *)
7162 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
906e58ca 7163
c7b8f16e
JB		 7164 newerr->type = VFP11_ERRATUM_ARM_VENEER;
7165 newerr->vma = -1;
7166 newerr->u.v.branch = branch;
7167 newerr->u.v.id = hash_table->num_vfp11_fixes;
7168 branch->u.b.veneer = newerr;
7169
7170 newerr->next = sec_data->erratumlist;
7171 sec_data->erratumlist = newerr;
7172
7173 /* A symbol for the return from the veneer. */
7174 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
7175 hash_table->num_vfp11_fixes);
7176
7177 myh = elf_link_hash_lookup
7178 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7179
c7b8f16e
JB		 7180 if (myh != NULL)
7181 abort ();
7182
7183 bh = NULL;
7184 val = offset + 4;
7185 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7186 branch_sec, val, NULL, TRUE, FALSE, &bh);
906e58ca 7187
c7b8f16e
JB		 7188 myh = (struct elf_link_hash_entry *) bh;
7189 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7190 myh->forced_local = 1;
7191
7192 free (tmp_name);
906e58ca 7193
c7b8f16e
JB		 7194 /* Generate a mapping symbol for the veneer section, and explicitly add an
7195 entry for that symbol to the code/data map for the section. */
7196 if (hash_table->vfp11_erratum_glue_size == 0)
7197 {
7198 bh = NULL;
7199 /* FIXME: Creates an ARM symbol. Thumb mode will need attention if it
99059e56 7200 ever requires this erratum fix. */
c7b8f16e
JB		 7201 _bfd_generic_link_add_one_symbol (link_info,
7202 hash_table->bfd_of_glue_owner, "$a",
7203 BSF_LOCAL, s, 0, NULL,
99059e56 7204 TRUE, FALSE, &bh);
c7b8f16e
JB		 7205
7206 myh = (struct elf_link_hash_entry *) bh;
7207 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7208 myh->forced_local = 1;
906e58ca 7209
c7b8f16e 7210 /* The elf32_arm_init_maps function only cares about symbols from input
99059e56
RM		 7211 BFDs. We must make a note of this generated mapping symbol
7212 ourselves so that code byteswapping works properly in
7213 elf32_arm_write_section. */
c7b8f16e
JB		 7214 elf32_arm_section_map_add (s, 'a', 0);
7215 }
906e58ca 7216
c7b8f16e
JB		 7217 s->size += VFP11_ERRATUM_VENEER_SIZE;
7218 hash_table->vfp11_erratum_glue_size += VFP11_ERRATUM_VENEER_SIZE;
7219 hash_table->num_vfp11_fixes++;
906e58ca 7220
c7b8f16e
JB		 7221 /* The offset of the veneer. */
7222 return val;
7223}
7224
a504d23a
LA		 7225/* Record information about a STM32L4XX STM erratum veneer. Only THUMB-mode
7226 veneers need to be handled because used only in Cortex-M. */
7227
7228static bfd_vma
7229record_stm32l4xx_erratum_veneer (struct bfd_link_info *link_info,
7230 elf32_stm32l4xx_erratum_list *branch,
7231 bfd *branch_bfd,
7232 asection *branch_sec,
7233 unsigned int offset,
7234 bfd_size_type veneer_size)
7235{
7236 asection *s;
7237 struct elf32_arm_link_hash_table *hash_table;
7238 char *tmp_name;
7239 struct elf_link_hash_entry *myh;
7240 struct bfd_link_hash_entry *bh;
7241 bfd_vma val;
7242 struct _arm_elf_section_data *sec_data;
7243 elf32_stm32l4xx_erratum_list *newerr;
7244
7245 hash_table = elf32_arm_hash_table (link_info);
7246 BFD_ASSERT (hash_table != NULL);
7247 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
7248
7249 s = bfd_get_linker_section
7250 (hash_table->bfd_of_glue_owner, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
7251
7252 BFD_ASSERT (s != NULL);
7253
7254 sec_data = elf32_arm_section_data (s);
7255
7256 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
7257 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
7258
7259 BFD_ASSERT (tmp_name);
7260
7261 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
7262 hash_table->num_stm32l4xx_fixes);
7263
7264 myh = elf_link_hash_lookup
7265 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7266
7267 BFD_ASSERT (myh == NULL);
7268
7269 bh = NULL;
7270 val = hash_table->stm32l4xx_erratum_glue_size;
7271 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
7272 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7273 NULL, TRUE, FALSE, &bh);
7274
7275 myh = (struct elf_link_hash_entry *) bh;
7276 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7277 myh->forced_local = 1;
7278
7279 /* Link veneer back to calling location. */
7280 sec_data->stm32l4xx_erratumcount += 1;
7281 newerr = (elf32_stm32l4xx_erratum_list *)
7282 bfd_zmalloc (sizeof (elf32_stm32l4xx_erratum_list));
7283
7284 newerr->type = STM32L4XX_ERRATUM_VENEER;
7285 newerr->vma = -1;
7286 newerr->u.v.branch = branch;
7287 newerr->u.v.id = hash_table->num_stm32l4xx_fixes;
7288 branch->u.b.veneer = newerr;
7289
7290 newerr->next = sec_data->stm32l4xx_erratumlist;
7291 sec_data->stm32l4xx_erratumlist = newerr;
7292
7293 /* A symbol for the return from the veneer. */
7294 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
7295 hash_table->num_stm32l4xx_fixes);
7296
7297 myh = elf_link_hash_lookup
7298 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7299
7300 if (myh != NULL)
7301 abort ();
7302
7303 bh = NULL;
7304 val = offset + 4;
7305 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7306 branch_sec, val, NULL, TRUE, FALSE, &bh);
7307
7308 myh = (struct elf_link_hash_entry *) bh;
7309 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7310 myh->forced_local = 1;
7311
7312 free (tmp_name);
7313
7314 /* Generate a mapping symbol for the veneer section, and explicitly add an
7315 entry for that symbol to the code/data map for the section. */
7316 if (hash_table->stm32l4xx_erratum_glue_size == 0)
7317 {
7318 bh = NULL;
7319 /* Creates a THUMB symbol since there is no other choice. */
7320 _bfd_generic_link_add_one_symbol (link_info,
7321 hash_table->bfd_of_glue_owner, "$t",
7322 BSF_LOCAL, s, 0, NULL,
7323 TRUE, FALSE, &bh);
7324
7325 myh = (struct elf_link_hash_entry *) bh;
7326 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7327 myh->forced_local = 1;
7328
7329 /* The elf32_arm_init_maps function only cares about symbols from input
7330 BFDs. We must make a note of this generated mapping symbol
7331 ourselves so that code byteswapping works properly in
7332 elf32_arm_write_section. */
7333 elf32_arm_section_map_add (s, 't', 0);
7334 }
7335
7336 s->size += veneer_size;
7337 hash_table->stm32l4xx_erratum_glue_size += veneer_size;
7338 hash_table->num_stm32l4xx_fixes++;
7339
7340 /* The offset of the veneer. */
7341 return val;
7342}
7343
8029a119 7344#define ARM_GLUE_SECTION_FLAGS \
3e6b1042
DJ		 7345 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_CODE \
7346 | SEC_READONLY | SEC_LINKER_CREATED)
8029a119
NC		 7347
7348/* Create a fake section for use by the ARM backend of the linker. */
7349
7350static bfd_boolean
7351arm_make_glue_section (bfd * abfd, const char * name)
7352{
7353 asection * sec;
7354
3d4d4302 7355 sec = bfd_get_linker_section (abfd, name);
8029a119
NC		 7356 if (sec != NULL)
7357 /* Already made. */
7358 return TRUE;
7359
3d4d4302 7360 sec = bfd_make_section_anyway_with_flags (abfd, name, ARM_GLUE_SECTION_FLAGS);
8029a119
NC		 7361
7362 if (sec == NULL
7363 || !bfd_set_section_alignment (abfd, sec, 2))
7364 return FALSE;
7365
7366 /* Set the gc mark to prevent the section from being removed by garbage
7367 collection, despite the fact that no relocs refer to this section. */
7368 sec->gc_mark = 1;
7369
7370 return TRUE;
7371}
7372
1db37fe6
YG		 7373/* Set size of .plt entries. This function is called from the
7374 linker scripts in ld/emultempl/{armelf}.em. */
7375
7376void
7377bfd_elf32_arm_use_long_plt (void)
7378{
7379 elf32_arm_use_long_plt_entry = TRUE;
7380}
7381
8afb0e02
NC		 7382/* Add the glue sections to ABFD. This function is called from the
7383 linker scripts in ld/emultempl/{armelf}.em. */
9b485d32 7384
b34976b6 7385bfd_boolean
57e8b36a
NC		 7386bfd_elf32_arm_add_glue_sections_to_bfd (bfd *abfd,
7387 struct bfd_link_info *info)
252b5132 7388{
a504d23a
LA		 7389 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
7390 bfd_boolean dostm32l4xx = globals
7391 && globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE;
7392 bfd_boolean addglue;
7393
8afb0e02
NC		 7394 /* If we are only performing a partial
7395 link do not bother adding the glue. */
0e1862bb 7396 if (bfd_link_relocatable (info))
b34976b6 7397 return TRUE;
252b5132 7398
a504d23a 7399 addglue = arm_make_glue_section (abfd, ARM2THUMB_GLUE_SECTION_NAME)
8029a119
NC		 7400 && arm_make_glue_section (abfd, THUMB2ARM_GLUE_SECTION_NAME)
7401 && arm_make_glue_section (abfd, VFP11_ERRATUM_VENEER_SECTION_NAME)
7402 && arm_make_glue_section (abfd, ARM_BX_GLUE_SECTION_NAME);
a504d23a
LA		 7403
7404 if (!dostm32l4xx)
7405 return addglue;
7406
7407 return addglue
7408 && arm_make_glue_section (abfd, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
8afb0e02
NC		 7409}
7410
daa4adae
TP		 7411/* Mark output sections of veneers needing a dedicated one with SEC_KEEP. This
7412 ensures they are not marked for deletion by
7413 strip_excluded_output_sections () when veneers are going to be created
7414 later. Not doing so would trigger assert on empty section size in
7415 lang_size_sections_1 (). */
7416
7417void
7418bfd_elf32_arm_keep_private_stub_output_sections (struct bfd_link_info *info)
7419{
7420 enum elf32_arm_stub_type stub_type;
7421
7422 /* If we are only performing a partial
7423 link do not bother adding the glue. */
7424 if (bfd_link_relocatable (info))
7425 return;
7426
7427 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
7428 {
7429 asection *out_sec;
7430 const char *out_sec_name;
7431
7432 if (!arm_dedicated_stub_output_section_required (stub_type))
7433 continue;
7434
7435 out_sec_name = arm_dedicated_stub_output_section_name (stub_type);
7436 out_sec = bfd_get_section_by_name (info->output_bfd, out_sec_name);
7437 if (out_sec != NULL)
7438 out_sec->flags |= SEC_KEEP;
7439 }
7440}
7441
8afb0e02
NC		 7442/* Select a BFD to be used to hold the sections used by the glue code.
7443 This function is called from the linker scripts in ld/emultempl/
8029a119 7444 {armelf/pe}.em. */
8afb0e02 7445
b34976b6 7446bfd_boolean
57e8b36a 7447bfd_elf32_arm_get_bfd_for_interworking (bfd *abfd, struct bfd_link_info *info)
8afb0e02
NC		 7448{
7449 struct elf32_arm_link_hash_table *globals;
7450
7451 /* If we are only performing a partial link
7452 do not bother getting a bfd to hold the glue. */
0e1862bb 7453 if (bfd_link_relocatable (info))
b34976b6 7454 return TRUE;
8afb0e02 7455
b7693d02
DJ		 7456 /* Make sure we don't attach the glue sections to a dynamic object. */
7457 BFD_ASSERT (!(abfd->flags & DYNAMIC));
7458
8afb0e02 7459 globals = elf32_arm_hash_table (info);
8afb0e02
NC		 7460 BFD_ASSERT (globals != NULL);
7461
7462 if (globals->bfd_of_glue_owner != NULL)
b34976b6 7463 return TRUE;
8afb0e02 7464
252b5132
RH		 7465 /* Save the bfd for later use. */
7466 globals->bfd_of_glue_owner = abfd;
cedb70c5 7467
b34976b6 7468 return TRUE;
252b5132
RH		 7469}
7470
906e58ca
NC		 7471static void
7472check_use_blx (struct elf32_arm_link_hash_table *globals)
39b41c9c 7473{
2de70689
MGD		 7474 int cpu_arch;
7475
b38cadfb 7476 cpu_arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
2de70689
MGD		 7477 Tag_CPU_arch);
7478
7479 if (globals->fix_arm1176)
7480 {
7481 if (cpu_arch == TAG_CPU_ARCH_V6T2 || cpu_arch > TAG_CPU_ARCH_V6K)
7482 globals->use_blx = 1;
7483 }
7484 else
7485 {
7486 if (cpu_arch > TAG_CPU_ARCH_V4T)
7487 globals->use_blx = 1;
7488 }
39b41c9c
PB		 7489}
7490
b34976b6 7491bfd_boolean
57e8b36a 7492bfd_elf32_arm_process_before_allocation (bfd *abfd,
d504ffc8 7493 struct bfd_link_info *link_info)
252b5132
RH		 7494{
7495 Elf_Internal_Shdr *symtab_hdr;
6cdc0ccc 7496 Elf_Internal_Rela *internal_relocs = NULL;
252b5132
RH		 7497 Elf_Internal_Rela *irel, *irelend;
7498 bfd_byte *contents = NULL;
252b5132
RH		 7499
7500 asection *sec;
7501 struct elf32_arm_link_hash_table *globals;
7502
7503 /* If we are only performing a partial link do not bother
7504 to construct any glue. */
0e1862bb 7505 if (bfd_link_relocatable (link_info))
b34976b6 7506 return TRUE;
252b5132 7507
39ce1a6a
NC		 7508 /* Here we have a bfd that is to be included on the link. We have a
7509 hook to do reloc rummaging, before section sizes are nailed down. */
252b5132 7510 globals = elf32_arm_hash_table (link_info);
252b5132 7511 BFD_ASSERT (globals != NULL);
39ce1a6a
NC		 7512
7513 check_use_blx (globals);
252b5132 7514
d504ffc8 7515 if (globals->byteswap_code && !bfd_big_endian (abfd))
e489d0ae 7516 {
d003868e
AM		 7517 _bfd_error_handler (_("%B: BE8 images only valid in big-endian mode."),
7518 abfd);
e489d0ae
PB		 7519 return FALSE;
7520 }
f21f3fe0 7521
39ce1a6a
NC		 7522 /* PR 5398: If we have not decided to include any loadable sections in
7523 the output then we will not have a glue owner bfd. This is OK, it
7524 just means that there is nothing else for us to do here. */
7525 if (globals->bfd_of_glue_owner == NULL)
7526 return TRUE;
7527
252b5132
RH		 7528 /* Rummage around all the relocs and map the glue vectors. */
7529 sec = abfd->sections;
7530
7531 if (sec == NULL)
b34976b6 7532 return TRUE;
252b5132
RH		 7533
7534 for (; sec != NULL; sec = sec->next)
7535 {
7536 if (sec->reloc_count == 0)
7537 continue;
7538
2f475487
AM		 7539 if ((sec->flags & SEC_EXCLUDE) != 0)
7540 continue;
7541
0ffa91dd 7542 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 7543
9b485d32 7544 /* Load the relocs. */
6cdc0ccc 7545 internal_relocs
906e58ca 7546 = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, FALSE);
252b5132 7547
6cdc0ccc
AM		 7548 if (internal_relocs == NULL)
7549 goto error_return;
252b5132 7550
6cdc0ccc
AM		 7551 irelend = internal_relocs + sec->reloc_count;
7552 for (irel = internal_relocs; irel < irelend; irel++)
252b5132
RH		 7553 {
7554 long r_type;
7555 unsigned long r_index;
252b5132
RH		 7556
7557 struct elf_link_hash_entry *h;
7558
7559 r_type = ELF32_R_TYPE (irel->r_info);
7560 r_index = ELF32_R_SYM (irel->r_info);
7561
9b485d32 7562 /* These are the only relocation types we care about. */
ba96a88f 7563 if ( r_type != R_ARM_PC24
845b51d6 7564 && (r_type != R_ARM_V4BX || globals->fix_v4bx < 2))
252b5132
RH		 7565 continue;
7566
7567 /* Get the section contents if we haven't done so already. */
7568 if (contents == NULL)
7569 {
7570 /* Get cached copy if it exists. */
7571 if (elf_section_data (sec)->this_hdr.contents != NULL)
7572 contents = elf_section_data (sec)->this_hdr.contents;
7573 else
7574 {
7575 /* Go get them off disk. */
57e8b36a 7576 if (! bfd_malloc_and_get_section (abfd, sec, &contents))
252b5132
RH		 7577 goto error_return;
7578 }
7579 }
7580
845b51d6
PB		 7581 if (r_type == R_ARM_V4BX)
7582 {
7583 int reg;
7584
7585 reg = bfd_get_32 (abfd, contents + irel->r_offset) & 0xf;
7586 record_arm_bx_glue (link_info, reg);
7587 continue;
7588 }
7589
a7c10850 7590 /* If the relocation is not against a symbol it cannot concern us. */
252b5132
RH		 7591 h = NULL;
7592
9b485d32 7593 /* We don't care about local symbols. */
252b5132
RH		 7594 if (r_index < symtab_hdr->sh_info)
7595 continue;
7596
9b485d32 7597 /* This is an external symbol. */
252b5132
RH		 7598 r_index -= symtab_hdr->sh_info;
7599 h = (struct elf_link_hash_entry *)
7600 elf_sym_hashes (abfd)[r_index];
7601
7602 /* If the relocation is against a static symbol it must be within
7603 the current section and so cannot be a cross ARM/Thumb relocation. */
7604 if (h == NULL)
7605 continue;
7606
d504ffc8
DJ		 7607 /* If the call will go through a PLT entry then we do not need
7608 glue. */
362d30a1 7609 if (globals->root.splt != NULL && h->plt.offset != (bfd_vma) -1)
b7693d02
DJ		 7610 continue;
7611
252b5132
RH		 7612 switch (r_type)
7613 {
7614 case R_ARM_PC24:
7615 /* This one is a call from arm code. We need to look up
99059e56
RM		 7616 the target of the call. If it is a thumb target, we
7617 insert glue. */
39d911fc
TP		 7618 if (ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
7619 == ST_BRANCH_TO_THUMB)
252b5132
RH		 7620 record_arm_to_thumb_glue (link_info, h);
7621 break;
7622
252b5132 7623 default:
c6596c5e 7624 abort ();
252b5132
RH		 7625 }
7626 }
6cdc0ccc
AM		 7627
7628 if (contents != NULL
7629 && elf_section_data (sec)->this_hdr.contents != contents)
7630 free (contents);
7631 contents = NULL;
7632
7633 if (internal_relocs != NULL
7634 && elf_section_data (sec)->relocs != internal_relocs)
7635 free (internal_relocs);
7636 internal_relocs = NULL;
252b5132
RH		 7637 }
7638
b34976b6 7639 return TRUE;
9a5aca8c 7640
252b5132 7641error_return:
6cdc0ccc
AM		 7642 if (contents != NULL
7643 && elf_section_data (sec)->this_hdr.contents != contents)
7644 free (contents);
7645 if (internal_relocs != NULL
7646 && elf_section_data (sec)->relocs != internal_relocs)
7647 free (internal_relocs);
9a5aca8c 7648
b34976b6 7649 return FALSE;
252b5132 7650}
7e392df6 7651#endif
252b5132 7652
eb043451 7653
c7b8f16e
JB		 7654/* Initialise maps of ARM/Thumb/data for input BFDs. */
7655
7656void
7657bfd_elf32_arm_init_maps (bfd *abfd)
7658{
7659 Elf_Internal_Sym *isymbuf;
7660 Elf_Internal_Shdr *hdr;
7661 unsigned int i, localsyms;
7662
af1f4419
NC		 7663 /* PR 7093: Make sure that we are dealing with an arm elf binary. */
7664 if (! is_arm_elf (abfd))
7665 return;
7666
c7b8f16e
JB		 7667 if ((abfd->flags & DYNAMIC) != 0)
7668 return;
7669
0ffa91dd 7670 hdr = & elf_symtab_hdr (abfd);
c7b8f16e
JB		 7671 localsyms = hdr->sh_info;
7672
7673 /* Obtain a buffer full of symbols for this BFD. The hdr->sh_info field
7674 should contain the number of local symbols, which should come before any
7675 global symbols. Mapping symbols are always local. */
7676 isymbuf = bfd_elf_get_elf_syms (abfd, hdr, localsyms, 0, NULL, NULL,
7677 NULL);
7678
7679 /* No internal symbols read? Skip this BFD. */
7680 if (isymbuf == NULL)
7681 return;
7682
7683 for (i = 0; i < localsyms; i++)
7684 {
7685 Elf_Internal_Sym *isym = &isymbuf[i];
7686 asection *sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
7687 const char *name;
906e58ca 7688
c7b8f16e 7689 if (sec != NULL
99059e56
RM		 7690 && ELF_ST_BIND (isym->st_info) == STB_LOCAL)
7691 {
7692 name = bfd_elf_string_from_elf_section (abfd,
7693 hdr->sh_link, isym->st_name);
906e58ca 7694
99059e56 7695 if (bfd_is_arm_special_symbol_name (name,
c7b8f16e 7696 BFD_ARM_SPECIAL_SYM_TYPE_MAP))
99059e56
RM		 7697 elf32_arm_section_map_add (sec, name[1], isym->st_value);
7698 }
c7b8f16e
JB		 7699 }
7700}
7701
7702
48229727
JB		 7703/* Auto-select enabling of Cortex-A8 erratum fix if the user didn't explicitly
7704 say what they wanted. */
7705
7706void
7707bfd_elf32_arm_set_cortex_a8_fix (bfd *obfd, struct bfd_link_info *link_info)
7708{
7709 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
7710 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
7711
4dfe6ac6
NC		 7712 if (globals == NULL)
7713 return;
7714
48229727
JB		 7715 if (globals->fix_cortex_a8 == -1)
7716 {
7717 /* Turn on Cortex-A8 erratum workaround for ARMv7-A. */
7718 if (out_attr[Tag_CPU_arch].i == TAG_CPU_ARCH_V7
7719 && (out_attr[Tag_CPU_arch_profile].i == 'A'
7720 || out_attr[Tag_CPU_arch_profile].i == 0))
7721 globals->fix_cortex_a8 = 1;
7722 else
7723 globals->fix_cortex_a8 = 0;
7724 }
7725}
7726
7727
c7b8f16e
JB		 7728void
7729bfd_elf32_arm_set_vfp11_fix (bfd *obfd, struct bfd_link_info *link_info)
7730{
7731 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
104d59d1 7732 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
906e58ca 7733
4dfe6ac6
NC		 7734 if (globals == NULL)
7735 return;
c7b8f16e
JB		 7736 /* We assume that ARMv7+ does not need the VFP11 denorm erratum fix. */
7737 if (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V7)
7738 {
7739 switch (globals->vfp11_fix)
99059e56
RM		 7740 {
7741 case BFD_ARM_VFP11_FIX_DEFAULT:
7742 case BFD_ARM_VFP11_FIX_NONE:
7743 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
7744 break;
7745
7746 default:
7747 /* Give a warning, but do as the user requests anyway. */
4eca0228 7748 _bfd_error_handler (_("%B: warning: selected VFP11 erratum "
99059e56
RM		 7749 "workaround is not necessary for target architecture"), obfd);
7750 }
c7b8f16e
JB		 7751 }
7752 else if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_DEFAULT)
7753 /* For earlier architectures, we might need the workaround, but do not
7754 enable it by default. If users is running with broken hardware, they
7755 must enable the erratum fix explicitly. */
7756 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
7757}
7758
a504d23a
LA		 7759void
7760bfd_elf32_arm_set_stm32l4xx_fix (bfd *obfd, struct bfd_link_info *link_info)
7761{
7762 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
7763 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
7764
7765 if (globals == NULL)
7766 return;
7767
7768 /* We assume only Cortex-M4 may require the fix. */
7769 if (out_attr[Tag_CPU_arch].i != TAG_CPU_ARCH_V7E_M
7770 || out_attr[Tag_CPU_arch_profile].i != 'M')
7771 {
7772 if (globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE)
7773 /* Give a warning, but do as the user requests anyway. */
4eca0228 7774 _bfd_error_handler
a504d23a
LA		 7775 (_("%B: warning: selected STM32L4XX erratum "
7776 "workaround is not necessary for target architecture"), obfd);
7777 }
7778}
c7b8f16e 7779
906e58ca
NC		 7780enum bfd_arm_vfp11_pipe
7781{
c7b8f16e
JB		 7782 VFP11_FMAC,
7783 VFP11_LS,
7784 VFP11_DS,
7785 VFP11_BAD
7786};
7787
7788/* Return a VFP register number. This is encoded as RX:X for single-precision
7789 registers, or X:RX for double-precision registers, where RX is the group of
7790 four bits in the instruction encoding and X is the single extension bit.
7791 RX and X fields are specified using their lowest (starting) bit. The return
7792 value is:
7793
7794 0...31: single-precision registers s0...s31
7795 32...63: double-precision registers d0...d31.
906e58ca 7796
c7b8f16e
JB		 7797 Although X should be zero for VFP11 (encoding d0...d15 only), we might
7798 encounter VFP3 instructions, so we allow the full range for DP registers. */
906e58ca 7799
c7b8f16e
JB		 7800static unsigned int
7801bfd_arm_vfp11_regno (unsigned int insn, bfd_boolean is_double, unsigned int rx,
99059e56 7802 unsigned int x)
c7b8f16e
JB		 7803{
7804 if (is_double)
7805 return (((insn >> rx) & 0xf) | (((insn >> x) & 1) << 4)) + 32;
7806 else
7807 return (((insn >> rx) & 0xf) << 1) | ((insn >> x) & 1);
7808}
7809
7810/* Set bits in *WMASK according to a register number REG as encoded by
7811 bfd_arm_vfp11_regno(). Ignore d16-d31. */
7812
7813static void
7814bfd_arm_vfp11_write_mask (unsigned int *wmask, unsigned int reg)
7815{
7816 if (reg < 32)
7817 *wmask |= 1 << reg;
7818 else if (reg < 48)
7819 *wmask |= 3 << ((reg - 32) * 2);
7820}
7821
7822/* Return TRUE if WMASK overwrites anything in REGS. */
7823
7824static bfd_boolean
7825bfd_arm_vfp11_antidependency (unsigned int wmask, int *regs, int numregs)
7826{
7827 int i;
906e58ca 7828
c7b8f16e
JB		 7829 for (i = 0; i < numregs; i++)
7830 {
7831 unsigned int reg = regs[i];
7832
7833 if (reg < 32 && (wmask & (1 << reg)) != 0)
99059e56 7834 return TRUE;
906e58ca 7835
c7b8f16e
JB		 7836 reg -= 32;
7837
7838 if (reg >= 16)
99059e56 7839 continue;
906e58ca 7840
c7b8f16e 7841 if ((wmask & (3 << (reg * 2))) != 0)
99059e56 7842 return TRUE;
c7b8f16e 7843 }
906e58ca 7844
c7b8f16e
JB		 7845 return FALSE;
7846}
7847
7848/* In this function, we're interested in two things: finding input registers
7849 for VFP data-processing instructions, and finding the set of registers which
7850 arbitrary VFP instructions may write to. We use a 32-bit unsigned int to
7851 hold the written set, so FLDM etc. are easy to deal with (we're only
7852 interested in 32 SP registers or 16 dp registers, due to the VFP version
7853 implemented by the chip in question). DP registers are marked by setting
7854 both SP registers in the write mask). */
7855
7856static enum bfd_arm_vfp11_pipe
7857bfd_arm_vfp11_insn_decode (unsigned int insn, unsigned int *destmask, int *regs,
99059e56 7858 int *numregs)
c7b8f16e 7859{
91d6fa6a 7860 enum bfd_arm_vfp11_pipe vpipe = VFP11_BAD;
c7b8f16e
JB		 7861 bfd_boolean is_double = ((insn & 0xf00) == 0xb00) ? 1 : 0;
7862
7863 if ((insn & 0x0f000e10) == 0x0e000a00) /* A data-processing insn. */
7864 {
7865 unsigned int pqrs;
7866 unsigned int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
7867 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
7868
7869 pqrs = ((insn & 0x00800000) >> 20)
99059e56
RM		 7870 | ((insn & 0x00300000) >> 19)
7871 | ((insn & 0x00000040) >> 6);
c7b8f16e
JB		 7872
7873 switch (pqrs)
99059e56
RM		 7874 {
7875 case 0: /* fmac[sd]. */
7876 case 1: /* fnmac[sd]. */
7877 case 2: /* fmsc[sd]. */
7878 case 3: /* fnmsc[sd]. */
7879 vpipe = VFP11_FMAC;
7880 bfd_arm_vfp11_write_mask (destmask, fd);
7881 regs[0] = fd;
7882 regs[1] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
7883 regs[2] = fm;
7884 *numregs = 3;
7885 break;
7886
7887 case 4: /* fmul[sd]. */
7888 case 5: /* fnmul[sd]. */
7889 case 6: /* fadd[sd]. */
7890 case 7: /* fsub[sd]. */
7891 vpipe = VFP11_FMAC;
7892 goto vfp_binop;
7893
7894 case 8: /* fdiv[sd]. */
7895 vpipe = VFP11_DS;
7896 vfp_binop:
7897 bfd_arm_vfp11_write_mask (destmask, fd);
7898 regs[0] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
7899 regs[1] = fm;
7900 *numregs = 2;
7901 break;
7902
7903 case 15: /* extended opcode. */
7904 {
7905 unsigned int extn = ((insn >> 15) & 0x1e)
7906 | ((insn >> 7) & 1);
7907
7908 switch (extn)
7909 {
7910 case 0: /* fcpy[sd]. */
7911 case 1: /* fabs[sd]. */
7912 case 2: /* fneg[sd]. */
7913 case 8: /* fcmp[sd]. */
7914 case 9: /* fcmpe[sd]. */
7915 case 10: /* fcmpz[sd]. */
7916 case 11: /* fcmpez[sd]. */
7917 case 16: /* fuito[sd]. */
7918 case 17: /* fsito[sd]. */
7919 case 24: /* ftoui[sd]. */
7920 case 25: /* ftouiz[sd]. */
7921 case 26: /* ftosi[sd]. */
7922 case 27: /* ftosiz[sd]. */
7923 /* These instructions will not bounce due to underflow. */
7924 *numregs = 0;
7925 vpipe = VFP11_FMAC;
7926 break;
7927
7928 case 3: /* fsqrt[sd]. */
7929 /* fsqrt cannot underflow, but it can (perhaps) overwrite
7930 registers to cause the erratum in previous instructions. */
7931 bfd_arm_vfp11_write_mask (destmask, fd);
7932 vpipe = VFP11_DS;
7933 break;
7934
7935 case 15: /* fcvt{ds,sd}. */
7936 {
7937 int rnum = 0;
7938
7939 bfd_arm_vfp11_write_mask (destmask, fd);
c7b8f16e
JB		 7940
7941 /* Only FCVTSD can underflow. */
99059e56
RM		 7942 if ((insn & 0x100) != 0)
7943 regs[rnum++] = fm;
c7b8f16e 7944
99059e56 7945 *numregs = rnum;
c7b8f16e 7946
99059e56
RM		 7947 vpipe = VFP11_FMAC;
7948 }
7949 break;
c7b8f16e 7950
99059e56
RM		 7951 default:
7952 return VFP11_BAD;
7953 }
7954 }
7955 break;
c7b8f16e 7956
99059e56
RM		 7957 default:
7958 return VFP11_BAD;
7959 }
c7b8f16e
JB		 7960 }
7961 /* Two-register transfer. */
7962 else if ((insn & 0x0fe00ed0) == 0x0c400a10)
7963 {
7964 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
906e58ca 7965
c7b8f16e
JB		 7966 if ((insn & 0x100000) == 0)
7967 {
99059e56
RM		 7968 if (is_double)
7969 bfd_arm_vfp11_write_mask (destmask, fm);
7970 else
7971 {
7972 bfd_arm_vfp11_write_mask (destmask, fm);
7973 bfd_arm_vfp11_write_mask (destmask, fm + 1);
7974 }
c7b8f16e
JB		 7975 }
7976
91d6fa6a 7977 vpipe = VFP11_LS;
c7b8f16e
JB		 7978 }
7979 else if ((insn & 0x0e100e00) == 0x0c100a00) /* A load insn. */
7980 {
7981 int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
7982 unsigned int puw = ((insn >> 21) & 0x1) | (((insn >> 23) & 3) << 1);
906e58ca 7983
c7b8f16e 7984 switch (puw)
99059e56
RM		 7985 {
7986 case 0: /* Two-reg transfer. We should catch these above. */
7987 abort ();
906e58ca 7988
99059e56
RM		 7989 case 2: /* fldm[sdx]. */
7990 case 3:
7991 case 5:
7992 {
7993 unsigned int i, offset = insn & 0xff;
c7b8f16e 7994
99059e56
RM		 7995 if (is_double)
7996 offset >>= 1;
c7b8f16e 7997
99059e56
RM		 7998 for (i = fd; i < fd + offset; i++)
7999 bfd_arm_vfp11_write_mask (destmask, i);
8000 }
8001 break;
906e58ca 8002
99059e56
RM		 8003 case 4: /* fld[sd]. */
8004 case 6:
8005 bfd_arm_vfp11_write_mask (destmask, fd);
8006 break;
906e58ca 8007
99059e56
RM		 8008 default:
8009 return VFP11_BAD;
8010 }
c7b8f16e 8011
91d6fa6a 8012 vpipe = VFP11_LS;
c7b8f16e
JB		 8013 }
8014 /* Single-register transfer. Note L==0. */
8015 else if ((insn & 0x0f100e10) == 0x0e000a10)
8016 {
8017 unsigned int opcode = (insn >> 21) & 7;
8018 unsigned int fn = bfd_arm_vfp11_regno (insn, is_double, 16, 7);
8019
8020 switch (opcode)
99059e56
RM		 8021 {
8022 case 0: /* fmsr/fmdlr. */
8023 case 1: /* fmdhr. */
8024 /* Mark fmdhr and fmdlr as writing to the whole of the DP
8025 destination register. I don't know if this is exactly right,
8026 but it is the conservative choice. */
8027 bfd_arm_vfp11_write_mask (destmask, fn);
8028 break;
8029
8030 case 7: /* fmxr. */
8031 break;
8032 }
c7b8f16e 8033
91d6fa6a 8034 vpipe = VFP11_LS;
c7b8f16e
JB		 8035 }
8036
91d6fa6a 8037 return vpipe;
c7b8f16e
JB		 8038}
8039
8040
8041static int elf32_arm_compare_mapping (const void * a, const void * b);
8042
8043
8044/* Look for potentially-troublesome code sequences which might trigger the
8045 VFP11 denormal/antidependency erratum. See, e.g., the ARM1136 errata sheet
8046 (available from ARM) for details of the erratum. A short version is
8047 described in ld.texinfo. */
8048
8049bfd_boolean
8050bfd_elf32_arm_vfp11_erratum_scan (bfd *abfd, struct bfd_link_info *link_info)
8051{
8052 asection *sec;
8053 bfd_byte *contents = NULL;
8054 int state = 0;
8055 int regs[3], numregs = 0;
8056 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8057 int use_vector = (globals->vfp11_fix == BFD_ARM_VFP11_FIX_VECTOR);
906e58ca 8058
4dfe6ac6
NC		 8059 if (globals == NULL)
8060 return FALSE;
8061
c7b8f16e
JB		 8062 /* We use a simple FSM to match troublesome VFP11 instruction sequences.
8063 The states transition as follows:
906e58ca 8064
c7b8f16e 8065 0 -> 1 (vector) or 0 -> 2 (scalar)
99059e56
RM		 8066 A VFP FMAC-pipeline instruction has been seen. Fill
8067 regs[0]..regs[numregs-1] with its input operands. Remember this
8068 instruction in 'first_fmac'.
c7b8f16e
JB		 8069
8070 1 -> 2
99059e56
RM		 8071 Any instruction, except for a VFP instruction which overwrites
8072 regs[*].
906e58ca 8073
c7b8f16e
JB		 8074 1 -> 3 [ -> 0 ] or
8075 2 -> 3 [ -> 0 ]
99059e56
RM		 8076 A VFP instruction has been seen which overwrites any of regs[*].
8077 We must make a veneer! Reset state to 0 before examining next
8078 instruction.
906e58ca 8079
c7b8f16e 8080 2 -> 0
99059e56
RM		 8081 If we fail to match anything in state 2, reset to state 0 and reset
8082 the instruction pointer to the instruction after 'first_fmac'.
c7b8f16e
JB		 8083
8084 If the VFP11 vector mode is in use, there must be at least two unrelated
8085 instructions between anti-dependent VFP11 instructions to properly avoid
906e58ca 8086 triggering the erratum, hence the use of the extra state 1. */
c7b8f16e
JB		 8087
8088 /* If we are only performing a partial link do not bother
8089 to construct any glue. */
0e1862bb 8090 if (bfd_link_relocatable (link_info))
c7b8f16e
JB		 8091 return TRUE;
8092
0ffa91dd
NC		 8093 /* Skip if this bfd does not correspond to an ELF image. */
8094 if (! is_arm_elf (abfd))
8095 return TRUE;
906e58ca 8096
c7b8f16e
JB		 8097 /* We should have chosen a fix type by the time we get here. */
8098 BFD_ASSERT (globals->vfp11_fix != BFD_ARM_VFP11_FIX_DEFAULT);
8099
8100 if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_NONE)
8101 return TRUE;
2e6030b9 8102
33a7ffc2
JM		 8103 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8104 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8105 return TRUE;
8106
c7b8f16e
JB		 8107 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8108 {
8109 unsigned int i, span, first_fmac = 0, veneer_of_insn = 0;
8110 struct _arm_elf_section_data *sec_data;
8111
8112 /* If we don't have executable progbits, we're not interested in this
99059e56 8113 section. Also skip if section is to be excluded. */
c7b8f16e 8114 if (elf_section_type (sec) != SHT_PROGBITS
99059e56
RM		 8115 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8116 || (sec->flags & SEC_EXCLUDE) != 0
dbaa2011 8117 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
33a7ffc2 8118 || sec->output_section == bfd_abs_section_ptr
99059e56
RM		 8119 || strcmp (sec->name, VFP11_ERRATUM_VENEER_SECTION_NAME) == 0)
8120 continue;
c7b8f16e
JB		 8121
8122 sec_data = elf32_arm_section_data (sec);
906e58ca 8123
c7b8f16e 8124 if (sec_data->mapcount == 0)
99059e56 8125 continue;
906e58ca 8126
c7b8f16e
JB		 8127 if (elf_section_data (sec)->this_hdr.contents != NULL)
8128 contents = elf_section_data (sec)->this_hdr.contents;
8129 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8130 goto error_return;
8131
8132 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8133 elf32_arm_compare_mapping);
8134
8135 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 8136 {
8137 unsigned int span_start = sec_data->map[span].vma;
8138 unsigned int span_end = (span == sec_data->mapcount - 1)
c7b8f16e 8139 ? sec->size : sec_data->map[span + 1].vma;
99059e56
RM		 8140 char span_type = sec_data->map[span].type;
8141
8142 /* FIXME: Only ARM mode is supported at present. We may need to
8143 support Thumb-2 mode also at some point. */
8144 if (span_type != 'a')
8145 continue;
8146
8147 for (i = span_start; i < span_end;)
8148 {
8149 unsigned int next_i = i + 4;
8150 unsigned int insn = bfd_big_endian (abfd)
8151 ? (contents[i] << 24)
8152 | (contents[i + 1] << 16)
8153 | (contents[i + 2] << 8)
8154 | contents[i + 3]
8155 : (contents[i + 3] << 24)
8156 | (contents[i + 2] << 16)
8157 | (contents[i + 1] << 8)
8158 | contents[i];
8159 unsigned int writemask = 0;
8160 enum bfd_arm_vfp11_pipe vpipe;
8161
8162 switch (state)
8163 {
8164 case 0:
8165 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask, regs,
8166 &numregs);
8167 /* I'm assuming the VFP11 erratum can trigger with denorm
8168 operands on either the FMAC or the DS pipeline. This might
8169 lead to slightly overenthusiastic veneer insertion. */
8170 if (vpipe == VFP11_FMAC || vpipe == VFP11_DS)
8171 {
8172 state = use_vector ? 1 : 2;
8173 first_fmac = i;
8174 veneer_of_insn = insn;
8175 }
8176 break;
8177
8178 case 1:
8179 {
8180 int other_regs[3], other_numregs;
8181 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8182 other_regs,
99059e56
RM		 8183 &other_numregs);
8184 if (vpipe != VFP11_BAD
8185 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8186 numregs))
99059e56
RM		 8187 state = 3;
8188 else
8189 state = 2;
8190 }
8191 break;
8192
8193 case 2:
8194 {
8195 int other_regs[3], other_numregs;
8196 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8197 other_regs,
99059e56
RM		 8198 &other_numregs);
8199 if (vpipe != VFP11_BAD
8200 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8201 numregs))
99059e56
RM		 8202 state = 3;
8203 else
8204 {
8205 state = 0;
8206 next_i = first_fmac + 4;
8207 }
8208 }
8209 break;
8210
8211 case 3:
8212 abort (); /* Should be unreachable. */
8213 }
8214
8215 if (state == 3)
8216 {
8217 elf32_vfp11_erratum_list *newerr =(elf32_vfp11_erratum_list *)
8218 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
8219
8220 elf32_arm_section_data (sec)->erratumcount += 1;
8221
8222 newerr->u.b.vfp_insn = veneer_of_insn;
8223
8224 switch (span_type)
8225 {
8226 case 'a':
8227 newerr->type = VFP11_ERRATUM_BRANCH_TO_ARM_VENEER;
8228 break;
8229
8230 default:
8231 abort ();
8232 }
8233
8234 record_vfp11_erratum_veneer (link_info, newerr, abfd, sec,
c7b8f16e
JB		 8235 first_fmac);
8236
99059e56 8237 newerr->vma = -1;
c7b8f16e 8238
99059e56
RM		 8239 newerr->next = sec_data->erratumlist;
8240 sec_data->erratumlist = newerr;
c7b8f16e 8241
99059e56
RM		 8242 state = 0;
8243 }
c7b8f16e 8244
99059e56
RM		 8245 i = next_i;
8246 }
8247 }
906e58ca 8248
c7b8f16e 8249 if (contents != NULL
99059e56
RM		 8250 && elf_section_data (sec)->this_hdr.contents != contents)
8251 free (contents);
c7b8f16e
JB		 8252 contents = NULL;
8253 }
8254
8255 return TRUE;
8256
8257error_return:
8258 if (contents != NULL
8259 && elf_section_data (sec)->this_hdr.contents != contents)
8260 free (contents);
906e58ca 8261
c7b8f16e
JB		 8262 return FALSE;
8263}
8264
8265/* Find virtual-memory addresses for VFP11 erratum veneers and return locations
8266 after sections have been laid out, using specially-named symbols. */
8267
8268void
8269bfd_elf32_arm_vfp11_fix_veneer_locations (bfd *abfd,
8270 struct bfd_link_info *link_info)
8271{
8272 asection *sec;
8273 struct elf32_arm_link_hash_table *globals;
8274 char *tmp_name;
906e58ca 8275
0e1862bb 8276 if (bfd_link_relocatable (link_info))
c7b8f16e 8277 return;
2e6030b9
MS		 8278
8279 /* Skip if this bfd does not correspond to an ELF image. */
0ffa91dd 8280 if (! is_arm_elf (abfd))
2e6030b9
MS		 8281 return;
8282
c7b8f16e 8283 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8284 if (globals == NULL)
8285 return;
906e58ca 8286
21d799b5 8287 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 8288 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
c7b8f16e
JB		 8289
8290 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8291 {
8292 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8293 elf32_vfp11_erratum_list *errnode = sec_data->erratumlist;
906e58ca 8294
c7b8f16e 8295 for (; errnode != NULL; errnode = errnode->next)
99059e56
RM		 8296 {
8297 struct elf_link_hash_entry *myh;
8298 bfd_vma vma;
8299
8300 switch (errnode->type)
8301 {
8302 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
8303 case VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER:
8304 /* Find veneer symbol. */
8305 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
c7b8f16e
JB		 8306 errnode->u.b.veneer->u.v.id);
8307
99059e56
RM		 8308 myh = elf_link_hash_lookup
8309 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
c7b8f16e 8310
a504d23a 8311 if (myh == NULL)
4eca0228
AM		 8312 _bfd_error_handler (_("%B: unable to find VFP11 veneer "
8313 "`%s'"), abfd, tmp_name);
a504d23a
LA		 8314
8315 vma = myh->root.u.def.section->output_section->vma
8316 + myh->root.u.def.section->output_offset
8317 + myh->root.u.def.value;
8318
8319 errnode->u.b.veneer->vma = vma;
8320 break;
8321
8322 case VFP11_ERRATUM_ARM_VENEER:
8323 case VFP11_ERRATUM_THUMB_VENEER:
8324 /* Find return location. */
8325 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
8326 errnode->u.v.id);
8327
8328 myh = elf_link_hash_lookup
8329 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8330
8331 if (myh == NULL)
4eca0228
AM		 8332 _bfd_error_handler (_("%B: unable to find VFP11 veneer "
8333 "`%s'"), abfd, tmp_name);
a504d23a
LA		 8334
8335 vma = myh->root.u.def.section->output_section->vma
8336 + myh->root.u.def.section->output_offset
8337 + myh->root.u.def.value;
8338
8339 errnode->u.v.branch->vma = vma;
8340 break;
8341
8342 default:
8343 abort ();
8344 }
8345 }
8346 }
8347
8348 free (tmp_name);
8349}
8350
8351/* Find virtual-memory addresses for STM32L4XX erratum veneers and
8352 return locations after sections have been laid out, using
8353 specially-named symbols. */
8354
8355void
8356bfd_elf32_arm_stm32l4xx_fix_veneer_locations (bfd *abfd,
8357 struct bfd_link_info *link_info)
8358{
8359 asection *sec;
8360 struct elf32_arm_link_hash_table *globals;
8361 char *tmp_name;
8362
8363 if (bfd_link_relocatable (link_info))
8364 return;
8365
8366 /* Skip if this bfd does not correspond to an ELF image. */
8367 if (! is_arm_elf (abfd))
8368 return;
8369
8370 globals = elf32_arm_hash_table (link_info);
8371 if (globals == NULL)
8372 return;
8373
8374 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
8375 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
8376
8377 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8378 {
8379 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8380 elf32_stm32l4xx_erratum_list *errnode = sec_data->stm32l4xx_erratumlist;
8381
8382 for (; errnode != NULL; errnode = errnode->next)
8383 {
8384 struct elf_link_hash_entry *myh;
8385 bfd_vma vma;
8386
8387 switch (errnode->type)
8388 {
8389 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
8390 /* Find veneer symbol. */
8391 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
8392 errnode->u.b.veneer->u.v.id);
8393
8394 myh = elf_link_hash_lookup
8395 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8396
8397 if (myh == NULL)
4eca0228
AM		 8398 _bfd_error_handler (_("%B: unable to find STM32L4XX veneer "
8399 "`%s'"), abfd, tmp_name);
a504d23a
LA		 8400
8401 vma = myh->root.u.def.section->output_section->vma
8402 + myh->root.u.def.section->output_offset
8403 + myh->root.u.def.value;
8404
8405 errnode->u.b.veneer->vma = vma;
8406 break;
8407
8408 case STM32L4XX_ERRATUM_VENEER:
8409 /* Find return location. */
8410 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
8411 errnode->u.v.id);
8412
8413 myh = elf_link_hash_lookup
8414 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8415
8416 if (myh == NULL)
4eca0228
AM		 8417 _bfd_error_handler (_("%B: unable to find STM32L4XX veneer "
8418 "`%s'"), abfd, tmp_name);
a504d23a
LA		 8419
8420 vma = myh->root.u.def.section->output_section->vma
8421 + myh->root.u.def.section->output_offset
8422 + myh->root.u.def.value;
8423
8424 errnode->u.v.branch->vma = vma;
8425 break;
8426
8427 default:
8428 abort ();
8429 }
8430 }
8431 }
8432
8433 free (tmp_name);
8434}
8435
8436static inline bfd_boolean
8437is_thumb2_ldmia (const insn32 insn)
8438{
8439 /* Encoding T2: LDM<c>.W <Rn>{!},<registers>
8440 1110 - 1000 - 10W1 - rrrr - PM (0) l - llll - llll - llll. */
8441 return (insn & 0xffd02000) == 0xe8900000;
8442}
8443
8444static inline bfd_boolean
8445is_thumb2_ldmdb (const insn32 insn)
8446{
8447 /* Encoding T1: LDMDB<c> <Rn>{!},<registers>
8448 1110 - 1001 - 00W1 - rrrr - PM (0) l - llll - llll - llll. */
8449 return (insn & 0xffd02000) == 0xe9100000;
8450}
8451
8452static inline bfd_boolean
8453is_thumb2_vldm (const insn32 insn)
8454{
8455 /* A6.5 Extension register load or store instruction
8456 A7.7.229
9239bbd3
CM		 8457 We look for SP 32-bit and DP 64-bit registers.
8458 Encoding T1 VLDM{mode}<c> <Rn>{!}, <list>
8459 <list> is consecutive 64-bit registers
8460 1110 - 110P - UDW1 - rrrr - vvvv - 1011 - iiii - iiii
a504d23a
LA		 8461 Encoding T2 VLDM{mode}<c> <Rn>{!}, <list>
8462 <list> is consecutive 32-bit registers
8463 1110 - 110P - UDW1 - rrrr - vvvv - 1010 - iiii - iiii
8464 if P==0 && U==1 && W==1 && Rn=1101 VPOP
8465 if PUW=010 || PUW=011 || PUW=101 VLDM. */
8466 return
9239bbd3
CM		 8467 (((insn & 0xfe100f00) == 0xec100b00) ||
8468 ((insn & 0xfe100f00) == 0xec100a00))
a504d23a
LA		 8469 && /* (IA without !). */
8470 (((((insn << 7) >> 28) & 0xd) == 0x4)
9239bbd3 8471 /* (IA with !), includes VPOP (when reg number is SP). */
a504d23a
LA		 8472 || ((((insn << 7) >> 28) & 0xd) == 0x5)
8473 /* (DB with !). */
8474 || ((((insn << 7) >> 28) & 0xd) == 0x9));
8475}
8476
8477/* STM STM32L4XX erratum : This function assumes that it receives an LDM or
8478 VLDM opcode and:
8479 - computes the number and the mode of memory accesses
8480 - decides if the replacement should be done:
8481 . replaces only if > 8-word accesses
8482 . or (testing purposes only) replaces all accesses. */
8483
8484static bfd_boolean
8485stm32l4xx_need_create_replacing_stub (const insn32 insn,
8486 bfd_arm_stm32l4xx_fix stm32l4xx_fix)
8487{
9239bbd3 8488 int nb_words = 0;
a504d23a
LA		 8489
8490 /* The field encoding the register list is the same for both LDMIA
8491 and LDMDB encodings. */
8492 if (is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn))
b25e998d 8493 nb_words = elf32_arm_popcount (insn & 0x0000ffff);
a504d23a 8494 else if (is_thumb2_vldm (insn))
9239bbd3 8495 nb_words = (insn & 0xff);
a504d23a
LA		 8496
8497 /* DEFAULT mode accounts for the real bug condition situation,
8498 ALL mode inserts stubs for each LDM/VLDM instruction (testing). */
8499 return
9239bbd3 8500 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_DEFAULT) ? nb_words > 8 :
a504d23a
LA		 8501 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_ALL) ? TRUE : FALSE;
8502}
8503
8504/* Look for potentially-troublesome code sequences which might trigger
8505 the STM STM32L4XX erratum. */
8506
8507bfd_boolean
8508bfd_elf32_arm_stm32l4xx_erratum_scan (bfd *abfd,
8509 struct bfd_link_info *link_info)
8510{
8511 asection *sec;
8512 bfd_byte *contents = NULL;
8513 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8514
8515 if (globals == NULL)
8516 return FALSE;
8517
8518 /* If we are only performing a partial link do not bother
8519 to construct any glue. */
8520 if (bfd_link_relocatable (link_info))
8521 return TRUE;
8522
8523 /* Skip if this bfd does not correspond to an ELF image. */
8524 if (! is_arm_elf (abfd))
8525 return TRUE;
8526
8527 if (globals->stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_NONE)
8528 return TRUE;
8529
8530 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8531 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8532 return TRUE;
8533
8534 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8535 {
8536 unsigned int i, span;
8537 struct _arm_elf_section_data *sec_data;
8538
8539 /* If we don't have executable progbits, we're not interested in this
8540 section. Also skip if section is to be excluded. */
8541 if (elf_section_type (sec) != SHT_PROGBITS
8542 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8543 || (sec->flags & SEC_EXCLUDE) != 0
8544 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
8545 || sec->output_section == bfd_abs_section_ptr
8546 || strcmp (sec->name, STM32L4XX_ERRATUM_VENEER_SECTION_NAME) == 0)
8547 continue;
8548
8549 sec_data = elf32_arm_section_data (sec);
c7b8f16e 8550
a504d23a
LA		 8551 if (sec_data->mapcount == 0)
8552 continue;
c7b8f16e 8553
a504d23a
LA		 8554 if (elf_section_data (sec)->this_hdr.contents != NULL)
8555 contents = elf_section_data (sec)->this_hdr.contents;
8556 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8557 goto error_return;
c7b8f16e 8558
a504d23a
LA		 8559 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8560 elf32_arm_compare_mapping);
c7b8f16e 8561
a504d23a
LA		 8562 for (span = 0; span < sec_data->mapcount; span++)
8563 {
8564 unsigned int span_start = sec_data->map[span].vma;
8565 unsigned int span_end = (span == sec_data->mapcount - 1)
8566 ? sec->size : sec_data->map[span + 1].vma;
8567 char span_type = sec_data->map[span].type;
8568 int itblock_current_pos = 0;
c7b8f16e 8569
a504d23a
LA		 8570 /* Only Thumb2 mode need be supported with this CM4 specific
8571 code, we should not encounter any arm mode eg span_type
8572 != 'a'. */
8573 if (span_type != 't')
8574 continue;
c7b8f16e 8575
a504d23a
LA		 8576 for (i = span_start; i < span_end;)
8577 {
8578 unsigned int insn = bfd_get_16 (abfd, &contents[i]);
8579 bfd_boolean insn_32bit = FALSE;
8580 bfd_boolean is_ldm = FALSE;
8581 bfd_boolean is_vldm = FALSE;
8582 bfd_boolean is_not_last_in_it_block = FALSE;
8583
8584 /* The first 16-bits of all 32-bit thumb2 instructions start
8585 with opcode[15..13]=0b111 and the encoded op1 can be anything
8586 except opcode[12..11]!=0b00.
8587 See 32-bit Thumb instruction encoding. */
8588 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
8589 insn_32bit = TRUE;
c7b8f16e 8590
a504d23a
LA		 8591 /* Compute the predicate that tells if the instruction
8592 is concerned by the IT block
8593 - Creates an error if there is a ldm that is not
8594 last in the IT block thus cannot be replaced
8595 - Otherwise we can create a branch at the end of the
8596 IT block, it will be controlled naturally by IT
8597 with the proper pseudo-predicate
8598 - So the only interesting predicate is the one that
8599 tells that we are not on the last item of an IT
8600 block. */
8601 if (itblock_current_pos != 0)
8602 is_not_last_in_it_block = !!--itblock_current_pos;
906e58ca 8603
a504d23a
LA		 8604 if (insn_32bit)
8605 {
8606 /* Load the rest of the insn (in manual-friendly order). */
8607 insn = (insn << 16) | bfd_get_16 (abfd, &contents[i + 2]);
8608 is_ldm = is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn);
8609 is_vldm = is_thumb2_vldm (insn);
8610
8611 /* Veneers are created for (v)ldm depending on
8612 option flags and memory accesses conditions; but
8613 if the instruction is not the last instruction of
8614 an IT block, we cannot create a jump there, so we
8615 bail out. */
5025eb7c
AO		 8616 if ((is_ldm || is_vldm)
8617 && stm32l4xx_need_create_replacing_stub
a504d23a
LA		 8618 (insn, globals->stm32l4xx_fix))
8619 {
8620 if (is_not_last_in_it_block)
8621 {
4eca0228 8622 _bfd_error_handler
695344c0 8623 /* xgettext:c-format */
63a5468a
AM		 8624 (_("%B(%A+0x%lx): error: multiple load detected"
8625 " in non-last IT block instruction :"
8626 " STM32L4XX veneer cannot be generated.\n"
8627 "Use gcc option -mrestrict-it to generate"
8628 " only one instruction per IT block.\n"),
695344c0 8629 abfd, sec, (long) i);
a504d23a
LA		 8630 }
8631 else
8632 {
8633 elf32_stm32l4xx_erratum_list *newerr =
8634 (elf32_stm32l4xx_erratum_list *)
8635 bfd_zmalloc
8636 (sizeof (elf32_stm32l4xx_erratum_list));
8637
8638 elf32_arm_section_data (sec)
8639 ->stm32l4xx_erratumcount += 1;
8640 newerr->u.b.insn = insn;
8641 /* We create only thumb branches. */
8642 newerr->type =
8643 STM32L4XX_ERRATUM_BRANCH_TO_VENEER;
8644 record_stm32l4xx_erratum_veneer
8645 (link_info, newerr, abfd, sec,
8646 i,
8647 is_ldm ?
8648 STM32L4XX_ERRATUM_LDM_VENEER_SIZE:
8649 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
8650 newerr->vma = -1;
8651 newerr->next = sec_data->stm32l4xx_erratumlist;
8652 sec_data->stm32l4xx_erratumlist = newerr;
8653 }
8654 }
8655 }
8656 else
8657 {
8658 /* A7.7.37 IT p208
8659 IT blocks are only encoded in T1
8660 Encoding T1: IT{x{y{z}}} <firstcond>
8661 1 0 1 1 - 1 1 1 1 - firstcond - mask
8662 if mask = '0000' then see 'related encodings'
8663 We don't deal with UNPREDICTABLE, just ignore these.
8664 There can be no nested IT blocks so an IT block
8665 is naturally a new one for which it is worth
8666 computing its size. */
5025eb7c
AO		 8667 bfd_boolean is_newitblock = ((insn & 0xff00) == 0xbf00)
8668 && ((insn & 0x000f) != 0x0000);
a504d23a
LA		 8669 /* If we have a new IT block we compute its size. */
8670 if (is_newitblock)
8671 {
8672 /* Compute the number of instructions controlled
8673 by the IT block, it will be used to decide
8674 whether we are inside an IT block or not. */
8675 unsigned int mask = insn & 0x000f;
8676 itblock_current_pos = 4 - ctz (mask);
8677 }
8678 }
8679
8680 i += insn_32bit ? 4 : 2;
99059e56
RM		 8681 }
8682 }
a504d23a
LA		 8683
8684 if (contents != NULL
8685 && elf_section_data (sec)->this_hdr.contents != contents)
8686 free (contents);
8687 contents = NULL;
c7b8f16e 8688 }
906e58ca 8689
a504d23a
LA		 8690 return TRUE;
8691
8692error_return:
8693 if (contents != NULL
8694 && elf_section_data (sec)->this_hdr.contents != contents)
8695 free (contents);
c7b8f16e 8696
a504d23a
LA		 8697 return FALSE;
8698}
c7b8f16e 8699
eb043451
PB		 8700/* Set target relocation values needed during linking. */
8701
8702void
68c39892 8703bfd_elf32_arm_set_target_params (struct bfd *output_bfd,
bf21ed78 8704 struct bfd_link_info *link_info,
68c39892 8705 struct elf32_arm_params *params)
eb043451
PB		 8706{
8707 struct elf32_arm_link_hash_table *globals;
8708
8709 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8710 if (globals == NULL)
8711 return;
eb043451 8712
68c39892
TP		 8713 globals->target1_is_rel = params->target1_is_rel;
8714 if (strcmp (params->target2_type, "rel") == 0)
eb043451 8715 globals->target2_reloc = R_ARM_REL32;
68c39892 8716 else if (strcmp (params->target2_type, "abs") == 0)
eeac373a 8717 globals->target2_reloc = R_ARM_ABS32;
68c39892 8718 else if (strcmp (params->target2_type, "got-rel") == 0)
eb043451
PB		 8719 globals->target2_reloc = R_ARM_GOT_PREL;
8720 else
8721 {
8722 _bfd_error_handler (_("Invalid TARGET2 relocation type '%s'."),
68c39892 8723 params->target2_type);
eb043451 8724 }
68c39892
TP		 8725 globals->fix_v4bx = params->fix_v4bx;
8726 globals->use_blx |= params->use_blx;
8727 globals->vfp11_fix = params->vfp11_denorm_fix;
8728 globals->stm32l4xx_fix = params->stm32l4xx_fix;
8729 globals->pic_veneer = params->pic_veneer;
8730 globals->fix_cortex_a8 = params->fix_cortex_a8;
8731 globals->fix_arm1176 = params->fix_arm1176;
8732 globals->cmse_implib = params->cmse_implib;
8733 globals->in_implib_bfd = params->in_implib_bfd;
bf21ed78 8734
0ffa91dd 8735 BFD_ASSERT (is_arm_elf (output_bfd));
68c39892
TP		 8736 elf_arm_tdata (output_bfd)->no_enum_size_warning
8737 = params->no_enum_size_warning;
8738 elf_arm_tdata (output_bfd)->no_wchar_size_warning
8739 = params->no_wchar_size_warning;
eb043451 8740}
eb043451 8741
12a0a0fd 8742/* Replace the target offset of a Thumb bl or b.w instruction. */
252b5132 8743
12a0a0fd
PB		 8744static void
8745insert_thumb_branch (bfd *abfd, long int offset, bfd_byte *insn)
8746{
8747 bfd_vma upper;
8748 bfd_vma lower;
8749 int reloc_sign;
8750
8751 BFD_ASSERT ((offset & 1) == 0);
8752
8753 upper = bfd_get_16 (abfd, insn);
8754 lower = bfd_get_16 (abfd, insn + 2);
8755 reloc_sign = (offset < 0) ? 1 : 0;
8756 upper = (upper & ~(bfd_vma) 0x7ff)
8757 | ((offset >> 12) & 0x3ff)
8758 | (reloc_sign << 10);
906e58ca 8759 lower = (lower & ~(bfd_vma) 0x2fff)
12a0a0fd
PB		 8760 | (((!((offset >> 23) & 1)) ^ reloc_sign) << 13)
8761 | (((!((offset >> 22) & 1)) ^ reloc_sign) << 11)
8762 | ((offset >> 1) & 0x7ff);
8763 bfd_put_16 (abfd, upper, insn);
8764 bfd_put_16 (abfd, lower, insn + 2);
252b5132
RH		 8765}
8766
9b485d32
NC		 8767/* Thumb code calling an ARM function. */
8768
252b5132 8769static int
57e8b36a
NC		 8770elf32_thumb_to_arm_stub (struct bfd_link_info * info,
8771 const char * name,
8772 bfd * input_bfd,
8773 bfd * output_bfd,
8774 asection * input_section,
8775 bfd_byte * hit_data,
8776 asection * sym_sec,
8777 bfd_vma offset,
8778 bfd_signed_vma addend,
f2a9dd69
DJ		 8779 bfd_vma val,
8780 char **error_message)
252b5132 8781{
bcbdc74c 8782 asection * s = 0;
dc810e39 8783 bfd_vma my_offset;
252b5132 8784 long int ret_offset;
bcbdc74c
NC		 8785 struct elf_link_hash_entry * myh;
8786 struct elf32_arm_link_hash_table * globals;
252b5132 8787
f2a9dd69 8788 myh = find_thumb_glue (info, name, error_message);
252b5132 8789 if (myh == NULL)
b34976b6 8790 return FALSE;
252b5132
RH		 8791
8792 globals = elf32_arm_hash_table (info);
252b5132
RH		 8793 BFD_ASSERT (globals != NULL);
8794 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8795
8796 my_offset = myh->root.u.def.value;
8797
3d4d4302
AM		 8798 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
8799 THUMB2ARM_GLUE_SECTION_NAME);
252b5132
RH		 8800
8801 BFD_ASSERT (s != NULL);
8802 BFD_ASSERT (s->contents != NULL);
8803 BFD_ASSERT (s->output_section != NULL);
8804
8805 if ((my_offset & 0x01) == 0x01)
8806 {
8807 if (sym_sec != NULL
8808 && sym_sec->owner != NULL
8809 && !INTERWORK_FLAG (sym_sec->owner))
8810 {
4eca0228 8811 _bfd_error_handler
d003868e 8812 (_("%B(%s): warning: interworking not enabled.\n"
3aaeb7d3 8813 " first occurrence: %B: Thumb call to ARM"),
c08bb8dd 8814 sym_sec->owner, name, input_bfd);
252b5132 8815
b34976b6 8816 return FALSE;
252b5132
RH		 8817 }
8818
8819 --my_offset;
8820 myh->root.u.def.value = my_offset;
8821
52ab56c2
PB		 8822 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a1_bx_pc_insn,
8823 s->contents + my_offset);
252b5132 8824
52ab56c2
PB		 8825 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a2_noop_insn,
8826 s->contents + my_offset + 2);
252b5132
RH		 8827
8828 ret_offset =
9b485d32
NC		 8829 /* Address of destination of the stub. */
8830 ((bfd_signed_vma) val)
252b5132 8831 - ((bfd_signed_vma)
57e8b36a
NC		 8832 /* Offset from the start of the current section
8833 to the start of the stubs. */
9b485d32
NC		 8834 (s->output_offset
8835 /* Offset of the start of this stub from the start of the stubs. */
8836 + my_offset
8837 /* Address of the start of the current section. */
8838 + s->output_section->vma)
8839 /* The branch instruction is 4 bytes into the stub. */
8840 + 4
8841 /* ARM branches work from the pc of the instruction + 8. */
8842 + 8);
252b5132 8843
52ab56c2
PB		 8844 put_arm_insn (globals, output_bfd,
8845 (bfd_vma) t2a3_b_insn | ((ret_offset >> 2) & 0x00FFFFFF),
8846 s->contents + my_offset + 4);
252b5132
RH		 8847 }
8848
8849 BFD_ASSERT (my_offset <= globals->thumb_glue_size);
8850
427bfd90
NC		 8851 /* Now go back and fix up the original BL insn to point to here. */
8852 ret_offset =
8853 /* Address of where the stub is located. */
8854 (s->output_section->vma + s->output_offset + my_offset)
8855 /* Address of where the BL is located. */
57e8b36a
NC		 8856 - (input_section->output_section->vma + input_section->output_offset
8857 + offset)
427bfd90
NC		 8858 /* Addend in the relocation. */
8859 - addend
8860 /* Biassing for PC-relative addressing. */
8861 - 8;
252b5132 8862
12a0a0fd 8863 insert_thumb_branch (input_bfd, ret_offset, hit_data - input_section->vma);
252b5132 8864
b34976b6 8865 return TRUE;
252b5132
RH		 8866}
8867
a4fd1a8e 8868/* Populate an Arm to Thumb stub. Returns the stub symbol. */
9b485d32 8869
a4fd1a8e
PB		 8870static struct elf_link_hash_entry *
8871elf32_arm_create_thumb_stub (struct bfd_link_info * info,
8872 const char * name,
8873 bfd * input_bfd,
8874 bfd * output_bfd,
8875 asection * sym_sec,
8876 bfd_vma val,
8029a119
NC		 8877 asection * s,
8878 char ** error_message)
252b5132 8879{
dc810e39 8880 bfd_vma my_offset;
252b5132 8881 long int ret_offset;
bcbdc74c
NC		 8882 struct elf_link_hash_entry * myh;
8883 struct elf32_arm_link_hash_table * globals;
252b5132 8884
f2a9dd69 8885 myh = find_arm_glue (info, name, error_message);
252b5132 8886 if (myh == NULL)
a4fd1a8e 8887 return NULL;
252b5132
RH		 8888
8889 globals = elf32_arm_hash_table (info);
252b5132
RH		 8890 BFD_ASSERT (globals != NULL);
8891 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8892
8893 my_offset = myh->root.u.def.value;
252b5132
RH		 8894
8895 if ((my_offset & 0x01) == 0x01)
8896 {
8897 if (sym_sec != NULL
8898 && sym_sec->owner != NULL
8899 && !INTERWORK_FLAG (sym_sec->owner))
8900 {
4eca0228 8901 _bfd_error_handler
d003868e
AM		 8902 (_("%B(%s): warning: interworking not enabled.\n"
8903 " first occurrence: %B: arm call to thumb"),
c08bb8dd 8904 sym_sec->owner, name, input_bfd);
252b5132 8905 }
9b485d32 8906
252b5132
RH		 8907 --my_offset;
8908 myh->root.u.def.value = my_offset;
8909
0e1862bb
L		 8910 if (bfd_link_pic (info)
8911 || globals->root.is_relocatable_executable
27e55c4d 8912 || globals->pic_veneer)
8f6277f5
PB		 8913 {
8914 /* For relocatable objects we can't use absolute addresses,
8915 so construct the address from a relative offset. */
8916 /* TODO: If the offset is small it's probably worth
8917 constructing the address with adds. */
52ab56c2
PB		 8918 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1p_ldr_insn,
8919 s->contents + my_offset);
8920 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2p_add_pc_insn,
8921 s->contents + my_offset + 4);
8922 put_arm_insn (globals, output_bfd, (bfd_vma) a2t3p_bx_r12_insn,
8923 s->contents + my_offset + 8);
8f6277f5
PB		 8924 /* Adjust the offset by 4 for the position of the add,
8925 and 8 for the pipeline offset. */
8926 ret_offset = (val - (s->output_offset
8927 + s->output_section->vma
8928 + my_offset + 12))
8929 | 1;
8930 bfd_put_32 (output_bfd, ret_offset,
8931 s->contents + my_offset + 12);
8932 }
26079076
PB		 8933 else if (globals->use_blx)
8934 {
8935 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1v5_ldr_insn,
8936 s->contents + my_offset);
8937
8938 /* It's a thumb address. Add the low order bit. */
8939 bfd_put_32 (output_bfd, val | a2t2v5_func_addr_insn,
8940 s->contents + my_offset + 4);
8941 }
8f6277f5
PB		 8942 else
8943 {
52ab56c2
PB		 8944 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1_ldr_insn,
8945 s->contents + my_offset);
252b5132 8946
52ab56c2
PB		 8947 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2_bx_r12_insn,
8948 s->contents + my_offset + 4);
252b5132 8949
8f6277f5
PB		 8950 /* It's a thumb address. Add the low order bit. */
8951 bfd_put_32 (output_bfd, val | a2t3_func_addr_insn,
8952 s->contents + my_offset + 8);
8029a119
NC		 8953
8954 my_offset += 12;
8f6277f5 8955 }
252b5132
RH		 8956 }
8957
8958 BFD_ASSERT (my_offset <= globals->arm_glue_size);
8959
a4fd1a8e
PB		 8960 return myh;
8961}
8962
8963/* Arm code calling a Thumb function. */
8964
8965static int
8966elf32_arm_to_thumb_stub (struct bfd_link_info * info,
8967 const char * name,
8968 bfd * input_bfd,
8969 bfd * output_bfd,
8970 asection * input_section,
8971 bfd_byte * hit_data,
8972 asection * sym_sec,
8973 bfd_vma offset,
8974 bfd_signed_vma addend,
f2a9dd69
DJ		 8975 bfd_vma val,
8976 char **error_message)
a4fd1a8e
PB		 8977{
8978 unsigned long int tmp;
8979 bfd_vma my_offset;
8980 asection * s;
8981 long int ret_offset;
8982 struct elf_link_hash_entry * myh;
8983 struct elf32_arm_link_hash_table * globals;
8984
8985 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 8986 BFD_ASSERT (globals != NULL);
8987 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8988
3d4d4302
AM		 8989 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
8990 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 8991 BFD_ASSERT (s != NULL);
8992 BFD_ASSERT (s->contents != NULL);
8993 BFD_ASSERT (s->output_section != NULL);
8994
8995 myh = elf32_arm_create_thumb_stub (info, name, input_bfd, output_bfd,
f2a9dd69 8996 sym_sec, val, s, error_message);
a4fd1a8e
PB		 8997 if (!myh)
8998 return FALSE;
8999
9000 my_offset = myh->root.u.def.value;
252b5132
RH		 9001 tmp = bfd_get_32 (input_bfd, hit_data);
9002 tmp = tmp & 0xFF000000;
9003
9b485d32 9004 /* Somehow these are both 4 too far, so subtract 8. */
dc810e39
AM		 9005 ret_offset = (s->output_offset
9006 + my_offset
9007 + s->output_section->vma
9008 - (input_section->output_offset
9009 + input_section->output_section->vma
9010 + offset + addend)
9011 - 8);
9a5aca8c 9012
252b5132
RH		 9013 tmp = tmp | ((ret_offset >> 2) & 0x00FFFFFF);
9014
dc810e39 9015 bfd_put_32 (output_bfd, (bfd_vma) tmp, hit_data - input_section->vma);
252b5132 9016
b34976b6 9017 return TRUE;
252b5132
RH		 9018}
9019
a4fd1a8e
PB		 9020/* Populate Arm stub for an exported Thumb function. */
9021
9022static bfd_boolean
9023elf32_arm_to_thumb_export_stub (struct elf_link_hash_entry *h, void * inf)
9024{
9025 struct bfd_link_info * info = (struct bfd_link_info *) inf;
9026 asection * s;
9027 struct elf_link_hash_entry * myh;
9028 struct elf32_arm_link_hash_entry *eh;
9029 struct elf32_arm_link_hash_table * globals;
9030 asection *sec;
9031 bfd_vma val;
f2a9dd69 9032 char *error_message;
a4fd1a8e 9033
906e58ca 9034 eh = elf32_arm_hash_entry (h);
a4fd1a8e
PB		 9035 /* Allocate stubs for exported Thumb functions on v4t. */
9036 if (eh->export_glue == NULL)
9037 return TRUE;
9038
9039 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 9040 BFD_ASSERT (globals != NULL);
9041 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9042
3d4d4302
AM		 9043 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9044 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 9045 BFD_ASSERT (s != NULL);
9046 BFD_ASSERT (s->contents != NULL);
9047 BFD_ASSERT (s->output_section != NULL);
9048
9049 sec = eh->export_glue->root.u.def.section;
0eaedd0e
PB		 9050
9051 BFD_ASSERT (sec->output_section != NULL);
9052
a4fd1a8e
PB		 9053 val = eh->export_glue->root.u.def.value + sec->output_offset
9054 + sec->output_section->vma;
8029a119 9055
a4fd1a8e
PB		 9056 myh = elf32_arm_create_thumb_stub (info, h->root.root.string,
9057 h->root.u.def.section->owner,
f2a9dd69
DJ		 9058 globals->obfd, sec, val, s,
9059 &error_message);
a4fd1a8e
PB		 9060 BFD_ASSERT (myh);
9061 return TRUE;
9062}
9063
845b51d6
PB		 9064/* Populate ARMv4 BX veneers. Returns the absolute adress of the veneer. */
9065
9066static bfd_vma
9067elf32_arm_bx_glue (struct bfd_link_info * info, int reg)
9068{
9069 bfd_byte *p;
9070 bfd_vma glue_addr;
9071 asection *s;
9072 struct elf32_arm_link_hash_table *globals;
9073
9074 globals = elf32_arm_hash_table (info);
845b51d6
PB		 9075 BFD_ASSERT (globals != NULL);
9076 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9077
3d4d4302
AM		 9078 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9079 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 9080 BFD_ASSERT (s != NULL);
9081 BFD_ASSERT (s->contents != NULL);
9082 BFD_ASSERT (s->output_section != NULL);
9083
9084 BFD_ASSERT (globals->bx_glue_offset[reg] & 2);
9085
9086 glue_addr = globals->bx_glue_offset[reg] & ~(bfd_vma)3;
9087
9088 if ((globals->bx_glue_offset[reg] & 1) == 0)
9089 {
9090 p = s->contents + glue_addr;
9091 bfd_put_32 (globals->obfd, armbx1_tst_insn + (reg << 16), p);
9092 bfd_put_32 (globals->obfd, armbx2_moveq_insn + reg, p + 4);
9093 bfd_put_32 (globals->obfd, armbx3_bx_insn + reg, p + 8);
9094 globals->bx_glue_offset[reg] |= 1;
9095 }
9096
9097 return glue_addr + s->output_section->vma + s->output_offset;
9098}
9099
a4fd1a8e
PB		 9100/* Generate Arm stubs for exported Thumb symbols. */
9101static void
906e58ca 9102elf32_arm_begin_write_processing (bfd *abfd ATTRIBUTE_UNUSED,
a4fd1a8e
PB		 9103 struct bfd_link_info *link_info)
9104{
9105 struct elf32_arm_link_hash_table * globals;
9106
8029a119
NC		 9107 if (link_info == NULL)
9108 /* Ignore this if we are not called by the ELF backend linker. */
a4fd1a8e
PB		 9109 return;
9110
9111 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 9112 if (globals == NULL)
9113 return;
9114
84c08195
PB		 9115 /* If blx is available then exported Thumb symbols are OK and there is
9116 nothing to do. */
a4fd1a8e
PB		 9117 if (globals->use_blx)
9118 return;
9119
9120 elf_link_hash_traverse (&globals->root, elf32_arm_to_thumb_export_stub,
9121 link_info);
9122}
9123
47beaa6a
RS		 9124/* Reserve space for COUNT dynamic relocations in relocation selection
9125 SRELOC. */
9126
9127static void
9128elf32_arm_allocate_dynrelocs (struct bfd_link_info *info, asection *sreloc,
9129 bfd_size_type count)
9130{
9131 struct elf32_arm_link_hash_table *htab;
9132
9133 htab = elf32_arm_hash_table (info);
9134 BFD_ASSERT (htab->root.dynamic_sections_created);
9135 if (sreloc == NULL)
9136 abort ();
9137 sreloc->size += RELOC_SIZE (htab) * count;
9138}
9139
34e77a92
RS		 9140/* Reserve space for COUNT R_ARM_IRELATIVE relocations. If the link is
9141 dynamic, the relocations should go in SRELOC, otherwise they should
9142 go in the special .rel.iplt section. */
9143
9144static void
9145elf32_arm_allocate_irelocs (struct bfd_link_info *info, asection *sreloc,
9146 bfd_size_type count)
9147{
9148 struct elf32_arm_link_hash_table *htab;
9149
9150 htab = elf32_arm_hash_table (info);
9151 if (!htab->root.dynamic_sections_created)
9152 htab->root.irelplt->size += RELOC_SIZE (htab) * count;
9153 else
9154 {
9155 BFD_ASSERT (sreloc != NULL);
9156 sreloc->size += RELOC_SIZE (htab) * count;
9157 }
9158}
9159
47beaa6a
RS		 9160/* Add relocation REL to the end of relocation section SRELOC. */
9161
9162static void
9163elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
9164 asection *sreloc, Elf_Internal_Rela *rel)
9165{
9166 bfd_byte *loc;
9167 struct elf32_arm_link_hash_table *htab;
9168
9169 htab = elf32_arm_hash_table (info);
34e77a92
RS		 9170 if (!htab->root.dynamic_sections_created
9171 && ELF32_R_TYPE (rel->r_info) == R_ARM_IRELATIVE)
9172 sreloc = htab->root.irelplt;
47beaa6a
RS		 9173 if (sreloc == NULL)
9174 abort ();
9175 loc = sreloc->contents;
9176 loc += sreloc->reloc_count++ * RELOC_SIZE (htab);
9177 if (sreloc->reloc_count * RELOC_SIZE (htab) > sreloc->size)
9178 abort ();
9179 SWAP_RELOC_OUT (htab) (output_bfd, rel, loc);
9180}
9181
34e77a92
RS		 9182/* Allocate room for a PLT entry described by ROOT_PLT and ARM_PLT.
9183 IS_IPLT_ENTRY says whether the entry belongs to .iplt rather than
9184 to .plt. */
9185
9186static void
9187elf32_arm_allocate_plt_entry (struct bfd_link_info *info,
9188 bfd_boolean is_iplt_entry,
9189 union gotplt_union *root_plt,
9190 struct arm_plt_info *arm_plt)
9191{
9192 struct elf32_arm_link_hash_table *htab;
9193 asection *splt;
9194 asection *sgotplt;
9195
9196 htab = elf32_arm_hash_table (info);
9197
9198 if (is_iplt_entry)
9199 {
9200 splt = htab->root.iplt;
9201 sgotplt = htab->root.igotplt;
9202
99059e56
RM		 9203 /* NaCl uses a special first entry in .iplt too. */
9204 if (htab->nacl_p && splt->size == 0)
9205 splt->size += htab->plt_header_size;
9206
34e77a92
RS		 9207 /* Allocate room for an R_ARM_IRELATIVE relocation in .rel.iplt. */
9208 elf32_arm_allocate_irelocs (info, htab->root.irelplt, 1);
9209 }
9210 else
9211 {
9212 splt = htab->root.splt;
9213 sgotplt = htab->root.sgotplt;
9214
9215 /* Allocate room for an R_JUMP_SLOT relocation in .rel.plt. */
9216 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
9217
9218 /* If this is the first .plt entry, make room for the special
9219 first entry. */
9220 if (splt->size == 0)
9221 splt->size += htab->plt_header_size;
9f19ab6d
WN		 9222
9223 htab->next_tls_desc_index++;
34e77a92
RS		 9224 }
9225
9226 /* Allocate the PLT entry itself, including any leading Thumb stub. */
9227 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9228 splt->size += PLT_THUMB_STUB_SIZE;
9229 root_plt->offset = splt->size;
9230 splt->size += htab->plt_entry_size;
9231
9232 if (!htab->symbian_p)
9233 {
9234 /* We also need to make an entry in the .got.plt section, which
9235 will be placed in the .got section by the linker script. */
9f19ab6d
WN		 9236 if (is_iplt_entry)
9237 arm_plt->got_offset = sgotplt->size;
9238 else
9239 arm_plt->got_offset = sgotplt->size - 8 * htab->num_tls_desc;
34e77a92
RS		 9240 sgotplt->size += 4;
9241 }
9242}
9243
b38cadfb
NC		 9244static bfd_vma
9245arm_movw_immediate (bfd_vma value)
9246{
9247 return (value & 0x00000fff) | ((value & 0x0000f000) << 4);
9248}
9249
9250static bfd_vma
9251arm_movt_immediate (bfd_vma value)
9252{
9253 return ((value & 0x0fff0000) >> 16) | ((value & 0xf0000000) >> 12);
9254}
9255
34e77a92
RS		 9256/* Fill in a PLT entry and its associated GOT slot. If DYNINDX == -1,
9257 the entry lives in .iplt and resolves to (*SYM_VALUE)().
9258 Otherwise, DYNINDX is the index of the symbol in the dynamic
9259 symbol table and SYM_VALUE is undefined.
9260
9261 ROOT_PLT points to the offset of the PLT entry from the start of its
9262 section (.iplt or .plt). ARM_PLT points to the symbol's ARM-specific
57460bcf 9263 bookkeeping information.
34e77a92 9264
57460bcf
NC		 9265 Returns FALSE if there was a problem. */
9266
9267static bfd_boolean
34e77a92
RS		 9268elf32_arm_populate_plt_entry (bfd *output_bfd, struct bfd_link_info *info,
9269 union gotplt_union *root_plt,
9270 struct arm_plt_info *arm_plt,
9271 int dynindx, bfd_vma sym_value)
9272{
9273 struct elf32_arm_link_hash_table *htab;
9274 asection *sgot;
9275 asection *splt;
9276 asection *srel;
9277 bfd_byte *loc;
9278 bfd_vma plt_index;
9279 Elf_Internal_Rela rel;
9280 bfd_vma plt_header_size;
9281 bfd_vma got_header_size;
9282
9283 htab = elf32_arm_hash_table (info);
9284
9285 /* Pick the appropriate sections and sizes. */
9286 if (dynindx == -1)
9287 {
9288 splt = htab->root.iplt;
9289 sgot = htab->root.igotplt;
9290 srel = htab->root.irelplt;
9291
9292 /* There are no reserved entries in .igot.plt, and no special
9293 first entry in .iplt. */
9294 got_header_size = 0;
9295 plt_header_size = 0;
9296 }
9297 else
9298 {
9299 splt = htab->root.splt;
9300 sgot = htab->root.sgotplt;
9301 srel = htab->root.srelplt;
9302
9303 got_header_size = get_elf_backend_data (output_bfd)->got_header_size;
9304 plt_header_size = htab->plt_header_size;
9305 }
9306 BFD_ASSERT (splt != NULL && srel != NULL);
9307
9308 /* Fill in the entry in the procedure linkage table. */
9309 if (htab->symbian_p)
9310 {
9311 BFD_ASSERT (dynindx >= 0);
9312 put_arm_insn (htab, output_bfd,
9313 elf32_arm_symbian_plt_entry[0],
9314 splt->contents + root_plt->offset);
9315 bfd_put_32 (output_bfd,
9316 elf32_arm_symbian_plt_entry[1],
9317 splt->contents + root_plt->offset + 4);
9318
9319 /* Fill in the entry in the .rel.plt section. */
9320 rel.r_offset = (splt->output_section->vma
9321 + splt->output_offset
9322 + root_plt->offset + 4);
9323 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_GLOB_DAT);
9324
9325 /* Get the index in the procedure linkage table which
9326 corresponds to this symbol. This is the index of this symbol
9327 in all the symbols for which we are making plt entries. The
9328 first entry in the procedure linkage table is reserved. */
9329 plt_index = ((root_plt->offset - plt_header_size)
9330 / htab->plt_entry_size);
9331 }
9332 else
9333 {
9334 bfd_vma got_offset, got_address, plt_address;
9335 bfd_vma got_displacement, initial_got_entry;
9336 bfd_byte * ptr;
9337
9338 BFD_ASSERT (sgot != NULL);
9339
9340 /* Get the offset into the .(i)got.plt table of the entry that
9341 corresponds to this function. */
9342 got_offset = (arm_plt->got_offset & -2);
9343
9344 /* Get the index in the procedure linkage table which
9345 corresponds to this symbol. This is the index of this symbol
9346 in all the symbols for which we are making plt entries.
9347 After the reserved .got.plt entries, all symbols appear in
9348 the same order as in .plt. */
9349 plt_index = (got_offset - got_header_size) / 4;
9350
9351 /* Calculate the address of the GOT entry. */
9352 got_address = (sgot->output_section->vma
9353 + sgot->output_offset
9354 + got_offset);
9355
9356 /* ...and the address of the PLT entry. */
9357 plt_address = (splt->output_section->vma
9358 + splt->output_offset
9359 + root_plt->offset);
9360
9361 ptr = splt->contents + root_plt->offset;
0e1862bb 9362 if (htab->vxworks_p && bfd_link_pic (info))
34e77a92
RS		 9363 {
9364 unsigned int i;
9365 bfd_vma val;
9366
9367 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9368 {
9369 val = elf32_arm_vxworks_shared_plt_entry[i];
9370 if (i == 2)
9371 val |= got_address - sgot->output_section->vma;
9372 if (i == 5)
9373 val |= plt_index * RELOC_SIZE (htab);
9374 if (i == 2 || i == 5)
9375 bfd_put_32 (output_bfd, val, ptr);
9376 else
9377 put_arm_insn (htab, output_bfd, val, ptr);
9378 }
9379 }
9380 else if (htab->vxworks_p)
9381 {
9382 unsigned int i;
9383 bfd_vma val;
9384
9385 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9386 {
9387 val = elf32_arm_vxworks_exec_plt_entry[i];
9388 if (i == 2)
9389 val |= got_address;
9390 if (i == 4)
9391 val |= 0xffffff & -((root_plt->offset + i * 4 + 8) >> 2);
9392 if (i == 5)
9393 val |= plt_index * RELOC_SIZE (htab);
9394 if (i == 2 || i == 5)
9395 bfd_put_32 (output_bfd, val, ptr);
9396 else
9397 put_arm_insn (htab, output_bfd, val, ptr);
9398 }
9399
9400 loc = (htab->srelplt2->contents
9401 + (plt_index * 2 + 1) * RELOC_SIZE (htab));
9402
9403 /* Create the .rela.plt.unloaded R_ARM_ABS32 relocation
9404 referencing the GOT for this PLT entry. */
9405 rel.r_offset = plt_address + 8;
9406 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
9407 rel.r_addend = got_offset;
9408 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9409 loc += RELOC_SIZE (htab);
9410
9411 /* Create the R_ARM_ABS32 relocation referencing the
9412 beginning of the PLT for this GOT entry. */
9413 rel.r_offset = got_address;
9414 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
9415 rel.r_addend = 0;
9416 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9417 }
b38cadfb
NC		 9418 else if (htab->nacl_p)
9419 {
9420 /* Calculate the displacement between the PLT slot and the
9421 common tail that's part of the special initial PLT slot. */
6034aab8 9422 int32_t tail_displacement
b38cadfb
NC		 9423 = ((splt->output_section->vma + splt->output_offset
9424 + ARM_NACL_PLT_TAIL_OFFSET)
9425 - (plt_address + htab->plt_entry_size + 4));
9426 BFD_ASSERT ((tail_displacement & 3) == 0);
9427 tail_displacement >>= 2;
9428
9429 BFD_ASSERT ((tail_displacement & 0xff000000) == 0
9430 || (-tail_displacement & 0xff000000) == 0);
9431
9432 /* Calculate the displacement between the PLT slot and the entry
9433 in the GOT. The offset accounts for the value produced by
9434 adding to pc in the penultimate instruction of the PLT stub. */
6034aab8 9435 got_displacement = (got_address
99059e56 9436 - (plt_address + htab->plt_entry_size));
b38cadfb
NC		 9437
9438 /* NaCl does not support interworking at all. */
9439 BFD_ASSERT (!elf32_arm_plt_needs_thumb_stub_p (info, arm_plt));
9440
9441 put_arm_insn (htab, output_bfd,
9442 elf32_arm_nacl_plt_entry[0]
9443 | arm_movw_immediate (got_displacement),
9444 ptr + 0);
9445 put_arm_insn (htab, output_bfd,
9446 elf32_arm_nacl_plt_entry[1]
9447 | arm_movt_immediate (got_displacement),
9448 ptr + 4);
9449 put_arm_insn (htab, output_bfd,
9450 elf32_arm_nacl_plt_entry[2],
9451 ptr + 8);
9452 put_arm_insn (htab, output_bfd,
9453 elf32_arm_nacl_plt_entry[3]
9454 | (tail_displacement & 0x00ffffff),
9455 ptr + 12);
9456 }
57460bcf
NC		 9457 else if (using_thumb_only (htab))
9458 {
eed94f8f 9459 /* PR ld/16017: Generate thumb only PLT entries. */
469a3493 9460 if (!using_thumb2 (htab))
eed94f8f
NC		 9461 {
9462 /* FIXME: We ought to be able to generate thumb-1 PLT
9463 instructions... */
9464 _bfd_error_handler (_("%B: Warning: thumb-1 mode PLT generation not currently supported"),
9465 output_bfd);
9466 return FALSE;
9467 }
57460bcf 9468
eed94f8f
NC		 9469 /* Calculate the displacement between the PLT slot and the entry in
9470 the GOT. The 12-byte offset accounts for the value produced by
9471 adding to pc in the 3rd instruction of the PLT stub. */
9472 got_displacement = got_address - (plt_address + 12);
9473
9474 /* As we are using 32 bit instructions we have to use 'put_arm_insn'
9475 instead of 'put_thumb_insn'. */
9476 put_arm_insn (htab, output_bfd,
9477 elf32_thumb2_plt_entry[0]
9478 | ((got_displacement & 0x000000ff) << 16)
9479 | ((got_displacement & 0x00000700) << 20)
9480 | ((got_displacement & 0x00000800) >> 1)
9481 | ((got_displacement & 0x0000f000) >> 12),
9482 ptr + 0);
9483 put_arm_insn (htab, output_bfd,
9484 elf32_thumb2_plt_entry[1]
9485 | ((got_displacement & 0x00ff0000) )
9486 | ((got_displacement & 0x07000000) << 4)
9487 | ((got_displacement & 0x08000000) >> 17)
9488 | ((got_displacement & 0xf0000000) >> 28),
9489 ptr + 4);
9490 put_arm_insn (htab, output_bfd,
9491 elf32_thumb2_plt_entry[2],
9492 ptr + 8);
9493 put_arm_insn (htab, output_bfd,
9494 elf32_thumb2_plt_entry[3],
9495 ptr + 12);
57460bcf 9496 }
34e77a92
RS		 9497 else
9498 {
9499 /* Calculate the displacement between the PLT slot and the
9500 entry in the GOT. The eight-byte offset accounts for the
9501 value produced by adding to pc in the first instruction
9502 of the PLT stub. */
9503 got_displacement = got_address - (plt_address + 8);
9504
34e77a92
RS		 9505 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9506 {
9507 put_thumb_insn (htab, output_bfd,
9508 elf32_arm_plt_thumb_stub[0], ptr - 4);
9509 put_thumb_insn (htab, output_bfd,
9510 elf32_arm_plt_thumb_stub[1], ptr - 2);
9511 }
9512
1db37fe6
YG		 9513 if (!elf32_arm_use_long_plt_entry)
9514 {
9515 BFD_ASSERT ((got_displacement & 0xf0000000) == 0);
9516
9517 put_arm_insn (htab, output_bfd,
9518 elf32_arm_plt_entry_short[0]
9519 | ((got_displacement & 0x0ff00000) >> 20),
9520 ptr + 0);
9521 put_arm_insn (htab, output_bfd,
9522 elf32_arm_plt_entry_short[1]
9523 | ((got_displacement & 0x000ff000) >> 12),
9524 ptr+ 4);
9525 put_arm_insn (htab, output_bfd,
9526 elf32_arm_plt_entry_short[2]
9527 | (got_displacement & 0x00000fff),
9528 ptr + 8);
34e77a92 9529#ifdef FOUR_WORD_PLT
1db37fe6 9530 bfd_put_32 (output_bfd, elf32_arm_plt_entry_short[3], ptr + 12);
34e77a92 9531#endif
1db37fe6
YG		 9532 }
9533 else
9534 {
9535 put_arm_insn (htab, output_bfd,
9536 elf32_arm_plt_entry_long[0]
9537 | ((got_displacement & 0xf0000000) >> 28),
9538 ptr + 0);
9539 put_arm_insn (htab, output_bfd,
9540 elf32_arm_plt_entry_long[1]
9541 | ((got_displacement & 0x0ff00000) >> 20),
9542 ptr + 4);
9543 put_arm_insn (htab, output_bfd,
9544 elf32_arm_plt_entry_long[2]
9545 | ((got_displacement & 0x000ff000) >> 12),
9546 ptr+ 8);
9547 put_arm_insn (htab, output_bfd,
9548 elf32_arm_plt_entry_long[3]
9549 | (got_displacement & 0x00000fff),
9550 ptr + 12);
9551 }
34e77a92
RS		 9552 }
9553
9554 /* Fill in the entry in the .rel(a).(i)plt section. */
9555 rel.r_offset = got_address;
9556 rel.r_addend = 0;
9557 if (dynindx == -1)
9558 {
9559 /* .igot.plt entries use IRELATIVE relocations against SYM_VALUE.
9560 The dynamic linker or static executable then calls SYM_VALUE
9561 to determine the correct run-time value of the .igot.plt entry. */
9562 rel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
9563 initial_got_entry = sym_value;
9564 }
9565 else
9566 {
9567 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_JUMP_SLOT);
9568 initial_got_entry = (splt->output_section->vma
9569 + splt->output_offset);
9570 }
9571
9572 /* Fill in the entry in the global offset table. */
9573 bfd_put_32 (output_bfd, initial_got_entry,
9574 sgot->contents + got_offset);
9575 }
9576
aba8c3de
WN		 9577 if (dynindx == -1)
9578 elf32_arm_add_dynreloc (output_bfd, info, srel, &rel);
9579 else
9580 {
9581 loc = srel->contents + plt_index * RELOC_SIZE (htab);
9582 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9583 }
57460bcf
NC		 9584
9585 return TRUE;
34e77a92
RS		 9586}
9587
eb043451
PB		 9588/* Some relocations map to different relocations depending on the
9589 target. Return the real relocation. */
8029a119 9590
eb043451
PB		 9591static int
9592arm_real_reloc_type (struct elf32_arm_link_hash_table * globals,
9593 int r_type)
9594{
9595 switch (r_type)
9596 {
9597 case R_ARM_TARGET1:
9598 if (globals->target1_is_rel)
9599 return R_ARM_REL32;
9600 else
9601 return R_ARM_ABS32;
9602
9603 case R_ARM_TARGET2:
9604 return globals->target2_reloc;
9605
9606 default:
9607 return r_type;
9608 }
9609}
eb043451 9610
ba93b8ac
DJ		 9611/* Return the base VMA address which should be subtracted from real addresses
9612 when resolving @dtpoff relocation.
9613 This is PT_TLS segment p_vaddr. */
9614
9615static bfd_vma
9616dtpoff_base (struct bfd_link_info *info)
9617{
9618 /* If tls_sec is NULL, we should have signalled an error already. */
9619 if (elf_hash_table (info)->tls_sec == NULL)
9620 return 0;
9621 return elf_hash_table (info)->tls_sec->vma;
9622}
9623
9624/* Return the relocation value for @tpoff relocation
9625 if STT_TLS virtual address is ADDRESS. */
9626
9627static bfd_vma
9628tpoff (struct bfd_link_info *info, bfd_vma address)
9629{
9630 struct elf_link_hash_table *htab = elf_hash_table (info);
9631 bfd_vma base;
9632
9633 /* If tls_sec is NULL, we should have signalled an error already. */
9634 if (htab->tls_sec == NULL)
9635 return 0;
9636 base = align_power ((bfd_vma) TCB_SIZE, htab->tls_sec->alignment_power);
9637 return address - htab->tls_sec->vma + base;
9638}
9639
00a97672
RS		 9640/* Perform an R_ARM_ABS12 relocation on the field pointed to by DATA.
9641 VALUE is the relocation value. */
9642
9643static bfd_reloc_status_type
9644elf32_arm_abs12_reloc (bfd *abfd, void *data, bfd_vma value)
9645{
9646 if (value > 0xfff)
9647 return bfd_reloc_overflow;
9648
9649 value |= bfd_get_32 (abfd, data) & 0xfffff000;
9650 bfd_put_32 (abfd, value, data);
9651 return bfd_reloc_ok;
9652}
9653
0855e32b
NS		 9654/* Handle TLS relaxations. Relaxing is possible for symbols that use
9655 R_ARM_GOTDESC, R_ARM_{,THM_}TLS_CALL or
9656 R_ARM_{,THM_}TLS_DESCSEQ relocations, during a static link.
9657
9658 Return bfd_reloc_ok if we're done, bfd_reloc_continue if the caller
9659 is to then call final_link_relocate. Return other values in the
62672b10
NS		 9660 case of error.
9661
9662 FIXME:When --emit-relocs is in effect, we'll emit relocs describing
9663 the pre-relaxed code. It would be nice if the relocs were updated
9664 to match the optimization. */
0855e32b 9665
b38cadfb 9666static bfd_reloc_status_type
0855e32b 9667elf32_arm_tls_relax (struct elf32_arm_link_hash_table *globals,
b38cadfb 9668 bfd *input_bfd, asection *input_sec, bfd_byte *contents,
0855e32b
NS		 9669 Elf_Internal_Rela *rel, unsigned long is_local)
9670{
9671 unsigned long insn;
b38cadfb 9672
0855e32b
NS		 9673 switch (ELF32_R_TYPE (rel->r_info))
9674 {
9675 default:
9676 return bfd_reloc_notsupported;
b38cadfb 9677
0855e32b
NS		 9678 case R_ARM_TLS_GOTDESC:
9679 if (is_local)
9680 insn = 0;
9681 else
9682 {
9683 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
9684 if (insn & 1)
9685 insn -= 5; /* THUMB */
9686 else
9687 insn -= 8; /* ARM */
9688 }
9689 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
9690 return bfd_reloc_continue;
9691
9692 case R_ARM_THM_TLS_DESCSEQ:
9693 /* Thumb insn. */
9694 insn = bfd_get_16 (input_bfd, contents + rel->r_offset);
9695 if ((insn & 0xff78) == 0x4478) /* add rx, pc */
9696 {
9697 if (is_local)
9698 /* nop */
9699 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
9700 }
9701 else if ((insn & 0xffc0) == 0x6840) /* ldr rx,[ry,#4] */
9702 {
9703 if (is_local)
9704 /* nop */
9705 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
9706 else
9707 /* ldr rx,[ry] */
9708 bfd_put_16 (input_bfd, insn & 0xf83f, contents + rel->r_offset);
9709 }
9710 else if ((insn & 0xff87) == 0x4780) /* blx rx */
9711 {
9712 if (is_local)
9713 /* nop */
9714 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
9715 else
9716 /* mov r0, rx */
9717 bfd_put_16 (input_bfd, 0x4600 | (insn & 0x78),
9718 contents + rel->r_offset);
9719 }
9720 else
9721 {
9722 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
9723 /* It's a 32 bit instruction, fetch the rest of it for
9724 error generation. */
9725 insn = (insn << 16)
9726 | bfd_get_16 (input_bfd, contents + rel->r_offset + 2);
4eca0228 9727 _bfd_error_handler
695344c0
NC		 9728 /* xgettext:c-format */
9729 (_("%B(%A+0x%lx): unexpected Thumb instruction '0x%x' in TLS trampoline"),
0855e32b
NS		 9730 input_bfd, input_sec, (unsigned long)rel->r_offset, insn);
9731 return bfd_reloc_notsupported;
9732 }
9733 break;
b38cadfb 9734
0855e32b
NS		 9735 case R_ARM_TLS_DESCSEQ:
9736 /* arm insn. */
9737 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
9738 if ((insn & 0xffff0ff0) == 0xe08f0000) /* add rx,pc,ry */
9739 {
9740 if (is_local)
9741 /* mov rx, ry */
9742 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xffff),
9743 contents + rel->r_offset);
9744 }
9745 else if ((insn & 0xfff00fff) == 0xe5900004) /* ldr rx,[ry,#4]*/
9746 {
9747 if (is_local)
9748 /* nop */
9749 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
9750 else
9751 /* ldr rx,[ry] */
9752 bfd_put_32 (input_bfd, insn & 0xfffff000,
9753 contents + rel->r_offset);
9754 }
9755 else if ((insn & 0xfffffff0) == 0xe12fff30) /* blx rx */
9756 {
9757 if (is_local)
9758 /* nop */
9759 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
9760 else
9761 /* mov r0, rx */
9762 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xf),
9763 contents + rel->r_offset);
9764 }
9765 else
9766 {
4eca0228 9767 _bfd_error_handler
695344c0
NC		 9768 /* xgettext:c-format */
9769 (_("%B(%A+0x%lx): unexpected ARM instruction '0x%x' in TLS trampoline"),
0855e32b
NS		 9770 input_bfd, input_sec, (unsigned long)rel->r_offset, insn);
9771 return bfd_reloc_notsupported;
9772 }
9773 break;
9774
9775 case R_ARM_TLS_CALL:
9776 /* GD->IE relaxation, turn the instruction into 'nop' or
9777 'ldr r0, [pc,r0]' */
9778 insn = is_local ? 0xe1a00000 : 0xe79f0000;
9779 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
9780 break;
b38cadfb 9781
0855e32b 9782 case R_ARM_THM_TLS_CALL:
6a631e86 9783 /* GD->IE relaxation. */
0855e32b
NS		 9784 if (!is_local)
9785 /* add r0,pc; ldr r0, [r0] */
9786 insn = 0x44786800;
60a019a0 9787 else if (using_thumb2 (globals))
0855e32b
NS		 9788 /* nop.w */
9789 insn = 0xf3af8000;
9790 else
9791 /* nop; nop */
9792 insn = 0xbf00bf00;
b38cadfb 9793
0855e32b
NS		 9794 bfd_put_16 (input_bfd, insn >> 16, contents + rel->r_offset);
9795 bfd_put_16 (input_bfd, insn & 0xffff, contents + rel->r_offset + 2);
9796 break;
9797 }
9798 return bfd_reloc_ok;
9799}
9800
4962c51a
MS		 9801/* For a given value of n, calculate the value of G_n as required to
9802 deal with group relocations. We return it in the form of an
9803 encoded constant-and-rotation, together with the final residual. If n is
9804 specified as less than zero, then final_residual is filled with the
9805 input value and no further action is performed. */
9806
9807static bfd_vma
9808calculate_group_reloc_mask (bfd_vma value, int n, bfd_vma *final_residual)
9809{
9810 int current_n;
9811 bfd_vma g_n;
9812 bfd_vma encoded_g_n = 0;
9813 bfd_vma residual = value; /* Also known as Y_n. */
9814
9815 for (current_n = 0; current_n <= n; current_n++)
9816 {
9817 int shift;
9818
9819 /* Calculate which part of the value to mask. */
9820 if (residual == 0)
99059e56 9821 shift = 0;
4962c51a 9822 else
99059e56
RM		 9823 {
9824 int msb;
9825
9826 /* Determine the most significant bit in the residual and
9827 align the resulting value to a 2-bit boundary. */
9828 for (msb = 30; msb >= 0; msb -= 2)
9829 if (residual & (3 << msb))
9830 break;
9831
9832 /* The desired shift is now (msb - 6), or zero, whichever
9833 is the greater. */
9834 shift = msb - 6;
9835 if (shift < 0)
9836 shift = 0;
9837 }
4962c51a
MS		 9838
9839 /* Calculate g_n in 32-bit as well as encoded constant+rotation form. */
9840 g_n = residual & (0xff << shift);
9841 encoded_g_n = (g_n >> shift)
99059e56 9842 | ((g_n <= 0xff ? 0 : (32 - shift) / 2) << 8);
4962c51a
MS		 9843
9844 /* Calculate the residual for the next time around. */
9845 residual &= ~g_n;
9846 }
9847
9848 *final_residual = residual;
9849
9850 return encoded_g_n;
9851}
9852
9853/* Given an ARM instruction, determine whether it is an ADD or a SUB.
9854 Returns 1 if it is an ADD, -1 if it is a SUB, and 0 otherwise. */
906e58ca 9855
4962c51a 9856static int
906e58ca 9857identify_add_or_sub (bfd_vma insn)
4962c51a
MS		 9858{
9859 int opcode = insn & 0x1e00000;
9860
9861 if (opcode == 1 << 23) /* ADD */
9862 return 1;
9863
9864 if (opcode == 1 << 22) /* SUB */
9865 return -1;
9866
9867 return 0;
9868}
9869
252b5132 9870/* Perform a relocation as part of a final link. */
9b485d32 9871
252b5132 9872static bfd_reloc_status_type
57e8b36a
NC		 9873elf32_arm_final_link_relocate (reloc_howto_type * howto,
9874 bfd * input_bfd,
9875 bfd * output_bfd,
9876 asection * input_section,
9877 bfd_byte * contents,
9878 Elf_Internal_Rela * rel,
9879 bfd_vma value,
9880 struct bfd_link_info * info,
9881 asection * sym_sec,
9882 const char * sym_name,
34e77a92
RS		 9883 unsigned char st_type,
9884 enum arm_st_branch_type branch_type,
0945cdfd 9885 struct elf_link_hash_entry * h,
f2a9dd69 9886 bfd_boolean * unresolved_reloc_p,
8029a119 9887 char ** error_message)
252b5132
RH		 9888{
9889 unsigned long r_type = howto->type;
9890 unsigned long r_symndx;
9891 bfd_byte * hit_data = contents + rel->r_offset;
252b5132 9892 bfd_vma * local_got_offsets;
0855e32b 9893 bfd_vma * local_tlsdesc_gotents;
34e77a92
RS		 9894 asection * sgot;
9895 asection * splt;
252b5132 9896 asection * sreloc = NULL;
362d30a1 9897 asection * srelgot;
252b5132 9898 bfd_vma addend;
ba96a88f 9899 bfd_signed_vma signed_addend;
34e77a92
RS		 9900 unsigned char dynreloc_st_type;
9901 bfd_vma dynreloc_value;
ba96a88f 9902 struct elf32_arm_link_hash_table * globals;
34e77a92
RS		 9903 struct elf32_arm_link_hash_entry *eh;
9904 union gotplt_union *root_plt;
9905 struct arm_plt_info *arm_plt;
9906 bfd_vma plt_offset;
9907 bfd_vma gotplt_offset;
9908 bfd_boolean has_iplt_entry;
f21f3fe0 9909
9c504268 9910 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 9911 if (globals == NULL)
9912 return bfd_reloc_notsupported;
9c504268 9913
0ffa91dd
NC		 9914 BFD_ASSERT (is_arm_elf (input_bfd));
9915
9916 /* Some relocation types map to different relocations depending on the
9c504268 9917 target. We pick the right one here. */
eb043451 9918 r_type = arm_real_reloc_type (globals, r_type);
0855e32b
NS		 9919
9920 /* It is possible to have linker relaxations on some TLS access
9921 models. Update our information here. */
9922 r_type = elf32_arm_tls_transition (info, r_type, h);
9923
eb043451
PB		 9924 if (r_type != howto->type)
9925 howto = elf32_arm_howto_from_type (r_type);
9c504268 9926
34e77a92 9927 eh = (struct elf32_arm_link_hash_entry *) h;
362d30a1 9928 sgot = globals->root.sgot;
252b5132 9929 local_got_offsets = elf_local_got_offsets (input_bfd);
0855e32b
NS		 9930 local_tlsdesc_gotents = elf32_arm_local_tlsdesc_gotent (input_bfd);
9931
34e77a92
RS		 9932 if (globals->root.dynamic_sections_created)
9933 srelgot = globals->root.srelgot;
9934 else
9935 srelgot = NULL;
9936
252b5132
RH		 9937 r_symndx = ELF32_R_SYM (rel->r_info);
9938
4e7fd91e 9939 if (globals->use_rel)
ba96a88f 9940 {
4e7fd91e
PB		 9941 addend = bfd_get_32 (input_bfd, hit_data) & howto->src_mask;
9942
9943 if (addend & ((howto->src_mask + 1) >> 1))
9944 {
9945 signed_addend = -1;
9946 signed_addend &= ~ howto->src_mask;
9947 signed_addend |= addend;
9948 }
9949 else
9950 signed_addend = addend;
ba96a88f
NC		 9951 }
9952 else
4e7fd91e 9953 addend = signed_addend = rel->r_addend;
f21f3fe0 9954
39f21624
NC		 9955 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
9956 are resolving a function call relocation. */
9957 if (using_thumb_only (globals)
9958 && (r_type == R_ARM_THM_CALL
9959 || r_type == R_ARM_THM_JUMP24)
9960 && branch_type == ST_BRANCH_TO_ARM)
9961 branch_type = ST_BRANCH_TO_THUMB;
9962
34e77a92
RS		 9963 /* Record the symbol information that should be used in dynamic
9964 relocations. */
9965 dynreloc_st_type = st_type;
9966 dynreloc_value = value;
9967 if (branch_type == ST_BRANCH_TO_THUMB)
9968 dynreloc_value |= 1;
9969
9970 /* Find out whether the symbol has a PLT. Set ST_VALUE, BRANCH_TYPE and
9971 VALUE appropriately for relocations that we resolve at link time. */
9972 has_iplt_entry = FALSE;
4ba2ef8f
TP		 9973 if (elf32_arm_get_plt_info (input_bfd, globals, eh, r_symndx, &root_plt,
9974 &arm_plt)
34e77a92
RS		 9975 && root_plt->offset != (bfd_vma) -1)
9976 {
9977 plt_offset = root_plt->offset;
9978 gotplt_offset = arm_plt->got_offset;
9979
9980 if (h == NULL || eh->is_iplt)
9981 {
9982 has_iplt_entry = TRUE;
9983 splt = globals->root.iplt;
9984
9985 /* Populate .iplt entries here, because not all of them will
9986 be seen by finish_dynamic_symbol. The lower bit is set if
9987 we have already populated the entry. */
9988 if (plt_offset & 1)
9989 plt_offset--;
9990 else
9991 {
57460bcf
NC		 9992 if (elf32_arm_populate_plt_entry (output_bfd, info, root_plt, arm_plt,
9993 -1, dynreloc_value))
9994 root_plt->offset |= 1;
9995 else
9996 return bfd_reloc_notsupported;
34e77a92
RS		 9997 }
9998
9999 /* Static relocations always resolve to the .iplt entry. */
10000 st_type = STT_FUNC;
10001 value = (splt->output_section->vma
10002 + splt->output_offset
10003 + plt_offset);
10004 branch_type = ST_BRANCH_TO_ARM;
10005
10006 /* If there are non-call relocations that resolve to the .iplt
10007 entry, then all dynamic ones must too. */
10008 if (arm_plt->noncall_refcount != 0)
10009 {
10010 dynreloc_st_type = st_type;
10011 dynreloc_value = value;
10012 }
10013 }
10014 else
10015 /* We populate the .plt entry in finish_dynamic_symbol. */
10016 splt = globals->root.splt;
10017 }
10018 else
10019 {
10020 splt = NULL;
10021 plt_offset = (bfd_vma) -1;
10022 gotplt_offset = (bfd_vma) -1;
10023 }
10024
252b5132
RH		 10025 switch (r_type)
10026 {
10027 case R_ARM_NONE:
28a094c2
DJ		 10028 /* We don't need to find a value for this symbol. It's just a
10029 marker. */
10030 *unresolved_reloc_p = FALSE;
252b5132
RH		 10031 return bfd_reloc_ok;
10032
00a97672
RS		 10033 case R_ARM_ABS12:
10034 if (!globals->vxworks_p)
10035 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
1a0670f3 10036 /* Fall through. */
00a97672 10037
252b5132
RH		 10038 case R_ARM_PC24:
10039 case R_ARM_ABS32:
bb224fc3 10040 case R_ARM_ABS32_NOI:
252b5132 10041 case R_ARM_REL32:
bb224fc3 10042 case R_ARM_REL32_NOI:
5b5bb741
PB		 10043 case R_ARM_CALL:
10044 case R_ARM_JUMP24:
dfc5f959 10045 case R_ARM_XPC25:
eb043451 10046 case R_ARM_PREL31:
7359ea65 10047 case R_ARM_PLT32:
7359ea65
DJ		 10048 /* Handle relocations which should use the PLT entry. ABS32/REL32
10049 will use the symbol's value, which may point to a PLT entry, but we
10050 don't need to handle that here. If we created a PLT entry, all
5fa9e92f
CL		 10051 branches in this object should go to it, except if the PLT is too
10052 far away, in which case a long branch stub should be inserted. */
bb224fc3 10053 if ((r_type != R_ARM_ABS32 && r_type != R_ARM_REL32
99059e56 10054 && r_type != R_ARM_ABS32_NOI && r_type != R_ARM_REL32_NOI
155d87d7
CL		 10055 && r_type != R_ARM_CALL
10056 && r_type != R_ARM_JUMP24
10057 && r_type != R_ARM_PLT32)
34e77a92 10058 && plt_offset != (bfd_vma) -1)
7359ea65 10059 {
34e77a92
RS		 10060 /* If we've created a .plt section, and assigned a PLT entry
10061 to this function, it must either be a STT_GNU_IFUNC reference
10062 or not be known to bind locally. In other cases, we should
10063 have cleared the PLT entry by now. */
10064 BFD_ASSERT (has_iplt_entry || !SYMBOL_CALLS_LOCAL (info, h));
7359ea65
DJ		 10065
10066 value = (splt->output_section->vma
10067 + splt->output_offset
34e77a92 10068 + plt_offset);
0945cdfd 10069 *unresolved_reloc_p = FALSE;
7359ea65
DJ		 10070 return _bfd_final_link_relocate (howto, input_bfd, input_section,
10071 contents, rel->r_offset, value,
00a97672 10072 rel->r_addend);
7359ea65
DJ		 10073 }
10074
67687978
PB		 10075 /* When generating a shared object or relocatable executable, these
10076 relocations are copied into the output file to be resolved at
10077 run time. */
0e1862bb
L		 10078 if ((bfd_link_pic (info)
10079 || globals->root.is_relocatable_executable)
7359ea65 10080 && (input_section->flags & SEC_ALLOC)
4dfe6ac6 10081 && !(globals->vxworks_p
3348747a
NS		 10082 && strcmp (input_section->output_section->name,
10083 ".tls_vars") == 0)
bb224fc3 10084 && ((r_type != R_ARM_REL32 && r_type != R_ARM_REL32_NOI)
ee06dc07 10085 || !SYMBOL_CALLS_LOCAL (info, h))
ca6b5f82
AM		 10086 && !(input_bfd == globals->stub_bfd
10087 && strstr (input_section->name, STUB_SUFFIX))
7359ea65
DJ		 10088 && (h == NULL
10089 || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
10090 || h->root.type != bfd_link_hash_undefweak)
10091 && r_type != R_ARM_PC24
5b5bb741
PB		 10092 && r_type != R_ARM_CALL
10093 && r_type != R_ARM_JUMP24
ee06dc07 10094 && r_type != R_ARM_PREL31
7359ea65 10095 && r_type != R_ARM_PLT32)
252b5132 10096 {
947216bf 10097 Elf_Internal_Rela outrel;
b34976b6 10098 bfd_boolean skip, relocate;
f21f3fe0 10099
52db4ec2
JW		 10100 if ((r_type == R_ARM_REL32 || r_type == R_ARM_REL32_NOI)
10101 && !h->def_regular)
10102 {
10103 char *v = _("shared object");
10104
0e1862bb 10105 if (bfd_link_executable (info))
52db4ec2
JW		 10106 v = _("PIE executable");
10107
4eca0228 10108 _bfd_error_handler
52db4ec2
JW		 10109 (_("%B: relocation %s against external or undefined symbol `%s'"
10110 " can not be used when making a %s; recompile with -fPIC"), input_bfd,
10111 elf32_arm_howto_table_1[r_type].name, h->root.root.string, v);
10112 return bfd_reloc_notsupported;
10113 }
10114
0945cdfd
DJ		 10115 *unresolved_reloc_p = FALSE;
10116
34e77a92 10117 if (sreloc == NULL && globals->root.dynamic_sections_created)
252b5132 10118 {
83bac4b0
NC		 10119 sreloc = _bfd_elf_get_dynamic_reloc_section (input_bfd, input_section,
10120 ! globals->use_rel);
f21f3fe0 10121
83bac4b0 10122 if (sreloc == NULL)
252b5132 10123 return bfd_reloc_notsupported;
252b5132 10124 }
f21f3fe0 10125
b34976b6
AM		 10126 skip = FALSE;
10127 relocate = FALSE;
f21f3fe0 10128
00a97672 10129 outrel.r_addend = addend;
c629eae0
JJ		 10130 outrel.r_offset =
10131 _bfd_elf_section_offset (output_bfd, info, input_section,
10132 rel->r_offset);
10133 if (outrel.r_offset == (bfd_vma) -1)
b34976b6 10134 skip = TRUE;
0bb2d96a 10135 else if (outrel.r_offset == (bfd_vma) -2)
b34976b6 10136 skip = TRUE, relocate = TRUE;
252b5132
RH		 10137 outrel.r_offset += (input_section->output_section->vma
10138 + input_section->output_offset);
f21f3fe0 10139
252b5132 10140 if (skip)
0bb2d96a 10141 memset (&outrel, 0, sizeof outrel);
5e681ec4
PB		 10142 else if (h != NULL
10143 && h->dynindx != -1
0e1862bb 10144 && (!bfd_link_pic (info)
1dcb9720
JW		 10145 || !(bfd_link_pie (info)
10146 || SYMBOLIC_BIND (info, h))
f5385ebf 10147 || !h->def_regular))
5e681ec4 10148 outrel.r_info = ELF32_R_INFO (h->dynindx, r_type);
252b5132
RH		 10149 else
10150 {
a16385dc
MM		 10151 int symbol;
10152
5e681ec4 10153 /* This symbol is local, or marked to become local. */
34e77a92 10154 BFD_ASSERT (r_type == R_ARM_ABS32 || r_type == R_ARM_ABS32_NOI);
a16385dc 10155 if (globals->symbian_p)
6366ff1e 10156 {
74541ad4
AM		 10157 asection *osec;
10158
6366ff1e
MM		 10159 /* On Symbian OS, the data segment and text segement
10160 can be relocated independently. Therefore, we
10161 must indicate the segment to which this
10162 relocation is relative. The BPABI allows us to
10163 use any symbol in the right segment; we just use
10164 the section symbol as it is convenient. (We
10165 cannot use the symbol given by "h" directly as it
74541ad4
AM		 10166 will not appear in the dynamic symbol table.)
10167
10168 Note that the dynamic linker ignores the section
10169 symbol value, so we don't subtract osec->vma
10170 from the emitted reloc addend. */
10dbd1f3 10171 if (sym_sec)
74541ad4 10172 osec = sym_sec->output_section;
10dbd1f3 10173 else
74541ad4
AM		 10174 osec = input_section->output_section;
10175 symbol = elf_section_data (osec)->dynindx;
10176 if (symbol == 0)
10177 {
10178 struct elf_link_hash_table *htab = elf_hash_table (info);
10179
10180 if ((osec->flags & SEC_READONLY) == 0
10181 && htab->data_index_section != NULL)
10182 osec = htab->data_index_section;
10183 else
10184 osec = htab->text_index_section;
10185 symbol = elf_section_data (osec)->dynindx;
10186 }
6366ff1e
MM		 10187 BFD_ASSERT (symbol != 0);
10188 }
a16385dc
MM		 10189 else
10190 /* On SVR4-ish systems, the dynamic loader cannot
10191 relocate the text and data segments independently,
10192 so the symbol does not matter. */
10193 symbol = 0;
34e77a92
RS		 10194 if (dynreloc_st_type == STT_GNU_IFUNC)
10195 /* We have an STT_GNU_IFUNC symbol that doesn't resolve
10196 to the .iplt entry. Instead, every non-call reference
10197 must use an R_ARM_IRELATIVE relocation to obtain the
10198 correct run-time address. */
10199 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_IRELATIVE);
10200 else
10201 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_RELATIVE);
00a97672
RS		 10202 if (globals->use_rel)
10203 relocate = TRUE;
10204 else
34e77a92 10205 outrel.r_addend += dynreloc_value;
252b5132 10206 }
f21f3fe0 10207
47beaa6a 10208 elf32_arm_add_dynreloc (output_bfd, info, sreloc, &outrel);
9a5aca8c 10209
f21f3fe0 10210 /* If this reloc is against an external symbol, we do not want to
252b5132 10211 fiddle with the addend. Otherwise, we need to include the symbol
9b485d32 10212 value so that it becomes an addend for the dynamic reloc. */
252b5132
RH		 10213 if (! relocate)
10214 return bfd_reloc_ok;
9a5aca8c 10215
f21f3fe0 10216 return _bfd_final_link_relocate (howto, input_bfd, input_section,
34e77a92
RS		 10217 contents, rel->r_offset,
10218 dynreloc_value, (bfd_vma) 0);
252b5132
RH		 10219 }
10220 else switch (r_type)
10221 {
00a97672
RS		 10222 case R_ARM_ABS12:
10223 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
10224
dfc5f959 10225 case R_ARM_XPC25: /* Arm BLX instruction. */
5b5bb741
PB		 10226 case R_ARM_CALL:
10227 case R_ARM_JUMP24:
8029a119 10228 case R_ARM_PC24: /* Arm B/BL instruction. */
7359ea65 10229 case R_ARM_PLT32:
906e58ca 10230 {
906e58ca
NC		 10231 struct elf32_arm_stub_hash_entry *stub_entry = NULL;
10232
dfc5f959 10233 if (r_type == R_ARM_XPC25)
252b5132 10234 {
dfc5f959
NC		 10235 /* Check for Arm calling Arm function. */
10236 /* FIXME: Should we translate the instruction into a BL
10237 instruction instead ? */
35fc36a8 10238 if (branch_type != ST_BRANCH_TO_THUMB)
4eca0228 10239 _bfd_error_handler
d003868e
AM		 10240 (_("\%B: Warning: Arm BLX instruction targets Arm function '%s'."),
10241 input_bfd,
10242 h ? h->root.root.string : "(local)");
dfc5f959 10243 }
155d87d7 10244 else if (r_type == R_ARM_PC24)
dfc5f959
NC		 10245 {
10246 /* Check for Arm calling Thumb function. */
35fc36a8 10247 if (branch_type == ST_BRANCH_TO_THUMB)
dfc5f959 10248 {
f2a9dd69
DJ		 10249 if (elf32_arm_to_thumb_stub (info, sym_name, input_bfd,
10250 output_bfd, input_section,
10251 hit_data, sym_sec, rel->r_offset,
10252 signed_addend, value,
10253 error_message))
10254 return bfd_reloc_ok;
10255 else
10256 return bfd_reloc_dangerous;
dfc5f959 10257 }
252b5132 10258 }
ba96a88f 10259
906e58ca 10260 /* Check if a stub has to be inserted because the
8029a119 10261 destination is too far or we are changing mode. */
155d87d7
CL		 10262 if ( r_type == R_ARM_CALL
10263 || r_type == R_ARM_JUMP24
10264 || r_type == R_ARM_PLT32)
906e58ca 10265 {
fe33d2fa
CL		 10266 enum elf32_arm_stub_type stub_type = arm_stub_none;
10267 struct elf32_arm_link_hash_entry *hash;
10268
10269 hash = (struct elf32_arm_link_hash_entry *) h;
10270 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 10271 st_type, &branch_type,
10272 hash, value, sym_sec,
fe33d2fa 10273 input_bfd, sym_name);
5fa9e92f 10274
fe33d2fa 10275 if (stub_type != arm_stub_none)
906e58ca
NC		 10276 {
10277 /* The target is out of reach, so redirect the
10278 branch to the local stub for this function. */
906e58ca
NC		 10279 stub_entry = elf32_arm_get_stub_entry (input_section,
10280 sym_sec, h,
fe33d2fa
CL		 10281 rel, globals,
10282 stub_type);
9cd3e4e5
NC		 10283 {
10284 if (stub_entry != NULL)
10285 value = (stub_entry->stub_offset
10286 + stub_entry->stub_sec->output_offset
10287 + stub_entry->stub_sec->output_section->vma);
10288
10289 if (plt_offset != (bfd_vma) -1)
10290 *unresolved_reloc_p = FALSE;
10291 }
906e58ca 10292 }
fe33d2fa
CL		 10293 else
10294 {
10295 /* If the call goes through a PLT entry, make sure to
10296 check distance to the right destination address. */
34e77a92 10297 if (plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 10298 {
10299 value = (splt->output_section->vma
10300 + splt->output_offset
34e77a92 10301 + plt_offset);
fe33d2fa
CL		 10302 *unresolved_reloc_p = FALSE;
10303 /* The PLT entry is in ARM mode, regardless of the
10304 target function. */
35fc36a8 10305 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 10306 }
10307 }
906e58ca
NC		 10308 }
10309
dea514f5
PB		 10310 /* The ARM ELF ABI says that this reloc is computed as: S - P + A
10311 where:
10312 S is the address of the symbol in the relocation.
10313 P is address of the instruction being relocated.
10314 A is the addend (extracted from the instruction) in bytes.
10315
10316 S is held in 'value'.
10317 P is the base address of the section containing the
10318 instruction plus the offset of the reloc into that
10319 section, ie:
10320 (input_section->output_section->vma +
10321 input_section->output_offset +
10322 rel->r_offset).
10323 A is the addend, converted into bytes, ie:
10324 (signed_addend * 4)
10325
10326 Note: None of these operations have knowledge of the pipeline
10327 size of the processor, thus it is up to the assembler to
10328 encode this information into the addend. */
10329 value -= (input_section->output_section->vma
10330 + input_section->output_offset);
10331 value -= rel->r_offset;
4e7fd91e
PB		 10332 if (globals->use_rel)
10333 value += (signed_addend << howto->size);
10334 else
10335 /* RELA addends do not have to be adjusted by howto->size. */
10336 value += signed_addend;
23080146 10337
dcb5e6e6
NC		 10338 signed_addend = value;
10339 signed_addend >>= howto->rightshift;
9a5aca8c 10340
5ab79981 10341 /* A branch to an undefined weak symbol is turned into a jump to
ffcb4889 10342 the next instruction unless a PLT entry will be created.
77b4f08f 10343 Do the same for local undefined symbols (but not for STN_UNDEF).
cd1dac3d
DG		 10344 The jump to the next instruction is optimized as a NOP depending
10345 on the architecture. */
ffcb4889 10346 if (h ? (h->root.type == bfd_link_hash_undefweak
34e77a92 10347 && plt_offset == (bfd_vma) -1)
77b4f08f 10348 : r_symndx != STN_UNDEF && bfd_is_und_section (sym_sec))
5ab79981 10349 {
cd1dac3d
DG		 10350 value = (bfd_get_32 (input_bfd, hit_data) & 0xf0000000);
10351
10352 if (arch_has_arm_nop (globals))
10353 value |= 0x0320f000;
10354 else
10355 value |= 0x01a00000; /* Using pre-UAL nop: mov r0, r0. */
5ab79981
PB		 10356 }
10357 else
59f2c4e7 10358 {
9b485d32 10359 /* Perform a signed range check. */
dcb5e6e6 10360 if ( signed_addend > ((bfd_signed_vma) (howto->dst_mask >> 1))
59f2c4e7
NC		 10361 || signed_addend < - ((bfd_signed_vma) ((howto->dst_mask + 1) >> 1)))
10362 return bfd_reloc_overflow;
9a5aca8c 10363
5ab79981 10364 addend = (value & 2);
39b41c9c 10365
5ab79981
PB		 10366 value = (signed_addend & howto->dst_mask)
10367 | (bfd_get_32 (input_bfd, hit_data) & (~ howto->dst_mask));
39b41c9c 10368
5ab79981
PB		 10369 if (r_type == R_ARM_CALL)
10370 {
155d87d7 10371 /* Set the H bit in the BLX instruction. */
35fc36a8 10372 if (branch_type == ST_BRANCH_TO_THUMB)
155d87d7
CL		 10373 {
10374 if (addend)
10375 value |= (1 << 24);
10376 else
10377 value &= ~(bfd_vma)(1 << 24);
10378 }
10379
5ab79981 10380 /* Select the correct instruction (BL or BLX). */
906e58ca 10381 /* Only if we are not handling a BL to a stub. In this
8029a119 10382 case, mode switching is performed by the stub. */
35fc36a8 10383 if (branch_type == ST_BRANCH_TO_THUMB && !stub_entry)
5ab79981 10384 value |= (1 << 28);
63e1a0fc 10385 else if (stub_entry || branch_type != ST_BRANCH_UNKNOWN)
5ab79981
PB		 10386 {
10387 value &= ~(bfd_vma)(1 << 28);
10388 value |= (1 << 24);
10389 }
39b41c9c
PB		 10390 }
10391 }
906e58ca 10392 }
252b5132 10393 break;
f21f3fe0 10394
252b5132
RH		 10395 case R_ARM_ABS32:
10396 value += addend;
35fc36a8 10397 if (branch_type == ST_BRANCH_TO_THUMB)
252b5132
RH		 10398 value |= 1;
10399 break;
f21f3fe0 10400
bb224fc3
MS		 10401 case R_ARM_ABS32_NOI:
10402 value += addend;
10403 break;
10404
252b5132 10405 case R_ARM_REL32:
a8bc6c78 10406 value += addend;
35fc36a8 10407 if (branch_type == ST_BRANCH_TO_THUMB)
a8bc6c78 10408 value |= 1;
252b5132 10409 value -= (input_section->output_section->vma
62efb346 10410 + input_section->output_offset + rel->r_offset);
252b5132 10411 break;
eb043451 10412
bb224fc3
MS		 10413 case R_ARM_REL32_NOI:
10414 value += addend;
10415 value -= (input_section->output_section->vma
10416 + input_section->output_offset + rel->r_offset);
10417 break;
10418
eb043451
PB		 10419 case R_ARM_PREL31:
10420 value -= (input_section->output_section->vma
10421 + input_section->output_offset + rel->r_offset);
10422 value += signed_addend;
10423 if (! h || h->root.type != bfd_link_hash_undefweak)
10424 {
8029a119 10425 /* Check for overflow. */
eb043451
PB		 10426 if ((value ^ (value >> 1)) & (1 << 30))
10427 return bfd_reloc_overflow;
10428 }
10429 value &= 0x7fffffff;
10430 value |= (bfd_get_32 (input_bfd, hit_data) & 0x80000000);
35fc36a8 10431 if (branch_type == ST_BRANCH_TO_THUMB)
eb043451
PB		 10432 value |= 1;
10433 break;
252b5132 10434 }
f21f3fe0 10435
252b5132
RH		 10436 bfd_put_32 (input_bfd, value, hit_data);
10437 return bfd_reloc_ok;
10438
10439 case R_ARM_ABS8:
fd0fd00c
MJ		 10440 /* PR 16202: Refectch the addend using the correct size. */
10441 if (globals->use_rel)
10442 addend = bfd_get_8 (input_bfd, hit_data);
252b5132 10443 value += addend;
4e67d4ca
DG		 10444
10445 /* There is no way to tell whether the user intended to use a signed or
10446 unsigned addend. When checking for overflow we accept either,
10447 as specified by the AAELF. */
10448 if ((long) value > 0xff || (long) value < -0x80)
252b5132
RH		 10449 return bfd_reloc_overflow;
10450
10451 bfd_put_8 (input_bfd, value, hit_data);
10452 return bfd_reloc_ok;
10453
10454 case R_ARM_ABS16:
fd0fd00c
MJ		 10455 /* PR 16202: Refectch the addend using the correct size. */
10456 if (globals->use_rel)
10457 addend = bfd_get_16 (input_bfd, hit_data);
252b5132
RH		 10458 value += addend;
10459
4e67d4ca
DG		 10460 /* See comment for R_ARM_ABS8. */
10461 if ((long) value > 0xffff || (long) value < -0x8000)
252b5132
RH		 10462 return bfd_reloc_overflow;
10463
10464 bfd_put_16 (input_bfd, value, hit_data);
10465 return bfd_reloc_ok;
10466
252b5132 10467 case R_ARM_THM_ABS5:
9b485d32 10468 /* Support ldr and str instructions for the thumb. */
4e7fd91e
PB		 10469 if (globals->use_rel)
10470 {
10471 /* Need to refetch addend. */
10472 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
10473 /* ??? Need to determine shift amount from operand size. */
10474 addend >>= howto->rightshift;
10475 }
252b5132
RH		 10476 value += addend;
10477
10478 /* ??? Isn't value unsigned? */
10479 if ((long) value > 0x1f || (long) value < -0x10)
10480 return bfd_reloc_overflow;
10481
10482 /* ??? Value needs to be properly shifted into place first. */
10483 value |= bfd_get_16 (input_bfd, hit_data) & 0xf83f;
10484 bfd_put_16 (input_bfd, value, hit_data);
10485 return bfd_reloc_ok;
10486
2cab6cc3
MS		 10487 case R_ARM_THM_ALU_PREL_11_0:
10488 /* Corresponds to: addw.w reg, pc, #offset (and similarly for subw). */
10489 {
10490 bfd_vma insn;
10491 bfd_signed_vma relocation;
10492
10493 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 10494 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 10495
99059e56
RM		 10496 if (globals->use_rel)
10497 {
10498 signed_addend = (insn & 0xff) | ((insn & 0x7000) >> 4)
10499 | ((insn & (1 << 26)) >> 15);
10500 if (insn & 0xf00000)
10501 signed_addend = -signed_addend;
10502 }
2cab6cc3
MS		 10503
10504 relocation = value + signed_addend;
79f08007 10505 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10506 + input_section->output_offset
10507 + rel->r_offset);
2cab6cc3 10508
b6518b38 10509 value = relocation;
2cab6cc3 10510
99059e56
RM		 10511 if (value >= 0x1000)
10512 return bfd_reloc_overflow;
2cab6cc3
MS		 10513
10514 insn = (insn & 0xfb0f8f00) | (value & 0xff)
99059e56
RM		 10515 | ((value & 0x700) << 4)
10516 | ((value & 0x800) << 15);
10517 if (relocation < 0)
10518 insn |= 0xa00000;
2cab6cc3
MS		 10519
10520 bfd_put_16 (input_bfd, insn >> 16, hit_data);
10521 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
10522
99059e56 10523 return bfd_reloc_ok;
2cab6cc3
MS		 10524 }
10525
e1ec24c6
NC		 10526 case R_ARM_THM_PC8:
10527 /* PR 10073: This reloc is not generated by the GNU toolchain,
10528 but it is supported for compatibility with third party libraries
10529 generated by other compilers, specifically the ARM/IAR. */
10530 {
10531 bfd_vma insn;
10532 bfd_signed_vma relocation;
10533
10534 insn = bfd_get_16 (input_bfd, hit_data);
10535
99059e56 10536 if (globals->use_rel)
79f08007 10537 addend = ((((insn & 0x00ff) << 2) + 4) & 0x3ff) -4;
e1ec24c6
NC		 10538
10539 relocation = value + addend;
79f08007 10540 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10541 + input_section->output_offset
10542 + rel->r_offset);
e1ec24c6 10543
b6518b38 10544 value = relocation;
e1ec24c6
NC		 10545
10546 /* We do not check for overflow of this reloc. Although strictly
10547 speaking this is incorrect, it appears to be necessary in order
10548 to work with IAR generated relocs. Since GCC and GAS do not
10549 generate R_ARM_THM_PC8 relocs, the lack of a check should not be
10550 a problem for them. */
10551 value &= 0x3fc;
10552
10553 insn = (insn & 0xff00) | (value >> 2);
10554
10555 bfd_put_16 (input_bfd, insn, hit_data);
10556
99059e56 10557 return bfd_reloc_ok;
e1ec24c6
NC		 10558 }
10559
2cab6cc3
MS		 10560 case R_ARM_THM_PC12:
10561 /* Corresponds to: ldr.w reg, [pc, #offset]. */
10562 {
10563 bfd_vma insn;
10564 bfd_signed_vma relocation;
10565
10566 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 10567 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 10568
99059e56
RM		 10569 if (globals->use_rel)
10570 {
10571 signed_addend = insn & 0xfff;
10572 if (!(insn & (1 << 23)))
10573 signed_addend = -signed_addend;
10574 }
2cab6cc3
MS		 10575
10576 relocation = value + signed_addend;
79f08007 10577 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10578 + input_section->output_offset
10579 + rel->r_offset);
2cab6cc3 10580
b6518b38 10581 value = relocation;
2cab6cc3 10582
99059e56
RM		 10583 if (value >= 0x1000)
10584 return bfd_reloc_overflow;
2cab6cc3
MS		 10585
10586 insn = (insn & 0xff7ff000) | value;
99059e56
RM		 10587 if (relocation >= 0)
10588 insn |= (1 << 23);
2cab6cc3
MS		 10589
10590 bfd_put_16 (input_bfd, insn >> 16, hit_data);
10591 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
10592
99059e56 10593 return bfd_reloc_ok;
2cab6cc3
MS		 10594 }
10595
dfc5f959 10596 case R_ARM_THM_XPC22:
c19d1205 10597 case R_ARM_THM_CALL:
bd97cb95 10598 case R_ARM_THM_JUMP24:
dfc5f959 10599 /* Thumb BL (branch long instruction). */
252b5132 10600 {
b34976b6 10601 bfd_vma relocation;
99059e56 10602 bfd_vma reloc_sign;
b34976b6
AM		 10603 bfd_boolean overflow = FALSE;
10604 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
10605 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
e95de063
MS		 10606 bfd_signed_vma reloc_signed_max;
10607 bfd_signed_vma reloc_signed_min;
b34976b6 10608 bfd_vma check;
252b5132 10609 bfd_signed_vma signed_check;
e95de063 10610 int bitsize;
cd1dac3d 10611 const int thumb2 = using_thumb2 (globals);
5e866f5a 10612 const int thumb2_bl = using_thumb2_bl (globals);
252b5132 10613
5ab79981 10614 /* A branch to an undefined weak symbol is turned into a jump to
cd1dac3d
DG		 10615 the next instruction unless a PLT entry will be created.
10616 The jump to the next instruction is optimized as a NOP.W for
10617 Thumb-2 enabled architectures. */
19540007 10618 if (h && h->root.type == bfd_link_hash_undefweak
34e77a92 10619 && plt_offset == (bfd_vma) -1)
5ab79981 10620 {
60a019a0 10621 if (thumb2)
cd1dac3d
DG		 10622 {
10623 bfd_put_16 (input_bfd, 0xf3af, hit_data);
10624 bfd_put_16 (input_bfd, 0x8000, hit_data + 2);
10625 }
10626 else
10627 {
10628 bfd_put_16 (input_bfd, 0xe000, hit_data);
10629 bfd_put_16 (input_bfd, 0xbf00, hit_data + 2);
10630 }
5ab79981
PB		 10631 return bfd_reloc_ok;
10632 }
10633
e95de063 10634 /* Fetch the addend. We use the Thumb-2 encoding (backwards compatible
99059e56 10635 with Thumb-1) involving the J1 and J2 bits. */
4e7fd91e
PB		 10636 if (globals->use_rel)
10637 {
99059e56
RM		 10638 bfd_vma s = (upper_insn & (1 << 10)) >> 10;
10639 bfd_vma upper = upper_insn & 0x3ff;
10640 bfd_vma lower = lower_insn & 0x7ff;
e95de063
MS		 10641 bfd_vma j1 = (lower_insn & (1 << 13)) >> 13;
10642 bfd_vma j2 = (lower_insn & (1 << 11)) >> 11;
99059e56
RM		 10643 bfd_vma i1 = j1 ^ s ? 0 : 1;
10644 bfd_vma i2 = j2 ^ s ? 0 : 1;
e95de063 10645
99059e56
RM		 10646 addend = (i1 << 23) | (i2 << 22) | (upper << 12) | (lower << 1);
10647 /* Sign extend. */
10648 addend = (addend | ((s ? 0 : 1) << 24)) - (1 << 24);
e95de063 10649
4e7fd91e
PB		 10650 signed_addend = addend;
10651 }
cb1afa5c 10652
dfc5f959
NC		 10653 if (r_type == R_ARM_THM_XPC22)
10654 {
10655 /* Check for Thumb to Thumb call. */
10656 /* FIXME: Should we translate the instruction into a BL
10657 instruction instead ? */
35fc36a8 10658 if (branch_type == ST_BRANCH_TO_THUMB)
4eca0228 10659 _bfd_error_handler
d003868e
AM		 10660 (_("%B: Warning: Thumb BLX instruction targets thumb function '%s'."),
10661 input_bfd,
10662 h ? h->root.root.string : "(local)");
dfc5f959
NC		 10663 }
10664 else
252b5132 10665 {
dfc5f959
NC		 10666 /* If it is not a call to Thumb, assume call to Arm.
10667 If it is a call relative to a section name, then it is not a
b7693d02
DJ		 10668 function call at all, but rather a long jump. Calls through
10669 the PLT do not require stubs. */
34e77a92 10670 if (branch_type == ST_BRANCH_TO_ARM && plt_offset == (bfd_vma) -1)
dfc5f959 10671 {
bd97cb95 10672 if (globals->use_blx && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 10673 {
10674 /* Convert BL to BLX. */
10675 lower_insn = (lower_insn & ~0x1000) | 0x0800;
10676 }
155d87d7
CL		 10677 else if (( r_type != R_ARM_THM_CALL)
10678 && (r_type != R_ARM_THM_JUMP24))
8029a119
NC		 10679 {
10680 if (elf32_thumb_to_arm_stub
10681 (info, sym_name, input_bfd, output_bfd, input_section,
10682 hit_data, sym_sec, rel->r_offset, signed_addend, value,
10683 error_message))
10684 return bfd_reloc_ok;
10685 else
10686 return bfd_reloc_dangerous;
10687 }
da5938a2 10688 }
35fc36a8
RS		 10689 else if (branch_type == ST_BRANCH_TO_THUMB
10690 && globals->use_blx
bd97cb95 10691 && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 10692 {
10693 /* Make sure this is a BL. */
10694 lower_insn |= 0x1800;
10695 }
252b5132 10696 }
f21f3fe0 10697
fe33d2fa 10698 enum elf32_arm_stub_type stub_type = arm_stub_none;
155d87d7 10699 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24)
906e58ca
NC		 10700 {
10701 /* Check if a stub has to be inserted because the destination
8029a119 10702 is too far. */
fe33d2fa
CL		 10703 struct elf32_arm_stub_hash_entry *stub_entry;
10704 struct elf32_arm_link_hash_entry *hash;
10705
10706 hash = (struct elf32_arm_link_hash_entry *) h;
10707
10708 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 10709 st_type, &branch_type,
10710 hash, value, sym_sec,
fe33d2fa
CL		 10711 input_bfd, sym_name);
10712
10713 if (stub_type != arm_stub_none)
906e58ca
NC		 10714 {
10715 /* The target is out of reach or we are changing modes, so
10716 redirect the branch to the local stub for this
10717 function. */
10718 stub_entry = elf32_arm_get_stub_entry (input_section,
10719 sym_sec, h,
fe33d2fa
CL		 10720 rel, globals,
10721 stub_type);
906e58ca 10722 if (stub_entry != NULL)
9cd3e4e5
NC		 10723 {
10724 value = (stub_entry->stub_offset
10725 + stub_entry->stub_sec->output_offset
10726 + stub_entry->stub_sec->output_section->vma);
10727
10728 if (plt_offset != (bfd_vma) -1)
10729 *unresolved_reloc_p = FALSE;
10730 }
906e58ca 10731
f4ac8484 10732 /* If this call becomes a call to Arm, force BLX. */
155d87d7 10733 if (globals->use_blx && (r_type == R_ARM_THM_CALL))
f4ac8484
DJ		 10734 {
10735 if ((stub_entry
10736 && !arm_stub_is_thumb (stub_entry->stub_type))
35fc36a8 10737 || branch_type != ST_BRANCH_TO_THUMB)
f4ac8484
DJ		 10738 lower_insn = (lower_insn & ~0x1000) | 0x0800;
10739 }
906e58ca
NC		 10740 }
10741 }
10742
fe33d2fa 10743 /* Handle calls via the PLT. */
34e77a92 10744 if (stub_type == arm_stub_none && plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 10745 {
10746 value = (splt->output_section->vma
10747 + splt->output_offset
34e77a92 10748 + plt_offset);
fe33d2fa 10749
eed94f8f
NC		 10750 if (globals->use_blx
10751 && r_type == R_ARM_THM_CALL
10752 && ! using_thumb_only (globals))
fe33d2fa
CL		 10753 {
10754 /* If the Thumb BLX instruction is available, convert
10755 the BL to a BLX instruction to call the ARM-mode
10756 PLT entry. */
10757 lower_insn = (lower_insn & ~0x1000) | 0x0800;
35fc36a8 10758 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 10759 }
10760 else
10761 {
eed94f8f
NC		 10762 if (! using_thumb_only (globals))
10763 /* Target the Thumb stub before the ARM PLT entry. */
10764 value -= PLT_THUMB_STUB_SIZE;
35fc36a8 10765 branch_type = ST_BRANCH_TO_THUMB;
fe33d2fa
CL		 10766 }
10767 *unresolved_reloc_p = FALSE;
10768 }
10769
ba96a88f 10770 relocation = value + signed_addend;
f21f3fe0 10771
252b5132 10772 relocation -= (input_section->output_section->vma
ba96a88f
NC		 10773 + input_section->output_offset
10774 + rel->r_offset);
9a5aca8c 10775
252b5132
RH		 10776 check = relocation >> howto->rightshift;
10777
10778 /* If this is a signed value, the rightshift just dropped
10779 leading 1 bits (assuming twos complement). */
10780 if ((bfd_signed_vma) relocation >= 0)
10781 signed_check = check;
10782 else
10783 signed_check = check | ~((bfd_vma) -1 >> howto->rightshift);
10784
e95de063
MS		 10785 /* Calculate the permissable maximum and minimum values for
10786 this relocation according to whether we're relocating for
10787 Thumb-2 or not. */
10788 bitsize = howto->bitsize;
5e866f5a 10789 if (!thumb2_bl)
e95de063 10790 bitsize -= 2;
f6ebfac0 10791 reloc_signed_max = (1 << (bitsize - 1)) - 1;
e95de063
MS		 10792 reloc_signed_min = ~reloc_signed_max;
10793
252b5132 10794 /* Assumes two's complement. */
ba96a88f 10795 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
b34976b6 10796 overflow = TRUE;
252b5132 10797
bd97cb95 10798 if ((lower_insn & 0x5000) == 0x4000)
c62e1cc3
NC		 10799 /* For a BLX instruction, make sure that the relocation is rounded up
10800 to a word boundary. This follows the semantics of the instruction
10801 which specifies that bit 1 of the target address will come from bit
10802 1 of the base address. */
10803 relocation = (relocation + 2) & ~ 3;
cb1afa5c 10804
e95de063
MS		 10805 /* Put RELOCATION back into the insn. Assumes two's complement.
10806 We use the Thumb-2 encoding, which is safe even if dealing with
10807 a Thumb-1 instruction by virtue of our overflow check above. */
99059e56 10808 reloc_sign = (signed_check < 0) ? 1 : 0;
e95de063 10809 upper_insn = (upper_insn & ~(bfd_vma) 0x7ff)
99059e56
RM		 10810 | ((relocation >> 12) & 0x3ff)
10811 | (reloc_sign << 10);
906e58ca 10812 lower_insn = (lower_insn & ~(bfd_vma) 0x2fff)
99059e56
RM		 10813 | (((!((relocation >> 23) & 1)) ^ reloc_sign) << 13)
10814 | (((!((relocation >> 22) & 1)) ^ reloc_sign) << 11)
10815 | ((relocation >> 1) & 0x7ff);
c62e1cc3 10816
252b5132
RH		 10817 /* Put the relocated value back in the object file: */
10818 bfd_put_16 (input_bfd, upper_insn, hit_data);
10819 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
10820
10821 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
10822 }
10823 break;
10824
c19d1205
ZW		 10825 case R_ARM_THM_JUMP19:
10826 /* Thumb32 conditional branch instruction. */
10827 {
10828 bfd_vma relocation;
10829 bfd_boolean overflow = FALSE;
10830 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
10831 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
a00a1f35
MS		 10832 bfd_signed_vma reloc_signed_max = 0xffffe;
10833 bfd_signed_vma reloc_signed_min = -0x100000;
c19d1205 10834 bfd_signed_vma signed_check;
c5423981
TG		 10835 enum elf32_arm_stub_type stub_type = arm_stub_none;
10836 struct elf32_arm_stub_hash_entry *stub_entry;
10837 struct elf32_arm_link_hash_entry *hash;
c19d1205
ZW		 10838
10839 /* Need to refetch the addend, reconstruct the top three bits,
10840 and squish the two 11 bit pieces together. */
10841 if (globals->use_rel)
10842 {
10843 bfd_vma S = (upper_insn & 0x0400) >> 10;
a00a1f35 10844 bfd_vma upper = (upper_insn & 0x003f);
c19d1205
ZW		 10845 bfd_vma J1 = (lower_insn & 0x2000) >> 13;
10846 bfd_vma J2 = (lower_insn & 0x0800) >> 11;
10847 bfd_vma lower = (lower_insn & 0x07ff);
10848
a00a1f35
MS		 10849 upper |= J1 << 6;
10850 upper |= J2 << 7;
10851 upper |= (!S) << 8;
c19d1205
ZW		 10852 upper -= 0x0100; /* Sign extend. */
10853
10854 addend = (upper << 12) | (lower << 1);
10855 signed_addend = addend;
10856 }
10857
bd97cb95 10858 /* Handle calls via the PLT. */
34e77a92 10859 if (plt_offset != (bfd_vma) -1)
bd97cb95
DJ		 10860 {
10861 value = (splt->output_section->vma
10862 + splt->output_offset
34e77a92 10863 + plt_offset);
bd97cb95
DJ		 10864 /* Target the Thumb stub before the ARM PLT entry. */
10865 value -= PLT_THUMB_STUB_SIZE;
10866 *unresolved_reloc_p = FALSE;
10867 }
10868
c5423981
TG		 10869 hash = (struct elf32_arm_link_hash_entry *)h;
10870
10871 stub_type = arm_type_of_stub (info, input_section, rel,
10872 st_type, &branch_type,
10873 hash, value, sym_sec,
10874 input_bfd, sym_name);
10875 if (stub_type != arm_stub_none)
10876 {
10877 stub_entry = elf32_arm_get_stub_entry (input_section,
10878 sym_sec, h,
10879 rel, globals,
10880 stub_type);
10881 if (stub_entry != NULL)
10882 {
10883 value = (stub_entry->stub_offset
10884 + stub_entry->stub_sec->output_offset
10885 + stub_entry->stub_sec->output_section->vma);
10886 }
10887 }
c19d1205 10888
99059e56 10889 relocation = value + signed_addend;
c19d1205
ZW		 10890 relocation -= (input_section->output_section->vma
10891 + input_section->output_offset
10892 + rel->r_offset);
a00a1f35 10893 signed_check = (bfd_signed_vma) relocation;
c19d1205 10894
c19d1205
ZW		 10895 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
10896 overflow = TRUE;
10897
10898 /* Put RELOCATION back into the insn. */
10899 {
10900 bfd_vma S = (relocation & 0x00100000) >> 20;
10901 bfd_vma J2 = (relocation & 0x00080000) >> 19;
10902 bfd_vma J1 = (relocation & 0x00040000) >> 18;
10903 bfd_vma hi = (relocation & 0x0003f000) >> 12;
10904 bfd_vma lo = (relocation & 0x00000ffe) >> 1;
10905
a00a1f35 10906 upper_insn = (upper_insn & 0xfbc0) | (S << 10) | hi;
c19d1205
ZW		 10907 lower_insn = (lower_insn & 0xd000) | (J1 << 13) | (J2 << 11) | lo;
10908 }
10909
10910 /* Put the relocated value back in the object file: */
10911 bfd_put_16 (input_bfd, upper_insn, hit_data);
10912 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
10913
10914 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
10915 }
10916
10917 case R_ARM_THM_JUMP11:
10918 case R_ARM_THM_JUMP8:
10919 case R_ARM_THM_JUMP6:
51c5503b
NC		 10920 /* Thumb B (branch) instruction). */
10921 {
6cf9e9fe 10922 bfd_signed_vma relocation;
51c5503b
NC		 10923 bfd_signed_vma reloc_signed_max = (1 << (howto->bitsize - 1)) - 1;
10924 bfd_signed_vma reloc_signed_min = ~ reloc_signed_max;
51c5503b
NC		 10925 bfd_signed_vma signed_check;
10926
c19d1205
ZW		 10927 /* CZB cannot jump backward. */
10928 if (r_type == R_ARM_THM_JUMP6)
10929 reloc_signed_min = 0;
10930
4e7fd91e 10931 if (globals->use_rel)
6cf9e9fe 10932 {
4e7fd91e
PB		 10933 /* Need to refetch addend. */
10934 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
10935 if (addend & ((howto->src_mask + 1) >> 1))
10936 {
10937 signed_addend = -1;
10938 signed_addend &= ~ howto->src_mask;
10939 signed_addend |= addend;
10940 }
10941 else
10942 signed_addend = addend;
10943 /* The value in the insn has been right shifted. We need to
10944 undo this, so that we can perform the address calculation
10945 in terms of bytes. */
10946 signed_addend <<= howto->rightshift;
6cf9e9fe 10947 }
6cf9e9fe 10948 relocation = value + signed_addend;
51c5503b
NC		 10949
10950 relocation -= (input_section->output_section->vma
10951 + input_section->output_offset
10952 + rel->r_offset);
10953
6cf9e9fe
NC		 10954 relocation >>= howto->rightshift;
10955 signed_check = relocation;
c19d1205
ZW		 10956
10957 if (r_type == R_ARM_THM_JUMP6)
10958 relocation = ((relocation & 0x0020) << 4) | ((relocation & 0x001f) << 3);
10959 else
10960 relocation &= howto->dst_mask;
51c5503b 10961 relocation |= (bfd_get_16 (input_bfd, hit_data) & (~ howto->dst_mask));
cedb70c5 10962
51c5503b
NC		 10963 bfd_put_16 (input_bfd, relocation, hit_data);
10964
10965 /* Assumes two's complement. */
10966 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
10967 return bfd_reloc_overflow;
10968
10969 return bfd_reloc_ok;
10970 }
cedb70c5 10971
8375c36b
PB		 10972 case R_ARM_ALU_PCREL7_0:
10973 case R_ARM_ALU_PCREL15_8:
10974 case R_ARM_ALU_PCREL23_15:
10975 {
10976 bfd_vma insn;
10977 bfd_vma relocation;
10978
10979 insn = bfd_get_32 (input_bfd, hit_data);
4e7fd91e
PB		 10980 if (globals->use_rel)
10981 {
10982 /* Extract the addend. */
10983 addend = (insn & 0xff) << ((insn & 0xf00) >> 7);
10984 signed_addend = addend;
10985 }
8375c36b
PB		 10986 relocation = value + signed_addend;
10987
10988 relocation -= (input_section->output_section->vma
10989 + input_section->output_offset
10990 + rel->r_offset);
10991 insn = (insn & ~0xfff)
10992 | ((howto->bitpos << 7) & 0xf00)
10993 | ((relocation >> howto->bitpos) & 0xff);
10994 bfd_put_32 (input_bfd, value, hit_data);
10995 }
10996 return bfd_reloc_ok;
10997
252b5132
RH		 10998 case R_ARM_GNU_VTINHERIT:
10999 case R_ARM_GNU_VTENTRY:
11000 return bfd_reloc_ok;
11001
c19d1205 11002 case R_ARM_GOTOFF32:
252b5132 11003 /* Relocation is relative to the start of the
99059e56 11004 global offset table. */
252b5132
RH		 11005
11006 BFD_ASSERT (sgot != NULL);
11007 if (sgot == NULL)
99059e56 11008 return bfd_reloc_notsupported;
9a5aca8c 11009
cedb70c5 11010 /* If we are addressing a Thumb function, we need to adjust the
ee29b9fb
RE		 11011 address by one, so that attempts to call the function pointer will
11012 correctly interpret it as Thumb code. */
35fc36a8 11013 if (branch_type == ST_BRANCH_TO_THUMB)
ee29b9fb
RE		 11014 value += 1;
11015
252b5132 11016 /* Note that sgot->output_offset is not involved in this
99059e56
RM		 11017 calculation. We always want the start of .got. If we
11018 define _GLOBAL_OFFSET_TABLE in a different way, as is
11019 permitted by the ABI, we might have to change this
11020 calculation. */
252b5132 11021 value -= sgot->output_section->vma;
f21f3fe0 11022 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11023 contents, rel->r_offset, value,
00a97672 11024 rel->r_addend);
252b5132
RH		 11025
11026 case R_ARM_GOTPC:
a7c10850 11027 /* Use global offset table as symbol value. */
252b5132 11028 BFD_ASSERT (sgot != NULL);
f21f3fe0 11029
252b5132 11030 if (sgot == NULL)
99059e56 11031 return bfd_reloc_notsupported;
252b5132 11032
0945cdfd 11033 *unresolved_reloc_p = FALSE;
252b5132 11034 value = sgot->output_section->vma;
f21f3fe0 11035 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11036 contents, rel->r_offset, value,
00a97672 11037 rel->r_addend);
f21f3fe0 11038
252b5132 11039 case R_ARM_GOT32:
eb043451 11040 case R_ARM_GOT_PREL:
252b5132 11041 /* Relocation is to the entry for this symbol in the
99059e56 11042 global offset table. */
252b5132
RH		 11043 if (sgot == NULL)
11044 return bfd_reloc_notsupported;
f21f3fe0 11045
34e77a92
RS		 11046 if (dynreloc_st_type == STT_GNU_IFUNC
11047 && plt_offset != (bfd_vma) -1
11048 && (h == NULL || SYMBOL_REFERENCES_LOCAL (info, h)))
11049 {
11050 /* We have a relocation against a locally-binding STT_GNU_IFUNC
11051 symbol, and the relocation resolves directly to the runtime
11052 target rather than to the .iplt entry. This means that any
11053 .got entry would be the same value as the .igot.plt entry,
11054 so there's no point creating both. */
11055 sgot = globals->root.igotplt;
11056 value = sgot->output_offset + gotplt_offset;
11057 }
11058 else if (h != NULL)
252b5132
RH		 11059 {
11060 bfd_vma off;
f21f3fe0 11061
252b5132
RH		 11062 off = h->got.offset;
11063 BFD_ASSERT (off != (bfd_vma) -1);
b436d854 11064 if ((off & 1) != 0)
252b5132 11065 {
b436d854
RS		 11066 /* We have already processsed one GOT relocation against
11067 this symbol. */
11068 off &= ~1;
11069 if (globals->root.dynamic_sections_created
11070 && !SYMBOL_REFERENCES_LOCAL (info, h))
11071 *unresolved_reloc_p = FALSE;
11072 }
11073 else
11074 {
11075 Elf_Internal_Rela outrel;
11076
6f820c85 11077 if (h->dynindx != -1 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 11078 {
11079 /* If the symbol doesn't resolve locally in a static
11080 object, we have an undefined reference. If the
11081 symbol doesn't resolve locally in a dynamic object,
11082 it should be resolved by the dynamic linker. */
11083 if (globals->root.dynamic_sections_created)
11084 {
11085 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_GLOB_DAT);
11086 *unresolved_reloc_p = FALSE;
11087 }
11088 else
11089 outrel.r_info = 0;
11090 outrel.r_addend = 0;
11091 }
252b5132
RH		 11092 else
11093 {
34e77a92 11094 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 11095 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
5025eb7c
AO		 11096 else if (bfd_link_pic (info)
11097 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
11098 || h->root.type != bfd_link_hash_undefweak))
99059e56
RM		 11099 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
11100 else
11101 outrel.r_info = 0;
34e77a92 11102 outrel.r_addend = dynreloc_value;
b436d854 11103 }
ee29b9fb 11104
b436d854
RS		 11105 /* The GOT entry is initialized to zero by default.
11106 See if we should install a different value. */
11107 if (outrel.r_addend != 0
11108 && (outrel.r_info == 0 || globals->use_rel))
11109 {
11110 bfd_put_32 (output_bfd, outrel.r_addend,
11111 sgot->contents + off);
11112 outrel.r_addend = 0;
252b5132 11113 }
f21f3fe0 11114
b436d854
RS		 11115 if (outrel.r_info != 0)
11116 {
11117 outrel.r_offset = (sgot->output_section->vma
11118 + sgot->output_offset
11119 + off);
11120 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
11121 }
11122 h->got.offset |= 1;
11123 }
252b5132
RH		 11124 value = sgot->output_offset + off;
11125 }
11126 else
11127 {
11128 bfd_vma off;
f21f3fe0 11129
5025eb7c
AO		 11130 BFD_ASSERT (local_got_offsets != NULL
11131 && local_got_offsets[r_symndx] != (bfd_vma) -1);
f21f3fe0 11132
252b5132 11133 off = local_got_offsets[r_symndx];
f21f3fe0 11134
252b5132
RH		 11135 /* The offset must always be a multiple of 4. We use the
11136 least significant bit to record whether we have already
9b485d32 11137 generated the necessary reloc. */
252b5132
RH		 11138 if ((off & 1) != 0)
11139 off &= ~1;
11140 else
11141 {
00a97672 11142 if (globals->use_rel)
34e77a92 11143 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + off);
f21f3fe0 11144
0e1862bb 11145 if (bfd_link_pic (info) || dynreloc_st_type == STT_GNU_IFUNC)
252b5132 11146 {
947216bf 11147 Elf_Internal_Rela outrel;
f21f3fe0 11148
34e77a92 11149 outrel.r_addend = addend + dynreloc_value;
252b5132 11150 outrel.r_offset = (sgot->output_section->vma
f21f3fe0 11151 + sgot->output_offset
252b5132 11152 + off);
34e77a92 11153 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 11154 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
34e77a92
RS		 11155 else
11156 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
47beaa6a 11157 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
252b5132 11158 }
f21f3fe0 11159
252b5132
RH		 11160 local_got_offsets[r_symndx] |= 1;
11161 }
f21f3fe0 11162
252b5132
RH		 11163 value = sgot->output_offset + off;
11164 }
eb043451
PB		 11165 if (r_type != R_ARM_GOT32)
11166 value += sgot->output_section->vma;
9a5aca8c 11167
f21f3fe0 11168 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11169 contents, rel->r_offset, value,
00a97672 11170 rel->r_addend);
f21f3fe0 11171
ba93b8ac
DJ		 11172 case R_ARM_TLS_LDO32:
11173 value = value - dtpoff_base (info);
11174
11175 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 11176 contents, rel->r_offset, value,
11177 rel->r_addend);
ba93b8ac
DJ		 11178
11179 case R_ARM_TLS_LDM32:
11180 {
11181 bfd_vma off;
11182
362d30a1 11183 if (sgot == NULL)
ba93b8ac
DJ		 11184 abort ();
11185
11186 off = globals->tls_ldm_got.offset;
11187
11188 if ((off & 1) != 0)
11189 off &= ~1;
11190 else
11191 {
11192 /* If we don't know the module number, create a relocation
11193 for it. */
0e1862bb 11194 if (bfd_link_pic (info))
ba93b8ac
DJ		 11195 {
11196 Elf_Internal_Rela outrel;
ba93b8ac 11197
362d30a1 11198 if (srelgot == NULL)
ba93b8ac
DJ		 11199 abort ();
11200
00a97672 11201 outrel.r_addend = 0;
362d30a1
RS		 11202 outrel.r_offset = (sgot->output_section->vma
11203 + sgot->output_offset + off);
ba93b8ac
DJ		 11204 outrel.r_info = ELF32_R_INFO (0, R_ARM_TLS_DTPMOD32);
11205
00a97672
RS		 11206 if (globals->use_rel)
11207 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11208 sgot->contents + off);
ba93b8ac 11209
47beaa6a 11210 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11211 }
11212 else
362d30a1 11213 bfd_put_32 (output_bfd, 1, sgot->contents + off);
ba93b8ac
DJ		 11214
11215 globals->tls_ldm_got.offset |= 1;
11216 }
11217
362d30a1 11218 value = sgot->output_section->vma + sgot->output_offset + off
ba93b8ac
DJ		 11219 - (input_section->output_section->vma + input_section->output_offset + rel->r_offset);
11220
11221 return _bfd_final_link_relocate (howto, input_bfd, input_section,
11222 contents, rel->r_offset, value,
00a97672 11223 rel->r_addend);
ba93b8ac
DJ		 11224 }
11225
0855e32b
NS		 11226 case R_ARM_TLS_CALL:
11227 case R_ARM_THM_TLS_CALL:
ba93b8ac
DJ		 11228 case R_ARM_TLS_GD32:
11229 case R_ARM_TLS_IE32:
0855e32b
NS		 11230 case R_ARM_TLS_GOTDESC:
11231 case R_ARM_TLS_DESCSEQ:
11232 case R_ARM_THM_TLS_DESCSEQ:
ba93b8ac 11233 {
0855e32b
NS		 11234 bfd_vma off, offplt;
11235 int indx = 0;
ba93b8ac
DJ		 11236 char tls_type;
11237
0855e32b 11238 BFD_ASSERT (sgot != NULL);
ba93b8ac 11239
ba93b8ac
DJ		 11240 if (h != NULL)
11241 {
11242 bfd_boolean dyn;
11243 dyn = globals->root.dynamic_sections_created;
0e1862bb
L		 11244 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
11245 bfd_link_pic (info),
11246 h)
11247 && (!bfd_link_pic (info)
ba93b8ac
DJ		 11248 || !SYMBOL_REFERENCES_LOCAL (info, h)))
11249 {
11250 *unresolved_reloc_p = FALSE;
11251 indx = h->dynindx;
11252 }
11253 off = h->got.offset;
0855e32b 11254 offplt = elf32_arm_hash_entry (h)->tlsdesc_got;
ba93b8ac
DJ		 11255 tls_type = ((struct elf32_arm_link_hash_entry *) h)->tls_type;
11256 }
11257 else
11258 {
0855e32b 11259 BFD_ASSERT (local_got_offsets != NULL);
ba93b8ac 11260 off = local_got_offsets[r_symndx];
0855e32b 11261 offplt = local_tlsdesc_gotents[r_symndx];
ba93b8ac
DJ		 11262 tls_type = elf32_arm_local_got_tls_type (input_bfd)[r_symndx];
11263 }
11264
0855e32b 11265 /* Linker relaxations happens from one of the
b38cadfb 11266 R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
0855e32b 11267 if (ELF32_R_TYPE(rel->r_info) != r_type)
b38cadfb 11268 tls_type = GOT_TLS_IE;
0855e32b
NS		 11269
11270 BFD_ASSERT (tls_type != GOT_UNKNOWN);
ba93b8ac
DJ		 11271
11272 if ((off & 1) != 0)
11273 off &= ~1;
11274 else
11275 {
11276 bfd_boolean need_relocs = FALSE;
11277 Elf_Internal_Rela outrel;
ba93b8ac
DJ		 11278 int cur_off = off;
11279
11280 /* The GOT entries have not been initialized yet. Do it
11281 now, and emit any relocations. If both an IE GOT and a
11282 GD GOT are necessary, we emit the GD first. */
11283
0e1862bb 11284 if ((bfd_link_pic (info) || indx != 0)
ba93b8ac
DJ		 11285 && (h == NULL
11286 || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
11287 || h->root.type != bfd_link_hash_undefweak))
11288 {
11289 need_relocs = TRUE;
0855e32b 11290 BFD_ASSERT (srelgot != NULL);
ba93b8ac
DJ		 11291 }
11292
0855e32b
NS		 11293 if (tls_type & GOT_TLS_GDESC)
11294 {
47beaa6a
RS		 11295 bfd_byte *loc;
11296
0855e32b
NS		 11297 /* We should have relaxed, unless this is an undefined
11298 weak symbol. */
11299 BFD_ASSERT ((h && (h->root.type == bfd_link_hash_undefweak))
0e1862bb 11300 || bfd_link_pic (info));
0855e32b 11301 BFD_ASSERT (globals->sgotplt_jump_table_size + offplt + 8
99059e56 11302 <= globals->root.sgotplt->size);
0855e32b
NS		 11303
11304 outrel.r_addend = 0;
11305 outrel.r_offset = (globals->root.sgotplt->output_section->vma
11306 + globals->root.sgotplt->output_offset
11307 + offplt
11308 + globals->sgotplt_jump_table_size);
b38cadfb 11309
0855e32b
NS		 11310 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DESC);
11311 sreloc = globals->root.srelplt;
11312 loc = sreloc->contents;
11313 loc += globals->next_tls_desc_index++ * RELOC_SIZE (globals);
11314 BFD_ASSERT (loc + RELOC_SIZE (globals)
99059e56 11315 <= sreloc->contents + sreloc->size);
0855e32b
NS		 11316
11317 SWAP_RELOC_OUT (globals) (output_bfd, &outrel, loc);
11318
11319 /* For globals, the first word in the relocation gets
11320 the relocation index and the top bit set, or zero,
11321 if we're binding now. For locals, it gets the
11322 symbol's offset in the tls section. */
99059e56 11323 bfd_put_32 (output_bfd,
0855e32b
NS		 11324 !h ? value - elf_hash_table (info)->tls_sec->vma
11325 : info->flags & DF_BIND_NOW ? 0
11326 : 0x80000000 | ELF32_R_SYM (outrel.r_info),
b38cadfb
NC		 11327 globals->root.sgotplt->contents + offplt
11328 + globals->sgotplt_jump_table_size);
11329
0855e32b 11330 /* Second word in the relocation is always zero. */
99059e56 11331 bfd_put_32 (output_bfd, 0,
b38cadfb
NC		 11332 globals->root.sgotplt->contents + offplt
11333 + globals->sgotplt_jump_table_size + 4);
0855e32b 11334 }
ba93b8ac
DJ		 11335 if (tls_type & GOT_TLS_GD)
11336 {
11337 if (need_relocs)
11338 {
00a97672 11339 outrel.r_addend = 0;
362d30a1
RS		 11340 outrel.r_offset = (sgot->output_section->vma
11341 + sgot->output_offset
00a97672 11342 + cur_off);
ba93b8ac 11343 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DTPMOD32);
ba93b8ac 11344
00a97672
RS		 11345 if (globals->use_rel)
11346 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11347 sgot->contents + cur_off);
00a97672 11348
47beaa6a 11349 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11350
11351 if (indx == 0)
11352 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11353 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11354 else
11355 {
00a97672 11356 outrel.r_addend = 0;
ba93b8ac
DJ		 11357 outrel.r_info = ELF32_R_INFO (indx,
11358 R_ARM_TLS_DTPOFF32);
11359 outrel.r_offset += 4;
00a97672
RS		 11360
11361 if (globals->use_rel)
11362 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11363 sgot->contents + cur_off + 4);
00a97672 11364
47beaa6a
RS		 11365 elf32_arm_add_dynreloc (output_bfd, info,
11366 srelgot, &outrel);
ba93b8ac
DJ		 11367 }
11368 }
11369 else
11370 {
11371 /* If we are not emitting relocations for a
11372 general dynamic reference, then we must be in a
11373 static link or an executable link with the
11374 symbol binding locally. Mark it as belonging
11375 to module 1, the executable. */
11376 bfd_put_32 (output_bfd, 1,
362d30a1 11377 sgot->contents + cur_off);
ba93b8ac 11378 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11379 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11380 }
11381
11382 cur_off += 8;
11383 }
11384
11385 if (tls_type & GOT_TLS_IE)
11386 {
11387 if (need_relocs)
11388 {
00a97672
RS		 11389 if (indx == 0)
11390 outrel.r_addend = value - dtpoff_base (info);
11391 else
11392 outrel.r_addend = 0;
362d30a1
RS		 11393 outrel.r_offset = (sgot->output_section->vma
11394 + sgot->output_offset
ba93b8ac
DJ		 11395 + cur_off);
11396 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_TPOFF32);
11397
00a97672
RS		 11398 if (globals->use_rel)
11399 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11400 sgot->contents + cur_off);
ba93b8ac 11401
47beaa6a 11402 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11403 }
11404 else
11405 bfd_put_32 (output_bfd, tpoff (info, value),
362d30a1 11406 sgot->contents + cur_off);
ba93b8ac
DJ		 11407 cur_off += 4;
11408 }
11409
11410 if (h != NULL)
11411 h->got.offset |= 1;
11412 else
11413 local_got_offsets[r_symndx] |= 1;
11414 }
11415
11416 if ((tls_type & GOT_TLS_GD) && r_type != R_ARM_TLS_GD32)
11417 off += 8;
0855e32b
NS		 11418 else if (tls_type & GOT_TLS_GDESC)
11419 off = offplt;
11420
11421 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL
11422 || ELF32_R_TYPE(rel->r_info) == R_ARM_THM_TLS_CALL)
11423 {
11424 bfd_signed_vma offset;
12352d3f
PB		 11425 /* TLS stubs are arm mode. The original symbol is a
11426 data object, so branch_type is bogus. */
11427 branch_type = ST_BRANCH_TO_ARM;
0855e32b 11428 enum elf32_arm_stub_type stub_type
34e77a92
RS		 11429 = arm_type_of_stub (info, input_section, rel,
11430 st_type, &branch_type,
0855e32b
NS		 11431 (struct elf32_arm_link_hash_entry *)h,
11432 globals->tls_trampoline, globals->root.splt,
11433 input_bfd, sym_name);
11434
11435 if (stub_type != arm_stub_none)
11436 {
11437 struct elf32_arm_stub_hash_entry *stub_entry
11438 = elf32_arm_get_stub_entry
11439 (input_section, globals->root.splt, 0, rel,
11440 globals, stub_type);
11441 offset = (stub_entry->stub_offset
11442 + stub_entry->stub_sec->output_offset
11443 + stub_entry->stub_sec->output_section->vma);
11444 }
11445 else
11446 offset = (globals->root.splt->output_section->vma
11447 + globals->root.splt->output_offset
11448 + globals->tls_trampoline);
11449
11450 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL)
11451 {
11452 unsigned long inst;
b38cadfb
NC		 11453
11454 offset -= (input_section->output_section->vma
11455 + input_section->output_offset
11456 + rel->r_offset + 8);
0855e32b
NS		 11457
11458 inst = offset >> 2;
11459 inst &= 0x00ffffff;
11460 value = inst | (globals->use_blx ? 0xfa000000 : 0xeb000000);
11461 }
11462 else
11463 {
11464 /* Thumb blx encodes the offset in a complicated
11465 fashion. */
11466 unsigned upper_insn, lower_insn;
11467 unsigned neg;
11468
b38cadfb
NC		 11469 offset -= (input_section->output_section->vma
11470 + input_section->output_offset
0855e32b 11471 + rel->r_offset + 4);
b38cadfb 11472
12352d3f
PB		 11473 if (stub_type != arm_stub_none
11474 && arm_stub_is_thumb (stub_type))
11475 {
11476 lower_insn = 0xd000;
11477 }
11478 else
11479 {
11480 lower_insn = 0xc000;
6a631e86 11481 /* Round up the offset to a word boundary. */
12352d3f
PB		 11482 offset = (offset + 2) & ~2;
11483 }
11484
0855e32b
NS		 11485 neg = offset < 0;
11486 upper_insn = (0xf000
11487 | ((offset >> 12) & 0x3ff)
11488 | (neg << 10));
12352d3f 11489 lower_insn |= (((!((offset >> 23) & 1)) ^ neg) << 13)
0855e32b 11490 | (((!((offset >> 22) & 1)) ^ neg) << 11)
12352d3f 11491 | ((offset >> 1) & 0x7ff);
0855e32b
NS		 11492 bfd_put_16 (input_bfd, upper_insn, hit_data);
11493 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11494 return bfd_reloc_ok;
11495 }
11496 }
11497 /* These relocations needs special care, as besides the fact
11498 they point somewhere in .gotplt, the addend must be
11499 adjusted accordingly depending on the type of instruction
6a631e86 11500 we refer to. */
0855e32b
NS		 11501 else if ((r_type == R_ARM_TLS_GOTDESC) && (tls_type & GOT_TLS_GDESC))
11502 {
11503 unsigned long data, insn;
11504 unsigned thumb;
b38cadfb 11505
0855e32b
NS		 11506 data = bfd_get_32 (input_bfd, hit_data);
11507 thumb = data & 1;
11508 data &= ~1u;
b38cadfb 11509
0855e32b
NS		 11510 if (thumb)
11511 {
11512 insn = bfd_get_16 (input_bfd, contents + rel->r_offset - data);
11513 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
11514 insn = (insn << 16)
11515 | bfd_get_16 (input_bfd,
11516 contents + rel->r_offset - data + 2);
11517 if ((insn & 0xf800c000) == 0xf000c000)
11518 /* bl/blx */
11519 value = -6;
11520 else if ((insn & 0xffffff00) == 0x4400)
11521 /* add */
11522 value = -5;
11523 else
11524 {
4eca0228 11525 _bfd_error_handler
695344c0
NC		 11526 /* xgettext:c-format */
11527 (_("%B(%A+0x%lx): unexpected Thumb instruction '0x%x' referenced by TLS_GOTDESC"),
0855e32b
NS		 11528 input_bfd, input_section,
11529 (unsigned long)rel->r_offset, insn);
11530 return bfd_reloc_notsupported;
11531 }
11532 }
11533 else
11534 {
11535 insn = bfd_get_32 (input_bfd, contents + rel->r_offset - data);
11536
11537 switch (insn >> 24)
11538 {
11539 case 0xeb: /* bl */
11540 case 0xfa: /* blx */
11541 value = -4;
11542 break;
11543
11544 case 0xe0: /* add */
11545 value = -8;
11546 break;
b38cadfb 11547
0855e32b 11548 default:
4eca0228 11549 _bfd_error_handler
695344c0
NC		 11550 /* xgettext:c-format */
11551 (_("%B(%A+0x%lx): unexpected ARM instruction '0x%x' referenced by TLS_GOTDESC"),
0855e32b
NS		 11552 input_bfd, input_section,
11553 (unsigned long)rel->r_offset, insn);
11554 return bfd_reloc_notsupported;
11555 }
11556 }
b38cadfb 11557
0855e32b
NS		 11558 value += ((globals->root.sgotplt->output_section->vma
11559 + globals->root.sgotplt->output_offset + off)
11560 - (input_section->output_section->vma
11561 + input_section->output_offset
11562 + rel->r_offset)
11563 + globals->sgotplt_jump_table_size);
11564 }
11565 else
11566 value = ((globals->root.sgot->output_section->vma
11567 + globals->root.sgot->output_offset + off)
11568 - (input_section->output_section->vma
11569 + input_section->output_offset + rel->r_offset));
ba93b8ac
DJ		 11570
11571 return _bfd_final_link_relocate (howto, input_bfd, input_section,
11572 contents, rel->r_offset, value,
00a97672 11573 rel->r_addend);
ba93b8ac
DJ		 11574 }
11575
11576 case R_ARM_TLS_LE32:
3cbc1e5e 11577 if (bfd_link_dll (info))
ba93b8ac 11578 {
4eca0228 11579 _bfd_error_handler
695344c0 11580 /* xgettext:c-format */
ba93b8ac
DJ		 11581 (_("%B(%A+0x%lx): R_ARM_TLS_LE32 relocation not permitted in shared object"),
11582 input_bfd, input_section,
11583 (long) rel->r_offset, howto->name);
46691134 11584 return bfd_reloc_notsupported;
ba93b8ac
DJ		 11585 }
11586 else
11587 value = tpoff (info, value);
906e58ca 11588
ba93b8ac 11589 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 11590 contents, rel->r_offset, value,
11591 rel->r_addend);
ba93b8ac 11592
319850b4
JB		 11593 case R_ARM_V4BX:
11594 if (globals->fix_v4bx)
845b51d6
PB		 11595 {
11596 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
319850b4 11597
845b51d6
PB		 11598 /* Ensure that we have a BX instruction. */
11599 BFD_ASSERT ((insn & 0x0ffffff0) == 0x012fff10);
319850b4 11600
845b51d6
PB		 11601 if (globals->fix_v4bx == 2 && (insn & 0xf) != 0xf)
11602 {
11603 /* Branch to veneer. */
11604 bfd_vma glue_addr;
11605 glue_addr = elf32_arm_bx_glue (info, insn & 0xf);
11606 glue_addr -= input_section->output_section->vma
11607 + input_section->output_offset
11608 + rel->r_offset + 8;
11609 insn = (insn & 0xf0000000) | 0x0a000000
11610 | ((glue_addr >> 2) & 0x00ffffff);
11611 }
11612 else
11613 {
11614 /* Preserve Rm (lowest four bits) and the condition code
11615 (highest four bits). Other bits encode MOV PC,Rm. */
11616 insn = (insn & 0xf000000f) | 0x01a0f000;
11617 }
319850b4 11618
845b51d6
PB		 11619 bfd_put_32 (input_bfd, insn, hit_data);
11620 }
319850b4
JB		 11621 return bfd_reloc_ok;
11622
b6895b4f
PB		 11623 case R_ARM_MOVW_ABS_NC:
11624 case R_ARM_MOVT_ABS:
11625 case R_ARM_MOVW_PREL_NC:
11626 case R_ARM_MOVT_PREL:
92f5d02b
MS		 11627 /* Until we properly support segment-base-relative addressing then
11628 we assume the segment base to be zero, as for the group relocations.
11629 Thus R_ARM_MOVW_BREL_NC has the same semantics as R_ARM_MOVW_ABS_NC
11630 and R_ARM_MOVT_BREL has the same semantics as R_ARM_MOVT_ABS. */
11631 case R_ARM_MOVW_BREL_NC:
11632 case R_ARM_MOVW_BREL:
11633 case R_ARM_MOVT_BREL:
b6895b4f
PB		 11634 {
11635 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
11636
11637 if (globals->use_rel)
11638 {
11639 addend = ((insn >> 4) & 0xf000) | (insn & 0xfff);
39623e12 11640 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 11641 }
92f5d02b 11642
b6895b4f 11643 value += signed_addend;
b6895b4f
PB		 11644
11645 if (r_type == R_ARM_MOVW_PREL_NC || r_type == R_ARM_MOVT_PREL)
11646 value -= (input_section->output_section->vma
11647 + input_section->output_offset + rel->r_offset);
11648
92f5d02b 11649 if (r_type == R_ARM_MOVW_BREL && value >= 0x10000)
99059e56 11650 return bfd_reloc_overflow;
92f5d02b 11651
35fc36a8 11652 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 11653 value |= 1;
11654
11655 if (r_type == R_ARM_MOVT_ABS || r_type == R_ARM_MOVT_PREL
99059e56 11656 || r_type == R_ARM_MOVT_BREL)
b6895b4f
PB		 11657 value >>= 16;
11658
11659 insn &= 0xfff0f000;
11660 insn |= value & 0xfff;
11661 insn |= (value & 0xf000) << 4;
11662 bfd_put_32 (input_bfd, insn, hit_data);
11663 }
11664 return bfd_reloc_ok;
11665
11666 case R_ARM_THM_MOVW_ABS_NC:
11667 case R_ARM_THM_MOVT_ABS:
11668 case R_ARM_THM_MOVW_PREL_NC:
11669 case R_ARM_THM_MOVT_PREL:
92f5d02b
MS		 11670 /* Until we properly support segment-base-relative addressing then
11671 we assume the segment base to be zero, as for the above relocations.
11672 Thus R_ARM_THM_MOVW_BREL_NC has the same semantics as
11673 R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_BREL has the same semantics
11674 as R_ARM_THM_MOVT_ABS. */
11675 case R_ARM_THM_MOVW_BREL_NC:
11676 case R_ARM_THM_MOVW_BREL:
11677 case R_ARM_THM_MOVT_BREL:
b6895b4f
PB		 11678 {
11679 bfd_vma insn;
906e58ca 11680
b6895b4f
PB		 11681 insn = bfd_get_16 (input_bfd, hit_data) << 16;
11682 insn |= bfd_get_16 (input_bfd, hit_data + 2);
11683
11684 if (globals->use_rel)
11685 {
11686 addend = ((insn >> 4) & 0xf000)
11687 | ((insn >> 15) & 0x0800)
11688 | ((insn >> 4) & 0x0700)
11689 | (insn & 0x00ff);
39623e12 11690 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 11691 }
92f5d02b 11692
b6895b4f 11693 value += signed_addend;
b6895b4f
PB		 11694
11695 if (r_type == R_ARM_THM_MOVW_PREL_NC || r_type == R_ARM_THM_MOVT_PREL)
11696 value -= (input_section->output_section->vma
11697 + input_section->output_offset + rel->r_offset);
11698
92f5d02b 11699 if (r_type == R_ARM_THM_MOVW_BREL && value >= 0x10000)
99059e56 11700 return bfd_reloc_overflow;
92f5d02b 11701
35fc36a8 11702 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 11703 value |= 1;
11704
11705 if (r_type == R_ARM_THM_MOVT_ABS || r_type == R_ARM_THM_MOVT_PREL
99059e56 11706 || r_type == R_ARM_THM_MOVT_BREL)
b6895b4f
PB		 11707 value >>= 16;
11708
11709 insn &= 0xfbf08f00;
11710 insn |= (value & 0xf000) << 4;
11711 insn |= (value & 0x0800) << 15;
11712 insn |= (value & 0x0700) << 4;
11713 insn |= (value & 0x00ff);
11714
11715 bfd_put_16 (input_bfd, insn >> 16, hit_data);
11716 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
11717 }
11718 return bfd_reloc_ok;
11719
4962c51a
MS		 11720 case R_ARM_ALU_PC_G0_NC:
11721 case R_ARM_ALU_PC_G1_NC:
11722 case R_ARM_ALU_PC_G0:
11723 case R_ARM_ALU_PC_G1:
11724 case R_ARM_ALU_PC_G2:
11725 case R_ARM_ALU_SB_G0_NC:
11726 case R_ARM_ALU_SB_G1_NC:
11727 case R_ARM_ALU_SB_G0:
11728 case R_ARM_ALU_SB_G1:
11729 case R_ARM_ALU_SB_G2:
11730 {
11731 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 11732 bfd_vma pc = input_section->output_section->vma
4962c51a 11733 + input_section->output_offset + rel->r_offset;
31a91d61 11734 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 11735 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56
RM		 11736 bfd_vma residual;
11737 bfd_vma g_n;
4962c51a 11738 bfd_signed_vma signed_value;
99059e56
RM		 11739 int group = 0;
11740
11741 /* Determine which group of bits to select. */
11742 switch (r_type)
11743 {
11744 case R_ARM_ALU_PC_G0_NC:
11745 case R_ARM_ALU_PC_G0:
11746 case R_ARM_ALU_SB_G0_NC:
11747 case R_ARM_ALU_SB_G0:
11748 group = 0;
11749 break;
11750
11751 case R_ARM_ALU_PC_G1_NC:
11752 case R_ARM_ALU_PC_G1:
11753 case R_ARM_ALU_SB_G1_NC:
11754 case R_ARM_ALU_SB_G1:
11755 group = 1;
11756 break;
11757
11758 case R_ARM_ALU_PC_G2:
11759 case R_ARM_ALU_SB_G2:
11760 group = 2;
11761 break;
11762
11763 default:
11764 abort ();
11765 }
11766
11767 /* If REL, extract the addend from the insn. If RELA, it will
11768 have already been fetched for us. */
4962c51a 11769 if (globals->use_rel)
99059e56
RM		 11770 {
11771 int negative;
11772 bfd_vma constant = insn & 0xff;
11773 bfd_vma rotation = (insn & 0xf00) >> 8;
11774
11775 if (rotation == 0)
11776 signed_addend = constant;
11777 else
11778 {
11779 /* Compensate for the fact that in the instruction, the
11780 rotation is stored in multiples of 2 bits. */
11781 rotation *= 2;
11782
11783 /* Rotate "constant" right by "rotation" bits. */
11784 signed_addend = (constant >> rotation) |
11785 (constant << (8 * sizeof (bfd_vma) - rotation));
11786 }
11787
11788 /* Determine if the instruction is an ADD or a SUB.
11789 (For REL, this determines the sign of the addend.) */
11790 negative = identify_add_or_sub (insn);
11791 if (negative == 0)
11792 {
4eca0228 11793 _bfd_error_handler
695344c0 11794 /* xgettext:c-format */
99059e56
RM		 11795 (_("%B(%A+0x%lx): Only ADD or SUB instructions are allowed for ALU group relocations"),
11796 input_bfd, input_section,
11797 (long) rel->r_offset, howto->name);
11798 return bfd_reloc_overflow;
11799 }
11800
11801 signed_addend *= negative;
11802 }
4962c51a
MS		 11803
11804 /* Compute the value (X) to go in the place. */
99059e56
RM		 11805 if (r_type == R_ARM_ALU_PC_G0_NC
11806 || r_type == R_ARM_ALU_PC_G1_NC
11807 || r_type == R_ARM_ALU_PC_G0
11808 || r_type == R_ARM_ALU_PC_G1
11809 || r_type == R_ARM_ALU_PC_G2)
11810 /* PC relative. */
11811 signed_value = value - pc + signed_addend;
11812 else
11813 /* Section base relative. */
11814 signed_value = value - sb + signed_addend;
11815
11816 /* If the target symbol is a Thumb function, then set the
11817 Thumb bit in the address. */
35fc36a8 11818 if (branch_type == ST_BRANCH_TO_THUMB)
4962c51a
MS		 11819 signed_value |= 1;
11820
99059e56
RM		 11821 /* Calculate the value of the relevant G_n, in encoded
11822 constant-with-rotation format. */
b6518b38
NC		 11823 g_n = calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
11824 group, &residual);
99059e56
RM		 11825
11826 /* Check for overflow if required. */
11827 if ((r_type == R_ARM_ALU_PC_G0
11828 || r_type == R_ARM_ALU_PC_G1
11829 || r_type == R_ARM_ALU_PC_G2
11830 || r_type == R_ARM_ALU_SB_G0
11831 || r_type == R_ARM_ALU_SB_G1
11832 || r_type == R_ARM_ALU_SB_G2) && residual != 0)
11833 {
4eca0228 11834 _bfd_error_handler
695344c0 11835 /* xgettext:c-format */
99059e56
RM		 11836 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
11837 input_bfd, input_section,
b6518b38
NC		 11838 (long) rel->r_offset, signed_value < 0 ? - signed_value : signed_value,
11839 howto->name);
99059e56
RM		 11840 return bfd_reloc_overflow;
11841 }
11842
11843 /* Mask out the value and the ADD/SUB part of the opcode; take care
11844 not to destroy the S bit. */
11845 insn &= 0xff1ff000;
11846
11847 /* Set the opcode according to whether the value to go in the
11848 place is negative. */
11849 if (signed_value < 0)
11850 insn |= 1 << 22;
11851 else
11852 insn |= 1 << 23;
11853
11854 /* Encode the offset. */
11855 insn |= g_n;
4962c51a
MS		 11856
11857 bfd_put_32 (input_bfd, insn, hit_data);
11858 }
11859 return bfd_reloc_ok;
11860
11861 case R_ARM_LDR_PC_G0:
11862 case R_ARM_LDR_PC_G1:
11863 case R_ARM_LDR_PC_G2:
11864 case R_ARM_LDR_SB_G0:
11865 case R_ARM_LDR_SB_G1:
11866 case R_ARM_LDR_SB_G2:
11867 {
11868 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 11869 bfd_vma pc = input_section->output_section->vma
4962c51a 11870 + input_section->output_offset + rel->r_offset;
31a91d61 11871 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 11872 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 11873 bfd_vma residual;
4962c51a 11874 bfd_signed_vma signed_value;
99059e56
RM		 11875 int group = 0;
11876
11877 /* Determine which groups of bits to calculate. */
11878 switch (r_type)
11879 {
11880 case R_ARM_LDR_PC_G0:
11881 case R_ARM_LDR_SB_G0:
11882 group = 0;
11883 break;
11884
11885 case R_ARM_LDR_PC_G1:
11886 case R_ARM_LDR_SB_G1:
11887 group = 1;
11888 break;
11889
11890 case R_ARM_LDR_PC_G2:
11891 case R_ARM_LDR_SB_G2:
11892 group = 2;
11893 break;
11894
11895 default:
11896 abort ();
11897 }
11898
11899 /* If REL, extract the addend from the insn. If RELA, it will
11900 have already been fetched for us. */
4962c51a 11901 if (globals->use_rel)
99059e56
RM		 11902 {
11903 int negative = (insn & (1 << 23)) ? 1 : -1;
11904 signed_addend = negative * (insn & 0xfff);
11905 }
4962c51a
MS		 11906
11907 /* Compute the value (X) to go in the place. */
99059e56
RM		 11908 if (r_type == R_ARM_LDR_PC_G0
11909 || r_type == R_ARM_LDR_PC_G1
11910 || r_type == R_ARM_LDR_PC_G2)
11911 /* PC relative. */
11912 signed_value = value - pc + signed_addend;
11913 else
11914 /* Section base relative. */
11915 signed_value = value - sb + signed_addend;
11916
11917 /* Calculate the value of the relevant G_{n-1} to obtain
11918 the residual at that stage. */
b6518b38
NC		 11919 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
11920 group - 1, &residual);
99059e56
RM		 11921
11922 /* Check for overflow. */
11923 if (residual >= 0x1000)
11924 {
4eca0228 11925 _bfd_error_handler
695344c0 11926 /* xgettext:c-format */
99059e56 11927 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
b6518b38
NC		 11928 input_bfd, input_section,
11929 (long) rel->r_offset, labs (signed_value), howto->name);
99059e56
RM		 11930 return bfd_reloc_overflow;
11931 }
11932
11933 /* Mask out the value and U bit. */
11934 insn &= 0xff7ff000;
11935
11936 /* Set the U bit if the value to go in the place is non-negative. */
11937 if (signed_value >= 0)
11938 insn |= 1 << 23;
11939
11940 /* Encode the offset. */
11941 insn |= residual;
4962c51a
MS		 11942
11943 bfd_put_32 (input_bfd, insn, hit_data);
11944 }
11945 return bfd_reloc_ok;
11946
11947 case R_ARM_LDRS_PC_G0:
11948 case R_ARM_LDRS_PC_G1:
11949 case R_ARM_LDRS_PC_G2:
11950 case R_ARM_LDRS_SB_G0:
11951 case R_ARM_LDRS_SB_G1:
11952 case R_ARM_LDRS_SB_G2:
11953 {
11954 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 11955 bfd_vma pc = input_section->output_section->vma
4962c51a 11956 + input_section->output_offset + rel->r_offset;
31a91d61 11957 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 11958 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 11959 bfd_vma residual;
4962c51a 11960 bfd_signed_vma signed_value;
99059e56
RM		 11961 int group = 0;
11962
11963 /* Determine which groups of bits to calculate. */
11964 switch (r_type)
11965 {
11966 case R_ARM_LDRS_PC_G0:
11967 case R_ARM_LDRS_SB_G0:
11968 group = 0;
11969 break;
11970
11971 case R_ARM_LDRS_PC_G1:
11972 case R_ARM_LDRS_SB_G1:
11973 group = 1;
11974 break;
11975
11976 case R_ARM_LDRS_PC_G2:
11977 case R_ARM_LDRS_SB_G2:
11978 group = 2;
11979 break;
11980
11981 default:
11982 abort ();
11983 }
11984
11985 /* If REL, extract the addend from the insn. If RELA, it will
11986 have already been fetched for us. */
4962c51a 11987 if (globals->use_rel)
99059e56
RM		 11988 {
11989 int negative = (insn & (1 << 23)) ? 1 : -1;
11990 signed_addend = negative * (((insn & 0xf00) >> 4) + (insn & 0xf));
11991 }
4962c51a
MS		 11992
11993 /* Compute the value (X) to go in the place. */
99059e56
RM		 11994 if (r_type == R_ARM_LDRS_PC_G0
11995 || r_type == R_ARM_LDRS_PC_G1
11996 || r_type == R_ARM_LDRS_PC_G2)
11997 /* PC relative. */
11998 signed_value = value - pc + signed_addend;
11999 else
12000 /* Section base relative. */
12001 signed_value = value - sb + signed_addend;
12002
12003 /* Calculate the value of the relevant G_{n-1} to obtain
12004 the residual at that stage. */
b6518b38
NC		 12005 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12006 group - 1, &residual);
99059e56
RM		 12007
12008 /* Check for overflow. */
12009 if (residual >= 0x100)
12010 {
4eca0228 12011 _bfd_error_handler
695344c0 12012 /* xgettext:c-format */
99059e56 12013 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
b6518b38
NC		 12014 input_bfd, input_section,
12015 (long) rel->r_offset, labs (signed_value), howto->name);
99059e56
RM		 12016 return bfd_reloc_overflow;
12017 }
12018
12019 /* Mask out the value and U bit. */
12020 insn &= 0xff7ff0f0;
12021
12022 /* Set the U bit if the value to go in the place is non-negative. */
12023 if (signed_value >= 0)
12024 insn |= 1 << 23;
12025
12026 /* Encode the offset. */
12027 insn |= ((residual & 0xf0) << 4) | (residual & 0xf);
4962c51a
MS		 12028
12029 bfd_put_32 (input_bfd, insn, hit_data);
12030 }
12031 return bfd_reloc_ok;
12032
12033 case R_ARM_LDC_PC_G0:
12034 case R_ARM_LDC_PC_G1:
12035 case R_ARM_LDC_PC_G2:
12036 case R_ARM_LDC_SB_G0:
12037 case R_ARM_LDC_SB_G1:
12038 case R_ARM_LDC_SB_G2:
12039 {
12040 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12041 bfd_vma pc = input_section->output_section->vma
4962c51a 12042 + input_section->output_offset + rel->r_offset;
31a91d61 12043 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12044 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12045 bfd_vma residual;
4962c51a 12046 bfd_signed_vma signed_value;
99059e56
RM		 12047 int group = 0;
12048
12049 /* Determine which groups of bits to calculate. */
12050 switch (r_type)
12051 {
12052 case R_ARM_LDC_PC_G0:
12053 case R_ARM_LDC_SB_G0:
12054 group = 0;
12055 break;
12056
12057 case R_ARM_LDC_PC_G1:
12058 case R_ARM_LDC_SB_G1:
12059 group = 1;
12060 break;
12061
12062 case R_ARM_LDC_PC_G2:
12063 case R_ARM_LDC_SB_G2:
12064 group = 2;
12065 break;
12066
12067 default:
12068 abort ();
12069 }
12070
12071 /* If REL, extract the addend from the insn. If RELA, it will
12072 have already been fetched for us. */
4962c51a 12073 if (globals->use_rel)
99059e56
RM		 12074 {
12075 int negative = (insn & (1 << 23)) ? 1 : -1;
12076 signed_addend = negative * ((insn & 0xff) << 2);
12077 }
4962c51a
MS		 12078
12079 /* Compute the value (X) to go in the place. */
99059e56
RM		 12080 if (r_type == R_ARM_LDC_PC_G0
12081 || r_type == R_ARM_LDC_PC_G1
12082 || r_type == R_ARM_LDC_PC_G2)
12083 /* PC relative. */
12084 signed_value = value - pc + signed_addend;
12085 else
12086 /* Section base relative. */
12087 signed_value = value - sb + signed_addend;
12088
12089 /* Calculate the value of the relevant G_{n-1} to obtain
12090 the residual at that stage. */
b6518b38
NC		 12091 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12092 group - 1, &residual);
99059e56
RM		 12093
12094 /* Check for overflow. (The absolute value to go in the place must be
12095 divisible by four and, after having been divided by four, must
12096 fit in eight bits.) */
12097 if ((residual & 0x3) != 0 || residual >= 0x400)
12098 {
4eca0228 12099 _bfd_error_handler
695344c0 12100 /* xgettext:c-format */
99059e56
RM		 12101 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
12102 input_bfd, input_section,
b6518b38 12103 (long) rel->r_offset, labs (signed_value), howto->name);
99059e56
RM		 12104 return bfd_reloc_overflow;
12105 }
12106
12107 /* Mask out the value and U bit. */
12108 insn &= 0xff7fff00;
12109
12110 /* Set the U bit if the value to go in the place is non-negative. */
12111 if (signed_value >= 0)
12112 insn |= 1 << 23;
12113
12114 /* Encode the offset. */
12115 insn |= residual >> 2;
4962c51a
MS		 12116
12117 bfd_put_32 (input_bfd, insn, hit_data);
12118 }
12119 return bfd_reloc_ok;
12120
72d98d16
MG		 12121 case R_ARM_THM_ALU_ABS_G0_NC:
12122 case R_ARM_THM_ALU_ABS_G1_NC:
12123 case R_ARM_THM_ALU_ABS_G2_NC:
12124 case R_ARM_THM_ALU_ABS_G3_NC:
12125 {
12126 const int shift_array[4] = {0, 8, 16, 24};
12127 bfd_vma insn = bfd_get_16 (input_bfd, hit_data);
12128 bfd_vma addr = value;
12129 int shift = shift_array[r_type - R_ARM_THM_ALU_ABS_G0_NC];
12130
12131 /* Compute address. */
12132 if (globals->use_rel)
12133 signed_addend = insn & 0xff;
12134 addr += signed_addend;
12135 if (branch_type == ST_BRANCH_TO_THUMB)
12136 addr |= 1;
12137 /* Clean imm8 insn. */
12138 insn &= 0xff00;
12139 /* And update with correct part of address. */
12140 insn |= (addr >> shift) & 0xff;
12141 /* Update insn. */
12142 bfd_put_16 (input_bfd, insn, hit_data);
12143 }
12144
12145 *unresolved_reloc_p = FALSE;
12146 return bfd_reloc_ok;
12147
252b5132
RH		 12148 default:
12149 return bfd_reloc_notsupported;
12150 }
12151}
12152
98c1d4aa
NC		 12153/* Add INCREMENT to the reloc (of type HOWTO) at ADDRESS. */
12154static void
57e8b36a
NC		 12155arm_add_to_rel (bfd * abfd,
12156 bfd_byte * address,
12157 reloc_howto_type * howto,
12158 bfd_signed_vma increment)
98c1d4aa 12159{
98c1d4aa
NC		 12160 bfd_signed_vma addend;
12161
bd97cb95
DJ		 12162 if (howto->type == R_ARM_THM_CALL
12163 || howto->type == R_ARM_THM_JUMP24)
98c1d4aa 12164 {
9a5aca8c
AM		 12165 int upper_insn, lower_insn;
12166 int upper, lower;
98c1d4aa 12167
9a5aca8c
AM		 12168 upper_insn = bfd_get_16 (abfd, address);
12169 lower_insn = bfd_get_16 (abfd, address + 2);
12170 upper = upper_insn & 0x7ff;
12171 lower = lower_insn & 0x7ff;
12172
12173 addend = (upper << 12) | (lower << 1);
ddda4409 12174 addend += increment;
9a5aca8c 12175 addend >>= 1;
98c1d4aa 12176
9a5aca8c
AM		 12177 upper_insn = (upper_insn & 0xf800) | ((addend >> 11) & 0x7ff);
12178 lower_insn = (lower_insn & 0xf800) | (addend & 0x7ff);
12179
dc810e39
AM		 12180 bfd_put_16 (abfd, (bfd_vma) upper_insn, address);
12181 bfd_put_16 (abfd, (bfd_vma) lower_insn, address + 2);
9a5aca8c
AM		 12182 }
12183 else
12184 {
12185 bfd_vma contents;
12186
12187 contents = bfd_get_32 (abfd, address);
12188
12189 /* Get the (signed) value from the instruction. */
12190 addend = contents & howto->src_mask;
12191 if (addend & ((howto->src_mask + 1) >> 1))
12192 {
12193 bfd_signed_vma mask;
12194
12195 mask = -1;
12196 mask &= ~ howto->src_mask;
12197 addend |= mask;
12198 }
12199
12200 /* Add in the increment, (which is a byte value). */
12201 switch (howto->type)
12202 {
12203 default:
12204 addend += increment;
12205 break;
12206
12207 case R_ARM_PC24:
c6596c5e 12208 case R_ARM_PLT32:
5b5bb741
PB		 12209 case R_ARM_CALL:
12210 case R_ARM_JUMP24:
9a5aca8c 12211 addend <<= howto->size;
dc810e39 12212 addend += increment;
9a5aca8c
AM		 12213
12214 /* Should we check for overflow here ? */
12215
12216 /* Drop any undesired bits. */
12217 addend >>= howto->rightshift;
12218 break;
12219 }
12220
12221 contents = (contents & ~ howto->dst_mask) | (addend & howto->dst_mask);
12222
12223 bfd_put_32 (abfd, contents, address);
ddda4409 12224 }
98c1d4aa 12225}
252b5132 12226
ba93b8ac
DJ		 12227#define IS_ARM_TLS_RELOC(R_TYPE) \
12228 ((R_TYPE) == R_ARM_TLS_GD32 \
12229 || (R_TYPE) == R_ARM_TLS_LDO32 \
12230 || (R_TYPE) == R_ARM_TLS_LDM32 \
12231 || (R_TYPE) == R_ARM_TLS_DTPOFF32 \
12232 || (R_TYPE) == R_ARM_TLS_DTPMOD32 \
12233 || (R_TYPE) == R_ARM_TLS_TPOFF32 \
12234 || (R_TYPE) == R_ARM_TLS_LE32 \
0855e32b
NS		 12235 || (R_TYPE) == R_ARM_TLS_IE32 \
12236 || IS_ARM_TLS_GNU_RELOC (R_TYPE))
12237
12238/* Specific set of relocations for the gnu tls dialect. */
12239#define IS_ARM_TLS_GNU_RELOC(R_TYPE) \
12240 ((R_TYPE) == R_ARM_TLS_GOTDESC \
12241 || (R_TYPE) == R_ARM_TLS_CALL \
12242 || (R_TYPE) == R_ARM_THM_TLS_CALL \
12243 || (R_TYPE) == R_ARM_TLS_DESCSEQ \
12244 || (R_TYPE) == R_ARM_THM_TLS_DESCSEQ)
ba93b8ac 12245
252b5132 12246/* Relocate an ARM ELF section. */
906e58ca 12247
b34976b6 12248static bfd_boolean
57e8b36a
NC		 12249elf32_arm_relocate_section (bfd * output_bfd,
12250 struct bfd_link_info * info,
12251 bfd * input_bfd,
12252 asection * input_section,
12253 bfd_byte * contents,
12254 Elf_Internal_Rela * relocs,
12255 Elf_Internal_Sym * local_syms,
12256 asection ** local_sections)
252b5132 12257{
b34976b6
AM		 12258 Elf_Internal_Shdr *symtab_hdr;
12259 struct elf_link_hash_entry **sym_hashes;
12260 Elf_Internal_Rela *rel;
12261 Elf_Internal_Rela *relend;
12262 const char *name;
b32d3aa2 12263 struct elf32_arm_link_hash_table * globals;
252b5132 12264
4e7fd91e 12265 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 12266 if (globals == NULL)
12267 return FALSE;
b491616a 12268
0ffa91dd 12269 symtab_hdr = & elf_symtab_hdr (input_bfd);
252b5132
RH		 12270 sym_hashes = elf_sym_hashes (input_bfd);
12271
12272 rel = relocs;
12273 relend = relocs + input_section->reloc_count;
12274 for (; rel < relend; rel++)
12275 {
ba96a88f
NC		 12276 int r_type;
12277 reloc_howto_type * howto;
12278 unsigned long r_symndx;
12279 Elf_Internal_Sym * sym;
12280 asection * sec;
252b5132 12281 struct elf_link_hash_entry * h;
ba96a88f
NC		 12282 bfd_vma relocation;
12283 bfd_reloc_status_type r;
12284 arelent bfd_reloc;
ba93b8ac 12285 char sym_type;
0945cdfd 12286 bfd_boolean unresolved_reloc = FALSE;
f2a9dd69 12287 char *error_message = NULL;
f21f3fe0 12288
252b5132 12289 r_symndx = ELF32_R_SYM (rel->r_info);
ba96a88f 12290 r_type = ELF32_R_TYPE (rel->r_info);
b32d3aa2 12291 r_type = arm_real_reloc_type (globals, r_type);
252b5132 12292
ba96a88f 12293 if ( r_type == R_ARM_GNU_VTENTRY
99059e56
RM		 12294 || r_type == R_ARM_GNU_VTINHERIT)
12295 continue;
252b5132 12296
b32d3aa2 12297 bfd_reloc.howto = elf32_arm_howto_from_type (r_type);
ba96a88f 12298 howto = bfd_reloc.howto;
252b5132 12299
252b5132
RH		 12300 h = NULL;
12301 sym = NULL;
12302 sec = NULL;
9b485d32 12303
252b5132
RH		 12304 if (r_symndx < symtab_hdr->sh_info)
12305 {
12306 sym = local_syms + r_symndx;
ba93b8ac 12307 sym_type = ELF32_ST_TYPE (sym->st_info);
252b5132 12308 sec = local_sections[r_symndx];
ffcb4889
NS		 12309
12310 /* An object file might have a reference to a local
12311 undefined symbol. This is a daft object file, but we
12312 should at least do something about it. V4BX & NONE
12313 relocations do not use the symbol and are explicitly
77b4f08f
TS		 12314 allowed to use the undefined symbol, so allow those.
12315 Likewise for relocations against STN_UNDEF. */
ffcb4889
NS		 12316 if (r_type != R_ARM_V4BX
12317 && r_type != R_ARM_NONE
77b4f08f 12318 && r_symndx != STN_UNDEF
ffcb4889
NS		 12319 && bfd_is_und_section (sec)
12320 && ELF_ST_BIND (sym->st_info) != STB_WEAK)
1a72702b
AM		 12321 (*info->callbacks->undefined_symbol)
12322 (info, bfd_elf_string_from_elf_section
12323 (input_bfd, symtab_hdr->sh_link, sym->st_name),
12324 input_bfd, input_section,
12325 rel->r_offset, TRUE);
b38cadfb 12326
4e7fd91e 12327 if (globals->use_rel)
f8df10f4 12328 {
4e7fd91e
PB		 12329 relocation = (sec->output_section->vma
12330 + sec->output_offset
12331 + sym->st_value);
0e1862bb 12332 if (!bfd_link_relocatable (info)
ab96bf03
AM		 12333 && (sec->flags & SEC_MERGE)
12334 && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
f8df10f4 12335 {
4e7fd91e
PB		 12336 asection *msec;
12337 bfd_vma addend, value;
12338
39623e12 12339 switch (r_type)
4e7fd91e 12340 {
39623e12
PB		 12341 case R_ARM_MOVW_ABS_NC:
12342 case R_ARM_MOVT_ABS:
12343 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
12344 addend = ((value & 0xf0000) >> 4) | (value & 0xfff);
12345 addend = (addend ^ 0x8000) - 0x8000;
12346 break;
f8df10f4 12347
39623e12
PB		 12348 case R_ARM_THM_MOVW_ABS_NC:
12349 case R_ARM_THM_MOVT_ABS:
12350 value = bfd_get_16 (input_bfd, contents + rel->r_offset)
12351 << 16;
12352 value |= bfd_get_16 (input_bfd,
12353 contents + rel->r_offset + 2);
12354 addend = ((value & 0xf7000) >> 4) | (value & 0xff)
12355 | ((value & 0x04000000) >> 15);
12356 addend = (addend ^ 0x8000) - 0x8000;
12357 break;
f8df10f4 12358
39623e12
PB		 12359 default:
12360 if (howto->rightshift
12361 || (howto->src_mask & (howto->src_mask + 1)))
12362 {
4eca0228 12363 _bfd_error_handler
695344c0 12364 /* xgettext:c-format */
39623e12
PB		 12365 (_("%B(%A+0x%lx): %s relocation against SEC_MERGE section"),
12366 input_bfd, input_section,
12367 (long) rel->r_offset, howto->name);
12368 return FALSE;
12369 }
12370
12371 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
12372
12373 /* Get the (signed) value from the instruction. */
12374 addend = value & howto->src_mask;
12375 if (addend & ((howto->src_mask + 1) >> 1))
12376 {
12377 bfd_signed_vma mask;
12378
12379 mask = -1;
12380 mask &= ~ howto->src_mask;
12381 addend |= mask;
12382 }
12383 break;
4e7fd91e 12384 }
39623e12 12385
4e7fd91e
PB		 12386 msec = sec;
12387 addend =
12388 _bfd_elf_rel_local_sym (output_bfd, sym, &msec, addend)
12389 - relocation;
12390 addend += msec->output_section->vma + msec->output_offset;
39623e12 12391
cc643b88 12392 /* Cases here must match those in the preceding
39623e12
PB		 12393 switch statement. */
12394 switch (r_type)
12395 {
12396 case R_ARM_MOVW_ABS_NC:
12397 case R_ARM_MOVT_ABS:
12398 value = (value & 0xfff0f000) | ((addend & 0xf000) << 4)
12399 | (addend & 0xfff);
12400 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
12401 break;
12402
12403 case R_ARM_THM_MOVW_ABS_NC:
12404 case R_ARM_THM_MOVT_ABS:
12405 value = (value & 0xfbf08f00) | ((addend & 0xf700) << 4)
12406 | (addend & 0xff) | ((addend & 0x0800) << 15);
12407 bfd_put_16 (input_bfd, value >> 16,
12408 contents + rel->r_offset);
12409 bfd_put_16 (input_bfd, value,
12410 contents + rel->r_offset + 2);
12411 break;
12412
12413 default:
12414 value = (value & ~ howto->dst_mask)
12415 | (addend & howto->dst_mask);
12416 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
12417 break;
12418 }
f8df10f4 12419 }
f8df10f4 12420 }
4e7fd91e
PB		 12421 else
12422 relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
252b5132
RH		 12423 }
12424 else
12425 {
62d887d4 12426 bfd_boolean warned, ignored;
560e09e9 12427
b2a8e766
AM		 12428 RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
12429 r_symndx, symtab_hdr, sym_hashes,
12430 h, sec, relocation,
62d887d4 12431 unresolved_reloc, warned, ignored);
ba93b8ac
DJ		 12432
12433 sym_type = h->type;
252b5132
RH		 12434 }
12435
dbaa2011 12436 if (sec != NULL && discarded_section (sec))
e4067dbb 12437 RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
545fd46b 12438 rel, 1, relend, howto, 0, contents);
ab96bf03 12439
0e1862bb 12440 if (bfd_link_relocatable (info))
ab96bf03
AM		 12441 {
12442 /* This is a relocatable link. We don't have to change
12443 anything, unless the reloc is against a section symbol,
12444 in which case we have to adjust according to where the
12445 section symbol winds up in the output section. */
12446 if (sym != NULL && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
12447 {
12448 if (globals->use_rel)
12449 arm_add_to_rel (input_bfd, contents + rel->r_offset,
12450 howto, (bfd_signed_vma) sec->output_offset);
12451 else
12452 rel->r_addend += sec->output_offset;
12453 }
12454 continue;
12455 }
12456
252b5132
RH		 12457 if (h != NULL)
12458 name = h->root.root.string;
12459 else
12460 {
12461 name = (bfd_elf_string_from_elf_section
12462 (input_bfd, symtab_hdr->sh_link, sym->st_name));
12463 if (name == NULL || *name == '\0')
12464 name = bfd_section_name (input_bfd, sec);
12465 }
f21f3fe0 12466
cf35638d 12467 if (r_symndx != STN_UNDEF
ba93b8ac
DJ		 12468 && r_type != R_ARM_NONE
12469 && (h == NULL
12470 || h->root.type == bfd_link_hash_defined
12471 || h->root.type == bfd_link_hash_defweak)
12472 && IS_ARM_TLS_RELOC (r_type) != (sym_type == STT_TLS))
12473 {
4eca0228 12474 _bfd_error_handler
ba93b8ac 12475 ((sym_type == STT_TLS
695344c0 12476 /* xgettext:c-format */
ba93b8ac 12477 ? _("%B(%A+0x%lx): %s used with TLS symbol %s")
695344c0 12478 /* xgettext:c-format */
ba93b8ac
DJ		 12479 : _("%B(%A+0x%lx): %s used with non-TLS symbol %s")),
12480 input_bfd,
12481 input_section,
12482 (long) rel->r_offset,
12483 howto->name,
12484 name);
12485 }
12486
0855e32b 12487 /* We call elf32_arm_final_link_relocate unless we're completely
99059e56
RM		 12488 done, i.e., the relaxation produced the final output we want,
12489 and we won't let anybody mess with it. Also, we have to do
12490 addend adjustments in case of a R_ARM_TLS_GOTDESC relocation
6a631e86 12491 both in relaxed and non-relaxed cases. */
39d911fc
TP		 12492 if ((elf32_arm_tls_transition (info, r_type, h) != (unsigned)r_type)
12493 || (IS_ARM_TLS_GNU_RELOC (r_type)
12494 && !((h ? elf32_arm_hash_entry (h)->tls_type :
12495 elf32_arm_local_got_tls_type (input_bfd)[r_symndx])
12496 & GOT_TLS_GDESC)))
12497 {
12498 r = elf32_arm_tls_relax (globals, input_bfd, input_section,
12499 contents, rel, h == NULL);
12500 /* This may have been marked unresolved because it came from
12501 a shared library. But we've just dealt with that. */
12502 unresolved_reloc = 0;
12503 }
12504 else
12505 r = bfd_reloc_continue;
b38cadfb 12506
39d911fc
TP		 12507 if (r == bfd_reloc_continue)
12508 {
12509 unsigned char branch_type =
12510 h ? ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
12511 : ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
12512
12513 r = elf32_arm_final_link_relocate (howto, input_bfd, output_bfd,
12514 input_section, contents, rel,
12515 relocation, info, sec, name,
12516 sym_type, branch_type, h,
12517 &unresolved_reloc,
12518 &error_message);
12519 }
0945cdfd
DJ		 12520
12521 /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
12522 because such sections are not SEC_ALLOC and thus ld.so will
12523 not process them. */
12524 if (unresolved_reloc
99059e56
RM		 12525 && !((input_section->flags & SEC_DEBUGGING) != 0
12526 && h->def_dynamic)
1d5316ab
AM		 12527 && _bfd_elf_section_offset (output_bfd, info, input_section,
12528 rel->r_offset) != (bfd_vma) -1)
0945cdfd 12529 {
4eca0228 12530 _bfd_error_handler
695344c0 12531 /* xgettext:c-format */
843fe662
L		 12532 (_("%B(%A+0x%lx): unresolvable %s relocation against symbol `%s'"),
12533 input_bfd,
12534 input_section,
12535 (long) rel->r_offset,
12536 howto->name,
12537 h->root.root.string);
0945cdfd
DJ		 12538 return FALSE;
12539 }
252b5132
RH		 12540
12541 if (r != bfd_reloc_ok)
12542 {
252b5132
RH		 12543 switch (r)
12544 {
12545 case bfd_reloc_overflow:
cf919dfd
PB		 12546 /* If the overflowing reloc was to an undefined symbol,
12547 we have already printed one error message and there
12548 is no point complaining again. */
1a72702b
AM		 12549 if (!h || h->root.type != bfd_link_hash_undefined)
12550 (*info->callbacks->reloc_overflow)
12551 (info, (h ? &h->root : NULL), name, howto->name,
12552 (bfd_vma) 0, input_bfd, input_section, rel->r_offset);
252b5132
RH		 12553 break;
12554
12555 case bfd_reloc_undefined:
1a72702b
AM		 12556 (*info->callbacks->undefined_symbol)
12557 (info, name, input_bfd, input_section, rel->r_offset, TRUE);
252b5132
RH		 12558 break;
12559
12560 case bfd_reloc_outofrange:
f2a9dd69 12561 error_message = _("out of range");
252b5132
RH		 12562 goto common_error;
12563
12564 case bfd_reloc_notsupported:
f2a9dd69 12565 error_message = _("unsupported relocation");
252b5132
RH		 12566 goto common_error;
12567
12568 case bfd_reloc_dangerous:
f2a9dd69 12569 /* error_message should already be set. */
252b5132
RH		 12570 goto common_error;
12571
12572 default:
f2a9dd69 12573 error_message = _("unknown error");
8029a119 12574 /* Fall through. */
252b5132
RH		 12575
12576 common_error:
f2a9dd69 12577 BFD_ASSERT (error_message != NULL);
1a72702b
AM		 12578 (*info->callbacks->reloc_dangerous)
12579 (info, error_message, input_bfd, input_section, rel->r_offset);
252b5132
RH		 12580 break;
12581 }
12582 }
12583 }
12584
b34976b6 12585 return TRUE;
252b5132
RH		 12586}
12587
91d6fa6a 12588/* Add a new unwind edit to the list described by HEAD, TAIL. If TINDEX is zero,
2468f9c9 12589 adds the edit to the start of the list. (The list must be built in order of
91d6fa6a 12590 ascending TINDEX: the function's callers are primarily responsible for
2468f9c9
PB		 12591 maintaining that condition). */
12592
12593static void
12594add_unwind_table_edit (arm_unwind_table_edit **head,
12595 arm_unwind_table_edit **tail,
12596 arm_unwind_edit_type type,
12597 asection *linked_section,
91d6fa6a 12598 unsigned int tindex)
2468f9c9 12599{
21d799b5
NC		 12600 arm_unwind_table_edit *new_edit = (arm_unwind_table_edit *)
12601 xmalloc (sizeof (arm_unwind_table_edit));
b38cadfb 12602
2468f9c9
PB		 12603 new_edit->type = type;
12604 new_edit->linked_section = linked_section;
91d6fa6a 12605 new_edit->index = tindex;
b38cadfb 12606
91d6fa6a 12607 if (tindex > 0)
2468f9c9
PB		 12608 {
12609 new_edit->next = NULL;
12610
12611 if (*tail)
12612 (*tail)->next = new_edit;
12613
12614 (*tail) = new_edit;
12615
12616 if (!*head)
12617 (*head) = new_edit;
12618 }
12619 else
12620 {
12621 new_edit->next = *head;
12622
12623 if (!*tail)
12624 *tail = new_edit;
12625
12626 *head = new_edit;
12627 }
12628}
12629
12630static _arm_elf_section_data *get_arm_elf_section_data (asection *);
12631
12632/* Increase the size of EXIDX_SEC by ADJUST bytes. ADJUST mau be negative. */
12633static void
12634adjust_exidx_size(asection *exidx_sec, int adjust)
12635{
12636 asection *out_sec;
12637
12638 if (!exidx_sec->rawsize)
12639 exidx_sec->rawsize = exidx_sec->size;
12640
12641 bfd_set_section_size (exidx_sec->owner, exidx_sec, exidx_sec->size + adjust);
12642 out_sec = exidx_sec->output_section;
12643 /* Adjust size of output section. */
12644 bfd_set_section_size (out_sec->owner, out_sec, out_sec->size +adjust);
12645}
12646
12647/* Insert an EXIDX_CANTUNWIND marker at the end of a section. */
12648static void
12649insert_cantunwind_after(asection *text_sec, asection *exidx_sec)
12650{
12651 struct _arm_elf_section_data *exidx_arm_data;
12652
12653 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
12654 add_unwind_table_edit (
12655 &exidx_arm_data->u.exidx.unwind_edit_list,
12656 &exidx_arm_data->u.exidx.unwind_edit_tail,
12657 INSERT_EXIDX_CANTUNWIND_AT_END, text_sec, UINT_MAX);
12658
491d01d3
YU		 12659 exidx_arm_data->additional_reloc_count++;
12660
2468f9c9
PB		 12661 adjust_exidx_size(exidx_sec, 8);
12662}
12663
12664/* Scan .ARM.exidx tables, and create a list describing edits which should be
12665 made to those tables, such that:
b38cadfb 12666
2468f9c9
PB		 12667 1. Regions without unwind data are marked with EXIDX_CANTUNWIND entries.
12668 2. Duplicate entries are merged together (EXIDX_CANTUNWIND, or unwind
99059e56 12669 codes which have been inlined into the index).
2468f9c9 12670
85fdf906
AH		 12671 If MERGE_EXIDX_ENTRIES is false, duplicate entries are not merged.
12672
2468f9c9 12673 The edits are applied when the tables are written
b38cadfb 12674 (in elf32_arm_write_section). */
2468f9c9
PB		 12675
12676bfd_boolean
12677elf32_arm_fix_exidx_coverage (asection **text_section_order,
12678 unsigned int num_text_sections,
85fdf906
AH		 12679 struct bfd_link_info *info,
12680 bfd_boolean merge_exidx_entries)
2468f9c9
PB		 12681{
12682 bfd *inp;
12683 unsigned int last_second_word = 0, i;
12684 asection *last_exidx_sec = NULL;
12685 asection *last_text_sec = NULL;
12686 int last_unwind_type = -1;
12687
12688 /* Walk over all EXIDX sections, and create backlinks from the corrsponding
12689 text sections. */
c72f2fb2 12690 for (inp = info->input_bfds; inp != NULL; inp = inp->link.next)
2468f9c9
PB		 12691 {
12692 asection *sec;
b38cadfb 12693
2468f9c9 12694 for (sec = inp->sections; sec != NULL; sec = sec->next)
99059e56 12695 {
2468f9c9
PB		 12696 struct bfd_elf_section_data *elf_sec = elf_section_data (sec);
12697 Elf_Internal_Shdr *hdr = &elf_sec->this_hdr;
b38cadfb 12698
dec9d5df 12699 if (!hdr || hdr->sh_type != SHT_ARM_EXIDX)
2468f9c9 12700 continue;
b38cadfb 12701
2468f9c9
PB		 12702 if (elf_sec->linked_to)
12703 {
12704 Elf_Internal_Shdr *linked_hdr
99059e56 12705 = &elf_section_data (elf_sec->linked_to)->this_hdr;
2468f9c9 12706 struct _arm_elf_section_data *linked_sec_arm_data
99059e56 12707 = get_arm_elf_section_data (linked_hdr->bfd_section);
2468f9c9
PB		 12708
12709 if (linked_sec_arm_data == NULL)
99059e56 12710 continue;
2468f9c9
PB		 12711
12712 /* Link this .ARM.exidx section back from the text section it
99059e56 12713 describes. */
2468f9c9
PB		 12714 linked_sec_arm_data->u.text.arm_exidx_sec = sec;
12715 }
12716 }
12717 }
12718
12719 /* Walk all text sections in order of increasing VMA. Eilminate duplicate
12720 index table entries (EXIDX_CANTUNWIND and inlined unwind opcodes),
91d6fa6a 12721 and add EXIDX_CANTUNWIND entries for sections with no unwind table data. */
2468f9c9
PB		 12722
12723 for (i = 0; i < num_text_sections; i++)
12724 {
12725 asection *sec = text_section_order[i];
12726 asection *exidx_sec;
12727 struct _arm_elf_section_data *arm_data = get_arm_elf_section_data (sec);
12728 struct _arm_elf_section_data *exidx_arm_data;
12729 bfd_byte *contents = NULL;
12730 int deleted_exidx_bytes = 0;
12731 bfd_vma j;
12732 arm_unwind_table_edit *unwind_edit_head = NULL;
12733 arm_unwind_table_edit *unwind_edit_tail = NULL;
12734 Elf_Internal_Shdr *hdr;
12735 bfd *ibfd;
12736
12737 if (arm_data == NULL)
99059e56 12738 continue;
2468f9c9
PB		 12739
12740 exidx_sec = arm_data->u.text.arm_exidx_sec;
12741 if (exidx_sec == NULL)
12742 {
12743 /* Section has no unwind data. */
12744 if (last_unwind_type == 0 || !last_exidx_sec)
12745 continue;
12746
12747 /* Ignore zero sized sections. */
12748 if (sec->size == 0)
12749 continue;
12750
12751 insert_cantunwind_after(last_text_sec, last_exidx_sec);
12752 last_unwind_type = 0;
12753 continue;
12754 }
12755
22a8f80e
PB		 12756 /* Skip /DISCARD/ sections. */
12757 if (bfd_is_abs_section (exidx_sec->output_section))
12758 continue;
12759
2468f9c9
PB		 12760 hdr = &elf_section_data (exidx_sec)->this_hdr;
12761 if (hdr->sh_type != SHT_ARM_EXIDX)
99059e56 12762 continue;
b38cadfb 12763
2468f9c9
PB		 12764 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
12765 if (exidx_arm_data == NULL)
99059e56 12766 continue;
b38cadfb 12767
2468f9c9 12768 ibfd = exidx_sec->owner;
b38cadfb 12769
2468f9c9
PB		 12770 if (hdr->contents != NULL)
12771 contents = hdr->contents;
12772 else if (! bfd_malloc_and_get_section (ibfd, exidx_sec, &contents))
12773 /* An error? */
12774 continue;
12775
ac06903d
YU		 12776 if (last_unwind_type > 0)
12777 {
12778 unsigned int first_word = bfd_get_32 (ibfd, contents);
12779 /* Add cantunwind if first unwind item does not match section
12780 start. */
12781 if (first_word != sec->vma)
12782 {
12783 insert_cantunwind_after (last_text_sec, last_exidx_sec);
12784 last_unwind_type = 0;
12785 }
12786 }
12787
2468f9c9
PB		 12788 for (j = 0; j < hdr->sh_size; j += 8)
12789 {
12790 unsigned int second_word = bfd_get_32 (ibfd, contents + j + 4);
12791 int unwind_type;
12792 int elide = 0;
12793
12794 /* An EXIDX_CANTUNWIND entry. */
12795 if (second_word == 1)
12796 {
12797 if (last_unwind_type == 0)
12798 elide = 1;
12799 unwind_type = 0;
12800 }
12801 /* Inlined unwinding data. Merge if equal to previous. */
12802 else if ((second_word & 0x80000000) != 0)
12803 {
85fdf906
AH		 12804 if (merge_exidx_entries
12805 && last_second_word == second_word && last_unwind_type == 1)
2468f9c9
PB		 12806 elide = 1;
12807 unwind_type = 1;
12808 last_second_word = second_word;
12809 }
12810 /* Normal table entry. In theory we could merge these too,
12811 but duplicate entries are likely to be much less common. */
12812 else
12813 unwind_type = 2;
12814
491d01d3 12815 if (elide && !bfd_link_relocatable (info))
2468f9c9
PB		 12816 {
12817 add_unwind_table_edit (&unwind_edit_head, &unwind_edit_tail,
12818 DELETE_EXIDX_ENTRY, NULL, j / 8);
12819
12820 deleted_exidx_bytes += 8;
12821 }
12822
12823 last_unwind_type = unwind_type;
12824 }
12825
12826 /* Free contents if we allocated it ourselves. */
12827 if (contents != hdr->contents)
99059e56 12828 free (contents);
2468f9c9
PB		 12829
12830 /* Record edits to be applied later (in elf32_arm_write_section). */
12831 exidx_arm_data->u.exidx.unwind_edit_list = unwind_edit_head;
12832 exidx_arm_data->u.exidx.unwind_edit_tail = unwind_edit_tail;
b38cadfb 12833
2468f9c9
PB		 12834 if (deleted_exidx_bytes > 0)
12835 adjust_exidx_size(exidx_sec, -deleted_exidx_bytes);
12836
12837 last_exidx_sec = exidx_sec;
12838 last_text_sec = sec;
12839 }
12840
12841 /* Add terminating CANTUNWIND entry. */
491d01d3
YU		 12842 if (!bfd_link_relocatable (info) && last_exidx_sec
12843 && last_unwind_type != 0)
2468f9c9
PB		 12844 insert_cantunwind_after(last_text_sec, last_exidx_sec);
12845
12846 return TRUE;
12847}
12848
3e6b1042
DJ		 12849static bfd_boolean
12850elf32_arm_output_glue_section (struct bfd_link_info *info, bfd *obfd,
12851 bfd *ibfd, const char *name)
12852{
12853 asection *sec, *osec;
12854
3d4d4302 12855 sec = bfd_get_linker_section (ibfd, name);
3e6b1042
DJ		 12856 if (sec == NULL || (sec->flags & SEC_EXCLUDE) != 0)
12857 return TRUE;
12858
12859 osec = sec->output_section;
12860 if (elf32_arm_write_section (obfd, info, sec, sec->contents))
12861 return TRUE;
12862
12863 if (! bfd_set_section_contents (obfd, osec, sec->contents,
12864 sec->output_offset, sec->size))
12865 return FALSE;
12866
12867 return TRUE;
12868}
12869
12870static bfd_boolean
12871elf32_arm_final_link (bfd *abfd, struct bfd_link_info *info)
12872{
12873 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
fe33d2fa 12874 asection *sec, *osec;
3e6b1042 12875
4dfe6ac6
NC		 12876 if (globals == NULL)
12877 return FALSE;
12878
3e6b1042
DJ		 12879 /* Invoke the regular ELF backend linker to do all the work. */
12880 if (!bfd_elf_final_link (abfd, info))
12881 return FALSE;
12882
fe33d2fa
CL		 12883 /* Process stub sections (eg BE8 encoding, ...). */
12884 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
7292b3ac 12885 unsigned int i;
cdb21a0a
NS		 12886 for (i=0; i<htab->top_id; i++)
12887 {
12888 sec = htab->stub_group[i].stub_sec;
12889 /* Only process it once, in its link_sec slot. */
12890 if (sec && i == htab->stub_group[i].link_sec->id)
12891 {
12892 osec = sec->output_section;
12893 elf32_arm_write_section (abfd, info, sec, sec->contents);
12894 if (! bfd_set_section_contents (abfd, osec, sec->contents,
12895 sec->output_offset, sec->size))
12896 return FALSE;
12897 }
fe33d2fa 12898 }
fe33d2fa 12899
3e6b1042
DJ		 12900 /* Write out any glue sections now that we have created all the
12901 stubs. */
12902 if (globals->bfd_of_glue_owner != NULL)
12903 {
12904 if (! elf32_arm_output_glue_section (info, abfd,
12905 globals->bfd_of_glue_owner,
12906 ARM2THUMB_GLUE_SECTION_NAME))
12907 return FALSE;
12908
12909 if (! elf32_arm_output_glue_section (info, abfd,
12910 globals->bfd_of_glue_owner,
12911 THUMB2ARM_GLUE_SECTION_NAME))
12912 return FALSE;
12913
12914 if (! elf32_arm_output_glue_section (info, abfd,
12915 globals->bfd_of_glue_owner,
12916 VFP11_ERRATUM_VENEER_SECTION_NAME))
12917 return FALSE;
12918
a504d23a
LA		 12919 if (! elf32_arm_output_glue_section (info, abfd,
12920 globals->bfd_of_glue_owner,
12921 STM32L4XX_ERRATUM_VENEER_SECTION_NAME))
12922 return FALSE;
12923
3e6b1042
DJ		 12924 if (! elf32_arm_output_glue_section (info, abfd,
12925 globals->bfd_of_glue_owner,
12926 ARM_BX_GLUE_SECTION_NAME))
12927 return FALSE;
12928 }
12929
12930 return TRUE;
12931}
12932
5968a7b8
NC		 12933/* Return a best guess for the machine number based on the attributes. */
12934
12935static unsigned int
12936bfd_arm_get_mach_from_attributes (bfd * abfd)
12937{
12938 int arch = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_CPU_arch);
12939
12940 switch (arch)
12941 {
12942 case TAG_CPU_ARCH_V4: return bfd_mach_arm_4;
12943 case TAG_CPU_ARCH_V4T: return bfd_mach_arm_4T;
12944 case TAG_CPU_ARCH_V5T: return bfd_mach_arm_5T;
12945
12946 case TAG_CPU_ARCH_V5TE:
12947 {
12948 char * name;
12949
12950 BFD_ASSERT (Tag_CPU_name < NUM_KNOWN_OBJ_ATTRIBUTES);
12951 name = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_CPU_name].s;
12952
12953 if (name)
12954 {
12955 if (strcmp (name, "IWMMXT2") == 0)
12956 return bfd_mach_arm_iWMMXt2;
12957
12958 if (strcmp (name, "IWMMXT") == 0)
6034aab8 12959 return bfd_mach_arm_iWMMXt;
088ca6c1
NC		 12960
12961 if (strcmp (name, "XSCALE") == 0)
12962 {
12963 int wmmx;
12964
12965 BFD_ASSERT (Tag_WMMX_arch < NUM_KNOWN_OBJ_ATTRIBUTES);
12966 wmmx = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_WMMX_arch].i;
12967 switch (wmmx)
12968 {
12969 case 1: return bfd_mach_arm_iWMMXt;
12970 case 2: return bfd_mach_arm_iWMMXt2;
12971 default: return bfd_mach_arm_XScale;
12972 }
12973 }
5968a7b8
NC		 12974 }
12975
12976 return bfd_mach_arm_5TE;
12977 }
12978
12979 default:
12980 return bfd_mach_arm_unknown;
12981 }
12982}
12983
c178919b
NC		 12984/* Set the right machine number. */
12985
12986static bfd_boolean
57e8b36a 12987elf32_arm_object_p (bfd *abfd)
c178919b 12988{
5a6c6817 12989 unsigned int mach;
57e8b36a 12990
5a6c6817 12991 mach = bfd_arm_get_mach_from_notes (abfd, ARM_NOTE_SECTION);
c178919b 12992
5968a7b8
NC		 12993 if (mach == bfd_mach_arm_unknown)
12994 {
12995 if (elf_elfheader (abfd)->e_flags & EF_ARM_MAVERICK_FLOAT)
12996 mach = bfd_mach_arm_ep9312;
12997 else
12998 mach = bfd_arm_get_mach_from_attributes (abfd);
12999 }
c178919b 13000
5968a7b8 13001 bfd_default_set_arch_mach (abfd, bfd_arch_arm, mach);
c178919b
NC		 13002 return TRUE;
13003}
13004
fc830a83 13005/* Function to keep ARM specific flags in the ELF header. */
3c9458e9 13006
b34976b6 13007static bfd_boolean
57e8b36a 13008elf32_arm_set_private_flags (bfd *abfd, flagword flags)
252b5132
RH		 13009{
13010 if (elf_flags_init (abfd)
13011 && elf_elfheader (abfd)->e_flags != flags)
13012 {
fc830a83
NC		 13013 if (EF_ARM_EABI_VERSION (flags) == EF_ARM_EABI_UNKNOWN)
13014 {
fd2ec330 13015 if (flags & EF_ARM_INTERWORK)
4eca0228 13016 _bfd_error_handler
d003868e
AM		 13017 (_("Warning: Not setting interworking flag of %B since it has already been specified as non-interworking"),
13018 abfd);
fc830a83 13019 else
d003868e
AM		 13020 _bfd_error_handler
13021 (_("Warning: Clearing the interworking flag of %B due to outside request"),
13022 abfd);
fc830a83 13023 }
252b5132
RH		 13024 }
13025 else
13026 {
13027 elf_elfheader (abfd)->e_flags = flags;
b34976b6 13028 elf_flags_init (abfd) = TRUE;
252b5132
RH		 13029 }
13030
b34976b6 13031 return TRUE;
252b5132
RH		 13032}
13033
fc830a83 13034/* Copy backend specific data from one object module to another. */
9b485d32 13035
b34976b6 13036static bfd_boolean
57e8b36a 13037elf32_arm_copy_private_bfd_data (bfd *ibfd, bfd *obfd)
252b5132
RH		 13038{
13039 flagword in_flags;
13040 flagword out_flags;
13041
0ffa91dd 13042 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
b34976b6 13043 return TRUE;
252b5132 13044
fc830a83 13045 in_flags = elf_elfheader (ibfd)->e_flags;
252b5132
RH		 13046 out_flags = elf_elfheader (obfd)->e_flags;
13047
fc830a83
NC		 13048 if (elf_flags_init (obfd)
13049 && EF_ARM_EABI_VERSION (out_flags) == EF_ARM_EABI_UNKNOWN
13050 && in_flags != out_flags)
252b5132 13051 {
252b5132 13052 /* Cannot mix APCS26 and APCS32 code. */
fd2ec330 13053 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
b34976b6 13054 return FALSE;
252b5132
RH		 13055
13056 /* Cannot mix float APCS and non-float APCS code. */
fd2ec330 13057 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
b34976b6 13058 return FALSE;
252b5132
RH		 13059
13060 /* If the src and dest have different interworking flags
99059e56 13061 then turn off the interworking bit. */
fd2ec330 13062 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
252b5132 13063 {
fd2ec330 13064 if (out_flags & EF_ARM_INTERWORK)
d003868e
AM		 13065 _bfd_error_handler
13066 (_("Warning: Clearing the interworking flag of %B because non-interworking code in %B has been linked with it"),
13067 obfd, ibfd);
252b5132 13068
fd2ec330 13069 in_flags &= ~EF_ARM_INTERWORK;
252b5132 13070 }
1006ba19
PB		 13071
13072 /* Likewise for PIC, though don't warn for this case. */
fd2ec330
PB		 13073 if ((in_flags & EF_ARM_PIC) != (out_flags & EF_ARM_PIC))
13074 in_flags &= ~EF_ARM_PIC;
252b5132
RH		 13075 }
13076
13077 elf_elfheader (obfd)->e_flags = in_flags;
b34976b6 13078 elf_flags_init (obfd) = TRUE;
252b5132 13079
e2349352 13080 return _bfd_elf_copy_private_bfd_data (ibfd, obfd);
ee065d83
PB		 13081}
13082
13083/* Values for Tag_ABI_PCS_R9_use. */
13084enum
13085{
13086 AEABI_R9_V6,
13087 AEABI_R9_SB,
13088 AEABI_R9_TLS,
13089 AEABI_R9_unused
13090};
13091
13092/* Values for Tag_ABI_PCS_RW_data. */
13093enum
13094{
13095 AEABI_PCS_RW_data_absolute,
13096 AEABI_PCS_RW_data_PCrel,
13097 AEABI_PCS_RW_data_SBrel,
13098 AEABI_PCS_RW_data_unused
13099};
13100
13101/* Values for Tag_ABI_enum_size. */
13102enum
13103{
13104 AEABI_enum_unused,
13105 AEABI_enum_short,
13106 AEABI_enum_wide,
13107 AEABI_enum_forced_wide
13108};
13109
104d59d1
JM		 13110/* Determine whether an object attribute tag takes an integer, a
13111 string or both. */
906e58ca 13112
104d59d1
JM		 13113static int
13114elf32_arm_obj_attrs_arg_type (int tag)
13115{
13116 if (tag == Tag_compatibility)
3483fe2e 13117 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_STR_VAL;
2d0bb761 13118 else if (tag == Tag_nodefaults)
3483fe2e
AS		 13119 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_NO_DEFAULT;
13120 else if (tag == Tag_CPU_raw_name || tag == Tag_CPU_name)
13121 return ATTR_TYPE_FLAG_STR_VAL;
104d59d1 13122 else if (tag < 32)
3483fe2e 13123 return ATTR_TYPE_FLAG_INT_VAL;
104d59d1 13124 else
3483fe2e 13125 return (tag & 1) != 0 ? ATTR_TYPE_FLAG_STR_VAL : ATTR_TYPE_FLAG_INT_VAL;
104d59d1
JM		 13126}
13127
5aa6ff7c
AS		 13128/* The ABI defines that Tag_conformance should be emitted first, and that
13129 Tag_nodefaults should be second (if either is defined). This sets those
13130 two positions, and bumps up the position of all the remaining tags to
13131 compensate. */
13132static int
13133elf32_arm_obj_attrs_order (int num)
13134{
3de4a297 13135 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE)
5aa6ff7c 13136 return Tag_conformance;
3de4a297 13137 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE + 1)
5aa6ff7c
AS		 13138 return Tag_nodefaults;
13139 if ((num - 2) < Tag_nodefaults)
13140 return num - 2;
13141 if ((num - 1) < Tag_conformance)
13142 return num - 1;
13143 return num;
13144}
13145
e8b36cd1
JM		 13146/* Attribute numbers >=64 (mod 128) can be safely ignored. */
13147static bfd_boolean
13148elf32_arm_obj_attrs_handle_unknown (bfd *abfd, int tag)
13149{
13150 if ((tag & 127) < 64)
13151 {
13152 _bfd_error_handler
13153 (_("%B: Unknown mandatory EABI object attribute %d"),
13154 abfd, tag);
13155 bfd_set_error (bfd_error_bad_value);
13156 return FALSE;
13157 }
13158 else
13159 {
13160 _bfd_error_handler
13161 (_("Warning: %B: Unknown EABI object attribute %d"),
13162 abfd, tag);
13163 return TRUE;
13164 }
13165}
13166
91e22acd
AS		 13167/* Read the architecture from the Tag_also_compatible_with attribute, if any.
13168 Returns -1 if no architecture could be read. */
13169
13170static int
13171get_secondary_compatible_arch (bfd *abfd)
13172{
13173 obj_attribute *attr =
13174 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
13175
13176 /* Note: the tag and its argument below are uleb128 values, though
13177 currently-defined values fit in one byte for each. */
13178 if (attr->s
13179 && attr->s[0] == Tag_CPU_arch
13180 && (attr->s[1] & 128) != 128
13181 && attr->s[2] == 0)
13182 return attr->s[1];
13183
13184 /* This tag is "safely ignorable", so don't complain if it looks funny. */
13185 return -1;
13186}
13187
13188/* Set, or unset, the architecture of the Tag_also_compatible_with attribute.
13189 The tag is removed if ARCH is -1. */
13190
8e79c3df 13191static void
91e22acd 13192set_secondary_compatible_arch (bfd *abfd, int arch)
8e79c3df 13193{
91e22acd
AS		 13194 obj_attribute *attr =
13195 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
8e79c3df 13196
91e22acd
AS		 13197 if (arch == -1)
13198 {
13199 attr->s = NULL;
13200 return;
8e79c3df 13201 }
91e22acd
AS		 13202
13203 /* Note: the tag and its argument below are uleb128 values, though
13204 currently-defined values fit in one byte for each. */
13205 if (!attr->s)
21d799b5 13206 attr->s = (char *) bfd_alloc (abfd, 3);
91e22acd
AS		 13207 attr->s[0] = Tag_CPU_arch;
13208 attr->s[1] = arch;
13209 attr->s[2] = '\0';
8e79c3df
CM		 13210}
13211
91e22acd
AS		 13212/* Combine two values for Tag_CPU_arch, taking secondary compatibility tags
13213 into account. */
13214
13215static int
13216tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
13217 int newtag, int secondary_compat)
8e79c3df 13218{
91e22acd
AS		 13219#define T(X) TAG_CPU_ARCH_##X
13220 int tagl, tagh, result;
13221 const int v6t2[] =
13222 {
13223 T(V6T2), /* PRE_V4. */
13224 T(V6T2), /* V4. */
13225 T(V6T2), /* V4T. */
13226 T(V6T2), /* V5T. */
13227 T(V6T2), /* V5TE. */
13228 T(V6T2), /* V5TEJ. */
13229 T(V6T2), /* V6. */
13230 T(V7), /* V6KZ. */
13231 T(V6T2) /* V6T2. */
13232 };
13233 const int v6k[] =
13234 {
13235 T(V6K), /* PRE_V4. */
13236 T(V6K), /* V4. */
13237 T(V6K), /* V4T. */
13238 T(V6K), /* V5T. */
13239 T(V6K), /* V5TE. */
13240 T(V6K), /* V5TEJ. */
13241 T(V6K), /* V6. */
13242 T(V6KZ), /* V6KZ. */
13243 T(V7), /* V6T2. */
13244 T(V6K) /* V6K. */
13245 };
13246 const int v7[] =
13247 {
13248 T(V7), /* PRE_V4. */
13249 T(V7), /* V4. */
13250 T(V7), /* V4T. */
13251 T(V7), /* V5T. */
13252 T(V7), /* V5TE. */
13253 T(V7), /* V5TEJ. */
13254 T(V7), /* V6. */
13255 T(V7), /* V6KZ. */
13256 T(V7), /* V6T2. */
13257 T(V7), /* V6K. */
13258 T(V7) /* V7. */
13259 };
13260 const int v6_m[] =
13261 {
13262 -1, /* PRE_V4. */
13263 -1, /* V4. */
13264 T(V6K), /* V4T. */
13265 T(V6K), /* V5T. */
13266 T(V6K), /* V5TE. */
13267 T(V6K), /* V5TEJ. */
13268 T(V6K), /* V6. */
13269 T(V6KZ), /* V6KZ. */
13270 T(V7), /* V6T2. */
13271 T(V6K), /* V6K. */
13272 T(V7), /* V7. */
13273 T(V6_M) /* V6_M. */
13274 };
13275 const int v6s_m[] =
13276 {
13277 -1, /* PRE_V4. */
13278 -1, /* V4. */
13279 T(V6K), /* V4T. */
13280 T(V6K), /* V5T. */
13281 T(V6K), /* V5TE. */
13282 T(V6K), /* V5TEJ. */
13283 T(V6K), /* V6. */
13284 T(V6KZ), /* V6KZ. */
13285 T(V7), /* V6T2. */
13286 T(V6K), /* V6K. */
13287 T(V7), /* V7. */
13288 T(V6S_M), /* V6_M. */
13289 T(V6S_M) /* V6S_M. */
13290 };
9e3c6df6
PB		 13291 const int v7e_m[] =
13292 {
13293 -1, /* PRE_V4. */
13294 -1, /* V4. */
13295 T(V7E_M), /* V4T. */
13296 T(V7E_M), /* V5T. */
13297 T(V7E_M), /* V5TE. */
13298 T(V7E_M), /* V5TEJ. */
13299 T(V7E_M), /* V6. */
13300 T(V7E_M), /* V6KZ. */
13301 T(V7E_M), /* V6T2. */
13302 T(V7E_M), /* V6K. */
13303 T(V7E_M), /* V7. */
13304 T(V7E_M), /* V6_M. */
13305 T(V7E_M), /* V6S_M. */
13306 T(V7E_M) /* V7E_M. */
13307 };
bca38921
MGD		 13308 const int v8[] =
13309 {
13310 T(V8), /* PRE_V4. */
13311 T(V8), /* V4. */
13312 T(V8), /* V4T. */
13313 T(V8), /* V5T. */
13314 T(V8), /* V5TE. */
13315 T(V8), /* V5TEJ. */
13316 T(V8), /* V6. */
13317 T(V8), /* V6KZ. */
13318 T(V8), /* V6T2. */
13319 T(V8), /* V6K. */
13320 T(V8), /* V7. */
13321 T(V8), /* V6_M. */
13322 T(V8), /* V6S_M. */
13323 T(V8), /* V7E_M. */
13324 T(V8) /* V8. */
13325 };
2fd158eb
TP		 13326 const int v8m_baseline[] =
13327 {
13328 -1, /* PRE_V4. */
13329 -1, /* V4. */
13330 -1, /* V4T. */
13331 -1, /* V5T. */
13332 -1, /* V5TE. */
13333 -1, /* V5TEJ. */
13334 -1, /* V6. */
13335 -1, /* V6KZ. */
13336 -1, /* V6T2. */
13337 -1, /* V6K. */
13338 -1, /* V7. */
13339 T(V8M_BASE), /* V6_M. */
13340 T(V8M_BASE), /* V6S_M. */
13341 -1, /* V7E_M. */
13342 -1, /* V8. */
13343 -1,
13344 T(V8M_BASE) /* V8-M BASELINE. */
13345 };
13346 const int v8m_mainline[] =
13347 {
13348 -1, /* PRE_V4. */
13349 -1, /* V4. */
13350 -1, /* V4T. */
13351 -1, /* V5T. */
13352 -1, /* V5TE. */
13353 -1, /* V5TEJ. */
13354 -1, /* V6. */
13355 -1, /* V6KZ. */
13356 -1, /* V6T2. */
13357 -1, /* V6K. */
13358 T(V8M_MAIN), /* V7. */
13359 T(V8M_MAIN), /* V6_M. */
13360 T(V8M_MAIN), /* V6S_M. */
13361 T(V8M_MAIN), /* V7E_M. */
13362 -1, /* V8. */
13363 -1,
13364 T(V8M_MAIN), /* V8-M BASELINE. */
13365 T(V8M_MAIN) /* V8-M MAINLINE. */
13366 };
91e22acd
AS		 13367 const int v4t_plus_v6_m[] =
13368 {
13369 -1, /* PRE_V4. */
13370 -1, /* V4. */
13371 T(V4T), /* V4T. */
13372 T(V5T), /* V5T. */
13373 T(V5TE), /* V5TE. */
13374 T(V5TEJ), /* V5TEJ. */
13375 T(V6), /* V6. */
13376 T(V6KZ), /* V6KZ. */
13377 T(V6T2), /* V6T2. */
13378 T(V6K), /* V6K. */
13379 T(V7), /* V7. */
13380 T(V6_M), /* V6_M. */
13381 T(V6S_M), /* V6S_M. */
9e3c6df6 13382 T(V7E_M), /* V7E_M. */
bca38921 13383 T(V8), /* V8. */
4ed7ed8d 13384 -1, /* Unused. */
2fd158eb
TP		 13385 T(V8M_BASE), /* V8-M BASELINE. */
13386 T(V8M_MAIN), /* V8-M MAINLINE. */
91e22acd
AS		 13387 T(V4T_PLUS_V6_M) /* V4T plus V6_M. */
13388 };
13389 const int *comb[] =
13390 {
13391 v6t2,
13392 v6k,
13393 v7,
13394 v6_m,
13395 v6s_m,
9e3c6df6 13396 v7e_m,
bca38921 13397 v8,
4ed7ed8d 13398 NULL,
2fd158eb
TP		 13399 v8m_baseline,
13400 v8m_mainline,
91e22acd
AS		 13401 /* Pseudo-architecture. */
13402 v4t_plus_v6_m
13403 };
13404
13405 /* Check we've not got a higher architecture than we know about. */
13406
9e3c6df6 13407 if (oldtag > MAX_TAG_CPU_ARCH || newtag > MAX_TAG_CPU_ARCH)
91e22acd 13408 {
3895f852 13409 _bfd_error_handler (_("error: %B: Unknown CPU architecture"), ibfd);
91e22acd
AS		 13410 return -1;
13411 }
13412
13413 /* Override old tag if we have a Tag_also_compatible_with on the output. */
13414
13415 if ((oldtag == T(V6_M) && *secondary_compat_out == T(V4T))
13416 || (oldtag == T(V4T) && *secondary_compat_out == T(V6_M)))
13417 oldtag = T(V4T_PLUS_V6_M);
13418
13419 /* And override the new tag if we have a Tag_also_compatible_with on the
13420 input. */
13421
13422 if ((newtag == T(V6_M) && secondary_compat == T(V4T))
13423 || (newtag == T(V4T) && secondary_compat == T(V6_M)))
13424 newtag = T(V4T_PLUS_V6_M);
13425
13426 tagl = (oldtag < newtag) ? oldtag : newtag;
13427 result = tagh = (oldtag > newtag) ? oldtag : newtag;
13428
13429 /* Architectures before V6KZ add features monotonically. */
13430 if (tagh <= TAG_CPU_ARCH_V6KZ)
13431 return result;
13432
4ed7ed8d 13433 result = comb[tagh - T(V6T2)] ? comb[tagh - T(V6T2)][tagl] : -1;
91e22acd
AS		 13434
13435 /* Use Tag_CPU_arch == V4T and Tag_also_compatible_with (Tag_CPU_arch V6_M)
13436 as the canonical version. */
13437 if (result == T(V4T_PLUS_V6_M))
13438 {
13439 result = T(V4T);
13440 *secondary_compat_out = T(V6_M);
13441 }
13442 else
13443 *secondary_compat_out = -1;
13444
13445 if (result == -1)
13446 {
3895f852 13447 _bfd_error_handler (_("error: %B: Conflicting CPU architectures %d/%d"),
91e22acd
AS		 13448 ibfd, oldtag, newtag);
13449 return -1;
13450 }
13451
13452 return result;
13453#undef T
8e79c3df
CM		 13454}
13455
ac56ee8f
MGD		 13456/* Query attributes object to see if integer divide instructions may be
13457 present in an object. */
13458static bfd_boolean
13459elf32_arm_attributes_accept_div (const obj_attribute *attr)
13460{
13461 int arch = attr[Tag_CPU_arch].i;
13462 int profile = attr[Tag_CPU_arch_profile].i;
13463
13464 switch (attr[Tag_DIV_use].i)
13465 {
13466 case 0:
13467 /* Integer divide allowed if instruction contained in archetecture. */
13468 if (arch == TAG_CPU_ARCH_V7 && (profile == 'R' || profile == 'M'))
13469 return TRUE;
13470 else if (arch >= TAG_CPU_ARCH_V7E_M)
13471 return TRUE;
13472 else
13473 return FALSE;
13474
13475 case 1:
13476 /* Integer divide explicitly prohibited. */
13477 return FALSE;
13478
13479 default:
13480 /* Unrecognised case - treat as allowing divide everywhere. */
13481 case 2:
13482 /* Integer divide allowed in ARM state. */
13483 return TRUE;
13484 }
13485}
13486
13487/* Query attributes object to see if integer divide instructions are
13488 forbidden to be in the object. This is not the inverse of
13489 elf32_arm_attributes_accept_div. */
13490static bfd_boolean
13491elf32_arm_attributes_forbid_div (const obj_attribute *attr)
13492{
13493 return attr[Tag_DIV_use].i == 1;
13494}
13495
ee065d83
PB		 13496/* Merge EABI object attributes from IBFD into OBFD. Raise an error if there
13497 are conflicting attributes. */
906e58ca 13498
ee065d83 13499static bfd_boolean
50e03d47 13500elf32_arm_merge_eabi_attributes (bfd *ibfd, struct bfd_link_info *info)
ee065d83 13501{
50e03d47 13502 bfd *obfd = info->output_bfd;
104d59d1
JM		 13503 obj_attribute *in_attr;
13504 obj_attribute *out_attr;
ee065d83
PB		 13505 /* Some tags have 0 = don't care, 1 = strong requirement,
13506 2 = weak requirement. */
91e22acd 13507 static const int order_021[3] = {0, 2, 1};
ee065d83 13508 int i;
91e22acd 13509 bfd_boolean result = TRUE;
9274e9de 13510 const char *sec_name = get_elf_backend_data (ibfd)->obj_attrs_section;
ee065d83 13511
3e6b1042
DJ		 13512 /* Skip the linker stubs file. This preserves previous behavior
13513 of accepting unknown attributes in the first input file - but
13514 is that a bug? */
13515 if (ibfd->flags & BFD_LINKER_CREATED)
13516 return TRUE;
13517
9274e9de
TG		 13518 /* Skip any input that hasn't attribute section.
13519 This enables to link object files without attribute section with
13520 any others. */
13521 if (bfd_get_section_by_name (ibfd, sec_name) == NULL)
13522 return TRUE;
13523
104d59d1 13524 if (!elf_known_obj_attributes_proc (obfd)[0].i)
ee065d83
PB		 13525 {
13526 /* This is the first object. Copy the attributes. */
104d59d1 13527 _bfd_elf_copy_obj_attributes (ibfd, obfd);
004ae526 13528
cd21e546
MGD		 13529 out_attr = elf_known_obj_attributes_proc (obfd);
13530
004ae526
PB		 13531 /* Use the Tag_null value to indicate the attributes have been
13532 initialized. */
cd21e546 13533 out_attr[0].i = 1;
004ae526 13534
cd21e546
MGD		 13535 /* We do not output objects with Tag_MPextension_use_legacy - we move
13536 the attribute's value to Tag_MPextension_use. */
13537 if (out_attr[Tag_MPextension_use_legacy].i != 0)
13538 {
13539 if (out_attr[Tag_MPextension_use].i != 0
13540 && out_attr[Tag_MPextension_use_legacy].i
99059e56 13541 != out_attr[Tag_MPextension_use].i)
cd21e546
MGD		 13542 {
13543 _bfd_error_handler
13544 (_("Error: %B has both the current and legacy "
13545 "Tag_MPextension_use attributes"), ibfd);
13546 result = FALSE;
13547 }
13548
13549 out_attr[Tag_MPextension_use] =
13550 out_attr[Tag_MPextension_use_legacy];
13551 out_attr[Tag_MPextension_use_legacy].type = 0;
13552 out_attr[Tag_MPextension_use_legacy].i = 0;
13553 }
13554
13555 return result;
ee065d83
PB		 13556 }
13557
104d59d1
JM		 13558 in_attr = elf_known_obj_attributes_proc (ibfd);
13559 out_attr = elf_known_obj_attributes_proc (obfd);
ee065d83
PB		 13560 /* This needs to happen before Tag_ABI_FP_number_model is merged. */
13561 if (in_attr[Tag_ABI_VFP_args].i != out_attr[Tag_ABI_VFP_args].i)
13562 {
5c294fee
TG		 13563 /* Ignore mismatches if the object doesn't use floating point or is
13564 floating point ABI independent. */
13565 if (out_attr[Tag_ABI_FP_number_model].i == AEABI_FP_number_model_none
13566 || (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
13567 && out_attr[Tag_ABI_VFP_args].i == AEABI_VFP_args_compatible))
ee065d83 13568 out_attr[Tag_ABI_VFP_args].i = in_attr[Tag_ABI_VFP_args].i;
5c294fee
TG		 13569 else if (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
13570 && in_attr[Tag_ABI_VFP_args].i != AEABI_VFP_args_compatible)
ee065d83
PB		 13571 {
13572 _bfd_error_handler
3895f852 13573 (_("error: %B uses VFP register arguments, %B does not"),
deddc40b
NS		 13574 in_attr[Tag_ABI_VFP_args].i ? ibfd : obfd,
13575 in_attr[Tag_ABI_VFP_args].i ? obfd : ibfd);
91e22acd 13576 result = FALSE;
ee065d83
PB		 13577 }
13578 }
13579
3de4a297 13580 for (i = LEAST_KNOWN_OBJ_ATTRIBUTE; i < NUM_KNOWN_OBJ_ATTRIBUTES; i++)
ee065d83
PB		 13581 {
13582 /* Merge this attribute with existing attributes. */
13583 switch (i)
13584 {
13585 case Tag_CPU_raw_name:
13586 case Tag_CPU_name:
6a631e86 13587 /* These are merged after Tag_CPU_arch. */
ee065d83
PB		 13588 break;
13589
13590 case Tag_ABI_optimization_goals:
13591 case Tag_ABI_FP_optimization_goals:
13592 /* Use the first value seen. */
13593 break;
13594
13595 case Tag_CPU_arch:
91e22acd
AS		 13596 {
13597 int secondary_compat = -1, secondary_compat_out = -1;
13598 unsigned int saved_out_attr = out_attr[i].i;
70e99720
TG		 13599 int arch_attr;
13600 static const char *name_table[] =
13601 {
91e22acd
AS		 13602 /* These aren't real CPU names, but we can't guess
13603 that from the architecture version alone. */
13604 "Pre v4",
13605 "ARM v4",
13606 "ARM v4T",
13607 "ARM v5T",
13608 "ARM v5TE",
13609 "ARM v5TEJ",
13610 "ARM v6",
13611 "ARM v6KZ",
13612 "ARM v6T2",
13613 "ARM v6K",
13614 "ARM v7",
13615 "ARM v6-M",
bca38921 13616 "ARM v6S-M",
2fd158eb
TP		 13617 "ARM v8",
13618 "",
13619 "ARM v8-M.baseline",
13620 "ARM v8-M.mainline",
91e22acd
AS		 13621 };
13622
13623 /* Merge Tag_CPU_arch and Tag_also_compatible_with. */
13624 secondary_compat = get_secondary_compatible_arch (ibfd);
13625 secondary_compat_out = get_secondary_compatible_arch (obfd);
70e99720
TG		 13626 arch_attr = tag_cpu_arch_combine (ibfd, out_attr[i].i,
13627 &secondary_compat_out,
13628 in_attr[i].i,
13629 secondary_compat);
13630
13631 /* Return with error if failed to merge. */
13632 if (arch_attr == -1)
13633 return FALSE;
13634
13635 out_attr[i].i = arch_attr;
13636
91e22acd
AS		 13637 set_secondary_compatible_arch (obfd, secondary_compat_out);
13638
13639 /* Merge Tag_CPU_name and Tag_CPU_raw_name. */
13640 if (out_attr[i].i == saved_out_attr)
13641 ; /* Leave the names alone. */
13642 else if (out_attr[i].i == in_attr[i].i)
13643 {
13644 /* The output architecture has been changed to match the
13645 input architecture. Use the input names. */
13646 out_attr[Tag_CPU_name].s = in_attr[Tag_CPU_name].s
13647 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_name].s)
13648 : NULL;
13649 out_attr[Tag_CPU_raw_name].s = in_attr[Tag_CPU_raw_name].s
13650 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_raw_name].s)
13651 : NULL;
13652 }
13653 else
13654 {
13655 out_attr[Tag_CPU_name].s = NULL;
13656 out_attr[Tag_CPU_raw_name].s = NULL;
13657 }
13658
13659 /* If we still don't have a value for Tag_CPU_name,
13660 make one up now. Tag_CPU_raw_name remains blank. */
13661 if (out_attr[Tag_CPU_name].s == NULL
13662 && out_attr[i].i < ARRAY_SIZE (name_table))
13663 out_attr[Tag_CPU_name].s =
13664 _bfd_elf_attr_strdup (obfd, name_table[out_attr[i].i]);
13665 }
13666 break;
13667
ee065d83
PB		 13668 case Tag_ARM_ISA_use:
13669 case Tag_THUMB_ISA_use:
ee065d83 13670 case Tag_WMMX_arch:
91e22acd
AS		 13671 case Tag_Advanced_SIMD_arch:
13672 /* ??? Do Advanced_SIMD (NEON) and WMMX conflict? */
ee065d83 13673 case Tag_ABI_FP_rounding:
ee065d83
PB		 13674 case Tag_ABI_FP_exceptions:
13675 case Tag_ABI_FP_user_exceptions:
13676 case Tag_ABI_FP_number_model:
75375b3e 13677 case Tag_FP_HP_extension:
91e22acd
AS		 13678 case Tag_CPU_unaligned_access:
13679 case Tag_T2EE_use:
91e22acd 13680 case Tag_MPextension_use:
ee065d83
PB		 13681 /* Use the largest value specified. */
13682 if (in_attr[i].i > out_attr[i].i)
13683 out_attr[i].i = in_attr[i].i;
13684 break;
13685
75375b3e 13686 case Tag_ABI_align_preserved:
91e22acd
AS		 13687 case Tag_ABI_PCS_RO_data:
13688 /* Use the smallest value specified. */
13689 if (in_attr[i].i < out_attr[i].i)
13690 out_attr[i].i = in_attr[i].i;
13691 break;
13692
75375b3e 13693 case Tag_ABI_align_needed:
91e22acd 13694 if ((in_attr[i].i > 0 || out_attr[i].i > 0)
75375b3e
MGD		 13695 && (in_attr[Tag_ABI_align_preserved].i == 0
13696 || out_attr[Tag_ABI_align_preserved].i == 0))
ee065d83 13697 {
91e22acd
AS		 13698 /* This error message should be enabled once all non-conformant
13699 binaries in the toolchain have had the attributes set
13700 properly.
ee065d83 13701 _bfd_error_handler
3895f852 13702 (_("error: %B: 8-byte data alignment conflicts with %B"),
91e22acd
AS		 13703 obfd, ibfd);
13704 result = FALSE; */
ee065d83 13705 }
91e22acd
AS		 13706 /* Fall through. */
13707 case Tag_ABI_FP_denormal:
13708 case Tag_ABI_PCS_GOT_use:
13709 /* Use the "greatest" from the sequence 0, 2, 1, or the largest
13710 value if greater than 2 (for future-proofing). */
13711 if ((in_attr[i].i > 2 && in_attr[i].i > out_attr[i].i)
13712 || (in_attr[i].i <= 2 && out_attr[i].i <= 2
13713 && order_021[in_attr[i].i] > order_021[out_attr[i].i]))
ee065d83
PB		 13714 out_attr[i].i = in_attr[i].i;
13715 break;
91e22acd 13716
75375b3e
MGD		 13717 case Tag_Virtualization_use:
13718 /* The virtualization tag effectively stores two bits of
13719 information: the intended use of TrustZone (in bit 0), and the
13720 intended use of Virtualization (in bit 1). */
13721 if (out_attr[i].i == 0)
13722 out_attr[i].i = in_attr[i].i;
13723 else if (in_attr[i].i != 0
13724 && in_attr[i].i != out_attr[i].i)
13725 {
13726 if (in_attr[i].i <= 3 && out_attr[i].i <= 3)
13727 out_attr[i].i = 3;
13728 else
13729 {
13730 _bfd_error_handler
13731 (_("error: %B: unable to merge virtualization attributes "
13732 "with %B"),
13733 obfd, ibfd);
13734 result = FALSE;
13735 }
13736 }
13737 break;
91e22acd
AS		 13738
13739 case Tag_CPU_arch_profile:
13740 if (out_attr[i].i != in_attr[i].i)
13741 {
13742 /* 0 will merge with anything.
13743 'A' and 'S' merge to 'A'.
13744 'R' and 'S' merge to 'R'.
99059e56 13745 'M' and 'A|R|S' is an error. */
91e22acd
AS		 13746 if (out_attr[i].i == 0
13747 || (out_attr[i].i == 'S'
13748 && (in_attr[i].i == 'A' || in_attr[i].i == 'R')))
13749 out_attr[i].i = in_attr[i].i;
13750 else if (in_attr[i].i == 0
13751 || (in_attr[i].i == 'S'
13752 && (out_attr[i].i == 'A' || out_attr[i].i == 'R')))
6a631e86 13753 ; /* Do nothing. */
91e22acd
AS		 13754 else
13755 {
13756 _bfd_error_handler
3895f852 13757 (_("error: %B: Conflicting architecture profiles %c/%c"),
91e22acd
AS		 13758 ibfd,
13759 in_attr[i].i ? in_attr[i].i : '0',
13760 out_attr[i].i ? out_attr[i].i : '0');
13761 result = FALSE;
13762 }
13763 }
13764 break;
15afaa63
TP		 13765
13766 case Tag_DSP_extension:
13767 /* No need to change output value if any of:
13768 - pre (<=) ARMv5T input architecture (do not have DSP)
13769 - M input profile not ARMv7E-M and do not have DSP. */
13770 if (in_attr[Tag_CPU_arch].i <= 3
13771 || (in_attr[Tag_CPU_arch_profile].i == 'M'
13772 && in_attr[Tag_CPU_arch].i != 13
13773 && in_attr[i].i == 0))
13774 ; /* Do nothing. */
13775 /* Output value should be 0 if DSP part of architecture, ie.
13776 - post (>=) ARMv5te architecture output
13777 - A, R or S profile output or ARMv7E-M output architecture. */
13778 else if (out_attr[Tag_CPU_arch].i >= 4
13779 && (out_attr[Tag_CPU_arch_profile].i == 'A'
13780 || out_attr[Tag_CPU_arch_profile].i == 'R'
13781 || out_attr[Tag_CPU_arch_profile].i == 'S'
13782 || out_attr[Tag_CPU_arch].i == 13))
13783 out_attr[i].i = 0;
13784 /* Otherwise, DSP instructions are added and not part of output
13785 architecture. */
13786 else
13787 out_attr[i].i = 1;
13788 break;
13789
75375b3e 13790 case Tag_FP_arch:
62f3b8c8 13791 {
4547cb56
NC		 13792 /* Tag_ABI_HardFP_use is handled along with Tag_FP_arch since
13793 the meaning of Tag_ABI_HardFP_use depends on Tag_FP_arch
13794 when it's 0. It might mean absence of FP hardware if
99654aaf 13795 Tag_FP_arch is zero. */
4547cb56 13796
a715796b 13797#define VFP_VERSION_COUNT 9
62f3b8c8
PB		 13798 static const struct
13799 {
13800 int ver;
13801 int regs;
bca38921 13802 } vfp_versions[VFP_VERSION_COUNT] =
62f3b8c8
PB		 13803 {
13804 {0, 0},
13805 {1, 16},
13806 {2, 16},
13807 {3, 32},
13808 {3, 16},
13809 {4, 32},
bca38921 13810 {4, 16},
a715796b
TG		 13811 {8, 32},
13812 {8, 16}
62f3b8c8
PB		 13813 };
13814 int ver;
13815 int regs;
13816 int newval;
13817
4547cb56
NC		 13818 /* If the output has no requirement about FP hardware,
13819 follow the requirement of the input. */
13820 if (out_attr[i].i == 0)
13821 {
13822 BFD_ASSERT (out_attr[Tag_ABI_HardFP_use].i == 0);
13823 out_attr[i].i = in_attr[i].i;
13824 out_attr[Tag_ABI_HardFP_use].i
13825 = in_attr[Tag_ABI_HardFP_use].i;
13826 break;
13827 }
13828 /* If the input has no requirement about FP hardware, do
13829 nothing. */
13830 else if (in_attr[i].i == 0)
13831 {
13832 BFD_ASSERT (in_attr[Tag_ABI_HardFP_use].i == 0);
13833 break;
13834 }
13835
13836 /* Both the input and the output have nonzero Tag_FP_arch.
99654aaf 13837 So Tag_ABI_HardFP_use is implied by Tag_FP_arch when it's zero. */
4547cb56
NC		 13838
13839 /* If both the input and the output have zero Tag_ABI_HardFP_use,
13840 do nothing. */
13841 if (in_attr[Tag_ABI_HardFP_use].i == 0
13842 && out_attr[Tag_ABI_HardFP_use].i == 0)
13843 ;
13844 /* If the input and the output have different Tag_ABI_HardFP_use,
99654aaf 13845 the combination of them is 0 (implied by Tag_FP_arch). */
4547cb56
NC		 13846 else if (in_attr[Tag_ABI_HardFP_use].i
13847 != out_attr[Tag_ABI_HardFP_use].i)
99654aaf 13848 out_attr[Tag_ABI_HardFP_use].i = 0;
4547cb56
NC		 13849
13850 /* Now we can handle Tag_FP_arch. */
13851
bca38921
MGD		 13852 /* Values of VFP_VERSION_COUNT or more aren't defined, so just
13853 pick the biggest. */
13854 if (in_attr[i].i >= VFP_VERSION_COUNT
13855 && in_attr[i].i > out_attr[i].i)
62f3b8c8
PB		 13856 {
13857 out_attr[i] = in_attr[i];
13858 break;
13859 }
13860 /* The output uses the superset of input features
13861 (ISA version) and registers. */
13862 ver = vfp_versions[in_attr[i].i].ver;
13863 if (ver < vfp_versions[out_attr[i].i].ver)
13864 ver = vfp_versions[out_attr[i].i].ver;
13865 regs = vfp_versions[in_attr[i].i].regs;
13866 if (regs < vfp_versions[out_attr[i].i].regs)
13867 regs = vfp_versions[out_attr[i].i].regs;
13868 /* This assumes all possible supersets are also a valid
99059e56 13869 options. */
bca38921 13870 for (newval = VFP_VERSION_COUNT - 1; newval > 0; newval--)
62f3b8c8
PB		 13871 {
13872 if (regs == vfp_versions[newval].regs
13873 && ver == vfp_versions[newval].ver)
13874 break;
13875 }
13876 out_attr[i].i = newval;
13877 }
b1cc4aeb 13878 break;
ee065d83
PB		 13879 case Tag_PCS_config:
13880 if (out_attr[i].i == 0)
13881 out_attr[i].i = in_attr[i].i;
b6009aca 13882 else if (in_attr[i].i != 0 && out_attr[i].i != in_attr[i].i)
ee065d83
PB		 13883 {
13884 /* It's sometimes ok to mix different configs, so this is only
99059e56 13885 a warning. */
ee065d83
PB		 13886 _bfd_error_handler
13887 (_("Warning: %B: Conflicting platform configuration"), ibfd);
13888 }
13889 break;
13890 case Tag_ABI_PCS_R9_use:
004ae526
PB		 13891 if (in_attr[i].i != out_attr[i].i
13892 && out_attr[i].i != AEABI_R9_unused
ee065d83
PB		 13893 && in_attr[i].i != AEABI_R9_unused)
13894 {
13895 _bfd_error_handler
3895f852 13896 (_("error: %B: Conflicting use of R9"), ibfd);
91e22acd 13897 result = FALSE;
ee065d83
PB		 13898 }
13899 if (out_attr[i].i == AEABI_R9_unused)
13900 out_attr[i].i = in_attr[i].i;
13901 break;
13902 case Tag_ABI_PCS_RW_data:
13903 if (in_attr[i].i == AEABI_PCS_RW_data_SBrel
13904 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_SB
13905 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_unused)
13906 {
13907 _bfd_error_handler
3895f852 13908 (_("error: %B: SB relative addressing conflicts with use of R9"),
ee065d83 13909 ibfd);
91e22acd 13910 result = FALSE;
ee065d83
PB		 13911 }
13912 /* Use the smallest value specified. */
13913 if (in_attr[i].i < out_attr[i].i)
13914 out_attr[i].i = in_attr[i].i;
13915 break;
ee065d83 13916 case Tag_ABI_PCS_wchar_t:
a9dc9481
JM		 13917 if (out_attr[i].i && in_attr[i].i && out_attr[i].i != in_attr[i].i
13918 && !elf_arm_tdata (obfd)->no_wchar_size_warning)
ee065d83
PB		 13919 {
13920 _bfd_error_handler
a9dc9481
JM		 13921 (_("warning: %B uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"),
13922 ibfd, in_attr[i].i, out_attr[i].i);
ee065d83 13923 }
a9dc9481 13924 else if (in_attr[i].i && !out_attr[i].i)
ee065d83
PB		 13925 out_attr[i].i = in_attr[i].i;
13926 break;
ee065d83
PB		 13927 case Tag_ABI_enum_size:
13928 if (in_attr[i].i != AEABI_enum_unused)
13929 {
13930 if (out_attr[i].i == AEABI_enum_unused
13931 || out_attr[i].i == AEABI_enum_forced_wide)
13932 {
13933 /* The existing object is compatible with anything.
13934 Use whatever requirements the new object has. */
13935 out_attr[i].i = in_attr[i].i;
13936 }
13937 else if (in_attr[i].i != AEABI_enum_forced_wide
bf21ed78 13938 && out_attr[i].i != in_attr[i].i
0ffa91dd 13939 && !elf_arm_tdata (obfd)->no_enum_size_warning)
ee065d83 13940 {
91e22acd 13941 static const char *aeabi_enum_names[] =
bf21ed78 13942 { "", "variable-size", "32-bit", "" };
91e22acd
AS		 13943 const char *in_name =
13944 in_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
13945 ? aeabi_enum_names[in_attr[i].i]
13946 : "<unknown>";
13947 const char *out_name =
13948 out_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
13949 ? aeabi_enum_names[out_attr[i].i]
13950 : "<unknown>";
ee065d83 13951 _bfd_error_handler
bf21ed78 13952 (_("warning: %B uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"),
91e22acd 13953 ibfd, in_name, out_name);
ee065d83
PB		 13954 }
13955 }
13956 break;
13957 case Tag_ABI_VFP_args:
13958 /* Aready done. */
13959 break;
13960 case Tag_ABI_WMMX_args:
13961 if (in_attr[i].i != out_attr[i].i)
13962 {
13963 _bfd_error_handler
3895f852 13964 (_("error: %B uses iWMMXt register arguments, %B does not"),
ee065d83 13965 ibfd, obfd);
91e22acd 13966 result = FALSE;
ee065d83
PB		 13967 }
13968 break;
7b86a9fa
AS		 13969 case Tag_compatibility:
13970 /* Merged in target-independent code. */
13971 break;
91e22acd 13972 case Tag_ABI_HardFP_use:
4547cb56 13973 /* This is handled along with Tag_FP_arch. */
91e22acd
AS		 13974 break;
13975 case Tag_ABI_FP_16bit_format:
13976 if (in_attr[i].i != 0 && out_attr[i].i != 0)
13977 {
13978 if (in_attr[i].i != out_attr[i].i)
13979 {
13980 _bfd_error_handler
3895f852 13981 (_("error: fp16 format mismatch between %B and %B"),
91e22acd
AS		 13982 ibfd, obfd);
13983 result = FALSE;
13984 }
13985 }
13986 if (in_attr[i].i != 0)
13987 out_attr[i].i = in_attr[i].i;
13988 break;
7b86a9fa 13989
cd21e546 13990 case Tag_DIV_use:
ac56ee8f
MGD		 13991 /* A value of zero on input means that the divide instruction may
13992 be used if available in the base architecture as specified via
13993 Tag_CPU_arch and Tag_CPU_arch_profile. A value of 1 means that
13994 the user did not want divide instructions. A value of 2
13995 explicitly means that divide instructions were allowed in ARM
13996 and Thumb state. */
13997 if (in_attr[i].i == out_attr[i].i)
13998 /* Do nothing. */ ;
13999 else if (elf32_arm_attributes_forbid_div (in_attr)
14000 && !elf32_arm_attributes_accept_div (out_attr))
14001 out_attr[i].i = 1;
14002 else if (elf32_arm_attributes_forbid_div (out_attr)
14003 && elf32_arm_attributes_accept_div (in_attr))
14004 out_attr[i].i = in_attr[i].i;
14005 else if (in_attr[i].i == 2)
14006 out_attr[i].i = in_attr[i].i;
cd21e546
MGD		 14007 break;
14008
14009 case Tag_MPextension_use_legacy:
14010 /* We don't output objects with Tag_MPextension_use_legacy - we
14011 move the value to Tag_MPextension_use. */
14012 if (in_attr[i].i != 0 && in_attr[Tag_MPextension_use].i != 0)
14013 {
14014 if (in_attr[Tag_MPextension_use].i != in_attr[i].i)
14015 {
14016 _bfd_error_handler
14017 (_("%B has has both the current and legacy "
b38cadfb 14018 "Tag_MPextension_use attributes"),
cd21e546
MGD		 14019 ibfd);
14020 result = FALSE;
14021 }
14022 }
14023
14024 if (in_attr[i].i > out_attr[Tag_MPextension_use].i)
14025 out_attr[Tag_MPextension_use] = in_attr[i];
14026
14027 break;
14028
91e22acd 14029 case Tag_nodefaults:
2d0bb761
AS		 14030 /* This tag is set if it exists, but the value is unused (and is
14031 typically zero). We don't actually need to do anything here -
14032 the merge happens automatically when the type flags are merged
14033 below. */
91e22acd
AS		 14034 break;
14035 case Tag_also_compatible_with:
14036 /* Already done in Tag_CPU_arch. */
14037 break;
14038 case Tag_conformance:
14039 /* Keep the attribute if it matches. Throw it away otherwise.
14040 No attribute means no claim to conform. */
14041 if (!in_attr[i].s || !out_attr[i].s
14042 || strcmp (in_attr[i].s, out_attr[i].s) != 0)
14043 out_attr[i].s = NULL;
14044 break;
3cfad14c 14045
91e22acd 14046 default:
e8b36cd1
JM		 14047 result
14048 = result && _bfd_elf_merge_unknown_attribute_low (ibfd, obfd, i);
91e22acd
AS		 14049 }
14050
14051 /* If out_attr was copied from in_attr then it won't have a type yet. */
14052 if (in_attr[i].type && !out_attr[i].type)
14053 out_attr[i].type = in_attr[i].type;
ee065d83
PB		 14054 }
14055
104d59d1 14056 /* Merge Tag_compatibility attributes and any common GNU ones. */
50e03d47 14057 if (!_bfd_elf_merge_object_attributes (ibfd, info))
5488d830 14058 return FALSE;
ee065d83 14059
104d59d1 14060 /* Check for any attributes not known on ARM. */
e8b36cd1 14061 result &= _bfd_elf_merge_unknown_attribute_list (ibfd, obfd);
91e22acd 14062
91e22acd 14063 return result;
252b5132
RH		 14064}
14065
3a4a14e9
PB		 14066
14067/* Return TRUE if the two EABI versions are incompatible. */
14068
14069static bfd_boolean
14070elf32_arm_versions_compatible (unsigned iver, unsigned over)
14071{
14072 /* v4 and v5 are the same spec before and after it was released,
14073 so allow mixing them. */
14074 if ((iver == EF_ARM_EABI_VER4 && over == EF_ARM_EABI_VER5)
14075 || (iver == EF_ARM_EABI_VER5 && over == EF_ARM_EABI_VER4))
14076 return TRUE;
14077
14078 return (iver == over);
14079}
14080
252b5132
RH		 14081/* Merge backend specific data from an object file to the output
14082 object file when linking. */
9b485d32 14083
b34976b6 14084static bfd_boolean
50e03d47 14085elf32_arm_merge_private_bfd_data (bfd *, struct bfd_link_info *);
252b5132 14086
9b485d32
NC		 14087/* Display the flags field. */
14088
b34976b6 14089static bfd_boolean
57e8b36a 14090elf32_arm_print_private_bfd_data (bfd *abfd, void * ptr)
252b5132 14091{
fc830a83
NC		 14092 FILE * file = (FILE *) ptr;
14093 unsigned long flags;
252b5132
RH		 14094
14095 BFD_ASSERT (abfd != NULL && ptr != NULL);
14096
14097 /* Print normal ELF private data. */
14098 _bfd_elf_print_private_bfd_data (abfd, ptr);
14099
fc830a83 14100 flags = elf_elfheader (abfd)->e_flags;
9b485d32
NC		 14101 /* Ignore init flag - it may not be set, despite the flags field
14102 containing valid data. */
252b5132 14103
9b485d32 14104 fprintf (file, _("private flags = %lx:"), elf_elfheader (abfd)->e_flags);
252b5132 14105
fc830a83
NC		 14106 switch (EF_ARM_EABI_VERSION (flags))
14107 {
14108 case EF_ARM_EABI_UNKNOWN:
4cc11e76 14109 /* The following flag bits are GNU extensions and not part of the
fc830a83
NC		 14110 official ARM ELF extended ABI. Hence they are only decoded if
14111 the EABI version is not set. */
fd2ec330 14112 if (flags & EF_ARM_INTERWORK)
9b485d32 14113 fprintf (file, _(" [interworking enabled]"));
9a5aca8c 14114
fd2ec330 14115 if (flags & EF_ARM_APCS_26)
6c571f00 14116 fprintf (file, " [APCS-26]");
fc830a83 14117 else
6c571f00 14118 fprintf (file, " [APCS-32]");
9a5aca8c 14119
96a846ea
RE		 14120 if (flags & EF_ARM_VFP_FLOAT)
14121 fprintf (file, _(" [VFP float format]"));
fde78edd
NC		 14122 else if (flags & EF_ARM_MAVERICK_FLOAT)
14123 fprintf (file, _(" [Maverick float format]"));
96a846ea
RE		 14124 else
14125 fprintf (file, _(" [FPA float format]"));
14126
fd2ec330 14127 if (flags & EF_ARM_APCS_FLOAT)
9b485d32 14128 fprintf (file, _(" [floats passed in float registers]"));
9a5aca8c 14129
fd2ec330 14130 if (flags & EF_ARM_PIC)
9b485d32 14131 fprintf (file, _(" [position independent]"));
fc830a83 14132
fd2ec330 14133 if (flags & EF_ARM_NEW_ABI)
9b485d32 14134 fprintf (file, _(" [new ABI]"));
9a5aca8c 14135
fd2ec330 14136 if (flags & EF_ARM_OLD_ABI)
9b485d32 14137 fprintf (file, _(" [old ABI]"));
9a5aca8c 14138
fd2ec330 14139 if (flags & EF_ARM_SOFT_FLOAT)
9b485d32 14140 fprintf (file, _(" [software FP]"));
9a5aca8c 14141
96a846ea
RE		 14142 flags &= ~(EF_ARM_INTERWORK | EF_ARM_APCS_26 | EF_ARM_APCS_FLOAT
14143 | EF_ARM_PIC | EF_ARM_NEW_ABI | EF_ARM_OLD_ABI
fde78edd
NC		 14144 | EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT
14145 | EF_ARM_MAVERICK_FLOAT);
fc830a83 14146 break;
9a5aca8c 14147
fc830a83 14148 case EF_ARM_EABI_VER1:
9b485d32 14149 fprintf (file, _(" [Version1 EABI]"));
9a5aca8c 14150
fc830a83 14151 if (flags & EF_ARM_SYMSARESORTED)
9b485d32 14152 fprintf (file, _(" [sorted symbol table]"));
fc830a83 14153 else
9b485d32 14154 fprintf (file, _(" [unsorted symbol table]"));
9a5aca8c 14155
fc830a83
NC		 14156 flags &= ~ EF_ARM_SYMSARESORTED;
14157 break;
9a5aca8c 14158
fd2ec330
PB		 14159 case EF_ARM_EABI_VER2:
14160 fprintf (file, _(" [Version2 EABI]"));
14161
14162 if (flags & EF_ARM_SYMSARESORTED)
14163 fprintf (file, _(" [sorted symbol table]"));
14164 else
14165 fprintf (file, _(" [unsorted symbol table]"));
14166
14167 if (flags & EF_ARM_DYNSYMSUSESEGIDX)
14168 fprintf (file, _(" [dynamic symbols use segment index]"));
14169
14170 if (flags & EF_ARM_MAPSYMSFIRST)
14171 fprintf (file, _(" [mapping symbols precede others]"));
14172
99e4ae17 14173 flags &= ~(EF_ARM_SYMSARESORTED | EF_ARM_DYNSYMSUSESEGIDX
fd2ec330
PB		 14174 | EF_ARM_MAPSYMSFIRST);
14175 break;
14176
d507cf36
PB		 14177 case EF_ARM_EABI_VER3:
14178 fprintf (file, _(" [Version3 EABI]"));
8cb51566
PB		 14179 break;
14180
14181 case EF_ARM_EABI_VER4:
14182 fprintf (file, _(" [Version4 EABI]"));
3a4a14e9 14183 goto eabi;
d507cf36 14184
3a4a14e9
PB		 14185 case EF_ARM_EABI_VER5:
14186 fprintf (file, _(" [Version5 EABI]"));
3bfcb652
NC		 14187
14188 if (flags & EF_ARM_ABI_FLOAT_SOFT)
14189 fprintf (file, _(" [soft-float ABI]"));
14190
14191 if (flags & EF_ARM_ABI_FLOAT_HARD)
14192 fprintf (file, _(" [hard-float ABI]"));
14193
14194 flags &= ~(EF_ARM_ABI_FLOAT_SOFT | EF_ARM_ABI_FLOAT_HARD);
14195
3a4a14e9 14196 eabi:
d507cf36
PB		 14197 if (flags & EF_ARM_BE8)
14198 fprintf (file, _(" [BE8]"));
14199
14200 if (flags & EF_ARM_LE8)
14201 fprintf (file, _(" [LE8]"));
14202
14203 flags &= ~(EF_ARM_LE8 | EF_ARM_BE8);
14204 break;
14205
fc830a83 14206 default:
9b485d32 14207 fprintf (file, _(" <EABI version unrecognised>"));
fc830a83
NC		 14208 break;
14209 }
252b5132 14210
fc830a83 14211 flags &= ~ EF_ARM_EABIMASK;
252b5132 14212
fc830a83 14213 if (flags & EF_ARM_RELEXEC)
9b485d32 14214 fprintf (file, _(" [relocatable executable]"));
252b5132 14215
a5721edd 14216 flags &= ~EF_ARM_RELEXEC;
fc830a83
NC		 14217
14218 if (flags)
9b485d32 14219 fprintf (file, _("<Unrecognised flag bits set>"));
9a5aca8c 14220
252b5132
RH		 14221 fputc ('\n', file);
14222
b34976b6 14223 return TRUE;
252b5132
RH		 14224}
14225
14226static int
57e8b36a 14227elf32_arm_get_symbol_type (Elf_Internal_Sym * elf_sym, int type)
252b5132 14228{
2f0ca46a
NC		 14229 switch (ELF_ST_TYPE (elf_sym->st_info))
14230 {
14231 case STT_ARM_TFUNC:
14232 return ELF_ST_TYPE (elf_sym->st_info);
ce855c42 14233
2f0ca46a
NC		 14234 case STT_ARM_16BIT:
14235 /* If the symbol is not an object, return the STT_ARM_16BIT flag.
14236 This allows us to distinguish between data used by Thumb instructions
14237 and non-data (which is probably code) inside Thumb regions of an
14238 executable. */
1a0eb693 14239 if (type != STT_OBJECT && type != STT_TLS)
2f0ca46a
NC		 14240 return ELF_ST_TYPE (elf_sym->st_info);
14241 break;
9a5aca8c 14242
ce855c42
NC		 14243 default:
14244 break;
2f0ca46a
NC		 14245 }
14246
14247 return type;
252b5132 14248}
f21f3fe0 14249
252b5132 14250static asection *
07adf181
AM		 14251elf32_arm_gc_mark_hook (asection *sec,
14252 struct bfd_link_info *info,
14253 Elf_Internal_Rela *rel,
14254 struct elf_link_hash_entry *h,
14255 Elf_Internal_Sym *sym)
252b5132
RH		 14256{
14257 if (h != NULL)
07adf181 14258 switch (ELF32_R_TYPE (rel->r_info))
252b5132
RH		 14259 {
14260 case R_ARM_GNU_VTINHERIT:
14261 case R_ARM_GNU_VTENTRY:
07adf181
AM		 14262 return NULL;
14263 }
9ad5cbcf 14264
07adf181 14265 return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym);
252b5132
RH		 14266}
14267
780a67af
NC		 14268/* Update the got entry reference counts for the section being removed. */
14269
b34976b6 14270static bfd_boolean
ba93b8ac
DJ		 14271elf32_arm_gc_sweep_hook (bfd * abfd,
14272 struct bfd_link_info * info,
14273 asection * sec,
14274 const Elf_Internal_Rela * relocs)
252b5132 14275{
5e681ec4
PB		 14276 Elf_Internal_Shdr *symtab_hdr;
14277 struct elf_link_hash_entry **sym_hashes;
14278 bfd_signed_vma *local_got_refcounts;
14279 const Elf_Internal_Rela *rel, *relend;
eb043451
PB		 14280 struct elf32_arm_link_hash_table * globals;
14281
0e1862bb 14282 if (bfd_link_relocatable (info))
7dda2462
TG		 14283 return TRUE;
14284
eb043451 14285 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14286 if (globals == NULL)
14287 return FALSE;
5e681ec4
PB		 14288
14289 elf_section_data (sec)->local_dynrel = NULL;
14290
0ffa91dd 14291 symtab_hdr = & elf_symtab_hdr (abfd);
5e681ec4
PB		 14292 sym_hashes = elf_sym_hashes (abfd);
14293 local_got_refcounts = elf_local_got_refcounts (abfd);
14294
906e58ca 14295 check_use_blx (globals);
bd97cb95 14296
5e681ec4
PB		 14297 relend = relocs + sec->reloc_count;
14298 for (rel = relocs; rel < relend; rel++)
eb043451 14299 {
3eb128b2
AM		 14300 unsigned long r_symndx;
14301 struct elf_link_hash_entry *h = NULL;
f6e32f6d 14302 struct elf32_arm_link_hash_entry *eh;
eb043451 14303 int r_type;
34e77a92 14304 bfd_boolean call_reloc_p;
f6e32f6d
RS		 14305 bfd_boolean may_become_dynamic_p;
14306 bfd_boolean may_need_local_target_p;
34e77a92
RS		 14307 union gotplt_union *root_plt;
14308 struct arm_plt_info *arm_plt;
5e681ec4 14309
3eb128b2
AM		 14310 r_symndx = ELF32_R_SYM (rel->r_info);
14311 if (r_symndx >= symtab_hdr->sh_info)
14312 {
14313 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
14314 while (h->root.type == bfd_link_hash_indirect
14315 || h->root.type == bfd_link_hash_warning)
14316 h = (struct elf_link_hash_entry *) h->root.u.i.link;
14317 }
f6e32f6d
RS		 14318 eh = (struct elf32_arm_link_hash_entry *) h;
14319
34e77a92 14320 call_reloc_p = FALSE;
f6e32f6d
RS		 14321 may_become_dynamic_p = FALSE;
14322 may_need_local_target_p = FALSE;
3eb128b2 14323
eb043451 14324 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 14325 r_type = arm_real_reloc_type (globals, r_type);
eb043451
PB		 14326 switch (r_type)
14327 {
14328 case R_ARM_GOT32:
eb043451 14329 case R_ARM_GOT_PREL:
ba93b8ac
DJ		 14330 case R_ARM_TLS_GD32:
14331 case R_ARM_TLS_IE32:
3eb128b2 14332 if (h != NULL)
eb043451 14333 {
eb043451
PB		 14334 if (h->got.refcount > 0)
14335 h->got.refcount -= 1;
14336 }
14337 else if (local_got_refcounts != NULL)
14338 {
14339 if (local_got_refcounts[r_symndx] > 0)
14340 local_got_refcounts[r_symndx] -= 1;
14341 }
14342 break;
14343
ba93b8ac 14344 case R_ARM_TLS_LDM32:
4dfe6ac6 14345 globals->tls_ldm_got.refcount -= 1;
ba93b8ac
DJ		 14346 break;
14347
eb043451
PB		 14348 case R_ARM_PC24:
14349 case R_ARM_PLT32:
5b5bb741
PB		 14350 case R_ARM_CALL:
14351 case R_ARM_JUMP24:
eb043451 14352 case R_ARM_PREL31:
c19d1205 14353 case R_ARM_THM_CALL:
bd97cb95
DJ		 14354 case R_ARM_THM_JUMP24:
14355 case R_ARM_THM_JUMP19:
34e77a92 14356 call_reloc_p = TRUE;
f6e32f6d
RS		 14357 may_need_local_target_p = TRUE;
14358 break;
14359
14360 case R_ARM_ABS12:
14361 if (!globals->vxworks_p)
14362 {
14363 may_need_local_target_p = TRUE;
14364 break;
14365 }
14366 /* Fall through. */
14367 case R_ARM_ABS32:
14368 case R_ARM_ABS32_NOI:
14369 case R_ARM_REL32:
14370 case R_ARM_REL32_NOI:
b6895b4f
PB		 14371 case R_ARM_MOVW_ABS_NC:
14372 case R_ARM_MOVT_ABS:
14373 case R_ARM_MOVW_PREL_NC:
14374 case R_ARM_MOVT_PREL:
14375 case R_ARM_THM_MOVW_ABS_NC:
14376 case R_ARM_THM_MOVT_ABS:
14377 case R_ARM_THM_MOVW_PREL_NC:
14378 case R_ARM_THM_MOVT_PREL:
b7693d02 14379 /* Should the interworking branches be here also? */
0e1862bb 14380 if ((bfd_link_pic (info) || globals->root.is_relocatable_executable)
34e77a92
RS		 14381 && (sec->flags & SEC_ALLOC) != 0)
14382 {
14383 if (h == NULL
469a3493 14384 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 14385 {
14386 call_reloc_p = TRUE;
14387 may_need_local_target_p = TRUE;
14388 }
14389 else
14390 may_become_dynamic_p = TRUE;
14391 }
f6e32f6d
RS		 14392 else
14393 may_need_local_target_p = TRUE;
14394 break;
b7693d02 14395
f6e32f6d
RS		 14396 default:
14397 break;
14398 }
5e681ec4 14399
34e77a92 14400 if (may_need_local_target_p
4ba2ef8f
TP		 14401 && elf32_arm_get_plt_info (abfd, globals, eh, r_symndx, &root_plt,
14402 &arm_plt))
f6e32f6d 14403 {
27586251
HPN		 14404 /* If PLT refcount book-keeping is wrong and too low, we'll
14405 see a zero value (going to -1) for the root PLT reference
14406 count. */
14407 if (root_plt->refcount >= 0)
14408 {
14409 BFD_ASSERT (root_plt->refcount != 0);
14410 root_plt->refcount -= 1;
14411 }
14412 else
14413 /* A value of -1 means the symbol has become local, forced
14414 or seeing a hidden definition. Any other negative value
14415 is an error. */
14416 BFD_ASSERT (root_plt->refcount == -1);
34e77a92
RS		 14417
14418 if (!call_reloc_p)
14419 arm_plt->noncall_refcount--;
5e681ec4 14420
f6e32f6d 14421 if (r_type == R_ARM_THM_CALL)
34e77a92 14422 arm_plt->maybe_thumb_refcount--;
bd97cb95 14423
f6e32f6d
RS		 14424 if (r_type == R_ARM_THM_JUMP24
14425 || r_type == R_ARM_THM_JUMP19)
34e77a92 14426 arm_plt->thumb_refcount--;
f6e32f6d 14427 }
5e681ec4 14428
34e77a92 14429 if (may_become_dynamic_p)
f6e32f6d
RS		 14430 {
14431 struct elf_dyn_relocs **pp;
14432 struct elf_dyn_relocs *p;
5e681ec4 14433
34e77a92 14434 if (h != NULL)
9c489990 14435 pp = &(eh->dyn_relocs);
34e77a92
RS		 14436 else
14437 {
14438 Elf_Internal_Sym *isym;
14439
14440 isym = bfd_sym_from_r_symndx (&globals->sym_cache,
14441 abfd, r_symndx);
14442 if (isym == NULL)
14443 return FALSE;
14444 pp = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
14445 if (pp == NULL)
14446 return FALSE;
14447 }
9c489990 14448 for (; (p = *pp) != NULL; pp = &p->next)
f6e32f6d
RS		 14449 if (p->sec == sec)
14450 {
14451 /* Everything must go for SEC. */
14452 *pp = p->next;
14453 break;
14454 }
eb043451
PB		 14455 }
14456 }
5e681ec4 14457
b34976b6 14458 return TRUE;
252b5132
RH		 14459}
14460
780a67af
NC		 14461/* Look through the relocs for a section during the first phase. */
14462
b34976b6 14463static bfd_boolean
57e8b36a
NC		 14464elf32_arm_check_relocs (bfd *abfd, struct bfd_link_info *info,
14465 asection *sec, const Elf_Internal_Rela *relocs)
252b5132 14466{
b34976b6
AM		 14467 Elf_Internal_Shdr *symtab_hdr;
14468 struct elf_link_hash_entry **sym_hashes;
b34976b6
AM		 14469 const Elf_Internal_Rela *rel;
14470 const Elf_Internal_Rela *rel_end;
14471 bfd *dynobj;
5e681ec4 14472 asection *sreloc;
5e681ec4 14473 struct elf32_arm_link_hash_table *htab;
f6e32f6d
RS		 14474 bfd_boolean call_reloc_p;
14475 bfd_boolean may_become_dynamic_p;
14476 bfd_boolean may_need_local_target_p;
ce98a316 14477 unsigned long nsyms;
9a5aca8c 14478
0e1862bb 14479 if (bfd_link_relocatable (info))
b34976b6 14480 return TRUE;
9a5aca8c 14481
0ffa91dd
NC		 14482 BFD_ASSERT (is_arm_elf (abfd));
14483
5e681ec4 14484 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14485 if (htab == NULL)
14486 return FALSE;
14487
5e681ec4 14488 sreloc = NULL;
9a5aca8c 14489
67687978
PB		 14490 /* Create dynamic sections for relocatable executables so that we can
14491 copy relocations. */
14492 if (htab->root.is_relocatable_executable
14493 && ! htab->root.dynamic_sections_created)
14494 {
14495 if (! _bfd_elf_link_create_dynamic_sections (abfd, info))
14496 return FALSE;
14497 }
14498
cbc704f3
RS		 14499 if (htab->root.dynobj == NULL)
14500 htab->root.dynobj = abfd;
34e77a92
RS		 14501 if (!create_ifunc_sections (info))
14502 return FALSE;
cbc704f3
RS		 14503
14504 dynobj = htab->root.dynobj;
14505
0ffa91dd 14506 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 14507 sym_hashes = elf_sym_hashes (abfd);
ce98a316 14508 nsyms = NUM_SHDR_ENTRIES (symtab_hdr);
b38cadfb 14509
252b5132
RH		 14510 rel_end = relocs + sec->reloc_count;
14511 for (rel = relocs; rel < rel_end; rel++)
14512 {
34e77a92 14513 Elf_Internal_Sym *isym;
252b5132 14514 struct elf_link_hash_entry *h;
b7693d02 14515 struct elf32_arm_link_hash_entry *eh;
252b5132 14516 unsigned long r_symndx;
eb043451 14517 int r_type;
9a5aca8c 14518
252b5132 14519 r_symndx = ELF32_R_SYM (rel->r_info);
eb043451 14520 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 14521 r_type = arm_real_reloc_type (htab, r_type);
ba93b8ac 14522
ce98a316
NC		 14523 if (r_symndx >= nsyms
14524 /* PR 9934: It is possible to have relocations that do not
14525 refer to symbols, thus it is also possible to have an
14526 object file containing relocations but no symbol table. */
cf35638d 14527 && (r_symndx > STN_UNDEF || nsyms > 0))
ba93b8ac 14528 {
4eca0228
AM		 14529 _bfd_error_handler (_("%B: bad symbol index: %d"), abfd,
14530 r_symndx);
ba93b8ac
DJ		 14531 return FALSE;
14532 }
14533
34e77a92
RS		 14534 h = NULL;
14535 isym = NULL;
14536 if (nsyms > 0)
973a3492 14537 {
34e77a92
RS		 14538 if (r_symndx < symtab_hdr->sh_info)
14539 {
14540 /* A local symbol. */
14541 isym = bfd_sym_from_r_symndx (&htab->sym_cache,
14542 abfd, r_symndx);
14543 if (isym == NULL)
14544 return FALSE;
14545 }
14546 else
14547 {
14548 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
14549 while (h->root.type == bfd_link_hash_indirect
14550 || h->root.type == bfd_link_hash_warning)
14551 h = (struct elf_link_hash_entry *) h->root.u.i.link;
81fbe831
AM		 14552
14553 /* PR15323, ref flags aren't set for references in the
14554 same object. */
14555 h->root.non_ir_ref = 1;
34e77a92 14556 }
973a3492 14557 }
9a5aca8c 14558
b7693d02
DJ		 14559 eh = (struct elf32_arm_link_hash_entry *) h;
14560
f6e32f6d
RS		 14561 call_reloc_p = FALSE;
14562 may_become_dynamic_p = FALSE;
14563 may_need_local_target_p = FALSE;
14564
0855e32b
NS		 14565 /* Could be done earlier, if h were already available. */
14566 r_type = elf32_arm_tls_transition (info, r_type, h);
eb043451 14567 switch (r_type)
99059e56 14568 {
5e681ec4 14569 case R_ARM_GOT32:
eb043451 14570 case R_ARM_GOT_PREL:
ba93b8ac
DJ		 14571 case R_ARM_TLS_GD32:
14572 case R_ARM_TLS_IE32:
0855e32b
NS		 14573 case R_ARM_TLS_GOTDESC:
14574 case R_ARM_TLS_DESCSEQ:
14575 case R_ARM_THM_TLS_DESCSEQ:
14576 case R_ARM_TLS_CALL:
14577 case R_ARM_THM_TLS_CALL:
5e681ec4 14578 /* This symbol requires a global offset table entry. */
ba93b8ac
DJ		 14579 {
14580 int tls_type, old_tls_type;
5e681ec4 14581
ba93b8ac
DJ		 14582 switch (r_type)
14583 {
14584 case R_ARM_TLS_GD32: tls_type = GOT_TLS_GD; break;
b38cadfb 14585
ba93b8ac 14586 case R_ARM_TLS_IE32: tls_type = GOT_TLS_IE; break;
b38cadfb 14587
0855e32b
NS		 14588 case R_ARM_TLS_GOTDESC:
14589 case R_ARM_TLS_CALL: case R_ARM_THM_TLS_CALL:
14590 case R_ARM_TLS_DESCSEQ: case R_ARM_THM_TLS_DESCSEQ:
14591 tls_type = GOT_TLS_GDESC; break;
b38cadfb 14592
ba93b8ac
DJ		 14593 default: tls_type = GOT_NORMAL; break;
14594 }
252b5132 14595
0e1862bb 14596 if (!bfd_link_executable (info) && (tls_type & GOT_TLS_IE))
eea6dad2
KM		 14597 info->flags |= DF_STATIC_TLS;
14598
ba93b8ac
DJ		 14599 if (h != NULL)
14600 {
14601 h->got.refcount++;
14602 old_tls_type = elf32_arm_hash_entry (h)->tls_type;
14603 }
14604 else
14605 {
ba93b8ac 14606 /* This is a global offset table entry for a local symbol. */
34e77a92
RS		 14607 if (!elf32_arm_allocate_local_sym_info (abfd))
14608 return FALSE;
14609 elf_local_got_refcounts (abfd)[r_symndx] += 1;
ba93b8ac
DJ		 14610 old_tls_type = elf32_arm_local_got_tls_type (abfd) [r_symndx];
14611 }
14612
0855e32b 14613 /* If a variable is accessed with both tls methods, two
99059e56 14614 slots may be created. */
0855e32b
NS		 14615 if (GOT_TLS_GD_ANY_P (old_tls_type)
14616 && GOT_TLS_GD_ANY_P (tls_type))
14617 tls_type |= old_tls_type;
14618
14619 /* We will already have issued an error message if there
14620 is a TLS/non-TLS mismatch, based on the symbol
14621 type. So just combine any TLS types needed. */
ba93b8ac
DJ		 14622 if (old_tls_type != GOT_UNKNOWN && old_tls_type != GOT_NORMAL
14623 && tls_type != GOT_NORMAL)
14624 tls_type |= old_tls_type;
14625
0855e32b 14626 /* If the symbol is accessed in both IE and GDESC
99059e56
RM		 14627 method, we're able to relax. Turn off the GDESC flag,
14628 without messing up with any other kind of tls types
6a631e86 14629 that may be involved. */
0855e32b
NS		 14630 if ((tls_type & GOT_TLS_IE) && (tls_type & GOT_TLS_GDESC))
14631 tls_type &= ~GOT_TLS_GDESC;
14632
ba93b8ac
DJ		 14633 if (old_tls_type != tls_type)
14634 {
14635 if (h != NULL)
14636 elf32_arm_hash_entry (h)->tls_type = tls_type;
14637 else
14638 elf32_arm_local_got_tls_type (abfd) [r_symndx] = tls_type;
14639 }
14640 }
8029a119 14641 /* Fall through. */
ba93b8ac
DJ		 14642
14643 case R_ARM_TLS_LDM32:
14644 if (r_type == R_ARM_TLS_LDM32)
14645 htab->tls_ldm_got.refcount++;
8029a119 14646 /* Fall through. */
252b5132 14647
c19d1205 14648 case R_ARM_GOTOFF32:
5e681ec4 14649 case R_ARM_GOTPC:
cbc704f3
RS		 14650 if (htab->root.sgot == NULL
14651 && !create_got_section (htab->root.dynobj, info))
14652 return FALSE;
252b5132
RH		 14653 break;
14654
252b5132 14655 case R_ARM_PC24:
7359ea65 14656 case R_ARM_PLT32:
5b5bb741
PB		 14657 case R_ARM_CALL:
14658 case R_ARM_JUMP24:
eb043451 14659 case R_ARM_PREL31:
c19d1205 14660 case R_ARM_THM_CALL:
bd97cb95
DJ		 14661 case R_ARM_THM_JUMP24:
14662 case R_ARM_THM_JUMP19:
f6e32f6d
RS		 14663 call_reloc_p = TRUE;
14664 may_need_local_target_p = TRUE;
14665 break;
14666
14667 case R_ARM_ABS12:
14668 /* VxWorks uses dynamic R_ARM_ABS12 relocations for
14669 ldr __GOTT_INDEX__ offsets. */
14670 if (!htab->vxworks_p)
14671 {
14672 may_need_local_target_p = TRUE;
14673 break;
14674 }
aebf9be7 14675 else goto jump_over;
9eaff861 14676
f6e32f6d 14677 /* Fall through. */
39623e12 14678
96c23d59
JM		 14679 case R_ARM_MOVW_ABS_NC:
14680 case R_ARM_MOVT_ABS:
14681 case R_ARM_THM_MOVW_ABS_NC:
14682 case R_ARM_THM_MOVT_ABS:
0e1862bb 14683 if (bfd_link_pic (info))
96c23d59 14684 {
4eca0228 14685 _bfd_error_handler
96c23d59
JM		 14686 (_("%B: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
14687 abfd, elf32_arm_howto_table_1[r_type].name,
14688 (h) ? h->root.root.string : "a local symbol");
14689 bfd_set_error (bfd_error_bad_value);
14690 return FALSE;
14691 }
14692
14693 /* Fall through. */
39623e12
PB		 14694 case R_ARM_ABS32:
14695 case R_ARM_ABS32_NOI:
aebf9be7 14696 jump_over:
0e1862bb 14697 if (h != NULL && bfd_link_executable (info))
97323ad1
WN		 14698 {
14699 h->pointer_equality_needed = 1;
14700 }
14701 /* Fall through. */
39623e12
PB		 14702 case R_ARM_REL32:
14703 case R_ARM_REL32_NOI:
b6895b4f
PB		 14704 case R_ARM_MOVW_PREL_NC:
14705 case R_ARM_MOVT_PREL:
b6895b4f
PB		 14706 case R_ARM_THM_MOVW_PREL_NC:
14707 case R_ARM_THM_MOVT_PREL:
39623e12 14708
b7693d02 14709 /* Should the interworking branches be listed here? */
0e1862bb 14710 if ((bfd_link_pic (info) || htab->root.is_relocatable_executable)
34e77a92
RS		 14711 && (sec->flags & SEC_ALLOC) != 0)
14712 {
14713 if (h == NULL
469a3493 14714 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 14715 {
14716 /* In shared libraries and relocatable executables,
14717 we treat local relative references as calls;
14718 see the related SYMBOL_CALLS_LOCAL code in
14719 allocate_dynrelocs. */
14720 call_reloc_p = TRUE;
14721 may_need_local_target_p = TRUE;
14722 }
14723 else
14724 /* We are creating a shared library or relocatable
14725 executable, and this is a reloc against a global symbol,
14726 or a non-PC-relative reloc against a local symbol.
14727 We may need to copy the reloc into the output. */
14728 may_become_dynamic_p = TRUE;
14729 }
f6e32f6d
RS		 14730 else
14731 may_need_local_target_p = TRUE;
252b5132
RH		 14732 break;
14733
99059e56
RM		 14734 /* This relocation describes the C++ object vtable hierarchy.
14735 Reconstruct it for later use during GC. */
14736 case R_ARM_GNU_VTINHERIT:
14737 if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset))
14738 return FALSE;
14739 break;
14740
14741 /* This relocation describes which C++ vtable entries are actually
14742 used. Record for later use during GC. */
14743 case R_ARM_GNU_VTENTRY:
14744 BFD_ASSERT (h != NULL);
14745 if (h != NULL
14746 && !bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_offset))
14747 return FALSE;
14748 break;
14749 }
f6e32f6d
RS		 14750
14751 if (h != NULL)
14752 {
14753 if (call_reloc_p)
14754 /* We may need a .plt entry if the function this reloc
14755 refers to is in a different object, regardless of the
14756 symbol's type. We can't tell for sure yet, because
14757 something later might force the symbol local. */
14758 h->needs_plt = 1;
14759 else if (may_need_local_target_p)
14760 /* If this reloc is in a read-only section, we might
14761 need a copy reloc. We can't check reliably at this
14762 stage whether the section is read-only, as input
14763 sections have not yet been mapped to output sections.
14764 Tentatively set the flag for now, and correct in
14765 adjust_dynamic_symbol. */
14766 h->non_got_ref = 1;
14767 }
14768
34e77a92
RS		 14769 if (may_need_local_target_p
14770 && (h != NULL || ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC))
f6e32f6d 14771 {
34e77a92
RS		 14772 union gotplt_union *root_plt;
14773 struct arm_plt_info *arm_plt;
14774 struct arm_local_iplt_info *local_iplt;
14775
14776 if (h != NULL)
14777 {
14778 root_plt = &h->plt;
14779 arm_plt = &eh->plt;
14780 }
14781 else
14782 {
14783 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
14784 if (local_iplt == NULL)
14785 return FALSE;
14786 root_plt = &local_iplt->root;
14787 arm_plt = &local_iplt->arm;
14788 }
14789
f6e32f6d
RS		 14790 /* If the symbol is a function that doesn't bind locally,
14791 this relocation will need a PLT entry. */
a8c887dd
NC		 14792 if (root_plt->refcount != -1)
14793 root_plt->refcount += 1;
34e77a92
RS		 14794
14795 if (!call_reloc_p)
14796 arm_plt->noncall_refcount++;
f6e32f6d
RS		 14797
14798 /* It's too early to use htab->use_blx here, so we have to
14799 record possible blx references separately from
14800 relocs that definitely need a thumb stub. */
14801
14802 if (r_type == R_ARM_THM_CALL)
34e77a92 14803 arm_plt->maybe_thumb_refcount += 1;
f6e32f6d
RS		 14804
14805 if (r_type == R_ARM_THM_JUMP24
14806 || r_type == R_ARM_THM_JUMP19)
34e77a92 14807 arm_plt->thumb_refcount += 1;
f6e32f6d
RS		 14808 }
14809
14810 if (may_become_dynamic_p)
14811 {
14812 struct elf_dyn_relocs *p, **head;
14813
14814 /* Create a reloc section in dynobj. */
14815 if (sreloc == NULL)
14816 {
14817 sreloc = _bfd_elf_make_dynamic_reloc_section
14818 (sec, dynobj, 2, abfd, ! htab->use_rel);
14819
14820 if (sreloc == NULL)
14821 return FALSE;
14822
14823 /* BPABI objects never have dynamic relocations mapped. */
14824 if (htab->symbian_p)
14825 {
14826 flagword flags;
14827
14828 flags = bfd_get_section_flags (dynobj, sreloc);
14829 flags &= ~(SEC_LOAD | SEC_ALLOC);
14830 bfd_set_section_flags (dynobj, sreloc, flags);
14831 }
14832 }
14833
14834 /* If this is a global symbol, count the number of
14835 relocations we need for this symbol. */
14836 if (h != NULL)
14837 head = &((struct elf32_arm_link_hash_entry *) h)->dyn_relocs;
14838 else
14839 {
34e77a92
RS		 14840 head = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
14841 if (head == NULL)
f6e32f6d 14842 return FALSE;
f6e32f6d
RS		 14843 }
14844
14845 p = *head;
14846 if (p == NULL || p->sec != sec)
14847 {
14848 bfd_size_type amt = sizeof *p;
14849
14850 p = (struct elf_dyn_relocs *) bfd_alloc (htab->root.dynobj, amt);
14851 if (p == NULL)
14852 return FALSE;
14853 p->next = *head;
14854 *head = p;
14855 p->sec = sec;
14856 p->count = 0;
14857 p->pc_count = 0;
14858 }
14859
469a3493 14860 if (elf32_arm_howto_from_type (r_type)->pc_relative)
f6e32f6d
RS		 14861 p->pc_count += 1;
14862 p->count += 1;
14863 }
252b5132 14864 }
f21f3fe0 14865
b34976b6 14866 return TRUE;
252b5132
RH		 14867}
14868
9eaff861
AO		 14869static void
14870elf32_arm_update_relocs (asection *o,
14871 struct bfd_elf_section_reloc_data *reldata)
14872{
14873 void (*swap_in) (bfd *, const bfd_byte *, Elf_Internal_Rela *);
14874 void (*swap_out) (bfd *, const Elf_Internal_Rela *, bfd_byte *);
14875 const struct elf_backend_data *bed;
14876 _arm_elf_section_data *eado;
14877 struct bfd_link_order *p;
14878 bfd_byte *erela_head, *erela;
14879 Elf_Internal_Rela *irela_head, *irela;
14880 Elf_Internal_Shdr *rel_hdr;
14881 bfd *abfd;
14882 unsigned int count;
14883
14884 eado = get_arm_elf_section_data (o);
14885
14886 if (!eado || eado->elf.this_hdr.sh_type != SHT_ARM_EXIDX)
14887 return;
14888
14889 abfd = o->owner;
14890 bed = get_elf_backend_data (abfd);
14891 rel_hdr = reldata->hdr;
14892
14893 if (rel_hdr->sh_entsize == bed->s->sizeof_rel)
14894 {
14895 swap_in = bed->s->swap_reloc_in;
14896 swap_out = bed->s->swap_reloc_out;
14897 }
14898 else if (rel_hdr->sh_entsize == bed->s->sizeof_rela)
14899 {
14900 swap_in = bed->s->swap_reloca_in;
14901 swap_out = bed->s->swap_reloca_out;
14902 }
14903 else
14904 abort ();
14905
14906 erela_head = rel_hdr->contents;
14907 irela_head = (Elf_Internal_Rela *) bfd_zmalloc
14908 ((NUM_SHDR_ENTRIES (rel_hdr) + 1) * sizeof (*irela_head));
14909
14910 erela = erela_head;
14911 irela = irela_head;
14912 count = 0;
14913
14914 for (p = o->map_head.link_order; p; p = p->next)
14915 {
14916 if (p->type == bfd_section_reloc_link_order
14917 || p->type == bfd_symbol_reloc_link_order)
14918 {
14919 (*swap_in) (abfd, erela, irela);
14920 erela += rel_hdr->sh_entsize;
14921 irela++;
14922 count++;
14923 }
14924 else if (p->type == bfd_indirect_link_order)
14925 {
14926 struct bfd_elf_section_reloc_data *input_reldata;
14927 arm_unwind_table_edit *edit_list, *edit_tail;
14928 _arm_elf_section_data *eadi;
14929 bfd_size_type j;
14930 bfd_vma offset;
14931 asection *i;
14932
14933 i = p->u.indirect.section;
14934
14935 eadi = get_arm_elf_section_data (i);
14936 edit_list = eadi->u.exidx.unwind_edit_list;
14937 edit_tail = eadi->u.exidx.unwind_edit_tail;
14938 offset = o->vma + i->output_offset;
14939
14940 if (eadi->elf.rel.hdr &&
14941 eadi->elf.rel.hdr->sh_entsize == rel_hdr->sh_entsize)
14942 input_reldata = &eadi->elf.rel;
14943 else if (eadi->elf.rela.hdr &&
14944 eadi->elf.rela.hdr->sh_entsize == rel_hdr->sh_entsize)
14945 input_reldata = &eadi->elf.rela;
14946 else
14947 abort ();
14948
14949 if (edit_list)
14950 {
14951 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
14952 {
14953 arm_unwind_table_edit *edit_node, *edit_next;
14954 bfd_vma bias;
c48182bf 14955 bfd_vma reloc_index;
9eaff861
AO		 14956
14957 (*swap_in) (abfd, erela, irela);
c48182bf 14958 reloc_index = (irela->r_offset - offset) / 8;
9eaff861
AO		 14959
14960 bias = 0;
14961 edit_node = edit_list;
14962 for (edit_next = edit_list;
c48182bf 14963 edit_next && edit_next->index <= reloc_index;
9eaff861
AO		 14964 edit_next = edit_node->next)
14965 {
14966 bias++;
14967 edit_node = edit_next;
14968 }
14969
14970 if (edit_node->type != DELETE_EXIDX_ENTRY
c48182bf 14971 || edit_node->index != reloc_index)
9eaff861
AO		 14972 {
14973 irela->r_offset -= bias * 8;
14974 irela++;
14975 count++;
14976 }
14977
14978 erela += rel_hdr->sh_entsize;
14979 }
14980
14981 if (edit_tail->type == INSERT_EXIDX_CANTUNWIND_AT_END)
14982 {
14983 /* New relocation entity. */
14984 asection *text_sec = edit_tail->linked_section;
14985 asection *text_out = text_sec->output_section;
14986 bfd_vma exidx_offset = offset + i->size - 8;
14987
14988 irela->r_addend = 0;
14989 irela->r_offset = exidx_offset;
14990 irela->r_info = ELF32_R_INFO
14991 (text_out->target_index, R_ARM_PREL31);
14992 irela++;
14993 count++;
14994 }
14995 }
14996 else
14997 {
14998 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
14999 {
15000 (*swap_in) (abfd, erela, irela);
15001 erela += rel_hdr->sh_entsize;
15002 irela++;
15003 }
15004
15005 count += NUM_SHDR_ENTRIES (input_reldata->hdr);
15006 }
15007 }
15008 }
15009
15010 reldata->count = count;
15011 rel_hdr->sh_size = count * rel_hdr->sh_entsize;
15012
15013 erela = erela_head;
15014 irela = irela_head;
15015 while (count > 0)
15016 {
15017 (*swap_out) (abfd, irela, erela);
15018 erela += rel_hdr->sh_entsize;
15019 irela++;
15020 count--;
15021 }
15022
15023 free (irela_head);
15024
15025 /* Hashes are no longer valid. */
15026 free (reldata->hashes);
15027 reldata->hashes = NULL;
15028}
15029
6a5bb875 15030/* Unwinding tables are not referenced directly. This pass marks them as
4ba2ef8f
TP		 15031 required if the corresponding code section is marked. Similarly, ARMv8-M
15032 secure entry functions can only be referenced by SG veneers which are
15033 created after the GC process. They need to be marked in case they reside in
15034 their own section (as would be the case if code was compiled with
15035 -ffunction-sections). */
6a5bb875
PB		 15036
15037static bfd_boolean
906e58ca
NC		 15038elf32_arm_gc_mark_extra_sections (struct bfd_link_info *info,
15039 elf_gc_mark_hook_fn gc_mark_hook)
6a5bb875
PB		 15040{
15041 bfd *sub;
15042 Elf_Internal_Shdr **elf_shdrp;
4ba2ef8f
TP		 15043 asection *cmse_sec;
15044 obj_attribute *out_attr;
15045 Elf_Internal_Shdr *symtab_hdr;
15046 unsigned i, sym_count, ext_start;
15047 const struct elf_backend_data *bed;
15048 struct elf_link_hash_entry **sym_hashes;
15049 struct elf32_arm_link_hash_entry *cmse_hash;
15050 bfd_boolean again, is_v8m, first_bfd_browse = TRUE;
6a5bb875 15051
7f6ab9f8
AM		 15052 _bfd_elf_gc_mark_extra_sections (info, gc_mark_hook);
15053
4ba2ef8f
TP		 15054 out_attr = elf_known_obj_attributes_proc (info->output_bfd);
15055 is_v8m = out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
15056 && out_attr[Tag_CPU_arch_profile].i == 'M';
15057
6a5bb875
PB		 15058 /* Marking EH data may cause additional code sections to be marked,
15059 requiring multiple passes. */
15060 again = TRUE;
15061 while (again)
15062 {
15063 again = FALSE;
c72f2fb2 15064 for (sub = info->input_bfds; sub != NULL; sub = sub->link.next)
6a5bb875
PB		 15065 {
15066 asection *o;
15067
0ffa91dd 15068 if (! is_arm_elf (sub))
6a5bb875
PB		 15069 continue;
15070
15071 elf_shdrp = elf_elfsections (sub);
15072 for (o = sub->sections; o != NULL; o = o->next)
15073 {
15074 Elf_Internal_Shdr *hdr;
0ffa91dd 15075
6a5bb875 15076 hdr = &elf_section_data (o)->this_hdr;
4fbb74a6
AM		 15077 if (hdr->sh_type == SHT_ARM_EXIDX
15078 && hdr->sh_link
15079 && hdr->sh_link < elf_numsections (sub)
6a5bb875
PB		 15080 && !o->gc_mark
15081 && elf_shdrp[hdr->sh_link]->bfd_section->gc_mark)
15082 {
15083 again = TRUE;
15084 if (!_bfd_elf_gc_mark (info, o, gc_mark_hook))
15085 return FALSE;
15086 }
15087 }
4ba2ef8f
TP		 15088
15089 /* Mark section holding ARMv8-M secure entry functions. We mark all
15090 of them so no need for a second browsing. */
15091 if (is_v8m && first_bfd_browse)
15092 {
15093 sym_hashes = elf_sym_hashes (sub);
15094 bed = get_elf_backend_data (sub);
15095 symtab_hdr = &elf_tdata (sub)->symtab_hdr;
15096 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
15097 ext_start = symtab_hdr->sh_info;
15098
15099 /* Scan symbols. */
15100 for (i = ext_start; i < sym_count; i++)
15101 {
15102 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
15103
15104 /* Assume it is a special symbol. If not, cmse_scan will
15105 warn about it and user can do something about it. */
15106 if (ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
15107 {
15108 cmse_sec = cmse_hash->root.root.u.def.section;
5025eb7c
AO		 15109 if (!cmse_sec->gc_mark
15110 && !_bfd_elf_gc_mark (info, cmse_sec, gc_mark_hook))
4ba2ef8f
TP		 15111 return FALSE;
15112 }
15113 }
15114 }
6a5bb875 15115 }
4ba2ef8f 15116 first_bfd_browse = FALSE;
6a5bb875
PB		 15117 }
15118
15119 return TRUE;
15120}
15121
3c9458e9
NC		 15122/* Treat mapping symbols as special target symbols. */
15123
15124static bfd_boolean
15125elf32_arm_is_target_special_symbol (bfd * abfd ATTRIBUTE_UNUSED, asymbol * sym)
15126{
b0796911
PB		 15127 return bfd_is_arm_special_symbol_name (sym->name,
15128 BFD_ARM_SPECIAL_SYM_TYPE_ANY);
3c9458e9
NC		 15129}
15130
0367ecfb
NC		 15131/* This is a copy of elf_find_function() from elf.c except that
15132 ARM mapping symbols are ignored when looking for function names
15133 and STT_ARM_TFUNC is considered to a function type. */
252b5132 15134
0367ecfb
NC		 15135static bfd_boolean
15136arm_elf_find_function (bfd * abfd ATTRIBUTE_UNUSED,
0367ecfb 15137 asymbol ** symbols,
fb167eb2 15138 asection * section,
0367ecfb
NC		 15139 bfd_vma offset,
15140 const char ** filename_ptr,
15141 const char ** functionname_ptr)
15142{
15143 const char * filename = NULL;
15144 asymbol * func = NULL;
15145 bfd_vma low_func = 0;
15146 asymbol ** p;
252b5132
RH		 15147
15148 for (p = symbols; *p != NULL; p++)
15149 {
15150 elf_symbol_type *q;
15151
15152 q = (elf_symbol_type *) *p;
15153
252b5132
RH		 15154 switch (ELF_ST_TYPE (q->internal_elf_sym.st_info))
15155 {
15156 default:
15157 break;
15158 case STT_FILE:
15159 filename = bfd_asymbol_name (&q->symbol);
15160 break;
252b5132
RH		 15161 case STT_FUNC:
15162 case STT_ARM_TFUNC:
9d2da7ca 15163 case STT_NOTYPE:
b0796911 15164 /* Skip mapping symbols. */
0367ecfb 15165 if ((q->symbol.flags & BSF_LOCAL)
b0796911
PB		 15166 && bfd_is_arm_special_symbol_name (q->symbol.name,
15167 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
0367ecfb
NC		 15168 continue;
15169 /* Fall through. */
6b40fcba 15170 if (bfd_get_section (&q->symbol) == section
252b5132
RH		 15171 && q->symbol.value >= low_func
15172 && q->symbol.value <= offset)
15173 {
15174 func = (asymbol *) q;
15175 low_func = q->symbol.value;
15176 }
15177 break;
15178 }
15179 }
15180
15181 if (func == NULL)
b34976b6 15182 return FALSE;
252b5132 15183
0367ecfb
NC		 15184 if (filename_ptr)
15185 *filename_ptr = filename;
15186 if (functionname_ptr)
15187 *functionname_ptr = bfd_asymbol_name (func);
15188
15189 return TRUE;
906e58ca 15190}
0367ecfb
NC		 15191
15192
15193/* Find the nearest line to a particular section and offset, for error
15194 reporting. This code is a duplicate of the code in elf.c, except
15195 that it uses arm_elf_find_function. */
15196
15197static bfd_boolean
15198elf32_arm_find_nearest_line (bfd * abfd,
0367ecfb 15199 asymbol ** symbols,
fb167eb2 15200 asection * section,
0367ecfb
NC		 15201 bfd_vma offset,
15202 const char ** filename_ptr,
15203 const char ** functionname_ptr,
fb167eb2
AM		 15204 unsigned int * line_ptr,
15205 unsigned int * discriminator_ptr)
0367ecfb
NC		 15206{
15207 bfd_boolean found = FALSE;
15208
fb167eb2 15209 if (_bfd_dwarf2_find_nearest_line (abfd, symbols, NULL, section, offset,
0367ecfb 15210 filename_ptr, functionname_ptr,
fb167eb2
AM		 15211 line_ptr, discriminator_ptr,
15212 dwarf_debug_sections, 0,
0367ecfb
NC		 15213 & elf_tdata (abfd)->dwarf2_find_line_info))
15214 {
15215 if (!*functionname_ptr)
fb167eb2 15216 arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 15217 *filename_ptr ? NULL : filename_ptr,
15218 functionname_ptr);
f21f3fe0 15219
0367ecfb
NC		 15220 return TRUE;
15221 }
15222
fb167eb2
AM		 15223 /* Skip _bfd_dwarf1_find_nearest_line since no known ARM toolchain
15224 uses DWARF1. */
15225
0367ecfb
NC		 15226 if (! _bfd_stab_section_find_nearest_line (abfd, symbols, section, offset,
15227 & found, filename_ptr,
15228 functionname_ptr, line_ptr,
15229 & elf_tdata (abfd)->line_info))
15230 return FALSE;
15231
15232 if (found && (*functionname_ptr || *line_ptr))
15233 return TRUE;
15234
15235 if (symbols == NULL)
15236 return FALSE;
15237
fb167eb2 15238 if (! arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 15239 filename_ptr, functionname_ptr))
15240 return FALSE;
15241
15242 *line_ptr = 0;
b34976b6 15243 return TRUE;
252b5132
RH		 15244}
15245
4ab527b0
FF		 15246static bfd_boolean
15247elf32_arm_find_inliner_info (bfd * abfd,
15248 const char ** filename_ptr,
15249 const char ** functionname_ptr,
15250 unsigned int * line_ptr)
15251{
15252 bfd_boolean found;
15253 found = _bfd_dwarf2_find_inliner_info (abfd, filename_ptr,
15254 functionname_ptr, line_ptr,
15255 & elf_tdata (abfd)->dwarf2_find_line_info);
15256 return found;
15257}
15258
252b5132
RH		 15259/* Adjust a symbol defined by a dynamic object and referenced by a
15260 regular object. The current definition is in some section of the
15261 dynamic object, but we're not including those sections. We have to
15262 change the definition to something the rest of the link can
15263 understand. */
15264
b34976b6 15265static bfd_boolean
57e8b36a
NC		 15266elf32_arm_adjust_dynamic_symbol (struct bfd_link_info * info,
15267 struct elf_link_hash_entry * h)
252b5132
RH		 15268{
15269 bfd * dynobj;
5474d94f 15270 asection *s, *srel;
b7693d02 15271 struct elf32_arm_link_hash_entry * eh;
67687978 15272 struct elf32_arm_link_hash_table *globals;
252b5132 15273
67687978 15274 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15275 if (globals == NULL)
15276 return FALSE;
15277
252b5132
RH		 15278 dynobj = elf_hash_table (info)->dynobj;
15279
15280 /* Make sure we know what is going on here. */
15281 BFD_ASSERT (dynobj != NULL
f5385ebf 15282 && (h->needs_plt
34e77a92 15283 || h->type == STT_GNU_IFUNC
f6e332e6 15284 || h->u.weakdef != NULL
f5385ebf
AM		 15285 || (h->def_dynamic
15286 && h->ref_regular
15287 && !h->def_regular)));
252b5132 15288
b7693d02
DJ		 15289 eh = (struct elf32_arm_link_hash_entry *) h;
15290
252b5132
RH		 15291 /* If this is a function, put it in the procedure linkage table. We
15292 will fill in the contents of the procedure linkage table later,
15293 when we know the address of the .got section. */
34e77a92 15294 if (h->type == STT_FUNC || h->type == STT_GNU_IFUNC || h->needs_plt)
252b5132 15295 {
34e77a92
RS		 15296 /* Calls to STT_GNU_IFUNC symbols always use a PLT, even if the
15297 symbol binds locally. */
5e681ec4 15298 if (h->plt.refcount <= 0
34e77a92
RS		 15299 || (h->type != STT_GNU_IFUNC
15300 && (SYMBOL_CALLS_LOCAL (info, h)
15301 || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
15302 && h->root.type == bfd_link_hash_undefweak))))
252b5132
RH		 15303 {
15304 /* This case can occur if we saw a PLT32 reloc in an input
5e681ec4
PB		 15305 file, but the symbol was never referred to by a dynamic
15306 object, or if all references were garbage collected. In
15307 such a case, we don't actually need to build a procedure
15308 linkage table, and we can just do a PC24 reloc instead. */
15309 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 15310 eh->plt.thumb_refcount = 0;
15311 eh->plt.maybe_thumb_refcount = 0;
15312 eh->plt.noncall_refcount = 0;
f5385ebf 15313 h->needs_plt = 0;
252b5132
RH		 15314 }
15315
b34976b6 15316 return TRUE;
252b5132 15317 }
5e681ec4 15318 else
b7693d02
DJ		 15319 {
15320 /* It's possible that we incorrectly decided a .plt reloc was
15321 needed for an R_ARM_PC24 or similar reloc to a non-function sym
15322 in check_relocs. We can't decide accurately between function
15323 and non-function syms in check-relocs; Objects loaded later in
15324 the link may change h->type. So fix it now. */
15325 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 15326 eh->plt.thumb_refcount = 0;
15327 eh->plt.maybe_thumb_refcount = 0;
15328 eh->plt.noncall_refcount = 0;
b7693d02 15329 }
252b5132
RH		 15330
15331 /* If this is a weak symbol, and there is a real definition, the
15332 processor independent code will have arranged for us to see the
15333 real definition first, and we can just use the same value. */
f6e332e6 15334 if (h->u.weakdef != NULL)
252b5132 15335 {
f6e332e6
AM		 15336 BFD_ASSERT (h->u.weakdef->root.type == bfd_link_hash_defined
15337 || h->u.weakdef->root.type == bfd_link_hash_defweak);
15338 h->root.u.def.section = h->u.weakdef->root.u.def.section;
15339 h->root.u.def.value = h->u.weakdef->root.u.def.value;
b34976b6 15340 return TRUE;
252b5132
RH		 15341 }
15342
ba93b8ac
DJ		 15343 /* If there are no non-GOT references, we do not need a copy
15344 relocation. */
15345 if (!h->non_got_ref)
15346 return TRUE;
15347
252b5132
RH		 15348 /* This is a reference to a symbol defined by a dynamic object which
15349 is not a function. */
15350
15351 /* If we are creating a shared library, we must presume that the
15352 only references to the symbol are via the global offset table.
15353 For such cases we need not do anything here; the relocations will
67687978
PB		 15354 be handled correctly by relocate_section. Relocatable executables
15355 can reference data in shared objects directly, so we don't need to
15356 do anything here. */
0e1862bb 15357 if (bfd_link_pic (info) || globals->root.is_relocatable_executable)
b34976b6 15358 return TRUE;
252b5132
RH		 15359
15360 /* We must allocate the symbol in our .dynbss section, which will
15361 become part of the .bss section of the executable. There will be
15362 an entry for this symbol in the .dynsym section. The dynamic
15363 object will contain position independent code, so all references
15364 from the dynamic object to this symbol will go through the global
15365 offset table. The dynamic linker will use the .dynsym entry to
15366 determine the address it must put in the global offset table, so
15367 both the dynamic object and the regular object will refer to the
15368 same memory location for the variable. */
5522f910
NC		 15369 /* If allowed, we must generate a R_ARM_COPY reloc to tell the dynamic
15370 linker to copy the initial value out of the dynamic object and into
15371 the runtime process image. We need to remember the offset into the
00a97672 15372 .rel(a).bss section we are going to use. */
5474d94f
AM		 15373 if ((h->root.u.def.section->flags & SEC_READONLY) != 0)
15374 {
15375 s = globals->root.sdynrelro;
15376 srel = globals->root.sreldynrelro;
15377 }
15378 else
15379 {
15380 s = globals->root.sdynbss;
15381 srel = globals->root.srelbss;
15382 }
5522f910
NC		 15383 if (info->nocopyreloc == 0
15384 && (h->root.u.def.section->flags & SEC_ALLOC) != 0
5522f910 15385 && h->size != 0)
252b5132 15386 {
47beaa6a 15387 elf32_arm_allocate_dynrelocs (info, srel, 1);
f5385ebf 15388 h->needs_copy = 1;
252b5132
RH		 15389 }
15390
6cabe1ea 15391 return _bfd_elf_adjust_dynamic_copy (info, h, s);
252b5132
RH		 15392}
15393
5e681ec4
PB		 15394/* Allocate space in .plt, .got and associated reloc sections for
15395 dynamic relocs. */
15396
15397static bfd_boolean
47beaa6a 15398allocate_dynrelocs_for_symbol (struct elf_link_hash_entry *h, void * inf)
5e681ec4
PB		 15399{
15400 struct bfd_link_info *info;
15401 struct elf32_arm_link_hash_table *htab;
15402 struct elf32_arm_link_hash_entry *eh;
0bdcacaf 15403 struct elf_dyn_relocs *p;
5e681ec4
PB		 15404
15405 if (h->root.type == bfd_link_hash_indirect)
15406 return TRUE;
15407
e6a6bb22
AM		 15408 eh = (struct elf32_arm_link_hash_entry *) h;
15409
5e681ec4
PB		 15410 info = (struct bfd_link_info *) inf;
15411 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15412 if (htab == NULL)
15413 return FALSE;
5e681ec4 15414
34e77a92 15415 if ((htab->root.dynamic_sections_created || h->type == STT_GNU_IFUNC)
5e681ec4
PB		 15416 && h->plt.refcount > 0)
15417 {
15418 /* Make sure this symbol is output as a dynamic symbol.
15419 Undefined weak syms won't yet be marked as dynamic. */
15420 if (h->dynindx == -1
f5385ebf 15421 && !h->forced_local)
5e681ec4 15422 {
c152c796 15423 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 15424 return FALSE;
15425 }
15426
34e77a92
RS		 15427 /* If the call in the PLT entry binds locally, the associated
15428 GOT entry should use an R_ARM_IRELATIVE relocation instead of
15429 the usual R_ARM_JUMP_SLOT. Put it in the .iplt section rather
15430 than the .plt section. */
15431 if (h->type == STT_GNU_IFUNC && SYMBOL_CALLS_LOCAL (info, h))
15432 {
15433 eh->is_iplt = 1;
15434 if (eh->plt.noncall_refcount == 0
15435 && SYMBOL_REFERENCES_LOCAL (info, h))
15436 /* All non-call references can be resolved directly.
15437 This means that they can (and in some cases, must)
15438 resolve directly to the run-time target, rather than
15439 to the PLT. That in turns means that any .got entry
15440 would be equal to the .igot.plt entry, so there's
15441 no point having both. */
15442 h->got.refcount = 0;
15443 }
15444
0e1862bb 15445 if (bfd_link_pic (info)
34e77a92 15446 || eh->is_iplt
7359ea65 15447 || WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, 0, h))
5e681ec4 15448 {
34e77a92 15449 elf32_arm_allocate_plt_entry (info, eh->is_iplt, &h->plt, &eh->plt);
b7693d02 15450
5e681ec4
PB		 15451 /* If this symbol is not defined in a regular file, and we are
15452 not generating a shared library, then set the symbol to this
15453 location in the .plt. This is required to make function
15454 pointers compare as equal between the normal executable and
15455 the shared library. */
0e1862bb 15456 if (! bfd_link_pic (info)
f5385ebf 15457 && !h->def_regular)
5e681ec4 15458 {
34e77a92 15459 h->root.u.def.section = htab->root.splt;
5e681ec4 15460 h->root.u.def.value = h->plt.offset;
5e681ec4 15461
67d74e43
DJ		 15462 /* Make sure the function is not marked as Thumb, in case
15463 it is the target of an ABS32 relocation, which will
15464 point to the PLT entry. */
39d911fc 15465 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
67d74e43 15466 }
022f8312 15467
00a97672
RS		 15468 /* VxWorks executables have a second set of relocations for
15469 each PLT entry. They go in a separate relocation section,
15470 which is processed by the kernel loader. */
0e1862bb 15471 if (htab->vxworks_p && !bfd_link_pic (info))
00a97672
RS		 15472 {
15473 /* There is a relocation for the initial PLT entry:
15474 an R_ARM_32 relocation for _GLOBAL_OFFSET_TABLE_. */
15475 if (h->plt.offset == htab->plt_header_size)
47beaa6a 15476 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 1);
00a97672
RS		 15477
15478 /* There are two extra relocations for each subsequent
15479 PLT entry: an R_ARM_32 relocation for the GOT entry,
15480 and an R_ARM_32 relocation for the PLT entry. */
47beaa6a 15481 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 2);
00a97672 15482 }
5e681ec4
PB		 15483 }
15484 else
15485 {
15486 h->plt.offset = (bfd_vma) -1;
f5385ebf 15487 h->needs_plt = 0;
5e681ec4
PB		 15488 }
15489 }
15490 else
15491 {
15492 h->plt.offset = (bfd_vma) -1;
f5385ebf 15493 h->needs_plt = 0;
5e681ec4
PB		 15494 }
15495
0855e32b
NS		 15496 eh = (struct elf32_arm_link_hash_entry *) h;
15497 eh->tlsdesc_got = (bfd_vma) -1;
15498
5e681ec4
PB		 15499 if (h->got.refcount > 0)
15500 {
15501 asection *s;
15502 bfd_boolean dyn;
ba93b8ac
DJ		 15503 int tls_type = elf32_arm_hash_entry (h)->tls_type;
15504 int indx;
5e681ec4
PB		 15505
15506 /* Make sure this symbol is output as a dynamic symbol.
15507 Undefined weak syms won't yet be marked as dynamic. */
15508 if (h->dynindx == -1
f5385ebf 15509 && !h->forced_local)
5e681ec4 15510 {
c152c796 15511 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 15512 return FALSE;
15513 }
15514
e5a52504
MM		 15515 if (!htab->symbian_p)
15516 {
362d30a1 15517 s = htab->root.sgot;
e5a52504 15518 h->got.offset = s->size;
ba93b8ac
DJ		 15519
15520 if (tls_type == GOT_UNKNOWN)
15521 abort ();
15522
15523 if (tls_type == GOT_NORMAL)
15524 /* Non-TLS symbols need one GOT slot. */
15525 s->size += 4;
15526 else
15527 {
99059e56
RM		 15528 if (tls_type & GOT_TLS_GDESC)
15529 {
0855e32b 15530 /* R_ARM_TLS_DESC needs 2 GOT slots. */
99059e56 15531 eh->tlsdesc_got
0855e32b
NS		 15532 = (htab->root.sgotplt->size
15533 - elf32_arm_compute_jump_table_size (htab));
99059e56
RM		 15534 htab->root.sgotplt->size += 8;
15535 h->got.offset = (bfd_vma) -2;
34e77a92 15536 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 15537 reloc in the middle of .got.plt. */
99059e56
RM		 15538 htab->num_tls_desc++;
15539 }
0855e32b 15540
ba93b8ac 15541 if (tls_type & GOT_TLS_GD)
0855e32b
NS		 15542 {
15543 /* R_ARM_TLS_GD32 needs 2 consecutive GOT slots. If
15544 the symbol is both GD and GDESC, got.offset may
15545 have been overwritten. */
15546 h->got.offset = s->size;
15547 s->size += 8;
15548 }
15549
ba93b8ac
DJ		 15550 if (tls_type & GOT_TLS_IE)
15551 /* R_ARM_TLS_IE32 needs one GOT slot. */
15552 s->size += 4;
15553 }
15554
e5a52504 15555 dyn = htab->root.dynamic_sections_created;
ba93b8ac
DJ		 15556
15557 indx = 0;
0e1862bb
L		 15558 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
15559 bfd_link_pic (info),
15560 h)
15561 && (!bfd_link_pic (info)
ba93b8ac
DJ		 15562 || !SYMBOL_REFERENCES_LOCAL (info, h)))
15563 indx = h->dynindx;
15564
15565 if (tls_type != GOT_NORMAL
0e1862bb 15566 && (bfd_link_pic (info) || indx != 0)
ba93b8ac
DJ		 15567 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
15568 || h->root.type != bfd_link_hash_undefweak))
15569 {
15570 if (tls_type & GOT_TLS_IE)
47beaa6a 15571 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 15572
15573 if (tls_type & GOT_TLS_GD)
47beaa6a 15574 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 15575
b38cadfb 15576 if (tls_type & GOT_TLS_GDESC)
0855e32b 15577 {
47beaa6a 15578 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
0855e32b
NS		 15579 /* GDESC needs a trampoline to jump to. */
15580 htab->tls_trampoline = -1;
15581 }
15582
15583 /* Only GD needs it. GDESC just emits one relocation per
15584 2 entries. */
b38cadfb 15585 if ((tls_type & GOT_TLS_GD) && indx != 0)
47beaa6a 15586 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 15587 }
6f820c85 15588 else if (indx != -1 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 15589 {
15590 if (htab->root.dynamic_sections_created)
15591 /* Reserve room for the GOT entry's R_ARM_GLOB_DAT relocation. */
15592 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
15593 }
34e77a92
RS		 15594 else if (h->type == STT_GNU_IFUNC
15595 && eh->plt.noncall_refcount == 0)
15596 /* No non-call references resolve the STT_GNU_IFUNC's PLT entry;
15597 they all resolve dynamically instead. Reserve room for the
15598 GOT entry's R_ARM_IRELATIVE relocation. */
15599 elf32_arm_allocate_irelocs (info, htab->root.srelgot, 1);
0e1862bb
L		 15600 else if (bfd_link_pic (info)
15601 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
15602 || h->root.type != bfd_link_hash_undefweak))
b436d854 15603 /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
47beaa6a 15604 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
e5a52504 15605 }
5e681ec4
PB		 15606 }
15607 else
15608 h->got.offset = (bfd_vma) -1;
15609
a4fd1a8e
PB		 15610 /* Allocate stubs for exported Thumb functions on v4t. */
15611 if (!htab->use_blx && h->dynindx != -1
0eaedd0e 15612 && h->def_regular
39d911fc 15613 && ARM_GET_SYM_BRANCH_TYPE (h->target_internal) == ST_BRANCH_TO_THUMB
a4fd1a8e
PB		 15614 && ELF_ST_VISIBILITY (h->other) == STV_DEFAULT)
15615 {
15616 struct elf_link_hash_entry * th;
15617 struct bfd_link_hash_entry * bh;
15618 struct elf_link_hash_entry * myh;
15619 char name[1024];
15620 asection *s;
15621 bh = NULL;
15622 /* Create a new symbol to regist the real location of the function. */
15623 s = h->root.u.def.section;
906e58ca 15624 sprintf (name, "__real_%s", h->root.root.string);
a4fd1a8e
PB		 15625 _bfd_generic_link_add_one_symbol (info, s->owner,
15626 name, BSF_GLOBAL, s,
15627 h->root.u.def.value,
15628 NULL, TRUE, FALSE, &bh);
15629
15630 myh = (struct elf_link_hash_entry *) bh;
35fc36a8 15631 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
a4fd1a8e 15632 myh->forced_local = 1;
39d911fc 15633 ARM_SET_SYM_BRANCH_TYPE (myh->target_internal, ST_BRANCH_TO_THUMB);
a4fd1a8e
PB		 15634 eh->export_glue = myh;
15635 th = record_arm_to_thumb_glue (info, h);
15636 /* Point the symbol at the stub. */
15637 h->type = ELF_ST_INFO (ELF_ST_BIND (h->type), STT_FUNC);
39d911fc 15638 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
a4fd1a8e
PB		 15639 h->root.u.def.section = th->root.u.def.section;
15640 h->root.u.def.value = th->root.u.def.value & ~1;
15641 }
15642
0bdcacaf 15643 if (eh->dyn_relocs == NULL)
5e681ec4
PB		 15644 return TRUE;
15645
15646 /* In the shared -Bsymbolic case, discard space allocated for
15647 dynamic pc-relative relocs against symbols which turn out to be
15648 defined in regular objects. For the normal shared case, discard
15649 space for pc-relative relocs that have become local due to symbol
15650 visibility changes. */
15651
0e1862bb 15652 if (bfd_link_pic (info) || htab->root.is_relocatable_executable)
5e681ec4 15653 {
469a3493
RM		 15654 /* Relocs that use pc_count are PC-relative forms, which will appear
15655 on something like ".long foo - ." or "movw REG, foo - .". We want
15656 calls to protected symbols to resolve directly to the function
15657 rather than going via the plt. If people want function pointer
15658 comparisons to work as expected then they should avoid writing
15659 assembly like ".long foo - .". */
ba93b8ac
DJ		 15660 if (SYMBOL_CALLS_LOCAL (info, h))
15661 {
0bdcacaf 15662 struct elf_dyn_relocs **pp;
ba93b8ac 15663
0bdcacaf 15664 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
ba93b8ac
DJ		 15665 {
15666 p->count -= p->pc_count;
15667 p->pc_count = 0;
15668 if (p->count == 0)
15669 *pp = p->next;
15670 else
15671 pp = &p->next;
15672 }
15673 }
15674
4dfe6ac6 15675 if (htab->vxworks_p)
3348747a 15676 {
0bdcacaf 15677 struct elf_dyn_relocs **pp;
3348747a 15678
0bdcacaf 15679 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
3348747a 15680 {
0bdcacaf 15681 if (strcmp (p->sec->output_section->name, ".tls_vars") == 0)
3348747a
NS		 15682 *pp = p->next;
15683 else
15684 pp = &p->next;
15685 }
15686 }
15687
ba93b8ac 15688 /* Also discard relocs on undefined weak syms with non-default
99059e56 15689 visibility. */
0bdcacaf 15690 if (eh->dyn_relocs != NULL
5e681ec4 15691 && h->root.type == bfd_link_hash_undefweak)
22d606e9
AM		 15692 {
15693 if (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT)
0bdcacaf 15694 eh->dyn_relocs = NULL;
22d606e9
AM		 15695
15696 /* Make sure undefined weak symbols are output as a dynamic
15697 symbol in PIEs. */
15698 else if (h->dynindx == -1
15699 && !h->forced_local)
15700 {
15701 if (! bfd_elf_link_record_dynamic_symbol (info, h))
15702 return FALSE;
15703 }
15704 }
15705
67687978
PB		 15706 else if (htab->root.is_relocatable_executable && h->dynindx == -1
15707 && h->root.type == bfd_link_hash_new)
15708 {
15709 /* Output absolute symbols so that we can create relocations
15710 against them. For normal symbols we output a relocation
15711 against the section that contains them. */
15712 if (! bfd_elf_link_record_dynamic_symbol (info, h))
15713 return FALSE;
15714 }
15715
5e681ec4
PB		 15716 }
15717 else
15718 {
15719 /* For the non-shared case, discard space for relocs against
15720 symbols which turn out to need copy relocs or are not
15721 dynamic. */
15722
f5385ebf
AM		 15723 if (!h->non_got_ref
15724 && ((h->def_dynamic
15725 && !h->def_regular)
5e681ec4
PB		 15726 || (htab->root.dynamic_sections_created
15727 && (h->root.type == bfd_link_hash_undefweak
15728 || h->root.type == bfd_link_hash_undefined))))
15729 {
15730 /* Make sure this symbol is output as a dynamic symbol.
15731 Undefined weak syms won't yet be marked as dynamic. */
15732 if (h->dynindx == -1
f5385ebf 15733 && !h->forced_local)
5e681ec4 15734 {
c152c796 15735 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 15736 return FALSE;
15737 }
15738
15739 /* If that succeeded, we know we'll be keeping all the
15740 relocs. */
15741 if (h->dynindx != -1)
15742 goto keep;
15743 }
15744
0bdcacaf 15745 eh->dyn_relocs = NULL;
5e681ec4
PB		 15746
15747 keep: ;
15748 }
15749
15750 /* Finally, allocate space. */
0bdcacaf 15751 for (p = eh->dyn_relocs; p != NULL; p = p->next)
5e681ec4 15752 {
0bdcacaf 15753 asection *sreloc = elf_section_data (p->sec)->sreloc;
34e77a92
RS		 15754 if (h->type == STT_GNU_IFUNC
15755 && eh->plt.noncall_refcount == 0
15756 && SYMBOL_REFERENCES_LOCAL (info, h))
15757 elf32_arm_allocate_irelocs (info, sreloc, p->count);
15758 else
15759 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
5e681ec4
PB		 15760 }
15761
15762 return TRUE;
15763}
15764
08d1f311
DJ		 15765/* Find any dynamic relocs that apply to read-only sections. */
15766
15767static bfd_boolean
8029a119 15768elf32_arm_readonly_dynrelocs (struct elf_link_hash_entry * h, void * inf)
08d1f311 15769{
8029a119 15770 struct elf32_arm_link_hash_entry * eh;
0bdcacaf 15771 struct elf_dyn_relocs * p;
08d1f311 15772
08d1f311 15773 eh = (struct elf32_arm_link_hash_entry *) h;
0bdcacaf 15774 for (p = eh->dyn_relocs; p != NULL; p = p->next)
08d1f311 15775 {
0bdcacaf 15776 asection *s = p->sec;
08d1f311
DJ		 15777
15778 if (s != NULL && (s->flags & SEC_READONLY) != 0)
15779 {
15780 struct bfd_link_info *info = (struct bfd_link_info *) inf;
15781
15782 info->flags |= DF_TEXTREL;
15783
15784 /* Not an error, just cut short the traversal. */
15785 return FALSE;
15786 }
15787 }
15788 return TRUE;
15789}
15790
d504ffc8
DJ		 15791void
15792bfd_elf32_arm_set_byteswap_code (struct bfd_link_info *info,
15793 int byteswap_code)
15794{
15795 struct elf32_arm_link_hash_table *globals;
15796
15797 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15798 if (globals == NULL)
15799 return;
15800
d504ffc8
DJ		 15801 globals->byteswap_code = byteswap_code;
15802}
15803
252b5132
RH		 15804/* Set the sizes of the dynamic sections. */
15805
b34976b6 15806static bfd_boolean
57e8b36a
NC		 15807elf32_arm_size_dynamic_sections (bfd * output_bfd ATTRIBUTE_UNUSED,
15808 struct bfd_link_info * info)
252b5132
RH		 15809{
15810 bfd * dynobj;
15811 asection * s;
b34976b6
AM		 15812 bfd_boolean plt;
15813 bfd_boolean relocs;
5e681ec4
PB		 15814 bfd *ibfd;
15815 struct elf32_arm_link_hash_table *htab;
252b5132 15816
5e681ec4 15817 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15818 if (htab == NULL)
15819 return FALSE;
15820
252b5132
RH		 15821 dynobj = elf_hash_table (info)->dynobj;
15822 BFD_ASSERT (dynobj != NULL);
39b41c9c 15823 check_use_blx (htab);
252b5132
RH		 15824
15825 if (elf_hash_table (info)->dynamic_sections_created)
15826 {
15827 /* Set the contents of the .interp section to the interpreter. */
9b8b325a 15828 if (bfd_link_executable (info) && !info->nointerp)
252b5132 15829 {
3d4d4302 15830 s = bfd_get_linker_section (dynobj, ".interp");
252b5132 15831 BFD_ASSERT (s != NULL);
eea6121a 15832 s->size = sizeof ELF_DYNAMIC_INTERPRETER;
252b5132
RH		 15833 s->contents = (unsigned char *) ELF_DYNAMIC_INTERPRETER;
15834 }
15835 }
5e681ec4
PB		 15836
15837 /* Set up .got offsets for local syms, and space for local dynamic
15838 relocs. */
c72f2fb2 15839 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
252b5132 15840 {
5e681ec4
PB		 15841 bfd_signed_vma *local_got;
15842 bfd_signed_vma *end_local_got;
34e77a92 15843 struct arm_local_iplt_info **local_iplt_ptr, *local_iplt;
5e681ec4 15844 char *local_tls_type;
0855e32b 15845 bfd_vma *local_tlsdesc_gotent;
5e681ec4
PB		 15846 bfd_size_type locsymcount;
15847 Elf_Internal_Shdr *symtab_hdr;
15848 asection *srel;
4dfe6ac6 15849 bfd_boolean is_vxworks = htab->vxworks_p;
34e77a92 15850 unsigned int symndx;
5e681ec4 15851
0ffa91dd 15852 if (! is_arm_elf (ibfd))
5e681ec4
PB		 15853 continue;
15854
15855 for (s = ibfd->sections; s != NULL; s = s->next)
15856 {
0bdcacaf 15857 struct elf_dyn_relocs *p;
5e681ec4 15858
0bdcacaf 15859 for (p = (struct elf_dyn_relocs *)
99059e56 15860 elf_section_data (s)->local_dynrel; p != NULL; p = p->next)
5e681ec4 15861 {
0bdcacaf
RS		 15862 if (!bfd_is_abs_section (p->sec)
15863 && bfd_is_abs_section (p->sec->output_section))
5e681ec4
PB		 15864 {
15865 /* Input section has been discarded, either because
15866 it is a copy of a linkonce section or due to
15867 linker script /DISCARD/, so we'll be discarding
15868 the relocs too. */
15869 }
3348747a 15870 else if (is_vxworks
0bdcacaf 15871 && strcmp (p->sec->output_section->name,
3348747a
NS		 15872 ".tls_vars") == 0)
15873 {
15874 /* Relocations in vxworks .tls_vars sections are
15875 handled specially by the loader. */
15876 }
5e681ec4
PB		 15877 else if (p->count != 0)
15878 {
0bdcacaf 15879 srel = elf_section_data (p->sec)->sreloc;
47beaa6a 15880 elf32_arm_allocate_dynrelocs (info, srel, p->count);
0bdcacaf 15881 if ((p->sec->output_section->flags & SEC_READONLY) != 0)
5e681ec4
PB		 15882 info->flags |= DF_TEXTREL;
15883 }
15884 }
15885 }
15886
15887 local_got = elf_local_got_refcounts (ibfd);
15888 if (!local_got)
15889 continue;
15890
0ffa91dd 15891 symtab_hdr = & elf_symtab_hdr (ibfd);
5e681ec4
PB		 15892 locsymcount = symtab_hdr->sh_info;
15893 end_local_got = local_got + locsymcount;
34e77a92 15894 local_iplt_ptr = elf32_arm_local_iplt (ibfd);
ba93b8ac 15895 local_tls_type = elf32_arm_local_got_tls_type (ibfd);
0855e32b 15896 local_tlsdesc_gotent = elf32_arm_local_tlsdesc_gotent (ibfd);
34e77a92 15897 symndx = 0;
362d30a1
RS		 15898 s = htab->root.sgot;
15899 srel = htab->root.srelgot;
0855e32b 15900 for (; local_got < end_local_got;
34e77a92
RS		 15901 ++local_got, ++local_iplt_ptr, ++local_tls_type,
15902 ++local_tlsdesc_gotent, ++symndx)
5e681ec4 15903 {
0855e32b 15904 *local_tlsdesc_gotent = (bfd_vma) -1;
34e77a92
RS		 15905 local_iplt = *local_iplt_ptr;
15906 if (local_iplt != NULL)
15907 {
15908 struct elf_dyn_relocs *p;
15909
15910 if (local_iplt->root.refcount > 0)
15911 {
15912 elf32_arm_allocate_plt_entry (info, TRUE,
15913 &local_iplt->root,
15914 &local_iplt->arm);
15915 if (local_iplt->arm.noncall_refcount == 0)
15916 /* All references to the PLT are calls, so all
15917 non-call references can resolve directly to the
15918 run-time target. This means that the .got entry
15919 would be the same as the .igot.plt entry, so there's
15920 no point creating both. */
15921 *local_got = 0;
15922 }
15923 else
15924 {
15925 BFD_ASSERT (local_iplt->arm.noncall_refcount == 0);
15926 local_iplt->root.offset = (bfd_vma) -1;
15927 }
15928
15929 for (p = local_iplt->dyn_relocs; p != NULL; p = p->next)
15930 {
15931 asection *psrel;
15932
15933 psrel = elf_section_data (p->sec)->sreloc;
15934 if (local_iplt->arm.noncall_refcount == 0)
15935 elf32_arm_allocate_irelocs (info, psrel, p->count);
15936 else
15937 elf32_arm_allocate_dynrelocs (info, psrel, p->count);
15938 }
15939 }
5e681ec4
PB		 15940 if (*local_got > 0)
15941 {
34e77a92
RS		 15942 Elf_Internal_Sym *isym;
15943
eea6121a 15944 *local_got = s->size;
ba93b8ac
DJ		 15945 if (*local_tls_type & GOT_TLS_GD)
15946 /* TLS_GD relocs need an 8-byte structure in the GOT. */
15947 s->size += 8;
0855e32b
NS		 15948 if (*local_tls_type & GOT_TLS_GDESC)
15949 {
15950 *local_tlsdesc_gotent = htab->root.sgotplt->size
15951 - elf32_arm_compute_jump_table_size (htab);
15952 htab->root.sgotplt->size += 8;
15953 *local_got = (bfd_vma) -2;
34e77a92 15954 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 15955 reloc in the middle of .got.plt. */
99059e56 15956 htab->num_tls_desc++;
0855e32b 15957 }
ba93b8ac
DJ		 15958 if (*local_tls_type & GOT_TLS_IE)
15959 s->size += 4;
ba93b8ac 15960
0855e32b
NS		 15961 if (*local_tls_type & GOT_NORMAL)
15962 {
15963 /* If the symbol is both GD and GDESC, *local_got
15964 may have been overwritten. */
15965 *local_got = s->size;
15966 s->size += 4;
15967 }
15968
34e77a92
RS		 15969 isym = bfd_sym_from_r_symndx (&htab->sym_cache, ibfd, symndx);
15970 if (isym == NULL)
15971 return FALSE;
15972
15973 /* If all references to an STT_GNU_IFUNC PLT are calls,
15974 then all non-call references, including this GOT entry,
15975 resolve directly to the run-time target. */
15976 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC
15977 && (local_iplt == NULL
15978 || local_iplt->arm.noncall_refcount == 0))
15979 elf32_arm_allocate_irelocs (info, srel, 1);
0e1862bb 15980 else if (bfd_link_pic (info) || output_bfd->flags & DYNAMIC)
0855e32b 15981 {
0e1862bb 15982 if ((bfd_link_pic (info) && !(*local_tls_type & GOT_TLS_GDESC))
3064e1ff
JB		 15983 || *local_tls_type & GOT_TLS_GD)
15984 elf32_arm_allocate_dynrelocs (info, srel, 1);
99059e56 15985
0e1862bb 15986 if (bfd_link_pic (info) && *local_tls_type & GOT_TLS_GDESC)
3064e1ff
JB		 15987 {
15988 elf32_arm_allocate_dynrelocs (info,
15989 htab->root.srelplt, 1);
15990 htab->tls_trampoline = -1;
15991 }
0855e32b 15992 }
5e681ec4
PB		 15993 }
15994 else
15995 *local_got = (bfd_vma) -1;
15996 }
252b5132
RH		 15997 }
15998
ba93b8ac
DJ		 15999 if (htab->tls_ldm_got.refcount > 0)
16000 {
16001 /* Allocate two GOT entries and one dynamic relocation (if necessary)
16002 for R_ARM_TLS_LDM32 relocations. */
362d30a1
RS		 16003 htab->tls_ldm_got.offset = htab->root.sgot->size;
16004 htab->root.sgot->size += 8;
0e1862bb 16005 if (bfd_link_pic (info))
47beaa6a 16006 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 16007 }
16008 else
16009 htab->tls_ldm_got.offset = -1;
16010
5e681ec4
PB		 16011 /* Allocate global sym .plt and .got entries, and space for global
16012 sym dynamic relocs. */
47beaa6a 16013 elf_link_hash_traverse (& htab->root, allocate_dynrelocs_for_symbol, info);
252b5132 16014
d504ffc8 16015 /* Here we rummage through the found bfds to collect glue information. */
c72f2fb2 16016 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
c7b8f16e 16017 {
0ffa91dd 16018 if (! is_arm_elf (ibfd))
e44a2c9c
AM		 16019 continue;
16020
c7b8f16e
JB		 16021 /* Initialise mapping tables for code/data. */
16022 bfd_elf32_arm_init_maps (ibfd);
906e58ca 16023
c7b8f16e 16024 if (!bfd_elf32_arm_process_before_allocation (ibfd, info)
a504d23a
LA		 16025 || !bfd_elf32_arm_vfp11_erratum_scan (ibfd, info)
16026 || !bfd_elf32_arm_stm32l4xx_erratum_scan (ibfd, info))
dae82561 16027 _bfd_error_handler (_("Errors encountered processing file %B"), ibfd);
c7b8f16e 16028 }
d504ffc8 16029
3e6b1042
DJ		 16030 /* Allocate space for the glue sections now that we've sized them. */
16031 bfd_elf32_arm_allocate_interworking_sections (info);
16032
0855e32b
NS		 16033 /* For every jump slot reserved in the sgotplt, reloc_count is
16034 incremented. However, when we reserve space for TLS descriptors,
16035 it's not incremented, so in order to compute the space reserved
16036 for them, it suffices to multiply the reloc count by the jump
16037 slot size. */
16038 if (htab->root.srelplt)
16039 htab->sgotplt_jump_table_size = elf32_arm_compute_jump_table_size(htab);
16040
16041 if (htab->tls_trampoline)
16042 {
16043 if (htab->root.splt->size == 0)
16044 htab->root.splt->size += htab->plt_header_size;
b38cadfb 16045
0855e32b
NS		 16046 htab->tls_trampoline = htab->root.splt->size;
16047 htab->root.splt->size += htab->plt_entry_size;
b38cadfb 16048
0855e32b 16049 /* If we're not using lazy TLS relocations, don't generate the
99059e56 16050 PLT and GOT entries they require. */
0855e32b
NS		 16051 if (!(info->flags & DF_BIND_NOW))
16052 {
16053 htab->dt_tlsdesc_got = htab->root.sgot->size;
16054 htab->root.sgot->size += 4;
16055
16056 htab->dt_tlsdesc_plt = htab->root.splt->size;
16057 htab->root.splt->size += 4 * ARRAY_SIZE (dl_tlsdesc_lazy_trampoline);
16058 }
16059 }
16060
252b5132
RH		 16061 /* The check_relocs and adjust_dynamic_symbol entry points have
16062 determined the sizes of the various dynamic sections. Allocate
16063 memory for them. */
b34976b6
AM		 16064 plt = FALSE;
16065 relocs = FALSE;
252b5132
RH		 16066 for (s = dynobj->sections; s != NULL; s = s->next)
16067 {
16068 const char * name;
252b5132
RH		 16069
16070 if ((s->flags & SEC_LINKER_CREATED) == 0)
16071 continue;
16072
16073 /* It's OK to base decisions on the section name, because none
16074 of the dynobj section names depend upon the input files. */
16075 name = bfd_get_section_name (dynobj, s);
16076
34e77a92 16077 if (s == htab->root.splt)
252b5132 16078 {
c456f082
AM		 16079 /* Remember whether there is a PLT. */
16080 plt = s->size != 0;
252b5132 16081 }
0112cd26 16082 else if (CONST_STRNEQ (name, ".rel"))
252b5132 16083 {
c456f082 16084 if (s->size != 0)
252b5132 16085 {
252b5132 16086 /* Remember whether there are any reloc sections other
00a97672 16087 than .rel(a).plt and .rela.plt.unloaded. */
362d30a1 16088 if (s != htab->root.srelplt && s != htab->srelplt2)
b34976b6 16089 relocs = TRUE;
252b5132
RH		 16090
16091 /* We use the reloc_count field as a counter if we need
16092 to copy relocs into the output file. */
16093 s->reloc_count = 0;
16094 }
16095 }
34e77a92
RS		 16096 else if (s != htab->root.sgot
16097 && s != htab->root.sgotplt
16098 && s != htab->root.iplt
16099 && s != htab->root.igotplt
5474d94f
AM		 16100 && s != htab->root.sdynbss
16101 && s != htab->root.sdynrelro)
252b5132
RH		 16102 {
16103 /* It's not one of our sections, so don't allocate space. */
16104 continue;
16105 }
16106
c456f082 16107 if (s->size == 0)
252b5132 16108 {
c456f082 16109 /* If we don't need this section, strip it from the
00a97672
RS		 16110 output file. This is mostly to handle .rel(a).bss and
16111 .rel(a).plt. We must create both sections in
c456f082
AM		 16112 create_dynamic_sections, because they must be created
16113 before the linker maps input sections to output
16114 sections. The linker does that before
16115 adjust_dynamic_symbol is called, and it is that
16116 function which decides whether anything needs to go
16117 into these sections. */
8423293d 16118 s->flags |= SEC_EXCLUDE;
252b5132
RH		 16119 continue;
16120 }
16121
c456f082
AM		 16122 if ((s->flags & SEC_HAS_CONTENTS) == 0)
16123 continue;
16124
252b5132 16125 /* Allocate memory for the section contents. */
21d799b5 16126 s->contents = (unsigned char *) bfd_zalloc (dynobj, s->size);
c456f082 16127 if (s->contents == NULL)
b34976b6 16128 return FALSE;
252b5132
RH		 16129 }
16130
16131 if (elf_hash_table (info)->dynamic_sections_created)
16132 {
16133 /* Add some entries to the .dynamic section. We fill in the
16134 values later, in elf32_arm_finish_dynamic_sections, but we
16135 must add the entries now so that we get the correct size for
16136 the .dynamic section. The DT_DEBUG entry is filled in by the
16137 dynamic linker and used by the debugger. */
dc810e39 16138#define add_dynamic_entry(TAG, VAL) \
5a580b3a 16139 _bfd_elf_add_dynamic_entry (info, TAG, VAL)
dc810e39 16140
0e1862bb 16141 if (bfd_link_executable (info))
252b5132 16142 {
dc810e39 16143 if (!add_dynamic_entry (DT_DEBUG, 0))
b34976b6 16144 return FALSE;
252b5132
RH		 16145 }
16146
16147 if (plt)
16148 {
dc810e39
AM		 16149 if ( !add_dynamic_entry (DT_PLTGOT, 0)
16150 || !add_dynamic_entry (DT_PLTRELSZ, 0)
00a97672
RS		 16151 || !add_dynamic_entry (DT_PLTREL,
16152 htab->use_rel ? DT_REL : DT_RELA)
dc810e39 16153 || !add_dynamic_entry (DT_JMPREL, 0))
b34976b6 16154 return FALSE;
0855e32b 16155
5025eb7c
AO		 16156 if (htab->dt_tlsdesc_plt
16157 && (!add_dynamic_entry (DT_TLSDESC_PLT,0)
16158 || !add_dynamic_entry (DT_TLSDESC_GOT,0)))
b38cadfb 16159 return FALSE;
252b5132
RH		 16160 }
16161
16162 if (relocs)
16163 {
00a97672
RS		 16164 if (htab->use_rel)
16165 {
16166 if (!add_dynamic_entry (DT_REL, 0)
16167 || !add_dynamic_entry (DT_RELSZ, 0)
16168 || !add_dynamic_entry (DT_RELENT, RELOC_SIZE (htab)))
16169 return FALSE;
16170 }
16171 else
16172 {
16173 if (!add_dynamic_entry (DT_RELA, 0)
16174 || !add_dynamic_entry (DT_RELASZ, 0)
16175 || !add_dynamic_entry (DT_RELAENT, RELOC_SIZE (htab)))
16176 return FALSE;
16177 }
252b5132
RH		 16178 }
16179
08d1f311
DJ		 16180 /* If any dynamic relocs apply to a read-only section,
16181 then we need a DT_TEXTREL entry. */
16182 if ((info->flags & DF_TEXTREL) == 0)
8029a119
NC		 16183 elf_link_hash_traverse (& htab->root, elf32_arm_readonly_dynrelocs,
16184 info);
08d1f311 16185
99e4ae17 16186 if ((info->flags & DF_TEXTREL) != 0)
252b5132 16187 {
dc810e39 16188 if (!add_dynamic_entry (DT_TEXTREL, 0))
b34976b6 16189 return FALSE;
252b5132 16190 }
7a2b07ff
NS		 16191 if (htab->vxworks_p
16192 && !elf_vxworks_add_dynamic_entries (output_bfd, info))
16193 return FALSE;
252b5132 16194 }
8532796c 16195#undef add_dynamic_entry
252b5132 16196
b34976b6 16197 return TRUE;
252b5132
RH		 16198}
16199
0855e32b
NS		 16200/* Size sections even though they're not dynamic. We use it to setup
16201 _TLS_MODULE_BASE_, if needed. */
16202
16203static bfd_boolean
16204elf32_arm_always_size_sections (bfd *output_bfd,
99059e56 16205 struct bfd_link_info *info)
0855e32b
NS		 16206{
16207 asection *tls_sec;
16208
0e1862bb 16209 if (bfd_link_relocatable (info))
0855e32b
NS		 16210 return TRUE;
16211
16212 tls_sec = elf_hash_table (info)->tls_sec;
16213
16214 if (tls_sec)
16215 {
16216 struct elf_link_hash_entry *tlsbase;
16217
16218 tlsbase = elf_link_hash_lookup
16219 (elf_hash_table (info), "_TLS_MODULE_BASE_", TRUE, TRUE, FALSE);
16220
16221 if (tlsbase)
99059e56
RM		 16222 {
16223 struct bfd_link_hash_entry *bh = NULL;
0855e32b 16224 const struct elf_backend_data *bed
99059e56 16225 = get_elf_backend_data (output_bfd);
0855e32b 16226
99059e56 16227 if (!(_bfd_generic_link_add_one_symbol
0855e32b
NS		 16228 (info, output_bfd, "_TLS_MODULE_BASE_", BSF_LOCAL,
16229 tls_sec, 0, NULL, FALSE,
16230 bed->collect, &bh)))
16231 return FALSE;
b38cadfb 16232
99059e56
RM		 16233 tlsbase->type = STT_TLS;
16234 tlsbase = (struct elf_link_hash_entry *)bh;
16235 tlsbase->def_regular = 1;
16236 tlsbase->other = STV_HIDDEN;
16237 (*bed->elf_backend_hide_symbol) (info, tlsbase, TRUE);
0855e32b
NS		 16238 }
16239 }
16240 return TRUE;
16241}
16242
252b5132
RH		 16243/* Finish up dynamic symbol handling. We set the contents of various
16244 dynamic sections here. */
16245
b34976b6 16246static bfd_boolean
906e58ca
NC		 16247elf32_arm_finish_dynamic_symbol (bfd * output_bfd,
16248 struct bfd_link_info * info,
16249 struct elf_link_hash_entry * h,
16250 Elf_Internal_Sym * sym)
252b5132 16251{
e5a52504 16252 struct elf32_arm_link_hash_table *htab;
b7693d02 16253 struct elf32_arm_link_hash_entry *eh;
252b5132 16254
e5a52504 16255 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16256 if (htab == NULL)
16257 return FALSE;
16258
b7693d02 16259 eh = (struct elf32_arm_link_hash_entry *) h;
252b5132
RH		 16260
16261 if (h->plt.offset != (bfd_vma) -1)
16262 {
34e77a92 16263 if (!eh->is_iplt)
e5a52504 16264 {
34e77a92 16265 BFD_ASSERT (h->dynindx != -1);
57460bcf
NC		 16266 if (! elf32_arm_populate_plt_entry (output_bfd, info, &h->plt, &eh->plt,
16267 h->dynindx, 0))
16268 return FALSE;
e5a52504 16269 }
57e8b36a 16270
f5385ebf 16271 if (!h->def_regular)
252b5132
RH		 16272 {
16273 /* Mark the symbol as undefined, rather than as defined in
3a635617 16274 the .plt section. */
252b5132 16275 sym->st_shndx = SHN_UNDEF;
3a635617 16276 /* If the symbol is weak we need to clear the value.
d982ba73
PB		 16277 Otherwise, the PLT entry would provide a definition for
16278 the symbol even if the symbol wasn't defined anywhere,
3a635617
WN		 16279 and so the symbol would never be NULL. Leave the value if
16280 there were any relocations where pointer equality matters
16281 (this is a clue for the dynamic linker, to make function
16282 pointer comparisons work between an application and shared
16283 library). */
97323ad1 16284 if (!h->ref_regular_nonweak || !h->pointer_equality_needed)
d982ba73 16285 sym->st_value = 0;
252b5132 16286 }
34e77a92
RS		 16287 else if (eh->is_iplt && eh->plt.noncall_refcount != 0)
16288 {
16289 /* At least one non-call relocation references this .iplt entry,
16290 so the .iplt entry is the function's canonical address. */
16291 sym->st_info = ELF_ST_INFO (ELF_ST_BIND (sym->st_info), STT_FUNC);
39d911fc 16292 ARM_SET_SYM_BRANCH_TYPE (sym->st_target_internal, ST_BRANCH_TO_ARM);
34e77a92
RS		 16293 sym->st_shndx = (_bfd_elf_section_from_bfd_section
16294 (output_bfd, htab->root.iplt->output_section));
16295 sym->st_value = (h->plt.offset
16296 + htab->root.iplt->output_section->vma
16297 + htab->root.iplt->output_offset);
16298 }
252b5132
RH		 16299 }
16300
f5385ebf 16301 if (h->needs_copy)
252b5132
RH		 16302 {
16303 asection * s;
947216bf 16304 Elf_Internal_Rela rel;
252b5132
RH		 16305
16306 /* This symbol needs a copy reloc. Set it up. */
252b5132
RH		 16307 BFD_ASSERT (h->dynindx != -1
16308 && (h->root.type == bfd_link_hash_defined
16309 || h->root.type == bfd_link_hash_defweak));
16310
00a97672 16311 rel.r_addend = 0;
252b5132
RH		 16312 rel.r_offset = (h->root.u.def.value
16313 + h->root.u.def.section->output_section->vma
16314 + h->root.u.def.section->output_offset);
16315 rel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_COPY);
afbf7e8e 16316 if (h->root.u.def.section == htab->root.sdynrelro)
5474d94f
AM		 16317 s = htab->root.sreldynrelro;
16318 else
16319 s = htab->root.srelbss;
47beaa6a 16320 elf32_arm_add_dynreloc (output_bfd, info, s, &rel);
252b5132
RH		 16321 }
16322
00a97672
RS		 16323 /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. On VxWorks,
16324 the _GLOBAL_OFFSET_TABLE_ symbol is not absolute: it is relative
16325 to the ".got" section. */
9637f6ef 16326 if (h == htab->root.hdynamic
00a97672 16327 || (!htab->vxworks_p && h == htab->root.hgot))
252b5132
RH		 16328 sym->st_shndx = SHN_ABS;
16329
b34976b6 16330 return TRUE;
252b5132
RH		 16331}
16332
0855e32b
NS		 16333static void
16334arm_put_trampoline (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
16335 void *contents,
16336 const unsigned long *template, unsigned count)
16337{
16338 unsigned ix;
b38cadfb 16339
0855e32b
NS		 16340 for (ix = 0; ix != count; ix++)
16341 {
16342 unsigned long insn = template[ix];
16343
16344 /* Emit mov pc,rx if bx is not permitted. */
16345 if (htab->fix_v4bx == 1 && (insn & 0x0ffffff0) == 0x012fff10)
16346 insn = (insn & 0xf000000f) | 0x01a0f000;
16347 put_arm_insn (htab, output_bfd, insn, (char *)contents + ix*4);
16348 }
16349}
16350
99059e56
RM		 16351/* Install the special first PLT entry for elf32-arm-nacl. Unlike
16352 other variants, NaCl needs this entry in a static executable's
16353 .iplt too. When we're handling that case, GOT_DISPLACEMENT is
16354 zero. For .iplt really only the last bundle is useful, and .iplt
16355 could have a shorter first entry, with each individual PLT entry's
16356 relative branch calculated differently so it targets the last
16357 bundle instead of the instruction before it (labelled .Lplt_tail
16358 above). But it's simpler to keep the size and layout of PLT0
16359 consistent with the dynamic case, at the cost of some dead code at
16360 the start of .iplt and the one dead store to the stack at the start
16361 of .Lplt_tail. */
16362static void
16363arm_nacl_put_plt0 (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
16364 asection *plt, bfd_vma got_displacement)
16365{
16366 unsigned int i;
16367
16368 put_arm_insn (htab, output_bfd,
16369 elf32_arm_nacl_plt0_entry[0]
16370 | arm_movw_immediate (got_displacement),
16371 plt->contents + 0);
16372 put_arm_insn (htab, output_bfd,
16373 elf32_arm_nacl_plt0_entry[1]
16374 | arm_movt_immediate (got_displacement),
16375 plt->contents + 4);
16376
16377 for (i = 2; i < ARRAY_SIZE (elf32_arm_nacl_plt0_entry); ++i)
16378 put_arm_insn (htab, output_bfd,
16379 elf32_arm_nacl_plt0_entry[i],
16380 plt->contents + (i * 4));
16381}
16382
252b5132
RH		 16383/* Finish up the dynamic sections. */
16384
b34976b6 16385static bfd_boolean
57e8b36a 16386elf32_arm_finish_dynamic_sections (bfd * output_bfd, struct bfd_link_info * info)
252b5132
RH		 16387{
16388 bfd * dynobj;
16389 asection * sgot;
16390 asection * sdyn;
4dfe6ac6
NC		 16391 struct elf32_arm_link_hash_table *htab;
16392
16393 htab = elf32_arm_hash_table (info);
16394 if (htab == NULL)
16395 return FALSE;
252b5132
RH		 16396
16397 dynobj = elf_hash_table (info)->dynobj;
16398
362d30a1 16399 sgot = htab->root.sgotplt;
894891db
NC		 16400 /* A broken linker script might have discarded the dynamic sections.
16401 Catch this here so that we do not seg-fault later on. */
16402 if (sgot != NULL && bfd_is_abs_section (sgot->output_section))
16403 return FALSE;
3d4d4302 16404 sdyn = bfd_get_linker_section (dynobj, ".dynamic");
252b5132
RH		 16405
16406 if (elf_hash_table (info)->dynamic_sections_created)
16407 {
16408 asection *splt;
16409 Elf32_External_Dyn *dyncon, *dynconend;
16410
362d30a1 16411 splt = htab->root.splt;
24a1ba0f 16412 BFD_ASSERT (splt != NULL && sdyn != NULL);
cbc704f3 16413 BFD_ASSERT (htab->symbian_p || sgot != NULL);
252b5132
RH		 16414
16415 dyncon = (Elf32_External_Dyn *) sdyn->contents;
eea6121a 16416 dynconend = (Elf32_External_Dyn *) (sdyn->contents + sdyn->size);
9b485d32 16417
252b5132
RH		 16418 for (; dyncon < dynconend; dyncon++)
16419 {
16420 Elf_Internal_Dyn dyn;
16421 const char * name;
16422 asection * s;
16423
16424 bfd_elf32_swap_dyn_in (dynobj, dyncon, &dyn);
16425
16426 switch (dyn.d_tag)
16427 {
229fcec5
MM		 16428 unsigned int type;
16429
252b5132 16430 default:
7a2b07ff
NS		 16431 if (htab->vxworks_p
16432 && elf_vxworks_finish_dynamic_entry (output_bfd, &dyn))
16433 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
252b5132
RH		 16434 break;
16435
229fcec5
MM		 16436 case DT_HASH:
16437 name = ".hash";
16438 goto get_vma_if_bpabi;
16439 case DT_STRTAB:
16440 name = ".dynstr";
16441 goto get_vma_if_bpabi;
16442 case DT_SYMTAB:
16443 name = ".dynsym";
16444 goto get_vma_if_bpabi;
c0042f5d
MM		 16445 case DT_VERSYM:
16446 name = ".gnu.version";
16447 goto get_vma_if_bpabi;
16448 case DT_VERDEF:
16449 name = ".gnu.version_d";
16450 goto get_vma_if_bpabi;
16451 case DT_VERNEED:
16452 name = ".gnu.version_r";
16453 goto get_vma_if_bpabi;
16454
252b5132 16455 case DT_PLTGOT:
4ade44b7 16456 name = htab->symbian_p ? ".got" : ".got.plt";
252b5132
RH		 16457 goto get_vma;
16458 case DT_JMPREL:
00a97672 16459 name = RELOC_SECTION (htab, ".plt");
252b5132 16460 get_vma:
4ade44b7 16461 s = bfd_get_linker_section (dynobj, name);
05456594
NC		 16462 if (s == NULL)
16463 {
4eca0228 16464 _bfd_error_handler
4ade44b7 16465 (_("could not find section %s"), name);
05456594
NC		 16466 bfd_set_error (bfd_error_invalid_operation);
16467 return FALSE;
16468 }
229fcec5 16469 if (!htab->symbian_p)
4ade44b7 16470 dyn.d_un.d_ptr = s->output_section->vma + s->output_offset;
229fcec5
MM		 16471 else
16472 /* In the BPABI, tags in the PT_DYNAMIC section point
16473 at the file offset, not the memory address, for the
16474 convenience of the post linker. */
4ade44b7 16475 dyn.d_un.d_ptr = s->output_section->filepos + s->output_offset;
252b5132
RH		 16476 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16477 break;
16478
229fcec5
MM		 16479 get_vma_if_bpabi:
16480 if (htab->symbian_p)
16481 goto get_vma;
16482 break;
16483
252b5132 16484 case DT_PLTRELSZ:
362d30a1 16485 s = htab->root.srelplt;
252b5132 16486 BFD_ASSERT (s != NULL);
eea6121a 16487 dyn.d_un.d_val = s->size;
252b5132
RH		 16488 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16489 break;
906e58ca 16490
252b5132 16491 case DT_RELSZ:
00a97672 16492 case DT_RELASZ:
229fcec5
MM		 16493 case DT_REL:
16494 case DT_RELA:
229fcec5
MM		 16495 /* In the BPABI, the DT_REL tag must point at the file
16496 offset, not the VMA, of the first relocation
16497 section. So, we use code similar to that in
16498 elflink.c, but do not check for SHF_ALLOC on the
64f52338
AM		 16499 relocation section, since relocation sections are
16500 never allocated under the BPABI. PLT relocs are also
16501 included. */
229fcec5
MM		 16502 if (htab->symbian_p)
16503 {
16504 unsigned int i;
16505 type = ((dyn.d_tag == DT_REL || dyn.d_tag == DT_RELSZ)
16506 ? SHT_REL : SHT_RELA);
16507 dyn.d_un.d_val = 0;
16508 for (i = 1; i < elf_numsections (output_bfd); i++)
16509 {
906e58ca 16510 Elf_Internal_Shdr *hdr
229fcec5
MM		 16511 = elf_elfsections (output_bfd)[i];
16512 if (hdr->sh_type == type)
16513 {
906e58ca 16514 if (dyn.d_tag == DT_RELSZ
229fcec5
MM		 16515 || dyn.d_tag == DT_RELASZ)
16516 dyn.d_un.d_val += hdr->sh_size;
de52dba4
AM		 16517 else if ((ufile_ptr) hdr->sh_offset
16518 <= dyn.d_un.d_val - 1)
229fcec5
MM		 16519 dyn.d_un.d_val = hdr->sh_offset;
16520 }
16521 }
16522 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16523 }
252b5132 16524 break;
88f7bcd5 16525
0855e32b 16526 case DT_TLSDESC_PLT:
99059e56 16527 s = htab->root.splt;
0855e32b
NS		 16528 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
16529 + htab->dt_tlsdesc_plt);
16530 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16531 break;
16532
16533 case DT_TLSDESC_GOT:
99059e56 16534 s = htab->root.sgot;
0855e32b 16535 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
99059e56 16536 + htab->dt_tlsdesc_got);
0855e32b
NS		 16537 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16538 break;
16539
88f7bcd5
NC		 16540 /* Set the bottom bit of DT_INIT/FINI if the
16541 corresponding function is Thumb. */
16542 case DT_INIT:
16543 name = info->init_function;
16544 goto get_sym;
16545 case DT_FINI:
16546 name = info->fini_function;
16547 get_sym:
16548 /* If it wasn't set by elf_bfd_final_link
4cc11e76 16549 then there is nothing to adjust. */
88f7bcd5
NC		 16550 if (dyn.d_un.d_val != 0)
16551 {
16552 struct elf_link_hash_entry * eh;
16553
16554 eh = elf_link_hash_lookup (elf_hash_table (info), name,
b34976b6 16555 FALSE, FALSE, TRUE);
39d911fc
TP		 16556 if (eh != NULL
16557 && ARM_GET_SYM_BRANCH_TYPE (eh->target_internal)
16558 == ST_BRANCH_TO_THUMB)
88f7bcd5
NC		 16559 {
16560 dyn.d_un.d_val |= 1;
b34976b6 16561 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
88f7bcd5
NC		 16562 }
16563 }
16564 break;
252b5132
RH		 16565 }
16566 }
16567
24a1ba0f 16568 /* Fill in the first entry in the procedure linkage table. */
4dfe6ac6 16569 if (splt->size > 0 && htab->plt_header_size)
f7a74f8c 16570 {
00a97672
RS		 16571 const bfd_vma *plt0_entry;
16572 bfd_vma got_address, plt_address, got_displacement;
16573
16574 /* Calculate the addresses of the GOT and PLT. */
16575 got_address = sgot->output_section->vma + sgot->output_offset;
16576 plt_address = splt->output_section->vma + splt->output_offset;
16577
16578 if (htab->vxworks_p)
16579 {
16580 /* The VxWorks GOT is relocated by the dynamic linker.
16581 Therefore, we must emit relocations rather than simply
16582 computing the values now. */
16583 Elf_Internal_Rela rel;
16584
16585 plt0_entry = elf32_arm_vxworks_exec_plt0_entry;
52ab56c2
PB		 16586 put_arm_insn (htab, output_bfd, plt0_entry[0],
16587 splt->contents + 0);
16588 put_arm_insn (htab, output_bfd, plt0_entry[1],
16589 splt->contents + 4);
16590 put_arm_insn (htab, output_bfd, plt0_entry[2],
16591 splt->contents + 8);
00a97672
RS		 16592 bfd_put_32 (output_bfd, got_address, splt->contents + 12);
16593
8029a119 16594 /* Generate a relocation for _GLOBAL_OFFSET_TABLE_. */
00a97672
RS		 16595 rel.r_offset = plt_address + 12;
16596 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
16597 rel.r_addend = 0;
16598 SWAP_RELOC_OUT (htab) (output_bfd, &rel,
16599 htab->srelplt2->contents);
16600 }
b38cadfb 16601 else if (htab->nacl_p)
99059e56
RM		 16602 arm_nacl_put_plt0 (htab, output_bfd, splt,
16603 got_address + 8 - (plt_address + 16));
eed94f8f
NC		 16604 else if (using_thumb_only (htab))
16605 {
16606 got_displacement = got_address - (plt_address + 12);
16607
16608 plt0_entry = elf32_thumb2_plt0_entry;
16609 put_arm_insn (htab, output_bfd, plt0_entry[0],
16610 splt->contents + 0);
16611 put_arm_insn (htab, output_bfd, plt0_entry[1],
16612 splt->contents + 4);
16613 put_arm_insn (htab, output_bfd, plt0_entry[2],
16614 splt->contents + 8);
16615
16616 bfd_put_32 (output_bfd, got_displacement, splt->contents + 12);
16617 }
00a97672
RS		 16618 else
16619 {
16620 got_displacement = got_address - (plt_address + 16);
16621
16622 plt0_entry = elf32_arm_plt0_entry;
52ab56c2
PB		 16623 put_arm_insn (htab, output_bfd, plt0_entry[0],
16624 splt->contents + 0);
16625 put_arm_insn (htab, output_bfd, plt0_entry[1],
16626 splt->contents + 4);
16627 put_arm_insn (htab, output_bfd, plt0_entry[2],
16628 splt->contents + 8);
16629 put_arm_insn (htab, output_bfd, plt0_entry[3],
16630 splt->contents + 12);
5e681ec4 16631
5e681ec4 16632#ifdef FOUR_WORD_PLT
00a97672
RS		 16633 /* The displacement value goes in the otherwise-unused
16634 last word of the second entry. */
16635 bfd_put_32 (output_bfd, got_displacement, splt->contents + 28);
5e681ec4 16636#else
00a97672 16637 bfd_put_32 (output_bfd, got_displacement, splt->contents + 16);
5e681ec4 16638#endif
00a97672 16639 }
f7a74f8c 16640 }
252b5132
RH		 16641
16642 /* UnixWare sets the entsize of .plt to 4, although that doesn't
16643 really seem like the right value. */
74541ad4
AM		 16644 if (splt->output_section->owner == output_bfd)
16645 elf_section_data (splt->output_section)->this_hdr.sh_entsize = 4;
00a97672 16646
0855e32b
NS		 16647 if (htab->dt_tlsdesc_plt)
16648 {
16649 bfd_vma got_address
16650 = sgot->output_section->vma + sgot->output_offset;
16651 bfd_vma gotplt_address = (htab->root.sgot->output_section->vma
16652 + htab->root.sgot->output_offset);
16653 bfd_vma plt_address
16654 = splt->output_section->vma + splt->output_offset;
16655
b38cadfb 16656 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 16657 splt->contents + htab->dt_tlsdesc_plt,
16658 dl_tlsdesc_lazy_trampoline, 6);
16659
16660 bfd_put_32 (output_bfd,
16661 gotplt_address + htab->dt_tlsdesc_got
16662 - (plt_address + htab->dt_tlsdesc_plt)
16663 - dl_tlsdesc_lazy_trampoline[6],
16664 splt->contents + htab->dt_tlsdesc_plt + 24);
16665 bfd_put_32 (output_bfd,
16666 got_address - (plt_address + htab->dt_tlsdesc_plt)
16667 - dl_tlsdesc_lazy_trampoline[7],
16668 splt->contents + htab->dt_tlsdesc_plt + 24 + 4);
16669 }
16670
16671 if (htab->tls_trampoline)
16672 {
b38cadfb 16673 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 16674 splt->contents + htab->tls_trampoline,
16675 tls_trampoline, 3);
16676#ifdef FOUR_WORD_PLT
16677 bfd_put_32 (output_bfd, 0x00000000,
16678 splt->contents + htab->tls_trampoline + 12);
b38cadfb 16679#endif
0855e32b
NS		 16680 }
16681
0e1862bb
L		 16682 if (htab->vxworks_p
16683 && !bfd_link_pic (info)
16684 && htab->root.splt->size > 0)
00a97672
RS		 16685 {
16686 /* Correct the .rel(a).plt.unloaded relocations. They will have
16687 incorrect symbol indexes. */
16688 int num_plts;
eed62c48 16689 unsigned char *p;
00a97672 16690
362d30a1 16691 num_plts = ((htab->root.splt->size - htab->plt_header_size)
00a97672
RS		 16692 / htab->plt_entry_size);
16693 p = htab->srelplt2->contents + RELOC_SIZE (htab);
16694
16695 for (; num_plts; num_plts--)
16696 {
16697 Elf_Internal_Rela rel;
16698
16699 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
16700 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
16701 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
16702 p += RELOC_SIZE (htab);
16703
16704 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
16705 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
16706 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
16707 p += RELOC_SIZE (htab);
16708 }
16709 }
252b5132
RH		 16710 }
16711
99059e56
RM		 16712 if (htab->nacl_p && htab->root.iplt != NULL && htab->root.iplt->size > 0)
16713 /* NaCl uses a special first entry in .iplt too. */
16714 arm_nacl_put_plt0 (htab, output_bfd, htab->root.iplt, 0);
16715
252b5132 16716 /* Fill in the first three entries in the global offset table. */
229fcec5 16717 if (sgot)
252b5132 16718 {
229fcec5
MM		 16719 if (sgot->size > 0)
16720 {
16721 if (sdyn == NULL)
16722 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents);
16723 else
16724 bfd_put_32 (output_bfd,
16725 sdyn->output_section->vma + sdyn->output_offset,
16726 sgot->contents);
16727 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 4);
16728 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 8);
16729 }
252b5132 16730
229fcec5
MM		 16731 elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4;
16732 }
252b5132 16733
b34976b6 16734 return TRUE;
252b5132
RH		 16735}
16736
ba96a88f 16737static void
57e8b36a 16738elf32_arm_post_process_headers (bfd * abfd, struct bfd_link_info * link_info ATTRIBUTE_UNUSED)
ba96a88f 16739{
9b485d32 16740 Elf_Internal_Ehdr * i_ehdrp; /* ELF file header, internal form. */
e489d0ae 16741 struct elf32_arm_link_hash_table *globals;
ac4c9b04 16742 struct elf_segment_map *m;
ba96a88f
NC		 16743
16744 i_ehdrp = elf_elfheader (abfd);
16745
94a3258f
PB		 16746 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_UNKNOWN)
16747 i_ehdrp->e_ident[EI_OSABI] = ELFOSABI_ARM;
16748 else
7394f108 16749 _bfd_elf_post_process_headers (abfd, link_info);
ba96a88f 16750 i_ehdrp->e_ident[EI_ABIVERSION] = ARM_ELF_ABI_VERSION;
e489d0ae 16751
93204d3a
PB		 16752 if (link_info)
16753 {
16754 globals = elf32_arm_hash_table (link_info);
4dfe6ac6 16755 if (globals != NULL && globals->byteswap_code)
93204d3a
PB		 16756 i_ehdrp->e_flags |= EF_ARM_BE8;
16757 }
3bfcb652
NC		 16758
16759 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_VER5
16760 && ((i_ehdrp->e_type == ET_DYN) || (i_ehdrp->e_type == ET_EXEC)))
16761 {
16762 int abi = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_ABI_VFP_args);
5c294fee 16763 if (abi == AEABI_VFP_args_vfp)
3bfcb652
NC		 16764 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_HARD;
16765 else
16766 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_SOFT;
16767 }
ac4c9b04
MG		 16768
16769 /* Scan segment to set p_flags attribute if it contains only sections with
f0728ee3 16770 SHF_ARM_PURECODE flag. */
ac4c9b04
MG		 16771 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
16772 {
16773 unsigned int j;
16774
16775 if (m->count == 0)
16776 continue;
16777 for (j = 0; j < m->count; j++)
16778 {
f0728ee3 16779 if (!(elf_section_flags (m->sections[j]) & SHF_ARM_PURECODE))
ac4c9b04
MG		 16780 break;
16781 }
16782 if (j == m->count)
16783 {
16784 m->p_flags = PF_X;
16785 m->p_flags_valid = 1;
16786 }
16787 }
ba96a88f
NC		 16788}
16789
99e4ae17 16790static enum elf_reloc_type_class
7e612e98
AM		 16791elf32_arm_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UNUSED,
16792 const asection *rel_sec ATTRIBUTE_UNUSED,
16793 const Elf_Internal_Rela *rela)
99e4ae17 16794{
f51e552e 16795 switch ((int) ELF32_R_TYPE (rela->r_info))
99e4ae17
AJ		 16796 {
16797 case R_ARM_RELATIVE:
16798 return reloc_class_relative;
16799 case R_ARM_JUMP_SLOT:
16800 return reloc_class_plt;
16801 case R_ARM_COPY:
16802 return reloc_class_copy;
109575d7
JW		 16803 case R_ARM_IRELATIVE:
16804 return reloc_class_ifunc;
99e4ae17
AJ		 16805 default:
16806 return reloc_class_normal;
16807 }
16808}
16809
e489d0ae 16810static void
57e8b36a 16811elf32_arm_final_write_processing (bfd *abfd, bfd_boolean linker ATTRIBUTE_UNUSED)
e16bb312 16812{
5a6c6817 16813 bfd_arm_update_notes (abfd, ARM_NOTE_SECTION);
e16bb312
NC		 16814}
16815
40a18ebd
NC		 16816/* Return TRUE if this is an unwinding table entry. */
16817
16818static bfd_boolean
16819is_arm_elf_unwind_section_name (bfd * abfd ATTRIBUTE_UNUSED, const char * name)
16820{
0112cd26
NC		 16821 return (CONST_STRNEQ (name, ELF_STRING_ARM_unwind)
16822 || CONST_STRNEQ (name, ELF_STRING_ARM_unwind_once));
40a18ebd
NC		 16823}
16824
16825
16826/* Set the type and flags for an ARM section. We do this by
16827 the section name, which is a hack, but ought to work. */
16828
16829static bfd_boolean
16830elf32_arm_fake_sections (bfd * abfd, Elf_Internal_Shdr * hdr, asection * sec)
16831{
16832 const char * name;
16833
16834 name = bfd_get_section_name (abfd, sec);
16835
16836 if (is_arm_elf_unwind_section_name (abfd, name))
16837 {
16838 hdr->sh_type = SHT_ARM_EXIDX;
16839 hdr->sh_flags |= SHF_LINK_ORDER;
16840 }
ac4c9b04 16841
f0728ee3
AV		 16842 if (sec->flags & SEC_ELF_PURECODE)
16843 hdr->sh_flags |= SHF_ARM_PURECODE;
ac4c9b04 16844
40a18ebd
NC		 16845 return TRUE;
16846}
16847
6dc132d9
L		 16848/* Handle an ARM specific section when reading an object file. This is
16849 called when bfd_section_from_shdr finds a section with an unknown
16850 type. */
40a18ebd
NC		 16851
16852static bfd_boolean
16853elf32_arm_section_from_shdr (bfd *abfd,
16854 Elf_Internal_Shdr * hdr,
6dc132d9
L		 16855 const char *name,
16856 int shindex)
40a18ebd
NC		 16857{
16858 /* There ought to be a place to keep ELF backend specific flags, but
16859 at the moment there isn't one. We just keep track of the
16860 sections by their name, instead. Fortunately, the ABI gives
16861 names for all the ARM specific sections, so we will probably get
16862 away with this. */
16863 switch (hdr->sh_type)
16864 {
16865 case SHT_ARM_EXIDX:
0951f019
RE		 16866 case SHT_ARM_PREEMPTMAP:
16867 case SHT_ARM_ATTRIBUTES:
40a18ebd
NC		 16868 break;
16869
16870 default:
16871 return FALSE;
16872 }
16873
6dc132d9 16874 if (! _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex))
40a18ebd
NC		 16875 return FALSE;
16876
16877 return TRUE;
16878}
e489d0ae 16879
44444f50
NC		 16880static _arm_elf_section_data *
16881get_arm_elf_section_data (asection * sec)
16882{
47b2e99c
JZ		 16883 if (sec && sec->owner && is_arm_elf (sec->owner))
16884 return elf32_arm_section_data (sec);
44444f50
NC		 16885 else
16886 return NULL;
8e3de13a
NC		 16887}
16888
4e617b1e
PB		 16889typedef struct
16890{
57402f1e 16891 void *flaginfo;
4e617b1e 16892 struct bfd_link_info *info;
91a5743d
PB		 16893 asection *sec;
16894 int sec_shndx;
6e0b88f1
AM		 16895 int (*func) (void *, const char *, Elf_Internal_Sym *,
16896 asection *, struct elf_link_hash_entry *);
4e617b1e
PB		 16897} output_arch_syminfo;
16898
16899enum map_symbol_type
16900{
16901 ARM_MAP_ARM,
16902 ARM_MAP_THUMB,
16903 ARM_MAP_DATA
16904};
16905
16906
7413f23f 16907/* Output a single mapping symbol. */
4e617b1e
PB		 16908
16909static bfd_boolean
7413f23f
DJ		 16910elf32_arm_output_map_sym (output_arch_syminfo *osi,
16911 enum map_symbol_type type,
16912 bfd_vma offset)
4e617b1e
PB		 16913{
16914 static const char *names[3] = {"$a", "$t", "$d"};
4e617b1e
PB		 16915 Elf_Internal_Sym sym;
16916
91a5743d
PB		 16917 sym.st_value = osi->sec->output_section->vma
16918 + osi->sec->output_offset
16919 + offset;
4e617b1e
PB		 16920 sym.st_size = 0;
16921 sym.st_other = 0;
16922 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
91a5743d 16923 sym.st_shndx = osi->sec_shndx;
35fc36a8 16924 sym.st_target_internal = 0;
fe33d2fa 16925 elf32_arm_section_map_add (osi->sec, names[type][1], offset);
57402f1e 16926 return osi->func (osi->flaginfo, names[type], &sym, osi->sec, NULL) == 1;
4e617b1e
PB		 16927}
16928
34e77a92
RS		 16929/* Output mapping symbols for the PLT entry described by ROOT_PLT and ARM_PLT.
16930 IS_IPLT_ENTRY_P says whether the PLT is in .iplt rather than .plt. */
4e617b1e
PB		 16931
16932static bfd_boolean
34e77a92
RS		 16933elf32_arm_output_plt_map_1 (output_arch_syminfo *osi,
16934 bfd_boolean is_iplt_entry_p,
16935 union gotplt_union *root_plt,
16936 struct arm_plt_info *arm_plt)
4e617b1e 16937{
4e617b1e 16938 struct elf32_arm_link_hash_table *htab;
34e77a92 16939 bfd_vma addr, plt_header_size;
4e617b1e 16940
34e77a92 16941 if (root_plt->offset == (bfd_vma) -1)
4e617b1e
PB		 16942 return TRUE;
16943
4dfe6ac6
NC		 16944 htab = elf32_arm_hash_table (osi->info);
16945 if (htab == NULL)
16946 return FALSE;
16947
34e77a92
RS		 16948 if (is_iplt_entry_p)
16949 {
16950 osi->sec = htab->root.iplt;
16951 plt_header_size = 0;
16952 }
16953 else
16954 {
16955 osi->sec = htab->root.splt;
16956 plt_header_size = htab->plt_header_size;
16957 }
16958 osi->sec_shndx = (_bfd_elf_section_from_bfd_section
16959 (osi->info->output_bfd, osi->sec->output_section));
16960
16961 addr = root_plt->offset & -2;
4e617b1e
PB		 16962 if (htab->symbian_p)
16963 {
7413f23f 16964 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 16965 return FALSE;
7413f23f 16966 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 4))
4e617b1e
PB		 16967 return FALSE;
16968 }
16969 else if (htab->vxworks_p)
16970 {
7413f23f 16971 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 16972 return FALSE;
7413f23f 16973 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 8))
4e617b1e 16974 return FALSE;
7413f23f 16975 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr + 12))
4e617b1e 16976 return FALSE;
7413f23f 16977 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 20))
4e617b1e
PB		 16978 return FALSE;
16979 }
b38cadfb
NC		 16980 else if (htab->nacl_p)
16981 {
16982 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
16983 return FALSE;
16984 }
eed94f8f
NC		 16985 else if (using_thumb_only (htab))
16986 {
16987 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr))
16988 return FALSE;
6a631e86 16989 }
4e617b1e
PB		 16990 else
16991 {
34e77a92 16992 bfd_boolean thumb_stub_p;
bd97cb95 16993
34e77a92
RS		 16994 thumb_stub_p = elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt);
16995 if (thumb_stub_p)
4e617b1e 16996 {
7413f23f 16997 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
4e617b1e
PB		 16998 return FALSE;
16999 }
17000#ifdef FOUR_WORD_PLT
7413f23f 17001 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 17002 return FALSE;
7413f23f 17003 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 12))
4e617b1e
PB		 17004 return FALSE;
17005#else
906e58ca 17006 /* A three-word PLT with no Thumb thunk contains only Arm code,
4e617b1e
PB		 17007 so only need to output a mapping symbol for the first PLT entry and
17008 entries with thumb thunks. */
34e77a92 17009 if (thumb_stub_p || addr == plt_header_size)
4e617b1e 17010 {
7413f23f 17011 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e
PB		 17012 return FALSE;
17013 }
17014#endif
17015 }
17016
17017 return TRUE;
17018}
17019
34e77a92
RS		 17020/* Output mapping symbols for PLT entries associated with H. */
17021
17022static bfd_boolean
17023elf32_arm_output_plt_map (struct elf_link_hash_entry *h, void *inf)
17024{
17025 output_arch_syminfo *osi = (output_arch_syminfo *) inf;
17026 struct elf32_arm_link_hash_entry *eh;
17027
17028 if (h->root.type == bfd_link_hash_indirect)
17029 return TRUE;
17030
17031 if (h->root.type == bfd_link_hash_warning)
17032 /* When warning symbols are created, they **replace** the "real"
17033 entry in the hash table, thus we never get to see the real
17034 symbol in a hash traversal. So look at it now. */
17035 h = (struct elf_link_hash_entry *) h->root.u.i.link;
17036
17037 eh = (struct elf32_arm_link_hash_entry *) h;
17038 return elf32_arm_output_plt_map_1 (osi, SYMBOL_CALLS_LOCAL (osi->info, h),
17039 &h->plt, &eh->plt);
17040}
17041
4f4faa4d
TP		 17042/* Bind a veneered symbol to its veneer identified by its hash entry
17043 STUB_ENTRY. The veneered location thus loose its symbol. */
17044
17045static void
17046arm_stub_claim_sym (struct elf32_arm_stub_hash_entry *stub_entry)
17047{
17048 struct elf32_arm_link_hash_entry *hash = stub_entry->h;
17049
17050 BFD_ASSERT (hash);
17051 hash->root.root.u.def.section = stub_entry->stub_sec;
17052 hash->root.root.u.def.value = stub_entry->stub_offset;
17053 hash->root.size = stub_entry->stub_size;
17054}
17055
7413f23f
DJ		 17056/* Output a single local symbol for a generated stub. */
17057
17058static bfd_boolean
17059elf32_arm_output_stub_sym (output_arch_syminfo *osi, const char *name,
17060 bfd_vma offset, bfd_vma size)
17061{
7413f23f
DJ		 17062 Elf_Internal_Sym sym;
17063
7413f23f
DJ		 17064 sym.st_value = osi->sec->output_section->vma
17065 + osi->sec->output_offset
17066 + offset;
17067 sym.st_size = size;
17068 sym.st_other = 0;
17069 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
17070 sym.st_shndx = osi->sec_shndx;
35fc36a8 17071 sym.st_target_internal = 0;
57402f1e 17072 return osi->func (osi->flaginfo, name, &sym, osi->sec, NULL) == 1;
7413f23f 17073}
4e617b1e 17074
da5938a2 17075static bfd_boolean
8029a119
NC		 17076arm_map_one_stub (struct bfd_hash_entry * gen_entry,
17077 void * in_arg)
da5938a2
NC		 17078{
17079 struct elf32_arm_stub_hash_entry *stub_entry;
da5938a2
NC		 17080 asection *stub_sec;
17081 bfd_vma addr;
7413f23f 17082 char *stub_name;
9a008db3 17083 output_arch_syminfo *osi;
d3ce72d0 17084 const insn_sequence *template_sequence;
461a49ca
DJ		 17085 enum stub_insn_type prev_type;
17086 int size;
17087 int i;
17088 enum map_symbol_type sym_type;
da5938a2
NC		 17089
17090 /* Massage our args to the form they really have. */
17091 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
9a008db3 17092 osi = (output_arch_syminfo *) in_arg;
da5938a2 17093
da5938a2
NC		 17094 stub_sec = stub_entry->stub_sec;
17095
17096 /* Ensure this stub is attached to the current section being
7413f23f 17097 processed. */
da5938a2
NC		 17098 if (stub_sec != osi->sec)
17099 return TRUE;
17100
7413f23f 17101 addr = (bfd_vma) stub_entry->stub_offset;
d3ce72d0 17102 template_sequence = stub_entry->stub_template;
4f4faa4d
TP		 17103
17104 if (arm_stub_sym_claimed (stub_entry->stub_type))
17105 arm_stub_claim_sym (stub_entry);
17106 else
7413f23f 17107 {
4f4faa4d
TP		 17108 stub_name = stub_entry->output_name;
17109 switch (template_sequence[0].type)
17110 {
17111 case ARM_TYPE:
17112 if (!elf32_arm_output_stub_sym (osi, stub_name, addr,
17113 stub_entry->stub_size))
17114 return FALSE;
17115 break;
17116 case THUMB16_TYPE:
17117 case THUMB32_TYPE:
17118 if (!elf32_arm_output_stub_sym (osi, stub_name, addr | 1,
17119 stub_entry->stub_size))
17120 return FALSE;
17121 break;
17122 default:
17123 BFD_FAIL ();
17124 return 0;
17125 }
7413f23f 17126 }
da5938a2 17127
461a49ca
DJ		 17128 prev_type = DATA_TYPE;
17129 size = 0;
17130 for (i = 0; i < stub_entry->stub_template_size; i++)
17131 {
d3ce72d0 17132 switch (template_sequence[i].type)
461a49ca
DJ		 17133 {
17134 case ARM_TYPE:
17135 sym_type = ARM_MAP_ARM;
17136 break;
17137
17138 case THUMB16_TYPE:
48229727 17139 case THUMB32_TYPE:
461a49ca
DJ		 17140 sym_type = ARM_MAP_THUMB;
17141 break;
17142
17143 case DATA_TYPE:
17144 sym_type = ARM_MAP_DATA;
17145 break;
17146
17147 default:
17148 BFD_FAIL ();
4e31c731 17149 return FALSE;
461a49ca
DJ		 17150 }
17151
d3ce72d0 17152 if (template_sequence[i].type != prev_type)
461a49ca 17153 {
d3ce72d0 17154 prev_type = template_sequence[i].type;
461a49ca
DJ		 17155 if (!elf32_arm_output_map_sym (osi, sym_type, addr + size))
17156 return FALSE;
17157 }
17158
d3ce72d0 17159 switch (template_sequence[i].type)
461a49ca
DJ		 17160 {
17161 case ARM_TYPE:
48229727 17162 case THUMB32_TYPE:
461a49ca
DJ		 17163 size += 4;
17164 break;
17165
17166 case THUMB16_TYPE:
17167 size += 2;
17168 break;
17169
17170 case DATA_TYPE:
17171 size += 4;
17172 break;
17173
17174 default:
17175 BFD_FAIL ();
4e31c731 17176 return FALSE;
461a49ca
DJ		 17177 }
17178 }
17179
da5938a2
NC		 17180 return TRUE;
17181}
17182
33811162
DG		 17183/* Output mapping symbols for linker generated sections,
17184 and for those data-only sections that do not have a
17185 $d. */
4e617b1e
PB		 17186
17187static bfd_boolean
17188elf32_arm_output_arch_local_syms (bfd *output_bfd,
906e58ca 17189 struct bfd_link_info *info,
57402f1e 17190 void *flaginfo,
6e0b88f1
AM		 17191 int (*func) (void *, const char *,
17192 Elf_Internal_Sym *,
17193 asection *,
17194 struct elf_link_hash_entry *))
4e617b1e
PB		 17195{
17196 output_arch_syminfo osi;
17197 struct elf32_arm_link_hash_table *htab;
91a5743d
PB		 17198 bfd_vma offset;
17199 bfd_size_type size;
33811162 17200 bfd *input_bfd;
4e617b1e
PB		 17201
17202 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 17203 if (htab == NULL)
17204 return FALSE;
17205
906e58ca 17206 check_use_blx (htab);
91a5743d 17207
57402f1e 17208 osi.flaginfo = flaginfo;
4e617b1e
PB		 17209 osi.info = info;
17210 osi.func = func;
906e58ca 17211
33811162
DG		 17212 /* Add a $d mapping symbol to data-only sections that
17213 don't have any mapping symbol. This may result in (harmless) redundant
17214 mapping symbols. */
17215 for (input_bfd = info->input_bfds;
17216 input_bfd != NULL;
c72f2fb2 17217 input_bfd = input_bfd->link.next)
33811162
DG		 17218 {
17219 if ((input_bfd->flags & (BFD_LINKER_CREATED | HAS_SYMS)) == HAS_SYMS)
17220 for (osi.sec = input_bfd->sections;
17221 osi.sec != NULL;
17222 osi.sec = osi.sec->next)
17223 {
17224 if (osi.sec->output_section != NULL
f7dd8c79
DJ		 17225 && ((osi.sec->output_section->flags & (SEC_ALLOC | SEC_CODE))
17226 != 0)
33811162
DG		 17227 && (osi.sec->flags & (SEC_HAS_CONTENTS | SEC_LINKER_CREATED))
17228 == SEC_HAS_CONTENTS
17229 && get_arm_elf_section_data (osi.sec) != NULL
501abfe0 17230 && get_arm_elf_section_data (osi.sec)->mapcount == 0
7d500b83
CL		 17231 && osi.sec->size > 0
17232 && (osi.sec->flags & SEC_EXCLUDE) == 0)
33811162
DG		 17233 {
17234 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17235 (output_bfd, osi.sec->output_section);
17236 if (osi.sec_shndx != (int)SHN_BAD)
17237 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 0);
17238 }
17239 }
17240 }
17241
91a5743d
PB		 17242 /* ARM->Thumb glue. */
17243 if (htab->arm_glue_size > 0)
17244 {
3d4d4302
AM		 17245 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
17246 ARM2THUMB_GLUE_SECTION_NAME);
91a5743d
PB		 17247
17248 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17249 (output_bfd, osi.sec->output_section);
0e1862bb 17250 if (bfd_link_pic (info) || htab->root.is_relocatable_executable
91a5743d
PB		 17251 || htab->pic_veneer)
17252 size = ARM2THUMB_PIC_GLUE_SIZE;
17253 else if (htab->use_blx)
17254 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
17255 else
17256 size = ARM2THUMB_STATIC_GLUE_SIZE;
4e617b1e 17257
91a5743d
PB		 17258 for (offset = 0; offset < htab->arm_glue_size; offset += size)
17259 {
7413f23f
DJ		 17260 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset);
17261 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, offset + size - 4);
91a5743d
PB		 17262 }
17263 }
17264
17265 /* Thumb->ARM glue. */
17266 if (htab->thumb_glue_size > 0)
17267 {
3d4d4302
AM		 17268 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
17269 THUMB2ARM_GLUE_SECTION_NAME);
91a5743d
PB		 17270
17271 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17272 (output_bfd, osi.sec->output_section);
17273 size = THUMB2ARM_GLUE_SIZE;
17274
17275 for (offset = 0; offset < htab->thumb_glue_size; offset += size)
17276 {
7413f23f
DJ		 17277 elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, offset);
17278 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset + 4);
91a5743d
PB		 17279 }
17280 }
17281
845b51d6
PB		 17282 /* ARMv4 BX veneers. */
17283 if (htab->bx_glue_size > 0)
17284 {
3d4d4302
AM		 17285 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
17286 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 17287
17288 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17289 (output_bfd, osi.sec->output_section);
17290
7413f23f 17291 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0);
845b51d6
PB		 17292 }
17293
8029a119
NC		 17294 /* Long calls stubs. */
17295 if (htab->stub_bfd && htab->stub_bfd->sections)
17296 {
da5938a2 17297 asection* stub_sec;
8029a119 17298
da5938a2
NC		 17299 for (stub_sec = htab->stub_bfd->sections;
17300 stub_sec != NULL;
8029a119
NC		 17301 stub_sec = stub_sec->next)
17302 {
17303 /* Ignore non-stub sections. */
17304 if (!strstr (stub_sec->name, STUB_SUFFIX))
17305 continue;
da5938a2 17306
8029a119 17307 osi.sec = stub_sec;
da5938a2 17308
8029a119
NC		 17309 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17310 (output_bfd, osi.sec->output_section);
da5938a2 17311
8029a119
NC		 17312 bfd_hash_traverse (&htab->stub_hash_table, arm_map_one_stub, &osi);
17313 }
17314 }
da5938a2 17315
91a5743d 17316 /* Finally, output mapping symbols for the PLT. */
34e77a92 17317 if (htab->root.splt && htab->root.splt->size > 0)
4e617b1e 17318 {
34e77a92
RS		 17319 osi.sec = htab->root.splt;
17320 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
17321 (output_bfd, osi.sec->output_section));
17322
17323 /* Output mapping symbols for the plt header. SymbianOS does not have a
17324 plt header. */
17325 if (htab->vxworks_p)
17326 {
17327 /* VxWorks shared libraries have no PLT header. */
0e1862bb 17328 if (!bfd_link_pic (info))
34e77a92
RS		 17329 {
17330 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
17331 return FALSE;
17332 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
17333 return FALSE;
17334 }
17335 }
b38cadfb
NC		 17336 else if (htab->nacl_p)
17337 {
17338 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
17339 return FALSE;
17340 }
eed94f8f
NC		 17341 else if (using_thumb_only (htab))
17342 {
17343 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 0))
17344 return FALSE;
17345 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
17346 return FALSE;
17347 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 16))
17348 return FALSE;
17349 }
34e77a92 17350 else if (!htab->symbian_p)
4e617b1e 17351 {
7413f23f 17352 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
4e617b1e 17353 return FALSE;
34e77a92
RS		 17354#ifndef FOUR_WORD_PLT
17355 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 16))
4e617b1e 17356 return FALSE;
34e77a92 17357#endif
4e617b1e
PB		 17358 }
17359 }
99059e56
RM		 17360 if (htab->nacl_p && htab->root.iplt && htab->root.iplt->size > 0)
17361 {
17362 /* NaCl uses a special first entry in .iplt too. */
17363 osi.sec = htab->root.iplt;
17364 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
17365 (output_bfd, osi.sec->output_section));
17366 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
17367 return FALSE;
17368 }
34e77a92
RS		 17369 if ((htab->root.splt && htab->root.splt->size > 0)
17370 || (htab->root.iplt && htab->root.iplt->size > 0))
4e617b1e 17371 {
34e77a92
RS		 17372 elf_link_hash_traverse (&htab->root, elf32_arm_output_plt_map, &osi);
17373 for (input_bfd = info->input_bfds;
17374 input_bfd != NULL;
c72f2fb2 17375 input_bfd = input_bfd->link.next)
34e77a92
RS		 17376 {
17377 struct arm_local_iplt_info **local_iplt;
17378 unsigned int i, num_syms;
4e617b1e 17379
34e77a92
RS		 17380 local_iplt = elf32_arm_local_iplt (input_bfd);
17381 if (local_iplt != NULL)
17382 {
17383 num_syms = elf_symtab_hdr (input_bfd).sh_info;
17384 for (i = 0; i < num_syms; i++)
17385 if (local_iplt[i] != NULL
17386 && !elf32_arm_output_plt_map_1 (&osi, TRUE,
17387 &local_iplt[i]->root,
17388 &local_iplt[i]->arm))
17389 return FALSE;
17390 }
17391 }
17392 }
0855e32b
NS		 17393 if (htab->dt_tlsdesc_plt != 0)
17394 {
17395 /* Mapping symbols for the lazy tls trampoline. */
17396 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->dt_tlsdesc_plt))
17397 return FALSE;
b38cadfb 17398
0855e32b
NS		 17399 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
17400 htab->dt_tlsdesc_plt + 24))
17401 return FALSE;
17402 }
17403 if (htab->tls_trampoline != 0)
17404 {
17405 /* Mapping symbols for the tls trampoline. */
17406 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->tls_trampoline))
17407 return FALSE;
17408#ifdef FOUR_WORD_PLT
17409 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
17410 htab->tls_trampoline + 12))
17411 return FALSE;
b38cadfb 17412#endif
0855e32b 17413 }
b38cadfb 17414
4e617b1e
PB		 17415 return TRUE;
17416}
17417
54ddd295
TP		 17418/* Filter normal symbols of CMSE entry functions of ABFD to include in
17419 the import library. All SYMCOUNT symbols of ABFD can be examined
17420 from their pointers in SYMS. Pointers of symbols to keep should be
17421 stored continuously at the beginning of that array.
17422
17423 Returns the number of symbols to keep. */
17424
17425static unsigned int
17426elf32_arm_filter_cmse_symbols (bfd *abfd ATTRIBUTE_UNUSED,
17427 struct bfd_link_info *info,
17428 asymbol **syms, long symcount)
17429{
17430 size_t maxnamelen;
17431 char *cmse_name;
17432 long src_count, dst_count = 0;
17433 struct elf32_arm_link_hash_table *htab;
17434
17435 htab = elf32_arm_hash_table (info);
17436 if (!htab->stub_bfd || !htab->stub_bfd->sections)
17437 symcount = 0;
17438
17439 maxnamelen = 128;
17440 cmse_name = (char *) bfd_malloc (maxnamelen);
17441 for (src_count = 0; src_count < symcount; src_count++)
17442 {
17443 struct elf32_arm_link_hash_entry *cmse_hash;
17444 asymbol *sym;
17445 flagword flags;
17446 char *name;
17447 size_t namelen;
17448
17449 sym = syms[src_count];
17450 flags = sym->flags;
17451 name = (char *) bfd_asymbol_name (sym);
17452
17453 if ((flags & BSF_FUNCTION) != BSF_FUNCTION)
17454 continue;
17455 if (!(flags & (BSF_GLOBAL | BSF_WEAK)))
17456 continue;
17457
17458 namelen = strlen (name) + sizeof (CMSE_PREFIX) + 1;
17459 if (namelen > maxnamelen)
17460 {
17461 cmse_name = (char *)
17462 bfd_realloc (cmse_name, namelen);
17463 maxnamelen = namelen;
17464 }
17465 snprintf (cmse_name, maxnamelen, "%s%s", CMSE_PREFIX, name);
17466 cmse_hash = (struct elf32_arm_link_hash_entry *)
17467 elf_link_hash_lookup (&(htab)->root, cmse_name, FALSE, FALSE, TRUE);
17468
17469 if (!cmse_hash
17470 || (cmse_hash->root.root.type != bfd_link_hash_defined
17471 && cmse_hash->root.root.type != bfd_link_hash_defweak)
17472 || cmse_hash->root.type != STT_FUNC)
17473 continue;
17474
17475 if (!ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
17476 continue;
17477
17478 syms[dst_count++] = sym;
17479 }
17480 free (cmse_name);
17481
17482 syms[dst_count] = NULL;
17483
17484 return dst_count;
17485}
17486
17487/* Filter symbols of ABFD to include in the import library. All
17488 SYMCOUNT symbols of ABFD can be examined from their pointers in
17489 SYMS. Pointers of symbols to keep should be stored continuously at
17490 the beginning of that array.
17491
17492 Returns the number of symbols to keep. */
17493
17494static unsigned int
17495elf32_arm_filter_implib_symbols (bfd *abfd ATTRIBUTE_UNUSED,
17496 struct bfd_link_info *info,
17497 asymbol **syms, long symcount)
17498{
17499 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
17500
17501 if (globals->cmse_implib)
17502 return elf32_arm_filter_cmse_symbols (abfd, info, syms, symcount);
17503 else
17504 return _bfd_elf_filter_global_symbols (abfd, info, syms, symcount);
17505}
17506
e489d0ae
PB		 17507/* Allocate target specific section data. */
17508
17509static bfd_boolean
17510elf32_arm_new_section_hook (bfd *abfd, asection *sec)
17511{
f592407e
AM		 17512 if (!sec->used_by_bfd)
17513 {
17514 _arm_elf_section_data *sdata;
17515 bfd_size_type amt = sizeof (*sdata);
e489d0ae 17516
21d799b5 17517 sdata = (_arm_elf_section_data *) bfd_zalloc (abfd, amt);
f592407e
AM		 17518 if (sdata == NULL)
17519 return FALSE;
17520 sec->used_by_bfd = sdata;
17521 }
e489d0ae
PB		 17522
17523 return _bfd_elf_new_section_hook (abfd, sec);
17524}
17525
17526
17527/* Used to order a list of mapping symbols by address. */
17528
17529static int
17530elf32_arm_compare_mapping (const void * a, const void * b)
17531{
7f6a71ff
JM		 17532 const elf32_arm_section_map *amap = (const elf32_arm_section_map *) a;
17533 const elf32_arm_section_map *bmap = (const elf32_arm_section_map *) b;
17534
17535 if (amap->vma > bmap->vma)
17536 return 1;
17537 else if (amap->vma < bmap->vma)
17538 return -1;
17539 else if (amap->type > bmap->type)
17540 /* Ensure results do not depend on the host qsort for objects with
17541 multiple mapping symbols at the same address by sorting on type
17542 after vma. */
17543 return 1;
17544 else if (amap->type < bmap->type)
17545 return -1;
17546 else
17547 return 0;
e489d0ae
PB		 17548}
17549
2468f9c9
PB		 17550/* Add OFFSET to lower 31 bits of ADDR, leaving other bits unmodified. */
17551
17552static unsigned long
17553offset_prel31 (unsigned long addr, bfd_vma offset)
17554{
17555 return (addr & ~0x7ffffffful) | ((addr + offset) & 0x7ffffffful);
17556}
17557
17558/* Copy an .ARM.exidx table entry, adding OFFSET to (applied) PREL31
17559 relocations. */
17560
17561static void
17562copy_exidx_entry (bfd *output_bfd, bfd_byte *to, bfd_byte *from, bfd_vma offset)
17563{
17564 unsigned long first_word = bfd_get_32 (output_bfd, from);
17565 unsigned long second_word = bfd_get_32 (output_bfd, from + 4);
b38cadfb 17566
2468f9c9
PB		 17567 /* High bit of first word is supposed to be zero. */
17568 if ((first_word & 0x80000000ul) == 0)
17569 first_word = offset_prel31 (first_word, offset);
b38cadfb 17570
2468f9c9
PB		 17571 /* If the high bit of the first word is clear, and the bit pattern is not 0x1
17572 (EXIDX_CANTUNWIND), this is an offset to an .ARM.extab entry. */
17573 if ((second_word != 0x1) && ((second_word & 0x80000000ul) == 0))
17574 second_word = offset_prel31 (second_word, offset);
b38cadfb 17575
2468f9c9
PB		 17576 bfd_put_32 (output_bfd, first_word, to);
17577 bfd_put_32 (output_bfd, second_word, to + 4);
17578}
e489d0ae 17579
48229727
JB		 17580/* Data for make_branch_to_a8_stub(). */
17581
b38cadfb
NC		 17582struct a8_branch_to_stub_data
17583{
48229727
JB		 17584 asection *writing_section;
17585 bfd_byte *contents;
17586};
17587
17588
17589/* Helper to insert branches to Cortex-A8 erratum stubs in the right
17590 places for a particular section. */
17591
17592static bfd_boolean
17593make_branch_to_a8_stub (struct bfd_hash_entry *gen_entry,
99059e56 17594 void *in_arg)
48229727
JB		 17595{
17596 struct elf32_arm_stub_hash_entry *stub_entry;
17597 struct a8_branch_to_stub_data *data;
17598 bfd_byte *contents;
17599 unsigned long branch_insn;
17600 bfd_vma veneered_insn_loc, veneer_entry_loc;
17601 bfd_signed_vma branch_offset;
17602 bfd *abfd;
8d9d9490 17603 unsigned int loc;
48229727
JB		 17604
17605 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
17606 data = (struct a8_branch_to_stub_data *) in_arg;
17607
17608 if (stub_entry->target_section != data->writing_section
4563a860 17609 || stub_entry->stub_type < arm_stub_a8_veneer_lwm)
48229727
JB		 17610 return TRUE;
17611
17612 contents = data->contents;
17613
8d9d9490
TP		 17614 /* We use target_section as Cortex-A8 erratum workaround stubs are only
17615 generated when both source and target are in the same section. */
48229727
JB		 17616 veneered_insn_loc = stub_entry->target_section->output_section->vma
17617 + stub_entry->target_section->output_offset
8d9d9490 17618 + stub_entry->source_value;
48229727
JB		 17619
17620 veneer_entry_loc = stub_entry->stub_sec->output_section->vma
17621 + stub_entry->stub_sec->output_offset
17622 + stub_entry->stub_offset;
17623
17624 if (stub_entry->stub_type == arm_stub_a8_veneer_blx)
17625 veneered_insn_loc &= ~3u;
17626
17627 branch_offset = veneer_entry_loc - veneered_insn_loc - 4;
17628
17629 abfd = stub_entry->target_section->owner;
8d9d9490 17630 loc = stub_entry->source_value;
48229727
JB		 17631
17632 /* We attempt to avoid this condition by setting stubs_always_after_branch
17633 in elf32_arm_size_stubs if we've enabled the Cortex-A8 erratum workaround.
17634 This check is just to be on the safe side... */
17635 if ((veneered_insn_loc & ~0xfff) == (veneer_entry_loc & ~0xfff))
17636 {
4eca0228
AM		 17637 _bfd_error_handler (_("%B: error: Cortex-A8 erratum stub is "
17638 "allocated in unsafe location"), abfd);
48229727
JB		 17639 return FALSE;
17640 }
17641
17642 switch (stub_entry->stub_type)
17643 {
17644 case arm_stub_a8_veneer_b:
17645 case arm_stub_a8_veneer_b_cond:
17646 branch_insn = 0xf0009000;
17647 goto jump24;
17648
17649 case arm_stub_a8_veneer_blx:
17650 branch_insn = 0xf000e800;
17651 goto jump24;
17652
17653 case arm_stub_a8_veneer_bl:
17654 {
17655 unsigned int i1, j1, i2, j2, s;
17656
17657 branch_insn = 0xf000d000;
17658
17659 jump24:
17660 if (branch_offset < -16777216 || branch_offset > 16777214)
17661 {
17662 /* There's not much we can do apart from complain if this
17663 happens. */
4eca0228
AM		 17664 _bfd_error_handler (_("%B: error: Cortex-A8 erratum stub out "
17665 "of range (input file too large)"), abfd);
48229727
JB		 17666 return FALSE;
17667 }
17668
17669 /* i1 = not(j1 eor s), so:
17670 not i1 = j1 eor s
17671 j1 = (not i1) eor s. */
17672
17673 branch_insn |= (branch_offset >> 1) & 0x7ff;
17674 branch_insn |= ((branch_offset >> 12) & 0x3ff) << 16;
17675 i2 = (branch_offset >> 22) & 1;
17676 i1 = (branch_offset >> 23) & 1;
17677 s = (branch_offset >> 24) & 1;
17678 j1 = (!i1) ^ s;
17679 j2 = (!i2) ^ s;
17680 branch_insn |= j2 << 11;
17681 branch_insn |= j1 << 13;
17682 branch_insn |= s << 26;
17683 }
17684 break;
17685
17686 default:
17687 BFD_FAIL ();
17688 return FALSE;
17689 }
17690
8d9d9490
TP		 17691 bfd_put_16 (abfd, (branch_insn >> 16) & 0xffff, &contents[loc]);
17692 bfd_put_16 (abfd, branch_insn & 0xffff, &contents[loc + 2]);
48229727
JB		 17693
17694 return TRUE;
17695}
17696
a504d23a
LA		 17697/* Beginning of stm32l4xx work-around. */
17698
17699/* Functions encoding instructions necessary for the emission of the
17700 fix-stm32l4xx-629360.
17701 Encoding is extracted from the
17702 ARM (C) Architecture Reference Manual
17703 ARMv7-A and ARMv7-R edition
17704 ARM DDI 0406C.b (ID072512). */
17705
17706static inline bfd_vma
82188b29 17707create_instruction_branch_absolute (int branch_offset)
a504d23a
LA		 17708{
17709 /* A8.8.18 B (A8-334)
17710 B target_address (Encoding T4). */
17711 /* 1111 - 0Sii - iiii - iiii - 10J1 - Jiii - iiii - iiii. */
17712 /* jump offset is: S:I1:I2:imm10:imm11:0. */
17713 /* with : I1 = NOT (J1 EOR S) I2 = NOT (J2 EOR S). */
17714
a504d23a
LA		 17715 int s = ((branch_offset & 0x1000000) >> 24);
17716 int j1 = s ^ !((branch_offset & 0x800000) >> 23);
17717 int j2 = s ^ !((branch_offset & 0x400000) >> 22);
17718
17719 if (branch_offset < -(1 << 24) || branch_offset >= (1 << 24))
17720 BFD_ASSERT (0 && "Error: branch out of range. Cannot create branch.");
17721
17722 bfd_vma patched_inst = 0xf0009000
17723 | s << 26 /* S. */
17724 | (((unsigned long) (branch_offset) >> 12) & 0x3ff) << 16 /* imm10. */
17725 | j1 << 13 /* J1. */
17726 | j2 << 11 /* J2. */
17727 | (((unsigned long) (branch_offset) >> 1) & 0x7ff); /* imm11. */
17728
17729 return patched_inst;
17730}
17731
17732static inline bfd_vma
17733create_instruction_ldmia (int base_reg, int wback, int reg_mask)
17734{
17735 /* A8.8.57 LDM/LDMIA/LDMFD (A8-396)
17736 LDMIA Rn!, {Ra, Rb, Rc, ...} (Encoding T2). */
17737 bfd_vma patched_inst = 0xe8900000
17738 | (/*W=*/wback << 21)
17739 | (base_reg << 16)
17740 | (reg_mask & 0x0000ffff);
17741
17742 return patched_inst;
17743}
17744
17745static inline bfd_vma
17746create_instruction_ldmdb (int base_reg, int wback, int reg_mask)
17747{
17748 /* A8.8.60 LDMDB/LDMEA (A8-402)
17749 LDMDB Rn!, {Ra, Rb, Rc, ...} (Encoding T1). */
17750 bfd_vma patched_inst = 0xe9100000
17751 | (/*W=*/wback << 21)
17752 | (base_reg << 16)
17753 | (reg_mask & 0x0000ffff);
17754
17755 return patched_inst;
17756}
17757
17758static inline bfd_vma
17759create_instruction_mov (int target_reg, int source_reg)
17760{
17761 /* A8.8.103 MOV (register) (A8-486)
17762 MOV Rd, Rm (Encoding T1). */
17763 bfd_vma patched_inst = 0x4600
17764 | (target_reg & 0x7)
17765 | ((target_reg & 0x8) >> 3) << 7
17766 | (source_reg << 3);
17767
17768 return patched_inst;
17769}
17770
17771static inline bfd_vma
17772create_instruction_sub (int target_reg, int source_reg, int value)
17773{
17774 /* A8.8.221 SUB (immediate) (A8-708)
17775 SUB Rd, Rn, #value (Encoding T3). */
17776 bfd_vma patched_inst = 0xf1a00000
17777 | (target_reg << 8)
17778 | (source_reg << 16)
17779 | (/*S=*/0 << 20)
17780 | ((value & 0x800) >> 11) << 26
17781 | ((value & 0x700) >> 8) << 12
17782 | (value & 0x0ff);
17783
17784 return patched_inst;
17785}
17786
17787static inline bfd_vma
9239bbd3 17788create_instruction_vldmia (int base_reg, int is_dp, int wback, int num_words,
a504d23a
LA		 17789 int first_reg)
17790{
17791 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 17792 VLMD{MODE} Rn{!}, {list} (Encoding T1 or T2). */
17793 bfd_vma patched_inst = (is_dp ? 0xec900b00 : 0xec900a00)
a504d23a
LA		 17794 | (/*W=*/wback << 21)
17795 | (base_reg << 16)
9239bbd3
CM		 17796 | (num_words & 0x000000ff)
17797 | (((unsigned)first_reg >> 1) & 0x0000000f) << 12
a504d23a
LA		 17798 | (first_reg & 0x00000001) << 22;
17799
17800 return patched_inst;
17801}
17802
17803static inline bfd_vma
9239bbd3
CM		 17804create_instruction_vldmdb (int base_reg, int is_dp, int num_words,
17805 int first_reg)
a504d23a
LA		 17806{
17807 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 17808 VLMD{MODE} Rn!, {} (Encoding T1 or T2). */
17809 bfd_vma patched_inst = (is_dp ? 0xed300b00 : 0xed300a00)
a504d23a 17810 | (base_reg << 16)
9239bbd3
CM		 17811 | (num_words & 0x000000ff)
17812 | (((unsigned)first_reg >>1 ) & 0x0000000f) << 12
a504d23a
LA		 17813 | (first_reg & 0x00000001) << 22;
17814
17815 return patched_inst;
17816}
17817
17818static inline bfd_vma
17819create_instruction_udf_w (int value)
17820{
17821 /* A8.8.247 UDF (A8-758)
17822 Undefined (Encoding T2). */
17823 bfd_vma patched_inst = 0xf7f0a000
17824 | (value & 0x00000fff)
17825 | (value & 0x000f0000) << 16;
17826
17827 return patched_inst;
17828}
17829
17830static inline bfd_vma
17831create_instruction_udf (int value)
17832{
17833 /* A8.8.247 UDF (A8-758)
17834 Undefined (Encoding T1). */
17835 bfd_vma patched_inst = 0xde00
17836 | (value & 0xff);
17837
17838 return patched_inst;
17839}
17840
17841/* Functions writing an instruction in memory, returning the next
17842 memory position to write to. */
17843
17844static inline bfd_byte *
17845push_thumb2_insn32 (struct elf32_arm_link_hash_table * htab,
17846 bfd * output_bfd, bfd_byte *pt, insn32 insn)
17847{
17848 put_thumb2_insn (htab, output_bfd, insn, pt);
17849 return pt + 4;
17850}
17851
17852static inline bfd_byte *
17853push_thumb2_insn16 (struct elf32_arm_link_hash_table * htab,
17854 bfd * output_bfd, bfd_byte *pt, insn32 insn)
17855{
17856 put_thumb_insn (htab, output_bfd, insn, pt);
17857 return pt + 2;
17858}
17859
17860/* Function filling up a region in memory with T1 and T2 UDFs taking
17861 care of alignment. */
17862
17863static bfd_byte *
17864stm32l4xx_fill_stub_udf (struct elf32_arm_link_hash_table * htab,
17865 bfd * output_bfd,
17866 const bfd_byte * const base_stub_contents,
17867 bfd_byte * const from_stub_contents,
17868 const bfd_byte * const end_stub_contents)
17869{
17870 bfd_byte *current_stub_contents = from_stub_contents;
17871
17872 /* Fill the remaining of the stub with deterministic contents : UDF
17873 instructions.
17874 Check if realignment is needed on modulo 4 frontier using T1, to
17875 further use T2. */
17876 if ((current_stub_contents < end_stub_contents)
17877 && !((current_stub_contents - base_stub_contents) % 2)
17878 && ((current_stub_contents - base_stub_contents) % 4))
17879 current_stub_contents =
17880 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
17881 create_instruction_udf (0));
17882
17883 for (; current_stub_contents < end_stub_contents;)
17884 current_stub_contents =
17885 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17886 create_instruction_udf_w (0));
17887
17888 return current_stub_contents;
17889}
17890
17891/* Functions writing the stream of instructions equivalent to the
17892 derived sequence for ldmia, ldmdb, vldm respectively. */
17893
17894static void
17895stm32l4xx_create_replacing_stub_ldmia (struct elf32_arm_link_hash_table * htab,
17896 bfd * output_bfd,
17897 const insn32 initial_insn,
17898 const bfd_byte *const initial_insn_addr,
17899 bfd_byte *const base_stub_contents)
17900{
17901 int wback = (initial_insn & 0x00200000) >> 21;
17902 int ri, rn = (initial_insn & 0x000F0000) >> 16;
17903 int insn_all_registers = initial_insn & 0x0000ffff;
17904 int insn_low_registers, insn_high_registers;
17905 int usable_register_mask;
b25e998d 17906 int nb_registers = elf32_arm_popcount (insn_all_registers);
a504d23a
LA		 17907 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
17908 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
17909 bfd_byte *current_stub_contents = base_stub_contents;
17910
17911 BFD_ASSERT (is_thumb2_ldmia (initial_insn));
17912
17913 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
17914 smaller than 8 registers load sequences that do not cause the
17915 hardware issue. */
17916 if (nb_registers <= 8)
17917 {
17918 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
17919 current_stub_contents =
17920 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17921 initial_insn);
17922
17923 /* B initial_insn_addr+4. */
17924 if (!restore_pc)
17925 current_stub_contents =
17926 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17927 create_instruction_branch_absolute
82188b29 17928 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17929
17930 /* Fill the remaining of the stub with deterministic contents. */
17931 current_stub_contents =
17932 stm32l4xx_fill_stub_udf (htab, output_bfd,
17933 base_stub_contents, current_stub_contents,
17934 base_stub_contents +
17935 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
17936
17937 return;
17938 }
17939
17940 /* - reg_list[13] == 0. */
17941 BFD_ASSERT ((insn_all_registers & (1 << 13))==0);
17942
17943 /* - reg_list[14] & reg_list[15] != 1. */
17944 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
17945
17946 /* - if (wback==1) reg_list[rn] == 0. */
17947 BFD_ASSERT (!wback || !restore_rn);
17948
17949 /* - nb_registers > 8. */
b25e998d 17950 BFD_ASSERT (elf32_arm_popcount (insn_all_registers) > 8);
a504d23a
LA		 17951
17952 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
17953
17954 /* In the following algorithm, we split this wide LDM using 2 LDM insns:
17955 - One with the 7 lowest registers (register mask 0x007F)
17956 This LDM will finally contain between 2 and 7 registers
17957 - One with the 7 highest registers (register mask 0xDF80)
17958 This ldm will finally contain between 2 and 7 registers. */
17959 insn_low_registers = insn_all_registers & 0x007F;
17960 insn_high_registers = insn_all_registers & 0xDF80;
17961
17962 /* A spare register may be needed during this veneer to temporarily
17963 handle the base register. This register will be restored with the
17964 last LDM operation.
17965 The usable register may be any general purpose register (that
17966 excludes PC, SP, LR : register mask is 0x1FFF). */
17967 usable_register_mask = 0x1FFF;
17968
17969 /* Generate the stub function. */
17970 if (wback)
17971 {
17972 /* LDMIA Rn!, {R-low-register-list} : (Encoding T2). */
17973 current_stub_contents =
17974 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17975 create_instruction_ldmia
17976 (rn, /*wback=*/1, insn_low_registers));
17977
17978 /* LDMIA Rn!, {R-high-register-list} : (Encoding T2). */
17979 current_stub_contents =
17980 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17981 create_instruction_ldmia
17982 (rn, /*wback=*/1, insn_high_registers));
17983 if (!restore_pc)
17984 {
17985 /* B initial_insn_addr+4. */
17986 current_stub_contents =
17987 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17988 create_instruction_branch_absolute
82188b29 17989 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17990 }
17991 }
17992 else /* if (!wback). */
17993 {
17994 ri = rn;
17995
17996 /* If Rn is not part of the high-register-list, move it there. */
17997 if (!(insn_high_registers & (1 << rn)))
17998 {
17999 /* Choose a Ri in the high-register-list that will be restored. */
18000 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
18001
18002 /* MOV Ri, Rn. */
18003 current_stub_contents =
18004 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18005 create_instruction_mov (ri, rn));
18006 }
18007
18008 /* LDMIA Ri!, {R-low-register-list} : (Encoding T2). */
18009 current_stub_contents =
18010 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18011 create_instruction_ldmia
18012 (ri, /*wback=*/1, insn_low_registers));
18013
18014 /* LDMIA Ri, {R-high-register-list} : (Encoding T2). */
18015 current_stub_contents =
18016 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18017 create_instruction_ldmia
18018 (ri, /*wback=*/0, insn_high_registers));
18019
18020 if (!restore_pc)
18021 {
18022 /* B initial_insn_addr+4. */
18023 current_stub_contents =
18024 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18025 create_instruction_branch_absolute
82188b29 18026 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18027 }
18028 }
18029
18030 /* Fill the remaining of the stub with deterministic contents. */
18031 current_stub_contents =
18032 stm32l4xx_fill_stub_udf (htab, output_bfd,
18033 base_stub_contents, current_stub_contents,
18034 base_stub_contents +
18035 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18036}
18037
18038static void
18039stm32l4xx_create_replacing_stub_ldmdb (struct elf32_arm_link_hash_table * htab,
18040 bfd * output_bfd,
18041 const insn32 initial_insn,
18042 const bfd_byte *const initial_insn_addr,
18043 bfd_byte *const base_stub_contents)
18044{
18045 int wback = (initial_insn & 0x00200000) >> 21;
18046 int ri, rn = (initial_insn & 0x000f0000) >> 16;
18047 int insn_all_registers = initial_insn & 0x0000ffff;
18048 int insn_low_registers, insn_high_registers;
18049 int usable_register_mask;
18050 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
18051 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
b25e998d 18052 int nb_registers = elf32_arm_popcount (insn_all_registers);
a504d23a
LA		 18053 bfd_byte *current_stub_contents = base_stub_contents;
18054
18055 BFD_ASSERT (is_thumb2_ldmdb (initial_insn));
18056
18057 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
18058 smaller than 8 registers load sequences that do not cause the
18059 hardware issue. */
18060 if (nb_registers <= 8)
18061 {
18062 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
18063 current_stub_contents =
18064 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18065 initial_insn);
18066
18067 /* B initial_insn_addr+4. */
18068 current_stub_contents =
18069 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18070 create_instruction_branch_absolute
82188b29 18071 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18072
18073 /* Fill the remaining of the stub with deterministic contents. */
18074 current_stub_contents =
18075 stm32l4xx_fill_stub_udf (htab, output_bfd,
18076 base_stub_contents, current_stub_contents,
18077 base_stub_contents +
18078 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18079
18080 return;
18081 }
18082
18083 /* - reg_list[13] == 0. */
18084 BFD_ASSERT ((insn_all_registers & (1 << 13)) == 0);
18085
18086 /* - reg_list[14] & reg_list[15] != 1. */
18087 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
18088
18089 /* - if (wback==1) reg_list[rn] == 0. */
18090 BFD_ASSERT (!wback || !restore_rn);
18091
18092 /* - nb_registers > 8. */
b25e998d 18093 BFD_ASSERT (elf32_arm_popcount (insn_all_registers) > 8);
a504d23a
LA		 18094
18095 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
18096
18097 /* In the following algorithm, we split this wide LDM using 2 LDM insn:
18098 - One with the 7 lowest registers (register mask 0x007F)
18099 This LDM will finally contain between 2 and 7 registers
18100 - One with the 7 highest registers (register mask 0xDF80)
18101 This ldm will finally contain between 2 and 7 registers. */
18102 insn_low_registers = insn_all_registers & 0x007F;
18103 insn_high_registers = insn_all_registers & 0xDF80;
18104
18105 /* A spare register may be needed during this veneer to temporarily
18106 handle the base register. This register will be restored with
18107 the last LDM operation.
18108 The usable register may be any general purpose register (that excludes
18109 PC, SP, LR : register mask is 0x1FFF). */
18110 usable_register_mask = 0x1FFF;
18111
18112 /* Generate the stub function. */
18113 if (!wback && !restore_pc && !restore_rn)
18114 {
18115 /* Choose a Ri in the low-register-list that will be restored. */
18116 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
18117
18118 /* MOV Ri, Rn. */
18119 current_stub_contents =
18120 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18121 create_instruction_mov (ri, rn));
18122
18123 /* LDMDB Ri!, {R-high-register-list}. */
18124 current_stub_contents =
18125 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18126 create_instruction_ldmdb
18127 (ri, /*wback=*/1, insn_high_registers));
18128
18129 /* LDMDB Ri, {R-low-register-list}. */
18130 current_stub_contents =
18131 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18132 create_instruction_ldmdb
18133 (ri, /*wback=*/0, insn_low_registers));
18134
18135 /* B initial_insn_addr+4. */
18136 current_stub_contents =
18137 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18138 create_instruction_branch_absolute
82188b29 18139 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18140 }
18141 else if (wback && !restore_pc && !restore_rn)
18142 {
18143 /* LDMDB Rn!, {R-high-register-list}. */
18144 current_stub_contents =
18145 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18146 create_instruction_ldmdb
18147 (rn, /*wback=*/1, insn_high_registers));
18148
18149 /* LDMDB Rn!, {R-low-register-list}. */
18150 current_stub_contents =
18151 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18152 create_instruction_ldmdb
18153 (rn, /*wback=*/1, insn_low_registers));
18154
18155 /* B initial_insn_addr+4. */
18156 current_stub_contents =
18157 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18158 create_instruction_branch_absolute
82188b29 18159 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18160 }
18161 else if (!wback && restore_pc && !restore_rn)
18162 {
18163 /* Choose a Ri in the high-register-list that will be restored. */
18164 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
18165
18166 /* SUB Ri, Rn, #(4*nb_registers). */
18167 current_stub_contents =
18168 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18169 create_instruction_sub (ri, rn, (4 * nb_registers)));
18170
18171 /* LDMIA Ri!, {R-low-register-list}. */
18172 current_stub_contents =
18173 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18174 create_instruction_ldmia
18175 (ri, /*wback=*/1, insn_low_registers));
18176
18177 /* LDMIA Ri, {R-high-register-list}. */
18178 current_stub_contents =
18179 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18180 create_instruction_ldmia
18181 (ri, /*wback=*/0, insn_high_registers));
18182 }
18183 else if (wback && restore_pc && !restore_rn)
18184 {
18185 /* Choose a Ri in the high-register-list that will be restored. */
18186 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
18187
18188 /* SUB Rn, Rn, #(4*nb_registers) */
18189 current_stub_contents =
18190 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18191 create_instruction_sub (rn, rn, (4 * nb_registers)));
18192
18193 /* MOV Ri, Rn. */
18194 current_stub_contents =
18195 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18196 create_instruction_mov (ri, rn));
18197
18198 /* LDMIA Ri!, {R-low-register-list}. */
18199 current_stub_contents =
18200 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18201 create_instruction_ldmia
18202 (ri, /*wback=*/1, insn_low_registers));
18203
18204 /* LDMIA Ri, {R-high-register-list}. */
18205 current_stub_contents =
18206 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18207 create_instruction_ldmia
18208 (ri, /*wback=*/0, insn_high_registers));
18209 }
18210 else if (!wback && !restore_pc && restore_rn)
18211 {
18212 ri = rn;
18213 if (!(insn_low_registers & (1 << rn)))
18214 {
18215 /* Choose a Ri in the low-register-list that will be restored. */
18216 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
18217
18218 /* MOV Ri, Rn. */
18219 current_stub_contents =
18220 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18221 create_instruction_mov (ri, rn));
18222 }
18223
18224 /* LDMDB Ri!, {R-high-register-list}. */
18225 current_stub_contents =
18226 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18227 create_instruction_ldmdb
18228 (ri, /*wback=*/1, insn_high_registers));
18229
18230 /* LDMDB Ri, {R-low-register-list}. */
18231 current_stub_contents =
18232 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18233 create_instruction_ldmdb
18234 (ri, /*wback=*/0, insn_low_registers));
18235
18236 /* B initial_insn_addr+4. */
18237 current_stub_contents =
18238 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18239 create_instruction_branch_absolute
82188b29 18240 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18241 }
18242 else if (!wback && restore_pc && restore_rn)
18243 {
18244 ri = rn;
18245 if (!(insn_high_registers & (1 << rn)))
18246 {
18247 /* Choose a Ri in the high-register-list that will be restored. */
18248 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
18249 }
18250
18251 /* SUB Ri, Rn, #(4*nb_registers). */
18252 current_stub_contents =
18253 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18254 create_instruction_sub (ri, rn, (4 * nb_registers)));
18255
18256 /* LDMIA Ri!, {R-low-register-list}. */
18257 current_stub_contents =
18258 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18259 create_instruction_ldmia
18260 (ri, /*wback=*/1, insn_low_registers));
18261
18262 /* LDMIA Ri, {R-high-register-list}. */
18263 current_stub_contents =
18264 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18265 create_instruction_ldmia
18266 (ri, /*wback=*/0, insn_high_registers));
18267 }
18268 else if (wback && restore_rn)
18269 {
18270 /* The assembler should not have accepted to encode this. */
18271 BFD_ASSERT (0 && "Cannot patch an instruction that has an "
18272 "undefined behavior.\n");
18273 }
18274
18275 /* Fill the remaining of the stub with deterministic contents. */
18276 current_stub_contents =
18277 stm32l4xx_fill_stub_udf (htab, output_bfd,
18278 base_stub_contents, current_stub_contents,
18279 base_stub_contents +
18280 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18281
18282}
18283
18284static void
18285stm32l4xx_create_replacing_stub_vldm (struct elf32_arm_link_hash_table * htab,
18286 bfd * output_bfd,
18287 const insn32 initial_insn,
18288 const bfd_byte *const initial_insn_addr,
18289 bfd_byte *const base_stub_contents)
18290{
9239bbd3 18291 int num_words = ((unsigned int) initial_insn << 24) >> 24;
a504d23a
LA		 18292 bfd_byte *current_stub_contents = base_stub_contents;
18293
18294 BFD_ASSERT (is_thumb2_vldm (initial_insn));
18295
18296 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
9239bbd3 18297 smaller than 8 words load sequences that do not cause the
a504d23a 18298 hardware issue. */
9239bbd3 18299 if (num_words <= 8)
a504d23a
LA		 18300 {
18301 /* Untouched instruction. */
18302 current_stub_contents =
18303 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18304 initial_insn);
18305
18306 /* B initial_insn_addr+4. */
18307 current_stub_contents =
18308 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18309 create_instruction_branch_absolute
82188b29 18310 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18311 }
18312 else
18313 {
9eaff861 18314 bfd_boolean is_dp = /* DP encoding. */
9239bbd3 18315 (initial_insn & 0xfe100f00) == 0xec100b00;
a504d23a
LA		 18316 bfd_boolean is_ia_nobang = /* (IA without !). */
18317 (((initial_insn << 7) >> 28) & 0xd) == 0x4;
18318 bfd_boolean is_ia_bang = /* (IA with !) - includes VPOP. */
18319 (((initial_insn << 7) >> 28) & 0xd) == 0x5;
18320 bfd_boolean is_db_bang = /* (DB with !). */
18321 (((initial_insn << 7) >> 28) & 0xd) == 0x9;
9239bbd3 18322 int base_reg = ((unsigned int) initial_insn << 12) >> 28;
a504d23a 18323 /* d = UInt (Vd:D);. */
9239bbd3 18324 int first_reg = ((((unsigned int) initial_insn << 16) >> 28) << 1)
a504d23a
LA		 18325 | (((unsigned int)initial_insn << 9) >> 31);
18326
9239bbd3
CM		 18327 /* Compute the number of 8-words chunks needed to split. */
18328 int chunks = (num_words % 8) ? (num_words / 8 + 1) : (num_words / 8);
a504d23a
LA		 18329 int chunk;
18330
18331 /* The test coverage has been done assuming the following
18332 hypothesis that exactly one of the previous is_ predicates is
18333 true. */
9239bbd3
CM		 18334 BFD_ASSERT ( (is_ia_nobang ^ is_ia_bang ^ is_db_bang)
18335 && !(is_ia_nobang & is_ia_bang & is_db_bang));
a504d23a 18336
9239bbd3 18337 /* We treat the cutting of the words in one pass for all
a504d23a
LA		 18338 cases, then we emit the adjustments:
18339
18340 vldm rx, {...}
18341 -> vldm rx!, {8_words_or_less} for each needed 8_word
18342 -> sub rx, rx, #size (list)
18343
18344 vldm rx!, {...}
18345 -> vldm rx!, {8_words_or_less} for each needed 8_word
18346 This also handles vpop instruction (when rx is sp)
18347
18348 vldmd rx!, {...}
18349 -> vldmb rx!, {8_words_or_less} for each needed 8_word. */
9239bbd3 18350 for (chunk = 0; chunk < chunks; ++chunk)
a504d23a 18351 {
9239bbd3
CM		 18352 bfd_vma new_insn = 0;
18353
a504d23a
LA		 18354 if (is_ia_nobang || is_ia_bang)
18355 {
9239bbd3
CM		 18356 new_insn = create_instruction_vldmia
18357 (base_reg,
18358 is_dp,
18359 /*wback= . */1,
18360 chunks - (chunk + 1) ?
18361 8 : num_words - chunk * 8,
18362 first_reg + chunk * 8);
a504d23a
LA		 18363 }
18364 else if (is_db_bang)
18365 {
9239bbd3
CM		 18366 new_insn = create_instruction_vldmdb
18367 (base_reg,
18368 is_dp,
18369 chunks - (chunk + 1) ?
18370 8 : num_words - chunk * 8,
18371 first_reg + chunk * 8);
a504d23a 18372 }
9239bbd3
CM		 18373
18374 if (new_insn)
18375 current_stub_contents =
18376 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18377 new_insn);
a504d23a
LA		 18378 }
18379
18380 /* Only this case requires the base register compensation
18381 subtract. */
18382 if (is_ia_nobang)
18383 {
18384 current_stub_contents =
18385 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18386 create_instruction_sub
9239bbd3 18387 (base_reg, base_reg, 4*num_words));
a504d23a
LA		 18388 }
18389
18390 /* B initial_insn_addr+4. */
18391 current_stub_contents =
18392 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18393 create_instruction_branch_absolute
82188b29 18394 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18395 }
18396
18397 /* Fill the remaining of the stub with deterministic contents. */
18398 current_stub_contents =
18399 stm32l4xx_fill_stub_udf (htab, output_bfd,
18400 base_stub_contents, current_stub_contents,
18401 base_stub_contents +
18402 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
18403}
18404
18405static void
18406stm32l4xx_create_replacing_stub (struct elf32_arm_link_hash_table * htab,
18407 bfd * output_bfd,
18408 const insn32 wrong_insn,
18409 const bfd_byte *const wrong_insn_addr,
18410 bfd_byte *const stub_contents)
18411{
18412 if (is_thumb2_ldmia (wrong_insn))
18413 stm32l4xx_create_replacing_stub_ldmia (htab, output_bfd,
18414 wrong_insn, wrong_insn_addr,
18415 stub_contents);
18416 else if (is_thumb2_ldmdb (wrong_insn))
18417 stm32l4xx_create_replacing_stub_ldmdb (htab, output_bfd,
18418 wrong_insn, wrong_insn_addr,
18419 stub_contents);
18420 else if (is_thumb2_vldm (wrong_insn))
18421 stm32l4xx_create_replacing_stub_vldm (htab, output_bfd,
18422 wrong_insn, wrong_insn_addr,
18423 stub_contents);
18424}
18425
18426/* End of stm32l4xx work-around. */
18427
18428
e489d0ae
PB		 18429/* Do code byteswapping. Return FALSE afterwards so that the section is
18430 written out as normal. */
18431
18432static bfd_boolean
c7b8f16e 18433elf32_arm_write_section (bfd *output_bfd,
8029a119
NC		 18434 struct bfd_link_info *link_info,
18435 asection *sec,
e489d0ae
PB		 18436 bfd_byte *contents)
18437{
48229727 18438 unsigned int mapcount, errcount;
8e3de13a 18439 _arm_elf_section_data *arm_data;
c7b8f16e 18440 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
e489d0ae 18441 elf32_arm_section_map *map;
c7b8f16e 18442 elf32_vfp11_erratum_list *errnode;
a504d23a 18443 elf32_stm32l4xx_erratum_list *stm32l4xx_errnode;
e489d0ae
PB		 18444 bfd_vma ptr;
18445 bfd_vma end;
c7b8f16e 18446 bfd_vma offset = sec->output_section->vma + sec->output_offset;
e489d0ae 18447 bfd_byte tmp;
48229727 18448 unsigned int i;
57e8b36a 18449
4dfe6ac6
NC		 18450 if (globals == NULL)
18451 return FALSE;
18452
8e3de13a
NC		 18453 /* If this section has not been allocated an _arm_elf_section_data
18454 structure then we cannot record anything. */
18455 arm_data = get_arm_elf_section_data (sec);
18456 if (arm_data == NULL)
18457 return FALSE;
18458
18459 mapcount = arm_data->mapcount;
18460 map = arm_data->map;
c7b8f16e
JB		 18461 errcount = arm_data->erratumcount;
18462
18463 if (errcount != 0)
18464 {
18465 unsigned int endianflip = bfd_big_endian (output_bfd) ? 3 : 0;
18466
18467 for (errnode = arm_data->erratumlist; errnode != 0;
99059e56
RM		 18468 errnode = errnode->next)
18469 {
18470 bfd_vma target = errnode->vma - offset;
18471
18472 switch (errnode->type)
18473 {
18474 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
18475 {
18476 bfd_vma branch_to_veneer;
18477 /* Original condition code of instruction, plus bit mask for
18478 ARM B instruction. */
18479 unsigned int insn = (errnode->u.b.vfp_insn & 0xf0000000)
18480 | 0x0a000000;
c7b8f16e
JB		 18481
18482 /* The instruction is before the label. */
91d6fa6a 18483 target -= 4;
c7b8f16e
JB		 18484
18485 /* Above offset included in -4 below. */
18486 branch_to_veneer = errnode->u.b.veneer->vma
99059e56 18487 - errnode->vma - 4;
c7b8f16e
JB		 18488
18489 if ((signed) branch_to_veneer < -(1 << 25)
18490 || (signed) branch_to_veneer >= (1 << 25))
4eca0228
AM		 18491 _bfd_error_handler (_("%B: error: VFP11 veneer out of "
18492 "range"), output_bfd);
c7b8f16e 18493
99059e56
RM		 18494 insn |= (branch_to_veneer >> 2) & 0xffffff;
18495 contents[endianflip ^ target] = insn & 0xff;
18496 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
18497 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
18498 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
18499 }
18500 break;
c7b8f16e
JB		 18501
18502 case VFP11_ERRATUM_ARM_VENEER:
99059e56
RM		 18503 {
18504 bfd_vma branch_from_veneer;
18505 unsigned int insn;
c7b8f16e 18506
99059e56
RM		 18507 /* Take size of veneer into account. */
18508 branch_from_veneer = errnode->u.v.branch->vma
18509 - errnode->vma - 12;
c7b8f16e
JB		 18510
18511 if ((signed) branch_from_veneer < -(1 << 25)
18512 || (signed) branch_from_veneer >= (1 << 25))
4eca0228
AM		 18513 _bfd_error_handler (_("%B: error: VFP11 veneer out of "
18514 "range"), output_bfd);
c7b8f16e 18515
99059e56
RM		 18516 /* Original instruction. */
18517 insn = errnode->u.v.branch->u.b.vfp_insn;
18518 contents[endianflip ^ target] = insn & 0xff;
18519 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
18520 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
18521 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
18522
18523 /* Branch back to insn after original insn. */
18524 insn = 0xea000000 | ((branch_from_veneer >> 2) & 0xffffff);
18525 contents[endianflip ^ (target + 4)] = insn & 0xff;
18526 contents[endianflip ^ (target + 5)] = (insn >> 8) & 0xff;
18527 contents[endianflip ^ (target + 6)] = (insn >> 16) & 0xff;
18528 contents[endianflip ^ (target + 7)] = (insn >> 24) & 0xff;
18529 }
18530 break;
c7b8f16e 18531
99059e56
RM		 18532 default:
18533 abort ();
18534 }
18535 }
c7b8f16e 18536 }
e489d0ae 18537
a504d23a
LA		 18538 if (arm_data->stm32l4xx_erratumcount != 0)
18539 {
18540 for (stm32l4xx_errnode = arm_data->stm32l4xx_erratumlist;
18541 stm32l4xx_errnode != 0;
18542 stm32l4xx_errnode = stm32l4xx_errnode->next)
18543 {
18544 bfd_vma target = stm32l4xx_errnode->vma - offset;
18545
18546 switch (stm32l4xx_errnode->type)
18547 {
18548 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
18549 {
18550 unsigned int insn;
18551 bfd_vma branch_to_veneer =
18552 stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma;
18553
18554 if ((signed) branch_to_veneer < -(1 << 24)
18555 || (signed) branch_to_veneer >= (1 << 24))
18556 {
18557 bfd_vma out_of_range =
18558 ((signed) branch_to_veneer < -(1 << 24)) ?
18559 - branch_to_veneer - (1 << 24) :
18560 ((signed) branch_to_veneer >= (1 << 24)) ?
18561 branch_to_veneer - (1 << 24) : 0;
18562
4eca0228 18563 _bfd_error_handler
a504d23a 18564 (_("%B(%#x): error: Cannot create STM32L4XX veneer. "
eee926f2 18565 "Jump out of range by %ld bytes. "
a504d23a
LA		 18566 "Cannot encode branch instruction. "),
18567 output_bfd,
eee926f2 18568 (long) (stm32l4xx_errnode->vma - 4),
a504d23a
LA		 18569 out_of_range);
18570 continue;
18571 }
18572
18573 insn = create_instruction_branch_absolute
82188b29 18574 (stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma);
a504d23a
LA		 18575
18576 /* The instruction is before the label. */
18577 target -= 4;
18578
18579 put_thumb2_insn (globals, output_bfd,
18580 (bfd_vma) insn, contents + target);
18581 }
18582 break;
18583
18584 case STM32L4XX_ERRATUM_VENEER:
18585 {
82188b29
NC		 18586 bfd_byte * veneer;
18587 bfd_byte * veneer_r;
a504d23a
LA		 18588 unsigned int insn;
18589
82188b29
NC		 18590 veneer = contents + target;
18591 veneer_r = veneer
18592 + stm32l4xx_errnode->u.b.veneer->vma
18593 - stm32l4xx_errnode->vma - 4;
a504d23a
LA		 18594
18595 if ((signed) (veneer_r - veneer -
18596 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE >
18597 STM32L4XX_ERRATUM_LDM_VENEER_SIZE ?
18598 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE :
18599 STM32L4XX_ERRATUM_LDM_VENEER_SIZE) < -(1 << 24)
18600 || (signed) (veneer_r - veneer) >= (1 << 24))
18601 {
4eca0228
AM		 18602 _bfd_error_handler (_("%B: error: Cannot create STM32L4XX "
18603 "veneer."), output_bfd);
a504d23a
LA		 18604 continue;
18605 }
18606
18607 /* Original instruction. */
18608 insn = stm32l4xx_errnode->u.v.branch->u.b.insn;
18609
18610 stm32l4xx_create_replacing_stub
18611 (globals, output_bfd, insn, (void*)veneer_r, (void*)veneer);
18612 }
18613 break;
18614
18615 default:
18616 abort ();
18617 }
18618 }
18619 }
18620
2468f9c9
PB		 18621 if (arm_data->elf.this_hdr.sh_type == SHT_ARM_EXIDX)
18622 {
18623 arm_unwind_table_edit *edit_node
99059e56 18624 = arm_data->u.exidx.unwind_edit_list;
2468f9c9 18625 /* Now, sec->size is the size of the section we will write. The original
99059e56 18626 size (before we merged duplicate entries and inserted EXIDX_CANTUNWIND
2468f9c9
PB		 18627 markers) was sec->rawsize. (This isn't the case if we perform no
18628 edits, then rawsize will be zero and we should use size). */
21d799b5 18629 bfd_byte *edited_contents = (bfd_byte *) bfd_malloc (sec->size);
2468f9c9
PB		 18630 unsigned int input_size = sec->rawsize ? sec->rawsize : sec->size;
18631 unsigned int in_index, out_index;
18632 bfd_vma add_to_offsets = 0;
18633
18634 for (in_index = 0, out_index = 0; in_index * 8 < input_size || edit_node;)
99059e56 18635 {
2468f9c9
PB		 18636 if (edit_node)
18637 {
18638 unsigned int edit_index = edit_node->index;
b38cadfb 18639
2468f9c9 18640 if (in_index < edit_index && in_index * 8 < input_size)
99059e56 18641 {
2468f9c9
PB		 18642 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
18643 contents + in_index * 8, add_to_offsets);
18644 out_index++;
18645 in_index++;
18646 }
18647 else if (in_index == edit_index
18648 || (in_index * 8 >= input_size
18649 && edit_index == UINT_MAX))
99059e56 18650 {
2468f9c9
PB		 18651 switch (edit_node->type)
18652 {
18653 case DELETE_EXIDX_ENTRY:
18654 in_index++;
18655 add_to_offsets += 8;
18656 break;
b38cadfb 18657
2468f9c9
PB		 18658 case INSERT_EXIDX_CANTUNWIND_AT_END:
18659 {
99059e56 18660 asection *text_sec = edit_node->linked_section;
2468f9c9
PB		 18661 bfd_vma text_offset = text_sec->output_section->vma
18662 + text_sec->output_offset
18663 + text_sec->size;
18664 bfd_vma exidx_offset = offset + out_index * 8;
99059e56 18665 unsigned long prel31_offset;
2468f9c9
PB		 18666
18667 /* Note: this is meant to be equivalent to an
18668 R_ARM_PREL31 relocation. These synthetic
18669 EXIDX_CANTUNWIND markers are not relocated by the
18670 usual BFD method. */
18671 prel31_offset = (text_offset - exidx_offset)
18672 & 0x7ffffffful;
491d01d3
YU		 18673 if (bfd_link_relocatable (link_info))
18674 {
18675 /* Here relocation for new EXIDX_CANTUNWIND is
18676 created, so there is no need to
18677 adjust offset by hand. */
18678 prel31_offset = text_sec->output_offset
18679 + text_sec->size;
491d01d3 18680 }
2468f9c9
PB		 18681
18682 /* First address we can't unwind. */
18683 bfd_put_32 (output_bfd, prel31_offset,
18684 &edited_contents[out_index * 8]);
18685
18686 /* Code for EXIDX_CANTUNWIND. */
18687 bfd_put_32 (output_bfd, 0x1,
18688 &edited_contents[out_index * 8 + 4]);
18689
18690 out_index++;
18691 add_to_offsets -= 8;
18692 }
18693 break;
18694 }
b38cadfb 18695
2468f9c9
PB		 18696 edit_node = edit_node->next;
18697 }
18698 }
18699 else
18700 {
18701 /* No more edits, copy remaining entries verbatim. */
18702 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
18703 contents + in_index * 8, add_to_offsets);
18704 out_index++;
18705 in_index++;
18706 }
18707 }
18708
18709 if (!(sec->flags & SEC_EXCLUDE) && !(sec->flags & SEC_NEVER_LOAD))
18710 bfd_set_section_contents (output_bfd, sec->output_section,
18711 edited_contents,
18712 (file_ptr) sec->output_offset, sec->size);
18713
18714 return TRUE;
18715 }
18716
48229727
JB		 18717 /* Fix code to point to Cortex-A8 erratum stubs. */
18718 if (globals->fix_cortex_a8)
18719 {
18720 struct a8_branch_to_stub_data data;
18721
18722 data.writing_section = sec;
18723 data.contents = contents;
18724
a504d23a
LA		 18725 bfd_hash_traverse (& globals->stub_hash_table, make_branch_to_a8_stub,
18726 & data);
48229727
JB		 18727 }
18728
e489d0ae
PB		 18729 if (mapcount == 0)
18730 return FALSE;
18731
c7b8f16e 18732 if (globals->byteswap_code)
e489d0ae 18733 {
c7b8f16e 18734 qsort (map, mapcount, sizeof (* map), elf32_arm_compare_mapping);
57e8b36a 18735
c7b8f16e
JB		 18736 ptr = map[0].vma;
18737 for (i = 0; i < mapcount; i++)
99059e56
RM		 18738 {
18739 if (i == mapcount - 1)
c7b8f16e 18740 end = sec->size;
99059e56
RM		 18741 else
18742 end = map[i + 1].vma;
e489d0ae 18743
99059e56 18744 switch (map[i].type)
e489d0ae 18745 {
c7b8f16e
JB		 18746 case 'a':
18747 /* Byte swap code words. */
18748 while (ptr + 3 < end)
99059e56
RM		 18749 {
18750 tmp = contents[ptr];
18751 contents[ptr] = contents[ptr + 3];
18752 contents[ptr + 3] = tmp;
18753 tmp = contents[ptr + 1];
18754 contents[ptr + 1] = contents[ptr + 2];
18755 contents[ptr + 2] = tmp;
18756 ptr += 4;
18757 }
c7b8f16e 18758 break;
e489d0ae 18759
c7b8f16e
JB		 18760 case 't':
18761 /* Byte swap code halfwords. */
18762 while (ptr + 1 < end)
99059e56
RM		 18763 {
18764 tmp = contents[ptr];
18765 contents[ptr] = contents[ptr + 1];
18766 contents[ptr + 1] = tmp;
18767 ptr += 2;
18768 }
c7b8f16e
JB		 18769 break;
18770
18771 case 'd':
18772 /* Leave data alone. */
18773 break;
18774 }
99059e56
RM		 18775 ptr = end;
18776 }
e489d0ae 18777 }
8e3de13a 18778
93204d3a 18779 free (map);
47b2e99c 18780 arm_data->mapcount = -1;
c7b8f16e 18781 arm_data->mapsize = 0;
8e3de13a 18782 arm_data->map = NULL;
8e3de13a 18783
e489d0ae
PB		 18784 return FALSE;
18785}
18786
0beaef2b
PB		 18787/* Mangle thumb function symbols as we read them in. */
18788
8384fb8f 18789static bfd_boolean
0beaef2b
PB		 18790elf32_arm_swap_symbol_in (bfd * abfd,
18791 const void *psrc,
18792 const void *pshn,
18793 Elf_Internal_Sym *dst)
18794{
4ba2ef8f
TP		 18795 Elf_Internal_Shdr *symtab_hdr;
18796 const char *name = NULL;
18797
8384fb8f
AM		 18798 if (!bfd_elf32_swap_symbol_in (abfd, psrc, pshn, dst))
18799 return FALSE;
39d911fc 18800 dst->st_target_internal = 0;
0beaef2b
PB		 18801
18802 /* New EABI objects mark thumb function symbols by setting the low bit of
35fc36a8 18803 the address. */
63e1a0fc
PB		 18804 if (ELF_ST_TYPE (dst->st_info) == STT_FUNC
18805 || ELF_ST_TYPE (dst->st_info) == STT_GNU_IFUNC)
0beaef2b 18806 {
63e1a0fc
PB		 18807 if (dst->st_value & 1)
18808 {
18809 dst->st_value &= ~(bfd_vma) 1;
39d911fc
TP		 18810 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal,
18811 ST_BRANCH_TO_THUMB);
63e1a0fc
PB		 18812 }
18813 else
39d911fc 18814 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_ARM);
35fc36a8
RS		 18815 }
18816 else if (ELF_ST_TYPE (dst->st_info) == STT_ARM_TFUNC)
18817 {
18818 dst->st_info = ELF_ST_INFO (ELF_ST_BIND (dst->st_info), STT_FUNC);
39d911fc 18819 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_THUMB);
0beaef2b 18820 }
35fc36a8 18821 else if (ELF_ST_TYPE (dst->st_info) == STT_SECTION)
39d911fc 18822 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_LONG);
35fc36a8 18823 else
39d911fc 18824 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_UNKNOWN);
35fc36a8 18825
4ba2ef8f
TP		 18826 /* Mark CMSE special symbols. */
18827 symtab_hdr = & elf_symtab_hdr (abfd);
18828 if (symtab_hdr->sh_size)
18829 name = bfd_elf_sym_name (abfd, symtab_hdr, dst, NULL);
18830 if (name && CONST_STRNEQ (name, CMSE_PREFIX))
18831 ARM_SET_SYM_CMSE_SPCL (dst->st_target_internal);
18832
8384fb8f 18833 return TRUE;
0beaef2b
PB		 18834}
18835
18836
18837/* Mangle thumb function symbols as we write them out. */
18838
18839static void
18840elf32_arm_swap_symbol_out (bfd *abfd,
18841 const Elf_Internal_Sym *src,
18842 void *cdst,
18843 void *shndx)
18844{
18845 Elf_Internal_Sym newsym;
18846
18847 /* We convert STT_ARM_TFUNC symbols into STT_FUNC with the low bit
18848 of the address set, as per the new EABI. We do this unconditionally
18849 because objcopy does not set the elf header flags until after
18850 it writes out the symbol table. */
39d911fc 18851 if (ARM_GET_SYM_BRANCH_TYPE (src->st_target_internal) == ST_BRANCH_TO_THUMB)
0beaef2b
PB		 18852 {
18853 newsym = *src;
34e77a92
RS		 18854 if (ELF_ST_TYPE (src->st_info) != STT_GNU_IFUNC)
18855 newsym.st_info = ELF_ST_INFO (ELF_ST_BIND (src->st_info), STT_FUNC);
0fa3dcad 18856 if (newsym.st_shndx != SHN_UNDEF)
99059e56
RM		 18857 {
18858 /* Do this only for defined symbols. At link type, the static
18859 linker will simulate the work of dynamic linker of resolving
18860 symbols and will carry over the thumbness of found symbols to
18861 the output symbol table. It's not clear how it happens, but
18862 the thumbness of undefined symbols can well be different at
18863 runtime, and writing '1' for them will be confusing for users
18864 and possibly for dynamic linker itself.
18865 */
18866 newsym.st_value |= 1;
18867 }
906e58ca 18868
0beaef2b
PB		 18869 src = &newsym;
18870 }
18871 bfd_elf32_swap_symbol_out (abfd, src, cdst, shndx);
18872}
18873
b294bdf8
MM		 18874/* Add the PT_ARM_EXIDX program header. */
18875
18876static bfd_boolean
906e58ca 18877elf32_arm_modify_segment_map (bfd *abfd,
b294bdf8
MM		 18878 struct bfd_link_info *info ATTRIBUTE_UNUSED)
18879{
18880 struct elf_segment_map *m;
18881 asection *sec;
18882
18883 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
18884 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
18885 {
18886 /* If there is already a PT_ARM_EXIDX header, then we do not
18887 want to add another one. This situation arises when running
18888 "strip"; the input binary already has the header. */
12bd6957 18889 m = elf_seg_map (abfd);
b294bdf8
MM		 18890 while (m && m->p_type != PT_ARM_EXIDX)
18891 m = m->next;
18892 if (!m)
18893 {
21d799b5 18894 m = (struct elf_segment_map *)
99059e56 18895 bfd_zalloc (abfd, sizeof (struct elf_segment_map));
b294bdf8
MM		 18896 if (m == NULL)
18897 return FALSE;
18898 m->p_type = PT_ARM_EXIDX;
18899 m->count = 1;
18900 m->sections[0] = sec;
18901
12bd6957
AM		 18902 m->next = elf_seg_map (abfd);
18903 elf_seg_map (abfd) = m;
b294bdf8
MM		 18904 }
18905 }
18906
18907 return TRUE;
18908}
18909
18910/* We may add a PT_ARM_EXIDX program header. */
18911
18912static int
a6b96beb
AM		 18913elf32_arm_additional_program_headers (bfd *abfd,
18914 struct bfd_link_info *info ATTRIBUTE_UNUSED)
b294bdf8
MM		 18915{
18916 asection *sec;
18917
18918 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
18919 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
18920 return 1;
18921 else
18922 return 0;
18923}
18924
34e77a92
RS		 18925/* Hook called by the linker routine which adds symbols from an object
18926 file. */
18927
18928static bfd_boolean
18929elf32_arm_add_symbol_hook (bfd *abfd, struct bfd_link_info *info,
18930 Elf_Internal_Sym *sym, const char **namep,
18931 flagword *flagsp, asection **secp, bfd_vma *valp)
18932{
a43942db 18933 if (ELF_ST_TYPE (sym->st_info) == STT_GNU_IFUNC
f1885d1e
AM		 18934 && (abfd->flags & DYNAMIC) == 0
18935 && bfd_get_flavour (info->output_bfd) == bfd_target_elf_flavour)
a43942db 18936 elf_tdata (info->output_bfd)->has_gnu_symbols |= elf_gnu_symbol_ifunc;
34e77a92 18937
c792917c
NC		 18938 if (elf32_arm_hash_table (info) == NULL)
18939 return FALSE;
18940
34e77a92
RS		 18941 if (elf32_arm_hash_table (info)->vxworks_p
18942 && !elf_vxworks_add_symbol_hook (abfd, info, sym, namep,
18943 flagsp, secp, valp))
18944 return FALSE;
18945
18946 return TRUE;
18947}
18948
0beaef2b 18949/* We use this to override swap_symbol_in and swap_symbol_out. */
906e58ca
NC		 18950const struct elf_size_info elf32_arm_size_info =
18951{
0beaef2b
PB		 18952 sizeof (Elf32_External_Ehdr),
18953 sizeof (Elf32_External_Phdr),
18954 sizeof (Elf32_External_Shdr),
18955 sizeof (Elf32_External_Rel),
18956 sizeof (Elf32_External_Rela),
18957 sizeof (Elf32_External_Sym),
18958 sizeof (Elf32_External_Dyn),
18959 sizeof (Elf_External_Note),
18960 4,
18961 1,
18962 32, 2,
18963 ELFCLASS32, EV_CURRENT,
18964 bfd_elf32_write_out_phdrs,
18965 bfd_elf32_write_shdrs_and_ehdr,
1489a3a0 18966 bfd_elf32_checksum_contents,
0beaef2b
PB		 18967 bfd_elf32_write_relocs,
18968 elf32_arm_swap_symbol_in,
18969 elf32_arm_swap_symbol_out,
18970 bfd_elf32_slurp_reloc_table,
18971 bfd_elf32_slurp_symbol_table,
18972 bfd_elf32_swap_dyn_in,
18973 bfd_elf32_swap_dyn_out,
18974 bfd_elf32_swap_reloc_in,
18975 bfd_elf32_swap_reloc_out,
18976 bfd_elf32_swap_reloca_in,
18977 bfd_elf32_swap_reloca_out
18978};
18979
685e70ae
VK		 18980static bfd_vma
18981read_code32 (const bfd *abfd, const bfd_byte *addr)
18982{
18983 /* V7 BE8 code is always little endian. */
18984 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
18985 return bfd_getl32 (addr);
18986
18987 return bfd_get_32 (abfd, addr);
18988}
18989
18990static bfd_vma
18991read_code16 (const bfd *abfd, const bfd_byte *addr)
18992{
18993 /* V7 BE8 code is always little endian. */
18994 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
18995 return bfd_getl16 (addr);
18996
18997 return bfd_get_16 (abfd, addr);
18998}
18999
6a631e86
YG		 19000/* Return size of plt0 entry starting at ADDR
19001 or (bfd_vma) -1 if size can not be determined. */
19002
19003static bfd_vma
19004elf32_arm_plt0_size (const bfd *abfd, const bfd_byte *addr)
19005{
19006 bfd_vma first_word;
19007 bfd_vma plt0_size;
19008
685e70ae 19009 first_word = read_code32 (abfd, addr);
6a631e86
YG		 19010
19011 if (first_word == elf32_arm_plt0_entry[0])
19012 plt0_size = 4 * ARRAY_SIZE (elf32_arm_plt0_entry);
19013 else if (first_word == elf32_thumb2_plt0_entry[0])
19014 plt0_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
19015 else
19016 /* We don't yet handle this PLT format. */
19017 return (bfd_vma) -1;
19018
19019 return plt0_size;
19020}
19021
19022/* Return size of plt entry starting at offset OFFSET
19023 of plt section located at address START
19024 or (bfd_vma) -1 if size can not be determined. */
19025
19026static bfd_vma
19027elf32_arm_plt_size (const bfd *abfd, const bfd_byte *start, bfd_vma offset)
19028{
19029 bfd_vma first_insn;
19030 bfd_vma plt_size = 0;
19031 const bfd_byte *addr = start + offset;
19032
19033 /* PLT entry size if fixed on Thumb-only platforms. */
685e70ae 19034 if (read_code32 (abfd, start) == elf32_thumb2_plt0_entry[0])
6a631e86
YG		 19035 return 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
19036
19037 /* Respect Thumb stub if necessary. */
685e70ae 19038 if (read_code16 (abfd, addr) == elf32_arm_plt_thumb_stub[0])
6a631e86
YG		 19039 {
19040 plt_size += 2 * ARRAY_SIZE(elf32_arm_plt_thumb_stub);
19041 }
19042
19043 /* Strip immediate from first add. */
685e70ae 19044 first_insn = read_code32 (abfd, addr + plt_size) & 0xffffff00;
6a631e86
YG		 19045
19046#ifdef FOUR_WORD_PLT
19047 if (first_insn == elf32_arm_plt_entry[0])
19048 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry);
19049#else
19050 if (first_insn == elf32_arm_plt_entry_long[0])
19051 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_long);
19052 else if (first_insn == elf32_arm_plt_entry_short[0])
19053 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_short);
19054#endif
19055 else
19056 /* We don't yet handle this PLT format. */
19057 return (bfd_vma) -1;
19058
19059 return plt_size;
19060}
19061
19062/* Implementation is shamelessly borrowed from _bfd_elf_get_synthetic_symtab. */
19063
19064static long
19065elf32_arm_get_synthetic_symtab (bfd *abfd,
19066 long symcount ATTRIBUTE_UNUSED,
19067 asymbol **syms ATTRIBUTE_UNUSED,
19068 long dynsymcount,
19069 asymbol **dynsyms,
19070 asymbol **ret)
19071{
19072 asection *relplt;
19073 asymbol *s;
19074 arelent *p;
19075 long count, i, n;
19076 size_t size;
19077 Elf_Internal_Shdr *hdr;
19078 char *names;
19079 asection *plt;
19080 bfd_vma offset;
19081 bfd_byte *data;
19082
19083 *ret = NULL;
19084
19085 if ((abfd->flags & (DYNAMIC | EXEC_P)) == 0)
19086 return 0;
19087
19088 if (dynsymcount <= 0)
19089 return 0;
19090
19091 relplt = bfd_get_section_by_name (abfd, ".rel.plt");
19092 if (relplt == NULL)
19093 return 0;
19094
19095 hdr = &elf_section_data (relplt)->this_hdr;
19096 if (hdr->sh_link != elf_dynsymtab (abfd)
19097 || (hdr->sh_type != SHT_REL && hdr->sh_type != SHT_RELA))
19098 return 0;
19099
19100 plt = bfd_get_section_by_name (abfd, ".plt");
19101 if (plt == NULL)
19102 return 0;
19103
19104 if (!elf32_arm_size_info.slurp_reloc_table (abfd, relplt, dynsyms, TRUE))
19105 return -1;
19106
19107 data = plt->contents;
19108 if (data == NULL)
19109 {
19110 if (!bfd_get_full_section_contents(abfd, (asection *) plt, &data) || data == NULL)
19111 return -1;
19112 bfd_cache_section_contents((asection *) plt, data);
19113 }
19114
19115 count = relplt->size / hdr->sh_entsize;
19116 size = count * sizeof (asymbol);
19117 p = relplt->relocation;
19118 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
19119 {
19120 size += strlen ((*p->sym_ptr_ptr)->name) + sizeof ("@plt");
19121 if (p->addend != 0)
19122 size += sizeof ("+0x") - 1 + 8;
19123 }
19124
19125 s = *ret = (asymbol *) bfd_malloc (size);
19126 if (s == NULL)
19127 return -1;
19128
19129 offset = elf32_arm_plt0_size (abfd, data);
19130 if (offset == (bfd_vma) -1)
19131 return -1;
19132
19133 names = (char *) (s + count);
19134 p = relplt->relocation;
19135 n = 0;
19136 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
19137 {
19138 size_t len;
19139
19140 bfd_vma plt_size = elf32_arm_plt_size (abfd, data, offset);
19141 if (plt_size == (bfd_vma) -1)
19142 break;
19143
19144 *s = **p->sym_ptr_ptr;
19145 /* Undefined syms won't have BSF_LOCAL or BSF_GLOBAL set. Since
19146 we are defining a symbol, ensure one of them is set. */
19147 if ((s->flags & BSF_LOCAL) == 0)
19148 s->flags |= BSF_GLOBAL;
19149 s->flags |= BSF_SYNTHETIC;
19150 s->section = plt;
19151 s->value = offset;
19152 s->name = names;
19153 s->udata.p = NULL;
19154 len = strlen ((*p->sym_ptr_ptr)->name);
19155 memcpy (names, (*p->sym_ptr_ptr)->name, len);
19156 names += len;
19157 if (p->addend != 0)
19158 {
19159 char buf[30], *a;
19160
19161 memcpy (names, "+0x", sizeof ("+0x") - 1);
19162 names += sizeof ("+0x") - 1;
19163 bfd_sprintf_vma (abfd, buf, p->addend);
19164 for (a = buf; *a == '0'; ++a)
19165 ;
19166 len = strlen (a);
19167 memcpy (names, a, len);
19168 names += len;
19169 }
19170 memcpy (names, "@plt", sizeof ("@plt"));
19171 names += sizeof ("@plt");
19172 ++s, ++n;
19173 offset += plt_size;
19174 }
19175
19176 return n;
19177}
19178
ac4c9b04
MG		 19179static bfd_boolean
19180elf32_arm_section_flags (flagword *flags, const Elf_Internal_Shdr * hdr)
19181{
f0728ee3
AV		 19182 if (hdr->sh_flags & SHF_ARM_PURECODE)
19183 *flags |= SEC_ELF_PURECODE;
ac4c9b04
MG		 19184 return TRUE;
19185}
19186
19187static flagword
19188elf32_arm_lookup_section_flags (char *flag_name)
19189{
f0728ee3
AV		 19190 if (!strcmp (flag_name, "SHF_ARM_PURECODE"))
19191 return SHF_ARM_PURECODE;
ac4c9b04
MG		 19192
19193 return SEC_NO_FLAGS;
19194}
19195
491d01d3
YU		 19196static unsigned int
19197elf32_arm_count_additional_relocs (asection *sec)
19198{
19199 struct _arm_elf_section_data *arm_data;
19200 arm_data = get_arm_elf_section_data (sec);
5025eb7c 19201
6342be70 19202 return arm_data == NULL ? 0 : arm_data->additional_reloc_count;
491d01d3
YU		 19203}
19204
5522f910 19205/* Called to set the sh_flags, sh_link and sh_info fields of OSECTION which
9eaff861 19206 has a type >= SHT_LOOS. Returns TRUE if these fields were initialised
5522f910
NC		 19207 FALSE otherwise. ISECTION is the best guess matching section from the
19208 input bfd IBFD, but it might be NULL. */
19209
19210static bfd_boolean
19211elf32_arm_copy_special_section_fields (const bfd *ibfd ATTRIBUTE_UNUSED,
19212 bfd *obfd ATTRIBUTE_UNUSED,
19213 const Elf_Internal_Shdr *isection ATTRIBUTE_UNUSED,
19214 Elf_Internal_Shdr *osection)
19215{
19216 switch (osection->sh_type)
19217 {
19218 case SHT_ARM_EXIDX:
19219 {
19220 Elf_Internal_Shdr **oheaders = elf_elfsections (obfd);
19221 Elf_Internal_Shdr **iheaders = elf_elfsections (ibfd);
19222 unsigned i = 0;
19223
19224 osection->sh_flags = SHF_ALLOC | SHF_LINK_ORDER;
19225 osection->sh_info = 0;
19226
19227 /* The sh_link field must be set to the text section associated with
19228 this index section. Unfortunately the ARM EHABI does not specify
19229 exactly how to determine this association. Our caller does try
19230 to match up OSECTION with its corresponding input section however
19231 so that is a good first guess. */
19232 if (isection != NULL
19233 && osection->bfd_section != NULL
19234 && isection->bfd_section != NULL
19235 && isection->bfd_section->output_section != NULL
19236 && isection->bfd_section->output_section == osection->bfd_section
19237 && iheaders != NULL
19238 && isection->sh_link > 0
19239 && isection->sh_link < elf_numsections (ibfd)
19240 && iheaders[isection->sh_link]->bfd_section != NULL
19241 && iheaders[isection->sh_link]->bfd_section->output_section != NULL
19242 )
19243 {
19244 for (i = elf_numsections (obfd); i-- > 0;)
19245 if (oheaders[i]->bfd_section
19246 == iheaders[isection->sh_link]->bfd_section->output_section)
19247 break;
19248 }
9eaff861 19249
5522f910
NC		 19250 if (i == 0)
19251 {
19252 /* Failing that we have to find a matching section ourselves. If
19253 we had the output section name available we could compare that
19254 with input section names. Unfortunately we don't. So instead
19255 we use a simple heuristic and look for the nearest executable
19256 section before this one. */
19257 for (i = elf_numsections (obfd); i-- > 0;)
19258 if (oheaders[i] == osection)
19259 break;
19260 if (i == 0)
19261 break;
19262
19263 while (i-- > 0)
19264 if (oheaders[i]->sh_type == SHT_PROGBITS
19265 && (oheaders[i]->sh_flags & (SHF_ALLOC | SHF_EXECINSTR))
19266 == (SHF_ALLOC | SHF_EXECINSTR))
19267 break;
19268 }
19269
19270 if (i)
19271 {
19272 osection->sh_link = i;
19273 /* If the text section was part of a group
19274 then the index section should be too. */
19275 if (oheaders[i]->sh_flags & SHF_GROUP)
19276 osection->sh_flags |= SHF_GROUP;
19277 return TRUE;
19278 }
19279 }
19280 break;
19281
19282 case SHT_ARM_PREEMPTMAP:
19283 osection->sh_flags = SHF_ALLOC;
19284 break;
19285
19286 case SHT_ARM_ATTRIBUTES:
19287 case SHT_ARM_DEBUGOVERLAY:
19288 case SHT_ARM_OVERLAYSECTION:
19289 default:
19290 break;
19291 }
19292
19293 return FALSE;
19294}
19295
d691934d
NC		 19296/* Returns TRUE if NAME is an ARM mapping symbol.
19297 Traditionally the symbols $a, $d and $t have been used.
19298 The ARM ELF standard also defines $x (for A64 code). It also allows a
19299 period initiated suffix to be added to the symbol: "$[adtx]\.[:sym_char]+".
19300 Other tools might also produce $b (Thumb BL), $f, $p, $m and $v, but we do
19301 not support them here. $t.x indicates the start of ThumbEE instructions. */
19302
19303static bfd_boolean
19304is_arm_mapping_symbol (const char * name)
19305{
19306 return name != NULL /* Paranoia. */
19307 && name[0] == '$' /* Note: if objcopy --prefix-symbols has been used then
19308 the mapping symbols could have acquired a prefix.
19309 We do not support this here, since such symbols no
19310 longer conform to the ARM ELF ABI. */
19311 && (name[1] == 'a' || name[1] == 'd' || name[1] == 't' || name[1] == 'x')
19312 && (name[2] == 0 || name[2] == '.');
19313 /* FIXME: Strictly speaking the symbol is only a valid mapping symbol if
19314 any characters that follow the period are legal characters for the body
19315 of a symbol's name. For now we just assume that this is the case. */
19316}
19317
fca2a38f
NC		 19318/* Make sure that mapping symbols in object files are not removed via the
19319 "strip --strip-unneeded" tool. These symbols are needed in order to
19320 correctly generate interworking veneers, and for byte swapping code
19321 regions. Once an object file has been linked, it is safe to remove the
19322 symbols as they will no longer be needed. */
19323
19324static void
19325elf32_arm_backend_symbol_processing (bfd *abfd, asymbol *sym)
19326{
19327 if (((abfd->flags & (EXEC_P | DYNAMIC)) == 0)
fca2a38f 19328 && sym->section != bfd_abs_section_ptr
d691934d 19329 && is_arm_mapping_symbol (sym->name))
fca2a38f
NC		 19330 sym->flags |= BSF_KEEP;
19331}
19332
5522f910
NC		 19333#undef elf_backend_copy_special_section_fields
19334#define elf_backend_copy_special_section_fields elf32_arm_copy_special_section_fields
19335
252b5132 19336#define ELF_ARCH bfd_arch_arm
ae95ffa6 19337#define ELF_TARGET_ID ARM_ELF_DATA
252b5132 19338#define ELF_MACHINE_CODE EM_ARM
d0facd1b
NC		 19339#ifdef __QNXTARGET__
19340#define ELF_MAXPAGESIZE 0x1000
19341#else
7572ca89 19342#define ELF_MAXPAGESIZE 0x10000
d0facd1b 19343#endif
b1342370 19344#define ELF_MINPAGESIZE 0x1000
24718e3b 19345#define ELF_COMMONPAGESIZE 0x1000
252b5132 19346
ba93b8ac
DJ		 19347#define bfd_elf32_mkobject elf32_arm_mkobject
19348
99e4ae17
AJ		 19349#define bfd_elf32_bfd_copy_private_bfd_data elf32_arm_copy_private_bfd_data
19350#define bfd_elf32_bfd_merge_private_bfd_data elf32_arm_merge_private_bfd_data
252b5132
RH		 19351#define bfd_elf32_bfd_set_private_flags elf32_arm_set_private_flags
19352#define bfd_elf32_bfd_print_private_bfd_data elf32_arm_print_private_bfd_data
19353#define bfd_elf32_bfd_link_hash_table_create elf32_arm_link_hash_table_create
dc810e39 19354#define bfd_elf32_bfd_reloc_type_lookup elf32_arm_reloc_type_lookup
b38cadfb 19355#define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
252b5132 19356#define bfd_elf32_find_nearest_line elf32_arm_find_nearest_line
4ab527b0 19357#define bfd_elf32_find_inliner_info elf32_arm_find_inliner_info
e489d0ae 19358#define bfd_elf32_new_section_hook elf32_arm_new_section_hook
3c9458e9 19359#define bfd_elf32_bfd_is_target_special_symbol elf32_arm_is_target_special_symbol
3e6b1042 19360#define bfd_elf32_bfd_final_link elf32_arm_final_link
6a631e86 19361#define bfd_elf32_get_synthetic_symtab elf32_arm_get_synthetic_symtab
252b5132
RH		 19362
19363#define elf_backend_get_symbol_type elf32_arm_get_symbol_type
19364#define elf_backend_gc_mark_hook elf32_arm_gc_mark_hook
6a5bb875 19365#define elf_backend_gc_mark_extra_sections elf32_arm_gc_mark_extra_sections
252b5132
RH		 19366#define elf_backend_gc_sweep_hook elf32_arm_gc_sweep_hook
19367#define elf_backend_check_relocs elf32_arm_check_relocs
9eaff861 19368#define elf_backend_update_relocs elf32_arm_update_relocs
dc810e39 19369#define elf_backend_relocate_section elf32_arm_relocate_section
e489d0ae 19370#define elf_backend_write_section elf32_arm_write_section
252b5132 19371#define elf_backend_adjust_dynamic_symbol elf32_arm_adjust_dynamic_symbol
5e681ec4 19372#define elf_backend_create_dynamic_sections elf32_arm_create_dynamic_sections
252b5132
RH		 19373#define elf_backend_finish_dynamic_symbol elf32_arm_finish_dynamic_symbol
19374#define elf_backend_finish_dynamic_sections elf32_arm_finish_dynamic_sections
19375#define elf_backend_size_dynamic_sections elf32_arm_size_dynamic_sections
0855e32b 19376#define elf_backend_always_size_sections elf32_arm_always_size_sections
74541ad4 19377#define elf_backend_init_index_section _bfd_elf_init_2_index_sections
ba96a88f 19378#define elf_backend_post_process_headers elf32_arm_post_process_headers
99e4ae17 19379#define elf_backend_reloc_type_class elf32_arm_reloc_type_class
c178919b 19380#define elf_backend_object_p elf32_arm_object_p
40a18ebd
NC		 19381#define elf_backend_fake_sections elf32_arm_fake_sections
19382#define elf_backend_section_from_shdr elf32_arm_section_from_shdr
e16bb312 19383#define elf_backend_final_write_processing elf32_arm_final_write_processing
5e681ec4 19384#define elf_backend_copy_indirect_symbol elf32_arm_copy_indirect_symbol
0beaef2b 19385#define elf_backend_size_info elf32_arm_size_info
b294bdf8 19386#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
906e58ca
NC		 19387#define elf_backend_additional_program_headers elf32_arm_additional_program_headers
19388#define elf_backend_output_arch_local_syms elf32_arm_output_arch_local_syms
54ddd295 19389#define elf_backend_filter_implib_symbols elf32_arm_filter_implib_symbols
906e58ca 19390#define elf_backend_begin_write_processing elf32_arm_begin_write_processing
34e77a92 19391#define elf_backend_add_symbol_hook elf32_arm_add_symbol_hook
491d01d3 19392#define elf_backend_count_additional_relocs elf32_arm_count_additional_relocs
fca2a38f 19393#define elf_backend_symbol_processing elf32_arm_backend_symbol_processing
906e58ca
NC		 19394
19395#define elf_backend_can_refcount 1
19396#define elf_backend_can_gc_sections 1
19397#define elf_backend_plt_readonly 1
19398#define elf_backend_want_got_plt 1
19399#define elf_backend_want_plt_sym 0
5474d94f 19400#define elf_backend_want_dynrelro 1
906e58ca
NC		 19401#define elf_backend_may_use_rel_p 1
19402#define elf_backend_may_use_rela_p 0
4e7fd91e 19403#define elf_backend_default_use_rela_p 0
64f52338 19404#define elf_backend_dtrel_excludes_plt 1
252b5132 19405
04f7c78d 19406#define elf_backend_got_header_size 12
b68a20d6 19407#define elf_backend_extern_protected_data 1
04f7c78d 19408
906e58ca
NC		 19409#undef elf_backend_obj_attrs_vendor
19410#define elf_backend_obj_attrs_vendor "aeabi"
19411#undef elf_backend_obj_attrs_section
19412#define elf_backend_obj_attrs_section ".ARM.attributes"
19413#undef elf_backend_obj_attrs_arg_type
19414#define elf_backend_obj_attrs_arg_type elf32_arm_obj_attrs_arg_type
19415#undef elf_backend_obj_attrs_section_type
104d59d1 19416#define elf_backend_obj_attrs_section_type SHT_ARM_ATTRIBUTES
b38cadfb
NC		 19417#define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
19418#define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
104d59d1 19419
5025eb7c 19420#undef elf_backend_section_flags
ac4c9b04 19421#define elf_backend_section_flags elf32_arm_section_flags
5025eb7c 19422#undef elf_backend_lookup_section_flags_hook
ac4c9b04
MG		 19423#define elf_backend_lookup_section_flags_hook elf32_arm_lookup_section_flags
19424
252b5132 19425#include "elf32-target.h"
7f266840 19426
b38cadfb
NC		 19427/* Native Client targets. */
19428
19429#undef TARGET_LITTLE_SYM
6d00b590 19430#define TARGET_LITTLE_SYM arm_elf32_nacl_le_vec
b38cadfb
NC		 19431#undef TARGET_LITTLE_NAME
19432#define TARGET_LITTLE_NAME "elf32-littlearm-nacl"
19433#undef TARGET_BIG_SYM
6d00b590 19434#define TARGET_BIG_SYM arm_elf32_nacl_be_vec
b38cadfb
NC		 19435#undef TARGET_BIG_NAME
19436#define TARGET_BIG_NAME "elf32-bigarm-nacl"
19437
19438/* Like elf32_arm_link_hash_table_create -- but overrides
19439 appropriately for NaCl. */
19440
19441static struct bfd_link_hash_table *
19442elf32_arm_nacl_link_hash_table_create (bfd *abfd)
19443{
19444 struct bfd_link_hash_table *ret;
19445
19446 ret = elf32_arm_link_hash_table_create (abfd);
19447 if (ret)
19448 {
19449 struct elf32_arm_link_hash_table *htab
19450 = (struct elf32_arm_link_hash_table *) ret;
19451
19452 htab->nacl_p = 1;
19453
19454 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt0_entry);
19455 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt_entry);
19456 }
19457 return ret;
19458}
19459
19460/* Since NaCl doesn't use the ARM-specific unwind format, we don't
19461 really need to use elf32_arm_modify_segment_map. But we do it
19462 anyway just to reduce gratuitous differences with the stock ARM backend. */
19463
19464static bfd_boolean
19465elf32_arm_nacl_modify_segment_map (bfd *abfd, struct bfd_link_info *info)
19466{
19467 return (elf32_arm_modify_segment_map (abfd, info)
19468 && nacl_modify_segment_map (abfd, info));
19469}
19470
887badb3
RM		 19471static void
19472elf32_arm_nacl_final_write_processing (bfd *abfd, bfd_boolean linker)
19473{
19474 elf32_arm_final_write_processing (abfd, linker);
19475 nacl_final_write_processing (abfd, linker);
19476}
19477
6a631e86
YG		 19478static bfd_vma
19479elf32_arm_nacl_plt_sym_val (bfd_vma i, const asection *plt,
19480 const arelent *rel ATTRIBUTE_UNUSED)
19481{
19482 return plt->vma
19483 + 4 * (ARRAY_SIZE (elf32_arm_nacl_plt0_entry) +
19484 i * ARRAY_SIZE (elf32_arm_nacl_plt_entry));
19485}
887badb3 19486
b38cadfb 19487#undef elf32_bed
6a631e86 19488#define elf32_bed elf32_arm_nacl_bed
b38cadfb
NC		 19489#undef bfd_elf32_bfd_link_hash_table_create
19490#define bfd_elf32_bfd_link_hash_table_create \
19491 elf32_arm_nacl_link_hash_table_create
19492#undef elf_backend_plt_alignment
6a631e86 19493#define elf_backend_plt_alignment 4
b38cadfb
NC		 19494#undef elf_backend_modify_segment_map
19495#define elf_backend_modify_segment_map elf32_arm_nacl_modify_segment_map
19496#undef elf_backend_modify_program_headers
19497#define elf_backend_modify_program_headers nacl_modify_program_headers
887badb3
RM		 19498#undef elf_backend_final_write_processing
19499#define elf_backend_final_write_processing elf32_arm_nacl_final_write_processing
6a631e86
YG		 19500#undef bfd_elf32_get_synthetic_symtab
19501#undef elf_backend_plt_sym_val
19502#define elf_backend_plt_sym_val elf32_arm_nacl_plt_sym_val
5522f910 19503#undef elf_backend_copy_special_section_fields
b38cadfb 19504
887badb3
RM		 19505#undef ELF_MINPAGESIZE
19506#undef ELF_COMMONPAGESIZE
19507
b38cadfb
NC		 19508
19509#include "elf32-target.h"
19510
19511/* Reset to defaults. */
19512#undef elf_backend_plt_alignment
19513#undef elf_backend_modify_segment_map
19514#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
19515#undef elf_backend_modify_program_headers
887badb3
RM		 19516#undef elf_backend_final_write_processing
19517#define elf_backend_final_write_processing elf32_arm_final_write_processing
19518#undef ELF_MINPAGESIZE
19519#define ELF_MINPAGESIZE 0x1000
19520#undef ELF_COMMONPAGESIZE
19521#define ELF_COMMONPAGESIZE 0x1000
19522
b38cadfb 19523
906e58ca 19524/* VxWorks Targets. */
4e7fd91e 19525
906e58ca 19526#undef TARGET_LITTLE_SYM
6d00b590 19527#define TARGET_LITTLE_SYM arm_elf32_vxworks_le_vec
906e58ca 19528#undef TARGET_LITTLE_NAME
4e7fd91e 19529#define TARGET_LITTLE_NAME "elf32-littlearm-vxworks"
906e58ca 19530#undef TARGET_BIG_SYM
6d00b590 19531#define TARGET_BIG_SYM arm_elf32_vxworks_be_vec
906e58ca 19532#undef TARGET_BIG_NAME
4e7fd91e
PB		 19533#define TARGET_BIG_NAME "elf32-bigarm-vxworks"
19534
19535/* Like elf32_arm_link_hash_table_create -- but overrides
19536 appropriately for VxWorks. */
906e58ca 19537
4e7fd91e
PB		 19538static struct bfd_link_hash_table *
19539elf32_arm_vxworks_link_hash_table_create (bfd *abfd)
19540{
19541 struct bfd_link_hash_table *ret;
19542
19543 ret = elf32_arm_link_hash_table_create (abfd);
19544 if (ret)
19545 {
19546 struct elf32_arm_link_hash_table *htab
00a97672 19547 = (struct elf32_arm_link_hash_table *) ret;
4e7fd91e 19548 htab->use_rel = 0;
00a97672 19549 htab->vxworks_p = 1;
4e7fd91e
PB		 19550 }
19551 return ret;
906e58ca 19552}
4e7fd91e 19553
00a97672
RS		 19554static void
19555elf32_arm_vxworks_final_write_processing (bfd *abfd, bfd_boolean linker)
19556{
19557 elf32_arm_final_write_processing (abfd, linker);
19558 elf_vxworks_final_write_processing (abfd, linker);
19559}
19560
906e58ca 19561#undef elf32_bed
4e7fd91e
PB		 19562#define elf32_bed elf32_arm_vxworks_bed
19563
906e58ca
NC		 19564#undef bfd_elf32_bfd_link_hash_table_create
19565#define bfd_elf32_bfd_link_hash_table_create elf32_arm_vxworks_link_hash_table_create
906e58ca
NC		 19566#undef elf_backend_final_write_processing
19567#define elf_backend_final_write_processing elf32_arm_vxworks_final_write_processing
19568#undef elf_backend_emit_relocs
9eaff861 19569#define elf_backend_emit_relocs elf_vxworks_emit_relocs
4e7fd91e 19570
906e58ca 19571#undef elf_backend_may_use_rel_p
00a97672 19572#define elf_backend_may_use_rel_p 0
906e58ca 19573#undef elf_backend_may_use_rela_p
00a97672 19574#define elf_backend_may_use_rela_p 1
906e58ca 19575#undef elf_backend_default_use_rela_p
00a97672 19576#define elf_backend_default_use_rela_p 1
906e58ca 19577#undef elf_backend_want_plt_sym
00a97672 19578#define elf_backend_want_plt_sym 1
906e58ca 19579#undef ELF_MAXPAGESIZE
00a97672 19580#define ELF_MAXPAGESIZE 0x1000
4e7fd91e
PB		 19581
19582#include "elf32-target.h"
19583
19584
21d799b5
NC		 19585/* Merge backend specific data from an object file to the output
19586 object file when linking. */
19587
19588static bfd_boolean
50e03d47 19589elf32_arm_merge_private_bfd_data (bfd *ibfd, struct bfd_link_info *info)
21d799b5 19590{
50e03d47 19591 bfd *obfd = info->output_bfd;
21d799b5
NC		 19592 flagword out_flags;
19593 flagword in_flags;
19594 bfd_boolean flags_compatible = TRUE;
19595 asection *sec;
19596
cc643b88 19597 /* Check if we have the same endianness. */
50e03d47 19598 if (! _bfd_generic_verify_endian_match (ibfd, info))
21d799b5
NC		 19599 return FALSE;
19600
19601 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
19602 return TRUE;
19603
50e03d47 19604 if (!elf32_arm_merge_eabi_attributes (ibfd, info))
21d799b5
NC		 19605 return FALSE;
19606
19607 /* The input BFD must have had its flags initialised. */
19608 /* The following seems bogus to me -- The flags are initialized in
19609 the assembler but I don't think an elf_flags_init field is
19610 written into the object. */
19611 /* BFD_ASSERT (elf_flags_init (ibfd)); */
19612
19613 in_flags = elf_elfheader (ibfd)->e_flags;
19614 out_flags = elf_elfheader (obfd)->e_flags;
19615
19616 /* In theory there is no reason why we couldn't handle this. However
19617 in practice it isn't even close to working and there is no real
19618 reason to want it. */
19619 if (EF_ARM_EABI_VERSION (in_flags) >= EF_ARM_EABI_VER4
19620 && !(ibfd->flags & DYNAMIC)
19621 && (in_flags & EF_ARM_BE8))
19622 {
19623 _bfd_error_handler (_("error: %B is already in final BE8 format"),
19624 ibfd);
19625 return FALSE;
19626 }
19627
19628 if (!elf_flags_init (obfd))
19629 {
19630 /* If the input is the default architecture and had the default
19631 flags then do not bother setting the flags for the output
19632 architecture, instead allow future merges to do this. If no
19633 future merges ever set these flags then they will retain their
99059e56
RM		 19634 uninitialised values, which surprise surprise, correspond
19635 to the default values. */
21d799b5
NC		 19636 if (bfd_get_arch_info (ibfd)->the_default
19637 && elf_elfheader (ibfd)->e_flags == 0)
19638 return TRUE;
19639
19640 elf_flags_init (obfd) = TRUE;
19641 elf_elfheader (obfd)->e_flags = in_flags;
19642
19643 if (bfd_get_arch (obfd) == bfd_get_arch (ibfd)
19644 && bfd_get_arch_info (obfd)->the_default)
19645 return bfd_set_arch_mach (obfd, bfd_get_arch (ibfd), bfd_get_mach (ibfd));
19646
19647 return TRUE;
19648 }
19649
19650 /* Determine what should happen if the input ARM architecture
19651 does not match the output ARM architecture. */
19652 if (! bfd_arm_merge_machines (ibfd, obfd))
19653 return FALSE;
19654
19655 /* Identical flags must be compatible. */
19656 if (in_flags == out_flags)
19657 return TRUE;
19658
19659 /* Check to see if the input BFD actually contains any sections. If
19660 not, its flags may not have been initialised either, but it
19661 cannot actually cause any incompatiblity. Do not short-circuit
19662 dynamic objects; their section list may be emptied by
19663 elf_link_add_object_symbols.
19664
19665 Also check to see if there are no code sections in the input.
19666 In this case there is no need to check for code specific flags.
19667 XXX - do we need to worry about floating-point format compatability
19668 in data sections ? */
19669 if (!(ibfd->flags & DYNAMIC))
19670 {
19671 bfd_boolean null_input_bfd = TRUE;
19672 bfd_boolean only_data_sections = TRUE;
19673
19674 for (sec = ibfd->sections; sec != NULL; sec = sec->next)
19675 {
19676 /* Ignore synthetic glue sections. */
19677 if (strcmp (sec->name, ".glue_7")
19678 && strcmp (sec->name, ".glue_7t"))
19679 {
19680 if ((bfd_get_section_flags (ibfd, sec)
19681 & (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
19682 == (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
99059e56 19683 only_data_sections = FALSE;
21d799b5
NC		 19684
19685 null_input_bfd = FALSE;
19686 break;
19687 }
19688 }
19689
19690 if (null_input_bfd || only_data_sections)
19691 return TRUE;
19692 }
19693
19694 /* Complain about various flag mismatches. */
19695 if (!elf32_arm_versions_compatible (EF_ARM_EABI_VERSION (in_flags),
19696 EF_ARM_EABI_VERSION (out_flags)))
19697 {
19698 _bfd_error_handler
19699 (_("error: Source object %B has EABI version %d, but target %B has EABI version %d"),
c08bb8dd
AM		 19700 ibfd, (in_flags & EF_ARM_EABIMASK) >> 24,
19701 obfd, (out_flags & EF_ARM_EABIMASK) >> 24);
21d799b5
NC		 19702 return FALSE;
19703 }
19704
19705 /* Not sure what needs to be checked for EABI versions >= 1. */
19706 /* VxWorks libraries do not use these flags. */
19707 if (get_elf_backend_data (obfd) != &elf32_arm_vxworks_bed
19708 && get_elf_backend_data (ibfd) != &elf32_arm_vxworks_bed
19709 && EF_ARM_EABI_VERSION (in_flags) == EF_ARM_EABI_UNKNOWN)
19710 {
19711 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
19712 {
19713 _bfd_error_handler
19714 (_("error: %B is compiled for APCS-%d, whereas target %B uses APCS-%d"),
c08bb8dd
AM		 19715 ibfd, in_flags & EF_ARM_APCS_26 ? 26 : 32,
19716 obfd, out_flags & EF_ARM_APCS_26 ? 26 : 32);
21d799b5
NC		 19717 flags_compatible = FALSE;
19718 }
19719
19720 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
19721 {
19722 if (in_flags & EF_ARM_APCS_FLOAT)
19723 _bfd_error_handler
19724 (_("error: %B passes floats in float registers, whereas %B passes them in integer registers"),
19725 ibfd, obfd);
19726 else
19727 _bfd_error_handler
19728 (_("error: %B passes floats in integer registers, whereas %B passes them in float registers"),
19729 ibfd, obfd);
19730
19731 flags_compatible = FALSE;
19732 }
19733
19734 if ((in_flags & EF_ARM_VFP_FLOAT) != (out_flags & EF_ARM_VFP_FLOAT))
19735 {
19736 if (in_flags & EF_ARM_VFP_FLOAT)
19737 _bfd_error_handler
19738 (_("error: %B uses VFP instructions, whereas %B does not"),
19739 ibfd, obfd);
19740 else
19741 _bfd_error_handler
19742 (_("error: %B uses FPA instructions, whereas %B does not"),
19743 ibfd, obfd);
19744
19745 flags_compatible = FALSE;
19746 }
19747
19748 if ((in_flags & EF_ARM_MAVERICK_FLOAT) != (out_flags & EF_ARM_MAVERICK_FLOAT))
19749 {
19750 if (in_flags & EF_ARM_MAVERICK_FLOAT)
19751 _bfd_error_handler
19752 (_("error: %B uses Maverick instructions, whereas %B does not"),
19753 ibfd, obfd);
19754 else
19755 _bfd_error_handler
19756 (_("error: %B does not use Maverick instructions, whereas %B does"),
19757 ibfd, obfd);
19758
19759 flags_compatible = FALSE;
19760 }
19761
19762#ifdef EF_ARM_SOFT_FLOAT
19763 if ((in_flags & EF_ARM_SOFT_FLOAT) != (out_flags & EF_ARM_SOFT_FLOAT))
19764 {
19765 /* We can allow interworking between code that is VFP format
19766 layout, and uses either soft float or integer regs for
19767 passing floating point arguments and results. We already
19768 know that the APCS_FLOAT flags match; similarly for VFP
19769 flags. */
19770 if ((in_flags & EF_ARM_APCS_FLOAT) != 0
19771 || (in_flags & EF_ARM_VFP_FLOAT) == 0)
19772 {
19773 if (in_flags & EF_ARM_SOFT_FLOAT)
19774 _bfd_error_handler
19775 (_("error: %B uses software FP, whereas %B uses hardware FP"),
19776 ibfd, obfd);
19777 else
19778 _bfd_error_handler
19779 (_("error: %B uses hardware FP, whereas %B uses software FP"),
19780 ibfd, obfd);
19781
19782 flags_compatible = FALSE;
19783 }
19784 }
19785#endif
19786
19787 /* Interworking mismatch is only a warning. */
19788 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
19789 {
19790 if (in_flags & EF_ARM_INTERWORK)
19791 {
19792 _bfd_error_handler
19793 (_("Warning: %B supports interworking, whereas %B does not"),
19794 ibfd, obfd);
19795 }
19796 else
19797 {
19798 _bfd_error_handler
19799 (_("Warning: %B does not support interworking, whereas %B does"),
19800 ibfd, obfd);
19801 }
19802 }
19803 }
19804
19805 return flags_compatible;
19806}
19807
19808
906e58ca 19809/* Symbian OS Targets. */
7f266840 19810
906e58ca 19811#undef TARGET_LITTLE_SYM
6d00b590 19812#define TARGET_LITTLE_SYM arm_elf32_symbian_le_vec
906e58ca 19813#undef TARGET_LITTLE_NAME
7f266840 19814#define TARGET_LITTLE_NAME "elf32-littlearm-symbian"
906e58ca 19815#undef TARGET_BIG_SYM
6d00b590 19816#define TARGET_BIG_SYM arm_elf32_symbian_be_vec
906e58ca 19817#undef TARGET_BIG_NAME
7f266840
DJ		 19818#define TARGET_BIG_NAME "elf32-bigarm-symbian"
19819
19820/* Like elf32_arm_link_hash_table_create -- but overrides
19821 appropriately for Symbian OS. */
906e58ca 19822
7f266840
DJ		 19823static struct bfd_link_hash_table *
19824elf32_arm_symbian_link_hash_table_create (bfd *abfd)
19825{
19826 struct bfd_link_hash_table *ret;
19827
19828 ret = elf32_arm_link_hash_table_create (abfd);
19829 if (ret)
19830 {
19831 struct elf32_arm_link_hash_table *htab
19832 = (struct elf32_arm_link_hash_table *)ret;
19833 /* There is no PLT header for Symbian OS. */
19834 htab->plt_header_size = 0;
95720a86
DJ		 19835 /* The PLT entries are each one instruction and one word. */
19836 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry);
7f266840 19837 htab->symbian_p = 1;
33bfe774
JB		 19838 /* Symbian uses armv5t or above, so use_blx is always true. */
19839 htab->use_blx = 1;
67687978 19840 htab->root.is_relocatable_executable = 1;
7f266840
DJ		 19841 }
19842 return ret;
906e58ca 19843}
7f266840 19844
b35d266b 19845static const struct bfd_elf_special_section
551b43fd 19846elf32_arm_symbian_special_sections[] =
7f266840 19847{
5cd3778d
MM		 19848 /* In a BPABI executable, the dynamic linking sections do not go in
19849 the loadable read-only segment. The post-linker may wish to
19850 refer to these sections, but they are not part of the final
19851 program image. */
0112cd26
NC		 19852 { STRING_COMMA_LEN (".dynamic"), 0, SHT_DYNAMIC, 0 },
19853 { STRING_COMMA_LEN (".dynstr"), 0, SHT_STRTAB, 0 },
19854 { STRING_COMMA_LEN (".dynsym"), 0, SHT_DYNSYM, 0 },
19855 { STRING_COMMA_LEN (".got"), 0, SHT_PROGBITS, 0 },
19856 { STRING_COMMA_LEN (".hash"), 0, SHT_HASH, 0 },
5cd3778d
MM		 19857 /* These sections do not need to be writable as the SymbianOS
19858 postlinker will arrange things so that no dynamic relocation is
19859 required. */
0112cd26
NC		 19860 { STRING_COMMA_LEN (".init_array"), 0, SHT_INIT_ARRAY, SHF_ALLOC },
19861 { STRING_COMMA_LEN (".fini_array"), 0, SHT_FINI_ARRAY, SHF_ALLOC },
19862 { STRING_COMMA_LEN (".preinit_array"), 0, SHT_PREINIT_ARRAY, SHF_ALLOC },
19863 { NULL, 0, 0, 0, 0 }
7f266840
DJ		 19864};
19865
c3c76620 19866static void
906e58ca 19867elf32_arm_symbian_begin_write_processing (bfd *abfd,
a4fd1a8e 19868 struct bfd_link_info *link_info)
c3c76620
MM		 19869{
19870 /* BPABI objects are never loaded directly by an OS kernel; they are
19871 processed by a postlinker first, into an OS-specific format. If
19872 the D_PAGED bit is set on the file, BFD will align segments on
19873 page boundaries, so that an OS can directly map the file. With
19874 BPABI objects, that just results in wasted space. In addition,
19875 because we clear the D_PAGED bit, map_sections_to_segments will
19876 recognize that the program headers should not be mapped into any
19877 loadable segment. */
19878 abfd->flags &= ~D_PAGED;
906e58ca 19879 elf32_arm_begin_write_processing (abfd, link_info);
c3c76620 19880}
7f266840
DJ		 19881
19882static bfd_boolean
906e58ca 19883elf32_arm_symbian_modify_segment_map (bfd *abfd,
b294bdf8 19884 struct bfd_link_info *info)
7f266840
DJ		 19885{
19886 struct elf_segment_map *m;
19887 asection *dynsec;
19888
7f266840
DJ		 19889 /* BPABI shared libraries and executables should have a PT_DYNAMIC
19890 segment. However, because the .dynamic section is not marked
19891 with SEC_LOAD, the generic ELF code will not create such a
19892 segment. */
19893 dynsec = bfd_get_section_by_name (abfd, ".dynamic");
19894 if (dynsec)
19895 {
12bd6957 19896 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
8ded5a0f
AM		 19897 if (m->p_type == PT_DYNAMIC)
19898 break;
19899
19900 if (m == NULL)
19901 {
19902 m = _bfd_elf_make_dynamic_segment (abfd, dynsec);
12bd6957
AM		 19903 m->next = elf_seg_map (abfd);
19904 elf_seg_map (abfd) = m;
8ded5a0f 19905 }
7f266840
DJ		 19906 }
19907
b294bdf8
MM		 19908 /* Also call the generic arm routine. */
19909 return elf32_arm_modify_segment_map (abfd, info);
7f266840
DJ		 19910}
19911
95720a86
DJ		 19912/* Return address for Ith PLT stub in section PLT, for relocation REL
19913 or (bfd_vma) -1 if it should not be included. */
19914
19915static bfd_vma
19916elf32_arm_symbian_plt_sym_val (bfd_vma i, const asection *plt,
19917 const arelent *rel ATTRIBUTE_UNUSED)
19918{
19919 return plt->vma + 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry) * i;
19920}
19921
8029a119 19922#undef elf32_bed
7f266840
DJ		 19923#define elf32_bed elf32_arm_symbian_bed
19924
19925/* The dynamic sections are not allocated on SymbianOS; the postlinker
19926 will process them and then discard them. */
906e58ca 19927#undef ELF_DYNAMIC_SEC_FLAGS
7f266840
DJ		 19928#define ELF_DYNAMIC_SEC_FLAGS \
19929 (SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED)
19930
9eaff861 19931#undef elf_backend_emit_relocs
c3c76620 19932
906e58ca
NC		 19933#undef bfd_elf32_bfd_link_hash_table_create
19934#define bfd_elf32_bfd_link_hash_table_create elf32_arm_symbian_link_hash_table_create
19935#undef elf_backend_special_sections
19936#define elf_backend_special_sections elf32_arm_symbian_special_sections
19937#undef elf_backend_begin_write_processing
19938#define elf_backend_begin_write_processing elf32_arm_symbian_begin_write_processing
19939#undef elf_backend_final_write_processing
19940#define elf_backend_final_write_processing elf32_arm_final_write_processing
19941
19942#undef elf_backend_modify_segment_map
7f266840
DJ		 19943#define elf_backend_modify_segment_map elf32_arm_symbian_modify_segment_map
19944
19945/* There is no .got section for BPABI objects, and hence no header. */
906e58ca 19946#undef elf_backend_got_header_size
7f266840
DJ		 19947#define elf_backend_got_header_size 0
19948
19949/* Similarly, there is no .got.plt section. */
906e58ca 19950#undef elf_backend_want_got_plt
7f266840
DJ		 19951#define elf_backend_want_got_plt 0
19952
906e58ca 19953#undef elf_backend_plt_sym_val
95720a86
DJ		 19954#define elf_backend_plt_sym_val elf32_arm_symbian_plt_sym_val
19955
906e58ca 19956#undef elf_backend_may_use_rel_p
00a97672 19957#define elf_backend_may_use_rel_p 1
906e58ca 19958#undef elf_backend_may_use_rela_p
00a97672 19959#define elf_backend_may_use_rela_p 0
906e58ca 19960#undef elf_backend_default_use_rela_p
00a97672 19961#define elf_backend_default_use_rela_p 0
906e58ca 19962#undef elf_backend_want_plt_sym
00a97672 19963#define elf_backend_want_plt_sym 0
64f52338
AM		 19964#undef elf_backend_dtrel_excludes_plt
19965#define elf_backend_dtrel_excludes_plt 0
906e58ca 19966#undef ELF_MAXPAGESIZE
00a97672 19967#define ELF_MAXPAGESIZE 0x8000
4e7fd91e 19968
7f266840 19969#include "elf32-target.h"
GDB Binutils - Deliverables
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