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Add support for stable secure gateway veneers addresses
[deliverable/binutils-gdb.git] / bfd / elf32-arm.c
CommitLineData
252b5132 1/* 32-bit ELF support for ARM
6f2750fe 2 Copyright (C) 1998-2016 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of BFD, the Binary File Descriptor library.
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
cd123cb7 8 the Free Software Foundation; either version 3 of the License, or
252b5132
RH		 9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
cd123cb7
NC		 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
252b5132 20
6e6718a3 21#include "sysdep.h"
2468f9c9
PB		 22#include <limits.h>
23
3db64b00 24#include "bfd.h"
6034aab8 25#include "bfd_stdint.h"
00a97672 26#include "libiberty.h"
7f266840
DJ		 27#include "libbfd.h"
28#include "elf-bfd.h"
b38cadfb 29#include "elf-nacl.h"
00a97672 30#include "elf-vxworks.h"
ee065d83 31#include "elf/arm.h"
7f266840 32
00a97672
RS		 33/* Return the relocation section associated with NAME. HTAB is the
34 bfd's elf32_arm_link_hash_entry. */
35#define RELOC_SECTION(HTAB, NAME) \
36 ((HTAB)->use_rel ? ".rel" NAME : ".rela" NAME)
37
38/* Return size of a relocation entry. HTAB is the bfd's
39 elf32_arm_link_hash_entry. */
40#define RELOC_SIZE(HTAB) \
41 ((HTAB)->use_rel \
42 ? sizeof (Elf32_External_Rel) \
43 : sizeof (Elf32_External_Rela))
44
45/* Return function to swap relocations in. HTAB is the bfd's
46 elf32_arm_link_hash_entry. */
47#define SWAP_RELOC_IN(HTAB) \
48 ((HTAB)->use_rel \
49 ? bfd_elf32_swap_reloc_in \
50 : bfd_elf32_swap_reloca_in)
51
52/* Return function to swap relocations out. HTAB is the bfd's
53 elf32_arm_link_hash_entry. */
54#define SWAP_RELOC_OUT(HTAB) \
55 ((HTAB)->use_rel \
56 ? bfd_elf32_swap_reloc_out \
57 : bfd_elf32_swap_reloca_out)
58
7f266840
DJ		 59#define elf_info_to_howto 0
60#define elf_info_to_howto_rel elf32_arm_info_to_howto
61
62#define ARM_ELF_ABI_VERSION 0
63#define ARM_ELF_OS_ABI_VERSION ELFOSABI_ARM
64
79f08007
YZ		 65/* The Adjusted Place, as defined by AAELF. */
66#define Pa(X) ((X) & 0xfffffffc)
67
3e6b1042
DJ		 68static bfd_boolean elf32_arm_write_section (bfd *output_bfd,
69 struct bfd_link_info *link_info,
70 asection *sec,
71 bfd_byte *contents);
72
7f266840
DJ		 73/* Note: code such as elf32_arm_reloc_type_lookup expect to use e.g.
74 R_ARM_PC24 as an index into this, and find the R_ARM_PC24 HOWTO
75 in that slot. */
76
c19d1205 77static reloc_howto_type elf32_arm_howto_table_1[] =
7f266840 78{
8029a119 79 /* No relocation. */
7f266840
DJ		 80 HOWTO (R_ARM_NONE, /* type */
81 0, /* rightshift */
6346d5ca 82 3, /* size (0 = byte, 1 = short, 2 = long) */
7f266840
DJ		 83 0, /* bitsize */
84 FALSE, /* pc_relative */
85 0, /* bitpos */
86 complain_overflow_dont,/* complain_on_overflow */
87 bfd_elf_generic_reloc, /* special_function */
88 "R_ARM_NONE", /* name */
89 FALSE, /* partial_inplace */
90 0, /* src_mask */
91 0, /* dst_mask */
92 FALSE), /* pcrel_offset */
93
94 HOWTO (R_ARM_PC24, /* type */
95 2, /* rightshift */
96 2, /* size (0 = byte, 1 = short, 2 = long) */
97 24, /* bitsize */
98 TRUE, /* pc_relative */
99 0, /* bitpos */
100 complain_overflow_signed,/* complain_on_overflow */
101 bfd_elf_generic_reloc, /* special_function */
102 "R_ARM_PC24", /* name */
103 FALSE, /* partial_inplace */
104 0x00ffffff, /* src_mask */
105 0x00ffffff, /* dst_mask */
106 TRUE), /* pcrel_offset */
107
108 /* 32 bit absolute */
109 HOWTO (R_ARM_ABS32, /* type */
110 0, /* rightshift */
111 2, /* size (0 = byte, 1 = short, 2 = long) */
112 32, /* bitsize */
113 FALSE, /* pc_relative */
114 0, /* bitpos */
115 complain_overflow_bitfield,/* complain_on_overflow */
116 bfd_elf_generic_reloc, /* special_function */
117 "R_ARM_ABS32", /* name */
118 FALSE, /* partial_inplace */
119 0xffffffff, /* src_mask */
120 0xffffffff, /* dst_mask */
121 FALSE), /* pcrel_offset */
122
123 /* standard 32bit pc-relative reloc */
124 HOWTO (R_ARM_REL32, /* type */
125 0, /* rightshift */
126 2, /* size (0 = byte, 1 = short, 2 = long) */
127 32, /* bitsize */
128 TRUE, /* pc_relative */
129 0, /* bitpos */
130 complain_overflow_bitfield,/* complain_on_overflow */
131 bfd_elf_generic_reloc, /* special_function */
132 "R_ARM_REL32", /* name */
133 FALSE, /* partial_inplace */
134 0xffffffff, /* src_mask */
135 0xffffffff, /* dst_mask */
136 TRUE), /* pcrel_offset */
137
c19d1205 138 /* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */
4962c51a 139 HOWTO (R_ARM_LDR_PC_G0, /* type */
7f266840
DJ		 140 0, /* rightshift */
141 0, /* size (0 = byte, 1 = short, 2 = long) */
4962c51a
MS		 142 32, /* bitsize */
143 TRUE, /* pc_relative */
7f266840 144 0, /* bitpos */
4962c51a 145 complain_overflow_dont,/* complain_on_overflow */
7f266840 146 bfd_elf_generic_reloc, /* special_function */
4962c51a 147 "R_ARM_LDR_PC_G0", /* name */
7f266840 148 FALSE, /* partial_inplace */
4962c51a
MS		 149 0xffffffff, /* src_mask */
150 0xffffffff, /* dst_mask */
151 TRUE), /* pcrel_offset */
7f266840
DJ		 152
153 /* 16 bit absolute */
154 HOWTO (R_ARM_ABS16, /* type */
155 0, /* rightshift */
156 1, /* size (0 = byte, 1 = short, 2 = long) */
157 16, /* bitsize */
158 FALSE, /* pc_relative */
159 0, /* bitpos */
160 complain_overflow_bitfield,/* complain_on_overflow */
161 bfd_elf_generic_reloc, /* special_function */
162 "R_ARM_ABS16", /* name */
163 FALSE, /* partial_inplace */
164 0x0000ffff, /* src_mask */
165 0x0000ffff, /* dst_mask */
166 FALSE), /* pcrel_offset */
167
168 /* 12 bit absolute */
169 HOWTO (R_ARM_ABS12, /* type */
170 0, /* rightshift */
171 2, /* size (0 = byte, 1 = short, 2 = long) */
172 12, /* bitsize */
173 FALSE, /* pc_relative */
174 0, /* bitpos */
175 complain_overflow_bitfield,/* complain_on_overflow */
176 bfd_elf_generic_reloc, /* special_function */
177 "R_ARM_ABS12", /* name */
178 FALSE, /* partial_inplace */
00a97672
RS		 179 0x00000fff, /* src_mask */
180 0x00000fff, /* dst_mask */
7f266840
DJ		 181 FALSE), /* pcrel_offset */
182
183 HOWTO (R_ARM_THM_ABS5, /* type */
184 6, /* rightshift */
185 1, /* size (0 = byte, 1 = short, 2 = long) */
186 5, /* bitsize */
187 FALSE, /* pc_relative */
188 0, /* bitpos */
189 complain_overflow_bitfield,/* complain_on_overflow */
190 bfd_elf_generic_reloc, /* special_function */
191 "R_ARM_THM_ABS5", /* name */
192 FALSE, /* partial_inplace */
193 0x000007e0, /* src_mask */
194 0x000007e0, /* dst_mask */
195 FALSE), /* pcrel_offset */
196
197 /* 8 bit absolute */
198 HOWTO (R_ARM_ABS8, /* type */
199 0, /* rightshift */
200 0, /* size (0 = byte, 1 = short, 2 = long) */
201 8, /* bitsize */
202 FALSE, /* pc_relative */
203 0, /* bitpos */
204 complain_overflow_bitfield,/* complain_on_overflow */
205 bfd_elf_generic_reloc, /* special_function */
206 "R_ARM_ABS8", /* name */
207 FALSE, /* partial_inplace */
208 0x000000ff, /* src_mask */
209 0x000000ff, /* dst_mask */
210 FALSE), /* pcrel_offset */
211
212 HOWTO (R_ARM_SBREL32, /* type */
213 0, /* rightshift */
214 2, /* size (0 = byte, 1 = short, 2 = long) */
215 32, /* bitsize */
216 FALSE, /* pc_relative */
217 0, /* bitpos */
218 complain_overflow_dont,/* complain_on_overflow */
219 bfd_elf_generic_reloc, /* special_function */
220 "R_ARM_SBREL32", /* name */
221 FALSE, /* partial_inplace */
222 0xffffffff, /* src_mask */
223 0xffffffff, /* dst_mask */
224 FALSE), /* pcrel_offset */
225
c19d1205 226 HOWTO (R_ARM_THM_CALL, /* type */
7f266840
DJ		 227 1, /* rightshift */
228 2, /* size (0 = byte, 1 = short, 2 = long) */
f6ebfac0 229 24, /* bitsize */
7f266840
DJ		 230 TRUE, /* pc_relative */
231 0, /* bitpos */
232 complain_overflow_signed,/* complain_on_overflow */
233 bfd_elf_generic_reloc, /* special_function */
c19d1205 234 "R_ARM_THM_CALL", /* name */
7f266840 235 FALSE, /* partial_inplace */
7f6ab9f8
AM		 236 0x07ff2fff, /* src_mask */
237 0x07ff2fff, /* dst_mask */
7f266840
DJ		 238 TRUE), /* pcrel_offset */
239
240 HOWTO (R_ARM_THM_PC8, /* type */
241 1, /* rightshift */
242 1, /* size (0 = byte, 1 = short, 2 = long) */
243 8, /* bitsize */
244 TRUE, /* pc_relative */
245 0, /* bitpos */
246 complain_overflow_signed,/* complain_on_overflow */
247 bfd_elf_generic_reloc, /* special_function */
248 "R_ARM_THM_PC8", /* name */
249 FALSE, /* partial_inplace */
250 0x000000ff, /* src_mask */
251 0x000000ff, /* dst_mask */
252 TRUE), /* pcrel_offset */
253
c19d1205 254 HOWTO (R_ARM_BREL_ADJ, /* type */
7f266840
DJ		 255 1, /* rightshift */
256 1, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 257 32, /* bitsize */
258 FALSE, /* pc_relative */
7f266840
DJ		 259 0, /* bitpos */
260 complain_overflow_signed,/* complain_on_overflow */
261 bfd_elf_generic_reloc, /* special_function */
c19d1205 262 "R_ARM_BREL_ADJ", /* name */
7f266840 263 FALSE, /* partial_inplace */
c19d1205
ZW		 264 0xffffffff, /* src_mask */
265 0xffffffff, /* dst_mask */
266 FALSE), /* pcrel_offset */
7f266840 267
0855e32b 268 HOWTO (R_ARM_TLS_DESC, /* type */
7f266840 269 0, /* rightshift */
0855e32b
NS		 270 2, /* size (0 = byte, 1 = short, 2 = long) */
271 32, /* bitsize */
7f266840
DJ		 272 FALSE, /* pc_relative */
273 0, /* bitpos */
0855e32b 274 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 275 bfd_elf_generic_reloc, /* special_function */
0855e32b 276 "R_ARM_TLS_DESC", /* name */
7f266840 277 FALSE, /* partial_inplace */
0855e32b
NS		 278 0xffffffff, /* src_mask */
279 0xffffffff, /* dst_mask */
7f266840
DJ		 280 FALSE), /* pcrel_offset */
281
282 HOWTO (R_ARM_THM_SWI8, /* type */
283 0, /* rightshift */
284 0, /* size (0 = byte, 1 = short, 2 = long) */
285 0, /* bitsize */
286 FALSE, /* pc_relative */
287 0, /* bitpos */
288 complain_overflow_signed,/* complain_on_overflow */
289 bfd_elf_generic_reloc, /* special_function */
290 "R_ARM_SWI8", /* name */
291 FALSE, /* partial_inplace */
292 0x00000000, /* src_mask */
293 0x00000000, /* dst_mask */
294 FALSE), /* pcrel_offset */
295
296 /* BLX instruction for the ARM. */
297 HOWTO (R_ARM_XPC25, /* type */
298 2, /* rightshift */
299 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 300 24, /* bitsize */
7f266840
DJ		 301 TRUE, /* pc_relative */
302 0, /* bitpos */
303 complain_overflow_signed,/* complain_on_overflow */
304 bfd_elf_generic_reloc, /* special_function */
305 "R_ARM_XPC25", /* name */
306 FALSE, /* partial_inplace */
307 0x00ffffff, /* src_mask */
308 0x00ffffff, /* dst_mask */
309 TRUE), /* pcrel_offset */
310
311 /* BLX instruction for the Thumb. */
312 HOWTO (R_ARM_THM_XPC22, /* type */
313 2, /* rightshift */
314 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 315 24, /* bitsize */
7f266840
DJ		 316 TRUE, /* pc_relative */
317 0, /* bitpos */
318 complain_overflow_signed,/* complain_on_overflow */
319 bfd_elf_generic_reloc, /* special_function */
320 "R_ARM_THM_XPC22", /* name */
321 FALSE, /* partial_inplace */
7f6ab9f8
AM		 322 0x07ff2fff, /* src_mask */
323 0x07ff2fff, /* dst_mask */
7f266840
DJ		 324 TRUE), /* pcrel_offset */
325
ba93b8ac 326 /* Dynamic TLS relocations. */
7f266840 327
ba93b8ac 328 HOWTO (R_ARM_TLS_DTPMOD32, /* type */
99059e56
RM		 329 0, /* rightshift */
330 2, /* size (0 = byte, 1 = short, 2 = long) */
331 32, /* bitsize */
332 FALSE, /* pc_relative */
333 0, /* bitpos */
334 complain_overflow_bitfield,/* complain_on_overflow */
335 bfd_elf_generic_reloc, /* special_function */
336 "R_ARM_TLS_DTPMOD32", /* name */
337 TRUE, /* partial_inplace */
338 0xffffffff, /* src_mask */
339 0xffffffff, /* dst_mask */
340 FALSE), /* pcrel_offset */
7f266840 341
ba93b8ac 342 HOWTO (R_ARM_TLS_DTPOFF32, /* type */
99059e56
RM		 343 0, /* rightshift */
344 2, /* size (0 = byte, 1 = short, 2 = long) */
345 32, /* bitsize */
346 FALSE, /* pc_relative */
347 0, /* bitpos */
348 complain_overflow_bitfield,/* complain_on_overflow */
349 bfd_elf_generic_reloc, /* special_function */
350 "R_ARM_TLS_DTPOFF32", /* name */
351 TRUE, /* partial_inplace */
352 0xffffffff, /* src_mask */
353 0xffffffff, /* dst_mask */
354 FALSE), /* pcrel_offset */
7f266840 355
ba93b8ac 356 HOWTO (R_ARM_TLS_TPOFF32, /* type */
99059e56
RM		 357 0, /* rightshift */
358 2, /* size (0 = byte, 1 = short, 2 = long) */
359 32, /* bitsize */
360 FALSE, /* pc_relative */
361 0, /* bitpos */
362 complain_overflow_bitfield,/* complain_on_overflow */
363 bfd_elf_generic_reloc, /* special_function */
364 "R_ARM_TLS_TPOFF32", /* name */
365 TRUE, /* partial_inplace */
366 0xffffffff, /* src_mask */
367 0xffffffff, /* dst_mask */
368 FALSE), /* pcrel_offset */
7f266840
DJ		 369
370 /* Relocs used in ARM Linux */
371
372 HOWTO (R_ARM_COPY, /* type */
99059e56
RM		 373 0, /* rightshift */
374 2, /* size (0 = byte, 1 = short, 2 = long) */
375 32, /* bitsize */
376 FALSE, /* pc_relative */
377 0, /* bitpos */
378 complain_overflow_bitfield,/* complain_on_overflow */
379 bfd_elf_generic_reloc, /* special_function */
380 "R_ARM_COPY", /* name */
381 TRUE, /* partial_inplace */
382 0xffffffff, /* src_mask */
383 0xffffffff, /* dst_mask */
384 FALSE), /* pcrel_offset */
7f266840
DJ		 385
386 HOWTO (R_ARM_GLOB_DAT, /* type */
99059e56
RM		 387 0, /* rightshift */
388 2, /* size (0 = byte, 1 = short, 2 = long) */
389 32, /* bitsize */
390 FALSE, /* pc_relative */
391 0, /* bitpos */
392 complain_overflow_bitfield,/* complain_on_overflow */
393 bfd_elf_generic_reloc, /* special_function */
394 "R_ARM_GLOB_DAT", /* name */
395 TRUE, /* partial_inplace */
396 0xffffffff, /* src_mask */
397 0xffffffff, /* dst_mask */
398 FALSE), /* pcrel_offset */
7f266840
DJ		 399
400 HOWTO (R_ARM_JUMP_SLOT, /* type */
99059e56
RM		 401 0, /* rightshift */
402 2, /* size (0 = byte, 1 = short, 2 = long) */
403 32, /* bitsize */
404 FALSE, /* pc_relative */
405 0, /* bitpos */
406 complain_overflow_bitfield,/* complain_on_overflow */
407 bfd_elf_generic_reloc, /* special_function */
408 "R_ARM_JUMP_SLOT", /* name */
409 TRUE, /* partial_inplace */
410 0xffffffff, /* src_mask */
411 0xffffffff, /* dst_mask */
412 FALSE), /* pcrel_offset */
7f266840
DJ		 413
414 HOWTO (R_ARM_RELATIVE, /* type */
99059e56
RM		 415 0, /* rightshift */
416 2, /* size (0 = byte, 1 = short, 2 = long) */
417 32, /* bitsize */
418 FALSE, /* pc_relative */
419 0, /* bitpos */
420 complain_overflow_bitfield,/* complain_on_overflow */
421 bfd_elf_generic_reloc, /* special_function */
422 "R_ARM_RELATIVE", /* name */
423 TRUE, /* partial_inplace */
424 0xffffffff, /* src_mask */
425 0xffffffff, /* dst_mask */
426 FALSE), /* pcrel_offset */
7f266840 427
c19d1205 428 HOWTO (R_ARM_GOTOFF32, /* type */
99059e56
RM		 429 0, /* rightshift */
430 2, /* size (0 = byte, 1 = short, 2 = long) */
431 32, /* bitsize */
432 FALSE, /* pc_relative */
433 0, /* bitpos */
434 complain_overflow_bitfield,/* complain_on_overflow */
435 bfd_elf_generic_reloc, /* special_function */
436 "R_ARM_GOTOFF32", /* name */
437 TRUE, /* partial_inplace */
438 0xffffffff, /* src_mask */
439 0xffffffff, /* dst_mask */
440 FALSE), /* pcrel_offset */
7f266840
DJ		 441
442 HOWTO (R_ARM_GOTPC, /* type */
99059e56
RM		 443 0, /* rightshift */
444 2, /* size (0 = byte, 1 = short, 2 = long) */
445 32, /* bitsize */
446 TRUE, /* pc_relative */
447 0, /* bitpos */
448 complain_overflow_bitfield,/* complain_on_overflow */
449 bfd_elf_generic_reloc, /* special_function */
450 "R_ARM_GOTPC", /* name */
451 TRUE, /* partial_inplace */
452 0xffffffff, /* src_mask */
453 0xffffffff, /* dst_mask */
454 TRUE), /* pcrel_offset */
7f266840
DJ		 455
456 HOWTO (R_ARM_GOT32, /* type */
99059e56
RM		 457 0, /* rightshift */
458 2, /* size (0 = byte, 1 = short, 2 = long) */
459 32, /* bitsize */
460 FALSE, /* pc_relative */
461 0, /* bitpos */
462 complain_overflow_bitfield,/* complain_on_overflow */
463 bfd_elf_generic_reloc, /* special_function */
464 "R_ARM_GOT32", /* name */
465 TRUE, /* partial_inplace */
466 0xffffffff, /* src_mask */
467 0xffffffff, /* dst_mask */
468 FALSE), /* pcrel_offset */
7f266840
DJ		 469
470 HOWTO (R_ARM_PLT32, /* type */
99059e56
RM		 471 2, /* rightshift */
472 2, /* size (0 = byte, 1 = short, 2 = long) */
473 24, /* bitsize */
474 TRUE, /* pc_relative */
475 0, /* bitpos */
476 complain_overflow_bitfield,/* complain_on_overflow */
477 bfd_elf_generic_reloc, /* special_function */
478 "R_ARM_PLT32", /* name */
479 FALSE, /* partial_inplace */
480 0x00ffffff, /* src_mask */
481 0x00ffffff, /* dst_mask */
482 TRUE), /* pcrel_offset */
7f266840
DJ		 483
484 HOWTO (R_ARM_CALL, /* type */
485 2, /* rightshift */
486 2, /* size (0 = byte, 1 = short, 2 = long) */
487 24, /* bitsize */
488 TRUE, /* pc_relative */
489 0, /* bitpos */
490 complain_overflow_signed,/* complain_on_overflow */
491 bfd_elf_generic_reloc, /* special_function */
492 "R_ARM_CALL", /* name */
493 FALSE, /* partial_inplace */
494 0x00ffffff, /* src_mask */
495 0x00ffffff, /* dst_mask */
496 TRUE), /* pcrel_offset */
497
498 HOWTO (R_ARM_JUMP24, /* type */
499 2, /* rightshift */
500 2, /* size (0 = byte, 1 = short, 2 = long) */
501 24, /* bitsize */
502 TRUE, /* pc_relative */
503 0, /* bitpos */
504 complain_overflow_signed,/* complain_on_overflow */
505 bfd_elf_generic_reloc, /* special_function */
506 "R_ARM_JUMP24", /* name */
507 FALSE, /* partial_inplace */
508 0x00ffffff, /* src_mask */
509 0x00ffffff, /* dst_mask */
510 TRUE), /* pcrel_offset */
511
c19d1205
ZW		 512 HOWTO (R_ARM_THM_JUMP24, /* type */
513 1, /* rightshift */
514 2, /* size (0 = byte, 1 = short, 2 = long) */
515 24, /* bitsize */
516 TRUE, /* pc_relative */
7f266840 517 0, /* bitpos */
c19d1205 518 complain_overflow_signed,/* complain_on_overflow */
7f266840 519 bfd_elf_generic_reloc, /* special_function */
c19d1205 520 "R_ARM_THM_JUMP24", /* name */
7f266840 521 FALSE, /* partial_inplace */
c19d1205
ZW		 522 0x07ff2fff, /* src_mask */
523 0x07ff2fff, /* dst_mask */
524 TRUE), /* pcrel_offset */
7f266840 525
c19d1205 526 HOWTO (R_ARM_BASE_ABS, /* type */
7f266840 527 0, /* rightshift */
c19d1205
ZW		 528 2, /* size (0 = byte, 1 = short, 2 = long) */
529 32, /* bitsize */
7f266840
DJ		 530 FALSE, /* pc_relative */
531 0, /* bitpos */
532 complain_overflow_dont,/* complain_on_overflow */
533 bfd_elf_generic_reloc, /* special_function */
c19d1205 534 "R_ARM_BASE_ABS", /* name */
7f266840 535 FALSE, /* partial_inplace */
c19d1205
ZW		 536 0xffffffff, /* src_mask */
537 0xffffffff, /* dst_mask */
7f266840
DJ		 538 FALSE), /* pcrel_offset */
539
540 HOWTO (R_ARM_ALU_PCREL7_0, /* type */
541 0, /* rightshift */
542 2, /* size (0 = byte, 1 = short, 2 = long) */
543 12, /* bitsize */
544 TRUE, /* pc_relative */
545 0, /* bitpos */
546 complain_overflow_dont,/* complain_on_overflow */
547 bfd_elf_generic_reloc, /* special_function */
548 "R_ARM_ALU_PCREL_7_0", /* name */
549 FALSE, /* partial_inplace */
550 0x00000fff, /* src_mask */
551 0x00000fff, /* dst_mask */
552 TRUE), /* pcrel_offset */
553
554 HOWTO (R_ARM_ALU_PCREL15_8, /* type */
555 0, /* rightshift */
556 2, /* size (0 = byte, 1 = short, 2 = long) */
557 12, /* bitsize */
558 TRUE, /* pc_relative */
559 8, /* bitpos */
560 complain_overflow_dont,/* complain_on_overflow */
561 bfd_elf_generic_reloc, /* special_function */
562 "R_ARM_ALU_PCREL_15_8",/* name */
563 FALSE, /* partial_inplace */
564 0x00000fff, /* src_mask */
565 0x00000fff, /* dst_mask */
566 TRUE), /* pcrel_offset */
567
568 HOWTO (R_ARM_ALU_PCREL23_15, /* type */
569 0, /* rightshift */
570 2, /* size (0 = byte, 1 = short, 2 = long) */
571 12, /* bitsize */
572 TRUE, /* pc_relative */
573 16, /* bitpos */
574 complain_overflow_dont,/* complain_on_overflow */
575 bfd_elf_generic_reloc, /* special_function */
576 "R_ARM_ALU_PCREL_23_15",/* name */
577 FALSE, /* partial_inplace */
578 0x00000fff, /* src_mask */
579 0x00000fff, /* dst_mask */
580 TRUE), /* pcrel_offset */
581
582 HOWTO (R_ARM_LDR_SBREL_11_0, /* type */
583 0, /* rightshift */
584 2, /* size (0 = byte, 1 = short, 2 = long) */
585 12, /* bitsize */
586 FALSE, /* pc_relative */
587 0, /* bitpos */
588 complain_overflow_dont,/* complain_on_overflow */
589 bfd_elf_generic_reloc, /* special_function */
590 "R_ARM_LDR_SBREL_11_0",/* name */
591 FALSE, /* partial_inplace */
592 0x00000fff, /* src_mask */
593 0x00000fff, /* dst_mask */
594 FALSE), /* pcrel_offset */
595
596 HOWTO (R_ARM_ALU_SBREL_19_12, /* type */
597 0, /* rightshift */
598 2, /* size (0 = byte, 1 = short, 2 = long) */
599 8, /* bitsize */
600 FALSE, /* pc_relative */
601 12, /* bitpos */
602 complain_overflow_dont,/* complain_on_overflow */
603 bfd_elf_generic_reloc, /* special_function */
604 "R_ARM_ALU_SBREL_19_12",/* name */
605 FALSE, /* partial_inplace */
606 0x000ff000, /* src_mask */
607 0x000ff000, /* dst_mask */
608 FALSE), /* pcrel_offset */
609
610 HOWTO (R_ARM_ALU_SBREL_27_20, /* type */
611 0, /* rightshift */
612 2, /* size (0 = byte, 1 = short, 2 = long) */
613 8, /* bitsize */
614 FALSE, /* pc_relative */
615 20, /* bitpos */
616 complain_overflow_dont,/* complain_on_overflow */
617 bfd_elf_generic_reloc, /* special_function */
618 "R_ARM_ALU_SBREL_27_20",/* name */
619 FALSE, /* partial_inplace */
620 0x0ff00000, /* src_mask */
621 0x0ff00000, /* dst_mask */
622 FALSE), /* pcrel_offset */
623
624 HOWTO (R_ARM_TARGET1, /* type */
625 0, /* rightshift */
626 2, /* size (0 = byte, 1 = short, 2 = long) */
627 32, /* bitsize */
628 FALSE, /* pc_relative */
629 0, /* bitpos */
630 complain_overflow_dont,/* complain_on_overflow */
631 bfd_elf_generic_reloc, /* special_function */
632 "R_ARM_TARGET1", /* name */
633 FALSE, /* partial_inplace */
634 0xffffffff, /* src_mask */
635 0xffffffff, /* dst_mask */
636 FALSE), /* pcrel_offset */
637
638 HOWTO (R_ARM_ROSEGREL32, /* type */
639 0, /* rightshift */
640 2, /* size (0 = byte, 1 = short, 2 = long) */
641 32, /* bitsize */
642 FALSE, /* pc_relative */
643 0, /* bitpos */
644 complain_overflow_dont,/* complain_on_overflow */
645 bfd_elf_generic_reloc, /* special_function */
646 "R_ARM_ROSEGREL32", /* name */
647 FALSE, /* partial_inplace */
648 0xffffffff, /* src_mask */
649 0xffffffff, /* dst_mask */
650 FALSE), /* pcrel_offset */
651
652 HOWTO (R_ARM_V4BX, /* type */
653 0, /* rightshift */
654 2, /* size (0 = byte, 1 = short, 2 = long) */
655 32, /* bitsize */
656 FALSE, /* pc_relative */
657 0, /* bitpos */
658 complain_overflow_dont,/* complain_on_overflow */
659 bfd_elf_generic_reloc, /* special_function */
660 "R_ARM_V4BX", /* name */
661 FALSE, /* partial_inplace */
662 0xffffffff, /* src_mask */
663 0xffffffff, /* dst_mask */
664 FALSE), /* pcrel_offset */
665
666 HOWTO (R_ARM_TARGET2, /* type */
667 0, /* rightshift */
668 2, /* size (0 = byte, 1 = short, 2 = long) */
669 32, /* bitsize */
670 FALSE, /* pc_relative */
671 0, /* bitpos */
672 complain_overflow_signed,/* complain_on_overflow */
673 bfd_elf_generic_reloc, /* special_function */
674 "R_ARM_TARGET2", /* name */
675 FALSE, /* partial_inplace */
676 0xffffffff, /* src_mask */
677 0xffffffff, /* dst_mask */
678 TRUE), /* pcrel_offset */
679
680 HOWTO (R_ARM_PREL31, /* type */
681 0, /* rightshift */
682 2, /* size (0 = byte, 1 = short, 2 = long) */
683 31, /* bitsize */
684 TRUE, /* pc_relative */
685 0, /* bitpos */
686 complain_overflow_signed,/* complain_on_overflow */
687 bfd_elf_generic_reloc, /* special_function */
688 "R_ARM_PREL31", /* name */
689 FALSE, /* partial_inplace */
690 0x7fffffff, /* src_mask */
691 0x7fffffff, /* dst_mask */
692 TRUE), /* pcrel_offset */
c19d1205
ZW		 693
694 HOWTO (R_ARM_MOVW_ABS_NC, /* type */
695 0, /* rightshift */
696 2, /* size (0 = byte, 1 = short, 2 = long) */
697 16, /* bitsize */
698 FALSE, /* pc_relative */
699 0, /* bitpos */
700 complain_overflow_dont,/* complain_on_overflow */
701 bfd_elf_generic_reloc, /* special_function */
702 "R_ARM_MOVW_ABS_NC", /* name */
703 FALSE, /* partial_inplace */
39623e12
PB		 704 0x000f0fff, /* src_mask */
705 0x000f0fff, /* dst_mask */
c19d1205
ZW		 706 FALSE), /* pcrel_offset */
707
708 HOWTO (R_ARM_MOVT_ABS, /* type */
709 0, /* rightshift */
710 2, /* size (0 = byte, 1 = short, 2 = long) */
711 16, /* bitsize */
712 FALSE, /* pc_relative */
713 0, /* bitpos */
714 complain_overflow_bitfield,/* complain_on_overflow */
715 bfd_elf_generic_reloc, /* special_function */
716 "R_ARM_MOVT_ABS", /* name */
717 FALSE, /* partial_inplace */
39623e12
PB		 718 0x000f0fff, /* src_mask */
719 0x000f0fff, /* dst_mask */
c19d1205
ZW		 720 FALSE), /* pcrel_offset */
721
722 HOWTO (R_ARM_MOVW_PREL_NC, /* type */
723 0, /* rightshift */
724 2, /* size (0 = byte, 1 = short, 2 = long) */
725 16, /* bitsize */
726 TRUE, /* pc_relative */
727 0, /* bitpos */
728 complain_overflow_dont,/* complain_on_overflow */
729 bfd_elf_generic_reloc, /* special_function */
730 "R_ARM_MOVW_PREL_NC", /* name */
731 FALSE, /* partial_inplace */
39623e12
PB		 732 0x000f0fff, /* src_mask */
733 0x000f0fff, /* dst_mask */
c19d1205
ZW		 734 TRUE), /* pcrel_offset */
735
736 HOWTO (R_ARM_MOVT_PREL, /* type */
737 0, /* rightshift */
738 2, /* size (0 = byte, 1 = short, 2 = long) */
739 16, /* bitsize */
740 TRUE, /* pc_relative */
741 0, /* bitpos */
742 complain_overflow_bitfield,/* complain_on_overflow */
743 bfd_elf_generic_reloc, /* special_function */
744 "R_ARM_MOVT_PREL", /* name */
745 FALSE, /* partial_inplace */
39623e12
PB		 746 0x000f0fff, /* src_mask */
747 0x000f0fff, /* dst_mask */
c19d1205
ZW		 748 TRUE), /* pcrel_offset */
749
750 HOWTO (R_ARM_THM_MOVW_ABS_NC, /* type */
751 0, /* rightshift */
752 2, /* size (0 = byte, 1 = short, 2 = long) */
753 16, /* bitsize */
754 FALSE, /* pc_relative */
755 0, /* bitpos */
756 complain_overflow_dont,/* complain_on_overflow */
757 bfd_elf_generic_reloc, /* special_function */
758 "R_ARM_THM_MOVW_ABS_NC",/* name */
759 FALSE, /* partial_inplace */
760 0x040f70ff, /* src_mask */
761 0x040f70ff, /* dst_mask */
762 FALSE), /* pcrel_offset */
763
764 HOWTO (R_ARM_THM_MOVT_ABS, /* type */
765 0, /* rightshift */
766 2, /* size (0 = byte, 1 = short, 2 = long) */
767 16, /* bitsize */
768 FALSE, /* pc_relative */
769 0, /* bitpos */
770 complain_overflow_bitfield,/* complain_on_overflow */
771 bfd_elf_generic_reloc, /* special_function */
772 "R_ARM_THM_MOVT_ABS", /* name */
773 FALSE, /* partial_inplace */
774 0x040f70ff, /* src_mask */
775 0x040f70ff, /* dst_mask */
776 FALSE), /* pcrel_offset */
777
778 HOWTO (R_ARM_THM_MOVW_PREL_NC,/* type */
779 0, /* rightshift */
780 2, /* size (0 = byte, 1 = short, 2 = long) */
781 16, /* bitsize */
782 TRUE, /* pc_relative */
783 0, /* bitpos */
784 complain_overflow_dont,/* complain_on_overflow */
785 bfd_elf_generic_reloc, /* special_function */
786 "R_ARM_THM_MOVW_PREL_NC",/* name */
787 FALSE, /* partial_inplace */
788 0x040f70ff, /* src_mask */
789 0x040f70ff, /* dst_mask */
790 TRUE), /* pcrel_offset */
791
792 HOWTO (R_ARM_THM_MOVT_PREL, /* type */
793 0, /* rightshift */
794 2, /* size (0 = byte, 1 = short, 2 = long) */
795 16, /* bitsize */
796 TRUE, /* pc_relative */
797 0, /* bitpos */
798 complain_overflow_bitfield,/* complain_on_overflow */
799 bfd_elf_generic_reloc, /* special_function */
800 "R_ARM_THM_MOVT_PREL", /* name */
801 FALSE, /* partial_inplace */
802 0x040f70ff, /* src_mask */
803 0x040f70ff, /* dst_mask */
804 TRUE), /* pcrel_offset */
805
806 HOWTO (R_ARM_THM_JUMP19, /* type */
807 1, /* rightshift */
808 2, /* size (0 = byte, 1 = short, 2 = long) */
809 19, /* bitsize */
810 TRUE, /* pc_relative */
811 0, /* bitpos */
812 complain_overflow_signed,/* complain_on_overflow */
813 bfd_elf_generic_reloc, /* special_function */
814 "R_ARM_THM_JUMP19", /* name */
815 FALSE, /* partial_inplace */
816 0x043f2fff, /* src_mask */
817 0x043f2fff, /* dst_mask */
818 TRUE), /* pcrel_offset */
819
820 HOWTO (R_ARM_THM_JUMP6, /* type */
821 1, /* rightshift */
822 1, /* size (0 = byte, 1 = short, 2 = long) */
823 6, /* bitsize */
824 TRUE, /* pc_relative */
825 0, /* bitpos */
826 complain_overflow_unsigned,/* complain_on_overflow */
827 bfd_elf_generic_reloc, /* special_function */
828 "R_ARM_THM_JUMP6", /* name */
829 FALSE, /* partial_inplace */
830 0x02f8, /* src_mask */
831 0x02f8, /* dst_mask */
832 TRUE), /* pcrel_offset */
833
834 /* These are declared as 13-bit signed relocations because we can
835 address -4095 .. 4095(base) by altering ADDW to SUBW or vice
836 versa. */
837 HOWTO (R_ARM_THM_ALU_PREL_11_0,/* type */
838 0, /* rightshift */
839 2, /* size (0 = byte, 1 = short, 2 = long) */
840 13, /* bitsize */
841 TRUE, /* pc_relative */
842 0, /* bitpos */
2cab6cc3 843 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 844 bfd_elf_generic_reloc, /* special_function */
845 "R_ARM_THM_ALU_PREL_11_0",/* name */
846 FALSE, /* partial_inplace */
2cab6cc3
MS		 847 0xffffffff, /* src_mask */
848 0xffffffff, /* dst_mask */
c19d1205
ZW		 849 TRUE), /* pcrel_offset */
850
851 HOWTO (R_ARM_THM_PC12, /* type */
852 0, /* rightshift */
853 2, /* size (0 = byte, 1 = short, 2 = long) */
854 13, /* bitsize */
855 TRUE, /* pc_relative */
856 0, /* bitpos */
2cab6cc3 857 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 858 bfd_elf_generic_reloc, /* special_function */
859 "R_ARM_THM_PC12", /* name */
860 FALSE, /* partial_inplace */
2cab6cc3
MS		 861 0xffffffff, /* src_mask */
862 0xffffffff, /* dst_mask */
c19d1205
ZW		 863 TRUE), /* pcrel_offset */
864
865 HOWTO (R_ARM_ABS32_NOI, /* type */
866 0, /* rightshift */
867 2, /* size (0 = byte, 1 = short, 2 = long) */
868 32, /* bitsize */
869 FALSE, /* pc_relative */
870 0, /* bitpos */
871 complain_overflow_dont,/* complain_on_overflow */
872 bfd_elf_generic_reloc, /* special_function */
873 "R_ARM_ABS32_NOI", /* name */
874 FALSE, /* partial_inplace */
875 0xffffffff, /* src_mask */
876 0xffffffff, /* dst_mask */
877 FALSE), /* pcrel_offset */
878
879 HOWTO (R_ARM_REL32_NOI, /* type */
880 0, /* rightshift */
881 2, /* size (0 = byte, 1 = short, 2 = long) */
882 32, /* bitsize */
883 TRUE, /* pc_relative */
884 0, /* bitpos */
885 complain_overflow_dont,/* complain_on_overflow */
886 bfd_elf_generic_reloc, /* special_function */
887 "R_ARM_REL32_NOI", /* name */
888 FALSE, /* partial_inplace */
889 0xffffffff, /* src_mask */
890 0xffffffff, /* dst_mask */
891 FALSE), /* pcrel_offset */
7f266840 892
4962c51a
MS		 893 /* Group relocations. */
894
895 HOWTO (R_ARM_ALU_PC_G0_NC, /* type */
896 0, /* rightshift */
897 2, /* size (0 = byte, 1 = short, 2 = long) */
898 32, /* bitsize */
899 TRUE, /* pc_relative */
900 0, /* bitpos */
901 complain_overflow_dont,/* complain_on_overflow */
902 bfd_elf_generic_reloc, /* special_function */
903 "R_ARM_ALU_PC_G0_NC", /* name */
904 FALSE, /* partial_inplace */
905 0xffffffff, /* src_mask */
906 0xffffffff, /* dst_mask */
907 TRUE), /* pcrel_offset */
908
909 HOWTO (R_ARM_ALU_PC_G0, /* type */
910 0, /* rightshift */
911 2, /* size (0 = byte, 1 = short, 2 = long) */
912 32, /* bitsize */
913 TRUE, /* pc_relative */
914 0, /* bitpos */
915 complain_overflow_dont,/* complain_on_overflow */
916 bfd_elf_generic_reloc, /* special_function */
917 "R_ARM_ALU_PC_G0", /* name */
918 FALSE, /* partial_inplace */
919 0xffffffff, /* src_mask */
920 0xffffffff, /* dst_mask */
921 TRUE), /* pcrel_offset */
922
923 HOWTO (R_ARM_ALU_PC_G1_NC, /* type */
924 0, /* rightshift */
925 2, /* size (0 = byte, 1 = short, 2 = long) */
926 32, /* bitsize */
927 TRUE, /* pc_relative */
928 0, /* bitpos */
929 complain_overflow_dont,/* complain_on_overflow */
930 bfd_elf_generic_reloc, /* special_function */
931 "R_ARM_ALU_PC_G1_NC", /* name */
932 FALSE, /* partial_inplace */
933 0xffffffff, /* src_mask */
934 0xffffffff, /* dst_mask */
935 TRUE), /* pcrel_offset */
936
937 HOWTO (R_ARM_ALU_PC_G1, /* type */
938 0, /* rightshift */
939 2, /* size (0 = byte, 1 = short, 2 = long) */
940 32, /* bitsize */
941 TRUE, /* pc_relative */
942 0, /* bitpos */
943 complain_overflow_dont,/* complain_on_overflow */
944 bfd_elf_generic_reloc, /* special_function */
945 "R_ARM_ALU_PC_G1", /* name */
946 FALSE, /* partial_inplace */
947 0xffffffff, /* src_mask */
948 0xffffffff, /* dst_mask */
949 TRUE), /* pcrel_offset */
950
951 HOWTO (R_ARM_ALU_PC_G2, /* type */
952 0, /* rightshift */
953 2, /* size (0 = byte, 1 = short, 2 = long) */
954 32, /* bitsize */
955 TRUE, /* pc_relative */
956 0, /* bitpos */
957 complain_overflow_dont,/* complain_on_overflow */
958 bfd_elf_generic_reloc, /* special_function */
959 "R_ARM_ALU_PC_G2", /* name */
960 FALSE, /* partial_inplace */
961 0xffffffff, /* src_mask */
962 0xffffffff, /* dst_mask */
963 TRUE), /* pcrel_offset */
964
965 HOWTO (R_ARM_LDR_PC_G1, /* type */
966 0, /* rightshift */
967 2, /* size (0 = byte, 1 = short, 2 = long) */
968 32, /* bitsize */
969 TRUE, /* pc_relative */
970 0, /* bitpos */
971 complain_overflow_dont,/* complain_on_overflow */
972 bfd_elf_generic_reloc, /* special_function */
973 "R_ARM_LDR_PC_G1", /* name */
974 FALSE, /* partial_inplace */
975 0xffffffff, /* src_mask */
976 0xffffffff, /* dst_mask */
977 TRUE), /* pcrel_offset */
978
979 HOWTO (R_ARM_LDR_PC_G2, /* type */
980 0, /* rightshift */
981 2, /* size (0 = byte, 1 = short, 2 = long) */
982 32, /* bitsize */
983 TRUE, /* pc_relative */
984 0, /* bitpos */
985 complain_overflow_dont,/* complain_on_overflow */
986 bfd_elf_generic_reloc, /* special_function */
987 "R_ARM_LDR_PC_G2", /* name */
988 FALSE, /* partial_inplace */
989 0xffffffff, /* src_mask */
990 0xffffffff, /* dst_mask */
991 TRUE), /* pcrel_offset */
992
993 HOWTO (R_ARM_LDRS_PC_G0, /* type */
994 0, /* rightshift */
995 2, /* size (0 = byte, 1 = short, 2 = long) */
996 32, /* bitsize */
997 TRUE, /* pc_relative */
998 0, /* bitpos */
999 complain_overflow_dont,/* complain_on_overflow */
1000 bfd_elf_generic_reloc, /* special_function */
1001 "R_ARM_LDRS_PC_G0", /* name */
1002 FALSE, /* partial_inplace */
1003 0xffffffff, /* src_mask */
1004 0xffffffff, /* dst_mask */
1005 TRUE), /* pcrel_offset */
1006
1007 HOWTO (R_ARM_LDRS_PC_G1, /* type */
1008 0, /* rightshift */
1009 2, /* size (0 = byte, 1 = short, 2 = long) */
1010 32, /* bitsize */
1011 TRUE, /* pc_relative */
1012 0, /* bitpos */
1013 complain_overflow_dont,/* complain_on_overflow */
1014 bfd_elf_generic_reloc, /* special_function */
1015 "R_ARM_LDRS_PC_G1", /* name */
1016 FALSE, /* partial_inplace */
1017 0xffffffff, /* src_mask */
1018 0xffffffff, /* dst_mask */
1019 TRUE), /* pcrel_offset */
1020
1021 HOWTO (R_ARM_LDRS_PC_G2, /* type */
1022 0, /* rightshift */
1023 2, /* size (0 = byte, 1 = short, 2 = long) */
1024 32, /* bitsize */
1025 TRUE, /* pc_relative */
1026 0, /* bitpos */
1027 complain_overflow_dont,/* complain_on_overflow */
1028 bfd_elf_generic_reloc, /* special_function */
1029 "R_ARM_LDRS_PC_G2", /* name */
1030 FALSE, /* partial_inplace */
1031 0xffffffff, /* src_mask */
1032 0xffffffff, /* dst_mask */
1033 TRUE), /* pcrel_offset */
1034
1035 HOWTO (R_ARM_LDC_PC_G0, /* type */
1036 0, /* rightshift */
1037 2, /* size (0 = byte, 1 = short, 2 = long) */
1038 32, /* bitsize */
1039 TRUE, /* pc_relative */
1040 0, /* bitpos */
1041 complain_overflow_dont,/* complain_on_overflow */
1042 bfd_elf_generic_reloc, /* special_function */
1043 "R_ARM_LDC_PC_G0", /* name */
1044 FALSE, /* partial_inplace */
1045 0xffffffff, /* src_mask */
1046 0xffffffff, /* dst_mask */
1047 TRUE), /* pcrel_offset */
1048
1049 HOWTO (R_ARM_LDC_PC_G1, /* type */
1050 0, /* rightshift */
1051 2, /* size (0 = byte, 1 = short, 2 = long) */
1052 32, /* bitsize */
1053 TRUE, /* pc_relative */
1054 0, /* bitpos */
1055 complain_overflow_dont,/* complain_on_overflow */
1056 bfd_elf_generic_reloc, /* special_function */
1057 "R_ARM_LDC_PC_G1", /* name */
1058 FALSE, /* partial_inplace */
1059 0xffffffff, /* src_mask */
1060 0xffffffff, /* dst_mask */
1061 TRUE), /* pcrel_offset */
1062
1063 HOWTO (R_ARM_LDC_PC_G2, /* type */
1064 0, /* rightshift */
1065 2, /* size (0 = byte, 1 = short, 2 = long) */
1066 32, /* bitsize */
1067 TRUE, /* pc_relative */
1068 0, /* bitpos */
1069 complain_overflow_dont,/* complain_on_overflow */
1070 bfd_elf_generic_reloc, /* special_function */
1071 "R_ARM_LDC_PC_G2", /* name */
1072 FALSE, /* partial_inplace */
1073 0xffffffff, /* src_mask */
1074 0xffffffff, /* dst_mask */
1075 TRUE), /* pcrel_offset */
1076
1077 HOWTO (R_ARM_ALU_SB_G0_NC, /* type */
1078 0, /* rightshift */
1079 2, /* size (0 = byte, 1 = short, 2 = long) */
1080 32, /* bitsize */
1081 TRUE, /* pc_relative */
1082 0, /* bitpos */
1083 complain_overflow_dont,/* complain_on_overflow */
1084 bfd_elf_generic_reloc, /* special_function */
1085 "R_ARM_ALU_SB_G0_NC", /* name */
1086 FALSE, /* partial_inplace */
1087 0xffffffff, /* src_mask */
1088 0xffffffff, /* dst_mask */
1089 TRUE), /* pcrel_offset */
1090
1091 HOWTO (R_ARM_ALU_SB_G0, /* type */
1092 0, /* rightshift */
1093 2, /* size (0 = byte, 1 = short, 2 = long) */
1094 32, /* bitsize */
1095 TRUE, /* pc_relative */
1096 0, /* bitpos */
1097 complain_overflow_dont,/* complain_on_overflow */
1098 bfd_elf_generic_reloc, /* special_function */
1099 "R_ARM_ALU_SB_G0", /* name */
1100 FALSE, /* partial_inplace */
1101 0xffffffff, /* src_mask */
1102 0xffffffff, /* dst_mask */
1103 TRUE), /* pcrel_offset */
1104
1105 HOWTO (R_ARM_ALU_SB_G1_NC, /* type */
1106 0, /* rightshift */
1107 2, /* size (0 = byte, 1 = short, 2 = long) */
1108 32, /* bitsize */
1109 TRUE, /* pc_relative */
1110 0, /* bitpos */
1111 complain_overflow_dont,/* complain_on_overflow */
1112 bfd_elf_generic_reloc, /* special_function */
1113 "R_ARM_ALU_SB_G1_NC", /* name */
1114 FALSE, /* partial_inplace */
1115 0xffffffff, /* src_mask */
1116 0xffffffff, /* dst_mask */
1117 TRUE), /* pcrel_offset */
1118
1119 HOWTO (R_ARM_ALU_SB_G1, /* type */
1120 0, /* rightshift */
1121 2, /* size (0 = byte, 1 = short, 2 = long) */
1122 32, /* bitsize */
1123 TRUE, /* pc_relative */
1124 0, /* bitpos */
1125 complain_overflow_dont,/* complain_on_overflow */
1126 bfd_elf_generic_reloc, /* special_function */
1127 "R_ARM_ALU_SB_G1", /* name */
1128 FALSE, /* partial_inplace */
1129 0xffffffff, /* src_mask */
1130 0xffffffff, /* dst_mask */
1131 TRUE), /* pcrel_offset */
1132
1133 HOWTO (R_ARM_ALU_SB_G2, /* type */
1134 0, /* rightshift */
1135 2, /* size (0 = byte, 1 = short, 2 = long) */
1136 32, /* bitsize */
1137 TRUE, /* pc_relative */
1138 0, /* bitpos */
1139 complain_overflow_dont,/* complain_on_overflow */
1140 bfd_elf_generic_reloc, /* special_function */
1141 "R_ARM_ALU_SB_G2", /* name */
1142 FALSE, /* partial_inplace */
1143 0xffffffff, /* src_mask */
1144 0xffffffff, /* dst_mask */
1145 TRUE), /* pcrel_offset */
1146
1147 HOWTO (R_ARM_LDR_SB_G0, /* type */
1148 0, /* rightshift */
1149 2, /* size (0 = byte, 1 = short, 2 = long) */
1150 32, /* bitsize */
1151 TRUE, /* pc_relative */
1152 0, /* bitpos */
1153 complain_overflow_dont,/* complain_on_overflow */
1154 bfd_elf_generic_reloc, /* special_function */
1155 "R_ARM_LDR_SB_G0", /* name */
1156 FALSE, /* partial_inplace */
1157 0xffffffff, /* src_mask */
1158 0xffffffff, /* dst_mask */
1159 TRUE), /* pcrel_offset */
1160
1161 HOWTO (R_ARM_LDR_SB_G1, /* type */
1162 0, /* rightshift */
1163 2, /* size (0 = byte, 1 = short, 2 = long) */
1164 32, /* bitsize */
1165 TRUE, /* pc_relative */
1166 0, /* bitpos */
1167 complain_overflow_dont,/* complain_on_overflow */
1168 bfd_elf_generic_reloc, /* special_function */
1169 "R_ARM_LDR_SB_G1", /* name */
1170 FALSE, /* partial_inplace */
1171 0xffffffff, /* src_mask */
1172 0xffffffff, /* dst_mask */
1173 TRUE), /* pcrel_offset */
1174
1175 HOWTO (R_ARM_LDR_SB_G2, /* type */
1176 0, /* rightshift */
1177 2, /* size (0 = byte, 1 = short, 2 = long) */
1178 32, /* bitsize */
1179 TRUE, /* pc_relative */
1180 0, /* bitpos */
1181 complain_overflow_dont,/* complain_on_overflow */
1182 bfd_elf_generic_reloc, /* special_function */
1183 "R_ARM_LDR_SB_G2", /* name */
1184 FALSE, /* partial_inplace */
1185 0xffffffff, /* src_mask */
1186 0xffffffff, /* dst_mask */
1187 TRUE), /* pcrel_offset */
1188
1189 HOWTO (R_ARM_LDRS_SB_G0, /* type */
1190 0, /* rightshift */
1191 2, /* size (0 = byte, 1 = short, 2 = long) */
1192 32, /* bitsize */
1193 TRUE, /* pc_relative */
1194 0, /* bitpos */
1195 complain_overflow_dont,/* complain_on_overflow */
1196 bfd_elf_generic_reloc, /* special_function */
1197 "R_ARM_LDRS_SB_G0", /* name */
1198 FALSE, /* partial_inplace */
1199 0xffffffff, /* src_mask */
1200 0xffffffff, /* dst_mask */
1201 TRUE), /* pcrel_offset */
1202
1203 HOWTO (R_ARM_LDRS_SB_G1, /* type */
1204 0, /* rightshift */
1205 2, /* size (0 = byte, 1 = short, 2 = long) */
1206 32, /* bitsize */
1207 TRUE, /* pc_relative */
1208 0, /* bitpos */
1209 complain_overflow_dont,/* complain_on_overflow */
1210 bfd_elf_generic_reloc, /* special_function */
1211 "R_ARM_LDRS_SB_G1", /* name */
1212 FALSE, /* partial_inplace */
1213 0xffffffff, /* src_mask */
1214 0xffffffff, /* dst_mask */
1215 TRUE), /* pcrel_offset */
1216
1217 HOWTO (R_ARM_LDRS_SB_G2, /* type */
1218 0, /* rightshift */
1219 2, /* size (0 = byte, 1 = short, 2 = long) */
1220 32, /* bitsize */
1221 TRUE, /* pc_relative */
1222 0, /* bitpos */
1223 complain_overflow_dont,/* complain_on_overflow */
1224 bfd_elf_generic_reloc, /* special_function */
1225 "R_ARM_LDRS_SB_G2", /* name */
1226 FALSE, /* partial_inplace */
1227 0xffffffff, /* src_mask */
1228 0xffffffff, /* dst_mask */
1229 TRUE), /* pcrel_offset */
1230
1231 HOWTO (R_ARM_LDC_SB_G0, /* type */
1232 0, /* rightshift */
1233 2, /* size (0 = byte, 1 = short, 2 = long) */
1234 32, /* bitsize */
1235 TRUE, /* pc_relative */
1236 0, /* bitpos */
1237 complain_overflow_dont,/* complain_on_overflow */
1238 bfd_elf_generic_reloc, /* special_function */
1239 "R_ARM_LDC_SB_G0", /* name */
1240 FALSE, /* partial_inplace */
1241 0xffffffff, /* src_mask */
1242 0xffffffff, /* dst_mask */
1243 TRUE), /* pcrel_offset */
1244
1245 HOWTO (R_ARM_LDC_SB_G1, /* type */
1246 0, /* rightshift */
1247 2, /* size (0 = byte, 1 = short, 2 = long) */
1248 32, /* bitsize */
1249 TRUE, /* pc_relative */
1250 0, /* bitpos */
1251 complain_overflow_dont,/* complain_on_overflow */
1252 bfd_elf_generic_reloc, /* special_function */
1253 "R_ARM_LDC_SB_G1", /* name */
1254 FALSE, /* partial_inplace */
1255 0xffffffff, /* src_mask */
1256 0xffffffff, /* dst_mask */
1257 TRUE), /* pcrel_offset */
1258
1259 HOWTO (R_ARM_LDC_SB_G2, /* type */
1260 0, /* rightshift */
1261 2, /* size (0 = byte, 1 = short, 2 = long) */
1262 32, /* bitsize */
1263 TRUE, /* pc_relative */
1264 0, /* bitpos */
1265 complain_overflow_dont,/* complain_on_overflow */
1266 bfd_elf_generic_reloc, /* special_function */
1267 "R_ARM_LDC_SB_G2", /* name */
1268 FALSE, /* partial_inplace */
1269 0xffffffff, /* src_mask */
1270 0xffffffff, /* dst_mask */
1271 TRUE), /* pcrel_offset */
1272
1273 /* End of group relocations. */
c19d1205 1274
c19d1205
ZW		 1275 HOWTO (R_ARM_MOVW_BREL_NC, /* type */
1276 0, /* rightshift */
1277 2, /* size (0 = byte, 1 = short, 2 = long) */
1278 16, /* bitsize */
1279 FALSE, /* pc_relative */
1280 0, /* bitpos */
1281 complain_overflow_dont,/* complain_on_overflow */
1282 bfd_elf_generic_reloc, /* special_function */
1283 "R_ARM_MOVW_BREL_NC", /* name */
1284 FALSE, /* partial_inplace */
1285 0x0000ffff, /* src_mask */
1286 0x0000ffff, /* dst_mask */
1287 FALSE), /* pcrel_offset */
1288
1289 HOWTO (R_ARM_MOVT_BREL, /* type */
1290 0, /* rightshift */
1291 2, /* size (0 = byte, 1 = short, 2 = long) */
1292 16, /* bitsize */
1293 FALSE, /* pc_relative */
1294 0, /* bitpos */
1295 complain_overflow_bitfield,/* complain_on_overflow */
1296 bfd_elf_generic_reloc, /* special_function */
1297 "R_ARM_MOVT_BREL", /* name */
1298 FALSE, /* partial_inplace */
1299 0x0000ffff, /* src_mask */
1300 0x0000ffff, /* dst_mask */
1301 FALSE), /* pcrel_offset */
1302
1303 HOWTO (R_ARM_MOVW_BREL, /* type */
1304 0, /* rightshift */
1305 2, /* size (0 = byte, 1 = short, 2 = long) */
1306 16, /* bitsize */
1307 FALSE, /* pc_relative */
1308 0, /* bitpos */
1309 complain_overflow_dont,/* complain_on_overflow */
1310 bfd_elf_generic_reloc, /* special_function */
1311 "R_ARM_MOVW_BREL", /* name */
1312 FALSE, /* partial_inplace */
1313 0x0000ffff, /* src_mask */
1314 0x0000ffff, /* dst_mask */
1315 FALSE), /* pcrel_offset */
1316
1317 HOWTO (R_ARM_THM_MOVW_BREL_NC,/* type */
1318 0, /* rightshift */
1319 2, /* size (0 = byte, 1 = short, 2 = long) */
1320 16, /* bitsize */
1321 FALSE, /* pc_relative */
1322 0, /* bitpos */
1323 complain_overflow_dont,/* complain_on_overflow */
1324 bfd_elf_generic_reloc, /* special_function */
1325 "R_ARM_THM_MOVW_BREL_NC",/* name */
1326 FALSE, /* partial_inplace */
1327 0x040f70ff, /* src_mask */
1328 0x040f70ff, /* dst_mask */
1329 FALSE), /* pcrel_offset */
1330
1331 HOWTO (R_ARM_THM_MOVT_BREL, /* type */
1332 0, /* rightshift */
1333 2, /* size (0 = byte, 1 = short, 2 = long) */
1334 16, /* bitsize */
1335 FALSE, /* pc_relative */
1336 0, /* bitpos */
1337 complain_overflow_bitfield,/* complain_on_overflow */
1338 bfd_elf_generic_reloc, /* special_function */
1339 "R_ARM_THM_MOVT_BREL", /* name */
1340 FALSE, /* partial_inplace */
1341 0x040f70ff, /* src_mask */
1342 0x040f70ff, /* dst_mask */
1343 FALSE), /* pcrel_offset */
1344
1345 HOWTO (R_ARM_THM_MOVW_BREL, /* type */
1346 0, /* rightshift */
1347 2, /* size (0 = byte, 1 = short, 2 = long) */
1348 16, /* bitsize */
1349 FALSE, /* pc_relative */
1350 0, /* bitpos */
1351 complain_overflow_dont,/* complain_on_overflow */
1352 bfd_elf_generic_reloc, /* special_function */
1353 "R_ARM_THM_MOVW_BREL", /* name */
1354 FALSE, /* partial_inplace */
1355 0x040f70ff, /* src_mask */
1356 0x040f70ff, /* dst_mask */
1357 FALSE), /* pcrel_offset */
1358
0855e32b
NS		 1359 HOWTO (R_ARM_TLS_GOTDESC, /* type */
1360 0, /* rightshift */
1361 2, /* size (0 = byte, 1 = short, 2 = long) */
1362 32, /* bitsize */
1363 FALSE, /* pc_relative */
1364 0, /* bitpos */
1365 complain_overflow_bitfield,/* complain_on_overflow */
1366 NULL, /* special_function */
1367 "R_ARM_TLS_GOTDESC", /* name */
1368 TRUE, /* partial_inplace */
1369 0xffffffff, /* src_mask */
1370 0xffffffff, /* dst_mask */
1371 FALSE), /* pcrel_offset */
1372
1373 HOWTO (R_ARM_TLS_CALL, /* type */
1374 0, /* rightshift */
1375 2, /* size (0 = byte, 1 = short, 2 = long) */
1376 24, /* bitsize */
1377 FALSE, /* pc_relative */
1378 0, /* bitpos */
1379 complain_overflow_dont,/* complain_on_overflow */
1380 bfd_elf_generic_reloc, /* special_function */
1381 "R_ARM_TLS_CALL", /* name */
1382 FALSE, /* partial_inplace */
1383 0x00ffffff, /* src_mask */
1384 0x00ffffff, /* dst_mask */
1385 FALSE), /* pcrel_offset */
1386
1387 HOWTO (R_ARM_TLS_DESCSEQ, /* type */
1388 0, /* rightshift */
1389 2, /* size (0 = byte, 1 = short, 2 = long) */
1390 0, /* bitsize */
1391 FALSE, /* pc_relative */
1392 0, /* bitpos */
1393 complain_overflow_bitfield,/* complain_on_overflow */
1394 bfd_elf_generic_reloc, /* special_function */
1395 "R_ARM_TLS_DESCSEQ", /* name */
1396 FALSE, /* partial_inplace */
1397 0x00000000, /* src_mask */
1398 0x00000000, /* dst_mask */
1399 FALSE), /* pcrel_offset */
1400
1401 HOWTO (R_ARM_THM_TLS_CALL, /* type */
1402 0, /* rightshift */
1403 2, /* size (0 = byte, 1 = short, 2 = long) */
1404 24, /* bitsize */
1405 FALSE, /* pc_relative */
1406 0, /* bitpos */
1407 complain_overflow_dont,/* complain_on_overflow */
1408 bfd_elf_generic_reloc, /* special_function */
1409 "R_ARM_THM_TLS_CALL", /* name */
1410 FALSE, /* partial_inplace */
1411 0x07ff07ff, /* src_mask */
1412 0x07ff07ff, /* dst_mask */
1413 FALSE), /* pcrel_offset */
c19d1205
ZW		 1414
1415 HOWTO (R_ARM_PLT32_ABS, /* type */
1416 0, /* rightshift */
1417 2, /* size (0 = byte, 1 = short, 2 = long) */
1418 32, /* bitsize */
1419 FALSE, /* pc_relative */
1420 0, /* bitpos */
1421 complain_overflow_dont,/* complain_on_overflow */
1422 bfd_elf_generic_reloc, /* special_function */
1423 "R_ARM_PLT32_ABS", /* name */
1424 FALSE, /* partial_inplace */
1425 0xffffffff, /* src_mask */
1426 0xffffffff, /* dst_mask */
1427 FALSE), /* pcrel_offset */
1428
1429 HOWTO (R_ARM_GOT_ABS, /* type */
1430 0, /* rightshift */
1431 2, /* size (0 = byte, 1 = short, 2 = long) */
1432 32, /* bitsize */
1433 FALSE, /* pc_relative */
1434 0, /* bitpos */
1435 complain_overflow_dont,/* complain_on_overflow */
1436 bfd_elf_generic_reloc, /* special_function */
1437 "R_ARM_GOT_ABS", /* name */
1438 FALSE, /* partial_inplace */
1439 0xffffffff, /* src_mask */
1440 0xffffffff, /* dst_mask */
1441 FALSE), /* pcrel_offset */
1442
1443 HOWTO (R_ARM_GOT_PREL, /* type */
1444 0, /* rightshift */
1445 2, /* size (0 = byte, 1 = short, 2 = long) */
1446 32, /* bitsize */
1447 TRUE, /* pc_relative */
1448 0, /* bitpos */
1449 complain_overflow_dont, /* complain_on_overflow */
1450 bfd_elf_generic_reloc, /* special_function */
1451 "R_ARM_GOT_PREL", /* name */
1452 FALSE, /* partial_inplace */
1453 0xffffffff, /* src_mask */
1454 0xffffffff, /* dst_mask */
1455 TRUE), /* pcrel_offset */
1456
1457 HOWTO (R_ARM_GOT_BREL12, /* type */
1458 0, /* rightshift */
1459 2, /* size (0 = byte, 1 = short, 2 = long) */
1460 12, /* bitsize */
1461 FALSE, /* pc_relative */
1462 0, /* bitpos */
1463 complain_overflow_bitfield,/* complain_on_overflow */
1464 bfd_elf_generic_reloc, /* special_function */
1465 "R_ARM_GOT_BREL12", /* name */
1466 FALSE, /* partial_inplace */
1467 0x00000fff, /* src_mask */
1468 0x00000fff, /* dst_mask */
1469 FALSE), /* pcrel_offset */
1470
1471 HOWTO (R_ARM_GOTOFF12, /* type */
1472 0, /* rightshift */
1473 2, /* size (0 = byte, 1 = short, 2 = long) */
1474 12, /* bitsize */
1475 FALSE, /* pc_relative */
1476 0, /* bitpos */
1477 complain_overflow_bitfield,/* complain_on_overflow */
1478 bfd_elf_generic_reloc, /* special_function */
1479 "R_ARM_GOTOFF12", /* name */
1480 FALSE, /* partial_inplace */
1481 0x00000fff, /* src_mask */
1482 0x00000fff, /* dst_mask */
1483 FALSE), /* pcrel_offset */
1484
1485 EMPTY_HOWTO (R_ARM_GOTRELAX), /* reserved for future GOT-load optimizations */
1486
1487 /* GNU extension to record C++ vtable member usage */
1488 HOWTO (R_ARM_GNU_VTENTRY, /* type */
99059e56
RM		 1489 0, /* rightshift */
1490 2, /* size (0 = byte, 1 = short, 2 = long) */
1491 0, /* bitsize */
1492 FALSE, /* pc_relative */
1493 0, /* bitpos */
1494 complain_overflow_dont, /* complain_on_overflow */
1495 _bfd_elf_rel_vtable_reloc_fn, /* special_function */
1496 "R_ARM_GNU_VTENTRY", /* name */
1497 FALSE, /* partial_inplace */
1498 0, /* src_mask */
1499 0, /* dst_mask */
1500 FALSE), /* pcrel_offset */
c19d1205
ZW		 1501
1502 /* GNU extension to record C++ vtable hierarchy */
1503 HOWTO (R_ARM_GNU_VTINHERIT, /* type */
99059e56
RM		 1504 0, /* rightshift */
1505 2, /* size (0 = byte, 1 = short, 2 = long) */
1506 0, /* bitsize */
1507 FALSE, /* pc_relative */
1508 0, /* bitpos */
1509 complain_overflow_dont, /* complain_on_overflow */
1510 NULL, /* special_function */
1511 "R_ARM_GNU_VTINHERIT", /* name */
1512 FALSE, /* partial_inplace */
1513 0, /* src_mask */
1514 0, /* dst_mask */
1515 FALSE), /* pcrel_offset */
c19d1205
ZW		 1516
1517 HOWTO (R_ARM_THM_JUMP11, /* type */
1518 1, /* rightshift */
1519 1, /* size (0 = byte, 1 = short, 2 = long) */
1520 11, /* bitsize */
1521 TRUE, /* pc_relative */
1522 0, /* bitpos */
1523 complain_overflow_signed, /* complain_on_overflow */
1524 bfd_elf_generic_reloc, /* special_function */
1525 "R_ARM_THM_JUMP11", /* name */
1526 FALSE, /* partial_inplace */
1527 0x000007ff, /* src_mask */
1528 0x000007ff, /* dst_mask */
1529 TRUE), /* pcrel_offset */
1530
1531 HOWTO (R_ARM_THM_JUMP8, /* type */
1532 1, /* rightshift */
1533 1, /* size (0 = byte, 1 = short, 2 = long) */
1534 8, /* bitsize */
1535 TRUE, /* pc_relative */
1536 0, /* bitpos */
1537 complain_overflow_signed, /* complain_on_overflow */
1538 bfd_elf_generic_reloc, /* special_function */
1539 "R_ARM_THM_JUMP8", /* name */
1540 FALSE, /* partial_inplace */
1541 0x000000ff, /* src_mask */
1542 0x000000ff, /* dst_mask */
1543 TRUE), /* pcrel_offset */
ba93b8ac 1544
c19d1205
ZW		 1545 /* TLS relocations */
1546 HOWTO (R_ARM_TLS_GD32, /* type */
99059e56
RM		 1547 0, /* rightshift */
1548 2, /* size (0 = byte, 1 = short, 2 = long) */
1549 32, /* bitsize */
1550 FALSE, /* pc_relative */
1551 0, /* bitpos */
1552 complain_overflow_bitfield,/* complain_on_overflow */
1553 NULL, /* special_function */
1554 "R_ARM_TLS_GD32", /* name */
1555 TRUE, /* partial_inplace */
1556 0xffffffff, /* src_mask */
1557 0xffffffff, /* dst_mask */
1558 FALSE), /* pcrel_offset */
ba93b8ac 1559
ba93b8ac 1560 HOWTO (R_ARM_TLS_LDM32, /* type */
99059e56
RM		 1561 0, /* rightshift */
1562 2, /* size (0 = byte, 1 = short, 2 = long) */
1563 32, /* bitsize */
1564 FALSE, /* pc_relative */
1565 0, /* bitpos */
1566 complain_overflow_bitfield,/* complain_on_overflow */
1567 bfd_elf_generic_reloc, /* special_function */
1568 "R_ARM_TLS_LDM32", /* name */
1569 TRUE, /* partial_inplace */
1570 0xffffffff, /* src_mask */
1571 0xffffffff, /* dst_mask */
1572 FALSE), /* pcrel_offset */
ba93b8ac 1573
c19d1205 1574 HOWTO (R_ARM_TLS_LDO32, /* type */
99059e56
RM		 1575 0, /* rightshift */
1576 2, /* size (0 = byte, 1 = short, 2 = long) */
1577 32, /* bitsize */
1578 FALSE, /* pc_relative */
1579 0, /* bitpos */
1580 complain_overflow_bitfield,/* complain_on_overflow */
1581 bfd_elf_generic_reloc, /* special_function */
1582 "R_ARM_TLS_LDO32", /* name */
1583 TRUE, /* partial_inplace */
1584 0xffffffff, /* src_mask */
1585 0xffffffff, /* dst_mask */
1586 FALSE), /* pcrel_offset */
ba93b8ac 1587
ba93b8ac 1588 HOWTO (R_ARM_TLS_IE32, /* type */
99059e56
RM		 1589 0, /* rightshift */
1590 2, /* size (0 = byte, 1 = short, 2 = long) */
1591 32, /* bitsize */
1592 FALSE, /* pc_relative */
1593 0, /* bitpos */
1594 complain_overflow_bitfield,/* complain_on_overflow */
1595 NULL, /* special_function */
1596 "R_ARM_TLS_IE32", /* name */
1597 TRUE, /* partial_inplace */
1598 0xffffffff, /* src_mask */
1599 0xffffffff, /* dst_mask */
1600 FALSE), /* pcrel_offset */
7f266840 1601
c19d1205 1602 HOWTO (R_ARM_TLS_LE32, /* type */
99059e56
RM		 1603 0, /* rightshift */
1604 2, /* size (0 = byte, 1 = short, 2 = long) */
1605 32, /* bitsize */
1606 FALSE, /* pc_relative */
1607 0, /* bitpos */
1608 complain_overflow_bitfield,/* complain_on_overflow */
75c11999 1609 NULL, /* special_function */
99059e56
RM		 1610 "R_ARM_TLS_LE32", /* name */
1611 TRUE, /* partial_inplace */
1612 0xffffffff, /* src_mask */
1613 0xffffffff, /* dst_mask */
1614 FALSE), /* pcrel_offset */
7f266840 1615
c19d1205
ZW		 1616 HOWTO (R_ARM_TLS_LDO12, /* type */
1617 0, /* rightshift */
1618 2, /* size (0 = byte, 1 = short, 2 = long) */
1619 12, /* bitsize */
1620 FALSE, /* pc_relative */
7f266840 1621 0, /* bitpos */
c19d1205 1622 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1623 bfd_elf_generic_reloc, /* special_function */
c19d1205 1624 "R_ARM_TLS_LDO12", /* name */
7f266840 1625 FALSE, /* partial_inplace */
c19d1205
ZW		 1626 0x00000fff, /* src_mask */
1627 0x00000fff, /* dst_mask */
1628 FALSE), /* pcrel_offset */
7f266840 1629
c19d1205
ZW		 1630 HOWTO (R_ARM_TLS_LE12, /* type */
1631 0, /* rightshift */
1632 2, /* size (0 = byte, 1 = short, 2 = long) */
1633 12, /* bitsize */
1634 FALSE, /* pc_relative */
7f266840 1635 0, /* bitpos */
c19d1205 1636 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1637 bfd_elf_generic_reloc, /* special_function */
c19d1205 1638 "R_ARM_TLS_LE12", /* name */
7f266840 1639 FALSE, /* partial_inplace */
c19d1205
ZW		 1640 0x00000fff, /* src_mask */
1641 0x00000fff, /* dst_mask */
1642 FALSE), /* pcrel_offset */
7f266840 1643
c19d1205 1644 HOWTO (R_ARM_TLS_IE12GP, /* type */
7f266840
DJ		 1645 0, /* rightshift */
1646 2, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 1647 12, /* bitsize */
1648 FALSE, /* pc_relative */
7f266840 1649 0, /* bitpos */
c19d1205 1650 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1651 bfd_elf_generic_reloc, /* special_function */
c19d1205 1652 "R_ARM_TLS_IE12GP", /* name */
7f266840 1653 FALSE, /* partial_inplace */
c19d1205
ZW		 1654 0x00000fff, /* src_mask */
1655 0x00000fff, /* dst_mask */
1656 FALSE), /* pcrel_offset */
0855e32b 1657
34e77a92 1658 /* 112-127 private relocations. */
0855e32b
NS		 1659 EMPTY_HOWTO (112),
1660 EMPTY_HOWTO (113),
1661 EMPTY_HOWTO (114),
1662 EMPTY_HOWTO (115),
1663 EMPTY_HOWTO (116),
1664 EMPTY_HOWTO (117),
1665 EMPTY_HOWTO (118),
1666 EMPTY_HOWTO (119),
1667 EMPTY_HOWTO (120),
1668 EMPTY_HOWTO (121),
1669 EMPTY_HOWTO (122),
1670 EMPTY_HOWTO (123),
1671 EMPTY_HOWTO (124),
1672 EMPTY_HOWTO (125),
1673 EMPTY_HOWTO (126),
1674 EMPTY_HOWTO (127),
34e77a92
RS		 1675
1676 /* R_ARM_ME_TOO, obsolete. */
0855e32b
NS		 1677 EMPTY_HOWTO (128),
1678
1679 HOWTO (R_ARM_THM_TLS_DESCSEQ, /* type */
1680 0, /* rightshift */
1681 1, /* size (0 = byte, 1 = short, 2 = long) */
1682 0, /* bitsize */
1683 FALSE, /* pc_relative */
1684 0, /* bitpos */
1685 complain_overflow_bitfield,/* complain_on_overflow */
1686 bfd_elf_generic_reloc, /* special_function */
1687 "R_ARM_THM_TLS_DESCSEQ",/* name */
1688 FALSE, /* partial_inplace */
1689 0x00000000, /* src_mask */
1690 0x00000000, /* dst_mask */
1691 FALSE), /* pcrel_offset */
72d98d16
MG		 1692 EMPTY_HOWTO (130),
1693 EMPTY_HOWTO (131),
1694 HOWTO (R_ARM_THM_ALU_ABS_G0_NC,/* type. */
1695 0, /* rightshift. */
1696 1, /* size (0 = byte, 1 = short, 2 = long). */
1697 16, /* bitsize. */
1698 FALSE, /* pc_relative. */
1699 0, /* bitpos. */
1700 complain_overflow_bitfield,/* complain_on_overflow. */
1701 bfd_elf_generic_reloc, /* special_function. */
1702 "R_ARM_THM_ALU_ABS_G0_NC",/* name. */
1703 FALSE, /* partial_inplace. */
1704 0x00000000, /* src_mask. */
1705 0x00000000, /* dst_mask. */
1706 FALSE), /* pcrel_offset. */
1707 HOWTO (R_ARM_THM_ALU_ABS_G1_NC,/* type. */
1708 0, /* rightshift. */
1709 1, /* size (0 = byte, 1 = short, 2 = long). */
1710 16, /* bitsize. */
1711 FALSE, /* pc_relative. */
1712 0, /* bitpos. */
1713 complain_overflow_bitfield,/* complain_on_overflow. */
1714 bfd_elf_generic_reloc, /* special_function. */
1715 "R_ARM_THM_ALU_ABS_G1_NC",/* name. */
1716 FALSE, /* partial_inplace. */
1717 0x00000000, /* src_mask. */
1718 0x00000000, /* dst_mask. */
1719 FALSE), /* pcrel_offset. */
1720 HOWTO (R_ARM_THM_ALU_ABS_G2_NC,/* type. */
1721 0, /* rightshift. */
1722 1, /* size (0 = byte, 1 = short, 2 = long). */
1723 16, /* bitsize. */
1724 FALSE, /* pc_relative. */
1725 0, /* bitpos. */
1726 complain_overflow_bitfield,/* complain_on_overflow. */
1727 bfd_elf_generic_reloc, /* special_function. */
1728 "R_ARM_THM_ALU_ABS_G2_NC",/* name. */
1729 FALSE, /* partial_inplace. */
1730 0x00000000, /* src_mask. */
1731 0x00000000, /* dst_mask. */
1732 FALSE), /* pcrel_offset. */
1733 HOWTO (R_ARM_THM_ALU_ABS_G3_NC,/* type. */
1734 0, /* rightshift. */
1735 1, /* size (0 = byte, 1 = short, 2 = long). */
1736 16, /* bitsize. */
1737 FALSE, /* pc_relative. */
1738 0, /* bitpos. */
1739 complain_overflow_bitfield,/* complain_on_overflow. */
1740 bfd_elf_generic_reloc, /* special_function. */
1741 "R_ARM_THM_ALU_ABS_G3_NC",/* name. */
1742 FALSE, /* partial_inplace. */
1743 0x00000000, /* src_mask. */
1744 0x00000000, /* dst_mask. */
1745 FALSE), /* pcrel_offset. */
c19d1205
ZW		 1746};
1747
34e77a92
RS		 1748/* 160 onwards: */
1749static reloc_howto_type elf32_arm_howto_table_2[1] =
1750{
1751 HOWTO (R_ARM_IRELATIVE, /* type */
99059e56
RM		 1752 0, /* rightshift */
1753 2, /* size (0 = byte, 1 = short, 2 = long) */
1754 32, /* bitsize */
1755 FALSE, /* pc_relative */
1756 0, /* bitpos */
1757 complain_overflow_bitfield,/* complain_on_overflow */
1758 bfd_elf_generic_reloc, /* special_function */
1759 "R_ARM_IRELATIVE", /* name */
1760 TRUE, /* partial_inplace */
1761 0xffffffff, /* src_mask */
1762 0xffffffff, /* dst_mask */
1763 FALSE) /* pcrel_offset */
34e77a92 1764};
c19d1205 1765
34e77a92
RS		 1766/* 249-255 extended, currently unused, relocations: */
1767static reloc_howto_type elf32_arm_howto_table_3[4] =
7f266840
DJ		 1768{
1769 HOWTO (R_ARM_RREL32, /* type */
1770 0, /* rightshift */
1771 0, /* size (0 = byte, 1 = short, 2 = long) */
1772 0, /* bitsize */
1773 FALSE, /* pc_relative */
1774 0, /* bitpos */
1775 complain_overflow_dont,/* complain_on_overflow */
1776 bfd_elf_generic_reloc, /* special_function */
1777 "R_ARM_RREL32", /* name */
1778 FALSE, /* partial_inplace */
1779 0, /* src_mask */
1780 0, /* dst_mask */
1781 FALSE), /* pcrel_offset */
1782
1783 HOWTO (R_ARM_RABS32, /* type */
1784 0, /* rightshift */
1785 0, /* size (0 = byte, 1 = short, 2 = long) */
1786 0, /* bitsize */
1787 FALSE, /* pc_relative */
1788 0, /* bitpos */
1789 complain_overflow_dont,/* complain_on_overflow */
1790 bfd_elf_generic_reloc, /* special_function */
1791 "R_ARM_RABS32", /* name */
1792 FALSE, /* partial_inplace */
1793 0, /* src_mask */
1794 0, /* dst_mask */
1795 FALSE), /* pcrel_offset */
1796
1797 HOWTO (R_ARM_RPC24, /* type */
1798 0, /* rightshift */
1799 0, /* size (0 = byte, 1 = short, 2 = long) */
1800 0, /* bitsize */
1801 FALSE, /* pc_relative */
1802 0, /* bitpos */
1803 complain_overflow_dont,/* complain_on_overflow */
1804 bfd_elf_generic_reloc, /* special_function */
1805 "R_ARM_RPC24", /* name */
1806 FALSE, /* partial_inplace */
1807 0, /* src_mask */
1808 0, /* dst_mask */
1809 FALSE), /* pcrel_offset */
1810
1811 HOWTO (R_ARM_RBASE, /* type */
1812 0, /* rightshift */
1813 0, /* size (0 = byte, 1 = short, 2 = long) */
1814 0, /* bitsize */
1815 FALSE, /* pc_relative */
1816 0, /* bitpos */
1817 complain_overflow_dont,/* complain_on_overflow */
1818 bfd_elf_generic_reloc, /* special_function */
1819 "R_ARM_RBASE", /* name */
1820 FALSE, /* partial_inplace */
1821 0, /* src_mask */
1822 0, /* dst_mask */
1823 FALSE) /* pcrel_offset */
1824};
1825
1826static reloc_howto_type *
1827elf32_arm_howto_from_type (unsigned int r_type)
1828{
906e58ca 1829 if (r_type < ARRAY_SIZE (elf32_arm_howto_table_1))
c19d1205 1830 return &elf32_arm_howto_table_1[r_type];
ba93b8ac 1831
34e77a92
RS		 1832 if (r_type == R_ARM_IRELATIVE)
1833 return &elf32_arm_howto_table_2[r_type - R_ARM_IRELATIVE];
1834
c19d1205 1835 if (r_type >= R_ARM_RREL32
34e77a92
RS		 1836 && r_type < R_ARM_RREL32 + ARRAY_SIZE (elf32_arm_howto_table_3))
1837 return &elf32_arm_howto_table_3[r_type - R_ARM_RREL32];
7f266840 1838
c19d1205 1839 return NULL;
7f266840
DJ		 1840}
1841
1842static void
1843elf32_arm_info_to_howto (bfd * abfd ATTRIBUTE_UNUSED, arelent * bfd_reloc,
1844 Elf_Internal_Rela * elf_reloc)
1845{
1846 unsigned int r_type;
1847
1848 r_type = ELF32_R_TYPE (elf_reloc->r_info);
1849 bfd_reloc->howto = elf32_arm_howto_from_type (r_type);
1850}
1851
1852struct elf32_arm_reloc_map
1853 {
1854 bfd_reloc_code_real_type bfd_reloc_val;
1855 unsigned char elf_reloc_val;
1856 };
1857
1858/* All entries in this list must also be present in elf32_arm_howto_table. */
1859static const struct elf32_arm_reloc_map elf32_arm_reloc_map[] =
1860 {
1861 {BFD_RELOC_NONE, R_ARM_NONE},
1862 {BFD_RELOC_ARM_PCREL_BRANCH, R_ARM_PC24},
39b41c9c
PB		 1863 {BFD_RELOC_ARM_PCREL_CALL, R_ARM_CALL},
1864 {BFD_RELOC_ARM_PCREL_JUMP, R_ARM_JUMP24},
7f266840
DJ		 1865 {BFD_RELOC_ARM_PCREL_BLX, R_ARM_XPC25},
1866 {BFD_RELOC_THUMB_PCREL_BLX, R_ARM_THM_XPC22},
1867 {BFD_RELOC_32, R_ARM_ABS32},
1868 {BFD_RELOC_32_PCREL, R_ARM_REL32},
1869 {BFD_RELOC_8, R_ARM_ABS8},
1870 {BFD_RELOC_16, R_ARM_ABS16},
1871 {BFD_RELOC_ARM_OFFSET_IMM, R_ARM_ABS12},
1872 {BFD_RELOC_ARM_THUMB_OFFSET, R_ARM_THM_ABS5},
c19d1205
ZW		 1873 {BFD_RELOC_THUMB_PCREL_BRANCH25, R_ARM_THM_JUMP24},
1874 {BFD_RELOC_THUMB_PCREL_BRANCH23, R_ARM_THM_CALL},
1875 {BFD_RELOC_THUMB_PCREL_BRANCH12, R_ARM_THM_JUMP11},
1876 {BFD_RELOC_THUMB_PCREL_BRANCH20, R_ARM_THM_JUMP19},
1877 {BFD_RELOC_THUMB_PCREL_BRANCH9, R_ARM_THM_JUMP8},
1878 {BFD_RELOC_THUMB_PCREL_BRANCH7, R_ARM_THM_JUMP6},
7f266840
DJ		 1879 {BFD_RELOC_ARM_GLOB_DAT, R_ARM_GLOB_DAT},
1880 {BFD_RELOC_ARM_JUMP_SLOT, R_ARM_JUMP_SLOT},
1881 {BFD_RELOC_ARM_RELATIVE, R_ARM_RELATIVE},
c19d1205 1882 {BFD_RELOC_ARM_GOTOFF, R_ARM_GOTOFF32},
7f266840 1883 {BFD_RELOC_ARM_GOTPC, R_ARM_GOTPC},
b43420e6 1884 {BFD_RELOC_ARM_GOT_PREL, R_ARM_GOT_PREL},
7f266840
DJ		 1885 {BFD_RELOC_ARM_GOT32, R_ARM_GOT32},
1886 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
1887 {BFD_RELOC_ARM_TARGET1, R_ARM_TARGET1},
1888 {BFD_RELOC_ARM_ROSEGREL32, R_ARM_ROSEGREL32},
1889 {BFD_RELOC_ARM_SBREL32, R_ARM_SBREL32},
1890 {BFD_RELOC_ARM_PREL31, R_ARM_PREL31},
ba93b8ac
DJ		 1891 {BFD_RELOC_ARM_TARGET2, R_ARM_TARGET2},
1892 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
0855e32b
NS		 1893 {BFD_RELOC_ARM_TLS_GOTDESC, R_ARM_TLS_GOTDESC},
1894 {BFD_RELOC_ARM_TLS_CALL, R_ARM_TLS_CALL},
1895 {BFD_RELOC_ARM_THM_TLS_CALL, R_ARM_THM_TLS_CALL},
1896 {BFD_RELOC_ARM_TLS_DESCSEQ, R_ARM_TLS_DESCSEQ},
1897 {BFD_RELOC_ARM_THM_TLS_DESCSEQ, R_ARM_THM_TLS_DESCSEQ},
1898 {BFD_RELOC_ARM_TLS_DESC, R_ARM_TLS_DESC},
ba93b8ac
DJ		 1899 {BFD_RELOC_ARM_TLS_GD32, R_ARM_TLS_GD32},
1900 {BFD_RELOC_ARM_TLS_LDO32, R_ARM_TLS_LDO32},
1901 {BFD_RELOC_ARM_TLS_LDM32, R_ARM_TLS_LDM32},
1902 {BFD_RELOC_ARM_TLS_DTPMOD32, R_ARM_TLS_DTPMOD32},
1903 {BFD_RELOC_ARM_TLS_DTPOFF32, R_ARM_TLS_DTPOFF32},
1904 {BFD_RELOC_ARM_TLS_TPOFF32, R_ARM_TLS_TPOFF32},
1905 {BFD_RELOC_ARM_TLS_IE32, R_ARM_TLS_IE32},
1906 {BFD_RELOC_ARM_TLS_LE32, R_ARM_TLS_LE32},
34e77a92 1907 {BFD_RELOC_ARM_IRELATIVE, R_ARM_IRELATIVE},
c19d1205
ZW		 1908 {BFD_RELOC_VTABLE_INHERIT, R_ARM_GNU_VTINHERIT},
1909 {BFD_RELOC_VTABLE_ENTRY, R_ARM_GNU_VTENTRY},
b6895b4f
PB		 1910 {BFD_RELOC_ARM_MOVW, R_ARM_MOVW_ABS_NC},
1911 {BFD_RELOC_ARM_MOVT, R_ARM_MOVT_ABS},
1912 {BFD_RELOC_ARM_MOVW_PCREL, R_ARM_MOVW_PREL_NC},
1913 {BFD_RELOC_ARM_MOVT_PCREL, R_ARM_MOVT_PREL},
1914 {BFD_RELOC_ARM_THUMB_MOVW, R_ARM_THM_MOVW_ABS_NC},
1915 {BFD_RELOC_ARM_THUMB_MOVT, R_ARM_THM_MOVT_ABS},
1916 {BFD_RELOC_ARM_THUMB_MOVW_PCREL, R_ARM_THM_MOVW_PREL_NC},
1917 {BFD_RELOC_ARM_THUMB_MOVT_PCREL, R_ARM_THM_MOVT_PREL},
4962c51a
MS		 1918 {BFD_RELOC_ARM_ALU_PC_G0_NC, R_ARM_ALU_PC_G0_NC},
1919 {BFD_RELOC_ARM_ALU_PC_G0, R_ARM_ALU_PC_G0},
1920 {BFD_RELOC_ARM_ALU_PC_G1_NC, R_ARM_ALU_PC_G1_NC},
1921 {BFD_RELOC_ARM_ALU_PC_G1, R_ARM_ALU_PC_G1},
1922 {BFD_RELOC_ARM_ALU_PC_G2, R_ARM_ALU_PC_G2},
1923 {BFD_RELOC_ARM_LDR_PC_G0, R_ARM_LDR_PC_G0},
1924 {BFD_RELOC_ARM_LDR_PC_G1, R_ARM_LDR_PC_G1},
1925 {BFD_RELOC_ARM_LDR_PC_G2, R_ARM_LDR_PC_G2},
1926 {BFD_RELOC_ARM_LDRS_PC_G0, R_ARM_LDRS_PC_G0},
1927 {BFD_RELOC_ARM_LDRS_PC_G1, R_ARM_LDRS_PC_G1},
1928 {BFD_RELOC_ARM_LDRS_PC_G2, R_ARM_LDRS_PC_G2},
1929 {BFD_RELOC_ARM_LDC_PC_G0, R_ARM_LDC_PC_G0},
1930 {BFD_RELOC_ARM_LDC_PC_G1, R_ARM_LDC_PC_G1},
1931 {BFD_RELOC_ARM_LDC_PC_G2, R_ARM_LDC_PC_G2},
1932 {BFD_RELOC_ARM_ALU_SB_G0_NC, R_ARM_ALU_SB_G0_NC},
1933 {BFD_RELOC_ARM_ALU_SB_G0, R_ARM_ALU_SB_G0},
1934 {BFD_RELOC_ARM_ALU_SB_G1_NC, R_ARM_ALU_SB_G1_NC},
1935 {BFD_RELOC_ARM_ALU_SB_G1, R_ARM_ALU_SB_G1},
1936 {BFD_RELOC_ARM_ALU_SB_G2, R_ARM_ALU_SB_G2},
1937 {BFD_RELOC_ARM_LDR_SB_G0, R_ARM_LDR_SB_G0},
1938 {BFD_RELOC_ARM_LDR_SB_G1, R_ARM_LDR_SB_G1},
1939 {BFD_RELOC_ARM_LDR_SB_G2, R_ARM_LDR_SB_G2},
1940 {BFD_RELOC_ARM_LDRS_SB_G0, R_ARM_LDRS_SB_G0},
1941 {BFD_RELOC_ARM_LDRS_SB_G1, R_ARM_LDRS_SB_G1},
1942 {BFD_RELOC_ARM_LDRS_SB_G2, R_ARM_LDRS_SB_G2},
1943 {BFD_RELOC_ARM_LDC_SB_G0, R_ARM_LDC_SB_G0},
1944 {BFD_RELOC_ARM_LDC_SB_G1, R_ARM_LDC_SB_G1},
845b51d6 1945 {BFD_RELOC_ARM_LDC_SB_G2, R_ARM_LDC_SB_G2},
72d98d16
MG		 1946 {BFD_RELOC_ARM_V4BX, R_ARM_V4BX},
1947 {BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC, R_ARM_THM_ALU_ABS_G3_NC},
1948 {BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC, R_ARM_THM_ALU_ABS_G2_NC},
1949 {BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC, R_ARM_THM_ALU_ABS_G1_NC},
1950 {BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC, R_ARM_THM_ALU_ABS_G0_NC}
7f266840
DJ		 1951 };
1952
1953static reloc_howto_type *
f1c71a59
ZW		 1954elf32_arm_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
1955 bfd_reloc_code_real_type code)
7f266840
DJ		 1956{
1957 unsigned int i;
8029a119 1958
906e58ca 1959 for (i = 0; i < ARRAY_SIZE (elf32_arm_reloc_map); i ++)
c19d1205
ZW		 1960 if (elf32_arm_reloc_map[i].bfd_reloc_val == code)
1961 return elf32_arm_howto_from_type (elf32_arm_reloc_map[i].elf_reloc_val);
7f266840 1962
c19d1205 1963 return NULL;
7f266840
DJ		 1964}
1965
157090f7
AM		 1966static reloc_howto_type *
1967elf32_arm_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
1968 const char *r_name)
1969{
1970 unsigned int i;
1971
906e58ca 1972 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_1); i++)
157090f7
AM		 1973 if (elf32_arm_howto_table_1[i].name != NULL
1974 && strcasecmp (elf32_arm_howto_table_1[i].name, r_name) == 0)
1975 return &elf32_arm_howto_table_1[i];
1976
906e58ca 1977 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_2); i++)
157090f7
AM		 1978 if (elf32_arm_howto_table_2[i].name != NULL
1979 && strcasecmp (elf32_arm_howto_table_2[i].name, r_name) == 0)
1980 return &elf32_arm_howto_table_2[i];
1981
34e77a92
RS		 1982 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_3); i++)
1983 if (elf32_arm_howto_table_3[i].name != NULL
1984 && strcasecmp (elf32_arm_howto_table_3[i].name, r_name) == 0)
1985 return &elf32_arm_howto_table_3[i];
1986
157090f7
AM		 1987 return NULL;
1988}
1989
906e58ca
NC		 1990/* Support for core dump NOTE sections. */
1991
7f266840 1992static bfd_boolean
f1c71a59 1993elf32_arm_nabi_grok_prstatus (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 1994{
1995 int offset;
1996 size_t size;
1997
1998 switch (note->descsz)
1999 {
2000 default:
2001 return FALSE;
2002
8029a119 2003 case 148: /* Linux/ARM 32-bit. */
7f266840 2004 /* pr_cursig */
228e534f 2005 elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12);
7f266840
DJ		 2006
2007 /* pr_pid */
228e534f 2008 elf_tdata (abfd)->core->lwpid = bfd_get_32 (abfd, note->descdata + 24);
7f266840
DJ		 2009
2010 /* pr_reg */
2011 offset = 72;
2012 size = 72;
2013
2014 break;
2015 }
2016
2017 /* Make a ".reg/999" section. */
2018 return _bfd_elfcore_make_pseudosection (abfd, ".reg",
2019 size, note->descpos + offset);
2020}
2021
2022static bfd_boolean
f1c71a59 2023elf32_arm_nabi_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2024{
2025 switch (note->descsz)
2026 {
2027 default:
2028 return FALSE;
2029
8029a119 2030 case 124: /* Linux/ARM elf_prpsinfo. */
228e534f 2031 elf_tdata (abfd)->core->pid
4395ee08 2032 = bfd_get_32 (abfd, note->descdata + 12);
228e534f 2033 elf_tdata (abfd)->core->program
7f266840 2034 = _bfd_elfcore_strndup (abfd, note->descdata + 28, 16);
228e534f 2035 elf_tdata (abfd)->core->command
7f266840
DJ		 2036 = _bfd_elfcore_strndup (abfd, note->descdata + 44, 80);
2037 }
2038
2039 /* Note that for some reason, a spurious space is tacked
2040 onto the end of the args in some (at least one anyway)
2041 implementations, so strip it off if it exists. */
7f266840 2042 {
228e534f 2043 char *command = elf_tdata (abfd)->core->command;
7f266840
DJ		 2044 int n = strlen (command);
2045
2046 if (0 < n && command[n - 1] == ' ')
2047 command[n - 1] = '\0';
2048 }
2049
2050 return TRUE;
2051}
2052
1f20dca5
UW		 2053static char *
2054elf32_arm_nabi_write_core_note (bfd *abfd, char *buf, int *bufsiz,
2055 int note_type, ...)
2056{
2057 switch (note_type)
2058 {
2059 default:
2060 return NULL;
2061
2062 case NT_PRPSINFO:
2063 {
2064 char data[124];
2065 va_list ap;
2066
2067 va_start (ap, note_type);
2068 memset (data, 0, sizeof (data));
2069 strncpy (data + 28, va_arg (ap, const char *), 16);
2070 strncpy (data + 44, va_arg (ap, const char *), 80);
2071 va_end (ap);
2072
2073 return elfcore_write_note (abfd, buf, bufsiz,
2074 "CORE", note_type, data, sizeof (data));
2075 }
2076
2077 case NT_PRSTATUS:
2078 {
2079 char data[148];
2080 va_list ap;
2081 long pid;
2082 int cursig;
2083 const void *greg;
2084
2085 va_start (ap, note_type);
2086 memset (data, 0, sizeof (data));
2087 pid = va_arg (ap, long);
2088 bfd_put_32 (abfd, pid, data + 24);
2089 cursig = va_arg (ap, int);
2090 bfd_put_16 (abfd, cursig, data + 12);
2091 greg = va_arg (ap, const void *);
2092 memcpy (data + 72, greg, 72);
2093 va_end (ap);
2094
2095 return elfcore_write_note (abfd, buf, bufsiz,
2096 "CORE", note_type, data, sizeof (data));
2097 }
2098 }
2099}
2100
6d00b590 2101#define TARGET_LITTLE_SYM arm_elf32_le_vec
7f266840 2102#define TARGET_LITTLE_NAME "elf32-littlearm"
6d00b590 2103#define TARGET_BIG_SYM arm_elf32_be_vec
7f266840
DJ		 2104#define TARGET_BIG_NAME "elf32-bigarm"
2105
2106#define elf_backend_grok_prstatus elf32_arm_nabi_grok_prstatus
2107#define elf_backend_grok_psinfo elf32_arm_nabi_grok_psinfo
1f20dca5 2108#define elf_backend_write_core_note elf32_arm_nabi_write_core_note
7f266840 2109
252b5132
RH		 2110typedef unsigned long int insn32;
2111typedef unsigned short int insn16;
2112
3a4a14e9
PB		 2113/* In lieu of proper flags, assume all EABIv4 or later objects are
2114 interworkable. */
57e8b36a 2115#define INTERWORK_FLAG(abfd) \
3a4a14e9 2116 (EF_ARM_EABI_VERSION (elf_elfheader (abfd)->e_flags) >= EF_ARM_EABI_VER4 \
3e6b1042
DJ		 2117 || (elf_elfheader (abfd)->e_flags & EF_ARM_INTERWORK) \
2118 || ((abfd)->flags & BFD_LINKER_CREATED))
9b485d32 2119
252b5132
RH		 2120/* The linker script knows the section names for placement.
2121 The entry_names are used to do simple name mangling on the stubs.
2122 Given a function name, and its type, the stub can be found. The
9b485d32 2123 name can be changed. The only requirement is the %s be present. */
252b5132
RH		 2124#define THUMB2ARM_GLUE_SECTION_NAME ".glue_7t"
2125#define THUMB2ARM_GLUE_ENTRY_NAME "__%s_from_thumb"
2126
2127#define ARM2THUMB_GLUE_SECTION_NAME ".glue_7"
2128#define ARM2THUMB_GLUE_ENTRY_NAME "__%s_from_arm"
2129
c7b8f16e
JB		 2130#define VFP11_ERRATUM_VENEER_SECTION_NAME ".vfp11_veneer"
2131#define VFP11_ERRATUM_VENEER_ENTRY_NAME "__vfp11_veneer_%x"
2132
a504d23a
LA		 2133#define STM32L4XX_ERRATUM_VENEER_SECTION_NAME ".text.stm32l4xx_veneer"
2134#define STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "__stm32l4xx_veneer_%x"
2135
845b51d6
PB		 2136#define ARM_BX_GLUE_SECTION_NAME ".v4_bx"
2137#define ARM_BX_GLUE_ENTRY_NAME "__bx_r%d"
2138
7413f23f
DJ		 2139#define STUB_ENTRY_NAME "__%s_veneer"
2140
4ba2ef8f
TP		 2141#define CMSE_PREFIX "__acle_se_"
2142
252b5132
RH		 2143/* The name of the dynamic interpreter. This is put in the .interp
2144 section. */
2145#define ELF_DYNAMIC_INTERPRETER "/usr/lib/ld.so.1"
2146
0855e32b 2147static const unsigned long tls_trampoline [] =
b38cadfb
NC		 2148{
2149 0xe08e0000, /* add r0, lr, r0 */
2150 0xe5901004, /* ldr r1, [r0,#4] */
2151 0xe12fff11, /* bx r1 */
2152};
0855e32b
NS		 2153
2154static const unsigned long dl_tlsdesc_lazy_trampoline [] =
b38cadfb
NC		 2155{
2156 0xe52d2004, /* push {r2} */
2157 0xe59f200c, /* ldr r2, [pc, #3f - . - 8] */
2158 0xe59f100c, /* ldr r1, [pc, #4f - . - 8] */
2159 0xe79f2002, /* 1: ldr r2, [pc, r2] */
2160 0xe081100f, /* 2: add r1, pc */
2161 0xe12fff12, /* bx r2 */
2162 0x00000014, /* 3: .word _GLOBAL_OFFSET_TABLE_ - 1b - 8
99059e56 2163 + dl_tlsdesc_lazy_resolver(GOT) */
b38cadfb
NC		 2164 0x00000018, /* 4: .word _GLOBAL_OFFSET_TABLE_ - 2b - 8 */
2165};
0855e32b 2166
5e681ec4
PB		 2167#ifdef FOUR_WORD_PLT
2168
252b5132
RH		 2169/* The first entry in a procedure linkage table looks like
2170 this. It is set up so that any shared library function that is
59f2c4e7 2171 called before the relocation has been set up calls the dynamic
9b485d32 2172 linker first. */
e5a52504 2173static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2174{
2175 0xe52de004, /* str lr, [sp, #-4]! */
2176 0xe59fe010, /* ldr lr, [pc, #16] */
2177 0xe08fe00e, /* add lr, pc, lr */
2178 0xe5bef008, /* ldr pc, [lr, #8]! */
2179};
5e681ec4
PB		 2180
2181/* Subsequent entries in a procedure linkage table look like
2182 this. */
e5a52504 2183static const bfd_vma elf32_arm_plt_entry [] =
b38cadfb
NC		 2184{
2185 0xe28fc600, /* add ip, pc, #NN */
2186 0xe28cca00, /* add ip, ip, #NN */
2187 0xe5bcf000, /* ldr pc, [ip, #NN]! */
2188 0x00000000, /* unused */
2189};
5e681ec4 2190
eed94f8f 2191#else /* not FOUR_WORD_PLT */
5e681ec4 2192
5e681ec4
PB		 2193/* The first entry in a procedure linkage table looks like
2194 this. It is set up so that any shared library function that is
2195 called before the relocation has been set up calls the dynamic
2196 linker first. */
e5a52504 2197static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2198{
2199 0xe52de004, /* str lr, [sp, #-4]! */
2200 0xe59fe004, /* ldr lr, [pc, #4] */
2201 0xe08fe00e, /* add lr, pc, lr */
2202 0xe5bef008, /* ldr pc, [lr, #8]! */
2203 0x00000000, /* &GOT[0] - . */
2204};
252b5132 2205
1db37fe6
YG		 2206/* By default subsequent entries in a procedure linkage table look like
2207 this. Offsets that don't fit into 28 bits will cause link error. */
2208static const bfd_vma elf32_arm_plt_entry_short [] =
b38cadfb
NC		 2209{
2210 0xe28fc600, /* add ip, pc, #0xNN00000 */
2211 0xe28cca00, /* add ip, ip, #0xNN000 */
2212 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2213};
5e681ec4 2214
1db37fe6
YG		 2215/* When explicitly asked, we'll use this "long" entry format
2216 which can cope with arbitrary displacements. */
2217static const bfd_vma elf32_arm_plt_entry_long [] =
2218{
2219 0xe28fc200, /* add ip, pc, #0xN0000000 */
2220 0xe28cc600, /* add ip, ip, #0xNN00000 */
2221 0xe28cca00, /* add ip, ip, #0xNN000 */
2222 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2223};
2224
2225static bfd_boolean elf32_arm_use_long_plt_entry = FALSE;
2226
eed94f8f
NC		 2227#endif /* not FOUR_WORD_PLT */
2228
2229/* The first entry in a procedure linkage table looks like this.
2230 It is set up so that any shared library function that is called before the
2231 relocation has been set up calls the dynamic linker first. */
2232static const bfd_vma elf32_thumb2_plt0_entry [] =
2233{
2234 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2235 an instruction maybe encoded to one or two array elements. */
2236 0xf8dfb500, /* push {lr} */
2237 0x44fee008, /* ldr.w lr, [pc, #8] */
469a3493 2238 /* add lr, pc */
eed94f8f
NC		 2239 0xff08f85e, /* ldr.w pc, [lr, #8]! */
2240 0x00000000, /* &GOT[0] - . */
2241};
2242
2243/* Subsequent entries in a procedure linkage table for thumb only target
2244 look like this. */
2245static const bfd_vma elf32_thumb2_plt_entry [] =
2246{
2247 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2248 an instruction maybe encoded to one or two array elements. */
2249 0x0c00f240, /* movw ip, #0xNNNN */
2250 0x0c00f2c0, /* movt ip, #0xNNNN */
2251 0xf8dc44fc, /* add ip, pc */
2252 0xbf00f000 /* ldr.w pc, [ip] */
469a3493 2253 /* nop */
eed94f8f 2254};
252b5132 2255
00a97672
RS		 2256/* The format of the first entry in the procedure linkage table
2257 for a VxWorks executable. */
2258static const bfd_vma elf32_arm_vxworks_exec_plt0_entry[] =
b38cadfb
NC		 2259{
2260 0xe52dc008, /* str ip,[sp,#-8]! */
2261 0xe59fc000, /* ldr ip,[pc] */
2262 0xe59cf008, /* ldr pc,[ip,#8] */
2263 0x00000000, /* .long _GLOBAL_OFFSET_TABLE_ */
2264};
00a97672
RS		 2265
2266/* The format of subsequent entries in a VxWorks executable. */
2267static const bfd_vma elf32_arm_vxworks_exec_plt_entry[] =
b38cadfb
NC		 2268{
2269 0xe59fc000, /* ldr ip,[pc] */
2270 0xe59cf000, /* ldr pc,[ip] */
2271 0x00000000, /* .long @got */
2272 0xe59fc000, /* ldr ip,[pc] */
2273 0xea000000, /* b _PLT */
2274 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
2275};
00a97672
RS		 2276
2277/* The format of entries in a VxWorks shared library. */
2278static const bfd_vma elf32_arm_vxworks_shared_plt_entry[] =
b38cadfb
NC		 2279{
2280 0xe59fc000, /* ldr ip,[pc] */
2281 0xe79cf009, /* ldr pc,[ip,r9] */
2282 0x00000000, /* .long @got */
2283 0xe59fc000, /* ldr ip,[pc] */
2284 0xe599f008, /* ldr pc,[r9,#8] */
2285 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
2286};
00a97672 2287
b7693d02
DJ		 2288/* An initial stub used if the PLT entry is referenced from Thumb code. */
2289#define PLT_THUMB_STUB_SIZE 4
2290static const bfd_vma elf32_arm_plt_thumb_stub [] =
b38cadfb
NC		 2291{
2292 0x4778, /* bx pc */
2293 0x46c0 /* nop */
2294};
b7693d02 2295
e5a52504
MM		 2296/* The entries in a PLT when using a DLL-based target with multiple
2297 address spaces. */
906e58ca 2298static const bfd_vma elf32_arm_symbian_plt_entry [] =
b38cadfb
NC		 2299{
2300 0xe51ff004, /* ldr pc, [pc, #-4] */
2301 0x00000000, /* dcd R_ARM_GLOB_DAT(X) */
2302};
2303
2304/* The first entry in a procedure linkage table looks like
2305 this. It is set up so that any shared library function that is
2306 called before the relocation has been set up calls the dynamic
2307 linker first. */
2308static const bfd_vma elf32_arm_nacl_plt0_entry [] =
2309{
2310 /* First bundle: */
2311 0xe300c000, /* movw ip, #:lower16:&GOT[2]-.+8 */
2312 0xe340c000, /* movt ip, #:upper16:&GOT[2]-.+8 */
2313 0xe08cc00f, /* add ip, ip, pc */
2314 0xe52dc008, /* str ip, [sp, #-8]! */
2315 /* Second bundle: */
edccdf7c
RM		 2316 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2317 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2318 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2319 0xe12fff1c, /* bx ip */
b38cadfb 2320 /* Third bundle: */
edccdf7c
RM		 2321 0xe320f000, /* nop */
2322 0xe320f000, /* nop */
2323 0xe320f000, /* nop */
b38cadfb
NC		 2324 /* .Lplt_tail: */
2325 0xe50dc004, /* str ip, [sp, #-4] */
2326 /* Fourth bundle: */
edccdf7c
RM		 2327 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2328 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2329 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2330 0xe12fff1c, /* bx ip */
b38cadfb
NC		 2331};
2332#define ARM_NACL_PLT_TAIL_OFFSET (11 * 4)
2333
2334/* Subsequent entries in a procedure linkage table look like this. */
2335static const bfd_vma elf32_arm_nacl_plt_entry [] =
2336{
2337 0xe300c000, /* movw ip, #:lower16:&GOT[n]-.+8 */
2338 0xe340c000, /* movt ip, #:upper16:&GOT[n]-.+8 */
2339 0xe08cc00f, /* add ip, ip, pc */
2340 0xea000000, /* b .Lplt_tail */
2341};
e5a52504 2342
906e58ca
NC		 2343#define ARM_MAX_FWD_BRANCH_OFFSET ((((1 << 23) - 1) << 2) + 8)
2344#define ARM_MAX_BWD_BRANCH_OFFSET ((-((1 << 23) << 2)) + 8)
2345#define THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) -2 + 4)
2346#define THM_MAX_BWD_BRANCH_OFFSET (-(1 << 22) + 4)
2347#define THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 2) + 4)
2348#define THM2_MAX_BWD_BRANCH_OFFSET (-(1 << 24) + 4)
c5423981
TG		 2349#define THM2_MAX_FWD_COND_BRANCH_OFFSET (((1 << 20) -2) + 4)
2350#define THM2_MAX_BWD_COND_BRANCH_OFFSET (-(1 << 20) + 4)
906e58ca 2351
461a49ca 2352enum stub_insn_type
b38cadfb
NC		 2353{
2354 THUMB16_TYPE = 1,
2355 THUMB32_TYPE,
2356 ARM_TYPE,
2357 DATA_TYPE
2358};
461a49ca 2359
48229727
JB		 2360#define THUMB16_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 0}
2361/* A bit of a hack. A Thumb conditional branch, in which the proper condition
2362 is inserted in arm_build_one_stub(). */
2363#define THUMB16_BCOND_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 1}
2364#define THUMB32_INSN(X) {(X), THUMB32_TYPE, R_ARM_NONE, 0}
d5a67c02
AV		 2365#define THUMB32_MOVT(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVT_ABS, 0}
2366#define THUMB32_MOVW(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVW_ABS_NC, 0}
48229727
JB		 2367#define THUMB32_B_INSN(X, Z) {(X), THUMB32_TYPE, R_ARM_THM_JUMP24, (Z)}
2368#define ARM_INSN(X) {(X), ARM_TYPE, R_ARM_NONE, 0}
2369#define ARM_REL_INSN(X, Z) {(X), ARM_TYPE, R_ARM_JUMP24, (Z)}
2370#define DATA_WORD(X,Y,Z) {(X), DATA_TYPE, (Y), (Z)}
461a49ca
DJ		 2371
2372typedef struct
2373{
b38cadfb
NC		 2374 bfd_vma data;
2375 enum stub_insn_type type;
2376 unsigned int r_type;
2377 int reloc_addend;
461a49ca
DJ		 2378} insn_sequence;
2379
fea2b4d6
CL		 2380/* Arm/Thumb -> Arm/Thumb long branch stub. On V5T and above, use blx
2381 to reach the stub if necessary. */
461a49ca 2382static const insn_sequence elf32_arm_stub_long_branch_any_any[] =
b38cadfb
NC		 2383{
2384 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
2385 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2386};
906e58ca 2387
fea2b4d6
CL		 2388/* V4T Arm -> Thumb long branch stub. Used on V4T where blx is not
2389 available. */
461a49ca 2390static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb[] =
b38cadfb
NC		 2391{
2392 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2393 ARM_INSN (0xe12fff1c), /* bx ip */
2394 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2395};
906e58ca 2396
d3626fb0 2397/* Thumb -> Thumb long branch stub. Used on M-profile architectures. */
461a49ca 2398static const insn_sequence elf32_arm_stub_long_branch_thumb_only[] =
b38cadfb
NC		 2399{
2400 THUMB16_INSN (0xb401), /* push {r0} */
2401 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2402 THUMB16_INSN (0x4684), /* mov ip, r0 */
2403 THUMB16_INSN (0xbc01), /* pop {r0} */
2404 THUMB16_INSN (0x4760), /* bx ip */
2405 THUMB16_INSN (0xbf00), /* nop */
2406 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2407};
906e58ca 2408
80c135e5
TP		 2409/* Thumb -> Thumb long branch stub in thumb2 encoding. Used on armv7. */
2410static const insn_sequence elf32_arm_stub_long_branch_thumb2_only[] =
2411{
2412 THUMB32_INSN (0xf85ff000), /* ldr.w pc, [pc, #-0] */
2413 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(x) */
2414};
2415
d5a67c02
AV		 2416/* Thumb -> Thumb long branch stub. Used for PureCode sections on Thumb2
2417 M-profile architectures. */
2418static const insn_sequence elf32_arm_stub_long_branch_thumb2_only_pure[] =
2419{
2420 THUMB32_MOVW (0xf2400c00), /* mov.w ip, R_ARM_MOVW_ABS_NC */
2421 THUMB32_MOVT (0xf2c00c00), /* movt ip, R_ARM_MOVT_ABS << 16 */
2422 THUMB16_INSN (0x4760), /* bx ip */
2423};
2424
d3626fb0
CL		 2425/* V4T Thumb -> Thumb long branch stub. Using the stack is not
2426 allowed. */
2427static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb[] =
b38cadfb
NC		 2428{
2429 THUMB16_INSN (0x4778), /* bx pc */
2430 THUMB16_INSN (0x46c0), /* nop */
2431 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2432 ARM_INSN (0xe12fff1c), /* bx ip */
2433 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2434};
d3626fb0 2435
fea2b4d6
CL		 2436/* V4T Thumb -> ARM long branch stub. Used on V4T where blx is not
2437 available. */
461a49ca 2438static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm[] =
b38cadfb
NC		 2439{
2440 THUMB16_INSN (0x4778), /* bx pc */
2441 THUMB16_INSN (0x46c0), /* nop */
2442 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
2443 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2444};
906e58ca 2445
fea2b4d6
CL		 2446/* V4T Thumb -> ARM short branch stub. Shorter variant of the above
2447 one, when the destination is close enough. */
461a49ca 2448static const insn_sequence elf32_arm_stub_short_branch_v4t_thumb_arm[] =
b38cadfb
NC		 2449{
2450 THUMB16_INSN (0x4778), /* bx pc */
2451 THUMB16_INSN (0x46c0), /* nop */
2452 ARM_REL_INSN (0xea000000, -8), /* b (X-8) */
2453};
c820be07 2454
cf3eccff 2455/* ARM/Thumb -> ARM long branch stub, PIC. On V5T and above, use
fea2b4d6 2456 blx to reach the stub if necessary. */
cf3eccff 2457static const insn_sequence elf32_arm_stub_long_branch_any_arm_pic[] =
b38cadfb
NC		 2458{
2459 ARM_INSN (0xe59fc000), /* ldr ip, [pc] */
2460 ARM_INSN (0xe08ff00c), /* add pc, pc, ip */
2461 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
2462};
906e58ca 2463
cf3eccff
DJ		 2464/* ARM/Thumb -> Thumb long branch stub, PIC. On V5T and above, use
2465 blx to reach the stub if necessary. We can not add into pc;
2466 it is not guaranteed to mode switch (different in ARMv6 and
2467 ARMv7). */
2468static const insn_sequence elf32_arm_stub_long_branch_any_thumb_pic[] =
b38cadfb
NC		 2469{
2470 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2471 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2472 ARM_INSN (0xe12fff1c), /* bx ip */
2473 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2474};
cf3eccff 2475
ebe24dd4
CL		 2476/* V4T ARM -> ARM long branch stub, PIC. */
2477static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb_pic[] =
b38cadfb
NC		 2478{
2479 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2480 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2481 ARM_INSN (0xe12fff1c), /* bx ip */
2482 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2483};
ebe24dd4
CL		 2484
2485/* V4T Thumb -> ARM long branch stub, PIC. */
2486static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm_pic[] =
b38cadfb
NC		 2487{
2488 THUMB16_INSN (0x4778), /* bx pc */
2489 THUMB16_INSN (0x46c0), /* nop */
2490 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2491 ARM_INSN (0xe08cf00f), /* add pc, ip, pc */
2492 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
2493};
ebe24dd4 2494
d3626fb0
CL		 2495/* Thumb -> Thumb long branch stub, PIC. Used on M-profile
2496 architectures. */
ebe24dd4 2497static const insn_sequence elf32_arm_stub_long_branch_thumb_only_pic[] =
b38cadfb
NC		 2498{
2499 THUMB16_INSN (0xb401), /* push {r0} */
2500 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2501 THUMB16_INSN (0x46fc), /* mov ip, pc */
2502 THUMB16_INSN (0x4484), /* add ip, r0 */
2503 THUMB16_INSN (0xbc01), /* pop {r0} */
2504 THUMB16_INSN (0x4760), /* bx ip */
2505 DATA_WORD (0, R_ARM_REL32, 4), /* dcd R_ARM_REL32(X) */
2506};
ebe24dd4 2507
d3626fb0
CL		 2508/* V4T Thumb -> Thumb long branch stub, PIC. Using the stack is not
2509 allowed. */
2510static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb_pic[] =
b38cadfb
NC		 2511{
2512 THUMB16_INSN (0x4778), /* bx pc */
2513 THUMB16_INSN (0x46c0), /* nop */
2514 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2515 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2516 ARM_INSN (0xe12fff1c), /* bx ip */
2517 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2518};
d3626fb0 2519
0855e32b
NS		 2520/* Thumb2/ARM -> TLS trampoline. Lowest common denominator, which is a
2521 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2522static const insn_sequence elf32_arm_stub_long_branch_any_tls_pic[] =
2523{
b38cadfb
NC		 2524 ARM_INSN (0xe59f1000), /* ldr r1, [pc] */
2525 ARM_INSN (0xe08ff001), /* add pc, pc, r1 */
2526 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
0855e32b
NS		 2527};
2528
2529/* V4T Thumb -> TLS trampoline. lowest common denominator, which is a
2530 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2531static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_tls_pic[] =
2532{
b38cadfb
NC		 2533 THUMB16_INSN (0x4778), /* bx pc */
2534 THUMB16_INSN (0x46c0), /* nop */
2535 ARM_INSN (0xe59f1000), /* ldr r1, [pc, #0] */
2536 ARM_INSN (0xe081f00f), /* add pc, r1, pc */
2537 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
0855e32b
NS		 2538};
2539
7a89b94e
NC		 2540/* NaCl ARM -> ARM long branch stub. */
2541static const insn_sequence elf32_arm_stub_long_branch_arm_nacl[] =
2542{
2543 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2544 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
2545 ARM_INSN (0xe12fff1c), /* bx ip */
2546 ARM_INSN (0xe320f000), /* nop */
2547 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2548 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2549 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2550 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2551};
2552
2553/* NaCl ARM -> ARM long branch stub, PIC. */
2554static const insn_sequence elf32_arm_stub_long_branch_arm_nacl_pic[] =
2555{
2556 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2557 ARM_INSN (0xe08cc00f), /* add ip, ip, pc */
2558 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
2559 ARM_INSN (0xe12fff1c), /* bx ip */
2560 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2561 DATA_WORD (0, R_ARM_REL32, 8), /* dcd R_ARM_REL32(X+8) */
2562 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2563 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2564};
2565
4ba2ef8f
TP		 2566/* Stub used for transition to secure state (aka SG veneer). */
2567static const insn_sequence elf32_arm_stub_cmse_branch_thumb_only[] =
2568{
2569 THUMB32_INSN (0xe97fe97f), /* sg. */
2570 THUMB32_B_INSN (0xf000b800, -4), /* b.w original_branch_dest. */
2571};
2572
7a89b94e 2573
48229727
JB		 2574/* Cortex-A8 erratum-workaround stubs. */
2575
2576/* Stub used for conditional branches (which may be beyond +/-1MB away, so we
2577 can't use a conditional branch to reach this stub). */
2578
2579static const insn_sequence elf32_arm_stub_a8_veneer_b_cond[] =
b38cadfb
NC		 2580{
2581 THUMB16_BCOND_INSN (0xd001), /* b<cond>.n true. */
2582 THUMB32_B_INSN (0xf000b800, -4), /* b.w insn_after_original_branch. */
2583 THUMB32_B_INSN (0xf000b800, -4) /* true: b.w original_branch_dest. */
2584};
48229727
JB		 2585
2586/* Stub used for b.w and bl.w instructions. */
2587
2588static const insn_sequence elf32_arm_stub_a8_veneer_b[] =
b38cadfb
NC		 2589{
2590 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2591};
48229727
JB		 2592
2593static const insn_sequence elf32_arm_stub_a8_veneer_bl[] =
b38cadfb
NC		 2594{
2595 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2596};
48229727
JB		 2597
2598/* Stub used for Thumb-2 blx.w instructions. We modified the original blx.w
2599 instruction (which switches to ARM mode) to point to this stub. Jump to the
2600 real destination using an ARM-mode branch. */
2601
2602static const insn_sequence elf32_arm_stub_a8_veneer_blx[] =
b38cadfb
NC		 2603{
2604 ARM_REL_INSN (0xea000000, -8) /* b original_branch_dest. */
2605};
48229727 2606
9553db3c
NC		 2607/* For each section group there can be a specially created linker section
2608 to hold the stubs for that group. The name of the stub section is based
2609 upon the name of another section within that group with the suffix below
2610 applied.
2611
2612 PR 13049: STUB_SUFFIX used to be ".stub", but this allowed the user to
2613 create what appeared to be a linker stub section when it actually
2614 contained user code/data. For example, consider this fragment:
b38cadfb 2615
9553db3c
NC		 2616 const char * stubborn_problems[] = { "np" };
2617
2618 If this is compiled with "-fPIC -fdata-sections" then gcc produces a
2619 section called:
2620
2621 .data.rel.local.stubborn_problems
2622
2623 This then causes problems in arm32_arm_build_stubs() as it triggers:
2624
2625 // Ignore non-stub sections.
2626 if (!strstr (stub_sec->name, STUB_SUFFIX))
2627 continue;
2628
2629 And so the section would be ignored instead of being processed. Hence
2630 the change in definition of STUB_SUFFIX to a name that cannot be a valid
2631 C identifier. */
2632#define STUB_SUFFIX ".__stub"
906e58ca 2633
738a79f6
CL		 2634/* One entry per long/short branch stub defined above. */
2635#define DEF_STUBS \
2636 DEF_STUB(long_branch_any_any) \
2637 DEF_STUB(long_branch_v4t_arm_thumb) \
2638 DEF_STUB(long_branch_thumb_only) \
2639 DEF_STUB(long_branch_v4t_thumb_thumb) \
2640 DEF_STUB(long_branch_v4t_thumb_arm) \
2641 DEF_STUB(short_branch_v4t_thumb_arm) \
2642 DEF_STUB(long_branch_any_arm_pic) \
2643 DEF_STUB(long_branch_any_thumb_pic) \
2644 DEF_STUB(long_branch_v4t_thumb_thumb_pic) \
2645 DEF_STUB(long_branch_v4t_arm_thumb_pic) \
2646 DEF_STUB(long_branch_v4t_thumb_arm_pic) \
48229727 2647 DEF_STUB(long_branch_thumb_only_pic) \
0855e32b
NS		 2648 DEF_STUB(long_branch_any_tls_pic) \
2649 DEF_STUB(long_branch_v4t_thumb_tls_pic) \
7a89b94e
NC		 2650 DEF_STUB(long_branch_arm_nacl) \
2651 DEF_STUB(long_branch_arm_nacl_pic) \
4ba2ef8f 2652 DEF_STUB(cmse_branch_thumb_only) \
48229727
JB		 2653 DEF_STUB(a8_veneer_b_cond) \
2654 DEF_STUB(a8_veneer_b) \
2655 DEF_STUB(a8_veneer_bl) \
80c135e5
TP		 2656 DEF_STUB(a8_veneer_blx) \
2657 DEF_STUB(long_branch_thumb2_only) \
d5a67c02 2658 DEF_STUB(long_branch_thumb2_only_pure)
738a79f6
CL		 2659
2660#define DEF_STUB(x) arm_stub_##x,
b38cadfb
NC		 2661enum elf32_arm_stub_type
2662{
906e58ca 2663 arm_stub_none,
738a79f6 2664 DEF_STUBS
4f4faa4d 2665 max_stub_type
738a79f6
CL		 2666};
2667#undef DEF_STUB
2668
8d9d9490
TP		 2669/* Note the first a8_veneer type. */
2670const unsigned arm_stub_a8_veneer_lwm = arm_stub_a8_veneer_b_cond;
2671
738a79f6
CL		 2672typedef struct
2673{
d3ce72d0 2674 const insn_sequence* template_sequence;
738a79f6
CL		 2675 int template_size;
2676} stub_def;
2677
2678#define DEF_STUB(x) {elf32_arm_stub_##x, ARRAY_SIZE(elf32_arm_stub_##x)},
b38cadfb
NC		 2679static const stub_def stub_definitions[] =
2680{
738a79f6
CL		 2681 {NULL, 0},
2682 DEF_STUBS
906e58ca
NC		 2683};
2684
2685struct elf32_arm_stub_hash_entry
2686{
2687 /* Base hash table entry structure. */
2688 struct bfd_hash_entry root;
2689
2690 /* The stub section. */
2691 asection *stub_sec;
2692
2693 /* Offset within stub_sec of the beginning of this stub. */
2694 bfd_vma stub_offset;
2695
2696 /* Given the symbol's value and its section we can determine its final
2697 value when building the stubs (so the stub knows where to jump). */
2698 bfd_vma target_value;
2699 asection *target_section;
2700
8d9d9490
TP		 2701 /* Same as above but for the source of the branch to the stub. Used for
2702 Cortex-A8 erratum workaround to patch it to branch to the stub. As
2703 such, source section does not need to be recorded since Cortex-A8 erratum
2704 workaround stubs are only generated when both source and target are in the
2705 same section. */
2706 bfd_vma source_value;
48229727
JB		 2707
2708 /* The instruction which caused this stub to be generated (only valid for
2709 Cortex-A8 erratum workaround stubs at present). */
2710 unsigned long orig_insn;
2711
461a49ca 2712 /* The stub type. */
906e58ca 2713 enum elf32_arm_stub_type stub_type;
461a49ca
DJ		 2714 /* Its encoding size in bytes. */
2715 int stub_size;
2716 /* Its template. */
2717 const insn_sequence *stub_template;
2718 /* The size of the template (number of entries). */
2719 int stub_template_size;
906e58ca
NC		 2720
2721 /* The symbol table entry, if any, that this was derived from. */
2722 struct elf32_arm_link_hash_entry *h;
2723
35fc36a8
RS		 2724 /* Type of branch. */
2725 enum arm_st_branch_type branch_type;
906e58ca
NC		 2726
2727 /* Where this stub is being called from, or, in the case of combined
2728 stub sections, the first input section in the group. */
2729 asection *id_sec;
7413f23f
DJ		 2730
2731 /* The name for the local symbol at the start of this stub. The
2732 stub name in the hash table has to be unique; this does not, so
2733 it can be friendlier. */
2734 char *output_name;
906e58ca
NC		 2735};
2736
e489d0ae
PB		 2737/* Used to build a map of a section. This is required for mixed-endian
2738 code/data. */
2739
2740typedef struct elf32_elf_section_map
2741{
2742 bfd_vma vma;
2743 char type;
2744}
2745elf32_arm_section_map;
2746
c7b8f16e
JB		 2747/* Information about a VFP11 erratum veneer, or a branch to such a veneer. */
2748
2749typedef enum
2750{
2751 VFP11_ERRATUM_BRANCH_TO_ARM_VENEER,
2752 VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER,
2753 VFP11_ERRATUM_ARM_VENEER,
2754 VFP11_ERRATUM_THUMB_VENEER
2755}
2756elf32_vfp11_erratum_type;
2757
2758typedef struct elf32_vfp11_erratum_list
2759{
2760 struct elf32_vfp11_erratum_list *next;
2761 bfd_vma vma;
2762 union
2763 {
2764 struct
2765 {
2766 struct elf32_vfp11_erratum_list *veneer;
2767 unsigned int vfp_insn;
2768 } b;
2769 struct
2770 {
2771 struct elf32_vfp11_erratum_list *branch;
2772 unsigned int id;
2773 } v;
2774 } u;
2775 elf32_vfp11_erratum_type type;
2776}
2777elf32_vfp11_erratum_list;
2778
a504d23a
LA		 2779/* Information about a STM32L4XX erratum veneer, or a branch to such a
2780 veneer. */
2781typedef enum
2782{
2783 STM32L4XX_ERRATUM_BRANCH_TO_VENEER,
2784 STM32L4XX_ERRATUM_VENEER
2785}
2786elf32_stm32l4xx_erratum_type;
2787
2788typedef struct elf32_stm32l4xx_erratum_list
2789{
2790 struct elf32_stm32l4xx_erratum_list *next;
2791 bfd_vma vma;
2792 union
2793 {
2794 struct
2795 {
2796 struct elf32_stm32l4xx_erratum_list *veneer;
2797 unsigned int insn;
2798 } b;
2799 struct
2800 {
2801 struct elf32_stm32l4xx_erratum_list *branch;
2802 unsigned int id;
2803 } v;
2804 } u;
2805 elf32_stm32l4xx_erratum_type type;
2806}
2807elf32_stm32l4xx_erratum_list;
2808
2468f9c9
PB		 2809typedef enum
2810{
2811 DELETE_EXIDX_ENTRY,
2812 INSERT_EXIDX_CANTUNWIND_AT_END
2813}
2814arm_unwind_edit_type;
2815
2816/* A (sorted) list of edits to apply to an unwind table. */
2817typedef struct arm_unwind_table_edit
2818{
2819 arm_unwind_edit_type type;
2820 /* Note: we sometimes want to insert an unwind entry corresponding to a
2821 section different from the one we're currently writing out, so record the
2822 (text) section this edit relates to here. */
2823 asection *linked_section;
2824 unsigned int index;
2825 struct arm_unwind_table_edit *next;
2826}
2827arm_unwind_table_edit;
2828
8e3de13a 2829typedef struct _arm_elf_section_data
e489d0ae 2830{
2468f9c9 2831 /* Information about mapping symbols. */
e489d0ae 2832 struct bfd_elf_section_data elf;
8e3de13a 2833 unsigned int mapcount;
c7b8f16e 2834 unsigned int mapsize;
e489d0ae 2835 elf32_arm_section_map *map;
2468f9c9 2836 /* Information about CPU errata. */
c7b8f16e
JB		 2837 unsigned int erratumcount;
2838 elf32_vfp11_erratum_list *erratumlist;
a504d23a
LA		 2839 unsigned int stm32l4xx_erratumcount;
2840 elf32_stm32l4xx_erratum_list *stm32l4xx_erratumlist;
491d01d3 2841 unsigned int additional_reloc_count;
2468f9c9
PB		 2842 /* Information about unwind tables. */
2843 union
2844 {
2845 /* Unwind info attached to a text section. */
2846 struct
2847 {
2848 asection *arm_exidx_sec;
2849 } text;
2850
2851 /* Unwind info attached to an .ARM.exidx section. */
2852 struct
2853 {
2854 arm_unwind_table_edit *unwind_edit_list;
2855 arm_unwind_table_edit *unwind_edit_tail;
2856 } exidx;
2857 } u;
8e3de13a
NC		 2858}
2859_arm_elf_section_data;
e489d0ae
PB		 2860
2861#define elf32_arm_section_data(sec) \
8e3de13a 2862 ((_arm_elf_section_data *) elf_section_data (sec))
e489d0ae 2863
48229727
JB		 2864/* A fix which might be required for Cortex-A8 Thumb-2 branch/TLB erratum.
2865 These fixes are subject to a relaxation procedure (in elf32_arm_size_stubs),
2866 so may be created multiple times: we use an array of these entries whilst
2867 relaxing which we can refresh easily, then create stubs for each potentially
2868 erratum-triggering instruction once we've settled on a solution. */
2869
b38cadfb
NC		 2870struct a8_erratum_fix
2871{
48229727
JB		 2872 bfd *input_bfd;
2873 asection *section;
2874 bfd_vma offset;
8d9d9490 2875 bfd_vma target_offset;
48229727
JB		 2876 unsigned long orig_insn;
2877 char *stub_name;
2878 enum elf32_arm_stub_type stub_type;
35fc36a8 2879 enum arm_st_branch_type branch_type;
48229727
JB		 2880};
2881
2882/* A table of relocs applied to branches which might trigger Cortex-A8
2883 erratum. */
2884
b38cadfb
NC		 2885struct a8_erratum_reloc
2886{
48229727
JB		 2887 bfd_vma from;
2888 bfd_vma destination;
92750f34
DJ		 2889 struct elf32_arm_link_hash_entry *hash;
2890 const char *sym_name;
48229727 2891 unsigned int r_type;
35fc36a8 2892 enum arm_st_branch_type branch_type;
48229727
JB		 2893 bfd_boolean non_a8_stub;
2894};
2895
ba93b8ac
DJ		 2896/* The size of the thread control block. */
2897#define TCB_SIZE 8
2898
34e77a92
RS		 2899/* ARM-specific information about a PLT entry, over and above the usual
2900 gotplt_union. */
b38cadfb
NC		 2901struct arm_plt_info
2902{
34e77a92
RS		 2903 /* We reference count Thumb references to a PLT entry separately,
2904 so that we can emit the Thumb trampoline only if needed. */
2905 bfd_signed_vma thumb_refcount;
2906
2907 /* Some references from Thumb code may be eliminated by BL->BLX
2908 conversion, so record them separately. */
2909 bfd_signed_vma maybe_thumb_refcount;
2910
2911 /* How many of the recorded PLT accesses were from non-call relocations.
2912 This information is useful when deciding whether anything takes the
2913 address of an STT_GNU_IFUNC PLT. A value of 0 means that all
2914 non-call references to the function should resolve directly to the
2915 real runtime target. */
2916 unsigned int noncall_refcount;
2917
2918 /* Since PLT entries have variable size if the Thumb prologue is
2919 used, we need to record the index into .got.plt instead of
2920 recomputing it from the PLT offset. */
2921 bfd_signed_vma got_offset;
2922};
2923
2924/* Information about an .iplt entry for a local STT_GNU_IFUNC symbol. */
b38cadfb
NC		 2925struct arm_local_iplt_info
2926{
34e77a92
RS		 2927 /* The information that is usually found in the generic ELF part of
2928 the hash table entry. */
2929 union gotplt_union root;
2930
2931 /* The information that is usually found in the ARM-specific part of
2932 the hash table entry. */
2933 struct arm_plt_info arm;
2934
2935 /* A list of all potential dynamic relocations against this symbol. */
2936 struct elf_dyn_relocs *dyn_relocs;
2937};
2938
0ffa91dd 2939struct elf_arm_obj_tdata
ba93b8ac
DJ		 2940{
2941 struct elf_obj_tdata root;
2942
2943 /* tls_type for each local got entry. */
2944 char *local_got_tls_type;
ee065d83 2945
0855e32b
NS		 2946 /* GOTPLT entries for TLS descriptors. */
2947 bfd_vma *local_tlsdesc_gotent;
2948
34e77a92
RS		 2949 /* Information for local symbols that need entries in .iplt. */
2950 struct arm_local_iplt_info **local_iplt;
2951
bf21ed78
MS		 2952 /* Zero to warn when linking objects with incompatible enum sizes. */
2953 int no_enum_size_warning;
a9dc9481
JM		 2954
2955 /* Zero to warn when linking objects with incompatible wchar_t sizes. */
2956 int no_wchar_size_warning;
ba93b8ac
DJ		 2957};
2958
0ffa91dd
NC		 2959#define elf_arm_tdata(bfd) \
2960 ((struct elf_arm_obj_tdata *) (bfd)->tdata.any)
ba93b8ac 2961
0ffa91dd
NC		 2962#define elf32_arm_local_got_tls_type(bfd) \
2963 (elf_arm_tdata (bfd)->local_got_tls_type)
2964
0855e32b
NS		 2965#define elf32_arm_local_tlsdesc_gotent(bfd) \
2966 (elf_arm_tdata (bfd)->local_tlsdesc_gotent)
2967
34e77a92
RS		 2968#define elf32_arm_local_iplt(bfd) \
2969 (elf_arm_tdata (bfd)->local_iplt)
2970
0ffa91dd
NC		 2971#define is_arm_elf(bfd) \
2972 (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
2973 && elf_tdata (bfd) != NULL \
4dfe6ac6 2974 && elf_object_id (bfd) == ARM_ELF_DATA)
ba93b8ac
DJ		 2975
2976static bfd_boolean
2977elf32_arm_mkobject (bfd *abfd)
2978{
0ffa91dd 2979 return bfd_elf_allocate_object (abfd, sizeof (struct elf_arm_obj_tdata),
4dfe6ac6 2980 ARM_ELF_DATA);
ba93b8ac
DJ		 2981}
2982
ba93b8ac
DJ		 2983#define elf32_arm_hash_entry(ent) ((struct elf32_arm_link_hash_entry *)(ent))
2984
ba96a88f 2985/* Arm ELF linker hash entry. */
252b5132 2986struct elf32_arm_link_hash_entry
b38cadfb
NC		 2987{
2988 struct elf_link_hash_entry root;
252b5132 2989
b38cadfb
NC		 2990 /* Track dynamic relocs copied for this symbol. */
2991 struct elf_dyn_relocs *dyn_relocs;
b7693d02 2992
b38cadfb
NC		 2993 /* ARM-specific PLT information. */
2994 struct arm_plt_info plt;
ba93b8ac
DJ		 2995
2996#define GOT_UNKNOWN 0
2997#define GOT_NORMAL 1
2998#define GOT_TLS_GD 2
2999#define GOT_TLS_IE 4
0855e32b
NS		 3000#define GOT_TLS_GDESC 8
3001#define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLS_GDESC))
b38cadfb 3002 unsigned int tls_type : 8;
34e77a92 3003
b38cadfb
NC		 3004 /* True if the symbol's PLT entry is in .iplt rather than .plt. */
3005 unsigned int is_iplt : 1;
34e77a92 3006
b38cadfb 3007 unsigned int unused : 23;
a4fd1a8e 3008
b38cadfb
NC		 3009 /* Offset of the GOTPLT entry reserved for the TLS descriptor,
3010 starting at the end of the jump table. */
3011 bfd_vma tlsdesc_got;
0855e32b 3012
b38cadfb
NC		 3013 /* The symbol marking the real symbol location for exported thumb
3014 symbols with Arm stubs. */
3015 struct elf_link_hash_entry *export_glue;
906e58ca 3016
b38cadfb 3017 /* A pointer to the most recently used stub hash entry against this
8029a119 3018 symbol. */
b38cadfb
NC		 3019 struct elf32_arm_stub_hash_entry *stub_cache;
3020};
252b5132 3021
252b5132 3022/* Traverse an arm ELF linker hash table. */
252b5132
RH		 3023#define elf32_arm_link_hash_traverse(table, func, info) \
3024 (elf_link_hash_traverse \
3025 (&(table)->root, \
b7693d02 3026 (bfd_boolean (*) (struct elf_link_hash_entry *, void *)) (func), \
252b5132
RH		 3027 (info)))
3028
3029/* Get the ARM elf linker hash table from a link_info structure. */
3030#define elf32_arm_hash_table(info) \
4dfe6ac6
NC		 3031 (elf_hash_table_id ((struct elf_link_hash_table *) ((info)->hash)) \
3032 == ARM_ELF_DATA ? ((struct elf32_arm_link_hash_table *) ((info)->hash)) : NULL)
252b5132 3033
906e58ca
NC		 3034#define arm_stub_hash_lookup(table, string, create, copy) \
3035 ((struct elf32_arm_stub_hash_entry *) \
3036 bfd_hash_lookup ((table), (string), (create), (copy)))
3037
21d799b5
NC		 3038/* Array to keep track of which stub sections have been created, and
3039 information on stub grouping. */
3040struct map_stub
3041{
3042 /* This is the section to which stubs in the group will be
3043 attached. */
3044 asection *link_sec;
3045 /* The stub section. */
3046 asection *stub_sec;
3047};
3048
0855e32b
NS		 3049#define elf32_arm_compute_jump_table_size(htab) \
3050 ((htab)->next_tls_desc_index * 4)
3051
9b485d32 3052/* ARM ELF linker hash table. */
252b5132 3053struct elf32_arm_link_hash_table
906e58ca
NC		 3054{
3055 /* The main hash table. */
3056 struct elf_link_hash_table root;
252b5132 3057
906e58ca
NC		 3058 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
3059 bfd_size_type thumb_glue_size;
252b5132 3060
906e58ca
NC		 3061 /* The size in bytes of the section containing the ARM-to-Thumb glue. */
3062 bfd_size_type arm_glue_size;
252b5132 3063
906e58ca
NC		 3064 /* The size in bytes of section containing the ARMv4 BX veneers. */
3065 bfd_size_type bx_glue_size;
845b51d6 3066
906e58ca
NC		 3067 /* Offsets of ARMv4 BX veneers. Bit1 set if present, and Bit0 set when
3068 veneer has been populated. */
3069 bfd_vma bx_glue_offset[15];
845b51d6 3070
906e58ca
NC		 3071 /* The size in bytes of the section containing glue for VFP11 erratum
3072 veneers. */
3073 bfd_size_type vfp11_erratum_glue_size;
c7b8f16e 3074
a504d23a
LA		 3075 /* The size in bytes of the section containing glue for STM32L4XX erratum
3076 veneers. */
3077 bfd_size_type stm32l4xx_erratum_glue_size;
3078
48229727
JB		 3079 /* A table of fix locations for Cortex-A8 Thumb-2 branch/TLB erratum. This
3080 holds Cortex-A8 erratum fix locations between elf32_arm_size_stubs() and
3081 elf32_arm_write_section(). */
3082 struct a8_erratum_fix *a8_erratum_fixes;
3083 unsigned int num_a8_erratum_fixes;
3084
906e58ca
NC		 3085 /* An arbitrary input BFD chosen to hold the glue sections. */
3086 bfd * bfd_of_glue_owner;
ba96a88f 3087
906e58ca
NC		 3088 /* Nonzero to output a BE8 image. */
3089 int byteswap_code;
e489d0ae 3090
906e58ca
NC		 3091 /* Zero if R_ARM_TARGET1 means R_ARM_ABS32.
3092 Nonzero if R_ARM_TARGET1 means R_ARM_REL32. */
3093 int target1_is_rel;
9c504268 3094
906e58ca
NC		 3095 /* The relocation to use for R_ARM_TARGET2 relocations. */
3096 int target2_reloc;
eb043451 3097
906e58ca
NC		 3098 /* 0 = Ignore R_ARM_V4BX.
3099 1 = Convert BX to MOV PC.
3100 2 = Generate v4 interworing stubs. */
3101 int fix_v4bx;
319850b4 3102
48229727
JB		 3103 /* Whether we should fix the Cortex-A8 Thumb-2 branch/TLB erratum. */
3104 int fix_cortex_a8;
3105
2de70689
MGD		 3106 /* Whether we should fix the ARM1176 BLX immediate issue. */
3107 int fix_arm1176;
3108
906e58ca
NC		 3109 /* Nonzero if the ARM/Thumb BLX instructions are available for use. */
3110 int use_blx;
33bfe774 3111
906e58ca
NC		 3112 /* What sort of code sequences we should look for which may trigger the
3113 VFP11 denorm erratum. */
3114 bfd_arm_vfp11_fix vfp11_fix;
c7b8f16e 3115
906e58ca
NC		 3116 /* Global counter for the number of fixes we have emitted. */
3117 int num_vfp11_fixes;
c7b8f16e 3118
a504d23a
LA		 3119 /* What sort of code sequences we should look for which may trigger the
3120 STM32L4XX erratum. */
3121 bfd_arm_stm32l4xx_fix stm32l4xx_fix;
3122
3123 /* Global counter for the number of fixes we have emitted. */
3124 int num_stm32l4xx_fixes;
3125
906e58ca
NC		 3126 /* Nonzero to force PIC branch veneers. */
3127 int pic_veneer;
27e55c4d 3128
906e58ca
NC		 3129 /* The number of bytes in the initial entry in the PLT. */
3130 bfd_size_type plt_header_size;
e5a52504 3131
906e58ca
NC		 3132 /* The number of bytes in the subsequent PLT etries. */
3133 bfd_size_type plt_entry_size;
e5a52504 3134
906e58ca
NC		 3135 /* True if the target system is VxWorks. */
3136 int vxworks_p;
00a97672 3137
906e58ca
NC		 3138 /* True if the target system is Symbian OS. */
3139 int symbian_p;
e5a52504 3140
b38cadfb
NC		 3141 /* True if the target system is Native Client. */
3142 int nacl_p;
3143
906e58ca
NC		 3144 /* True if the target uses REL relocations. */
3145 int use_rel;
4e7fd91e 3146
54ddd295
TP		 3147 /* Nonzero if import library must be a secure gateway import library
3148 as per ARMv8-M Security Extensions. */
3149 int cmse_implib;
3150
0955507f
TP		 3151 /* The import library whose symbols' address must remain stable in
3152 the import library generated. */
3153 bfd *in_implib_bfd;
3154
0855e32b
NS		 3155 /* The index of the next unused R_ARM_TLS_DESC slot in .rel.plt. */
3156 bfd_vma next_tls_desc_index;
3157
3158 /* How many R_ARM_TLS_DESC relocations were generated so far. */
3159 bfd_vma num_tls_desc;
3160
906e58ca 3161 /* Short-cuts to get to dynamic linker sections. */
906e58ca
NC		 3162 asection *sdynbss;
3163 asection *srelbss;
5e681ec4 3164
906e58ca
NC		 3165 /* The (unloaded but important) VxWorks .rela.plt.unloaded section. */
3166 asection *srelplt2;
00a97672 3167
0855e32b
NS		 3168 /* The offset into splt of the PLT entry for the TLS descriptor
3169 resolver. Special values are 0, if not necessary (or not found
3170 to be necessary yet), and -1 if needed but not determined
3171 yet. */
3172 bfd_vma dt_tlsdesc_plt;
3173
3174 /* The offset into sgot of the GOT entry used by the PLT entry
3175 above. */
b38cadfb 3176 bfd_vma dt_tlsdesc_got;
0855e32b
NS		 3177
3178 /* Offset in .plt section of tls_arm_trampoline. */
3179 bfd_vma tls_trampoline;
3180
906e58ca
NC		 3181 /* Data for R_ARM_TLS_LDM32 relocations. */
3182 union
3183 {
3184 bfd_signed_vma refcount;
3185 bfd_vma offset;
3186 } tls_ldm_got;
b7693d02 3187
87d72d41
AM		 3188 /* Small local sym cache. */
3189 struct sym_cache sym_cache;
906e58ca
NC		 3190
3191 /* For convenience in allocate_dynrelocs. */
3192 bfd * obfd;
3193
0855e32b
NS		 3194 /* The amount of space used by the reserved portion of the sgotplt
3195 section, plus whatever space is used by the jump slots. */
3196 bfd_vma sgotplt_jump_table_size;
3197
906e58ca
NC		 3198 /* The stub hash table. */
3199 struct bfd_hash_table stub_hash_table;
3200
3201 /* Linker stub bfd. */
3202 bfd *stub_bfd;
3203
3204 /* Linker call-backs. */
6bde4c52
TP		 3205 asection * (*add_stub_section) (const char *, asection *, asection *,
3206 unsigned int);
906e58ca
NC		 3207 void (*layout_sections_again) (void);
3208
3209 /* Array to keep track of which stub sections have been created, and
3210 information on stub grouping. */
21d799b5 3211 struct map_stub *stub_group;
906e58ca 3212
4ba2ef8f
TP		 3213 /* Input stub section holding secure gateway veneers. */
3214 asection *cmse_stub_sec;
3215
0955507f
TP		 3216 /* Offset in cmse_stub_sec where new SG veneers (not in input import library)
3217 start to be allocated. */
3218 bfd_vma new_cmse_stub_offset;
3219
fe33d2fa 3220 /* Number of elements in stub_group. */
7292b3ac 3221 unsigned int top_id;
fe33d2fa 3222
906e58ca
NC		 3223 /* Assorted information used by elf32_arm_size_stubs. */
3224 unsigned int bfd_count;
7292b3ac 3225 unsigned int top_index;
906e58ca
NC		 3226 asection **input_list;
3227};
252b5132 3228
a504d23a
LA		 3229static inline int
3230ctz (unsigned int mask)
3231{
3232#if GCC_VERSION >= 3004
3233 return __builtin_ctz (mask);
3234#else
3235 unsigned int i;
3236
3237 for (i = 0; i < 8 * sizeof (mask); i++)
3238 {
3239 if (mask & 0x1)
3240 break;
3241 mask = (mask >> 1);
3242 }
3243 return i;
3244#endif
3245}
3246
3247static inline int
3248popcount (unsigned int mask)
3249{
3250#if GCC_VERSION >= 3004
3251 return __builtin_popcount (mask);
3252#else
3253 unsigned int i, sum = 0;
3254
3255 for (i = 0; i < 8 * sizeof (mask); i++)
3256 {
3257 if (mask & 0x1)
3258 sum++;
3259 mask = (mask >> 1);
3260 }
3261 return sum;
3262#endif
3263}
3264
780a67af
NC		 3265/* Create an entry in an ARM ELF linker hash table. */
3266
3267static struct bfd_hash_entry *
57e8b36a 3268elf32_arm_link_hash_newfunc (struct bfd_hash_entry * entry,
99059e56
RM		 3269 struct bfd_hash_table * table,
3270 const char * string)
780a67af
NC		 3271{
3272 struct elf32_arm_link_hash_entry * ret =
3273 (struct elf32_arm_link_hash_entry *) entry;
3274
3275 /* Allocate the structure if it has not already been allocated by a
3276 subclass. */
906e58ca 3277 if (ret == NULL)
21d799b5 3278 ret = (struct elf32_arm_link_hash_entry *)
99059e56 3279 bfd_hash_allocate (table, sizeof (struct elf32_arm_link_hash_entry));
57e8b36a 3280 if (ret == NULL)
780a67af
NC		 3281 return (struct bfd_hash_entry *) ret;
3282
3283 /* Call the allocation method of the superclass. */
3284 ret = ((struct elf32_arm_link_hash_entry *)
3285 _bfd_elf_link_hash_newfunc ((struct bfd_hash_entry *) ret,
3286 table, string));
57e8b36a 3287 if (ret != NULL)
b7693d02 3288 {
0bdcacaf 3289 ret->dyn_relocs = NULL;
ba93b8ac 3290 ret->tls_type = GOT_UNKNOWN;
0855e32b 3291 ret->tlsdesc_got = (bfd_vma) -1;
34e77a92
RS		 3292 ret->plt.thumb_refcount = 0;
3293 ret->plt.maybe_thumb_refcount = 0;
3294 ret->plt.noncall_refcount = 0;
3295 ret->plt.got_offset = -1;
3296 ret->is_iplt = FALSE;
a4fd1a8e 3297 ret->export_glue = NULL;
906e58ca
NC		 3298
3299 ret->stub_cache = NULL;
b7693d02 3300 }
780a67af
NC		 3301
3302 return (struct bfd_hash_entry *) ret;
3303}
3304
34e77a92
RS		 3305/* Ensure that we have allocated bookkeeping structures for ABFD's local
3306 symbols. */
3307
3308static bfd_boolean
3309elf32_arm_allocate_local_sym_info (bfd *abfd)
3310{
3311 if (elf_local_got_refcounts (abfd) == NULL)
3312 {
3313 bfd_size_type num_syms;
3314 bfd_size_type size;
3315 char *data;
3316
3317 num_syms = elf_tdata (abfd)->symtab_hdr.sh_info;
3318 size = num_syms * (sizeof (bfd_signed_vma)
3319 + sizeof (struct arm_local_iplt_info *)
3320 + sizeof (bfd_vma)
3321 + sizeof (char));
3322 data = bfd_zalloc (abfd, size);
3323 if (data == NULL)
3324 return FALSE;
3325
3326 elf_local_got_refcounts (abfd) = (bfd_signed_vma *) data;
3327 data += num_syms * sizeof (bfd_signed_vma);
3328
3329 elf32_arm_local_iplt (abfd) = (struct arm_local_iplt_info **) data;
3330 data += num_syms * sizeof (struct arm_local_iplt_info *);
3331
3332 elf32_arm_local_tlsdesc_gotent (abfd) = (bfd_vma *) data;
3333 data += num_syms * sizeof (bfd_vma);
3334
3335 elf32_arm_local_got_tls_type (abfd) = data;
3336 }
3337 return TRUE;
3338}
3339
3340/* Return the .iplt information for local symbol R_SYMNDX, which belongs
3341 to input bfd ABFD. Create the information if it doesn't already exist.
3342 Return null if an allocation fails. */
3343
3344static struct arm_local_iplt_info *
3345elf32_arm_create_local_iplt (bfd *abfd, unsigned long r_symndx)
3346{
3347 struct arm_local_iplt_info **ptr;
3348
3349 if (!elf32_arm_allocate_local_sym_info (abfd))
3350 return NULL;
3351
3352 BFD_ASSERT (r_symndx < elf_tdata (abfd)->symtab_hdr.sh_info);
3353 ptr = &elf32_arm_local_iplt (abfd)[r_symndx];
3354 if (*ptr == NULL)
3355 *ptr = bfd_zalloc (abfd, sizeof (**ptr));
3356 return *ptr;
3357}
3358
3359/* Try to obtain PLT information for the symbol with index R_SYMNDX
3360 in ABFD's symbol table. If the symbol is global, H points to its
3361 hash table entry, otherwise H is null.
3362
3363 Return true if the symbol does have PLT information. When returning
3364 true, point *ROOT_PLT at the target-independent reference count/offset
3365 union and *ARM_PLT at the ARM-specific information. */
3366
3367static bfd_boolean
4ba2ef8f
TP		 3368elf32_arm_get_plt_info (bfd *abfd, struct elf32_arm_link_hash_table *globals,
3369 struct elf32_arm_link_hash_entry *h,
34e77a92
RS		 3370 unsigned long r_symndx, union gotplt_union **root_plt,
3371 struct arm_plt_info **arm_plt)
3372{
3373 struct arm_local_iplt_info *local_iplt;
3374
4ba2ef8f
TP		 3375 if (globals->root.splt == NULL && globals->root.iplt == NULL)
3376 return FALSE;
3377
34e77a92
RS		 3378 if (h != NULL)
3379 {
3380 *root_plt = &h->root.plt;
3381 *arm_plt = &h->plt;
3382 return TRUE;
3383 }
3384
3385 if (elf32_arm_local_iplt (abfd) == NULL)
3386 return FALSE;
3387
3388 local_iplt = elf32_arm_local_iplt (abfd)[r_symndx];
3389 if (local_iplt == NULL)
3390 return FALSE;
3391
3392 *root_plt = &local_iplt->root;
3393 *arm_plt = &local_iplt->arm;
3394 return TRUE;
3395}
3396
3397/* Return true if the PLT described by ARM_PLT requires a Thumb stub
3398 before it. */
3399
3400static bfd_boolean
3401elf32_arm_plt_needs_thumb_stub_p (struct bfd_link_info *info,
3402 struct arm_plt_info *arm_plt)
3403{
3404 struct elf32_arm_link_hash_table *htab;
3405
3406 htab = elf32_arm_hash_table (info);
3407 return (arm_plt->thumb_refcount != 0
3408 || (!htab->use_blx && arm_plt->maybe_thumb_refcount != 0));
3409}
3410
3411/* Return a pointer to the head of the dynamic reloc list that should
3412 be used for local symbol ISYM, which is symbol number R_SYMNDX in
3413 ABFD's symbol table. Return null if an error occurs. */
3414
3415static struct elf_dyn_relocs **
3416elf32_arm_get_local_dynreloc_list (bfd *abfd, unsigned long r_symndx,
3417 Elf_Internal_Sym *isym)
3418{
3419 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC)
3420 {
3421 struct arm_local_iplt_info *local_iplt;
3422
3423 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
3424 if (local_iplt == NULL)
3425 return NULL;
3426 return &local_iplt->dyn_relocs;
3427 }
3428 else
3429 {
3430 /* Track dynamic relocs needed for local syms too.
3431 We really need local syms available to do this
3432 easily. Oh well. */
3433 asection *s;
3434 void *vpp;
3435
3436 s = bfd_section_from_elf_index (abfd, isym->st_shndx);
3437 if (s == NULL)
3438 abort ();
3439
3440 vpp = &elf_section_data (s)->local_dynrel;
3441 return (struct elf_dyn_relocs **) vpp;
3442 }
3443}
3444
906e58ca
NC		 3445/* Initialize an entry in the stub hash table. */
3446
3447static struct bfd_hash_entry *
3448stub_hash_newfunc (struct bfd_hash_entry *entry,
3449 struct bfd_hash_table *table,
3450 const char *string)
3451{
3452 /* Allocate the structure if it has not already been allocated by a
3453 subclass. */
3454 if (entry == NULL)
3455 {
21d799b5 3456 entry = (struct bfd_hash_entry *)
99059e56 3457 bfd_hash_allocate (table, sizeof (struct elf32_arm_stub_hash_entry));
906e58ca
NC		 3458 if (entry == NULL)
3459 return entry;
3460 }
3461
3462 /* Call the allocation method of the superclass. */
3463 entry = bfd_hash_newfunc (entry, table, string);
3464 if (entry != NULL)
3465 {
3466 struct elf32_arm_stub_hash_entry *eh;
3467
3468 /* Initialize the local fields. */
3469 eh = (struct elf32_arm_stub_hash_entry *) entry;
3470 eh->stub_sec = NULL;
0955507f 3471 eh->stub_offset = (bfd_vma) -1;
8d9d9490 3472 eh->source_value = 0;
906e58ca
NC		 3473 eh->target_value = 0;
3474 eh->target_section = NULL;
cedfb179 3475 eh->orig_insn = 0;
906e58ca 3476 eh->stub_type = arm_stub_none;
461a49ca
DJ		 3477 eh->stub_size = 0;
3478 eh->stub_template = NULL;
0955507f 3479 eh->stub_template_size = -1;
906e58ca
NC		 3480 eh->h = NULL;
3481 eh->id_sec = NULL;
d8d2f433 3482 eh->output_name = NULL;
906e58ca
NC		 3483 }
3484
3485 return entry;
3486}
3487
00a97672 3488/* Create .got, .gotplt, and .rel(a).got sections in DYNOBJ, and set up
5e681ec4
PB		 3489 shortcuts to them in our hash table. */
3490
3491static bfd_boolean
57e8b36a 3492create_got_section (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3493{
3494 struct elf32_arm_link_hash_table *htab;
3495
e5a52504 3496 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3497 if (htab == NULL)
3498 return FALSE;
3499
e5a52504
MM		 3500 /* BPABI objects never have a GOT, or associated sections. */
3501 if (htab->symbian_p)
3502 return TRUE;
3503
5e681ec4
PB		 3504 if (! _bfd_elf_create_got_section (dynobj, info))
3505 return FALSE;
3506
5e681ec4
PB		 3507 return TRUE;
3508}
3509
34e77a92
RS		 3510/* Create the .iplt, .rel(a).iplt and .igot.plt sections. */
3511
3512static bfd_boolean
3513create_ifunc_sections (struct bfd_link_info *info)
3514{
3515 struct elf32_arm_link_hash_table *htab;
3516 const struct elf_backend_data *bed;
3517 bfd *dynobj;
3518 asection *s;
3519 flagword flags;
b38cadfb 3520
34e77a92
RS		 3521 htab = elf32_arm_hash_table (info);
3522 dynobj = htab->root.dynobj;
3523 bed = get_elf_backend_data (dynobj);
3524 flags = bed->dynamic_sec_flags;
3525
3526 if (htab->root.iplt == NULL)
3527 {
3d4d4302
AM		 3528 s = bfd_make_section_anyway_with_flags (dynobj, ".iplt",
3529 flags | SEC_READONLY | SEC_CODE);
34e77a92 3530 if (s == NULL
a0f49396 3531 || !bfd_set_section_alignment (dynobj, s, bed->plt_alignment))
34e77a92
RS		 3532 return FALSE;
3533 htab->root.iplt = s;
3534 }
3535
3536 if (htab->root.irelplt == NULL)
3537 {
3d4d4302
AM		 3538 s = bfd_make_section_anyway_with_flags (dynobj,
3539 RELOC_SECTION (htab, ".iplt"),
3540 flags | SEC_READONLY);
34e77a92 3541 if (s == NULL
a0f49396 3542 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
34e77a92
RS		 3543 return FALSE;
3544 htab->root.irelplt = s;
3545 }
3546
3547 if (htab->root.igotplt == NULL)
3548 {
3d4d4302 3549 s = bfd_make_section_anyway_with_flags (dynobj, ".igot.plt", flags);
34e77a92
RS		 3550 if (s == NULL
3551 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
3552 return FALSE;
3553 htab->root.igotplt = s;
3554 }
3555 return TRUE;
3556}
3557
eed94f8f
NC		 3558/* Determine if we're dealing with a Thumb only architecture. */
3559
3560static bfd_boolean
3561using_thumb_only (struct elf32_arm_link_hash_table *globals)
3562{
2fd158eb
TP		 3563 int arch;
3564 int profile = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3565 Tag_CPU_arch_profile);
eed94f8f 3566
2fd158eb
TP		 3567 if (profile)
3568 return profile == 'M';
eed94f8f 3569
2fd158eb 3570 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
eed94f8f 3571
60a019a0
TP		 3572 /* Force return logic to be reviewed for each new architecture. */
3573 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8
3574 || arch == TAG_CPU_ARCH_V8M_BASE
3575 || arch == TAG_CPU_ARCH_V8M_MAIN);
3576
2fd158eb
TP		 3577 if (arch == TAG_CPU_ARCH_V6_M
3578 || arch == TAG_CPU_ARCH_V6S_M
3579 || arch == TAG_CPU_ARCH_V7E_M
3580 || arch == TAG_CPU_ARCH_V8M_BASE
3581 || arch == TAG_CPU_ARCH_V8M_MAIN)
3582 return TRUE;
eed94f8f 3583
2fd158eb 3584 return FALSE;
eed94f8f
NC		 3585}
3586
3587/* Determine if we're dealing with a Thumb-2 object. */
3588
3589static bfd_boolean
3590using_thumb2 (struct elf32_arm_link_hash_table *globals)
3591{
60a019a0
TP		 3592 int arch;
3593 int thumb_isa = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3594 Tag_THUMB_ISA_use);
3595
3596 if (thumb_isa)
3597 return thumb_isa == 2;
3598
3599 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3600
3601 /* Force return logic to be reviewed for each new architecture. */
3602 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8
3603 || arch == TAG_CPU_ARCH_V8M_BASE
3604 || arch == TAG_CPU_ARCH_V8M_MAIN);
3605
3606 return (arch == TAG_CPU_ARCH_V6T2
3607 || arch == TAG_CPU_ARCH_V7
3608 || arch == TAG_CPU_ARCH_V7E_M
3609 || arch == TAG_CPU_ARCH_V8
3610 || arch == TAG_CPU_ARCH_V8M_MAIN);
eed94f8f
NC		 3611}
3612
5e866f5a
TP		 3613/* Determine whether Thumb-2 BL instruction is available. */
3614
3615static bfd_boolean
3616using_thumb2_bl (struct elf32_arm_link_hash_table *globals)
3617{
3618 int arch =
3619 bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3620
3621 /* Force return logic to be reviewed for each new architecture. */
3622 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8
3623 || arch == TAG_CPU_ARCH_V8M_BASE
3624 || arch == TAG_CPU_ARCH_V8M_MAIN);
3625
3626 /* Architecture was introduced after ARMv6T2 (eg. ARMv6-M). */
3627 return (arch == TAG_CPU_ARCH_V6T2
3628 || arch >= TAG_CPU_ARCH_V7);
3629}
3630
00a97672
RS		 3631/* Create .plt, .rel(a).plt, .got, .got.plt, .rel(a).got, .dynbss, and
3632 .rel(a).bss sections in DYNOBJ, and set up shortcuts to them in our
5e681ec4
PB		 3633 hash table. */
3634
3635static bfd_boolean
57e8b36a 3636elf32_arm_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3637{
3638 struct elf32_arm_link_hash_table *htab;
3639
3640 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3641 if (htab == NULL)
3642 return FALSE;
3643
362d30a1 3644 if (!htab->root.sgot && !create_got_section (dynobj, info))
5e681ec4
PB		 3645 return FALSE;
3646
3647 if (!_bfd_elf_create_dynamic_sections (dynobj, info))
3648 return FALSE;
3649
3d4d4302 3650 htab->sdynbss = bfd_get_linker_section (dynobj, ".dynbss");
0e1862bb 3651 if (!bfd_link_pic (info))
3d4d4302
AM		 3652 htab->srelbss = bfd_get_linker_section (dynobj,
3653 RELOC_SECTION (htab, ".bss"));
00a97672
RS		 3654
3655 if (htab->vxworks_p)
3656 {
3657 if (!elf_vxworks_create_dynamic_sections (dynobj, info, &htab->srelplt2))
3658 return FALSE;
3659
0e1862bb 3660 if (bfd_link_pic (info))
00a97672
RS		 3661 {
3662 htab->plt_header_size = 0;
3663 htab->plt_entry_size
3664 = 4 * ARRAY_SIZE (elf32_arm_vxworks_shared_plt_entry);
3665 }
3666 else
3667 {
3668 htab->plt_header_size
3669 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt0_entry);
3670 htab->plt_entry_size
3671 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt_entry);
3672 }
aebf9be7
NC		 3673
3674 if (elf_elfheader (dynobj))
3675 elf_elfheader (dynobj)->e_ident[EI_CLASS] = ELFCLASS32;
00a97672 3676 }
eed94f8f
NC		 3677 else
3678 {
3679 /* PR ld/16017
3680 Test for thumb only architectures. Note - we cannot just call
3681 using_thumb_only() as the attributes in the output bfd have not been
3682 initialised at this point, so instead we use the input bfd. */
3683 bfd * saved_obfd = htab->obfd;
3684
3685 htab->obfd = dynobj;
3686 if (using_thumb_only (htab))
3687 {
3688 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
3689 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
3690 }
3691 htab->obfd = saved_obfd;
3692 }
5e681ec4 3693
362d30a1
RS		 3694 if (!htab->root.splt
3695 || !htab->root.srelplt
e5a52504 3696 || !htab->sdynbss
0e1862bb 3697 || (!bfd_link_pic (info) && !htab->srelbss))
5e681ec4
PB		 3698 abort ();
3699
3700 return TRUE;
3701}
3702
906e58ca
NC		 3703/* Copy the extra info we tack onto an elf_link_hash_entry. */
3704
3705static void
3706elf32_arm_copy_indirect_symbol (struct bfd_link_info *info,
3707 struct elf_link_hash_entry *dir,
3708 struct elf_link_hash_entry *ind)
3709{
3710 struct elf32_arm_link_hash_entry *edir, *eind;
3711
3712 edir = (struct elf32_arm_link_hash_entry *) dir;
3713 eind = (struct elf32_arm_link_hash_entry *) ind;
3714
0bdcacaf 3715 if (eind->dyn_relocs != NULL)
906e58ca 3716 {
0bdcacaf 3717 if (edir->dyn_relocs != NULL)
906e58ca 3718 {
0bdcacaf
RS		 3719 struct elf_dyn_relocs **pp;
3720 struct elf_dyn_relocs *p;
906e58ca
NC		 3721
3722 /* Add reloc counts against the indirect sym to the direct sym
3723 list. Merge any entries against the same section. */
0bdcacaf 3724 for (pp = &eind->dyn_relocs; (p = *pp) != NULL; )
906e58ca 3725 {
0bdcacaf 3726 struct elf_dyn_relocs *q;
906e58ca 3727
0bdcacaf
RS		 3728 for (q = edir->dyn_relocs; q != NULL; q = q->next)
3729 if (q->sec == p->sec)
906e58ca
NC		 3730 {
3731 q->pc_count += p->pc_count;
3732 q->count += p->count;
3733 *pp = p->next;
3734 break;
3735 }
3736 if (q == NULL)
3737 pp = &p->next;
3738 }
0bdcacaf 3739 *pp = edir->dyn_relocs;
906e58ca
NC		 3740 }
3741
0bdcacaf
RS		 3742 edir->dyn_relocs = eind->dyn_relocs;
3743 eind->dyn_relocs = NULL;
906e58ca
NC		 3744 }
3745
3746 if (ind->root.type == bfd_link_hash_indirect)
3747 {
3748 /* Copy over PLT info. */
34e77a92
RS		 3749 edir->plt.thumb_refcount += eind->plt.thumb_refcount;
3750 eind->plt.thumb_refcount = 0;
3751 edir->plt.maybe_thumb_refcount += eind->plt.maybe_thumb_refcount;
3752 eind->plt.maybe_thumb_refcount = 0;
3753 edir->plt.noncall_refcount += eind->plt.noncall_refcount;
3754 eind->plt.noncall_refcount = 0;
3755
3756 /* We should only allocate a function to .iplt once the final
3757 symbol information is known. */
3758 BFD_ASSERT (!eind->is_iplt);
906e58ca
NC		 3759
3760 if (dir->got.refcount <= 0)
3761 {
3762 edir->tls_type = eind->tls_type;
3763 eind->tls_type = GOT_UNKNOWN;
3764 }
3765 }
3766
3767 _bfd_elf_link_hash_copy_indirect (info, dir, ind);
3768}
3769
68faa637
AM		 3770/* Destroy an ARM elf linker hash table. */
3771
3772static void
d495ab0d 3773elf32_arm_link_hash_table_free (bfd *obfd)
68faa637
AM		 3774{
3775 struct elf32_arm_link_hash_table *ret
d495ab0d 3776 = (struct elf32_arm_link_hash_table *) obfd->link.hash;
68faa637
AM		 3777
3778 bfd_hash_table_free (&ret->stub_hash_table);
d495ab0d 3779 _bfd_elf_link_hash_table_free (obfd);
68faa637
AM		 3780}
3781
906e58ca
NC		 3782/* Create an ARM elf linker hash table. */
3783
3784static struct bfd_link_hash_table *
3785elf32_arm_link_hash_table_create (bfd *abfd)
3786{
3787 struct elf32_arm_link_hash_table *ret;
3788 bfd_size_type amt = sizeof (struct elf32_arm_link_hash_table);
3789
7bf52ea2 3790 ret = (struct elf32_arm_link_hash_table *) bfd_zmalloc (amt);
906e58ca
NC		 3791 if (ret == NULL)
3792 return NULL;
3793
3794 if (!_bfd_elf_link_hash_table_init (& ret->root, abfd,
3795 elf32_arm_link_hash_newfunc,
4dfe6ac6
NC		 3796 sizeof (struct elf32_arm_link_hash_entry),
3797 ARM_ELF_DATA))
906e58ca
NC		 3798 {
3799 free (ret);
3800 return NULL;
3801 }
3802
906e58ca 3803 ret->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
a504d23a 3804 ret->stm32l4xx_fix = BFD_ARM_STM32L4XX_FIX_NONE;
906e58ca
NC		 3805#ifdef FOUR_WORD_PLT
3806 ret->plt_header_size = 16;
3807 ret->plt_entry_size = 16;
3808#else
3809 ret->plt_header_size = 20;
1db37fe6 3810 ret->plt_entry_size = elf32_arm_use_long_plt_entry ? 16 : 12;
906e58ca 3811#endif
906e58ca 3812 ret->use_rel = 1;
906e58ca 3813 ret->obfd = abfd;
906e58ca
NC		 3814
3815 if (!bfd_hash_table_init (&ret->stub_hash_table, stub_hash_newfunc,
3816 sizeof (struct elf32_arm_stub_hash_entry)))
3817 {
d495ab0d 3818 _bfd_elf_link_hash_table_free (abfd);
906e58ca
NC		 3819 return NULL;
3820 }
d495ab0d 3821 ret->root.root.hash_table_free = elf32_arm_link_hash_table_free;
906e58ca
NC		 3822
3823 return &ret->root.root;
3824}
3825
cd1dac3d
DG		 3826/* Determine what kind of NOPs are available. */
3827
3828static bfd_boolean
3829arch_has_arm_nop (struct elf32_arm_link_hash_table *globals)
3830{
3831 const int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3832 Tag_CPU_arch);
cd1dac3d 3833
60a019a0
TP		 3834 /* Force return logic to be reviewed for each new architecture. */
3835 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8
3836 || arch == TAG_CPU_ARCH_V8M_BASE
3837 || arch == TAG_CPU_ARCH_V8M_MAIN);
3838
3839 return (arch == TAG_CPU_ARCH_V6T2
3840 || arch == TAG_CPU_ARCH_V6K
3841 || arch == TAG_CPU_ARCH_V7
3842 || arch == TAG_CPU_ARCH_V8);
cd1dac3d
DG		 3843}
3844
f4ac8484
DJ		 3845static bfd_boolean
3846arm_stub_is_thumb (enum elf32_arm_stub_type stub_type)
3847{
3848 switch (stub_type)
3849 {
fea2b4d6 3850 case arm_stub_long_branch_thumb_only:
80c135e5 3851 case arm_stub_long_branch_thumb2_only:
d5a67c02 3852 case arm_stub_long_branch_thumb2_only_pure:
fea2b4d6
CL		 3853 case arm_stub_long_branch_v4t_thumb_arm:
3854 case arm_stub_short_branch_v4t_thumb_arm:
ebe24dd4 3855 case arm_stub_long_branch_v4t_thumb_arm_pic:
12352d3f 3856 case arm_stub_long_branch_v4t_thumb_tls_pic:
ebe24dd4 3857 case arm_stub_long_branch_thumb_only_pic:
4ba2ef8f 3858 case arm_stub_cmse_branch_thumb_only:
f4ac8484
DJ		 3859 return TRUE;
3860 case arm_stub_none:
3861 BFD_FAIL ();
3862 return FALSE;
3863 break;
3864 default:
3865 return FALSE;
3866 }
3867}
3868
906e58ca
NC		 3869/* Determine the type of stub needed, if any, for a call. */
3870
3871static enum elf32_arm_stub_type
3872arm_type_of_stub (struct bfd_link_info *info,
3873 asection *input_sec,
3874 const Elf_Internal_Rela *rel,
34e77a92 3875 unsigned char st_type,
35fc36a8 3876 enum arm_st_branch_type *actual_branch_type,
906e58ca 3877 struct elf32_arm_link_hash_entry *hash,
c820be07
NC		 3878 bfd_vma destination,
3879 asection *sym_sec,
3880 bfd *input_bfd,
3881 const char *name)
906e58ca
NC		 3882{
3883 bfd_vma location;
3884 bfd_signed_vma branch_offset;
3885 unsigned int r_type;
3886 struct elf32_arm_link_hash_table * globals;
5e866f5a 3887 bfd_boolean thumb2, thumb2_bl, thumb_only;
906e58ca 3888 enum elf32_arm_stub_type stub_type = arm_stub_none;
5fa9e92f 3889 int use_plt = 0;
35fc36a8 3890 enum arm_st_branch_type branch_type = *actual_branch_type;
34e77a92
RS		 3891 union gotplt_union *root_plt;
3892 struct arm_plt_info *arm_plt;
d5a67c02
AV		 3893 int arch;
3894 int thumb2_movw;
906e58ca 3895
35fc36a8 3896 if (branch_type == ST_BRANCH_LONG)
da5938a2
NC		 3897 return stub_type;
3898
906e58ca 3899 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3900 if (globals == NULL)
3901 return stub_type;
906e58ca
NC		 3902
3903 thumb_only = using_thumb_only (globals);
906e58ca 3904 thumb2 = using_thumb2 (globals);
5e866f5a 3905 thumb2_bl = using_thumb2_bl (globals);
906e58ca 3906
d5a67c02
AV		 3907 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3908
3909 /* True for architectures that implement the thumb2 movw instruction. */
3910 thumb2_movw = thumb2 || (arch == TAG_CPU_ARCH_V8M_BASE);
3911
906e58ca
NC		 3912 /* Determine where the call point is. */
3913 location = (input_sec->output_offset
3914 + input_sec->output_section->vma
3915 + rel->r_offset);
3916
906e58ca
NC		 3917 r_type = ELF32_R_TYPE (rel->r_info);
3918
39f21624
NC		 3919 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
3920 are considering a function call relocation. */
c5423981
TG		 3921 if (thumb_only && (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
3922 || r_type == R_ARM_THM_JUMP19)
39f21624
NC		 3923 && branch_type == ST_BRANCH_TO_ARM)
3924 branch_type = ST_BRANCH_TO_THUMB;
3925
34e77a92
RS		 3926 /* For TLS call relocs, it is the caller's responsibility to provide
3927 the address of the appropriate trampoline. */
3928 if (r_type != R_ARM_TLS_CALL
3929 && r_type != R_ARM_THM_TLS_CALL
4ba2ef8f
TP		 3930 && elf32_arm_get_plt_info (input_bfd, globals, hash,
3931 ELF32_R_SYM (rel->r_info), &root_plt,
3932 &arm_plt)
34e77a92 3933 && root_plt->offset != (bfd_vma) -1)
5fa9e92f 3934 {
34e77a92 3935 asection *splt;
fe33d2fa 3936
34e77a92
RS		 3937 if (hash == NULL || hash->is_iplt)
3938 splt = globals->root.iplt;
3939 else
3940 splt = globals->root.splt;
3941 if (splt != NULL)
b38cadfb 3942 {
34e77a92
RS		 3943 use_plt = 1;
3944
3945 /* Note when dealing with PLT entries: the main PLT stub is in
3946 ARM mode, so if the branch is in Thumb mode, another
3947 Thumb->ARM stub will be inserted later just before the ARM
3948 PLT stub. We don't take this extra distance into account
3949 here, because if a long branch stub is needed, we'll add a
3950 Thumb->Arm one and branch directly to the ARM PLT entry
3951 because it avoids spreading offset corrections in several
3952 places. */
3953
3954 destination = (splt->output_section->vma
3955 + splt->output_offset
3956 + root_plt->offset);
3957 st_type = STT_FUNC;
3958 branch_type = ST_BRANCH_TO_ARM;
3959 }
5fa9e92f 3960 }
34e77a92
RS		 3961 /* Calls to STT_GNU_IFUNC symbols should go through a PLT. */
3962 BFD_ASSERT (st_type != STT_GNU_IFUNC);
906e58ca 3963
fe33d2fa
CL		 3964 branch_offset = (bfd_signed_vma)(destination - location);
3965
0855e32b 3966 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
c5423981 3967 || r_type == R_ARM_THM_TLS_CALL || r_type == R_ARM_THM_JUMP19)
906e58ca 3968 {
5fa9e92f
CL		 3969 /* Handle cases where:
3970 - this call goes too far (different Thumb/Thumb2 max
99059e56 3971 distance)
155d87d7 3972 - it's a Thumb->Arm call and blx is not available, or it's a
99059e56
RM		 3973 Thumb->Arm branch (not bl). A stub is needed in this case,
3974 but only if this call is not through a PLT entry. Indeed,
3975 PLT stubs handle mode switching already.
5fa9e92f 3976 */
5e866f5a 3977 if ((!thumb2_bl
906e58ca
NC		 3978 && (branch_offset > THM_MAX_FWD_BRANCH_OFFSET
3979 || (branch_offset < THM_MAX_BWD_BRANCH_OFFSET)))
5e866f5a 3980 || (thumb2_bl
906e58ca
NC		 3981 && (branch_offset > THM2_MAX_FWD_BRANCH_OFFSET
3982 || (branch_offset < THM2_MAX_BWD_BRANCH_OFFSET)))
c5423981
TG		 3983 || (thumb2
3984 && (branch_offset > THM2_MAX_FWD_COND_BRANCH_OFFSET
3985 || (branch_offset < THM2_MAX_BWD_COND_BRANCH_OFFSET))
3986 && (r_type == R_ARM_THM_JUMP19))
35fc36a8 3987 || (branch_type == ST_BRANCH_TO_ARM
0855e32b
NS		 3988 && (((r_type == R_ARM_THM_CALL
3989 || r_type == R_ARM_THM_TLS_CALL) && !globals->use_blx)
c5423981
TG		 3990 || (r_type == R_ARM_THM_JUMP24)
3991 || (r_type == R_ARM_THM_JUMP19))
5fa9e92f 3992 && !use_plt))
906e58ca 3993 {
35fc36a8 3994 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 3995 {
3996 /* Thumb to thumb. */
3997 if (!thumb_only)
3998 {
d5a67c02
AV		 3999 if (input_sec->flags & SEC_ELF_PURECODE)
4000 (*_bfd_error_handler) (_("%B(%s): warning: long branch "
4001 " veneers used in section with "
4002 "SHF_ARM_PURECODE section "
4003 "attribute is only supported"
4004 " for M-profile targets that "
4005 "implement the movw "
4006 "instruction."));
4007
0e1862bb 4008 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4009 /* PIC stubs. */
155d87d7 4010 ? ((globals->use_blx
9553db3c 4011 && (r_type == R_ARM_THM_CALL))
155d87d7
CL		 4012 /* V5T and above. Stub starts with ARM code, so
4013 we must be able to switch mode before
4014 reaching it, which is only possible for 'bl'
4015 (ie R_ARM_THM_CALL relocation). */
cf3eccff 4016 ? arm_stub_long_branch_any_thumb_pic
ebe24dd4 4017 /* On V4T, use Thumb code only. */
d3626fb0 4018 : arm_stub_long_branch_v4t_thumb_thumb_pic)
c2b4a39d
CL		 4019
4020 /* non-PIC stubs. */
155d87d7 4021 : ((globals->use_blx
9553db3c 4022 && (r_type == R_ARM_THM_CALL))
c2b4a39d
CL		 4023 /* V5T and above. */
4024 ? arm_stub_long_branch_any_any
4025 /* V4T. */
d3626fb0 4026 : arm_stub_long_branch_v4t_thumb_thumb);
906e58ca
NC		 4027 }
4028 else
4029 {
d5a67c02
AV		 4030 if (thumb2_movw && (input_sec->flags & SEC_ELF_PURECODE))
4031 stub_type = arm_stub_long_branch_thumb2_only_pure;
4032 else
4033 {
4034 if (input_sec->flags & SEC_ELF_PURECODE)
4035 (*_bfd_error_handler) (_("%B(%s): warning: long branch "
4036 " veneers used in section with "
4037 "SHF_ARM_PURECODE section "
4038 "attribute is only supported"
4039 " for M-profile targets that "
4040 "implement the movw "
4041 "instruction."));
4042
4043 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
4044 /* PIC stub. */
4045 ? arm_stub_long_branch_thumb_only_pic
4046 /* non-PIC stub. */
4047 : (thumb2 ? arm_stub_long_branch_thumb2_only
4048 : arm_stub_long_branch_thumb_only);
4049 }
906e58ca
NC		 4050 }
4051 }
4052 else
4053 {
d5a67c02
AV		 4054 if (input_sec->flags & SEC_ELF_PURECODE)
4055 (*_bfd_error_handler) (_("%B(%s): warning: long branch "
4056 " veneers used in section with "
4057 "SHF_ARM_PURECODE section "
4058 "attribute is only supported"
4059 " for M-profile targets that "
4060 "implement the movw "
4061 "instruction."));
4062
906e58ca 4063 /* Thumb to arm. */
c820be07
NC		 4064 if (sym_sec != NULL
4065 && sym_sec->owner != NULL
4066 && !INTERWORK_FLAG (sym_sec->owner))
4067 {
4068 (*_bfd_error_handler)
4069 (_("%B(%s): warning: interworking not enabled.\n"
4070 " first occurrence: %B: Thumb call to ARM"),
4071 sym_sec->owner, input_bfd, name);
4072 }
4073
0855e32b 4074 stub_type =
0e1862bb 4075 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4076 /* PIC stubs. */
0855e32b 4077 ? (r_type == R_ARM_THM_TLS_CALL
6a631e86 4078 /* TLS PIC stubs. */
0855e32b
NS		 4079 ? (globals->use_blx ? arm_stub_long_branch_any_tls_pic
4080 : arm_stub_long_branch_v4t_thumb_tls_pic)
4081 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
4082 /* V5T PIC and above. */
4083 ? arm_stub_long_branch_any_arm_pic
4084 /* V4T PIC stub. */
4085 : arm_stub_long_branch_v4t_thumb_arm_pic))
c2b4a39d
CL		 4086
4087 /* non-PIC stubs. */
0855e32b 4088 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
c2b4a39d
CL		 4089 /* V5T and above. */
4090 ? arm_stub_long_branch_any_any
4091 /* V4T. */
4092 : arm_stub_long_branch_v4t_thumb_arm);
c820be07
NC		 4093
4094 /* Handle v4t short branches. */
fea2b4d6 4095 if ((stub_type == arm_stub_long_branch_v4t_thumb_arm)
c820be07
NC		 4096 && (branch_offset <= THM_MAX_FWD_BRANCH_OFFSET)
4097 && (branch_offset >= THM_MAX_BWD_BRANCH_OFFSET))
fea2b4d6 4098 stub_type = arm_stub_short_branch_v4t_thumb_arm;
906e58ca
NC		 4099 }
4100 }
4101 }
fe33d2fa
CL		 4102 else if (r_type == R_ARM_CALL
4103 || r_type == R_ARM_JUMP24
0855e32b
NS		 4104 || r_type == R_ARM_PLT32
4105 || r_type == R_ARM_TLS_CALL)
906e58ca 4106 {
d5a67c02
AV		 4107 if (input_sec->flags & SEC_ELF_PURECODE)
4108 (*_bfd_error_handler) (_("%B(%s): warning: long branch "
4109 " veneers used in section with "
4110 "SHF_ARM_PURECODE section "
4111 "attribute is only supported"
4112 " for M-profile targets that "
4113 "implement the movw "
4114 "instruction."));
35fc36a8 4115 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4116 {
4117 /* Arm to thumb. */
c820be07
NC		 4118
4119 if (sym_sec != NULL
4120 && sym_sec->owner != NULL
4121 && !INTERWORK_FLAG (sym_sec->owner))
4122 {
4123 (*_bfd_error_handler)
4124 (_("%B(%s): warning: interworking not enabled.\n"
c2b4a39d 4125 " first occurrence: %B: ARM call to Thumb"),
c820be07
NC		 4126 sym_sec->owner, input_bfd, name);
4127 }
4128
4129 /* We have an extra 2-bytes reach because of
4130 the mode change (bit 24 (H) of BLX encoding). */
4116d8d7
PB		 4131 if (branch_offset > (ARM_MAX_FWD_BRANCH_OFFSET + 2)
4132 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET)
0855e32b 4133 || (r_type == R_ARM_CALL && !globals->use_blx)
4116d8d7
PB		 4134 || (r_type == R_ARM_JUMP24)
4135 || (r_type == R_ARM_PLT32))
906e58ca 4136 {
0e1862bb 4137 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4138 /* PIC stubs. */
ebe24dd4
CL		 4139 ? ((globals->use_blx)
4140 /* V5T and above. */
4141 ? arm_stub_long_branch_any_thumb_pic
4142 /* V4T stub. */
4143 : arm_stub_long_branch_v4t_arm_thumb_pic)
4144
c2b4a39d
CL		 4145 /* non-PIC stubs. */
4146 : ((globals->use_blx)
4147 /* V5T and above. */
4148 ? arm_stub_long_branch_any_any
4149 /* V4T. */
4150 : arm_stub_long_branch_v4t_arm_thumb);
906e58ca
NC		 4151 }
4152 }
4153 else
4154 {
4155 /* Arm to arm. */
4156 if (branch_offset > ARM_MAX_FWD_BRANCH_OFFSET
4157 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET))
4158 {
0855e32b 4159 stub_type =
0e1862bb 4160 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4161 /* PIC stubs. */
0855e32b 4162 ? (r_type == R_ARM_TLS_CALL
6a631e86 4163 /* TLS PIC Stub. */
0855e32b 4164 ? arm_stub_long_branch_any_tls_pic
7a89b94e
NC		 4165 : (globals->nacl_p
4166 ? arm_stub_long_branch_arm_nacl_pic
4167 : arm_stub_long_branch_any_arm_pic))
c2b4a39d 4168 /* non-PIC stubs. */
7a89b94e
NC		 4169 : (globals->nacl_p
4170 ? arm_stub_long_branch_arm_nacl
4171 : arm_stub_long_branch_any_any);
906e58ca
NC		 4172 }
4173 }
4174 }
4175
fe33d2fa
CL		 4176 /* If a stub is needed, record the actual destination type. */
4177 if (stub_type != arm_stub_none)
35fc36a8 4178 *actual_branch_type = branch_type;
fe33d2fa 4179
906e58ca
NC		 4180 return stub_type;
4181}
4182
4183/* Build a name for an entry in the stub hash table. */
4184
4185static char *
4186elf32_arm_stub_name (const asection *input_section,
4187 const asection *sym_sec,
4188 const struct elf32_arm_link_hash_entry *hash,
fe33d2fa
CL		 4189 const Elf_Internal_Rela *rel,
4190 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4191{
4192 char *stub_name;
4193 bfd_size_type len;
4194
4195 if (hash)
4196 {
fe33d2fa 4197 len = 8 + 1 + strlen (hash->root.root.root.string) + 1 + 8 + 1 + 2 + 1;
21d799b5 4198 stub_name = (char *) bfd_malloc (len);
906e58ca 4199 if (stub_name != NULL)
fe33d2fa 4200 sprintf (stub_name, "%08x_%s+%x_%d",
906e58ca
NC		 4201 input_section->id & 0xffffffff,
4202 hash->root.root.root.string,
fe33d2fa
CL		 4203 (int) rel->r_addend & 0xffffffff,
4204 (int) stub_type);
906e58ca
NC		 4205 }
4206 else
4207 {
fe33d2fa 4208 len = 8 + 1 + 8 + 1 + 8 + 1 + 8 + 1 + 2 + 1;
21d799b5 4209 stub_name = (char *) bfd_malloc (len);
906e58ca 4210 if (stub_name != NULL)
fe33d2fa 4211 sprintf (stub_name, "%08x_%x:%x+%x_%d",
906e58ca
NC		 4212 input_section->id & 0xffffffff,
4213 sym_sec->id & 0xffffffff,
0855e32b
NS		 4214 ELF32_R_TYPE (rel->r_info) == R_ARM_TLS_CALL
4215 || ELF32_R_TYPE (rel->r_info) == R_ARM_THM_TLS_CALL
4216 ? 0 : (int) ELF32_R_SYM (rel->r_info) & 0xffffffff,
fe33d2fa
CL		 4217 (int) rel->r_addend & 0xffffffff,
4218 (int) stub_type);
906e58ca
NC		 4219 }
4220
4221 return stub_name;
4222}
4223
4224/* Look up an entry in the stub hash. Stub entries are cached because
4225 creating the stub name takes a bit of time. */
4226
4227static struct elf32_arm_stub_hash_entry *
4228elf32_arm_get_stub_entry (const asection *input_section,
4229 const asection *sym_sec,
4230 struct elf_link_hash_entry *hash,
4231 const Elf_Internal_Rela *rel,
fe33d2fa
CL		 4232 struct elf32_arm_link_hash_table *htab,
4233 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4234{
4235 struct elf32_arm_stub_hash_entry *stub_entry;
4236 struct elf32_arm_link_hash_entry *h = (struct elf32_arm_link_hash_entry *) hash;
4237 const asection *id_sec;
4238
4239 if ((input_section->flags & SEC_CODE) == 0)
4240 return NULL;
4241
4242 /* If this input section is part of a group of sections sharing one
4243 stub section, then use the id of the first section in the group.
4244 Stub names need to include a section id, as there may well be
4245 more than one stub used to reach say, printf, and we need to
4246 distinguish between them. */
4247 id_sec = htab->stub_group[input_section->id].link_sec;
4248
4249 if (h != NULL && h->stub_cache != NULL
4250 && h->stub_cache->h == h
fe33d2fa
CL		 4251 && h->stub_cache->id_sec == id_sec
4252 && h->stub_cache->stub_type == stub_type)
906e58ca
NC		 4253 {
4254 stub_entry = h->stub_cache;
4255 }
4256 else
4257 {
4258 char *stub_name;
4259
fe33d2fa 4260 stub_name = elf32_arm_stub_name (id_sec, sym_sec, h, rel, stub_type);
906e58ca
NC		 4261 if (stub_name == NULL)
4262 return NULL;
4263
4264 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table,
4265 stub_name, FALSE, FALSE);
4266 if (h != NULL)
4267 h->stub_cache = stub_entry;
4268
4269 free (stub_name);
4270 }
4271
4272 return stub_entry;
4273}
4274
daa4adae
TP		 4275/* Whether veneers of type STUB_TYPE require to be in a dedicated output
4276 section. */
4277
4278static bfd_boolean
4279arm_dedicated_stub_output_section_required (enum elf32_arm_stub_type stub_type)
4280{
4281 if (stub_type >= max_stub_type)
4282 abort (); /* Should be unreachable. */
4283
4ba2ef8f
TP		 4284 switch (stub_type)
4285 {
4286 case arm_stub_cmse_branch_thumb_only:
4287 return TRUE;
4288
4289 default:
4290 return FALSE;
4291 }
4292
4293 abort (); /* Should be unreachable. */
daa4adae
TP		 4294}
4295
4296/* Required alignment (as a power of 2) for the dedicated section holding
4297 veneers of type STUB_TYPE, or 0 if veneers of this type are interspersed
4298 with input sections. */
4299
4300static int
4301arm_dedicated_stub_output_section_required_alignment
4302 (enum elf32_arm_stub_type stub_type)
4303{
4304 if (stub_type >= max_stub_type)
4305 abort (); /* Should be unreachable. */
4306
4ba2ef8f
TP		 4307 switch (stub_type)
4308 {
4309 /* Vectors of Secure Gateway veneers must be aligned on 32byte
4310 boundary. */
4311 case arm_stub_cmse_branch_thumb_only:
4312 return 5;
4313
4314 default:
4315 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4316 return 0;
4317 }
4318
4319 abort (); /* Should be unreachable. */
daa4adae
TP		 4320}
4321
4322/* Name of the dedicated output section to put veneers of type STUB_TYPE, or
4323 NULL if veneers of this type are interspersed with input sections. */
4324
4325static const char *
4326arm_dedicated_stub_output_section_name (enum elf32_arm_stub_type stub_type)
4327{
4328 if (stub_type >= max_stub_type)
4329 abort (); /* Should be unreachable. */
4330
4ba2ef8f
TP		 4331 switch (stub_type)
4332 {
4333 case arm_stub_cmse_branch_thumb_only:
4334 return ".gnu.sgstubs";
4335
4336 default:
4337 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4338 return NULL;
4339 }
4340
4341 abort (); /* Should be unreachable. */
daa4adae
TP		 4342}
4343
4344/* If veneers of type STUB_TYPE should go in a dedicated output section,
4345 returns the address of the hash table field in HTAB holding a pointer to the
4346 corresponding input section. Otherwise, returns NULL. */
4347
4348static asection **
4ba2ef8f
TP		 4349arm_dedicated_stub_input_section_ptr (struct elf32_arm_link_hash_table *htab,
4350 enum elf32_arm_stub_type stub_type)
daa4adae
TP		 4351{
4352 if (stub_type >= max_stub_type)
4353 abort (); /* Should be unreachable. */
4354
4ba2ef8f
TP		 4355 switch (stub_type)
4356 {
4357 case arm_stub_cmse_branch_thumb_only:
4358 return &htab->cmse_stub_sec;
4359
4360 default:
4361 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4362 return NULL;
4363 }
4364
4365 abort (); /* Should be unreachable. */
daa4adae
TP		 4366}
4367
4368/* Find or create a stub section to contain a stub of type STUB_TYPE. SECTION
4369 is the section that branch into veneer and can be NULL if stub should go in
4370 a dedicated output section. Returns a pointer to the stub section, and the
4371 section to which the stub section will be attached (in *LINK_SEC_P).
48229727 4372 LINK_SEC_P may be NULL. */
906e58ca 4373
48229727
JB		 4374static asection *
4375elf32_arm_create_or_find_stub_sec (asection **link_sec_p, asection *section,
daa4adae
TP		 4376 struct elf32_arm_link_hash_table *htab,
4377 enum elf32_arm_stub_type stub_type)
906e58ca 4378{
daa4adae
TP		 4379 asection *link_sec, *out_sec, **stub_sec_p;
4380 const char *stub_sec_prefix;
4381 bfd_boolean dedicated_output_section =
4382 arm_dedicated_stub_output_section_required (stub_type);
4383 int align;
906e58ca 4384
daa4adae 4385 if (dedicated_output_section)
906e58ca 4386 {
daa4adae
TP		 4387 bfd *output_bfd = htab->obfd;
4388 const char *out_sec_name =
4389 arm_dedicated_stub_output_section_name (stub_type);
4390 link_sec = NULL;
4391 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
4392 stub_sec_prefix = out_sec_name;
4393 align = arm_dedicated_stub_output_section_required_alignment (stub_type);
4394 out_sec = bfd_get_section_by_name (output_bfd, out_sec_name);
4395 if (out_sec == NULL)
906e58ca 4396 {
daa4adae
TP		 4397 (*_bfd_error_handler) (_("No address assigned to the veneers output "
4398 "section %s"), out_sec_name);
4399 return NULL;
906e58ca 4400 }
daa4adae
TP		 4401 }
4402 else
4403 {
4404 link_sec = htab->stub_group[section->id].link_sec;
4405 BFD_ASSERT (link_sec != NULL);
4406 stub_sec_p = &htab->stub_group[section->id].stub_sec;
4407 if (*stub_sec_p == NULL)
4408 stub_sec_p = &htab->stub_group[link_sec->id].stub_sec;
4409 stub_sec_prefix = link_sec->name;
4410 out_sec = link_sec->output_section;
4411 align = htab->nacl_p ? 4 : 3;
906e58ca 4412 }
b38cadfb 4413
daa4adae
TP		 4414 if (*stub_sec_p == NULL)
4415 {
4416 size_t namelen;
4417 bfd_size_type len;
4418 char *s_name;
4419
4420 namelen = strlen (stub_sec_prefix);
4421 len = namelen + sizeof (STUB_SUFFIX);
4422 s_name = (char *) bfd_alloc (htab->stub_bfd, len);
4423 if (s_name == NULL)
4424 return NULL;
4425
4426 memcpy (s_name, stub_sec_prefix, namelen);
4427 memcpy (s_name + namelen, STUB_SUFFIX, sizeof (STUB_SUFFIX));
4428 *stub_sec_p = (*htab->add_stub_section) (s_name, out_sec, link_sec,
4429 align);
4430 if (*stub_sec_p == NULL)
4431 return NULL;
4432
4433 out_sec->flags |= SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_CODE
4434 | SEC_HAS_CONTENTS | SEC_RELOC | SEC_IN_MEMORY
4435 | SEC_KEEP;
4436 }
4437
4438 if (!dedicated_output_section)
4439 htab->stub_group[section->id].stub_sec = *stub_sec_p;
4440
48229727
JB		 4441 if (link_sec_p)
4442 *link_sec_p = link_sec;
b38cadfb 4443
daa4adae 4444 return *stub_sec_p;
48229727
JB		 4445}
4446
4447/* Add a new stub entry to the stub hash. Not all fields of the new
4448 stub entry are initialised. */
4449
4450static struct elf32_arm_stub_hash_entry *
daa4adae
TP		 4451elf32_arm_add_stub (const char *stub_name, asection *section,
4452 struct elf32_arm_link_hash_table *htab,
4453 enum elf32_arm_stub_type stub_type)
48229727
JB		 4454{
4455 asection *link_sec;
4456 asection *stub_sec;
4457 struct elf32_arm_stub_hash_entry *stub_entry;
4458
daa4adae
TP		 4459 stub_sec = elf32_arm_create_or_find_stub_sec (&link_sec, section, htab,
4460 stub_type);
48229727
JB		 4461 if (stub_sec == NULL)
4462 return NULL;
906e58ca
NC		 4463
4464 /* Enter this entry into the linker stub hash table. */
4465 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
4466 TRUE, FALSE);
4467 if (stub_entry == NULL)
4468 {
6bde4c52
TP		 4469 if (section == NULL)
4470 section = stub_sec;
906e58ca
NC		 4471 (*_bfd_error_handler) (_("%s: cannot create stub entry %s"),
4472 section->owner,
4473 stub_name);
4474 return NULL;
4475 }
4476
4477 stub_entry->stub_sec = stub_sec;
0955507f 4478 stub_entry->stub_offset = (bfd_vma) -1;
906e58ca
NC		 4479 stub_entry->id_sec = link_sec;
4480
906e58ca
NC		 4481 return stub_entry;
4482}
4483
4484/* Store an Arm insn into an output section not processed by
4485 elf32_arm_write_section. */
4486
4487static void
8029a119
NC		 4488put_arm_insn (struct elf32_arm_link_hash_table * htab,
4489 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4490{
4491 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4492 bfd_putl32 (val, ptr);
4493 else
4494 bfd_putb32 (val, ptr);
4495}
4496
4497/* Store a 16-bit Thumb insn into an output section not processed by
4498 elf32_arm_write_section. */
4499
4500static void
8029a119
NC		 4501put_thumb_insn (struct elf32_arm_link_hash_table * htab,
4502 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4503{
4504 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4505 bfd_putl16 (val, ptr);
4506 else
4507 bfd_putb16 (val, ptr);
4508}
4509
a504d23a
LA		 4510/* Store a Thumb2 insn into an output section not processed by
4511 elf32_arm_write_section. */
4512
4513static void
4514put_thumb2_insn (struct elf32_arm_link_hash_table * htab,
b98e6871 4515 bfd * output_bfd, bfd_vma val, bfd_byte * ptr)
a504d23a
LA		 4516{
4517 /* T2 instructions are 16-bit streamed. */
4518 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4519 {
4520 bfd_putl16 ((val >> 16) & 0xffff, ptr);
4521 bfd_putl16 ((val & 0xffff), ptr + 2);
4522 }
4523 else
4524 {
4525 bfd_putb16 ((val >> 16) & 0xffff, ptr);
4526 bfd_putb16 ((val & 0xffff), ptr + 2);
4527 }
4528}
4529
0855e32b
NS		 4530/* If it's possible to change R_TYPE to a more efficient access
4531 model, return the new reloc type. */
4532
4533static unsigned
b38cadfb 4534elf32_arm_tls_transition (struct bfd_link_info *info, int r_type,
0855e32b
NS		 4535 struct elf_link_hash_entry *h)
4536{
4537 int is_local = (h == NULL);
4538
0e1862bb
L		 4539 if (bfd_link_pic (info)
4540 || (h && h->root.type == bfd_link_hash_undefweak))
0855e32b
NS		 4541 return r_type;
4542
b38cadfb 4543 /* We do not support relaxations for Old TLS models. */
0855e32b
NS		 4544 switch (r_type)
4545 {
4546 case R_ARM_TLS_GOTDESC:
4547 case R_ARM_TLS_CALL:
4548 case R_ARM_THM_TLS_CALL:
4549 case R_ARM_TLS_DESCSEQ:
4550 case R_ARM_THM_TLS_DESCSEQ:
4551 return is_local ? R_ARM_TLS_LE32 : R_ARM_TLS_IE32;
4552 }
4553
4554 return r_type;
4555}
4556
48229727
JB		 4557static bfd_reloc_status_type elf32_arm_final_link_relocate
4558 (reloc_howto_type *, bfd *, bfd *, asection *, bfd_byte *,
4559 Elf_Internal_Rela *, bfd_vma, struct bfd_link_info *, asection *,
34e77a92
RS		 4560 const char *, unsigned char, enum arm_st_branch_type,
4561 struct elf_link_hash_entry *, bfd_boolean *, char **);
48229727 4562
4563a860
JB		 4563static unsigned int
4564arm_stub_required_alignment (enum elf32_arm_stub_type stub_type)
4565{
4566 switch (stub_type)
4567 {
4568 case arm_stub_a8_veneer_b_cond:
4569 case arm_stub_a8_veneer_b:
4570 case arm_stub_a8_veneer_bl:
4571 return 2;
4572
4573 case arm_stub_long_branch_any_any:
4574 case arm_stub_long_branch_v4t_arm_thumb:
4575 case arm_stub_long_branch_thumb_only:
80c135e5 4576 case arm_stub_long_branch_thumb2_only:
d5a67c02 4577 case arm_stub_long_branch_thumb2_only_pure:
4563a860
JB		 4578 case arm_stub_long_branch_v4t_thumb_thumb:
4579 case arm_stub_long_branch_v4t_thumb_arm:
4580 case arm_stub_short_branch_v4t_thumb_arm:
4581 case arm_stub_long_branch_any_arm_pic:
4582 case arm_stub_long_branch_any_thumb_pic:
4583 case arm_stub_long_branch_v4t_thumb_thumb_pic:
4584 case arm_stub_long_branch_v4t_arm_thumb_pic:
4585 case arm_stub_long_branch_v4t_thumb_arm_pic:
4586 case arm_stub_long_branch_thumb_only_pic:
0855e32b
NS		 4587 case arm_stub_long_branch_any_tls_pic:
4588 case arm_stub_long_branch_v4t_thumb_tls_pic:
4ba2ef8f 4589 case arm_stub_cmse_branch_thumb_only:
4563a860
JB		 4590 case arm_stub_a8_veneer_blx:
4591 return 4;
b38cadfb 4592
7a89b94e
NC		 4593 case arm_stub_long_branch_arm_nacl:
4594 case arm_stub_long_branch_arm_nacl_pic:
4595 return 16;
4596
4563a860
JB		 4597 default:
4598 abort (); /* Should be unreachable. */
4599 }
4600}
4601
4f4faa4d
TP		 4602/* Returns whether stubs of type STUB_TYPE take over the symbol they are
4603 veneering (TRUE) or have their own symbol (FALSE). */
4604
4605static bfd_boolean
4606arm_stub_sym_claimed (enum elf32_arm_stub_type stub_type)
4607{
4608 if (stub_type >= max_stub_type)
4609 abort (); /* Should be unreachable. */
4610
4ba2ef8f
TP		 4611 switch (stub_type)
4612 {
4613 case arm_stub_cmse_branch_thumb_only:
4614 return TRUE;
4615
4616 default:
4617 return FALSE;
4618 }
4619
4620 abort (); /* Should be unreachable. */
4f4faa4d
TP		 4621}
4622
d7c5bd02
TP		 4623/* Returns the padding needed for the dedicated section used stubs of type
4624 STUB_TYPE. */
4625
4626static int
4627arm_dedicated_stub_section_padding (enum elf32_arm_stub_type stub_type)
4628{
4629 if (stub_type >= max_stub_type)
4630 abort (); /* Should be unreachable. */
4631
4ba2ef8f
TP		 4632 switch (stub_type)
4633 {
4634 case arm_stub_cmse_branch_thumb_only:
4635 return 32;
4636
4637 default:
4638 return 0;
4639 }
4640
4641 abort (); /* Should be unreachable. */
d7c5bd02
TP		 4642}
4643
0955507f
TP		 4644/* If veneers of type STUB_TYPE should go in a dedicated output section,
4645 returns the address of the hash table field in HTAB holding the offset at
4646 which new veneers should be layed out in the stub section. */
4647
4648static bfd_vma*
4649arm_new_stubs_start_offset_ptr (struct elf32_arm_link_hash_table *htab,
4650 enum elf32_arm_stub_type stub_type)
4651{
4652 switch (stub_type)
4653 {
4654 case arm_stub_cmse_branch_thumb_only:
4655 return &htab->new_cmse_stub_offset;
4656
4657 default:
4658 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4659 return NULL;
4660 }
4661}
4662
906e58ca
NC		 4663static bfd_boolean
4664arm_build_one_stub (struct bfd_hash_entry *gen_entry,
4665 void * in_arg)
4666{
7a89b94e 4667#define MAXRELOCS 3
0955507f 4668 bfd_boolean removed_sg_veneer;
906e58ca 4669 struct elf32_arm_stub_hash_entry *stub_entry;
4dfe6ac6 4670 struct elf32_arm_link_hash_table *globals;
906e58ca 4671 struct bfd_link_info *info;
906e58ca
NC		 4672 asection *stub_sec;
4673 bfd *stub_bfd;
906e58ca
NC		 4674 bfd_byte *loc;
4675 bfd_vma sym_value;
4676 int template_size;
4677 int size;
d3ce72d0 4678 const insn_sequence *template_sequence;
906e58ca 4679 int i;
48229727
JB		 4680 int stub_reloc_idx[MAXRELOCS] = {-1, -1};
4681 int stub_reloc_offset[MAXRELOCS] = {0, 0};
4682 int nrelocs = 0;
0955507f 4683 int just_allocated = 0;
906e58ca
NC		 4684
4685 /* Massage our args to the form they really have. */
4686 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
4687 info = (struct bfd_link_info *) in_arg;
4688
4689 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 4690 if (globals == NULL)
4691 return FALSE;
906e58ca 4692
906e58ca
NC		 4693 stub_sec = stub_entry->stub_sec;
4694
4dfe6ac6 4695 if ((globals->fix_cortex_a8 < 0)
4563a860
JB		 4696 != (arm_stub_required_alignment (stub_entry->stub_type) == 2))
4697 /* We have to do less-strictly-aligned fixes last. */
eb7c4339 4698 return TRUE;
fe33d2fa 4699
0955507f
TP		 4700 /* Assign a slot at the end of section if none assigned yet. */
4701 if (stub_entry->stub_offset == (bfd_vma) -1)
4702 {
4703 stub_entry->stub_offset = stub_sec->size;
4704 just_allocated = 1;
4705 }
906e58ca
NC		 4706 loc = stub_sec->contents + stub_entry->stub_offset;
4707
4708 stub_bfd = stub_sec->owner;
4709
906e58ca
NC		 4710 /* This is the address of the stub destination. */
4711 sym_value = (stub_entry->target_value
4712 + stub_entry->target_section->output_offset
4713 + stub_entry->target_section->output_section->vma);
4714
d3ce72d0 4715 template_sequence = stub_entry->stub_template;
461a49ca 4716 template_size = stub_entry->stub_template_size;
906e58ca
NC		 4717
4718 size = 0;
461a49ca 4719 for (i = 0; i < template_size; i++)
906e58ca 4720 {
d3ce72d0 4721 switch (template_sequence[i].type)
461a49ca
DJ		 4722 {
4723 case THUMB16_TYPE:
48229727 4724 {
d3ce72d0
NC		 4725 bfd_vma data = (bfd_vma) template_sequence[i].data;
4726 if (template_sequence[i].reloc_addend != 0)
48229727 4727 {
99059e56
RM		 4728 /* We've borrowed the reloc_addend field to mean we should
4729 insert a condition code into this (Thumb-1 branch)
4730 instruction. See THUMB16_BCOND_INSN. */
4731 BFD_ASSERT ((data & 0xff00) == 0xd000);
4732 data |= ((stub_entry->orig_insn >> 22) & 0xf) << 8;
48229727 4733 }
fe33d2fa 4734 bfd_put_16 (stub_bfd, data, loc + size);
48229727
JB		 4735 size += 2;
4736 }
461a49ca 4737 break;
906e58ca 4738
48229727 4739 case THUMB32_TYPE:
fe33d2fa
CL		 4740 bfd_put_16 (stub_bfd,
4741 (template_sequence[i].data >> 16) & 0xffff,
4742 loc + size);
4743 bfd_put_16 (stub_bfd, template_sequence[i].data & 0xffff,
4744 loc + size + 2);
99059e56
RM		 4745 if (template_sequence[i].r_type != R_ARM_NONE)
4746 {
4747 stub_reloc_idx[nrelocs] = i;
4748 stub_reloc_offset[nrelocs++] = size;
4749 }
4750 size += 4;
4751 break;
48229727 4752
461a49ca 4753 case ARM_TYPE:
fe33d2fa
CL		 4754 bfd_put_32 (stub_bfd, template_sequence[i].data,
4755 loc + size);
461a49ca
DJ		 4756 /* Handle cases where the target is encoded within the
4757 instruction. */
d3ce72d0 4758 if (template_sequence[i].r_type == R_ARM_JUMP24)
461a49ca 4759 {
48229727
JB		 4760 stub_reloc_idx[nrelocs] = i;
4761 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 4762 }
4763 size += 4;
4764 break;
4765
4766 case DATA_TYPE:
d3ce72d0 4767 bfd_put_32 (stub_bfd, template_sequence[i].data, loc + size);
48229727
JB		 4768 stub_reloc_idx[nrelocs] = i;
4769 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 4770 size += 4;
4771 break;
4772
4773 default:
4774 BFD_FAIL ();
4775 return FALSE;
4776 }
906e58ca 4777 }
461a49ca 4778
0955507f
TP		 4779 if (just_allocated)
4780 stub_sec->size += size;
906e58ca 4781
461a49ca
DJ		 4782 /* Stub size has already been computed in arm_size_one_stub. Check
4783 consistency. */
4784 BFD_ASSERT (size == stub_entry->stub_size);
4785
906e58ca 4786 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
35fc36a8 4787 if (stub_entry->branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4788 sym_value |= 1;
4789
0955507f
TP		 4790 /* Assume non empty slots have at least one and at most MAXRELOCS entries
4791 to relocate in each stub. */
4792 removed_sg_veneer =
4793 (size == 0 && stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
4794 BFD_ASSERT (removed_sg_veneer || (nrelocs != 0 && nrelocs <= MAXRELOCS));
c820be07 4795
48229727 4796 for (i = 0; i < nrelocs; i++)
8d9d9490
TP		 4797 {
4798 Elf_Internal_Rela rel;
4799 bfd_boolean unresolved_reloc;
4800 char *error_message;
4801 bfd_vma points_to =
4802 sym_value + template_sequence[stub_reloc_idx[i]].reloc_addend;
4803
4804 rel.r_offset = stub_entry->stub_offset + stub_reloc_offset[i];
4805 rel.r_info = ELF32_R_INFO (0,
4806 template_sequence[stub_reloc_idx[i]].r_type);
4807 rel.r_addend = 0;
4808
4809 if (stub_entry->stub_type == arm_stub_a8_veneer_b_cond && i == 0)
4810 /* The first relocation in the elf32_arm_stub_a8_veneer_b_cond[]
4811 template should refer back to the instruction after the original
4812 branch. We use target_section as Cortex-A8 erratum workaround stubs
4813 are only generated when both source and target are in the same
4814 section. */
4815 points_to = stub_entry->target_section->output_section->vma
4816 + stub_entry->target_section->output_offset
4817 + stub_entry->source_value;
4818
4819 elf32_arm_final_link_relocate (elf32_arm_howto_from_type
4820 (template_sequence[stub_reloc_idx[i]].r_type),
4821 stub_bfd, info->output_bfd, stub_sec, stub_sec->contents, &rel,
4822 points_to, info, stub_entry->target_section, "", STT_FUNC,
4823 stub_entry->branch_type,
4824 (struct elf_link_hash_entry *) stub_entry->h, &unresolved_reloc,
4825 &error_message);
4826 }
906e58ca
NC		 4827
4828 return TRUE;
48229727 4829#undef MAXRELOCS
906e58ca
NC		 4830}
4831
48229727
JB		 4832/* Calculate the template, template size and instruction size for a stub.
4833 Return value is the instruction size. */
906e58ca 4834
48229727
JB		 4835static unsigned int
4836find_stub_size_and_template (enum elf32_arm_stub_type stub_type,
4837 const insn_sequence **stub_template,
4838 int *stub_template_size)
906e58ca 4839{
d3ce72d0 4840 const insn_sequence *template_sequence = NULL;
48229727
JB		 4841 int template_size = 0, i;
4842 unsigned int size;
906e58ca 4843
d3ce72d0 4844 template_sequence = stub_definitions[stub_type].template_sequence;
2a229407
AM		 4845 if (stub_template)
4846 *stub_template = template_sequence;
4847
48229727 4848 template_size = stub_definitions[stub_type].template_size;
2a229407
AM		 4849 if (stub_template_size)
4850 *stub_template_size = template_size;
906e58ca
NC		 4851
4852 size = 0;
461a49ca
DJ		 4853 for (i = 0; i < template_size; i++)
4854 {
d3ce72d0 4855 switch (template_sequence[i].type)
461a49ca
DJ		 4856 {
4857 case THUMB16_TYPE:
4858 size += 2;
4859 break;
4860
4861 case ARM_TYPE:
48229727 4862 case THUMB32_TYPE:
461a49ca
DJ		 4863 case DATA_TYPE:
4864 size += 4;
4865 break;
4866
4867 default:
4868 BFD_FAIL ();
2a229407 4869 return 0;
461a49ca
DJ		 4870 }
4871 }
4872
48229727
JB		 4873 return size;
4874}
4875
4876/* As above, but don't actually build the stub. Just bump offset so
4877 we know stub section sizes. */
4878
4879static bfd_boolean
4880arm_size_one_stub (struct bfd_hash_entry *gen_entry,
c7e2358a 4881 void *in_arg ATTRIBUTE_UNUSED)
48229727
JB		 4882{
4883 struct elf32_arm_stub_hash_entry *stub_entry;
d3ce72d0 4884 const insn_sequence *template_sequence;
48229727
JB		 4885 int template_size, size;
4886
4887 /* Massage our args to the form they really have. */
4888 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
48229727
JB		 4889
4890 BFD_ASSERT((stub_entry->stub_type > arm_stub_none)
4891 && stub_entry->stub_type < ARRAY_SIZE(stub_definitions));
4892
d3ce72d0 4893 size = find_stub_size_and_template (stub_entry->stub_type, &template_sequence,
48229727
JB		 4894 &template_size);
4895
0955507f
TP		 4896 /* Initialized to -1. Null size indicates an empty slot full of zeros. */
4897 if (stub_entry->stub_template_size)
4898 {
4899 stub_entry->stub_size = size;
4900 stub_entry->stub_template = template_sequence;
4901 stub_entry->stub_template_size = template_size;
4902 }
4903
4904 /* Already accounted for. */
4905 if (stub_entry->stub_offset != (bfd_vma) -1)
4906 return TRUE;
461a49ca 4907
906e58ca
NC		 4908 size = (size + 7) & ~7;
4909 stub_entry->stub_sec->size += size;
461a49ca 4910
906e58ca
NC		 4911 return TRUE;
4912}
4913
4914/* External entry points for sizing and building linker stubs. */
4915
4916/* Set up various things so that we can make a list of input sections
4917 for each output section included in the link. Returns -1 on error,
4918 0 when no stubs will be needed, and 1 on success. */
4919
4920int
4921elf32_arm_setup_section_lists (bfd *output_bfd,
4922 struct bfd_link_info *info)
4923{
4924 bfd *input_bfd;
4925 unsigned int bfd_count;
7292b3ac 4926 unsigned int top_id, top_index;
906e58ca
NC		 4927 asection *section;
4928 asection **input_list, **list;
4929 bfd_size_type amt;
4930 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
4931
4dfe6ac6
NC		 4932 if (htab == NULL)
4933 return 0;
906e58ca
NC		 4934 if (! is_elf_hash_table (htab))
4935 return 0;
4936
4937 /* Count the number of input BFDs and find the top input section id. */
4938 for (input_bfd = info->input_bfds, bfd_count = 0, top_id = 0;
4939 input_bfd != NULL;
c72f2fb2 4940 input_bfd = input_bfd->link.next)
906e58ca
NC		 4941 {
4942 bfd_count += 1;
4943 for (section = input_bfd->sections;
4944 section != NULL;
4945 section = section->next)
4946 {
4947 if (top_id < section->id)
4948 top_id = section->id;
4949 }
4950 }
4951 htab->bfd_count = bfd_count;
4952
4953 amt = sizeof (struct map_stub) * (top_id + 1);
21d799b5 4954 htab->stub_group = (struct map_stub *) bfd_zmalloc (amt);
906e58ca
NC		 4955 if (htab->stub_group == NULL)
4956 return -1;
fe33d2fa 4957 htab->top_id = top_id;
906e58ca
NC		 4958
4959 /* We can't use output_bfd->section_count here to find the top output
4960 section index as some sections may have been removed, and
4961 _bfd_strip_section_from_output doesn't renumber the indices. */
4962 for (section = output_bfd->sections, top_index = 0;
4963 section != NULL;
4964 section = section->next)
4965 {
4966 if (top_index < section->index)
4967 top_index = section->index;
4968 }
4969
4970 htab->top_index = top_index;
4971 amt = sizeof (asection *) * (top_index + 1);
21d799b5 4972 input_list = (asection **) bfd_malloc (amt);
906e58ca
NC		 4973 htab->input_list = input_list;
4974 if (input_list == NULL)
4975 return -1;
4976
4977 /* For sections we aren't interested in, mark their entries with a
4978 value we can check later. */
4979 list = input_list + top_index;
4980 do
4981 *list = bfd_abs_section_ptr;
4982 while (list-- != input_list);
4983
4984 for (section = output_bfd->sections;
4985 section != NULL;
4986 section = section->next)
4987 {
4988 if ((section->flags & SEC_CODE) != 0)
4989 input_list[section->index] = NULL;
4990 }
4991
4992 return 1;
4993}
4994
4995/* The linker repeatedly calls this function for each input section,
4996 in the order that input sections are linked into output sections.
4997 Build lists of input sections to determine groupings between which
4998 we may insert linker stubs. */
4999
5000void
5001elf32_arm_next_input_section (struct bfd_link_info *info,
5002 asection *isec)
5003{
5004 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5005
4dfe6ac6
NC		 5006 if (htab == NULL)
5007 return;
5008
906e58ca
NC		 5009 if (isec->output_section->index <= htab->top_index)
5010 {
5011 asection **list = htab->input_list + isec->output_section->index;
5012
a7470592 5013 if (*list != bfd_abs_section_ptr && (isec->flags & SEC_CODE) != 0)
906e58ca
NC		 5014 {
5015 /* Steal the link_sec pointer for our list. */
5016#define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
5017 /* This happens to make the list in reverse order,
07d72278 5018 which we reverse later. */
906e58ca
NC		 5019 PREV_SEC (isec) = *list;
5020 *list = isec;
5021 }
5022 }
5023}
5024
5025/* See whether we can group stub sections together. Grouping stub
5026 sections may result in fewer stubs. More importantly, we need to
07d72278 5027 put all .init* and .fini* stubs at the end of the .init or
906e58ca
NC		 5028 .fini output sections respectively, because glibc splits the
5029 _init and _fini functions into multiple parts. Putting a stub in
5030 the middle of a function is not a good idea. */
5031
5032static void
5033group_sections (struct elf32_arm_link_hash_table *htab,
5034 bfd_size_type stub_group_size,
07d72278 5035 bfd_boolean stubs_always_after_branch)
906e58ca 5036{
07d72278 5037 asection **list = htab->input_list;
906e58ca
NC		 5038
5039 do
5040 {
5041 asection *tail = *list;
07d72278 5042 asection *head;
906e58ca
NC		 5043
5044 if (tail == bfd_abs_section_ptr)
5045 continue;
5046
07d72278
DJ		 5047 /* Reverse the list: we must avoid placing stubs at the
5048 beginning of the section because the beginning of the text
5049 section may be required for an interrupt vector in bare metal
5050 code. */
5051#define NEXT_SEC PREV_SEC
e780aef2
CL		 5052 head = NULL;
5053 while (tail != NULL)
99059e56
RM		 5054 {
5055 /* Pop from tail. */
5056 asection *item = tail;
5057 tail = PREV_SEC (item);
e780aef2 5058
99059e56
RM		 5059 /* Push on head. */
5060 NEXT_SEC (item) = head;
5061 head = item;
5062 }
07d72278
DJ		 5063
5064 while (head != NULL)
906e58ca
NC		 5065 {
5066 asection *curr;
07d72278 5067 asection *next;
e780aef2
CL		 5068 bfd_vma stub_group_start = head->output_offset;
5069 bfd_vma end_of_next;
906e58ca 5070
07d72278 5071 curr = head;
e780aef2 5072 while (NEXT_SEC (curr) != NULL)
8cd931b7 5073 {
e780aef2
CL		 5074 next = NEXT_SEC (curr);
5075 end_of_next = next->output_offset + next->size;
5076 if (end_of_next - stub_group_start >= stub_group_size)
5077 /* End of NEXT is too far from start, so stop. */
8cd931b7 5078 break;
e780aef2
CL		 5079 /* Add NEXT to the group. */
5080 curr = next;
8cd931b7 5081 }
906e58ca 5082
07d72278 5083 /* OK, the size from the start to the start of CURR is less
906e58ca 5084 than stub_group_size and thus can be handled by one stub
07d72278 5085 section. (Or the head section is itself larger than
906e58ca
NC		 5086 stub_group_size, in which case we may be toast.)
5087 We should really be keeping track of the total size of
5088 stubs added here, as stubs contribute to the final output
7fb9f789 5089 section size. */
906e58ca
NC		 5090 do
5091 {
07d72278 5092 next = NEXT_SEC (head);
906e58ca 5093 /* Set up this stub group. */
07d72278 5094 htab->stub_group[head->id].link_sec = curr;
906e58ca 5095 }
07d72278 5096 while (head != curr && (head = next) != NULL);
906e58ca
NC		 5097
5098 /* But wait, there's more! Input sections up to stub_group_size
07d72278
DJ		 5099 bytes after the stub section can be handled by it too. */
5100 if (!stubs_always_after_branch)
906e58ca 5101 {
e780aef2
CL		 5102 stub_group_start = curr->output_offset + curr->size;
5103
8cd931b7 5104 while (next != NULL)
906e58ca 5105 {
e780aef2
CL		 5106 end_of_next = next->output_offset + next->size;
5107 if (end_of_next - stub_group_start >= stub_group_size)
5108 /* End of NEXT is too far from stubs, so stop. */
8cd931b7 5109 break;
e780aef2 5110 /* Add NEXT to the stub group. */
07d72278
DJ		 5111 head = next;
5112 next = NEXT_SEC (head);
5113 htab->stub_group[head->id].link_sec = curr;
906e58ca
NC		 5114 }
5115 }
07d72278 5116 head = next;
906e58ca
NC		 5117 }
5118 }
07d72278 5119 while (list++ != htab->input_list + htab->top_index);
906e58ca
NC		 5120
5121 free (htab->input_list);
5122#undef PREV_SEC
07d72278 5123#undef NEXT_SEC
906e58ca
NC		 5124}
5125
48229727
JB		 5126/* Comparison function for sorting/searching relocations relating to Cortex-A8
5127 erratum fix. */
5128
5129static int
5130a8_reloc_compare (const void *a, const void *b)
5131{
21d799b5
NC		 5132 const struct a8_erratum_reloc *ra = (const struct a8_erratum_reloc *) a;
5133 const struct a8_erratum_reloc *rb = (const struct a8_erratum_reloc *) b;
48229727
JB		 5134
5135 if (ra->from < rb->from)
5136 return -1;
5137 else if (ra->from > rb->from)
5138 return 1;
5139 else
5140 return 0;
5141}
5142
5143static struct elf_link_hash_entry *find_thumb_glue (struct bfd_link_info *,
5144 const char *, char **);
5145
5146/* Helper function to scan code for sequences which might trigger the Cortex-A8
5147 branch/TLB erratum. Fill in the table described by A8_FIXES_P,
81694485 5148 NUM_A8_FIXES_P, A8_FIX_TABLE_SIZE_P. Returns true if an error occurs, false
48229727
JB		 5149 otherwise. */
5150
81694485
NC		 5151static bfd_boolean
5152cortex_a8_erratum_scan (bfd *input_bfd,
5153 struct bfd_link_info *info,
48229727
JB		 5154 struct a8_erratum_fix **a8_fixes_p,
5155 unsigned int *num_a8_fixes_p,
5156 unsigned int *a8_fix_table_size_p,
5157 struct a8_erratum_reloc *a8_relocs,
eb7c4339
NS		 5158 unsigned int num_a8_relocs,
5159 unsigned prev_num_a8_fixes,
5160 bfd_boolean *stub_changed_p)
48229727
JB		 5161{
5162 asection *section;
5163 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5164 struct a8_erratum_fix *a8_fixes = *a8_fixes_p;
5165 unsigned int num_a8_fixes = *num_a8_fixes_p;
5166 unsigned int a8_fix_table_size = *a8_fix_table_size_p;
5167
4dfe6ac6
NC		 5168 if (htab == NULL)
5169 return FALSE;
5170
48229727
JB		 5171 for (section = input_bfd->sections;
5172 section != NULL;
5173 section = section->next)
5174 {
5175 bfd_byte *contents = NULL;
5176 struct _arm_elf_section_data *sec_data;
5177 unsigned int span;
5178 bfd_vma base_vma;
5179
5180 if (elf_section_type (section) != SHT_PROGBITS
99059e56
RM		 5181 || (elf_section_flags (section) & SHF_EXECINSTR) == 0
5182 || (section->flags & SEC_EXCLUDE) != 0
5183 || (section->sec_info_type == SEC_INFO_TYPE_JUST_SYMS)
5184 || (section->output_section == bfd_abs_section_ptr))
5185 continue;
48229727
JB		 5186
5187 base_vma = section->output_section->vma + section->output_offset;
5188
5189 if (elf_section_data (section)->this_hdr.contents != NULL)
99059e56 5190 contents = elf_section_data (section)->this_hdr.contents;
48229727 5191 else if (! bfd_malloc_and_get_section (input_bfd, section, &contents))
99059e56 5192 return TRUE;
48229727
JB		 5193
5194 sec_data = elf32_arm_section_data (section);
5195
5196 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 5197 {
5198 unsigned int span_start = sec_data->map[span].vma;
5199 unsigned int span_end = (span == sec_data->mapcount - 1)
5200 ? section->size : sec_data->map[span + 1].vma;
5201 unsigned int i;
5202 char span_type = sec_data->map[span].type;
5203 bfd_boolean last_was_32bit = FALSE, last_was_branch = FALSE;
5204
5205 if (span_type != 't')
5206 continue;
5207
5208 /* Span is entirely within a single 4KB region: skip scanning. */
5209 if (((base_vma + span_start) & ~0xfff)
48229727 5210 == ((base_vma + span_end) & ~0xfff))
99059e56
RM		 5211 continue;
5212
5213 /* Scan for 32-bit Thumb-2 branches which span two 4K regions, where:
5214
5215 * The opcode is BLX.W, BL.W, B.W, Bcc.W
5216 * The branch target is in the same 4KB region as the
5217 first half of the branch.
5218 * The instruction before the branch is a 32-bit
5219 length non-branch instruction. */
5220 for (i = span_start; i < span_end;)
5221 {
5222 unsigned int insn = bfd_getl16 (&contents[i]);
5223 bfd_boolean insn_32bit = FALSE, is_blx = FALSE, is_b = FALSE;
48229727
JB		 5224 bfd_boolean is_bl = FALSE, is_bcc = FALSE, is_32bit_branch;
5225
99059e56
RM		 5226 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
5227 insn_32bit = TRUE;
48229727
JB		 5228
5229 if (insn_32bit)
99059e56
RM		 5230 {
5231 /* Load the rest of the insn (in manual-friendly order). */
5232 insn = (insn << 16) | bfd_getl16 (&contents[i + 2]);
5233
5234 /* Encoding T4: B<c>.W. */
5235 is_b = (insn & 0xf800d000) == 0xf0009000;
5236 /* Encoding T1: BL<c>.W. */
5237 is_bl = (insn & 0xf800d000) == 0xf000d000;
5238 /* Encoding T2: BLX<c>.W. */
5239 is_blx = (insn & 0xf800d000) == 0xf000c000;
48229727
JB		 5240 /* Encoding T3: B<c>.W (not permitted in IT block). */
5241 is_bcc = (insn & 0xf800d000) == 0xf0008000
5242 && (insn & 0x07f00000) != 0x03800000;
5243 }
5244
5245 is_32bit_branch = is_b || is_bl || is_blx || is_bcc;
fe33d2fa 5246
99059e56 5247 if (((base_vma + i) & 0xfff) == 0xffe
81694485
NC		 5248 && insn_32bit
5249 && is_32bit_branch
5250 && last_was_32bit
5251 && ! last_was_branch)
99059e56
RM		 5252 {
5253 bfd_signed_vma offset = 0;
5254 bfd_boolean force_target_arm = FALSE;
48229727 5255 bfd_boolean force_target_thumb = FALSE;
99059e56
RM		 5256 bfd_vma target;
5257 enum elf32_arm_stub_type stub_type = arm_stub_none;
5258 struct a8_erratum_reloc key, *found;
5259 bfd_boolean use_plt = FALSE;
48229727 5260
99059e56
RM		 5261 key.from = base_vma + i;
5262 found = (struct a8_erratum_reloc *)
5263 bsearch (&key, a8_relocs, num_a8_relocs,
5264 sizeof (struct a8_erratum_reloc),
5265 &a8_reloc_compare);
48229727
JB		 5266
5267 if (found)
5268 {
5269 char *error_message = NULL;
5270 struct elf_link_hash_entry *entry;
5271
5272 /* We don't care about the error returned from this
99059e56 5273 function, only if there is glue or not. */
48229727
JB		 5274 entry = find_thumb_glue (info, found->sym_name,
5275 &error_message);
5276
5277 if (entry)
5278 found->non_a8_stub = TRUE;
5279
92750f34 5280 /* Keep a simpler condition, for the sake of clarity. */
362d30a1 5281 if (htab->root.splt != NULL && found->hash != NULL
92750f34
DJ		 5282 && found->hash->root.plt.offset != (bfd_vma) -1)
5283 use_plt = TRUE;
5284
5285 if (found->r_type == R_ARM_THM_CALL)
5286 {
35fc36a8
RS		 5287 if (found->branch_type == ST_BRANCH_TO_ARM
5288 || use_plt)
92750f34
DJ		 5289 force_target_arm = TRUE;
5290 else
5291 force_target_thumb = TRUE;
5292 }
48229727
JB		 5293 }
5294
99059e56 5295 /* Check if we have an offending branch instruction. */
48229727
JB		 5296
5297 if (found && found->non_a8_stub)
5298 /* We've already made a stub for this instruction, e.g.
5299 it's a long branch or a Thumb->ARM stub. Assume that
5300 stub will suffice to work around the A8 erratum (see
5301 setting of always_after_branch above). */
5302 ;
99059e56
RM		 5303 else if (is_bcc)
5304 {
5305 offset = (insn & 0x7ff) << 1;
5306 offset |= (insn & 0x3f0000) >> 4;
5307 offset |= (insn & 0x2000) ? 0x40000 : 0;
5308 offset |= (insn & 0x800) ? 0x80000 : 0;
5309 offset |= (insn & 0x4000000) ? 0x100000 : 0;
5310 if (offset & 0x100000)
5311 offset |= ~ ((bfd_signed_vma) 0xfffff);
5312 stub_type = arm_stub_a8_veneer_b_cond;
5313 }
5314 else if (is_b || is_bl || is_blx)
5315 {
5316 int s = (insn & 0x4000000) != 0;
5317 int j1 = (insn & 0x2000) != 0;
5318 int j2 = (insn & 0x800) != 0;
5319 int i1 = !(j1 ^ s);
5320 int i2 = !(j2 ^ s);
5321
5322 offset = (insn & 0x7ff) << 1;
5323 offset |= (insn & 0x3ff0000) >> 4;
5324 offset |= i2 << 22;
5325 offset |= i1 << 23;
5326 offset |= s << 24;
5327 if (offset & 0x1000000)
5328 offset |= ~ ((bfd_signed_vma) 0xffffff);
5329
5330 if (is_blx)
5331 offset &= ~ ((bfd_signed_vma) 3);
5332
5333 stub_type = is_blx ? arm_stub_a8_veneer_blx :
5334 is_bl ? arm_stub_a8_veneer_bl : arm_stub_a8_veneer_b;
5335 }
5336
5337 if (stub_type != arm_stub_none)
5338 {
5339 bfd_vma pc_for_insn = base_vma + i + 4;
48229727
JB		 5340
5341 /* The original instruction is a BL, but the target is
99059e56 5342 an ARM instruction. If we were not making a stub,
48229727
JB		 5343 the BL would have been converted to a BLX. Use the
5344 BLX stub instead in that case. */
5345 if (htab->use_blx && force_target_arm
5346 && stub_type == arm_stub_a8_veneer_bl)
5347 {
5348 stub_type = arm_stub_a8_veneer_blx;
5349 is_blx = TRUE;
5350 is_bl = FALSE;
5351 }
5352 /* Conversely, if the original instruction was
5353 BLX but the target is Thumb mode, use the BL
5354 stub. */
5355 else if (force_target_thumb
5356 && stub_type == arm_stub_a8_veneer_blx)
5357 {
5358 stub_type = arm_stub_a8_veneer_bl;
5359 is_blx = FALSE;
5360 is_bl = TRUE;
5361 }
5362
99059e56
RM		 5363 if (is_blx)
5364 pc_for_insn &= ~ ((bfd_vma) 3);
48229727 5365
99059e56
RM		 5366 /* If we found a relocation, use the proper destination,
5367 not the offset in the (unrelocated) instruction.
48229727
JB		 5368 Note this is always done if we switched the stub type
5369 above. */
99059e56
RM		 5370 if (found)
5371 offset =
81694485 5372 (bfd_signed_vma) (found->destination - pc_for_insn);
48229727 5373
99059e56
RM		 5374 /* If the stub will use a Thumb-mode branch to a
5375 PLT target, redirect it to the preceding Thumb
5376 entry point. */
5377 if (stub_type != arm_stub_a8_veneer_blx && use_plt)
5378 offset -= PLT_THUMB_STUB_SIZE;
7d24e6a6 5379
99059e56 5380 target = pc_for_insn + offset;
48229727 5381
99059e56
RM		 5382 /* The BLX stub is ARM-mode code. Adjust the offset to
5383 take the different PC value (+8 instead of +4) into
48229727 5384 account. */
99059e56
RM		 5385 if (stub_type == arm_stub_a8_veneer_blx)
5386 offset += 4;
5387
5388 if (((base_vma + i) & ~0xfff) == (target & ~0xfff))
5389 {
5390 char *stub_name = NULL;
5391
5392 if (num_a8_fixes == a8_fix_table_size)
5393 {
5394 a8_fix_table_size *= 2;
5395 a8_fixes = (struct a8_erratum_fix *)
5396 bfd_realloc (a8_fixes,
5397 sizeof (struct a8_erratum_fix)
5398 * a8_fix_table_size);
5399 }
48229727 5400
eb7c4339
NS		 5401 if (num_a8_fixes < prev_num_a8_fixes)
5402 {
5403 /* If we're doing a subsequent scan,
5404 check if we've found the same fix as
5405 before, and try and reuse the stub
5406 name. */
5407 stub_name = a8_fixes[num_a8_fixes].stub_name;
5408 if ((a8_fixes[num_a8_fixes].section != section)
5409 || (a8_fixes[num_a8_fixes].offset != i))
5410 {
5411 free (stub_name);
5412 stub_name = NULL;
5413 *stub_changed_p = TRUE;
5414 }
5415 }
5416
5417 if (!stub_name)
5418 {
21d799b5 5419 stub_name = (char *) bfd_malloc (8 + 1 + 8 + 1);
eb7c4339
NS		 5420 if (stub_name != NULL)
5421 sprintf (stub_name, "%x:%x", section->id, i);
5422 }
48229727 5423
99059e56
RM		 5424 a8_fixes[num_a8_fixes].input_bfd = input_bfd;
5425 a8_fixes[num_a8_fixes].section = section;
5426 a8_fixes[num_a8_fixes].offset = i;
8d9d9490
TP		 5427 a8_fixes[num_a8_fixes].target_offset =
5428 target - base_vma;
99059e56
RM		 5429 a8_fixes[num_a8_fixes].orig_insn = insn;
5430 a8_fixes[num_a8_fixes].stub_name = stub_name;
5431 a8_fixes[num_a8_fixes].stub_type = stub_type;
5432 a8_fixes[num_a8_fixes].branch_type =
35fc36a8 5433 is_blx ? ST_BRANCH_TO_ARM : ST_BRANCH_TO_THUMB;
48229727 5434
99059e56
RM		 5435 num_a8_fixes++;
5436 }
5437 }
5438 }
48229727 5439
99059e56
RM		 5440 i += insn_32bit ? 4 : 2;
5441 last_was_32bit = insn_32bit;
48229727 5442 last_was_branch = is_32bit_branch;
99059e56
RM		 5443 }
5444 }
48229727
JB		 5445
5446 if (elf_section_data (section)->this_hdr.contents == NULL)
99059e56 5447 free (contents);
48229727 5448 }
fe33d2fa 5449
48229727
JB		 5450 *a8_fixes_p = a8_fixes;
5451 *num_a8_fixes_p = num_a8_fixes;
5452 *a8_fix_table_size_p = a8_fix_table_size;
fe33d2fa 5453
81694485 5454 return FALSE;
48229727
JB		 5455}
5456
b715f643
TP		 5457/* Create or update a stub entry depending on whether the stub can already be
5458 found in HTAB. The stub is identified by:
5459 - its type STUB_TYPE
5460 - its source branch (note that several can share the same stub) whose
5461 section and relocation (if any) are given by SECTION and IRELA
5462 respectively
5463 - its target symbol whose input section, hash, name, value and branch type
5464 are given in SYM_SEC, HASH, SYM_NAME, SYM_VALUE and BRANCH_TYPE
5465 respectively
5466
5467 If found, the value of the stub's target symbol is updated from SYM_VALUE
5468 and *NEW_STUB is set to FALSE. Otherwise, *NEW_STUB is set to
5469 TRUE and the stub entry is initialized.
5470
0955507f
TP		 5471 Returns the stub that was created or updated, or NULL if an error
5472 occurred. */
b715f643 5473
0955507f 5474static struct elf32_arm_stub_hash_entry *
b715f643
TP		 5475elf32_arm_create_stub (struct elf32_arm_link_hash_table *htab,
5476 enum elf32_arm_stub_type stub_type, asection *section,
5477 Elf_Internal_Rela *irela, asection *sym_sec,
5478 struct elf32_arm_link_hash_entry *hash, char *sym_name,
5479 bfd_vma sym_value, enum arm_st_branch_type branch_type,
5480 bfd_boolean *new_stub)
5481{
5482 const asection *id_sec;
5483 char *stub_name;
5484 struct elf32_arm_stub_hash_entry *stub_entry;
5485 unsigned int r_type;
4f4faa4d 5486 bfd_boolean sym_claimed = arm_stub_sym_claimed (stub_type);
b715f643
TP		 5487
5488 BFD_ASSERT (stub_type != arm_stub_none);
5489 *new_stub = FALSE;
5490
4f4faa4d
TP		 5491 if (sym_claimed)
5492 stub_name = sym_name;
5493 else
5494 {
5495 BFD_ASSERT (irela);
5496 BFD_ASSERT (section);
b715f643 5497
4f4faa4d
TP		 5498 /* Support for grouping stub sections. */
5499 id_sec = htab->stub_group[section->id].link_sec;
b715f643 5500
4f4faa4d
TP		 5501 /* Get the name of this stub. */
5502 stub_name = elf32_arm_stub_name (id_sec, sym_sec, hash, irela,
5503 stub_type);
5504 if (!stub_name)
0955507f 5505 return NULL;
4f4faa4d 5506 }
b715f643
TP		 5507
5508 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name, FALSE,
5509 FALSE);
5510 /* The proper stub has already been created, just update its value. */
5511 if (stub_entry != NULL)
5512 {
4f4faa4d
TP		 5513 if (!sym_claimed)
5514 free (stub_name);
b715f643 5515 stub_entry->target_value = sym_value;
0955507f 5516 return stub_entry;
b715f643
TP		 5517 }
5518
daa4adae 5519 stub_entry = elf32_arm_add_stub (stub_name, section, htab, stub_type);
b715f643
TP		 5520 if (stub_entry == NULL)
5521 {
4f4faa4d
TP		 5522 if (!sym_claimed)
5523 free (stub_name);
0955507f 5524 return NULL;
b715f643
TP		 5525 }
5526
5527 stub_entry->target_value = sym_value;
5528 stub_entry->target_section = sym_sec;
5529 stub_entry->stub_type = stub_type;
5530 stub_entry->h = hash;
5531 stub_entry->branch_type = branch_type;
5532
4f4faa4d
TP		 5533 if (sym_claimed)
5534 stub_entry->output_name = sym_name;
5535 else
b715f643 5536 {
4f4faa4d
TP		 5537 if (sym_name == NULL)
5538 sym_name = "unnamed";
5539 stub_entry->output_name = (char *)
5540 bfd_alloc (htab->stub_bfd, sizeof (THUMB2ARM_GLUE_ENTRY_NAME)
5541 + strlen (sym_name));
5542 if (stub_entry->output_name == NULL)
5543 {
5544 free (stub_name);
0955507f 5545 return NULL;
4f4faa4d 5546 }
b715f643 5547
4f4faa4d
TP		 5548 /* For historical reasons, use the existing names for ARM-to-Thumb and
5549 Thumb-to-ARM stubs. */
5550 r_type = ELF32_R_TYPE (irela->r_info);
5551 if ((r_type == (unsigned int) R_ARM_THM_CALL
5552 || r_type == (unsigned int) R_ARM_THM_JUMP24
5553 || r_type == (unsigned int) R_ARM_THM_JUMP19)
5554 && branch_type == ST_BRANCH_TO_ARM)
5555 sprintf (stub_entry->output_name, THUMB2ARM_GLUE_ENTRY_NAME, sym_name);
5556 else if ((r_type == (unsigned int) R_ARM_CALL
5557 || r_type == (unsigned int) R_ARM_JUMP24)
5558 && branch_type == ST_BRANCH_TO_THUMB)
5559 sprintf (stub_entry->output_name, ARM2THUMB_GLUE_ENTRY_NAME, sym_name);
5560 else
5561 sprintf (stub_entry->output_name, STUB_ENTRY_NAME, sym_name);
5562 }
b715f643
TP		 5563
5564 *new_stub = TRUE;
0955507f 5565 return stub_entry;
b715f643
TP		 5566}
5567
4ba2ef8f
TP		 5568/* Scan symbols in INPUT_BFD to identify secure entry functions needing a
5569 gateway veneer to transition from non secure to secure state and create them
5570 accordingly.
5571
5572 "ARMv8-M Security Extensions: Requirements on Development Tools" document
5573 defines the conditions that govern Secure Gateway veneer creation for a
5574 given symbol <SYM> as follows:
5575 - it has function type
5576 - it has non local binding
5577 - a symbol named __acle_se_<SYM> (called special symbol) exists with the
5578 same type, binding and value as <SYM> (called normal symbol).
5579 An entry function can handle secure state transition itself in which case
5580 its special symbol would have a different value from the normal symbol.
5581
5582 OUT_ATTR gives the output attributes, SYM_HASHES the symbol index to hash
5583 entry mapping while HTAB gives the name to hash entry mapping.
0955507f
TP		 5584 *CMSE_STUB_CREATED is increased by the number of secure gateway veneer
5585 created.
4ba2ef8f 5586
0955507f 5587 The return value gives whether a stub failed to be allocated. */
4ba2ef8f
TP		 5588
5589static bfd_boolean
5590cmse_scan (bfd *input_bfd, struct elf32_arm_link_hash_table *htab,
5591 obj_attribute *out_attr, struct elf_link_hash_entry **sym_hashes,
0955507f 5592 int *cmse_stub_created)
4ba2ef8f
TP		 5593{
5594 const struct elf_backend_data *bed;
5595 Elf_Internal_Shdr *symtab_hdr;
5596 unsigned i, j, sym_count, ext_start;
5597 Elf_Internal_Sym *cmse_sym, *local_syms;
5598 struct elf32_arm_link_hash_entry *hash, *cmse_hash = NULL;
5599 enum arm_st_branch_type branch_type;
5600 char *sym_name, *lsym_name;
5601 bfd_vma sym_value;
5602 asection *section;
0955507f
TP		 5603 struct elf32_arm_stub_hash_entry *stub_entry;
5604 bfd_boolean is_v8m, new_stub, cmse_invalid, ret = TRUE;
4ba2ef8f
TP		 5605
5606 bed = get_elf_backend_data (input_bfd);
5607 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
5608 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
5609 ext_start = symtab_hdr->sh_info;
5610 is_v8m = (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
5611 && out_attr[Tag_CPU_arch_profile].i == 'M');
5612
5613 local_syms = (Elf_Internal_Sym *) symtab_hdr->contents;
5614 if (local_syms == NULL)
5615 local_syms = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
5616 symtab_hdr->sh_info, 0, NULL, NULL,
5617 NULL);
5618 if (symtab_hdr->sh_info && local_syms == NULL)
5619 return FALSE;
5620
5621 /* Scan symbols. */
5622 for (i = 0; i < sym_count; i++)
5623 {
5624 cmse_invalid = FALSE;
5625
5626 if (i < ext_start)
5627 {
5628 cmse_sym = &local_syms[i];
5629 /* Not a special symbol. */
5630 if (!ARM_GET_SYM_CMSE_SPCL (cmse_sym->st_target_internal))
5631 continue;
5632 sym_name = bfd_elf_string_from_elf_section (input_bfd,
5633 symtab_hdr->sh_link,
5634 cmse_sym->st_name);
5635 /* Special symbol with local binding. */
5636 cmse_invalid = TRUE;
5637 }
5638 else
5639 {
5640 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
5641 sym_name = (char *) cmse_hash->root.root.root.string;
5642
5643 /* Not a special symbol. */
5644 if (!ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
5645 continue;
5646
5647 /* Special symbol has incorrect binding or type. */
5648 if ((cmse_hash->root.root.type != bfd_link_hash_defined
5649 && cmse_hash->root.root.type != bfd_link_hash_defweak)
5650 || cmse_hash->root.type != STT_FUNC)
5651 cmse_invalid = TRUE;
5652 }
5653
5654 if (!is_v8m)
5655 {
5656 (*_bfd_error_handler) (_("%B: Special symbol `%s' only allowed for "
5657 "ARMv8-M architecture or later."),
5658 input_bfd, sym_name);
5659 is_v8m = TRUE; /* Avoid multiple warning. */
5660 ret = FALSE;
5661 }
5662
5663 if (cmse_invalid)
5664 {
5665 (*_bfd_error_handler) (_("%B: invalid special symbol `%s'."),
5666 input_bfd, sym_name);
5667 (*_bfd_error_handler) (_("It must be a global or weak function "
5668 "symbol."));
5669 ret = FALSE;
5670 if (i < ext_start)
5671 continue;
5672 }
5673
5674 sym_name += strlen (CMSE_PREFIX);
5675 hash = (struct elf32_arm_link_hash_entry *)
5676 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
5677
5678 /* No associated normal symbol or it is neither global nor weak. */
5679 if (!hash
5680 || (hash->root.root.type != bfd_link_hash_defined
5681 && hash->root.root.type != bfd_link_hash_defweak)
5682 || hash->root.type != STT_FUNC)
5683 {
5684 /* Initialize here to avoid warning about use of possibly
5685 uninitialized variable. */
5686 j = 0;
5687
5688 if (!hash)
5689 {
5690 /* Searching for a normal symbol with local binding. */
5691 for (; j < ext_start; j++)
5692 {
5693 lsym_name =
5694 bfd_elf_string_from_elf_section (input_bfd,
5695 symtab_hdr->sh_link,
5696 local_syms[j].st_name);
5697 if (!strcmp (sym_name, lsym_name))
5698 break;
5699 }
5700 }
5701
5702 if (hash || j < ext_start)
5703 {
5704 (*_bfd_error_handler)
5705 (_("%B: invalid standard symbol `%s'."), input_bfd, sym_name);
5706 (*_bfd_error_handler)
5707 (_("It must be a global or weak function symbol."));
5708 }
5709 else
5710 (*_bfd_error_handler)
5711 (_("%B: absent standard symbol `%s'."), input_bfd, sym_name);
5712 ret = FALSE;
5713 if (!hash)
5714 continue;
5715 }
5716
5717 sym_value = hash->root.root.u.def.value;
5718 section = hash->root.root.u.def.section;
5719
5720 if (cmse_hash->root.root.u.def.section != section)
5721 {
5722 (*_bfd_error_handler)
5723 (_("%B: `%s' and its special symbol are in different sections."),
5724 input_bfd, sym_name);
5725 ret = FALSE;
5726 }
5727 if (cmse_hash->root.root.u.def.value != sym_value)
5728 continue; /* Ignore: could be an entry function starting with SG. */
5729
5730 /* If this section is a link-once section that will be discarded, then
5731 don't create any stubs. */
5732 if (section->output_section == NULL)
5733 {
5734 (*_bfd_error_handler)
5735 (_("%B: entry function `%s' not output."), input_bfd, sym_name);
5736 continue;
5737 }
5738
5739 if (hash->root.size == 0)
5740 {
5741 (*_bfd_error_handler)
5742 (_("%B: entry function `%s' is empty."), input_bfd, sym_name);
5743 ret = FALSE;
5744 }
5745
5746 if (!ret)
5747 continue;
5748 branch_type = ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
0955507f 5749 stub_entry
4ba2ef8f
TP		 5750 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
5751 NULL, NULL, section, hash, sym_name,
5752 sym_value, branch_type, &new_stub);
5753
0955507f 5754 if (stub_entry == NULL)
4ba2ef8f
TP		 5755 ret = FALSE;
5756 else
5757 {
5758 BFD_ASSERT (new_stub);
0955507f 5759 (*cmse_stub_created)++;
4ba2ef8f
TP		 5760 }
5761 }
5762
5763 if (!symtab_hdr->contents)
5764 free (local_syms);
5765 return ret;
5766}
5767
0955507f
TP		 5768/* Return TRUE iff a symbol identified by its linker HASH entry is a secure
5769 code entry function, ie can be called from non secure code without using a
5770 veneer. */
5771
5772static bfd_boolean
5773cmse_entry_fct_p (struct elf32_arm_link_hash_entry *hash)
5774{
5775 uint32_t first_insn;
5776 asection *section;
5777 file_ptr offset;
5778 bfd *abfd;
5779
5780 /* Defined symbol of function type. */
5781 if (hash->root.root.type != bfd_link_hash_defined
5782 && hash->root.root.type != bfd_link_hash_defweak)
5783 return FALSE;
5784 if (hash->root.type != STT_FUNC)
5785 return FALSE;
5786
5787 /* Read first instruction. */
5788 section = hash->root.root.u.def.section;
5789 abfd = section->owner;
5790 offset = hash->root.root.u.def.value - section->vma;
5791 if (!bfd_get_section_contents (abfd, section, &first_insn, offset,
5792 sizeof (first_insn)))
5793 return FALSE;
5794
5795 /* Start by SG instruction. */
5796 return first_insn == 0xe97fe97f;
5797}
5798
5799/* Output the name (in symbol table) of the veneer GEN_ENTRY if it is a new
5800 secure gateway veneers (ie. the veneers was not in the input import library)
5801 and there is no output import library (GEN_INFO->out_implib_bfd is NULL. */
5802
5803static bfd_boolean
5804arm_list_new_cmse_stub (struct bfd_hash_entry *gen_entry, void *gen_info)
5805{
5806 struct elf32_arm_stub_hash_entry *stub_entry;
5807 struct bfd_link_info *info;
5808
5809 /* Massage our args to the form they really have. */
5810 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
5811 info = (struct bfd_link_info *) gen_info;
5812
5813 if (info->out_implib_bfd)
5814 return TRUE;
5815
5816 if (stub_entry->stub_type != arm_stub_cmse_branch_thumb_only)
5817 return TRUE;
5818
5819 if (stub_entry->stub_offset == (bfd_vma) -1)
5820 (*_bfd_error_handler) (" %s", stub_entry->output_name);
5821
5822 return TRUE;
5823}
5824
5825/* Set offset of each secure gateway veneers so that its address remain
5826 identical to the one in the input import library referred by
5827 HTAB->in_implib_bfd. A warning is issued for veneers that disappeared
5828 (present in input import library but absent from the executable being
5829 linked) or if new veneers appeared and there is no output import library
5830 (INFO->out_implib_bfd is NULL and *CMSE_STUB_CREATED is bigger than the
5831 number of secure gateway veneers found in the input import library.
5832
5833 The function returns whether an error occurred. If no error occurred,
5834 *CMSE_STUB_CREATED gives the number of SG veneers created by both cmse_scan
5835 and this function and HTAB->new_cmse_stub_offset is set to the biggest
5836 veneer observed set for new veneers to be layed out after. */
5837
5838static bfd_boolean
5839set_cmse_veneer_addr_from_implib (struct bfd_link_info *info,
5840 struct elf32_arm_link_hash_table *htab,
5841 int *cmse_stub_created)
5842{
5843 long symsize;
5844 char *sym_name;
5845 flagword flags;
5846 long i, symcount;
5847 bfd *in_implib_bfd;
5848 asection *stub_out_sec;
5849 bfd_boolean ret = TRUE;
5850 Elf_Internal_Sym *intsym;
5851 const char *out_sec_name;
5852 bfd_size_type cmse_stub_size;
5853 asymbol **sympp = NULL, *sym;
5854 struct elf32_arm_link_hash_entry *hash;
5855 const insn_sequence *cmse_stub_template;
5856 struct elf32_arm_stub_hash_entry *stub_entry;
5857 int cmse_stub_template_size, new_cmse_stubs_created = *cmse_stub_created;
5858 bfd_vma veneer_value, stub_offset, next_cmse_stub_offset;
5859 bfd_vma cmse_stub_array_start = (bfd_vma) -1, cmse_stub_sec_vma = 0;
5860
5861 /* No input secure gateway import library. */
5862 if (!htab->in_implib_bfd)
5863 return TRUE;
5864
5865 in_implib_bfd = htab->in_implib_bfd;
5866 if (!htab->cmse_implib)
5867 {
5868 (*_bfd_error_handler) (_("%B: --in-implib only supported for Secure "
5869 "Gateway import libraries."), in_implib_bfd);
5870 return FALSE;
5871 }
5872
5873 /* Get symbol table size. */
5874 symsize = bfd_get_symtab_upper_bound (in_implib_bfd);
5875 if (symsize < 0)
5876 return FALSE;
5877
5878 /* Read in the input secure gateway import library's symbol table. */
5879 sympp = (asymbol **) xmalloc (symsize);
5880 symcount = bfd_canonicalize_symtab (in_implib_bfd, sympp);
5881 if (symcount < 0)
5882 {
5883 ret = FALSE;
5884 goto free_sym_buf;
5885 }
5886
5887 htab->new_cmse_stub_offset = 0;
5888 cmse_stub_size =
5889 find_stub_size_and_template (arm_stub_cmse_branch_thumb_only,
5890 &cmse_stub_template,
5891 &cmse_stub_template_size);
5892 out_sec_name =
5893 arm_dedicated_stub_output_section_name (arm_stub_cmse_branch_thumb_only);
5894 stub_out_sec =
5895 bfd_get_section_by_name (htab->obfd, out_sec_name);
5896 if (stub_out_sec != NULL)
5897 cmse_stub_sec_vma = stub_out_sec->vma;
5898
5899 /* Set addresses of veneers mentionned in input secure gateway import
5900 library's symbol table. */
5901 for (i = 0; i < symcount; i++)
5902 {
5903 sym = sympp[i];
5904 flags = sym->flags;
5905 sym_name = (char *) bfd_asymbol_name (sym);
5906 intsym = &((elf_symbol_type *) sym)->internal_elf_sym;
5907
5908 if (sym->section != bfd_abs_section_ptr
5909 || !(flags & (BSF_GLOBAL | BSF_WEAK))
5910 || (flags & BSF_FUNCTION) != BSF_FUNCTION
5911 || (ARM_GET_SYM_BRANCH_TYPE (intsym->st_target_internal)
5912 != ST_BRANCH_TO_THUMB))
5913 {
5914 (*_bfd_error_handler) (_("%B: invalid import library entry: `%s'."),
5915 in_implib_bfd, sym_name);
5916 (*_bfd_error_handler) (_("Symbol should be absolute, global and "
5917 "refer to Thumb functions."));
5918 ret = FALSE;
5919 continue;
5920 }
5921
5922 veneer_value = bfd_asymbol_value (sym);
5923 stub_offset = veneer_value - cmse_stub_sec_vma;
5924 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, sym_name,
5925 FALSE, FALSE);
5926 hash = (struct elf32_arm_link_hash_entry *)
5927 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
5928
5929 /* Stub entry should have been created by cmse_scan or the symbol be of
5930 a secure function callable from non secure code. */
5931 if (!stub_entry && !hash)
5932 {
5933 bfd_boolean new_stub;
5934
5935 (*_bfd_error_handler)
5936 (_("Entry function `%s' disappeared from secure code."), sym_name);
5937 hash = (struct elf32_arm_link_hash_entry *)
5938 elf_link_hash_lookup (&(htab)->root, sym_name, TRUE, TRUE, TRUE);
5939 stub_entry
5940 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
5941 NULL, NULL, bfd_abs_section_ptr, hash,
5942 sym_name, veneer_value,
5943 ST_BRANCH_TO_THUMB, &new_stub);
5944 if (stub_entry == NULL)
5945 ret = FALSE;
5946 else
5947 {
5948 BFD_ASSERT (new_stub);
5949 new_cmse_stubs_created++;
5950 (*cmse_stub_created)++;
5951 }
5952 stub_entry->stub_template_size = stub_entry->stub_size = 0;
5953 stub_entry->stub_offset = stub_offset;
5954 }
5955 /* Symbol found is not callable from non secure code. */
5956 else if (!stub_entry)
5957 {
5958 if (!cmse_entry_fct_p (hash))
5959 {
5960 (*_bfd_error_handler) (_("`%s' refers to a non entry function."),
5961 sym_name);
5962 ret = FALSE;
5963 }
5964 continue;
5965 }
5966 else
5967 {
5968 /* Only stubs for SG veneers should have been created. */
5969 BFD_ASSERT (stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
5970
5971 /* Check visibility hasn't changed. */
5972 if (!!(flags & BSF_GLOBAL)
5973 != (hash->root.root.type == bfd_link_hash_defined))
5974 (*_bfd_error_handler)
5975 (_("%B: visibility of symbol `%s' has changed."), in_implib_bfd,
5976 sym_name);
5977
5978 stub_entry->stub_offset = stub_offset;
5979 }
5980
5981 /* Size should match that of a SG veneer. */
5982 if (intsym->st_size != cmse_stub_size)
5983 {
5984 (*_bfd_error_handler) (_("%B: incorrect size for symbol `%s'."),
5985 in_implib_bfd, sym_name);
5986 ret = FALSE;
5987 }
5988
5989 /* Previous veneer address is before current SG veneer section. */
5990 if (veneer_value < cmse_stub_sec_vma)
5991 {
5992 /* Avoid offset underflow. */
5993 if (stub_entry)
5994 stub_entry->stub_offset = 0;
5995 stub_offset = 0;
5996 ret = FALSE;
5997 }
5998
5999 /* Complain if stub offset not a multiple of stub size. */
6000 if (stub_offset % cmse_stub_size)
6001 {
6002 (*_bfd_error_handler)
6003 (_("Offset of veneer for entry function `%s' not a multiple of "
6004 "its size."), sym_name);
6005 ret = FALSE;
6006 }
6007
6008 if (!ret)
6009 continue;
6010
6011 new_cmse_stubs_created--;
6012 if (veneer_value < cmse_stub_array_start)
6013 cmse_stub_array_start = veneer_value;
6014 next_cmse_stub_offset = stub_offset + ((cmse_stub_size + 7) & ~7);
6015 if (next_cmse_stub_offset > htab->new_cmse_stub_offset)
6016 htab->new_cmse_stub_offset = next_cmse_stub_offset;
6017 }
6018
6019 if (!info->out_implib_bfd && new_cmse_stubs_created != 0)
6020 {
6021 BFD_ASSERT (new_cmse_stubs_created > 0);
6022 (*_bfd_error_handler)
6023 (_("new entry function(s) introduced but no output import library "
6024 "specified:"));
6025 bfd_hash_traverse (&htab->stub_hash_table, arm_list_new_cmse_stub, info);
6026 }
6027
6028 if (cmse_stub_array_start != cmse_stub_sec_vma)
6029 {
6030 (*_bfd_error_handler)
6031 (_("Start address of `%s' is different from previous link."),
6032 out_sec_name);
6033 ret = FALSE;
6034 }
6035
6036free_sym_buf:
6037 free (sympp);
6038 return ret;
6039}
6040
906e58ca
NC		 6041/* Determine and set the size of the stub section for a final link.
6042
6043 The basic idea here is to examine all the relocations looking for
6044 PC-relative calls to a target that is unreachable with a "bl"
6045 instruction. */
6046
6047bfd_boolean
6048elf32_arm_size_stubs (bfd *output_bfd,
6049 bfd *stub_bfd,
6050 struct bfd_link_info *info,
6051 bfd_signed_vma group_size,
7a89b94e 6052 asection * (*add_stub_section) (const char *, asection *,
6bde4c52 6053 asection *,
7a89b94e 6054 unsigned int),
906e58ca
NC		 6055 void (*layout_sections_again) (void))
6056{
0955507f 6057 bfd_boolean ret = TRUE;
4ba2ef8f 6058 obj_attribute *out_attr;
0955507f 6059 int cmse_stub_created = 0;
906e58ca 6060 bfd_size_type stub_group_size;
4ba2ef8f 6061 bfd_boolean m_profile, stubs_always_after_branch, first_veneer_scan = TRUE;
906e58ca 6062 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
48229727 6063 struct a8_erratum_fix *a8_fixes = NULL;
eb7c4339 6064 unsigned int num_a8_fixes = 0, a8_fix_table_size = 10;
48229727
JB		 6065 struct a8_erratum_reloc *a8_relocs = NULL;
6066 unsigned int num_a8_relocs = 0, a8_reloc_table_size = 10, i;
6067
4dfe6ac6
NC		 6068 if (htab == NULL)
6069 return FALSE;
6070
48229727
JB		 6071 if (htab->fix_cortex_a8)
6072 {
21d799b5 6073 a8_fixes = (struct a8_erratum_fix *)
99059e56 6074 bfd_zmalloc (sizeof (struct a8_erratum_fix) * a8_fix_table_size);
21d799b5 6075 a8_relocs = (struct a8_erratum_reloc *)
99059e56 6076 bfd_zmalloc (sizeof (struct a8_erratum_reloc) * a8_reloc_table_size);
48229727 6077 }
906e58ca
NC		 6078
6079 /* Propagate mach to stub bfd, because it may not have been
6080 finalized when we created stub_bfd. */
6081 bfd_set_arch_mach (stub_bfd, bfd_get_arch (output_bfd),
6082 bfd_get_mach (output_bfd));
6083
6084 /* Stash our params away. */
6085 htab->stub_bfd = stub_bfd;
6086 htab->add_stub_section = add_stub_section;
6087 htab->layout_sections_again = layout_sections_again;
07d72278 6088 stubs_always_after_branch = group_size < 0;
48229727 6089
4ba2ef8f
TP		 6090 out_attr = elf_known_obj_attributes_proc (output_bfd);
6091 m_profile = out_attr[Tag_CPU_arch_profile].i == 'M';
0955507f 6092
48229727
JB		 6093 /* The Cortex-A8 erratum fix depends on stubs not being in the same 4K page
6094 as the first half of a 32-bit branch straddling two 4K pages. This is a
6095 crude way of enforcing that. */
6096 if (htab->fix_cortex_a8)
6097 stubs_always_after_branch = 1;
6098
906e58ca
NC		 6099 if (group_size < 0)
6100 stub_group_size = -group_size;
6101 else
6102 stub_group_size = group_size;
6103
6104 if (stub_group_size == 1)
6105 {
6106 /* Default values. */
6107 /* Thumb branch range is +-4MB has to be used as the default
6108 maximum size (a given section can contain both ARM and Thumb
6109 code, so the worst case has to be taken into account).
6110
6111 This value is 24K less than that, which allows for 2025
6112 12-byte stubs. If we exceed that, then we will fail to link.
6113 The user will have to relink with an explicit group size
6114 option. */
6115 stub_group_size = 4170000;
6116 }
6117
07d72278 6118 group_sections (htab, stub_group_size, stubs_always_after_branch);
906e58ca 6119
3ae046cc
NS		 6120 /* If we're applying the cortex A8 fix, we need to determine the
6121 program header size now, because we cannot change it later --
6122 that could alter section placements. Notice the A8 erratum fix
6123 ends up requiring the section addresses to remain unchanged
6124 modulo the page size. That's something we cannot represent
6125 inside BFD, and we don't want to force the section alignment to
6126 be the page size. */
6127 if (htab->fix_cortex_a8)
6128 (*htab->layout_sections_again) ();
6129
906e58ca
NC		 6130 while (1)
6131 {
6132 bfd *input_bfd;
6133 unsigned int bfd_indx;
6134 asection *stub_sec;
d7c5bd02 6135 enum elf32_arm_stub_type stub_type;
eb7c4339
NS		 6136 bfd_boolean stub_changed = FALSE;
6137 unsigned prev_num_a8_fixes = num_a8_fixes;
906e58ca 6138
48229727 6139 num_a8_fixes = 0;
906e58ca
NC		 6140 for (input_bfd = info->input_bfds, bfd_indx = 0;
6141 input_bfd != NULL;
c72f2fb2 6142 input_bfd = input_bfd->link.next, bfd_indx++)
906e58ca
NC		 6143 {
6144 Elf_Internal_Shdr *symtab_hdr;
6145 asection *section;
6146 Elf_Internal_Sym *local_syms = NULL;
6147
99059e56
RM		 6148 if (!is_arm_elf (input_bfd))
6149 continue;
adbcc655 6150
48229727
JB		 6151 num_a8_relocs = 0;
6152
906e58ca
NC		 6153 /* We'll need the symbol table in a second. */
6154 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
6155 if (symtab_hdr->sh_info == 0)
6156 continue;
6157
4ba2ef8f
TP		 6158 /* Limit scan of symbols to object file whose profile is
6159 Microcontroller to not hinder performance in the general case. */
6160 if (m_profile && first_veneer_scan)
6161 {
6162 struct elf_link_hash_entry **sym_hashes;
6163
6164 sym_hashes = elf_sym_hashes (input_bfd);
6165 if (!cmse_scan (input_bfd, htab, out_attr, sym_hashes,
0955507f 6166 &cmse_stub_created))
4ba2ef8f 6167 goto error_ret_free_local;
0955507f
TP		 6168
6169 if (cmse_stub_created != 0)
6170 stub_changed = TRUE;
4ba2ef8f
TP		 6171 }
6172
906e58ca
NC		 6173 /* Walk over each section attached to the input bfd. */
6174 for (section = input_bfd->sections;
6175 section != NULL;
6176 section = section->next)
6177 {
6178 Elf_Internal_Rela *internal_relocs, *irelaend, *irela;
6179
6180 /* If there aren't any relocs, then there's nothing more
6181 to do. */
6182 if ((section->flags & SEC_RELOC) == 0
6183 || section->reloc_count == 0
6184 || (section->flags & SEC_CODE) == 0)
6185 continue;
6186
6187 /* If this section is a link-once section that will be
6188 discarded, then don't create any stubs. */
6189 if (section->output_section == NULL
6190 || section->output_section->owner != output_bfd)
6191 continue;
6192
6193 /* Get the relocs. */
6194 internal_relocs
6195 = _bfd_elf_link_read_relocs (input_bfd, section, NULL,
6196 NULL, info->keep_memory);
6197 if (internal_relocs == NULL)
6198 goto error_ret_free_local;
6199
6200 /* Now examine each relocation. */
6201 irela = internal_relocs;
6202 irelaend = irela + section->reloc_count;
6203 for (; irela < irelaend; irela++)
6204 {
6205 unsigned int r_type, r_indx;
906e58ca
NC		 6206 asection *sym_sec;
6207 bfd_vma sym_value;
6208 bfd_vma destination;
6209 struct elf32_arm_link_hash_entry *hash;
7413f23f 6210 const char *sym_name;
34e77a92 6211 unsigned char st_type;
35fc36a8 6212 enum arm_st_branch_type branch_type;
48229727 6213 bfd_boolean created_stub = FALSE;
906e58ca
NC		 6214
6215 r_type = ELF32_R_TYPE (irela->r_info);
6216 r_indx = ELF32_R_SYM (irela->r_info);
6217
6218 if (r_type >= (unsigned int) R_ARM_max)
6219 {
6220 bfd_set_error (bfd_error_bad_value);
6221 error_ret_free_internal:
6222 if (elf_section_data (section)->relocs == NULL)
6223 free (internal_relocs);
15dd01b1
TP		 6224 /* Fall through. */
6225 error_ret_free_local:
6226 if (local_syms != NULL
6227 && (symtab_hdr->contents
6228 != (unsigned char *) local_syms))
6229 free (local_syms);
6230 return FALSE;
906e58ca 6231 }
b38cadfb 6232
0855e32b
NS		 6233 hash = NULL;
6234 if (r_indx >= symtab_hdr->sh_info)
6235 hash = elf32_arm_hash_entry
6236 (elf_sym_hashes (input_bfd)
6237 [r_indx - symtab_hdr->sh_info]);
b38cadfb 6238
0855e32b
NS		 6239 /* Only look for stubs on branch instructions, or
6240 non-relaxed TLSCALL */
906e58ca 6241 if ((r_type != (unsigned int) R_ARM_CALL)
155d87d7
CL		 6242 && (r_type != (unsigned int) R_ARM_THM_CALL)
6243 && (r_type != (unsigned int) R_ARM_JUMP24)
48229727
JB		 6244 && (r_type != (unsigned int) R_ARM_THM_JUMP19)
6245 && (r_type != (unsigned int) R_ARM_THM_XPC22)
155d87d7 6246 && (r_type != (unsigned int) R_ARM_THM_JUMP24)
0855e32b
NS		 6247 && (r_type != (unsigned int) R_ARM_PLT32)
6248 && !((r_type == (unsigned int) R_ARM_TLS_CALL
6249 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6250 && r_type == elf32_arm_tls_transition
6251 (info, r_type, &hash->root)
6252 && ((hash ? hash->tls_type
6253 : (elf32_arm_local_got_tls_type
6254 (input_bfd)[r_indx]))
6255 & GOT_TLS_GDESC) != 0))
906e58ca
NC		 6256 continue;
6257
6258 /* Now determine the call target, its name, value,
6259 section. */
6260 sym_sec = NULL;
6261 sym_value = 0;
6262 destination = 0;
7413f23f 6263 sym_name = NULL;
b38cadfb 6264
0855e32b
NS		 6265 if (r_type == (unsigned int) R_ARM_TLS_CALL
6266 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6267 {
6268 /* A non-relaxed TLS call. The target is the
6269 plt-resident trampoline and nothing to do
6270 with the symbol. */
6271 BFD_ASSERT (htab->tls_trampoline > 0);
6272 sym_sec = htab->root.splt;
6273 sym_value = htab->tls_trampoline;
6274 hash = 0;
34e77a92 6275 st_type = STT_FUNC;
35fc36a8 6276 branch_type = ST_BRANCH_TO_ARM;
0855e32b
NS		 6277 }
6278 else if (!hash)
906e58ca
NC		 6279 {
6280 /* It's a local symbol. */
6281 Elf_Internal_Sym *sym;
906e58ca
NC		 6282
6283 if (local_syms == NULL)
6284 {
6285 local_syms
6286 = (Elf_Internal_Sym *) symtab_hdr->contents;
6287 if (local_syms == NULL)
6288 local_syms
6289 = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
6290 symtab_hdr->sh_info, 0,
6291 NULL, NULL, NULL);
6292 if (local_syms == NULL)
6293 goto error_ret_free_internal;
6294 }
6295
6296 sym = local_syms + r_indx;
f6d250ce
TS		 6297 if (sym->st_shndx == SHN_UNDEF)
6298 sym_sec = bfd_und_section_ptr;
6299 else if (sym->st_shndx == SHN_ABS)
6300 sym_sec = bfd_abs_section_ptr;
6301 else if (sym->st_shndx == SHN_COMMON)
6302 sym_sec = bfd_com_section_ptr;
6303 else
6304 sym_sec =
6305 bfd_section_from_elf_index (input_bfd, sym->st_shndx);
6306
ffcb4889
NS		 6307 if (!sym_sec)
6308 /* This is an undefined symbol. It can never
6a631e86 6309 be resolved. */
ffcb4889 6310 continue;
fe33d2fa 6311
906e58ca
NC		 6312 if (ELF_ST_TYPE (sym->st_info) != STT_SECTION)
6313 sym_value = sym->st_value;
6314 destination = (sym_value + irela->r_addend
6315 + sym_sec->output_offset
6316 + sym_sec->output_section->vma);
34e77a92 6317 st_type = ELF_ST_TYPE (sym->st_info);
39d911fc
TP		 6318 branch_type =
6319 ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
7413f23f
DJ		 6320 sym_name
6321 = bfd_elf_string_from_elf_section (input_bfd,
6322 symtab_hdr->sh_link,
6323 sym->st_name);
906e58ca
NC		 6324 }
6325 else
6326 {
6327 /* It's an external symbol. */
906e58ca
NC		 6328 while (hash->root.root.type == bfd_link_hash_indirect
6329 || hash->root.root.type == bfd_link_hash_warning)
6330 hash = ((struct elf32_arm_link_hash_entry *)
6331 hash->root.root.u.i.link);
6332
6333 if (hash->root.root.type == bfd_link_hash_defined
6334 || hash->root.root.type == bfd_link_hash_defweak)
6335 {
6336 sym_sec = hash->root.root.u.def.section;
6337 sym_value = hash->root.root.u.def.value;
022f8312
CL		 6338
6339 struct elf32_arm_link_hash_table *globals =
6340 elf32_arm_hash_table (info);
6341
6342 /* For a destination in a shared library,
6343 use the PLT stub as target address to
6344 decide whether a branch stub is
6345 needed. */
4dfe6ac6 6346 if (globals != NULL
362d30a1 6347 && globals->root.splt != NULL
4dfe6ac6 6348 && hash != NULL
022f8312
CL		 6349 && hash->root.plt.offset != (bfd_vma) -1)
6350 {
362d30a1 6351 sym_sec = globals->root.splt;
022f8312
CL		 6352 sym_value = hash->root.plt.offset;
6353 if (sym_sec->output_section != NULL)
6354 destination = (sym_value
6355 + sym_sec->output_offset
6356 + sym_sec->output_section->vma);
6357 }
6358 else if (sym_sec->output_section != NULL)
906e58ca
NC		 6359 destination = (sym_value + irela->r_addend
6360 + sym_sec->output_offset
6361 + sym_sec->output_section->vma);
6362 }
69c5861e
CL		 6363 else if ((hash->root.root.type == bfd_link_hash_undefined)
6364 || (hash->root.root.type == bfd_link_hash_undefweak))
6365 {
6366 /* For a shared library, use the PLT stub as
6367 target address to decide whether a long
6368 branch stub is needed.
6369 For absolute code, they cannot be handled. */
6370 struct elf32_arm_link_hash_table *globals =
6371 elf32_arm_hash_table (info);
6372
4dfe6ac6 6373 if (globals != NULL
362d30a1 6374 && globals->root.splt != NULL
4dfe6ac6 6375 && hash != NULL
69c5861e
CL		 6376 && hash->root.plt.offset != (bfd_vma) -1)
6377 {
362d30a1 6378 sym_sec = globals->root.splt;
69c5861e
CL		 6379 sym_value = hash->root.plt.offset;
6380 if (sym_sec->output_section != NULL)
6381 destination = (sym_value
6382 + sym_sec->output_offset
6383 + sym_sec->output_section->vma);
6384 }
6385 else
6386 continue;
6387 }
906e58ca
NC		 6388 else
6389 {
6390 bfd_set_error (bfd_error_bad_value);
6391 goto error_ret_free_internal;
6392 }
34e77a92 6393 st_type = hash->root.type;
39d911fc
TP		 6394 branch_type =
6395 ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
7413f23f 6396 sym_name = hash->root.root.root.string;
906e58ca
NC		 6397 }
6398
48229727 6399 do
7413f23f 6400 {
b715f643 6401 bfd_boolean new_stub;
0955507f 6402 struct elf32_arm_stub_hash_entry *stub_entry;
b715f643 6403
48229727
JB		 6404 /* Determine what (if any) linker stub is needed. */
6405 stub_type = arm_type_of_stub (info, section, irela,
34e77a92
RS		 6406 st_type, &branch_type,
6407 hash, destination, sym_sec,
48229727
JB		 6408 input_bfd, sym_name);
6409 if (stub_type == arm_stub_none)
6410 break;
6411
48229727
JB		 6412 /* We've either created a stub for this reloc already,
6413 or we are about to. */
0955507f 6414 stub_entry =
b715f643
TP		 6415 elf32_arm_create_stub (htab, stub_type, section, irela,
6416 sym_sec, hash,
6417 (char *) sym_name, sym_value,
6418 branch_type, &new_stub);
7413f23f 6419
0955507f 6420 created_stub = stub_entry != NULL;
b715f643
TP		 6421 if (!created_stub)
6422 goto error_ret_free_internal;
6423 else if (!new_stub)
6424 break;
99059e56 6425 else
b715f643 6426 stub_changed = TRUE;
99059e56
RM		 6427 }
6428 while (0);
6429
6430 /* Look for relocations which might trigger Cortex-A8
6431 erratum. */
6432 if (htab->fix_cortex_a8
6433 && (r_type == (unsigned int) R_ARM_THM_JUMP24
6434 || r_type == (unsigned int) R_ARM_THM_JUMP19
6435 || r_type == (unsigned int) R_ARM_THM_CALL
6436 || r_type == (unsigned int) R_ARM_THM_XPC22))
6437 {
6438 bfd_vma from = section->output_section->vma
6439 + section->output_offset
6440 + irela->r_offset;
6441
6442 if ((from & 0xfff) == 0xffe)
6443 {
6444 /* Found a candidate. Note we haven't checked the
6445 destination is within 4K here: if we do so (and
6446 don't create an entry in a8_relocs) we can't tell
6447 that a branch should have been relocated when
6448 scanning later. */
6449 if (num_a8_relocs == a8_reloc_table_size)
6450 {
6451 a8_reloc_table_size *= 2;
6452 a8_relocs = (struct a8_erratum_reloc *)
6453 bfd_realloc (a8_relocs,
6454 sizeof (struct a8_erratum_reloc)
6455 * a8_reloc_table_size);
6456 }
6457
6458 a8_relocs[num_a8_relocs].from = from;
6459 a8_relocs[num_a8_relocs].destination = destination;
6460 a8_relocs[num_a8_relocs].r_type = r_type;
6461 a8_relocs[num_a8_relocs].branch_type = branch_type;
6462 a8_relocs[num_a8_relocs].sym_name = sym_name;
6463 a8_relocs[num_a8_relocs].non_a8_stub = created_stub;
6464 a8_relocs[num_a8_relocs].hash = hash;
6465
6466 num_a8_relocs++;
6467 }
6468 }
906e58ca
NC		 6469 }
6470
99059e56
RM		 6471 /* We're done with the internal relocs, free them. */
6472 if (elf_section_data (section)->relocs == NULL)
6473 free (internal_relocs);
6474 }
48229727 6475
99059e56 6476 if (htab->fix_cortex_a8)
48229727 6477 {
99059e56
RM		 6478 /* Sort relocs which might apply to Cortex-A8 erratum. */
6479 qsort (a8_relocs, num_a8_relocs,
eb7c4339 6480 sizeof (struct a8_erratum_reloc),
99059e56 6481 &a8_reloc_compare);
48229727 6482
99059e56
RM		 6483 /* Scan for branches which might trigger Cortex-A8 erratum. */
6484 if (cortex_a8_erratum_scan (input_bfd, info, &a8_fixes,
48229727 6485 &num_a8_fixes, &a8_fix_table_size,
eb7c4339
NS		 6486 a8_relocs, num_a8_relocs,
6487 prev_num_a8_fixes, &stub_changed)
6488 != 0)
48229727 6489 goto error_ret_free_local;
5e681ec4 6490 }
7f991970
AM		 6491
6492 if (local_syms != NULL
6493 && symtab_hdr->contents != (unsigned char *) local_syms)
6494 {
6495 if (!info->keep_memory)
6496 free (local_syms);
6497 else
6498 symtab_hdr->contents = (unsigned char *) local_syms;
6499 }
5e681ec4
PB		 6500 }
6501
0955507f
TP		 6502 if (first_veneer_scan
6503 && !set_cmse_veneer_addr_from_implib (info, htab,
6504 &cmse_stub_created))
6505 ret = FALSE;
6506
eb7c4339 6507 if (prev_num_a8_fixes != num_a8_fixes)
99059e56 6508 stub_changed = TRUE;
48229727 6509
906e58ca
NC		 6510 if (!stub_changed)
6511 break;
5e681ec4 6512
906e58ca
NC		 6513 /* OK, we've added some stubs. Find out the new size of the
6514 stub sections. */
6515 for (stub_sec = htab->stub_bfd->sections;
6516 stub_sec != NULL;
6517 stub_sec = stub_sec->next)
3e6b1042
DJ		 6518 {
6519 /* Ignore non-stub sections. */
6520 if (!strstr (stub_sec->name, STUB_SUFFIX))
6521 continue;
6522
6523 stub_sec->size = 0;
6524 }
b34b2d70 6525
0955507f
TP		 6526 /* Add new SG veneers after those already in the input import
6527 library. */
6528 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6529 stub_type++)
6530 {
6531 bfd_vma *start_offset_p;
6532 asection **stub_sec_p;
6533
6534 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
6535 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6536 if (start_offset_p == NULL)
6537 continue;
6538
6539 BFD_ASSERT (stub_sec_p != NULL);
6540 if (*stub_sec_p != NULL)
6541 (*stub_sec_p)->size = *start_offset_p;
6542 }
6543
d7c5bd02 6544 /* Compute stub section size, considering padding. */
906e58ca 6545 bfd_hash_traverse (&htab->stub_hash_table, arm_size_one_stub, htab);
d7c5bd02
TP		 6546 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6547 stub_type++)
6548 {
6549 int size, padding;
6550 asection **stub_sec_p;
6551
6552 padding = arm_dedicated_stub_section_padding (stub_type);
6553 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6554 /* Skip if no stub input section or no stub section padding
6555 required. */
6556 if ((stub_sec_p != NULL && *stub_sec_p == NULL) || padding == 0)
6557 continue;
6558 /* Stub section padding required but no dedicated section. */
6559 BFD_ASSERT (stub_sec_p);
6560
6561 size = (*stub_sec_p)->size;
6562 size = (size + padding - 1) & ~(padding - 1);
6563 (*stub_sec_p)->size = size;
6564 }
906e58ca 6565
48229727
JB		 6566 /* Add Cortex-A8 erratum veneers to stub section sizes too. */
6567 if (htab->fix_cortex_a8)
99059e56
RM		 6568 for (i = 0; i < num_a8_fixes; i++)
6569 {
48229727 6570 stub_sec = elf32_arm_create_or_find_stub_sec (NULL,
daa4adae 6571 a8_fixes[i].section, htab, a8_fixes[i].stub_type);
48229727
JB		 6572
6573 if (stub_sec == NULL)
7f991970 6574 return FALSE;
48229727 6575
99059e56
RM		 6576 stub_sec->size
6577 += find_stub_size_and_template (a8_fixes[i].stub_type, NULL,
6578 NULL);
6579 }
48229727
JB		 6580
6581
906e58ca
NC		 6582 /* Ask the linker to do its stuff. */
6583 (*htab->layout_sections_again) ();
4ba2ef8f 6584 first_veneer_scan = FALSE;
ba93b8ac
DJ		 6585 }
6586
48229727
JB		 6587 /* Add stubs for Cortex-A8 erratum fixes now. */
6588 if (htab->fix_cortex_a8)
6589 {
6590 for (i = 0; i < num_a8_fixes; i++)
99059e56
RM		 6591 {
6592 struct elf32_arm_stub_hash_entry *stub_entry;
6593 char *stub_name = a8_fixes[i].stub_name;
6594 asection *section = a8_fixes[i].section;
6595 unsigned int section_id = a8_fixes[i].section->id;
6596 asection *link_sec = htab->stub_group[section_id].link_sec;
6597 asection *stub_sec = htab->stub_group[section_id].stub_sec;
6598 const insn_sequence *template_sequence;
6599 int template_size, size = 0;
6600
6601 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
6602 TRUE, FALSE);
6603 if (stub_entry == NULL)
6604 {
6605 (*_bfd_error_handler) (_("%s: cannot create stub entry %s"),
6606 section->owner,
6607 stub_name);
6608 return FALSE;
6609 }
6610
6611 stub_entry->stub_sec = stub_sec;
0955507f 6612 stub_entry->stub_offset = (bfd_vma) -1;
99059e56
RM		 6613 stub_entry->id_sec = link_sec;
6614 stub_entry->stub_type = a8_fixes[i].stub_type;
8d9d9490 6615 stub_entry->source_value = a8_fixes[i].offset;
99059e56 6616 stub_entry->target_section = a8_fixes[i].section;
8d9d9490 6617 stub_entry->target_value = a8_fixes[i].target_offset;
99059e56 6618 stub_entry->orig_insn = a8_fixes[i].orig_insn;
35fc36a8 6619 stub_entry->branch_type = a8_fixes[i].branch_type;
48229727 6620
99059e56
RM		 6621 size = find_stub_size_and_template (a8_fixes[i].stub_type,
6622 &template_sequence,
6623 &template_size);
48229727 6624
99059e56
RM		 6625 stub_entry->stub_size = size;
6626 stub_entry->stub_template = template_sequence;
6627 stub_entry->stub_template_size = template_size;
6628 }
48229727
JB		 6629
6630 /* Stash the Cortex-A8 erratum fix array for use later in
99059e56 6631 elf32_arm_write_section(). */
48229727
JB		 6632 htab->a8_erratum_fixes = a8_fixes;
6633 htab->num_a8_erratum_fixes = num_a8_fixes;
6634 }
6635 else
6636 {
6637 htab->a8_erratum_fixes = NULL;
6638 htab->num_a8_erratum_fixes = 0;
6639 }
0955507f 6640 return ret;
5e681ec4
PB		 6641}
6642
906e58ca
NC		 6643/* Build all the stubs associated with the current output file. The
6644 stubs are kept in a hash table attached to the main linker hash
6645 table. We also set up the .plt entries for statically linked PIC
6646 functions here. This function is called via arm_elf_finish in the
6647 linker. */
252b5132 6648
906e58ca
NC		 6649bfd_boolean
6650elf32_arm_build_stubs (struct bfd_link_info *info)
252b5132 6651{
906e58ca
NC		 6652 asection *stub_sec;
6653 struct bfd_hash_table *table;
0955507f 6654 enum elf32_arm_stub_type stub_type;
906e58ca 6655 struct elf32_arm_link_hash_table *htab;
252b5132 6656
906e58ca 6657 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 6658 if (htab == NULL)
6659 return FALSE;
252b5132 6660
906e58ca
NC		 6661 for (stub_sec = htab->stub_bfd->sections;
6662 stub_sec != NULL;
6663 stub_sec = stub_sec->next)
252b5132 6664 {
906e58ca
NC		 6665 bfd_size_type size;
6666
8029a119 6667 /* Ignore non-stub sections. */
906e58ca
NC		 6668 if (!strstr (stub_sec->name, STUB_SUFFIX))
6669 continue;
6670
d7c5bd02 6671 /* Allocate memory to hold the linker stubs. Zeroing the stub sections
0955507f
TP		 6672 must at least be done for stub section requiring padding and for SG
6673 veneers to ensure that a non secure code branching to a removed SG
6674 veneer causes an error. */
906e58ca 6675 size = stub_sec->size;
21d799b5 6676 stub_sec->contents = (unsigned char *) bfd_zalloc (htab->stub_bfd, size);
906e58ca
NC		 6677 if (stub_sec->contents == NULL && size != 0)
6678 return FALSE;
0955507f 6679
906e58ca 6680 stub_sec->size = 0;
252b5132
RH		 6681 }
6682
0955507f
TP		 6683 /* Add new SG veneers after those already in the input import library. */
6684 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
6685 {
6686 bfd_vma *start_offset_p;
6687 asection **stub_sec_p;
6688
6689 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
6690 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6691 if (start_offset_p == NULL)
6692 continue;
6693
6694 BFD_ASSERT (stub_sec_p != NULL);
6695 if (*stub_sec_p != NULL)
6696 (*stub_sec_p)->size = *start_offset_p;
6697 }
6698
906e58ca
NC		 6699 /* Build the stubs as directed by the stub hash table. */
6700 table = &htab->stub_hash_table;
6701 bfd_hash_traverse (table, arm_build_one_stub, info);
eb7c4339
NS		 6702 if (htab->fix_cortex_a8)
6703 {
6704 /* Place the cortex a8 stubs last. */
6705 htab->fix_cortex_a8 = -1;
6706 bfd_hash_traverse (table, arm_build_one_stub, info);
6707 }
252b5132 6708
906e58ca 6709 return TRUE;
252b5132
RH		 6710}
6711
9b485d32
NC		 6712/* Locate the Thumb encoded calling stub for NAME. */
6713
252b5132 6714static struct elf_link_hash_entry *
57e8b36a
NC		 6715find_thumb_glue (struct bfd_link_info *link_info,
6716 const char *name,
f2a9dd69 6717 char **error_message)
252b5132
RH		 6718{
6719 char *tmp_name;
6720 struct elf_link_hash_entry *hash;
6721 struct elf32_arm_link_hash_table *hash_table;
6722
6723 /* We need a pointer to the armelf specific hash table. */
6724 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 6725 if (hash_table == NULL)
6726 return NULL;
252b5132 6727
21d799b5 6728 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 6729 + strlen (THUMB2ARM_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 6730
6731 BFD_ASSERT (tmp_name);
6732
6733 sprintf (tmp_name, THUMB2ARM_GLUE_ENTRY_NAME, name);
6734
6735 hash = elf_link_hash_lookup
b34976b6 6736 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 6737
b1657152
AM		 6738 if (hash == NULL
6739 && asprintf (error_message, _("unable to find THUMB glue '%s' for '%s'"),
6740 tmp_name, name) == -1)
6741 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 6742
6743 free (tmp_name);
6744
6745 return hash;
6746}
6747
9b485d32
NC		 6748/* Locate the ARM encoded calling stub for NAME. */
6749
252b5132 6750static struct elf_link_hash_entry *
57e8b36a
NC		 6751find_arm_glue (struct bfd_link_info *link_info,
6752 const char *name,
f2a9dd69 6753 char **error_message)
252b5132
RH		 6754{
6755 char *tmp_name;
6756 struct elf_link_hash_entry *myh;
6757 struct elf32_arm_link_hash_table *hash_table;
6758
6759 /* We need a pointer to the elfarm specific hash table. */
6760 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 6761 if (hash_table == NULL)
6762 return NULL;
252b5132 6763
21d799b5 6764 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 6765 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 6766
6767 BFD_ASSERT (tmp_name);
6768
6769 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
6770
6771 myh = elf_link_hash_lookup
b34976b6 6772 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 6773
b1657152
AM		 6774 if (myh == NULL
6775 && asprintf (error_message, _("unable to find ARM glue '%s' for '%s'"),
6776 tmp_name, name) == -1)
6777 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 6778
6779 free (tmp_name);
6780
6781 return myh;
6782}
6783
8f6277f5 6784/* ARM->Thumb glue (static images):
252b5132
RH		 6785
6786 .arm
6787 __func_from_arm:
6788 ldr r12, __func_addr
6789 bx r12
6790 __func_addr:
906e58ca 6791 .word func @ behave as if you saw a ARM_32 reloc.
252b5132 6792
26079076
PB		 6793 (v5t static images)
6794 .arm
6795 __func_from_arm:
6796 ldr pc, __func_addr
6797 __func_addr:
906e58ca 6798 .word func @ behave as if you saw a ARM_32 reloc.
26079076 6799
8f6277f5
PB		 6800 (relocatable images)
6801 .arm
6802 __func_from_arm:
6803 ldr r12, __func_offset
6804 add r12, r12, pc
6805 bx r12
6806 __func_offset:
8029a119 6807 .word func - . */
8f6277f5
PB		 6808
6809#define ARM2THUMB_STATIC_GLUE_SIZE 12
252b5132
RH		 6810static const insn32 a2t1_ldr_insn = 0xe59fc000;
6811static const insn32 a2t2_bx_r12_insn = 0xe12fff1c;
6812static const insn32 a2t3_func_addr_insn = 0x00000001;
6813
26079076
PB		 6814#define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
6815static const insn32 a2t1v5_ldr_insn = 0xe51ff004;
6816static const insn32 a2t2v5_func_addr_insn = 0x00000001;
6817
8f6277f5
PB		 6818#define ARM2THUMB_PIC_GLUE_SIZE 16
6819static const insn32 a2t1p_ldr_insn = 0xe59fc004;
6820static const insn32 a2t2p_add_pc_insn = 0xe08cc00f;
6821static const insn32 a2t3p_bx_r12_insn = 0xe12fff1c;
6822
9b485d32 6823/* Thumb->ARM: Thumb->(non-interworking aware) ARM
252b5132 6824
8029a119
NC		 6825 .thumb .thumb
6826 .align 2 .align 2
6827 __func_from_thumb: __func_from_thumb:
6828 bx pc push {r6, lr}
6829 nop ldr r6, __func_addr
6830 .arm mov lr, pc
6831 b func bx r6
99059e56
RM		 6832 .arm
6833 ;; back_to_thumb
6834 ldmia r13! {r6, lr}
6835 bx lr
6836 __func_addr:
6837 .word func */
252b5132
RH		 6838
6839#define THUMB2ARM_GLUE_SIZE 8
6840static const insn16 t2a1_bx_pc_insn = 0x4778;
6841static const insn16 t2a2_noop_insn = 0x46c0;
6842static const insn32 t2a3_b_insn = 0xea000000;
6843
c7b8f16e 6844#define VFP11_ERRATUM_VENEER_SIZE 8
a504d23a
LA		 6845#define STM32L4XX_ERRATUM_LDM_VENEER_SIZE 16
6846#define STM32L4XX_ERRATUM_VLDM_VENEER_SIZE 24
c7b8f16e 6847
845b51d6
PB		 6848#define ARM_BX_VENEER_SIZE 12
6849static const insn32 armbx1_tst_insn = 0xe3100001;
6850static const insn32 armbx2_moveq_insn = 0x01a0f000;
6851static const insn32 armbx3_bx_insn = 0xe12fff10;
6852
7e392df6 6853#ifndef ELFARM_NABI_C_INCLUDED
8029a119
NC		 6854static void
6855arm_allocate_glue_section_space (bfd * abfd, bfd_size_type size, const char * name)
252b5132
RH		 6856{
6857 asection * s;
8029a119 6858 bfd_byte * contents;
252b5132 6859
8029a119 6860 if (size == 0)
3e6b1042
DJ		 6861 {
6862 /* Do not include empty glue sections in the output. */
6863 if (abfd != NULL)
6864 {
3d4d4302 6865 s = bfd_get_linker_section (abfd, name);
3e6b1042
DJ		 6866 if (s != NULL)
6867 s->flags |= SEC_EXCLUDE;
6868 }
6869 return;
6870 }
252b5132 6871
8029a119 6872 BFD_ASSERT (abfd != NULL);
252b5132 6873
3d4d4302 6874 s = bfd_get_linker_section (abfd, name);
8029a119 6875 BFD_ASSERT (s != NULL);
252b5132 6876
21d799b5 6877 contents = (bfd_byte *) bfd_alloc (abfd, size);
252b5132 6878
8029a119
NC		 6879 BFD_ASSERT (s->size == size);
6880 s->contents = contents;
6881}
906e58ca 6882
8029a119
NC		 6883bfd_boolean
6884bfd_elf32_arm_allocate_interworking_sections (struct bfd_link_info * info)
6885{
6886 struct elf32_arm_link_hash_table * globals;
906e58ca 6887
8029a119
NC		 6888 globals = elf32_arm_hash_table (info);
6889 BFD_ASSERT (globals != NULL);
906e58ca 6890
8029a119
NC		 6891 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6892 globals->arm_glue_size,
6893 ARM2THUMB_GLUE_SECTION_NAME);
906e58ca 6894
8029a119
NC		 6895 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6896 globals->thumb_glue_size,
6897 THUMB2ARM_GLUE_SECTION_NAME);
252b5132 6898
8029a119
NC		 6899 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6900 globals->vfp11_erratum_glue_size,
6901 VFP11_ERRATUM_VENEER_SECTION_NAME);
845b51d6 6902
a504d23a
LA		 6903 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6904 globals->stm32l4xx_erratum_glue_size,
6905 STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
6906
8029a119
NC		 6907 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6908 globals->bx_glue_size,
845b51d6
PB		 6909 ARM_BX_GLUE_SECTION_NAME);
6910
b34976b6 6911 return TRUE;
252b5132
RH		 6912}
6913
a4fd1a8e 6914/* Allocate space and symbols for calling a Thumb function from Arm mode.
906e58ca
NC		 6915 returns the symbol identifying the stub. */
6916
a4fd1a8e 6917static struct elf_link_hash_entry *
57e8b36a
NC		 6918record_arm_to_thumb_glue (struct bfd_link_info * link_info,
6919 struct elf_link_hash_entry * h)
252b5132
RH		 6920{
6921 const char * name = h->root.root.string;
63b0f745 6922 asection * s;
252b5132
RH		 6923 char * tmp_name;
6924 struct elf_link_hash_entry * myh;
14a793b2 6925 struct bfd_link_hash_entry * bh;
252b5132 6926 struct elf32_arm_link_hash_table * globals;
dc810e39 6927 bfd_vma val;
2f475487 6928 bfd_size_type size;
252b5132
RH		 6929
6930 globals = elf32_arm_hash_table (link_info);
252b5132
RH		 6931 BFD_ASSERT (globals != NULL);
6932 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
6933
3d4d4302 6934 s = bfd_get_linker_section
252b5132
RH		 6935 (globals->bfd_of_glue_owner, ARM2THUMB_GLUE_SECTION_NAME);
6936
252b5132
RH		 6937 BFD_ASSERT (s != NULL);
6938
21d799b5 6939 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 6940 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 6941
6942 BFD_ASSERT (tmp_name);
6943
6944 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
6945
6946 myh = elf_link_hash_lookup
b34976b6 6947 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132
RH		 6948
6949 if (myh != NULL)
6950 {
9b485d32 6951 /* We've already seen this guy. */
252b5132 6952 free (tmp_name);
a4fd1a8e 6953 return myh;
252b5132
RH		 6954 }
6955
57e8b36a
NC		 6956 /* The only trick here is using hash_table->arm_glue_size as the value.
6957 Even though the section isn't allocated yet, this is where we will be
3dccd7b7
DJ		 6958 putting it. The +1 on the value marks that the stub has not been
6959 output yet - not that it is a Thumb function. */
14a793b2 6960 bh = NULL;
dc810e39
AM		 6961 val = globals->arm_glue_size + 1;
6962 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
6963 tmp_name, BSF_GLOBAL, s, val,
b34976b6 6964 NULL, TRUE, FALSE, &bh);
252b5132 6965
b7693d02
DJ		 6966 myh = (struct elf_link_hash_entry *) bh;
6967 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6968 myh->forced_local = 1;
6969
252b5132
RH		 6970 free (tmp_name);
6971
0e1862bb
L		 6972 if (bfd_link_pic (link_info)
6973 || globals->root.is_relocatable_executable
27e55c4d 6974 || globals->pic_veneer)
2f475487 6975 size = ARM2THUMB_PIC_GLUE_SIZE;
26079076
PB		 6976 else if (globals->use_blx)
6977 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
8f6277f5 6978 else
2f475487
AM		 6979 size = ARM2THUMB_STATIC_GLUE_SIZE;
6980
6981 s->size += size;
6982 globals->arm_glue_size += size;
252b5132 6983
a4fd1a8e 6984 return myh;
252b5132
RH		 6985}
6986
845b51d6
PB		 6987/* Allocate space for ARMv4 BX veneers. */
6988
6989static void
6990record_arm_bx_glue (struct bfd_link_info * link_info, int reg)
6991{
6992 asection * s;
6993 struct elf32_arm_link_hash_table *globals;
6994 char *tmp_name;
6995 struct elf_link_hash_entry *myh;
6996 struct bfd_link_hash_entry *bh;
6997 bfd_vma val;
6998
6999 /* BX PC does not need a veneer. */
7000 if (reg == 15)
7001 return;
7002
7003 globals = elf32_arm_hash_table (link_info);
845b51d6
PB		 7004 BFD_ASSERT (globals != NULL);
7005 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7006
7007 /* Check if this veneer has already been allocated. */
7008 if (globals->bx_glue_offset[reg])
7009 return;
7010
3d4d4302 7011 s = bfd_get_linker_section
845b51d6
PB		 7012 (globals->bfd_of_glue_owner, ARM_BX_GLUE_SECTION_NAME);
7013
7014 BFD_ASSERT (s != NULL);
7015
7016 /* Add symbol for veneer. */
21d799b5
NC		 7017 tmp_name = (char *)
7018 bfd_malloc ((bfd_size_type) strlen (ARM_BX_GLUE_ENTRY_NAME) + 1);
906e58ca 7019
845b51d6 7020 BFD_ASSERT (tmp_name);
906e58ca 7021
845b51d6 7022 sprintf (tmp_name, ARM_BX_GLUE_ENTRY_NAME, reg);
906e58ca 7023
845b51d6
PB		 7024 myh = elf_link_hash_lookup
7025 (&(globals)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7026
845b51d6 7027 BFD_ASSERT (myh == NULL);
906e58ca 7028
845b51d6
PB		 7029 bh = NULL;
7030 val = globals->bx_glue_size;
7031 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
99059e56
RM		 7032 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7033 NULL, TRUE, FALSE, &bh);
845b51d6
PB		 7034
7035 myh = (struct elf_link_hash_entry *) bh;
7036 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7037 myh->forced_local = 1;
7038
7039 s->size += ARM_BX_VENEER_SIZE;
7040 globals->bx_glue_offset[reg] = globals->bx_glue_size | 2;
7041 globals->bx_glue_size += ARM_BX_VENEER_SIZE;
7042}
7043
7044
c7b8f16e
JB		 7045/* Add an entry to the code/data map for section SEC. */
7046
7047static void
7048elf32_arm_section_map_add (asection *sec, char type, bfd_vma vma)
7049{
7050 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
7051 unsigned int newidx;
906e58ca 7052
c7b8f16e
JB		 7053 if (sec_data->map == NULL)
7054 {
21d799b5 7055 sec_data->map = (elf32_arm_section_map *)
99059e56 7056 bfd_malloc (sizeof (elf32_arm_section_map));
c7b8f16e
JB		 7057 sec_data->mapcount = 0;
7058 sec_data->mapsize = 1;
7059 }
906e58ca 7060
c7b8f16e 7061 newidx = sec_data->mapcount++;
906e58ca 7062
c7b8f16e
JB		 7063 if (sec_data->mapcount > sec_data->mapsize)
7064 {
7065 sec_data->mapsize *= 2;
21d799b5 7066 sec_data->map = (elf32_arm_section_map *)
99059e56
RM		 7067 bfd_realloc_or_free (sec_data->map, sec_data->mapsize
7068 * sizeof (elf32_arm_section_map));
515ef31d
NC		 7069 }
7070
7071 if (sec_data->map)
7072 {
7073 sec_data->map[newidx].vma = vma;
7074 sec_data->map[newidx].type = type;
c7b8f16e 7075 }
c7b8f16e
JB		 7076}
7077
7078
7079/* Record information about a VFP11 denorm-erratum veneer. Only ARM-mode
7080 veneers are handled for now. */
7081
7082static bfd_vma
7083record_vfp11_erratum_veneer (struct bfd_link_info *link_info,
99059e56
RM		 7084 elf32_vfp11_erratum_list *branch,
7085 bfd *branch_bfd,
7086 asection *branch_sec,
7087 unsigned int offset)
c7b8f16e
JB		 7088{
7089 asection *s;
7090 struct elf32_arm_link_hash_table *hash_table;
7091 char *tmp_name;
7092 struct elf_link_hash_entry *myh;
7093 struct bfd_link_hash_entry *bh;
7094 bfd_vma val;
7095 struct _arm_elf_section_data *sec_data;
c7b8f16e 7096 elf32_vfp11_erratum_list *newerr;
906e58ca 7097
c7b8f16e 7098 hash_table = elf32_arm_hash_table (link_info);
c7b8f16e
JB		 7099 BFD_ASSERT (hash_table != NULL);
7100 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
906e58ca 7101
3d4d4302 7102 s = bfd_get_linker_section
c7b8f16e 7103 (hash_table->bfd_of_glue_owner, VFP11_ERRATUM_VENEER_SECTION_NAME);
906e58ca 7104
c7b8f16e 7105 sec_data = elf32_arm_section_data (s);
906e58ca 7106
c7b8f16e 7107 BFD_ASSERT (s != NULL);
906e58ca 7108
21d799b5 7109 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 7110 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
906e58ca 7111
c7b8f16e 7112 BFD_ASSERT (tmp_name);
906e58ca 7113
c7b8f16e
JB		 7114 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
7115 hash_table->num_vfp11_fixes);
906e58ca 7116
c7b8f16e
JB		 7117 myh = elf_link_hash_lookup
7118 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7119
c7b8f16e 7120 BFD_ASSERT (myh == NULL);
906e58ca 7121
c7b8f16e
JB		 7122 bh = NULL;
7123 val = hash_table->vfp11_erratum_glue_size;
7124 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
99059e56
RM		 7125 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7126 NULL, TRUE, FALSE, &bh);
c7b8f16e
JB		 7127
7128 myh = (struct elf_link_hash_entry *) bh;
7129 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7130 myh->forced_local = 1;
7131
7132 /* Link veneer back to calling location. */
c7e2358a 7133 sec_data->erratumcount += 1;
21d799b5
NC		 7134 newerr = (elf32_vfp11_erratum_list *)
7135 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
906e58ca 7136
c7b8f16e
JB		 7137 newerr->type = VFP11_ERRATUM_ARM_VENEER;
7138 newerr->vma = -1;
7139 newerr->u.v.branch = branch;
7140 newerr->u.v.id = hash_table->num_vfp11_fixes;
7141 branch->u.b.veneer = newerr;
7142
7143 newerr->next = sec_data->erratumlist;
7144 sec_data->erratumlist = newerr;
7145
7146 /* A symbol for the return from the veneer. */
7147 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
7148 hash_table->num_vfp11_fixes);
7149
7150 myh = elf_link_hash_lookup
7151 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7152
c7b8f16e
JB		 7153 if (myh != NULL)
7154 abort ();
7155
7156 bh = NULL;
7157 val = offset + 4;
7158 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7159 branch_sec, val, NULL, TRUE, FALSE, &bh);
906e58ca 7160
c7b8f16e
JB		 7161 myh = (struct elf_link_hash_entry *) bh;
7162 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7163 myh->forced_local = 1;
7164
7165 free (tmp_name);
906e58ca 7166
c7b8f16e
JB		 7167 /* Generate a mapping symbol for the veneer section, and explicitly add an
7168 entry for that symbol to the code/data map for the section. */
7169 if (hash_table->vfp11_erratum_glue_size == 0)
7170 {
7171 bh = NULL;
7172 /* FIXME: Creates an ARM symbol. Thumb mode will need attention if it
99059e56 7173 ever requires this erratum fix. */
c7b8f16e
JB		 7174 _bfd_generic_link_add_one_symbol (link_info,
7175 hash_table->bfd_of_glue_owner, "$a",
7176 BSF_LOCAL, s, 0, NULL,
99059e56 7177 TRUE, FALSE, &bh);
c7b8f16e
JB		 7178
7179 myh = (struct elf_link_hash_entry *) bh;
7180 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7181 myh->forced_local = 1;
906e58ca 7182
c7b8f16e 7183 /* The elf32_arm_init_maps function only cares about symbols from input
99059e56
RM		 7184 BFDs. We must make a note of this generated mapping symbol
7185 ourselves so that code byteswapping works properly in
7186 elf32_arm_write_section. */
c7b8f16e
JB		 7187 elf32_arm_section_map_add (s, 'a', 0);
7188 }
906e58ca 7189
c7b8f16e
JB		 7190 s->size += VFP11_ERRATUM_VENEER_SIZE;
7191 hash_table->vfp11_erratum_glue_size += VFP11_ERRATUM_VENEER_SIZE;
7192 hash_table->num_vfp11_fixes++;
906e58ca 7193
c7b8f16e
JB		 7194 /* The offset of the veneer. */
7195 return val;
7196}
7197
a504d23a
LA		 7198/* Record information about a STM32L4XX STM erratum veneer. Only THUMB-mode
7199 veneers need to be handled because used only in Cortex-M. */
7200
7201static bfd_vma
7202record_stm32l4xx_erratum_veneer (struct bfd_link_info *link_info,
7203 elf32_stm32l4xx_erratum_list *branch,
7204 bfd *branch_bfd,
7205 asection *branch_sec,
7206 unsigned int offset,
7207 bfd_size_type veneer_size)
7208{
7209 asection *s;
7210 struct elf32_arm_link_hash_table *hash_table;
7211 char *tmp_name;
7212 struct elf_link_hash_entry *myh;
7213 struct bfd_link_hash_entry *bh;
7214 bfd_vma val;
7215 struct _arm_elf_section_data *sec_data;
7216 elf32_stm32l4xx_erratum_list *newerr;
7217
7218 hash_table = elf32_arm_hash_table (link_info);
7219 BFD_ASSERT (hash_table != NULL);
7220 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
7221
7222 s = bfd_get_linker_section
7223 (hash_table->bfd_of_glue_owner, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
7224
7225 BFD_ASSERT (s != NULL);
7226
7227 sec_data = elf32_arm_section_data (s);
7228
7229 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
7230 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
7231
7232 BFD_ASSERT (tmp_name);
7233
7234 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
7235 hash_table->num_stm32l4xx_fixes);
7236
7237 myh = elf_link_hash_lookup
7238 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7239
7240 BFD_ASSERT (myh == NULL);
7241
7242 bh = NULL;
7243 val = hash_table->stm32l4xx_erratum_glue_size;
7244 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
7245 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7246 NULL, TRUE, FALSE, &bh);
7247
7248 myh = (struct elf_link_hash_entry *) bh;
7249 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7250 myh->forced_local = 1;
7251
7252 /* Link veneer back to calling location. */
7253 sec_data->stm32l4xx_erratumcount += 1;
7254 newerr = (elf32_stm32l4xx_erratum_list *)
7255 bfd_zmalloc (sizeof (elf32_stm32l4xx_erratum_list));
7256
7257 newerr->type = STM32L4XX_ERRATUM_VENEER;
7258 newerr->vma = -1;
7259 newerr->u.v.branch = branch;
7260 newerr->u.v.id = hash_table->num_stm32l4xx_fixes;
7261 branch->u.b.veneer = newerr;
7262
7263 newerr->next = sec_data->stm32l4xx_erratumlist;
7264 sec_data->stm32l4xx_erratumlist = newerr;
7265
7266 /* A symbol for the return from the veneer. */
7267 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
7268 hash_table->num_stm32l4xx_fixes);
7269
7270 myh = elf_link_hash_lookup
7271 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7272
7273 if (myh != NULL)
7274 abort ();
7275
7276 bh = NULL;
7277 val = offset + 4;
7278 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7279 branch_sec, val, NULL, TRUE, FALSE, &bh);
7280
7281 myh = (struct elf_link_hash_entry *) bh;
7282 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7283 myh->forced_local = 1;
7284
7285 free (tmp_name);
7286
7287 /* Generate a mapping symbol for the veneer section, and explicitly add an
7288 entry for that symbol to the code/data map for the section. */
7289 if (hash_table->stm32l4xx_erratum_glue_size == 0)
7290 {
7291 bh = NULL;
7292 /* Creates a THUMB symbol since there is no other choice. */
7293 _bfd_generic_link_add_one_symbol (link_info,
7294 hash_table->bfd_of_glue_owner, "$t",
7295 BSF_LOCAL, s, 0, NULL,
7296 TRUE, FALSE, &bh);
7297
7298 myh = (struct elf_link_hash_entry *) bh;
7299 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7300 myh->forced_local = 1;
7301
7302 /* The elf32_arm_init_maps function only cares about symbols from input
7303 BFDs. We must make a note of this generated mapping symbol
7304 ourselves so that code byteswapping works properly in
7305 elf32_arm_write_section. */
7306 elf32_arm_section_map_add (s, 't', 0);
7307 }
7308
7309 s->size += veneer_size;
7310 hash_table->stm32l4xx_erratum_glue_size += veneer_size;
7311 hash_table->num_stm32l4xx_fixes++;
7312
7313 /* The offset of the veneer. */
7314 return val;
7315}
7316
8029a119 7317#define ARM_GLUE_SECTION_FLAGS \
3e6b1042
DJ		 7318 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_CODE \
7319 | SEC_READONLY | SEC_LINKER_CREATED)
8029a119
NC		 7320
7321/* Create a fake section for use by the ARM backend of the linker. */
7322
7323static bfd_boolean
7324arm_make_glue_section (bfd * abfd, const char * name)
7325{
7326 asection * sec;
7327
3d4d4302 7328 sec = bfd_get_linker_section (abfd, name);
8029a119
NC		 7329 if (sec != NULL)
7330 /* Already made. */
7331 return TRUE;
7332
3d4d4302 7333 sec = bfd_make_section_anyway_with_flags (abfd, name, ARM_GLUE_SECTION_FLAGS);
8029a119
NC		 7334
7335 if (sec == NULL
7336 || !bfd_set_section_alignment (abfd, sec, 2))
7337 return FALSE;
7338
7339 /* Set the gc mark to prevent the section from being removed by garbage
7340 collection, despite the fact that no relocs refer to this section. */
7341 sec->gc_mark = 1;
7342
7343 return TRUE;
7344}
7345
1db37fe6
YG		 7346/* Set size of .plt entries. This function is called from the
7347 linker scripts in ld/emultempl/{armelf}.em. */
7348
7349void
7350bfd_elf32_arm_use_long_plt (void)
7351{
7352 elf32_arm_use_long_plt_entry = TRUE;
7353}
7354
8afb0e02
NC		 7355/* Add the glue sections to ABFD. This function is called from the
7356 linker scripts in ld/emultempl/{armelf}.em. */
9b485d32 7357
b34976b6 7358bfd_boolean
57e8b36a
NC		 7359bfd_elf32_arm_add_glue_sections_to_bfd (bfd *abfd,
7360 struct bfd_link_info *info)
252b5132 7361{
a504d23a
LA		 7362 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
7363 bfd_boolean dostm32l4xx = globals
7364 && globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE;
7365 bfd_boolean addglue;
7366
8afb0e02
NC		 7367 /* If we are only performing a partial
7368 link do not bother adding the glue. */
0e1862bb 7369 if (bfd_link_relocatable (info))
b34976b6 7370 return TRUE;
252b5132 7371
a504d23a 7372 addglue = arm_make_glue_section (abfd, ARM2THUMB_GLUE_SECTION_NAME)
8029a119
NC		 7373 && arm_make_glue_section (abfd, THUMB2ARM_GLUE_SECTION_NAME)
7374 && arm_make_glue_section (abfd, VFP11_ERRATUM_VENEER_SECTION_NAME)
7375 && arm_make_glue_section (abfd, ARM_BX_GLUE_SECTION_NAME);
a504d23a
LA		 7376
7377 if (!dostm32l4xx)
7378 return addglue;
7379
7380 return addglue
7381 && arm_make_glue_section (abfd, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
8afb0e02
NC		 7382}
7383
daa4adae
TP		 7384/* Mark output sections of veneers needing a dedicated one with SEC_KEEP. This
7385 ensures they are not marked for deletion by
7386 strip_excluded_output_sections () when veneers are going to be created
7387 later. Not doing so would trigger assert on empty section size in
7388 lang_size_sections_1 (). */
7389
7390void
7391bfd_elf32_arm_keep_private_stub_output_sections (struct bfd_link_info *info)
7392{
7393 enum elf32_arm_stub_type stub_type;
7394
7395 /* If we are only performing a partial
7396 link do not bother adding the glue. */
7397 if (bfd_link_relocatable (info))
7398 return;
7399
7400 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
7401 {
7402 asection *out_sec;
7403 const char *out_sec_name;
7404
7405 if (!arm_dedicated_stub_output_section_required (stub_type))
7406 continue;
7407
7408 out_sec_name = arm_dedicated_stub_output_section_name (stub_type);
7409 out_sec = bfd_get_section_by_name (info->output_bfd, out_sec_name);
7410 if (out_sec != NULL)
7411 out_sec->flags |= SEC_KEEP;
7412 }
7413}
7414
8afb0e02
NC		 7415/* Select a BFD to be used to hold the sections used by the glue code.
7416 This function is called from the linker scripts in ld/emultempl/
8029a119 7417 {armelf/pe}.em. */
8afb0e02 7418
b34976b6 7419bfd_boolean
57e8b36a 7420bfd_elf32_arm_get_bfd_for_interworking (bfd *abfd, struct bfd_link_info *info)
8afb0e02
NC		 7421{
7422 struct elf32_arm_link_hash_table *globals;
7423
7424 /* If we are only performing a partial link
7425 do not bother getting a bfd to hold the glue. */
0e1862bb 7426 if (bfd_link_relocatable (info))
b34976b6 7427 return TRUE;
8afb0e02 7428
b7693d02
DJ		 7429 /* Make sure we don't attach the glue sections to a dynamic object. */
7430 BFD_ASSERT (!(abfd->flags & DYNAMIC));
7431
8afb0e02 7432 globals = elf32_arm_hash_table (info);
8afb0e02
NC		 7433 BFD_ASSERT (globals != NULL);
7434
7435 if (globals->bfd_of_glue_owner != NULL)
b34976b6 7436 return TRUE;
8afb0e02 7437
252b5132
RH		 7438 /* Save the bfd for later use. */
7439 globals->bfd_of_glue_owner = abfd;
cedb70c5 7440
b34976b6 7441 return TRUE;
252b5132
RH		 7442}
7443
906e58ca
NC		 7444static void
7445check_use_blx (struct elf32_arm_link_hash_table *globals)
39b41c9c 7446{
2de70689
MGD		 7447 int cpu_arch;
7448
b38cadfb 7449 cpu_arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
2de70689
MGD		 7450 Tag_CPU_arch);
7451
7452 if (globals->fix_arm1176)
7453 {
7454 if (cpu_arch == TAG_CPU_ARCH_V6T2 || cpu_arch > TAG_CPU_ARCH_V6K)
7455 globals->use_blx = 1;
7456 }
7457 else
7458 {
7459 if (cpu_arch > TAG_CPU_ARCH_V4T)
7460 globals->use_blx = 1;
7461 }
39b41c9c
PB		 7462}
7463
b34976b6 7464bfd_boolean
57e8b36a 7465bfd_elf32_arm_process_before_allocation (bfd *abfd,
d504ffc8 7466 struct bfd_link_info *link_info)
252b5132
RH		 7467{
7468 Elf_Internal_Shdr *symtab_hdr;
6cdc0ccc 7469 Elf_Internal_Rela *internal_relocs = NULL;
252b5132
RH		 7470 Elf_Internal_Rela *irel, *irelend;
7471 bfd_byte *contents = NULL;
252b5132
RH		 7472
7473 asection *sec;
7474 struct elf32_arm_link_hash_table *globals;
7475
7476 /* If we are only performing a partial link do not bother
7477 to construct any glue. */
0e1862bb 7478 if (bfd_link_relocatable (link_info))
b34976b6 7479 return TRUE;
252b5132 7480
39ce1a6a
NC		 7481 /* Here we have a bfd that is to be included on the link. We have a
7482 hook to do reloc rummaging, before section sizes are nailed down. */
252b5132 7483 globals = elf32_arm_hash_table (link_info);
252b5132 7484 BFD_ASSERT (globals != NULL);
39ce1a6a
NC		 7485
7486 check_use_blx (globals);
252b5132 7487
d504ffc8 7488 if (globals->byteswap_code && !bfd_big_endian (abfd))
e489d0ae 7489 {
d003868e
AM		 7490 _bfd_error_handler (_("%B: BE8 images only valid in big-endian mode."),
7491 abfd);
e489d0ae
PB		 7492 return FALSE;
7493 }
f21f3fe0 7494
39ce1a6a
NC		 7495 /* PR 5398: If we have not decided to include any loadable sections in
7496 the output then we will not have a glue owner bfd. This is OK, it
7497 just means that there is nothing else for us to do here. */
7498 if (globals->bfd_of_glue_owner == NULL)
7499 return TRUE;
7500
252b5132
RH		 7501 /* Rummage around all the relocs and map the glue vectors. */
7502 sec = abfd->sections;
7503
7504 if (sec == NULL)
b34976b6 7505 return TRUE;
252b5132
RH		 7506
7507 for (; sec != NULL; sec = sec->next)
7508 {
7509 if (sec->reloc_count == 0)
7510 continue;
7511
2f475487
AM		 7512 if ((sec->flags & SEC_EXCLUDE) != 0)
7513 continue;
7514
0ffa91dd 7515 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 7516
9b485d32 7517 /* Load the relocs. */
6cdc0ccc 7518 internal_relocs
906e58ca 7519 = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, FALSE);
252b5132 7520
6cdc0ccc
AM		 7521 if (internal_relocs == NULL)
7522 goto error_return;
252b5132 7523
6cdc0ccc
AM		 7524 irelend = internal_relocs + sec->reloc_count;
7525 for (irel = internal_relocs; irel < irelend; irel++)
252b5132
RH		 7526 {
7527 long r_type;
7528 unsigned long r_index;
252b5132
RH		 7529
7530 struct elf_link_hash_entry *h;
7531
7532 r_type = ELF32_R_TYPE (irel->r_info);
7533 r_index = ELF32_R_SYM (irel->r_info);
7534
9b485d32 7535 /* These are the only relocation types we care about. */
ba96a88f 7536 if ( r_type != R_ARM_PC24
845b51d6 7537 && (r_type != R_ARM_V4BX || globals->fix_v4bx < 2))
252b5132
RH		 7538 continue;
7539
7540 /* Get the section contents if we haven't done so already. */
7541 if (contents == NULL)
7542 {
7543 /* Get cached copy if it exists. */
7544 if (elf_section_data (sec)->this_hdr.contents != NULL)
7545 contents = elf_section_data (sec)->this_hdr.contents;
7546 else
7547 {
7548 /* Go get them off disk. */
57e8b36a 7549 if (! bfd_malloc_and_get_section (abfd, sec, &contents))
252b5132
RH		 7550 goto error_return;
7551 }
7552 }
7553
845b51d6
PB		 7554 if (r_type == R_ARM_V4BX)
7555 {
7556 int reg;
7557
7558 reg = bfd_get_32 (abfd, contents + irel->r_offset) & 0xf;
7559 record_arm_bx_glue (link_info, reg);
7560 continue;
7561 }
7562
a7c10850 7563 /* If the relocation is not against a symbol it cannot concern us. */
252b5132
RH		 7564 h = NULL;
7565
9b485d32 7566 /* We don't care about local symbols. */
252b5132
RH		 7567 if (r_index < symtab_hdr->sh_info)
7568 continue;
7569
9b485d32 7570 /* This is an external symbol. */
252b5132
RH		 7571 r_index -= symtab_hdr->sh_info;
7572 h = (struct elf_link_hash_entry *)
7573 elf_sym_hashes (abfd)[r_index];
7574
7575 /* If the relocation is against a static symbol it must be within
7576 the current section and so cannot be a cross ARM/Thumb relocation. */
7577 if (h == NULL)
7578 continue;
7579
d504ffc8
DJ		 7580 /* If the call will go through a PLT entry then we do not need
7581 glue. */
362d30a1 7582 if (globals->root.splt != NULL && h->plt.offset != (bfd_vma) -1)
b7693d02
DJ		 7583 continue;
7584
252b5132
RH		 7585 switch (r_type)
7586 {
7587 case R_ARM_PC24:
7588 /* This one is a call from arm code. We need to look up
99059e56
RM		 7589 the target of the call. If it is a thumb target, we
7590 insert glue. */
39d911fc
TP		 7591 if (ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
7592 == ST_BRANCH_TO_THUMB)
252b5132
RH		 7593 record_arm_to_thumb_glue (link_info, h);
7594 break;
7595
252b5132 7596 default:
c6596c5e 7597 abort ();
252b5132
RH		 7598 }
7599 }
6cdc0ccc
AM		 7600
7601 if (contents != NULL
7602 && elf_section_data (sec)->this_hdr.contents != contents)
7603 free (contents);
7604 contents = NULL;
7605
7606 if (internal_relocs != NULL
7607 && elf_section_data (sec)->relocs != internal_relocs)
7608 free (internal_relocs);
7609 internal_relocs = NULL;
252b5132
RH		 7610 }
7611
b34976b6 7612 return TRUE;
9a5aca8c 7613
252b5132 7614error_return:
6cdc0ccc
AM		 7615 if (contents != NULL
7616 && elf_section_data (sec)->this_hdr.contents != contents)
7617 free (contents);
7618 if (internal_relocs != NULL
7619 && elf_section_data (sec)->relocs != internal_relocs)
7620 free (internal_relocs);
9a5aca8c 7621
b34976b6 7622 return FALSE;
252b5132 7623}
7e392df6 7624#endif
252b5132 7625
eb043451 7626
c7b8f16e
JB		 7627/* Initialise maps of ARM/Thumb/data for input BFDs. */
7628
7629void
7630bfd_elf32_arm_init_maps (bfd *abfd)
7631{
7632 Elf_Internal_Sym *isymbuf;
7633 Elf_Internal_Shdr *hdr;
7634 unsigned int i, localsyms;
7635
af1f4419
NC		 7636 /* PR 7093: Make sure that we are dealing with an arm elf binary. */
7637 if (! is_arm_elf (abfd))
7638 return;
7639
c7b8f16e
JB		 7640 if ((abfd->flags & DYNAMIC) != 0)
7641 return;
7642
0ffa91dd 7643 hdr = & elf_symtab_hdr (abfd);
c7b8f16e
JB		 7644 localsyms = hdr->sh_info;
7645
7646 /* Obtain a buffer full of symbols for this BFD. The hdr->sh_info field
7647 should contain the number of local symbols, which should come before any
7648 global symbols. Mapping symbols are always local. */
7649 isymbuf = bfd_elf_get_elf_syms (abfd, hdr, localsyms, 0, NULL, NULL,
7650 NULL);
7651
7652 /* No internal symbols read? Skip this BFD. */
7653 if (isymbuf == NULL)
7654 return;
7655
7656 for (i = 0; i < localsyms; i++)
7657 {
7658 Elf_Internal_Sym *isym = &isymbuf[i];
7659 asection *sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
7660 const char *name;
906e58ca 7661
c7b8f16e 7662 if (sec != NULL
99059e56
RM		 7663 && ELF_ST_BIND (isym->st_info) == STB_LOCAL)
7664 {
7665 name = bfd_elf_string_from_elf_section (abfd,
7666 hdr->sh_link, isym->st_name);
906e58ca 7667
99059e56 7668 if (bfd_is_arm_special_symbol_name (name,
c7b8f16e 7669 BFD_ARM_SPECIAL_SYM_TYPE_MAP))
99059e56
RM		 7670 elf32_arm_section_map_add (sec, name[1], isym->st_value);
7671 }
c7b8f16e
JB		 7672 }
7673}
7674
7675
48229727
JB		 7676/* Auto-select enabling of Cortex-A8 erratum fix if the user didn't explicitly
7677 say what they wanted. */
7678
7679void
7680bfd_elf32_arm_set_cortex_a8_fix (bfd *obfd, struct bfd_link_info *link_info)
7681{
7682 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
7683 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
7684
4dfe6ac6
NC		 7685 if (globals == NULL)
7686 return;
7687
48229727
JB		 7688 if (globals->fix_cortex_a8 == -1)
7689 {
7690 /* Turn on Cortex-A8 erratum workaround for ARMv7-A. */
7691 if (out_attr[Tag_CPU_arch].i == TAG_CPU_ARCH_V7
7692 && (out_attr[Tag_CPU_arch_profile].i == 'A'
7693 || out_attr[Tag_CPU_arch_profile].i == 0))
7694 globals->fix_cortex_a8 = 1;
7695 else
7696 globals->fix_cortex_a8 = 0;
7697 }
7698}
7699
7700
c7b8f16e
JB		 7701void
7702bfd_elf32_arm_set_vfp11_fix (bfd *obfd, struct bfd_link_info *link_info)
7703{
7704 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
104d59d1 7705 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
906e58ca 7706
4dfe6ac6
NC		 7707 if (globals == NULL)
7708 return;
c7b8f16e
JB		 7709 /* We assume that ARMv7+ does not need the VFP11 denorm erratum fix. */
7710 if (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V7)
7711 {
7712 switch (globals->vfp11_fix)
99059e56
RM		 7713 {
7714 case BFD_ARM_VFP11_FIX_DEFAULT:
7715 case BFD_ARM_VFP11_FIX_NONE:
7716 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
7717 break;
7718
7719 default:
7720 /* Give a warning, but do as the user requests anyway. */
7721 (*_bfd_error_handler) (_("%B: warning: selected VFP11 erratum "
7722 "workaround is not necessary for target architecture"), obfd);
7723 }
c7b8f16e
JB		 7724 }
7725 else if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_DEFAULT)
7726 /* For earlier architectures, we might need the workaround, but do not
7727 enable it by default. If users is running with broken hardware, they
7728 must enable the erratum fix explicitly. */
7729 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
7730}
7731
a504d23a
LA		 7732void
7733bfd_elf32_arm_set_stm32l4xx_fix (bfd *obfd, struct bfd_link_info *link_info)
7734{
7735 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
7736 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
7737
7738 if (globals == NULL)
7739 return;
7740
7741 /* We assume only Cortex-M4 may require the fix. */
7742 if (out_attr[Tag_CPU_arch].i != TAG_CPU_ARCH_V7E_M
7743 || out_attr[Tag_CPU_arch_profile].i != 'M')
7744 {
7745 if (globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE)
7746 /* Give a warning, but do as the user requests anyway. */
7747 (*_bfd_error_handler)
7748 (_("%B: warning: selected STM32L4XX erratum "
7749 "workaround is not necessary for target architecture"), obfd);
7750 }
7751}
c7b8f16e 7752
906e58ca
NC		 7753enum bfd_arm_vfp11_pipe
7754{
c7b8f16e
JB		 7755 VFP11_FMAC,
7756 VFP11_LS,
7757 VFP11_DS,
7758 VFP11_BAD
7759};
7760
7761/* Return a VFP register number. This is encoded as RX:X for single-precision
7762 registers, or X:RX for double-precision registers, where RX is the group of
7763 four bits in the instruction encoding and X is the single extension bit.
7764 RX and X fields are specified using their lowest (starting) bit. The return
7765 value is:
7766
7767 0...31: single-precision registers s0...s31
7768 32...63: double-precision registers d0...d31.
906e58ca 7769
c7b8f16e
JB		 7770 Although X should be zero for VFP11 (encoding d0...d15 only), we might
7771 encounter VFP3 instructions, so we allow the full range for DP registers. */
906e58ca 7772
c7b8f16e
JB		 7773static unsigned int
7774bfd_arm_vfp11_regno (unsigned int insn, bfd_boolean is_double, unsigned int rx,
99059e56 7775 unsigned int x)
c7b8f16e
JB		 7776{
7777 if (is_double)
7778 return (((insn >> rx) & 0xf) | (((insn >> x) & 1) << 4)) + 32;
7779 else
7780 return (((insn >> rx) & 0xf) << 1) | ((insn >> x) & 1);
7781}
7782
7783/* Set bits in *WMASK according to a register number REG as encoded by
7784 bfd_arm_vfp11_regno(). Ignore d16-d31. */
7785
7786static void
7787bfd_arm_vfp11_write_mask (unsigned int *wmask, unsigned int reg)
7788{
7789 if (reg < 32)
7790 *wmask |= 1 << reg;
7791 else if (reg < 48)
7792 *wmask |= 3 << ((reg - 32) * 2);
7793}
7794
7795/* Return TRUE if WMASK overwrites anything in REGS. */
7796
7797static bfd_boolean
7798bfd_arm_vfp11_antidependency (unsigned int wmask, int *regs, int numregs)
7799{
7800 int i;
906e58ca 7801
c7b8f16e
JB		 7802 for (i = 0; i < numregs; i++)
7803 {
7804 unsigned int reg = regs[i];
7805
7806 if (reg < 32 && (wmask & (1 << reg)) != 0)
99059e56 7807 return TRUE;
906e58ca 7808
c7b8f16e
JB		 7809 reg -= 32;
7810
7811 if (reg >= 16)
99059e56 7812 continue;
906e58ca 7813
c7b8f16e 7814 if ((wmask & (3 << (reg * 2))) != 0)
99059e56 7815 return TRUE;
c7b8f16e 7816 }
906e58ca 7817
c7b8f16e
JB		 7818 return FALSE;
7819}
7820
7821/* In this function, we're interested in two things: finding input registers
7822 for VFP data-processing instructions, and finding the set of registers which
7823 arbitrary VFP instructions may write to. We use a 32-bit unsigned int to
7824 hold the written set, so FLDM etc. are easy to deal with (we're only
7825 interested in 32 SP registers or 16 dp registers, due to the VFP version
7826 implemented by the chip in question). DP registers are marked by setting
7827 both SP registers in the write mask). */
7828
7829static enum bfd_arm_vfp11_pipe
7830bfd_arm_vfp11_insn_decode (unsigned int insn, unsigned int *destmask, int *regs,
99059e56 7831 int *numregs)
c7b8f16e 7832{
91d6fa6a 7833 enum bfd_arm_vfp11_pipe vpipe = VFP11_BAD;
c7b8f16e
JB		 7834 bfd_boolean is_double = ((insn & 0xf00) == 0xb00) ? 1 : 0;
7835
7836 if ((insn & 0x0f000e10) == 0x0e000a00) /* A data-processing insn. */
7837 {
7838 unsigned int pqrs;
7839 unsigned int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
7840 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
7841
7842 pqrs = ((insn & 0x00800000) >> 20)
99059e56
RM		 7843 | ((insn & 0x00300000) >> 19)
7844 | ((insn & 0x00000040) >> 6);
c7b8f16e
JB		 7845
7846 switch (pqrs)
99059e56
RM		 7847 {
7848 case 0: /* fmac[sd]. */
7849 case 1: /* fnmac[sd]. */
7850 case 2: /* fmsc[sd]. */
7851 case 3: /* fnmsc[sd]. */
7852 vpipe = VFP11_FMAC;
7853 bfd_arm_vfp11_write_mask (destmask, fd);
7854 regs[0] = fd;
7855 regs[1] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
7856 regs[2] = fm;
7857 *numregs = 3;
7858 break;
7859
7860 case 4: /* fmul[sd]. */
7861 case 5: /* fnmul[sd]. */
7862 case 6: /* fadd[sd]. */
7863 case 7: /* fsub[sd]. */
7864 vpipe = VFP11_FMAC;
7865 goto vfp_binop;
7866
7867 case 8: /* fdiv[sd]. */
7868 vpipe = VFP11_DS;
7869 vfp_binop:
7870 bfd_arm_vfp11_write_mask (destmask, fd);
7871 regs[0] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
7872 regs[1] = fm;
7873 *numregs = 2;
7874 break;
7875
7876 case 15: /* extended opcode. */
7877 {
7878 unsigned int extn = ((insn >> 15) & 0x1e)
7879 | ((insn >> 7) & 1);
7880
7881 switch (extn)
7882 {
7883 case 0: /* fcpy[sd]. */
7884 case 1: /* fabs[sd]. */
7885 case 2: /* fneg[sd]. */
7886 case 8: /* fcmp[sd]. */
7887 case 9: /* fcmpe[sd]. */
7888 case 10: /* fcmpz[sd]. */
7889 case 11: /* fcmpez[sd]. */
7890 case 16: /* fuito[sd]. */
7891 case 17: /* fsito[sd]. */
7892 case 24: /* ftoui[sd]. */
7893 case 25: /* ftouiz[sd]. */
7894 case 26: /* ftosi[sd]. */
7895 case 27: /* ftosiz[sd]. */
7896 /* These instructions will not bounce due to underflow. */
7897 *numregs = 0;
7898 vpipe = VFP11_FMAC;
7899 break;
7900
7901 case 3: /* fsqrt[sd]. */
7902 /* fsqrt cannot underflow, but it can (perhaps) overwrite
7903 registers to cause the erratum in previous instructions. */
7904 bfd_arm_vfp11_write_mask (destmask, fd);
7905 vpipe = VFP11_DS;
7906 break;
7907
7908 case 15: /* fcvt{ds,sd}. */
7909 {
7910 int rnum = 0;
7911
7912 bfd_arm_vfp11_write_mask (destmask, fd);
c7b8f16e
JB		 7913
7914 /* Only FCVTSD can underflow. */
99059e56
RM		 7915 if ((insn & 0x100) != 0)
7916 regs[rnum++] = fm;
c7b8f16e 7917
99059e56 7918 *numregs = rnum;
c7b8f16e 7919
99059e56
RM		 7920 vpipe = VFP11_FMAC;
7921 }
7922 break;
c7b8f16e 7923
99059e56
RM		 7924 default:
7925 return VFP11_BAD;
7926 }
7927 }
7928 break;
c7b8f16e 7929
99059e56
RM		 7930 default:
7931 return VFP11_BAD;
7932 }
c7b8f16e
JB		 7933 }
7934 /* Two-register transfer. */
7935 else if ((insn & 0x0fe00ed0) == 0x0c400a10)
7936 {
7937 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
906e58ca 7938
c7b8f16e
JB		 7939 if ((insn & 0x100000) == 0)
7940 {
99059e56
RM		 7941 if (is_double)
7942 bfd_arm_vfp11_write_mask (destmask, fm);
7943 else
7944 {
7945 bfd_arm_vfp11_write_mask (destmask, fm);
7946 bfd_arm_vfp11_write_mask (destmask, fm + 1);
7947 }
c7b8f16e
JB		 7948 }
7949
91d6fa6a 7950 vpipe = VFP11_LS;
c7b8f16e
JB		 7951 }
7952 else if ((insn & 0x0e100e00) == 0x0c100a00) /* A load insn. */
7953 {
7954 int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
7955 unsigned int puw = ((insn >> 21) & 0x1) | (((insn >> 23) & 3) << 1);
906e58ca 7956
c7b8f16e 7957 switch (puw)
99059e56
RM		 7958 {
7959 case 0: /* Two-reg transfer. We should catch these above. */
7960 abort ();
906e58ca 7961
99059e56
RM		 7962 case 2: /* fldm[sdx]. */
7963 case 3:
7964 case 5:
7965 {
7966 unsigned int i, offset = insn & 0xff;
c7b8f16e 7967
99059e56
RM		 7968 if (is_double)
7969 offset >>= 1;
c7b8f16e 7970
99059e56
RM		 7971 for (i = fd; i < fd + offset; i++)
7972 bfd_arm_vfp11_write_mask (destmask, i);
7973 }
7974 break;
906e58ca 7975
99059e56
RM		 7976 case 4: /* fld[sd]. */
7977 case 6:
7978 bfd_arm_vfp11_write_mask (destmask, fd);
7979 break;
906e58ca 7980
99059e56
RM		 7981 default:
7982 return VFP11_BAD;
7983 }
c7b8f16e 7984
91d6fa6a 7985 vpipe = VFP11_LS;
c7b8f16e
JB		 7986 }
7987 /* Single-register transfer. Note L==0. */
7988 else if ((insn & 0x0f100e10) == 0x0e000a10)
7989 {
7990 unsigned int opcode = (insn >> 21) & 7;
7991 unsigned int fn = bfd_arm_vfp11_regno (insn, is_double, 16, 7);
7992
7993 switch (opcode)
99059e56
RM		 7994 {
7995 case 0: /* fmsr/fmdlr. */
7996 case 1: /* fmdhr. */
7997 /* Mark fmdhr and fmdlr as writing to the whole of the DP
7998 destination register. I don't know if this is exactly right,
7999 but it is the conservative choice. */
8000 bfd_arm_vfp11_write_mask (destmask, fn);
8001 break;
8002
8003 case 7: /* fmxr. */
8004 break;
8005 }
c7b8f16e 8006
91d6fa6a 8007 vpipe = VFP11_LS;
c7b8f16e
JB		 8008 }
8009
91d6fa6a 8010 return vpipe;
c7b8f16e
JB		 8011}
8012
8013
8014static int elf32_arm_compare_mapping (const void * a, const void * b);
8015
8016
8017/* Look for potentially-troublesome code sequences which might trigger the
8018 VFP11 denormal/antidependency erratum. See, e.g., the ARM1136 errata sheet
8019 (available from ARM) for details of the erratum. A short version is
8020 described in ld.texinfo. */
8021
8022bfd_boolean
8023bfd_elf32_arm_vfp11_erratum_scan (bfd *abfd, struct bfd_link_info *link_info)
8024{
8025 asection *sec;
8026 bfd_byte *contents = NULL;
8027 int state = 0;
8028 int regs[3], numregs = 0;
8029 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8030 int use_vector = (globals->vfp11_fix == BFD_ARM_VFP11_FIX_VECTOR);
906e58ca 8031
4dfe6ac6
NC		 8032 if (globals == NULL)
8033 return FALSE;
8034
c7b8f16e
JB		 8035 /* We use a simple FSM to match troublesome VFP11 instruction sequences.
8036 The states transition as follows:
906e58ca 8037
c7b8f16e 8038 0 -> 1 (vector) or 0 -> 2 (scalar)
99059e56
RM		 8039 A VFP FMAC-pipeline instruction has been seen. Fill
8040 regs[0]..regs[numregs-1] with its input operands. Remember this
8041 instruction in 'first_fmac'.
c7b8f16e
JB		 8042
8043 1 -> 2
99059e56
RM		 8044 Any instruction, except for a VFP instruction which overwrites
8045 regs[*].
906e58ca 8046
c7b8f16e
JB		 8047 1 -> 3 [ -> 0 ] or
8048 2 -> 3 [ -> 0 ]
99059e56
RM		 8049 A VFP instruction has been seen which overwrites any of regs[*].
8050 We must make a veneer! Reset state to 0 before examining next
8051 instruction.
906e58ca 8052
c7b8f16e 8053 2 -> 0
99059e56
RM		 8054 If we fail to match anything in state 2, reset to state 0 and reset
8055 the instruction pointer to the instruction after 'first_fmac'.
c7b8f16e
JB		 8056
8057 If the VFP11 vector mode is in use, there must be at least two unrelated
8058 instructions between anti-dependent VFP11 instructions to properly avoid
906e58ca 8059 triggering the erratum, hence the use of the extra state 1. */
c7b8f16e
JB		 8060
8061 /* If we are only performing a partial link do not bother
8062 to construct any glue. */
0e1862bb 8063 if (bfd_link_relocatable (link_info))
c7b8f16e
JB		 8064 return TRUE;
8065
0ffa91dd
NC		 8066 /* Skip if this bfd does not correspond to an ELF image. */
8067 if (! is_arm_elf (abfd))
8068 return TRUE;
906e58ca 8069
c7b8f16e
JB		 8070 /* We should have chosen a fix type by the time we get here. */
8071 BFD_ASSERT (globals->vfp11_fix != BFD_ARM_VFP11_FIX_DEFAULT);
8072
8073 if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_NONE)
8074 return TRUE;
2e6030b9 8075
33a7ffc2
JM		 8076 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8077 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8078 return TRUE;
8079
c7b8f16e
JB		 8080 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8081 {
8082 unsigned int i, span, first_fmac = 0, veneer_of_insn = 0;
8083 struct _arm_elf_section_data *sec_data;
8084
8085 /* If we don't have executable progbits, we're not interested in this
99059e56 8086 section. Also skip if section is to be excluded. */
c7b8f16e 8087 if (elf_section_type (sec) != SHT_PROGBITS
99059e56
RM		 8088 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8089 || (sec->flags & SEC_EXCLUDE) != 0
dbaa2011 8090 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
33a7ffc2 8091 || sec->output_section == bfd_abs_section_ptr
99059e56
RM		 8092 || strcmp (sec->name, VFP11_ERRATUM_VENEER_SECTION_NAME) == 0)
8093 continue;
c7b8f16e
JB		 8094
8095 sec_data = elf32_arm_section_data (sec);
906e58ca 8096
c7b8f16e 8097 if (sec_data->mapcount == 0)
99059e56 8098 continue;
906e58ca 8099
c7b8f16e
JB		 8100 if (elf_section_data (sec)->this_hdr.contents != NULL)
8101 contents = elf_section_data (sec)->this_hdr.contents;
8102 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8103 goto error_return;
8104
8105 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8106 elf32_arm_compare_mapping);
8107
8108 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 8109 {
8110 unsigned int span_start = sec_data->map[span].vma;
8111 unsigned int span_end = (span == sec_data->mapcount - 1)
c7b8f16e 8112 ? sec->size : sec_data->map[span + 1].vma;
99059e56
RM		 8113 char span_type = sec_data->map[span].type;
8114
8115 /* FIXME: Only ARM mode is supported at present. We may need to
8116 support Thumb-2 mode also at some point. */
8117 if (span_type != 'a')
8118 continue;
8119
8120 for (i = span_start; i < span_end;)
8121 {
8122 unsigned int next_i = i + 4;
8123 unsigned int insn = bfd_big_endian (abfd)
8124 ? (contents[i] << 24)
8125 | (contents[i + 1] << 16)
8126 | (contents[i + 2] << 8)
8127 | contents[i + 3]
8128 : (contents[i + 3] << 24)
8129 | (contents[i + 2] << 16)
8130 | (contents[i + 1] << 8)
8131 | contents[i];
8132 unsigned int writemask = 0;
8133 enum bfd_arm_vfp11_pipe vpipe;
8134
8135 switch (state)
8136 {
8137 case 0:
8138 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask, regs,
8139 &numregs);
8140 /* I'm assuming the VFP11 erratum can trigger with denorm
8141 operands on either the FMAC or the DS pipeline. This might
8142 lead to slightly overenthusiastic veneer insertion. */
8143 if (vpipe == VFP11_FMAC || vpipe == VFP11_DS)
8144 {
8145 state = use_vector ? 1 : 2;
8146 first_fmac = i;
8147 veneer_of_insn = insn;
8148 }
8149 break;
8150
8151 case 1:
8152 {
8153 int other_regs[3], other_numregs;
8154 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8155 other_regs,
99059e56
RM		 8156 &other_numregs);
8157 if (vpipe != VFP11_BAD
8158 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8159 numregs))
99059e56
RM		 8160 state = 3;
8161 else
8162 state = 2;
8163 }
8164 break;
8165
8166 case 2:
8167 {
8168 int other_regs[3], other_numregs;
8169 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8170 other_regs,
99059e56
RM		 8171 &other_numregs);
8172 if (vpipe != VFP11_BAD
8173 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8174 numregs))
99059e56
RM		 8175 state = 3;
8176 else
8177 {
8178 state = 0;
8179 next_i = first_fmac + 4;
8180 }
8181 }
8182 break;
8183
8184 case 3:
8185 abort (); /* Should be unreachable. */
8186 }
8187
8188 if (state == 3)
8189 {
8190 elf32_vfp11_erratum_list *newerr =(elf32_vfp11_erratum_list *)
8191 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
8192
8193 elf32_arm_section_data (sec)->erratumcount += 1;
8194
8195 newerr->u.b.vfp_insn = veneer_of_insn;
8196
8197 switch (span_type)
8198 {
8199 case 'a':
8200 newerr->type = VFP11_ERRATUM_BRANCH_TO_ARM_VENEER;
8201 break;
8202
8203 default:
8204 abort ();
8205 }
8206
8207 record_vfp11_erratum_veneer (link_info, newerr, abfd, sec,
c7b8f16e
JB		 8208 first_fmac);
8209
99059e56 8210 newerr->vma = -1;
c7b8f16e 8211
99059e56
RM		 8212 newerr->next = sec_data->erratumlist;
8213 sec_data->erratumlist = newerr;
c7b8f16e 8214
99059e56
RM		 8215 state = 0;
8216 }
c7b8f16e 8217
99059e56
RM		 8218 i = next_i;
8219 }
8220 }
906e58ca 8221
c7b8f16e 8222 if (contents != NULL
99059e56
RM		 8223 && elf_section_data (sec)->this_hdr.contents != contents)
8224 free (contents);
c7b8f16e
JB		 8225 contents = NULL;
8226 }
8227
8228 return TRUE;
8229
8230error_return:
8231 if (contents != NULL
8232 && elf_section_data (sec)->this_hdr.contents != contents)
8233 free (contents);
906e58ca 8234
c7b8f16e
JB		 8235 return FALSE;
8236}
8237
8238/* Find virtual-memory addresses for VFP11 erratum veneers and return locations
8239 after sections have been laid out, using specially-named symbols. */
8240
8241void
8242bfd_elf32_arm_vfp11_fix_veneer_locations (bfd *abfd,
8243 struct bfd_link_info *link_info)
8244{
8245 asection *sec;
8246 struct elf32_arm_link_hash_table *globals;
8247 char *tmp_name;
906e58ca 8248
0e1862bb 8249 if (bfd_link_relocatable (link_info))
c7b8f16e 8250 return;
2e6030b9
MS		 8251
8252 /* Skip if this bfd does not correspond to an ELF image. */
0ffa91dd 8253 if (! is_arm_elf (abfd))
2e6030b9
MS		 8254 return;
8255
c7b8f16e 8256 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8257 if (globals == NULL)
8258 return;
906e58ca 8259
21d799b5 8260 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 8261 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
c7b8f16e
JB		 8262
8263 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8264 {
8265 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8266 elf32_vfp11_erratum_list *errnode = sec_data->erratumlist;
906e58ca 8267
c7b8f16e 8268 for (; errnode != NULL; errnode = errnode->next)
99059e56
RM		 8269 {
8270 struct elf_link_hash_entry *myh;
8271 bfd_vma vma;
8272
8273 switch (errnode->type)
8274 {
8275 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
8276 case VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER:
8277 /* Find veneer symbol. */
8278 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
c7b8f16e
JB		 8279 errnode->u.b.veneer->u.v.id);
8280
99059e56
RM		 8281 myh = elf_link_hash_lookup
8282 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
c7b8f16e 8283
a504d23a
LA		 8284 if (myh == NULL)
8285 (*_bfd_error_handler) (_("%B: unable to find VFP11 veneer "
8286 "`%s'"), abfd, tmp_name);
8287
8288 vma = myh->root.u.def.section->output_section->vma
8289 + myh->root.u.def.section->output_offset
8290 + myh->root.u.def.value;
8291
8292 errnode->u.b.veneer->vma = vma;
8293 break;
8294
8295 case VFP11_ERRATUM_ARM_VENEER:
8296 case VFP11_ERRATUM_THUMB_VENEER:
8297 /* Find return location. */
8298 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
8299 errnode->u.v.id);
8300
8301 myh = elf_link_hash_lookup
8302 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8303
8304 if (myh == NULL)
8305 (*_bfd_error_handler) (_("%B: unable to find VFP11 veneer "
8306 "`%s'"), abfd, tmp_name);
8307
8308 vma = myh->root.u.def.section->output_section->vma
8309 + myh->root.u.def.section->output_offset
8310 + myh->root.u.def.value;
8311
8312 errnode->u.v.branch->vma = vma;
8313 break;
8314
8315 default:
8316 abort ();
8317 }
8318 }
8319 }
8320
8321 free (tmp_name);
8322}
8323
8324/* Find virtual-memory addresses for STM32L4XX erratum veneers and
8325 return locations after sections have been laid out, using
8326 specially-named symbols. */
8327
8328void
8329bfd_elf32_arm_stm32l4xx_fix_veneer_locations (bfd *abfd,
8330 struct bfd_link_info *link_info)
8331{
8332 asection *sec;
8333 struct elf32_arm_link_hash_table *globals;
8334 char *tmp_name;
8335
8336 if (bfd_link_relocatable (link_info))
8337 return;
8338
8339 /* Skip if this bfd does not correspond to an ELF image. */
8340 if (! is_arm_elf (abfd))
8341 return;
8342
8343 globals = elf32_arm_hash_table (link_info);
8344 if (globals == NULL)
8345 return;
8346
8347 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
8348 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
8349
8350 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8351 {
8352 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8353 elf32_stm32l4xx_erratum_list *errnode = sec_data->stm32l4xx_erratumlist;
8354
8355 for (; errnode != NULL; errnode = errnode->next)
8356 {
8357 struct elf_link_hash_entry *myh;
8358 bfd_vma vma;
8359
8360 switch (errnode->type)
8361 {
8362 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
8363 /* Find veneer symbol. */
8364 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
8365 errnode->u.b.veneer->u.v.id);
8366
8367 myh = elf_link_hash_lookup
8368 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8369
8370 if (myh == NULL)
8371 (*_bfd_error_handler) (_("%B: unable to find STM32L4XX veneer "
8372 "`%s'"), abfd, tmp_name);
8373
8374 vma = myh->root.u.def.section->output_section->vma
8375 + myh->root.u.def.section->output_offset
8376 + myh->root.u.def.value;
8377
8378 errnode->u.b.veneer->vma = vma;
8379 break;
8380
8381 case STM32L4XX_ERRATUM_VENEER:
8382 /* Find return location. */
8383 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
8384 errnode->u.v.id);
8385
8386 myh = elf_link_hash_lookup
8387 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8388
8389 if (myh == NULL)
8390 (*_bfd_error_handler) (_("%B: unable to find STM32L4XX veneer "
8391 "`%s'"), abfd, tmp_name);
8392
8393 vma = myh->root.u.def.section->output_section->vma
8394 + myh->root.u.def.section->output_offset
8395 + myh->root.u.def.value;
8396
8397 errnode->u.v.branch->vma = vma;
8398 break;
8399
8400 default:
8401 abort ();
8402 }
8403 }
8404 }
8405
8406 free (tmp_name);
8407}
8408
8409static inline bfd_boolean
8410is_thumb2_ldmia (const insn32 insn)
8411{
8412 /* Encoding T2: LDM<c>.W <Rn>{!},<registers>
8413 1110 - 1000 - 10W1 - rrrr - PM (0) l - llll - llll - llll. */
8414 return (insn & 0xffd02000) == 0xe8900000;
8415}
8416
8417static inline bfd_boolean
8418is_thumb2_ldmdb (const insn32 insn)
8419{
8420 /* Encoding T1: LDMDB<c> <Rn>{!},<registers>
8421 1110 - 1001 - 00W1 - rrrr - PM (0) l - llll - llll - llll. */
8422 return (insn & 0xffd02000) == 0xe9100000;
8423}
8424
8425static inline bfd_boolean
8426is_thumb2_vldm (const insn32 insn)
8427{
8428 /* A6.5 Extension register load or store instruction
8429 A7.7.229
9239bbd3
CM		 8430 We look for SP 32-bit and DP 64-bit registers.
8431 Encoding T1 VLDM{mode}<c> <Rn>{!}, <list>
8432 <list> is consecutive 64-bit registers
8433 1110 - 110P - UDW1 - rrrr - vvvv - 1011 - iiii - iiii
a504d23a
LA		 8434 Encoding T2 VLDM{mode}<c> <Rn>{!}, <list>
8435 <list> is consecutive 32-bit registers
8436 1110 - 110P - UDW1 - rrrr - vvvv - 1010 - iiii - iiii
8437 if P==0 && U==1 && W==1 && Rn=1101 VPOP
8438 if PUW=010 || PUW=011 || PUW=101 VLDM. */
8439 return
9239bbd3
CM		 8440 (((insn & 0xfe100f00) == 0xec100b00) ||
8441 ((insn & 0xfe100f00) == 0xec100a00))
a504d23a
LA		 8442 && /* (IA without !). */
8443 (((((insn << 7) >> 28) & 0xd) == 0x4)
9239bbd3 8444 /* (IA with !), includes VPOP (when reg number is SP). */
a504d23a
LA		 8445 || ((((insn << 7) >> 28) & 0xd) == 0x5)
8446 /* (DB with !). */
8447 || ((((insn << 7) >> 28) & 0xd) == 0x9));
8448}
8449
8450/* STM STM32L4XX erratum : This function assumes that it receives an LDM or
8451 VLDM opcode and:
8452 - computes the number and the mode of memory accesses
8453 - decides if the replacement should be done:
8454 . replaces only if > 8-word accesses
8455 . or (testing purposes only) replaces all accesses. */
8456
8457static bfd_boolean
8458stm32l4xx_need_create_replacing_stub (const insn32 insn,
8459 bfd_arm_stm32l4xx_fix stm32l4xx_fix)
8460{
9239bbd3 8461 int nb_words = 0;
a504d23a
LA		 8462
8463 /* The field encoding the register list is the same for both LDMIA
8464 and LDMDB encodings. */
8465 if (is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn))
9239bbd3 8466 nb_words = popcount (insn & 0x0000ffff);
a504d23a 8467 else if (is_thumb2_vldm (insn))
9239bbd3 8468 nb_words = (insn & 0xff);
a504d23a
LA		 8469
8470 /* DEFAULT mode accounts for the real bug condition situation,
8471 ALL mode inserts stubs for each LDM/VLDM instruction (testing). */
8472 return
9239bbd3 8473 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_DEFAULT) ? nb_words > 8 :
a504d23a
LA		 8474 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_ALL) ? TRUE : FALSE;
8475}
8476
8477/* Look for potentially-troublesome code sequences which might trigger
8478 the STM STM32L4XX erratum. */
8479
8480bfd_boolean
8481bfd_elf32_arm_stm32l4xx_erratum_scan (bfd *abfd,
8482 struct bfd_link_info *link_info)
8483{
8484 asection *sec;
8485 bfd_byte *contents = NULL;
8486 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8487
8488 if (globals == NULL)
8489 return FALSE;
8490
8491 /* If we are only performing a partial link do not bother
8492 to construct any glue. */
8493 if (bfd_link_relocatable (link_info))
8494 return TRUE;
8495
8496 /* Skip if this bfd does not correspond to an ELF image. */
8497 if (! is_arm_elf (abfd))
8498 return TRUE;
8499
8500 if (globals->stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_NONE)
8501 return TRUE;
8502
8503 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8504 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8505 return TRUE;
8506
8507 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8508 {
8509 unsigned int i, span;
8510 struct _arm_elf_section_data *sec_data;
8511
8512 /* If we don't have executable progbits, we're not interested in this
8513 section. Also skip if section is to be excluded. */
8514 if (elf_section_type (sec) != SHT_PROGBITS
8515 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8516 || (sec->flags & SEC_EXCLUDE) != 0
8517 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
8518 || sec->output_section == bfd_abs_section_ptr
8519 || strcmp (sec->name, STM32L4XX_ERRATUM_VENEER_SECTION_NAME) == 0)
8520 continue;
8521
8522 sec_data = elf32_arm_section_data (sec);
c7b8f16e 8523
a504d23a
LA		 8524 if (sec_data->mapcount == 0)
8525 continue;
c7b8f16e 8526
a504d23a
LA		 8527 if (elf_section_data (sec)->this_hdr.contents != NULL)
8528 contents = elf_section_data (sec)->this_hdr.contents;
8529 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8530 goto error_return;
c7b8f16e 8531
a504d23a
LA		 8532 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8533 elf32_arm_compare_mapping);
c7b8f16e 8534
a504d23a
LA		 8535 for (span = 0; span < sec_data->mapcount; span++)
8536 {
8537 unsigned int span_start = sec_data->map[span].vma;
8538 unsigned int span_end = (span == sec_data->mapcount - 1)
8539 ? sec->size : sec_data->map[span + 1].vma;
8540 char span_type = sec_data->map[span].type;
8541 int itblock_current_pos = 0;
c7b8f16e 8542
a504d23a
LA		 8543 /* Only Thumb2 mode need be supported with this CM4 specific
8544 code, we should not encounter any arm mode eg span_type
8545 != 'a'. */
8546 if (span_type != 't')
8547 continue;
c7b8f16e 8548
a504d23a
LA		 8549 for (i = span_start; i < span_end;)
8550 {
8551 unsigned int insn = bfd_get_16 (abfd, &contents[i]);
8552 bfd_boolean insn_32bit = FALSE;
8553 bfd_boolean is_ldm = FALSE;
8554 bfd_boolean is_vldm = FALSE;
8555 bfd_boolean is_not_last_in_it_block = FALSE;
8556
8557 /* The first 16-bits of all 32-bit thumb2 instructions start
8558 with opcode[15..13]=0b111 and the encoded op1 can be anything
8559 except opcode[12..11]!=0b00.
8560 See 32-bit Thumb instruction encoding. */
8561 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
8562 insn_32bit = TRUE;
c7b8f16e 8563
a504d23a
LA		 8564 /* Compute the predicate that tells if the instruction
8565 is concerned by the IT block
8566 - Creates an error if there is a ldm that is not
8567 last in the IT block thus cannot be replaced
8568 - Otherwise we can create a branch at the end of the
8569 IT block, it will be controlled naturally by IT
8570 with the proper pseudo-predicate
8571 - So the only interesting predicate is the one that
8572 tells that we are not on the last item of an IT
8573 block. */
8574 if (itblock_current_pos != 0)
8575 is_not_last_in_it_block = !!--itblock_current_pos;
906e58ca 8576
a504d23a
LA		 8577 if (insn_32bit)
8578 {
8579 /* Load the rest of the insn (in manual-friendly order). */
8580 insn = (insn << 16) | bfd_get_16 (abfd, &contents[i + 2]);
8581 is_ldm = is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn);
8582 is_vldm = is_thumb2_vldm (insn);
8583
8584 /* Veneers are created for (v)ldm depending on
8585 option flags and memory accesses conditions; but
8586 if the instruction is not the last instruction of
8587 an IT block, we cannot create a jump there, so we
8588 bail out. */
8589 if ((is_ldm || is_vldm) &&
8590 stm32l4xx_need_create_replacing_stub
8591 (insn, globals->stm32l4xx_fix))
8592 {
8593 if (is_not_last_in_it_block)
8594 {
8595 (*_bfd_error_handler)
8596 /* Note - overlong line used here to allow for translation. */
8597 (_("\
8598%B(%A+0x%lx): error: multiple load detected in non-last IT block instruction : STM32L4XX veneer cannot be generated.\n"
8599 "Use gcc option -mrestrict-it to generate only one instruction per IT block.\n"),
8600 abfd, sec, (long)i);
8601 }
8602 else
8603 {
8604 elf32_stm32l4xx_erratum_list *newerr =
8605 (elf32_stm32l4xx_erratum_list *)
8606 bfd_zmalloc
8607 (sizeof (elf32_stm32l4xx_erratum_list));
8608
8609 elf32_arm_section_data (sec)
8610 ->stm32l4xx_erratumcount += 1;
8611 newerr->u.b.insn = insn;
8612 /* We create only thumb branches. */
8613 newerr->type =
8614 STM32L4XX_ERRATUM_BRANCH_TO_VENEER;
8615 record_stm32l4xx_erratum_veneer
8616 (link_info, newerr, abfd, sec,
8617 i,
8618 is_ldm ?
8619 STM32L4XX_ERRATUM_LDM_VENEER_SIZE:
8620 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
8621 newerr->vma = -1;
8622 newerr->next = sec_data->stm32l4xx_erratumlist;
8623 sec_data->stm32l4xx_erratumlist = newerr;
8624 }
8625 }
8626 }
8627 else
8628 {
8629 /* A7.7.37 IT p208
8630 IT blocks are only encoded in T1
8631 Encoding T1: IT{x{y{z}}} <firstcond>
8632 1 0 1 1 - 1 1 1 1 - firstcond - mask
8633 if mask = '0000' then see 'related encodings'
8634 We don't deal with UNPREDICTABLE, just ignore these.
8635 There can be no nested IT blocks so an IT block
8636 is naturally a new one for which it is worth
8637 computing its size. */
8638 bfd_boolean is_newitblock = ((insn & 0xff00) == 0xbf00) &&
8639 ((insn & 0x000f) != 0x0000);
8640 /* If we have a new IT block we compute its size. */
8641 if (is_newitblock)
8642 {
8643 /* Compute the number of instructions controlled
8644 by the IT block, it will be used to decide
8645 whether we are inside an IT block or not. */
8646 unsigned int mask = insn & 0x000f;
8647 itblock_current_pos = 4 - ctz (mask);
8648 }
8649 }
8650
8651 i += insn_32bit ? 4 : 2;
99059e56
RM		 8652 }
8653 }
a504d23a
LA		 8654
8655 if (contents != NULL
8656 && elf_section_data (sec)->this_hdr.contents != contents)
8657 free (contents);
8658 contents = NULL;
c7b8f16e 8659 }
906e58ca 8660
a504d23a
LA		 8661 return TRUE;
8662
8663error_return:
8664 if (contents != NULL
8665 && elf_section_data (sec)->this_hdr.contents != contents)
8666 free (contents);
c7b8f16e 8667
a504d23a
LA		 8668 return FALSE;
8669}
c7b8f16e 8670
eb043451
PB		 8671/* Set target relocation values needed during linking. */
8672
8673void
bf21ed78
MS		 8674bfd_elf32_arm_set_target_relocs (struct bfd *output_bfd,
8675 struct bfd_link_info *link_info,
eb043451 8676 int target1_is_rel,
319850b4 8677 char * target2_type,
99059e56 8678 int fix_v4bx,
c7b8f16e 8679 int use_blx,
99059e56 8680 bfd_arm_vfp11_fix vfp11_fix,
a504d23a 8681 bfd_arm_stm32l4xx_fix stm32l4xx_fix,
a9dc9481 8682 int no_enum_warn, int no_wchar_warn,
2de70689 8683 int pic_veneer, int fix_cortex_a8,
0955507f
TP		 8684 int fix_arm1176, int cmse_implib,
8685 bfd *in_implib_bfd)
eb043451
PB		 8686{
8687 struct elf32_arm_link_hash_table *globals;
8688
8689 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8690 if (globals == NULL)
8691 return;
eb043451
PB		 8692
8693 globals->target1_is_rel = target1_is_rel;
8694 if (strcmp (target2_type, "rel") == 0)
8695 globals->target2_reloc = R_ARM_REL32;
eeac373a
PB		 8696 else if (strcmp (target2_type, "abs") == 0)
8697 globals->target2_reloc = R_ARM_ABS32;
eb043451
PB		 8698 else if (strcmp (target2_type, "got-rel") == 0)
8699 globals->target2_reloc = R_ARM_GOT_PREL;
8700 else
8701 {
8702 _bfd_error_handler (_("Invalid TARGET2 relocation type '%s'."),
8703 target2_type);
8704 }
319850b4 8705 globals->fix_v4bx = fix_v4bx;
33bfe774 8706 globals->use_blx |= use_blx;
c7b8f16e 8707 globals->vfp11_fix = vfp11_fix;
a504d23a 8708 globals->stm32l4xx_fix = stm32l4xx_fix;
27e55c4d 8709 globals->pic_veneer = pic_veneer;
48229727 8710 globals->fix_cortex_a8 = fix_cortex_a8;
2de70689 8711 globals->fix_arm1176 = fix_arm1176;
54ddd295 8712 globals->cmse_implib = cmse_implib;
0955507f 8713 globals->in_implib_bfd = in_implib_bfd;
bf21ed78 8714
0ffa91dd
NC		 8715 BFD_ASSERT (is_arm_elf (output_bfd));
8716 elf_arm_tdata (output_bfd)->no_enum_size_warning = no_enum_warn;
a9dc9481 8717 elf_arm_tdata (output_bfd)->no_wchar_size_warning = no_wchar_warn;
eb043451 8718}
eb043451 8719
12a0a0fd 8720/* Replace the target offset of a Thumb bl or b.w instruction. */
252b5132 8721
12a0a0fd
PB		 8722static void
8723insert_thumb_branch (bfd *abfd, long int offset, bfd_byte *insn)
8724{
8725 bfd_vma upper;
8726 bfd_vma lower;
8727 int reloc_sign;
8728
8729 BFD_ASSERT ((offset & 1) == 0);
8730
8731 upper = bfd_get_16 (abfd, insn);
8732 lower = bfd_get_16 (abfd, insn + 2);
8733 reloc_sign = (offset < 0) ? 1 : 0;
8734 upper = (upper & ~(bfd_vma) 0x7ff)
8735 | ((offset >> 12) & 0x3ff)
8736 | (reloc_sign << 10);
906e58ca 8737 lower = (lower & ~(bfd_vma) 0x2fff)
12a0a0fd
PB		 8738 | (((!((offset >> 23) & 1)) ^ reloc_sign) << 13)
8739 | (((!((offset >> 22) & 1)) ^ reloc_sign) << 11)
8740 | ((offset >> 1) & 0x7ff);
8741 bfd_put_16 (abfd, upper, insn);
8742 bfd_put_16 (abfd, lower, insn + 2);
252b5132
RH		 8743}
8744
9b485d32
NC		 8745/* Thumb code calling an ARM function. */
8746
252b5132 8747static int
57e8b36a
NC		 8748elf32_thumb_to_arm_stub (struct bfd_link_info * info,
8749 const char * name,
8750 bfd * input_bfd,
8751 bfd * output_bfd,
8752 asection * input_section,
8753 bfd_byte * hit_data,
8754 asection * sym_sec,
8755 bfd_vma offset,
8756 bfd_signed_vma addend,
f2a9dd69
DJ		 8757 bfd_vma val,
8758 char **error_message)
252b5132 8759{
bcbdc74c 8760 asection * s = 0;
dc810e39 8761 bfd_vma my_offset;
252b5132 8762 long int ret_offset;
bcbdc74c
NC		 8763 struct elf_link_hash_entry * myh;
8764 struct elf32_arm_link_hash_table * globals;
252b5132 8765
f2a9dd69 8766 myh = find_thumb_glue (info, name, error_message);
252b5132 8767 if (myh == NULL)
b34976b6 8768 return FALSE;
252b5132
RH		 8769
8770 globals = elf32_arm_hash_table (info);
252b5132
RH		 8771 BFD_ASSERT (globals != NULL);
8772 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8773
8774 my_offset = myh->root.u.def.value;
8775
3d4d4302
AM		 8776 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
8777 THUMB2ARM_GLUE_SECTION_NAME);
252b5132
RH		 8778
8779 BFD_ASSERT (s != NULL);
8780 BFD_ASSERT (s->contents != NULL);
8781 BFD_ASSERT (s->output_section != NULL);
8782
8783 if ((my_offset & 0x01) == 0x01)
8784 {
8785 if (sym_sec != NULL
8786 && sym_sec->owner != NULL
8787 && !INTERWORK_FLAG (sym_sec->owner))
8788 {
8f615d07 8789 (*_bfd_error_handler)
d003868e 8790 (_("%B(%s): warning: interworking not enabled.\n"
3aaeb7d3 8791 " first occurrence: %B: Thumb call to ARM"),
d003868e 8792 sym_sec->owner, input_bfd, name);
252b5132 8793
b34976b6 8794 return FALSE;
252b5132
RH		 8795 }
8796
8797 --my_offset;
8798 myh->root.u.def.value = my_offset;
8799
52ab56c2
PB		 8800 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a1_bx_pc_insn,
8801 s->contents + my_offset);
252b5132 8802
52ab56c2
PB		 8803 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a2_noop_insn,
8804 s->contents + my_offset + 2);
252b5132
RH		 8805
8806 ret_offset =
9b485d32
NC		 8807 /* Address of destination of the stub. */
8808 ((bfd_signed_vma) val)
252b5132 8809 - ((bfd_signed_vma)
57e8b36a
NC		 8810 /* Offset from the start of the current section
8811 to the start of the stubs. */
9b485d32
NC		 8812 (s->output_offset
8813 /* Offset of the start of this stub from the start of the stubs. */
8814 + my_offset
8815 /* Address of the start of the current section. */
8816 + s->output_section->vma)
8817 /* The branch instruction is 4 bytes into the stub. */
8818 + 4
8819 /* ARM branches work from the pc of the instruction + 8. */
8820 + 8);
252b5132 8821
52ab56c2
PB		 8822 put_arm_insn (globals, output_bfd,
8823 (bfd_vma) t2a3_b_insn | ((ret_offset >> 2) & 0x00FFFFFF),
8824 s->contents + my_offset + 4);
252b5132
RH		 8825 }
8826
8827 BFD_ASSERT (my_offset <= globals->thumb_glue_size);
8828
427bfd90
NC		 8829 /* Now go back and fix up the original BL insn to point to here. */
8830 ret_offset =
8831 /* Address of where the stub is located. */
8832 (s->output_section->vma + s->output_offset + my_offset)
8833 /* Address of where the BL is located. */
57e8b36a
NC		 8834 - (input_section->output_section->vma + input_section->output_offset
8835 + offset)
427bfd90
NC		 8836 /* Addend in the relocation. */
8837 - addend
8838 /* Biassing for PC-relative addressing. */
8839 - 8;
252b5132 8840
12a0a0fd 8841 insert_thumb_branch (input_bfd, ret_offset, hit_data - input_section->vma);
252b5132 8842
b34976b6 8843 return TRUE;
252b5132
RH		 8844}
8845
a4fd1a8e 8846/* Populate an Arm to Thumb stub. Returns the stub symbol. */
9b485d32 8847
a4fd1a8e
PB		 8848static struct elf_link_hash_entry *
8849elf32_arm_create_thumb_stub (struct bfd_link_info * info,
8850 const char * name,
8851 bfd * input_bfd,
8852 bfd * output_bfd,
8853 asection * sym_sec,
8854 bfd_vma val,
8029a119
NC		 8855 asection * s,
8856 char ** error_message)
252b5132 8857{
dc810e39 8858 bfd_vma my_offset;
252b5132 8859 long int ret_offset;
bcbdc74c
NC		 8860 struct elf_link_hash_entry * myh;
8861 struct elf32_arm_link_hash_table * globals;
252b5132 8862
f2a9dd69 8863 myh = find_arm_glue (info, name, error_message);
252b5132 8864 if (myh == NULL)
a4fd1a8e 8865 return NULL;
252b5132
RH		 8866
8867 globals = elf32_arm_hash_table (info);
252b5132
RH		 8868 BFD_ASSERT (globals != NULL);
8869 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8870
8871 my_offset = myh->root.u.def.value;
252b5132
RH		 8872
8873 if ((my_offset & 0x01) == 0x01)
8874 {
8875 if (sym_sec != NULL
8876 && sym_sec->owner != NULL
8877 && !INTERWORK_FLAG (sym_sec->owner))
8878 {
8f615d07 8879 (*_bfd_error_handler)
d003868e
AM		 8880 (_("%B(%s): warning: interworking not enabled.\n"
8881 " first occurrence: %B: arm call to thumb"),
8882 sym_sec->owner, input_bfd, name);
252b5132 8883 }
9b485d32 8884
252b5132
RH		 8885 --my_offset;
8886 myh->root.u.def.value = my_offset;
8887
0e1862bb
L		 8888 if (bfd_link_pic (info)
8889 || globals->root.is_relocatable_executable
27e55c4d 8890 || globals->pic_veneer)
8f6277f5
PB		 8891 {
8892 /* For relocatable objects we can't use absolute addresses,
8893 so construct the address from a relative offset. */
8894 /* TODO: If the offset is small it's probably worth
8895 constructing the address with adds. */
52ab56c2
PB		 8896 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1p_ldr_insn,
8897 s->contents + my_offset);
8898 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2p_add_pc_insn,
8899 s->contents + my_offset + 4);
8900 put_arm_insn (globals, output_bfd, (bfd_vma) a2t3p_bx_r12_insn,
8901 s->contents + my_offset + 8);
8f6277f5
PB		 8902 /* Adjust the offset by 4 for the position of the add,
8903 and 8 for the pipeline offset. */
8904 ret_offset = (val - (s->output_offset
8905 + s->output_section->vma
8906 + my_offset + 12))
8907 | 1;
8908 bfd_put_32 (output_bfd, ret_offset,
8909 s->contents + my_offset + 12);
8910 }
26079076
PB		 8911 else if (globals->use_blx)
8912 {
8913 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1v5_ldr_insn,
8914 s->contents + my_offset);
8915
8916 /* It's a thumb address. Add the low order bit. */
8917 bfd_put_32 (output_bfd, val | a2t2v5_func_addr_insn,
8918 s->contents + my_offset + 4);
8919 }
8f6277f5
PB		 8920 else
8921 {
52ab56c2
PB		 8922 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1_ldr_insn,
8923 s->contents + my_offset);
252b5132 8924
52ab56c2
PB		 8925 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2_bx_r12_insn,
8926 s->contents + my_offset + 4);
252b5132 8927
8f6277f5
PB		 8928 /* It's a thumb address. Add the low order bit. */
8929 bfd_put_32 (output_bfd, val | a2t3_func_addr_insn,
8930 s->contents + my_offset + 8);
8029a119
NC		 8931
8932 my_offset += 12;
8f6277f5 8933 }
252b5132
RH		 8934 }
8935
8936 BFD_ASSERT (my_offset <= globals->arm_glue_size);
8937
a4fd1a8e
PB		 8938 return myh;
8939}
8940
8941/* Arm code calling a Thumb function. */
8942
8943static int
8944elf32_arm_to_thumb_stub (struct bfd_link_info * info,
8945 const char * name,
8946 bfd * input_bfd,
8947 bfd * output_bfd,
8948 asection * input_section,
8949 bfd_byte * hit_data,
8950 asection * sym_sec,
8951 bfd_vma offset,
8952 bfd_signed_vma addend,
f2a9dd69
DJ		 8953 bfd_vma val,
8954 char **error_message)
a4fd1a8e
PB		 8955{
8956 unsigned long int tmp;
8957 bfd_vma my_offset;
8958 asection * s;
8959 long int ret_offset;
8960 struct elf_link_hash_entry * myh;
8961 struct elf32_arm_link_hash_table * globals;
8962
8963 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 8964 BFD_ASSERT (globals != NULL);
8965 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8966
3d4d4302
AM		 8967 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
8968 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 8969 BFD_ASSERT (s != NULL);
8970 BFD_ASSERT (s->contents != NULL);
8971 BFD_ASSERT (s->output_section != NULL);
8972
8973 myh = elf32_arm_create_thumb_stub (info, name, input_bfd, output_bfd,
f2a9dd69 8974 sym_sec, val, s, error_message);
a4fd1a8e
PB		 8975 if (!myh)
8976 return FALSE;
8977
8978 my_offset = myh->root.u.def.value;
252b5132
RH		 8979 tmp = bfd_get_32 (input_bfd, hit_data);
8980 tmp = tmp & 0xFF000000;
8981
9b485d32 8982 /* Somehow these are both 4 too far, so subtract 8. */
dc810e39
AM		 8983 ret_offset = (s->output_offset
8984 + my_offset
8985 + s->output_section->vma
8986 - (input_section->output_offset
8987 + input_section->output_section->vma
8988 + offset + addend)
8989 - 8);
9a5aca8c 8990
252b5132
RH		 8991 tmp = tmp | ((ret_offset >> 2) & 0x00FFFFFF);
8992
dc810e39 8993 bfd_put_32 (output_bfd, (bfd_vma) tmp, hit_data - input_section->vma);
252b5132 8994
b34976b6 8995 return TRUE;
252b5132
RH		 8996}
8997
a4fd1a8e
PB		 8998/* Populate Arm stub for an exported Thumb function. */
8999
9000static bfd_boolean
9001elf32_arm_to_thumb_export_stub (struct elf_link_hash_entry *h, void * inf)
9002{
9003 struct bfd_link_info * info = (struct bfd_link_info *) inf;
9004 asection * s;
9005 struct elf_link_hash_entry * myh;
9006 struct elf32_arm_link_hash_entry *eh;
9007 struct elf32_arm_link_hash_table * globals;
9008 asection *sec;
9009 bfd_vma val;
f2a9dd69 9010 char *error_message;
a4fd1a8e 9011
906e58ca 9012 eh = elf32_arm_hash_entry (h);
a4fd1a8e
PB		 9013 /* Allocate stubs for exported Thumb functions on v4t. */
9014 if (eh->export_glue == NULL)
9015 return TRUE;
9016
9017 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 9018 BFD_ASSERT (globals != NULL);
9019 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9020
3d4d4302
AM		 9021 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9022 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 9023 BFD_ASSERT (s != NULL);
9024 BFD_ASSERT (s->contents != NULL);
9025 BFD_ASSERT (s->output_section != NULL);
9026
9027 sec = eh->export_glue->root.u.def.section;
0eaedd0e
PB		 9028
9029 BFD_ASSERT (sec->output_section != NULL);
9030
a4fd1a8e
PB		 9031 val = eh->export_glue->root.u.def.value + sec->output_offset
9032 + sec->output_section->vma;
8029a119 9033
a4fd1a8e
PB		 9034 myh = elf32_arm_create_thumb_stub (info, h->root.root.string,
9035 h->root.u.def.section->owner,
f2a9dd69
DJ		 9036 globals->obfd, sec, val, s,
9037 &error_message);
a4fd1a8e
PB		 9038 BFD_ASSERT (myh);
9039 return TRUE;
9040}
9041
845b51d6
PB		 9042/* Populate ARMv4 BX veneers. Returns the absolute adress of the veneer. */
9043
9044static bfd_vma
9045elf32_arm_bx_glue (struct bfd_link_info * info, int reg)
9046{
9047 bfd_byte *p;
9048 bfd_vma glue_addr;
9049 asection *s;
9050 struct elf32_arm_link_hash_table *globals;
9051
9052 globals = elf32_arm_hash_table (info);
845b51d6
PB		 9053 BFD_ASSERT (globals != NULL);
9054 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9055
3d4d4302
AM		 9056 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9057 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 9058 BFD_ASSERT (s != NULL);
9059 BFD_ASSERT (s->contents != NULL);
9060 BFD_ASSERT (s->output_section != NULL);
9061
9062 BFD_ASSERT (globals->bx_glue_offset[reg] & 2);
9063
9064 glue_addr = globals->bx_glue_offset[reg] & ~(bfd_vma)3;
9065
9066 if ((globals->bx_glue_offset[reg] & 1) == 0)
9067 {
9068 p = s->contents + glue_addr;
9069 bfd_put_32 (globals->obfd, armbx1_tst_insn + (reg << 16), p);
9070 bfd_put_32 (globals->obfd, armbx2_moveq_insn + reg, p + 4);
9071 bfd_put_32 (globals->obfd, armbx3_bx_insn + reg, p + 8);
9072 globals->bx_glue_offset[reg] |= 1;
9073 }
9074
9075 return glue_addr + s->output_section->vma + s->output_offset;
9076}
9077
a4fd1a8e
PB		 9078/* Generate Arm stubs for exported Thumb symbols. */
9079static void
906e58ca 9080elf32_arm_begin_write_processing (bfd *abfd ATTRIBUTE_UNUSED,
a4fd1a8e
PB		 9081 struct bfd_link_info *link_info)
9082{
9083 struct elf32_arm_link_hash_table * globals;
9084
8029a119
NC		 9085 if (link_info == NULL)
9086 /* Ignore this if we are not called by the ELF backend linker. */
a4fd1a8e
PB		 9087 return;
9088
9089 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 9090 if (globals == NULL)
9091 return;
9092
84c08195
PB		 9093 /* If blx is available then exported Thumb symbols are OK and there is
9094 nothing to do. */
a4fd1a8e
PB		 9095 if (globals->use_blx)
9096 return;
9097
9098 elf_link_hash_traverse (&globals->root, elf32_arm_to_thumb_export_stub,
9099 link_info);
9100}
9101
47beaa6a
RS		 9102/* Reserve space for COUNT dynamic relocations in relocation selection
9103 SRELOC. */
9104
9105static void
9106elf32_arm_allocate_dynrelocs (struct bfd_link_info *info, asection *sreloc,
9107 bfd_size_type count)
9108{
9109 struct elf32_arm_link_hash_table *htab;
9110
9111 htab = elf32_arm_hash_table (info);
9112 BFD_ASSERT (htab->root.dynamic_sections_created);
9113 if (sreloc == NULL)
9114 abort ();
9115 sreloc->size += RELOC_SIZE (htab) * count;
9116}
9117
34e77a92
RS		 9118/* Reserve space for COUNT R_ARM_IRELATIVE relocations. If the link is
9119 dynamic, the relocations should go in SRELOC, otherwise they should
9120 go in the special .rel.iplt section. */
9121
9122static void
9123elf32_arm_allocate_irelocs (struct bfd_link_info *info, asection *sreloc,
9124 bfd_size_type count)
9125{
9126 struct elf32_arm_link_hash_table *htab;
9127
9128 htab = elf32_arm_hash_table (info);
9129 if (!htab->root.dynamic_sections_created)
9130 htab->root.irelplt->size += RELOC_SIZE (htab) * count;
9131 else
9132 {
9133 BFD_ASSERT (sreloc != NULL);
9134 sreloc->size += RELOC_SIZE (htab) * count;
9135 }
9136}
9137
47beaa6a
RS		 9138/* Add relocation REL to the end of relocation section SRELOC. */
9139
9140static void
9141elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
9142 asection *sreloc, Elf_Internal_Rela *rel)
9143{
9144 bfd_byte *loc;
9145 struct elf32_arm_link_hash_table *htab;
9146
9147 htab = elf32_arm_hash_table (info);
34e77a92
RS		 9148 if (!htab->root.dynamic_sections_created
9149 && ELF32_R_TYPE (rel->r_info) == R_ARM_IRELATIVE)
9150 sreloc = htab->root.irelplt;
47beaa6a
RS		 9151 if (sreloc == NULL)
9152 abort ();
9153 loc = sreloc->contents;
9154 loc += sreloc->reloc_count++ * RELOC_SIZE (htab);
9155 if (sreloc->reloc_count * RELOC_SIZE (htab) > sreloc->size)
9156 abort ();
9157 SWAP_RELOC_OUT (htab) (output_bfd, rel, loc);
9158}
9159
34e77a92
RS		 9160/* Allocate room for a PLT entry described by ROOT_PLT and ARM_PLT.
9161 IS_IPLT_ENTRY says whether the entry belongs to .iplt rather than
9162 to .plt. */
9163
9164static void
9165elf32_arm_allocate_plt_entry (struct bfd_link_info *info,
9166 bfd_boolean is_iplt_entry,
9167 union gotplt_union *root_plt,
9168 struct arm_plt_info *arm_plt)
9169{
9170 struct elf32_arm_link_hash_table *htab;
9171 asection *splt;
9172 asection *sgotplt;
9173
9174 htab = elf32_arm_hash_table (info);
9175
9176 if (is_iplt_entry)
9177 {
9178 splt = htab->root.iplt;
9179 sgotplt = htab->root.igotplt;
9180
99059e56
RM		 9181 /* NaCl uses a special first entry in .iplt too. */
9182 if (htab->nacl_p && splt->size == 0)
9183 splt->size += htab->plt_header_size;
9184
34e77a92
RS		 9185 /* Allocate room for an R_ARM_IRELATIVE relocation in .rel.iplt. */
9186 elf32_arm_allocate_irelocs (info, htab->root.irelplt, 1);
9187 }
9188 else
9189 {
9190 splt = htab->root.splt;
9191 sgotplt = htab->root.sgotplt;
9192
9193 /* Allocate room for an R_JUMP_SLOT relocation in .rel.plt. */
9194 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
9195
9196 /* If this is the first .plt entry, make room for the special
9197 first entry. */
9198 if (splt->size == 0)
9199 splt->size += htab->plt_header_size;
9f19ab6d
WN		 9200
9201 htab->next_tls_desc_index++;
34e77a92
RS		 9202 }
9203
9204 /* Allocate the PLT entry itself, including any leading Thumb stub. */
9205 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9206 splt->size += PLT_THUMB_STUB_SIZE;
9207 root_plt->offset = splt->size;
9208 splt->size += htab->plt_entry_size;
9209
9210 if (!htab->symbian_p)
9211 {
9212 /* We also need to make an entry in the .got.plt section, which
9213 will be placed in the .got section by the linker script. */
9f19ab6d
WN		 9214 if (is_iplt_entry)
9215 arm_plt->got_offset = sgotplt->size;
9216 else
9217 arm_plt->got_offset = sgotplt->size - 8 * htab->num_tls_desc;
34e77a92
RS		 9218 sgotplt->size += 4;
9219 }
9220}
9221
b38cadfb
NC		 9222static bfd_vma
9223arm_movw_immediate (bfd_vma value)
9224{
9225 return (value & 0x00000fff) | ((value & 0x0000f000) << 4);
9226}
9227
9228static bfd_vma
9229arm_movt_immediate (bfd_vma value)
9230{
9231 return ((value & 0x0fff0000) >> 16) | ((value & 0xf0000000) >> 12);
9232}
9233
34e77a92
RS		 9234/* Fill in a PLT entry and its associated GOT slot. If DYNINDX == -1,
9235 the entry lives in .iplt and resolves to (*SYM_VALUE)().
9236 Otherwise, DYNINDX is the index of the symbol in the dynamic
9237 symbol table and SYM_VALUE is undefined.
9238
9239 ROOT_PLT points to the offset of the PLT entry from the start of its
9240 section (.iplt or .plt). ARM_PLT points to the symbol's ARM-specific
57460bcf 9241 bookkeeping information.
34e77a92 9242
57460bcf
NC		 9243 Returns FALSE if there was a problem. */
9244
9245static bfd_boolean
34e77a92
RS		 9246elf32_arm_populate_plt_entry (bfd *output_bfd, struct bfd_link_info *info,
9247 union gotplt_union *root_plt,
9248 struct arm_plt_info *arm_plt,
9249 int dynindx, bfd_vma sym_value)
9250{
9251 struct elf32_arm_link_hash_table *htab;
9252 asection *sgot;
9253 asection *splt;
9254 asection *srel;
9255 bfd_byte *loc;
9256 bfd_vma plt_index;
9257 Elf_Internal_Rela rel;
9258 bfd_vma plt_header_size;
9259 bfd_vma got_header_size;
9260
9261 htab = elf32_arm_hash_table (info);
9262
9263 /* Pick the appropriate sections and sizes. */
9264 if (dynindx == -1)
9265 {
9266 splt = htab->root.iplt;
9267 sgot = htab->root.igotplt;
9268 srel = htab->root.irelplt;
9269
9270 /* There are no reserved entries in .igot.plt, and no special
9271 first entry in .iplt. */
9272 got_header_size = 0;
9273 plt_header_size = 0;
9274 }
9275 else
9276 {
9277 splt = htab->root.splt;
9278 sgot = htab->root.sgotplt;
9279 srel = htab->root.srelplt;
9280
9281 got_header_size = get_elf_backend_data (output_bfd)->got_header_size;
9282 plt_header_size = htab->plt_header_size;
9283 }
9284 BFD_ASSERT (splt != NULL && srel != NULL);
9285
9286 /* Fill in the entry in the procedure linkage table. */
9287 if (htab->symbian_p)
9288 {
9289 BFD_ASSERT (dynindx >= 0);
9290 put_arm_insn (htab, output_bfd,
9291 elf32_arm_symbian_plt_entry[0],
9292 splt->contents + root_plt->offset);
9293 bfd_put_32 (output_bfd,
9294 elf32_arm_symbian_plt_entry[1],
9295 splt->contents + root_plt->offset + 4);
9296
9297 /* Fill in the entry in the .rel.plt section. */
9298 rel.r_offset = (splt->output_section->vma
9299 + splt->output_offset
9300 + root_plt->offset + 4);
9301 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_GLOB_DAT);
9302
9303 /* Get the index in the procedure linkage table which
9304 corresponds to this symbol. This is the index of this symbol
9305 in all the symbols for which we are making plt entries. The
9306 first entry in the procedure linkage table is reserved. */
9307 plt_index = ((root_plt->offset - plt_header_size)
9308 / htab->plt_entry_size);
9309 }
9310 else
9311 {
9312 bfd_vma got_offset, got_address, plt_address;
9313 bfd_vma got_displacement, initial_got_entry;
9314 bfd_byte * ptr;
9315
9316 BFD_ASSERT (sgot != NULL);
9317
9318 /* Get the offset into the .(i)got.plt table of the entry that
9319 corresponds to this function. */
9320 got_offset = (arm_plt->got_offset & -2);
9321
9322 /* Get the index in the procedure linkage table which
9323 corresponds to this symbol. This is the index of this symbol
9324 in all the symbols for which we are making plt entries.
9325 After the reserved .got.plt entries, all symbols appear in
9326 the same order as in .plt. */
9327 plt_index = (got_offset - got_header_size) / 4;
9328
9329 /* Calculate the address of the GOT entry. */
9330 got_address = (sgot->output_section->vma
9331 + sgot->output_offset
9332 + got_offset);
9333
9334 /* ...and the address of the PLT entry. */
9335 plt_address = (splt->output_section->vma
9336 + splt->output_offset
9337 + root_plt->offset);
9338
9339 ptr = splt->contents + root_plt->offset;
0e1862bb 9340 if (htab->vxworks_p && bfd_link_pic (info))
34e77a92
RS		 9341 {
9342 unsigned int i;
9343 bfd_vma val;
9344
9345 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9346 {
9347 val = elf32_arm_vxworks_shared_plt_entry[i];
9348 if (i == 2)
9349 val |= got_address - sgot->output_section->vma;
9350 if (i == 5)
9351 val |= plt_index * RELOC_SIZE (htab);
9352 if (i == 2 || i == 5)
9353 bfd_put_32 (output_bfd, val, ptr);
9354 else
9355 put_arm_insn (htab, output_bfd, val, ptr);
9356 }
9357 }
9358 else if (htab->vxworks_p)
9359 {
9360 unsigned int i;
9361 bfd_vma val;
9362
9363 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9364 {
9365 val = elf32_arm_vxworks_exec_plt_entry[i];
9366 if (i == 2)
9367 val |= got_address;
9368 if (i == 4)
9369 val |= 0xffffff & -((root_plt->offset + i * 4 + 8) >> 2);
9370 if (i == 5)
9371 val |= plt_index * RELOC_SIZE (htab);
9372 if (i == 2 || i == 5)
9373 bfd_put_32 (output_bfd, val, ptr);
9374 else
9375 put_arm_insn (htab, output_bfd, val, ptr);
9376 }
9377
9378 loc = (htab->srelplt2->contents
9379 + (plt_index * 2 + 1) * RELOC_SIZE (htab));
9380
9381 /* Create the .rela.plt.unloaded R_ARM_ABS32 relocation
9382 referencing the GOT for this PLT entry. */
9383 rel.r_offset = plt_address + 8;
9384 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
9385 rel.r_addend = got_offset;
9386 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9387 loc += RELOC_SIZE (htab);
9388
9389 /* Create the R_ARM_ABS32 relocation referencing the
9390 beginning of the PLT for this GOT entry. */
9391 rel.r_offset = got_address;
9392 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
9393 rel.r_addend = 0;
9394 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9395 }
b38cadfb
NC		 9396 else if (htab->nacl_p)
9397 {
9398 /* Calculate the displacement between the PLT slot and the
9399 common tail that's part of the special initial PLT slot. */
6034aab8 9400 int32_t tail_displacement
b38cadfb
NC		 9401 = ((splt->output_section->vma + splt->output_offset
9402 + ARM_NACL_PLT_TAIL_OFFSET)
9403 - (plt_address + htab->plt_entry_size + 4));
9404 BFD_ASSERT ((tail_displacement & 3) == 0);
9405 tail_displacement >>= 2;
9406
9407 BFD_ASSERT ((tail_displacement & 0xff000000) == 0
9408 || (-tail_displacement & 0xff000000) == 0);
9409
9410 /* Calculate the displacement between the PLT slot and the entry
9411 in the GOT. The offset accounts for the value produced by
9412 adding to pc in the penultimate instruction of the PLT stub. */
6034aab8 9413 got_displacement = (got_address
99059e56 9414 - (plt_address + htab->plt_entry_size));
b38cadfb
NC		 9415
9416 /* NaCl does not support interworking at all. */
9417 BFD_ASSERT (!elf32_arm_plt_needs_thumb_stub_p (info, arm_plt));
9418
9419 put_arm_insn (htab, output_bfd,
9420 elf32_arm_nacl_plt_entry[0]
9421 | arm_movw_immediate (got_displacement),
9422 ptr + 0);
9423 put_arm_insn (htab, output_bfd,
9424 elf32_arm_nacl_plt_entry[1]
9425 | arm_movt_immediate (got_displacement),
9426 ptr + 4);
9427 put_arm_insn (htab, output_bfd,
9428 elf32_arm_nacl_plt_entry[2],
9429 ptr + 8);
9430 put_arm_insn (htab, output_bfd,
9431 elf32_arm_nacl_plt_entry[3]
9432 | (tail_displacement & 0x00ffffff),
9433 ptr + 12);
9434 }
57460bcf
NC		 9435 else if (using_thumb_only (htab))
9436 {
eed94f8f 9437 /* PR ld/16017: Generate thumb only PLT entries. */
469a3493 9438 if (!using_thumb2 (htab))
eed94f8f
NC		 9439 {
9440 /* FIXME: We ought to be able to generate thumb-1 PLT
9441 instructions... */
9442 _bfd_error_handler (_("%B: Warning: thumb-1 mode PLT generation not currently supported"),
9443 output_bfd);
9444 return FALSE;
9445 }
57460bcf 9446
eed94f8f
NC		 9447 /* Calculate the displacement between the PLT slot and the entry in
9448 the GOT. The 12-byte offset accounts for the value produced by
9449 adding to pc in the 3rd instruction of the PLT stub. */
9450 got_displacement = got_address - (plt_address + 12);
9451
9452 /* As we are using 32 bit instructions we have to use 'put_arm_insn'
9453 instead of 'put_thumb_insn'. */
9454 put_arm_insn (htab, output_bfd,
9455 elf32_thumb2_plt_entry[0]
9456 | ((got_displacement & 0x000000ff) << 16)
9457 | ((got_displacement & 0x00000700) << 20)
9458 | ((got_displacement & 0x00000800) >> 1)
9459 | ((got_displacement & 0x0000f000) >> 12),
9460 ptr + 0);
9461 put_arm_insn (htab, output_bfd,
9462 elf32_thumb2_plt_entry[1]
9463 | ((got_displacement & 0x00ff0000) )
9464 | ((got_displacement & 0x07000000) << 4)
9465 | ((got_displacement & 0x08000000) >> 17)
9466 | ((got_displacement & 0xf0000000) >> 28),
9467 ptr + 4);
9468 put_arm_insn (htab, output_bfd,
9469 elf32_thumb2_plt_entry[2],
9470 ptr + 8);
9471 put_arm_insn (htab, output_bfd,
9472 elf32_thumb2_plt_entry[3],
9473 ptr + 12);
57460bcf 9474 }
34e77a92
RS		 9475 else
9476 {
9477 /* Calculate the displacement between the PLT slot and the
9478 entry in the GOT. The eight-byte offset accounts for the
9479 value produced by adding to pc in the first instruction
9480 of the PLT stub. */
9481 got_displacement = got_address - (plt_address + 8);
9482
34e77a92
RS		 9483 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9484 {
9485 put_thumb_insn (htab, output_bfd,
9486 elf32_arm_plt_thumb_stub[0], ptr - 4);
9487 put_thumb_insn (htab, output_bfd,
9488 elf32_arm_plt_thumb_stub[1], ptr - 2);
9489 }
9490
1db37fe6
YG		 9491 if (!elf32_arm_use_long_plt_entry)
9492 {
9493 BFD_ASSERT ((got_displacement & 0xf0000000) == 0);
9494
9495 put_arm_insn (htab, output_bfd,
9496 elf32_arm_plt_entry_short[0]
9497 | ((got_displacement & 0x0ff00000) >> 20),
9498 ptr + 0);
9499 put_arm_insn (htab, output_bfd,
9500 elf32_arm_plt_entry_short[1]
9501 | ((got_displacement & 0x000ff000) >> 12),
9502 ptr+ 4);
9503 put_arm_insn (htab, output_bfd,
9504 elf32_arm_plt_entry_short[2]
9505 | (got_displacement & 0x00000fff),
9506 ptr + 8);
34e77a92 9507#ifdef FOUR_WORD_PLT
1db37fe6 9508 bfd_put_32 (output_bfd, elf32_arm_plt_entry_short[3], ptr + 12);
34e77a92 9509#endif
1db37fe6
YG		 9510 }
9511 else
9512 {
9513 put_arm_insn (htab, output_bfd,
9514 elf32_arm_plt_entry_long[0]
9515 | ((got_displacement & 0xf0000000) >> 28),
9516 ptr + 0);
9517 put_arm_insn (htab, output_bfd,
9518 elf32_arm_plt_entry_long[1]
9519 | ((got_displacement & 0x0ff00000) >> 20),
9520 ptr + 4);
9521 put_arm_insn (htab, output_bfd,
9522 elf32_arm_plt_entry_long[2]
9523 | ((got_displacement & 0x000ff000) >> 12),
9524 ptr+ 8);
9525 put_arm_insn (htab, output_bfd,
9526 elf32_arm_plt_entry_long[3]
9527 | (got_displacement & 0x00000fff),
9528 ptr + 12);
9529 }
34e77a92
RS		 9530 }
9531
9532 /* Fill in the entry in the .rel(a).(i)plt section. */
9533 rel.r_offset = got_address;
9534 rel.r_addend = 0;
9535 if (dynindx == -1)
9536 {
9537 /* .igot.plt entries use IRELATIVE relocations against SYM_VALUE.
9538 The dynamic linker or static executable then calls SYM_VALUE
9539 to determine the correct run-time value of the .igot.plt entry. */
9540 rel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
9541 initial_got_entry = sym_value;
9542 }
9543 else
9544 {
9545 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_JUMP_SLOT);
9546 initial_got_entry = (splt->output_section->vma
9547 + splt->output_offset);
9548 }
9549
9550 /* Fill in the entry in the global offset table. */
9551 bfd_put_32 (output_bfd, initial_got_entry,
9552 sgot->contents + got_offset);
9553 }
9554
aba8c3de
WN		 9555 if (dynindx == -1)
9556 elf32_arm_add_dynreloc (output_bfd, info, srel, &rel);
9557 else
9558 {
9559 loc = srel->contents + plt_index * RELOC_SIZE (htab);
9560 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9561 }
57460bcf
NC		 9562
9563 return TRUE;
34e77a92
RS		 9564}
9565
eb043451
PB		 9566/* Some relocations map to different relocations depending on the
9567 target. Return the real relocation. */
8029a119 9568
eb043451
PB		 9569static int
9570arm_real_reloc_type (struct elf32_arm_link_hash_table * globals,
9571 int r_type)
9572{
9573 switch (r_type)
9574 {
9575 case R_ARM_TARGET1:
9576 if (globals->target1_is_rel)
9577 return R_ARM_REL32;
9578 else
9579 return R_ARM_ABS32;
9580
9581 case R_ARM_TARGET2:
9582 return globals->target2_reloc;
9583
9584 default:
9585 return r_type;
9586 }
9587}
eb043451 9588
ba93b8ac
DJ		 9589/* Return the base VMA address which should be subtracted from real addresses
9590 when resolving @dtpoff relocation.
9591 This is PT_TLS segment p_vaddr. */
9592
9593static bfd_vma
9594dtpoff_base (struct bfd_link_info *info)
9595{
9596 /* If tls_sec is NULL, we should have signalled an error already. */
9597 if (elf_hash_table (info)->tls_sec == NULL)
9598 return 0;
9599 return elf_hash_table (info)->tls_sec->vma;
9600}
9601
9602/* Return the relocation value for @tpoff relocation
9603 if STT_TLS virtual address is ADDRESS. */
9604
9605static bfd_vma
9606tpoff (struct bfd_link_info *info, bfd_vma address)
9607{
9608 struct elf_link_hash_table *htab = elf_hash_table (info);
9609 bfd_vma base;
9610
9611 /* If tls_sec is NULL, we should have signalled an error already. */
9612 if (htab->tls_sec == NULL)
9613 return 0;
9614 base = align_power ((bfd_vma) TCB_SIZE, htab->tls_sec->alignment_power);
9615 return address - htab->tls_sec->vma + base;
9616}
9617
00a97672
RS		 9618/* Perform an R_ARM_ABS12 relocation on the field pointed to by DATA.
9619 VALUE is the relocation value. */
9620
9621static bfd_reloc_status_type
9622elf32_arm_abs12_reloc (bfd *abfd, void *data, bfd_vma value)
9623{
9624 if (value > 0xfff)
9625 return bfd_reloc_overflow;
9626
9627 value |= bfd_get_32 (abfd, data) & 0xfffff000;
9628 bfd_put_32 (abfd, value, data);
9629 return bfd_reloc_ok;
9630}
9631
0855e32b
NS		 9632/* Handle TLS relaxations. Relaxing is possible for symbols that use
9633 R_ARM_GOTDESC, R_ARM_{,THM_}TLS_CALL or
9634 R_ARM_{,THM_}TLS_DESCSEQ relocations, during a static link.
9635
9636 Return bfd_reloc_ok if we're done, bfd_reloc_continue if the caller
9637 is to then call final_link_relocate. Return other values in the
62672b10
NS		 9638 case of error.
9639
9640 FIXME:When --emit-relocs is in effect, we'll emit relocs describing
9641 the pre-relaxed code. It would be nice if the relocs were updated
9642 to match the optimization. */
0855e32b 9643
b38cadfb 9644static bfd_reloc_status_type
0855e32b 9645elf32_arm_tls_relax (struct elf32_arm_link_hash_table *globals,
b38cadfb 9646 bfd *input_bfd, asection *input_sec, bfd_byte *contents,
0855e32b
NS		 9647 Elf_Internal_Rela *rel, unsigned long is_local)
9648{
9649 unsigned long insn;
b38cadfb 9650
0855e32b
NS		 9651 switch (ELF32_R_TYPE (rel->r_info))
9652 {
9653 default:
9654 return bfd_reloc_notsupported;
b38cadfb 9655
0855e32b
NS		 9656 case R_ARM_TLS_GOTDESC:
9657 if (is_local)
9658 insn = 0;
9659 else
9660 {
9661 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
9662 if (insn & 1)
9663 insn -= 5; /* THUMB */
9664 else
9665 insn -= 8; /* ARM */
9666 }
9667 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
9668 return bfd_reloc_continue;
9669
9670 case R_ARM_THM_TLS_DESCSEQ:
9671 /* Thumb insn. */
9672 insn = bfd_get_16 (input_bfd, contents + rel->r_offset);
9673 if ((insn & 0xff78) == 0x4478) /* add rx, pc */
9674 {
9675 if (is_local)
9676 /* nop */
9677 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
9678 }
9679 else if ((insn & 0xffc0) == 0x6840) /* ldr rx,[ry,#4] */
9680 {
9681 if (is_local)
9682 /* nop */
9683 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
9684 else
9685 /* ldr rx,[ry] */
9686 bfd_put_16 (input_bfd, insn & 0xf83f, contents + rel->r_offset);
9687 }
9688 else if ((insn & 0xff87) == 0x4780) /* blx rx */
9689 {
9690 if (is_local)
9691 /* nop */
9692 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
9693 else
9694 /* mov r0, rx */
9695 bfd_put_16 (input_bfd, 0x4600 | (insn & 0x78),
9696 contents + rel->r_offset);
9697 }
9698 else
9699 {
9700 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
9701 /* It's a 32 bit instruction, fetch the rest of it for
9702 error generation. */
9703 insn = (insn << 16)
9704 | bfd_get_16 (input_bfd, contents + rel->r_offset + 2);
9705 (*_bfd_error_handler)
9706 (_("%B(%A+0x%lx):unexpected Thumb instruction '0x%x' in TLS trampoline"),
9707 input_bfd, input_sec, (unsigned long)rel->r_offset, insn);
9708 return bfd_reloc_notsupported;
9709 }
9710 break;
b38cadfb 9711
0855e32b
NS		 9712 case R_ARM_TLS_DESCSEQ:
9713 /* arm insn. */
9714 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
9715 if ((insn & 0xffff0ff0) == 0xe08f0000) /* add rx,pc,ry */
9716 {
9717 if (is_local)
9718 /* mov rx, ry */
9719 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xffff),
9720 contents + rel->r_offset);
9721 }
9722 else if ((insn & 0xfff00fff) == 0xe5900004) /* ldr rx,[ry,#4]*/
9723 {
9724 if (is_local)
9725 /* nop */
9726 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
9727 else
9728 /* ldr rx,[ry] */
9729 bfd_put_32 (input_bfd, insn & 0xfffff000,
9730 contents + rel->r_offset);
9731 }
9732 else if ((insn & 0xfffffff0) == 0xe12fff30) /* blx rx */
9733 {
9734 if (is_local)
9735 /* nop */
9736 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
9737 else
9738 /* mov r0, rx */
9739 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xf),
9740 contents + rel->r_offset);
9741 }
9742 else
9743 {
9744 (*_bfd_error_handler)
9745 (_("%B(%A+0x%lx):unexpected ARM instruction '0x%x' in TLS trampoline"),
9746 input_bfd, input_sec, (unsigned long)rel->r_offset, insn);
9747 return bfd_reloc_notsupported;
9748 }
9749 break;
9750
9751 case R_ARM_TLS_CALL:
9752 /* GD->IE relaxation, turn the instruction into 'nop' or
9753 'ldr r0, [pc,r0]' */
9754 insn = is_local ? 0xe1a00000 : 0xe79f0000;
9755 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
9756 break;
b38cadfb 9757
0855e32b 9758 case R_ARM_THM_TLS_CALL:
6a631e86 9759 /* GD->IE relaxation. */
0855e32b
NS		 9760 if (!is_local)
9761 /* add r0,pc; ldr r0, [r0] */
9762 insn = 0x44786800;
60a019a0 9763 else if (using_thumb2 (globals))
0855e32b
NS		 9764 /* nop.w */
9765 insn = 0xf3af8000;
9766 else
9767 /* nop; nop */
9768 insn = 0xbf00bf00;
b38cadfb 9769
0855e32b
NS		 9770 bfd_put_16 (input_bfd, insn >> 16, contents + rel->r_offset);
9771 bfd_put_16 (input_bfd, insn & 0xffff, contents + rel->r_offset + 2);
9772 break;
9773 }
9774 return bfd_reloc_ok;
9775}
9776
4962c51a
MS		 9777/* For a given value of n, calculate the value of G_n as required to
9778 deal with group relocations. We return it in the form of an
9779 encoded constant-and-rotation, together with the final residual. If n is
9780 specified as less than zero, then final_residual is filled with the
9781 input value and no further action is performed. */
9782
9783static bfd_vma
9784calculate_group_reloc_mask (bfd_vma value, int n, bfd_vma *final_residual)
9785{
9786 int current_n;
9787 bfd_vma g_n;
9788 bfd_vma encoded_g_n = 0;
9789 bfd_vma residual = value; /* Also known as Y_n. */
9790
9791 for (current_n = 0; current_n <= n; current_n++)
9792 {
9793 int shift;
9794
9795 /* Calculate which part of the value to mask. */
9796 if (residual == 0)
99059e56 9797 shift = 0;
4962c51a 9798 else
99059e56
RM		 9799 {
9800 int msb;
9801
9802 /* Determine the most significant bit in the residual and
9803 align the resulting value to a 2-bit boundary. */
9804 for (msb = 30; msb >= 0; msb -= 2)
9805 if (residual & (3 << msb))
9806 break;
9807
9808 /* The desired shift is now (msb - 6), or zero, whichever
9809 is the greater. */
9810 shift = msb - 6;
9811 if (shift < 0)
9812 shift = 0;
9813 }
4962c51a
MS		 9814
9815 /* Calculate g_n in 32-bit as well as encoded constant+rotation form. */
9816 g_n = residual & (0xff << shift);
9817 encoded_g_n = (g_n >> shift)
99059e56 9818 | ((g_n <= 0xff ? 0 : (32 - shift) / 2) << 8);
4962c51a
MS		 9819
9820 /* Calculate the residual for the next time around. */
9821 residual &= ~g_n;
9822 }
9823
9824 *final_residual = residual;
9825
9826 return encoded_g_n;
9827}
9828
9829/* Given an ARM instruction, determine whether it is an ADD or a SUB.
9830 Returns 1 if it is an ADD, -1 if it is a SUB, and 0 otherwise. */
906e58ca 9831
4962c51a 9832static int
906e58ca 9833identify_add_or_sub (bfd_vma insn)
4962c51a
MS		 9834{
9835 int opcode = insn & 0x1e00000;
9836
9837 if (opcode == 1 << 23) /* ADD */
9838 return 1;
9839
9840 if (opcode == 1 << 22) /* SUB */
9841 return -1;
9842
9843 return 0;
9844}
9845
252b5132 9846/* Perform a relocation as part of a final link. */
9b485d32 9847
252b5132 9848static bfd_reloc_status_type
57e8b36a
NC		 9849elf32_arm_final_link_relocate (reloc_howto_type * howto,
9850 bfd * input_bfd,
9851 bfd * output_bfd,
9852 asection * input_section,
9853 bfd_byte * contents,
9854 Elf_Internal_Rela * rel,
9855 bfd_vma value,
9856 struct bfd_link_info * info,
9857 asection * sym_sec,
9858 const char * sym_name,
34e77a92
RS		 9859 unsigned char st_type,
9860 enum arm_st_branch_type branch_type,
0945cdfd 9861 struct elf_link_hash_entry * h,
f2a9dd69 9862 bfd_boolean * unresolved_reloc_p,
8029a119 9863 char ** error_message)
252b5132
RH		 9864{
9865 unsigned long r_type = howto->type;
9866 unsigned long r_symndx;
9867 bfd_byte * hit_data = contents + rel->r_offset;
252b5132 9868 bfd_vma * local_got_offsets;
0855e32b 9869 bfd_vma * local_tlsdesc_gotents;
34e77a92
RS		 9870 asection * sgot;
9871 asection * splt;
252b5132 9872 asection * sreloc = NULL;
362d30a1 9873 asection * srelgot;
252b5132 9874 bfd_vma addend;
ba96a88f 9875 bfd_signed_vma signed_addend;
34e77a92
RS		 9876 unsigned char dynreloc_st_type;
9877 bfd_vma dynreloc_value;
ba96a88f 9878 struct elf32_arm_link_hash_table * globals;
34e77a92
RS		 9879 struct elf32_arm_link_hash_entry *eh;
9880 union gotplt_union *root_plt;
9881 struct arm_plt_info *arm_plt;
9882 bfd_vma plt_offset;
9883 bfd_vma gotplt_offset;
9884 bfd_boolean has_iplt_entry;
f21f3fe0 9885
9c504268 9886 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 9887 if (globals == NULL)
9888 return bfd_reloc_notsupported;
9c504268 9889
0ffa91dd
NC		 9890 BFD_ASSERT (is_arm_elf (input_bfd));
9891
9892 /* Some relocation types map to different relocations depending on the
9c504268 9893 target. We pick the right one here. */
eb043451 9894 r_type = arm_real_reloc_type (globals, r_type);
0855e32b
NS		 9895
9896 /* It is possible to have linker relaxations on some TLS access
9897 models. Update our information here. */
9898 r_type = elf32_arm_tls_transition (info, r_type, h);
9899
eb043451
PB		 9900 if (r_type != howto->type)
9901 howto = elf32_arm_howto_from_type (r_type);
9c504268 9902
34e77a92 9903 eh = (struct elf32_arm_link_hash_entry *) h;
362d30a1 9904 sgot = globals->root.sgot;
252b5132 9905 local_got_offsets = elf_local_got_offsets (input_bfd);
0855e32b
NS		 9906 local_tlsdesc_gotents = elf32_arm_local_tlsdesc_gotent (input_bfd);
9907
34e77a92
RS		 9908 if (globals->root.dynamic_sections_created)
9909 srelgot = globals->root.srelgot;
9910 else
9911 srelgot = NULL;
9912
252b5132
RH		 9913 r_symndx = ELF32_R_SYM (rel->r_info);
9914
4e7fd91e 9915 if (globals->use_rel)
ba96a88f 9916 {
4e7fd91e
PB		 9917 addend = bfd_get_32 (input_bfd, hit_data) & howto->src_mask;
9918
9919 if (addend & ((howto->src_mask + 1) >> 1))
9920 {
9921 signed_addend = -1;
9922 signed_addend &= ~ howto->src_mask;
9923 signed_addend |= addend;
9924 }
9925 else
9926 signed_addend = addend;
ba96a88f
NC		 9927 }
9928 else
4e7fd91e 9929 addend = signed_addend = rel->r_addend;
f21f3fe0 9930
39f21624
NC		 9931 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
9932 are resolving a function call relocation. */
9933 if (using_thumb_only (globals)
9934 && (r_type == R_ARM_THM_CALL
9935 || r_type == R_ARM_THM_JUMP24)
9936 && branch_type == ST_BRANCH_TO_ARM)
9937 branch_type = ST_BRANCH_TO_THUMB;
9938
34e77a92
RS		 9939 /* Record the symbol information that should be used in dynamic
9940 relocations. */
9941 dynreloc_st_type = st_type;
9942 dynreloc_value = value;
9943 if (branch_type == ST_BRANCH_TO_THUMB)
9944 dynreloc_value |= 1;
9945
9946 /* Find out whether the symbol has a PLT. Set ST_VALUE, BRANCH_TYPE and
9947 VALUE appropriately for relocations that we resolve at link time. */
9948 has_iplt_entry = FALSE;
4ba2ef8f
TP		 9949 if (elf32_arm_get_plt_info (input_bfd, globals, eh, r_symndx, &root_plt,
9950 &arm_plt)
34e77a92
RS		 9951 && root_plt->offset != (bfd_vma) -1)
9952 {
9953 plt_offset = root_plt->offset;
9954 gotplt_offset = arm_plt->got_offset;
9955
9956 if (h == NULL || eh->is_iplt)
9957 {
9958 has_iplt_entry = TRUE;
9959 splt = globals->root.iplt;
9960
9961 /* Populate .iplt entries here, because not all of them will
9962 be seen by finish_dynamic_symbol. The lower bit is set if
9963 we have already populated the entry. */
9964 if (plt_offset & 1)
9965 plt_offset--;
9966 else
9967 {
57460bcf
NC		 9968 if (elf32_arm_populate_plt_entry (output_bfd, info, root_plt, arm_plt,
9969 -1, dynreloc_value))
9970 root_plt->offset |= 1;
9971 else
9972 return bfd_reloc_notsupported;
34e77a92
RS		 9973 }
9974
9975 /* Static relocations always resolve to the .iplt entry. */
9976 st_type = STT_FUNC;
9977 value = (splt->output_section->vma
9978 + splt->output_offset
9979 + plt_offset);
9980 branch_type = ST_BRANCH_TO_ARM;
9981
9982 /* If there are non-call relocations that resolve to the .iplt
9983 entry, then all dynamic ones must too. */
9984 if (arm_plt->noncall_refcount != 0)
9985 {
9986 dynreloc_st_type = st_type;
9987 dynreloc_value = value;
9988 }
9989 }
9990 else
9991 /* We populate the .plt entry in finish_dynamic_symbol. */
9992 splt = globals->root.splt;
9993 }
9994 else
9995 {
9996 splt = NULL;
9997 plt_offset = (bfd_vma) -1;
9998 gotplt_offset = (bfd_vma) -1;
9999 }
10000
252b5132
RH		 10001 switch (r_type)
10002 {
10003 case R_ARM_NONE:
28a094c2
DJ		 10004 /* We don't need to find a value for this symbol. It's just a
10005 marker. */
10006 *unresolved_reloc_p = FALSE;
252b5132
RH		 10007 return bfd_reloc_ok;
10008
00a97672
RS		 10009 case R_ARM_ABS12:
10010 if (!globals->vxworks_p)
10011 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
10012
252b5132
RH		 10013 case R_ARM_PC24:
10014 case R_ARM_ABS32:
bb224fc3 10015 case R_ARM_ABS32_NOI:
252b5132 10016 case R_ARM_REL32:
bb224fc3 10017 case R_ARM_REL32_NOI:
5b5bb741
PB		 10018 case R_ARM_CALL:
10019 case R_ARM_JUMP24:
dfc5f959 10020 case R_ARM_XPC25:
eb043451 10021 case R_ARM_PREL31:
7359ea65 10022 case R_ARM_PLT32:
7359ea65
DJ		 10023 /* Handle relocations which should use the PLT entry. ABS32/REL32
10024 will use the symbol's value, which may point to a PLT entry, but we
10025 don't need to handle that here. If we created a PLT entry, all
5fa9e92f
CL		 10026 branches in this object should go to it, except if the PLT is too
10027 far away, in which case a long branch stub should be inserted. */
bb224fc3 10028 if ((r_type != R_ARM_ABS32 && r_type != R_ARM_REL32
99059e56 10029 && r_type != R_ARM_ABS32_NOI && r_type != R_ARM_REL32_NOI
155d87d7
CL		 10030 && r_type != R_ARM_CALL
10031 && r_type != R_ARM_JUMP24
10032 && r_type != R_ARM_PLT32)
34e77a92 10033 && plt_offset != (bfd_vma) -1)
7359ea65 10034 {
34e77a92
RS		 10035 /* If we've created a .plt section, and assigned a PLT entry
10036 to this function, it must either be a STT_GNU_IFUNC reference
10037 or not be known to bind locally. In other cases, we should
10038 have cleared the PLT entry by now. */
10039 BFD_ASSERT (has_iplt_entry || !SYMBOL_CALLS_LOCAL (info, h));
7359ea65
DJ		 10040
10041 value = (splt->output_section->vma
10042 + splt->output_offset
34e77a92 10043 + plt_offset);
0945cdfd 10044 *unresolved_reloc_p = FALSE;
7359ea65
DJ		 10045 return _bfd_final_link_relocate (howto, input_bfd, input_section,
10046 contents, rel->r_offset, value,
00a97672 10047 rel->r_addend);
7359ea65
DJ		 10048 }
10049
67687978
PB		 10050 /* When generating a shared object or relocatable executable, these
10051 relocations are copied into the output file to be resolved at
10052 run time. */
0e1862bb
L		 10053 if ((bfd_link_pic (info)
10054 || globals->root.is_relocatable_executable)
7359ea65 10055 && (input_section->flags & SEC_ALLOC)
4dfe6ac6 10056 && !(globals->vxworks_p
3348747a
NS		 10057 && strcmp (input_section->output_section->name,
10058 ".tls_vars") == 0)
bb224fc3 10059 && ((r_type != R_ARM_REL32 && r_type != R_ARM_REL32_NOI)
ee06dc07 10060 || !SYMBOL_CALLS_LOCAL (info, h))
ca6b5f82
AM		 10061 && !(input_bfd == globals->stub_bfd
10062 && strstr (input_section->name, STUB_SUFFIX))
7359ea65
DJ		 10063 && (h == NULL
10064 || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
10065 || h->root.type != bfd_link_hash_undefweak)
10066 && r_type != R_ARM_PC24
5b5bb741
PB		 10067 && r_type != R_ARM_CALL
10068 && r_type != R_ARM_JUMP24
ee06dc07 10069 && r_type != R_ARM_PREL31
7359ea65 10070 && r_type != R_ARM_PLT32)
252b5132 10071 {
947216bf 10072 Elf_Internal_Rela outrel;
b34976b6 10073 bfd_boolean skip, relocate;
f21f3fe0 10074
52db4ec2
JW		 10075 if ((r_type == R_ARM_REL32 || r_type == R_ARM_REL32_NOI)
10076 && !h->def_regular)
10077 {
10078 char *v = _("shared object");
10079
0e1862bb 10080 if (bfd_link_executable (info))
52db4ec2
JW		 10081 v = _("PIE executable");
10082
10083 (*_bfd_error_handler)
10084 (_("%B: relocation %s against external or undefined symbol `%s'"
10085 " can not be used when making a %s; recompile with -fPIC"), input_bfd,
10086 elf32_arm_howto_table_1[r_type].name, h->root.root.string, v);
10087 return bfd_reloc_notsupported;
10088 }
10089
0945cdfd
DJ		 10090 *unresolved_reloc_p = FALSE;
10091
34e77a92 10092 if (sreloc == NULL && globals->root.dynamic_sections_created)
252b5132 10093 {
83bac4b0
NC		 10094 sreloc = _bfd_elf_get_dynamic_reloc_section (input_bfd, input_section,
10095 ! globals->use_rel);
f21f3fe0 10096
83bac4b0 10097 if (sreloc == NULL)
252b5132 10098 return bfd_reloc_notsupported;
252b5132 10099 }
f21f3fe0 10100
b34976b6
AM		 10101 skip = FALSE;
10102 relocate = FALSE;
f21f3fe0 10103
00a97672 10104 outrel.r_addend = addend;
c629eae0
JJ		 10105 outrel.r_offset =
10106 _bfd_elf_section_offset (output_bfd, info, input_section,
10107 rel->r_offset);
10108 if (outrel.r_offset == (bfd_vma) -1)
b34976b6 10109 skip = TRUE;
0bb2d96a 10110 else if (outrel.r_offset == (bfd_vma) -2)
b34976b6 10111 skip = TRUE, relocate = TRUE;
252b5132
RH		 10112 outrel.r_offset += (input_section->output_section->vma
10113 + input_section->output_offset);
f21f3fe0 10114
252b5132 10115 if (skip)
0bb2d96a 10116 memset (&outrel, 0, sizeof outrel);
5e681ec4
PB		 10117 else if (h != NULL
10118 && h->dynindx != -1
0e1862bb 10119 && (!bfd_link_pic (info)
a496fbc8 10120 || !SYMBOLIC_BIND (info, h)
f5385ebf 10121 || !h->def_regular))
5e681ec4 10122 outrel.r_info = ELF32_R_INFO (h->dynindx, r_type);
252b5132
RH		 10123 else
10124 {
a16385dc
MM		 10125 int symbol;
10126
5e681ec4 10127 /* This symbol is local, or marked to become local. */
34e77a92 10128 BFD_ASSERT (r_type == R_ARM_ABS32 || r_type == R_ARM_ABS32_NOI);
a16385dc 10129 if (globals->symbian_p)
6366ff1e 10130 {
74541ad4
AM		 10131 asection *osec;
10132
6366ff1e
MM		 10133 /* On Symbian OS, the data segment and text segement
10134 can be relocated independently. Therefore, we
10135 must indicate the segment to which this
10136 relocation is relative. The BPABI allows us to
10137 use any symbol in the right segment; we just use
10138 the section symbol as it is convenient. (We
10139 cannot use the symbol given by "h" directly as it
74541ad4
AM		 10140 will not appear in the dynamic symbol table.)
10141
10142 Note that the dynamic linker ignores the section
10143 symbol value, so we don't subtract osec->vma
10144 from the emitted reloc addend. */
10dbd1f3 10145 if (sym_sec)
74541ad4 10146 osec = sym_sec->output_section;
10dbd1f3 10147 else
74541ad4
AM		 10148 osec = input_section->output_section;
10149 symbol = elf_section_data (osec)->dynindx;
10150 if (symbol == 0)
10151 {
10152 struct elf_link_hash_table *htab = elf_hash_table (info);
10153
10154 if ((osec->flags & SEC_READONLY) == 0
10155 && htab->data_index_section != NULL)
10156 osec = htab->data_index_section;
10157 else
10158 osec = htab->text_index_section;
10159 symbol = elf_section_data (osec)->dynindx;
10160 }
6366ff1e
MM		 10161 BFD_ASSERT (symbol != 0);
10162 }
a16385dc
MM		 10163 else
10164 /* On SVR4-ish systems, the dynamic loader cannot
10165 relocate the text and data segments independently,
10166 so the symbol does not matter. */
10167 symbol = 0;
34e77a92
RS		 10168 if (dynreloc_st_type == STT_GNU_IFUNC)
10169 /* We have an STT_GNU_IFUNC symbol that doesn't resolve
10170 to the .iplt entry. Instead, every non-call reference
10171 must use an R_ARM_IRELATIVE relocation to obtain the
10172 correct run-time address. */
10173 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_IRELATIVE);
10174 else
10175 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_RELATIVE);
00a97672
RS		 10176 if (globals->use_rel)
10177 relocate = TRUE;
10178 else
34e77a92 10179 outrel.r_addend += dynreloc_value;
252b5132 10180 }
f21f3fe0 10181
47beaa6a 10182 elf32_arm_add_dynreloc (output_bfd, info, sreloc, &outrel);
9a5aca8c 10183
f21f3fe0 10184 /* If this reloc is against an external symbol, we do not want to
252b5132 10185 fiddle with the addend. Otherwise, we need to include the symbol
9b485d32 10186 value so that it becomes an addend for the dynamic reloc. */
252b5132
RH		 10187 if (! relocate)
10188 return bfd_reloc_ok;
9a5aca8c 10189
f21f3fe0 10190 return _bfd_final_link_relocate (howto, input_bfd, input_section,
34e77a92
RS		 10191 contents, rel->r_offset,
10192 dynreloc_value, (bfd_vma) 0);
252b5132
RH		 10193 }
10194 else switch (r_type)
10195 {
00a97672
RS		 10196 case R_ARM_ABS12:
10197 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
10198
dfc5f959 10199 case R_ARM_XPC25: /* Arm BLX instruction. */
5b5bb741
PB		 10200 case R_ARM_CALL:
10201 case R_ARM_JUMP24:
8029a119 10202 case R_ARM_PC24: /* Arm B/BL instruction. */
7359ea65 10203 case R_ARM_PLT32:
906e58ca 10204 {
906e58ca
NC		 10205 struct elf32_arm_stub_hash_entry *stub_entry = NULL;
10206
dfc5f959 10207 if (r_type == R_ARM_XPC25)
252b5132 10208 {
dfc5f959
NC		 10209 /* Check for Arm calling Arm function. */
10210 /* FIXME: Should we translate the instruction into a BL
10211 instruction instead ? */
35fc36a8 10212 if (branch_type != ST_BRANCH_TO_THUMB)
d003868e
AM		 10213 (*_bfd_error_handler)
10214 (_("\%B: Warning: Arm BLX instruction targets Arm function '%s'."),
10215 input_bfd,
10216 h ? h->root.root.string : "(local)");
dfc5f959 10217 }
155d87d7 10218 else if (r_type == R_ARM_PC24)
dfc5f959
NC		 10219 {
10220 /* Check for Arm calling Thumb function. */
35fc36a8 10221 if (branch_type == ST_BRANCH_TO_THUMB)
dfc5f959 10222 {
f2a9dd69
DJ		 10223 if (elf32_arm_to_thumb_stub (info, sym_name, input_bfd,
10224 output_bfd, input_section,
10225 hit_data, sym_sec, rel->r_offset,
10226 signed_addend, value,
10227 error_message))
10228 return bfd_reloc_ok;
10229 else
10230 return bfd_reloc_dangerous;
dfc5f959 10231 }
252b5132 10232 }
ba96a88f 10233
906e58ca 10234 /* Check if a stub has to be inserted because the
8029a119 10235 destination is too far or we are changing mode. */
155d87d7
CL		 10236 if ( r_type == R_ARM_CALL
10237 || r_type == R_ARM_JUMP24
10238 || r_type == R_ARM_PLT32)
906e58ca 10239 {
fe33d2fa
CL		 10240 enum elf32_arm_stub_type stub_type = arm_stub_none;
10241 struct elf32_arm_link_hash_entry *hash;
10242
10243 hash = (struct elf32_arm_link_hash_entry *) h;
10244 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 10245 st_type, &branch_type,
10246 hash, value, sym_sec,
fe33d2fa 10247 input_bfd, sym_name);
5fa9e92f 10248
fe33d2fa 10249 if (stub_type != arm_stub_none)
906e58ca
NC		 10250 {
10251 /* The target is out of reach, so redirect the
10252 branch to the local stub for this function. */
906e58ca
NC		 10253 stub_entry = elf32_arm_get_stub_entry (input_section,
10254 sym_sec, h,
fe33d2fa
CL		 10255 rel, globals,
10256 stub_type);
9cd3e4e5
NC		 10257 {
10258 if (stub_entry != NULL)
10259 value = (stub_entry->stub_offset
10260 + stub_entry->stub_sec->output_offset
10261 + stub_entry->stub_sec->output_section->vma);
10262
10263 if (plt_offset != (bfd_vma) -1)
10264 *unresolved_reloc_p = FALSE;
10265 }
906e58ca 10266 }
fe33d2fa
CL		 10267 else
10268 {
10269 /* If the call goes through a PLT entry, make sure to
10270 check distance to the right destination address. */
34e77a92 10271 if (plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 10272 {
10273 value = (splt->output_section->vma
10274 + splt->output_offset
34e77a92 10275 + plt_offset);
fe33d2fa
CL		 10276 *unresolved_reloc_p = FALSE;
10277 /* The PLT entry is in ARM mode, regardless of the
10278 target function. */
35fc36a8 10279 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 10280 }
10281 }
906e58ca
NC		 10282 }
10283
dea514f5
PB		 10284 /* The ARM ELF ABI says that this reloc is computed as: S - P + A
10285 where:
10286 S is the address of the symbol in the relocation.
10287 P is address of the instruction being relocated.
10288 A is the addend (extracted from the instruction) in bytes.
10289
10290 S is held in 'value'.
10291 P is the base address of the section containing the
10292 instruction plus the offset of the reloc into that
10293 section, ie:
10294 (input_section->output_section->vma +
10295 input_section->output_offset +
10296 rel->r_offset).
10297 A is the addend, converted into bytes, ie:
10298 (signed_addend * 4)
10299
10300 Note: None of these operations have knowledge of the pipeline
10301 size of the processor, thus it is up to the assembler to
10302 encode this information into the addend. */
10303 value -= (input_section->output_section->vma
10304 + input_section->output_offset);
10305 value -= rel->r_offset;
4e7fd91e
PB		 10306 if (globals->use_rel)
10307 value += (signed_addend << howto->size);
10308 else
10309 /* RELA addends do not have to be adjusted by howto->size. */
10310 value += signed_addend;
23080146 10311
dcb5e6e6
NC		 10312 signed_addend = value;
10313 signed_addend >>= howto->rightshift;
9a5aca8c 10314
5ab79981 10315 /* A branch to an undefined weak symbol is turned into a jump to
ffcb4889 10316 the next instruction unless a PLT entry will be created.
77b4f08f 10317 Do the same for local undefined symbols (but not for STN_UNDEF).
cd1dac3d
DG		 10318 The jump to the next instruction is optimized as a NOP depending
10319 on the architecture. */
ffcb4889 10320 if (h ? (h->root.type == bfd_link_hash_undefweak
34e77a92 10321 && plt_offset == (bfd_vma) -1)
77b4f08f 10322 : r_symndx != STN_UNDEF && bfd_is_und_section (sym_sec))
5ab79981 10323 {
cd1dac3d
DG		 10324 value = (bfd_get_32 (input_bfd, hit_data) & 0xf0000000);
10325
10326 if (arch_has_arm_nop (globals))
10327 value |= 0x0320f000;
10328 else
10329 value |= 0x01a00000; /* Using pre-UAL nop: mov r0, r0. */
5ab79981
PB		 10330 }
10331 else
59f2c4e7 10332 {
9b485d32 10333 /* Perform a signed range check. */
dcb5e6e6 10334 if ( signed_addend > ((bfd_signed_vma) (howto->dst_mask >> 1))
59f2c4e7
NC		 10335 || signed_addend < - ((bfd_signed_vma) ((howto->dst_mask + 1) >> 1)))
10336 return bfd_reloc_overflow;
9a5aca8c 10337
5ab79981 10338 addend = (value & 2);
39b41c9c 10339
5ab79981
PB		 10340 value = (signed_addend & howto->dst_mask)
10341 | (bfd_get_32 (input_bfd, hit_data) & (~ howto->dst_mask));
39b41c9c 10342
5ab79981
PB		 10343 if (r_type == R_ARM_CALL)
10344 {
155d87d7 10345 /* Set the H bit in the BLX instruction. */
35fc36a8 10346 if (branch_type == ST_BRANCH_TO_THUMB)
155d87d7
CL		 10347 {
10348 if (addend)
10349 value |= (1 << 24);
10350 else
10351 value &= ~(bfd_vma)(1 << 24);
10352 }
10353
5ab79981 10354 /* Select the correct instruction (BL or BLX). */
906e58ca 10355 /* Only if we are not handling a BL to a stub. In this
8029a119 10356 case, mode switching is performed by the stub. */
35fc36a8 10357 if (branch_type == ST_BRANCH_TO_THUMB && !stub_entry)
5ab79981 10358 value |= (1 << 28);
63e1a0fc 10359 else if (stub_entry || branch_type != ST_BRANCH_UNKNOWN)
5ab79981
PB		 10360 {
10361 value &= ~(bfd_vma)(1 << 28);
10362 value |= (1 << 24);
10363 }
39b41c9c
PB		 10364 }
10365 }
906e58ca 10366 }
252b5132 10367 break;
f21f3fe0 10368
252b5132
RH		 10369 case R_ARM_ABS32:
10370 value += addend;
35fc36a8 10371 if (branch_type == ST_BRANCH_TO_THUMB)
252b5132
RH		 10372 value |= 1;
10373 break;
f21f3fe0 10374
bb224fc3
MS		 10375 case R_ARM_ABS32_NOI:
10376 value += addend;
10377 break;
10378
252b5132 10379 case R_ARM_REL32:
a8bc6c78 10380 value += addend;
35fc36a8 10381 if (branch_type == ST_BRANCH_TO_THUMB)
a8bc6c78 10382 value |= 1;
252b5132 10383 value -= (input_section->output_section->vma
62efb346 10384 + input_section->output_offset + rel->r_offset);
252b5132 10385 break;
eb043451 10386
bb224fc3
MS		 10387 case R_ARM_REL32_NOI:
10388 value += addend;
10389 value -= (input_section->output_section->vma
10390 + input_section->output_offset + rel->r_offset);
10391 break;
10392
eb043451
PB		 10393 case R_ARM_PREL31:
10394 value -= (input_section->output_section->vma
10395 + input_section->output_offset + rel->r_offset);
10396 value += signed_addend;
10397 if (! h || h->root.type != bfd_link_hash_undefweak)
10398 {
8029a119 10399 /* Check for overflow. */
eb043451
PB		 10400 if ((value ^ (value >> 1)) & (1 << 30))
10401 return bfd_reloc_overflow;
10402 }
10403 value &= 0x7fffffff;
10404 value |= (bfd_get_32 (input_bfd, hit_data) & 0x80000000);
35fc36a8 10405 if (branch_type == ST_BRANCH_TO_THUMB)
eb043451
PB		 10406 value |= 1;
10407 break;
252b5132 10408 }
f21f3fe0 10409
252b5132
RH		 10410 bfd_put_32 (input_bfd, value, hit_data);
10411 return bfd_reloc_ok;
10412
10413 case R_ARM_ABS8:
fd0fd00c
MJ		 10414 /* PR 16202: Refectch the addend using the correct size. */
10415 if (globals->use_rel)
10416 addend = bfd_get_8 (input_bfd, hit_data);
252b5132 10417 value += addend;
4e67d4ca
DG		 10418
10419 /* There is no way to tell whether the user intended to use a signed or
10420 unsigned addend. When checking for overflow we accept either,
10421 as specified by the AAELF. */
10422 if ((long) value > 0xff || (long) value < -0x80)
252b5132
RH		 10423 return bfd_reloc_overflow;
10424
10425 bfd_put_8 (input_bfd, value, hit_data);
10426 return bfd_reloc_ok;
10427
10428 case R_ARM_ABS16:
fd0fd00c
MJ		 10429 /* PR 16202: Refectch the addend using the correct size. */
10430 if (globals->use_rel)
10431 addend = bfd_get_16 (input_bfd, hit_data);
252b5132
RH		 10432 value += addend;
10433
4e67d4ca
DG		 10434 /* See comment for R_ARM_ABS8. */
10435 if ((long) value > 0xffff || (long) value < -0x8000)
252b5132
RH		 10436 return bfd_reloc_overflow;
10437
10438 bfd_put_16 (input_bfd, value, hit_data);
10439 return bfd_reloc_ok;
10440
252b5132 10441 case R_ARM_THM_ABS5:
9b485d32 10442 /* Support ldr and str instructions for the thumb. */
4e7fd91e
PB		 10443 if (globals->use_rel)
10444 {
10445 /* Need to refetch addend. */
10446 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
10447 /* ??? Need to determine shift amount from operand size. */
10448 addend >>= howto->rightshift;
10449 }
252b5132
RH		 10450 value += addend;
10451
10452 /* ??? Isn't value unsigned? */
10453 if ((long) value > 0x1f || (long) value < -0x10)
10454 return bfd_reloc_overflow;
10455
10456 /* ??? Value needs to be properly shifted into place first. */
10457 value |= bfd_get_16 (input_bfd, hit_data) & 0xf83f;
10458 bfd_put_16 (input_bfd, value, hit_data);
10459 return bfd_reloc_ok;
10460
2cab6cc3
MS		 10461 case R_ARM_THM_ALU_PREL_11_0:
10462 /* Corresponds to: addw.w reg, pc, #offset (and similarly for subw). */
10463 {
10464 bfd_vma insn;
10465 bfd_signed_vma relocation;
10466
10467 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 10468 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 10469
99059e56
RM		 10470 if (globals->use_rel)
10471 {
10472 signed_addend = (insn & 0xff) | ((insn & 0x7000) >> 4)
10473 | ((insn & (1 << 26)) >> 15);
10474 if (insn & 0xf00000)
10475 signed_addend = -signed_addend;
10476 }
2cab6cc3
MS		 10477
10478 relocation = value + signed_addend;
79f08007 10479 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10480 + input_section->output_offset
10481 + rel->r_offset);
2cab6cc3 10482
b6518b38 10483 value = relocation;
2cab6cc3 10484
99059e56
RM		 10485 if (value >= 0x1000)
10486 return bfd_reloc_overflow;
2cab6cc3
MS		 10487
10488 insn = (insn & 0xfb0f8f00) | (value & 0xff)
99059e56
RM		 10489 | ((value & 0x700) << 4)
10490 | ((value & 0x800) << 15);
10491 if (relocation < 0)
10492 insn |= 0xa00000;
2cab6cc3
MS		 10493
10494 bfd_put_16 (input_bfd, insn >> 16, hit_data);
10495 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
10496
99059e56 10497 return bfd_reloc_ok;
2cab6cc3
MS		 10498 }
10499
e1ec24c6
NC		 10500 case R_ARM_THM_PC8:
10501 /* PR 10073: This reloc is not generated by the GNU toolchain,
10502 but it is supported for compatibility with third party libraries
10503 generated by other compilers, specifically the ARM/IAR. */
10504 {
10505 bfd_vma insn;
10506 bfd_signed_vma relocation;
10507
10508 insn = bfd_get_16 (input_bfd, hit_data);
10509
99059e56 10510 if (globals->use_rel)
79f08007 10511 addend = ((((insn & 0x00ff) << 2) + 4) & 0x3ff) -4;
e1ec24c6
NC		 10512
10513 relocation = value + addend;
79f08007 10514 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10515 + input_section->output_offset
10516 + rel->r_offset);
e1ec24c6 10517
b6518b38 10518 value = relocation;
e1ec24c6
NC		 10519
10520 /* We do not check for overflow of this reloc. Although strictly
10521 speaking this is incorrect, it appears to be necessary in order
10522 to work with IAR generated relocs. Since GCC and GAS do not
10523 generate R_ARM_THM_PC8 relocs, the lack of a check should not be
10524 a problem for them. */
10525 value &= 0x3fc;
10526
10527 insn = (insn & 0xff00) | (value >> 2);
10528
10529 bfd_put_16 (input_bfd, insn, hit_data);
10530
99059e56 10531 return bfd_reloc_ok;
e1ec24c6
NC		 10532 }
10533
2cab6cc3
MS		 10534 case R_ARM_THM_PC12:
10535 /* Corresponds to: ldr.w reg, [pc, #offset]. */
10536 {
10537 bfd_vma insn;
10538 bfd_signed_vma relocation;
10539
10540 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 10541 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 10542
99059e56
RM		 10543 if (globals->use_rel)
10544 {
10545 signed_addend = insn & 0xfff;
10546 if (!(insn & (1 << 23)))
10547 signed_addend = -signed_addend;
10548 }
2cab6cc3
MS		 10549
10550 relocation = value + signed_addend;
79f08007 10551 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10552 + input_section->output_offset
10553 + rel->r_offset);
2cab6cc3 10554
b6518b38 10555 value = relocation;
2cab6cc3 10556
99059e56
RM		 10557 if (value >= 0x1000)
10558 return bfd_reloc_overflow;
2cab6cc3
MS		 10559
10560 insn = (insn & 0xff7ff000) | value;
99059e56
RM		 10561 if (relocation >= 0)
10562 insn |= (1 << 23);
2cab6cc3
MS		 10563
10564 bfd_put_16 (input_bfd, insn >> 16, hit_data);
10565 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
10566
99059e56 10567 return bfd_reloc_ok;
2cab6cc3
MS		 10568 }
10569
dfc5f959 10570 case R_ARM_THM_XPC22:
c19d1205 10571 case R_ARM_THM_CALL:
bd97cb95 10572 case R_ARM_THM_JUMP24:
dfc5f959 10573 /* Thumb BL (branch long instruction). */
252b5132 10574 {
b34976b6 10575 bfd_vma relocation;
99059e56 10576 bfd_vma reloc_sign;
b34976b6
AM		 10577 bfd_boolean overflow = FALSE;
10578 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
10579 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
e95de063
MS		 10580 bfd_signed_vma reloc_signed_max;
10581 bfd_signed_vma reloc_signed_min;
b34976b6 10582 bfd_vma check;
252b5132 10583 bfd_signed_vma signed_check;
e95de063 10584 int bitsize;
cd1dac3d 10585 const int thumb2 = using_thumb2 (globals);
5e866f5a 10586 const int thumb2_bl = using_thumb2_bl (globals);
252b5132 10587
5ab79981 10588 /* A branch to an undefined weak symbol is turned into a jump to
cd1dac3d
DG		 10589 the next instruction unless a PLT entry will be created.
10590 The jump to the next instruction is optimized as a NOP.W for
10591 Thumb-2 enabled architectures. */
19540007 10592 if (h && h->root.type == bfd_link_hash_undefweak
34e77a92 10593 && plt_offset == (bfd_vma) -1)
5ab79981 10594 {
60a019a0 10595 if (thumb2)
cd1dac3d
DG		 10596 {
10597 bfd_put_16 (input_bfd, 0xf3af, hit_data);
10598 bfd_put_16 (input_bfd, 0x8000, hit_data + 2);
10599 }
10600 else
10601 {
10602 bfd_put_16 (input_bfd, 0xe000, hit_data);
10603 bfd_put_16 (input_bfd, 0xbf00, hit_data + 2);
10604 }
5ab79981
PB		 10605 return bfd_reloc_ok;
10606 }
10607
e95de063 10608 /* Fetch the addend. We use the Thumb-2 encoding (backwards compatible
99059e56 10609 with Thumb-1) involving the J1 and J2 bits. */
4e7fd91e
PB		 10610 if (globals->use_rel)
10611 {
99059e56
RM		 10612 bfd_vma s = (upper_insn & (1 << 10)) >> 10;
10613 bfd_vma upper = upper_insn & 0x3ff;
10614 bfd_vma lower = lower_insn & 0x7ff;
e95de063
MS		 10615 bfd_vma j1 = (lower_insn & (1 << 13)) >> 13;
10616 bfd_vma j2 = (lower_insn & (1 << 11)) >> 11;
99059e56
RM		 10617 bfd_vma i1 = j1 ^ s ? 0 : 1;
10618 bfd_vma i2 = j2 ^ s ? 0 : 1;
e95de063 10619
99059e56
RM		 10620 addend = (i1 << 23) | (i2 << 22) | (upper << 12) | (lower << 1);
10621 /* Sign extend. */
10622 addend = (addend | ((s ? 0 : 1) << 24)) - (1 << 24);
e95de063 10623
4e7fd91e
PB		 10624 signed_addend = addend;
10625 }
cb1afa5c 10626
dfc5f959
NC		 10627 if (r_type == R_ARM_THM_XPC22)
10628 {
10629 /* Check for Thumb to Thumb call. */
10630 /* FIXME: Should we translate the instruction into a BL
10631 instruction instead ? */
35fc36a8 10632 if (branch_type == ST_BRANCH_TO_THUMB)
d003868e
AM		 10633 (*_bfd_error_handler)
10634 (_("%B: Warning: Thumb BLX instruction targets thumb function '%s'."),
10635 input_bfd,
10636 h ? h->root.root.string : "(local)");
dfc5f959
NC		 10637 }
10638 else
252b5132 10639 {
dfc5f959
NC		 10640 /* If it is not a call to Thumb, assume call to Arm.
10641 If it is a call relative to a section name, then it is not a
b7693d02
DJ		 10642 function call at all, but rather a long jump. Calls through
10643 the PLT do not require stubs. */
34e77a92 10644 if (branch_type == ST_BRANCH_TO_ARM && plt_offset == (bfd_vma) -1)
dfc5f959 10645 {
bd97cb95 10646 if (globals->use_blx && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 10647 {
10648 /* Convert BL to BLX. */
10649 lower_insn = (lower_insn & ~0x1000) | 0x0800;
10650 }
155d87d7
CL		 10651 else if (( r_type != R_ARM_THM_CALL)
10652 && (r_type != R_ARM_THM_JUMP24))
8029a119
NC		 10653 {
10654 if (elf32_thumb_to_arm_stub
10655 (info, sym_name, input_bfd, output_bfd, input_section,
10656 hit_data, sym_sec, rel->r_offset, signed_addend, value,
10657 error_message))
10658 return bfd_reloc_ok;
10659 else
10660 return bfd_reloc_dangerous;
10661 }
da5938a2 10662 }
35fc36a8
RS		 10663 else if (branch_type == ST_BRANCH_TO_THUMB
10664 && globals->use_blx
bd97cb95 10665 && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 10666 {
10667 /* Make sure this is a BL. */
10668 lower_insn |= 0x1800;
10669 }
252b5132 10670 }
f21f3fe0 10671
fe33d2fa 10672 enum elf32_arm_stub_type stub_type = arm_stub_none;
155d87d7 10673 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24)
906e58ca
NC		 10674 {
10675 /* Check if a stub has to be inserted because the destination
8029a119 10676 is too far. */
fe33d2fa
CL		 10677 struct elf32_arm_stub_hash_entry *stub_entry;
10678 struct elf32_arm_link_hash_entry *hash;
10679
10680 hash = (struct elf32_arm_link_hash_entry *) h;
10681
10682 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 10683 st_type, &branch_type,
10684 hash, value, sym_sec,
fe33d2fa
CL		 10685 input_bfd, sym_name);
10686
10687 if (stub_type != arm_stub_none)
906e58ca
NC		 10688 {
10689 /* The target is out of reach or we are changing modes, so
10690 redirect the branch to the local stub for this
10691 function. */
10692 stub_entry = elf32_arm_get_stub_entry (input_section,
10693 sym_sec, h,
fe33d2fa
CL		 10694 rel, globals,
10695 stub_type);
906e58ca 10696 if (stub_entry != NULL)
9cd3e4e5
NC		 10697 {
10698 value = (stub_entry->stub_offset
10699 + stub_entry->stub_sec->output_offset
10700 + stub_entry->stub_sec->output_section->vma);
10701
10702 if (plt_offset != (bfd_vma) -1)
10703 *unresolved_reloc_p = FALSE;
10704 }
906e58ca 10705
f4ac8484 10706 /* If this call becomes a call to Arm, force BLX. */
155d87d7 10707 if (globals->use_blx && (r_type == R_ARM_THM_CALL))
f4ac8484
DJ		 10708 {
10709 if ((stub_entry
10710 && !arm_stub_is_thumb (stub_entry->stub_type))
35fc36a8 10711 || branch_type != ST_BRANCH_TO_THUMB)
f4ac8484
DJ		 10712 lower_insn = (lower_insn & ~0x1000) | 0x0800;
10713 }
906e58ca
NC		 10714 }
10715 }
10716
fe33d2fa 10717 /* Handle calls via the PLT. */
34e77a92 10718 if (stub_type == arm_stub_none && plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 10719 {
10720 value = (splt->output_section->vma
10721 + splt->output_offset
34e77a92 10722 + plt_offset);
fe33d2fa 10723
eed94f8f
NC		 10724 if (globals->use_blx
10725 && r_type == R_ARM_THM_CALL
10726 && ! using_thumb_only (globals))
fe33d2fa
CL		 10727 {
10728 /* If the Thumb BLX instruction is available, convert
10729 the BL to a BLX instruction to call the ARM-mode
10730 PLT entry. */
10731 lower_insn = (lower_insn & ~0x1000) | 0x0800;
35fc36a8 10732 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 10733 }
10734 else
10735 {
eed94f8f
NC		 10736 if (! using_thumb_only (globals))
10737 /* Target the Thumb stub before the ARM PLT entry. */
10738 value -= PLT_THUMB_STUB_SIZE;
35fc36a8 10739 branch_type = ST_BRANCH_TO_THUMB;
fe33d2fa
CL		 10740 }
10741 *unresolved_reloc_p = FALSE;
10742 }
10743
ba96a88f 10744 relocation = value + signed_addend;
f21f3fe0 10745
252b5132 10746 relocation -= (input_section->output_section->vma
ba96a88f
NC		 10747 + input_section->output_offset
10748 + rel->r_offset);
9a5aca8c 10749
252b5132
RH		 10750 check = relocation >> howto->rightshift;
10751
10752 /* If this is a signed value, the rightshift just dropped
10753 leading 1 bits (assuming twos complement). */
10754 if ((bfd_signed_vma) relocation >= 0)
10755 signed_check = check;
10756 else
10757 signed_check = check | ~((bfd_vma) -1 >> howto->rightshift);
10758
e95de063
MS		 10759 /* Calculate the permissable maximum and minimum values for
10760 this relocation according to whether we're relocating for
10761 Thumb-2 or not. */
10762 bitsize = howto->bitsize;
5e866f5a 10763 if (!thumb2_bl)
e95de063 10764 bitsize -= 2;
f6ebfac0 10765 reloc_signed_max = (1 << (bitsize - 1)) - 1;
e95de063
MS		 10766 reloc_signed_min = ~reloc_signed_max;
10767
252b5132 10768 /* Assumes two's complement. */
ba96a88f 10769 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
b34976b6 10770 overflow = TRUE;
252b5132 10771
bd97cb95 10772 if ((lower_insn & 0x5000) == 0x4000)
c62e1cc3
NC		 10773 /* For a BLX instruction, make sure that the relocation is rounded up
10774 to a word boundary. This follows the semantics of the instruction
10775 which specifies that bit 1 of the target address will come from bit
10776 1 of the base address. */
10777 relocation = (relocation + 2) & ~ 3;
cb1afa5c 10778
e95de063
MS		 10779 /* Put RELOCATION back into the insn. Assumes two's complement.
10780 We use the Thumb-2 encoding, which is safe even if dealing with
10781 a Thumb-1 instruction by virtue of our overflow check above. */
99059e56 10782 reloc_sign = (signed_check < 0) ? 1 : 0;
e95de063 10783 upper_insn = (upper_insn & ~(bfd_vma) 0x7ff)
99059e56
RM		 10784 | ((relocation >> 12) & 0x3ff)
10785 | (reloc_sign << 10);
906e58ca 10786 lower_insn = (lower_insn & ~(bfd_vma) 0x2fff)
99059e56
RM		 10787 | (((!((relocation >> 23) & 1)) ^ reloc_sign) << 13)
10788 | (((!((relocation >> 22) & 1)) ^ reloc_sign) << 11)
10789 | ((relocation >> 1) & 0x7ff);
c62e1cc3 10790
252b5132
RH		 10791 /* Put the relocated value back in the object file: */
10792 bfd_put_16 (input_bfd, upper_insn, hit_data);
10793 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
10794
10795 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
10796 }
10797 break;
10798
c19d1205
ZW		 10799 case R_ARM_THM_JUMP19:
10800 /* Thumb32 conditional branch instruction. */
10801 {
10802 bfd_vma relocation;
10803 bfd_boolean overflow = FALSE;
10804 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
10805 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
a00a1f35
MS		 10806 bfd_signed_vma reloc_signed_max = 0xffffe;
10807 bfd_signed_vma reloc_signed_min = -0x100000;
c19d1205 10808 bfd_signed_vma signed_check;
c5423981
TG		 10809 enum elf32_arm_stub_type stub_type = arm_stub_none;
10810 struct elf32_arm_stub_hash_entry *stub_entry;
10811 struct elf32_arm_link_hash_entry *hash;
c19d1205
ZW		 10812
10813 /* Need to refetch the addend, reconstruct the top three bits,
10814 and squish the two 11 bit pieces together. */
10815 if (globals->use_rel)
10816 {
10817 bfd_vma S = (upper_insn & 0x0400) >> 10;
a00a1f35 10818 bfd_vma upper = (upper_insn & 0x003f);
c19d1205
ZW		 10819 bfd_vma J1 = (lower_insn & 0x2000) >> 13;
10820 bfd_vma J2 = (lower_insn & 0x0800) >> 11;
10821 bfd_vma lower = (lower_insn & 0x07ff);
10822
a00a1f35
MS		 10823 upper |= J1 << 6;
10824 upper |= J2 << 7;
10825 upper |= (!S) << 8;
c19d1205
ZW		 10826 upper -= 0x0100; /* Sign extend. */
10827
10828 addend = (upper << 12) | (lower << 1);
10829 signed_addend = addend;
10830 }
10831
bd97cb95 10832 /* Handle calls via the PLT. */
34e77a92 10833 if (plt_offset != (bfd_vma) -1)
bd97cb95
DJ		 10834 {
10835 value = (splt->output_section->vma
10836 + splt->output_offset
34e77a92 10837 + plt_offset);
bd97cb95
DJ		 10838 /* Target the Thumb stub before the ARM PLT entry. */
10839 value -= PLT_THUMB_STUB_SIZE;
10840 *unresolved_reloc_p = FALSE;
10841 }
10842
c5423981
TG		 10843 hash = (struct elf32_arm_link_hash_entry *)h;
10844
10845 stub_type = arm_type_of_stub (info, input_section, rel,
10846 st_type, &branch_type,
10847 hash, value, sym_sec,
10848 input_bfd, sym_name);
10849 if (stub_type != arm_stub_none)
10850 {
10851 stub_entry = elf32_arm_get_stub_entry (input_section,
10852 sym_sec, h,
10853 rel, globals,
10854 stub_type);
10855 if (stub_entry != NULL)
10856 {
10857 value = (stub_entry->stub_offset
10858 + stub_entry->stub_sec->output_offset
10859 + stub_entry->stub_sec->output_section->vma);
10860 }
10861 }
c19d1205 10862
99059e56 10863 relocation = value + signed_addend;
c19d1205
ZW		 10864 relocation -= (input_section->output_section->vma
10865 + input_section->output_offset
10866 + rel->r_offset);
a00a1f35 10867 signed_check = (bfd_signed_vma) relocation;
c19d1205 10868
c19d1205
ZW		 10869 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
10870 overflow = TRUE;
10871
10872 /* Put RELOCATION back into the insn. */
10873 {
10874 bfd_vma S = (relocation & 0x00100000) >> 20;
10875 bfd_vma J2 = (relocation & 0x00080000) >> 19;
10876 bfd_vma J1 = (relocation & 0x00040000) >> 18;
10877 bfd_vma hi = (relocation & 0x0003f000) >> 12;
10878 bfd_vma lo = (relocation & 0x00000ffe) >> 1;
10879
a00a1f35 10880 upper_insn = (upper_insn & 0xfbc0) | (S << 10) | hi;
c19d1205
ZW		 10881 lower_insn = (lower_insn & 0xd000) | (J1 << 13) | (J2 << 11) | lo;
10882 }
10883
10884 /* Put the relocated value back in the object file: */
10885 bfd_put_16 (input_bfd, upper_insn, hit_data);
10886 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
10887
10888 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
10889 }
10890
10891 case R_ARM_THM_JUMP11:
10892 case R_ARM_THM_JUMP8:
10893 case R_ARM_THM_JUMP6:
51c5503b
NC		 10894 /* Thumb B (branch) instruction). */
10895 {
6cf9e9fe 10896 bfd_signed_vma relocation;
51c5503b
NC		 10897 bfd_signed_vma reloc_signed_max = (1 << (howto->bitsize - 1)) - 1;
10898 bfd_signed_vma reloc_signed_min = ~ reloc_signed_max;
51c5503b
NC		 10899 bfd_signed_vma signed_check;
10900
c19d1205
ZW		 10901 /* CZB cannot jump backward. */
10902 if (r_type == R_ARM_THM_JUMP6)
10903 reloc_signed_min = 0;
10904
4e7fd91e 10905 if (globals->use_rel)
6cf9e9fe 10906 {
4e7fd91e
PB		 10907 /* Need to refetch addend. */
10908 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
10909 if (addend & ((howto->src_mask + 1) >> 1))
10910 {
10911 signed_addend = -1;
10912 signed_addend &= ~ howto->src_mask;
10913 signed_addend |= addend;
10914 }
10915 else
10916 signed_addend = addend;
10917 /* The value in the insn has been right shifted. We need to
10918 undo this, so that we can perform the address calculation
10919 in terms of bytes. */
10920 signed_addend <<= howto->rightshift;
6cf9e9fe 10921 }
6cf9e9fe 10922 relocation = value + signed_addend;
51c5503b
NC		 10923
10924 relocation -= (input_section->output_section->vma
10925 + input_section->output_offset
10926 + rel->r_offset);
10927
6cf9e9fe
NC		 10928 relocation >>= howto->rightshift;
10929 signed_check = relocation;
c19d1205
ZW		 10930
10931 if (r_type == R_ARM_THM_JUMP6)
10932 relocation = ((relocation & 0x0020) << 4) | ((relocation & 0x001f) << 3);
10933 else
10934 relocation &= howto->dst_mask;
51c5503b 10935 relocation |= (bfd_get_16 (input_bfd, hit_data) & (~ howto->dst_mask));
cedb70c5 10936
51c5503b
NC		 10937 bfd_put_16 (input_bfd, relocation, hit_data);
10938
10939 /* Assumes two's complement. */
10940 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
10941 return bfd_reloc_overflow;
10942
10943 return bfd_reloc_ok;
10944 }
cedb70c5 10945
8375c36b
PB		 10946 case R_ARM_ALU_PCREL7_0:
10947 case R_ARM_ALU_PCREL15_8:
10948 case R_ARM_ALU_PCREL23_15:
10949 {
10950 bfd_vma insn;
10951 bfd_vma relocation;
10952
10953 insn = bfd_get_32 (input_bfd, hit_data);
4e7fd91e
PB		 10954 if (globals->use_rel)
10955 {
10956 /* Extract the addend. */
10957 addend = (insn & 0xff) << ((insn & 0xf00) >> 7);
10958 signed_addend = addend;
10959 }
8375c36b
PB		 10960 relocation = value + signed_addend;
10961
10962 relocation -= (input_section->output_section->vma
10963 + input_section->output_offset
10964 + rel->r_offset);
10965 insn = (insn & ~0xfff)
10966 | ((howto->bitpos << 7) & 0xf00)
10967 | ((relocation >> howto->bitpos) & 0xff);
10968 bfd_put_32 (input_bfd, value, hit_data);
10969 }
10970 return bfd_reloc_ok;
10971
252b5132
RH		 10972 case R_ARM_GNU_VTINHERIT:
10973 case R_ARM_GNU_VTENTRY:
10974 return bfd_reloc_ok;
10975
c19d1205 10976 case R_ARM_GOTOFF32:
252b5132 10977 /* Relocation is relative to the start of the
99059e56 10978 global offset table. */
252b5132
RH		 10979
10980 BFD_ASSERT (sgot != NULL);
10981 if (sgot == NULL)
99059e56 10982 return bfd_reloc_notsupported;
9a5aca8c 10983
cedb70c5 10984 /* If we are addressing a Thumb function, we need to adjust the
ee29b9fb
RE		 10985 address by one, so that attempts to call the function pointer will
10986 correctly interpret it as Thumb code. */
35fc36a8 10987 if (branch_type == ST_BRANCH_TO_THUMB)
ee29b9fb
RE		 10988 value += 1;
10989
252b5132 10990 /* Note that sgot->output_offset is not involved in this
99059e56
RM		 10991 calculation. We always want the start of .got. If we
10992 define _GLOBAL_OFFSET_TABLE in a different way, as is
10993 permitted by the ABI, we might have to change this
10994 calculation. */
252b5132 10995 value -= sgot->output_section->vma;
f21f3fe0 10996 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 10997 contents, rel->r_offset, value,
00a97672 10998 rel->r_addend);
252b5132
RH		 10999
11000 case R_ARM_GOTPC:
a7c10850 11001 /* Use global offset table as symbol value. */
252b5132 11002 BFD_ASSERT (sgot != NULL);
f21f3fe0 11003
252b5132 11004 if (sgot == NULL)
99059e56 11005 return bfd_reloc_notsupported;
252b5132 11006
0945cdfd 11007 *unresolved_reloc_p = FALSE;
252b5132 11008 value = sgot->output_section->vma;
f21f3fe0 11009 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11010 contents, rel->r_offset, value,
00a97672 11011 rel->r_addend);
f21f3fe0 11012
252b5132 11013 case R_ARM_GOT32:
eb043451 11014 case R_ARM_GOT_PREL:
252b5132 11015 /* Relocation is to the entry for this symbol in the
99059e56 11016 global offset table. */
252b5132
RH		 11017 if (sgot == NULL)
11018 return bfd_reloc_notsupported;
f21f3fe0 11019
34e77a92
RS		 11020 if (dynreloc_st_type == STT_GNU_IFUNC
11021 && plt_offset != (bfd_vma) -1
11022 && (h == NULL || SYMBOL_REFERENCES_LOCAL (info, h)))
11023 {
11024 /* We have a relocation against a locally-binding STT_GNU_IFUNC
11025 symbol, and the relocation resolves directly to the runtime
11026 target rather than to the .iplt entry. This means that any
11027 .got entry would be the same value as the .igot.plt entry,
11028 so there's no point creating both. */
11029 sgot = globals->root.igotplt;
11030 value = sgot->output_offset + gotplt_offset;
11031 }
11032 else if (h != NULL)
252b5132
RH		 11033 {
11034 bfd_vma off;
f21f3fe0 11035
252b5132
RH		 11036 off = h->got.offset;
11037 BFD_ASSERT (off != (bfd_vma) -1);
b436d854 11038 if ((off & 1) != 0)
252b5132 11039 {
b436d854
RS		 11040 /* We have already processsed one GOT relocation against
11041 this symbol. */
11042 off &= ~1;
11043 if (globals->root.dynamic_sections_created
11044 && !SYMBOL_REFERENCES_LOCAL (info, h))
11045 *unresolved_reloc_p = FALSE;
11046 }
11047 else
11048 {
11049 Elf_Internal_Rela outrel;
11050
6f820c85 11051 if (h->dynindx != -1 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 11052 {
11053 /* If the symbol doesn't resolve locally in a static
11054 object, we have an undefined reference. If the
11055 symbol doesn't resolve locally in a dynamic object,
11056 it should be resolved by the dynamic linker. */
11057 if (globals->root.dynamic_sections_created)
11058 {
11059 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_GLOB_DAT);
11060 *unresolved_reloc_p = FALSE;
11061 }
11062 else
11063 outrel.r_info = 0;
11064 outrel.r_addend = 0;
11065 }
252b5132
RH		 11066 else
11067 {
34e77a92 11068 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 11069 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
0e1862bb 11070 else if (bfd_link_pic (info) &&
31943882
WN		 11071 (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
11072 || h->root.type != bfd_link_hash_undefweak))
99059e56
RM		 11073 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
11074 else
11075 outrel.r_info = 0;
34e77a92 11076 outrel.r_addend = dynreloc_value;
b436d854 11077 }
ee29b9fb 11078
b436d854
RS		 11079 /* The GOT entry is initialized to zero by default.
11080 See if we should install a different value. */
11081 if (outrel.r_addend != 0
11082 && (outrel.r_info == 0 || globals->use_rel))
11083 {
11084 bfd_put_32 (output_bfd, outrel.r_addend,
11085 sgot->contents + off);
11086 outrel.r_addend = 0;
252b5132 11087 }
f21f3fe0 11088
b436d854
RS		 11089 if (outrel.r_info != 0)
11090 {
11091 outrel.r_offset = (sgot->output_section->vma
11092 + sgot->output_offset
11093 + off);
11094 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
11095 }
11096 h->got.offset |= 1;
11097 }
252b5132
RH		 11098 value = sgot->output_offset + off;
11099 }
11100 else
11101 {
11102 bfd_vma off;
f21f3fe0 11103
252b5132
RH		 11104 BFD_ASSERT (local_got_offsets != NULL &&
11105 local_got_offsets[r_symndx] != (bfd_vma) -1);
f21f3fe0 11106
252b5132 11107 off = local_got_offsets[r_symndx];
f21f3fe0 11108
252b5132
RH		 11109 /* The offset must always be a multiple of 4. We use the
11110 least significant bit to record whether we have already
9b485d32 11111 generated the necessary reloc. */
252b5132
RH		 11112 if ((off & 1) != 0)
11113 off &= ~1;
11114 else
11115 {
00a97672 11116 if (globals->use_rel)
34e77a92 11117 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + off);
f21f3fe0 11118
0e1862bb 11119 if (bfd_link_pic (info) || dynreloc_st_type == STT_GNU_IFUNC)
252b5132 11120 {
947216bf 11121 Elf_Internal_Rela outrel;
f21f3fe0 11122
34e77a92 11123 outrel.r_addend = addend + dynreloc_value;
252b5132 11124 outrel.r_offset = (sgot->output_section->vma
f21f3fe0 11125 + sgot->output_offset
252b5132 11126 + off);
34e77a92 11127 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 11128 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
34e77a92
RS		 11129 else
11130 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
47beaa6a 11131 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
252b5132 11132 }
f21f3fe0 11133
252b5132
RH		 11134 local_got_offsets[r_symndx] |= 1;
11135 }
f21f3fe0 11136
252b5132
RH		 11137 value = sgot->output_offset + off;
11138 }
eb043451
PB		 11139 if (r_type != R_ARM_GOT32)
11140 value += sgot->output_section->vma;
9a5aca8c 11141
f21f3fe0 11142 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11143 contents, rel->r_offset, value,
00a97672 11144 rel->r_addend);
f21f3fe0 11145
ba93b8ac
DJ		 11146 case R_ARM_TLS_LDO32:
11147 value = value - dtpoff_base (info);
11148
11149 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 11150 contents, rel->r_offset, value,
11151 rel->r_addend);
ba93b8ac
DJ		 11152
11153 case R_ARM_TLS_LDM32:
11154 {
11155 bfd_vma off;
11156
362d30a1 11157 if (sgot == NULL)
ba93b8ac
DJ		 11158 abort ();
11159
11160 off = globals->tls_ldm_got.offset;
11161
11162 if ((off & 1) != 0)
11163 off &= ~1;
11164 else
11165 {
11166 /* If we don't know the module number, create a relocation
11167 for it. */
0e1862bb 11168 if (bfd_link_pic (info))
ba93b8ac
DJ		 11169 {
11170 Elf_Internal_Rela outrel;
ba93b8ac 11171
362d30a1 11172 if (srelgot == NULL)
ba93b8ac
DJ		 11173 abort ();
11174
00a97672 11175 outrel.r_addend = 0;
362d30a1
RS		 11176 outrel.r_offset = (sgot->output_section->vma
11177 + sgot->output_offset + off);
ba93b8ac
DJ		 11178 outrel.r_info = ELF32_R_INFO (0, R_ARM_TLS_DTPMOD32);
11179
00a97672
RS		 11180 if (globals->use_rel)
11181 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11182 sgot->contents + off);
ba93b8ac 11183
47beaa6a 11184 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11185 }
11186 else
362d30a1 11187 bfd_put_32 (output_bfd, 1, sgot->contents + off);
ba93b8ac
DJ		 11188
11189 globals->tls_ldm_got.offset |= 1;
11190 }
11191
362d30a1 11192 value = sgot->output_section->vma + sgot->output_offset + off
ba93b8ac
DJ		 11193 - (input_section->output_section->vma + input_section->output_offset + rel->r_offset);
11194
11195 return _bfd_final_link_relocate (howto, input_bfd, input_section,
11196 contents, rel->r_offset, value,
00a97672 11197 rel->r_addend);
ba93b8ac
DJ		 11198 }
11199
0855e32b
NS		 11200 case R_ARM_TLS_CALL:
11201 case R_ARM_THM_TLS_CALL:
ba93b8ac
DJ		 11202 case R_ARM_TLS_GD32:
11203 case R_ARM_TLS_IE32:
0855e32b
NS		 11204 case R_ARM_TLS_GOTDESC:
11205 case R_ARM_TLS_DESCSEQ:
11206 case R_ARM_THM_TLS_DESCSEQ:
ba93b8ac 11207 {
0855e32b
NS		 11208 bfd_vma off, offplt;
11209 int indx = 0;
ba93b8ac
DJ		 11210 char tls_type;
11211
0855e32b 11212 BFD_ASSERT (sgot != NULL);
ba93b8ac 11213
ba93b8ac
DJ		 11214 if (h != NULL)
11215 {
11216 bfd_boolean dyn;
11217 dyn = globals->root.dynamic_sections_created;
0e1862bb
L		 11218 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
11219 bfd_link_pic (info),
11220 h)
11221 && (!bfd_link_pic (info)
ba93b8ac
DJ		 11222 || !SYMBOL_REFERENCES_LOCAL (info, h)))
11223 {
11224 *unresolved_reloc_p = FALSE;
11225 indx = h->dynindx;
11226 }
11227 off = h->got.offset;
0855e32b 11228 offplt = elf32_arm_hash_entry (h)->tlsdesc_got;
ba93b8ac
DJ		 11229 tls_type = ((struct elf32_arm_link_hash_entry *) h)->tls_type;
11230 }
11231 else
11232 {
0855e32b 11233 BFD_ASSERT (local_got_offsets != NULL);
ba93b8ac 11234 off = local_got_offsets[r_symndx];
0855e32b 11235 offplt = local_tlsdesc_gotents[r_symndx];
ba93b8ac
DJ		 11236 tls_type = elf32_arm_local_got_tls_type (input_bfd)[r_symndx];
11237 }
11238
0855e32b 11239 /* Linker relaxations happens from one of the
b38cadfb 11240 R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
0855e32b 11241 if (ELF32_R_TYPE(rel->r_info) != r_type)
b38cadfb 11242 tls_type = GOT_TLS_IE;
0855e32b
NS		 11243
11244 BFD_ASSERT (tls_type != GOT_UNKNOWN);
ba93b8ac
DJ		 11245
11246 if ((off & 1) != 0)
11247 off &= ~1;
11248 else
11249 {
11250 bfd_boolean need_relocs = FALSE;
11251 Elf_Internal_Rela outrel;
ba93b8ac
DJ		 11252 int cur_off = off;
11253
11254 /* The GOT entries have not been initialized yet. Do it
11255 now, and emit any relocations. If both an IE GOT and a
11256 GD GOT are necessary, we emit the GD first. */
11257
0e1862bb 11258 if ((bfd_link_pic (info) || indx != 0)
ba93b8ac
DJ		 11259 && (h == NULL
11260 || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
11261 || h->root.type != bfd_link_hash_undefweak))
11262 {
11263 need_relocs = TRUE;
0855e32b 11264 BFD_ASSERT (srelgot != NULL);
ba93b8ac
DJ		 11265 }
11266
0855e32b
NS		 11267 if (tls_type & GOT_TLS_GDESC)
11268 {
47beaa6a
RS		 11269 bfd_byte *loc;
11270
0855e32b
NS		 11271 /* We should have relaxed, unless this is an undefined
11272 weak symbol. */
11273 BFD_ASSERT ((h && (h->root.type == bfd_link_hash_undefweak))
0e1862bb 11274 || bfd_link_pic (info));
0855e32b 11275 BFD_ASSERT (globals->sgotplt_jump_table_size + offplt + 8
99059e56 11276 <= globals->root.sgotplt->size);
0855e32b
NS		 11277
11278 outrel.r_addend = 0;
11279 outrel.r_offset = (globals->root.sgotplt->output_section->vma
11280 + globals->root.sgotplt->output_offset
11281 + offplt
11282 + globals->sgotplt_jump_table_size);
b38cadfb 11283
0855e32b
NS		 11284 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DESC);
11285 sreloc = globals->root.srelplt;
11286 loc = sreloc->contents;
11287 loc += globals->next_tls_desc_index++ * RELOC_SIZE (globals);
11288 BFD_ASSERT (loc + RELOC_SIZE (globals)
99059e56 11289 <= sreloc->contents + sreloc->size);
0855e32b
NS		 11290
11291 SWAP_RELOC_OUT (globals) (output_bfd, &outrel, loc);
11292
11293 /* For globals, the first word in the relocation gets
11294 the relocation index and the top bit set, or zero,
11295 if we're binding now. For locals, it gets the
11296 symbol's offset in the tls section. */
99059e56 11297 bfd_put_32 (output_bfd,
0855e32b
NS		 11298 !h ? value - elf_hash_table (info)->tls_sec->vma
11299 : info->flags & DF_BIND_NOW ? 0
11300 : 0x80000000 | ELF32_R_SYM (outrel.r_info),
b38cadfb
NC		 11301 globals->root.sgotplt->contents + offplt
11302 + globals->sgotplt_jump_table_size);
11303
0855e32b 11304 /* Second word in the relocation is always zero. */
99059e56 11305 bfd_put_32 (output_bfd, 0,
b38cadfb
NC		 11306 globals->root.sgotplt->contents + offplt
11307 + globals->sgotplt_jump_table_size + 4);
0855e32b 11308 }
ba93b8ac
DJ		 11309 if (tls_type & GOT_TLS_GD)
11310 {
11311 if (need_relocs)
11312 {
00a97672 11313 outrel.r_addend = 0;
362d30a1
RS		 11314 outrel.r_offset = (sgot->output_section->vma
11315 + sgot->output_offset
00a97672 11316 + cur_off);
ba93b8ac 11317 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DTPMOD32);
ba93b8ac 11318
00a97672
RS		 11319 if (globals->use_rel)
11320 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11321 sgot->contents + cur_off);
00a97672 11322
47beaa6a 11323 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11324
11325 if (indx == 0)
11326 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11327 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11328 else
11329 {
00a97672 11330 outrel.r_addend = 0;
ba93b8ac
DJ		 11331 outrel.r_info = ELF32_R_INFO (indx,
11332 R_ARM_TLS_DTPOFF32);
11333 outrel.r_offset += 4;
00a97672
RS		 11334
11335 if (globals->use_rel)
11336 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11337 sgot->contents + cur_off + 4);
00a97672 11338
47beaa6a
RS		 11339 elf32_arm_add_dynreloc (output_bfd, info,
11340 srelgot, &outrel);
ba93b8ac
DJ		 11341 }
11342 }
11343 else
11344 {
11345 /* If we are not emitting relocations for a
11346 general dynamic reference, then we must be in a
11347 static link or an executable link with the
11348 symbol binding locally. Mark it as belonging
11349 to module 1, the executable. */
11350 bfd_put_32 (output_bfd, 1,
362d30a1 11351 sgot->contents + cur_off);
ba93b8ac 11352 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11353 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11354 }
11355
11356 cur_off += 8;
11357 }
11358
11359 if (tls_type & GOT_TLS_IE)
11360 {
11361 if (need_relocs)
11362 {
00a97672
RS		 11363 if (indx == 0)
11364 outrel.r_addend = value - dtpoff_base (info);
11365 else
11366 outrel.r_addend = 0;
362d30a1
RS		 11367 outrel.r_offset = (sgot->output_section->vma
11368 + sgot->output_offset
ba93b8ac
DJ		 11369 + cur_off);
11370 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_TPOFF32);
11371
00a97672
RS		 11372 if (globals->use_rel)
11373 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11374 sgot->contents + cur_off);
ba93b8ac 11375
47beaa6a 11376 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11377 }
11378 else
11379 bfd_put_32 (output_bfd, tpoff (info, value),
362d30a1 11380 sgot->contents + cur_off);
ba93b8ac
DJ		 11381 cur_off += 4;
11382 }
11383
11384 if (h != NULL)
11385 h->got.offset |= 1;
11386 else
11387 local_got_offsets[r_symndx] |= 1;
11388 }
11389
11390 if ((tls_type & GOT_TLS_GD) && r_type != R_ARM_TLS_GD32)
11391 off += 8;
0855e32b
NS		 11392 else if (tls_type & GOT_TLS_GDESC)
11393 off = offplt;
11394
11395 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL
11396 || ELF32_R_TYPE(rel->r_info) == R_ARM_THM_TLS_CALL)
11397 {
11398 bfd_signed_vma offset;
12352d3f
PB		 11399 /* TLS stubs are arm mode. The original symbol is a
11400 data object, so branch_type is bogus. */
11401 branch_type = ST_BRANCH_TO_ARM;
0855e32b 11402 enum elf32_arm_stub_type stub_type
34e77a92
RS		 11403 = arm_type_of_stub (info, input_section, rel,
11404 st_type, &branch_type,
0855e32b
NS		 11405 (struct elf32_arm_link_hash_entry *)h,
11406 globals->tls_trampoline, globals->root.splt,
11407 input_bfd, sym_name);
11408
11409 if (stub_type != arm_stub_none)
11410 {
11411 struct elf32_arm_stub_hash_entry *stub_entry
11412 = elf32_arm_get_stub_entry
11413 (input_section, globals->root.splt, 0, rel,
11414 globals, stub_type);
11415 offset = (stub_entry->stub_offset
11416 + stub_entry->stub_sec->output_offset
11417 + stub_entry->stub_sec->output_section->vma);
11418 }
11419 else
11420 offset = (globals->root.splt->output_section->vma
11421 + globals->root.splt->output_offset
11422 + globals->tls_trampoline);
11423
11424 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL)
11425 {
11426 unsigned long inst;
b38cadfb
NC		 11427
11428 offset -= (input_section->output_section->vma
11429 + input_section->output_offset
11430 + rel->r_offset + 8);
0855e32b
NS		 11431
11432 inst = offset >> 2;
11433 inst &= 0x00ffffff;
11434 value = inst | (globals->use_blx ? 0xfa000000 : 0xeb000000);
11435 }
11436 else
11437 {
11438 /* Thumb blx encodes the offset in a complicated
11439 fashion. */
11440 unsigned upper_insn, lower_insn;
11441 unsigned neg;
11442
b38cadfb
NC		 11443 offset -= (input_section->output_section->vma
11444 + input_section->output_offset
0855e32b 11445 + rel->r_offset + 4);
b38cadfb 11446
12352d3f
PB		 11447 if (stub_type != arm_stub_none
11448 && arm_stub_is_thumb (stub_type))
11449 {
11450 lower_insn = 0xd000;
11451 }
11452 else
11453 {
11454 lower_insn = 0xc000;
6a631e86 11455 /* Round up the offset to a word boundary. */
12352d3f
PB		 11456 offset = (offset + 2) & ~2;
11457 }
11458
0855e32b
NS		 11459 neg = offset < 0;
11460 upper_insn = (0xf000
11461 | ((offset >> 12) & 0x3ff)
11462 | (neg << 10));
12352d3f 11463 lower_insn |= (((!((offset >> 23) & 1)) ^ neg) << 13)
0855e32b 11464 | (((!((offset >> 22) & 1)) ^ neg) << 11)
12352d3f 11465 | ((offset >> 1) & 0x7ff);
0855e32b
NS		 11466 bfd_put_16 (input_bfd, upper_insn, hit_data);
11467 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11468 return bfd_reloc_ok;
11469 }
11470 }
11471 /* These relocations needs special care, as besides the fact
11472 they point somewhere in .gotplt, the addend must be
11473 adjusted accordingly depending on the type of instruction
6a631e86 11474 we refer to. */
0855e32b
NS		 11475 else if ((r_type == R_ARM_TLS_GOTDESC) && (tls_type & GOT_TLS_GDESC))
11476 {
11477 unsigned long data, insn;
11478 unsigned thumb;
b38cadfb 11479
0855e32b
NS		 11480 data = bfd_get_32 (input_bfd, hit_data);
11481 thumb = data & 1;
11482 data &= ~1u;
b38cadfb 11483
0855e32b
NS		 11484 if (thumb)
11485 {
11486 insn = bfd_get_16 (input_bfd, contents + rel->r_offset - data);
11487 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
11488 insn = (insn << 16)
11489 | bfd_get_16 (input_bfd,
11490 contents + rel->r_offset - data + 2);
11491 if ((insn & 0xf800c000) == 0xf000c000)
11492 /* bl/blx */
11493 value = -6;
11494 else if ((insn & 0xffffff00) == 0x4400)
11495 /* add */
11496 value = -5;
11497 else
11498 {
11499 (*_bfd_error_handler)
11500 (_("%B(%A+0x%lx):unexpected Thumb instruction '0x%x' referenced by TLS_GOTDESC"),
11501 input_bfd, input_section,
11502 (unsigned long)rel->r_offset, insn);
11503 return bfd_reloc_notsupported;
11504 }
11505 }
11506 else
11507 {
11508 insn = bfd_get_32 (input_bfd, contents + rel->r_offset - data);
11509
11510 switch (insn >> 24)
11511 {
11512 case 0xeb: /* bl */
11513 case 0xfa: /* blx */
11514 value = -4;
11515 break;
11516
11517 case 0xe0: /* add */
11518 value = -8;
11519 break;
b38cadfb 11520
0855e32b
NS		 11521 default:
11522 (*_bfd_error_handler)
11523 (_("%B(%A+0x%lx):unexpected ARM instruction '0x%x' referenced by TLS_GOTDESC"),
11524 input_bfd, input_section,
11525 (unsigned long)rel->r_offset, insn);
11526 return bfd_reloc_notsupported;
11527 }
11528 }
b38cadfb 11529
0855e32b
NS		 11530 value += ((globals->root.sgotplt->output_section->vma
11531 + globals->root.sgotplt->output_offset + off)
11532 - (input_section->output_section->vma
11533 + input_section->output_offset
11534 + rel->r_offset)
11535 + globals->sgotplt_jump_table_size);
11536 }
11537 else
11538 value = ((globals->root.sgot->output_section->vma
11539 + globals->root.sgot->output_offset + off)
11540 - (input_section->output_section->vma
11541 + input_section->output_offset + rel->r_offset));
ba93b8ac
DJ		 11542
11543 return _bfd_final_link_relocate (howto, input_bfd, input_section,
11544 contents, rel->r_offset, value,
00a97672 11545 rel->r_addend);
ba93b8ac
DJ		 11546 }
11547
11548 case R_ARM_TLS_LE32:
3cbc1e5e 11549 if (bfd_link_dll (info))
ba93b8ac
DJ		 11550 {
11551 (*_bfd_error_handler)
11552 (_("%B(%A+0x%lx): R_ARM_TLS_LE32 relocation not permitted in shared object"),
11553 input_bfd, input_section,
11554 (long) rel->r_offset, howto->name);
46691134 11555 return bfd_reloc_notsupported;
ba93b8ac
DJ		 11556 }
11557 else
11558 value = tpoff (info, value);
906e58ca 11559
ba93b8ac 11560 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 11561 contents, rel->r_offset, value,
11562 rel->r_addend);
ba93b8ac 11563
319850b4
JB		 11564 case R_ARM_V4BX:
11565 if (globals->fix_v4bx)
845b51d6
PB		 11566 {
11567 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
319850b4 11568
845b51d6
PB		 11569 /* Ensure that we have a BX instruction. */
11570 BFD_ASSERT ((insn & 0x0ffffff0) == 0x012fff10);
319850b4 11571
845b51d6
PB		 11572 if (globals->fix_v4bx == 2 && (insn & 0xf) != 0xf)
11573 {
11574 /* Branch to veneer. */
11575 bfd_vma glue_addr;
11576 glue_addr = elf32_arm_bx_glue (info, insn & 0xf);
11577 glue_addr -= input_section->output_section->vma
11578 + input_section->output_offset
11579 + rel->r_offset + 8;
11580 insn = (insn & 0xf0000000) | 0x0a000000
11581 | ((glue_addr >> 2) & 0x00ffffff);
11582 }
11583 else
11584 {
11585 /* Preserve Rm (lowest four bits) and the condition code
11586 (highest four bits). Other bits encode MOV PC,Rm. */
11587 insn = (insn & 0xf000000f) | 0x01a0f000;
11588 }
319850b4 11589
845b51d6
PB		 11590 bfd_put_32 (input_bfd, insn, hit_data);
11591 }
319850b4
JB		 11592 return bfd_reloc_ok;
11593
b6895b4f
PB		 11594 case R_ARM_MOVW_ABS_NC:
11595 case R_ARM_MOVT_ABS:
11596 case R_ARM_MOVW_PREL_NC:
11597 case R_ARM_MOVT_PREL:
92f5d02b
MS		 11598 /* Until we properly support segment-base-relative addressing then
11599 we assume the segment base to be zero, as for the group relocations.
11600 Thus R_ARM_MOVW_BREL_NC has the same semantics as R_ARM_MOVW_ABS_NC
11601 and R_ARM_MOVT_BREL has the same semantics as R_ARM_MOVT_ABS. */
11602 case R_ARM_MOVW_BREL_NC:
11603 case R_ARM_MOVW_BREL:
11604 case R_ARM_MOVT_BREL:
b6895b4f
PB		 11605 {
11606 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
11607
11608 if (globals->use_rel)
11609 {
11610 addend = ((insn >> 4) & 0xf000) | (insn & 0xfff);
39623e12 11611 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 11612 }
92f5d02b 11613
b6895b4f 11614 value += signed_addend;
b6895b4f
PB		 11615
11616 if (r_type == R_ARM_MOVW_PREL_NC || r_type == R_ARM_MOVT_PREL)
11617 value -= (input_section->output_section->vma
11618 + input_section->output_offset + rel->r_offset);
11619
92f5d02b 11620 if (r_type == R_ARM_MOVW_BREL && value >= 0x10000)
99059e56 11621 return bfd_reloc_overflow;
92f5d02b 11622
35fc36a8 11623 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 11624 value |= 1;
11625
11626 if (r_type == R_ARM_MOVT_ABS || r_type == R_ARM_MOVT_PREL
99059e56 11627 || r_type == R_ARM_MOVT_BREL)
b6895b4f
PB		 11628 value >>= 16;
11629
11630 insn &= 0xfff0f000;
11631 insn |= value & 0xfff;
11632 insn |= (value & 0xf000) << 4;
11633 bfd_put_32 (input_bfd, insn, hit_data);
11634 }
11635 return bfd_reloc_ok;
11636
11637 case R_ARM_THM_MOVW_ABS_NC:
11638 case R_ARM_THM_MOVT_ABS:
11639 case R_ARM_THM_MOVW_PREL_NC:
11640 case R_ARM_THM_MOVT_PREL:
92f5d02b
MS		 11641 /* Until we properly support segment-base-relative addressing then
11642 we assume the segment base to be zero, as for the above relocations.
11643 Thus R_ARM_THM_MOVW_BREL_NC has the same semantics as
11644 R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_BREL has the same semantics
11645 as R_ARM_THM_MOVT_ABS. */
11646 case R_ARM_THM_MOVW_BREL_NC:
11647 case R_ARM_THM_MOVW_BREL:
11648 case R_ARM_THM_MOVT_BREL:
b6895b4f
PB		 11649 {
11650 bfd_vma insn;
906e58ca 11651
b6895b4f
PB		 11652 insn = bfd_get_16 (input_bfd, hit_data) << 16;
11653 insn |= bfd_get_16 (input_bfd, hit_data + 2);
11654
11655 if (globals->use_rel)
11656 {
11657 addend = ((insn >> 4) & 0xf000)
11658 | ((insn >> 15) & 0x0800)
11659 | ((insn >> 4) & 0x0700)
11660 | (insn & 0x00ff);
39623e12 11661 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 11662 }
92f5d02b 11663
b6895b4f 11664 value += signed_addend;
b6895b4f
PB		 11665
11666 if (r_type == R_ARM_THM_MOVW_PREL_NC || r_type == R_ARM_THM_MOVT_PREL)
11667 value -= (input_section->output_section->vma
11668 + input_section->output_offset + rel->r_offset);
11669
92f5d02b 11670 if (r_type == R_ARM_THM_MOVW_BREL && value >= 0x10000)
99059e56 11671 return bfd_reloc_overflow;
92f5d02b 11672
35fc36a8 11673 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 11674 value |= 1;
11675
11676 if (r_type == R_ARM_THM_MOVT_ABS || r_type == R_ARM_THM_MOVT_PREL
99059e56 11677 || r_type == R_ARM_THM_MOVT_BREL)
b6895b4f
PB		 11678 value >>= 16;
11679
11680 insn &= 0xfbf08f00;
11681 insn |= (value & 0xf000) << 4;
11682 insn |= (value & 0x0800) << 15;
11683 insn |= (value & 0x0700) << 4;
11684 insn |= (value & 0x00ff);
11685
11686 bfd_put_16 (input_bfd, insn >> 16, hit_data);
11687 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
11688 }
11689 return bfd_reloc_ok;
11690
4962c51a
MS		 11691 case R_ARM_ALU_PC_G0_NC:
11692 case R_ARM_ALU_PC_G1_NC:
11693 case R_ARM_ALU_PC_G0:
11694 case R_ARM_ALU_PC_G1:
11695 case R_ARM_ALU_PC_G2:
11696 case R_ARM_ALU_SB_G0_NC:
11697 case R_ARM_ALU_SB_G1_NC:
11698 case R_ARM_ALU_SB_G0:
11699 case R_ARM_ALU_SB_G1:
11700 case R_ARM_ALU_SB_G2:
11701 {
11702 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 11703 bfd_vma pc = input_section->output_section->vma
4962c51a 11704 + input_section->output_offset + rel->r_offset;
31a91d61 11705 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 11706 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56
RM		 11707 bfd_vma residual;
11708 bfd_vma g_n;
4962c51a 11709 bfd_signed_vma signed_value;
99059e56
RM		 11710 int group = 0;
11711
11712 /* Determine which group of bits to select. */
11713 switch (r_type)
11714 {
11715 case R_ARM_ALU_PC_G0_NC:
11716 case R_ARM_ALU_PC_G0:
11717 case R_ARM_ALU_SB_G0_NC:
11718 case R_ARM_ALU_SB_G0:
11719 group = 0;
11720 break;
11721
11722 case R_ARM_ALU_PC_G1_NC:
11723 case R_ARM_ALU_PC_G1:
11724 case R_ARM_ALU_SB_G1_NC:
11725 case R_ARM_ALU_SB_G1:
11726 group = 1;
11727 break;
11728
11729 case R_ARM_ALU_PC_G2:
11730 case R_ARM_ALU_SB_G2:
11731 group = 2;
11732 break;
11733
11734 default:
11735 abort ();
11736 }
11737
11738 /* If REL, extract the addend from the insn. If RELA, it will
11739 have already been fetched for us. */
4962c51a 11740 if (globals->use_rel)
99059e56
RM		 11741 {
11742 int negative;
11743 bfd_vma constant = insn & 0xff;
11744 bfd_vma rotation = (insn & 0xf00) >> 8;
11745
11746 if (rotation == 0)
11747 signed_addend = constant;
11748 else
11749 {
11750 /* Compensate for the fact that in the instruction, the
11751 rotation is stored in multiples of 2 bits. */
11752 rotation *= 2;
11753
11754 /* Rotate "constant" right by "rotation" bits. */
11755 signed_addend = (constant >> rotation) |
11756 (constant << (8 * sizeof (bfd_vma) - rotation));
11757 }
11758
11759 /* Determine if the instruction is an ADD or a SUB.
11760 (For REL, this determines the sign of the addend.) */
11761 negative = identify_add_or_sub (insn);
11762 if (negative == 0)
11763 {
11764 (*_bfd_error_handler)
11765 (_("%B(%A+0x%lx): Only ADD or SUB instructions are allowed for ALU group relocations"),
11766 input_bfd, input_section,
11767 (long) rel->r_offset, howto->name);
11768 return bfd_reloc_overflow;
11769 }
11770
11771 signed_addend *= negative;
11772 }
4962c51a
MS		 11773
11774 /* Compute the value (X) to go in the place. */
99059e56
RM		 11775 if (r_type == R_ARM_ALU_PC_G0_NC
11776 || r_type == R_ARM_ALU_PC_G1_NC
11777 || r_type == R_ARM_ALU_PC_G0
11778 || r_type == R_ARM_ALU_PC_G1
11779 || r_type == R_ARM_ALU_PC_G2)
11780 /* PC relative. */
11781 signed_value = value - pc + signed_addend;
11782 else
11783 /* Section base relative. */
11784 signed_value = value - sb + signed_addend;
11785
11786 /* If the target symbol is a Thumb function, then set the
11787 Thumb bit in the address. */
35fc36a8 11788 if (branch_type == ST_BRANCH_TO_THUMB)
4962c51a
MS		 11789 signed_value |= 1;
11790
99059e56
RM		 11791 /* Calculate the value of the relevant G_n, in encoded
11792 constant-with-rotation format. */
b6518b38
NC		 11793 g_n = calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
11794 group, &residual);
99059e56
RM		 11795
11796 /* Check for overflow if required. */
11797 if ((r_type == R_ARM_ALU_PC_G0
11798 || r_type == R_ARM_ALU_PC_G1
11799 || r_type == R_ARM_ALU_PC_G2
11800 || r_type == R_ARM_ALU_SB_G0
11801 || r_type == R_ARM_ALU_SB_G1
11802 || r_type == R_ARM_ALU_SB_G2) && residual != 0)
11803 {
11804 (*_bfd_error_handler)
11805 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
11806 input_bfd, input_section,
b6518b38
NC		 11807 (long) rel->r_offset, signed_value < 0 ? - signed_value : signed_value,
11808 howto->name);
99059e56
RM		 11809 return bfd_reloc_overflow;
11810 }
11811
11812 /* Mask out the value and the ADD/SUB part of the opcode; take care
11813 not to destroy the S bit. */
11814 insn &= 0xff1ff000;
11815
11816 /* Set the opcode according to whether the value to go in the
11817 place is negative. */
11818 if (signed_value < 0)
11819 insn |= 1 << 22;
11820 else
11821 insn |= 1 << 23;
11822
11823 /* Encode the offset. */
11824 insn |= g_n;
4962c51a
MS		 11825
11826 bfd_put_32 (input_bfd, insn, hit_data);
11827 }
11828 return bfd_reloc_ok;
11829
11830 case R_ARM_LDR_PC_G0:
11831 case R_ARM_LDR_PC_G1:
11832 case R_ARM_LDR_PC_G2:
11833 case R_ARM_LDR_SB_G0:
11834 case R_ARM_LDR_SB_G1:
11835 case R_ARM_LDR_SB_G2:
11836 {
11837 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 11838 bfd_vma pc = input_section->output_section->vma
4962c51a 11839 + input_section->output_offset + rel->r_offset;
31a91d61 11840 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 11841 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 11842 bfd_vma residual;
4962c51a 11843 bfd_signed_vma signed_value;
99059e56
RM		 11844 int group = 0;
11845
11846 /* Determine which groups of bits to calculate. */
11847 switch (r_type)
11848 {
11849 case R_ARM_LDR_PC_G0:
11850 case R_ARM_LDR_SB_G0:
11851 group = 0;
11852 break;
11853
11854 case R_ARM_LDR_PC_G1:
11855 case R_ARM_LDR_SB_G1:
11856 group = 1;
11857 break;
11858
11859 case R_ARM_LDR_PC_G2:
11860 case R_ARM_LDR_SB_G2:
11861 group = 2;
11862 break;
11863
11864 default:
11865 abort ();
11866 }
11867
11868 /* If REL, extract the addend from the insn. If RELA, it will
11869 have already been fetched for us. */
4962c51a 11870 if (globals->use_rel)
99059e56
RM		 11871 {
11872 int negative = (insn & (1 << 23)) ? 1 : -1;
11873 signed_addend = negative * (insn & 0xfff);
11874 }
4962c51a
MS		 11875
11876 /* Compute the value (X) to go in the place. */
99059e56
RM		 11877 if (r_type == R_ARM_LDR_PC_G0
11878 || r_type == R_ARM_LDR_PC_G1
11879 || r_type == R_ARM_LDR_PC_G2)
11880 /* PC relative. */
11881 signed_value = value - pc + signed_addend;
11882 else
11883 /* Section base relative. */
11884 signed_value = value - sb + signed_addend;
11885
11886 /* Calculate the value of the relevant G_{n-1} to obtain
11887 the residual at that stage. */
b6518b38
NC		 11888 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
11889 group - 1, &residual);
99059e56
RM		 11890
11891 /* Check for overflow. */
11892 if (residual >= 0x1000)
11893 {
11894 (*_bfd_error_handler)
11895 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
b6518b38
NC		 11896 input_bfd, input_section,
11897 (long) rel->r_offset, labs (signed_value), howto->name);
99059e56
RM		 11898 return bfd_reloc_overflow;
11899 }
11900
11901 /* Mask out the value and U bit. */
11902 insn &= 0xff7ff000;
11903
11904 /* Set the U bit if the value to go in the place is non-negative. */
11905 if (signed_value >= 0)
11906 insn |= 1 << 23;
11907
11908 /* Encode the offset. */
11909 insn |= residual;
4962c51a
MS		 11910
11911 bfd_put_32 (input_bfd, insn, hit_data);
11912 }
11913 return bfd_reloc_ok;
11914
11915 case R_ARM_LDRS_PC_G0:
11916 case R_ARM_LDRS_PC_G1:
11917 case R_ARM_LDRS_PC_G2:
11918 case R_ARM_LDRS_SB_G0:
11919 case R_ARM_LDRS_SB_G1:
11920 case R_ARM_LDRS_SB_G2:
11921 {
11922 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 11923 bfd_vma pc = input_section->output_section->vma
4962c51a 11924 + input_section->output_offset + rel->r_offset;
31a91d61 11925 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 11926 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 11927 bfd_vma residual;
4962c51a 11928 bfd_signed_vma signed_value;
99059e56
RM		 11929 int group = 0;
11930
11931 /* Determine which groups of bits to calculate. */
11932 switch (r_type)
11933 {
11934 case R_ARM_LDRS_PC_G0:
11935 case R_ARM_LDRS_SB_G0:
11936 group = 0;
11937 break;
11938
11939 case R_ARM_LDRS_PC_G1:
11940 case R_ARM_LDRS_SB_G1:
11941 group = 1;
11942 break;
11943
11944 case R_ARM_LDRS_PC_G2:
11945 case R_ARM_LDRS_SB_G2:
11946 group = 2;
11947 break;
11948
11949 default:
11950 abort ();
11951 }
11952
11953 /* If REL, extract the addend from the insn. If RELA, it will
11954 have already been fetched for us. */
4962c51a 11955 if (globals->use_rel)
99059e56
RM		 11956 {
11957 int negative = (insn & (1 << 23)) ? 1 : -1;
11958 signed_addend = negative * (((insn & 0xf00) >> 4) + (insn & 0xf));
11959 }
4962c51a
MS		 11960
11961 /* Compute the value (X) to go in the place. */
99059e56
RM		 11962 if (r_type == R_ARM_LDRS_PC_G0
11963 || r_type == R_ARM_LDRS_PC_G1
11964 || r_type == R_ARM_LDRS_PC_G2)
11965 /* PC relative. */
11966 signed_value = value - pc + signed_addend;
11967 else
11968 /* Section base relative. */
11969 signed_value = value - sb + signed_addend;
11970
11971 /* Calculate the value of the relevant G_{n-1} to obtain
11972 the residual at that stage. */
b6518b38
NC		 11973 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
11974 group - 1, &residual);
99059e56
RM		 11975
11976 /* Check for overflow. */
11977 if (residual >= 0x100)
11978 {
11979 (*_bfd_error_handler)
11980 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
b6518b38
NC		 11981 input_bfd, input_section,
11982 (long) rel->r_offset, labs (signed_value), howto->name);
99059e56
RM		 11983 return bfd_reloc_overflow;
11984 }
11985
11986 /* Mask out the value and U bit. */
11987 insn &= 0xff7ff0f0;
11988
11989 /* Set the U bit if the value to go in the place is non-negative. */
11990 if (signed_value >= 0)
11991 insn |= 1 << 23;
11992
11993 /* Encode the offset. */
11994 insn |= ((residual & 0xf0) << 4) | (residual & 0xf);
4962c51a
MS		 11995
11996 bfd_put_32 (input_bfd, insn, hit_data);
11997 }
11998 return bfd_reloc_ok;
11999
12000 case R_ARM_LDC_PC_G0:
12001 case R_ARM_LDC_PC_G1:
12002 case R_ARM_LDC_PC_G2:
12003 case R_ARM_LDC_SB_G0:
12004 case R_ARM_LDC_SB_G1:
12005 case R_ARM_LDC_SB_G2:
12006 {
12007 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12008 bfd_vma pc = input_section->output_section->vma
4962c51a 12009 + input_section->output_offset + rel->r_offset;
31a91d61 12010 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12011 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12012 bfd_vma residual;
4962c51a 12013 bfd_signed_vma signed_value;
99059e56
RM		 12014 int group = 0;
12015
12016 /* Determine which groups of bits to calculate. */
12017 switch (r_type)
12018 {
12019 case R_ARM_LDC_PC_G0:
12020 case R_ARM_LDC_SB_G0:
12021 group = 0;
12022 break;
12023
12024 case R_ARM_LDC_PC_G1:
12025 case R_ARM_LDC_SB_G1:
12026 group = 1;
12027 break;
12028
12029 case R_ARM_LDC_PC_G2:
12030 case R_ARM_LDC_SB_G2:
12031 group = 2;
12032 break;
12033
12034 default:
12035 abort ();
12036 }
12037
12038 /* If REL, extract the addend from the insn. If RELA, it will
12039 have already been fetched for us. */
4962c51a 12040 if (globals->use_rel)
99059e56
RM		 12041 {
12042 int negative = (insn & (1 << 23)) ? 1 : -1;
12043 signed_addend = negative * ((insn & 0xff) << 2);
12044 }
4962c51a
MS		 12045
12046 /* Compute the value (X) to go in the place. */
99059e56
RM		 12047 if (r_type == R_ARM_LDC_PC_G0
12048 || r_type == R_ARM_LDC_PC_G1
12049 || r_type == R_ARM_LDC_PC_G2)
12050 /* PC relative. */
12051 signed_value = value - pc + signed_addend;
12052 else
12053 /* Section base relative. */
12054 signed_value = value - sb + signed_addend;
12055
12056 /* Calculate the value of the relevant G_{n-1} to obtain
12057 the residual at that stage. */
b6518b38
NC		 12058 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12059 group - 1, &residual);
99059e56
RM		 12060
12061 /* Check for overflow. (The absolute value to go in the place must be
12062 divisible by four and, after having been divided by four, must
12063 fit in eight bits.) */
12064 if ((residual & 0x3) != 0 || residual >= 0x400)
12065 {
12066 (*_bfd_error_handler)
12067 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
12068 input_bfd, input_section,
b6518b38 12069 (long) rel->r_offset, labs (signed_value), howto->name);
99059e56
RM		 12070 return bfd_reloc_overflow;
12071 }
12072
12073 /* Mask out the value and U bit. */
12074 insn &= 0xff7fff00;
12075
12076 /* Set the U bit if the value to go in the place is non-negative. */
12077 if (signed_value >= 0)
12078 insn |= 1 << 23;
12079
12080 /* Encode the offset. */
12081 insn |= residual >> 2;
4962c51a
MS		 12082
12083 bfd_put_32 (input_bfd, insn, hit_data);
12084 }
12085 return bfd_reloc_ok;
12086
72d98d16
MG		 12087 case R_ARM_THM_ALU_ABS_G0_NC:
12088 case R_ARM_THM_ALU_ABS_G1_NC:
12089 case R_ARM_THM_ALU_ABS_G2_NC:
12090 case R_ARM_THM_ALU_ABS_G3_NC:
12091 {
12092 const int shift_array[4] = {0, 8, 16, 24};
12093 bfd_vma insn = bfd_get_16 (input_bfd, hit_data);
12094 bfd_vma addr = value;
12095 int shift = shift_array[r_type - R_ARM_THM_ALU_ABS_G0_NC];
12096
12097 /* Compute address. */
12098 if (globals->use_rel)
12099 signed_addend = insn & 0xff;
12100 addr += signed_addend;
12101 if (branch_type == ST_BRANCH_TO_THUMB)
12102 addr |= 1;
12103 /* Clean imm8 insn. */
12104 insn &= 0xff00;
12105 /* And update with correct part of address. */
12106 insn |= (addr >> shift) & 0xff;
12107 /* Update insn. */
12108 bfd_put_16 (input_bfd, insn, hit_data);
12109 }
12110
12111 *unresolved_reloc_p = FALSE;
12112 return bfd_reloc_ok;
12113
252b5132
RH		 12114 default:
12115 return bfd_reloc_notsupported;
12116 }
12117}
12118
98c1d4aa
NC		 12119/* Add INCREMENT to the reloc (of type HOWTO) at ADDRESS. */
12120static void
57e8b36a
NC		 12121arm_add_to_rel (bfd * abfd,
12122 bfd_byte * address,
12123 reloc_howto_type * howto,
12124 bfd_signed_vma increment)
98c1d4aa 12125{
98c1d4aa
NC		 12126 bfd_signed_vma addend;
12127
bd97cb95
DJ		 12128 if (howto->type == R_ARM_THM_CALL
12129 || howto->type == R_ARM_THM_JUMP24)
98c1d4aa 12130 {
9a5aca8c
AM		 12131 int upper_insn, lower_insn;
12132 int upper, lower;
98c1d4aa 12133
9a5aca8c
AM		 12134 upper_insn = bfd_get_16 (abfd, address);
12135 lower_insn = bfd_get_16 (abfd, address + 2);
12136 upper = upper_insn & 0x7ff;
12137 lower = lower_insn & 0x7ff;
12138
12139 addend = (upper << 12) | (lower << 1);
ddda4409 12140 addend += increment;
9a5aca8c 12141 addend >>= 1;
98c1d4aa 12142
9a5aca8c
AM		 12143 upper_insn = (upper_insn & 0xf800) | ((addend >> 11) & 0x7ff);
12144 lower_insn = (lower_insn & 0xf800) | (addend & 0x7ff);
12145
dc810e39
AM		 12146 bfd_put_16 (abfd, (bfd_vma) upper_insn, address);
12147 bfd_put_16 (abfd, (bfd_vma) lower_insn, address + 2);
9a5aca8c
AM		 12148 }
12149 else
12150 {
12151 bfd_vma contents;
12152
12153 contents = bfd_get_32 (abfd, address);
12154
12155 /* Get the (signed) value from the instruction. */
12156 addend = contents & howto->src_mask;
12157 if (addend & ((howto->src_mask + 1) >> 1))
12158 {
12159 bfd_signed_vma mask;
12160
12161 mask = -1;
12162 mask &= ~ howto->src_mask;
12163 addend |= mask;
12164 }
12165
12166 /* Add in the increment, (which is a byte value). */
12167 switch (howto->type)
12168 {
12169 default:
12170 addend += increment;
12171 break;
12172
12173 case R_ARM_PC24:
c6596c5e 12174 case R_ARM_PLT32:
5b5bb741
PB		 12175 case R_ARM_CALL:
12176 case R_ARM_JUMP24:
9a5aca8c 12177 addend <<= howto->size;
dc810e39 12178 addend += increment;
9a5aca8c
AM		 12179
12180 /* Should we check for overflow here ? */
12181
12182 /* Drop any undesired bits. */
12183 addend >>= howto->rightshift;
12184 break;
12185 }
12186
12187 contents = (contents & ~ howto->dst_mask) | (addend & howto->dst_mask);
12188
12189 bfd_put_32 (abfd, contents, address);
ddda4409 12190 }
98c1d4aa 12191}
252b5132 12192
ba93b8ac
DJ		 12193#define IS_ARM_TLS_RELOC(R_TYPE) \
12194 ((R_TYPE) == R_ARM_TLS_GD32 \
12195 || (R_TYPE) == R_ARM_TLS_LDO32 \
12196 || (R_TYPE) == R_ARM_TLS_LDM32 \
12197 || (R_TYPE) == R_ARM_TLS_DTPOFF32 \
12198 || (R_TYPE) == R_ARM_TLS_DTPMOD32 \
12199 || (R_TYPE) == R_ARM_TLS_TPOFF32 \
12200 || (R_TYPE) == R_ARM_TLS_LE32 \
0855e32b
NS		 12201 || (R_TYPE) == R_ARM_TLS_IE32 \
12202 || IS_ARM_TLS_GNU_RELOC (R_TYPE))
12203
12204/* Specific set of relocations for the gnu tls dialect. */
12205#define IS_ARM_TLS_GNU_RELOC(R_TYPE) \
12206 ((R_TYPE) == R_ARM_TLS_GOTDESC \
12207 || (R_TYPE) == R_ARM_TLS_CALL \
12208 || (R_TYPE) == R_ARM_THM_TLS_CALL \
12209 || (R_TYPE) == R_ARM_TLS_DESCSEQ \
12210 || (R_TYPE) == R_ARM_THM_TLS_DESCSEQ)
ba93b8ac 12211
252b5132 12212/* Relocate an ARM ELF section. */
906e58ca 12213
b34976b6 12214static bfd_boolean
57e8b36a
NC		 12215elf32_arm_relocate_section (bfd * output_bfd,
12216 struct bfd_link_info * info,
12217 bfd * input_bfd,
12218 asection * input_section,
12219 bfd_byte * contents,
12220 Elf_Internal_Rela * relocs,
12221 Elf_Internal_Sym * local_syms,
12222 asection ** local_sections)
252b5132 12223{
b34976b6
AM		 12224 Elf_Internal_Shdr *symtab_hdr;
12225 struct elf_link_hash_entry **sym_hashes;
12226 Elf_Internal_Rela *rel;
12227 Elf_Internal_Rela *relend;
12228 const char *name;
b32d3aa2 12229 struct elf32_arm_link_hash_table * globals;
252b5132 12230
4e7fd91e 12231 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 12232 if (globals == NULL)
12233 return FALSE;
b491616a 12234
0ffa91dd 12235 symtab_hdr = & elf_symtab_hdr (input_bfd);
252b5132
RH		 12236 sym_hashes = elf_sym_hashes (input_bfd);
12237
12238 rel = relocs;
12239 relend = relocs + input_section->reloc_count;
12240 for (; rel < relend; rel++)
12241 {
ba96a88f
NC		 12242 int r_type;
12243 reloc_howto_type * howto;
12244 unsigned long r_symndx;
12245 Elf_Internal_Sym * sym;
12246 asection * sec;
252b5132 12247 struct elf_link_hash_entry * h;
ba96a88f
NC		 12248 bfd_vma relocation;
12249 bfd_reloc_status_type r;
12250 arelent bfd_reloc;
ba93b8ac 12251 char sym_type;
0945cdfd 12252 bfd_boolean unresolved_reloc = FALSE;
f2a9dd69 12253 char *error_message = NULL;
f21f3fe0 12254
252b5132 12255 r_symndx = ELF32_R_SYM (rel->r_info);
ba96a88f 12256 r_type = ELF32_R_TYPE (rel->r_info);
b32d3aa2 12257 r_type = arm_real_reloc_type (globals, r_type);
252b5132 12258
ba96a88f 12259 if ( r_type == R_ARM_GNU_VTENTRY
99059e56
RM		 12260 || r_type == R_ARM_GNU_VTINHERIT)
12261 continue;
252b5132 12262
b32d3aa2 12263 bfd_reloc.howto = elf32_arm_howto_from_type (r_type);
ba96a88f 12264 howto = bfd_reloc.howto;
252b5132 12265
252b5132
RH		 12266 h = NULL;
12267 sym = NULL;
12268 sec = NULL;
9b485d32 12269
252b5132
RH		 12270 if (r_symndx < symtab_hdr->sh_info)
12271 {
12272 sym = local_syms + r_symndx;
ba93b8ac 12273 sym_type = ELF32_ST_TYPE (sym->st_info);
252b5132 12274 sec = local_sections[r_symndx];
ffcb4889
NS		 12275
12276 /* An object file might have a reference to a local
12277 undefined symbol. This is a daft object file, but we
12278 should at least do something about it. V4BX & NONE
12279 relocations do not use the symbol and are explicitly
77b4f08f
TS		 12280 allowed to use the undefined symbol, so allow those.
12281 Likewise for relocations against STN_UNDEF. */
ffcb4889
NS		 12282 if (r_type != R_ARM_V4BX
12283 && r_type != R_ARM_NONE
77b4f08f 12284 && r_symndx != STN_UNDEF
ffcb4889
NS		 12285 && bfd_is_und_section (sec)
12286 && ELF_ST_BIND (sym->st_info) != STB_WEAK)
1a72702b
AM		 12287 (*info->callbacks->undefined_symbol)
12288 (info, bfd_elf_string_from_elf_section
12289 (input_bfd, symtab_hdr->sh_link, sym->st_name),
12290 input_bfd, input_section,
12291 rel->r_offset, TRUE);
b38cadfb 12292
4e7fd91e 12293 if (globals->use_rel)
f8df10f4 12294 {
4e7fd91e
PB		 12295 relocation = (sec->output_section->vma
12296 + sec->output_offset
12297 + sym->st_value);
0e1862bb 12298 if (!bfd_link_relocatable (info)
ab96bf03
AM		 12299 && (sec->flags & SEC_MERGE)
12300 && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
f8df10f4 12301 {
4e7fd91e
PB		 12302 asection *msec;
12303 bfd_vma addend, value;
12304
39623e12 12305 switch (r_type)
4e7fd91e 12306 {
39623e12
PB		 12307 case R_ARM_MOVW_ABS_NC:
12308 case R_ARM_MOVT_ABS:
12309 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
12310 addend = ((value & 0xf0000) >> 4) | (value & 0xfff);
12311 addend = (addend ^ 0x8000) - 0x8000;
12312 break;
f8df10f4 12313
39623e12
PB		 12314 case R_ARM_THM_MOVW_ABS_NC:
12315 case R_ARM_THM_MOVT_ABS:
12316 value = bfd_get_16 (input_bfd, contents + rel->r_offset)
12317 << 16;
12318 value |= bfd_get_16 (input_bfd,
12319 contents + rel->r_offset + 2);
12320 addend = ((value & 0xf7000) >> 4) | (value & 0xff)
12321 | ((value & 0x04000000) >> 15);
12322 addend = (addend ^ 0x8000) - 0x8000;
12323 break;
f8df10f4 12324
39623e12
PB		 12325 default:
12326 if (howto->rightshift
12327 || (howto->src_mask & (howto->src_mask + 1)))
12328 {
12329 (*_bfd_error_handler)
12330 (_("%B(%A+0x%lx): %s relocation against SEC_MERGE section"),
12331 input_bfd, input_section,
12332 (long) rel->r_offset, howto->name);
12333 return FALSE;
12334 }
12335
12336 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
12337
12338 /* Get the (signed) value from the instruction. */
12339 addend = value & howto->src_mask;
12340 if (addend & ((howto->src_mask + 1) >> 1))
12341 {
12342 bfd_signed_vma mask;
12343
12344 mask = -1;
12345 mask &= ~ howto->src_mask;
12346 addend |= mask;
12347 }
12348 break;
4e7fd91e 12349 }
39623e12 12350
4e7fd91e
PB		 12351 msec = sec;
12352 addend =
12353 _bfd_elf_rel_local_sym (output_bfd, sym, &msec, addend)
12354 - relocation;
12355 addend += msec->output_section->vma + msec->output_offset;
39623e12 12356
cc643b88 12357 /* Cases here must match those in the preceding
39623e12
PB		 12358 switch statement. */
12359 switch (r_type)
12360 {
12361 case R_ARM_MOVW_ABS_NC:
12362 case R_ARM_MOVT_ABS:
12363 value = (value & 0xfff0f000) | ((addend & 0xf000) << 4)
12364 | (addend & 0xfff);
12365 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
12366 break;
12367
12368 case R_ARM_THM_MOVW_ABS_NC:
12369 case R_ARM_THM_MOVT_ABS:
12370 value = (value & 0xfbf08f00) | ((addend & 0xf700) << 4)
12371 | (addend & 0xff) | ((addend & 0x0800) << 15);
12372 bfd_put_16 (input_bfd, value >> 16,
12373 contents + rel->r_offset);
12374 bfd_put_16 (input_bfd, value,
12375 contents + rel->r_offset + 2);
12376 break;
12377
12378 default:
12379 value = (value & ~ howto->dst_mask)
12380 | (addend & howto->dst_mask);
12381 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
12382 break;
12383 }
f8df10f4 12384 }
f8df10f4 12385 }
4e7fd91e
PB		 12386 else
12387 relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
252b5132
RH		 12388 }
12389 else
12390 {
62d887d4 12391 bfd_boolean warned, ignored;
560e09e9 12392
b2a8e766
AM		 12393 RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
12394 r_symndx, symtab_hdr, sym_hashes,
12395 h, sec, relocation,
62d887d4 12396 unresolved_reloc, warned, ignored);
ba93b8ac
DJ		 12397
12398 sym_type = h->type;
252b5132
RH		 12399 }
12400
dbaa2011 12401 if (sec != NULL && discarded_section (sec))
e4067dbb 12402 RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
545fd46b 12403 rel, 1, relend, howto, 0, contents);
ab96bf03 12404
0e1862bb 12405 if (bfd_link_relocatable (info))
ab96bf03
AM		 12406 {
12407 /* This is a relocatable link. We don't have to change
12408 anything, unless the reloc is against a section symbol,
12409 in which case we have to adjust according to where the
12410 section symbol winds up in the output section. */
12411 if (sym != NULL && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
12412 {
12413 if (globals->use_rel)
12414 arm_add_to_rel (input_bfd, contents + rel->r_offset,
12415 howto, (bfd_signed_vma) sec->output_offset);
12416 else
12417 rel->r_addend += sec->output_offset;
12418 }
12419 continue;
12420 }
12421
252b5132
RH		 12422 if (h != NULL)
12423 name = h->root.root.string;
12424 else
12425 {
12426 name = (bfd_elf_string_from_elf_section
12427 (input_bfd, symtab_hdr->sh_link, sym->st_name));
12428 if (name == NULL || *name == '\0')
12429 name = bfd_section_name (input_bfd, sec);
12430 }
f21f3fe0 12431
cf35638d 12432 if (r_symndx != STN_UNDEF
ba93b8ac
DJ		 12433 && r_type != R_ARM_NONE
12434 && (h == NULL
12435 || h->root.type == bfd_link_hash_defined
12436 || h->root.type == bfd_link_hash_defweak)
12437 && IS_ARM_TLS_RELOC (r_type) != (sym_type == STT_TLS))
12438 {
12439 (*_bfd_error_handler)
12440 ((sym_type == STT_TLS
12441 ? _("%B(%A+0x%lx): %s used with TLS symbol %s")
12442 : _("%B(%A+0x%lx): %s used with non-TLS symbol %s")),
12443 input_bfd,
12444 input_section,
12445 (long) rel->r_offset,
12446 howto->name,
12447 name);
12448 }
12449
0855e32b 12450 /* We call elf32_arm_final_link_relocate unless we're completely
99059e56
RM		 12451 done, i.e., the relaxation produced the final output we want,
12452 and we won't let anybody mess with it. Also, we have to do
12453 addend adjustments in case of a R_ARM_TLS_GOTDESC relocation
6a631e86 12454 both in relaxed and non-relaxed cases. */
39d911fc
TP		 12455 if ((elf32_arm_tls_transition (info, r_type, h) != (unsigned)r_type)
12456 || (IS_ARM_TLS_GNU_RELOC (r_type)
12457 && !((h ? elf32_arm_hash_entry (h)->tls_type :
12458 elf32_arm_local_got_tls_type (input_bfd)[r_symndx])
12459 & GOT_TLS_GDESC)))
12460 {
12461 r = elf32_arm_tls_relax (globals, input_bfd, input_section,
12462 contents, rel, h == NULL);
12463 /* This may have been marked unresolved because it came from
12464 a shared library. But we've just dealt with that. */
12465 unresolved_reloc = 0;
12466 }
12467 else
12468 r = bfd_reloc_continue;
b38cadfb 12469
39d911fc
TP		 12470 if (r == bfd_reloc_continue)
12471 {
12472 unsigned char branch_type =
12473 h ? ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
12474 : ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
12475
12476 r = elf32_arm_final_link_relocate (howto, input_bfd, output_bfd,
12477 input_section, contents, rel,
12478 relocation, info, sec, name,
12479 sym_type, branch_type, h,
12480 &unresolved_reloc,
12481 &error_message);
12482 }
0945cdfd
DJ		 12483
12484 /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
12485 because such sections are not SEC_ALLOC and thus ld.so will
12486 not process them. */
12487 if (unresolved_reloc
99059e56
RM		 12488 && !((input_section->flags & SEC_DEBUGGING) != 0
12489 && h->def_dynamic)
1d5316ab
AM		 12490 && _bfd_elf_section_offset (output_bfd, info, input_section,
12491 rel->r_offset) != (bfd_vma) -1)
0945cdfd
DJ		 12492 {
12493 (*_bfd_error_handler)
843fe662
L		 12494 (_("%B(%A+0x%lx): unresolvable %s relocation against symbol `%s'"),
12495 input_bfd,
12496 input_section,
12497 (long) rel->r_offset,
12498 howto->name,
12499 h->root.root.string);
0945cdfd
DJ		 12500 return FALSE;
12501 }
252b5132
RH		 12502
12503 if (r != bfd_reloc_ok)
12504 {
252b5132
RH		 12505 switch (r)
12506 {
12507 case bfd_reloc_overflow:
cf919dfd
PB		 12508 /* If the overflowing reloc was to an undefined symbol,
12509 we have already printed one error message and there
12510 is no point complaining again. */
1a72702b
AM		 12511 if (!h || h->root.type != bfd_link_hash_undefined)
12512 (*info->callbacks->reloc_overflow)
12513 (info, (h ? &h->root : NULL), name, howto->name,
12514 (bfd_vma) 0, input_bfd, input_section, rel->r_offset);
252b5132
RH		 12515 break;
12516
12517 case bfd_reloc_undefined:
1a72702b
AM		 12518 (*info->callbacks->undefined_symbol)
12519 (info, name, input_bfd, input_section, rel->r_offset, TRUE);
252b5132
RH		 12520 break;
12521
12522 case bfd_reloc_outofrange:
f2a9dd69 12523 error_message = _("out of range");
252b5132
RH		 12524 goto common_error;
12525
12526 case bfd_reloc_notsupported:
f2a9dd69 12527 error_message = _("unsupported relocation");
252b5132
RH		 12528 goto common_error;
12529
12530 case bfd_reloc_dangerous:
f2a9dd69 12531 /* error_message should already be set. */
252b5132
RH		 12532 goto common_error;
12533
12534 default:
f2a9dd69 12535 error_message = _("unknown error");
8029a119 12536 /* Fall through. */
252b5132
RH		 12537
12538 common_error:
f2a9dd69 12539 BFD_ASSERT (error_message != NULL);
1a72702b
AM		 12540 (*info->callbacks->reloc_dangerous)
12541 (info, error_message, input_bfd, input_section, rel->r_offset);
252b5132
RH		 12542 break;
12543 }
12544 }
12545 }
12546
b34976b6 12547 return TRUE;
252b5132
RH		 12548}
12549
91d6fa6a 12550/* Add a new unwind edit to the list described by HEAD, TAIL. If TINDEX is zero,
2468f9c9 12551 adds the edit to the start of the list. (The list must be built in order of
91d6fa6a 12552 ascending TINDEX: the function's callers are primarily responsible for
2468f9c9
PB		 12553 maintaining that condition). */
12554
12555static void
12556add_unwind_table_edit (arm_unwind_table_edit **head,
12557 arm_unwind_table_edit **tail,
12558 arm_unwind_edit_type type,
12559 asection *linked_section,
91d6fa6a 12560 unsigned int tindex)
2468f9c9 12561{
21d799b5
NC		 12562 arm_unwind_table_edit *new_edit = (arm_unwind_table_edit *)
12563 xmalloc (sizeof (arm_unwind_table_edit));
b38cadfb 12564
2468f9c9
PB		 12565 new_edit->type = type;
12566 new_edit->linked_section = linked_section;
91d6fa6a 12567 new_edit->index = tindex;
b38cadfb 12568
91d6fa6a 12569 if (tindex > 0)
2468f9c9
PB		 12570 {
12571 new_edit->next = NULL;
12572
12573 if (*tail)
12574 (*tail)->next = new_edit;
12575
12576 (*tail) = new_edit;
12577
12578 if (!*head)
12579 (*head) = new_edit;
12580 }
12581 else
12582 {
12583 new_edit->next = *head;
12584
12585 if (!*tail)
12586 *tail = new_edit;
12587
12588 *head = new_edit;
12589 }
12590}
12591
12592static _arm_elf_section_data *get_arm_elf_section_data (asection *);
12593
12594/* Increase the size of EXIDX_SEC by ADJUST bytes. ADJUST mau be negative. */
12595static void
12596adjust_exidx_size(asection *exidx_sec, int adjust)
12597{
12598 asection *out_sec;
12599
12600 if (!exidx_sec->rawsize)
12601 exidx_sec->rawsize = exidx_sec->size;
12602
12603 bfd_set_section_size (exidx_sec->owner, exidx_sec, exidx_sec->size + adjust);
12604 out_sec = exidx_sec->output_section;
12605 /* Adjust size of output section. */
12606 bfd_set_section_size (out_sec->owner, out_sec, out_sec->size +adjust);
12607}
12608
12609/* Insert an EXIDX_CANTUNWIND marker at the end of a section. */
12610static void
12611insert_cantunwind_after(asection *text_sec, asection *exidx_sec)
12612{
12613 struct _arm_elf_section_data *exidx_arm_data;
12614
12615 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
12616 add_unwind_table_edit (
12617 &exidx_arm_data->u.exidx.unwind_edit_list,
12618 &exidx_arm_data->u.exidx.unwind_edit_tail,
12619 INSERT_EXIDX_CANTUNWIND_AT_END, text_sec, UINT_MAX);
12620
491d01d3
YU		 12621 exidx_arm_data->additional_reloc_count++;
12622
2468f9c9
PB		 12623 adjust_exidx_size(exidx_sec, 8);
12624}
12625
12626/* Scan .ARM.exidx tables, and create a list describing edits which should be
12627 made to those tables, such that:
b38cadfb 12628
2468f9c9
PB		 12629 1. Regions without unwind data are marked with EXIDX_CANTUNWIND entries.
12630 2. Duplicate entries are merged together (EXIDX_CANTUNWIND, or unwind
99059e56 12631 codes which have been inlined into the index).
2468f9c9 12632
85fdf906
AH		 12633 If MERGE_EXIDX_ENTRIES is false, duplicate entries are not merged.
12634
2468f9c9 12635 The edits are applied when the tables are written
b38cadfb 12636 (in elf32_arm_write_section). */
2468f9c9
PB		 12637
12638bfd_boolean
12639elf32_arm_fix_exidx_coverage (asection **text_section_order,
12640 unsigned int num_text_sections,
85fdf906
AH		 12641 struct bfd_link_info *info,
12642 bfd_boolean merge_exidx_entries)
2468f9c9
PB		 12643{
12644 bfd *inp;
12645 unsigned int last_second_word = 0, i;
12646 asection *last_exidx_sec = NULL;
12647 asection *last_text_sec = NULL;
12648 int last_unwind_type = -1;
12649
12650 /* Walk over all EXIDX sections, and create backlinks from the corrsponding
12651 text sections. */
c72f2fb2 12652 for (inp = info->input_bfds; inp != NULL; inp = inp->link.next)
2468f9c9
PB		 12653 {
12654 asection *sec;
b38cadfb 12655
2468f9c9 12656 for (sec = inp->sections; sec != NULL; sec = sec->next)
99059e56 12657 {
2468f9c9
PB		 12658 struct bfd_elf_section_data *elf_sec = elf_section_data (sec);
12659 Elf_Internal_Shdr *hdr = &elf_sec->this_hdr;
b38cadfb 12660
dec9d5df 12661 if (!hdr || hdr->sh_type != SHT_ARM_EXIDX)
2468f9c9 12662 continue;
b38cadfb 12663
2468f9c9
PB		 12664 if (elf_sec->linked_to)
12665 {
12666 Elf_Internal_Shdr *linked_hdr
99059e56 12667 = &elf_section_data (elf_sec->linked_to)->this_hdr;
2468f9c9 12668 struct _arm_elf_section_data *linked_sec_arm_data
99059e56 12669 = get_arm_elf_section_data (linked_hdr->bfd_section);
2468f9c9
PB		 12670
12671 if (linked_sec_arm_data == NULL)
99059e56 12672 continue;
2468f9c9
PB		 12673
12674 /* Link this .ARM.exidx section back from the text section it
99059e56 12675 describes. */
2468f9c9
PB		 12676 linked_sec_arm_data->u.text.arm_exidx_sec = sec;
12677 }
12678 }
12679 }
12680
12681 /* Walk all text sections in order of increasing VMA. Eilminate duplicate
12682 index table entries (EXIDX_CANTUNWIND and inlined unwind opcodes),
91d6fa6a 12683 and add EXIDX_CANTUNWIND entries for sections with no unwind table data. */
2468f9c9
PB		 12684
12685 for (i = 0; i < num_text_sections; i++)
12686 {
12687 asection *sec = text_section_order[i];
12688 asection *exidx_sec;
12689 struct _arm_elf_section_data *arm_data = get_arm_elf_section_data (sec);
12690 struct _arm_elf_section_data *exidx_arm_data;
12691 bfd_byte *contents = NULL;
12692 int deleted_exidx_bytes = 0;
12693 bfd_vma j;
12694 arm_unwind_table_edit *unwind_edit_head = NULL;
12695 arm_unwind_table_edit *unwind_edit_tail = NULL;
12696 Elf_Internal_Shdr *hdr;
12697 bfd *ibfd;
12698
12699 if (arm_data == NULL)
99059e56 12700 continue;
2468f9c9
PB		 12701
12702 exidx_sec = arm_data->u.text.arm_exidx_sec;
12703 if (exidx_sec == NULL)
12704 {
12705 /* Section has no unwind data. */
12706 if (last_unwind_type == 0 || !last_exidx_sec)
12707 continue;
12708
12709 /* Ignore zero sized sections. */
12710 if (sec->size == 0)
12711 continue;
12712
12713 insert_cantunwind_after(last_text_sec, last_exidx_sec);
12714 last_unwind_type = 0;
12715 continue;
12716 }
12717
22a8f80e
PB		 12718 /* Skip /DISCARD/ sections. */
12719 if (bfd_is_abs_section (exidx_sec->output_section))
12720 continue;
12721
2468f9c9
PB		 12722 hdr = &elf_section_data (exidx_sec)->this_hdr;
12723 if (hdr->sh_type != SHT_ARM_EXIDX)
99059e56 12724 continue;
b38cadfb 12725
2468f9c9
PB		 12726 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
12727 if (exidx_arm_data == NULL)
99059e56 12728 continue;
b38cadfb 12729
2468f9c9 12730 ibfd = exidx_sec->owner;
b38cadfb 12731
2468f9c9
PB		 12732 if (hdr->contents != NULL)
12733 contents = hdr->contents;
12734 else if (! bfd_malloc_and_get_section (ibfd, exidx_sec, &contents))
12735 /* An error? */
12736 continue;
12737
ac06903d
YU		 12738 if (last_unwind_type > 0)
12739 {
12740 unsigned int first_word = bfd_get_32 (ibfd, contents);
12741 /* Add cantunwind if first unwind item does not match section
12742 start. */
12743 if (first_word != sec->vma)
12744 {
12745 insert_cantunwind_after (last_text_sec, last_exidx_sec);
12746 last_unwind_type = 0;
12747 }
12748 }
12749
2468f9c9
PB		 12750 for (j = 0; j < hdr->sh_size; j += 8)
12751 {
12752 unsigned int second_word = bfd_get_32 (ibfd, contents + j + 4);
12753 int unwind_type;
12754 int elide = 0;
12755
12756 /* An EXIDX_CANTUNWIND entry. */
12757 if (second_word == 1)
12758 {
12759 if (last_unwind_type == 0)
12760 elide = 1;
12761 unwind_type = 0;
12762 }
12763 /* Inlined unwinding data. Merge if equal to previous. */
12764 else if ((second_word & 0x80000000) != 0)
12765 {
85fdf906
AH		 12766 if (merge_exidx_entries
12767 && last_second_word == second_word && last_unwind_type == 1)
2468f9c9
PB		 12768 elide = 1;
12769 unwind_type = 1;
12770 last_second_word = second_word;
12771 }
12772 /* Normal table entry. In theory we could merge these too,
12773 but duplicate entries are likely to be much less common. */
12774 else
12775 unwind_type = 2;
12776
491d01d3 12777 if (elide && !bfd_link_relocatable (info))
2468f9c9
PB		 12778 {
12779 add_unwind_table_edit (&unwind_edit_head, &unwind_edit_tail,
12780 DELETE_EXIDX_ENTRY, NULL, j / 8);
12781
12782 deleted_exidx_bytes += 8;
12783 }
12784
12785 last_unwind_type = unwind_type;
12786 }
12787
12788 /* Free contents if we allocated it ourselves. */
12789 if (contents != hdr->contents)
99059e56 12790 free (contents);
2468f9c9
PB		 12791
12792 /* Record edits to be applied later (in elf32_arm_write_section). */
12793 exidx_arm_data->u.exidx.unwind_edit_list = unwind_edit_head;
12794 exidx_arm_data->u.exidx.unwind_edit_tail = unwind_edit_tail;
b38cadfb 12795
2468f9c9
PB		 12796 if (deleted_exidx_bytes > 0)
12797 adjust_exidx_size(exidx_sec, -deleted_exidx_bytes);
12798
12799 last_exidx_sec = exidx_sec;
12800 last_text_sec = sec;
12801 }
12802
12803 /* Add terminating CANTUNWIND entry. */
491d01d3
YU		 12804 if (!bfd_link_relocatable (info) && last_exidx_sec
12805 && last_unwind_type != 0)
2468f9c9
PB		 12806 insert_cantunwind_after(last_text_sec, last_exidx_sec);
12807
12808 return TRUE;
12809}
12810
3e6b1042
DJ		 12811static bfd_boolean
12812elf32_arm_output_glue_section (struct bfd_link_info *info, bfd *obfd,
12813 bfd *ibfd, const char *name)
12814{
12815 asection *sec, *osec;
12816
3d4d4302 12817 sec = bfd_get_linker_section (ibfd, name);
3e6b1042
DJ		 12818 if (sec == NULL || (sec->flags & SEC_EXCLUDE) != 0)
12819 return TRUE;
12820
12821 osec = sec->output_section;
12822 if (elf32_arm_write_section (obfd, info, sec, sec->contents))
12823 return TRUE;
12824
12825 if (! bfd_set_section_contents (obfd, osec, sec->contents,
12826 sec->output_offset, sec->size))
12827 return FALSE;
12828
12829 return TRUE;
12830}
12831
12832static bfd_boolean
12833elf32_arm_final_link (bfd *abfd, struct bfd_link_info *info)
12834{
12835 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
fe33d2fa 12836 asection *sec, *osec;
3e6b1042 12837
4dfe6ac6
NC		 12838 if (globals == NULL)
12839 return FALSE;
12840
3e6b1042
DJ		 12841 /* Invoke the regular ELF backend linker to do all the work. */
12842 if (!bfd_elf_final_link (abfd, info))
12843 return FALSE;
12844
fe33d2fa
CL		 12845 /* Process stub sections (eg BE8 encoding, ...). */
12846 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
7292b3ac 12847 unsigned int i;
cdb21a0a
NS		 12848 for (i=0; i<htab->top_id; i++)
12849 {
12850 sec = htab->stub_group[i].stub_sec;
12851 /* Only process it once, in its link_sec slot. */
12852 if (sec && i == htab->stub_group[i].link_sec->id)
12853 {
12854 osec = sec->output_section;
12855 elf32_arm_write_section (abfd, info, sec, sec->contents);
12856 if (! bfd_set_section_contents (abfd, osec, sec->contents,
12857 sec->output_offset, sec->size))
12858 return FALSE;
12859 }
fe33d2fa 12860 }
fe33d2fa 12861
3e6b1042
DJ		 12862 /* Write out any glue sections now that we have created all the
12863 stubs. */
12864 if (globals->bfd_of_glue_owner != NULL)
12865 {
12866 if (! elf32_arm_output_glue_section (info, abfd,
12867 globals->bfd_of_glue_owner,
12868 ARM2THUMB_GLUE_SECTION_NAME))
12869 return FALSE;
12870
12871 if (! elf32_arm_output_glue_section (info, abfd,
12872 globals->bfd_of_glue_owner,
12873 THUMB2ARM_GLUE_SECTION_NAME))
12874 return FALSE;
12875
12876 if (! elf32_arm_output_glue_section (info, abfd,
12877 globals->bfd_of_glue_owner,
12878 VFP11_ERRATUM_VENEER_SECTION_NAME))
12879 return FALSE;
12880
a504d23a
LA		 12881 if (! elf32_arm_output_glue_section (info, abfd,
12882 globals->bfd_of_glue_owner,
12883 STM32L4XX_ERRATUM_VENEER_SECTION_NAME))
12884 return FALSE;
12885
3e6b1042
DJ		 12886 if (! elf32_arm_output_glue_section (info, abfd,
12887 globals->bfd_of_glue_owner,
12888 ARM_BX_GLUE_SECTION_NAME))
12889 return FALSE;
12890 }
12891
12892 return TRUE;
12893}
12894
5968a7b8
NC		 12895/* Return a best guess for the machine number based on the attributes. */
12896
12897static unsigned int
12898bfd_arm_get_mach_from_attributes (bfd * abfd)
12899{
12900 int arch = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_CPU_arch);
12901
12902 switch (arch)
12903 {
12904 case TAG_CPU_ARCH_V4: return bfd_mach_arm_4;
12905 case TAG_CPU_ARCH_V4T: return bfd_mach_arm_4T;
12906 case TAG_CPU_ARCH_V5T: return bfd_mach_arm_5T;
12907
12908 case TAG_CPU_ARCH_V5TE:
12909 {
12910 char * name;
12911
12912 BFD_ASSERT (Tag_CPU_name < NUM_KNOWN_OBJ_ATTRIBUTES);
12913 name = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_CPU_name].s;
12914
12915 if (name)
12916 {
12917 if (strcmp (name, "IWMMXT2") == 0)
12918 return bfd_mach_arm_iWMMXt2;
12919
12920 if (strcmp (name, "IWMMXT") == 0)
6034aab8 12921 return bfd_mach_arm_iWMMXt;
088ca6c1
NC		 12922
12923 if (strcmp (name, "XSCALE") == 0)
12924 {
12925 int wmmx;
12926
12927 BFD_ASSERT (Tag_WMMX_arch < NUM_KNOWN_OBJ_ATTRIBUTES);
12928 wmmx = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_WMMX_arch].i;
12929 switch (wmmx)
12930 {
12931 case 1: return bfd_mach_arm_iWMMXt;
12932 case 2: return bfd_mach_arm_iWMMXt2;
12933 default: return bfd_mach_arm_XScale;
12934 }
12935 }
5968a7b8
NC		 12936 }
12937
12938 return bfd_mach_arm_5TE;
12939 }
12940
12941 default:
12942 return bfd_mach_arm_unknown;
12943 }
12944}
12945
c178919b
NC		 12946/* Set the right machine number. */
12947
12948static bfd_boolean
57e8b36a 12949elf32_arm_object_p (bfd *abfd)
c178919b 12950{
5a6c6817 12951 unsigned int mach;
57e8b36a 12952
5a6c6817 12953 mach = bfd_arm_get_mach_from_notes (abfd, ARM_NOTE_SECTION);
c178919b 12954
5968a7b8
NC		 12955 if (mach == bfd_mach_arm_unknown)
12956 {
12957 if (elf_elfheader (abfd)->e_flags & EF_ARM_MAVERICK_FLOAT)
12958 mach = bfd_mach_arm_ep9312;
12959 else
12960 mach = bfd_arm_get_mach_from_attributes (abfd);
12961 }
c178919b 12962
5968a7b8 12963 bfd_default_set_arch_mach (abfd, bfd_arch_arm, mach);
c178919b
NC		 12964 return TRUE;
12965}
12966
fc830a83 12967/* Function to keep ARM specific flags in the ELF header. */
3c9458e9 12968
b34976b6 12969static bfd_boolean
57e8b36a 12970elf32_arm_set_private_flags (bfd *abfd, flagword flags)
252b5132
RH		 12971{
12972 if (elf_flags_init (abfd)
12973 && elf_elfheader (abfd)->e_flags != flags)
12974 {
fc830a83
NC		 12975 if (EF_ARM_EABI_VERSION (flags) == EF_ARM_EABI_UNKNOWN)
12976 {
fd2ec330 12977 if (flags & EF_ARM_INTERWORK)
d003868e
AM		 12978 (*_bfd_error_handler)
12979 (_("Warning: Not setting interworking flag of %B since it has already been specified as non-interworking"),
12980 abfd);
fc830a83 12981 else
d003868e
AM		 12982 _bfd_error_handler
12983 (_("Warning: Clearing the interworking flag of %B due to outside request"),
12984 abfd);
fc830a83 12985 }
252b5132
RH		 12986 }
12987 else
12988 {
12989 elf_elfheader (abfd)->e_flags = flags;
b34976b6 12990 elf_flags_init (abfd) = TRUE;
252b5132
RH		 12991 }
12992
b34976b6 12993 return TRUE;
252b5132
RH		 12994}
12995
fc830a83 12996/* Copy backend specific data from one object module to another. */
9b485d32 12997
b34976b6 12998static bfd_boolean
57e8b36a 12999elf32_arm_copy_private_bfd_data (bfd *ibfd, bfd *obfd)
252b5132
RH		 13000{
13001 flagword in_flags;
13002 flagword out_flags;
13003
0ffa91dd 13004 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
b34976b6 13005 return TRUE;
252b5132 13006
fc830a83 13007 in_flags = elf_elfheader (ibfd)->e_flags;
252b5132
RH		 13008 out_flags = elf_elfheader (obfd)->e_flags;
13009
fc830a83
NC		 13010 if (elf_flags_init (obfd)
13011 && EF_ARM_EABI_VERSION (out_flags) == EF_ARM_EABI_UNKNOWN
13012 && in_flags != out_flags)
252b5132 13013 {
252b5132 13014 /* Cannot mix APCS26 and APCS32 code. */
fd2ec330 13015 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
b34976b6 13016 return FALSE;
252b5132
RH		 13017
13018 /* Cannot mix float APCS and non-float APCS code. */
fd2ec330 13019 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
b34976b6 13020 return FALSE;
252b5132
RH		 13021
13022 /* If the src and dest have different interworking flags
99059e56 13023 then turn off the interworking bit. */
fd2ec330 13024 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
252b5132 13025 {
fd2ec330 13026 if (out_flags & EF_ARM_INTERWORK)
d003868e
AM		 13027 _bfd_error_handler
13028 (_("Warning: Clearing the interworking flag of %B because non-interworking code in %B has been linked with it"),
13029 obfd, ibfd);
252b5132 13030
fd2ec330 13031 in_flags &= ~EF_ARM_INTERWORK;
252b5132 13032 }
1006ba19
PB		 13033
13034 /* Likewise for PIC, though don't warn for this case. */
fd2ec330
PB		 13035 if ((in_flags & EF_ARM_PIC) != (out_flags & EF_ARM_PIC))
13036 in_flags &= ~EF_ARM_PIC;
252b5132
RH		 13037 }
13038
13039 elf_elfheader (obfd)->e_flags = in_flags;
b34976b6 13040 elf_flags_init (obfd) = TRUE;
252b5132 13041
e2349352 13042 return _bfd_elf_copy_private_bfd_data (ibfd, obfd);
ee065d83
PB		 13043}
13044
13045/* Values for Tag_ABI_PCS_R9_use. */
13046enum
13047{
13048 AEABI_R9_V6,
13049 AEABI_R9_SB,
13050 AEABI_R9_TLS,
13051 AEABI_R9_unused
13052};
13053
13054/* Values for Tag_ABI_PCS_RW_data. */
13055enum
13056{
13057 AEABI_PCS_RW_data_absolute,
13058 AEABI_PCS_RW_data_PCrel,
13059 AEABI_PCS_RW_data_SBrel,
13060 AEABI_PCS_RW_data_unused
13061};
13062
13063/* Values for Tag_ABI_enum_size. */
13064enum
13065{
13066 AEABI_enum_unused,
13067 AEABI_enum_short,
13068 AEABI_enum_wide,
13069 AEABI_enum_forced_wide
13070};
13071
104d59d1
JM		 13072/* Determine whether an object attribute tag takes an integer, a
13073 string or both. */
906e58ca 13074
104d59d1
JM		 13075static int
13076elf32_arm_obj_attrs_arg_type (int tag)
13077{
13078 if (tag == Tag_compatibility)
3483fe2e 13079 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_STR_VAL;
2d0bb761 13080 else if (tag == Tag_nodefaults)
3483fe2e
AS		 13081 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_NO_DEFAULT;
13082 else if (tag == Tag_CPU_raw_name || tag == Tag_CPU_name)
13083 return ATTR_TYPE_FLAG_STR_VAL;
104d59d1 13084 else if (tag < 32)
3483fe2e 13085 return ATTR_TYPE_FLAG_INT_VAL;
104d59d1 13086 else
3483fe2e 13087 return (tag & 1) != 0 ? ATTR_TYPE_FLAG_STR_VAL : ATTR_TYPE_FLAG_INT_VAL;
104d59d1
JM		 13088}
13089
5aa6ff7c
AS		 13090/* The ABI defines that Tag_conformance should be emitted first, and that
13091 Tag_nodefaults should be second (if either is defined). This sets those
13092 two positions, and bumps up the position of all the remaining tags to
13093 compensate. */
13094static int
13095elf32_arm_obj_attrs_order (int num)
13096{
3de4a297 13097 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE)
5aa6ff7c 13098 return Tag_conformance;
3de4a297 13099 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE + 1)
5aa6ff7c
AS		 13100 return Tag_nodefaults;
13101 if ((num - 2) < Tag_nodefaults)
13102 return num - 2;
13103 if ((num - 1) < Tag_conformance)
13104 return num - 1;
13105 return num;
13106}
13107
e8b36cd1
JM		 13108/* Attribute numbers >=64 (mod 128) can be safely ignored. */
13109static bfd_boolean
13110elf32_arm_obj_attrs_handle_unknown (bfd *abfd, int tag)
13111{
13112 if ((tag & 127) < 64)
13113 {
13114 _bfd_error_handler
13115 (_("%B: Unknown mandatory EABI object attribute %d"),
13116 abfd, tag);
13117 bfd_set_error (bfd_error_bad_value);
13118 return FALSE;
13119 }
13120 else
13121 {
13122 _bfd_error_handler
13123 (_("Warning: %B: Unknown EABI object attribute %d"),
13124 abfd, tag);
13125 return TRUE;
13126 }
13127}
13128
91e22acd
AS		 13129/* Read the architecture from the Tag_also_compatible_with attribute, if any.
13130 Returns -1 if no architecture could be read. */
13131
13132static int
13133get_secondary_compatible_arch (bfd *abfd)
13134{
13135 obj_attribute *attr =
13136 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
13137
13138 /* Note: the tag and its argument below are uleb128 values, though
13139 currently-defined values fit in one byte for each. */
13140 if (attr->s
13141 && attr->s[0] == Tag_CPU_arch
13142 && (attr->s[1] & 128) != 128
13143 && attr->s[2] == 0)
13144 return attr->s[1];
13145
13146 /* This tag is "safely ignorable", so don't complain if it looks funny. */
13147 return -1;
13148}
13149
13150/* Set, or unset, the architecture of the Tag_also_compatible_with attribute.
13151 The tag is removed if ARCH is -1. */
13152
8e79c3df 13153static void
91e22acd 13154set_secondary_compatible_arch (bfd *abfd, int arch)
8e79c3df 13155{
91e22acd
AS		 13156 obj_attribute *attr =
13157 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
8e79c3df 13158
91e22acd
AS		 13159 if (arch == -1)
13160 {
13161 attr->s = NULL;
13162 return;
8e79c3df 13163 }
91e22acd
AS		 13164
13165 /* Note: the tag and its argument below are uleb128 values, though
13166 currently-defined values fit in one byte for each. */
13167 if (!attr->s)
21d799b5 13168 attr->s = (char *) bfd_alloc (abfd, 3);
91e22acd
AS		 13169 attr->s[0] = Tag_CPU_arch;
13170 attr->s[1] = arch;
13171 attr->s[2] = '\0';
8e79c3df
CM		 13172}
13173
91e22acd
AS		 13174/* Combine two values for Tag_CPU_arch, taking secondary compatibility tags
13175 into account. */
13176
13177static int
13178tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
13179 int newtag, int secondary_compat)
8e79c3df 13180{
91e22acd
AS		 13181#define T(X) TAG_CPU_ARCH_##X
13182 int tagl, tagh, result;
13183 const int v6t2[] =
13184 {
13185 T(V6T2), /* PRE_V4. */
13186 T(V6T2), /* V4. */
13187 T(V6T2), /* V4T. */
13188 T(V6T2), /* V5T. */
13189 T(V6T2), /* V5TE. */
13190 T(V6T2), /* V5TEJ. */
13191 T(V6T2), /* V6. */
13192 T(V7), /* V6KZ. */
13193 T(V6T2) /* V6T2. */
13194 };
13195 const int v6k[] =
13196 {
13197 T(V6K), /* PRE_V4. */
13198 T(V6K), /* V4. */
13199 T(V6K), /* V4T. */
13200 T(V6K), /* V5T. */
13201 T(V6K), /* V5TE. */
13202 T(V6K), /* V5TEJ. */
13203 T(V6K), /* V6. */
13204 T(V6KZ), /* V6KZ. */
13205 T(V7), /* V6T2. */
13206 T(V6K) /* V6K. */
13207 };
13208 const int v7[] =
13209 {
13210 T(V7), /* PRE_V4. */
13211 T(V7), /* V4. */
13212 T(V7), /* V4T. */
13213 T(V7), /* V5T. */
13214 T(V7), /* V5TE. */
13215 T(V7), /* V5TEJ. */
13216 T(V7), /* V6. */
13217 T(V7), /* V6KZ. */
13218 T(V7), /* V6T2. */
13219 T(V7), /* V6K. */
13220 T(V7) /* V7. */
13221 };
13222 const int v6_m[] =
13223 {
13224 -1, /* PRE_V4. */
13225 -1, /* V4. */
13226 T(V6K), /* V4T. */
13227 T(V6K), /* V5T. */
13228 T(V6K), /* V5TE. */
13229 T(V6K), /* V5TEJ. */
13230 T(V6K), /* V6. */
13231 T(V6KZ), /* V6KZ. */
13232 T(V7), /* V6T2. */
13233 T(V6K), /* V6K. */
13234 T(V7), /* V7. */
13235 T(V6_M) /* V6_M. */
13236 };
13237 const int v6s_m[] =
13238 {
13239 -1, /* PRE_V4. */
13240 -1, /* V4. */
13241 T(V6K), /* V4T. */
13242 T(V6K), /* V5T. */
13243 T(V6K), /* V5TE. */
13244 T(V6K), /* V5TEJ. */
13245 T(V6K), /* V6. */
13246 T(V6KZ), /* V6KZ. */
13247 T(V7), /* V6T2. */
13248 T(V6K), /* V6K. */
13249 T(V7), /* V7. */
13250 T(V6S_M), /* V6_M. */
13251 T(V6S_M) /* V6S_M. */
13252 };
9e3c6df6
PB		 13253 const int v7e_m[] =
13254 {
13255 -1, /* PRE_V4. */
13256 -1, /* V4. */
13257 T(V7E_M), /* V4T. */
13258 T(V7E_M), /* V5T. */
13259 T(V7E_M), /* V5TE. */
13260 T(V7E_M), /* V5TEJ. */
13261 T(V7E_M), /* V6. */
13262 T(V7E_M), /* V6KZ. */
13263 T(V7E_M), /* V6T2. */
13264 T(V7E_M), /* V6K. */
13265 T(V7E_M), /* V7. */
13266 T(V7E_M), /* V6_M. */
13267 T(V7E_M), /* V6S_M. */
13268 T(V7E_M) /* V7E_M. */
13269 };
bca38921
MGD		 13270 const int v8[] =
13271 {
13272 T(V8), /* PRE_V4. */
13273 T(V8), /* V4. */
13274 T(V8), /* V4T. */
13275 T(V8), /* V5T. */
13276 T(V8), /* V5TE. */
13277 T(V8), /* V5TEJ. */
13278 T(V8), /* V6. */
13279 T(V8), /* V6KZ. */
13280 T(V8), /* V6T2. */
13281 T(V8), /* V6K. */
13282 T(V8), /* V7. */
13283 T(V8), /* V6_M. */
13284 T(V8), /* V6S_M. */
13285 T(V8), /* V7E_M. */
13286 T(V8) /* V8. */
13287 };
2fd158eb
TP		 13288 const int v8m_baseline[] =
13289 {
13290 -1, /* PRE_V4. */
13291 -1, /* V4. */
13292 -1, /* V4T. */
13293 -1, /* V5T. */
13294 -1, /* V5TE. */
13295 -1, /* V5TEJ. */
13296 -1, /* V6. */
13297 -1, /* V6KZ. */
13298 -1, /* V6T2. */
13299 -1, /* V6K. */
13300 -1, /* V7. */
13301 T(V8M_BASE), /* V6_M. */
13302 T(V8M_BASE), /* V6S_M. */
13303 -1, /* V7E_M. */
13304 -1, /* V8. */
13305 -1,
13306 T(V8M_BASE) /* V8-M BASELINE. */
13307 };
13308 const int v8m_mainline[] =
13309 {
13310 -1, /* PRE_V4. */
13311 -1, /* V4. */
13312 -1, /* V4T. */
13313 -1, /* V5T. */
13314 -1, /* V5TE. */
13315 -1, /* V5TEJ. */
13316 -1, /* V6. */
13317 -1, /* V6KZ. */
13318 -1, /* V6T2. */
13319 -1, /* V6K. */
13320 T(V8M_MAIN), /* V7. */
13321 T(V8M_MAIN), /* V6_M. */
13322 T(V8M_MAIN), /* V6S_M. */
13323 T(V8M_MAIN), /* V7E_M. */
13324 -1, /* V8. */
13325 -1,
13326 T(V8M_MAIN), /* V8-M BASELINE. */
13327 T(V8M_MAIN) /* V8-M MAINLINE. */
13328 };
91e22acd
AS		 13329 const int v4t_plus_v6_m[] =
13330 {
13331 -1, /* PRE_V4. */
13332 -1, /* V4. */
13333 T(V4T), /* V4T. */
13334 T(V5T), /* V5T. */
13335 T(V5TE), /* V5TE. */
13336 T(V5TEJ), /* V5TEJ. */
13337 T(V6), /* V6. */
13338 T(V6KZ), /* V6KZ. */
13339 T(V6T2), /* V6T2. */
13340 T(V6K), /* V6K. */
13341 T(V7), /* V7. */
13342 T(V6_M), /* V6_M. */
13343 T(V6S_M), /* V6S_M. */
9e3c6df6 13344 T(V7E_M), /* V7E_M. */
bca38921 13345 T(V8), /* V8. */
4ed7ed8d 13346 -1, /* Unused. */
2fd158eb
TP		 13347 T(V8M_BASE), /* V8-M BASELINE. */
13348 T(V8M_MAIN), /* V8-M MAINLINE. */
91e22acd
AS		 13349 T(V4T_PLUS_V6_M) /* V4T plus V6_M. */
13350 };
13351 const int *comb[] =
13352 {
13353 v6t2,
13354 v6k,
13355 v7,
13356 v6_m,
13357 v6s_m,
9e3c6df6 13358 v7e_m,
bca38921 13359 v8,
4ed7ed8d 13360 NULL,
2fd158eb
TP		 13361 v8m_baseline,
13362 v8m_mainline,
91e22acd
AS		 13363 /* Pseudo-architecture. */
13364 v4t_plus_v6_m
13365 };
13366
13367 /* Check we've not got a higher architecture than we know about. */
13368
9e3c6df6 13369 if (oldtag > MAX_TAG_CPU_ARCH || newtag > MAX_TAG_CPU_ARCH)
91e22acd 13370 {
3895f852 13371 _bfd_error_handler (_("error: %B: Unknown CPU architecture"), ibfd);
91e22acd
AS		 13372 return -1;
13373 }
13374
13375 /* Override old tag if we have a Tag_also_compatible_with on the output. */
13376
13377 if ((oldtag == T(V6_M) && *secondary_compat_out == T(V4T))
13378 || (oldtag == T(V4T) && *secondary_compat_out == T(V6_M)))
13379 oldtag = T(V4T_PLUS_V6_M);
13380
13381 /* And override the new tag if we have a Tag_also_compatible_with on the
13382 input. */
13383
13384 if ((newtag == T(V6_M) && secondary_compat == T(V4T))
13385 || (newtag == T(V4T) && secondary_compat == T(V6_M)))
13386 newtag = T(V4T_PLUS_V6_M);
13387
13388 tagl = (oldtag < newtag) ? oldtag : newtag;
13389 result = tagh = (oldtag > newtag) ? oldtag : newtag;
13390
13391 /* Architectures before V6KZ add features monotonically. */
13392 if (tagh <= TAG_CPU_ARCH_V6KZ)
13393 return result;
13394
4ed7ed8d 13395 result = comb[tagh - T(V6T2)] ? comb[tagh - T(V6T2)][tagl] : -1;
91e22acd
AS		 13396
13397 /* Use Tag_CPU_arch == V4T and Tag_also_compatible_with (Tag_CPU_arch V6_M)
13398 as the canonical version. */
13399 if (result == T(V4T_PLUS_V6_M))
13400 {
13401 result = T(V4T);
13402 *secondary_compat_out = T(V6_M);
13403 }
13404 else
13405 *secondary_compat_out = -1;
13406
13407 if (result == -1)
13408 {
3895f852 13409 _bfd_error_handler (_("error: %B: Conflicting CPU architectures %d/%d"),
91e22acd
AS		 13410 ibfd, oldtag, newtag);
13411 return -1;
13412 }
13413
13414 return result;
13415#undef T
8e79c3df
CM		 13416}
13417
ac56ee8f
MGD		 13418/* Query attributes object to see if integer divide instructions may be
13419 present in an object. */
13420static bfd_boolean
13421elf32_arm_attributes_accept_div (const obj_attribute *attr)
13422{
13423 int arch = attr[Tag_CPU_arch].i;
13424 int profile = attr[Tag_CPU_arch_profile].i;
13425
13426 switch (attr[Tag_DIV_use].i)
13427 {
13428 case 0:
13429 /* Integer divide allowed if instruction contained in archetecture. */
13430 if (arch == TAG_CPU_ARCH_V7 && (profile == 'R' || profile == 'M'))
13431 return TRUE;
13432 else if (arch >= TAG_CPU_ARCH_V7E_M)
13433 return TRUE;
13434 else
13435 return FALSE;
13436
13437 case 1:
13438 /* Integer divide explicitly prohibited. */
13439 return FALSE;
13440
13441 default:
13442 /* Unrecognised case - treat as allowing divide everywhere. */
13443 case 2:
13444 /* Integer divide allowed in ARM state. */
13445 return TRUE;
13446 }
13447}
13448
13449/* Query attributes object to see if integer divide instructions are
13450 forbidden to be in the object. This is not the inverse of
13451 elf32_arm_attributes_accept_div. */
13452static bfd_boolean
13453elf32_arm_attributes_forbid_div (const obj_attribute *attr)
13454{
13455 return attr[Tag_DIV_use].i == 1;
13456}
13457
ee065d83
PB		 13458/* Merge EABI object attributes from IBFD into OBFD. Raise an error if there
13459 are conflicting attributes. */
906e58ca 13460
ee065d83
PB		 13461static bfd_boolean
13462elf32_arm_merge_eabi_attributes (bfd *ibfd, bfd *obfd)
13463{
104d59d1
JM		 13464 obj_attribute *in_attr;
13465 obj_attribute *out_attr;
ee065d83
PB		 13466 /* Some tags have 0 = don't care, 1 = strong requirement,
13467 2 = weak requirement. */
91e22acd 13468 static const int order_021[3] = {0, 2, 1};
ee065d83 13469 int i;
91e22acd 13470 bfd_boolean result = TRUE;
9274e9de 13471 const char *sec_name = get_elf_backend_data (ibfd)->obj_attrs_section;
ee065d83 13472
3e6b1042
DJ		 13473 /* Skip the linker stubs file. This preserves previous behavior
13474 of accepting unknown attributes in the first input file - but
13475 is that a bug? */
13476 if (ibfd->flags & BFD_LINKER_CREATED)
13477 return TRUE;
13478
9274e9de
TG		 13479 /* Skip any input that hasn't attribute section.
13480 This enables to link object files without attribute section with
13481 any others. */
13482 if (bfd_get_section_by_name (ibfd, sec_name) == NULL)
13483 return TRUE;
13484
104d59d1 13485 if (!elf_known_obj_attributes_proc (obfd)[0].i)
ee065d83
PB		 13486 {
13487 /* This is the first object. Copy the attributes. */
104d59d1 13488 _bfd_elf_copy_obj_attributes (ibfd, obfd);
004ae526 13489
cd21e546
MGD		 13490 out_attr = elf_known_obj_attributes_proc (obfd);
13491
004ae526
PB		 13492 /* Use the Tag_null value to indicate the attributes have been
13493 initialized. */
cd21e546 13494 out_attr[0].i = 1;
004ae526 13495
cd21e546
MGD		 13496 /* We do not output objects with Tag_MPextension_use_legacy - we move
13497 the attribute's value to Tag_MPextension_use. */
13498 if (out_attr[Tag_MPextension_use_legacy].i != 0)
13499 {
13500 if (out_attr[Tag_MPextension_use].i != 0
13501 && out_attr[Tag_MPextension_use_legacy].i
99059e56 13502 != out_attr[Tag_MPextension_use].i)
cd21e546
MGD		 13503 {
13504 _bfd_error_handler
13505 (_("Error: %B has both the current and legacy "
13506 "Tag_MPextension_use attributes"), ibfd);
13507 result = FALSE;
13508 }
13509
13510 out_attr[Tag_MPextension_use] =
13511 out_attr[Tag_MPextension_use_legacy];
13512 out_attr[Tag_MPextension_use_legacy].type = 0;
13513 out_attr[Tag_MPextension_use_legacy].i = 0;
13514 }
13515
13516 return result;
ee065d83
PB		 13517 }
13518
104d59d1
JM		 13519 in_attr = elf_known_obj_attributes_proc (ibfd);
13520 out_attr = elf_known_obj_attributes_proc (obfd);
ee065d83
PB		 13521 /* This needs to happen before Tag_ABI_FP_number_model is merged. */
13522 if (in_attr[Tag_ABI_VFP_args].i != out_attr[Tag_ABI_VFP_args].i)
13523 {
5c294fee
TG		 13524 /* Ignore mismatches if the object doesn't use floating point or is
13525 floating point ABI independent. */
13526 if (out_attr[Tag_ABI_FP_number_model].i == AEABI_FP_number_model_none
13527 || (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
13528 && out_attr[Tag_ABI_VFP_args].i == AEABI_VFP_args_compatible))
ee065d83 13529 out_attr[Tag_ABI_VFP_args].i = in_attr[Tag_ABI_VFP_args].i;
5c294fee
TG		 13530 else if (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
13531 && in_attr[Tag_ABI_VFP_args].i != AEABI_VFP_args_compatible)
ee065d83
PB		 13532 {
13533 _bfd_error_handler
3895f852 13534 (_("error: %B uses VFP register arguments, %B does not"),
deddc40b
NS		 13535 in_attr[Tag_ABI_VFP_args].i ? ibfd : obfd,
13536 in_attr[Tag_ABI_VFP_args].i ? obfd : ibfd);
91e22acd 13537 result = FALSE;
ee065d83
PB		 13538 }
13539 }
13540
3de4a297 13541 for (i = LEAST_KNOWN_OBJ_ATTRIBUTE; i < NUM_KNOWN_OBJ_ATTRIBUTES; i++)
ee065d83
PB		 13542 {
13543 /* Merge this attribute with existing attributes. */
13544 switch (i)
13545 {
13546 case Tag_CPU_raw_name:
13547 case Tag_CPU_name:
6a631e86 13548 /* These are merged after Tag_CPU_arch. */
ee065d83
PB		 13549 break;
13550
13551 case Tag_ABI_optimization_goals:
13552 case Tag_ABI_FP_optimization_goals:
13553 /* Use the first value seen. */
13554 break;
13555
13556 case Tag_CPU_arch:
91e22acd
AS		 13557 {
13558 int secondary_compat = -1, secondary_compat_out = -1;
13559 unsigned int saved_out_attr = out_attr[i].i;
70e99720
TG		 13560 int arch_attr;
13561 static const char *name_table[] =
13562 {
91e22acd
AS		 13563 /* These aren't real CPU names, but we can't guess
13564 that from the architecture version alone. */
13565 "Pre v4",
13566 "ARM v4",
13567 "ARM v4T",
13568 "ARM v5T",
13569 "ARM v5TE",
13570 "ARM v5TEJ",
13571 "ARM v6",
13572 "ARM v6KZ",
13573 "ARM v6T2",
13574 "ARM v6K",
13575 "ARM v7",
13576 "ARM v6-M",
bca38921 13577 "ARM v6S-M",
2fd158eb
TP		 13578 "ARM v8",
13579 "",
13580 "ARM v8-M.baseline",
13581 "ARM v8-M.mainline",
91e22acd
AS		 13582 };
13583
13584 /* Merge Tag_CPU_arch and Tag_also_compatible_with. */
13585 secondary_compat = get_secondary_compatible_arch (ibfd);
13586 secondary_compat_out = get_secondary_compatible_arch (obfd);
70e99720
TG		 13587 arch_attr = tag_cpu_arch_combine (ibfd, out_attr[i].i,
13588 &secondary_compat_out,
13589 in_attr[i].i,
13590 secondary_compat);
13591
13592 /* Return with error if failed to merge. */
13593 if (arch_attr == -1)
13594 return FALSE;
13595
13596 out_attr[i].i = arch_attr;
13597
91e22acd
AS		 13598 set_secondary_compatible_arch (obfd, secondary_compat_out);
13599
13600 /* Merge Tag_CPU_name and Tag_CPU_raw_name. */
13601 if (out_attr[i].i == saved_out_attr)
13602 ; /* Leave the names alone. */
13603 else if (out_attr[i].i == in_attr[i].i)
13604 {
13605 /* The output architecture has been changed to match the
13606 input architecture. Use the input names. */
13607 out_attr[Tag_CPU_name].s = in_attr[Tag_CPU_name].s
13608 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_name].s)
13609 : NULL;
13610 out_attr[Tag_CPU_raw_name].s = in_attr[Tag_CPU_raw_name].s
13611 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_raw_name].s)
13612 : NULL;
13613 }
13614 else
13615 {
13616 out_attr[Tag_CPU_name].s = NULL;
13617 out_attr[Tag_CPU_raw_name].s = NULL;
13618 }
13619
13620 /* If we still don't have a value for Tag_CPU_name,
13621 make one up now. Tag_CPU_raw_name remains blank. */
13622 if (out_attr[Tag_CPU_name].s == NULL
13623 && out_attr[i].i < ARRAY_SIZE (name_table))
13624 out_attr[Tag_CPU_name].s =
13625 _bfd_elf_attr_strdup (obfd, name_table[out_attr[i].i]);
13626 }
13627 break;
13628
ee065d83
PB		 13629 case Tag_ARM_ISA_use:
13630 case Tag_THUMB_ISA_use:
ee065d83 13631 case Tag_WMMX_arch:
91e22acd
AS		 13632 case Tag_Advanced_SIMD_arch:
13633 /* ??? Do Advanced_SIMD (NEON) and WMMX conflict? */
ee065d83 13634 case Tag_ABI_FP_rounding:
ee065d83
PB		 13635 case Tag_ABI_FP_exceptions:
13636 case Tag_ABI_FP_user_exceptions:
13637 case Tag_ABI_FP_number_model:
75375b3e 13638 case Tag_FP_HP_extension:
91e22acd
AS		 13639 case Tag_CPU_unaligned_access:
13640 case Tag_T2EE_use:
91e22acd 13641 case Tag_MPextension_use:
ee065d83
PB		 13642 /* Use the largest value specified. */
13643 if (in_attr[i].i > out_attr[i].i)
13644 out_attr[i].i = in_attr[i].i;
13645 break;
13646
75375b3e 13647 case Tag_ABI_align_preserved:
91e22acd
AS		 13648 case Tag_ABI_PCS_RO_data:
13649 /* Use the smallest value specified. */
13650 if (in_attr[i].i < out_attr[i].i)
13651 out_attr[i].i = in_attr[i].i;
13652 break;
13653
75375b3e 13654 case Tag_ABI_align_needed:
91e22acd 13655 if ((in_attr[i].i > 0 || out_attr[i].i > 0)
75375b3e
MGD		 13656 && (in_attr[Tag_ABI_align_preserved].i == 0
13657 || out_attr[Tag_ABI_align_preserved].i == 0))
ee065d83 13658 {
91e22acd
AS		 13659 /* This error message should be enabled once all non-conformant
13660 binaries in the toolchain have had the attributes set
13661 properly.
ee065d83 13662 _bfd_error_handler
3895f852 13663 (_("error: %B: 8-byte data alignment conflicts with %B"),
91e22acd
AS		 13664 obfd, ibfd);
13665 result = FALSE; */
ee065d83 13666 }
91e22acd
AS		 13667 /* Fall through. */
13668 case Tag_ABI_FP_denormal:
13669 case Tag_ABI_PCS_GOT_use:
13670 /* Use the "greatest" from the sequence 0, 2, 1, or the largest
13671 value if greater than 2 (for future-proofing). */
13672 if ((in_attr[i].i > 2 && in_attr[i].i > out_attr[i].i)
13673 || (in_attr[i].i <= 2 && out_attr[i].i <= 2
13674 && order_021[in_attr[i].i] > order_021[out_attr[i].i]))
ee065d83
PB		 13675 out_attr[i].i = in_attr[i].i;
13676 break;
91e22acd 13677
75375b3e
MGD		 13678 case Tag_Virtualization_use:
13679 /* The virtualization tag effectively stores two bits of
13680 information: the intended use of TrustZone (in bit 0), and the
13681 intended use of Virtualization (in bit 1). */
13682 if (out_attr[i].i == 0)
13683 out_attr[i].i = in_attr[i].i;
13684 else if (in_attr[i].i != 0
13685 && in_attr[i].i != out_attr[i].i)
13686 {
13687 if (in_attr[i].i <= 3 && out_attr[i].i <= 3)
13688 out_attr[i].i = 3;
13689 else
13690 {
13691 _bfd_error_handler
13692 (_("error: %B: unable to merge virtualization attributes "
13693 "with %B"),
13694 obfd, ibfd);
13695 result = FALSE;
13696 }
13697 }
13698 break;
91e22acd
AS		 13699
13700 case Tag_CPU_arch_profile:
13701 if (out_attr[i].i != in_attr[i].i)
13702 {
13703 /* 0 will merge with anything.
13704 'A' and 'S' merge to 'A'.
13705 'R' and 'S' merge to 'R'.
99059e56 13706 'M' and 'A|R|S' is an error. */
91e22acd
AS		 13707 if (out_attr[i].i == 0
13708 || (out_attr[i].i == 'S'
13709 && (in_attr[i].i == 'A' || in_attr[i].i == 'R')))
13710 out_attr[i].i = in_attr[i].i;
13711 else if (in_attr[i].i == 0
13712 || (in_attr[i].i == 'S'
13713 && (out_attr[i].i == 'A' || out_attr[i].i == 'R')))
6a631e86 13714 ; /* Do nothing. */
91e22acd
AS		 13715 else
13716 {
13717 _bfd_error_handler
3895f852 13718 (_("error: %B: Conflicting architecture profiles %c/%c"),
91e22acd
AS		 13719 ibfd,
13720 in_attr[i].i ? in_attr[i].i : '0',
13721 out_attr[i].i ? out_attr[i].i : '0');
13722 result = FALSE;
13723 }
13724 }
13725 break;
15afaa63
TP		 13726
13727 case Tag_DSP_extension:
13728 /* No need to change output value if any of:
13729 - pre (<=) ARMv5T input architecture (do not have DSP)
13730 - M input profile not ARMv7E-M and do not have DSP. */
13731 if (in_attr[Tag_CPU_arch].i <= 3
13732 || (in_attr[Tag_CPU_arch_profile].i == 'M'
13733 && in_attr[Tag_CPU_arch].i != 13
13734 && in_attr[i].i == 0))
13735 ; /* Do nothing. */
13736 /* Output value should be 0 if DSP part of architecture, ie.
13737 - post (>=) ARMv5te architecture output
13738 - A, R or S profile output or ARMv7E-M output architecture. */
13739 else if (out_attr[Tag_CPU_arch].i >= 4
13740 && (out_attr[Tag_CPU_arch_profile].i == 'A'
13741 || out_attr[Tag_CPU_arch_profile].i == 'R'
13742 || out_attr[Tag_CPU_arch_profile].i == 'S'
13743 || out_attr[Tag_CPU_arch].i == 13))
13744 out_attr[i].i = 0;
13745 /* Otherwise, DSP instructions are added and not part of output
13746 architecture. */
13747 else
13748 out_attr[i].i = 1;
13749 break;
13750
75375b3e 13751 case Tag_FP_arch:
62f3b8c8 13752 {
4547cb56
NC		 13753 /* Tag_ABI_HardFP_use is handled along with Tag_FP_arch since
13754 the meaning of Tag_ABI_HardFP_use depends on Tag_FP_arch
13755 when it's 0. It might mean absence of FP hardware if
99654aaf 13756 Tag_FP_arch is zero. */
4547cb56 13757
a715796b 13758#define VFP_VERSION_COUNT 9
62f3b8c8
PB		 13759 static const struct
13760 {
13761 int ver;
13762 int regs;
bca38921 13763 } vfp_versions[VFP_VERSION_COUNT] =
62f3b8c8
PB		 13764 {
13765 {0, 0},
13766 {1, 16},
13767 {2, 16},
13768 {3, 32},
13769 {3, 16},
13770 {4, 32},
bca38921 13771 {4, 16},
a715796b
TG		 13772 {8, 32},
13773 {8, 16}
62f3b8c8
PB		 13774 };
13775 int ver;
13776 int regs;
13777 int newval;
13778
4547cb56
NC		 13779 /* If the output has no requirement about FP hardware,
13780 follow the requirement of the input. */
13781 if (out_attr[i].i == 0)
13782 {
13783 BFD_ASSERT (out_attr[Tag_ABI_HardFP_use].i == 0);
13784 out_attr[i].i = in_attr[i].i;
13785 out_attr[Tag_ABI_HardFP_use].i
13786 = in_attr[Tag_ABI_HardFP_use].i;
13787 break;
13788 }
13789 /* If the input has no requirement about FP hardware, do
13790 nothing. */
13791 else if (in_attr[i].i == 0)
13792 {
13793 BFD_ASSERT (in_attr[Tag_ABI_HardFP_use].i == 0);
13794 break;
13795 }
13796
13797 /* Both the input and the output have nonzero Tag_FP_arch.
99654aaf 13798 So Tag_ABI_HardFP_use is implied by Tag_FP_arch when it's zero. */
4547cb56
NC		 13799
13800 /* If both the input and the output have zero Tag_ABI_HardFP_use,
13801 do nothing. */
13802 if (in_attr[Tag_ABI_HardFP_use].i == 0
13803 && out_attr[Tag_ABI_HardFP_use].i == 0)
13804 ;
13805 /* If the input and the output have different Tag_ABI_HardFP_use,
99654aaf 13806 the combination of them is 0 (implied by Tag_FP_arch). */
4547cb56
NC		 13807 else if (in_attr[Tag_ABI_HardFP_use].i
13808 != out_attr[Tag_ABI_HardFP_use].i)
99654aaf 13809 out_attr[Tag_ABI_HardFP_use].i = 0;
4547cb56
NC		 13810
13811 /* Now we can handle Tag_FP_arch. */
13812
bca38921
MGD		 13813 /* Values of VFP_VERSION_COUNT or more aren't defined, so just
13814 pick the biggest. */
13815 if (in_attr[i].i >= VFP_VERSION_COUNT
13816 && in_attr[i].i > out_attr[i].i)
62f3b8c8
PB		 13817 {
13818 out_attr[i] = in_attr[i];
13819 break;
13820 }
13821 /* The output uses the superset of input features
13822 (ISA version) and registers. */
13823 ver = vfp_versions[in_attr[i].i].ver;
13824 if (ver < vfp_versions[out_attr[i].i].ver)
13825 ver = vfp_versions[out_attr[i].i].ver;
13826 regs = vfp_versions[in_attr[i].i].regs;
13827 if (regs < vfp_versions[out_attr[i].i].regs)
13828 regs = vfp_versions[out_attr[i].i].regs;
13829 /* This assumes all possible supersets are also a valid
99059e56 13830 options. */
bca38921 13831 for (newval = VFP_VERSION_COUNT - 1; newval > 0; newval--)
62f3b8c8
PB		 13832 {
13833 if (regs == vfp_versions[newval].regs
13834 && ver == vfp_versions[newval].ver)
13835 break;
13836 }
13837 out_attr[i].i = newval;
13838 }
b1cc4aeb 13839 break;
ee065d83
PB		 13840 case Tag_PCS_config:
13841 if (out_attr[i].i == 0)
13842 out_attr[i].i = in_attr[i].i;
b6009aca 13843 else if (in_attr[i].i != 0 && out_attr[i].i != in_attr[i].i)
ee065d83
PB		 13844 {
13845 /* It's sometimes ok to mix different configs, so this is only
99059e56 13846 a warning. */
ee065d83
PB		 13847 _bfd_error_handler
13848 (_("Warning: %B: Conflicting platform configuration"), ibfd);
13849 }
13850 break;
13851 case Tag_ABI_PCS_R9_use:
004ae526
PB		 13852 if (in_attr[i].i != out_attr[i].i
13853 && out_attr[i].i != AEABI_R9_unused
ee065d83
PB		 13854 && in_attr[i].i != AEABI_R9_unused)
13855 {
13856 _bfd_error_handler
3895f852 13857 (_("error: %B: Conflicting use of R9"), ibfd);
91e22acd 13858 result = FALSE;
ee065d83
PB		 13859 }
13860 if (out_attr[i].i == AEABI_R9_unused)
13861 out_attr[i].i = in_attr[i].i;
13862 break;
13863 case Tag_ABI_PCS_RW_data:
13864 if (in_attr[i].i == AEABI_PCS_RW_data_SBrel
13865 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_SB
13866 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_unused)
13867 {
13868 _bfd_error_handler
3895f852 13869 (_("error: %B: SB relative addressing conflicts with use of R9"),
ee065d83 13870 ibfd);
91e22acd 13871 result = FALSE;
ee065d83
PB		 13872 }
13873 /* Use the smallest value specified. */
13874 if (in_attr[i].i < out_attr[i].i)
13875 out_attr[i].i = in_attr[i].i;
13876 break;
ee065d83 13877 case Tag_ABI_PCS_wchar_t:
a9dc9481
JM		 13878 if (out_attr[i].i && in_attr[i].i && out_attr[i].i != in_attr[i].i
13879 && !elf_arm_tdata (obfd)->no_wchar_size_warning)
ee065d83
PB		 13880 {
13881 _bfd_error_handler
a9dc9481
JM		 13882 (_("warning: %B uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"),
13883 ibfd, in_attr[i].i, out_attr[i].i);
ee065d83 13884 }
a9dc9481 13885 else if (in_attr[i].i && !out_attr[i].i)
ee065d83
PB		 13886 out_attr[i].i = in_attr[i].i;
13887 break;
ee065d83
PB		 13888 case Tag_ABI_enum_size:
13889 if (in_attr[i].i != AEABI_enum_unused)
13890 {
13891 if (out_attr[i].i == AEABI_enum_unused
13892 || out_attr[i].i == AEABI_enum_forced_wide)
13893 {
13894 /* The existing object is compatible with anything.
13895 Use whatever requirements the new object has. */
13896 out_attr[i].i = in_attr[i].i;
13897 }
13898 else if (in_attr[i].i != AEABI_enum_forced_wide
bf21ed78 13899 && out_attr[i].i != in_attr[i].i
0ffa91dd 13900 && !elf_arm_tdata (obfd)->no_enum_size_warning)
ee065d83 13901 {
91e22acd 13902 static const char *aeabi_enum_names[] =
bf21ed78 13903 { "", "variable-size", "32-bit", "" };
91e22acd
AS		 13904 const char *in_name =
13905 in_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
13906 ? aeabi_enum_names[in_attr[i].i]
13907 : "<unknown>";
13908 const char *out_name =
13909 out_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
13910 ? aeabi_enum_names[out_attr[i].i]
13911 : "<unknown>";
ee065d83 13912 _bfd_error_handler
bf21ed78 13913 (_("warning: %B uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"),
91e22acd 13914 ibfd, in_name, out_name);
ee065d83
PB		 13915 }
13916 }
13917 break;
13918 case Tag_ABI_VFP_args:
13919 /* Aready done. */
13920 break;
13921 case Tag_ABI_WMMX_args:
13922 if (in_attr[i].i != out_attr[i].i)
13923 {
13924 _bfd_error_handler
3895f852 13925 (_("error: %B uses iWMMXt register arguments, %B does not"),
ee065d83 13926 ibfd, obfd);
91e22acd 13927 result = FALSE;
ee065d83
PB		 13928 }
13929 break;
7b86a9fa
AS		 13930 case Tag_compatibility:
13931 /* Merged in target-independent code. */
13932 break;
91e22acd 13933 case Tag_ABI_HardFP_use:
4547cb56 13934 /* This is handled along with Tag_FP_arch. */
91e22acd
AS		 13935 break;
13936 case Tag_ABI_FP_16bit_format:
13937 if (in_attr[i].i != 0 && out_attr[i].i != 0)
13938 {
13939 if (in_attr[i].i != out_attr[i].i)
13940 {
13941 _bfd_error_handler
3895f852 13942 (_("error: fp16 format mismatch between %B and %B"),
91e22acd
AS		 13943 ibfd, obfd);
13944 result = FALSE;
13945 }
13946 }
13947 if (in_attr[i].i != 0)
13948 out_attr[i].i = in_attr[i].i;
13949 break;
7b86a9fa 13950
cd21e546 13951 case Tag_DIV_use:
ac56ee8f
MGD		 13952 /* A value of zero on input means that the divide instruction may
13953 be used if available in the base architecture as specified via
13954 Tag_CPU_arch and Tag_CPU_arch_profile. A value of 1 means that
13955 the user did not want divide instructions. A value of 2
13956 explicitly means that divide instructions were allowed in ARM
13957 and Thumb state. */
13958 if (in_attr[i].i == out_attr[i].i)
13959 /* Do nothing. */ ;
13960 else if (elf32_arm_attributes_forbid_div (in_attr)
13961 && !elf32_arm_attributes_accept_div (out_attr))
13962 out_attr[i].i = 1;
13963 else if (elf32_arm_attributes_forbid_div (out_attr)
13964 && elf32_arm_attributes_accept_div (in_attr))
13965 out_attr[i].i = in_attr[i].i;
13966 else if (in_attr[i].i == 2)
13967 out_attr[i].i = in_attr[i].i;
cd21e546
MGD		 13968 break;
13969
13970 case Tag_MPextension_use_legacy:
13971 /* We don't output objects with Tag_MPextension_use_legacy - we
13972 move the value to Tag_MPextension_use. */
13973 if (in_attr[i].i != 0 && in_attr[Tag_MPextension_use].i != 0)
13974 {
13975 if (in_attr[Tag_MPextension_use].i != in_attr[i].i)
13976 {
13977 _bfd_error_handler
13978 (_("%B has has both the current and legacy "
b38cadfb 13979 "Tag_MPextension_use attributes"),
cd21e546
MGD		 13980 ibfd);
13981 result = FALSE;
13982 }
13983 }
13984
13985 if (in_attr[i].i > out_attr[Tag_MPextension_use].i)
13986 out_attr[Tag_MPextension_use] = in_attr[i];
13987
13988 break;
13989
91e22acd 13990 case Tag_nodefaults:
2d0bb761
AS		 13991 /* This tag is set if it exists, but the value is unused (and is
13992 typically zero). We don't actually need to do anything here -
13993 the merge happens automatically when the type flags are merged
13994 below. */
91e22acd
AS		 13995 break;
13996 case Tag_also_compatible_with:
13997 /* Already done in Tag_CPU_arch. */
13998 break;
13999 case Tag_conformance:
14000 /* Keep the attribute if it matches. Throw it away otherwise.
14001 No attribute means no claim to conform. */
14002 if (!in_attr[i].s || !out_attr[i].s
14003 || strcmp (in_attr[i].s, out_attr[i].s) != 0)
14004 out_attr[i].s = NULL;
14005 break;
3cfad14c 14006
91e22acd 14007 default:
e8b36cd1
JM		 14008 result
14009 = result && _bfd_elf_merge_unknown_attribute_low (ibfd, obfd, i);
91e22acd
AS		 14010 }
14011
14012 /* If out_attr was copied from in_attr then it won't have a type yet. */
14013 if (in_attr[i].type && !out_attr[i].type)
14014 out_attr[i].type = in_attr[i].type;
ee065d83
PB		 14015 }
14016
104d59d1 14017 /* Merge Tag_compatibility attributes and any common GNU ones. */
5488d830
MGD		 14018 if (!_bfd_elf_merge_object_attributes (ibfd, obfd))
14019 return FALSE;
ee065d83 14020
104d59d1 14021 /* Check for any attributes not known on ARM. */
e8b36cd1 14022 result &= _bfd_elf_merge_unknown_attribute_list (ibfd, obfd);
91e22acd 14023
91e22acd 14024 return result;
252b5132
RH		 14025}
14026
3a4a14e9
PB		 14027
14028/* Return TRUE if the two EABI versions are incompatible. */
14029
14030static bfd_boolean
14031elf32_arm_versions_compatible (unsigned iver, unsigned over)
14032{
14033 /* v4 and v5 are the same spec before and after it was released,
14034 so allow mixing them. */
14035 if ((iver == EF_ARM_EABI_VER4 && over == EF_ARM_EABI_VER5)
14036 || (iver == EF_ARM_EABI_VER5 && over == EF_ARM_EABI_VER4))
14037 return TRUE;
14038
14039 return (iver == over);
14040}
14041
252b5132
RH		 14042/* Merge backend specific data from an object file to the output
14043 object file when linking. */
9b485d32 14044
b34976b6 14045static bfd_boolean
21d799b5 14046elf32_arm_merge_private_bfd_data (bfd * ibfd, bfd * obfd);
252b5132 14047
9b485d32
NC		 14048/* Display the flags field. */
14049
b34976b6 14050static bfd_boolean
57e8b36a 14051elf32_arm_print_private_bfd_data (bfd *abfd, void * ptr)
252b5132 14052{
fc830a83
NC		 14053 FILE * file = (FILE *) ptr;
14054 unsigned long flags;
252b5132
RH		 14055
14056 BFD_ASSERT (abfd != NULL && ptr != NULL);
14057
14058 /* Print normal ELF private data. */
14059 _bfd_elf_print_private_bfd_data (abfd, ptr);
14060
fc830a83 14061 flags = elf_elfheader (abfd)->e_flags;
9b485d32
NC		 14062 /* Ignore init flag - it may not be set, despite the flags field
14063 containing valid data. */
252b5132
RH		 14064
14065 /* xgettext:c-format */
9b485d32 14066 fprintf (file, _("private flags = %lx:"), elf_elfheader (abfd)->e_flags);
252b5132 14067
fc830a83
NC		 14068 switch (EF_ARM_EABI_VERSION (flags))
14069 {
14070 case EF_ARM_EABI_UNKNOWN:
4cc11e76 14071 /* The following flag bits are GNU extensions and not part of the
fc830a83
NC		 14072 official ARM ELF extended ABI. Hence they are only decoded if
14073 the EABI version is not set. */
fd2ec330 14074 if (flags & EF_ARM_INTERWORK)
9b485d32 14075 fprintf (file, _(" [interworking enabled]"));
9a5aca8c 14076
fd2ec330 14077 if (flags & EF_ARM_APCS_26)
6c571f00 14078 fprintf (file, " [APCS-26]");
fc830a83 14079 else
6c571f00 14080 fprintf (file, " [APCS-32]");
9a5aca8c 14081
96a846ea
RE		 14082 if (flags & EF_ARM_VFP_FLOAT)
14083 fprintf (file, _(" [VFP float format]"));
fde78edd
NC		 14084 else if (flags & EF_ARM_MAVERICK_FLOAT)
14085 fprintf (file, _(" [Maverick float format]"));
96a846ea
RE		 14086 else
14087 fprintf (file, _(" [FPA float format]"));
14088
fd2ec330 14089 if (flags & EF_ARM_APCS_FLOAT)
9b485d32 14090 fprintf (file, _(" [floats passed in float registers]"));
9a5aca8c 14091
fd2ec330 14092 if (flags & EF_ARM_PIC)
9b485d32 14093 fprintf (file, _(" [position independent]"));
fc830a83 14094
fd2ec330 14095 if (flags & EF_ARM_NEW_ABI)
9b485d32 14096 fprintf (file, _(" [new ABI]"));
9a5aca8c 14097
fd2ec330 14098 if (flags & EF_ARM_OLD_ABI)
9b485d32 14099 fprintf (file, _(" [old ABI]"));
9a5aca8c 14100
fd2ec330 14101 if (flags & EF_ARM_SOFT_FLOAT)
9b485d32 14102 fprintf (file, _(" [software FP]"));
9a5aca8c 14103
96a846ea
RE		 14104 flags &= ~(EF_ARM_INTERWORK | EF_ARM_APCS_26 | EF_ARM_APCS_FLOAT
14105 | EF_ARM_PIC | EF_ARM_NEW_ABI | EF_ARM_OLD_ABI
fde78edd
NC		 14106 | EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT
14107 | EF_ARM_MAVERICK_FLOAT);
fc830a83 14108 break;
9a5aca8c 14109
fc830a83 14110 case EF_ARM_EABI_VER1:
9b485d32 14111 fprintf (file, _(" [Version1 EABI]"));
9a5aca8c 14112
fc830a83 14113 if (flags & EF_ARM_SYMSARESORTED)
9b485d32 14114 fprintf (file, _(" [sorted symbol table]"));
fc830a83 14115 else
9b485d32 14116 fprintf (file, _(" [unsorted symbol table]"));
9a5aca8c 14117
fc830a83
NC		 14118 flags &= ~ EF_ARM_SYMSARESORTED;
14119 break;
9a5aca8c 14120
fd2ec330
PB		 14121 case EF_ARM_EABI_VER2:
14122 fprintf (file, _(" [Version2 EABI]"));
14123
14124 if (flags & EF_ARM_SYMSARESORTED)
14125 fprintf (file, _(" [sorted symbol table]"));
14126 else
14127 fprintf (file, _(" [unsorted symbol table]"));
14128
14129 if (flags & EF_ARM_DYNSYMSUSESEGIDX)
14130 fprintf (file, _(" [dynamic symbols use segment index]"));
14131
14132 if (flags & EF_ARM_MAPSYMSFIRST)
14133 fprintf (file, _(" [mapping symbols precede others]"));
14134
99e4ae17 14135 flags &= ~(EF_ARM_SYMSARESORTED | EF_ARM_DYNSYMSUSESEGIDX
fd2ec330
PB		 14136 | EF_ARM_MAPSYMSFIRST);
14137 break;
14138
d507cf36
PB		 14139 case EF_ARM_EABI_VER3:
14140 fprintf (file, _(" [Version3 EABI]"));
8cb51566
PB		 14141 break;
14142
14143 case EF_ARM_EABI_VER4:
14144 fprintf (file, _(" [Version4 EABI]"));
3a4a14e9 14145 goto eabi;
d507cf36 14146
3a4a14e9
PB		 14147 case EF_ARM_EABI_VER5:
14148 fprintf (file, _(" [Version5 EABI]"));
3bfcb652
NC		 14149
14150 if (flags & EF_ARM_ABI_FLOAT_SOFT)
14151 fprintf (file, _(" [soft-float ABI]"));
14152
14153 if (flags & EF_ARM_ABI_FLOAT_HARD)
14154 fprintf (file, _(" [hard-float ABI]"));
14155
14156 flags &= ~(EF_ARM_ABI_FLOAT_SOFT | EF_ARM_ABI_FLOAT_HARD);
14157
3a4a14e9 14158 eabi:
d507cf36
PB		 14159 if (flags & EF_ARM_BE8)
14160 fprintf (file, _(" [BE8]"));
14161
14162 if (flags & EF_ARM_LE8)
14163 fprintf (file, _(" [LE8]"));
14164
14165 flags &= ~(EF_ARM_LE8 | EF_ARM_BE8);
14166 break;
14167
fc830a83 14168 default:
9b485d32 14169 fprintf (file, _(" <EABI version unrecognised>"));
fc830a83
NC		 14170 break;
14171 }
252b5132 14172
fc830a83 14173 flags &= ~ EF_ARM_EABIMASK;
252b5132 14174
fc830a83 14175 if (flags & EF_ARM_RELEXEC)
9b485d32 14176 fprintf (file, _(" [relocatable executable]"));
252b5132 14177
a5721edd 14178 flags &= ~EF_ARM_RELEXEC;
fc830a83
NC		 14179
14180 if (flags)
9b485d32 14181 fprintf (file, _("<Unrecognised flag bits set>"));
9a5aca8c 14182
252b5132
RH		 14183 fputc ('\n', file);
14184
b34976b6 14185 return TRUE;
252b5132
RH		 14186}
14187
14188static int
57e8b36a 14189elf32_arm_get_symbol_type (Elf_Internal_Sym * elf_sym, int type)
252b5132 14190{
2f0ca46a
NC		 14191 switch (ELF_ST_TYPE (elf_sym->st_info))
14192 {
14193 case STT_ARM_TFUNC:
14194 return ELF_ST_TYPE (elf_sym->st_info);
ce855c42 14195
2f0ca46a
NC		 14196 case STT_ARM_16BIT:
14197 /* If the symbol is not an object, return the STT_ARM_16BIT flag.
14198 This allows us to distinguish between data used by Thumb instructions
14199 and non-data (which is probably code) inside Thumb regions of an
14200 executable. */
1a0eb693 14201 if (type != STT_OBJECT && type != STT_TLS)
2f0ca46a
NC		 14202 return ELF_ST_TYPE (elf_sym->st_info);
14203 break;
9a5aca8c 14204
ce855c42
NC		 14205 default:
14206 break;
2f0ca46a
NC		 14207 }
14208
14209 return type;
252b5132 14210}
f21f3fe0 14211
252b5132 14212static asection *
07adf181
AM		 14213elf32_arm_gc_mark_hook (asection *sec,
14214 struct bfd_link_info *info,
14215 Elf_Internal_Rela *rel,
14216 struct elf_link_hash_entry *h,
14217 Elf_Internal_Sym *sym)
252b5132
RH		 14218{
14219 if (h != NULL)
07adf181 14220 switch (ELF32_R_TYPE (rel->r_info))
252b5132
RH		 14221 {
14222 case R_ARM_GNU_VTINHERIT:
14223 case R_ARM_GNU_VTENTRY:
07adf181
AM		 14224 return NULL;
14225 }
9ad5cbcf 14226
07adf181 14227 return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym);
252b5132
RH		 14228}
14229
780a67af
NC		 14230/* Update the got entry reference counts for the section being removed. */
14231
b34976b6 14232static bfd_boolean
ba93b8ac
DJ		 14233elf32_arm_gc_sweep_hook (bfd * abfd,
14234 struct bfd_link_info * info,
14235 asection * sec,
14236 const Elf_Internal_Rela * relocs)
252b5132 14237{
5e681ec4
PB		 14238 Elf_Internal_Shdr *symtab_hdr;
14239 struct elf_link_hash_entry **sym_hashes;
14240 bfd_signed_vma *local_got_refcounts;
14241 const Elf_Internal_Rela *rel, *relend;
eb043451
PB		 14242 struct elf32_arm_link_hash_table * globals;
14243
0e1862bb 14244 if (bfd_link_relocatable (info))
7dda2462
TG		 14245 return TRUE;
14246
eb043451 14247 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14248 if (globals == NULL)
14249 return FALSE;
5e681ec4
PB		 14250
14251 elf_section_data (sec)->local_dynrel = NULL;
14252
0ffa91dd 14253 symtab_hdr = & elf_symtab_hdr (abfd);
5e681ec4
PB		 14254 sym_hashes = elf_sym_hashes (abfd);
14255 local_got_refcounts = elf_local_got_refcounts (abfd);
14256
906e58ca 14257 check_use_blx (globals);
bd97cb95 14258
5e681ec4
PB		 14259 relend = relocs + sec->reloc_count;
14260 for (rel = relocs; rel < relend; rel++)
eb043451 14261 {
3eb128b2
AM		 14262 unsigned long r_symndx;
14263 struct elf_link_hash_entry *h = NULL;
f6e32f6d 14264 struct elf32_arm_link_hash_entry *eh;
eb043451 14265 int r_type;
34e77a92 14266 bfd_boolean call_reloc_p;
f6e32f6d
RS		 14267 bfd_boolean may_become_dynamic_p;
14268 bfd_boolean may_need_local_target_p;
34e77a92
RS		 14269 union gotplt_union *root_plt;
14270 struct arm_plt_info *arm_plt;
5e681ec4 14271
3eb128b2
AM		 14272 r_symndx = ELF32_R_SYM (rel->r_info);
14273 if (r_symndx >= symtab_hdr->sh_info)
14274 {
14275 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
14276 while (h->root.type == bfd_link_hash_indirect
14277 || h->root.type == bfd_link_hash_warning)
14278 h = (struct elf_link_hash_entry *) h->root.u.i.link;
14279 }
f6e32f6d
RS		 14280 eh = (struct elf32_arm_link_hash_entry *) h;
14281
34e77a92 14282 call_reloc_p = FALSE;
f6e32f6d
RS		 14283 may_become_dynamic_p = FALSE;
14284 may_need_local_target_p = FALSE;
3eb128b2 14285
eb043451 14286 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 14287 r_type = arm_real_reloc_type (globals, r_type);
eb043451
PB		 14288 switch (r_type)
14289 {
14290 case R_ARM_GOT32:
eb043451 14291 case R_ARM_GOT_PREL:
ba93b8ac
DJ		 14292 case R_ARM_TLS_GD32:
14293 case R_ARM_TLS_IE32:
3eb128b2 14294 if (h != NULL)
eb043451 14295 {
eb043451
PB		 14296 if (h->got.refcount > 0)
14297 h->got.refcount -= 1;
14298 }
14299 else if (local_got_refcounts != NULL)
14300 {
14301 if (local_got_refcounts[r_symndx] > 0)
14302 local_got_refcounts[r_symndx] -= 1;
14303 }
14304 break;
14305
ba93b8ac 14306 case R_ARM_TLS_LDM32:
4dfe6ac6 14307 globals->tls_ldm_got.refcount -= 1;
ba93b8ac
DJ		 14308 break;
14309
eb043451
PB		 14310 case R_ARM_PC24:
14311 case R_ARM_PLT32:
5b5bb741
PB		 14312 case R_ARM_CALL:
14313 case R_ARM_JUMP24:
eb043451 14314 case R_ARM_PREL31:
c19d1205 14315 case R_ARM_THM_CALL:
bd97cb95
DJ		 14316 case R_ARM_THM_JUMP24:
14317 case R_ARM_THM_JUMP19:
34e77a92 14318 call_reloc_p = TRUE;
f6e32f6d
RS		 14319 may_need_local_target_p = TRUE;
14320 break;
14321
14322 case R_ARM_ABS12:
14323 if (!globals->vxworks_p)
14324 {
14325 may_need_local_target_p = TRUE;
14326 break;
14327 }
14328 /* Fall through. */
14329 case R_ARM_ABS32:
14330 case R_ARM_ABS32_NOI:
14331 case R_ARM_REL32:
14332 case R_ARM_REL32_NOI:
b6895b4f
PB		 14333 case R_ARM_MOVW_ABS_NC:
14334 case R_ARM_MOVT_ABS:
14335 case R_ARM_MOVW_PREL_NC:
14336 case R_ARM_MOVT_PREL:
14337 case R_ARM_THM_MOVW_ABS_NC:
14338 case R_ARM_THM_MOVT_ABS:
14339 case R_ARM_THM_MOVW_PREL_NC:
14340 case R_ARM_THM_MOVT_PREL:
b7693d02 14341 /* Should the interworking branches be here also? */
0e1862bb 14342 if ((bfd_link_pic (info) || globals->root.is_relocatable_executable)
34e77a92
RS		 14343 && (sec->flags & SEC_ALLOC) != 0)
14344 {
14345 if (h == NULL
469a3493 14346 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 14347 {
14348 call_reloc_p = TRUE;
14349 may_need_local_target_p = TRUE;
14350 }
14351 else
14352 may_become_dynamic_p = TRUE;
14353 }
f6e32f6d
RS		 14354 else
14355 may_need_local_target_p = TRUE;
14356 break;
b7693d02 14357
f6e32f6d
RS		 14358 default:
14359 break;
14360 }
5e681ec4 14361
34e77a92 14362 if (may_need_local_target_p
4ba2ef8f
TP		 14363 && elf32_arm_get_plt_info (abfd, globals, eh, r_symndx, &root_plt,
14364 &arm_plt))
f6e32f6d 14365 {
27586251
HPN		 14366 /* If PLT refcount book-keeping is wrong and too low, we'll
14367 see a zero value (going to -1) for the root PLT reference
14368 count. */
14369 if (root_plt->refcount >= 0)
14370 {
14371 BFD_ASSERT (root_plt->refcount != 0);
14372 root_plt->refcount -= 1;
14373 }
14374 else
14375 /* A value of -1 means the symbol has become local, forced
14376 or seeing a hidden definition. Any other negative value
14377 is an error. */
14378 BFD_ASSERT (root_plt->refcount == -1);
34e77a92
RS		 14379
14380 if (!call_reloc_p)
14381 arm_plt->noncall_refcount--;
5e681ec4 14382
f6e32f6d 14383 if (r_type == R_ARM_THM_CALL)
34e77a92 14384 arm_plt->maybe_thumb_refcount--;
bd97cb95 14385
f6e32f6d
RS		 14386 if (r_type == R_ARM_THM_JUMP24
14387 || r_type == R_ARM_THM_JUMP19)
34e77a92 14388 arm_plt->thumb_refcount--;
f6e32f6d 14389 }
5e681ec4 14390
34e77a92 14391 if (may_become_dynamic_p)
f6e32f6d
RS		 14392 {
14393 struct elf_dyn_relocs **pp;
14394 struct elf_dyn_relocs *p;
5e681ec4 14395
34e77a92 14396 if (h != NULL)
9c489990 14397 pp = &(eh->dyn_relocs);
34e77a92
RS		 14398 else
14399 {
14400 Elf_Internal_Sym *isym;
14401
14402 isym = bfd_sym_from_r_symndx (&globals->sym_cache,
14403 abfd, r_symndx);
14404 if (isym == NULL)
14405 return FALSE;
14406 pp = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
14407 if (pp == NULL)
14408 return FALSE;
14409 }
9c489990 14410 for (; (p = *pp) != NULL; pp = &p->next)
f6e32f6d
RS		 14411 if (p->sec == sec)
14412 {
14413 /* Everything must go for SEC. */
14414 *pp = p->next;
14415 break;
14416 }
eb043451
PB		 14417 }
14418 }
5e681ec4 14419
b34976b6 14420 return TRUE;
252b5132
RH		 14421}
14422
780a67af
NC		 14423/* Look through the relocs for a section during the first phase. */
14424
b34976b6 14425static bfd_boolean
57e8b36a
NC		 14426elf32_arm_check_relocs (bfd *abfd, struct bfd_link_info *info,
14427 asection *sec, const Elf_Internal_Rela *relocs)
252b5132 14428{
b34976b6
AM		 14429 Elf_Internal_Shdr *symtab_hdr;
14430 struct elf_link_hash_entry **sym_hashes;
b34976b6
AM		 14431 const Elf_Internal_Rela *rel;
14432 const Elf_Internal_Rela *rel_end;
14433 bfd *dynobj;
5e681ec4 14434 asection *sreloc;
5e681ec4 14435 struct elf32_arm_link_hash_table *htab;
f6e32f6d
RS		 14436 bfd_boolean call_reloc_p;
14437 bfd_boolean may_become_dynamic_p;
14438 bfd_boolean may_need_local_target_p;
ce98a316 14439 unsigned long nsyms;
9a5aca8c 14440
0e1862bb 14441 if (bfd_link_relocatable (info))
b34976b6 14442 return TRUE;
9a5aca8c 14443
0ffa91dd
NC		 14444 BFD_ASSERT (is_arm_elf (abfd));
14445
5e681ec4 14446 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14447 if (htab == NULL)
14448 return FALSE;
14449
5e681ec4 14450 sreloc = NULL;
9a5aca8c 14451
67687978
PB		 14452 /* Create dynamic sections for relocatable executables so that we can
14453 copy relocations. */
14454 if (htab->root.is_relocatable_executable
14455 && ! htab->root.dynamic_sections_created)
14456 {
14457 if (! _bfd_elf_link_create_dynamic_sections (abfd, info))
14458 return FALSE;
14459 }
14460
cbc704f3
RS		 14461 if (htab->root.dynobj == NULL)
14462 htab->root.dynobj = abfd;
34e77a92
RS		 14463 if (!create_ifunc_sections (info))
14464 return FALSE;
cbc704f3
RS		 14465
14466 dynobj = htab->root.dynobj;
14467
0ffa91dd 14468 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 14469 sym_hashes = elf_sym_hashes (abfd);
ce98a316 14470 nsyms = NUM_SHDR_ENTRIES (symtab_hdr);
b38cadfb 14471
252b5132
RH		 14472 rel_end = relocs + sec->reloc_count;
14473 for (rel = relocs; rel < rel_end; rel++)
14474 {
34e77a92 14475 Elf_Internal_Sym *isym;
252b5132 14476 struct elf_link_hash_entry *h;
b7693d02 14477 struct elf32_arm_link_hash_entry *eh;
252b5132 14478 unsigned long r_symndx;
eb043451 14479 int r_type;
9a5aca8c 14480
252b5132 14481 r_symndx = ELF32_R_SYM (rel->r_info);
eb043451 14482 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 14483 r_type = arm_real_reloc_type (htab, r_type);
ba93b8ac 14484
ce98a316
NC		 14485 if (r_symndx >= nsyms
14486 /* PR 9934: It is possible to have relocations that do not
14487 refer to symbols, thus it is also possible to have an
14488 object file containing relocations but no symbol table. */
cf35638d 14489 && (r_symndx > STN_UNDEF || nsyms > 0))
ba93b8ac
DJ		 14490 {
14491 (*_bfd_error_handler) (_("%B: bad symbol index: %d"), abfd,
ce98a316 14492 r_symndx);
ba93b8ac
DJ		 14493 return FALSE;
14494 }
14495
34e77a92
RS		 14496 h = NULL;
14497 isym = NULL;
14498 if (nsyms > 0)
973a3492 14499 {
34e77a92
RS		 14500 if (r_symndx < symtab_hdr->sh_info)
14501 {
14502 /* A local symbol. */
14503 isym = bfd_sym_from_r_symndx (&htab->sym_cache,
14504 abfd, r_symndx);
14505 if (isym == NULL)
14506 return FALSE;
14507 }
14508 else
14509 {
14510 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
14511 while (h->root.type == bfd_link_hash_indirect
14512 || h->root.type == bfd_link_hash_warning)
14513 h = (struct elf_link_hash_entry *) h->root.u.i.link;
81fbe831
AM		 14514
14515 /* PR15323, ref flags aren't set for references in the
14516 same object. */
14517 h->root.non_ir_ref = 1;
34e77a92 14518 }
973a3492 14519 }
9a5aca8c 14520
b7693d02
DJ		 14521 eh = (struct elf32_arm_link_hash_entry *) h;
14522
f6e32f6d
RS		 14523 call_reloc_p = FALSE;
14524 may_become_dynamic_p = FALSE;
14525 may_need_local_target_p = FALSE;
14526
0855e32b
NS		 14527 /* Could be done earlier, if h were already available. */
14528 r_type = elf32_arm_tls_transition (info, r_type, h);
eb043451 14529 switch (r_type)
99059e56 14530 {
5e681ec4 14531 case R_ARM_GOT32:
eb043451 14532 case R_ARM_GOT_PREL:
ba93b8ac
DJ		 14533 case R_ARM_TLS_GD32:
14534 case R_ARM_TLS_IE32:
0855e32b
NS		 14535 case R_ARM_TLS_GOTDESC:
14536 case R_ARM_TLS_DESCSEQ:
14537 case R_ARM_THM_TLS_DESCSEQ:
14538 case R_ARM_TLS_CALL:
14539 case R_ARM_THM_TLS_CALL:
5e681ec4 14540 /* This symbol requires a global offset table entry. */
ba93b8ac
DJ		 14541 {
14542 int tls_type, old_tls_type;
5e681ec4 14543
ba93b8ac
DJ		 14544 switch (r_type)
14545 {
14546 case R_ARM_TLS_GD32: tls_type = GOT_TLS_GD; break;
b38cadfb 14547
ba93b8ac 14548 case R_ARM_TLS_IE32: tls_type = GOT_TLS_IE; break;
b38cadfb 14549
0855e32b
NS		 14550 case R_ARM_TLS_GOTDESC:
14551 case R_ARM_TLS_CALL: case R_ARM_THM_TLS_CALL:
14552 case R_ARM_TLS_DESCSEQ: case R_ARM_THM_TLS_DESCSEQ:
14553 tls_type = GOT_TLS_GDESC; break;
b38cadfb 14554
ba93b8ac
DJ		 14555 default: tls_type = GOT_NORMAL; break;
14556 }
252b5132 14557
0e1862bb 14558 if (!bfd_link_executable (info) && (tls_type & GOT_TLS_IE))
eea6dad2
KM		 14559 info->flags |= DF_STATIC_TLS;
14560
ba93b8ac
DJ		 14561 if (h != NULL)
14562 {
14563 h->got.refcount++;
14564 old_tls_type = elf32_arm_hash_entry (h)->tls_type;
14565 }
14566 else
14567 {
ba93b8ac 14568 /* This is a global offset table entry for a local symbol. */
34e77a92
RS		 14569 if (!elf32_arm_allocate_local_sym_info (abfd))
14570 return FALSE;
14571 elf_local_got_refcounts (abfd)[r_symndx] += 1;
ba93b8ac
DJ		 14572 old_tls_type = elf32_arm_local_got_tls_type (abfd) [r_symndx];
14573 }
14574
0855e32b 14575 /* If a variable is accessed with both tls methods, two
99059e56 14576 slots may be created. */
0855e32b
NS		 14577 if (GOT_TLS_GD_ANY_P (old_tls_type)
14578 && GOT_TLS_GD_ANY_P (tls_type))
14579 tls_type |= old_tls_type;
14580
14581 /* We will already have issued an error message if there
14582 is a TLS/non-TLS mismatch, based on the symbol
14583 type. So just combine any TLS types needed. */
ba93b8ac
DJ		 14584 if (old_tls_type != GOT_UNKNOWN && old_tls_type != GOT_NORMAL
14585 && tls_type != GOT_NORMAL)
14586 tls_type |= old_tls_type;
14587
0855e32b 14588 /* If the symbol is accessed in both IE and GDESC
99059e56
RM		 14589 method, we're able to relax. Turn off the GDESC flag,
14590 without messing up with any other kind of tls types
6a631e86 14591 that may be involved. */
0855e32b
NS		 14592 if ((tls_type & GOT_TLS_IE) && (tls_type & GOT_TLS_GDESC))
14593 tls_type &= ~GOT_TLS_GDESC;
14594
ba93b8ac
DJ		 14595 if (old_tls_type != tls_type)
14596 {
14597 if (h != NULL)
14598 elf32_arm_hash_entry (h)->tls_type = tls_type;
14599 else
14600 elf32_arm_local_got_tls_type (abfd) [r_symndx] = tls_type;
14601 }
14602 }
8029a119 14603 /* Fall through. */
ba93b8ac
DJ		 14604
14605 case R_ARM_TLS_LDM32:
14606 if (r_type == R_ARM_TLS_LDM32)
14607 htab->tls_ldm_got.refcount++;
8029a119 14608 /* Fall through. */
252b5132 14609
c19d1205 14610 case R_ARM_GOTOFF32:
5e681ec4 14611 case R_ARM_GOTPC:
cbc704f3
RS		 14612 if (htab->root.sgot == NULL
14613 && !create_got_section (htab->root.dynobj, info))
14614 return FALSE;
252b5132
RH		 14615 break;
14616
252b5132 14617 case R_ARM_PC24:
7359ea65 14618 case R_ARM_PLT32:
5b5bb741
PB		 14619 case R_ARM_CALL:
14620 case R_ARM_JUMP24:
eb043451 14621 case R_ARM_PREL31:
c19d1205 14622 case R_ARM_THM_CALL:
bd97cb95
DJ		 14623 case R_ARM_THM_JUMP24:
14624 case R_ARM_THM_JUMP19:
f6e32f6d
RS		 14625 call_reloc_p = TRUE;
14626 may_need_local_target_p = TRUE;
14627 break;
14628
14629 case R_ARM_ABS12:
14630 /* VxWorks uses dynamic R_ARM_ABS12 relocations for
14631 ldr __GOTT_INDEX__ offsets. */
14632 if (!htab->vxworks_p)
14633 {
14634 may_need_local_target_p = TRUE;
14635 break;
14636 }
aebf9be7
NC		 14637 else goto jump_over;
14638
f6e32f6d 14639 /* Fall through. */
39623e12 14640
96c23d59
JM		 14641 case R_ARM_MOVW_ABS_NC:
14642 case R_ARM_MOVT_ABS:
14643 case R_ARM_THM_MOVW_ABS_NC:
14644 case R_ARM_THM_MOVT_ABS:
0e1862bb 14645 if (bfd_link_pic (info))
96c23d59
JM		 14646 {
14647 (*_bfd_error_handler)
14648 (_("%B: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
14649 abfd, elf32_arm_howto_table_1[r_type].name,
14650 (h) ? h->root.root.string : "a local symbol");
14651 bfd_set_error (bfd_error_bad_value);
14652 return FALSE;
14653 }
14654
14655 /* Fall through. */
39623e12
PB		 14656 case R_ARM_ABS32:
14657 case R_ARM_ABS32_NOI:
aebf9be7 14658 jump_over:
0e1862bb 14659 if (h != NULL && bfd_link_executable (info))
97323ad1
WN		 14660 {
14661 h->pointer_equality_needed = 1;
14662 }
14663 /* Fall through. */
39623e12
PB		 14664 case R_ARM_REL32:
14665 case R_ARM_REL32_NOI:
b6895b4f
PB		 14666 case R_ARM_MOVW_PREL_NC:
14667 case R_ARM_MOVT_PREL:
b6895b4f
PB		 14668 case R_ARM_THM_MOVW_PREL_NC:
14669 case R_ARM_THM_MOVT_PREL:
39623e12 14670
b7693d02 14671 /* Should the interworking branches be listed here? */
0e1862bb 14672 if ((bfd_link_pic (info) || htab->root.is_relocatable_executable)
34e77a92
RS		 14673 && (sec->flags & SEC_ALLOC) != 0)
14674 {
14675 if (h == NULL
469a3493 14676 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 14677 {
14678 /* In shared libraries and relocatable executables,
14679 we treat local relative references as calls;
14680 see the related SYMBOL_CALLS_LOCAL code in
14681 allocate_dynrelocs. */
14682 call_reloc_p = TRUE;
14683 may_need_local_target_p = TRUE;
14684 }
14685 else
14686 /* We are creating a shared library or relocatable
14687 executable, and this is a reloc against a global symbol,
14688 or a non-PC-relative reloc against a local symbol.
14689 We may need to copy the reloc into the output. */
14690 may_become_dynamic_p = TRUE;
14691 }
f6e32f6d
RS		 14692 else
14693 may_need_local_target_p = TRUE;
252b5132
RH		 14694 break;
14695
99059e56
RM		 14696 /* This relocation describes the C++ object vtable hierarchy.
14697 Reconstruct it for later use during GC. */
14698 case R_ARM_GNU_VTINHERIT:
14699 if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset))
14700 return FALSE;
14701 break;
14702
14703 /* This relocation describes which C++ vtable entries are actually
14704 used. Record for later use during GC. */
14705 case R_ARM_GNU_VTENTRY:
14706 BFD_ASSERT (h != NULL);
14707 if (h != NULL
14708 && !bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_offset))
14709 return FALSE;
14710 break;
14711 }
f6e32f6d
RS		 14712
14713 if (h != NULL)
14714 {
14715 if (call_reloc_p)
14716 /* We may need a .plt entry if the function this reloc
14717 refers to is in a different object, regardless of the
14718 symbol's type. We can't tell for sure yet, because
14719 something later might force the symbol local. */
14720 h->needs_plt = 1;
14721 else if (may_need_local_target_p)
14722 /* If this reloc is in a read-only section, we might
14723 need a copy reloc. We can't check reliably at this
14724 stage whether the section is read-only, as input
14725 sections have not yet been mapped to output sections.
14726 Tentatively set the flag for now, and correct in
14727 adjust_dynamic_symbol. */
14728 h->non_got_ref = 1;
14729 }
14730
34e77a92
RS		 14731 if (may_need_local_target_p
14732 && (h != NULL || ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC))
f6e32f6d 14733 {
34e77a92
RS		 14734 union gotplt_union *root_plt;
14735 struct arm_plt_info *arm_plt;
14736 struct arm_local_iplt_info *local_iplt;
14737
14738 if (h != NULL)
14739 {
14740 root_plt = &h->plt;
14741 arm_plt = &eh->plt;
14742 }
14743 else
14744 {
14745 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
14746 if (local_iplt == NULL)
14747 return FALSE;
14748 root_plt = &local_iplt->root;
14749 arm_plt = &local_iplt->arm;
14750 }
14751
f6e32f6d
RS		 14752 /* If the symbol is a function that doesn't bind locally,
14753 this relocation will need a PLT entry. */
a8c887dd
NC		 14754 if (root_plt->refcount != -1)
14755 root_plt->refcount += 1;
34e77a92
RS		 14756
14757 if (!call_reloc_p)
14758 arm_plt->noncall_refcount++;
f6e32f6d
RS		 14759
14760 /* It's too early to use htab->use_blx here, so we have to
14761 record possible blx references separately from
14762 relocs that definitely need a thumb stub. */
14763
14764 if (r_type == R_ARM_THM_CALL)
34e77a92 14765 arm_plt->maybe_thumb_refcount += 1;
f6e32f6d
RS		 14766
14767 if (r_type == R_ARM_THM_JUMP24
14768 || r_type == R_ARM_THM_JUMP19)
34e77a92 14769 arm_plt->thumb_refcount += 1;
f6e32f6d
RS		 14770 }
14771
14772 if (may_become_dynamic_p)
14773 {
14774 struct elf_dyn_relocs *p, **head;
14775
14776 /* Create a reloc section in dynobj. */
14777 if (sreloc == NULL)
14778 {
14779 sreloc = _bfd_elf_make_dynamic_reloc_section
14780 (sec, dynobj, 2, abfd, ! htab->use_rel);
14781
14782 if (sreloc == NULL)
14783 return FALSE;
14784
14785 /* BPABI objects never have dynamic relocations mapped. */
14786 if (htab->symbian_p)
14787 {
14788 flagword flags;
14789
14790 flags = bfd_get_section_flags (dynobj, sreloc);
14791 flags &= ~(SEC_LOAD | SEC_ALLOC);
14792 bfd_set_section_flags (dynobj, sreloc, flags);
14793 }
14794 }
14795
14796 /* If this is a global symbol, count the number of
14797 relocations we need for this symbol. */
14798 if (h != NULL)
14799 head = &((struct elf32_arm_link_hash_entry *) h)->dyn_relocs;
14800 else
14801 {
34e77a92
RS		 14802 head = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
14803 if (head == NULL)
f6e32f6d 14804 return FALSE;
f6e32f6d
RS		 14805 }
14806
14807 p = *head;
14808 if (p == NULL || p->sec != sec)
14809 {
14810 bfd_size_type amt = sizeof *p;
14811
14812 p = (struct elf_dyn_relocs *) bfd_alloc (htab->root.dynobj, amt);
14813 if (p == NULL)
14814 return FALSE;
14815 p->next = *head;
14816 *head = p;
14817 p->sec = sec;
14818 p->count = 0;
14819 p->pc_count = 0;
14820 }
14821
469a3493 14822 if (elf32_arm_howto_from_type (r_type)->pc_relative)
f6e32f6d
RS		 14823 p->pc_count += 1;
14824 p->count += 1;
14825 }
252b5132 14826 }
f21f3fe0 14827
b34976b6 14828 return TRUE;
252b5132
RH		 14829}
14830
6a5bb875 14831/* Unwinding tables are not referenced directly. This pass marks them as
4ba2ef8f
TP		 14832 required if the corresponding code section is marked. Similarly, ARMv8-M
14833 secure entry functions can only be referenced by SG veneers which are
14834 created after the GC process. They need to be marked in case they reside in
14835 their own section (as would be the case if code was compiled with
14836 -ffunction-sections). */
6a5bb875
PB		 14837
14838static bfd_boolean
906e58ca
NC		 14839elf32_arm_gc_mark_extra_sections (struct bfd_link_info *info,
14840 elf_gc_mark_hook_fn gc_mark_hook)
6a5bb875
PB		 14841{
14842 bfd *sub;
14843 Elf_Internal_Shdr **elf_shdrp;
4ba2ef8f
TP		 14844 asection *cmse_sec;
14845 obj_attribute *out_attr;
14846 Elf_Internal_Shdr *symtab_hdr;
14847 unsigned i, sym_count, ext_start;
14848 const struct elf_backend_data *bed;
14849 struct elf_link_hash_entry **sym_hashes;
14850 struct elf32_arm_link_hash_entry *cmse_hash;
14851 bfd_boolean again, is_v8m, first_bfd_browse = TRUE;
6a5bb875 14852
7f6ab9f8
AM		 14853 _bfd_elf_gc_mark_extra_sections (info, gc_mark_hook);
14854
4ba2ef8f
TP		 14855 out_attr = elf_known_obj_attributes_proc (info->output_bfd);
14856 is_v8m = out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
14857 && out_attr[Tag_CPU_arch_profile].i == 'M';
14858
6a5bb875
PB		 14859 /* Marking EH data may cause additional code sections to be marked,
14860 requiring multiple passes. */
14861 again = TRUE;
14862 while (again)
14863 {
14864 again = FALSE;
c72f2fb2 14865 for (sub = info->input_bfds; sub != NULL; sub = sub->link.next)
6a5bb875
PB		 14866 {
14867 asection *o;
14868
0ffa91dd 14869 if (! is_arm_elf (sub))
6a5bb875
PB		 14870 continue;
14871
14872 elf_shdrp = elf_elfsections (sub);
14873 for (o = sub->sections; o != NULL; o = o->next)
14874 {
14875 Elf_Internal_Shdr *hdr;
0ffa91dd 14876
6a5bb875 14877 hdr = &elf_section_data (o)->this_hdr;
4fbb74a6
AM		 14878 if (hdr->sh_type == SHT_ARM_EXIDX
14879 && hdr->sh_link
14880 && hdr->sh_link < elf_numsections (sub)
6a5bb875
PB		 14881 && !o->gc_mark
14882 && elf_shdrp[hdr->sh_link]->bfd_section->gc_mark)
14883 {
14884 again = TRUE;
14885 if (!_bfd_elf_gc_mark (info, o, gc_mark_hook))
14886 return FALSE;
14887 }
14888 }
4ba2ef8f
TP		 14889
14890 /* Mark section holding ARMv8-M secure entry functions. We mark all
14891 of them so no need for a second browsing. */
14892 if (is_v8m && first_bfd_browse)
14893 {
14894 sym_hashes = elf_sym_hashes (sub);
14895 bed = get_elf_backend_data (sub);
14896 symtab_hdr = &elf_tdata (sub)->symtab_hdr;
14897 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
14898 ext_start = symtab_hdr->sh_info;
14899
14900 /* Scan symbols. */
14901 for (i = ext_start; i < sym_count; i++)
14902 {
14903 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
14904
14905 /* Assume it is a special symbol. If not, cmse_scan will
14906 warn about it and user can do something about it. */
14907 if (ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
14908 {
14909 cmse_sec = cmse_hash->root.root.u.def.section;
14910 if (!_bfd_elf_gc_mark (info, cmse_sec, gc_mark_hook))
14911 return FALSE;
14912 }
14913 }
14914 }
6a5bb875 14915 }
4ba2ef8f 14916 first_bfd_browse = FALSE;
6a5bb875
PB		 14917 }
14918
14919 return TRUE;
14920}
14921
3c9458e9
NC		 14922/* Treat mapping symbols as special target symbols. */
14923
14924static bfd_boolean
14925elf32_arm_is_target_special_symbol (bfd * abfd ATTRIBUTE_UNUSED, asymbol * sym)
14926{
b0796911
PB		 14927 return bfd_is_arm_special_symbol_name (sym->name,
14928 BFD_ARM_SPECIAL_SYM_TYPE_ANY);
3c9458e9
NC		 14929}
14930
0367ecfb
NC		 14931/* This is a copy of elf_find_function() from elf.c except that
14932 ARM mapping symbols are ignored when looking for function names
14933 and STT_ARM_TFUNC is considered to a function type. */
252b5132 14934
0367ecfb
NC		 14935static bfd_boolean
14936arm_elf_find_function (bfd * abfd ATTRIBUTE_UNUSED,
0367ecfb 14937 asymbol ** symbols,
fb167eb2 14938 asection * section,
0367ecfb
NC		 14939 bfd_vma offset,
14940 const char ** filename_ptr,
14941 const char ** functionname_ptr)
14942{
14943 const char * filename = NULL;
14944 asymbol * func = NULL;
14945 bfd_vma low_func = 0;
14946 asymbol ** p;
252b5132
RH		 14947
14948 for (p = symbols; *p != NULL; p++)
14949 {
14950 elf_symbol_type *q;
14951
14952 q = (elf_symbol_type *) *p;
14953
252b5132
RH		 14954 switch (ELF_ST_TYPE (q->internal_elf_sym.st_info))
14955 {
14956 default:
14957 break;
14958 case STT_FILE:
14959 filename = bfd_asymbol_name (&q->symbol);
14960 break;
252b5132
RH		 14961 case STT_FUNC:
14962 case STT_ARM_TFUNC:
9d2da7ca 14963 case STT_NOTYPE:
b0796911 14964 /* Skip mapping symbols. */
0367ecfb 14965 if ((q->symbol.flags & BSF_LOCAL)
b0796911
PB		 14966 && bfd_is_arm_special_symbol_name (q->symbol.name,
14967 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
0367ecfb
NC		 14968 continue;
14969 /* Fall through. */
6b40fcba 14970 if (bfd_get_section (&q->symbol) == section
252b5132
RH		 14971 && q->symbol.value >= low_func
14972 && q->symbol.value <= offset)
14973 {
14974 func = (asymbol *) q;
14975 low_func = q->symbol.value;
14976 }
14977 break;
14978 }
14979 }
14980
14981 if (func == NULL)
b34976b6 14982 return FALSE;
252b5132 14983
0367ecfb
NC		 14984 if (filename_ptr)
14985 *filename_ptr = filename;
14986 if (functionname_ptr)
14987 *functionname_ptr = bfd_asymbol_name (func);
14988
14989 return TRUE;
906e58ca 14990}
0367ecfb
NC		 14991
14992
14993/* Find the nearest line to a particular section and offset, for error
14994 reporting. This code is a duplicate of the code in elf.c, except
14995 that it uses arm_elf_find_function. */
14996
14997static bfd_boolean
14998elf32_arm_find_nearest_line (bfd * abfd,
0367ecfb 14999 asymbol ** symbols,
fb167eb2 15000 asection * section,
0367ecfb
NC		 15001 bfd_vma offset,
15002 const char ** filename_ptr,
15003 const char ** functionname_ptr,
fb167eb2
AM		 15004 unsigned int * line_ptr,
15005 unsigned int * discriminator_ptr)
0367ecfb
NC		 15006{
15007 bfd_boolean found = FALSE;
15008
fb167eb2 15009 if (_bfd_dwarf2_find_nearest_line (abfd, symbols, NULL, section, offset,
0367ecfb 15010 filename_ptr, functionname_ptr,
fb167eb2
AM		 15011 line_ptr, discriminator_ptr,
15012 dwarf_debug_sections, 0,
0367ecfb
NC		 15013 & elf_tdata (abfd)->dwarf2_find_line_info))
15014 {
15015 if (!*functionname_ptr)
fb167eb2 15016 arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 15017 *filename_ptr ? NULL : filename_ptr,
15018 functionname_ptr);
f21f3fe0 15019
0367ecfb
NC		 15020 return TRUE;
15021 }
15022
fb167eb2
AM		 15023 /* Skip _bfd_dwarf1_find_nearest_line since no known ARM toolchain
15024 uses DWARF1. */
15025
0367ecfb
NC		 15026 if (! _bfd_stab_section_find_nearest_line (abfd, symbols, section, offset,
15027 & found, filename_ptr,
15028 functionname_ptr, line_ptr,
15029 & elf_tdata (abfd)->line_info))
15030 return FALSE;
15031
15032 if (found && (*functionname_ptr || *line_ptr))
15033 return TRUE;
15034
15035 if (symbols == NULL)
15036 return FALSE;
15037
fb167eb2 15038 if (! arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 15039 filename_ptr, functionname_ptr))
15040 return FALSE;
15041
15042 *line_ptr = 0;
b34976b6 15043 return TRUE;
252b5132
RH		 15044}
15045
4ab527b0
FF		 15046static bfd_boolean
15047elf32_arm_find_inliner_info (bfd * abfd,
15048 const char ** filename_ptr,
15049 const char ** functionname_ptr,
15050 unsigned int * line_ptr)
15051{
15052 bfd_boolean found;
15053 found = _bfd_dwarf2_find_inliner_info (abfd, filename_ptr,
15054 functionname_ptr, line_ptr,
15055 & elf_tdata (abfd)->dwarf2_find_line_info);
15056 return found;
15057}
15058
252b5132
RH		 15059/* Adjust a symbol defined by a dynamic object and referenced by a
15060 regular object. The current definition is in some section of the
15061 dynamic object, but we're not including those sections. We have to
15062 change the definition to something the rest of the link can
15063 understand. */
15064
b34976b6 15065static bfd_boolean
57e8b36a
NC		 15066elf32_arm_adjust_dynamic_symbol (struct bfd_link_info * info,
15067 struct elf_link_hash_entry * h)
252b5132
RH		 15068{
15069 bfd * dynobj;
15070 asection * s;
b7693d02 15071 struct elf32_arm_link_hash_entry * eh;
67687978 15072 struct elf32_arm_link_hash_table *globals;
252b5132 15073
67687978 15074 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15075 if (globals == NULL)
15076 return FALSE;
15077
252b5132
RH		 15078 dynobj = elf_hash_table (info)->dynobj;
15079
15080 /* Make sure we know what is going on here. */
15081 BFD_ASSERT (dynobj != NULL
f5385ebf 15082 && (h->needs_plt
34e77a92 15083 || h->type == STT_GNU_IFUNC
f6e332e6 15084 || h->u.weakdef != NULL
f5385ebf
AM		 15085 || (h->def_dynamic
15086 && h->ref_regular
15087 && !h->def_regular)));
252b5132 15088
b7693d02
DJ		 15089 eh = (struct elf32_arm_link_hash_entry *) h;
15090
252b5132
RH		 15091 /* If this is a function, put it in the procedure linkage table. We
15092 will fill in the contents of the procedure linkage table later,
15093 when we know the address of the .got section. */
34e77a92 15094 if (h->type == STT_FUNC || h->type == STT_GNU_IFUNC || h->needs_plt)
252b5132 15095 {
34e77a92
RS		 15096 /* Calls to STT_GNU_IFUNC symbols always use a PLT, even if the
15097 symbol binds locally. */
5e681ec4 15098 if (h->plt.refcount <= 0
34e77a92
RS		 15099 || (h->type != STT_GNU_IFUNC
15100 && (SYMBOL_CALLS_LOCAL (info, h)
15101 || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
15102 && h->root.type == bfd_link_hash_undefweak))))
252b5132
RH		 15103 {
15104 /* This case can occur if we saw a PLT32 reloc in an input
5e681ec4
PB		 15105 file, but the symbol was never referred to by a dynamic
15106 object, or if all references were garbage collected. In
15107 such a case, we don't actually need to build a procedure
15108 linkage table, and we can just do a PC24 reloc instead. */
15109 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 15110 eh->plt.thumb_refcount = 0;
15111 eh->plt.maybe_thumb_refcount = 0;
15112 eh->plt.noncall_refcount = 0;
f5385ebf 15113 h->needs_plt = 0;
252b5132
RH		 15114 }
15115
b34976b6 15116 return TRUE;
252b5132 15117 }
5e681ec4 15118 else
b7693d02
DJ		 15119 {
15120 /* It's possible that we incorrectly decided a .plt reloc was
15121 needed for an R_ARM_PC24 or similar reloc to a non-function sym
15122 in check_relocs. We can't decide accurately between function
15123 and non-function syms in check-relocs; Objects loaded later in
15124 the link may change h->type. So fix it now. */
15125 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 15126 eh->plt.thumb_refcount = 0;
15127 eh->plt.maybe_thumb_refcount = 0;
15128 eh->plt.noncall_refcount = 0;
b7693d02 15129 }
252b5132
RH		 15130
15131 /* If this is a weak symbol, and there is a real definition, the
15132 processor independent code will have arranged for us to see the
15133 real definition first, and we can just use the same value. */
f6e332e6 15134 if (h->u.weakdef != NULL)
252b5132 15135 {
f6e332e6
AM		 15136 BFD_ASSERT (h->u.weakdef->root.type == bfd_link_hash_defined
15137 || h->u.weakdef->root.type == bfd_link_hash_defweak);
15138 h->root.u.def.section = h->u.weakdef->root.u.def.section;
15139 h->root.u.def.value = h->u.weakdef->root.u.def.value;
b34976b6 15140 return TRUE;
252b5132
RH		 15141 }
15142
ba93b8ac
DJ		 15143 /* If there are no non-GOT references, we do not need a copy
15144 relocation. */
15145 if (!h->non_got_ref)
15146 return TRUE;
15147
252b5132
RH		 15148 /* This is a reference to a symbol defined by a dynamic object which
15149 is not a function. */
15150
15151 /* If we are creating a shared library, we must presume that the
15152 only references to the symbol are via the global offset table.
15153 For such cases we need not do anything here; the relocations will
67687978
PB		 15154 be handled correctly by relocate_section. Relocatable executables
15155 can reference data in shared objects directly, so we don't need to
15156 do anything here. */
0e1862bb 15157 if (bfd_link_pic (info) || globals->root.is_relocatable_executable)
b34976b6 15158 return TRUE;
252b5132
RH		 15159
15160 /* We must allocate the symbol in our .dynbss section, which will
15161 become part of the .bss section of the executable. There will be
15162 an entry for this symbol in the .dynsym section. The dynamic
15163 object will contain position independent code, so all references
15164 from the dynamic object to this symbol will go through the global
15165 offset table. The dynamic linker will use the .dynsym entry to
15166 determine the address it must put in the global offset table, so
15167 both the dynamic object and the regular object will refer to the
15168 same memory location for the variable. */
3d4d4302 15169 s = bfd_get_linker_section (dynobj, ".dynbss");
252b5132
RH		 15170 BFD_ASSERT (s != NULL);
15171
5522f910
NC		 15172 /* If allowed, we must generate a R_ARM_COPY reloc to tell the dynamic
15173 linker to copy the initial value out of the dynamic object and into
15174 the runtime process image. We need to remember the offset into the
00a97672 15175 .rel(a).bss section we are going to use. */
5522f910
NC		 15176 if (info->nocopyreloc == 0
15177 && (h->root.u.def.section->flags & SEC_ALLOC) != 0
5522f910 15178 && h->size != 0)
252b5132
RH		 15179 {
15180 asection *srel;
15181
3d4d4302 15182 srel = bfd_get_linker_section (dynobj, RELOC_SECTION (globals, ".bss"));
47beaa6a 15183 elf32_arm_allocate_dynrelocs (info, srel, 1);
f5385ebf 15184 h->needs_copy = 1;
252b5132
RH		 15185 }
15186
6cabe1ea 15187 return _bfd_elf_adjust_dynamic_copy (info, h, s);
252b5132
RH		 15188}
15189
5e681ec4
PB		 15190/* Allocate space in .plt, .got and associated reloc sections for
15191 dynamic relocs. */
15192
15193static bfd_boolean
47beaa6a 15194allocate_dynrelocs_for_symbol (struct elf_link_hash_entry *h, void * inf)
5e681ec4
PB		 15195{
15196 struct bfd_link_info *info;
15197 struct elf32_arm_link_hash_table *htab;
15198 struct elf32_arm_link_hash_entry *eh;
0bdcacaf 15199 struct elf_dyn_relocs *p;
5e681ec4
PB		 15200
15201 if (h->root.type == bfd_link_hash_indirect)
15202 return TRUE;
15203
e6a6bb22
AM		 15204 eh = (struct elf32_arm_link_hash_entry *) h;
15205
5e681ec4
PB		 15206 info = (struct bfd_link_info *) inf;
15207 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15208 if (htab == NULL)
15209 return FALSE;
5e681ec4 15210
34e77a92 15211 if ((htab->root.dynamic_sections_created || h->type == STT_GNU_IFUNC)
5e681ec4
PB		 15212 && h->plt.refcount > 0)
15213 {
15214 /* Make sure this symbol is output as a dynamic symbol.
15215 Undefined weak syms won't yet be marked as dynamic. */
15216 if (h->dynindx == -1
f5385ebf 15217 && !h->forced_local)
5e681ec4 15218 {
c152c796 15219 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 15220 return FALSE;
15221 }
15222
34e77a92
RS		 15223 /* If the call in the PLT entry binds locally, the associated
15224 GOT entry should use an R_ARM_IRELATIVE relocation instead of
15225 the usual R_ARM_JUMP_SLOT. Put it in the .iplt section rather
15226 than the .plt section. */
15227 if (h->type == STT_GNU_IFUNC && SYMBOL_CALLS_LOCAL (info, h))
15228 {
15229 eh->is_iplt = 1;
15230 if (eh->plt.noncall_refcount == 0
15231 && SYMBOL_REFERENCES_LOCAL (info, h))
15232 /* All non-call references can be resolved directly.
15233 This means that they can (and in some cases, must)
15234 resolve directly to the run-time target, rather than
15235 to the PLT. That in turns means that any .got entry
15236 would be equal to the .igot.plt entry, so there's
15237 no point having both. */
15238 h->got.refcount = 0;
15239 }
15240
0e1862bb 15241 if (bfd_link_pic (info)
34e77a92 15242 || eh->is_iplt
7359ea65 15243 || WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, 0, h))
5e681ec4 15244 {
34e77a92 15245 elf32_arm_allocate_plt_entry (info, eh->is_iplt, &h->plt, &eh->plt);
b7693d02 15246
5e681ec4
PB		 15247 /* If this symbol is not defined in a regular file, and we are
15248 not generating a shared library, then set the symbol to this
15249 location in the .plt. This is required to make function
15250 pointers compare as equal between the normal executable and
15251 the shared library. */
0e1862bb 15252 if (! bfd_link_pic (info)
f5385ebf 15253 && !h->def_regular)
5e681ec4 15254 {
34e77a92 15255 h->root.u.def.section = htab->root.splt;
5e681ec4 15256 h->root.u.def.value = h->plt.offset;
5e681ec4 15257
67d74e43
DJ		 15258 /* Make sure the function is not marked as Thumb, in case
15259 it is the target of an ABS32 relocation, which will
15260 point to the PLT entry. */
39d911fc 15261 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
67d74e43 15262 }
022f8312 15263
00a97672
RS		 15264 /* VxWorks executables have a second set of relocations for
15265 each PLT entry. They go in a separate relocation section,
15266 which is processed by the kernel loader. */
0e1862bb 15267 if (htab->vxworks_p && !bfd_link_pic (info))
00a97672
RS		 15268 {
15269 /* There is a relocation for the initial PLT entry:
15270 an R_ARM_32 relocation for _GLOBAL_OFFSET_TABLE_. */
15271 if (h->plt.offset == htab->plt_header_size)
47beaa6a 15272 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 1);
00a97672
RS		 15273
15274 /* There are two extra relocations for each subsequent
15275 PLT entry: an R_ARM_32 relocation for the GOT entry,
15276 and an R_ARM_32 relocation for the PLT entry. */
47beaa6a 15277 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 2);
00a97672 15278 }
5e681ec4
PB		 15279 }
15280 else
15281 {
15282 h->plt.offset = (bfd_vma) -1;
f5385ebf 15283 h->needs_plt = 0;
5e681ec4
PB		 15284 }
15285 }
15286 else
15287 {
15288 h->plt.offset = (bfd_vma) -1;
f5385ebf 15289 h->needs_plt = 0;
5e681ec4
PB		 15290 }
15291
0855e32b
NS		 15292 eh = (struct elf32_arm_link_hash_entry *) h;
15293 eh->tlsdesc_got = (bfd_vma) -1;
15294
5e681ec4
PB		 15295 if (h->got.refcount > 0)
15296 {
15297 asection *s;
15298 bfd_boolean dyn;
ba93b8ac
DJ		 15299 int tls_type = elf32_arm_hash_entry (h)->tls_type;
15300 int indx;
5e681ec4
PB		 15301
15302 /* Make sure this symbol is output as a dynamic symbol.
15303 Undefined weak syms won't yet be marked as dynamic. */
15304 if (h->dynindx == -1
f5385ebf 15305 && !h->forced_local)
5e681ec4 15306 {
c152c796 15307 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 15308 return FALSE;
15309 }
15310
e5a52504
MM		 15311 if (!htab->symbian_p)
15312 {
362d30a1 15313 s = htab->root.sgot;
e5a52504 15314 h->got.offset = s->size;
ba93b8ac
DJ		 15315
15316 if (tls_type == GOT_UNKNOWN)
15317 abort ();
15318
15319 if (tls_type == GOT_NORMAL)
15320 /* Non-TLS symbols need one GOT slot. */
15321 s->size += 4;
15322 else
15323 {
99059e56
RM		 15324 if (tls_type & GOT_TLS_GDESC)
15325 {
0855e32b 15326 /* R_ARM_TLS_DESC needs 2 GOT slots. */
99059e56 15327 eh->tlsdesc_got
0855e32b
NS		 15328 = (htab->root.sgotplt->size
15329 - elf32_arm_compute_jump_table_size (htab));
99059e56
RM		 15330 htab->root.sgotplt->size += 8;
15331 h->got.offset = (bfd_vma) -2;
34e77a92 15332 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 15333 reloc in the middle of .got.plt. */
99059e56
RM		 15334 htab->num_tls_desc++;
15335 }
0855e32b 15336
ba93b8ac 15337 if (tls_type & GOT_TLS_GD)
0855e32b
NS		 15338 {
15339 /* R_ARM_TLS_GD32 needs 2 consecutive GOT slots. If
15340 the symbol is both GD and GDESC, got.offset may
15341 have been overwritten. */
15342 h->got.offset = s->size;
15343 s->size += 8;
15344 }
15345
ba93b8ac
DJ		 15346 if (tls_type & GOT_TLS_IE)
15347 /* R_ARM_TLS_IE32 needs one GOT slot. */
15348 s->size += 4;
15349 }
15350
e5a52504 15351 dyn = htab->root.dynamic_sections_created;
ba93b8ac
DJ		 15352
15353 indx = 0;
0e1862bb
L		 15354 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
15355 bfd_link_pic (info),
15356 h)
15357 && (!bfd_link_pic (info)
ba93b8ac
DJ		 15358 || !SYMBOL_REFERENCES_LOCAL (info, h)))
15359 indx = h->dynindx;
15360
15361 if (tls_type != GOT_NORMAL
0e1862bb 15362 && (bfd_link_pic (info) || indx != 0)
ba93b8ac
DJ		 15363 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
15364 || h->root.type != bfd_link_hash_undefweak))
15365 {
15366 if (tls_type & GOT_TLS_IE)
47beaa6a 15367 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 15368
15369 if (tls_type & GOT_TLS_GD)
47beaa6a 15370 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 15371
b38cadfb 15372 if (tls_type & GOT_TLS_GDESC)
0855e32b 15373 {
47beaa6a 15374 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
0855e32b
NS		 15375 /* GDESC needs a trampoline to jump to. */
15376 htab->tls_trampoline = -1;
15377 }
15378
15379 /* Only GD needs it. GDESC just emits one relocation per
15380 2 entries. */
b38cadfb 15381 if ((tls_type & GOT_TLS_GD) && indx != 0)
47beaa6a 15382 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 15383 }
6f820c85 15384 else if (indx != -1 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 15385 {
15386 if (htab->root.dynamic_sections_created)
15387 /* Reserve room for the GOT entry's R_ARM_GLOB_DAT relocation. */
15388 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
15389 }
34e77a92
RS		 15390 else if (h->type == STT_GNU_IFUNC
15391 && eh->plt.noncall_refcount == 0)
15392 /* No non-call references resolve the STT_GNU_IFUNC's PLT entry;
15393 they all resolve dynamically instead. Reserve room for the
15394 GOT entry's R_ARM_IRELATIVE relocation. */
15395 elf32_arm_allocate_irelocs (info, htab->root.srelgot, 1);
0e1862bb
L		 15396 else if (bfd_link_pic (info)
15397 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
15398 || h->root.type != bfd_link_hash_undefweak))
b436d854 15399 /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
47beaa6a 15400 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
e5a52504 15401 }
5e681ec4
PB		 15402 }
15403 else
15404 h->got.offset = (bfd_vma) -1;
15405
a4fd1a8e
PB		 15406 /* Allocate stubs for exported Thumb functions on v4t. */
15407 if (!htab->use_blx && h->dynindx != -1
0eaedd0e 15408 && h->def_regular
39d911fc 15409 && ARM_GET_SYM_BRANCH_TYPE (h->target_internal) == ST_BRANCH_TO_THUMB
a4fd1a8e
PB		 15410 && ELF_ST_VISIBILITY (h->other) == STV_DEFAULT)
15411 {
15412 struct elf_link_hash_entry * th;
15413 struct bfd_link_hash_entry * bh;
15414 struct elf_link_hash_entry * myh;
15415 char name[1024];
15416 asection *s;
15417 bh = NULL;
15418 /* Create a new symbol to regist the real location of the function. */
15419 s = h->root.u.def.section;
906e58ca 15420 sprintf (name, "__real_%s", h->root.root.string);
a4fd1a8e
PB		 15421 _bfd_generic_link_add_one_symbol (info, s->owner,
15422 name, BSF_GLOBAL, s,
15423 h->root.u.def.value,
15424 NULL, TRUE, FALSE, &bh);
15425
15426 myh = (struct elf_link_hash_entry *) bh;
35fc36a8 15427 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
a4fd1a8e 15428 myh->forced_local = 1;
39d911fc 15429 ARM_SET_SYM_BRANCH_TYPE (myh->target_internal, ST_BRANCH_TO_THUMB);
a4fd1a8e
PB		 15430 eh->export_glue = myh;
15431 th = record_arm_to_thumb_glue (info, h);
15432 /* Point the symbol at the stub. */
15433 h->type = ELF_ST_INFO (ELF_ST_BIND (h->type), STT_FUNC);
39d911fc 15434 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
a4fd1a8e
PB		 15435 h->root.u.def.section = th->root.u.def.section;
15436 h->root.u.def.value = th->root.u.def.value & ~1;
15437 }
15438
0bdcacaf 15439 if (eh->dyn_relocs == NULL)
5e681ec4
PB		 15440 return TRUE;
15441
15442 /* In the shared -Bsymbolic case, discard space allocated for
15443 dynamic pc-relative relocs against symbols which turn out to be
15444 defined in regular objects. For the normal shared case, discard
15445 space for pc-relative relocs that have become local due to symbol
15446 visibility changes. */
15447
0e1862bb 15448 if (bfd_link_pic (info) || htab->root.is_relocatable_executable)
5e681ec4 15449 {
469a3493
RM		 15450 /* Relocs that use pc_count are PC-relative forms, which will appear
15451 on something like ".long foo - ." or "movw REG, foo - .". We want
15452 calls to protected symbols to resolve directly to the function
15453 rather than going via the plt. If people want function pointer
15454 comparisons to work as expected then they should avoid writing
15455 assembly like ".long foo - .". */
ba93b8ac
DJ		 15456 if (SYMBOL_CALLS_LOCAL (info, h))
15457 {
0bdcacaf 15458 struct elf_dyn_relocs **pp;
ba93b8ac 15459
0bdcacaf 15460 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
ba93b8ac
DJ		 15461 {
15462 p->count -= p->pc_count;
15463 p->pc_count = 0;
15464 if (p->count == 0)
15465 *pp = p->next;
15466 else
15467 pp = &p->next;
15468 }
15469 }
15470
4dfe6ac6 15471 if (htab->vxworks_p)
3348747a 15472 {
0bdcacaf 15473 struct elf_dyn_relocs **pp;
3348747a 15474
0bdcacaf 15475 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
3348747a 15476 {
0bdcacaf 15477 if (strcmp (p->sec->output_section->name, ".tls_vars") == 0)
3348747a
NS		 15478 *pp = p->next;
15479 else
15480 pp = &p->next;
15481 }
15482 }
15483
ba93b8ac 15484 /* Also discard relocs on undefined weak syms with non-default
99059e56 15485 visibility. */
0bdcacaf 15486 if (eh->dyn_relocs != NULL
5e681ec4 15487 && h->root.type == bfd_link_hash_undefweak)
22d606e9
AM		 15488 {
15489 if (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT)
0bdcacaf 15490 eh->dyn_relocs = NULL;
22d606e9
AM		 15491
15492 /* Make sure undefined weak symbols are output as a dynamic
15493 symbol in PIEs. */
15494 else if (h->dynindx == -1
15495 && !h->forced_local)
15496 {
15497 if (! bfd_elf_link_record_dynamic_symbol (info, h))
15498 return FALSE;
15499 }
15500 }
15501
67687978
PB		 15502 else if (htab->root.is_relocatable_executable && h->dynindx == -1
15503 && h->root.type == bfd_link_hash_new)
15504 {
15505 /* Output absolute symbols so that we can create relocations
15506 against them. For normal symbols we output a relocation
15507 against the section that contains them. */
15508 if (! bfd_elf_link_record_dynamic_symbol (info, h))
15509 return FALSE;
15510 }
15511
5e681ec4
PB		 15512 }
15513 else
15514 {
15515 /* For the non-shared case, discard space for relocs against
15516 symbols which turn out to need copy relocs or are not
15517 dynamic. */
15518
f5385ebf
AM		 15519 if (!h->non_got_ref
15520 && ((h->def_dynamic
15521 && !h->def_regular)
5e681ec4
PB		 15522 || (htab->root.dynamic_sections_created
15523 && (h->root.type == bfd_link_hash_undefweak
15524 || h->root.type == bfd_link_hash_undefined))))
15525 {
15526 /* Make sure this symbol is output as a dynamic symbol.
15527 Undefined weak syms won't yet be marked as dynamic. */
15528 if (h->dynindx == -1
f5385ebf 15529 && !h->forced_local)
5e681ec4 15530 {
c152c796 15531 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 15532 return FALSE;
15533 }
15534
15535 /* If that succeeded, we know we'll be keeping all the
15536 relocs. */
15537 if (h->dynindx != -1)
15538 goto keep;
15539 }
15540
0bdcacaf 15541 eh->dyn_relocs = NULL;
5e681ec4
PB		 15542
15543 keep: ;
15544 }
15545
15546 /* Finally, allocate space. */
0bdcacaf 15547 for (p = eh->dyn_relocs; p != NULL; p = p->next)
5e681ec4 15548 {
0bdcacaf 15549 asection *sreloc = elf_section_data (p->sec)->sreloc;
34e77a92
RS		 15550 if (h->type == STT_GNU_IFUNC
15551 && eh->plt.noncall_refcount == 0
15552 && SYMBOL_REFERENCES_LOCAL (info, h))
15553 elf32_arm_allocate_irelocs (info, sreloc, p->count);
15554 else
15555 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
5e681ec4
PB		 15556 }
15557
15558 return TRUE;
15559}
15560
08d1f311
DJ		 15561/* Find any dynamic relocs that apply to read-only sections. */
15562
15563static bfd_boolean
8029a119 15564elf32_arm_readonly_dynrelocs (struct elf_link_hash_entry * h, void * inf)
08d1f311 15565{
8029a119 15566 struct elf32_arm_link_hash_entry * eh;
0bdcacaf 15567 struct elf_dyn_relocs * p;
08d1f311 15568
08d1f311 15569 eh = (struct elf32_arm_link_hash_entry *) h;
0bdcacaf 15570 for (p = eh->dyn_relocs; p != NULL; p = p->next)
08d1f311 15571 {
0bdcacaf 15572 asection *s = p->sec;
08d1f311
DJ		 15573
15574 if (s != NULL && (s->flags & SEC_READONLY) != 0)
15575 {
15576 struct bfd_link_info *info = (struct bfd_link_info *) inf;
15577
15578 info->flags |= DF_TEXTREL;
15579
15580 /* Not an error, just cut short the traversal. */
15581 return FALSE;
15582 }
15583 }
15584 return TRUE;
15585}
15586
d504ffc8
DJ		 15587void
15588bfd_elf32_arm_set_byteswap_code (struct bfd_link_info *info,
15589 int byteswap_code)
15590{
15591 struct elf32_arm_link_hash_table *globals;
15592
15593 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15594 if (globals == NULL)
15595 return;
15596
d504ffc8
DJ		 15597 globals->byteswap_code = byteswap_code;
15598}
15599
252b5132
RH		 15600/* Set the sizes of the dynamic sections. */
15601
b34976b6 15602static bfd_boolean
57e8b36a
NC		 15603elf32_arm_size_dynamic_sections (bfd * output_bfd ATTRIBUTE_UNUSED,
15604 struct bfd_link_info * info)
252b5132
RH		 15605{
15606 bfd * dynobj;
15607 asection * s;
b34976b6
AM		 15608 bfd_boolean plt;
15609 bfd_boolean relocs;
5e681ec4
PB		 15610 bfd *ibfd;
15611 struct elf32_arm_link_hash_table *htab;
252b5132 15612
5e681ec4 15613 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15614 if (htab == NULL)
15615 return FALSE;
15616
252b5132
RH		 15617 dynobj = elf_hash_table (info)->dynobj;
15618 BFD_ASSERT (dynobj != NULL);
39b41c9c 15619 check_use_blx (htab);
252b5132
RH		 15620
15621 if (elf_hash_table (info)->dynamic_sections_created)
15622 {
15623 /* Set the contents of the .interp section to the interpreter. */
9b8b325a 15624 if (bfd_link_executable (info) && !info->nointerp)
252b5132 15625 {
3d4d4302 15626 s = bfd_get_linker_section (dynobj, ".interp");
252b5132 15627 BFD_ASSERT (s != NULL);
eea6121a 15628 s->size = sizeof ELF_DYNAMIC_INTERPRETER;
252b5132
RH		 15629 s->contents = (unsigned char *) ELF_DYNAMIC_INTERPRETER;
15630 }
15631 }
5e681ec4
PB		 15632
15633 /* Set up .got offsets for local syms, and space for local dynamic
15634 relocs. */
c72f2fb2 15635 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
252b5132 15636 {
5e681ec4
PB		 15637 bfd_signed_vma *local_got;
15638 bfd_signed_vma *end_local_got;
34e77a92 15639 struct arm_local_iplt_info **local_iplt_ptr, *local_iplt;
5e681ec4 15640 char *local_tls_type;
0855e32b 15641 bfd_vma *local_tlsdesc_gotent;
5e681ec4
PB		 15642 bfd_size_type locsymcount;
15643 Elf_Internal_Shdr *symtab_hdr;
15644 asection *srel;
4dfe6ac6 15645 bfd_boolean is_vxworks = htab->vxworks_p;
34e77a92 15646 unsigned int symndx;
5e681ec4 15647
0ffa91dd 15648 if (! is_arm_elf (ibfd))
5e681ec4
PB		 15649 continue;
15650
15651 for (s = ibfd->sections; s != NULL; s = s->next)
15652 {
0bdcacaf 15653 struct elf_dyn_relocs *p;
5e681ec4 15654
0bdcacaf 15655 for (p = (struct elf_dyn_relocs *)
99059e56 15656 elf_section_data (s)->local_dynrel; p != NULL; p = p->next)
5e681ec4 15657 {
0bdcacaf
RS		 15658 if (!bfd_is_abs_section (p->sec)
15659 && bfd_is_abs_section (p->sec->output_section))
5e681ec4
PB		 15660 {
15661 /* Input section has been discarded, either because
15662 it is a copy of a linkonce section or due to
15663 linker script /DISCARD/, so we'll be discarding
15664 the relocs too. */
15665 }
3348747a 15666 else if (is_vxworks
0bdcacaf 15667 && strcmp (p->sec->output_section->name,
3348747a
NS		 15668 ".tls_vars") == 0)
15669 {
15670 /* Relocations in vxworks .tls_vars sections are
15671 handled specially by the loader. */
15672 }
5e681ec4
PB		 15673 else if (p->count != 0)
15674 {
0bdcacaf 15675 srel = elf_section_data (p->sec)->sreloc;
47beaa6a 15676 elf32_arm_allocate_dynrelocs (info, srel, p->count);
0bdcacaf 15677 if ((p->sec->output_section->flags & SEC_READONLY) != 0)
5e681ec4
PB		 15678 info->flags |= DF_TEXTREL;
15679 }
15680 }
15681 }
15682
15683 local_got = elf_local_got_refcounts (ibfd);
15684 if (!local_got)
15685 continue;
15686
0ffa91dd 15687 symtab_hdr = & elf_symtab_hdr (ibfd);
5e681ec4
PB		 15688 locsymcount = symtab_hdr->sh_info;
15689 end_local_got = local_got + locsymcount;
34e77a92 15690 local_iplt_ptr = elf32_arm_local_iplt (ibfd);
ba93b8ac 15691 local_tls_type = elf32_arm_local_got_tls_type (ibfd);
0855e32b 15692 local_tlsdesc_gotent = elf32_arm_local_tlsdesc_gotent (ibfd);
34e77a92 15693 symndx = 0;
362d30a1
RS		 15694 s = htab->root.sgot;
15695 srel = htab->root.srelgot;
0855e32b 15696 for (; local_got < end_local_got;
34e77a92
RS		 15697 ++local_got, ++local_iplt_ptr, ++local_tls_type,
15698 ++local_tlsdesc_gotent, ++symndx)
5e681ec4 15699 {
0855e32b 15700 *local_tlsdesc_gotent = (bfd_vma) -1;
34e77a92
RS		 15701 local_iplt = *local_iplt_ptr;
15702 if (local_iplt != NULL)
15703 {
15704 struct elf_dyn_relocs *p;
15705
15706 if (local_iplt->root.refcount > 0)
15707 {
15708 elf32_arm_allocate_plt_entry (info, TRUE,
15709 &local_iplt->root,
15710 &local_iplt->arm);
15711 if (local_iplt->arm.noncall_refcount == 0)
15712 /* All references to the PLT are calls, so all
15713 non-call references can resolve directly to the
15714 run-time target. This means that the .got entry
15715 would be the same as the .igot.plt entry, so there's
15716 no point creating both. */
15717 *local_got = 0;
15718 }
15719 else
15720 {
15721 BFD_ASSERT (local_iplt->arm.noncall_refcount == 0);
15722 local_iplt->root.offset = (bfd_vma) -1;
15723 }
15724
15725 for (p = local_iplt->dyn_relocs; p != NULL; p = p->next)
15726 {
15727 asection *psrel;
15728
15729 psrel = elf_section_data (p->sec)->sreloc;
15730 if (local_iplt->arm.noncall_refcount == 0)
15731 elf32_arm_allocate_irelocs (info, psrel, p->count);
15732 else
15733 elf32_arm_allocate_dynrelocs (info, psrel, p->count);
15734 }
15735 }
5e681ec4
PB		 15736 if (*local_got > 0)
15737 {
34e77a92
RS		 15738 Elf_Internal_Sym *isym;
15739
eea6121a 15740 *local_got = s->size;
ba93b8ac
DJ		 15741 if (*local_tls_type & GOT_TLS_GD)
15742 /* TLS_GD relocs need an 8-byte structure in the GOT. */
15743 s->size += 8;
0855e32b
NS		 15744 if (*local_tls_type & GOT_TLS_GDESC)
15745 {
15746 *local_tlsdesc_gotent = htab->root.sgotplt->size
15747 - elf32_arm_compute_jump_table_size (htab);
15748 htab->root.sgotplt->size += 8;
15749 *local_got = (bfd_vma) -2;
34e77a92 15750 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 15751 reloc in the middle of .got.plt. */
99059e56 15752 htab->num_tls_desc++;
0855e32b 15753 }
ba93b8ac
DJ		 15754 if (*local_tls_type & GOT_TLS_IE)
15755 s->size += 4;
ba93b8ac 15756
0855e32b
NS		 15757 if (*local_tls_type & GOT_NORMAL)
15758 {
15759 /* If the symbol is both GD and GDESC, *local_got
15760 may have been overwritten. */
15761 *local_got = s->size;
15762 s->size += 4;
15763 }
15764
34e77a92
RS		 15765 isym = bfd_sym_from_r_symndx (&htab->sym_cache, ibfd, symndx);
15766 if (isym == NULL)
15767 return FALSE;
15768
15769 /* If all references to an STT_GNU_IFUNC PLT are calls,
15770 then all non-call references, including this GOT entry,
15771 resolve directly to the run-time target. */
15772 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC
15773 && (local_iplt == NULL
15774 || local_iplt->arm.noncall_refcount == 0))
15775 elf32_arm_allocate_irelocs (info, srel, 1);
0e1862bb 15776 else if (bfd_link_pic (info) || output_bfd->flags & DYNAMIC)
0855e32b 15777 {
0e1862bb 15778 if ((bfd_link_pic (info) && !(*local_tls_type & GOT_TLS_GDESC))
3064e1ff
JB		 15779 || *local_tls_type & GOT_TLS_GD)
15780 elf32_arm_allocate_dynrelocs (info, srel, 1);
99059e56 15781
0e1862bb 15782 if (bfd_link_pic (info) && *local_tls_type & GOT_TLS_GDESC)
3064e1ff
JB		 15783 {
15784 elf32_arm_allocate_dynrelocs (info,
15785 htab->root.srelplt, 1);
15786 htab->tls_trampoline = -1;
15787 }
0855e32b 15788 }
5e681ec4
PB		 15789 }
15790 else
15791 *local_got = (bfd_vma) -1;
15792 }
252b5132
RH		 15793 }
15794
ba93b8ac
DJ		 15795 if (htab->tls_ldm_got.refcount > 0)
15796 {
15797 /* Allocate two GOT entries and one dynamic relocation (if necessary)
15798 for R_ARM_TLS_LDM32 relocations. */
362d30a1
RS		 15799 htab->tls_ldm_got.offset = htab->root.sgot->size;
15800 htab->root.sgot->size += 8;
0e1862bb 15801 if (bfd_link_pic (info))
47beaa6a 15802 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 15803 }
15804 else
15805 htab->tls_ldm_got.offset = -1;
15806
5e681ec4
PB		 15807 /* Allocate global sym .plt and .got entries, and space for global
15808 sym dynamic relocs. */
47beaa6a 15809 elf_link_hash_traverse (& htab->root, allocate_dynrelocs_for_symbol, info);
252b5132 15810
d504ffc8 15811 /* Here we rummage through the found bfds to collect glue information. */
c72f2fb2 15812 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
c7b8f16e 15813 {
0ffa91dd 15814 if (! is_arm_elf (ibfd))
e44a2c9c
AM		 15815 continue;
15816
c7b8f16e
JB		 15817 /* Initialise mapping tables for code/data. */
15818 bfd_elf32_arm_init_maps (ibfd);
906e58ca 15819
c7b8f16e 15820 if (!bfd_elf32_arm_process_before_allocation (ibfd, info)
a504d23a
LA		 15821 || !bfd_elf32_arm_vfp11_erratum_scan (ibfd, info)
15822 || !bfd_elf32_arm_stm32l4xx_erratum_scan (ibfd, info))
99059e56
RM		 15823 /* xgettext:c-format */
15824 _bfd_error_handler (_("Errors encountered processing file %s"),
c7b8f16e
JB		 15825 ibfd->filename);
15826 }
d504ffc8 15827
3e6b1042
DJ		 15828 /* Allocate space for the glue sections now that we've sized them. */
15829 bfd_elf32_arm_allocate_interworking_sections (info);
15830
0855e32b
NS		 15831 /* For every jump slot reserved in the sgotplt, reloc_count is
15832 incremented. However, when we reserve space for TLS descriptors,
15833 it's not incremented, so in order to compute the space reserved
15834 for them, it suffices to multiply the reloc count by the jump
15835 slot size. */
15836 if (htab->root.srelplt)
15837 htab->sgotplt_jump_table_size = elf32_arm_compute_jump_table_size(htab);
15838
15839 if (htab->tls_trampoline)
15840 {
15841 if (htab->root.splt->size == 0)
15842 htab->root.splt->size += htab->plt_header_size;
b38cadfb 15843
0855e32b
NS		 15844 htab->tls_trampoline = htab->root.splt->size;
15845 htab->root.splt->size += htab->plt_entry_size;
b38cadfb 15846
0855e32b 15847 /* If we're not using lazy TLS relocations, don't generate the
99059e56 15848 PLT and GOT entries they require. */
0855e32b
NS		 15849 if (!(info->flags & DF_BIND_NOW))
15850 {
15851 htab->dt_tlsdesc_got = htab->root.sgot->size;
15852 htab->root.sgot->size += 4;
15853
15854 htab->dt_tlsdesc_plt = htab->root.splt->size;
15855 htab->root.splt->size += 4 * ARRAY_SIZE (dl_tlsdesc_lazy_trampoline);
15856 }
15857 }
15858
252b5132
RH		 15859 /* The check_relocs and adjust_dynamic_symbol entry points have
15860 determined the sizes of the various dynamic sections. Allocate
15861 memory for them. */
b34976b6
AM		 15862 plt = FALSE;
15863 relocs = FALSE;
252b5132
RH		 15864 for (s = dynobj->sections; s != NULL; s = s->next)
15865 {
15866 const char * name;
252b5132
RH		 15867
15868 if ((s->flags & SEC_LINKER_CREATED) == 0)
15869 continue;
15870
15871 /* It's OK to base decisions on the section name, because none
15872 of the dynobj section names depend upon the input files. */
15873 name = bfd_get_section_name (dynobj, s);
15874
34e77a92 15875 if (s == htab->root.splt)
252b5132 15876 {
c456f082
AM		 15877 /* Remember whether there is a PLT. */
15878 plt = s->size != 0;
252b5132 15879 }
0112cd26 15880 else if (CONST_STRNEQ (name, ".rel"))
252b5132 15881 {
c456f082 15882 if (s->size != 0)
252b5132 15883 {
252b5132 15884 /* Remember whether there are any reloc sections other
00a97672 15885 than .rel(a).plt and .rela.plt.unloaded. */
362d30a1 15886 if (s != htab->root.srelplt && s != htab->srelplt2)
b34976b6 15887 relocs = TRUE;
252b5132
RH		 15888
15889 /* We use the reloc_count field as a counter if we need
15890 to copy relocs into the output file. */
15891 s->reloc_count = 0;
15892 }
15893 }
34e77a92
RS		 15894 else if (s != htab->root.sgot
15895 && s != htab->root.sgotplt
15896 && s != htab->root.iplt
15897 && s != htab->root.igotplt
15898 && s != htab->sdynbss)
252b5132
RH		 15899 {
15900 /* It's not one of our sections, so don't allocate space. */
15901 continue;
15902 }
15903
c456f082 15904 if (s->size == 0)
252b5132 15905 {
c456f082 15906 /* If we don't need this section, strip it from the
00a97672
RS		 15907 output file. This is mostly to handle .rel(a).bss and
15908 .rel(a).plt. We must create both sections in
c456f082
AM		 15909 create_dynamic_sections, because they must be created
15910 before the linker maps input sections to output
15911 sections. The linker does that before
15912 adjust_dynamic_symbol is called, and it is that
15913 function which decides whether anything needs to go
15914 into these sections. */
8423293d 15915 s->flags |= SEC_EXCLUDE;
252b5132
RH		 15916 continue;
15917 }
15918
c456f082
AM		 15919 if ((s->flags & SEC_HAS_CONTENTS) == 0)
15920 continue;
15921
252b5132 15922 /* Allocate memory for the section contents. */
21d799b5 15923 s->contents = (unsigned char *) bfd_zalloc (dynobj, s->size);
c456f082 15924 if (s->contents == NULL)
b34976b6 15925 return FALSE;
252b5132
RH		 15926 }
15927
15928 if (elf_hash_table (info)->dynamic_sections_created)
15929 {
15930 /* Add some entries to the .dynamic section. We fill in the
15931 values later, in elf32_arm_finish_dynamic_sections, but we
15932 must add the entries now so that we get the correct size for
15933 the .dynamic section. The DT_DEBUG entry is filled in by the
15934 dynamic linker and used by the debugger. */
dc810e39 15935#define add_dynamic_entry(TAG, VAL) \
5a580b3a 15936 _bfd_elf_add_dynamic_entry (info, TAG, VAL)
dc810e39 15937
0e1862bb 15938 if (bfd_link_executable (info))
252b5132 15939 {
dc810e39 15940 if (!add_dynamic_entry (DT_DEBUG, 0))
b34976b6 15941 return FALSE;
252b5132
RH		 15942 }
15943
15944 if (plt)
15945 {
dc810e39
AM		 15946 if ( !add_dynamic_entry (DT_PLTGOT, 0)
15947 || !add_dynamic_entry (DT_PLTRELSZ, 0)
00a97672
RS		 15948 || !add_dynamic_entry (DT_PLTREL,
15949 htab->use_rel ? DT_REL : DT_RELA)
dc810e39 15950 || !add_dynamic_entry (DT_JMPREL, 0))
b34976b6 15951 return FALSE;
0855e32b
NS		 15952
15953 if (htab->dt_tlsdesc_plt &&
b38cadfb 15954 (!add_dynamic_entry (DT_TLSDESC_PLT,0)
0855e32b 15955 || !add_dynamic_entry (DT_TLSDESC_GOT,0)))
b38cadfb 15956 return FALSE;
252b5132
RH		 15957 }
15958
15959 if (relocs)
15960 {
00a97672
RS		 15961 if (htab->use_rel)
15962 {
15963 if (!add_dynamic_entry (DT_REL, 0)
15964 || !add_dynamic_entry (DT_RELSZ, 0)
15965 || !add_dynamic_entry (DT_RELENT, RELOC_SIZE (htab)))
15966 return FALSE;
15967 }
15968 else
15969 {
15970 if (!add_dynamic_entry (DT_RELA, 0)
15971 || !add_dynamic_entry (DT_RELASZ, 0)
15972 || !add_dynamic_entry (DT_RELAENT, RELOC_SIZE (htab)))
15973 return FALSE;
15974 }
252b5132
RH		 15975 }
15976
08d1f311
DJ		 15977 /* If any dynamic relocs apply to a read-only section,
15978 then we need a DT_TEXTREL entry. */
15979 if ((info->flags & DF_TEXTREL) == 0)
8029a119
NC		 15980 elf_link_hash_traverse (& htab->root, elf32_arm_readonly_dynrelocs,
15981 info);
08d1f311 15982
99e4ae17 15983 if ((info->flags & DF_TEXTREL) != 0)
252b5132 15984 {
dc810e39 15985 if (!add_dynamic_entry (DT_TEXTREL, 0))
b34976b6 15986 return FALSE;
252b5132 15987 }
7a2b07ff
NS		 15988 if (htab->vxworks_p
15989 && !elf_vxworks_add_dynamic_entries (output_bfd, info))
15990 return FALSE;
252b5132 15991 }
8532796c 15992#undef add_dynamic_entry
252b5132 15993
b34976b6 15994 return TRUE;
252b5132
RH		 15995}
15996
0855e32b
NS		 15997/* Size sections even though they're not dynamic. We use it to setup
15998 _TLS_MODULE_BASE_, if needed. */
15999
16000static bfd_boolean
16001elf32_arm_always_size_sections (bfd *output_bfd,
99059e56 16002 struct bfd_link_info *info)
0855e32b
NS		 16003{
16004 asection *tls_sec;
16005
0e1862bb 16006 if (bfd_link_relocatable (info))
0855e32b
NS		 16007 return TRUE;
16008
16009 tls_sec = elf_hash_table (info)->tls_sec;
16010
16011 if (tls_sec)
16012 {
16013 struct elf_link_hash_entry *tlsbase;
16014
16015 tlsbase = elf_link_hash_lookup
16016 (elf_hash_table (info), "_TLS_MODULE_BASE_", TRUE, TRUE, FALSE);
16017
16018 if (tlsbase)
99059e56
RM		 16019 {
16020 struct bfd_link_hash_entry *bh = NULL;
0855e32b 16021 const struct elf_backend_data *bed
99059e56 16022 = get_elf_backend_data (output_bfd);
0855e32b 16023
99059e56 16024 if (!(_bfd_generic_link_add_one_symbol
0855e32b
NS		 16025 (info, output_bfd, "_TLS_MODULE_BASE_", BSF_LOCAL,
16026 tls_sec, 0, NULL, FALSE,
16027 bed->collect, &bh)))
16028 return FALSE;
b38cadfb 16029
99059e56
RM		 16030 tlsbase->type = STT_TLS;
16031 tlsbase = (struct elf_link_hash_entry *)bh;
16032 tlsbase->def_regular = 1;
16033 tlsbase->other = STV_HIDDEN;
16034 (*bed->elf_backend_hide_symbol) (info, tlsbase, TRUE);
0855e32b
NS		 16035 }
16036 }
16037 return TRUE;
16038}
16039
252b5132
RH		 16040/* Finish up dynamic symbol handling. We set the contents of various
16041 dynamic sections here. */
16042
b34976b6 16043static bfd_boolean
906e58ca
NC		 16044elf32_arm_finish_dynamic_symbol (bfd * output_bfd,
16045 struct bfd_link_info * info,
16046 struct elf_link_hash_entry * h,
16047 Elf_Internal_Sym * sym)
252b5132 16048{
e5a52504 16049 struct elf32_arm_link_hash_table *htab;
b7693d02 16050 struct elf32_arm_link_hash_entry *eh;
252b5132 16051
e5a52504 16052 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16053 if (htab == NULL)
16054 return FALSE;
16055
b7693d02 16056 eh = (struct elf32_arm_link_hash_entry *) h;
252b5132
RH		 16057
16058 if (h->plt.offset != (bfd_vma) -1)
16059 {
34e77a92 16060 if (!eh->is_iplt)
e5a52504 16061 {
34e77a92 16062 BFD_ASSERT (h->dynindx != -1);
57460bcf
NC		 16063 if (! elf32_arm_populate_plt_entry (output_bfd, info, &h->plt, &eh->plt,
16064 h->dynindx, 0))
16065 return FALSE;
e5a52504 16066 }
57e8b36a 16067
f5385ebf 16068 if (!h->def_regular)
252b5132
RH		 16069 {
16070 /* Mark the symbol as undefined, rather than as defined in
3a635617 16071 the .plt section. */
252b5132 16072 sym->st_shndx = SHN_UNDEF;
3a635617 16073 /* If the symbol is weak we need to clear the value.
d982ba73
PB		 16074 Otherwise, the PLT entry would provide a definition for
16075 the symbol even if the symbol wasn't defined anywhere,
3a635617
WN		 16076 and so the symbol would never be NULL. Leave the value if
16077 there were any relocations where pointer equality matters
16078 (this is a clue for the dynamic linker, to make function
16079 pointer comparisons work between an application and shared
16080 library). */
97323ad1 16081 if (!h->ref_regular_nonweak || !h->pointer_equality_needed)
d982ba73 16082 sym->st_value = 0;
252b5132 16083 }
34e77a92
RS		 16084 else if (eh->is_iplt && eh->plt.noncall_refcount != 0)
16085 {
16086 /* At least one non-call relocation references this .iplt entry,
16087 so the .iplt entry is the function's canonical address. */
16088 sym->st_info = ELF_ST_INFO (ELF_ST_BIND (sym->st_info), STT_FUNC);
39d911fc 16089 ARM_SET_SYM_BRANCH_TYPE (sym->st_target_internal, ST_BRANCH_TO_ARM);
34e77a92
RS		 16090 sym->st_shndx = (_bfd_elf_section_from_bfd_section
16091 (output_bfd, htab->root.iplt->output_section));
16092 sym->st_value = (h->plt.offset
16093 + htab->root.iplt->output_section->vma
16094 + htab->root.iplt->output_offset);
16095 }
252b5132
RH		 16096 }
16097
f5385ebf 16098 if (h->needs_copy)
252b5132
RH		 16099 {
16100 asection * s;
947216bf 16101 Elf_Internal_Rela rel;
252b5132
RH		 16102
16103 /* This symbol needs a copy reloc. Set it up. */
252b5132
RH		 16104 BFD_ASSERT (h->dynindx != -1
16105 && (h->root.type == bfd_link_hash_defined
16106 || h->root.type == bfd_link_hash_defweak));
16107
362d30a1 16108 s = htab->srelbss;
252b5132
RH		 16109 BFD_ASSERT (s != NULL);
16110
00a97672 16111 rel.r_addend = 0;
252b5132
RH		 16112 rel.r_offset = (h->root.u.def.value
16113 + h->root.u.def.section->output_section->vma
16114 + h->root.u.def.section->output_offset);
16115 rel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_COPY);
47beaa6a 16116 elf32_arm_add_dynreloc (output_bfd, info, s, &rel);
252b5132
RH		 16117 }
16118
00a97672
RS		 16119 /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. On VxWorks,
16120 the _GLOBAL_OFFSET_TABLE_ symbol is not absolute: it is relative
16121 to the ".got" section. */
9637f6ef 16122 if (h == htab->root.hdynamic
00a97672 16123 || (!htab->vxworks_p && h == htab->root.hgot))
252b5132
RH		 16124 sym->st_shndx = SHN_ABS;
16125
b34976b6 16126 return TRUE;
252b5132
RH		 16127}
16128
0855e32b
NS		 16129static void
16130arm_put_trampoline (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
16131 void *contents,
16132 const unsigned long *template, unsigned count)
16133{
16134 unsigned ix;
b38cadfb 16135
0855e32b
NS		 16136 for (ix = 0; ix != count; ix++)
16137 {
16138 unsigned long insn = template[ix];
16139
16140 /* Emit mov pc,rx if bx is not permitted. */
16141 if (htab->fix_v4bx == 1 && (insn & 0x0ffffff0) == 0x012fff10)
16142 insn = (insn & 0xf000000f) | 0x01a0f000;
16143 put_arm_insn (htab, output_bfd, insn, (char *)contents + ix*4);
16144 }
16145}
16146
99059e56
RM		 16147/* Install the special first PLT entry for elf32-arm-nacl. Unlike
16148 other variants, NaCl needs this entry in a static executable's
16149 .iplt too. When we're handling that case, GOT_DISPLACEMENT is
16150 zero. For .iplt really only the last bundle is useful, and .iplt
16151 could have a shorter first entry, with each individual PLT entry's
16152 relative branch calculated differently so it targets the last
16153 bundle instead of the instruction before it (labelled .Lplt_tail
16154 above). But it's simpler to keep the size and layout of PLT0
16155 consistent with the dynamic case, at the cost of some dead code at
16156 the start of .iplt and the one dead store to the stack at the start
16157 of .Lplt_tail. */
16158static void
16159arm_nacl_put_plt0 (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
16160 asection *plt, bfd_vma got_displacement)
16161{
16162 unsigned int i;
16163
16164 put_arm_insn (htab, output_bfd,
16165 elf32_arm_nacl_plt0_entry[0]
16166 | arm_movw_immediate (got_displacement),
16167 plt->contents + 0);
16168 put_arm_insn (htab, output_bfd,
16169 elf32_arm_nacl_plt0_entry[1]
16170 | arm_movt_immediate (got_displacement),
16171 plt->contents + 4);
16172
16173 for (i = 2; i < ARRAY_SIZE (elf32_arm_nacl_plt0_entry); ++i)
16174 put_arm_insn (htab, output_bfd,
16175 elf32_arm_nacl_plt0_entry[i],
16176 plt->contents + (i * 4));
16177}
16178
252b5132
RH		 16179/* Finish up the dynamic sections. */
16180
b34976b6 16181static bfd_boolean
57e8b36a 16182elf32_arm_finish_dynamic_sections (bfd * output_bfd, struct bfd_link_info * info)
252b5132
RH		 16183{
16184 bfd * dynobj;
16185 asection * sgot;
16186 asection * sdyn;
4dfe6ac6
NC		 16187 struct elf32_arm_link_hash_table *htab;
16188
16189 htab = elf32_arm_hash_table (info);
16190 if (htab == NULL)
16191 return FALSE;
252b5132
RH		 16192
16193 dynobj = elf_hash_table (info)->dynobj;
16194
362d30a1 16195 sgot = htab->root.sgotplt;
894891db
NC		 16196 /* A broken linker script might have discarded the dynamic sections.
16197 Catch this here so that we do not seg-fault later on. */
16198 if (sgot != NULL && bfd_is_abs_section (sgot->output_section))
16199 return FALSE;
3d4d4302 16200 sdyn = bfd_get_linker_section (dynobj, ".dynamic");
252b5132
RH		 16201
16202 if (elf_hash_table (info)->dynamic_sections_created)
16203 {
16204 asection *splt;
16205 Elf32_External_Dyn *dyncon, *dynconend;
16206
362d30a1 16207 splt = htab->root.splt;
24a1ba0f 16208 BFD_ASSERT (splt != NULL && sdyn != NULL);
cbc704f3 16209 BFD_ASSERT (htab->symbian_p || sgot != NULL);
252b5132
RH		 16210
16211 dyncon = (Elf32_External_Dyn *) sdyn->contents;
eea6121a 16212 dynconend = (Elf32_External_Dyn *) (sdyn->contents + sdyn->size);
9b485d32 16213
252b5132
RH		 16214 for (; dyncon < dynconend; dyncon++)
16215 {
16216 Elf_Internal_Dyn dyn;
16217 const char * name;
16218 asection * s;
16219
16220 bfd_elf32_swap_dyn_in (dynobj, dyncon, &dyn);
16221
16222 switch (dyn.d_tag)
16223 {
229fcec5
MM		 16224 unsigned int type;
16225
252b5132 16226 default:
7a2b07ff
NS		 16227 if (htab->vxworks_p
16228 && elf_vxworks_finish_dynamic_entry (output_bfd, &dyn))
16229 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
252b5132
RH		 16230 break;
16231
229fcec5
MM		 16232 case DT_HASH:
16233 name = ".hash";
16234 goto get_vma_if_bpabi;
16235 case DT_STRTAB:
16236 name = ".dynstr";
16237 goto get_vma_if_bpabi;
16238 case DT_SYMTAB:
16239 name = ".dynsym";
16240 goto get_vma_if_bpabi;
c0042f5d
MM		 16241 case DT_VERSYM:
16242 name = ".gnu.version";
16243 goto get_vma_if_bpabi;
16244 case DT_VERDEF:
16245 name = ".gnu.version_d";
16246 goto get_vma_if_bpabi;
16247 case DT_VERNEED:
16248 name = ".gnu.version_r";
16249 goto get_vma_if_bpabi;
16250
252b5132 16251 case DT_PLTGOT:
4ade44b7 16252 name = htab->symbian_p ? ".got" : ".got.plt";
252b5132
RH		 16253 goto get_vma;
16254 case DT_JMPREL:
00a97672 16255 name = RELOC_SECTION (htab, ".plt");
252b5132 16256 get_vma:
4ade44b7 16257 s = bfd_get_linker_section (dynobj, name);
05456594
NC		 16258 if (s == NULL)
16259 {
05456594 16260 (*_bfd_error_handler)
4ade44b7 16261 (_("could not find section %s"), name);
05456594
NC		 16262 bfd_set_error (bfd_error_invalid_operation);
16263 return FALSE;
16264 }
229fcec5 16265 if (!htab->symbian_p)
4ade44b7 16266 dyn.d_un.d_ptr = s->output_section->vma + s->output_offset;
229fcec5
MM		 16267 else
16268 /* In the BPABI, tags in the PT_DYNAMIC section point
16269 at the file offset, not the memory address, for the
16270 convenience of the post linker. */
4ade44b7 16271 dyn.d_un.d_ptr = s->output_section->filepos + s->output_offset;
252b5132
RH		 16272 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16273 break;
16274
229fcec5
MM		 16275 get_vma_if_bpabi:
16276 if (htab->symbian_p)
16277 goto get_vma;
16278 break;
16279
252b5132 16280 case DT_PLTRELSZ:
362d30a1 16281 s = htab->root.srelplt;
252b5132 16282 BFD_ASSERT (s != NULL);
eea6121a 16283 dyn.d_un.d_val = s->size;
252b5132
RH		 16284 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16285 break;
906e58ca 16286
252b5132 16287 case DT_RELSZ:
00a97672 16288 case DT_RELASZ:
229fcec5
MM		 16289 if (!htab->symbian_p)
16290 {
16291 /* My reading of the SVR4 ABI indicates that the
16292 procedure linkage table relocs (DT_JMPREL) should be
16293 included in the overall relocs (DT_REL). This is
16294 what Solaris does. However, UnixWare can not handle
16295 that case. Therefore, we override the DT_RELSZ entry
16296 here to make it not include the JMPREL relocs. Since
00a97672 16297 the linker script arranges for .rel(a).plt to follow all
229fcec5
MM		 16298 other relocation sections, we don't have to worry
16299 about changing the DT_REL entry. */
362d30a1 16300 s = htab->root.srelplt;
229fcec5
MM		 16301 if (s != NULL)
16302 dyn.d_un.d_val -= s->size;
16303 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16304 break;
16305 }
8029a119 16306 /* Fall through. */
229fcec5
MM		 16307
16308 case DT_REL:
16309 case DT_RELA:
229fcec5
MM		 16310 /* In the BPABI, the DT_REL tag must point at the file
16311 offset, not the VMA, of the first relocation
16312 section. So, we use code similar to that in
16313 elflink.c, but do not check for SHF_ALLOC on the
16314 relcoation section, since relocations sections are
16315 never allocated under the BPABI. The comments above
16316 about Unixware notwithstanding, we include all of the
16317 relocations here. */
16318 if (htab->symbian_p)
16319 {
16320 unsigned int i;
16321 type = ((dyn.d_tag == DT_REL || dyn.d_tag == DT_RELSZ)
16322 ? SHT_REL : SHT_RELA);
16323 dyn.d_un.d_val = 0;
16324 for (i = 1; i < elf_numsections (output_bfd); i++)
16325 {
906e58ca 16326 Elf_Internal_Shdr *hdr
229fcec5
MM		 16327 = elf_elfsections (output_bfd)[i];
16328 if (hdr->sh_type == type)
16329 {
906e58ca 16330 if (dyn.d_tag == DT_RELSZ
229fcec5
MM		 16331 || dyn.d_tag == DT_RELASZ)
16332 dyn.d_un.d_val += hdr->sh_size;
de52dba4
AM		 16333 else if ((ufile_ptr) hdr->sh_offset
16334 <= dyn.d_un.d_val - 1)
229fcec5
MM		 16335 dyn.d_un.d_val = hdr->sh_offset;
16336 }
16337 }
16338 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16339 }
252b5132 16340 break;
88f7bcd5 16341
0855e32b 16342 case DT_TLSDESC_PLT:
99059e56 16343 s = htab->root.splt;
0855e32b
NS		 16344 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
16345 + htab->dt_tlsdesc_plt);
16346 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16347 break;
16348
16349 case DT_TLSDESC_GOT:
99059e56 16350 s = htab->root.sgot;
0855e32b 16351 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
99059e56 16352 + htab->dt_tlsdesc_got);
0855e32b
NS		 16353 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16354 break;
16355
88f7bcd5
NC		 16356 /* Set the bottom bit of DT_INIT/FINI if the
16357 corresponding function is Thumb. */
16358 case DT_INIT:
16359 name = info->init_function;
16360 goto get_sym;
16361 case DT_FINI:
16362 name = info->fini_function;
16363 get_sym:
16364 /* If it wasn't set by elf_bfd_final_link
4cc11e76 16365 then there is nothing to adjust. */
88f7bcd5
NC		 16366 if (dyn.d_un.d_val != 0)
16367 {
16368 struct elf_link_hash_entry * eh;
16369
16370 eh = elf_link_hash_lookup (elf_hash_table (info), name,
b34976b6 16371 FALSE, FALSE, TRUE);
39d911fc
TP		 16372 if (eh != NULL
16373 && ARM_GET_SYM_BRANCH_TYPE (eh->target_internal)
16374 == ST_BRANCH_TO_THUMB)
88f7bcd5
NC		 16375 {
16376 dyn.d_un.d_val |= 1;
b34976b6 16377 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
88f7bcd5
NC		 16378 }
16379 }
16380 break;
252b5132
RH		 16381 }
16382 }
16383
24a1ba0f 16384 /* Fill in the first entry in the procedure linkage table. */
4dfe6ac6 16385 if (splt->size > 0 && htab->plt_header_size)
f7a74f8c 16386 {
00a97672
RS		 16387 const bfd_vma *plt0_entry;
16388 bfd_vma got_address, plt_address, got_displacement;
16389
16390 /* Calculate the addresses of the GOT and PLT. */
16391 got_address = sgot->output_section->vma + sgot->output_offset;
16392 plt_address = splt->output_section->vma + splt->output_offset;
16393
16394 if (htab->vxworks_p)
16395 {
16396 /* The VxWorks GOT is relocated by the dynamic linker.
16397 Therefore, we must emit relocations rather than simply
16398 computing the values now. */
16399 Elf_Internal_Rela rel;
16400
16401 plt0_entry = elf32_arm_vxworks_exec_plt0_entry;
52ab56c2
PB		 16402 put_arm_insn (htab, output_bfd, plt0_entry[0],
16403 splt->contents + 0);
16404 put_arm_insn (htab, output_bfd, plt0_entry[1],
16405 splt->contents + 4);
16406 put_arm_insn (htab, output_bfd, plt0_entry[2],
16407 splt->contents + 8);
00a97672
RS		 16408 bfd_put_32 (output_bfd, got_address, splt->contents + 12);
16409
8029a119 16410 /* Generate a relocation for _GLOBAL_OFFSET_TABLE_. */
00a97672
RS		 16411 rel.r_offset = plt_address + 12;
16412 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
16413 rel.r_addend = 0;
16414 SWAP_RELOC_OUT (htab) (output_bfd, &rel,
16415 htab->srelplt2->contents);
16416 }
b38cadfb 16417 else if (htab->nacl_p)
99059e56
RM		 16418 arm_nacl_put_plt0 (htab, output_bfd, splt,
16419 got_address + 8 - (plt_address + 16));
eed94f8f
NC		 16420 else if (using_thumb_only (htab))
16421 {
16422 got_displacement = got_address - (plt_address + 12);
16423
16424 plt0_entry = elf32_thumb2_plt0_entry;
16425 put_arm_insn (htab, output_bfd, plt0_entry[0],
16426 splt->contents + 0);
16427 put_arm_insn (htab, output_bfd, plt0_entry[1],
16428 splt->contents + 4);
16429 put_arm_insn (htab, output_bfd, plt0_entry[2],
16430 splt->contents + 8);
16431
16432 bfd_put_32 (output_bfd, got_displacement, splt->contents + 12);
16433 }
00a97672
RS		 16434 else
16435 {
16436 got_displacement = got_address - (plt_address + 16);
16437
16438 plt0_entry = elf32_arm_plt0_entry;
52ab56c2
PB		 16439 put_arm_insn (htab, output_bfd, plt0_entry[0],
16440 splt->contents + 0);
16441 put_arm_insn (htab, output_bfd, plt0_entry[1],
16442 splt->contents + 4);
16443 put_arm_insn (htab, output_bfd, plt0_entry[2],
16444 splt->contents + 8);
16445 put_arm_insn (htab, output_bfd, plt0_entry[3],
16446 splt->contents + 12);
5e681ec4 16447
5e681ec4 16448#ifdef FOUR_WORD_PLT
00a97672
RS		 16449 /* The displacement value goes in the otherwise-unused
16450 last word of the second entry. */
16451 bfd_put_32 (output_bfd, got_displacement, splt->contents + 28);
5e681ec4 16452#else
00a97672 16453 bfd_put_32 (output_bfd, got_displacement, splt->contents + 16);
5e681ec4 16454#endif
00a97672 16455 }
f7a74f8c 16456 }
252b5132
RH		 16457
16458 /* UnixWare sets the entsize of .plt to 4, although that doesn't
16459 really seem like the right value. */
74541ad4
AM		 16460 if (splt->output_section->owner == output_bfd)
16461 elf_section_data (splt->output_section)->this_hdr.sh_entsize = 4;
00a97672 16462
0855e32b
NS		 16463 if (htab->dt_tlsdesc_plt)
16464 {
16465 bfd_vma got_address
16466 = sgot->output_section->vma + sgot->output_offset;
16467 bfd_vma gotplt_address = (htab->root.sgot->output_section->vma
16468 + htab->root.sgot->output_offset);
16469 bfd_vma plt_address
16470 = splt->output_section->vma + splt->output_offset;
16471
b38cadfb 16472 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 16473 splt->contents + htab->dt_tlsdesc_plt,
16474 dl_tlsdesc_lazy_trampoline, 6);
16475
16476 bfd_put_32 (output_bfd,
16477 gotplt_address + htab->dt_tlsdesc_got
16478 - (plt_address + htab->dt_tlsdesc_plt)
16479 - dl_tlsdesc_lazy_trampoline[6],
16480 splt->contents + htab->dt_tlsdesc_plt + 24);
16481 bfd_put_32 (output_bfd,
16482 got_address - (plt_address + htab->dt_tlsdesc_plt)
16483 - dl_tlsdesc_lazy_trampoline[7],
16484 splt->contents + htab->dt_tlsdesc_plt + 24 + 4);
16485 }
16486
16487 if (htab->tls_trampoline)
16488 {
b38cadfb 16489 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 16490 splt->contents + htab->tls_trampoline,
16491 tls_trampoline, 3);
16492#ifdef FOUR_WORD_PLT
16493 bfd_put_32 (output_bfd, 0x00000000,
16494 splt->contents + htab->tls_trampoline + 12);
b38cadfb 16495#endif
0855e32b
NS		 16496 }
16497
0e1862bb
L		 16498 if (htab->vxworks_p
16499 && !bfd_link_pic (info)
16500 && htab->root.splt->size > 0)
00a97672
RS		 16501 {
16502 /* Correct the .rel(a).plt.unloaded relocations. They will have
16503 incorrect symbol indexes. */
16504 int num_plts;
eed62c48 16505 unsigned char *p;
00a97672 16506
362d30a1 16507 num_plts = ((htab->root.splt->size - htab->plt_header_size)
00a97672
RS		 16508 / htab->plt_entry_size);
16509 p = htab->srelplt2->contents + RELOC_SIZE (htab);
16510
16511 for (; num_plts; num_plts--)
16512 {
16513 Elf_Internal_Rela rel;
16514
16515 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
16516 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
16517 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
16518 p += RELOC_SIZE (htab);
16519
16520 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
16521 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
16522 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
16523 p += RELOC_SIZE (htab);
16524 }
16525 }
252b5132
RH		 16526 }
16527
99059e56
RM		 16528 if (htab->nacl_p && htab->root.iplt != NULL && htab->root.iplt->size > 0)
16529 /* NaCl uses a special first entry in .iplt too. */
16530 arm_nacl_put_plt0 (htab, output_bfd, htab->root.iplt, 0);
16531
252b5132 16532 /* Fill in the first three entries in the global offset table. */
229fcec5 16533 if (sgot)
252b5132 16534 {
229fcec5
MM		 16535 if (sgot->size > 0)
16536 {
16537 if (sdyn == NULL)
16538 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents);
16539 else
16540 bfd_put_32 (output_bfd,
16541 sdyn->output_section->vma + sdyn->output_offset,
16542 sgot->contents);
16543 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 4);
16544 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 8);
16545 }
252b5132 16546
229fcec5
MM		 16547 elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4;
16548 }
252b5132 16549
b34976b6 16550 return TRUE;
252b5132
RH		 16551}
16552
ba96a88f 16553static void
57e8b36a 16554elf32_arm_post_process_headers (bfd * abfd, struct bfd_link_info * link_info ATTRIBUTE_UNUSED)
ba96a88f 16555{
9b485d32 16556 Elf_Internal_Ehdr * i_ehdrp; /* ELF file header, internal form. */
e489d0ae 16557 struct elf32_arm_link_hash_table *globals;
ac4c9b04 16558 struct elf_segment_map *m;
ba96a88f
NC		 16559
16560 i_ehdrp = elf_elfheader (abfd);
16561
94a3258f
PB		 16562 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_UNKNOWN)
16563 i_ehdrp->e_ident[EI_OSABI] = ELFOSABI_ARM;
16564 else
7394f108 16565 _bfd_elf_post_process_headers (abfd, link_info);
ba96a88f 16566 i_ehdrp->e_ident[EI_ABIVERSION] = ARM_ELF_ABI_VERSION;
e489d0ae 16567
93204d3a
PB		 16568 if (link_info)
16569 {
16570 globals = elf32_arm_hash_table (link_info);
4dfe6ac6 16571 if (globals != NULL && globals->byteswap_code)
93204d3a
PB		 16572 i_ehdrp->e_flags |= EF_ARM_BE8;
16573 }
3bfcb652
NC		 16574
16575 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_VER5
16576 && ((i_ehdrp->e_type == ET_DYN) || (i_ehdrp->e_type == ET_EXEC)))
16577 {
16578 int abi = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_ABI_VFP_args);
5c294fee 16579 if (abi == AEABI_VFP_args_vfp)
3bfcb652
NC		 16580 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_HARD;
16581 else
16582 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_SOFT;
16583 }
ac4c9b04
MG		 16584
16585 /* Scan segment to set p_flags attribute if it contains only sections with
f0728ee3 16586 SHF_ARM_PURECODE flag. */
ac4c9b04
MG		 16587 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
16588 {
16589 unsigned int j;
16590
16591 if (m->count == 0)
16592 continue;
16593 for (j = 0; j < m->count; j++)
16594 {
f0728ee3 16595 if (!(elf_section_flags (m->sections[j]) & SHF_ARM_PURECODE))
ac4c9b04
MG		 16596 break;
16597 }
16598 if (j == m->count)
16599 {
16600 m->p_flags = PF_X;
16601 m->p_flags_valid = 1;
16602 }
16603 }
ba96a88f
NC		 16604}
16605
99e4ae17 16606static enum elf_reloc_type_class
7e612e98
AM		 16607elf32_arm_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UNUSED,
16608 const asection *rel_sec ATTRIBUTE_UNUSED,
16609 const Elf_Internal_Rela *rela)
99e4ae17 16610{
f51e552e 16611 switch ((int) ELF32_R_TYPE (rela->r_info))
99e4ae17
AJ		 16612 {
16613 case R_ARM_RELATIVE:
16614 return reloc_class_relative;
16615 case R_ARM_JUMP_SLOT:
16616 return reloc_class_plt;
16617 case R_ARM_COPY:
16618 return reloc_class_copy;
109575d7
JW		 16619 case R_ARM_IRELATIVE:
16620 return reloc_class_ifunc;
99e4ae17
AJ		 16621 default:
16622 return reloc_class_normal;
16623 }
16624}
16625
e489d0ae 16626static void
57e8b36a 16627elf32_arm_final_write_processing (bfd *abfd, bfd_boolean linker ATTRIBUTE_UNUSED)
e16bb312 16628{
5a6c6817 16629 bfd_arm_update_notes (abfd, ARM_NOTE_SECTION);
e16bb312
NC		 16630}
16631
40a18ebd
NC		 16632/* Return TRUE if this is an unwinding table entry. */
16633
16634static bfd_boolean
16635is_arm_elf_unwind_section_name (bfd * abfd ATTRIBUTE_UNUSED, const char * name)
16636{
0112cd26
NC		 16637 return (CONST_STRNEQ (name, ELF_STRING_ARM_unwind)
16638 || CONST_STRNEQ (name, ELF_STRING_ARM_unwind_once));
40a18ebd
NC		 16639}
16640
16641
16642/* Set the type and flags for an ARM section. We do this by
16643 the section name, which is a hack, but ought to work. */
16644
16645static bfd_boolean
16646elf32_arm_fake_sections (bfd * abfd, Elf_Internal_Shdr * hdr, asection * sec)
16647{
16648 const char * name;
16649
16650 name = bfd_get_section_name (abfd, sec);
16651
16652 if (is_arm_elf_unwind_section_name (abfd, name))
16653 {
16654 hdr->sh_type = SHT_ARM_EXIDX;
16655 hdr->sh_flags |= SHF_LINK_ORDER;
16656 }
ac4c9b04 16657
f0728ee3
AV		 16658 if (sec->flags & SEC_ELF_PURECODE)
16659 hdr->sh_flags |= SHF_ARM_PURECODE;
ac4c9b04 16660
40a18ebd
NC		 16661 return TRUE;
16662}
16663
6dc132d9
L		 16664/* Handle an ARM specific section when reading an object file. This is
16665 called when bfd_section_from_shdr finds a section with an unknown
16666 type. */
40a18ebd
NC		 16667
16668static bfd_boolean
16669elf32_arm_section_from_shdr (bfd *abfd,
16670 Elf_Internal_Shdr * hdr,
6dc132d9
L		 16671 const char *name,
16672 int shindex)
40a18ebd
NC		 16673{
16674 /* There ought to be a place to keep ELF backend specific flags, but
16675 at the moment there isn't one. We just keep track of the
16676 sections by their name, instead. Fortunately, the ABI gives
16677 names for all the ARM specific sections, so we will probably get
16678 away with this. */
16679 switch (hdr->sh_type)
16680 {
16681 case SHT_ARM_EXIDX:
0951f019
RE		 16682 case SHT_ARM_PREEMPTMAP:
16683 case SHT_ARM_ATTRIBUTES:
40a18ebd
NC		 16684 break;
16685
16686 default:
16687 return FALSE;
16688 }
16689
6dc132d9 16690 if (! _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex))
40a18ebd
NC		 16691 return FALSE;
16692
16693 return TRUE;
16694}
e489d0ae 16695
44444f50
NC		 16696static _arm_elf_section_data *
16697get_arm_elf_section_data (asection * sec)
16698{
47b2e99c
JZ		 16699 if (sec && sec->owner && is_arm_elf (sec->owner))
16700 return elf32_arm_section_data (sec);
44444f50
NC		 16701 else
16702 return NULL;
8e3de13a
NC		 16703}
16704
4e617b1e
PB		 16705typedef struct
16706{
57402f1e 16707 void *flaginfo;
4e617b1e 16708 struct bfd_link_info *info;
91a5743d
PB		 16709 asection *sec;
16710 int sec_shndx;
6e0b88f1
AM		 16711 int (*func) (void *, const char *, Elf_Internal_Sym *,
16712 asection *, struct elf_link_hash_entry *);
4e617b1e
PB		 16713} output_arch_syminfo;
16714
16715enum map_symbol_type
16716{
16717 ARM_MAP_ARM,
16718 ARM_MAP_THUMB,
16719 ARM_MAP_DATA
16720};
16721
16722
7413f23f 16723/* Output a single mapping symbol. */
4e617b1e
PB		 16724
16725static bfd_boolean
7413f23f
DJ		 16726elf32_arm_output_map_sym (output_arch_syminfo *osi,
16727 enum map_symbol_type type,
16728 bfd_vma offset)
4e617b1e
PB		 16729{
16730 static const char *names[3] = {"$a", "$t", "$d"};
4e617b1e
PB		 16731 Elf_Internal_Sym sym;
16732
91a5743d
PB		 16733 sym.st_value = osi->sec->output_section->vma
16734 + osi->sec->output_offset
16735 + offset;
4e617b1e
PB		 16736 sym.st_size = 0;
16737 sym.st_other = 0;
16738 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
91a5743d 16739 sym.st_shndx = osi->sec_shndx;
35fc36a8 16740 sym.st_target_internal = 0;
fe33d2fa 16741 elf32_arm_section_map_add (osi->sec, names[type][1], offset);
57402f1e 16742 return osi->func (osi->flaginfo, names[type], &sym, osi->sec, NULL) == 1;
4e617b1e
PB		 16743}
16744
34e77a92
RS		 16745/* Output mapping symbols for the PLT entry described by ROOT_PLT and ARM_PLT.
16746 IS_IPLT_ENTRY_P says whether the PLT is in .iplt rather than .plt. */
4e617b1e
PB		 16747
16748static bfd_boolean
34e77a92
RS		 16749elf32_arm_output_plt_map_1 (output_arch_syminfo *osi,
16750 bfd_boolean is_iplt_entry_p,
16751 union gotplt_union *root_plt,
16752 struct arm_plt_info *arm_plt)
4e617b1e 16753{
4e617b1e 16754 struct elf32_arm_link_hash_table *htab;
34e77a92 16755 bfd_vma addr, plt_header_size;
4e617b1e 16756
34e77a92 16757 if (root_plt->offset == (bfd_vma) -1)
4e617b1e
PB		 16758 return TRUE;
16759
4dfe6ac6
NC		 16760 htab = elf32_arm_hash_table (osi->info);
16761 if (htab == NULL)
16762 return FALSE;
16763
34e77a92
RS		 16764 if (is_iplt_entry_p)
16765 {
16766 osi->sec = htab->root.iplt;
16767 plt_header_size = 0;
16768 }
16769 else
16770 {
16771 osi->sec = htab->root.splt;
16772 plt_header_size = htab->plt_header_size;
16773 }
16774 osi->sec_shndx = (_bfd_elf_section_from_bfd_section
16775 (osi->info->output_bfd, osi->sec->output_section));
16776
16777 addr = root_plt->offset & -2;
4e617b1e
PB		 16778 if (htab->symbian_p)
16779 {
7413f23f 16780 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 16781 return FALSE;
7413f23f 16782 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 4))
4e617b1e
PB		 16783 return FALSE;
16784 }
16785 else if (htab->vxworks_p)
16786 {
7413f23f 16787 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 16788 return FALSE;
7413f23f 16789 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 8))
4e617b1e 16790 return FALSE;
7413f23f 16791 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr + 12))
4e617b1e 16792 return FALSE;
7413f23f 16793 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 20))
4e617b1e
PB		 16794 return FALSE;
16795 }
b38cadfb
NC		 16796 else if (htab->nacl_p)
16797 {
16798 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
16799 return FALSE;
16800 }
eed94f8f
NC		 16801 else if (using_thumb_only (htab))
16802 {
16803 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr))
16804 return FALSE;
6a631e86 16805 }
4e617b1e
PB		 16806 else
16807 {
34e77a92 16808 bfd_boolean thumb_stub_p;
bd97cb95 16809
34e77a92
RS		 16810 thumb_stub_p = elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt);
16811 if (thumb_stub_p)
4e617b1e 16812 {
7413f23f 16813 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
4e617b1e
PB		 16814 return FALSE;
16815 }
16816#ifdef FOUR_WORD_PLT
7413f23f 16817 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 16818 return FALSE;
7413f23f 16819 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 12))
4e617b1e
PB		 16820 return FALSE;
16821#else
906e58ca 16822 /* A three-word PLT with no Thumb thunk contains only Arm code,
4e617b1e
PB		 16823 so only need to output a mapping symbol for the first PLT entry and
16824 entries with thumb thunks. */
34e77a92 16825 if (thumb_stub_p || addr == plt_header_size)
4e617b1e 16826 {
7413f23f 16827 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e
PB		 16828 return FALSE;
16829 }
16830#endif
16831 }
16832
16833 return TRUE;
16834}
16835
34e77a92
RS		 16836/* Output mapping symbols for PLT entries associated with H. */
16837
16838static bfd_boolean
16839elf32_arm_output_plt_map (struct elf_link_hash_entry *h, void *inf)
16840{
16841 output_arch_syminfo *osi = (output_arch_syminfo *) inf;
16842 struct elf32_arm_link_hash_entry *eh;
16843
16844 if (h->root.type == bfd_link_hash_indirect)
16845 return TRUE;
16846
16847 if (h->root.type == bfd_link_hash_warning)
16848 /* When warning symbols are created, they **replace** the "real"
16849 entry in the hash table, thus we never get to see the real
16850 symbol in a hash traversal. So look at it now. */
16851 h = (struct elf_link_hash_entry *) h->root.u.i.link;
16852
16853 eh = (struct elf32_arm_link_hash_entry *) h;
16854 return elf32_arm_output_plt_map_1 (osi, SYMBOL_CALLS_LOCAL (osi->info, h),
16855 &h->plt, &eh->plt);
16856}
16857
4f4faa4d
TP		 16858/* Bind a veneered symbol to its veneer identified by its hash entry
16859 STUB_ENTRY. The veneered location thus loose its symbol. */
16860
16861static void
16862arm_stub_claim_sym (struct elf32_arm_stub_hash_entry *stub_entry)
16863{
16864 struct elf32_arm_link_hash_entry *hash = stub_entry->h;
16865
16866 BFD_ASSERT (hash);
16867 hash->root.root.u.def.section = stub_entry->stub_sec;
16868 hash->root.root.u.def.value = stub_entry->stub_offset;
16869 hash->root.size = stub_entry->stub_size;
16870}
16871
7413f23f
DJ		 16872/* Output a single local symbol for a generated stub. */
16873
16874static bfd_boolean
16875elf32_arm_output_stub_sym (output_arch_syminfo *osi, const char *name,
16876 bfd_vma offset, bfd_vma size)
16877{
7413f23f
DJ		 16878 Elf_Internal_Sym sym;
16879
7413f23f
DJ		 16880 sym.st_value = osi->sec->output_section->vma
16881 + osi->sec->output_offset
16882 + offset;
16883 sym.st_size = size;
16884 sym.st_other = 0;
16885 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
16886 sym.st_shndx = osi->sec_shndx;
35fc36a8 16887 sym.st_target_internal = 0;
57402f1e 16888 return osi->func (osi->flaginfo, name, &sym, osi->sec, NULL) == 1;
7413f23f 16889}
4e617b1e 16890
da5938a2 16891static bfd_boolean
8029a119
NC		 16892arm_map_one_stub (struct bfd_hash_entry * gen_entry,
16893 void * in_arg)
da5938a2
NC		 16894{
16895 struct elf32_arm_stub_hash_entry *stub_entry;
da5938a2
NC		 16896 asection *stub_sec;
16897 bfd_vma addr;
7413f23f 16898 char *stub_name;
9a008db3 16899 output_arch_syminfo *osi;
d3ce72d0 16900 const insn_sequence *template_sequence;
461a49ca
DJ		 16901 enum stub_insn_type prev_type;
16902 int size;
16903 int i;
16904 enum map_symbol_type sym_type;
da5938a2
NC		 16905
16906 /* Massage our args to the form they really have. */
16907 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
9a008db3 16908 osi = (output_arch_syminfo *) in_arg;
da5938a2 16909
da5938a2
NC		 16910 stub_sec = stub_entry->stub_sec;
16911
16912 /* Ensure this stub is attached to the current section being
7413f23f 16913 processed. */
da5938a2
NC		 16914 if (stub_sec != osi->sec)
16915 return TRUE;
16916
7413f23f 16917 addr = (bfd_vma) stub_entry->stub_offset;
d3ce72d0 16918 template_sequence = stub_entry->stub_template;
4f4faa4d
TP		 16919
16920 if (arm_stub_sym_claimed (stub_entry->stub_type))
16921 arm_stub_claim_sym (stub_entry);
16922 else
7413f23f 16923 {
4f4faa4d
TP		 16924 stub_name = stub_entry->output_name;
16925 switch (template_sequence[0].type)
16926 {
16927 case ARM_TYPE:
16928 if (!elf32_arm_output_stub_sym (osi, stub_name, addr,
16929 stub_entry->stub_size))
16930 return FALSE;
16931 break;
16932 case THUMB16_TYPE:
16933 case THUMB32_TYPE:
16934 if (!elf32_arm_output_stub_sym (osi, stub_name, addr | 1,
16935 stub_entry->stub_size))
16936 return FALSE;
16937 break;
16938 default:
16939 BFD_FAIL ();
16940 return 0;
16941 }
7413f23f 16942 }
da5938a2 16943
461a49ca
DJ		 16944 prev_type = DATA_TYPE;
16945 size = 0;
16946 for (i = 0; i < stub_entry->stub_template_size; i++)
16947 {
d3ce72d0 16948 switch (template_sequence[i].type)
461a49ca
DJ		 16949 {
16950 case ARM_TYPE:
16951 sym_type = ARM_MAP_ARM;
16952 break;
16953
16954 case THUMB16_TYPE:
48229727 16955 case THUMB32_TYPE:
461a49ca
DJ		 16956 sym_type = ARM_MAP_THUMB;
16957 break;
16958
16959 case DATA_TYPE:
16960 sym_type = ARM_MAP_DATA;
16961 break;
16962
16963 default:
16964 BFD_FAIL ();
4e31c731 16965 return FALSE;
461a49ca
DJ		 16966 }
16967
d3ce72d0 16968 if (template_sequence[i].type != prev_type)
461a49ca 16969 {
d3ce72d0 16970 prev_type = template_sequence[i].type;
461a49ca
DJ		 16971 if (!elf32_arm_output_map_sym (osi, sym_type, addr + size))
16972 return FALSE;
16973 }
16974
d3ce72d0 16975 switch (template_sequence[i].type)
461a49ca
DJ		 16976 {
16977 case ARM_TYPE:
48229727 16978 case THUMB32_TYPE:
461a49ca
DJ		 16979 size += 4;
16980 break;
16981
16982 case THUMB16_TYPE:
16983 size += 2;
16984 break;
16985
16986 case DATA_TYPE:
16987 size += 4;
16988 break;
16989
16990 default:
16991 BFD_FAIL ();
4e31c731 16992 return FALSE;
461a49ca
DJ		 16993 }
16994 }
16995
da5938a2
NC		 16996 return TRUE;
16997}
16998
33811162
DG		 16999/* Output mapping symbols for linker generated sections,
17000 and for those data-only sections that do not have a
17001 $d. */
4e617b1e
PB		 17002
17003static bfd_boolean
17004elf32_arm_output_arch_local_syms (bfd *output_bfd,
906e58ca 17005 struct bfd_link_info *info,
57402f1e 17006 void *flaginfo,
6e0b88f1
AM		 17007 int (*func) (void *, const char *,
17008 Elf_Internal_Sym *,
17009 asection *,
17010 struct elf_link_hash_entry *))
4e617b1e
PB		 17011{
17012 output_arch_syminfo osi;
17013 struct elf32_arm_link_hash_table *htab;
91a5743d
PB		 17014 bfd_vma offset;
17015 bfd_size_type size;
33811162 17016 bfd *input_bfd;
4e617b1e
PB		 17017
17018 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 17019 if (htab == NULL)
17020 return FALSE;
17021
906e58ca 17022 check_use_blx (htab);
91a5743d 17023
57402f1e 17024 osi.flaginfo = flaginfo;
4e617b1e
PB		 17025 osi.info = info;
17026 osi.func = func;
906e58ca 17027
33811162
DG		 17028 /* Add a $d mapping symbol to data-only sections that
17029 don't have any mapping symbol. This may result in (harmless) redundant
17030 mapping symbols. */
17031 for (input_bfd = info->input_bfds;
17032 input_bfd != NULL;
c72f2fb2 17033 input_bfd = input_bfd->link.next)
33811162
DG		 17034 {
17035 if ((input_bfd->flags & (BFD_LINKER_CREATED | HAS_SYMS)) == HAS_SYMS)
17036 for (osi.sec = input_bfd->sections;
17037 osi.sec != NULL;
17038 osi.sec = osi.sec->next)
17039 {
17040 if (osi.sec->output_section != NULL
f7dd8c79
DJ		 17041 && ((osi.sec->output_section->flags & (SEC_ALLOC | SEC_CODE))
17042 != 0)
33811162
DG		 17043 && (osi.sec->flags & (SEC_HAS_CONTENTS | SEC_LINKER_CREATED))
17044 == SEC_HAS_CONTENTS
17045 && get_arm_elf_section_data (osi.sec) != NULL
501abfe0 17046 && get_arm_elf_section_data (osi.sec)->mapcount == 0
7d500b83
CL		 17047 && osi.sec->size > 0
17048 && (osi.sec->flags & SEC_EXCLUDE) == 0)
33811162
DG		 17049 {
17050 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17051 (output_bfd, osi.sec->output_section);
17052 if (osi.sec_shndx != (int)SHN_BAD)
17053 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 0);
17054 }
17055 }
17056 }
17057
91a5743d
PB		 17058 /* ARM->Thumb glue. */
17059 if (htab->arm_glue_size > 0)
17060 {
3d4d4302
AM		 17061 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
17062 ARM2THUMB_GLUE_SECTION_NAME);
91a5743d
PB		 17063
17064 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17065 (output_bfd, osi.sec->output_section);
0e1862bb 17066 if (bfd_link_pic (info) || htab->root.is_relocatable_executable
91a5743d
PB		 17067 || htab->pic_veneer)
17068 size = ARM2THUMB_PIC_GLUE_SIZE;
17069 else if (htab->use_blx)
17070 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
17071 else
17072 size = ARM2THUMB_STATIC_GLUE_SIZE;
4e617b1e 17073
91a5743d
PB		 17074 for (offset = 0; offset < htab->arm_glue_size; offset += size)
17075 {
7413f23f
DJ		 17076 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset);
17077 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, offset + size - 4);
91a5743d
PB		 17078 }
17079 }
17080
17081 /* Thumb->ARM glue. */
17082 if (htab->thumb_glue_size > 0)
17083 {
3d4d4302
AM		 17084 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
17085 THUMB2ARM_GLUE_SECTION_NAME);
91a5743d
PB		 17086
17087 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17088 (output_bfd, osi.sec->output_section);
17089 size = THUMB2ARM_GLUE_SIZE;
17090
17091 for (offset = 0; offset < htab->thumb_glue_size; offset += size)
17092 {
7413f23f
DJ		 17093 elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, offset);
17094 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset + 4);
91a5743d
PB		 17095 }
17096 }
17097
845b51d6
PB		 17098 /* ARMv4 BX veneers. */
17099 if (htab->bx_glue_size > 0)
17100 {
3d4d4302
AM		 17101 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
17102 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 17103
17104 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17105 (output_bfd, osi.sec->output_section);
17106
7413f23f 17107 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0);
845b51d6
PB		 17108 }
17109
8029a119
NC		 17110 /* Long calls stubs. */
17111 if (htab->stub_bfd && htab->stub_bfd->sections)
17112 {
da5938a2 17113 asection* stub_sec;
8029a119 17114
da5938a2
NC		 17115 for (stub_sec = htab->stub_bfd->sections;
17116 stub_sec != NULL;
8029a119
NC		 17117 stub_sec = stub_sec->next)
17118 {
17119 /* Ignore non-stub sections. */
17120 if (!strstr (stub_sec->name, STUB_SUFFIX))
17121 continue;
da5938a2 17122
8029a119 17123 osi.sec = stub_sec;
da5938a2 17124
8029a119
NC		 17125 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17126 (output_bfd, osi.sec->output_section);
da5938a2 17127
8029a119
NC		 17128 bfd_hash_traverse (&htab->stub_hash_table, arm_map_one_stub, &osi);
17129 }
17130 }
da5938a2 17131
91a5743d 17132 /* Finally, output mapping symbols for the PLT. */
34e77a92 17133 if (htab->root.splt && htab->root.splt->size > 0)
4e617b1e 17134 {
34e77a92
RS		 17135 osi.sec = htab->root.splt;
17136 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
17137 (output_bfd, osi.sec->output_section));
17138
17139 /* Output mapping symbols for the plt header. SymbianOS does not have a
17140 plt header. */
17141 if (htab->vxworks_p)
17142 {
17143 /* VxWorks shared libraries have no PLT header. */
0e1862bb 17144 if (!bfd_link_pic (info))
34e77a92
RS		 17145 {
17146 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
17147 return FALSE;
17148 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
17149 return FALSE;
17150 }
17151 }
b38cadfb
NC		 17152 else if (htab->nacl_p)
17153 {
17154 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
17155 return FALSE;
17156 }
eed94f8f
NC		 17157 else if (using_thumb_only (htab))
17158 {
17159 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 0))
17160 return FALSE;
17161 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
17162 return FALSE;
17163 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 16))
17164 return FALSE;
17165 }
34e77a92 17166 else if (!htab->symbian_p)
4e617b1e 17167 {
7413f23f 17168 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
4e617b1e 17169 return FALSE;
34e77a92
RS		 17170#ifndef FOUR_WORD_PLT
17171 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 16))
4e617b1e 17172 return FALSE;
34e77a92 17173#endif
4e617b1e
PB		 17174 }
17175 }
99059e56
RM		 17176 if (htab->nacl_p && htab->root.iplt && htab->root.iplt->size > 0)
17177 {
17178 /* NaCl uses a special first entry in .iplt too. */
17179 osi.sec = htab->root.iplt;
17180 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
17181 (output_bfd, osi.sec->output_section));
17182 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
17183 return FALSE;
17184 }
34e77a92
RS		 17185 if ((htab->root.splt && htab->root.splt->size > 0)
17186 || (htab->root.iplt && htab->root.iplt->size > 0))
4e617b1e 17187 {
34e77a92
RS		 17188 elf_link_hash_traverse (&htab->root, elf32_arm_output_plt_map, &osi);
17189 for (input_bfd = info->input_bfds;
17190 input_bfd != NULL;
c72f2fb2 17191 input_bfd = input_bfd->link.next)
34e77a92
RS		 17192 {
17193 struct arm_local_iplt_info **local_iplt;
17194 unsigned int i, num_syms;
4e617b1e 17195
34e77a92
RS		 17196 local_iplt = elf32_arm_local_iplt (input_bfd);
17197 if (local_iplt != NULL)
17198 {
17199 num_syms = elf_symtab_hdr (input_bfd).sh_info;
17200 for (i = 0; i < num_syms; i++)
17201 if (local_iplt[i] != NULL
17202 && !elf32_arm_output_plt_map_1 (&osi, TRUE,
17203 &local_iplt[i]->root,
17204 &local_iplt[i]->arm))
17205 return FALSE;
17206 }
17207 }
17208 }
0855e32b
NS		 17209 if (htab->dt_tlsdesc_plt != 0)
17210 {
17211 /* Mapping symbols for the lazy tls trampoline. */
17212 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->dt_tlsdesc_plt))
17213 return FALSE;
b38cadfb 17214
0855e32b
NS		 17215 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
17216 htab->dt_tlsdesc_plt + 24))
17217 return FALSE;
17218 }
17219 if (htab->tls_trampoline != 0)
17220 {
17221 /* Mapping symbols for the tls trampoline. */
17222 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->tls_trampoline))
17223 return FALSE;
17224#ifdef FOUR_WORD_PLT
17225 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
17226 htab->tls_trampoline + 12))
17227 return FALSE;
b38cadfb 17228#endif
0855e32b 17229 }
b38cadfb 17230
4e617b1e
PB		 17231 return TRUE;
17232}
17233
54ddd295
TP		 17234/* Filter normal symbols of CMSE entry functions of ABFD to include in
17235 the import library. All SYMCOUNT symbols of ABFD can be examined
17236 from their pointers in SYMS. Pointers of symbols to keep should be
17237 stored continuously at the beginning of that array.
17238
17239 Returns the number of symbols to keep. */
17240
17241static unsigned int
17242elf32_arm_filter_cmse_symbols (bfd *abfd ATTRIBUTE_UNUSED,
17243 struct bfd_link_info *info,
17244 asymbol **syms, long symcount)
17245{
17246 size_t maxnamelen;
17247 char *cmse_name;
17248 long src_count, dst_count = 0;
17249 struct elf32_arm_link_hash_table *htab;
17250
17251 htab = elf32_arm_hash_table (info);
17252 if (!htab->stub_bfd || !htab->stub_bfd->sections)
17253 symcount = 0;
17254
17255 maxnamelen = 128;
17256 cmse_name = (char *) bfd_malloc (maxnamelen);
17257 for (src_count = 0; src_count < symcount; src_count++)
17258 {
17259 struct elf32_arm_link_hash_entry *cmse_hash;
17260 asymbol *sym;
17261 flagword flags;
17262 char *name;
17263 size_t namelen;
17264
17265 sym = syms[src_count];
17266 flags = sym->flags;
17267 name = (char *) bfd_asymbol_name (sym);
17268
17269 if ((flags & BSF_FUNCTION) != BSF_FUNCTION)
17270 continue;
17271 if (!(flags & (BSF_GLOBAL | BSF_WEAK)))
17272 continue;
17273
17274 namelen = strlen (name) + sizeof (CMSE_PREFIX) + 1;
17275 if (namelen > maxnamelen)
17276 {
17277 cmse_name = (char *)
17278 bfd_realloc (cmse_name, namelen);
17279 maxnamelen = namelen;
17280 }
17281 snprintf (cmse_name, maxnamelen, "%s%s", CMSE_PREFIX, name);
17282 cmse_hash = (struct elf32_arm_link_hash_entry *)
17283 elf_link_hash_lookup (&(htab)->root, cmse_name, FALSE, FALSE, TRUE);
17284
17285 if (!cmse_hash
17286 || (cmse_hash->root.root.type != bfd_link_hash_defined
17287 && cmse_hash->root.root.type != bfd_link_hash_defweak)
17288 || cmse_hash->root.type != STT_FUNC)
17289 continue;
17290
17291 if (!ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
17292 continue;
17293
17294 syms[dst_count++] = sym;
17295 }
17296 free (cmse_name);
17297
17298 syms[dst_count] = NULL;
17299
17300 return dst_count;
17301}
17302
17303/* Filter symbols of ABFD to include in the import library. All
17304 SYMCOUNT symbols of ABFD can be examined from their pointers in
17305 SYMS. Pointers of symbols to keep should be stored continuously at
17306 the beginning of that array.
17307
17308 Returns the number of symbols to keep. */
17309
17310static unsigned int
17311elf32_arm_filter_implib_symbols (bfd *abfd ATTRIBUTE_UNUSED,
17312 struct bfd_link_info *info,
17313 asymbol **syms, long symcount)
17314{
17315 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
17316
17317 if (globals->cmse_implib)
17318 return elf32_arm_filter_cmse_symbols (abfd, info, syms, symcount);
17319 else
17320 return _bfd_elf_filter_global_symbols (abfd, info, syms, symcount);
17321}
17322
e489d0ae
PB		 17323/* Allocate target specific section data. */
17324
17325static bfd_boolean
17326elf32_arm_new_section_hook (bfd *abfd, asection *sec)
17327{
f592407e
AM		 17328 if (!sec->used_by_bfd)
17329 {
17330 _arm_elf_section_data *sdata;
17331 bfd_size_type amt = sizeof (*sdata);
e489d0ae 17332
21d799b5 17333 sdata = (_arm_elf_section_data *) bfd_zalloc (abfd, amt);
f592407e
AM		 17334 if (sdata == NULL)
17335 return FALSE;
17336 sec->used_by_bfd = sdata;
17337 }
e489d0ae
PB		 17338
17339 return _bfd_elf_new_section_hook (abfd, sec);
17340}
17341
17342
17343/* Used to order a list of mapping symbols by address. */
17344
17345static int
17346elf32_arm_compare_mapping (const void * a, const void * b)
17347{
7f6a71ff
JM		 17348 const elf32_arm_section_map *amap = (const elf32_arm_section_map *) a;
17349 const elf32_arm_section_map *bmap = (const elf32_arm_section_map *) b;
17350
17351 if (amap->vma > bmap->vma)
17352 return 1;
17353 else if (amap->vma < bmap->vma)
17354 return -1;
17355 else if (amap->type > bmap->type)
17356 /* Ensure results do not depend on the host qsort for objects with
17357 multiple mapping symbols at the same address by sorting on type
17358 after vma. */
17359 return 1;
17360 else if (amap->type < bmap->type)
17361 return -1;
17362 else
17363 return 0;
e489d0ae
PB		 17364}
17365
2468f9c9
PB		 17366/* Add OFFSET to lower 31 bits of ADDR, leaving other bits unmodified. */
17367
17368static unsigned long
17369offset_prel31 (unsigned long addr, bfd_vma offset)
17370{
17371 return (addr & ~0x7ffffffful) | ((addr + offset) & 0x7ffffffful);
17372}
17373
17374/* Copy an .ARM.exidx table entry, adding OFFSET to (applied) PREL31
17375 relocations. */
17376
17377static void
17378copy_exidx_entry (bfd *output_bfd, bfd_byte *to, bfd_byte *from, bfd_vma offset)
17379{
17380 unsigned long first_word = bfd_get_32 (output_bfd, from);
17381 unsigned long second_word = bfd_get_32 (output_bfd, from + 4);
b38cadfb 17382
2468f9c9
PB		 17383 /* High bit of first word is supposed to be zero. */
17384 if ((first_word & 0x80000000ul) == 0)
17385 first_word = offset_prel31 (first_word, offset);
b38cadfb 17386
2468f9c9
PB		 17387 /* If the high bit of the first word is clear, and the bit pattern is not 0x1
17388 (EXIDX_CANTUNWIND), this is an offset to an .ARM.extab entry. */
17389 if ((second_word != 0x1) && ((second_word & 0x80000000ul) == 0))
17390 second_word = offset_prel31 (second_word, offset);
b38cadfb 17391
2468f9c9
PB		 17392 bfd_put_32 (output_bfd, first_word, to);
17393 bfd_put_32 (output_bfd, second_word, to + 4);
17394}
e489d0ae 17395
48229727
JB		 17396/* Data for make_branch_to_a8_stub(). */
17397
b38cadfb
NC		 17398struct a8_branch_to_stub_data
17399{
48229727
JB		 17400 asection *writing_section;
17401 bfd_byte *contents;
17402};
17403
17404
17405/* Helper to insert branches to Cortex-A8 erratum stubs in the right
17406 places for a particular section. */
17407
17408static bfd_boolean
17409make_branch_to_a8_stub (struct bfd_hash_entry *gen_entry,
99059e56 17410 void *in_arg)
48229727
JB		 17411{
17412 struct elf32_arm_stub_hash_entry *stub_entry;
17413 struct a8_branch_to_stub_data *data;
17414 bfd_byte *contents;
17415 unsigned long branch_insn;
17416 bfd_vma veneered_insn_loc, veneer_entry_loc;
17417 bfd_signed_vma branch_offset;
17418 bfd *abfd;
8d9d9490 17419 unsigned int loc;
48229727
JB		 17420
17421 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
17422 data = (struct a8_branch_to_stub_data *) in_arg;
17423
17424 if (stub_entry->target_section != data->writing_section
4563a860 17425 || stub_entry->stub_type < arm_stub_a8_veneer_lwm)
48229727
JB		 17426 return TRUE;
17427
17428 contents = data->contents;
17429
8d9d9490
TP		 17430 /* We use target_section as Cortex-A8 erratum workaround stubs are only
17431 generated when both source and target are in the same section. */
48229727
JB		 17432 veneered_insn_loc = stub_entry->target_section->output_section->vma
17433 + stub_entry->target_section->output_offset
8d9d9490 17434 + stub_entry->source_value;
48229727
JB		 17435
17436 veneer_entry_loc = stub_entry->stub_sec->output_section->vma
17437 + stub_entry->stub_sec->output_offset
17438 + stub_entry->stub_offset;
17439
17440 if (stub_entry->stub_type == arm_stub_a8_veneer_blx)
17441 veneered_insn_loc &= ~3u;
17442
17443 branch_offset = veneer_entry_loc - veneered_insn_loc - 4;
17444
17445 abfd = stub_entry->target_section->owner;
8d9d9490 17446 loc = stub_entry->source_value;
48229727
JB		 17447
17448 /* We attempt to avoid this condition by setting stubs_always_after_branch
17449 in elf32_arm_size_stubs if we've enabled the Cortex-A8 erratum workaround.
17450 This check is just to be on the safe side... */
17451 if ((veneered_insn_loc & ~0xfff) == (veneer_entry_loc & ~0xfff))
17452 {
17453 (*_bfd_error_handler) (_("%B: error: Cortex-A8 erratum stub is "
17454 "allocated in unsafe location"), abfd);
17455 return FALSE;
17456 }
17457
17458 switch (stub_entry->stub_type)
17459 {
17460 case arm_stub_a8_veneer_b:
17461 case arm_stub_a8_veneer_b_cond:
17462 branch_insn = 0xf0009000;
17463 goto jump24;
17464
17465 case arm_stub_a8_veneer_blx:
17466 branch_insn = 0xf000e800;
17467 goto jump24;
17468
17469 case arm_stub_a8_veneer_bl:
17470 {
17471 unsigned int i1, j1, i2, j2, s;
17472
17473 branch_insn = 0xf000d000;
17474
17475 jump24:
17476 if (branch_offset < -16777216 || branch_offset > 16777214)
17477 {
17478 /* There's not much we can do apart from complain if this
17479 happens. */
17480 (*_bfd_error_handler) (_("%B: error: Cortex-A8 erratum stub out "
17481 "of range (input file too large)"), abfd);
17482 return FALSE;
17483 }
17484
17485 /* i1 = not(j1 eor s), so:
17486 not i1 = j1 eor s
17487 j1 = (not i1) eor s. */
17488
17489 branch_insn |= (branch_offset >> 1) & 0x7ff;
17490 branch_insn |= ((branch_offset >> 12) & 0x3ff) << 16;
17491 i2 = (branch_offset >> 22) & 1;
17492 i1 = (branch_offset >> 23) & 1;
17493 s = (branch_offset >> 24) & 1;
17494 j1 = (!i1) ^ s;
17495 j2 = (!i2) ^ s;
17496 branch_insn |= j2 << 11;
17497 branch_insn |= j1 << 13;
17498 branch_insn |= s << 26;
17499 }
17500 break;
17501
17502 default:
17503 BFD_FAIL ();
17504 return FALSE;
17505 }
17506
8d9d9490
TP		 17507 bfd_put_16 (abfd, (branch_insn >> 16) & 0xffff, &contents[loc]);
17508 bfd_put_16 (abfd, branch_insn & 0xffff, &contents[loc + 2]);
48229727
JB		 17509
17510 return TRUE;
17511}
17512
a504d23a
LA		 17513/* Beginning of stm32l4xx work-around. */
17514
17515/* Functions encoding instructions necessary for the emission of the
17516 fix-stm32l4xx-629360.
17517 Encoding is extracted from the
17518 ARM (C) Architecture Reference Manual
17519 ARMv7-A and ARMv7-R edition
17520 ARM DDI 0406C.b (ID072512). */
17521
17522static inline bfd_vma
82188b29 17523create_instruction_branch_absolute (int branch_offset)
a504d23a
LA		 17524{
17525 /* A8.8.18 B (A8-334)
17526 B target_address (Encoding T4). */
17527 /* 1111 - 0Sii - iiii - iiii - 10J1 - Jiii - iiii - iiii. */
17528 /* jump offset is: S:I1:I2:imm10:imm11:0. */
17529 /* with : I1 = NOT (J1 EOR S) I2 = NOT (J2 EOR S). */
17530
a504d23a
LA		 17531 int s = ((branch_offset & 0x1000000) >> 24);
17532 int j1 = s ^ !((branch_offset & 0x800000) >> 23);
17533 int j2 = s ^ !((branch_offset & 0x400000) >> 22);
17534
17535 if (branch_offset < -(1 << 24) || branch_offset >= (1 << 24))
17536 BFD_ASSERT (0 && "Error: branch out of range. Cannot create branch.");
17537
17538 bfd_vma patched_inst = 0xf0009000
17539 | s << 26 /* S. */
17540 | (((unsigned long) (branch_offset) >> 12) & 0x3ff) << 16 /* imm10. */
17541 | j1 << 13 /* J1. */
17542 | j2 << 11 /* J2. */
17543 | (((unsigned long) (branch_offset) >> 1) & 0x7ff); /* imm11. */
17544
17545 return patched_inst;
17546}
17547
17548static inline bfd_vma
17549create_instruction_ldmia (int base_reg, int wback, int reg_mask)
17550{
17551 /* A8.8.57 LDM/LDMIA/LDMFD (A8-396)
17552 LDMIA Rn!, {Ra, Rb, Rc, ...} (Encoding T2). */
17553 bfd_vma patched_inst = 0xe8900000
17554 | (/*W=*/wback << 21)
17555 | (base_reg << 16)
17556 | (reg_mask & 0x0000ffff);
17557
17558 return patched_inst;
17559}
17560
17561static inline bfd_vma
17562create_instruction_ldmdb (int base_reg, int wback, int reg_mask)
17563{
17564 /* A8.8.60 LDMDB/LDMEA (A8-402)
17565 LDMDB Rn!, {Ra, Rb, Rc, ...} (Encoding T1). */
17566 bfd_vma patched_inst = 0xe9100000
17567 | (/*W=*/wback << 21)
17568 | (base_reg << 16)
17569 | (reg_mask & 0x0000ffff);
17570
17571 return patched_inst;
17572}
17573
17574static inline bfd_vma
17575create_instruction_mov (int target_reg, int source_reg)
17576{
17577 /* A8.8.103 MOV (register) (A8-486)
17578 MOV Rd, Rm (Encoding T1). */
17579 bfd_vma patched_inst = 0x4600
17580 | (target_reg & 0x7)
17581 | ((target_reg & 0x8) >> 3) << 7
17582 | (source_reg << 3);
17583
17584 return patched_inst;
17585}
17586
17587static inline bfd_vma
17588create_instruction_sub (int target_reg, int source_reg, int value)
17589{
17590 /* A8.8.221 SUB (immediate) (A8-708)
17591 SUB Rd, Rn, #value (Encoding T3). */
17592 bfd_vma patched_inst = 0xf1a00000
17593 | (target_reg << 8)
17594 | (source_reg << 16)
17595 | (/*S=*/0 << 20)
17596 | ((value & 0x800) >> 11) << 26
17597 | ((value & 0x700) >> 8) << 12
17598 | (value & 0x0ff);
17599
17600 return patched_inst;
17601}
17602
17603static inline bfd_vma
9239bbd3 17604create_instruction_vldmia (int base_reg, int is_dp, int wback, int num_words,
a504d23a
LA		 17605 int first_reg)
17606{
17607 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 17608 VLMD{MODE} Rn{!}, {list} (Encoding T1 or T2). */
17609 bfd_vma patched_inst = (is_dp ? 0xec900b00 : 0xec900a00)
a504d23a
LA		 17610 | (/*W=*/wback << 21)
17611 | (base_reg << 16)
9239bbd3
CM		 17612 | (num_words & 0x000000ff)
17613 | (((unsigned)first_reg >> 1) & 0x0000000f) << 12
a504d23a
LA		 17614 | (first_reg & 0x00000001) << 22;
17615
17616 return patched_inst;
17617}
17618
17619static inline bfd_vma
9239bbd3
CM		 17620create_instruction_vldmdb (int base_reg, int is_dp, int num_words,
17621 int first_reg)
a504d23a
LA		 17622{
17623 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 17624 VLMD{MODE} Rn!, {} (Encoding T1 or T2). */
17625 bfd_vma patched_inst = (is_dp ? 0xed300b00 : 0xed300a00)
a504d23a 17626 | (base_reg << 16)
9239bbd3
CM		 17627 | (num_words & 0x000000ff)
17628 | (((unsigned)first_reg >>1 ) & 0x0000000f) << 12
a504d23a
LA		 17629 | (first_reg & 0x00000001) << 22;
17630
17631 return patched_inst;
17632}
17633
17634static inline bfd_vma
17635create_instruction_udf_w (int value)
17636{
17637 /* A8.8.247 UDF (A8-758)
17638 Undefined (Encoding T2). */
17639 bfd_vma patched_inst = 0xf7f0a000
17640 | (value & 0x00000fff)
17641 | (value & 0x000f0000) << 16;
17642
17643 return patched_inst;
17644}
17645
17646static inline bfd_vma
17647create_instruction_udf (int value)
17648{
17649 /* A8.8.247 UDF (A8-758)
17650 Undefined (Encoding T1). */
17651 bfd_vma patched_inst = 0xde00
17652 | (value & 0xff);
17653
17654 return patched_inst;
17655}
17656
17657/* Functions writing an instruction in memory, returning the next
17658 memory position to write to. */
17659
17660static inline bfd_byte *
17661push_thumb2_insn32 (struct elf32_arm_link_hash_table * htab,
17662 bfd * output_bfd, bfd_byte *pt, insn32 insn)
17663{
17664 put_thumb2_insn (htab, output_bfd, insn, pt);
17665 return pt + 4;
17666}
17667
17668static inline bfd_byte *
17669push_thumb2_insn16 (struct elf32_arm_link_hash_table * htab,
17670 bfd * output_bfd, bfd_byte *pt, insn32 insn)
17671{
17672 put_thumb_insn (htab, output_bfd, insn, pt);
17673 return pt + 2;
17674}
17675
17676/* Function filling up a region in memory with T1 and T2 UDFs taking
17677 care of alignment. */
17678
17679static bfd_byte *
17680stm32l4xx_fill_stub_udf (struct elf32_arm_link_hash_table * htab,
17681 bfd * output_bfd,
17682 const bfd_byte * const base_stub_contents,
17683 bfd_byte * const from_stub_contents,
17684 const bfd_byte * const end_stub_contents)
17685{
17686 bfd_byte *current_stub_contents = from_stub_contents;
17687
17688 /* Fill the remaining of the stub with deterministic contents : UDF
17689 instructions.
17690 Check if realignment is needed on modulo 4 frontier using T1, to
17691 further use T2. */
17692 if ((current_stub_contents < end_stub_contents)
17693 && !((current_stub_contents - base_stub_contents) % 2)
17694 && ((current_stub_contents - base_stub_contents) % 4))
17695 current_stub_contents =
17696 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
17697 create_instruction_udf (0));
17698
17699 for (; current_stub_contents < end_stub_contents;)
17700 current_stub_contents =
17701 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17702 create_instruction_udf_w (0));
17703
17704 return current_stub_contents;
17705}
17706
17707/* Functions writing the stream of instructions equivalent to the
17708 derived sequence for ldmia, ldmdb, vldm respectively. */
17709
17710static void
17711stm32l4xx_create_replacing_stub_ldmia (struct elf32_arm_link_hash_table * htab,
17712 bfd * output_bfd,
17713 const insn32 initial_insn,
17714 const bfd_byte *const initial_insn_addr,
17715 bfd_byte *const base_stub_contents)
17716{
17717 int wback = (initial_insn & 0x00200000) >> 21;
17718 int ri, rn = (initial_insn & 0x000F0000) >> 16;
17719 int insn_all_registers = initial_insn & 0x0000ffff;
17720 int insn_low_registers, insn_high_registers;
17721 int usable_register_mask;
17722 int nb_registers = popcount (insn_all_registers);
17723 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
17724 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
17725 bfd_byte *current_stub_contents = base_stub_contents;
17726
17727 BFD_ASSERT (is_thumb2_ldmia (initial_insn));
17728
17729 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
17730 smaller than 8 registers load sequences that do not cause the
17731 hardware issue. */
17732 if (nb_registers <= 8)
17733 {
17734 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
17735 current_stub_contents =
17736 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17737 initial_insn);
17738
17739 /* B initial_insn_addr+4. */
17740 if (!restore_pc)
17741 current_stub_contents =
17742 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17743 create_instruction_branch_absolute
82188b29
NC		 17744 (initial_insn_addr - current_stub_contents));
17745
a504d23a
LA		 17746
17747 /* Fill the remaining of the stub with deterministic contents. */
17748 current_stub_contents =
17749 stm32l4xx_fill_stub_udf (htab, output_bfd,
17750 base_stub_contents, current_stub_contents,
17751 base_stub_contents +
17752 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
17753
17754 return;
17755 }
17756
17757 /* - reg_list[13] == 0. */
17758 BFD_ASSERT ((insn_all_registers & (1 << 13))==0);
17759
17760 /* - reg_list[14] & reg_list[15] != 1. */
17761 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
17762
17763 /* - if (wback==1) reg_list[rn] == 0. */
17764 BFD_ASSERT (!wback || !restore_rn);
17765
17766 /* - nb_registers > 8. */
17767 BFD_ASSERT (popcount (insn_all_registers) > 8);
17768
17769 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
17770
17771 /* In the following algorithm, we split this wide LDM using 2 LDM insns:
17772 - One with the 7 lowest registers (register mask 0x007F)
17773 This LDM will finally contain between 2 and 7 registers
17774 - One with the 7 highest registers (register mask 0xDF80)
17775 This ldm will finally contain between 2 and 7 registers. */
17776 insn_low_registers = insn_all_registers & 0x007F;
17777 insn_high_registers = insn_all_registers & 0xDF80;
17778
17779 /* A spare register may be needed during this veneer to temporarily
17780 handle the base register. This register will be restored with the
17781 last LDM operation.
17782 The usable register may be any general purpose register (that
17783 excludes PC, SP, LR : register mask is 0x1FFF). */
17784 usable_register_mask = 0x1FFF;
17785
17786 /* Generate the stub function. */
17787 if (wback)
17788 {
17789 /* LDMIA Rn!, {R-low-register-list} : (Encoding T2). */
17790 current_stub_contents =
17791 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17792 create_instruction_ldmia
17793 (rn, /*wback=*/1, insn_low_registers));
17794
17795 /* LDMIA Rn!, {R-high-register-list} : (Encoding T2). */
17796 current_stub_contents =
17797 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17798 create_instruction_ldmia
17799 (rn, /*wback=*/1, insn_high_registers));
17800 if (!restore_pc)
17801 {
17802 /* B initial_insn_addr+4. */
17803 current_stub_contents =
17804 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17805 create_instruction_branch_absolute
82188b29 17806 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17807 }
17808 }
17809 else /* if (!wback). */
17810 {
17811 ri = rn;
17812
17813 /* If Rn is not part of the high-register-list, move it there. */
17814 if (!(insn_high_registers & (1 << rn)))
17815 {
17816 /* Choose a Ri in the high-register-list that will be restored. */
17817 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
17818
17819 /* MOV Ri, Rn. */
17820 current_stub_contents =
17821 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
17822 create_instruction_mov (ri, rn));
17823 }
17824
17825 /* LDMIA Ri!, {R-low-register-list} : (Encoding T2). */
17826 current_stub_contents =
17827 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17828 create_instruction_ldmia
17829 (ri, /*wback=*/1, insn_low_registers));
17830
17831 /* LDMIA Ri, {R-high-register-list} : (Encoding T2). */
17832 current_stub_contents =
17833 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17834 create_instruction_ldmia
17835 (ri, /*wback=*/0, insn_high_registers));
17836
17837 if (!restore_pc)
17838 {
17839 /* B initial_insn_addr+4. */
17840 current_stub_contents =
17841 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17842 create_instruction_branch_absolute
82188b29 17843 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17844 }
17845 }
17846
17847 /* Fill the remaining of the stub with deterministic contents. */
17848 current_stub_contents =
17849 stm32l4xx_fill_stub_udf (htab, output_bfd,
17850 base_stub_contents, current_stub_contents,
17851 base_stub_contents +
17852 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
17853}
17854
17855static void
17856stm32l4xx_create_replacing_stub_ldmdb (struct elf32_arm_link_hash_table * htab,
17857 bfd * output_bfd,
17858 const insn32 initial_insn,
17859 const bfd_byte *const initial_insn_addr,
17860 bfd_byte *const base_stub_contents)
17861{
17862 int wback = (initial_insn & 0x00200000) >> 21;
17863 int ri, rn = (initial_insn & 0x000f0000) >> 16;
17864 int insn_all_registers = initial_insn & 0x0000ffff;
17865 int insn_low_registers, insn_high_registers;
17866 int usable_register_mask;
17867 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
17868 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
17869 int nb_registers = popcount (insn_all_registers);
17870 bfd_byte *current_stub_contents = base_stub_contents;
17871
17872 BFD_ASSERT (is_thumb2_ldmdb (initial_insn));
17873
17874 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
17875 smaller than 8 registers load sequences that do not cause the
17876 hardware issue. */
17877 if (nb_registers <= 8)
17878 {
17879 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
17880 current_stub_contents =
17881 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17882 initial_insn);
17883
17884 /* B initial_insn_addr+4. */
17885 current_stub_contents =
17886 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17887 create_instruction_branch_absolute
82188b29 17888 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17889
17890 /* Fill the remaining of the stub with deterministic contents. */
17891 current_stub_contents =
17892 stm32l4xx_fill_stub_udf (htab, output_bfd,
17893 base_stub_contents, current_stub_contents,
17894 base_stub_contents +
17895 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
17896
17897 return;
17898 }
17899
17900 /* - reg_list[13] == 0. */
17901 BFD_ASSERT ((insn_all_registers & (1 << 13)) == 0);
17902
17903 /* - reg_list[14] & reg_list[15] != 1. */
17904 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
17905
17906 /* - if (wback==1) reg_list[rn] == 0. */
17907 BFD_ASSERT (!wback || !restore_rn);
17908
17909 /* - nb_registers > 8. */
17910 BFD_ASSERT (popcount (insn_all_registers) > 8);
17911
17912 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
17913
17914 /* In the following algorithm, we split this wide LDM using 2 LDM insn:
17915 - One with the 7 lowest registers (register mask 0x007F)
17916 This LDM will finally contain between 2 and 7 registers
17917 - One with the 7 highest registers (register mask 0xDF80)
17918 This ldm will finally contain between 2 and 7 registers. */
17919 insn_low_registers = insn_all_registers & 0x007F;
17920 insn_high_registers = insn_all_registers & 0xDF80;
17921
17922 /* A spare register may be needed during this veneer to temporarily
17923 handle the base register. This register will be restored with
17924 the last LDM operation.
17925 The usable register may be any general purpose register (that excludes
17926 PC, SP, LR : register mask is 0x1FFF). */
17927 usable_register_mask = 0x1FFF;
17928
17929 /* Generate the stub function. */
17930 if (!wback && !restore_pc && !restore_rn)
17931 {
17932 /* Choose a Ri in the low-register-list that will be restored. */
17933 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
17934
17935 /* MOV Ri, Rn. */
17936 current_stub_contents =
17937 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
17938 create_instruction_mov (ri, rn));
17939
17940 /* LDMDB Ri!, {R-high-register-list}. */
17941 current_stub_contents =
17942 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17943 create_instruction_ldmdb
17944 (ri, /*wback=*/1, insn_high_registers));
17945
17946 /* LDMDB Ri, {R-low-register-list}. */
17947 current_stub_contents =
17948 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17949 create_instruction_ldmdb
17950 (ri, /*wback=*/0, insn_low_registers));
17951
17952 /* B initial_insn_addr+4. */
17953 current_stub_contents =
17954 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17955 create_instruction_branch_absolute
82188b29 17956 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17957 }
17958 else if (wback && !restore_pc && !restore_rn)
17959 {
17960 /* LDMDB Rn!, {R-high-register-list}. */
17961 current_stub_contents =
17962 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17963 create_instruction_ldmdb
17964 (rn, /*wback=*/1, insn_high_registers));
17965
17966 /* LDMDB Rn!, {R-low-register-list}. */
17967 current_stub_contents =
17968 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17969 create_instruction_ldmdb
17970 (rn, /*wback=*/1, insn_low_registers));
17971
17972 /* B initial_insn_addr+4. */
17973 current_stub_contents =
17974 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17975 create_instruction_branch_absolute
82188b29 17976 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17977 }
17978 else if (!wback && restore_pc && !restore_rn)
17979 {
17980 /* Choose a Ri in the high-register-list that will be restored. */
17981 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
17982
17983 /* SUB Ri, Rn, #(4*nb_registers). */
17984 current_stub_contents =
17985 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17986 create_instruction_sub (ri, rn, (4 * nb_registers)));
17987
17988 /* LDMIA Ri!, {R-low-register-list}. */
17989 current_stub_contents =
17990 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17991 create_instruction_ldmia
17992 (ri, /*wback=*/1, insn_low_registers));
17993
17994 /* LDMIA Ri, {R-high-register-list}. */
17995 current_stub_contents =
17996 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17997 create_instruction_ldmia
17998 (ri, /*wback=*/0, insn_high_registers));
17999 }
18000 else if (wback && restore_pc && !restore_rn)
18001 {
18002 /* Choose a Ri in the high-register-list that will be restored. */
18003 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
18004
18005 /* SUB Rn, Rn, #(4*nb_registers) */
18006 current_stub_contents =
18007 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18008 create_instruction_sub (rn, rn, (4 * nb_registers)));
18009
18010 /* MOV Ri, Rn. */
18011 current_stub_contents =
18012 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18013 create_instruction_mov (ri, rn));
18014
18015 /* LDMIA Ri!, {R-low-register-list}. */
18016 current_stub_contents =
18017 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18018 create_instruction_ldmia
18019 (ri, /*wback=*/1, insn_low_registers));
18020
18021 /* LDMIA Ri, {R-high-register-list}. */
18022 current_stub_contents =
18023 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18024 create_instruction_ldmia
18025 (ri, /*wback=*/0, insn_high_registers));
18026 }
18027 else if (!wback && !restore_pc && restore_rn)
18028 {
18029 ri = rn;
18030 if (!(insn_low_registers & (1 << rn)))
18031 {
18032 /* Choose a Ri in the low-register-list that will be restored. */
18033 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
18034
18035 /* MOV Ri, Rn. */
18036 current_stub_contents =
18037 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18038 create_instruction_mov (ri, rn));
18039 }
18040
18041 /* LDMDB Ri!, {R-high-register-list}. */
18042 current_stub_contents =
18043 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18044 create_instruction_ldmdb
18045 (ri, /*wback=*/1, insn_high_registers));
18046
18047 /* LDMDB Ri, {R-low-register-list}. */
18048 current_stub_contents =
18049 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18050 create_instruction_ldmdb
18051 (ri, /*wback=*/0, insn_low_registers));
18052
18053 /* B initial_insn_addr+4. */
18054 current_stub_contents =
18055 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18056 create_instruction_branch_absolute
82188b29 18057 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18058 }
18059 else if (!wback && restore_pc && restore_rn)
18060 {
18061 ri = rn;
18062 if (!(insn_high_registers & (1 << rn)))
18063 {
18064 /* Choose a Ri in the high-register-list that will be restored. */
18065 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
18066 }
18067
18068 /* SUB Ri, Rn, #(4*nb_registers). */
18069 current_stub_contents =
18070 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18071 create_instruction_sub (ri, rn, (4 * nb_registers)));
18072
18073 /* LDMIA Ri!, {R-low-register-list}. */
18074 current_stub_contents =
18075 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18076 create_instruction_ldmia
18077 (ri, /*wback=*/1, insn_low_registers));
18078
18079 /* LDMIA Ri, {R-high-register-list}. */
18080 current_stub_contents =
18081 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18082 create_instruction_ldmia
18083 (ri, /*wback=*/0, insn_high_registers));
18084 }
18085 else if (wback && restore_rn)
18086 {
18087 /* The assembler should not have accepted to encode this. */
18088 BFD_ASSERT (0 && "Cannot patch an instruction that has an "
18089 "undefined behavior.\n");
18090 }
18091
18092 /* Fill the remaining of the stub with deterministic contents. */
18093 current_stub_contents =
18094 stm32l4xx_fill_stub_udf (htab, output_bfd,
18095 base_stub_contents, current_stub_contents,
18096 base_stub_contents +
18097 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18098
18099}
18100
18101static void
18102stm32l4xx_create_replacing_stub_vldm (struct elf32_arm_link_hash_table * htab,
18103 bfd * output_bfd,
18104 const insn32 initial_insn,
18105 const bfd_byte *const initial_insn_addr,
18106 bfd_byte *const base_stub_contents)
18107{
9239bbd3 18108 int num_words = ((unsigned int) initial_insn << 24) >> 24;
a504d23a
LA		 18109 bfd_byte *current_stub_contents = base_stub_contents;
18110
18111 BFD_ASSERT (is_thumb2_vldm (initial_insn));
18112
18113 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
9239bbd3 18114 smaller than 8 words load sequences that do not cause the
a504d23a 18115 hardware issue. */
9239bbd3 18116 if (num_words <= 8)
a504d23a
LA		 18117 {
18118 /* Untouched instruction. */
18119 current_stub_contents =
18120 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18121 initial_insn);
18122
18123 /* B initial_insn_addr+4. */
18124 current_stub_contents =
18125 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18126 create_instruction_branch_absolute
82188b29 18127 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18128 }
18129 else
18130 {
9239bbd3
CM		 18131 bfd_boolean is_dp = /* DP encoding. */
18132 (initial_insn & 0xfe100f00) == 0xec100b00;
a504d23a
LA		 18133 bfd_boolean is_ia_nobang = /* (IA without !). */
18134 (((initial_insn << 7) >> 28) & 0xd) == 0x4;
18135 bfd_boolean is_ia_bang = /* (IA with !) - includes VPOP. */
18136 (((initial_insn << 7) >> 28) & 0xd) == 0x5;
18137 bfd_boolean is_db_bang = /* (DB with !). */
18138 (((initial_insn << 7) >> 28) & 0xd) == 0x9;
9239bbd3 18139 int base_reg = ((unsigned int) initial_insn << 12) >> 28;
a504d23a 18140 /* d = UInt (Vd:D);. */
9239bbd3 18141 int first_reg = ((((unsigned int) initial_insn << 16) >> 28) << 1)
a504d23a
LA		 18142 | (((unsigned int)initial_insn << 9) >> 31);
18143
9239bbd3
CM		 18144 /* Compute the number of 8-words chunks needed to split. */
18145 int chunks = (num_words % 8) ? (num_words / 8 + 1) : (num_words / 8);
a504d23a
LA		 18146 int chunk;
18147
18148 /* The test coverage has been done assuming the following
18149 hypothesis that exactly one of the previous is_ predicates is
18150 true. */
9239bbd3
CM		 18151 BFD_ASSERT ( (is_ia_nobang ^ is_ia_bang ^ is_db_bang)
18152 && !(is_ia_nobang & is_ia_bang & is_db_bang));
a504d23a 18153
9239bbd3 18154 /* We treat the cutting of the words in one pass for all
a504d23a
LA		 18155 cases, then we emit the adjustments:
18156
18157 vldm rx, {...}
18158 -> vldm rx!, {8_words_or_less} for each needed 8_word
18159 -> sub rx, rx, #size (list)
18160
18161 vldm rx!, {...}
18162 -> vldm rx!, {8_words_or_less} for each needed 8_word
18163 This also handles vpop instruction (when rx is sp)
18164
18165 vldmd rx!, {...}
18166 -> vldmb rx!, {8_words_or_less} for each needed 8_word. */
9239bbd3 18167 for (chunk = 0; chunk < chunks; ++chunk)
a504d23a 18168 {
9239bbd3
CM		 18169 bfd_vma new_insn = 0;
18170
a504d23a
LA		 18171 if (is_ia_nobang || is_ia_bang)
18172 {
9239bbd3
CM		 18173 new_insn = create_instruction_vldmia
18174 (base_reg,
18175 is_dp,
18176 /*wback= . */1,
18177 chunks - (chunk + 1) ?
18178 8 : num_words - chunk * 8,
18179 first_reg + chunk * 8);
a504d23a
LA		 18180 }
18181 else if (is_db_bang)
18182 {
9239bbd3
CM		 18183 new_insn = create_instruction_vldmdb
18184 (base_reg,
18185 is_dp,
18186 chunks - (chunk + 1) ?
18187 8 : num_words - chunk * 8,
18188 first_reg + chunk * 8);
a504d23a 18189 }
9239bbd3
CM		 18190
18191 if (new_insn)
18192 current_stub_contents =
18193 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18194 new_insn);
a504d23a
LA		 18195 }
18196
18197 /* Only this case requires the base register compensation
18198 subtract. */
18199 if (is_ia_nobang)
18200 {
18201 current_stub_contents =
18202 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18203 create_instruction_sub
9239bbd3 18204 (base_reg, base_reg, 4*num_words));
a504d23a
LA		 18205 }
18206
18207 /* B initial_insn_addr+4. */
18208 current_stub_contents =
18209 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18210 create_instruction_branch_absolute
82188b29 18211 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18212 }
18213
18214 /* Fill the remaining of the stub with deterministic contents. */
18215 current_stub_contents =
18216 stm32l4xx_fill_stub_udf (htab, output_bfd,
18217 base_stub_contents, current_stub_contents,
18218 base_stub_contents +
18219 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
18220}
18221
18222static void
18223stm32l4xx_create_replacing_stub (struct elf32_arm_link_hash_table * htab,
18224 bfd * output_bfd,
18225 const insn32 wrong_insn,
18226 const bfd_byte *const wrong_insn_addr,
18227 bfd_byte *const stub_contents)
18228{
18229 if (is_thumb2_ldmia (wrong_insn))
18230 stm32l4xx_create_replacing_stub_ldmia (htab, output_bfd,
18231 wrong_insn, wrong_insn_addr,
18232 stub_contents);
18233 else if (is_thumb2_ldmdb (wrong_insn))
18234 stm32l4xx_create_replacing_stub_ldmdb (htab, output_bfd,
18235 wrong_insn, wrong_insn_addr,
18236 stub_contents);
18237 else if (is_thumb2_vldm (wrong_insn))
18238 stm32l4xx_create_replacing_stub_vldm (htab, output_bfd,
18239 wrong_insn, wrong_insn_addr,
18240 stub_contents);
18241}
18242
18243/* End of stm32l4xx work-around. */
18244
18245
491d01d3
YU		 18246static void
18247elf32_arm_add_relocation (bfd *output_bfd, struct bfd_link_info *info,
18248 asection *output_sec, Elf_Internal_Rela *rel)
18249{
18250 BFD_ASSERT (output_sec && rel);
18251 struct bfd_elf_section_reloc_data *output_reldata;
18252 struct elf32_arm_link_hash_table *htab;
18253 struct bfd_elf_section_data *oesd = elf_section_data (output_sec);
18254 Elf_Internal_Shdr *rel_hdr;
18255
18256
18257 if (oesd->rel.hdr)
18258 {
18259 rel_hdr = oesd->rel.hdr;
18260 output_reldata = &(oesd->rel);
18261 }
18262 else if (oesd->rela.hdr)
18263 {
18264 rel_hdr = oesd->rela.hdr;
18265 output_reldata = &(oesd->rela);
18266 }
18267 else
18268 {
18269 abort ();
18270 }
18271
18272 bfd_byte *erel = rel_hdr->contents;
18273 erel += output_reldata->count * rel_hdr->sh_entsize;
18274 htab = elf32_arm_hash_table (info);
18275 SWAP_RELOC_OUT (htab) (output_bfd, rel, erel);
18276 output_reldata->count++;
18277}
18278
e489d0ae
PB		 18279/* Do code byteswapping. Return FALSE afterwards so that the section is
18280 written out as normal. */
18281
18282static bfd_boolean
c7b8f16e 18283elf32_arm_write_section (bfd *output_bfd,
8029a119
NC		 18284 struct bfd_link_info *link_info,
18285 asection *sec,
e489d0ae
PB		 18286 bfd_byte *contents)
18287{
48229727 18288 unsigned int mapcount, errcount;
8e3de13a 18289 _arm_elf_section_data *arm_data;
c7b8f16e 18290 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
e489d0ae 18291 elf32_arm_section_map *map;
c7b8f16e 18292 elf32_vfp11_erratum_list *errnode;
a504d23a 18293 elf32_stm32l4xx_erratum_list *stm32l4xx_errnode;
e489d0ae
PB		 18294 bfd_vma ptr;
18295 bfd_vma end;
c7b8f16e 18296 bfd_vma offset = sec->output_section->vma + sec->output_offset;
e489d0ae 18297 bfd_byte tmp;
48229727 18298 unsigned int i;
57e8b36a 18299
4dfe6ac6
NC		 18300 if (globals == NULL)
18301 return FALSE;
18302
8e3de13a
NC		 18303 /* If this section has not been allocated an _arm_elf_section_data
18304 structure then we cannot record anything. */
18305 arm_data = get_arm_elf_section_data (sec);
18306 if (arm_data == NULL)
18307 return FALSE;
18308
18309 mapcount = arm_data->mapcount;
18310 map = arm_data->map;
c7b8f16e
JB		 18311 errcount = arm_data->erratumcount;
18312
18313 if (errcount != 0)
18314 {
18315 unsigned int endianflip = bfd_big_endian (output_bfd) ? 3 : 0;
18316
18317 for (errnode = arm_data->erratumlist; errnode != 0;
99059e56
RM		 18318 errnode = errnode->next)
18319 {
18320 bfd_vma target = errnode->vma - offset;
18321
18322 switch (errnode->type)
18323 {
18324 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
18325 {
18326 bfd_vma branch_to_veneer;
18327 /* Original condition code of instruction, plus bit mask for
18328 ARM B instruction. */
18329 unsigned int insn = (errnode->u.b.vfp_insn & 0xf0000000)
18330 | 0x0a000000;
c7b8f16e
JB		 18331
18332 /* The instruction is before the label. */
91d6fa6a 18333 target -= 4;
c7b8f16e
JB		 18334
18335 /* Above offset included in -4 below. */
18336 branch_to_veneer = errnode->u.b.veneer->vma
99059e56 18337 - errnode->vma - 4;
c7b8f16e
JB		 18338
18339 if ((signed) branch_to_veneer < -(1 << 25)
18340 || (signed) branch_to_veneer >= (1 << 25))
18341 (*_bfd_error_handler) (_("%B: error: VFP11 veneer out of "
18342 "range"), output_bfd);
18343
99059e56
RM		 18344 insn |= (branch_to_veneer >> 2) & 0xffffff;
18345 contents[endianflip ^ target] = insn & 0xff;
18346 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
18347 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
18348 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
18349 }
18350 break;
c7b8f16e
JB		 18351
18352 case VFP11_ERRATUM_ARM_VENEER:
99059e56
RM		 18353 {
18354 bfd_vma branch_from_veneer;
18355 unsigned int insn;
c7b8f16e 18356
99059e56
RM		 18357 /* Take size of veneer into account. */
18358 branch_from_veneer = errnode->u.v.branch->vma
18359 - errnode->vma - 12;
c7b8f16e
JB		 18360
18361 if ((signed) branch_from_veneer < -(1 << 25)
18362 || (signed) branch_from_veneer >= (1 << 25))
18363 (*_bfd_error_handler) (_("%B: error: VFP11 veneer out of "
18364 "range"), output_bfd);
18365
99059e56
RM		 18366 /* Original instruction. */
18367 insn = errnode->u.v.branch->u.b.vfp_insn;
18368 contents[endianflip ^ target] = insn & 0xff;
18369 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
18370 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
18371 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
18372
18373 /* Branch back to insn after original insn. */
18374 insn = 0xea000000 | ((branch_from_veneer >> 2) & 0xffffff);
18375 contents[endianflip ^ (target + 4)] = insn & 0xff;
18376 contents[endianflip ^ (target + 5)] = (insn >> 8) & 0xff;
18377 contents[endianflip ^ (target + 6)] = (insn >> 16) & 0xff;
18378 contents[endianflip ^ (target + 7)] = (insn >> 24) & 0xff;
18379 }
18380 break;
c7b8f16e 18381
99059e56
RM		 18382 default:
18383 abort ();
18384 }
18385 }
c7b8f16e 18386 }
e489d0ae 18387
a504d23a
LA		 18388 if (arm_data->stm32l4xx_erratumcount != 0)
18389 {
18390 for (stm32l4xx_errnode = arm_data->stm32l4xx_erratumlist;
18391 stm32l4xx_errnode != 0;
18392 stm32l4xx_errnode = stm32l4xx_errnode->next)
18393 {
18394 bfd_vma target = stm32l4xx_errnode->vma - offset;
18395
18396 switch (stm32l4xx_errnode->type)
18397 {
18398 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
18399 {
18400 unsigned int insn;
18401 bfd_vma branch_to_veneer =
18402 stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma;
18403
18404 if ((signed) branch_to_veneer < -(1 << 24)
18405 || (signed) branch_to_veneer >= (1 << 24))
18406 {
18407 bfd_vma out_of_range =
18408 ((signed) branch_to_veneer < -(1 << 24)) ?
18409 - branch_to_veneer - (1 << 24) :
18410 ((signed) branch_to_veneer >= (1 << 24)) ?
18411 branch_to_veneer - (1 << 24) : 0;
18412
18413 (*_bfd_error_handler)
18414 (_("%B(%#x): error: Cannot create STM32L4XX veneer. "
eee926f2 18415 "Jump out of range by %ld bytes. "
a504d23a
LA		 18416 "Cannot encode branch instruction. "),
18417 output_bfd,
eee926f2 18418 (long) (stm32l4xx_errnode->vma - 4),
a504d23a
LA		 18419 out_of_range);
18420 continue;
18421 }
18422
18423 insn = create_instruction_branch_absolute
82188b29 18424 (stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma);
a504d23a
LA		 18425
18426 /* The instruction is before the label. */
18427 target -= 4;
18428
18429 put_thumb2_insn (globals, output_bfd,
18430 (bfd_vma) insn, contents + target);
18431 }
18432 break;
18433
18434 case STM32L4XX_ERRATUM_VENEER:
18435 {
82188b29
NC		 18436 bfd_byte * veneer;
18437 bfd_byte * veneer_r;
a504d23a
LA		 18438 unsigned int insn;
18439
82188b29
NC		 18440 veneer = contents + target;
18441 veneer_r = veneer
18442 + stm32l4xx_errnode->u.b.veneer->vma
18443 - stm32l4xx_errnode->vma - 4;
a504d23a
LA		 18444
18445 if ((signed) (veneer_r - veneer -
18446 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE >
18447 STM32L4XX_ERRATUM_LDM_VENEER_SIZE ?
18448 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE :
18449 STM32L4XX_ERRATUM_LDM_VENEER_SIZE) < -(1 << 24)
18450 || (signed) (veneer_r - veneer) >= (1 << 24))
18451 {
18452 (*_bfd_error_handler) (_("%B: error: Cannot create STM32L4XX "
18453 "veneer."), output_bfd);
18454 continue;
18455 }
18456
18457 /* Original instruction. */
18458 insn = stm32l4xx_errnode->u.v.branch->u.b.insn;
18459
18460 stm32l4xx_create_replacing_stub
18461 (globals, output_bfd, insn, (void*)veneer_r, (void*)veneer);
18462 }
18463 break;
18464
18465 default:
18466 abort ();
18467 }
18468 }
18469 }
18470
2468f9c9
PB		 18471 if (arm_data->elf.this_hdr.sh_type == SHT_ARM_EXIDX)
18472 {
18473 arm_unwind_table_edit *edit_node
99059e56 18474 = arm_data->u.exidx.unwind_edit_list;
2468f9c9 18475 /* Now, sec->size is the size of the section we will write. The original
99059e56 18476 size (before we merged duplicate entries and inserted EXIDX_CANTUNWIND
2468f9c9
PB		 18477 markers) was sec->rawsize. (This isn't the case if we perform no
18478 edits, then rawsize will be zero and we should use size). */
21d799b5 18479 bfd_byte *edited_contents = (bfd_byte *) bfd_malloc (sec->size);
2468f9c9
PB		 18480 unsigned int input_size = sec->rawsize ? sec->rawsize : sec->size;
18481 unsigned int in_index, out_index;
18482 bfd_vma add_to_offsets = 0;
18483
18484 for (in_index = 0, out_index = 0; in_index * 8 < input_size || edit_node;)
99059e56 18485 {
2468f9c9
PB		 18486 if (edit_node)
18487 {
18488 unsigned int edit_index = edit_node->index;
b38cadfb 18489
2468f9c9 18490 if (in_index < edit_index && in_index * 8 < input_size)
99059e56 18491 {
2468f9c9
PB		 18492 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
18493 contents + in_index * 8, add_to_offsets);
18494 out_index++;
18495 in_index++;
18496 }
18497 else if (in_index == edit_index
18498 || (in_index * 8 >= input_size
18499 && edit_index == UINT_MAX))
99059e56 18500 {
2468f9c9
PB		 18501 switch (edit_node->type)
18502 {
18503 case DELETE_EXIDX_ENTRY:
18504 in_index++;
18505 add_to_offsets += 8;
18506 break;
b38cadfb 18507
2468f9c9
PB		 18508 case INSERT_EXIDX_CANTUNWIND_AT_END:
18509 {
99059e56 18510 asection *text_sec = edit_node->linked_section;
2468f9c9
PB		 18511 bfd_vma text_offset = text_sec->output_section->vma
18512 + text_sec->output_offset
18513 + text_sec->size;
18514 bfd_vma exidx_offset = offset + out_index * 8;
99059e56 18515 unsigned long prel31_offset;
2468f9c9
PB		 18516
18517 /* Note: this is meant to be equivalent to an
18518 R_ARM_PREL31 relocation. These synthetic
18519 EXIDX_CANTUNWIND markers are not relocated by the
18520 usual BFD method. */
18521 prel31_offset = (text_offset - exidx_offset)
18522 & 0x7ffffffful;
491d01d3
YU		 18523 if (bfd_link_relocatable (link_info))
18524 {
18525 /* Here relocation for new EXIDX_CANTUNWIND is
18526 created, so there is no need to
18527 adjust offset by hand. */
18528 prel31_offset = text_sec->output_offset
18529 + text_sec->size;
18530
18531 /* New relocation entity. */
18532 asection *text_out = text_sec->output_section;
18533 Elf_Internal_Rela rel;
18534 rel.r_addend = 0;
18535 rel.r_offset = exidx_offset;
18536 rel.r_info = ELF32_R_INFO (text_out->target_index,
18537 R_ARM_PREL31);
18538
18539 elf32_arm_add_relocation (output_bfd, link_info,
18540 sec->output_section,
18541 &rel);
18542 }
2468f9c9
PB		 18543
18544 /* First address we can't unwind. */
18545 bfd_put_32 (output_bfd, prel31_offset,
18546 &edited_contents[out_index * 8]);
18547
18548 /* Code for EXIDX_CANTUNWIND. */
18549 bfd_put_32 (output_bfd, 0x1,
18550 &edited_contents[out_index * 8 + 4]);
18551
18552 out_index++;
18553 add_to_offsets -= 8;
18554 }
18555 break;
18556 }
b38cadfb 18557
2468f9c9
PB		 18558 edit_node = edit_node->next;
18559 }
18560 }
18561 else
18562 {
18563 /* No more edits, copy remaining entries verbatim. */
18564 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
18565 contents + in_index * 8, add_to_offsets);
18566 out_index++;
18567 in_index++;
18568 }
18569 }
18570
18571 if (!(sec->flags & SEC_EXCLUDE) && !(sec->flags & SEC_NEVER_LOAD))
18572 bfd_set_section_contents (output_bfd, sec->output_section,
18573 edited_contents,
18574 (file_ptr) sec->output_offset, sec->size);
18575
18576 return TRUE;
18577 }
18578
48229727
JB		 18579 /* Fix code to point to Cortex-A8 erratum stubs. */
18580 if (globals->fix_cortex_a8)
18581 {
18582 struct a8_branch_to_stub_data data;
18583
18584 data.writing_section = sec;
18585 data.contents = contents;
18586
a504d23a
LA		 18587 bfd_hash_traverse (& globals->stub_hash_table, make_branch_to_a8_stub,
18588 & data);
48229727
JB		 18589 }
18590
e489d0ae
PB		 18591 if (mapcount == 0)
18592 return FALSE;
18593
c7b8f16e 18594 if (globals->byteswap_code)
e489d0ae 18595 {
c7b8f16e 18596 qsort (map, mapcount, sizeof (* map), elf32_arm_compare_mapping);
57e8b36a 18597
c7b8f16e
JB		 18598 ptr = map[0].vma;
18599 for (i = 0; i < mapcount; i++)
99059e56
RM		 18600 {
18601 if (i == mapcount - 1)
c7b8f16e 18602 end = sec->size;
99059e56
RM		 18603 else
18604 end = map[i + 1].vma;
e489d0ae 18605
99059e56 18606 switch (map[i].type)
e489d0ae 18607 {
c7b8f16e
JB		 18608 case 'a':
18609 /* Byte swap code words. */
18610 while (ptr + 3 < end)
99059e56
RM		 18611 {
18612 tmp = contents[ptr];
18613 contents[ptr] = contents[ptr + 3];
18614 contents[ptr + 3] = tmp;
18615 tmp = contents[ptr + 1];
18616 contents[ptr + 1] = contents[ptr + 2];
18617 contents[ptr + 2] = tmp;
18618 ptr += 4;
18619 }
c7b8f16e 18620 break;
e489d0ae 18621
c7b8f16e
JB		 18622 case 't':
18623 /* Byte swap code halfwords. */
18624 while (ptr + 1 < end)
99059e56
RM		 18625 {
18626 tmp = contents[ptr];
18627 contents[ptr] = contents[ptr + 1];
18628 contents[ptr + 1] = tmp;
18629 ptr += 2;
18630 }
c7b8f16e
JB		 18631 break;
18632
18633 case 'd':
18634 /* Leave data alone. */
18635 break;
18636 }
99059e56
RM		 18637 ptr = end;
18638 }
e489d0ae 18639 }
8e3de13a 18640
93204d3a 18641 free (map);
47b2e99c 18642 arm_data->mapcount = -1;
c7b8f16e 18643 arm_data->mapsize = 0;
8e3de13a 18644 arm_data->map = NULL;
8e3de13a 18645
e489d0ae
PB		 18646 return FALSE;
18647}
18648
0beaef2b
PB		 18649/* Mangle thumb function symbols as we read them in. */
18650
8384fb8f 18651static bfd_boolean
0beaef2b
PB		 18652elf32_arm_swap_symbol_in (bfd * abfd,
18653 const void *psrc,
18654 const void *pshn,
18655 Elf_Internal_Sym *dst)
18656{
4ba2ef8f
TP		 18657 Elf_Internal_Shdr *symtab_hdr;
18658 const char *name = NULL;
18659
8384fb8f
AM		 18660 if (!bfd_elf32_swap_symbol_in (abfd, psrc, pshn, dst))
18661 return FALSE;
39d911fc 18662 dst->st_target_internal = 0;
0beaef2b
PB		 18663
18664 /* New EABI objects mark thumb function symbols by setting the low bit of
35fc36a8 18665 the address. */
63e1a0fc
PB		 18666 if (ELF_ST_TYPE (dst->st_info) == STT_FUNC
18667 || ELF_ST_TYPE (dst->st_info) == STT_GNU_IFUNC)
0beaef2b 18668 {
63e1a0fc
PB		 18669 if (dst->st_value & 1)
18670 {
18671 dst->st_value &= ~(bfd_vma) 1;
39d911fc
TP		 18672 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal,
18673 ST_BRANCH_TO_THUMB);
63e1a0fc
PB		 18674 }
18675 else
39d911fc 18676 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_ARM);
35fc36a8
RS		 18677 }
18678 else if (ELF_ST_TYPE (dst->st_info) == STT_ARM_TFUNC)
18679 {
18680 dst->st_info = ELF_ST_INFO (ELF_ST_BIND (dst->st_info), STT_FUNC);
39d911fc 18681 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_THUMB);
0beaef2b 18682 }
35fc36a8 18683 else if (ELF_ST_TYPE (dst->st_info) == STT_SECTION)
39d911fc 18684 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_LONG);
35fc36a8 18685 else
39d911fc 18686 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_UNKNOWN);
35fc36a8 18687
4ba2ef8f
TP		 18688 /* Mark CMSE special symbols. */
18689 symtab_hdr = & elf_symtab_hdr (abfd);
18690 if (symtab_hdr->sh_size)
18691 name = bfd_elf_sym_name (abfd, symtab_hdr, dst, NULL);
18692 if (name && CONST_STRNEQ (name, CMSE_PREFIX))
18693 ARM_SET_SYM_CMSE_SPCL (dst->st_target_internal);
18694
8384fb8f 18695 return TRUE;
0beaef2b
PB		 18696}
18697
18698
18699/* Mangle thumb function symbols as we write them out. */
18700
18701static void
18702elf32_arm_swap_symbol_out (bfd *abfd,
18703 const Elf_Internal_Sym *src,
18704 void *cdst,
18705 void *shndx)
18706{
18707 Elf_Internal_Sym newsym;
18708
18709 /* We convert STT_ARM_TFUNC symbols into STT_FUNC with the low bit
18710 of the address set, as per the new EABI. We do this unconditionally
18711 because objcopy does not set the elf header flags until after
18712 it writes out the symbol table. */
39d911fc 18713 if (ARM_GET_SYM_BRANCH_TYPE (src->st_target_internal) == ST_BRANCH_TO_THUMB)
0beaef2b
PB		 18714 {
18715 newsym = *src;
34e77a92
RS		 18716 if (ELF_ST_TYPE (src->st_info) != STT_GNU_IFUNC)
18717 newsym.st_info = ELF_ST_INFO (ELF_ST_BIND (src->st_info), STT_FUNC);
0fa3dcad 18718 if (newsym.st_shndx != SHN_UNDEF)
99059e56
RM		 18719 {
18720 /* Do this only for defined symbols. At link type, the static
18721 linker will simulate the work of dynamic linker of resolving
18722 symbols and will carry over the thumbness of found symbols to
18723 the output symbol table. It's not clear how it happens, but
18724 the thumbness of undefined symbols can well be different at
18725 runtime, and writing '1' for them will be confusing for users
18726 and possibly for dynamic linker itself.
18727 */
18728 newsym.st_value |= 1;
18729 }
906e58ca 18730
0beaef2b
PB		 18731 src = &newsym;
18732 }
18733 bfd_elf32_swap_symbol_out (abfd, src, cdst, shndx);
18734}
18735
b294bdf8
MM		 18736/* Add the PT_ARM_EXIDX program header. */
18737
18738static bfd_boolean
906e58ca 18739elf32_arm_modify_segment_map (bfd *abfd,
b294bdf8
MM		 18740 struct bfd_link_info *info ATTRIBUTE_UNUSED)
18741{
18742 struct elf_segment_map *m;
18743 asection *sec;
18744
18745 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
18746 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
18747 {
18748 /* If there is already a PT_ARM_EXIDX header, then we do not
18749 want to add another one. This situation arises when running
18750 "strip"; the input binary already has the header. */
12bd6957 18751 m = elf_seg_map (abfd);
b294bdf8
MM		 18752 while (m && m->p_type != PT_ARM_EXIDX)
18753 m = m->next;
18754 if (!m)
18755 {
21d799b5 18756 m = (struct elf_segment_map *)
99059e56 18757 bfd_zalloc (abfd, sizeof (struct elf_segment_map));
b294bdf8
MM		 18758 if (m == NULL)
18759 return FALSE;
18760 m->p_type = PT_ARM_EXIDX;
18761 m->count = 1;
18762 m->sections[0] = sec;
18763
12bd6957
AM		 18764 m->next = elf_seg_map (abfd);
18765 elf_seg_map (abfd) = m;
b294bdf8
MM		 18766 }
18767 }
18768
18769 return TRUE;
18770}
18771
18772/* We may add a PT_ARM_EXIDX program header. */
18773
18774static int
a6b96beb
AM		 18775elf32_arm_additional_program_headers (bfd *abfd,
18776 struct bfd_link_info *info ATTRIBUTE_UNUSED)
b294bdf8
MM		 18777{
18778 asection *sec;
18779
18780 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
18781 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
18782 return 1;
18783 else
18784 return 0;
18785}
18786
34e77a92
RS		 18787/* Hook called by the linker routine which adds symbols from an object
18788 file. */
18789
18790static bfd_boolean
18791elf32_arm_add_symbol_hook (bfd *abfd, struct bfd_link_info *info,
18792 Elf_Internal_Sym *sym, const char **namep,
18793 flagword *flagsp, asection **secp, bfd_vma *valp)
18794{
a43942db 18795 if (ELF_ST_TYPE (sym->st_info) == STT_GNU_IFUNC
f1885d1e
AM		 18796 && (abfd->flags & DYNAMIC) == 0
18797 && bfd_get_flavour (info->output_bfd) == bfd_target_elf_flavour)
a43942db 18798 elf_tdata (info->output_bfd)->has_gnu_symbols |= elf_gnu_symbol_ifunc;
34e77a92 18799
c792917c
NC		 18800 if (elf32_arm_hash_table (info) == NULL)
18801 return FALSE;
18802
34e77a92
RS		 18803 if (elf32_arm_hash_table (info)->vxworks_p
18804 && !elf_vxworks_add_symbol_hook (abfd, info, sym, namep,
18805 flagsp, secp, valp))
18806 return FALSE;
18807
18808 return TRUE;
18809}
18810
0beaef2b 18811/* We use this to override swap_symbol_in and swap_symbol_out. */
906e58ca
NC		 18812const struct elf_size_info elf32_arm_size_info =
18813{
0beaef2b
PB		 18814 sizeof (Elf32_External_Ehdr),
18815 sizeof (Elf32_External_Phdr),
18816 sizeof (Elf32_External_Shdr),
18817 sizeof (Elf32_External_Rel),
18818 sizeof (Elf32_External_Rela),
18819 sizeof (Elf32_External_Sym),
18820 sizeof (Elf32_External_Dyn),
18821 sizeof (Elf_External_Note),
18822 4,
18823 1,
18824 32, 2,
18825 ELFCLASS32, EV_CURRENT,
18826 bfd_elf32_write_out_phdrs,
18827 bfd_elf32_write_shdrs_and_ehdr,
1489a3a0 18828 bfd_elf32_checksum_contents,
0beaef2b
PB		 18829 bfd_elf32_write_relocs,
18830 elf32_arm_swap_symbol_in,
18831 elf32_arm_swap_symbol_out,
18832 bfd_elf32_slurp_reloc_table,
18833 bfd_elf32_slurp_symbol_table,
18834 bfd_elf32_swap_dyn_in,
18835 bfd_elf32_swap_dyn_out,
18836 bfd_elf32_swap_reloc_in,
18837 bfd_elf32_swap_reloc_out,
18838 bfd_elf32_swap_reloca_in,
18839 bfd_elf32_swap_reloca_out
18840};
18841
685e70ae
VK		 18842static bfd_vma
18843read_code32 (const bfd *abfd, const bfd_byte *addr)
18844{
18845 /* V7 BE8 code is always little endian. */
18846 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
18847 return bfd_getl32 (addr);
18848
18849 return bfd_get_32 (abfd, addr);
18850}
18851
18852static bfd_vma
18853read_code16 (const bfd *abfd, const bfd_byte *addr)
18854{
18855 /* V7 BE8 code is always little endian. */
18856 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
18857 return bfd_getl16 (addr);
18858
18859 return bfd_get_16 (abfd, addr);
18860}
18861
6a631e86
YG		 18862/* Return size of plt0 entry starting at ADDR
18863 or (bfd_vma) -1 if size can not be determined. */
18864
18865static bfd_vma
18866elf32_arm_plt0_size (const bfd *abfd, const bfd_byte *addr)
18867{
18868 bfd_vma first_word;
18869 bfd_vma plt0_size;
18870
685e70ae 18871 first_word = read_code32 (abfd, addr);
6a631e86
YG		 18872
18873 if (first_word == elf32_arm_plt0_entry[0])
18874 plt0_size = 4 * ARRAY_SIZE (elf32_arm_plt0_entry);
18875 else if (first_word == elf32_thumb2_plt0_entry[0])
18876 plt0_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
18877 else
18878 /* We don't yet handle this PLT format. */
18879 return (bfd_vma) -1;
18880
18881 return plt0_size;
18882}
18883
18884/* Return size of plt entry starting at offset OFFSET
18885 of plt section located at address START
18886 or (bfd_vma) -1 if size can not be determined. */
18887
18888static bfd_vma
18889elf32_arm_plt_size (const bfd *abfd, const bfd_byte *start, bfd_vma offset)
18890{
18891 bfd_vma first_insn;
18892 bfd_vma plt_size = 0;
18893 const bfd_byte *addr = start + offset;
18894
18895 /* PLT entry size if fixed on Thumb-only platforms. */
685e70ae 18896 if (read_code32 (abfd, start) == elf32_thumb2_plt0_entry[0])
6a631e86
YG		 18897 return 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
18898
18899 /* Respect Thumb stub if necessary. */
685e70ae 18900 if (read_code16 (abfd, addr) == elf32_arm_plt_thumb_stub[0])
6a631e86
YG		 18901 {
18902 plt_size += 2 * ARRAY_SIZE(elf32_arm_plt_thumb_stub);
18903 }
18904
18905 /* Strip immediate from first add. */
685e70ae 18906 first_insn = read_code32 (abfd, addr + plt_size) & 0xffffff00;
6a631e86
YG		 18907
18908#ifdef FOUR_WORD_PLT
18909 if (first_insn == elf32_arm_plt_entry[0])
18910 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry);
18911#else
18912 if (first_insn == elf32_arm_plt_entry_long[0])
18913 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_long);
18914 else if (first_insn == elf32_arm_plt_entry_short[0])
18915 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_short);
18916#endif
18917 else
18918 /* We don't yet handle this PLT format. */
18919 return (bfd_vma) -1;
18920
18921 return plt_size;
18922}
18923
18924/* Implementation is shamelessly borrowed from _bfd_elf_get_synthetic_symtab. */
18925
18926static long
18927elf32_arm_get_synthetic_symtab (bfd *abfd,
18928 long symcount ATTRIBUTE_UNUSED,
18929 asymbol **syms ATTRIBUTE_UNUSED,
18930 long dynsymcount,
18931 asymbol **dynsyms,
18932 asymbol **ret)
18933{
18934 asection *relplt;
18935 asymbol *s;
18936 arelent *p;
18937 long count, i, n;
18938 size_t size;
18939 Elf_Internal_Shdr *hdr;
18940 char *names;
18941 asection *plt;
18942 bfd_vma offset;
18943 bfd_byte *data;
18944
18945 *ret = NULL;
18946
18947 if ((abfd->flags & (DYNAMIC | EXEC_P)) == 0)
18948 return 0;
18949
18950 if (dynsymcount <= 0)
18951 return 0;
18952
18953 relplt = bfd_get_section_by_name (abfd, ".rel.plt");
18954 if (relplt == NULL)
18955 return 0;
18956
18957 hdr = &elf_section_data (relplt)->this_hdr;
18958 if (hdr->sh_link != elf_dynsymtab (abfd)
18959 || (hdr->sh_type != SHT_REL && hdr->sh_type != SHT_RELA))
18960 return 0;
18961
18962 plt = bfd_get_section_by_name (abfd, ".plt");
18963 if (plt == NULL)
18964 return 0;
18965
18966 if (!elf32_arm_size_info.slurp_reloc_table (abfd, relplt, dynsyms, TRUE))
18967 return -1;
18968
18969 data = plt->contents;
18970 if (data == NULL)
18971 {
18972 if (!bfd_get_full_section_contents(abfd, (asection *) plt, &data) || data == NULL)
18973 return -1;
18974 bfd_cache_section_contents((asection *) plt, data);
18975 }
18976
18977 count = relplt->size / hdr->sh_entsize;
18978 size = count * sizeof (asymbol);
18979 p = relplt->relocation;
18980 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
18981 {
18982 size += strlen ((*p->sym_ptr_ptr)->name) + sizeof ("@plt");
18983 if (p->addend != 0)
18984 size += sizeof ("+0x") - 1 + 8;
18985 }
18986
18987 s = *ret = (asymbol *) bfd_malloc (size);
18988 if (s == NULL)
18989 return -1;
18990
18991 offset = elf32_arm_plt0_size (abfd, data);
18992 if (offset == (bfd_vma) -1)
18993 return -1;
18994
18995 names = (char *) (s + count);
18996 p = relplt->relocation;
18997 n = 0;
18998 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
18999 {
19000 size_t len;
19001
19002 bfd_vma plt_size = elf32_arm_plt_size (abfd, data, offset);
19003 if (plt_size == (bfd_vma) -1)
19004 break;
19005
19006 *s = **p->sym_ptr_ptr;
19007 /* Undefined syms won't have BSF_LOCAL or BSF_GLOBAL set. Since
19008 we are defining a symbol, ensure one of them is set. */
19009 if ((s->flags & BSF_LOCAL) == 0)
19010 s->flags |= BSF_GLOBAL;
19011 s->flags |= BSF_SYNTHETIC;
19012 s->section = plt;
19013 s->value = offset;
19014 s->name = names;
19015 s->udata.p = NULL;
19016 len = strlen ((*p->sym_ptr_ptr)->name);
19017 memcpy (names, (*p->sym_ptr_ptr)->name, len);
19018 names += len;
19019 if (p->addend != 0)
19020 {
19021 char buf[30], *a;
19022
19023 memcpy (names, "+0x", sizeof ("+0x") - 1);
19024 names += sizeof ("+0x") - 1;
19025 bfd_sprintf_vma (abfd, buf, p->addend);
19026 for (a = buf; *a == '0'; ++a)
19027 ;
19028 len = strlen (a);
19029 memcpy (names, a, len);
19030 names += len;
19031 }
19032 memcpy (names, "@plt", sizeof ("@plt"));
19033 names += sizeof ("@plt");
19034 ++s, ++n;
19035 offset += plt_size;
19036 }
19037
19038 return n;
19039}
19040
ac4c9b04
MG		 19041static bfd_boolean
19042elf32_arm_section_flags (flagword *flags, const Elf_Internal_Shdr * hdr)
19043{
f0728ee3
AV		 19044 if (hdr->sh_flags & SHF_ARM_PURECODE)
19045 *flags |= SEC_ELF_PURECODE;
ac4c9b04
MG		 19046 return TRUE;
19047}
19048
19049static flagword
19050elf32_arm_lookup_section_flags (char *flag_name)
19051{
f0728ee3
AV		 19052 if (!strcmp (flag_name, "SHF_ARM_PURECODE"))
19053 return SHF_ARM_PURECODE;
ac4c9b04
MG		 19054
19055 return SEC_NO_FLAGS;
19056}
19057
491d01d3
YU		 19058static unsigned int
19059elf32_arm_count_additional_relocs (asection *sec)
19060{
19061 struct _arm_elf_section_data *arm_data;
19062 arm_data = get_arm_elf_section_data (sec);
6342be70 19063 return arm_data == NULL ? 0 : arm_data->additional_reloc_count;
491d01d3
YU		 19064}
19065
5522f910
NC		 19066/* Called to set the sh_flags, sh_link and sh_info fields of OSECTION which
19067 has a type >= SHT_LOOS. Returns TRUE if these fields were initialised
19068 FALSE otherwise. ISECTION is the best guess matching section from the
19069 input bfd IBFD, but it might be NULL. */
19070
19071static bfd_boolean
19072elf32_arm_copy_special_section_fields (const bfd *ibfd ATTRIBUTE_UNUSED,
19073 bfd *obfd ATTRIBUTE_UNUSED,
19074 const Elf_Internal_Shdr *isection ATTRIBUTE_UNUSED,
19075 Elf_Internal_Shdr *osection)
19076{
19077 switch (osection->sh_type)
19078 {
19079 case SHT_ARM_EXIDX:
19080 {
19081 Elf_Internal_Shdr **oheaders = elf_elfsections (obfd);
19082 Elf_Internal_Shdr **iheaders = elf_elfsections (ibfd);
19083 unsigned i = 0;
19084
19085 osection->sh_flags = SHF_ALLOC | SHF_LINK_ORDER;
19086 osection->sh_info = 0;
19087
19088 /* The sh_link field must be set to the text section associated with
19089 this index section. Unfortunately the ARM EHABI does not specify
19090 exactly how to determine this association. Our caller does try
19091 to match up OSECTION with its corresponding input section however
19092 so that is a good first guess. */
19093 if (isection != NULL
19094 && osection->bfd_section != NULL
19095 && isection->bfd_section != NULL
19096 && isection->bfd_section->output_section != NULL
19097 && isection->bfd_section->output_section == osection->bfd_section
19098 && iheaders != NULL
19099 && isection->sh_link > 0
19100 && isection->sh_link < elf_numsections (ibfd)
19101 && iheaders[isection->sh_link]->bfd_section != NULL
19102 && iheaders[isection->sh_link]->bfd_section->output_section != NULL
19103 )
19104 {
19105 for (i = elf_numsections (obfd); i-- > 0;)
19106 if (oheaders[i]->bfd_section
19107 == iheaders[isection->sh_link]->bfd_section->output_section)
19108 break;
19109 }
19110
19111 if (i == 0)
19112 {
19113 /* Failing that we have to find a matching section ourselves. If
19114 we had the output section name available we could compare that
19115 with input section names. Unfortunately we don't. So instead
19116 we use a simple heuristic and look for the nearest executable
19117 section before this one. */
19118 for (i = elf_numsections (obfd); i-- > 0;)
19119 if (oheaders[i] == osection)
19120 break;
19121 if (i == 0)
19122 break;
19123
19124 while (i-- > 0)
19125 if (oheaders[i]->sh_type == SHT_PROGBITS
19126 && (oheaders[i]->sh_flags & (SHF_ALLOC | SHF_EXECINSTR))
19127 == (SHF_ALLOC | SHF_EXECINSTR))
19128 break;
19129 }
19130
19131 if (i)
19132 {
19133 osection->sh_link = i;
19134 /* If the text section was part of a group
19135 then the index section should be too. */
19136 if (oheaders[i]->sh_flags & SHF_GROUP)
19137 osection->sh_flags |= SHF_GROUP;
19138 return TRUE;
19139 }
19140 }
19141 break;
19142
19143 case SHT_ARM_PREEMPTMAP:
19144 osection->sh_flags = SHF_ALLOC;
19145 break;
19146
19147 case SHT_ARM_ATTRIBUTES:
19148 case SHT_ARM_DEBUGOVERLAY:
19149 case SHT_ARM_OVERLAYSECTION:
19150 default:
19151 break;
19152 }
19153
19154 return FALSE;
19155}
19156
d691934d
NC		 19157/* Returns TRUE if NAME is an ARM mapping symbol.
19158 Traditionally the symbols $a, $d and $t have been used.
19159 The ARM ELF standard also defines $x (for A64 code). It also allows a
19160 period initiated suffix to be added to the symbol: "$[adtx]\.[:sym_char]+".
19161 Other tools might also produce $b (Thumb BL), $f, $p, $m and $v, but we do
19162 not support them here. $t.x indicates the start of ThumbEE instructions. */
19163
19164static bfd_boolean
19165is_arm_mapping_symbol (const char * name)
19166{
19167 return name != NULL /* Paranoia. */
19168 && name[0] == '$' /* Note: if objcopy --prefix-symbols has been used then
19169 the mapping symbols could have acquired a prefix.
19170 We do not support this here, since such symbols no
19171 longer conform to the ARM ELF ABI. */
19172 && (name[1] == 'a' || name[1] == 'd' || name[1] == 't' || name[1] == 'x')
19173 && (name[2] == 0 || name[2] == '.');
19174 /* FIXME: Strictly speaking the symbol is only a valid mapping symbol if
19175 any characters that follow the period are legal characters for the body
19176 of a symbol's name. For now we just assume that this is the case. */
19177}
19178
fca2a38f
NC		 19179/* Make sure that mapping symbols in object files are not removed via the
19180 "strip --strip-unneeded" tool. These symbols are needed in order to
19181 correctly generate interworking veneers, and for byte swapping code
19182 regions. Once an object file has been linked, it is safe to remove the
19183 symbols as they will no longer be needed. */
19184
19185static void
19186elf32_arm_backend_symbol_processing (bfd *abfd, asymbol *sym)
19187{
19188 if (((abfd->flags & (EXEC_P | DYNAMIC)) == 0)
fca2a38f 19189 && sym->section != bfd_abs_section_ptr
d691934d 19190 && is_arm_mapping_symbol (sym->name))
fca2a38f
NC		 19191 sym->flags |= BSF_KEEP;
19192}
19193
5522f910
NC		 19194#undef elf_backend_copy_special_section_fields
19195#define elf_backend_copy_special_section_fields elf32_arm_copy_special_section_fields
19196
252b5132 19197#define ELF_ARCH bfd_arch_arm
ae95ffa6 19198#define ELF_TARGET_ID ARM_ELF_DATA
252b5132 19199#define ELF_MACHINE_CODE EM_ARM
d0facd1b
NC		 19200#ifdef __QNXTARGET__
19201#define ELF_MAXPAGESIZE 0x1000
19202#else
7572ca89 19203#define ELF_MAXPAGESIZE 0x10000
d0facd1b 19204#endif
b1342370 19205#define ELF_MINPAGESIZE 0x1000
24718e3b 19206#define ELF_COMMONPAGESIZE 0x1000
252b5132 19207
ba93b8ac
DJ		 19208#define bfd_elf32_mkobject elf32_arm_mkobject
19209
99e4ae17
AJ		 19210#define bfd_elf32_bfd_copy_private_bfd_data elf32_arm_copy_private_bfd_data
19211#define bfd_elf32_bfd_merge_private_bfd_data elf32_arm_merge_private_bfd_data
252b5132
RH		 19212#define bfd_elf32_bfd_set_private_flags elf32_arm_set_private_flags
19213#define bfd_elf32_bfd_print_private_bfd_data elf32_arm_print_private_bfd_data
19214#define bfd_elf32_bfd_link_hash_table_create elf32_arm_link_hash_table_create
dc810e39 19215#define bfd_elf32_bfd_reloc_type_lookup elf32_arm_reloc_type_lookup
b38cadfb 19216#define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
252b5132 19217#define bfd_elf32_find_nearest_line elf32_arm_find_nearest_line
4ab527b0 19218#define bfd_elf32_find_inliner_info elf32_arm_find_inliner_info
e489d0ae 19219#define bfd_elf32_new_section_hook elf32_arm_new_section_hook
3c9458e9 19220#define bfd_elf32_bfd_is_target_special_symbol elf32_arm_is_target_special_symbol
3e6b1042 19221#define bfd_elf32_bfd_final_link elf32_arm_final_link
6a631e86 19222#define bfd_elf32_get_synthetic_symtab elf32_arm_get_synthetic_symtab
252b5132
RH		 19223
19224#define elf_backend_get_symbol_type elf32_arm_get_symbol_type
19225#define elf_backend_gc_mark_hook elf32_arm_gc_mark_hook
6a5bb875 19226#define elf_backend_gc_mark_extra_sections elf32_arm_gc_mark_extra_sections
252b5132
RH		 19227#define elf_backend_gc_sweep_hook elf32_arm_gc_sweep_hook
19228#define elf_backend_check_relocs elf32_arm_check_relocs
dc810e39 19229#define elf_backend_relocate_section elf32_arm_relocate_section
e489d0ae 19230#define elf_backend_write_section elf32_arm_write_section
252b5132 19231#define elf_backend_adjust_dynamic_symbol elf32_arm_adjust_dynamic_symbol
5e681ec4 19232#define elf_backend_create_dynamic_sections elf32_arm_create_dynamic_sections
252b5132
RH		 19233#define elf_backend_finish_dynamic_symbol elf32_arm_finish_dynamic_symbol
19234#define elf_backend_finish_dynamic_sections elf32_arm_finish_dynamic_sections
19235#define elf_backend_size_dynamic_sections elf32_arm_size_dynamic_sections
0855e32b 19236#define elf_backend_always_size_sections elf32_arm_always_size_sections
74541ad4 19237#define elf_backend_init_index_section _bfd_elf_init_2_index_sections
ba96a88f 19238#define elf_backend_post_process_headers elf32_arm_post_process_headers
99e4ae17 19239#define elf_backend_reloc_type_class elf32_arm_reloc_type_class
c178919b 19240#define elf_backend_object_p elf32_arm_object_p
40a18ebd
NC		 19241#define elf_backend_fake_sections elf32_arm_fake_sections
19242#define elf_backend_section_from_shdr elf32_arm_section_from_shdr
e16bb312 19243#define elf_backend_final_write_processing elf32_arm_final_write_processing
5e681ec4 19244#define elf_backend_copy_indirect_symbol elf32_arm_copy_indirect_symbol
0beaef2b 19245#define elf_backend_size_info elf32_arm_size_info
b294bdf8 19246#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
906e58ca
NC		 19247#define elf_backend_additional_program_headers elf32_arm_additional_program_headers
19248#define elf_backend_output_arch_local_syms elf32_arm_output_arch_local_syms
54ddd295 19249#define elf_backend_filter_implib_symbols elf32_arm_filter_implib_symbols
906e58ca 19250#define elf_backend_begin_write_processing elf32_arm_begin_write_processing
34e77a92 19251#define elf_backend_add_symbol_hook elf32_arm_add_symbol_hook
491d01d3 19252#define elf_backend_count_additional_relocs elf32_arm_count_additional_relocs
fca2a38f 19253#define elf_backend_symbol_processing elf32_arm_backend_symbol_processing
906e58ca
NC		 19254
19255#define elf_backend_can_refcount 1
19256#define elf_backend_can_gc_sections 1
19257#define elf_backend_plt_readonly 1
19258#define elf_backend_want_got_plt 1
19259#define elf_backend_want_plt_sym 0
19260#define elf_backend_may_use_rel_p 1
19261#define elf_backend_may_use_rela_p 0
4e7fd91e 19262#define elf_backend_default_use_rela_p 0
252b5132 19263
04f7c78d 19264#define elf_backend_got_header_size 12
b68a20d6 19265#define elf_backend_extern_protected_data 1
04f7c78d 19266
906e58ca
NC		 19267#undef elf_backend_obj_attrs_vendor
19268#define elf_backend_obj_attrs_vendor "aeabi"
19269#undef elf_backend_obj_attrs_section
19270#define elf_backend_obj_attrs_section ".ARM.attributes"
19271#undef elf_backend_obj_attrs_arg_type
19272#define elf_backend_obj_attrs_arg_type elf32_arm_obj_attrs_arg_type
19273#undef elf_backend_obj_attrs_section_type
104d59d1 19274#define elf_backend_obj_attrs_section_type SHT_ARM_ATTRIBUTES
b38cadfb
NC		 19275#define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
19276#define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
104d59d1 19277
ac4c9b04
MG		 19278#undef elf_backend_section_flags
19279#define elf_backend_section_flags elf32_arm_section_flags
19280#undef elf_backend_lookup_section_flags_hook
19281#define elf_backend_lookup_section_flags_hook elf32_arm_lookup_section_flags
19282
252b5132 19283#include "elf32-target.h"
7f266840 19284
b38cadfb
NC		 19285/* Native Client targets. */
19286
19287#undef TARGET_LITTLE_SYM
6d00b590 19288#define TARGET_LITTLE_SYM arm_elf32_nacl_le_vec
b38cadfb
NC		 19289#undef TARGET_LITTLE_NAME
19290#define TARGET_LITTLE_NAME "elf32-littlearm-nacl"
19291#undef TARGET_BIG_SYM
6d00b590 19292#define TARGET_BIG_SYM arm_elf32_nacl_be_vec
b38cadfb
NC		 19293#undef TARGET_BIG_NAME
19294#define TARGET_BIG_NAME "elf32-bigarm-nacl"
19295
19296/* Like elf32_arm_link_hash_table_create -- but overrides
19297 appropriately for NaCl. */
19298
19299static struct bfd_link_hash_table *
19300elf32_arm_nacl_link_hash_table_create (bfd *abfd)
19301{
19302 struct bfd_link_hash_table *ret;
19303
19304 ret = elf32_arm_link_hash_table_create (abfd);
19305 if (ret)
19306 {
19307 struct elf32_arm_link_hash_table *htab
19308 = (struct elf32_arm_link_hash_table *) ret;
19309
19310 htab->nacl_p = 1;
19311
19312 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt0_entry);
19313 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt_entry);
19314 }
19315 return ret;
19316}
19317
19318/* Since NaCl doesn't use the ARM-specific unwind format, we don't
19319 really need to use elf32_arm_modify_segment_map. But we do it
19320 anyway just to reduce gratuitous differences with the stock ARM backend. */
19321
19322static bfd_boolean
19323elf32_arm_nacl_modify_segment_map (bfd *abfd, struct bfd_link_info *info)
19324{
19325 return (elf32_arm_modify_segment_map (abfd, info)
19326 && nacl_modify_segment_map (abfd, info));
19327}
19328
887badb3
RM		 19329static void
19330elf32_arm_nacl_final_write_processing (bfd *abfd, bfd_boolean linker)
19331{
19332 elf32_arm_final_write_processing (abfd, linker);
19333 nacl_final_write_processing (abfd, linker);
19334}
19335
6a631e86
YG		 19336static bfd_vma
19337elf32_arm_nacl_plt_sym_val (bfd_vma i, const asection *plt,
19338 const arelent *rel ATTRIBUTE_UNUSED)
19339{
19340 return plt->vma
19341 + 4 * (ARRAY_SIZE (elf32_arm_nacl_plt0_entry) +
19342 i * ARRAY_SIZE (elf32_arm_nacl_plt_entry));
19343}
887badb3 19344
b38cadfb 19345#undef elf32_bed
6a631e86 19346#define elf32_bed elf32_arm_nacl_bed
b38cadfb
NC		 19347#undef bfd_elf32_bfd_link_hash_table_create
19348#define bfd_elf32_bfd_link_hash_table_create \
19349 elf32_arm_nacl_link_hash_table_create
19350#undef elf_backend_plt_alignment
6a631e86 19351#define elf_backend_plt_alignment 4
b38cadfb
NC		 19352#undef elf_backend_modify_segment_map
19353#define elf_backend_modify_segment_map elf32_arm_nacl_modify_segment_map
19354#undef elf_backend_modify_program_headers
19355#define elf_backend_modify_program_headers nacl_modify_program_headers
887badb3
RM		 19356#undef elf_backend_final_write_processing
19357#define elf_backend_final_write_processing elf32_arm_nacl_final_write_processing
6a631e86
YG		 19358#undef bfd_elf32_get_synthetic_symtab
19359#undef elf_backend_plt_sym_val
19360#define elf_backend_plt_sym_val elf32_arm_nacl_plt_sym_val
5522f910 19361#undef elf_backend_copy_special_section_fields
b38cadfb 19362
887badb3
RM		 19363#undef ELF_MINPAGESIZE
19364#undef ELF_COMMONPAGESIZE
19365
b38cadfb
NC		 19366
19367#include "elf32-target.h"
19368
19369/* Reset to defaults. */
19370#undef elf_backend_plt_alignment
19371#undef elf_backend_modify_segment_map
19372#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
19373#undef elf_backend_modify_program_headers
887badb3
RM		 19374#undef elf_backend_final_write_processing
19375#define elf_backend_final_write_processing elf32_arm_final_write_processing
19376#undef ELF_MINPAGESIZE
19377#define ELF_MINPAGESIZE 0x1000
19378#undef ELF_COMMONPAGESIZE
19379#define ELF_COMMONPAGESIZE 0x1000
19380
b38cadfb 19381
906e58ca 19382/* VxWorks Targets. */
4e7fd91e 19383
906e58ca 19384#undef TARGET_LITTLE_SYM
6d00b590 19385#define TARGET_LITTLE_SYM arm_elf32_vxworks_le_vec
906e58ca 19386#undef TARGET_LITTLE_NAME
4e7fd91e 19387#define TARGET_LITTLE_NAME "elf32-littlearm-vxworks"
906e58ca 19388#undef TARGET_BIG_SYM
6d00b590 19389#define TARGET_BIG_SYM arm_elf32_vxworks_be_vec
906e58ca 19390#undef TARGET_BIG_NAME
4e7fd91e
PB		 19391#define TARGET_BIG_NAME "elf32-bigarm-vxworks"
19392
19393/* Like elf32_arm_link_hash_table_create -- but overrides
19394 appropriately for VxWorks. */
906e58ca 19395
4e7fd91e
PB		 19396static struct bfd_link_hash_table *
19397elf32_arm_vxworks_link_hash_table_create (bfd *abfd)
19398{
19399 struct bfd_link_hash_table *ret;
19400
19401 ret = elf32_arm_link_hash_table_create (abfd);
19402 if (ret)
19403 {
19404 struct elf32_arm_link_hash_table *htab
00a97672 19405 = (struct elf32_arm_link_hash_table *) ret;
4e7fd91e 19406 htab->use_rel = 0;
00a97672 19407 htab->vxworks_p = 1;
4e7fd91e
PB		 19408 }
19409 return ret;
906e58ca 19410}
4e7fd91e 19411
00a97672
RS		 19412static void
19413elf32_arm_vxworks_final_write_processing (bfd *abfd, bfd_boolean linker)
19414{
19415 elf32_arm_final_write_processing (abfd, linker);
19416 elf_vxworks_final_write_processing (abfd, linker);
19417}
19418
906e58ca 19419#undef elf32_bed
4e7fd91e
PB		 19420#define elf32_bed elf32_arm_vxworks_bed
19421
906e58ca
NC		 19422#undef bfd_elf32_bfd_link_hash_table_create
19423#define bfd_elf32_bfd_link_hash_table_create elf32_arm_vxworks_link_hash_table_create
906e58ca
NC		 19424#undef elf_backend_final_write_processing
19425#define elf_backend_final_write_processing elf32_arm_vxworks_final_write_processing
19426#undef elf_backend_emit_relocs
19427#define elf_backend_emit_relocs elf_vxworks_emit_relocs
4e7fd91e 19428
906e58ca 19429#undef elf_backend_may_use_rel_p
00a97672 19430#define elf_backend_may_use_rel_p 0
906e58ca 19431#undef elf_backend_may_use_rela_p
00a97672 19432#define elf_backend_may_use_rela_p 1
906e58ca 19433#undef elf_backend_default_use_rela_p
00a97672 19434#define elf_backend_default_use_rela_p 1
906e58ca 19435#undef elf_backend_want_plt_sym
00a97672 19436#define elf_backend_want_plt_sym 1
906e58ca 19437#undef ELF_MAXPAGESIZE
00a97672 19438#define ELF_MAXPAGESIZE 0x1000
4e7fd91e
PB		 19439
19440#include "elf32-target.h"
19441
19442
21d799b5
NC		 19443/* Merge backend specific data from an object file to the output
19444 object file when linking. */
19445
19446static bfd_boolean
19447elf32_arm_merge_private_bfd_data (bfd * ibfd, bfd * obfd)
19448{
19449 flagword out_flags;
19450 flagword in_flags;
19451 bfd_boolean flags_compatible = TRUE;
19452 asection *sec;
19453
cc643b88 19454 /* Check if we have the same endianness. */
21d799b5
NC		 19455 if (! _bfd_generic_verify_endian_match (ibfd, obfd))
19456 return FALSE;
19457
19458 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
19459 return TRUE;
19460
19461 if (!elf32_arm_merge_eabi_attributes (ibfd, obfd))
19462 return FALSE;
19463
19464 /* The input BFD must have had its flags initialised. */
19465 /* The following seems bogus to me -- The flags are initialized in
19466 the assembler but I don't think an elf_flags_init field is
19467 written into the object. */
19468 /* BFD_ASSERT (elf_flags_init (ibfd)); */
19469
19470 in_flags = elf_elfheader (ibfd)->e_flags;
19471 out_flags = elf_elfheader (obfd)->e_flags;
19472
19473 /* In theory there is no reason why we couldn't handle this. However
19474 in practice it isn't even close to working and there is no real
19475 reason to want it. */
19476 if (EF_ARM_EABI_VERSION (in_flags) >= EF_ARM_EABI_VER4
19477 && !(ibfd->flags & DYNAMIC)
19478 && (in_flags & EF_ARM_BE8))
19479 {
19480 _bfd_error_handler (_("error: %B is already in final BE8 format"),
19481 ibfd);
19482 return FALSE;
19483 }
19484
19485 if (!elf_flags_init (obfd))
19486 {
19487 /* If the input is the default architecture and had the default
19488 flags then do not bother setting the flags for the output
19489 architecture, instead allow future merges to do this. If no
19490 future merges ever set these flags then they will retain their
99059e56
RM		 19491 uninitialised values, which surprise surprise, correspond
19492 to the default values. */
21d799b5
NC		 19493 if (bfd_get_arch_info (ibfd)->the_default
19494 && elf_elfheader (ibfd)->e_flags == 0)
19495 return TRUE;
19496
19497 elf_flags_init (obfd) = TRUE;
19498 elf_elfheader (obfd)->e_flags = in_flags;
19499
19500 if (bfd_get_arch (obfd) == bfd_get_arch (ibfd)
19501 && bfd_get_arch_info (obfd)->the_default)
19502 return bfd_set_arch_mach (obfd, bfd_get_arch (ibfd), bfd_get_mach (ibfd));
19503
19504 return TRUE;
19505 }
19506
19507 /* Determine what should happen if the input ARM architecture
19508 does not match the output ARM architecture. */
19509 if (! bfd_arm_merge_machines (ibfd, obfd))
19510 return FALSE;
19511
19512 /* Identical flags must be compatible. */
19513 if (in_flags == out_flags)
19514 return TRUE;
19515
19516 /* Check to see if the input BFD actually contains any sections. If
19517 not, its flags may not have been initialised either, but it
19518 cannot actually cause any incompatiblity. Do not short-circuit
19519 dynamic objects; their section list may be emptied by
19520 elf_link_add_object_symbols.
19521
19522 Also check to see if there are no code sections in the input.
19523 In this case there is no need to check for code specific flags.
19524 XXX - do we need to worry about floating-point format compatability
19525 in data sections ? */
19526 if (!(ibfd->flags & DYNAMIC))
19527 {
19528 bfd_boolean null_input_bfd = TRUE;
19529 bfd_boolean only_data_sections = TRUE;
19530
19531 for (sec = ibfd->sections; sec != NULL; sec = sec->next)
19532 {
19533 /* Ignore synthetic glue sections. */
19534 if (strcmp (sec->name, ".glue_7")
19535 && strcmp (sec->name, ".glue_7t"))
19536 {
19537 if ((bfd_get_section_flags (ibfd, sec)
19538 & (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
19539 == (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
99059e56 19540 only_data_sections = FALSE;
21d799b5
NC		 19541
19542 null_input_bfd = FALSE;
19543 break;
19544 }
19545 }
19546
19547 if (null_input_bfd || only_data_sections)
19548 return TRUE;
19549 }
19550
19551 /* Complain about various flag mismatches. */
19552 if (!elf32_arm_versions_compatible (EF_ARM_EABI_VERSION (in_flags),
19553 EF_ARM_EABI_VERSION (out_flags)))
19554 {
19555 _bfd_error_handler
19556 (_("error: Source object %B has EABI version %d, but target %B has EABI version %d"),
19557 ibfd, obfd,
19558 (in_flags & EF_ARM_EABIMASK) >> 24,
19559 (out_flags & EF_ARM_EABIMASK) >> 24);
19560 return FALSE;
19561 }
19562
19563 /* Not sure what needs to be checked for EABI versions >= 1. */
19564 /* VxWorks libraries do not use these flags. */
19565 if (get_elf_backend_data (obfd) != &elf32_arm_vxworks_bed
19566 && get_elf_backend_data (ibfd) != &elf32_arm_vxworks_bed
19567 && EF_ARM_EABI_VERSION (in_flags) == EF_ARM_EABI_UNKNOWN)
19568 {
19569 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
19570 {
19571 _bfd_error_handler
19572 (_("error: %B is compiled for APCS-%d, whereas target %B uses APCS-%d"),
19573 ibfd, obfd,
19574 in_flags & EF_ARM_APCS_26 ? 26 : 32,
19575 out_flags & EF_ARM_APCS_26 ? 26 : 32);
19576 flags_compatible = FALSE;
19577 }
19578
19579 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
19580 {
19581 if (in_flags & EF_ARM_APCS_FLOAT)
19582 _bfd_error_handler
19583 (_("error: %B passes floats in float registers, whereas %B passes them in integer registers"),
19584 ibfd, obfd);
19585 else
19586 _bfd_error_handler
19587 (_("error: %B passes floats in integer registers, whereas %B passes them in float registers"),
19588 ibfd, obfd);
19589
19590 flags_compatible = FALSE;
19591 }
19592
19593 if ((in_flags & EF_ARM_VFP_FLOAT) != (out_flags & EF_ARM_VFP_FLOAT))
19594 {
19595 if (in_flags & EF_ARM_VFP_FLOAT)
19596 _bfd_error_handler
19597 (_("error: %B uses VFP instructions, whereas %B does not"),
19598 ibfd, obfd);
19599 else
19600 _bfd_error_handler
19601 (_("error: %B uses FPA instructions, whereas %B does not"),
19602 ibfd, obfd);
19603
19604 flags_compatible = FALSE;
19605 }
19606
19607 if ((in_flags & EF_ARM_MAVERICK_FLOAT) != (out_flags & EF_ARM_MAVERICK_FLOAT))
19608 {
19609 if (in_flags & EF_ARM_MAVERICK_FLOAT)
19610 _bfd_error_handler
19611 (_("error: %B uses Maverick instructions, whereas %B does not"),
19612 ibfd, obfd);
19613 else
19614 _bfd_error_handler
19615 (_("error: %B does not use Maverick instructions, whereas %B does"),
19616 ibfd, obfd);
19617
19618 flags_compatible = FALSE;
19619 }
19620
19621#ifdef EF_ARM_SOFT_FLOAT
19622 if ((in_flags & EF_ARM_SOFT_FLOAT) != (out_flags & EF_ARM_SOFT_FLOAT))
19623 {
19624 /* We can allow interworking between code that is VFP format
19625 layout, and uses either soft float or integer regs for
19626 passing floating point arguments and results. We already
19627 know that the APCS_FLOAT flags match; similarly for VFP
19628 flags. */
19629 if ((in_flags & EF_ARM_APCS_FLOAT) != 0
19630 || (in_flags & EF_ARM_VFP_FLOAT) == 0)
19631 {
19632 if (in_flags & EF_ARM_SOFT_FLOAT)
19633 _bfd_error_handler
19634 (_("error: %B uses software FP, whereas %B uses hardware FP"),
19635 ibfd, obfd);
19636 else
19637 _bfd_error_handler
19638 (_("error: %B uses hardware FP, whereas %B uses software FP"),
19639 ibfd, obfd);
19640
19641 flags_compatible = FALSE;
19642 }
19643 }
19644#endif
19645
19646 /* Interworking mismatch is only a warning. */
19647 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
19648 {
19649 if (in_flags & EF_ARM_INTERWORK)
19650 {
19651 _bfd_error_handler
19652 (_("Warning: %B supports interworking, whereas %B does not"),
19653 ibfd, obfd);
19654 }
19655 else
19656 {
19657 _bfd_error_handler
19658 (_("Warning: %B does not support interworking, whereas %B does"),
19659 ibfd, obfd);
19660 }
19661 }
19662 }
19663
19664 return flags_compatible;
19665}
19666
19667
906e58ca 19668/* Symbian OS Targets. */
7f266840 19669
906e58ca 19670#undef TARGET_LITTLE_SYM
6d00b590 19671#define TARGET_LITTLE_SYM arm_elf32_symbian_le_vec
906e58ca 19672#undef TARGET_LITTLE_NAME
7f266840 19673#define TARGET_LITTLE_NAME "elf32-littlearm-symbian"
906e58ca 19674#undef TARGET_BIG_SYM
6d00b590 19675#define TARGET_BIG_SYM arm_elf32_symbian_be_vec
906e58ca 19676#undef TARGET_BIG_NAME
7f266840
DJ		 19677#define TARGET_BIG_NAME "elf32-bigarm-symbian"
19678
19679/* Like elf32_arm_link_hash_table_create -- but overrides
19680 appropriately for Symbian OS. */
906e58ca 19681
7f266840
DJ		 19682static struct bfd_link_hash_table *
19683elf32_arm_symbian_link_hash_table_create (bfd *abfd)
19684{
19685 struct bfd_link_hash_table *ret;
19686
19687 ret = elf32_arm_link_hash_table_create (abfd);
19688 if (ret)
19689 {
19690 struct elf32_arm_link_hash_table *htab
19691 = (struct elf32_arm_link_hash_table *)ret;
19692 /* There is no PLT header for Symbian OS. */
19693 htab->plt_header_size = 0;
95720a86
DJ		 19694 /* The PLT entries are each one instruction and one word. */
19695 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry);
7f266840 19696 htab->symbian_p = 1;
33bfe774
JB		 19697 /* Symbian uses armv5t or above, so use_blx is always true. */
19698 htab->use_blx = 1;
67687978 19699 htab->root.is_relocatable_executable = 1;
7f266840
DJ		 19700 }
19701 return ret;
906e58ca 19702}
7f266840 19703
b35d266b 19704static const struct bfd_elf_special_section
551b43fd 19705elf32_arm_symbian_special_sections[] =
7f266840 19706{
5cd3778d
MM		 19707 /* In a BPABI executable, the dynamic linking sections do not go in
19708 the loadable read-only segment. The post-linker may wish to
19709 refer to these sections, but they are not part of the final
19710 program image. */
0112cd26
NC		 19711 { STRING_COMMA_LEN (".dynamic"), 0, SHT_DYNAMIC, 0 },
19712 { STRING_COMMA_LEN (".dynstr"), 0, SHT_STRTAB, 0 },
19713 { STRING_COMMA_LEN (".dynsym"), 0, SHT_DYNSYM, 0 },
19714 { STRING_COMMA_LEN (".got"), 0, SHT_PROGBITS, 0 },
19715 { STRING_COMMA_LEN (".hash"), 0, SHT_HASH, 0 },
5cd3778d
MM		 19716 /* These sections do not need to be writable as the SymbianOS
19717 postlinker will arrange things so that no dynamic relocation is
19718 required. */
0112cd26
NC		 19719 { STRING_COMMA_LEN (".init_array"), 0, SHT_INIT_ARRAY, SHF_ALLOC },
19720 { STRING_COMMA_LEN (".fini_array"), 0, SHT_FINI_ARRAY, SHF_ALLOC },
19721 { STRING_COMMA_LEN (".preinit_array"), 0, SHT_PREINIT_ARRAY, SHF_ALLOC },
19722 { NULL, 0, 0, 0, 0 }
7f266840
DJ		 19723};
19724
c3c76620 19725static void
906e58ca 19726elf32_arm_symbian_begin_write_processing (bfd *abfd,
a4fd1a8e 19727 struct bfd_link_info *link_info)
c3c76620
MM		 19728{
19729 /* BPABI objects are never loaded directly by an OS kernel; they are
19730 processed by a postlinker first, into an OS-specific format. If
19731 the D_PAGED bit is set on the file, BFD will align segments on
19732 page boundaries, so that an OS can directly map the file. With
19733 BPABI objects, that just results in wasted space. In addition,
19734 because we clear the D_PAGED bit, map_sections_to_segments will
19735 recognize that the program headers should not be mapped into any
19736 loadable segment. */
19737 abfd->flags &= ~D_PAGED;
906e58ca 19738 elf32_arm_begin_write_processing (abfd, link_info);
c3c76620 19739}
7f266840
DJ		 19740
19741static bfd_boolean
906e58ca 19742elf32_arm_symbian_modify_segment_map (bfd *abfd,
b294bdf8 19743 struct bfd_link_info *info)
7f266840
DJ		 19744{
19745 struct elf_segment_map *m;
19746 asection *dynsec;
19747
7f266840
DJ		 19748 /* BPABI shared libraries and executables should have a PT_DYNAMIC
19749 segment. However, because the .dynamic section is not marked
19750 with SEC_LOAD, the generic ELF code will not create such a
19751 segment. */
19752 dynsec = bfd_get_section_by_name (abfd, ".dynamic");
19753 if (dynsec)
19754 {
12bd6957 19755 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
8ded5a0f
AM		 19756 if (m->p_type == PT_DYNAMIC)
19757 break;
19758
19759 if (m == NULL)
19760 {
19761 m = _bfd_elf_make_dynamic_segment (abfd, dynsec);
12bd6957
AM		 19762 m->next = elf_seg_map (abfd);
19763 elf_seg_map (abfd) = m;
8ded5a0f 19764 }
7f266840
DJ		 19765 }
19766
b294bdf8
MM		 19767 /* Also call the generic arm routine. */
19768 return elf32_arm_modify_segment_map (abfd, info);
7f266840
DJ		 19769}
19770
95720a86
DJ		 19771/* Return address for Ith PLT stub in section PLT, for relocation REL
19772 or (bfd_vma) -1 if it should not be included. */
19773
19774static bfd_vma
19775elf32_arm_symbian_plt_sym_val (bfd_vma i, const asection *plt,
19776 const arelent *rel ATTRIBUTE_UNUSED)
19777{
19778 return plt->vma + 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry) * i;
19779}
19780
8029a119 19781#undef elf32_bed
7f266840
DJ		 19782#define elf32_bed elf32_arm_symbian_bed
19783
19784/* The dynamic sections are not allocated on SymbianOS; the postlinker
19785 will process them and then discard them. */
906e58ca 19786#undef ELF_DYNAMIC_SEC_FLAGS
7f266840
DJ		 19787#define ELF_DYNAMIC_SEC_FLAGS \
19788 (SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED)
19789
00a97672 19790#undef elf_backend_emit_relocs
c3c76620 19791
906e58ca
NC		 19792#undef bfd_elf32_bfd_link_hash_table_create
19793#define bfd_elf32_bfd_link_hash_table_create elf32_arm_symbian_link_hash_table_create
19794#undef elf_backend_special_sections
19795#define elf_backend_special_sections elf32_arm_symbian_special_sections
19796#undef elf_backend_begin_write_processing
19797#define elf_backend_begin_write_processing elf32_arm_symbian_begin_write_processing
19798#undef elf_backend_final_write_processing
19799#define elf_backend_final_write_processing elf32_arm_final_write_processing
19800
19801#undef elf_backend_modify_segment_map
7f266840
DJ		 19802#define elf_backend_modify_segment_map elf32_arm_symbian_modify_segment_map
19803
19804/* There is no .got section for BPABI objects, and hence no header. */
906e58ca 19805#undef elf_backend_got_header_size
7f266840
DJ		 19806#define elf_backend_got_header_size 0
19807
19808/* Similarly, there is no .got.plt section. */
906e58ca 19809#undef elf_backend_want_got_plt
7f266840
DJ		 19810#define elf_backend_want_got_plt 0
19811
906e58ca 19812#undef elf_backend_plt_sym_val
95720a86
DJ		 19813#define elf_backend_plt_sym_val elf32_arm_symbian_plt_sym_val
19814
906e58ca 19815#undef elf_backend_may_use_rel_p
00a97672 19816#define elf_backend_may_use_rel_p 1
906e58ca 19817#undef elf_backend_may_use_rela_p
00a97672 19818#define elf_backend_may_use_rela_p 0
906e58ca 19819#undef elf_backend_default_use_rela_p
00a97672 19820#define elf_backend_default_use_rela_p 0
906e58ca 19821#undef elf_backend_want_plt_sym
00a97672 19822#define elf_backend_want_plt_sym 0
906e58ca 19823#undef ELF_MAXPAGESIZE
00a97672 19824#define ELF_MAXPAGESIZE 0x8000
4e7fd91e 19825
7f266840 19826#include "elf32-target.h"
GDB Binutils - Deliverables
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